From ba207ee5a573a6a6c8f133681b734e94f834613d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 23 Jan 2020 13:24:35 -0700
Subject: [PATCH 001/645] start split workload from the main.cpp in openfpga

---
 openfpga/src/base/openfpga_context.h | 35 +++++++++++
 openfpga/src/base/openfpga_title.cpp | 43 +++++++++++++
 openfpga/src/base/openfpga_title.h   | 14 +++++
 openfpga/src/main.cpp                | 94 ++++++----------------------
 openfpga/src/vpr_cmd/vpr_main.cpp    |  2 +
 5 files changed, 114 insertions(+), 74 deletions(-)
 create mode 100644 openfpga/src/base/openfpga_context.h
 create mode 100644 openfpga/src/base/openfpga_title.cpp
 create mode 100644 openfpga/src/base/openfpga_title.h

diff --git a/openfpga/src/base/openfpga_context.h b/openfpga/src/base/openfpga_context.h
new file mode 100644
index 000000000..a0e6272ff
--- /dev/null
+++ b/openfpga/src/base/openfpga_context.h
@@ -0,0 +1,35 @@
+#ifndef OPENFPGA_CONTEXT_H
+#define OPENFPGA_CONTEXT_H
+
+#include "openfpga_arch.h"
+
+/********************************************************************
+ * This file includes the declaration of the date structure 
+ * OpenfpgaContext, which is used for data exchange between 
+ * different modules in OpenFPGA shell environment 
+ *
+ * If a command of OpenFPGA needs to exchange data with other commands,
+ * it must use this data structure to access/mutate.
+ * In such case, you must add data structures to OpenfpgaContext
+ *
+ * Note:
+ * Please respect to the following rules when using the OpenfpgaContext
+ * 1. This data structure will be created only once in the main() function
+ *    The data structure is design to be large and contain all the 
+ *    data structure required by each module of OpenFPGA core engine.
+ *    Do NOT create or duplicate in your own module!     
+ * 2. Be clear in your mind if you want to access/mutate the data inside OpenfpgaContext
+ *    Read-only data should be accessed by 
+ *      const OpenfpgaContext& 
+ *    Mutate should use reference
+ *      OpenfpgaContext&
+ * 3. Please keep the definition of OpenfpgaContext short
+ *    Do put ONLY well-modularized data structure under this root.
+ *******************************************************************/
+class OpenfpgaContext {
+  private:
+    /* Data structure to store information from read_openfpga_arch library */
+    openfpga::Arch arch_;
+};
+
+#endif
diff --git a/openfpga/src/base/openfpga_title.cpp b/openfpga/src/base/openfpga_title.cpp
new file mode 100644
index 000000000..4a33bb72e
--- /dev/null
+++ b/openfpga/src/base/openfpga_title.cpp
@@ -0,0 +1,43 @@
+/********************************************************************
+ * This file includes the functions to create the title page
+ * which introduces generality of OpenFPGA framework
+ *******************************************************************/
+#include "openfpga_title.h"
+
+/********************************************************************
+ * Generate a string of openfpga title introduction
+ * This is mainly used when launching OpenFPGA shell 
+ *******************************************************************/
+const char* create_openfpga_title() {
+  std::string title;
+
+  title += std::string("\n");
+  title += std::string("               OpenFPGA: An Open-source FPGA IP Generator\n");
+  title += std::string("\n");
+  title += std::string("Contributors: Xifan Tang\tAurelien Alacchi\tBaudouin Chauviere\n");
+  title += std::string("\n");
+  title += std::string("The MIT License\n");
+  title += std::string("\n");
+  title += std::string("Copyright (c) 2018 LNIS - The University of Utah\n");
+  title += std::string("\n");
+  title += std::string("Permission is hereby granted, free of charge, to any person obtaining a copy\n");
+  title += std::string("of this software and associated documentation files (the \"Software\"), to deal\n");
+  title += std::string("in the Software without restriction, including without limitation the rights\n");
+  title += std::string("to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n");
+  title += std::string("copies of the Software, and to permit persons to whom the Software is\n");
+  title += std::string("furnished to do so, subject to the following conditions:\n");
+  title += std::string("\n");
+  title += std::string("The above copyright notice and this permission notice shall be included in\n");
+  title += std::string("all copies or substantial portions of the Software.\n");
+  title += std::string("\n");
+  title += std::string("THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n");
+  title += std::string("IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n");
+  title += std::string("FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n");
+  title += std::string("AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n");
+  title += std::string("LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n");
+  title += std::string("OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n");
+  title += std::string("THE SOFTWARE.\n");
+  title += std::string("\n");
+
+  return title.c_str();
+}
diff --git a/openfpga/src/base/openfpga_title.h b/openfpga/src/base/openfpga_title.h
new file mode 100644
index 000000000..b4826964a
--- /dev/null
+++ b/openfpga/src/base/openfpga_title.h
@@ -0,0 +1,14 @@
+#ifndef OPENFPGA_TITLE_H
+#define OPENFPGA_TITLE_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <string>
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+const char* create_openfpga_title();
+
+#endif
diff --git a/openfpga/src/main.cpp b/openfpga/src/main.cpp
index ec445f46e..d3698d18d 100644
--- a/openfpga/src/main.cpp
+++ b/openfpga/src/main.cpp
@@ -1,34 +1,27 @@
 /********************************************************************
  * Build the OpenFPGA shell interface 
  *******************************************************************/
+/* Header file from vtrutil library */
 #include "vtr_log.h"
+
+/* Header file from libopenfpgashell library */
 #include "command_parser.h"
 #include "command_echo.h"
 #include "shell.h"
 
+/* Header file from openfpga */
 #include "vpr_main.h"
 
+#include "openfpga_title.h"
+#include "openfpga_context.h"
+
 using namespace openfpga;
 
-class ShellContext {
-  public:
-    int a;
-};
-
-static
-void shell_execute_set(ShellContext& context, 
-                       const Command& cmd, const CommandContext& cmd_context) {
-  CommandOptionId opt_id = cmd.option("value");
-  /* Get the value of a in the command context */
-  context.a = std::atoi(cmd_context.option_value(cmd, opt_id).c_str());
-}
-
-static
-void shell_execute_print(ShellContext& context) {
-  VTR_LOG("a=%d\n", context.a);
-}
-
+/********************************************************************
+ * Main function to start OpenFPGA shell interface
+ *******************************************************************/
 int main(int argc, char** argv) {
+
   /* Create the command to launch shell in different modes */
   Command start_cmd("OpenFPGA");
   /* Add two options:
@@ -47,70 +40,23 @@ int main(int argc, char** argv) {
 
   /* Create a shell object
    * Add two commands, which are
-   * 1. help
-   * 2. exit
+   * 1. exit
+   * 2. help. This must the last to add
    */
-  Shell<ShellContext> shell("OpenFPGA");
-  std::string shell_title;
+  Shell<OpenfpgaContext> shell("OpenFPGA");
 
-  shell_title += std::string("\n");
-  shell_title += std::string("               OpenFPGA: An Open-source FPGA IP Generator\n");
-  shell_title += std::string("\n");
-  shell_title += std::string("Contributors: Xifan Tang\tAurelien Alacchi\tBaudouin Chauviere\n");
-  shell_title += std::string("\n");
-  shell_title += std::string("The MIT License\n");
-  shell_title += std::string("\n");
-  shell_title += std::string("Copyright (c) 2018 LNIS - The University of Utah\n");
-  shell_title += std::string("\n");
-  shell_title += std::string("Permission is hereby granted, free of charge, to any person obtaining a copy\n");
-  shell_title += std::string("of this software and associated documentation files (the \"Software\"), to deal\n");
-  shell_title += std::string("in the Software without restriction, including without limitation the rights\n");
-  shell_title += std::string("to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n");
-  shell_title += std::string("copies of the Software, and to permit persons to whom the Software is\n");
-  shell_title += std::string("furnished to do so, subject to the following conditions:\n");
-  shell_title += std::string("\n");
-  shell_title += std::string("The above copyright notice and this permission notice shall be included in\n");
-  shell_title += std::string("all copies or substantial portions of the Software.\n");
-  shell_title += std::string("\n");
-  shell_title += std::string("THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n");
-  shell_title += std::string("IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n");
-  shell_title += std::string("FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n");
-  shell_title += std::string("AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n");
-  shell_title += std::string("LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n");
-  shell_title += std::string("OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n");
-  shell_title += std::string("THE SOFTWARE.\n");
-
-  shell.add_title(shell_title.c_str());
+  shell.add_title(create_openfpga_title());
 
   /* Add a new class of commands */
-  ShellCommandClassId arith_cmd_class = shell.add_command_class("Arithmetic");
-
-  /* Create a command of 'set' with a required option 'value' with a value 
-   * This function sets a value to an internal variable of ShellContext 
-   */
-  Command shell_cmd_set("set");
-  CommandOptionId set_opt_value = shell_cmd_set.add_option("value", true, "value of variable");
-  shell_cmd_set.set_option_require_value(set_opt_value, OPT_STRING);
-  ShellCommandId shell_cmd_set_id = shell.add_command(shell_cmd_set, "Set a value to internal variable 'a'");
-  shell.set_command_class(shell_cmd_set_id, arith_cmd_class);
-  shell.set_command_execute_function(shell_cmd_set_id, shell_execute_set);
-
-  /* Create a command of 'print' 
-   * This function will print the value of an internal variable of ShellContext 
-   */
-  Command shell_cmd_print("print");
-  ShellCommandId shell_cmd_print_id = shell.add_command(shell_cmd_print, "Print the value of internal variable 'a'");
-  shell.set_command_class(shell_cmd_print_id, arith_cmd_class);
-  shell.set_command_execute_function(shell_cmd_print_id, shell_execute_print);
+  ShellCommandClassId arith_cmd_class = shell.add_command_class("VPR");
 
   /* Create a macro command of 'vpr' which will call the main engine of vpr 
    */
   Command shell_cmd_vpr("vpr");
-  ShellCommandId shell_cmd_vpr_id = shell.add_command(shell_cmd_vpr, "A macro function to print arguments");
+  ShellCommandId shell_cmd_vpr_id = shell.add_command(shell_cmd_vpr, "Start VPR core engine to pack, place and route a BLIF design on a FPGA architecture");
   shell.set_command_class(shell_cmd_vpr_id, arith_cmd_class);
   shell.set_command_execute_function(shell_cmd_vpr_id, vpr::vpr);
 
-
   /* Add a new class of commands */
   ShellCommandClassId basic_cmd_class = shell.add_command_class("Basic");
 
@@ -126,7 +72,7 @@ int main(int argc, char** argv) {
   shell.set_command_execute_function(shell_cmd_help_id, [shell](){shell.print_commands();});
 
   /* Create the data base for the shell */
-  ShellContext shell_context;
+  OpenfpgaContext openfpga_context;
 
   /* Parse the option, to avoid issues, we use the command name to replace the argv[0] */
   std::vector<std::string> cmd_opts; 
@@ -142,13 +88,13 @@ int main(int argc, char** argv) {
   } else {
     /* Parse succeed. Start a shell */ 
     if (true == start_cmd_context.option_enable(start_cmd, opt_interactive)) {
-      shell.run_interactive_mode(shell_context);
+      shell.run_interactive_mode(openfpga_context);
       return 0;
     } 
 
     if (true == start_cmd_context.option_enable(start_cmd, opt_script_mode)) {
       shell.run_script_mode(start_cmd_context.option_value(start_cmd, opt_script_mode).c_str(),
-                            shell_context);
+                            openfpga_context);
       return 0;
     }
     /* Reach here there is something wrong, show the help desk */
diff --git a/openfpga/src/vpr_cmd/vpr_main.cpp b/openfpga/src/vpr_cmd/vpr_main.cpp
index 08b8348c4..5b9db0455 100644
--- a/openfpga/src/vpr_cmd/vpr_main.cpp
+++ b/openfpga/src/vpr_cmd/vpr_main.cpp
@@ -19,6 +19,8 @@
 #include "vpr_signal_handler.h"
 #include "vpr_tatum_error.h"
 
+#include "vpr_main.h"
+
 #include "globals.h"
 
 namespace vpr {

From 3cb16a2279bc277e706f4ee5cd15d105305b7891 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 23 Jan 2020 14:42:49 -0700
Subject: [PATCH 002/645] move basic commands to separated CXX files

---
 openfpga/src/base/shell_basic_cmd.cpp  | 27 ++++++++++++++++++
 openfpga/src/base/shell_basic_cmd.h    | 21 ++++++++++++++
 openfpga/src/main.cpp                  | 39 ++++++++------------------
 openfpga/src/vpr_cmd/shell_vpr_cmd.cpp | 23 +++++++++++++++
 openfpga/src/vpr_cmd/shell_vpr_cmd.h   | 21 ++++++++++++++
 5 files changed, 104 insertions(+), 27 deletions(-)
 create mode 100644 openfpga/src/base/shell_basic_cmd.cpp
 create mode 100644 openfpga/src/base/shell_basic_cmd.h
 create mode 100644 openfpga/src/vpr_cmd/shell_vpr_cmd.cpp
 create mode 100644 openfpga/src/vpr_cmd/shell_vpr_cmd.h

diff --git a/openfpga/src/base/shell_basic_cmd.cpp b/openfpga/src/base/shell_basic_cmd.cpp
new file mode 100644
index 000000000..defb87f24
--- /dev/null
+++ b/openfpga/src/base/shell_basic_cmd.cpp
@@ -0,0 +1,27 @@
+/********************************************************************
+ * Add basic commands to the OpenFPGA shell interface, including:
+ * - exit
+ * - help
+ *******************************************************************/
+#include "shell_basic_cmd.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void add_basic_commands(openfpga::Shell<OpenfpgaContext>& shell) {
+  /* Add a new class of commands */
+  ShellCommandClassId basic_cmd_class = shell.add_command_class("Basic");
+
+  Command shell_cmd_exit("exit");
+  ShellCommandId shell_cmd_exit_id = shell.add_command(shell_cmd_exit, "Exit the shell");
+  shell.set_command_class(shell_cmd_exit_id, basic_cmd_class);
+  shell.set_command_execute_function(shell_cmd_exit_id, [shell](){shell.exit();});
+
+  /* Note: help must be the last to add because the linking to execute function will do a snapshot on the shell */
+  Command shell_cmd_help("help");
+  ShellCommandId shell_cmd_help_id = shell.add_command(shell_cmd_help, "Launch help desk");
+  shell.set_command_class(shell_cmd_help_id, basic_cmd_class);
+  shell.set_command_execute_function(shell_cmd_help_id, [shell](){shell.print_commands();});
+} 
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/base/shell_basic_cmd.h b/openfpga/src/base/shell_basic_cmd.h
new file mode 100644
index 000000000..1722c9c60
--- /dev/null
+++ b/openfpga/src/base/shell_basic_cmd.h
@@ -0,0 +1,21 @@
+#ifndef SHELL_BASIC_CMD_H
+#define SHELL_BASIC_CMD_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "shell.h"
+#include "openfpga_context.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void add_basic_commands(openfpga::Shell<OpenfpgaContext>& shell); 
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/main.cpp b/openfpga/src/main.cpp
index d3698d18d..7412684b6 100644
--- a/openfpga/src/main.cpp
+++ b/openfpga/src/main.cpp
@@ -10,7 +10,8 @@
 #include "shell.h"
 
 /* Header file from openfpga */
-#include "vpr_main.h"
+#include "shell_vpr_cmd.h"
+#include "shell_basic_cmd.h"
 
 #include "openfpga_title.h"
 #include "openfpga_context.h"
@@ -21,21 +22,20 @@ using namespace openfpga;
  * Main function to start OpenFPGA shell interface
  *******************************************************************/
 int main(int argc, char** argv) {
-
   /* Create the command to launch shell in different modes */
   Command start_cmd("OpenFPGA");
   /* Add two options:
    * '--interactive', -i': launch the interactive mode 
    * '--file', -f': launch the script mode 
    */
-  CommandOptionId opt_interactive = start_cmd.add_option("interactive", false, "Launch OpenFPGA in interactive mode");
+  openfpga::CommandOptionId opt_interactive = start_cmd.add_option("interactive", false, "Launch OpenFPGA in interactive mode");
   start_cmd.set_option_short_name(opt_interactive, "i");
 
-  CommandOptionId opt_script_mode = start_cmd.add_option("file", false, "Launch OpenFPGA in script mode");
-  start_cmd.set_option_require_value(opt_script_mode, OPT_STRING);
+  openfpga::CommandOptionId opt_script_mode = start_cmd.add_option("file", false, "Launch OpenFPGA in script mode");
+  start_cmd.set_option_require_value(opt_script_mode, openfpga::OPT_STRING);
   start_cmd.set_option_short_name(opt_script_mode, "f");
 
-  CommandOptionId opt_help = start_cmd.add_option("help", false, "Help desk"); 
+  openfpga::CommandOptionId opt_help = start_cmd.add_option("help", false, "Help desk"); 
   start_cmd.set_option_short_name(opt_help, "h");
 
   /* Create a shell object
@@ -47,29 +47,14 @@ int main(int argc, char** argv) {
 
   shell.add_title(create_openfpga_title());
 
-  /* Add a new class of commands */
-  ShellCommandClassId arith_cmd_class = shell.add_command_class("VPR");
+  /* Add vpr commands */
+  add_vpr_commands(shell);
 
-  /* Create a macro command of 'vpr' which will call the main engine of vpr 
+  /* Add basic commands: exit, help, etc. 
+   * Note:
+   * This MUST be the last command group to be added! 
    */
-  Command shell_cmd_vpr("vpr");
-  ShellCommandId shell_cmd_vpr_id = shell.add_command(shell_cmd_vpr, "Start VPR core engine to pack, place and route a BLIF design on a FPGA architecture");
-  shell.set_command_class(shell_cmd_vpr_id, arith_cmd_class);
-  shell.set_command_execute_function(shell_cmd_vpr_id, vpr::vpr);
-
-  /* Add a new class of commands */
-  ShellCommandClassId basic_cmd_class = shell.add_command_class("Basic");
-
-  Command shell_cmd_exit("exit");
-  ShellCommandId shell_cmd_exit_id = shell.add_command(shell_cmd_exit, "Exit the shell");
-  shell.set_command_class(shell_cmd_exit_id, basic_cmd_class);
-  shell.set_command_execute_function(shell_cmd_exit_id, [shell](){shell.exit();});
-
-  /* Note: help must be the last to add because the linking to execute function will do a snapshot on the shell */
-  Command shell_cmd_help("help");
-  ShellCommandId shell_cmd_help_id = shell.add_command(shell_cmd_help, "Launch help desk");
-  shell.set_command_class(shell_cmd_help_id, basic_cmd_class);
-  shell.set_command_execute_function(shell_cmd_help_id, [shell](){shell.print_commands();});
+  add_basic_commands(shell);
 
   /* Create the data base for the shell */
   OpenfpgaContext openfpga_context;
diff --git a/openfpga/src/vpr_cmd/shell_vpr_cmd.cpp b/openfpga/src/vpr_cmd/shell_vpr_cmd.cpp
new file mode 100644
index 000000000..22bace2c5
--- /dev/null
+++ b/openfpga/src/vpr_cmd/shell_vpr_cmd.cpp
@@ -0,0 +1,23 @@
+/********************************************************************
+ * Add vpr-related commands to the OpenFPGA shell interface 
+ *******************************************************************/
+#include "vpr_main.h"
+
+#include "shell_vpr_cmd.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void add_vpr_commands(openfpga::Shell<OpenfpgaContext>& shell) {
+  /* Add a new class of commands */
+  ShellCommandClassId arith_cmd_class = shell.add_command_class("VPR");
+
+  /* Create a macro command of 'vpr' which will call the main engine of vpr 
+   */
+  Command shell_cmd_vpr("vpr");
+  ShellCommandId shell_cmd_vpr_id = shell.add_command(shell_cmd_vpr, "Start VPR core engine to pack, place and route a BLIF design on a FPGA architecture");
+  shell.set_command_class(shell_cmd_vpr_id, arith_cmd_class);
+  shell.set_command_execute_function(shell_cmd_vpr_id, vpr::vpr);
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/vpr_cmd/shell_vpr_cmd.h b/openfpga/src/vpr_cmd/shell_vpr_cmd.h
new file mode 100644
index 000000000..c3aebe6dd
--- /dev/null
+++ b/openfpga/src/vpr_cmd/shell_vpr_cmd.h
@@ -0,0 +1,21 @@
+#ifndef SHELL_VPR_CMD_H
+#define SHELL_VPR_CMD_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "shell.h"
+#include "openfpga_context.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void add_vpr_commands(openfpga::Shell<OpenfpgaContext>& shell); 
+
+} /* end namespace openfpga */
+
+#endif

From 26e6c4012f2017c0937e7b447267f629249b1762 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 23 Jan 2020 14:50:03 -0700
Subject: [PATCH 003/645] add const context function execution for shell

---
 libopenfpga/libopenfpgashell/src/shell.h   | 10 ++++++++-
 libopenfpga/libopenfpgashell/src/shell.tpp | 24 ++++++++++++++++++++++
 2 files changed, 33 insertions(+), 1 deletion(-)

diff --git a/libopenfpga/libopenfpgashell/src/shell.h b/libopenfpga/libopenfpgashell/src/shell.h
index 78bd74acb..934901796 100644
--- a/libopenfpga/libopenfpgashell/src/shell.h
+++ b/libopenfpga/libopenfpgashell/src/shell.h
@@ -58,7 +58,9 @@ class Shell {
      * Built-in commands have their own execute functions inside the shell
      */
     enum e_exec_func_type {
+      CONST_STANDARD,
       STANDARD,
+      CONST_SHORT,
       SHORT,
       BUILTIN,
       MACRO,
@@ -93,8 +95,12 @@ class Shell {
      * 4. Marco function, which directly call a macro function without command parsing
      * Users just need to specify the function object and its type will be automatically inferred
      */
+    void set_command_execute_function(const ShellCommandId& cmd_id,
+                                      std::function<void(const T&, const Command&, const CommandContext&)> exec_func);
     void set_command_execute_function(const ShellCommandId& cmd_id,
                                       std::function<void(T&, const Command&, const CommandContext&)> exec_func);
+    void set_command_execute_function(const ShellCommandId& cmd_id,
+                                      std::function<void(const T&)> exec_func);
     void set_command_execute_function(const ShellCommandId& cmd_id,
                                       std::function<void(T&)> exec_func);
     void set_command_execute_function(const ShellCommandId& cmd_id,
@@ -156,8 +162,10 @@ class Shell {
      * 3. Built-in function, including only the shell envoriment variables
      * 4. Marco function, which directly call a macro function without command parsing
      */
+    vtr::vector<ShellCommandId, std::function<void(const T&, const Command&, const CommandContext&)>> command_const_execute_functions_;  
     vtr::vector<ShellCommandId, std::function<void(T&, const Command&, const CommandContext&)>> command_standard_execute_functions_;  
-    vtr::vector<ShellCommandId, std::function<void(T&)>> command_short_execute_functions_;  
+    vtr::vector<ShellCommandId, std::function<void(const T&)>> command_short_const_execute_functions_; 
+    vtr::vector<ShellCommandId, std::function<void(T&)>> command_short_execute_functions_; 
     vtr::vector<ShellCommandId, std::function<void()>> command_builtin_execute_functions_;  
     vtr::vector<ShellCommandId, std::function<int(int, const char**)>> command_macro_execute_functions_;  
 
diff --git a/libopenfpga/libopenfpgashell/src/shell.tpp b/libopenfpga/libopenfpgashell/src/shell.tpp
index 8e9c32860..20787905d 100644
--- a/libopenfpga/libopenfpgashell/src/shell.tpp
+++ b/libopenfpga/libopenfpgashell/src/shell.tpp
@@ -125,7 +125,9 @@ ShellCommandId Shell<T>::add_command(const Command& cmd, const char* descr) {
   command_description_.push_back(descr);
   command_classes_.push_back(ShellCommandClassId::INVALID());
   command_execute_function_types_.emplace_back();
+  command_const_execute_functions_.emplace_back();
   command_standard_execute_functions_.emplace_back();
+  command_short_const_execute_functions_.emplace_back();
   command_short_execute_functions_.emplace_back();
   command_builtin_execute_functions_.emplace_back();
   command_macro_execute_functions_.emplace_back();
@@ -150,6 +152,14 @@ void Shell<T>::set_command_class(const ShellCommandId& cmd_id, const ShellComman
   }
 }
 
+template<class T>
+void Shell<T>::set_command_execute_function(const ShellCommandId& cmd_id, 
+                                            std::function<void(const T&, const Command&, const CommandContext&)> exec_func) {
+  VTR_ASSERT(true == valid_command_id(cmd_id));
+  command_execute_function_types_[cmd_id] = CONST_STANDARD;
+  command_standard_execute_functions_[cmd_id] = exec_func;
+}
+
 template<class T>
 void Shell<T>::set_command_execute_function(const ShellCommandId& cmd_id, 
                                             std::function<void(T&, const Command&, const CommandContext&)> exec_func) {
@@ -158,6 +168,14 @@ void Shell<T>::set_command_execute_function(const ShellCommandId& cmd_id,
   command_standard_execute_functions_[cmd_id] = exec_func;
 }
 
+template<class T>
+void Shell<T>::set_command_execute_function(const ShellCommandId& cmd_id, 
+                                            std::function<void(const T&)> exec_func) {
+  VTR_ASSERT(true == valid_command_id(cmd_id));
+  command_execute_function_types_[cmd_id] = CONST_SHORT;
+  command_short_execute_functions_[cmd_id] = exec_func;
+}
+
 template<class T>
 void Shell<T>::set_command_execute_function(const ShellCommandId& cmd_id, 
                                             std::function<void(T&)> exec_func) {
@@ -379,9 +397,15 @@ void Shell<T>::execute_command(const char* cmd_line,
   
   /* Execute the command depending on the type of function ! */ 
   switch (command_execute_function_types_[cmd_id]) {
+  case CONST_STANDARD:
+    command_const_execute_functions_[cmd_id](common_context, commands_[cmd_id], command_contexts_[cmd_id]);
+    break;
   case STANDARD:
     command_standard_execute_functions_[cmd_id](common_context, commands_[cmd_id], command_contexts_[cmd_id]);
     break;
+  case CONST_SHORT:
+    command_short_const_execute_functions_[cmd_id](common_context);
+    break;
   case SHORT:
     command_short_execute_functions_[cmd_id](common_context);
     break;

From e69aa5ba309d0bbccccf8796304e2ab345aef6bc Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 23 Jan 2020 14:57:53 -0700
Subject: [PATCH 004/645] change type casting for vpr macro

---
 libopenfpga/libopenfpgashell/src/shell.h         | 4 ++--
 libopenfpga/libopenfpgashell/src/shell.tpp       | 4 ++--
 libopenfpga/libopenfpgashell/test/test_shell.cpp | 3 +--
 openfpga/src/vpr_cmd/vpr_main.cpp                | 4 ++--
 openfpga/src/vpr_cmd/vpr_main.h                  | 2 +-
 5 files changed, 8 insertions(+), 9 deletions(-)

diff --git a/libopenfpga/libopenfpgashell/src/shell.h b/libopenfpga/libopenfpgashell/src/shell.h
index 934901796..c053842a9 100644
--- a/libopenfpga/libopenfpgashell/src/shell.h
+++ b/libopenfpga/libopenfpgashell/src/shell.h
@@ -106,7 +106,7 @@ class Shell {
     void set_command_execute_function(const ShellCommandId& cmd_id,
                                       std::function<void()> exec_func);
     void set_command_execute_function(const ShellCommandId& cmd_id,
-                                      std::function<int(int, const char**)> exec_func);
+                                      std::function<int(int, char**)> exec_func);
     void set_command_dependency(const ShellCommandId& cmd_id,
                                 const std::vector<ShellCommandId> cmd_dependency);
     ShellCommandClassId add_command_class(const char* name);
@@ -167,7 +167,7 @@ class Shell {
     vtr::vector<ShellCommandId, std::function<void(const T&)>> command_short_const_execute_functions_; 
     vtr::vector<ShellCommandId, std::function<void(T&)>> command_short_execute_functions_; 
     vtr::vector<ShellCommandId, std::function<void()>> command_builtin_execute_functions_;  
-    vtr::vector<ShellCommandId, std::function<int(int, const char**)>> command_macro_execute_functions_;  
+    vtr::vector<ShellCommandId, std::function<int(int, char**)>> command_macro_execute_functions_;  
 
     /* Type of execute functions for each command.
      * This is supposed to be an internal data ONLY 
diff --git a/libopenfpga/libopenfpgashell/src/shell.tpp b/libopenfpga/libopenfpgashell/src/shell.tpp
index 20787905d..1df5ef744 100644
--- a/libopenfpga/libopenfpgashell/src/shell.tpp
+++ b/libopenfpga/libopenfpgashell/src/shell.tpp
@@ -194,7 +194,7 @@ void Shell<T>::set_command_execute_function(const ShellCommandId& cmd_id,
 
 template<class T>
 void Shell<T>::set_command_execute_function(const ShellCommandId& cmd_id, 
-                                            std::function<int(int, const char**)> exec_func) {
+                                            std::function<int(int, char**)> exec_func) {
   VTR_ASSERT(true == valid_command_id(cmd_id));
   command_execute_function_types_[cmd_id] = MACRO;
   command_macro_execute_functions_[cmd_id] = exec_func;
@@ -376,7 +376,7 @@ void Shell<T>::execute_command(const char* cmd_line,
       strcpy(argv[itok], tokens[itok].c_str());
     }
     /* Execute the marco function */
-    command_macro_execute_functions_[cmd_id](tokens.size(), (const char**)argv);
+    command_macro_execute_functions_[cmd_id](tokens.size(), argv);
     /* Free the argv */
     for (size_t itok = 0; itok < tokens.size(); ++itok) {
       free(argv[itok]);
diff --git a/libopenfpga/libopenfpgashell/test/test_shell.cpp b/libopenfpga/libopenfpgashell/test/test_shell.cpp
index f20c6fded..154986be7 100644
--- a/libopenfpga/libopenfpgashell/test/test_shell.cpp
+++ b/libopenfpga/libopenfpgashell/test/test_shell.cpp
@@ -28,7 +28,7 @@ void shell_execute_print(ShellContext& context) {
 }
 
 static
-int shell_execute_print_macro(int argc, const char** argv) {
+int shell_execute_print_macro(int argc, char** argv) {
   VTR_LOG("Number of arguments: %d\n", argc);
   VTR_LOG("Detailed arguments:\n");
   for (int iarg = 0; iarg < argc; ++iarg) {
@@ -116,7 +116,6 @@ int main(int argc, char** argv) {
   shell.set_command_class(shell_cmd_print_macro_id, arith_cmd_class);
   shell.set_command_execute_function(shell_cmd_print_macro_id, shell_execute_print_macro);
 
-
   /* Add a new class of commands */
   ShellCommandClassId basic_cmd_class = shell.add_command_class("Basic");
 
diff --git a/openfpga/src/vpr_cmd/vpr_main.cpp b/openfpga/src/vpr_cmd/vpr_main.cpp
index 5b9db0455..2af952584 100644
--- a/openfpga/src/vpr_cmd/vpr_main.cpp
+++ b/openfpga/src/vpr_cmd/vpr_main.cpp
@@ -37,7 +37,7 @@ namespace vpr {
  * 3.  Place-and-route and timing analysis
  * 4.  Clean up
  */
-int vpr(int argc, const char** argv) {
+int vpr(int argc, char** argv) {
     vtr::ScopedFinishTimer t("The entire flow of VPR");
 
     t_options Options = t_options();
@@ -48,7 +48,7 @@ int vpr(int argc, const char** argv) {
         vpr_install_signal_handler();
 
         /* Read options, architecture, and circuit netlist */
-        vpr_init(argc, argv, &Options, &vpr_setup, &Arch);
+        vpr_init(argc, (const char**)argv, &Options, &vpr_setup, &Arch);
 
         if (Options.show_version) {
             return SUCCESS_EXIT_CODE;
diff --git a/openfpga/src/vpr_cmd/vpr_main.h b/openfpga/src/vpr_cmd/vpr_main.h
index ede021f6b..056a4732f 100644
--- a/openfpga/src/vpr_cmd/vpr_main.h
+++ b/openfpga/src/vpr_cmd/vpr_main.h
@@ -4,7 +4,7 @@
 /* Begin namespace vpr */
 namespace vpr {
 
-int vpr(int argc, const char** argv);
+int vpr(int argc, char** argv);
 
 } /* End namespace vpr */
 

From cdb3b6de464595ba36a2642d2f32ce7251ed8509 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 23 Jan 2020 19:10:53 -0700
Subject: [PATCH 005/645] add read_openfpga_arch to OpenFPGA shell

---
 .../libarchopenfpga/arch/sample_arch.xml      | 12 ++---
 ...{shell_basic_cmd.cpp => basic_command.cpp} |  2 +-
 .../{shell_basic_cmd.h => basic_command.h}    |  4 +-
 openfpga/src/base/openfpga_context.h          | 13 ++++-
 openfpga/src/base/openfpga_read_arch.cpp      | 49 +++++++++++++++++++
 openfpga/src/base/openfpga_read_arch.h        | 23 +++++++++
 openfpga/src/base/openfpga_setup_command.cpp  | 28 +++++++++++
 openfpga/src/base/openfpga_setup_command.h    | 21 ++++++++
 openfpga/src/main.cpp                         | 24 ++++-----
 .../vpr_command.cpp}                          |  2 +-
 .../vpr_command.h}                            |  4 +-
 .../src/{vpr_cmd => vpr_wrapper}/vpr_main.cpp |  0
 .../src/{vpr_cmd => vpr_wrapper}/vpr_main.h   |  0
 13 files changed, 157 insertions(+), 25 deletions(-)
 rename openfpga/src/base/{shell_basic_cmd.cpp => basic_command.cpp} (97%)
 rename openfpga/src/base/{shell_basic_cmd.h => basic_command.h} (91%)
 create mode 100644 openfpga/src/base/openfpga_read_arch.cpp
 create mode 100644 openfpga/src/base/openfpga_read_arch.h
 create mode 100644 openfpga/src/base/openfpga_setup_command.cpp
 create mode 100644 openfpga/src/base/openfpga_setup_command.h
 rename openfpga/src/{vpr_cmd/shell_vpr_cmd.cpp => vpr_wrapper/vpr_command.cpp} (97%)
 rename openfpga/src/{vpr_cmd/shell_vpr_cmd.h => vpr_wrapper/vpr_command.h} (92%)
 rename openfpga/src/{vpr_cmd => vpr_wrapper}/vpr_main.cpp (100%)
 rename openfpga/src/{vpr_cmd => vpr_wrapper}/vpr_main.h (100%)

diff --git a/libopenfpga/libarchopenfpga/arch/sample_arch.xml b/libopenfpga/libarchopenfpga/arch/sample_arch.xml
index 56a8da59b..6d6484f7e 100644
--- a/libopenfpga/libarchopenfpga/arch/sample_arch.xml
+++ b/libopenfpga/libarchopenfpga/arch/sample_arch.xml
@@ -274,12 +274,12 @@
     <pb_type name="io[io_phy].iopad" circuit_model_name="iopad" mode_bits="1"/> 
     <pb_type name="io[io_phy].inpad" physical_pb_type_name="iopad" mode_bits="1"/> 
     <pb_type name="io[io_phy].outpad" physical_pb_type_name="iopad" mode_bits="0"/> 
-    <pb_type name="clb.fle" physical_mode_name="fle_phy" idle_mode_name="n2_lut5">
-    <pb_type name="clb.fle[fle_phy].frac_logic.frac_lut6" mode_bits="11" circuit_model_name="frac_lut6">
-    <pb_type name="clb.fle[fle_phy].frac_logic.adder_phy" circuit_model_name="adder">
-    <pb_type name="clb.fle[fle_phy].frac_logic.ff_phy" circuit_model_name="static_dff">
-    <mode name="fle_phy" disabled_in_packing="true">
-    <pb_type name="lut5" mode_bits="01" physical_pb_type_name="frac_lut6" physical_pb_type_index_factor="0.5">
+    <pb_type name="clb.fle" physical_mode_name="fle_phy" idle_mode_name="n2_lut5"/>
+    <pb_type name="clb.fle[fle_phy].frac_logic.frac_lut6" mode_bits="11" circuit_model_name="frac_lut6"/>
+    <pb_type name="clb.fle[fle_phy].frac_logic.adder_phy" circuit_model_name="adder"/>
+    <pb_type name="clb.fle[fle_phy].frac_logic.ff_phy" circuit_model_name="static_dff"/>
+    <mode name="fle_phy" disabled_in_packing="true"/>
+    <pb_type name="lut5" mode_bits="01" physical_pb_type_name="frac_lut6" physical_pb_type_index_factor="0.5"/>
     <input name="in" physical_mode_pin="in[5:0]"/>
     <output name="out" physical_mode_pin="lut5_out" physical_mode_pin_rotate_offset="1"/>
   </complex_blocks>
diff --git a/openfpga/src/base/shell_basic_cmd.cpp b/openfpga/src/base/basic_command.cpp
similarity index 97%
rename from openfpga/src/base/shell_basic_cmd.cpp
rename to openfpga/src/base/basic_command.cpp
index defb87f24..397c9272c 100644
--- a/openfpga/src/base/shell_basic_cmd.cpp
+++ b/openfpga/src/base/basic_command.cpp
@@ -3,7 +3,7 @@
  * - exit
  * - help
  *******************************************************************/
-#include "shell_basic_cmd.h"
+#include "basic_command.h"
 
 /* begin namespace openfpga */
 namespace openfpga {
diff --git a/openfpga/src/base/shell_basic_cmd.h b/openfpga/src/base/basic_command.h
similarity index 91%
rename from openfpga/src/base/shell_basic_cmd.h
rename to openfpga/src/base/basic_command.h
index 1722c9c60..8aaf9110a 100644
--- a/openfpga/src/base/shell_basic_cmd.h
+++ b/openfpga/src/base/basic_command.h
@@ -1,5 +1,5 @@
-#ifndef SHELL_BASIC_CMD_H
-#define SHELL_BASIC_CMD_H
+#ifndef BASIC_COMMAND_H
+#define BASIC_COMMAND_H
 
 /********************************************************************
  * Include header files that are required by function declaration
diff --git a/openfpga/src/base/openfpga_context.h b/openfpga/src/base/openfpga_context.h
index a0e6272ff..c66012615 100644
--- a/openfpga/src/base/openfpga_context.h
+++ b/openfpga/src/base/openfpga_context.h
@@ -1,6 +1,7 @@
 #ifndef OPENFPGA_CONTEXT_H
 #define OPENFPGA_CONTEXT_H
 
+#include "vpr_context.h"
 #include "openfpga_arch.h"
 
 /********************************************************************
@@ -25,9 +26,17 @@
  *      OpenfpgaContext&
  * 3. Please keep the definition of OpenfpgaContext short
  *    Do put ONLY well-modularized data structure under this root.
+ * 4. We build this data structure based on the Context from VPR
+ *    which does NOT allow users to copy the internal members
+ *    This is due to that the data structures in the OpenFPGA context
+ *    are typically big in terms of memory
  *******************************************************************/
-class OpenfpgaContext {
-  private:
+class OpenfpgaContext : public Context  {
+  public:  /* Public accessors */
+    const openfpga::Arch& arch() const { return arch_; }
+  public:  /* Public mutators */
+    openfpga::Arch& mutable_arch() { return arch_; }
+  private: /* Internal data */
     /* Data structure to store information from read_openfpga_arch library */
     openfpga::Arch arch_;
 };
diff --git a/openfpga/src/base/openfpga_read_arch.cpp b/openfpga/src/base/openfpga_read_arch.cpp
new file mode 100644
index 000000000..5d1f9ac8b
--- /dev/null
+++ b/openfpga/src/base/openfpga_read_arch.cpp
@@ -0,0 +1,49 @@
+/********************************************************************
+ * This file includes functions to read an OpenFPGA architecture file
+ * which are built on the libarchopenfpga library
+ *******************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_log.h"
+
+/* Headers from archopenfpga library */
+#include "read_xml_openfpga_arch.h"
+#include "check_circuit_library.h"
+
+#include "openfpga_read_arch.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Top-level function to read an OpenFPGA architecture file
+ * we use the APIs from the libarchopenfpga library 
+ *
+ * The command will accept an option '--file' which is the architecture
+ * file provided by users  
+ *******************************************************************/
+void read_arch(OpenfpgaContext& openfpga_context,
+               const Command& cmd, const CommandContext& cmd_context) {
+  /* Check the option '--file' is enabled or not 
+   * Actually, it must be enabled as the shell interface will check 
+   * before reaching this fuction
+   */
+  CommandOptionId opt_file = cmd.option("file");
+  VTR_ASSERT(true == cmd_context.option_enable(cmd, opt_file));
+  VTR_ASSERT(false == cmd_context.option_value(cmd, opt_file).empty());
+
+  std::string arch_file_name = cmd_context.option_value(cmd, opt_file);
+  
+  VTR_LOG("Reading XML architecture '%s'...\n",
+          arch_file_name.c_str());
+  openfpga_context.mutable_arch() = read_xml_openfpga_arch(arch_file_name.c_str());
+
+  /* Check the architecture:
+   * 1. Circuit library
+   * 2. Technology library (TODO)
+   * 3. Simulation settings (TODO)
+   */
+  check_circuit_library(openfpga_context.arch().circuit_lib);
+} 
+
+} /* end namespace openfpga */
+
diff --git a/openfpga/src/base/openfpga_read_arch.h b/openfpga/src/base/openfpga_read_arch.h
new file mode 100644
index 000000000..8b300bd54
--- /dev/null
+++ b/openfpga/src/base/openfpga_read_arch.h
@@ -0,0 +1,23 @@
+#ifndef OPENFPGA_READ_ARCH_COMMAND_H
+#define OPENFPGA_READ_ARCH_COMMAND_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "command.h"
+#include "command_context.h"
+#include "openfpga_context.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void read_arch(OpenfpgaContext& openfpga_context,
+               const Command& cmd, const CommandContext& cmd_context); 
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/base/openfpga_setup_command.cpp b/openfpga/src/base/openfpga_setup_command.cpp
new file mode 100644
index 000000000..a974e2704
--- /dev/null
+++ b/openfpga/src/base/openfpga_setup_command.cpp
@@ -0,0 +1,28 @@
+/********************************************************************
+ * Add commands to the OpenFPGA shell interface, 
+ * in purpose of setting up OpenFPGA core engine, including:
+ * - read_openfpga_arch : read OpenFPGA architecture file
+ *******************************************************************/
+#include "openfpga_read_arch.h"
+#include "openfpga_setup_command.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void add_openfpga_setup_commands(openfpga::Shell<OpenfpgaContext>& shell) {
+  /* Add a new class of commands */
+  ShellCommandClassId openfpga_setup_cmd_class = shell.add_command_class("OpenFPGA setup");
+
+  /* Command 'read_openfpga_arch' */
+  Command shell_cmd_read_arch("read_openfpga_arch");
+  /* Add an option '--file' in short '-f'*/
+  CommandOptionId read_arch_opt_file = shell_cmd_read_arch.add_option("file", true, "file path to the architecture XML");
+  shell_cmd_read_arch.set_option_short_name(read_arch_opt_file, "f");
+  shell_cmd_read_arch.set_option_require_value(read_arch_opt_file, openfpga::OPT_STRING);
+  
+  ShellCommandId shell_cmd_read_arch_id = shell.add_command(shell_cmd_read_arch, "read OpenFPGA architecture file");
+  shell.set_command_class(shell_cmd_read_arch_id, openfpga_setup_cmd_class);
+  shell.set_command_execute_function(shell_cmd_read_arch_id, read_arch);
+} 
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_setup_command.h b/openfpga/src/base/openfpga_setup_command.h
new file mode 100644
index 000000000..03d4220f5
--- /dev/null
+++ b/openfpga/src/base/openfpga_setup_command.h
@@ -0,0 +1,21 @@
+#ifndef OPENFPGA_SETUP_COMMAND_H
+#define OPENFPGA_SETUP_COMMAND_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "shell.h"
+#include "openfpga_context.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void add_openfpga_setup_commands(openfpga::Shell<OpenfpgaContext>& shell); 
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/main.cpp b/openfpga/src/main.cpp
index 7412684b6..c7c31b00c 100644
--- a/openfpga/src/main.cpp
+++ b/openfpga/src/main.cpp
@@ -10,20 +10,19 @@
 #include "shell.h"
 
 /* Header file from openfpga */
-#include "shell_vpr_cmd.h"
-#include "shell_basic_cmd.h"
+#include "vpr_command.h"
+#include "openfpga_setup_command.h"
+#include "basic_command.h"
 
 #include "openfpga_title.h"
 #include "openfpga_context.h"
 
-using namespace openfpga;
-
 /********************************************************************
  * Main function to start OpenFPGA shell interface
  *******************************************************************/
 int main(int argc, char** argv) {
   /* Create the command to launch shell in different modes */
-  Command start_cmd("OpenFPGA");
+  openfpga::Command start_cmd("OpenFPGA");
   /* Add two options:
    * '--interactive', -i': launch the interactive mode 
    * '--file', -f': launch the script mode 
@@ -43,18 +42,21 @@ int main(int argc, char** argv) {
    * 1. exit
    * 2. help. This must the last to add
    */
-  Shell<OpenfpgaContext> shell("OpenFPGA");
+  openfpga::Shell<OpenfpgaContext> shell("OpenFPGA");
 
   shell.add_title(create_openfpga_title());
 
   /* Add vpr commands */
-  add_vpr_commands(shell);
+  openfpga::add_vpr_commands(shell);
+
+  /* Add openfpga setup commands */
+  openfpga::add_openfpga_setup_commands(shell);
 
   /* Add basic commands: exit, help, etc. 
    * Note:
    * This MUST be the last command group to be added! 
    */
-  add_basic_commands(shell);
+  openfpga::add_basic_commands(shell);
 
   /* Create the data base for the shell */
   OpenfpgaContext openfpga_context;
@@ -66,10 +68,10 @@ int main(int argc, char** argv) {
     cmd_opts.push_back(std::string(argv[iarg]));
   }
 
-  CommandContext start_cmd_context(start_cmd);
+  openfpga::CommandContext start_cmd_context(start_cmd);
   if (false == parse_command(cmd_opts, start_cmd, start_cmd_context)) {
     /* Parse fail: Echo the command */
-    print_command_options(start_cmd);
+    openfpga::print_command_options(start_cmd);
   } else {
     /* Parse succeed. Start a shell */ 
     if (true == start_cmd_context.option_enable(start_cmd, opt_interactive)) {
@@ -83,7 +85,7 @@ int main(int argc, char** argv) {
       return 0;
     }
     /* Reach here there is something wrong, show the help desk */
-    print_command_options(start_cmd);
+    openfpga::print_command_options(start_cmd);
   }
 
   return 0;
diff --git a/openfpga/src/vpr_cmd/shell_vpr_cmd.cpp b/openfpga/src/vpr_wrapper/vpr_command.cpp
similarity index 97%
rename from openfpga/src/vpr_cmd/shell_vpr_cmd.cpp
rename to openfpga/src/vpr_wrapper/vpr_command.cpp
index 22bace2c5..5baa1ec84 100644
--- a/openfpga/src/vpr_cmd/shell_vpr_cmd.cpp
+++ b/openfpga/src/vpr_wrapper/vpr_command.cpp
@@ -3,7 +3,7 @@
  *******************************************************************/
 #include "vpr_main.h"
 
-#include "shell_vpr_cmd.h"
+#include "vpr_command.h"
 
 /* begin namespace openfpga */
 namespace openfpga {
diff --git a/openfpga/src/vpr_cmd/shell_vpr_cmd.h b/openfpga/src/vpr_wrapper/vpr_command.h
similarity index 92%
rename from openfpga/src/vpr_cmd/shell_vpr_cmd.h
rename to openfpga/src/vpr_wrapper/vpr_command.h
index c3aebe6dd..467e416d0 100644
--- a/openfpga/src/vpr_cmd/shell_vpr_cmd.h
+++ b/openfpga/src/vpr_wrapper/vpr_command.h
@@ -1,5 +1,5 @@
-#ifndef SHELL_VPR_CMD_H
-#define SHELL_VPR_CMD_H
+#ifndef VPR_COMMAND_H
+#define VPR_COMMAND_H
 
 /********************************************************************
  * Include header files that are required by function declaration
diff --git a/openfpga/src/vpr_cmd/vpr_main.cpp b/openfpga/src/vpr_wrapper/vpr_main.cpp
similarity index 100%
rename from openfpga/src/vpr_cmd/vpr_main.cpp
rename to openfpga/src/vpr_wrapper/vpr_main.cpp
diff --git a/openfpga/src/vpr_cmd/vpr_main.h b/openfpga/src/vpr_wrapper/vpr_main.h
similarity index 100%
rename from openfpga/src/vpr_cmd/vpr_main.h
rename to openfpga/src/vpr_wrapper/vpr_main.h

From a03f8aa3468f5156ce32707c8fe9b5ef6b864ea1 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 23 Jan 2020 20:12:30 -0700
Subject: [PATCH 006/645] add profiling for read arch

---
 libopenfpga/libarchopenfpga/src/check_circuit_library.cpp  | 6 +++---
 libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.cpp | 5 +++++
 openfpga/src/base/openfpga_read_arch.cpp                   | 2 +-
 3 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp b/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp
index ce5211374..93d5ae737 100644
--- a/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp
+++ b/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp
@@ -6,10 +6,10 @@
  * 3. if nay circuit model miss mandatory ports 
  ***********************************************************************/
 
-/* Header files should be included in a sequence */
-/* Standard header files required go first */
+/* Headers from vtrutil library */
 #include "vtr_assert.h"
 #include "vtr_log.h"
+#include "vtr_time.h"
 
 #include "check_circuit_library.h"
 
@@ -437,7 +437,7 @@ size_t check_circuit_library_ports(const CircuitLibrary& circuit_lib) {
 void check_circuit_library(const CircuitLibrary& circuit_lib) {
   size_t num_err = 0;
 
-  VTR_LOG("Checking circuit models...\n");
+  vtr::ScopedStartFinishTimer timer("Check circuit library");
 
   /* 1. Circuit models have unique names  
    * For each circuit model, we always make sure it does not share any name with any circuit model locating after it
diff --git a/libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.cpp b/libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.cpp
index 33cf951aa..10605b860 100644
--- a/libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.cpp
+++ b/libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.cpp
@@ -9,6 +9,9 @@
 #include "pugixml.hpp"
 #include "pugixml_util.hpp"
 
+/* Headers from vtrutil library */
+#include "vtr_time.h"
+
 /* Headers from libarchfpga */
 #include "arch_error.h"
 #include "read_xml_util.h"
@@ -26,6 +29,8 @@
  * 1. circuit library
  *******************************************************************/
 openfpga::Arch read_xml_openfpga_arch(const char* arch_file_name) {
+  vtr::ScopedStartFinishTimer timer("Read OpenFPGA architecture");
+
   openfpga::Arch openfpga_arch;
 
   pugi::xml_node Next;
diff --git a/openfpga/src/base/openfpga_read_arch.cpp b/openfpga/src/base/openfpga_read_arch.cpp
index 5d1f9ac8b..765241db8 100644
--- a/openfpga/src/base/openfpga_read_arch.cpp
+++ b/openfpga/src/base/openfpga_read_arch.cpp
@@ -32,7 +32,7 @@ void read_arch(OpenfpgaContext& openfpga_context,
   VTR_ASSERT(false == cmd_context.option_value(cmd, opt_file).empty());
 
   std::string arch_file_name = cmd_context.option_value(cmd, opt_file);
-  
+
   VTR_LOG("Reading XML architecture '%s'...\n",
           arch_file_name.c_str());
   openfpga_context.mutable_arch() = read_xml_openfpga_arch(arch_file_name.c_str());

From 655f84b00eb12eb460e75d1e37c0742b02715146 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 23 Jan 2020 20:58:15 -0700
Subject: [PATCH 007/645] add write_openfpga_arch command to openfpga shell

---
 .../src/write_xml_openfpga_arch.cpp           |  5 ++++
 libopenfpga/libopenfpgashell/src/shell.h      |  6 ++---
 libopenfpga/libopenfpgashell/src/shell.tpp    | 12 ++++-----
 openfpga/src/base/openfpga_read_arch.cpp      | 25 +++++++++++++++++++
 openfpga/src/base/openfpga_read_arch.h        |  3 +++
 openfpga/src/base/openfpga_setup_command.cpp  | 13 ++++++++++
 6 files changed, 55 insertions(+), 9 deletions(-)

diff --git a/libopenfpga/libarchopenfpga/src/write_xml_openfpga_arch.cpp b/libopenfpga/libarchopenfpga/src/write_xml_openfpga_arch.cpp
index 6d6945a66..e262735e4 100644
--- a/libopenfpga/libarchopenfpga/src/write_xml_openfpga_arch.cpp
+++ b/libopenfpga/libarchopenfpga/src/write_xml_openfpga_arch.cpp
@@ -4,6 +4,9 @@
  *******************************************************************/
 #include <fstream>
 
+/* Headers from vtrutil library */
+#include "vtr_time.h"
+
 /* Headers from openfpgautil library */
 #include "openfpga_digest.h"
 
@@ -20,6 +23,8 @@
  *******************************************************************/
 void write_xml_openfpga_arch(const char* fname, 
                              const openfpga::Arch& openfpga_arch) {
+  vtr::ScopedStartFinishTimer timer("Write OpenFPGA architecture");
+
   /* Create a file handler */
   std::fstream fp;
   /* Open the file stream */
diff --git a/libopenfpga/libopenfpgashell/src/shell.h b/libopenfpga/libopenfpgashell/src/shell.h
index c053842a9..2f67dd610 100644
--- a/libopenfpga/libopenfpgashell/src/shell.h
+++ b/libopenfpga/libopenfpgashell/src/shell.h
@@ -95,12 +95,12 @@ class Shell {
      * 4. Marco function, which directly call a macro function without command parsing
      * Users just need to specify the function object and its type will be automatically inferred
      */
-    void set_command_execute_function(const ShellCommandId& cmd_id,
+    void set_command_const_execute_function(const ShellCommandId& cmd_id,
                                       std::function<void(const T&, const Command&, const CommandContext&)> exec_func);
     void set_command_execute_function(const ShellCommandId& cmd_id,
                                       std::function<void(T&, const Command&, const CommandContext&)> exec_func);
-    void set_command_execute_function(const ShellCommandId& cmd_id,
-                                      std::function<void(const T&)> exec_func);
+    void set_command_const_execute_function(const ShellCommandId& cmd_id,
+                                            std::function<void(const T&)> exec_func);
     void set_command_execute_function(const ShellCommandId& cmd_id,
                                       std::function<void(T&)> exec_func);
     void set_command_execute_function(const ShellCommandId& cmd_id,
diff --git a/libopenfpga/libopenfpgashell/src/shell.tpp b/libopenfpga/libopenfpgashell/src/shell.tpp
index 1df5ef744..30534cfeb 100644
--- a/libopenfpga/libopenfpgashell/src/shell.tpp
+++ b/libopenfpga/libopenfpgashell/src/shell.tpp
@@ -153,11 +153,11 @@ void Shell<T>::set_command_class(const ShellCommandId& cmd_id, const ShellComman
 }
 
 template<class T>
-void Shell<T>::set_command_execute_function(const ShellCommandId& cmd_id, 
-                                            std::function<void(const T&, const Command&, const CommandContext&)> exec_func) {
+void Shell<T>::set_command_const_execute_function(const ShellCommandId& cmd_id, 
+                                                  std::function<void(const T&, const Command&, const CommandContext&)> exec_func) {
   VTR_ASSERT(true == valid_command_id(cmd_id));
   command_execute_function_types_[cmd_id] = CONST_STANDARD;
-  command_standard_execute_functions_[cmd_id] = exec_func;
+  command_const_execute_functions_[cmd_id] = exec_func;
 }
 
 template<class T>
@@ -169,11 +169,11 @@ void Shell<T>::set_command_execute_function(const ShellCommandId& cmd_id,
 }
 
 template<class T>
-void Shell<T>::set_command_execute_function(const ShellCommandId& cmd_id, 
-                                            std::function<void(const T&)> exec_func) {
+void Shell<T>::set_command_const_execute_function(const ShellCommandId& cmd_id, 
+                                                  std::function<void(const T&)> exec_func) {
   VTR_ASSERT(true == valid_command_id(cmd_id));
   command_execute_function_types_[cmd_id] = CONST_SHORT;
-  command_short_execute_functions_[cmd_id] = exec_func;
+  command_short_const_execute_functions_[cmd_id] = exec_func;
 }
 
 template<class T>
diff --git a/openfpga/src/base/openfpga_read_arch.cpp b/openfpga/src/base/openfpga_read_arch.cpp
index 765241db8..1a36e85a3 100644
--- a/openfpga/src/base/openfpga_read_arch.cpp
+++ b/openfpga/src/base/openfpga_read_arch.cpp
@@ -8,6 +8,7 @@
 /* Headers from archopenfpga library */
 #include "read_xml_openfpga_arch.h"
 #include "check_circuit_library.h"
+#include "write_xml_openfpga_arch.h"
 
 #include "openfpga_read_arch.h"
 
@@ -45,5 +46,29 @@ void read_arch(OpenfpgaContext& openfpga_context,
   check_circuit_library(openfpga_context.arch().circuit_lib);
 } 
 
+/********************************************************************
+ * A function to write an OpenFPGA architecture file
+ * we use the APIs from the libarchopenfpga library 
+ *
+ * The command will accept an option '--file' which is the architecture
+ * file provided by users  
+ *******************************************************************/
+void write_arch(const OpenfpgaContext& openfpga_context,
+                const Command& cmd, const CommandContext& cmd_context) {
+  /* Check the option '--file' is enabled or not 
+   * Actually, it must be enabled as the shell interface will check 
+   * before reaching this fuction
+   */
+  CommandOptionId opt_file = cmd.option("file");
+  VTR_ASSERT(true == cmd_context.option_enable(cmd, opt_file));
+  VTR_ASSERT(false == cmd_context.option_value(cmd, opt_file).empty());
+
+  std::string arch_file_name = cmd_context.option_value(cmd, opt_file);
+
+  VTR_LOG("Writing XML architecture to '%s'...\n",
+          arch_file_name.c_str());
+  write_xml_openfpga_arch(arch_file_name.c_str(), openfpga_context.arch());
+} 
+
 } /* end namespace openfpga */
 
diff --git a/openfpga/src/base/openfpga_read_arch.h b/openfpga/src/base/openfpga_read_arch.h
index 8b300bd54..dcc04d77a 100644
--- a/openfpga/src/base/openfpga_read_arch.h
+++ b/openfpga/src/base/openfpga_read_arch.h
@@ -18,6 +18,9 @@ namespace openfpga {
 void read_arch(OpenfpgaContext& openfpga_context,
                const Command& cmd, const CommandContext& cmd_context); 
 
+void write_arch(const OpenfpgaContext& openfpga_context,
+                const Command& cmd, const CommandContext& cmd_context);
+
 } /* end namespace openfpga */
 
 #endif
diff --git a/openfpga/src/base/openfpga_setup_command.cpp b/openfpga/src/base/openfpga_setup_command.cpp
index a974e2704..99d827bfb 100644
--- a/openfpga/src/base/openfpga_setup_command.cpp
+++ b/openfpga/src/base/openfpga_setup_command.cpp
@@ -20,9 +20,22 @@ void add_openfpga_setup_commands(openfpga::Shell<OpenfpgaContext>& shell) {
   shell_cmd_read_arch.set_option_short_name(read_arch_opt_file, "f");
   shell_cmd_read_arch.set_option_require_value(read_arch_opt_file, openfpga::OPT_STRING);
   
+  /* Add command 'read_openfpga_arch' to the Shell */
   ShellCommandId shell_cmd_read_arch_id = shell.add_command(shell_cmd_read_arch, "read OpenFPGA architecture file");
   shell.set_command_class(shell_cmd_read_arch_id, openfpga_setup_cmd_class);
   shell.set_command_execute_function(shell_cmd_read_arch_id, read_arch);
+
+  /* Command 'write_openfpga_arch' */
+  Command shell_cmd_write_arch("write_openfpga_arch");
+  /* Add an option '--file' in short '-f'*/
+  CommandOptionId write_arch_opt_file = shell_cmd_write_arch.add_option("file", true, "file path to the architecture XML");
+  shell_cmd_write_arch.set_option_short_name(write_arch_opt_file, "f");
+  shell_cmd_write_arch.set_option_require_value(write_arch_opt_file, openfpga::OPT_STRING);
+
+  /* Add command 'write_openfpga_arch' to the Shell */
+  ShellCommandId shell_cmd_write_arch_id = shell.add_command(shell_cmd_write_arch, "write OpenFPGA architecture file");
+  shell.set_command_class(shell_cmd_write_arch_id, openfpga_setup_cmd_class);
+  shell.set_command_const_execute_function(shell_cmd_write_arch_id, write_arch);
 } 
 
 } /* end namespace openfpga */

From d1725de6069f775e9fbdddbcf637464dd78dcfda Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 24 Jan 2020 10:15:16 -0700
Subject: [PATCH 008/645] add ctags script to index openfpga source files

---
 openfpga/src/ctag_src.sh | 1 +
 1 file changed, 1 insertion(+)
 create mode 100644 openfpga/src/ctag_src.sh

diff --git a/openfpga/src/ctag_src.sh b/openfpga/src/ctag_src.sh
new file mode 100644
index 000000000..e36d842ea
--- /dev/null
+++ b/openfpga/src/ctag_src.sh
@@ -0,0 +1 @@
+ctags -R . ../../libopenfpga/*/src/* ../../libs/*/src/* ../../vpr/src/*/*

From b641ae15d3d7aa4f5c55134cc7d52939c9ca08f1 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 24 Jan 2020 16:46:39 -0700
Subject: [PATCH 009/645] add command dependency in shell execution

---
 libopenfpga/libopenfpgashell/src/shell.h      |  5 ++++-
 libopenfpga/libopenfpgashell/src/shell.tpp    | 19 +++++++++++++++----
 .../libopenfpgashell/test/test_shell.cpp      |  2 ++
 3 files changed, 21 insertions(+), 5 deletions(-)

diff --git a/libopenfpga/libopenfpgashell/src/shell.h b/libopenfpga/libopenfpgashell/src/shell.h
index 2f67dd610..415fc1b1c 100644
--- a/libopenfpga/libopenfpgashell/src/shell.h
+++ b/libopenfpga/libopenfpgashell/src/shell.h
@@ -108,7 +108,7 @@ class Shell {
     void set_command_execute_function(const ShellCommandId& cmd_id,
                                       std::function<int(int, char**)> exec_func);
     void set_command_dependency(const ShellCommandId& cmd_id,
-                                const std::vector<ShellCommandId> cmd_dependency);
+                                const std::vector<ShellCommandId>& cmd_dependency);
     ShellCommandClassId add_command_class(const char* name);
   public: /* Public validators */
     bool valid_command_id(const ShellCommandId& cmd_id) const;
@@ -174,6 +174,9 @@ class Shell {
      */
     vtr::vector<ShellCommandId, e_exec_func_type> command_execute_function_types_;  
 
+    /* A flag to indicate if the command has been executed */  
+    vtr::vector<ShellCommandId, bool> command_status_;  
+
     /* Dependency graph for different commands,
      * This helps the shell interface to check if a command need other commands to be run before its execution  
      */
diff --git a/libopenfpga/libopenfpgashell/src/shell.tpp b/libopenfpga/libopenfpgashell/src/shell.tpp
index 30534cfeb..0a52fda0b 100644
--- a/libopenfpga/libopenfpgashell/src/shell.tpp
+++ b/libopenfpga/libopenfpgashell/src/shell.tpp
@@ -131,6 +131,7 @@ ShellCommandId Shell<T>::add_command(const Command& cmd, const char* descr) {
   command_short_execute_functions_.emplace_back();
   command_builtin_execute_functions_.emplace_back();
   command_macro_execute_functions_.emplace_back();
+  command_status_.push_back(false); /* By default, the command should be marked as never executed */
   command_dependencies_.emplace_back();
 
   /* Register the name in the name2id map */
@@ -202,7 +203,7 @@ void Shell<T>::set_command_execute_function(const ShellCommandId& cmd_id,
 
 template<class T>
 void Shell<T>::set_command_dependency(const ShellCommandId& cmd_id,
-                                      const std::vector<ShellCommandId> dependent_cmds) {
+                                      const std::vector<ShellCommandId>& dependent_cmds) {
   /* Validate the command id as well as each of the command dependency */
   VTR_ASSERT(true == valid_command_id(cmd_id));
   for (ShellCommandId dependent_cmd : dependent_cmds) {
@@ -362,7 +363,14 @@ void Shell<T>::execute_command(const char* cmd_line,
     return;
   }
 
-  /* TODO: Check the dependency graph to see if all the prequistics have been met */
+  /* Check the dependency graph to see if all the prequistics have been met */
+  for (const ShellCommandId& dep_cmd : command_dependencies_[cmd_id]) {
+    if (false == command_status_[dep_cmd]) {
+      VTR_LOG("Command '%s' is required to be executed before command '%s'!\n",
+              commands_[dep_cmd].name().c_str(), commands_[cmd_id].name().c_str());
+      return;
+    } 
+  }
 
   /* Find the command! Parse the options 
    * Note:
@@ -391,10 +399,10 @@ void Shell<T>::execute_command(const char* cmd_line,
     print_command_options(commands_[cmd_id]);
     return;
   }
-    
+ 
   /* Parse succeed. Let user to confirm selected options */ 
   print_command_context(commands_[cmd_id], command_contexts_[cmd_id]);
-  
+
   /* Execute the command depending on the type of function ! */ 
   switch (command_execute_function_types_[cmd_id]) {
   case CONST_STANDARD:
@@ -420,6 +428,9 @@ void Shell<T>::execute_command(const char* cmd_line,
     /* Exit the shell using the exit() function inside this class! */
     exit();
   }
+
+  /* Change the status of the command */
+  command_status_[cmd_id] = true;
 }
 
 /************************************************************************
diff --git a/libopenfpga/libopenfpgashell/test/test_shell.cpp b/libopenfpga/libopenfpgashell/test/test_shell.cpp
index 154986be7..649859d85 100644
--- a/libopenfpga/libopenfpgashell/test/test_shell.cpp
+++ b/libopenfpga/libopenfpgashell/test/test_shell.cpp
@@ -102,11 +102,13 @@ int main(int argc, char** argv) {
 
   /* Create a command of 'print' 
    * This function will print the value of an internal variable of ShellContext 
+   * We set a dependency to this command as it MUST be executed after 'set'
    */
   Command shell_cmd_print("print");
   ShellCommandId shell_cmd_print_id = shell.add_command(shell_cmd_print, "Print the value of internal variable 'a'");
   shell.set_command_class(shell_cmd_print_id, arith_cmd_class);
   shell.set_command_execute_function(shell_cmd_print_id, shell_execute_print);
+  shell.set_command_dependency(shell_cmd_print_id, std::vector<ShellCommandId>(1, shell_cmd_set_id));
 
   /* Create a macro command of 'print_macro' 
    * This function will print the value of an internal variable of ShellContext 

From a7a1fe8a746c44a7a49d1c83fef5da201fa6f9b0 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 24 Jan 2020 16:57:14 -0700
Subject: [PATCH 010/645] simplify openfpga title page and add command
 dependency on read_arch and write_arch

---
 openfpga/src/base/openfpga_setup_command.cpp | 2 ++
 openfpga/src/base/openfpga_title.cpp         | 6 ++----
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/openfpga/src/base/openfpga_setup_command.cpp b/openfpga/src/base/openfpga_setup_command.cpp
index 99d827bfb..322378b07 100644
--- a/openfpga/src/base/openfpga_setup_command.cpp
+++ b/openfpga/src/base/openfpga_setup_command.cpp
@@ -36,6 +36,8 @@ void add_openfpga_setup_commands(openfpga::Shell<OpenfpgaContext>& shell) {
   ShellCommandId shell_cmd_write_arch_id = shell.add_command(shell_cmd_write_arch, "write OpenFPGA architecture file");
   shell.set_command_class(shell_cmd_write_arch_id, openfpga_setup_cmd_class);
   shell.set_command_const_execute_function(shell_cmd_write_arch_id, write_arch);
+  /* The 'write_openfpga_arch' command should be executed before 'read_openfpga_arch' */
+  shell.set_command_dependency(shell_cmd_write_arch_id, std::vector<ShellCommandId>(1, shell_cmd_read_arch_id));
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_title.cpp b/openfpga/src/base/openfpga_title.cpp
index 4a33bb72e..8a3917ead 100644
--- a/openfpga/src/base/openfpga_title.cpp
+++ b/openfpga/src/base/openfpga_title.cpp
@@ -14,11 +14,9 @@ const char* create_openfpga_title() {
   title += std::string("\n");
   title += std::string("               OpenFPGA: An Open-source FPGA IP Generator\n");
   title += std::string("\n");
-  title += std::string("Contributors: Xifan Tang\tAurelien Alacchi\tBaudouin Chauviere\n");
+  title += std::string("             This is a free software under the MIT License\n");
   title += std::string("\n");
-  title += std::string("The MIT License\n");
-  title += std::string("\n");
-  title += std::string("Copyright (c) 2018 LNIS - The University of Utah\n");
+  title += std::string("             Copyright (c) 2018 LNIS - The University of Utah\n");
   title += std::string("\n");
   title += std::string("Permission is hereby granted, free of charge, to any person obtaining a copy\n");
   title += std::string("of this software and associated documentation files (the \"Software\"), to deal\n");

From 5039af2c2f90f0604a67d03fe20150389d317c71 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 24 Jan 2020 17:00:53 -0700
Subject: [PATCH 011/645] update title page

---
 openfpga/src/base/openfpga_title.cpp | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/openfpga/src/base/openfpga_title.cpp b/openfpga/src/base/openfpga_title.cpp
index 8a3917ead..ae4ce80c4 100644
--- a/openfpga/src/base/openfpga_title.cpp
+++ b/openfpga/src/base/openfpga_title.cpp
@@ -13,6 +13,11 @@ const char* create_openfpga_title() {
 
   title += std::string("\n");
   title += std::string("               OpenFPGA: An Open-source FPGA IP Generator\n");
+  title += std::string("                     Versatile Place and Route (VPR)\n");
+  title += std::string("                           FPGA-Verilog\n");
+  title += std::string("                           FPGA-SPICE\n");
+  title += std::string("                           FPGA-SDC\n");
+  title += std::string("                           FPGA-Bitstream\n");
   title += std::string("\n");
   title += std::string("             This is a free software under the MIT License\n");
   title += std::string("\n");

From 7feeee8c0e46aacf30639a7107bcac54a0b62426 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 25 Jan 2020 17:38:06 -0700
Subject: [PATCH 012/645] add full syntax to sample_arch.xml about the physical
 pb_type binding

---
 .../libarchopenfpga/arch/sample_arch.xml      | 35 +++++++++++++++----
 1 file changed, 28 insertions(+), 7 deletions(-)

diff --git a/libopenfpga/libarchopenfpga/arch/sample_arch.xml b/libopenfpga/libarchopenfpga/arch/sample_arch.xml
index 6d6484f7e..c27233427 100644
--- a/libopenfpga/libarchopenfpga/arch/sample_arch.xml
+++ b/libopenfpga/libarchopenfpga/arch/sample_arch.xml
@@ -270,18 +270,39 @@
   </direct_connection-->
   <complex_blocks>
     <pb_type name="io" physical_mode_name="io_phy"/>
-    <mode name="io[io_phy]" disable_in_packing="true"/>
     <pb_type name="io[io_phy].iopad" circuit_model_name="iopad" mode_bits="1"/> 
-    <pb_type name="io[io_phy].inpad" physical_pb_type_name="iopad" mode_bits="1"/> 
-    <pb_type name="io[io_phy].outpad" physical_pb_type_name="iopad" mode_bits="0"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="iopad" mode_bits="0"/> 
     <pb_type name="clb.fle" physical_mode_name="fle_phy" idle_mode_name="n2_lut5"/>
     <pb_type name="clb.fle[fle_phy].frac_logic.frac_lut6" mode_bits="11" circuit_model_name="frac_lut6"/>
     <pb_type name="clb.fle[fle_phy].frac_logic.adder_phy" circuit_model_name="adder"/>
     <pb_type name="clb.fle[fle_phy].frac_logic.ff_phy" circuit_model_name="static_dff"/>
-    <mode name="fle_phy" disabled_in_packing="true"/>
-    <pb_type name="lut5" mode_bits="01" physical_pb_type_name="frac_lut6" physical_pb_type_index_factor="0.5"/>
-    <input name="in" physical_mode_pin="in[5:0]"/>
-    <output name="out" physical_mode_pin="lut5_out" physical_mode_pin_rotate_offset="1"/>
+    <pb_type name="clb.fle[n2_lut5].lut5_inter.ble5[blut5].flut5.lut5" mode_bits="01" physical_pb_type_name="clb.fle[fle_phy].frac_logic.frac_lut6" physical_pb_type_index_factor="0.5">
+      <!-- If not specified, we by default assume the physical mode pin share the same name -->
+      <input name="in" physical_mode_pin="in[4:0]"/>
+      <output name="out" physical_mode_pin="lut5_out" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[n2_lut5].lut5_inter.ble5[blut5].flut5.ff" physical_pb_type_name="clb.fle[fle_phy].frac_logic.ff_phy"/>
+    <pb_type name="clb.fle[n2_lut5].lut5_inter.ble5[arithmetic].arithemetic.lut4" mode_bits="11" physical_pb_type_name="clb.fle[fle_phy].frac_logic.frac_lut6">
+      <!-- If not specified, we by default assume the physical mode pin share the same name -->
+      <input name="in" physical_mode_pin="in[3:0]"/>
+      <output name="out" physical_mode_pin="lut4_out" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[n2_lut5].lut5_inter.ble5[arithmetic].arithemetic.adder" physical_pb_type_name="clb.fle[fle_phy].frac_logic.adder_phy"/>
+    <pb_type name="clb.fle[n2_lut5].lut5_inter.ble5[arithmetic].arithemetic.ff" physical_pb_type_name="clb.fle[fle_phy].frac_logic.ff_phy"/>
+    <pb_type name="clb.fle[n1_lut6].ble6.lut6" mode_bits="00" physical_pb_type_name="clb.fle[fle_phy].frac_logic.frac_lut6">
+      <!-- If not specified, we by default assume the physical mode pin share the same name -->
+      <input name="in" physical_mode_pin="in[5:0]"/>
+      <output name="out" physical_mode_pin="lut6_out"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[fle_phy].frac_logic.ff_phy" physical_pb_type_index_factor="2" physical_pb_type_index_offset="1"/>
+    <pb_type name="clb.fle[shift_register].ble6_shift.ff" physical_pb_type_name="clb.fle[fle_phy].frac_logic.ff_phy"/>
+    <interconnect name="clb.crossbar0" circuit_model_name="mux_2level"/>
+    <interconnect name="clb.crossbar1" circuit_model_name="mux_2level"/>
+    <interconnect name="clb.crossbar2" circuit_model_name="mux_2level"/>
+    <interconnect name="clb.crossbar3" circuit_model_name="mux_2level"/>
+    <interconnect name="clb.crossbar4" circuit_model_name="mux_2level"/>
+    <interconnect name="clb.crossbar5" circuit_model_name="mux_2level"/>
   </complex_blocks>
 </openfpga_architecture>
 <openfpga_simulation_setting>

From b4f4bf62a2e5d044c1140c1ed11f56caf09fc886 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 25 Jan 2020 17:42:24 -0700
Subject: [PATCH 013/645] add comments to sample arch

---
 libopenfpga/libarchopenfpga/arch/sample_arch.xml | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/libopenfpga/libarchopenfpga/arch/sample_arch.xml b/libopenfpga/libarchopenfpga/arch/sample_arch.xml
index c27233427..8d19fc150 100644
--- a/libopenfpga/libarchopenfpga/arch/sample_arch.xml
+++ b/libopenfpga/libarchopenfpga/arch/sample_arch.xml
@@ -265,14 +265,18 @@
   <routing_segment>
     <segment name="L4" circuit_model_name="chan_segment"/>
   </routing_segment>
-  <!--direct_connection>
+  <direct_connection>
     <direct name="adder" circuit_model_name="direct_interc"/>
-  </direct_connection-->
+  </direct_connection>
   <complex_blocks>
+    <!-- physical pb_type binding in complex block IO -->
     <pb_type name="io" physical_mode_name="io_phy"/>
     <pb_type name="io[io_phy].iopad" circuit_model_name="iopad" mode_bits="1"/> 
     <pb_type name="io[inpad].inpad" physical_pb_type_name="iopad" mode_bits="1"/> 
     <pb_type name="io[outpad].outpad" physical_pb_type_name="iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
     <pb_type name="clb.fle" physical_mode_name="fle_phy" idle_mode_name="n2_lut5"/>
     <pb_type name="clb.fle[fle_phy].frac_logic.frac_lut6" mode_bits="11" circuit_model_name="frac_lut6"/>
     <pb_type name="clb.fle[fle_phy].frac_logic.adder_phy" circuit_model_name="adder"/>
@@ -297,12 +301,14 @@
     </pb_type>
     <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[fle_phy].frac_logic.ff_phy" physical_pb_type_index_factor="2" physical_pb_type_index_offset="1"/>
     <pb_type name="clb.fle[shift_register].ble6_shift.ff" physical_pb_type_name="clb.fle[fle_phy].frac_logic.ff_phy"/>
+    <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
     <interconnect name="clb.crossbar0" circuit_model_name="mux_2level"/>
     <interconnect name="clb.crossbar1" circuit_model_name="mux_2level"/>
     <interconnect name="clb.crossbar2" circuit_model_name="mux_2level"/>
     <interconnect name="clb.crossbar3" circuit_model_name="mux_2level"/>
     <interconnect name="clb.crossbar4" circuit_model_name="mux_2level"/>
     <interconnect name="clb.crossbar5" circuit_model_name="mux_2level"/>
+    <!-- End physical pb_type binding in complex block IO -->
   </complex_blocks>
 </openfpga_architecture>
 <openfpga_simulation_setting>

From f834954698f1165850cb3abc5538b0d8f5bb042f Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 25 Jan 2020 18:14:38 -0700
Subject: [PATCH 014/645] start developing the pb_type annotation

---
 .../libarchopenfpga/src/pb_annotation.h       | 52 +++++++++++++++++++
 1 file changed, 52 insertions(+)
 create mode 100644 libopenfpga/libarchopenfpga/src/pb_annotation.h

diff --git a/libopenfpga/libarchopenfpga/src/pb_annotation.h b/libopenfpga/libarchopenfpga/src/pb_annotation.h
new file mode 100644
index 000000000..2cd92d3a7
--- /dev/null
+++ b/libopenfpga/libarchopenfpga/src/pb_annotation.h
@@ -0,0 +1,52 @@
+#ifndef PB_PHYSICAL_ANNOTATION_H
+#ifndef PB_PHYSICAL_ANNOTATION_H
+
+/********************************************************************
+ * Include header files required by the data structure definition
+ *******************************************************************/
+#include <vector>
+#include <map>
+
+/********************************************************************
+ * This file include the declaration of data structures
+ * to store physical pb_type annotation, including
+ * 1. the binding between operating pb_type and physical_pb_type
+ *    this also cover the binding between pins of any pair of pb_types
+ * 2. the binding between physical pb_type and circuit models
+ * 3. the binding between interconnect under pb_types and circuit models
+ *    This is only applicable to physical pb_types
+ *
+ * Each PhysicalPbAnnotation includes the binding for ONLY a pb_type
+ * defined in the architecture XML
+ *
+ * Note:
+ * 1. Keep this data structure as general as possible. It is supposed
+ *    to contain the raw data from architecture XML! If you want to link
+ *    to other data structures, please create another one in other header files
+ *******************************************************************/
+class PhysicalPbAnnotation {
+  private: /* Internal data */
+    /* Binding between physical pb_type and operating pb_type 
+     * both operating and physial pb_type names are the full names 
+     * defined in the hierarchy of pb_types
+     * e.g.
+     *    clb.fle[frac_logic].frac_lut6
+     */
+    std::string operating_pb_type_name_;
+    std::string physical_pb_type_name_;
+    std::string mode_bits_;
+    std::string circuit_model_name_;
+    int physical_pb_type_index_factor_;
+    int physical_pb_type_index_offset_;
+
+    /* Link from the pins under an operating pb_type to physical pb_type  */
+    std::vector<std::string> operating_pb_type_pin_names_;
+    std::vector<std::string> physical_pb_type_pin_names_;
+    std::vector<int> physical_pin_rotate_offset_;
+
+    /* Link between the interconnects under this pb_type and circuit model names */
+    std::vector<std:map<std::string, std::string>> interconnect_circuit_model_names_;
+};
+
+#endif
+

From 9b4b6ae083d0a6cd58e45d43c6f51732eb0b5485 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 25 Jan 2020 18:17:00 -0700
Subject: [PATCH 015/645] rename pb_annotation and move it to openfpga
 namespace

---
 .../src/{pb_annotation.h => pb_type_annotation.h}        | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)
 rename libopenfpga/libarchopenfpga/src/{pb_annotation.h => pb_type_annotation.h} (93%)

diff --git a/libopenfpga/libarchopenfpga/src/pb_annotation.h b/libopenfpga/libarchopenfpga/src/pb_type_annotation.h
similarity index 93%
rename from libopenfpga/libarchopenfpga/src/pb_annotation.h
rename to libopenfpga/libarchopenfpga/src/pb_type_annotation.h
index 2cd92d3a7..bad6489b0 100644
--- a/libopenfpga/libarchopenfpga/src/pb_annotation.h
+++ b/libopenfpga/libarchopenfpga/src/pb_type_annotation.h
@@ -1,5 +1,5 @@
-#ifndef PB_PHYSICAL_ANNOTATION_H
-#ifndef PB_PHYSICAL_ANNOTATION_H
+#ifndef PB_TYPE_ANNOTATION_H
+#ifndef PB_TYPE_ANNOTATION_H
 
 /********************************************************************
  * Include header files required by the data structure definition
@@ -7,6 +7,9 @@
 #include <vector>
 #include <map>
 
+/* namespace openfpga begins */
+namespace openfpga {
+
 /********************************************************************
  * This file include the declaration of data structures
  * to store physical pb_type annotation, including
@@ -48,5 +51,7 @@ class PhysicalPbAnnotation {
     std::vector<std:map<std::string, std::string>> interconnect_circuit_model_names_;
 };
 
+} /* namespace openfpga ends */
+
 #endif
 

From b6f96e5a8fe7b7244f83a53a2372a76545393e87 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 25 Jan 2020 20:46:21 -0700
Subject: [PATCH 016/645] add method functions to pb_type annotation

---
 .../libarchopenfpga/arch/sample_arch.xml      |  17 +-
 .../src/pb_type_annotation.cpp                | 181 ++++++++++++++++++
 .../libarchopenfpga/src/pb_type_annotation.h  | 105 +++++++++-
 3 files changed, 289 insertions(+), 14 deletions(-)
 create mode 100644 libopenfpga/libarchopenfpga/src/pb_type_annotation.cpp

diff --git a/libopenfpga/libarchopenfpga/arch/sample_arch.xml b/libopenfpga/libarchopenfpga/arch/sample_arch.xml
index 8d19fc150..49eccdaa8 100644
--- a/libopenfpga/libarchopenfpga/arch/sample_arch.xml
+++ b/libopenfpga/libarchopenfpga/arch/sample_arch.xml
@@ -277,6 +277,16 @@
     <!-- End physical pb_type binding in complex block IO -->
 
     <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar0" circuit_model_name="mux_2level"/>
+      <interconnect name="crossbar1" circuit_model_name="mux_2level"/>
+      <interconnect name="crossbar2" circuit_model_name="mux_2level"/>
+      <interconnect name="crossbar3" circuit_model_name="mux_2level"/>
+      <interconnect name="crossbar4" circuit_model_name="mux_2level"/>
+      <interconnect name="crossbar5" circuit_model_name="mux_2level"/>
+    </pb_type>
     <pb_type name="clb.fle" physical_mode_name="fle_phy" idle_mode_name="n2_lut5"/>
     <pb_type name="clb.fle[fle_phy].frac_logic.frac_lut6" mode_bits="11" circuit_model_name="frac_lut6"/>
     <pb_type name="clb.fle[fle_phy].frac_logic.adder_phy" circuit_model_name="adder"/>
@@ -301,13 +311,6 @@
     </pb_type>
     <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[fle_phy].frac_logic.ff_phy" physical_pb_type_index_factor="2" physical_pb_type_index_offset="1"/>
     <pb_type name="clb.fle[shift_register].ble6_shift.ff" physical_pb_type_name="clb.fle[fle_phy].frac_logic.ff_phy"/>
-    <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
-    <interconnect name="clb.crossbar0" circuit_model_name="mux_2level"/>
-    <interconnect name="clb.crossbar1" circuit_model_name="mux_2level"/>
-    <interconnect name="clb.crossbar2" circuit_model_name="mux_2level"/>
-    <interconnect name="clb.crossbar3" circuit_model_name="mux_2level"/>
-    <interconnect name="clb.crossbar4" circuit_model_name="mux_2level"/>
-    <interconnect name="clb.crossbar5" circuit_model_name="mux_2level"/>
     <!-- End physical pb_type binding in complex block IO -->
   </complex_blocks>
 </openfpga_architecture>
diff --git a/libopenfpga/libarchopenfpga/src/pb_type_annotation.cpp b/libopenfpga/libarchopenfpga/src/pb_type_annotation.cpp
new file mode 100644
index 000000000..dda74520b
--- /dev/null
+++ b/libopenfpga/libarchopenfpga/src/pb_type_annotation.cpp
@@ -0,0 +1,181 @@
+/************************************************************************
+ * Member functions for class PbTypeAnnotation
+ ***********************************************************************/
+#include "vtr_log.h"
+#include "vtr_assert.h"
+#include "pb_type_annotation.h"
+
+/* namespace openfpga begins */
+namespace openfpga {
+
+/************************************************************************
+ * Constructors
+ ***********************************************************************/
+PbTypeAnnotation::PbTypeAnnotation() {
+  return;
+}
+
+/************************************************************************
+ * Public Accessors
+ ***********************************************************************/
+std::string PbTypeAnnotation::operating_pb_type_name() const {
+  return operating_pb_type_name_;
+}
+
+std::vector<std::string> PbTypeAnnotation::operating_parent_pb_type_names() const {
+  return operating_parent_pb_type_names_;
+}
+
+std::vector<std::string> PbTypeAnnotation::operating_parent_mode_names() const {
+  return operating_parent_mode_names_;
+}
+
+bool PbTypeAnnotation::is_operating_pb_type() const {
+  return true == operating_pb_type_name_.empty();
+}
+
+
+std::string PbTypeAnnotation::physical_pb_type_name() const {
+  return physical_pb_type_name_;
+}
+
+std::vector<std::string> PbTypeAnnotation::physical_parent_pb_type_names() const {
+  return physical_parent_pb_type_names_;
+}
+
+std::vector<std::string> PbTypeAnnotation::physical_parent_mode_names() const {
+  return physical_parent_mode_names_;
+}
+
+bool PbTypeAnnotation::is_physical_pb_type() const {
+  return true == physical_pb_type_name_.empty();
+}
+
+std::string PbTypeAnnotation::mode_bits() const {
+  return mode_bits_;
+}
+
+std::string PbTypeAnnotation::circuit_model_name() const {
+  return circuit_model_name_;
+}
+
+int PbTypeAnnotation::physical_pb_type_index_factor() const {
+  return physical_pb_type_index_factor_;
+}
+
+int PbTypeAnnotation::physical_pb_type_index_offset() const {
+  return physical_pb_type_index_offset_;
+}
+
+BasicPort PbTypeAnnotation::physical_pb_type_ports(const std::string& port_name) const {
+  std::map<std::string, BasicPort>::const_iterator it = operating_pb_type_ports_.find(port_name);
+  if (it == operating_pb_type_ports_.end()) {
+    /* Return an empty port */
+    return BasicPort();
+  }
+  return operating_pb_type_ports_.at(port_name);
+}
+
+int PbTypeAnnotation::physical_pin_rotate_offsets(const std::string& port_name) const {
+  std::map<std::string, int>::const_iterator it = physical_pin_rotate_offsets_.find(port_name);
+  if (it == physical_pin_rotate_offsets_.end()) {
+    /* Return a zero offset which is default */
+    return 0;
+  }
+  return physical_pin_rotate_offsets_.at(port_name);
+}
+
+std::string PbTypeAnnotation::interconnect_circuit_model_name(const std::string& interc_name) const {
+  std::map<std::string, std::string>::const_iterator it = interconnect_circuit_model_names_.find(interc_name);
+  if (it == interconnect_circuit_model_names_.end()) {
+    return std::string();
+  }
+
+  return interconnect_circuit_model_names_.at(interc_name);
+}
+
+/************************************************************************
+ * Public Mutators
+ ***********************************************************************/
+void PbTypeAnnotation::set_operating_pb_type_name(const std::string& name) {
+  operating_pb_type_name_ = name;
+}
+
+void PbTypeAnnotation::set_operating_parent_pb_type_names(const std::vector<std::string>& names) {
+  operating_parent_pb_type_names_ = names;
+}
+
+void PbTypeAnnotation::set_operating_parent_mode_names(const std::vector<std::string>& names) {
+  operating_parent_mode_names_ = names;
+}
+
+void PbTypeAnnotation::set_physical_pb_type_name(const std::string& name) {
+  physical_pb_type_name_ = name;
+}
+
+void PbTypeAnnotation::set_physical_parent_pb_type_names(const std::vector<std::string>& names) {
+  physical_parent_pb_type_names_ = names;
+}
+
+void PbTypeAnnotation::set_physical_parent_mode_names(const std::vector<std::string>& names) {
+  physical_parent_mode_names_ = names;
+}
+
+void PbTypeAnnotation::set_mode_bits(const std::string& mode_bits) {
+  mode_bits_ = mode_bits;
+}
+
+void PbTypeAnnotation::set_circuit_model_name(const std::string& name) {
+  VTR_ASSERT(true == is_physical_pb_type());
+  circuit_model_name_ = name;
+}
+
+void PbTypeAnnotation::physical_pb_type_index_factor(const int& value) {
+  VTR_ASSERT(true == is_operating_pb_type());
+  physical_pb_type_index_factor_ = value;
+}
+
+void PbTypeAnnotation::physical_pb_type_index_offset(const int& value) {
+  VTR_ASSERT(true == is_operating_pb_type());
+  physical_pb_type_index_offset_ = value;
+}
+
+void PbTypeAnnotation::add_pb_type_port_pair(const std::string& operating_pb_port_name,
+                                             const BasicPort& physical_pb_port) {
+  /* Give a warning if the operating_pb_port_name already exist */
+  std::map<std::string, BasicPort>::const_iterator it = operating_pb_type_ports_.find(operating_pb_port_name);
+  /* Give a warning if the interconnection name already exist */
+  if (it != operating_pb_type_ports_.end()) {
+    VTR_LOG_WARN("Redefine operating pb type port '%s' with physical pb type port '%s'\n",
+                  operating_pb_port_name.c_str(), physical_pb_port.get_name().c_str());
+  }
+
+  operating_pb_type_ports_[operating_pb_port_name] = physical_pb_port;
+}
+
+void PbTypeAnnotation::set_physical_pin_rotate_offset(const std::string& operating_pb_port_name,
+                                                      const int& physical_pin_rotate_offset) {
+  std::map<std::string, BasicPort>::const_iterator it = operating_pb_type_ports_.find(operating_pb_port_name);
+  /* Give a warning if the interconnection name already exist */
+  if (it == operating_pb_type_ports_.end()) {
+    VTR_LOG_ERROR("Operating pb type port '%s' does not exist! Ignore physical pin rotate offset '%d'\n",
+                  operating_pb_port_name.c_str(), physical_pin_rotate_offset);
+    return;
+  }
+
+  physical_pin_rotate_offsets_[operating_pb_port_name] = physical_pin_rotate_offset;
+}
+
+void PbTypeAnnotation::add_interconnect_circuit_model_pair(const std::string& interc_name,
+                                                           const std::string& circuit_model_name) {
+  std::map<std::string, std::string>::const_iterator it = interconnect_circuit_model_names_.find(interc_name);
+  /* Give a warning if the interconnection name already exist */
+  if (it != interconnect_circuit_model_names_.end()) {
+    VTR_LOG_WARN("Redefine interconnect '%s' with circuit model '%s'\n",
+                 interc_name.c_str(), circuit_model_name.c_str());
+  }
+
+  interconnect_circuit_model_names_[interc_name] = circuit_model_name;
+}
+
+} /* namespace openfpga ends */
diff --git a/libopenfpga/libarchopenfpga/src/pb_type_annotation.h b/libopenfpga/libarchopenfpga/src/pb_type_annotation.h
index bad6489b0..e2ca62df6 100644
--- a/libopenfpga/libarchopenfpga/src/pb_type_annotation.h
+++ b/libopenfpga/libarchopenfpga/src/pb_type_annotation.h
@@ -1,5 +1,5 @@
 #ifndef PB_TYPE_ANNOTATION_H
-#ifndef PB_TYPE_ANNOTATION_H
+#define PB_TYPE_ANNOTATION_H
 
 /********************************************************************
  * Include header files required by the data structure definition
@@ -7,6 +7,8 @@
 #include <vector>
 #include <map>
 
+#include "openfpga_port.h"
+
 /* namespace openfpga begins */
 namespace openfpga {
 
@@ -27,28 +29,117 @@ namespace openfpga {
  *    to contain the raw data from architecture XML! If you want to link
  *    to other data structures, please create another one in other header files
  *******************************************************************/
-class PhysicalPbAnnotation {
+class PbTypeAnnotation {
+  public:  /* Constructor */
+    PbTypeAnnotation();
+  public:  /* Public accessors */
+    std::string operating_pb_type_name() const;
+    std::vector<std::string> operating_parent_pb_type_names() const;
+    std::vector<std::string> operating_parent_mode_names() const;
+    bool is_operating_pb_type() const;
+    std::string physical_pb_type_name() const;
+    std::vector<std::string> physical_parent_pb_type_names() const;
+    std::vector<std::string> physical_parent_mode_names() const;
+    bool is_physical_pb_type() const;
+    std::string mode_bits() const;
+    std::string circuit_model_name() const;
+    int physical_pb_type_index_factor() const;
+    int physical_pb_type_index_offset() const;
+    BasicPort physical_pb_type_ports(const std::string& port_name) const;
+    int physical_pin_rotate_offsets(const std::string& port_name) const;
+    std::string interconnect_circuit_model_name(const std::string& interc_name) const;
+  public: /* Public mutators */
+    void set_operating_pb_type_name(const std::string& name);
+    void set_operating_parent_pb_type_names(const std::vector<std::string>& names);
+    void set_operating_parent_mode_names(const std::vector<std::string>& names);
+    void set_physical_pb_type_name(const std::string& name);
+    void set_physical_parent_pb_type_names(const std::vector<std::string>& names);
+    void set_physical_parent_mode_names(const std::vector<std::string>& names);
+    void set_mode_bits(const std::string& mode_bits);
+    void set_circuit_model_name(const std::string& name);
+    void physical_pb_type_index_factor(const int& value);
+    void physical_pb_type_index_offset(const int& value);
+    void add_pb_type_port_pair(const std::string& operating_pb_port_name,
+                               const BasicPort& physical_pb_port);
+    void set_physical_pin_rotate_offset(const std::string& operating_pb_port_name,
+                                        const int& physical_pin_rotate_offset);
+    void add_interconnect_circuit_model_pair(const std::string& interc_name,
+                                             const std::string& circuit_model_name);
   private: /* Internal data */
     /* Binding between physical pb_type and operating pb_type 
-     * both operating and physial pb_type names are the full names 
+     * both operating and physial pb_type names contain the full names 
      * defined in the hierarchy of pb_types
      * e.g.
      *    clb.fle[frac_logic].frac_lut6
+     *                ^
+     *                |
+     *             mode_name
+     *
+     * The pb_type name 'frac_lut6' will be stored in 
+     * either operating or physical pb_type_name
+     * The parent pb_type and mode names will be stored in
+     * either operating or physical parent_pb_type_name and parent_mode_names
+     *
      */
     std::string operating_pb_type_name_;
+    std::vector<std::string> operating_parent_pb_type_names_;
+    std::vector<std::string> operating_parent_mode_names_;
+
     std::string physical_pb_type_name_;
+    std::vector<std::string> physical_parent_pb_type_names_;
+    std::vector<std::string> physical_parent_mode_names_;
+
+    /* Configuration bits to select an operting mode for the circuit mode name */
     std::string mode_bits_;
+
+    /* Circuit mode name linked to a physical pb_type.
+     * This is only applicable to the physical pb_type
+     */
     std::string circuit_model_name_;
+
+    /* The factor aims to align the indices for pb_type between operating and physical modes, 
+     * especially when an operating mode contains multiple pb_type (num_pb>1) 
+     * that are linked to the same physical pb_type. 
+     * When number of physical_pb_type  is larger than 1, 
+     * the index of pb_type will be multipled by the given factor.
+     *
+     * For example, a factor of 2 is used to map 
+     * operating pb_type adder[5] with a full path clb.fle[arith].adder[5]
+     * to physical pb_type adder[10] with a full path clb.fle[physical].adder[10]
+     */
     int physical_pb_type_index_factor_;
+
+    /* The offset aims to align the indices for pb_type between operating and physical modes, 
+     * especially when an operating mode contains multiple pb_type (num_pb>1) 
+     * that are linked to the same physical pb_type. 
+     * When number of physical_pb_type is larger than 1, 
+     * the index of pb_type will be shifted by the given factor.
+     *
+     * For example, an offset of 1 is used to map 
+     * operating pb_type adder[0] with a full path clb.fle[arith].adder[0]
+     * to physical pb_type adder[1] with a full path clb.fle[physical].adder[1]
+     */
     int physical_pb_type_index_offset_;
 
     /* Link from the pins under an operating pb_type to physical pb_type  */
-    std::vector<std::string> operating_pb_type_pin_names_;
-    std::vector<std::string> physical_pb_type_pin_names_;
-    std::vector<int> physical_pin_rotate_offset_;
+    std::map<std::string, BasicPort> operating_pb_type_ports_;
+
+    /* The offset aims to align the pin indices for port of pb_type 
+     * between operating and physical modes, especially when an operating 
+     * mode contains multiple pb_type (num_pb>1) that are linked to 
+     * the same physical pb_type. 
+     * When physical_mode_pin_rotate_offset is larger than zero, 
+     * the pin index of pb_type (whose index is large than 1) 
+     * will be shifted by the given offset.
+     *
+     * For example, an offset of 1 is used to map 
+     * operating pb_type adder[0].pin[0] with a full path clb.fle[arith].adder[0]
+     * to physical pb_type adder[0].pin[1] with a full path clb.fle[physical].adder[0]
+     */
+    std::map<std::string, int> physical_pin_rotate_offsets_;
 
     /* Link between the interconnects under this pb_type and circuit model names */
-    std::vector<std:map<std::string, std::string>> interconnect_circuit_model_names_;
+    std::map<std::string, std::string> interconnect_circuit_model_names_;
 };
 
 } /* namespace openfpga ends */

From bafd866cfc37b34bc3123adc39fbf706a2a86b58 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 25 Jan 2020 21:19:08 -0700
Subject: [PATCH 017/645] start developing XML parser for pb_type annotation

---
 .../libarchopenfpga/arch/sample_arch.xml      | 16 ++--
 .../libarchopenfpga/src/openfpga_arch.h       |  8 ++
 .../src/read_xml_openfpga_arch.cpp            |  6 +-
 .../src/read_xml_pb_type_annotation.cpp       | 74 +++++++++++++++++++
 .../src/read_xml_pb_type_annotation.h         | 17 +++++
 5 files changed, 112 insertions(+), 9 deletions(-)
 create mode 100644 libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.cpp
 create mode 100644 libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.h

diff --git a/libopenfpga/libarchopenfpga/arch/sample_arch.xml b/libopenfpga/libarchopenfpga/arch/sample_arch.xml
index 49eccdaa8..d3b289b05 100644
--- a/libopenfpga/libarchopenfpga/arch/sample_arch.xml
+++ b/libopenfpga/libarchopenfpga/arch/sample_arch.xml
@@ -268,7 +268,7 @@
   <direct_connection>
     <direct name="adder" circuit_model_name="direct_interc"/>
   </direct_connection>
-  <complex_blocks>
+  <pb_type_annotations>
     <!-- physical pb_type binding in complex block IO -->
     <pb_type name="io" physical_mode_name="io_phy"/>
     <pb_type name="io[io_phy].iopad" circuit_model_name="iopad" mode_bits="1"/> 
@@ -293,26 +293,26 @@
     <pb_type name="clb.fle[fle_phy].frac_logic.ff_phy" circuit_model_name="static_dff"/>
     <pb_type name="clb.fle[n2_lut5].lut5_inter.ble5[blut5].flut5.lut5" mode_bits="01" physical_pb_type_name="clb.fle[fle_phy].frac_logic.frac_lut6" physical_pb_type_index_factor="0.5">
       <!-- If not specified, we by default assume the physical mode pin share the same name -->
-      <input name="in" physical_mode_pin="in[4:0]"/>
-      <output name="out" physical_mode_pin="lut5_out" physical_mode_pin_rotate_offset="1"/>
+      <port name="in" physical_mode_pin="in[4:0]"/>
+      <port name="out" physical_mode_pin="lut5_out" physical_mode_pin_rotate_offset="1"/>
     </pb_type>
     <pb_type name="clb.fle[n2_lut5].lut5_inter.ble5[blut5].flut5.ff" physical_pb_type_name="clb.fle[fle_phy].frac_logic.ff_phy"/>
     <pb_type name="clb.fle[n2_lut5].lut5_inter.ble5[arithmetic].arithemetic.lut4" mode_bits="11" physical_pb_type_name="clb.fle[fle_phy].frac_logic.frac_lut6">
       <!-- If not specified, we by default assume the physical mode pin share the same name -->
-      <input name="in" physical_mode_pin="in[3:0]"/>
-      <output name="out" physical_mode_pin="lut4_out" physical_mode_pin_rotate_offset="1"/>
+      <port name="in" physical_mode_pin="in[3:0]"/>
+      <port name="out" physical_mode_pin="lut4_out" physical_mode_pin_rotate_offset="1"/>
     </pb_type>
     <pb_type name="clb.fle[n2_lut5].lut5_inter.ble5[arithmetic].arithemetic.adder" physical_pb_type_name="clb.fle[fle_phy].frac_logic.adder_phy"/>
     <pb_type name="clb.fle[n2_lut5].lut5_inter.ble5[arithmetic].arithemetic.ff" physical_pb_type_name="clb.fle[fle_phy].frac_logic.ff_phy"/>
     <pb_type name="clb.fle[n1_lut6].ble6.lut6" mode_bits="00" physical_pb_type_name="clb.fle[fle_phy].frac_logic.frac_lut6">
       <!-- If not specified, we by default assume the physical mode pin share the same name -->
-      <input name="in" physical_mode_pin="in[5:0]"/>
-      <output name="out" physical_mode_pin="lut6_out"/>
+      <port name="in" physical_mode_pin="in[5:0]"/>
+      <port name="out" physical_mode_pin="lut6_out"/>
     </pb_type>
     <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[fle_phy].frac_logic.ff_phy" physical_pb_type_index_factor="2" physical_pb_type_index_offset="1"/>
     <pb_type name="clb.fle[shift_register].ble6_shift.ff" physical_pb_type_name="clb.fle[fle_phy].frac_logic.ff_phy"/>
     <!-- End physical pb_type binding in complex block IO -->
-  </complex_blocks>
+  </pb_type_annotations>
 </openfpga_architecture>
 <openfpga_simulation_setting>
   <clock_setting>
diff --git a/libopenfpga/libarchopenfpga/src/openfpga_arch.h b/libopenfpga/libarchopenfpga/src/openfpga_arch.h
index 491d8471a..7f102dc85 100644
--- a/libopenfpga/libarchopenfpga/src/openfpga_arch.h
+++ b/libopenfpga/libarchopenfpga/src/openfpga_arch.h
@@ -1,12 +1,14 @@
 #ifndef OPENFPGA_ARCH_H
 #define OPENFPGA_ARCH_H
 
+#include <vector>
 #include <map>
 
 #include "circuit_library.h"
 #include "technology_library.h"
 #include "simulation_setting.h"
 #include "config_protocol.h"
+#include "pb_type_annotation.h"
 
 /* namespace openfpga begins */
 namespace openfpga {
@@ -47,6 +49,12 @@ struct Arch {
    * to circuit models in circuit library 
    */
   std::map<std::string, CircuitModelId> direct2circuit;
+
+  /* Pb type annotations 
+   * Bind from operating to physical
+   * Bind from physical to circuit model
+   */
+  std::vector<PbTypeAnnotation> pb_type_annotations;
 };
 
 } /* namespace openfpga ends */
diff --git a/libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.cpp b/libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.cpp
index 10605b860..f30ff4f1e 100644
--- a/libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.cpp
+++ b/libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.cpp
@@ -21,6 +21,7 @@
 #include "read_xml_simulation_setting.h"
 #include "read_xml_config_protocol.h"
 #include "read_xml_routing_circuit.h"
+#include "read_xml_pb_type_annotation.h"
 #include "read_xml_openfpga_arch.h"
 #include "openfpga_arch_linker.h"
 
@@ -85,10 +86,13 @@ openfpga::Arch read_xml_openfpga_arch(const char* arch_file_name) {
     openfpga_arch.routing_seg2circuit = read_xml_routing_segment_circuit(xml_openfpga_arch, loc_data,
                                                                          openfpga_arch.circuit_lib);
 
-    /* Parse the routing segment circuit definition */
+    /* Parse the direct circuit definition */
     openfpga_arch.direct2circuit = read_xml_direct_circuit(xml_openfpga_arch, loc_data,
                                                            openfpga_arch.circuit_lib);
 
+    /* Parse the pb_type annotation */
+    openfpga_arch.pb_type_annotations = read_xml_pb_type_annotations(xml_openfpga_arch, loc_data);
+
     /* Second node should be <openfpga_simulation_setting> */
     auto xml_simulation_settings = get_single_child(doc, "openfpga_simulation_setting", loc_data); 
 
diff --git a/libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.cpp b/libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.cpp
new file mode 100644
index 000000000..9bf10a171
--- /dev/null
+++ b/libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.cpp
@@ -0,0 +1,74 @@
+/********************************************************************
+ * This file includes the top-level function of this library
+ * which reads an XML modeling OpenFPGA architecture to the associated
+ * data structures
+ *******************************************************************/
+#include <string>
+
+/* Headers from pugi XML library */
+#include "pugixml.hpp"
+#include "pugixml_util.hpp"
+
+/* Headers from vtr util library */
+#include "vtr_assert.h"
+
+/* Headers from libarchfpga */
+#include "arch_error.h"
+#include "read_xml_util.h"
+
+#include "read_xml_pb_type_annotation.h"
+
+/********************************************************************
+ * Parse XML description for a pb_type annotation under a <pb_type> XML node
+ *******************************************************************/
+static 
+void read_xml_pb_type_annotation(pugi::xml_node& xml_pb_type,
+                                 const pugiutil::loc_data& loc_data,
+                                 std::vector<openfpga::PbTypeAnnotation>& pb_type_annotations) {
+  openfpga::PbTypeAnnotation pb_type_annotation;
+
+  /* Find the name of pb_type */
+  const std::string& name_attr = get_attribute(xml_pb_type, "name", loc_data).as_string();
+  const std::string& physical_name_attr = get_attribute(xml_pb_type, "physical_pb_type_name", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string();
+
+  /* If both names are not empty, this is a operating pb_type */
+  if ( (false == name_attr.empty()) 
+    && (false == physical_name_attr.empty()) ) {
+    /* Parse the attributes for operating pb_type */
+    pb_type_annotation.set_operating_pb_type_name(name_attr);
+    pb_type_annotation.set_physical_pb_type_name(physical_name_attr);
+  } 
+
+  /* If there is only a name, this is a physical pb_type */
+  if ( (false == name_attr.empty()) 
+    && (true == physical_name_attr.empty()) ) {
+    pb_type_annotation.set_physical_pb_type_name(name_attr);
+  }
+
+  /* Finish parsing and add it to the vector */ 
+  pb_type_annotations.push_back(pb_type_annotation);
+}
+
+/********************************************************************
+ * Top function to parse XML description about pb_type annotation 
+ *******************************************************************/
+std::vector<openfpga::PbTypeAnnotation> read_xml_pb_type_annotations(pugi::xml_node& Node,
+                                                                     const pugiutil::loc_data& loc_data) {
+  std::vector<openfpga::PbTypeAnnotation> pb_type_annotations;
+
+  /* Parse configuration protocol root node */
+  pugi::xml_node xml_annotations = get_single_child(Node, "pb_type_annotations", loc_data);
+
+  /* Iterate over the children under this node,
+   * each child should be named after <pb_type>
+   */
+  for (pugi::xml_node xml_pb_type : xml_annotations.children()) {
+    /* Error out if the XML child has an invalid name! */
+    if (xml_pb_type.name() != std::string("pb_type")) {
+      bad_tag(xml_pb_type, loc_data, xml_annotations, {"pb_type"});
+    }
+    read_xml_pb_type_annotation(xml_pb_type, loc_data, pb_type_annotations);
+  } 
+
+  return pb_type_annotations;
+}
diff --git a/libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.h b/libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.h
new file mode 100644
index 000000000..98934a4b8
--- /dev/null
+++ b/libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.h
@@ -0,0 +1,17 @@
+#ifndef READ_XML_PB_TYPE_ANNOTATION_H
+#define READ_XML_PB_TYPE_ANNOTATION_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "pugixml_util.hpp"
+#include "pugixml.hpp"
+#include "pb_type_annotation.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+std::vector<openfpga::PbTypeAnnotation> read_xml_pb_type_annotations(pugi::xml_node& Node,
+                                                                     const pugiutil::loc_data& loc_data);
+
+#endif

From a9f03ce21b27405eb364f3482dce48916774b26f Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 26 Jan 2020 10:19:47 -0700
Subject: [PATCH 018/645] add XML attribute parsing for physical and operating
 pb_type annotation

---
 libopenfpga/libarchopenfpga/arch/sample_arch.xml |  2 +-
 .../libarchopenfpga/src/pb_type_annotation.cpp   | 16 ++++++++++++++++
 .../libarchopenfpga/src/pb_type_annotation.h     | 10 ++++++++++
 .../src/read_xml_pb_type_annotation.cpp          | 15 +++++++++++++++
 4 files changed, 42 insertions(+), 1 deletion(-)

diff --git a/libopenfpga/libarchopenfpga/arch/sample_arch.xml b/libopenfpga/libarchopenfpga/arch/sample_arch.xml
index d3b289b05..aaadd04ad 100644
--- a/libopenfpga/libarchopenfpga/arch/sample_arch.xml
+++ b/libopenfpga/libarchopenfpga/arch/sample_arch.xml
@@ -270,7 +270,7 @@
   </direct_connection>
   <pb_type_annotations>
     <!-- physical pb_type binding in complex block IO -->
-    <pb_type name="io" physical_mode_name="io_phy"/>
+    <pb_type name="io" physical_mode_name="io_phy" idle_mode_name="inpad"/>
     <pb_type name="io[io_phy].iopad" circuit_model_name="iopad" mode_bits="1"/> 
     <pb_type name="io[inpad].inpad" physical_pb_type_name="iopad" mode_bits="1"/> 
     <pb_type name="io[outpad].outpad" physical_pb_type_name="iopad" mode_bits="0"/> 
diff --git a/libopenfpga/libarchopenfpga/src/pb_type_annotation.cpp b/libopenfpga/libarchopenfpga/src/pb_type_annotation.cpp
index dda74520b..806a76c44 100644
--- a/libopenfpga/libarchopenfpga/src/pb_type_annotation.cpp
+++ b/libopenfpga/libarchopenfpga/src/pb_type_annotation.cpp
@@ -51,6 +51,14 @@ bool PbTypeAnnotation::is_physical_pb_type() const {
   return true == physical_pb_type_name_.empty();
 }
 
+std::string PbTypeAnnotation::physical_mode_name() const {
+  return physical_mode_name_;
+}
+
+std::string PbTypeAnnotation::idle_mode_name() const {
+  return idle_mode_name_;
+}
+
 std::string PbTypeAnnotation::mode_bits() const {
   return mode_bits_;
 }
@@ -121,6 +129,14 @@ void PbTypeAnnotation::set_physical_parent_mode_names(const std::vector<std::str
   physical_parent_mode_names_ = names;
 }
 
+void PbTypeAnnotation::set_physical_mode_name(const std::string& name) {
+  physical_mode_name_ = name;
+}
+
+void PbTypeAnnotation::set_idle_mode_name(const std::string& name) {
+  idle_mode_name_ = name;
+}
+
 void PbTypeAnnotation::set_mode_bits(const std::string& mode_bits) {
   mode_bits_ = mode_bits;
 }
diff --git a/libopenfpga/libarchopenfpga/src/pb_type_annotation.h b/libopenfpga/libarchopenfpga/src/pb_type_annotation.h
index e2ca62df6..8bf4480a8 100644
--- a/libopenfpga/libarchopenfpga/src/pb_type_annotation.h
+++ b/libopenfpga/libarchopenfpga/src/pb_type_annotation.h
@@ -41,6 +41,8 @@ class PbTypeAnnotation {
     std::vector<std::string> physical_parent_pb_type_names() const;
     std::vector<std::string> physical_parent_mode_names() const;
     bool is_physical_pb_type() const;
+    std::string physical_mode_name() const;
+    std::string idle_mode_name() const;
     std::string mode_bits() const;
     std::string circuit_model_name() const;
     int physical_pb_type_index_factor() const;
@@ -55,6 +57,8 @@ class PbTypeAnnotation {
     void set_physical_pb_type_name(const std::string& name);
     void set_physical_parent_pb_type_names(const std::vector<std::string>& names);
     void set_physical_parent_mode_names(const std::vector<std::string>& names);
+    void set_physical_mode_name(const std::string& name);
+    void set_idle_mode_name(const std::string& name);
     void set_mode_bits(const std::string& mode_bits);
     void set_circuit_model_name(const std::string& name);
     void physical_pb_type_index_factor(const int& value);
@@ -89,6 +93,12 @@ class PbTypeAnnotation {
     std::vector<std::string> physical_parent_pb_type_names_;
     std::vector<std::string> physical_parent_mode_names_;
 
+    /* Identify which mode is the physical implementation of an operating pb_type */
+    std::string physical_mode_name_;
+
+    /* Identify in which mode is the pb_type will operate when it is not used */
+    std::string idle_mode_name_;
+
     /* Configuration bits to select an operting mode for the circuit mode name */
     std::string mode_bits_;
 
diff --git a/libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.cpp b/libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.cpp
index 9bf10a171..7ac685436 100644
--- a/libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.cpp
+++ b/libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.cpp
@@ -30,6 +30,7 @@ void read_xml_pb_type_annotation(pugi::xml_node& xml_pb_type,
   /* Find the name of pb_type */
   const std::string& name_attr = get_attribute(xml_pb_type, "name", loc_data).as_string();
   const std::string& physical_name_attr = get_attribute(xml_pb_type, "physical_pb_type_name", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string();
+  const std::string& physical_mode_name_attr = get_attribute(xml_pb_type, "physical_mode_name", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string();
 
   /* If both names are not empty, this is a operating pb_type */
   if ( (false == name_attr.empty()) 
@@ -45,6 +46,20 @@ void read_xml_pb_type_annotation(pugi::xml_node& xml_pb_type,
     pb_type_annotation.set_physical_pb_type_name(name_attr);
   }
 
+  /* Parse physical mode name which are applied to both pb_types */
+  pb_type_annotation.set_physical_mode_name(get_attribute(xml_pb_type, "physical_mode_name", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string());
+
+  /* Parse idle mode name which are applied to both pb_types */
+  pb_type_annotation.set_idle_mode_name(get_attribute(xml_pb_type, "idle_mode_name", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string());
+
+  /* Parse mode bits which are applied to both pb_types */
+  pb_type_annotation.set_mode_bits(get_attribute(xml_pb_type, "mode_bits", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string());
+
+  /* If this is a physical pb_type, circuit model name is a mandatory attribute */
+  if (true == pb_type_annotation.is_physical_pb_type()) {
+    pb_type_annotation.set_circuit_model_name(get_attribute(xml_pb_type, "circuit_model_name", loc_data).as_string());
+  }
+
   /* Finish parsing and add it to the vector */ 
   pb_type_annotations.push_back(pb_type_annotation);
 }

From cd3565cf53086bae0509baeaa6c09e9b8dbf197b Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 26 Jan 2020 10:56:57 -0700
Subject: [PATCH 019/645] complete the XML parser for pb_type annotation

---
 .../libarchopenfpga/arch/sample_arch.xml      | 12 +--
 .../src/pb_type_annotation.cpp                |  4 +-
 .../libarchopenfpga/src/pb_type_annotation.h  |  4 +-
 .../src/read_xml_pb_type_annotation.cpp       | 77 +++++++++++++++++++
 4 files changed, 87 insertions(+), 10 deletions(-)

diff --git a/libopenfpga/libarchopenfpga/arch/sample_arch.xml b/libopenfpga/libarchopenfpga/arch/sample_arch.xml
index aaadd04ad..dafaa83dd 100644
--- a/libopenfpga/libarchopenfpga/arch/sample_arch.xml
+++ b/libopenfpga/libarchopenfpga/arch/sample_arch.xml
@@ -293,21 +293,21 @@
     <pb_type name="clb.fle[fle_phy].frac_logic.ff_phy" circuit_model_name="static_dff"/>
     <pb_type name="clb.fle[n2_lut5].lut5_inter.ble5[blut5].flut5.lut5" mode_bits="01" physical_pb_type_name="clb.fle[fle_phy].frac_logic.frac_lut6" physical_pb_type_index_factor="0.5">
       <!-- If not specified, we by default assume the physical mode pin share the same name -->
-      <port name="in" physical_mode_pin="in[4:0]"/>
-      <port name="out" physical_mode_pin="lut5_out" physical_mode_pin_rotate_offset="1"/>
+      <port name="in" physical_mode_port="in[4:0]"/>
+      <port name="out" physical_mode_port="lut5_out" physical_mode_pin_rotate_offset="1"/>
     </pb_type>
     <pb_type name="clb.fle[n2_lut5].lut5_inter.ble5[blut5].flut5.ff" physical_pb_type_name="clb.fle[fle_phy].frac_logic.ff_phy"/>
     <pb_type name="clb.fle[n2_lut5].lut5_inter.ble5[arithmetic].arithemetic.lut4" mode_bits="11" physical_pb_type_name="clb.fle[fle_phy].frac_logic.frac_lut6">
       <!-- If not specified, we by default assume the physical mode pin share the same name -->
-      <port name="in" physical_mode_pin="in[3:0]"/>
-      <port name="out" physical_mode_pin="lut4_out" physical_mode_pin_rotate_offset="1"/>
+      <port name="in" physical_mode_port="in[3:0]"/>
+      <port name="out" physical_mode_port="lut4_out" physical_mode_pin_rotate_offset="1"/>
     </pb_type>
     <pb_type name="clb.fle[n2_lut5].lut5_inter.ble5[arithmetic].arithemetic.adder" physical_pb_type_name="clb.fle[fle_phy].frac_logic.adder_phy"/>
     <pb_type name="clb.fle[n2_lut5].lut5_inter.ble5[arithmetic].arithemetic.ff" physical_pb_type_name="clb.fle[fle_phy].frac_logic.ff_phy"/>
     <pb_type name="clb.fle[n1_lut6].ble6.lut6" mode_bits="00" physical_pb_type_name="clb.fle[fle_phy].frac_logic.frac_lut6">
       <!-- If not specified, we by default assume the physical mode pin share the same name -->
-      <port name="in" physical_mode_pin="in[5:0]"/>
-      <port name="out" physical_mode_pin="lut6_out"/>
+      <port name="in" physical_mode_port="in[5:0]"/>
+      <port name="out" physical_mode_port="lut6_out"/>
     </pb_type>
     <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[fle_phy].frac_logic.ff_phy" physical_pb_type_index_factor="2" physical_pb_type_index_offset="1"/>
     <pb_type name="clb.fle[shift_register].ble6_shift.ff" physical_pb_type_name="clb.fle[fle_phy].frac_logic.ff_phy"/>
diff --git a/libopenfpga/libarchopenfpga/src/pb_type_annotation.cpp b/libopenfpga/libarchopenfpga/src/pb_type_annotation.cpp
index 806a76c44..98fad3dd0 100644
--- a/libopenfpga/libarchopenfpga/src/pb_type_annotation.cpp
+++ b/libopenfpga/libarchopenfpga/src/pb_type_annotation.cpp
@@ -146,12 +146,12 @@ void PbTypeAnnotation::set_circuit_model_name(const std::string& name) {
   circuit_model_name_ = name;
 }
 
-void PbTypeAnnotation::physical_pb_type_index_factor(const int& value) {
+void PbTypeAnnotation::set_physical_pb_type_index_factor(const int& value) {
   VTR_ASSERT(true == is_operating_pb_type());
   physical_pb_type_index_factor_ = value;
 }
 
-void PbTypeAnnotation::physical_pb_type_index_offset(const int& value) {
+void PbTypeAnnotation::set_physical_pb_type_index_offset(const int& value) {
   VTR_ASSERT(true == is_operating_pb_type());
   physical_pb_type_index_offset_ = value;
 }
diff --git a/libopenfpga/libarchopenfpga/src/pb_type_annotation.h b/libopenfpga/libarchopenfpga/src/pb_type_annotation.h
index 8bf4480a8..8849ef273 100644
--- a/libopenfpga/libarchopenfpga/src/pb_type_annotation.h
+++ b/libopenfpga/libarchopenfpga/src/pb_type_annotation.h
@@ -61,8 +61,8 @@ class PbTypeAnnotation {
     void set_idle_mode_name(const std::string& name);
     void set_mode_bits(const std::string& mode_bits);
     void set_circuit_model_name(const std::string& name);
-    void physical_pb_type_index_factor(const int& value);
-    void physical_pb_type_index_offset(const int& value);
+    void set_physical_pb_type_index_factor(const int& value);
+    void set_physical_pb_type_index_offset(const int& value);
     void add_pb_type_port_pair(const std::string& operating_pb_port_name,
                                const BasicPort& physical_pb_port);
     void set_physical_pin_rotate_offset(const std::string& operating_pb_port_name,
diff --git a/libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.cpp b/libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.cpp
index 7ac685436..160c3183a 100644
--- a/libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.cpp
+++ b/libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.cpp
@@ -12,12 +12,56 @@
 /* Headers from vtr util library */
 #include "vtr_assert.h"
 
+/* Headers from openfpga util library */
+#include "openfpga_port_parser.h"
+
 /* Headers from libarchfpga */
 #include "arch_error.h"
 #include "read_xml_util.h"
 
 #include "read_xml_pb_type_annotation.h"
 
+/********************************************************************
+ * Parse XML description for an interconnection annotation 
+ * under a <pb_type> XML node
+ *******************************************************************/
+static 
+void read_xml_interc_annotation(pugi::xml_node& xml_interc,
+                                 const pugiutil::loc_data& loc_data,
+                                 openfpga::PbTypeAnnotation& pb_type_annotation) {
+  /* We have two mandatory XML attribute
+   * 1. name of the interconnect
+   * 2. circuit model name of the interconnect 
+   */
+  const std::string& name_attr = get_attribute(xml_interc, "name", loc_data).as_string();
+  const std::string& circuit_model_name_attr = get_attribute(xml_interc, "circuit_model_name", loc_data).as_string();
+
+  pb_type_annotation.add_interconnect_circuit_model_pair(name_attr, circuit_model_name_attr);
+}
+
+/********************************************************************
+ * Parse XML description for a pb_type port annotation 
+ * under a <pb_type> XML node
+ *******************************************************************/
+static 
+void read_xml_pb_port_annotation(pugi::xml_node& xml_port,
+                                 const pugiutil::loc_data& loc_data,
+                                 openfpga::PbTypeAnnotation& pb_type_annotation) {
+  /* We have two mandatory XML attribute
+   * 1. name of the port
+   * 2. name of the port to be binded in physical mode
+   */
+  const std::string& name_attr = get_attribute(xml_port, "name", loc_data).as_string();
+  const std::string& physical_mode_port_attr = get_attribute(xml_port, "physical_mode_port", loc_data).as_string();
+
+  /* Parse the mode port using openfpga port parser */
+  openfpga::PortParser port_parser(physical_mode_port_attr); 
+  pb_type_annotation.add_pb_type_port_pair(name_attr, port_parser.port());
+
+  /* We have an optional attribute: physical_mode_pin_rotate_offset */
+  pb_type_annotation.set_physical_pin_rotate_offset(name_attr, get_attribute(xml_port, "physical_mode_pin_rotate_offset", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(0));
+}
+
 /********************************************************************
  * Parse XML description for a pb_type annotation under a <pb_type> XML node
  *******************************************************************/
@@ -60,6 +104,39 @@ void read_xml_pb_type_annotation(pugi::xml_node& xml_pb_type,
     pb_type_annotation.set_circuit_model_name(get_attribute(xml_pb_type, "circuit_model_name", loc_data).as_string());
   }
 
+  /* If this is an operating pb_type, index factor and offset may be optional needed */
+  if (true == pb_type_annotation.is_operating_pb_type()) {
+    pb_type_annotation.set_physical_pb_type_index_factor(get_attribute(xml_pb_type, "physical_pb_type_index_factor", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(1));
+    pb_type_annotation.set_physical_pb_type_index_offset(get_attribute(xml_pb_type, "physical_pb_type_index_offset", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(0));
+  }
+
+  /* Parse all the interconnect-to-circuit binding under this node
+   * All the bindings are defined in child node <interconnect>
+   */
+  size_t num_intercs = count_children(xml_pb_type, "interconnect", loc_data, pugiutil::ReqOpt::OPTIONAL);
+  if (0 < num_intercs) {
+    pugi::xml_node xml_interc = get_first_child(xml_pb_type, "interconnect", loc_data);
+    while (xml_interc) {
+      read_xml_interc_annotation(xml_interc, loc_data, pb_type_annotation);
+      xml_interc = xml_interc.next_sibling(xml_interc.name());
+    } 
+  }
+
+  /* Parse all the port-to-port binding from operating pb_type to physical pb_type under this node
+   * All the bindings are defined in child node <port>
+   * This is only applicable to operating pb_type
+   */
+  if (true == pb_type_annotation.is_operating_pb_type()) {
+    size_t num_ports = count_children(xml_pb_type, "port", loc_data, pugiutil::ReqOpt::OPTIONAL);
+    if (0 < num_ports) {
+      pugi::xml_node xml_port = get_first_child(xml_pb_type, "port", loc_data);
+      while (xml_port) {
+        read_xml_pb_port_annotation(xml_port, loc_data, pb_type_annotation);
+        xml_port = xml_port.next_sibling(xml_port.name());
+      } 
+    }
+  }
+
   /* Finish parsing and add it to the vector */ 
   pb_type_annotations.push_back(pb_type_annotation);
 }

From 1cba141dd0f8b1c32340998fb471486427ebc4a3 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 26 Jan 2020 11:52:58 -0700
Subject: [PATCH 020/645] add pb parser and support XML parsing for pb type
 name in full hiearchy

---
 .../src/read_xml_pb_type_annotation.cpp       |  29 ++++-
 .../src/openfpga_pb_parser.cpp                | 117 ++++++++++++++++++
 .../libopenfpgautil/src/openfpga_pb_parser.h  |  56 +++++++++
 3 files changed, 199 insertions(+), 3 deletions(-)
 create mode 100644 libopenfpga/libopenfpgautil/src/openfpga_pb_parser.cpp
 create mode 100644 libopenfpga/libopenfpgautil/src/openfpga_pb_parser.h

diff --git a/libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.cpp b/libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.cpp
index 160c3183a..25e1e12f8 100644
--- a/libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.cpp
+++ b/libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.cpp
@@ -14,6 +14,7 @@
 
 /* Headers from openfpga util library */
 #include "openfpga_port_parser.h"
+#include "openfpga_pb_parser.h"
 
 /* Headers from libarchfpga */
 #include "arch_error.h"
@@ -80,14 +81,36 @@ void read_xml_pb_type_annotation(pugi::xml_node& xml_pb_type,
   if ( (false == name_attr.empty()) 
     && (false == physical_name_attr.empty()) ) {
     /* Parse the attributes for operating pb_type */
-    pb_type_annotation.set_operating_pb_type_name(name_attr);
-    pb_type_annotation.set_physical_pb_type_name(physical_name_attr);
+    openfpga::PbParser operating_pb_parser(name_attr);
+    pb_type_annotation.set_operating_pb_type_name(operating_pb_parser.leaf());
+    if (0 < operating_pb_parser.parents().size()) {
+      pb_type_annotation.set_operating_parent_pb_type_names(operating_pb_parser.parents());
+    }
+    if (0 < operating_pb_parser.modes().size()) {
+      pb_type_annotation.set_operating_parent_mode_names(operating_pb_parser.modes());
+    }
+
+    openfpga::PbParser physical_pb_parser(physical_name_attr);
+    pb_type_annotation.set_physical_pb_type_name(physical_pb_parser.leaf());
+    if (0 < physical_pb_parser.parents().size()) {
+      pb_type_annotation.set_physical_parent_pb_type_names(physical_pb_parser.parents());
+    }
+    if (0 < physical_pb_parser.modes().size()) {
+      pb_type_annotation.set_physical_parent_mode_names(physical_pb_parser.modes());
+    }
   } 
 
   /* If there is only a name, this is a physical pb_type */
   if ( (false == name_attr.empty()) 
     && (true == physical_name_attr.empty()) ) {
-    pb_type_annotation.set_physical_pb_type_name(name_attr);
+    openfpga::PbParser physical_pb_parser(name_attr);
+    pb_type_annotation.set_physical_pb_type_name(physical_pb_parser.leaf());
+    if (0 < physical_pb_parser.parents().size()) {
+      pb_type_annotation.set_physical_parent_pb_type_names(physical_pb_parser.parents());
+    }
+    if (0 < physical_pb_parser.modes().size()) {
+      pb_type_annotation.set_physical_parent_mode_names(physical_pb_parser.modes());
+    }
   }
 
   /* Parse physical mode name which are applied to both pb_types */
diff --git a/libopenfpga/libopenfpgautil/src/openfpga_pb_parser.cpp b/libopenfpga/libopenfpgautil/src/openfpga_pb_parser.cpp
new file mode 100644
index 000000000..ee674b928
--- /dev/null
+++ b/libopenfpga/libopenfpgautil/src/openfpga_pb_parser.cpp
@@ -0,0 +1,117 @@
+/************************************************************************
+ * Member functions for Pb parsers
+ ***********************************************************************/
+#include <cstring>
+
+#include "vtr_assert.h"
+
+#include "openfpga_tokenizer.h"
+
+#include "openfpga_pb_parser.h"
+
+/* namespace openfpga begins */
+namespace openfpga {
+
+/************************************************************************
+ * Member functions for PbParser class 
+ ***********************************************************************/
+
+/************************************************************************
+ * Constructors
+ ***********************************************************************/
+PbParser::PbParser (const std::string& data) {
+  set_default_bracket();
+  set_default_delim();
+  set_data(data);
+}
+
+/************************************************************************
+ * Public Accessors
+ ***********************************************************************/
+/* Get the data string */
+std::string PbParser::data() const {
+  return data_;
+}
+
+std::string PbParser::leaf() const {
+  return leaf_;
+}
+
+std::vector<std::string> PbParser::parents() const {
+  return parents_;
+}
+
+std::vector<std::string> PbParser::modes() const {
+  return modes_;
+}
+
+/************************************************************************
+ * Public Mutators
+ ***********************************************************************/
+void PbParser::set_data(const std::string& data) {
+  data_ = data;
+  parse();
+}
+
+/************************************************************************
+ * Internal Mutators
+ ***********************************************************************/
+/* Parse the data */
+void PbParser::parse() {
+  /* Create a tokenizer */
+  StringToken tokenizer(data_);
+
+  /* Split the data into <pb_type>[<mode>] */
+  std::vector<std::string> pb_tokens = tokenizer.split(delim_);
+
+  /* The last pb is the leaf node.
+   * It should NOT be empty and should NOT contain any brackets!  
+   */
+  VTR_ASSERT(false == pb_tokens.back().empty());
+  VTR_ASSERT(pb_tokens.back().find(bracket_.x()) == std::string::npos);
+  VTR_ASSERT(pb_tokens.back().find(bracket_.y()) == std::string::npos);
+  /* Pass the check, we assign the value */
+  leaf_ = pb_tokens.back();
+
+  /* Split the rest of pb_tokens, split the pb_type and mode_name */
+  for (size_t itok = 0; itok < pb_tokens.size() - 1; ++itok) {
+    /* Create a tokenizer */
+    StringToken pb_tokenizer(pb_tokens[itok]);
+    std::vector<std::string> tokens = pb_tokenizer.split(bracket_.x());
+    /* Make sure we have a port name! */
+    VTR_ASSERT_SAFE ((1 == tokens.size()) || (2 == tokens.size()));
+    /* Store the pb_type name */
+    parents_.push_back(tokens[0]);
+
+    /* If we only have one token, the mode name is the default mode
+     * Here we use the default keyword 'default'
+     * from VPR function ProcessMode() in libarchfpga
+     */
+    if (1 == tokens.size()) {
+      modes_.push_back(std::string("default"));
+      continue; /* We can finish here */
+    }
+   
+    /* If there is a mode name, extract it */
+    VTR_ASSERT_SAFE (2 == tokens.size());
+
+    /* Chomp the ']' */
+    pb_tokenizer.set_data(tokens[1]);
+    std::vector<std::string> mode_tokens = pb_tokenizer.split(bracket_.y());
+
+    /* Make sure we have only one mode name inside */
+    VTR_ASSERT(1 == mode_tokens.size());
+    modes_.push_back(mode_tokens[0]);
+  }
+}
+
+void PbParser::set_default_bracket() {
+  bracket_.set_x('[');
+  bracket_.set_y(']');
+}
+
+void PbParser::set_default_delim() {
+  delim_ = '.';
+}
+
+} /* namespace openfpga ends */
diff --git a/libopenfpga/libopenfpgautil/src/openfpga_pb_parser.h b/libopenfpga/libopenfpgautil/src/openfpga_pb_parser.h
new file mode 100644
index 000000000..d59286136
--- /dev/null
+++ b/libopenfpga/libopenfpgautil/src/openfpga_pb_parser.h
@@ -0,0 +1,56 @@
+#ifndef OPENFPGA_PB_PARSER_H
+#define OPENFPGA_PB_PARSER_H
+
+/********************************************************************
+ * Include header files that are required by data structure declaration
+ *******************************************************************/
+#include <string>
+#include <vector>
+
+#include "vtr_geometry.h"
+
+#include "openfpga_tokenizer.h"
+
+/************************************************************************
+ * This file includes parsers for pb_type definition in the architecture XML
+ * language.
+ ***********************************************************************/
+
+/* namespace openfpga begins */
+namespace openfpga {
+
+/************************************************************************
+ * Class PbParser: pb_type name with full hierarchy parser
+ * Supported pb_type definition:
+ *   1. <pb_type>[<mode>].<sub_pb_type>[<mode>] ... .<leaf_pb_type>
+ *   2. <pb_type>.<sub_pb_type> ... .<leaf_pb_type>
+ * where each pb_type may be specified by a mode or use the default mode
+ * (mode name not given) 
+ ***********************************************************************/
+class PbParser{
+  public : /* Constructors*/
+    PbParser (const std::string& data);
+  public : /* Public Accessors */ 
+    std::string data() const;
+    std::string leaf() const;
+    std::vector<std::string> parents() const;
+    std::vector<std::string> modes() const;
+  public : /* Public Mutators */ 
+    void set_data(const std::string& data);
+  private : /* Private Mutators */ 
+    void parse();
+    void set_default_bracket();
+    void set_default_delim();
+  private: /* Internal data */
+    std::string data_; /* Lines to be splited */
+    vtr::Point<char> bracket_;
+    char delim_;
+    std::vector<std::string> parents_;
+    std::vector<std::string> modes_;
+    std::string leaf_;
+};
+
+} /* namespace openfpga ends */
+
+#endif
+

From 7d4b07421d949c945e4dc2b1118a55d31a636984 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 26 Jan 2020 15:54:49 -0700
Subject: [PATCH 021/645] finish XML parser and writer for pb_type annotation

---
 .../src/pb_type_annotation.cpp                |  26 +-
 .../libarchopenfpga/src/pb_type_annotation.h  |   6 +-
 .../src/read_xml_pb_type_annotation.cpp       |   7 +-
 .../src/write_xml_openfpga_arch.cpp           |   5 +
 .../src/write_xml_pb_type_annotation.cpp      | 224 ++++++++++++++++++
 .../src/write_xml_pb_type_annotation.h        |  22 ++
 .../libarchopenfpga/src/write_xml_utils.cpp   |  15 ++
 .../libarchopenfpga/src/write_xml_utils.h     |   4 +
 .../src/openfpga_pb_parser.cpp                |   1 +
 .../src/openfpga_port_parser.cpp              |  21 +-
 10 files changed, 312 insertions(+), 19 deletions(-)
 create mode 100644 libopenfpga/libarchopenfpga/src/write_xml_pb_type_annotation.cpp
 create mode 100644 libopenfpga/libarchopenfpga/src/write_xml_pb_type_annotation.h

diff --git a/libopenfpga/libarchopenfpga/src/pb_type_annotation.cpp b/libopenfpga/libarchopenfpga/src/pb_type_annotation.cpp
index 98fad3dd0..da494f77f 100644
--- a/libopenfpga/libarchopenfpga/src/pb_type_annotation.cpp
+++ b/libopenfpga/libarchopenfpga/src/pb_type_annotation.cpp
@@ -31,7 +31,8 @@ std::vector<std::string> PbTypeAnnotation::operating_parent_mode_names() const {
 }
 
 bool PbTypeAnnotation::is_operating_pb_type() const {
-  return true == operating_pb_type_name_.empty();
+  return (false == operating_pb_type_name_.empty())
+      && (false == physical_pb_type_name_.empty());
 }
 
 
@@ -48,7 +49,8 @@ std::vector<std::string> PbTypeAnnotation::physical_parent_mode_names() const {
 }
 
 bool PbTypeAnnotation::is_physical_pb_type() const {
-  return true == physical_pb_type_name_.empty();
+  return (true == operating_pb_type_name_.empty())
+      && (false == physical_pb_type_name_.empty());
 }
 
 std::string PbTypeAnnotation::physical_mode_name() const {
@@ -75,7 +77,15 @@ int PbTypeAnnotation::physical_pb_type_index_offset() const {
   return physical_pb_type_index_offset_;
 }
 
-BasicPort PbTypeAnnotation::physical_pb_type_ports(const std::string& port_name) const {
+std::vector<std::string> PbTypeAnnotation::port_names() const {
+  std::vector<std::string> keys;
+  for (auto const& element : operating_pb_type_ports_) {
+    keys.push_back(element.first);
+  }
+  return keys;
+}
+
+BasicPort PbTypeAnnotation::physical_pb_type_port(const std::string& port_name) const {
   std::map<std::string, BasicPort>::const_iterator it = operating_pb_type_ports_.find(port_name);
   if (it == operating_pb_type_ports_.end()) {
     /* Return an empty port */
@@ -84,7 +94,7 @@ BasicPort PbTypeAnnotation::physical_pb_type_ports(const std::string& port_name)
   return operating_pb_type_ports_.at(port_name);
 }
 
-int PbTypeAnnotation::physical_pin_rotate_offsets(const std::string& port_name) const {
+int PbTypeAnnotation::physical_pin_rotate_offset(const std::string& port_name) const {
   std::map<std::string, int>::const_iterator it = physical_pin_rotate_offsets_.find(port_name);
   if (it == physical_pin_rotate_offsets_.end()) {
     /* Return a zero offset which is default */
@@ -93,6 +103,14 @@ int PbTypeAnnotation::physical_pin_rotate_offsets(const std::string& port_name)
   return physical_pin_rotate_offsets_.at(port_name);
 }
 
+std::vector<std::string> PbTypeAnnotation::interconnect_names() const {
+  std::vector<std::string> keys;
+  for (auto const& element : interconnect_circuit_model_names_) {
+    keys.push_back(element.first);
+  }
+  return keys;
+}
+
 std::string PbTypeAnnotation::interconnect_circuit_model_name(const std::string& interc_name) const {
   std::map<std::string, std::string>::const_iterator it = interconnect_circuit_model_names_.find(interc_name);
   if (it == interconnect_circuit_model_names_.end()) {
diff --git a/libopenfpga/libarchopenfpga/src/pb_type_annotation.h b/libopenfpga/libarchopenfpga/src/pb_type_annotation.h
index 8849ef273..e03201cde 100644
--- a/libopenfpga/libarchopenfpga/src/pb_type_annotation.h
+++ b/libopenfpga/libarchopenfpga/src/pb_type_annotation.h
@@ -47,8 +47,10 @@ class PbTypeAnnotation {
     std::string circuit_model_name() const;
     int physical_pb_type_index_factor() const;
     int physical_pb_type_index_offset() const;
-    BasicPort physical_pb_type_ports(const std::string& port_name) const;
-    int physical_pin_rotate_offsets(const std::string& port_name) const;
+    std::vector<std::string> port_names() const;
+    BasicPort physical_pb_type_port(const std::string& port_name) const;
+    int physical_pin_rotate_offset(const std::string& port_name) const;
+    std::vector<std::string> interconnect_names() const;
     std::string interconnect_circuit_model_name(const std::string& interc_name) const;
   public: /* Public mutators */
     void set_operating_pb_type_name(const std::string& name);
diff --git a/libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.cpp b/libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.cpp
index 25e1e12f8..253053bf5 100644
--- a/libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.cpp
+++ b/libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.cpp
@@ -75,7 +75,6 @@ void read_xml_pb_type_annotation(pugi::xml_node& xml_pb_type,
   /* Find the name of pb_type */
   const std::string& name_attr = get_attribute(xml_pb_type, "name", loc_data).as_string();
   const std::string& physical_name_attr = get_attribute(xml_pb_type, "physical_pb_type_name", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string();
-  const std::string& physical_mode_name_attr = get_attribute(xml_pb_type, "physical_mode_name", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string();
 
   /* If both names are not empty, this is a operating pb_type */
   if ( (false == name_attr.empty()) 
@@ -122,9 +121,11 @@ void read_xml_pb_type_annotation(pugi::xml_node& xml_pb_type,
   /* Parse mode bits which are applied to both pb_types */
   pb_type_annotation.set_mode_bits(get_attribute(xml_pb_type, "mode_bits", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string());
 
-  /* If this is a physical pb_type, circuit model name is a mandatory attribute */
+  /* If this is a physical pb_type, circuit model name is an optional attribute, 
+   * which is applicable to leaf pb_type in the hierarchy 
+   */
   if (true == pb_type_annotation.is_physical_pb_type()) {
-    pb_type_annotation.set_circuit_model_name(get_attribute(xml_pb_type, "circuit_model_name", loc_data).as_string());
+    pb_type_annotation.set_circuit_model_name(get_attribute(xml_pb_type, "circuit_model_name", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string());
   }
 
   /* If this is an operating pb_type, index factor and offset may be optional needed */
diff --git a/libopenfpga/libarchopenfpga/src/write_xml_openfpga_arch.cpp b/libopenfpga/libarchopenfpga/src/write_xml_openfpga_arch.cpp
index e262735e4..b71853156 100644
--- a/libopenfpga/libarchopenfpga/src/write_xml_openfpga_arch.cpp
+++ b/libopenfpga/libarchopenfpga/src/write_xml_openfpga_arch.cpp
@@ -16,6 +16,7 @@
 #include "write_xml_simulation_setting.h"
 #include "write_xml_config_protocol.h"
 #include "write_xml_routing_circuit.h"
+#include "write_xml_pb_type_annotation.h"
 #include "write_xml_openfpga_arch.h"
 
 /********************************************************************
@@ -57,6 +58,10 @@ void write_xml_openfpga_arch(const char* fname,
   /* Write the direct connection circuit definition */
   write_xml_direct_circuit(fp, fname, openfpga_arch.circuit_lib, openfpga_arch.direct2circuit);
 
+
+  /* Write the pb_type annotations */
+  openfpga::write_xml_pb_type_annotations(fp, fname, openfpga_arch. pb_type_annotations);
+
   fp << "</openfpga_architecture>" << "\n";
 
   /* Write the simulation */
diff --git a/libopenfpga/libarchopenfpga/src/write_xml_pb_type_annotation.cpp b/libopenfpga/libarchopenfpga/src/write_xml_pb_type_annotation.cpp
new file mode 100644
index 000000000..a771c782d
--- /dev/null
+++ b/libopenfpga/libarchopenfpga/src/write_xml_pb_type_annotation.cpp
@@ -0,0 +1,224 @@
+/********************************************************************
+ * This file includes functions that outputs pb_type annotations to XML format
+ *******************************************************************/
+/* Headers from system goes first */
+#include <string>
+#include <algorithm>
+
+/* Headers from vtr util library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+#include "openfpga_digest.h"
+
+/* Headers from readarchopenfpga library */
+#include "write_xml_utils.h" 
+#include "write_xml_pb_type_annotation.h"
+
+/* namespace openfpga begins */
+namespace openfpga {
+
+/********************************************************************
+ * Generate the full hierarchy name for a operating pb_type
+ *******************************************************************/
+static 
+std::string generate_operating_pb_type_hierarchy_name(const PbTypeAnnotation& pb_type_annotation) {
+  /* Iterate over the parent_pb_type and modes names, they should well match */
+  VTR_ASSERT_SAFE(pb_type_annotation.operating_parent_pb_type_names().size() == pb_type_annotation.operating_parent_mode_names().size());
+
+  std::string hie_name;
+
+  for (size_t i = 0 ; i < pb_type_annotation.operating_parent_pb_type_names().size(); ++i) {
+    hie_name += pb_type_annotation.operating_parent_pb_type_names()[i];
+    hie_name += std::string("[");
+    hie_name += pb_type_annotation.operating_parent_mode_names()[i];
+    hie_name += std::string("]");
+    hie_name += std::string(".");
+  }
+
+  /* Add the leaf pb_type */
+  hie_name += pb_type_annotation.operating_pb_type_name();
+
+  return hie_name;
+}
+
+/********************************************************************
+ * Generate the full hierarchy name for a operating pb_type
+ *******************************************************************/
+static 
+std::string generate_physical_pb_type_hierarchy_name(const PbTypeAnnotation& pb_type_annotation) {
+  /* Iterate over the parent_pb_type and modes names, they should well match */
+  VTR_ASSERT_SAFE(pb_type_annotation.physical_parent_pb_type_names().size() == pb_type_annotation.physical_parent_mode_names().size());
+
+  std::string hie_name;
+
+  for (size_t i = 0 ; i < pb_type_annotation.physical_parent_pb_type_names().size(); ++i) {
+    hie_name += pb_type_annotation.physical_parent_pb_type_names()[i];
+    hie_name += std::string("[");
+    hie_name += pb_type_annotation.physical_parent_mode_names()[i];
+    hie_name += std::string("]");
+    hie_name += std::string(".");
+  }
+
+  /* Add the leaf pb_type */
+  hie_name += pb_type_annotation.physical_pb_type_name();
+
+  return hie_name;
+}
+
+/********************************************************************
+ * Generate the full hierarchy name for a operating pb_type
+ *******************************************************************/
+static 
+std::string generate_physical_pb_port_name(const BasicPort& pb_port) {
+  std::string port_name;
+
+  /* Output format: <port_name>[<LSB>:<MSB>] */
+  port_name += pb_port.get_name();
+  port_name += std::string("[");
+  port_name += std::to_string(pb_port.get_lsb());
+  port_name += std::string(":");
+  port_name += std::to_string(pb_port.get_msb());
+  port_name += std::string("]");
+
+  return port_name;
+}
+
+/********************************************************************
+ * A writer to output an pb_type interconnection annotation to XML format
+ *******************************************************************/
+static 
+void write_xml_interconnect_annotation(std::fstream& fp,
+                                       const char* fname,
+                                       const openfpga::PbTypeAnnotation& pb_type_annotation,
+                                       const std::string& interc_name) {
+  /* Validate the file stream */
+  openfpga::check_file_stream(fname, fp);
+
+  fp << "\t\t\t" << "<interconnect";
+ 
+  write_xml_attribute(fp, "name", interc_name.c_str());
+  write_xml_attribute(fp, "circuit_model_name", pb_type_annotation.interconnect_circuit_model_name(interc_name).c_str());
+
+  fp << "/>" << "\n";
+}
+
+/********************************************************************
+ * A writer to output an pb_type port annotation to XML format
+ *******************************************************************/
+static 
+void write_xml_pb_port_annotation(std::fstream& fp,
+                                  const char* fname,
+                                  const openfpga::PbTypeAnnotation& pb_type_annotation,
+                                  const std::string& port_name) {
+  /* Validate the file stream */
+  openfpga::check_file_stream(fname, fp);
+
+  fp << "\t\t\t" << "<port";
+ 
+  write_xml_attribute(fp, "name", port_name.c_str());
+  write_xml_attribute(fp, "physical_mode_port", generate_physical_pb_port_name(pb_type_annotation.physical_pb_type_port(port_name)).c_str());
+  write_xml_attribute(fp, "physical_mode_pin_rotate_offset", pb_type_annotation.physical_pin_rotate_offset(port_name));
+
+  fp << "/>" << "\n";
+}
+
+/********************************************************************
+ * A writer to output a device variation in a technology library to XML format
+ *******************************************************************/
+static 
+void write_xml_pb_type_annotation(std::fstream& fp,
+                                  const char* fname,
+                                  const openfpga::PbTypeAnnotation& pb_type_annotation) {
+  /* Validate the file stream */
+  openfpga::check_file_stream(fname, fp);
+
+  fp << "\t\t" << "<pb_type";
+
+  /* Write up name of the pb_type, which is different by the type of pb_type
+   * 1. operating pb_type, we output name, physical_pb_type_name
+   * 1. physical pb_type, we output name
+   */
+  if (true == pb_type_annotation.is_operating_pb_type()) { 
+    write_xml_attribute(fp, "name", generate_operating_pb_type_hierarchy_name(pb_type_annotation).c_str());
+    write_xml_attribute(fp, "physical_pb_type_name", generate_physical_pb_type_hierarchy_name(pb_type_annotation).c_str());
+  }
+  
+  if (true == pb_type_annotation.is_physical_pb_type()) { 
+    write_xml_attribute(fp, "name", generate_physical_pb_type_hierarchy_name(pb_type_annotation).c_str());
+  }
+
+  /* Output physical mode name */
+  if (!pb_type_annotation.physical_mode_name().empty()) { 
+    write_xml_attribute(fp, "physical_mode_name", pb_type_annotation.physical_mode_name().c_str());
+  }
+
+  /* Output idle mode name */
+  if (!pb_type_annotation.idle_mode_name().empty()) { 
+    write_xml_attribute(fp, "idle_mode_name", pb_type_annotation.idle_mode_name().c_str());
+  }
+
+  /* Output mode_bits */
+  if (!pb_type_annotation.mode_bits().empty()) { 
+    write_xml_attribute(fp, "mode_bits", pb_type_annotation.mode_bits().c_str());
+  }
+
+  /* Output circuit model name */
+  if (!pb_type_annotation.circuit_model_name().empty()) { 
+    write_xml_attribute(fp, "circuit_model_name", pb_type_annotation.circuit_model_name().c_str());
+  }
+
+  /* Output physical mode index factor and offset, only applicable to operating mode */
+  if (true == pb_type_annotation.is_operating_pb_type()) { 
+    write_xml_attribute(fp, "physical_pb_type_index_factor", pb_type_annotation.physical_pb_type_index_factor());
+    write_xml_attribute(fp, "physical_pb_type_index_offset", pb_type_annotation.physical_pb_type_index_offset());
+  }
+
+  /* If there are interconnect definition or port definition, output them
+   * Otherwise we can finish here 
+   */
+  if ( (0 == pb_type_annotation.interconnect_names().size())
+    && (0 == pb_type_annotation.port_names().size()) ) {
+    fp << "/>" << "\n";
+    return;
+  }
+
+  fp << ">" << "\n";
+
+  /* Output interconnects if there are any */
+  for (const std::string& interc_name : pb_type_annotation.interconnect_names()) {
+    write_xml_interconnect_annotation(fp, fname, pb_type_annotation, interc_name);
+  }
+
+  /* Output pb_type ports if there are any */
+  for (const std::string& port_name : pb_type_annotation.port_names()) {
+    write_xml_pb_port_annotation(fp, fname, pb_type_annotation, port_name);
+  }
+ 
+  fp << "\t\t</pb_type>" << "\n";
+}
+
+/********************************************************************
+ * A writer to output a number of pb_type annotations to XML format
+ *******************************************************************/
+void write_xml_pb_type_annotations(std::fstream& fp,
+                                   const char* fname,
+                                   const std::vector<PbTypeAnnotation>& pb_type_annotations) {
+  /* Validate the file stream */
+  openfpga::check_file_stream(fname, fp);
+  
+  /* Write the root node for pb_type annotations, 
+   * we apply a tab becuase pb_type annotations is just a subnode 
+   * under the root node <openfpga_arch>
+   */
+  fp << "\t" << "<pb_type_annotations>" << "\n";
+
+  /* Write device model one by one */ 
+  for (const PbTypeAnnotation& pb_type_annotation : pb_type_annotations) {
+    write_xml_pb_type_annotation(fp, fname, pb_type_annotation);
+  }
+
+  /* Write the root node for pb_type annotations */
+  fp << "\t" << "</pb_type_annotations>" << "\n";
+}
+
+} /* namespace openfpga ends */
diff --git a/libopenfpga/libarchopenfpga/src/write_xml_pb_type_annotation.h b/libopenfpga/libarchopenfpga/src/write_xml_pb_type_annotation.h
new file mode 100644
index 000000000..e40b5ad4e
--- /dev/null
+++ b/libopenfpga/libarchopenfpga/src/write_xml_pb_type_annotation.h
@@ -0,0 +1,22 @@
+#ifndef WRITE_XML_PB_TYPE_ANNOTATION_H
+#define WRITE_XML_PB_TYPE_ANNOTATION_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <fstream>
+#include "pb_type_annotation.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+/* namespace openfpga begins */
+namespace openfpga {
+
+void write_xml_pb_type_annotations(std::fstream& fp,
+                                   const char* fname,
+                                   const std::vector<PbTypeAnnotation>& pb_type_annotations);
+
+} /* namespace openfpga ends */
+
+#endif
diff --git a/libopenfpga/libarchopenfpga/src/write_xml_utils.cpp b/libopenfpga/libarchopenfpga/src/write_xml_utils.cpp
index ad887e10c..e4d32e720 100644
--- a/libopenfpga/libarchopenfpga/src/write_xml_utils.cpp
+++ b/libopenfpga/libarchopenfpga/src/write_xml_utils.cpp
@@ -46,6 +46,21 @@ void write_xml_attribute(std::fstream& fp,
   fp << "\""; 
 }
 
+/********************************************************************
+ * A most utilized function to write an XML attribute to file
+ * This accepts the value as a float
+ *******************************************************************/
+void write_xml_attribute(std::fstream& fp, 
+                         const char* attr,
+                         const int& value) {
+  /* Validate the file stream */
+  openfpga::valid_file_stream(fp);
+
+  fp << " " << attr << "=\"";
+  fp << value;
+  fp << "\""; 
+}
+
 /********************************************************************
  * A most utilized function to write an XML attribute to file
  * This accepts the value as a float
diff --git a/libopenfpga/libarchopenfpga/src/write_xml_utils.h b/libopenfpga/libarchopenfpga/src/write_xml_utils.h
index a827727e4..3976d78b9 100644
--- a/libopenfpga/libarchopenfpga/src/write_xml_utils.h
+++ b/libopenfpga/libarchopenfpga/src/write_xml_utils.h
@@ -18,6 +18,10 @@ void write_xml_attribute(std::fstream& fp,
                          const char* attr,
                          const bool& value);
 
+void write_xml_attribute(std::fstream& fp, 
+                         const char* attr,
+                         const int& value);
+
 void write_xml_attribute(std::fstream& fp, 
                          const char* attr,
                          const float& value);
diff --git a/libopenfpga/libopenfpgautil/src/openfpga_pb_parser.cpp b/libopenfpga/libopenfpgautil/src/openfpga_pb_parser.cpp
index ee674b928..3c174f589 100644
--- a/libopenfpga/libopenfpgautil/src/openfpga_pb_parser.cpp
+++ b/libopenfpga/libopenfpgautil/src/openfpga_pb_parser.cpp
@@ -67,6 +67,7 @@ void PbParser::parse() {
   /* The last pb is the leaf node.
    * It should NOT be empty and should NOT contain any brackets!  
    */
+  VTR_ASSERT(0 < pb_tokens.size());
   VTR_ASSERT(false == pb_tokens.back().empty());
   VTR_ASSERT(pb_tokens.back().find(bracket_.x()) == std::string::npos);
   VTR_ASSERT(pb_tokens.back().find(bracket_.y()) == std::string::npos);
diff --git a/libopenfpga/libopenfpgautil/src/openfpga_port_parser.cpp b/libopenfpga/libopenfpgautil/src/openfpga_port_parser.cpp
index 78f357b82..2006275dc 100644
--- a/libopenfpga/libopenfpgautil/src/openfpga_port_parser.cpp
+++ b/libopenfpga/libopenfpgautil/src/openfpga_port_parser.cpp
@@ -64,7 +64,7 @@ void PortParser::parse() {
 
   /* If we only have one token */
   if (1 == port_tokens.size()) {
-    port_.set_width(0); 
+    port_.set_width(1); 
     return; /* We can finish here */
   }
 
@@ -75,21 +75,22 @@ void PortParser::parse() {
   VTR_ASSERT_SAFE (1 == port_tokens.size());
 
   /* Split the pin string now */
-  tokenizer.set_data(port_tokens[0]);
+  tokenizer.set_data(pin_tokens[0]);
   pin_tokens = tokenizer.split(delim_);
 
   /* Check if we have LSB and MSB or just one */
   if ( 1 == pin_tokens.size() ) {
     /* Single pin */
-    port_.set_width(stoi(pin_tokens[0]), stoi(pin_tokens[0])); 
+    port_.set_width(std::stoi(pin_tokens[0]), std::stoi(pin_tokens[0])); 
   } else if ( 2 == pin_tokens.size() ) {
-    /* A number of pin */
-    port_.set_width(stoi(pin_tokens[0]), stoi(pin_tokens[1])); 
-  }
-
-  /* Re-order to ensure LSB <= MSB */
-  if (false == port_.is_valid()) {
-    port_.revert(); 
+    /* A number of pins. 
+     * Note that we always use the LSB for token[0] and MSB for token[1] 
+     */
+    if (std::stoi(pin_tokens[1]) < std::stoi(pin_tokens[0])) {
+      port_.set_width(std::stoi(pin_tokens[1]), std::stoi(pin_tokens[0])); 
+    } else {
+      port_.set_width(std::stoi(pin_tokens[0]), std::stoi(pin_tokens[1])); 
+    }
   }
 
   return;  

From 93ab4b8dd29b50d5698300d201a98b10a1557090 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 26 Jan 2020 17:30:46 -0700
Subject: [PATCH 022/645] add test case for openfpga shell

---
 ...rac_N10_frac_chain_depop50_mem32K_40nm.xml |  1438 ++
 openfpga/test_blif/riscv_core_lut6.blif       | 19187 ++++++++++++++++
 openfpga/test_script/riscv_core.openfpga      |     2 +
 3 files changed, 20627 insertions(+)
 create mode 100644 openfpga/test_arch/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml
 create mode 100644 openfpga/test_blif/riscv_core_lut6.blif
 create mode 100644 openfpga/test_script/riscv_core.openfpga

diff --git a/openfpga/test_arch/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml b/openfpga/test_arch/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml
new file mode 100644
index 000000000..4594c6496
--- /dev/null
+++ b/openfpga/test_arch/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml
@@ -0,0 +1,1438 @@
+<!-- 
+  Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with 8 total FLE inputs (2 inputs of which are shared by the 5-LUTs) 
+    with optionally registered outputs
+    Each 5-LUT has an arithemtic mode that converts it to a single-bit adder with both inputs driven by 4-LUTs (both 4-LUTs share all 4 inputs)
+    Carry chain links to vertically adjacent logic blocks
+  - Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.  
+    Height = 6, found on every (8n+2)th column
+  - Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.  
+    Height = 4, found on every (8n+6)th column
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Details on Modelling:
+
+  The electrical design of the architecture described here is NOT from an 
+  optimized, SPICED architecture.  Instead, we attempt to create a reasonable 
+  architecture file by using an existing commercial FPGA to approximate the area, 
+  delay, and power of the underlying components. This is combined with a reasonable 40 nm 
+  model of wiring and circuit design for low-level routing components, where available.
+  The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also 
+  has wiring electrical parameters that allow the wire lengths and switch patterns to be 
+  modified and you will still get reasonable delay results for the new architecture.
+  The following describes, in detail, how we obtained the various electrical values for this 
+  architecture.
+
+  Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar 
+  architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture. 
+  (n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)      
+  This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to 
+  match the overall target (a 40 nm FPGA).
+
+  We obtain delay numbers by measuring delays of routing, soft logic blocks, 
+  memories, and multipliers from test circuits on a Stratix IV GX device 
+  (EP4SGX230DF29C2X, i.e. fastest speed grade). For routing, we took the average delay of H4 and V4 
+  wires.  Rmetal and Cmetal values for the routing wires were obtained from work done by Charles 
+  Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal stack 40 nm routing) and 
+  take the R and C data from the ITRS roadmap.  
+
+  For the general purpose logic block, we assume that the area and delays of the Stratix IV 
+  crossbar is close enough to the crossbar modelled here.  
+  Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to 
+  36:1 multiplexers.  We match these parameters in this architecture.
+
+  For LUTs, we include LUT 
+  delays measured from Stratix IV which is dependant on the input used (ie. some 
+  LUT inputs are faster than others).  The CAD tools at the time of VTR 7 does 
+  not consider differences in LUT input delays.
+
+  Adder delays obtained as approximate values from a Stratix IV EP4SE230F29C3 device.  
+  Delay obtained by compiling a 256 bit adder (registered inputs and outputs, 
+  all pins except clock virtual) then measuring the delays in chip-planner, 
+  sumout delay = 0.271ns to 0.348 ns, intra-block carry delay = 0.011 ns, 
+  inter-block carry delay = 0.327 ns.  Given this data, I will approximate 
+  sumout 0.3 ns, intra-block carry-delay = 0.01 ns, and 
+  inter-block carry-delay = 0.16 ns (since Altera inter-block carry delay has 
+  overhead that we don't have, I'll approximate the delay of a simpler chain at 
+  one half what they have.  This is very rough, anything from 0.01ns to 0.327ns 
+  can be justified).
+
+  Logic block area numbers obtained by scaling overall tile area of a 65nm 
+  Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out 
+  routing area at a channel width of 300. We use a channel width of 300 because it can route 
+  all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
+  total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
+  choosing a width that provides high routability. The architecture can be routed at different channel
+  widths, but we estimate the tile size and hence the physical length of routing wires assuming
+  a channel width of 300.
+
+  Sanity checks employed:
+    1.  We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches 
+        common electrical design.
+
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <model name="multiply">
+      <input_ports>
+        <port name="a" combinational_sink_ports="out"/>
+        <port name="b" combinational_sink_ports="out"/>
+      </input_ports>
+      <output_ports>
+        <port name="out"/>
+      </output_ports>
+    </model>
+    <model name="single_port_ram">
+      <input_ports>
+        <port name="we" clock="clk"/>
+        <!-- control -->
+        <port name="addr" clock="clk"/>
+        <!-- address lines -->
+        <port name="data" clock="clk"/>
+        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
+        <port name="clk" is_clock="1"/>
+        <!-- memories are often clocked -->
+      </input_ports>
+      <output_ports>
+        <port name="out" clock="clk"/>
+        <!-- output can be broken down into smaller bit widths minimum size 1 -->
+      </output_ports>
+    </model>
+    <model name="dual_port_ram">
+      <input_ports>
+        <port name="we1" clock="clk"/>
+        <!-- write enable -->
+        <port name="we2" clock="clk"/>
+        <!-- write enable -->
+        <port name="addr1" clock="clk"/>
+        <!-- address lines -->
+        <port name="addr2" clock="clk"/>
+        <!-- address lines -->
+        <port name="data1" clock="clk"/>
+        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
+        <port name="data2" clock="clk"/>
+        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
+        <port name="clk" is_clock="1"/>
+        <!-- memories are often clocked -->
+      </input_ports>
+      <output_ports>
+        <port name="out1" clock="clk"/>
+        <!-- output can be broken down into smaller bit widths minimum size 1 -->
+        <port name="out2" clock="clk"/>
+        <!-- output can be broken down into smaller bit widths minimum size 1 -->
+      </output_ports>
+    </model>
+    <model name="adder">
+      <input_ports>
+        <port name="a" combinational_sink_ports="sumout cout"/>
+        <port name="b" combinational_sink_ports="sumout cout"/>
+        <port name="cin" combinational_sink_ports="sumout cout"/>
+      </input_ports>
+      <output_ports>
+        <port name="cout"/>
+        <port name="sumout"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <tile name="io" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <clock name="clock" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad io.clock</loc>
+        <loc side="top">io.outpad io.inpad io.clock</loc>
+        <loc side="right">io.outpad io.inpad io.clock</loc>
+        <loc side="bottom">io.outpad io.inpad io.clock</loc>
+      </pinlocations>
+    </tile>
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I1" num_pins="13" equivalent="full"/>
+      <input name="I2" num_pins="13" equivalent="full"/>
+      <input name="I3" num_pins="13" equivalent="full"/>
+      <input name="I4" num_pins="13" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
+      </fc>
+      <pinlocations pattern="spread"/>
+    </tile>
+    <tile name="mult_36" height="4" area="396000">
+      <equivalent_sites>
+        <site pb_type="mult_36"/>
+      </equivalent_sites>
+      <input name="a" num_pins="36"/>
+      <input name="b" num_pins="36"/>
+      <output name="out" num_pins="72"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="spread"/>
+    </tile>
+    <tile name="memory" height="6" area="548000">
+      <equivalent_sites>
+        <site pb_type="memory"/>
+      </equivalent_sites>
+      <input name="addr1" num_pins="15"/>
+      <input name="addr2" num_pins="15"/>
+      <input name="data" num_pins="64"/>
+      <input name="we1" num_pins="1"/>
+      <input name="we2" num_pins="1"/>
+      <output name="out" num_pins="64"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="spread"/>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout>
+    <auto_layout aspect_ratio="1.0">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+      <!--Column of 'mult_36' with 'EMPTY' blocks wherever a 'mult_36' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="mult_36" startx="6" starty="1" repeatx="8" priority="20"/>
+      <col type="EMPTY" startx="6" repeatx="8" starty="1" priority="19"/>
+      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
+      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
+    </auto_layout>
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	    -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+           book area formula. This means the mux transistors are about 5x minimum drive strength.
+           We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+           mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+           the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+           by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+           buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+           I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+           (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+           The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+           2.5x when looking up in Jeff's tables.
+           Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+           This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+             With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+             reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <segment freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <directlist>
+    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
+  </directlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <clock name="clock" num_pins="1"/>
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I1" num_pins="13" equivalent="full"/>
+      <input name="I2" num_pins="13" equivalent="full"/>
+      <input name="I3" num_pins="13" equivalent="full"/>
+      <input name="I4" num_pins="13" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe fracturable logic element.  
+             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
+             The outputs of the fracturable logic element can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="10">
+        <input name="in" num_pins="8"/>
+        <input name="cin" num_pins="1"/>
+        <output name="out" num_pins="2"/>
+        <output name="cout" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+        <mode name="n2_lut5">
+          <pb_type name="lut5inter" num_pb="1">
+            <input name="in" num_pins="8"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="ble5" num_pb="2">
+              <input name="in" num_pins="5"/>
+              <input name="cin" num_pins="1"/>
+              <output name="out" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <clock name="clk" num_pins="1"/>
+              <mode name="blut5">
+                <pb_type name="flut5" num_pb="1">
+                  <input name="in" num_pins="5"/>
+                  <output name="out" num_pins="1"/>
+                  <clock name="clk" num_pins="1"/>
+                  <!-- Regular LUT mode -->
+                  <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
+                    <input name="in" num_pins="5" port_class="lut_in"/>
+                    <output name="out" num_pins="1" port_class="lut_out"/>
+                    <!-- LUT timing using delay matrix -->
+                    <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                           we instead take the average of these numbers to get more stable results
+                        82e-12
+                        173e-12
+                        261e-12
+                        263e-12
+                        398e-12
+                        -->
+                    <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
+                        235e-12
+                        235e-12
+                        235e-12
+                        235e-12
+                        235e-12
+                      </delay_matrix>
+                  </pb_type>
+                  <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+                    <input name="D" num_pins="1" port_class="D"/>
+                    <output name="Q" num_pins="1" port_class="Q"/>
+                    <clock name="clk" num_pins="1" port_class="clock"/>
+                    <T_setup value="66e-12" port="ff.D" clock="clk"/>
+                    <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+                  </pb_type>
+                  <interconnect>
+                    <direct name="direct1" input="flut5.in" output="lut5.in"/>
+                    <direct name="direct2" input="lut5.out" output="ff.D">
+                      <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
+                    </direct>
+                    <direct name="direct3" input="flut5.clk" output="ff.clk"/>
+                    <mux name="mux1" input="ff.Q lut5.out" output="flut5.out">
+                      <delay_constant max="25e-12" in_port="lut5.out" out_port="flut5.out"/>
+                      <delay_constant max="45e-12" in_port="ff.Q" out_port="flut5.out"/>
+                    </mux>
+                  </interconnect>
+                </pb_type>
+                <interconnect>
+                  <direct name="direct1" input="ble5.in" output="flut5.in"/>
+                  <direct name="direct2" input="ble5.clk" output="flut5.clk"/>
+                  <direct name="direct3" input="flut5.out" output="ble5.out"/>
+                </interconnect>
+              </mode>
+              <mode name="arithmetic">
+                <pb_type name="arithmetic" num_pb="1">
+                  <input name="in" num_pins="4"/>
+                  <input name="cin" num_pins="1"/>
+                  <output name="out" num_pins="1"/>
+                  <output name="cout" num_pins="1"/>
+                  <clock name="clk" num_pins="1"/>
+                  <!-- Special dual-LUT mode that drives adder only -->
+                  <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
+                    <input name="in" num_pins="4" port_class="lut_in"/>
+                    <output name="out" num_pins="1" port_class="lut_out"/>
+                    <!-- LUT timing using delay matrix -->
+                    <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                             we instead take the average of these numbers to get more stable results
+                        82e-12
+                        173e-12
+                        261e-12
+                        263e-12
+                        -->
+                    <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                        195e-12
+                        195e-12
+                        195e-12
+                        195e-12
+                      </delay_matrix>
+                  </pb_type>
+                  <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
+                    <input name="a" num_pins="1"/>
+                    <input name="b" num_pins="1"/>
+                    <input name="cin" num_pins="1"/>
+                    <output name="cout" num_pins="1"/>
+                    <output name="sumout" num_pins="1"/>
+                    <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+                    <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+                    <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+                    <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+                    <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+                    <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+                  </pb_type>
+                  <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+                    <input name="D" num_pins="1" port_class="D"/>
+                    <output name="Q" num_pins="1" port_class="Q"/>
+                    <clock name="clk" num_pins="1" port_class="clock"/>
+                    <T_setup value="66e-12" port="ff.D" clock="clk"/>
+                    <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+                  </pb_type>
+                  <interconnect>
+                    <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
+                    <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
+                    <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
+                    <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
+                      </direct>
+                    <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
+                      </direct>
+                    <direct name="add_to_ff" input="adder.sumout" output="ff.D">
+                      <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
+                    </direct>
+                    <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
+                      <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
+                    </direct>
+                    <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
+                      <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
+                    </direct>
+                    <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
+                      <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
+                      <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out"/>
+                    </mux>
+                  </interconnect>
+                </pb_type>
+                <interconnect>
+                  <direct name="direct1" input="ble5.in[3:0]" output="arithmetic.in"/>
+                  <direct name="carry_in" input="ble5.cin" output="arithmetic.cin">
+                    <pack_pattern name="chain" in_port="ble5.cin" out_port="arithmetic.cin"/>
+                  </direct>
+                  <direct name="carry_out" input="arithmetic.cout" output="ble5.cout">
+                    <pack_pattern name="chain" in_port="arithmetic.cout" out_port="ble5.cout"/>
+                  </direct>
+                  <direct name="direct2" input="ble5.clk" output="arithmetic.clk"/>
+                  <direct name="direct3" input="arithmetic.out" output="ble5.out"/>
+                </interconnect>
+              </mode>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="lut5inter.in[4:0]" output="ble5[0:0].in"/>
+              <direct name="direct2" input="lut5inter.in[7:3]" output="ble5[1:1].in"/>
+              <direct name="direct3" input="ble5[1:0].out" output="lut5inter.out"/>
+              <direct name="carry_in" input="lut5inter.cin" output="ble5[0:0].cin">
+                <pack_pattern name="chain" in_port="lut5inter.cin" out_port="ble5[0:0].cin"/>
+              </direct>
+              <direct name="carry_out" input="ble5[1:1].cout" output="lut5inter.cout">
+                <pack_pattern name="chain" in_port="ble5[1:1].cout" out_port="lut5inter.cout"/>
+              </direct>
+              <direct name="carry_link" input="ble5[0:0].cout" output="ble5[1:1].cin">
+                <pack_pattern name="chain" in_port="ble5[0:0].cout" out_port="ble5[1:1].cout"/>
+              </direct>
+              <complete name="complete1" input="lut5inter.clk" output="ble5[1:0].clk"/>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="lut5inter.in"/>
+            <direct name="direct2" input="lut5inter.out" output="fle.out"/>
+            <direct name="direct3" input="fle.clk" output="lut5inter.clk"/>
+            <direct name="carry_in" input="fle.cin" output="lut5inter.cin">
+              <pack_pattern name="chain" in_port="fle.cin" out_port="lut5inter.cin"/>
+            </direct>
+            <direct name="carry_out" input="lut5inter.cout" output="fle.cout">
+              <pack_pattern name="chain" in_port="lut5inter.cout" out_port="fle.cout"/>
+            </direct>
+          </interconnect>
+        </mode>
+        <!-- n2_lut5 -->
+        <mode name="n1_lut6">
+          <pb_type name="ble6" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="6" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->
+              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+              <direct name="direct2" input="lut6.out" output="ff.D">
+                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
+            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+          </interconnect>
+        </mode>
+        <!-- n1_lut6 -->
+      </pb_type>
+      <interconnect>
+        <!-- We use a 50% depop crossbar built using small full xbars to get sets of logically equivalent pins at inputs of CLB 
+           The delays below come from Stratix IV. the delay through a connection block
+           input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+           delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+           delay within the crossbar is 95 ps. 
+           The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+           Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+           25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+           to get the part that should be marked on the crossbar.	 -->
+        <!-- 50% sparsely populated local routing -->
+        <complete name="lutA" input="clb.I4 clb.I3 fle[1:0].out fle[3:2].out fle[8:8].out" output="fle[9:0].in[0:0]">
+          <delay_constant max="95e-12" in_port="clb.I4" out_port="fle.in[0:0]"/>
+          <delay_constant max="95e-12" in_port="clb.I3" out_port="fle.in[0:0]"/>
+          <delay_constant max="75e-12" in_port="fle[1:0].out" out_port="fle.in[0:0]"/>
+          <delay_constant max="75e-12" in_port="fle[3:2].out" out_port="fle.in[0:0]"/>
+          <delay_constant max="75e-12" in_port="fle[8:8].out" out_port="fle.in[0:0]"/>
+        </complete>
+        <complete name="lutB" input="clb.I3 clb.I2 fle[3:2].out fle[5:4].out fle[9:9].out" output="fle[9:0].in[1:1]">
+          <delay_constant max="95e-12" in_port="clb.I3" out_port="fle.in[1:1]"/>
+          <delay_constant max="95e-12" in_port="clb.I2" out_port="fle.in[1:1]"/>
+          <delay_constant max="75e-12" in_port="fle[3:2].out" out_port="fle.in[1:1]"/>
+          <delay_constant max="75e-12" in_port="fle[5:4].out" out_port="fle.in[1:1]"/>
+          <delay_constant max="75e-12" in_port="fle[9:9].out" out_port="fle.in[1:1]"/>
+        </complete>
+        <complete name="lutC" input="clb.I2 clb.I1 fle[5:4].out fle[7:6].out fle[8:8].out" output="fle[9:0].in[2:2]">
+          <delay_constant max="95e-12" in_port="clb.I2" out_port="fle.in[2:2]"/>
+          <delay_constant max="95e-12" in_port="clb.I1" out_port="fle.in[2:2]"/>
+          <delay_constant max="75e-12" in_port="fle[5:4].out" out_port="fle.in[2:2]"/>
+          <delay_constant max="75e-12" in_port="fle[7:6].out" out_port="fle.in[2:2]"/>
+          <delay_constant max="75e-12" in_port="fle[8:8].out" out_port="fle.in[2:2]"/>
+        </complete>
+        <complete name="lutD" input="clb.I4 clb.I2 fle[1:0].out fle[5:4].out fle[9:9].out" output="fle[9:0].in[3:3]">
+          <delay_constant max="95e-12" in_port="clb.I4" out_port="fle.in[3:3]"/>
+          <delay_constant max="95e-12" in_port="clb.I2" out_port="fle.in[3:3]"/>
+          <delay_constant max="75e-12" in_port="fle[1:0].out" out_port="fle.in[3:3]"/>
+          <delay_constant max="75e-12" in_port="fle[5:4].out" out_port="fle.in[3:3]"/>
+          <delay_constant max="75e-12" in_port="fle[9:9].out" out_port="fle.in[3:3]"/>
+        </complete>
+        <complete name="lutE" input="clb.I3 clb.I1 fle[3:2].out fle[7:6].out fle[8:8].out" output="fle[9:0].in[4:4]">
+          <delay_constant max="95e-12" in_port="clb.I3" out_port="fle.in[4:4]"/>
+          <delay_constant max="95e-12" in_port="clb.I1" out_port="fle.in[4:4]"/>
+          <delay_constant max="75e-12" in_port="fle[3:2].out" out_port="fle.in[4:4]"/>
+          <delay_constant max="75e-12" in_port="fle[7:6].out" out_port="fle.in[4:4]"/>
+          <delay_constant max="75e-12" in_port="fle[8:8].out" out_port="fle.in[4:4]"/>
+        </complete>
+        <complete name="lutF" input="clb.I4 clb.I1 fle[1:0].out fle[7:6].out fle[9:9].out" output="fle[9:0].in[5:5]">
+          <delay_constant max="95e-12" in_port="clb.I4" out_port="fle.in[5:5]"/>
+          <delay_constant max="95e-12" in_port="clb.I1" out_port="fle.in[5:5]"/>
+          <delay_constant max="75e-12" in_port="fle[1:0].out" out_port="fle.in[5:5]"/>
+          <delay_constant max="75e-12" in_port="fle[7:6].out" out_port="fle.in[5:5]"/>
+          <delay_constant max="75e-12" in_port="fle[9:9].out" out_port="fle.in[5:5]"/>
+        </complete>
+        <complete name="lutG" input="clb.I4 clb.I3 fle[1:0].out fle[3:2].out fle[8:8].out" output="fle[9:0].in[6:6]">
+          <delay_constant max="95e-12" in_port="clb.I4" out_port="fle.in[6:6]"/>
+          <delay_constant max="95e-12" in_port="clb.I3" out_port="fle.in[6:6]"/>
+          <delay_constant max="75e-12" in_port="fle[1:0].out" out_port="fle.in[6:6]"/>
+          <delay_constant max="75e-12" in_port="fle[3:2].out" out_port="fle.in[6:6]"/>
+          <delay_constant max="75e-12" in_port="fle[8:8].out" out_port="fle.in[6:6]"/>
+        </complete>
+        <complete name="lutH" input="clb.I3 clb.I2 fle[3:2].out fle[5:4].out fle[9:9].out" output="fle[9:0].in[7:7]">
+          <delay_constant max="95e-12" in_port="clb.I3" out_port="fle.in[7:7]"/>
+          <delay_constant max="95e-12" in_port="clb.I2" out_port="fle.in[7:7]"/>
+          <delay_constant max="75e-12" in_port="fle[3:2].out" out_port="fle.in[7:7]"/>
+          <delay_constant max="75e-12" in_port="fle[5:4].out" out_port="fle.in[7:7]"/>
+          <delay_constant max="75e-12" in_port="fle[9:9].out" out_port="fle.in[7:7]"/>
+        </complete>
+        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+          </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+                 By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+                 then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+                 naive specification).
+          -->
+        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
+        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
+        <!-- Carry chain links -->
+        <direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
+          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
+        </direct>
+        <direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
+          <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
+        </direct>
+        <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
+          <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
+        </direct>
+      </interconnect>
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+    <!-- Define fracturable multiplier begin -->
+    <!-- This multiplier can operate as a 36x36 multiplier that can fracture to two 18x18 multipliers each of which can further fracture to two 9x9 multipliers 
+	   For delay modelling, the 36x36 DSP multiplier in Stratix IV has a delay of 1.523 ns + 1.93 ns
+	    = 3.45 ns. The 18x18 mode doesn't need to sum four 18x18 multipliers, so it is a bit
+	   faster: 1.523 ns for the multiplier, and 1.09 ns for the multiplier output block.
+	    For the input and output interconnect delays, unlike Stratix IV, we don't
+	   have any routing/logic flexibility (crossbars) at the inputs.  There is some output muxing
+	   in Stratix IV and this architecture to select which multiplier outputs should go out (e.g.
+	   9x9 outputs, 18x18 or 36x36) so those are very close between the two architectures. 
+	   We take the conservative (slightly pessimistic)
+           approach modelling the input as the same as the Stratix IV input delay and the output delay the same as the Stratix IV DSP out delay.
+		   
+	   We estimate block area by using the published Stratix III data (which is architecturally identical to Stratix IV)
+	      (H. Wong, V. Betz and J. Rose, "Comparing FPGA vs. Custom CMOS and the Impact on Processor Microarchitecture", FPGA 2011) of 0.2623 
+		  mm^2 and scaling from 65 to 40 nm to obtain 0.0993 mm^2. That area is for a DSP block with approximately 2x the functionality of 
+		  the block we use (can implement two 36x36 multiplies instead of our 1, eight 18x18 multiplies instead of our 4, etc.). Hence we 
+		  divide the area by 2 to obtain 0.0497 mm^2. One minimum-width transistor units = 60 L^2 (where L = 40 nm), so is 518,000 MWTUS. 
+		  That area includes routing and the connection block input muxes.  Our DSP block is four 
+		  rows high, and hence includes four horizontal routing channel segments and four vertical ones, which is 4x the routing of a logic 
+		  block (single tile). It also includes 3.6x the outputs of a logic block, and 1.8x the inputs. Hence a slight overestimate of the routing
+		  area associated with our DSP block is four times that of a logic tile, where the routing area of a logic tile was calculated above (at W = 300)
+		  as 30481 MWTAs. Hence the (core, non-routing) area our DSP block is approximately 518,000 - 4 * 30,481 = 396,000 MWTUs.
+      -->
+    <pb_type name="mult_36">
+      <input name="a" num_pins="36"/>
+      <input name="b" num_pins="36"/>
+      <output name="out" num_pins="72"/>
+      <mode name="two_divisible_mult_18x18">
+        <pb_type name="divisible_mult_18x18" num_pb="2">
+          <input name="a" num_pins="18"/>
+          <input name="b" num_pins="18"/>
+          <output name="out" num_pins="36"/>
+          <!-- Model 9x9 delay and 18x18 delay as the same.  9x9 could be faster, but in Stratix IV
+	          isn't, presumably because the multiplier layout is really optimized for 18x18.
+		-->
+          <mode name="two_mult_9x9">
+            <pb_type name="mult_9x9_slice" num_pb="2">
+              <input name="A_cfg" num_pins="9"/>
+              <input name="B_cfg" num_pins="9"/>
+              <output name="OUT_cfg" num_pins="18"/>
+              <pb_type name="mult_9x9" blif_model=".subckt multiply" num_pb="1">
+                <input name="a" num_pins="9"/>
+                <input name="b" num_pins="9"/>
+                <output name="out" num_pins="18"/>
+                <delay_constant max="1.523e-9" in_port="mult_9x9.a" out_port="mult_9x9.out"/>
+                <delay_constant max="1.523e-9" in_port="mult_9x9.b" out_port="mult_9x9.out"/>
+              </pb_type>
+              <interconnect>
+                <direct name="a2a" input="mult_9x9_slice.A_cfg" output="mult_9x9.a">
+                </direct>
+                <direct name="b2b" input="mult_9x9_slice.B_cfg" output="mult_9x9.b">
+                </direct>
+                <direct name="out2out" input="mult_9x9.out" output="mult_9x9_slice.OUT_cfg">
+                </direct>
+              </interconnect>
+              <power method="pin-toggle">
+                <port name="A_cfg" energy_per_toggle="1.45e-12"/>
+                <port name="B_cfg" energy_per_toggle="1.45e-12"/>
+                <static_power power_per_instance="0.0"/>
+              </power>
+            </pb_type>
+            <interconnect>
+              <direct name="a2a" input="divisible_mult_18x18.a" output="mult_9x9_slice[1:0].A_cfg">
+              </direct>
+              <direct name="b2b" input="divisible_mult_18x18.b" output="mult_9x9_slice[1:0].B_cfg">
+              </direct>
+              <direct name="out2out" input="mult_9x9_slice[1:0].OUT_cfg" output="divisible_mult_18x18.out">
+              </direct>
+            </interconnect>
+          </mode>
+          <mode name="mult_18x18">
+            <pb_type name="mult_18x18_slice" num_pb="1">
+              <input name="A_cfg" num_pins="18"/>
+              <input name="B_cfg" num_pins="18"/>
+              <output name="OUT_cfg" num_pins="36"/>
+              <pb_type name="mult_18x18" blif_model=".subckt multiply" num_pb="1">
+                <input name="a" num_pins="18"/>
+                <input name="b" num_pins="18"/>
+                <output name="out" num_pins="36"/>
+                <delay_constant max="1.523e-9" in_port="mult_18x18.a" out_port="mult_18x18.out"/>
+                <delay_constant max="1.523e-9" in_port="mult_18x18.b" out_port="mult_18x18.out"/>
+              </pb_type>
+              <interconnect>
+                <direct name="a2a" input="mult_18x18_slice.A_cfg" output="mult_18x18.a">
+                </direct>
+                <direct name="b2b" input="mult_18x18_slice.B_cfg" output="mult_18x18.b">
+                </direct>
+                <direct name="out2out" input="mult_18x18.out" output="mult_18x18_slice.OUT_cfg">
+                </direct>
+              </interconnect>
+              <power method="pin-toggle">
+                <port name="A_cfg" energy_per_toggle="1.09e-12"/>
+                <port name="B_cfg" energy_per_toggle="1.09e-12"/>
+                <static_power power_per_instance="0.0"/>
+              </power>
+            </pb_type>
+            <interconnect>
+              <direct name="a2a" input="divisible_mult_18x18.a" output="mult_18x18_slice.A_cfg">
+              </direct>
+              <direct name="b2b" input="divisible_mult_18x18.b" output="mult_18x18_slice.B_cfg">
+              </direct>
+              <direct name="out2out" input="mult_18x18_slice.OUT_cfg" output="divisible_mult_18x18.out">
+              </direct>
+            </interconnect>
+          </mode>
+          <power method="sum-of-children"/>
+        </pb_type>
+        <interconnect>
+          <!-- Stratix IV input delay of 207ps is conservative for this architecture because this architecture does not have an input crossbar in the multiplier. 
+		   Subtract 72.5 ps delay, which is already in the connection block input mux, leading
+              -->
+          <direct name="a2a" input="mult_36.a" output="divisible_mult_18x18[1:0].a">
+            <delay_constant max="134e-12" in_port="mult_36.a" out_port="divisible_mult_18x18[1:0].a"/>
+          </direct>
+          <direct name="b2b" input="mult_36.b" output="divisible_mult_18x18[1:0].b">
+            <delay_constant max="134e-12" in_port="mult_36.b" out_port="divisible_mult_18x18[1:0].b"/>
+          </direct>
+          <direct name="out2out" input="divisible_mult_18x18[1:0].out" output="mult_36.out">
+            <delay_constant max="1.09e-9" in_port="divisible_mult_18x18[1:0].out" out_port="mult_36.out"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="mult_36x36">
+        <pb_type name="mult_36x36_slice" num_pb="1">
+          <input name="A_cfg" num_pins="36"/>
+          <input name="B_cfg" num_pins="36"/>
+          <output name="OUT_cfg" num_pins="72"/>
+          <pb_type name="mult_36x36" blif_model=".subckt multiply" num_pb="1">
+            <input name="a" num_pins="36"/>
+            <input name="b" num_pins="36"/>
+            <output name="out" num_pins="72"/>
+            <delay_constant max="1.523e-9" in_port="mult_36x36.a" out_port="mult_36x36.out"/>
+            <delay_constant max="1.523e-9" in_port="mult_36x36.b" out_port="mult_36x36.out"/>
+          </pb_type>
+          <interconnect>
+            <direct name="a2a" input="mult_36x36_slice.A_cfg" output="mult_36x36.a">
+            </direct>
+            <direct name="b2b" input="mult_36x36_slice.B_cfg" output="mult_36x36.b">
+            </direct>
+            <direct name="out2out" input="mult_36x36.out" output="mult_36x36_slice.OUT_cfg">
+            </direct>
+          </interconnect>
+          <power method="pin-toggle">
+            <port name="A_cfg" energy_per_toggle="2.13e-12"/>
+            <port name="B_cfg" energy_per_toggle="2.13e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <!-- Stratix IV input delay of 207ps is conservative for this architecture because this architecture does not have an input crossbar in the multiplier. 
+		   Subtract 72.5 ps delay, which is already in the connection block input mux, leading
+		   to a 134 ps delay.
+              -->
+          <direct name="a2a" input="mult_36.a" output="mult_36x36_slice.A_cfg">
+            <delay_constant max="134e-12" in_port="mult_36.a" out_port="mult_36x36_slice.A_cfg"/>
+          </direct>
+          <direct name="b2b" input="mult_36.b" output="mult_36x36_slice.B_cfg">
+            <delay_constant max="134e-12" in_port="mult_36.b" out_port="mult_36x36_slice.B_cfg"/>
+          </direct>
+          <direct name="out2out" input="mult_36x36_slice.OUT_cfg" output="mult_36.out">
+            <delay_constant max="1.93e-9" in_port="mult_36x36_slice.OUT_cfg" out_port="mult_36.out"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Place this multiplier block every 8 columns from (and including) the sixth column -->
+      <power method="sum-of-children"/>
+    </pb_type>
+    <!-- Define fracturable multiplier end -->
+    <!-- Define fracturable memory begin -->
+    <!-- 32 Kb Memory that can operate from 512x64 to 32Kx1 for single-port mode and 1024x32 to 32Kx1 for dual-port mode.  
+           Area and delay based off Stratix IV 9K and 144K memories (delay from linear interpolation, Tsu(483 ps, 636 ps) Tco(1084ps, 1969ps)).  
+           Input delay = 204ps (from Stratix IV LAB line) - 72ps (this architecture does not lump connection box delay in internal delay)
+           Output delay = M9K buffer 50ps
+		   
+		   Area is obtained by appropriately scaling and adjusting the published Stratix III (which is architecturally identical to Stratix IV)
+		   data from H. Wong, V. Betz and J. Rose, "Comparing FPGA vs. Custom CMOS and the Impact on Processor Microarchitecture", FPGA 2011.
+		   Linearly interpolating (by bit count) between the M9k and M144k areas to obtain an M32k (our RAM size) point yields a 65 nm area of
+		   of 0.153 mm^2. Interpolating based on port count between the RAMs would instead yield an area of 0.209 mm^2 for our 32 kB RAM; since 
+		   bit count accounts for more area than ports for a RAM this size we choose the bit count interpolation; however, since the port interpolation
+		   is not radically different this also gives us confidence that interpolating based on bits is OK, but slightly underpredicts area.
+		   Scaling to 40 nm^2 yields .0579 mm^2, and converting to MWTUs at 60 L^2 / MWTU yields 604,000 MWTUs. This includes routing. A Stratix IV
+		   M9K RAM is one row high and hence has one routing tile (one horizonal and one vertical routing segment area). An M144k RAM has 8 such tiles.
+		   Linearly interpolating on
+		   bits to 32 kb yields 2.2 routing tiles incorporated in the area number above. The inter-block routing represents 30% of the area of a logic 
+		   tile according to D. Lewis et al, "Architectural Enhancements in Stratix V," FPGA 2013. Hence we should subtract 0.3 * 2.2 * 84,375 MWTUs to
+		   obtain a RAM core area (not including inter-block routing) of 548,000 MWTU areas for our 32 kb RAM in a 40 nm process.
+      -->
+    <pb_type name="memory">
+      <input name="addr1" num_pins="15"/>
+      <input name="addr2" num_pins="15"/>
+      <input name="data" num_pins="64"/>
+      <input name="we1" num_pins="1"/>
+      <input name="we2" num_pins="1"/>
+      <output name="out" num_pins="64"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Specify single port mode first -->
+      <mode name="mem_512x64_sp">
+        <pb_type name="mem_512x64_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
+          <input name="addr" num_pins="9" port_class="address"/>
+          <input name="data" num_pins="64" port_class="data_in"/>
+          <input name="we" num_pins="1" port_class="write_en"/>
+          <output name="out" num_pins="64" port_class="data_out"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_512x64_sp.addr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x64_sp.data" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x64_sp.we" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_512x64_sp.out" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="9.0e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="address1" input="memory.addr1[8:0]" output="mem_512x64_sp.addr">
+            <delay_constant max="132e-12" in_port="memory.addr1[8:0]" out_port="mem_512x64_sp.addr"/>
+          </direct>
+          <direct name="data1" input="memory.data[63:0]" output="mem_512x64_sp.data">
+            <delay_constant max="132e-12" in_port="memory.data[63:0]" out_port="mem_512x64_sp.data"/>
+          </direct>
+          <direct name="writeen1" input="memory.we1" output="mem_512x64_sp.we">
+            <delay_constant max="132e-12" in_port="memory.we1" out_port="mem_512x64_sp.we"/>
+          </direct>
+          <direct name="dataout1" input="mem_512x64_sp.out" output="memory.out[63:0]">
+            <delay_constant max="40e-12" in_port="mem_512x64_sp.out" out_port="memory.out[63:0]"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_512x64_sp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="mem_1024x32_sp">
+        <pb_type name="mem_1024x32_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
+          <input name="addr" num_pins="10" port_class="address"/>
+          <input name="data" num_pins="32" port_class="data_in"/>
+          <input name="we" num_pins="1" port_class="write_en"/>
+          <output name="out" num_pins="32" port_class="data_out"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_1024x32_sp.addr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_1024x32_sp.data" clock="clk"/>
+          <T_setup value="509e-12" port="mem_1024x32_sp.we" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_1024x32_sp.out" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="9.0e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="address1" input="memory.addr1[9:0]" output="mem_1024x32_sp.addr">
+            <delay_constant max="132e-12" in_port="memory.addr1[9:0]" out_port="mem_1024x32_sp.addr"/>
+          </direct>
+          <direct name="data1" input="memory.data[31:0]" output="mem_1024x32_sp.data">
+            <delay_constant max="132e-12" in_port="memory.data[31:0]" out_port="mem_1024x32_sp.data"/>
+          </direct>
+          <direct name="writeen1" input="memory.we1" output="mem_1024x32_sp.we">
+            <delay_constant max="132e-12" in_port="memory.we1" out_port="mem_1024x32_sp.we"/>
+          </direct>
+          <direct name="dataout1" input="mem_1024x32_sp.out" output="memory.out[31:0]">
+            <delay_constant max="40e-12" in_port="mem_1024x32_sp.out" out_port="memory.out[31:0]"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_1024x32_sp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="mem_2048x16_sp">
+        <pb_type name="mem_2048x16_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
+          <input name="addr" num_pins="11" port_class="address"/>
+          <input name="data" num_pins="16" port_class="data_in"/>
+          <input name="we" num_pins="1" port_class="write_en"/>
+          <output name="out" num_pins="16" port_class="data_out"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_2048x16_sp.addr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_2048x16_sp.data" clock="clk"/>
+          <T_setup value="509e-12" port="mem_2048x16_sp.we" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_2048x16_sp.out" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="9.0e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="address1" input="memory.addr1[10:0]" output="mem_2048x16_sp.addr">
+            <delay_constant max="132e-12" in_port="memory.addr1[10:0]" out_port="mem_2048x16_sp.addr"/>
+          </direct>
+          <direct name="data1" input="memory.data[15:0]" output="mem_2048x16_sp.data">
+            <delay_constant max="132e-12" in_port="memory.data[15:0]" out_port="mem_2048x16_sp.data"/>
+          </direct>
+          <direct name="writeen1" input="memory.we1" output="mem_2048x16_sp.we">
+            <delay_constant max="132e-12" in_port="memory.we1" out_port="mem_2048x16_sp.we"/>
+          </direct>
+          <direct name="dataout1" input="mem_2048x16_sp.out" output="memory.out[15:0]">
+            <delay_constant max="40e-12" in_port="mem_2048x16_sp.out" out_port="memory.out[15:0]"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_2048x16_sp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="mem_4096x8_sp">
+        <pb_type name="mem_4096x8_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
+          <input name="addr" num_pins="12" port_class="address"/>
+          <input name="data" num_pins="8" port_class="data_in"/>
+          <input name="we" num_pins="1" port_class="write_en"/>
+          <output name="out" num_pins="8" port_class="data_out"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_4096x8_sp.addr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_4096x8_sp.data" clock="clk"/>
+          <T_setup value="509e-12" port="mem_4096x8_sp.we" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_4096x8_sp.out" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="9.0e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="address1" input="memory.addr1[11:0]" output="mem_4096x8_sp.addr">
+            <delay_constant max="132e-12" in_port="memory.addr1[11:0]" out_port="mem_4096x8_sp.addr"/>
+          </direct>
+          <direct name="data1" input="memory.data[7:0]" output="mem_4096x8_sp.data">
+            <delay_constant max="132e-12" in_port="memory.data[7:0]" out_port="mem_4096x8_sp.data"/>
+          </direct>
+          <direct name="writeen1" input="memory.we1" output="mem_4096x8_sp.we">
+            <delay_constant max="132e-12" in_port="memory.we1" out_port="mem_4096x8_sp.we"/>
+          </direct>
+          <direct name="dataout1" input="mem_4096x8_sp.out" output="memory.out[7:0]">
+            <delay_constant max="40e-12" in_port="mem_4096x8_sp.out" out_port="memory.out[7:0]"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_4096x8_sp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="mem_8192x4_sp">
+        <pb_type name="mem_8192x4_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
+          <input name="addr" num_pins="13" port_class="address"/>
+          <input name="data" num_pins="4" port_class="data_in"/>
+          <input name="we" num_pins="1" port_class="write_en"/>
+          <output name="out" num_pins="4" port_class="data_out"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_8192x4_sp.addr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_8192x4_sp.data" clock="clk"/>
+          <T_setup value="509e-12" port="mem_8192x4_sp.we" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_8192x4_sp.out" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="9.0e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="address1" input="memory.addr1[12:0]" output="mem_8192x4_sp.addr">
+            <delay_constant max="132e-12" in_port="memory.addr1[12:0]" out_port="mem_8192x4_sp.addr"/>
+          </direct>
+          <direct name="data1" input="memory.data[3:0]" output="mem_8192x4_sp.data">
+            <delay_constant max="132e-12" in_port="memory.data[3:0]" out_port="mem_8192x4_sp.data"/>
+          </direct>
+          <direct name="writeen1" input="memory.we1" output="mem_8192x4_sp.we">
+            <delay_constant max="132e-12" in_port="memory.we1" out_port="mem_8192x4_sp.we"/>
+          </direct>
+          <direct name="dataout1" input="mem_8192x4_sp.out" output="memory.out[3:0]">
+            <delay_constant max="40e-12" in_port="mem_8192x4_sp.out" out_port="memory.out[3:0]"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_8192x4_sp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="mem_16384x2_sp">
+        <pb_type name="mem_16384x2_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
+          <input name="addr" num_pins="14" port_class="address"/>
+          <input name="data" num_pins="2" port_class="data_in"/>
+          <input name="we" num_pins="1" port_class="write_en"/>
+          <output name="out" num_pins="2" port_class="data_out"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_16384x2_sp.addr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_16384x2_sp.data" clock="clk"/>
+          <T_setup value="509e-12" port="mem_16384x2_sp.we" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_16384x2_sp.out" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="9.0e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="address1" input="memory.addr1[13:0]" output="mem_16384x2_sp.addr">
+            <delay_constant max="132e-12" in_port="memory.addr1[13:0]" out_port="mem_16384x2_sp.addr"/>
+          </direct>
+          <direct name="data1" input="memory.data[1:0]" output="mem_16384x2_sp.data">
+            <delay_constant max="132e-12" in_port="memory.data[1:0]" out_port="mem_16384x2_sp.data"/>
+          </direct>
+          <direct name="writeen1" input="memory.we1" output="mem_16384x2_sp.we">
+            <delay_constant max="132e-12" in_port="memory.we1" out_port="mem_16384x2_sp.we"/>
+          </direct>
+          <direct name="dataout1" input="mem_16384x2_sp.out" output="memory.out[1:0]">
+            <delay_constant max="40e-12" in_port="mem_16384x2_sp.out" out_port="memory.out[1:0]"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_16384x2_sp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="mem_32768x1_sp">
+        <pb_type name="mem_32768x1_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
+          <input name="addr" num_pins="15" port_class="address"/>
+          <input name="data" num_pins="1" port_class="data_in"/>
+          <input name="we" num_pins="1" port_class="write_en"/>
+          <output name="out" num_pins="1" port_class="data_out"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_32768x1_sp.addr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_32768x1_sp.data" clock="clk"/>
+          <T_setup value="509e-12" port="mem_32768x1_sp.we" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_32768x1_sp.out" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="9.0e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="address1" input="memory.addr1[14:0]" output="mem_32768x1_sp.addr">
+            <delay_constant max="132e-12" in_port="memory.addr1[14:0]" out_port="mem_32768x1_sp.addr"/>
+          </direct>
+          <direct name="data1" input="memory.data[0:0]" output="mem_32768x1_sp.data">
+            <delay_constant max="132e-12" in_port="memory.data[0:0]" out_port="mem_32768x1_sp.data"/>
+          </direct>
+          <direct name="writeen1" input="memory.we1" output="mem_32768x1_sp.we">
+            <delay_constant max="132e-12" in_port="memory.we1" out_port="mem_32768x1_sp.we"/>
+          </direct>
+          <direct name="dataout1" input="mem_32768x1_sp.out" output="memory.out[0:0]">
+            <delay_constant max="40e-12" in_port="mem_32768x1_sp.out" out_port="memory.out[0:0]"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_32768x1_sp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Specify true dual port mode next -->
+      <mode name="mem_1024x32_dp">
+        <pb_type name="mem_1024x32_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
+          <input name="addr1" num_pins="10" port_class="address1"/>
+          <input name="addr2" num_pins="10" port_class="address2"/>
+          <input name="data1" num_pins="32" port_class="data_in1"/>
+          <input name="data2" num_pins="32" port_class="data_in2"/>
+          <input name="we1" num_pins="1" port_class="write_en1"/>
+          <input name="we2" num_pins="1" port_class="write_en2"/>
+          <output name="out1" num_pins="32" port_class="data_out1"/>
+          <output name="out2" num_pins="32" port_class="data_out2"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_1024x32_dp.addr1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_1024x32_dp.data1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_1024x32_dp.we1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_1024x32_dp.addr2" clock="clk"/>
+          <T_setup value="509e-12" port="mem_1024x32_dp.data2" clock="clk"/>
+          <T_setup value="509e-12" port="mem_1024x32_dp.we2" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_1024x32_dp.out1" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_1024x32_dp.out2" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="17.9e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="address1" input="memory.addr1[9:0]" output="mem_1024x32_dp.addr1">
+            <delay_constant max="132e-12" in_port="memory.addr1[9:0]" out_port="mem_1024x32_dp.addr1"/>
+          </direct>
+          <direct name="address2" input="memory.addr2[9:0]" output="mem_1024x32_dp.addr2">
+            <delay_constant max="132e-12" in_port="memory.addr2[9:0]" out_port="mem_1024x32_dp.addr2"/>
+          </direct>
+          <direct name="data1" input="memory.data[31:0]" output="mem_1024x32_dp.data1">
+            <delay_constant max="132e-12" in_port="memory.data[31:0]" out_port="mem_1024x32_dp.data1"/>
+          </direct>
+          <direct name="data2" input="memory.data[63:32]" output="mem_1024x32_dp.data2">
+            <delay_constant max="132e-12" in_port="memory.data[63:32]" out_port="mem_1024x32_dp.data2"/>
+          </direct>
+          <direct name="writeen1" input="memory.we1" output="mem_1024x32_dp.we1">
+            <delay_constant max="132e-12" in_port="memory.we1" out_port="mem_1024x32_dp.we1"/>
+          </direct>
+          <direct name="writeen2" input="memory.we2" output="mem_1024x32_dp.we2">
+            <delay_constant max="132e-12" in_port="memory.we2" out_port="mem_1024x32_dp.we2"/>
+          </direct>
+          <direct name="dataout1" input="mem_1024x32_dp.out1" output="memory.out[31:0]">
+            <delay_constant max="40e-12" in_port="mem_1024x32_dp.out1" out_port="memory.out[31:0]"/>
+          </direct>
+          <direct name="dataout2" input="mem_1024x32_dp.out2" output="memory.out[63:32]">
+            <delay_constant max="40e-12" in_port="mem_1024x32_dp.out2" out_port="memory.out[63:32]"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_1024x32_dp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="mem_2048x16_dp">
+        <pb_type name="mem_2048x16_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
+          <input name="addr1" num_pins="11" port_class="address1"/>
+          <input name="addr2" num_pins="11" port_class="address2"/>
+          <input name="data1" num_pins="16" port_class="data_in1"/>
+          <input name="data2" num_pins="16" port_class="data_in2"/>
+          <input name="we1" num_pins="1" port_class="write_en1"/>
+          <input name="we2" num_pins="1" port_class="write_en2"/>
+          <output name="out1" num_pins="16" port_class="data_out1"/>
+          <output name="out2" num_pins="16" port_class="data_out2"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_2048x16_dp.addr1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_2048x16_dp.data1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_2048x16_dp.we1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_2048x16_dp.addr2" clock="clk"/>
+          <T_setup value="509e-12" port="mem_2048x16_dp.data2" clock="clk"/>
+          <T_setup value="509e-12" port="mem_2048x16_dp.we2" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_2048x16_dp.out1" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_2048x16_dp.out2" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="17.9e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="address1" input="memory.addr1[10:0]" output="mem_2048x16_dp.addr1">
+            <delay_constant max="132e-12" in_port="memory.addr1[10:0]" out_port="mem_2048x16_dp.addr1"/>
+          </direct>
+          <direct name="address2" input="memory.addr2[10:0]" output="mem_2048x16_dp.addr2">
+            <delay_constant max="132e-12" in_port="memory.addr2[10:0]" out_port="mem_2048x16_dp.addr2"/>
+          </direct>
+          <direct name="data1" input="memory.data[15:0]" output="mem_2048x16_dp.data1">
+            <delay_constant max="132e-12" in_port="memory.data[15:0]" out_port="mem_2048x16_dp.data1"/>
+          </direct>
+          <direct name="data2" input="memory.data[31:16]" output="mem_2048x16_dp.data2">
+            <delay_constant max="132e-12" in_port="memory.data[31:16]" out_port="mem_2048x16_dp.data2"/>
+          </direct>
+          <direct name="writeen1" input="memory.we1" output="mem_2048x16_dp.we1">
+            <delay_constant max="132e-12" in_port="memory.we1" out_port="mem_2048x16_dp.we1"/>
+          </direct>
+          <direct name="writeen2" input="memory.we2" output="mem_2048x16_dp.we2">
+            <delay_constant max="132e-12" in_port="memory.we2" out_port="mem_2048x16_dp.we2"/>
+          </direct>
+          <direct name="dataout1" input="mem_2048x16_dp.out1" output="memory.out[15:0]">
+            <delay_constant max="40e-12" in_port="mem_2048x16_dp.out1" out_port="memory.out[15:0]"/>
+          </direct>
+          <direct name="dataout2" input="mem_2048x16_dp.out2" output="memory.out[31:16]">
+            <delay_constant max="40e-12" in_port="mem_2048x16_dp.out2" out_port="memory.out[31:16]"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_2048x16_dp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="mem_2048x8_dp">
+        <pb_type name="mem_2048x8_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
+          <input name="addr1" num_pins="12" port_class="address1"/>
+          <input name="addr2" num_pins="12" port_class="address2"/>
+          <input name="data1" num_pins="8" port_class="data_in1"/>
+          <input name="data2" num_pins="8" port_class="data_in2"/>
+          <input name="we1" num_pins="1" port_class="write_en1"/>
+          <input name="we2" num_pins="1" port_class="write_en2"/>
+          <output name="out1" num_pins="8" port_class="data_out1"/>
+          <output name="out2" num_pins="8" port_class="data_out2"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_2048x8_dp.addr1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_2048x8_dp.data1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_2048x8_dp.we1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_2048x8_dp.addr2" clock="clk"/>
+          <T_setup value="509e-12" port="mem_2048x8_dp.data2" clock="clk"/>
+          <T_setup value="509e-12" port="mem_2048x8_dp.we2" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_2048x8_dp.out1" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_2048x8_dp.out2" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="17.9e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="address1" input="memory.addr1[11:0]" output="mem_2048x8_dp.addr1">
+            <delay_constant max="132e-12" in_port="memory.addr1[11:0]" out_port="mem_2048x8_dp.addr1"/>
+          </direct>
+          <direct name="address2" input="memory.addr2[11:0]" output="mem_2048x8_dp.addr2">
+            <delay_constant max="132e-12" in_port="memory.addr2[11:0]" out_port="mem_2048x8_dp.addr2"/>
+          </direct>
+          <direct name="data1" input="memory.data[7:0]" output="mem_2048x8_dp.data1">
+            <delay_constant max="132e-12" in_port="memory.data[7:0]" out_port="mem_2048x8_dp.data1"/>
+          </direct>
+          <direct name="data2" input="memory.data[15:8]" output="mem_2048x8_dp.data2">
+            <delay_constant max="132e-12" in_port="memory.data[15:8]" out_port="mem_2048x8_dp.data2"/>
+          </direct>
+          <direct name="writeen1" input="memory.we1" output="mem_2048x8_dp.we1">
+            <delay_constant max="132e-12" in_port="memory.we1" out_port="mem_2048x8_dp.we1"/>
+          </direct>
+          <direct name="writeen2" input="memory.we2" output="mem_2048x8_dp.we2">
+            <delay_constant max="132e-12" in_port="memory.we2" out_port="mem_2048x8_dp.we2"/>
+          </direct>
+          <direct name="dataout1" input="mem_2048x8_dp.out1" output="memory.out[7:0]">
+            <delay_constant max="40e-12" in_port="mem_2048x8_dp.out1" out_port="memory.out[7:0]"/>
+          </direct>
+          <direct name="dataout2" input="mem_2048x8_dp.out2" output="memory.out[15:8]">
+            <delay_constant max="40e-12" in_port="mem_2048x8_dp.out2" out_port="memory.out[15:8]"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_2048x8_dp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="mem_8192x4_dp">
+        <pb_type name="mem_8192x4_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
+          <input name="addr1" num_pins="13" port_class="address1"/>
+          <input name="addr2" num_pins="13" port_class="address2"/>
+          <input name="data1" num_pins="4" port_class="data_in1"/>
+          <input name="data2" num_pins="4" port_class="data_in2"/>
+          <input name="we1" num_pins="1" port_class="write_en1"/>
+          <input name="we2" num_pins="1" port_class="write_en2"/>
+          <output name="out1" num_pins="4" port_class="data_out1"/>
+          <output name="out2" num_pins="4" port_class="data_out2"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_8192x4_dp.addr1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_8192x4_dp.data1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_8192x4_dp.we1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_8192x4_dp.addr2" clock="clk"/>
+          <T_setup value="509e-12" port="mem_8192x4_dp.data2" clock="clk"/>
+          <T_setup value="509e-12" port="mem_8192x4_dp.we2" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_8192x4_dp.out1" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_8192x4_dp.out2" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="17.9e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="address1" input="memory.addr1[12:0]" output="mem_8192x4_dp.addr1">
+            <delay_constant max="132e-12" in_port="memory.addr1[12:0]" out_port="mem_8192x4_dp.addr1"/>
+          </direct>
+          <direct name="address2" input="memory.addr2[12:0]" output="mem_8192x4_dp.addr2">
+            <delay_constant max="132e-12" in_port="memory.addr2[12:0]" out_port="mem_8192x4_dp.addr2"/>
+          </direct>
+          <direct name="data1" input="memory.data[3:0]" output="mem_8192x4_dp.data1">
+            <delay_constant max="132e-12" in_port="memory.data[3:0]" out_port="mem_8192x4_dp.data1"/>
+          </direct>
+          <direct name="data2" input="memory.data[7:4]" output="mem_8192x4_dp.data2">
+            <delay_constant max="132e-12" in_port="memory.data[7:4]" out_port="mem_8192x4_dp.data2"/>
+          </direct>
+          <direct name="writeen1" input="memory.we1" output="mem_8192x4_dp.we1">
+            <delay_constant max="132e-12" in_port="memory.we1" out_port="mem_8192x4_dp.we1"/>
+          </direct>
+          <direct name="writeen2" input="memory.we2" output="mem_8192x4_dp.we2">
+            <delay_constant max="132e-12" in_port="memory.we2" out_port="mem_8192x4_dp.we2"/>
+          </direct>
+          <direct name="dataout1" input="mem_8192x4_dp.out1" output="memory.out[3:0]">
+            <delay_constant max="40e-12" in_port="mem_8192x4_dp.out1" out_port="memory.out[3:0]"/>
+          </direct>
+          <direct name="dataout2" input="mem_8192x4_dp.out2" output="memory.out[7:4]">
+            <delay_constant max="40e-12" in_port="mem_8192x4_dp.out2" out_port="memory.out[7:4]"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_8192x4_dp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="mem_16384x2_dp">
+        <pb_type name="mem_16384x2_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
+          <input name="addr1" num_pins="14" port_class="address1"/>
+          <input name="addr2" num_pins="14" port_class="address2"/>
+          <input name="data1" num_pins="2" port_class="data_in1"/>
+          <input name="data2" num_pins="2" port_class="data_in2"/>
+          <input name="we1" num_pins="1" port_class="write_en1"/>
+          <input name="we2" num_pins="1" port_class="write_en2"/>
+          <output name="out1" num_pins="2" port_class="data_out1"/>
+          <output name="out2" num_pins="2" port_class="data_out2"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_16384x2_dp.addr1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_16384x2_dp.data1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_16384x2_dp.we1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_16384x2_dp.addr2" clock="clk"/>
+          <T_setup value="509e-12" port="mem_16384x2_dp.data2" clock="clk"/>
+          <T_setup value="509e-12" port="mem_16384x2_dp.we2" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_16384x2_dp.out1" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_16384x2_dp.out2" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="17.9e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="address1" input="memory.addr1[13:0]" output="mem_16384x2_dp.addr1">
+            <delay_constant max="132e-12" in_port="memory.addr1[13:0]" out_port="mem_16384x2_dp.addr1"/>
+          </direct>
+          <direct name="address2" input="memory.addr2[13:0]" output="mem_16384x2_dp.addr2">
+            <delay_constant max="132e-12" in_port="memory.addr2[13:0]" out_port="mem_16384x2_dp.addr2"/>
+          </direct>
+          <direct name="data1" input="memory.data[1:0]" output="mem_16384x2_dp.data1">
+            <delay_constant max="132e-12" in_port="memory.data[1:0]" out_port="mem_16384x2_dp.data1"/>
+          </direct>
+          <direct name="data2" input="memory.data[3:2]" output="mem_16384x2_dp.data2">
+            <delay_constant max="132e-12" in_port="memory.data[3:2]" out_port="mem_16384x2_dp.data2"/>
+          </direct>
+          <direct name="writeen1" input="memory.we1" output="mem_16384x2_dp.we1">
+            <delay_constant max="132e-12" in_port="memory.we1" out_port="mem_16384x2_dp.we1"/>
+          </direct>
+          <direct name="writeen2" input="memory.we2" output="mem_16384x2_dp.we2">
+            <delay_constant max="132e-12" in_port="memory.we2" out_port="mem_16384x2_dp.we2"/>
+          </direct>
+          <direct name="dataout1" input="mem_16384x2_dp.out1" output="memory.out[1:0]">
+            <delay_constant max="40e-12" in_port="mem_16384x2_dp.out1" out_port="memory.out[1:0]"/>
+          </direct>
+          <direct name="dataout2" input="mem_16384x2_dp.out2" output="memory.out[3:2]">
+            <delay_constant max="40e-12" in_port="mem_16384x2_dp.out2" out_port="memory.out[3:2]"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_16384x2_dp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="mem_32768x1_dp">
+        <pb_type name="mem_32768x1_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
+          <input name="addr1" num_pins="15" port_class="address1"/>
+          <input name="addr2" num_pins="15" port_class="address2"/>
+          <input name="data1" num_pins="1" port_class="data_in1"/>
+          <input name="data2" num_pins="1" port_class="data_in2"/>
+          <input name="we1" num_pins="1" port_class="write_en1"/>
+          <input name="we2" num_pins="1" port_class="write_en2"/>
+          <output name="out1" num_pins="1" port_class="data_out1"/>
+          <output name="out2" num_pins="1" port_class="data_out2"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_32768x1_dp.addr1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_32768x1_dp.data1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_32768x1_dp.we1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_32768x1_dp.addr2" clock="clk"/>
+          <T_setup value="509e-12" port="mem_32768x1_dp.data2" clock="clk"/>
+          <T_setup value="509e-12" port="mem_32768x1_dp.we2" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_32768x1_dp.out1" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_32768x1_dp.out2" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="17.9e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="address1" input="memory.addr1[14:0]" output="mem_32768x1_dp.addr1">
+            <delay_constant max="132e-12" in_port="memory.addr1[14:0]" out_port="mem_32768x1_dp.addr1"/>
+          </direct>
+          <direct name="address2" input="memory.addr2[14:0]" output="mem_32768x1_dp.addr2">
+            <delay_constant max="132e-12" in_port="memory.addr2[14:0]" out_port="mem_32768x1_dp.addr2"/>
+          </direct>
+          <direct name="data1" input="memory.data[0:0]" output="mem_32768x1_dp.data1">
+            <delay_constant max="132e-12" in_port="memory.data[0:0]" out_port="mem_32768x1_dp.data1"/>
+          </direct>
+          <direct name="data2" input="memory.data[1:1]" output="mem_32768x1_dp.data2">
+            <delay_constant max="132e-12" in_port="memory.data[1:1]" out_port="mem_32768x1_dp.data2"/>
+          </direct>
+          <direct name="writeen1" input="memory.we1" output="mem_32768x1_dp.we1">
+            <delay_constant max="132e-12" in_port="memory.we1" out_port="mem_32768x1_dp.we1"/>
+          </direct>
+          <direct name="writeen2" input="memory.we2" output="mem_32768x1_dp.we2">
+            <delay_constant max="132e-12" in_port="memory.we2" out_port="mem_32768x1_dp.we2"/>
+          </direct>
+          <direct name="dataout1" input="mem_32768x1_dp.out1" output="memory.out[0:0]">
+            <delay_constant max="40e-12" in_port="mem_32768x1_dp.out1" out_port="memory.out[0:0]"/>
+          </direct>
+          <direct name="dataout2" input="mem_32768x1_dp.out2" output="memory.out[1:1]">
+            <delay_constant max="40e-12" in_port="mem_32768x1_dp.out2" out_port="memory.out[1:1]"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_32768x1_dp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- Place this memory block every 8 columns from (and including) the second column -->
+      <power method="sum-of-children"/>
+    </pb_type>
+    <!-- Define fracturable memory end -->
+  </complexblocklist>
+  <power>
+    <local_interconnect C_wire="2.5e-10"/>
+    <mux_transistor_size mux_transistor_size="3"/>
+    <FF_size FF_size="4"/>
+    <LUT_transistor_size LUT_transistor_size="4"/>
+  </power>
+  <clocks>
+    <clock buffer_size="auto" C_wire="2.5e-10"/>
+  </clocks>
+</architecture>
diff --git a/openfpga/test_blif/riscv_core_lut6.blif b/openfpga/test_blif/riscv_core_lut6.blif
new file mode 100644
index 000000000..a313bebc1
--- /dev/null
+++ b/openfpga/test_blif/riscv_core_lut6.blif
@@ -0,0 +1,19187 @@
+# Generated by Yosys 0.8+599 (git sha1 463f710, gcc 4.8.5 -fPIC -Os)
+
+.model riscv_core
+.inputs clock reset bus_read_data[0] bus_read_data[1] bus_read_data[2] bus_read_data[3] bus_read_data[4] bus_read_data[5] bus_read_data[6] bus_read_data[7] bus_read_data[8] bus_read_data[9] bus_read_data[10] bus_read_data[11] bus_read_data[12] bus_read_data[13] bus_read_data[14] bus_read_data[15] bus_read_data[16] bus_read_data[17] bus_read_data[18] bus_read_data[19] bus_read_data[20] bus_read_data[21] bus_read_data[22] bus_read_data[23] bus_read_data[24] bus_read_data[25] bus_read_data[26] bus_read_data[27] bus_read_data[28] bus_read_data[29] bus_read_data[30] bus_read_data[31] inst[0] inst[1] inst[2] inst[3] inst[4] inst[5] inst[6] inst[7] inst[8] inst[9] inst[10] inst[11] inst[12] inst[13] inst[14] inst[15] inst[16] inst[17] inst[18] inst[19] inst[20] inst[21] inst[22] inst[23] inst[24] inst[25] inst[26] inst[27] inst[28] inst[29] inst[30] inst[31] rs1_data[0] rs1_data[1] rs1_data[2] rs1_data[3] rs1_data[4] rs1_data[5] rs1_data[6] rs1_data[7] rs1_data[8] rs1_data[9] rs1_data[10] rs1_data[11] rs1_data[12] rs1_data[13] rs1_data[14] rs1_data[15] rs1_data[16] rs1_data[17] rs1_data[18] rs1_data[19] rs1_data[20] rs1_data[21] rs1_data[22] rs1_data[23] rs1_data[24] rs1_data[25] rs1_data[26] rs1_data[27] rs1_data[28] rs1_data[29] rs1_data[30] rs1_data[31] rs2_data[0] rs2_data[1] rs2_data[2] rs2_data[3] rs2_data[4] rs2_data[5] rs2_data[6] rs2_data[7] rs2_data[8] rs2_data[9] rs2_data[10] rs2_data[11] rs2_data[12] rs2_data[13] rs2_data[14] rs2_data[15] rs2_data[16] rs2_data[17] rs2_data[18] rs2_data[19] rs2_data[20] rs2_data[21] rs2_data[22] rs2_data[23] rs2_data[24] rs2_data[25] rs2_data[26] rs2_data[27] rs2_data[28] rs2_data[29] rs2_data[30] rs2_data[31]
+.outputs bus_address[0] bus_address[1] bus_address[2] bus_address[3] bus_address[4] bus_address[5] bus_address[6] bus_address[7] bus_address[8] bus_address[9] bus_address[10] bus_address[11] bus_address[12] bus_address[13] bus_address[14] bus_address[15] bus_address[16] bus_address[17] bus_address[18] bus_address[19] bus_address[20] bus_address[21] bus_address[22] bus_address[23] bus_address[24] bus_address[25] bus_address[26] bus_address[27] bus_address[28] bus_address[29] bus_address[30] bus_address[31] bus_write_data[0] bus_write_data[1] bus_write_data[2] bus_write_data[3] bus_write_data[4] bus_write_data[5] bus_write_data[6] bus_write_data[7] bus_write_data[8] bus_write_data[9] bus_write_data[10] bus_write_data[11] bus_write_data[12] bus_write_data[13] bus_write_data[14] bus_write_data[15] bus_write_data[16] bus_write_data[17] bus_write_data[18] bus_write_data[19] bus_write_data[20] bus_write_data[21] bus_write_data[22] bus_write_data[23] bus_write_data[24] bus_write_data[25] bus_write_data[26] bus_write_data[27] bus_write_data[28] bus_write_data[29] bus_write_data[30] bus_write_data[31] bus_byte_enable[0] bus_byte_enable[1] bus_byte_enable[2] bus_byte_enable[3] bus_read_enable bus_write_enable pc[0] pc[1] pc[2] pc[3] pc[4] pc[5] pc[6] pc[7] pc[8] pc[9] pc[10] pc[11] pc[12] pc[13] pc[14] pc[15] pc[16] pc[17] pc[18] pc[19] pc[20] pc[21] pc[22] pc[23] pc[24] pc[25] pc[26] pc[27] pc[28] pc[29] pc[30] pc[31] regfile_write_enable rd_address[0] rd_address[1] rd_address[2] rd_address[3] rd_address[4] rs1_address[0] rs1_address[1] rs1_address[2] rs1_address[3] rs1_address[4] rs2_address[0] rs2_address[1] rs2_address[2] rs2_address[3] rs2_address[4] rd_data[0] rd_data[1] rd_data[2] rd_data[3] rd_data[4] rd_data[5] rd_data[6] rd_data[7] rd_data[8] rd_data[9] rd_data[10] rd_data[11] rd_data[12] rd_data[13] rd_data[14] rd_data[15] rd_data[16] rd_data[17] rd_data[18] rd_data[19] rd_data[20] rd_data[21] rd_data[22] rd_data[23] rd_data[24] rd_data[25] rd_data[26] rd_data[27] rd_data[28] rd_data[29] rd_data[30] rd_data[31]
+.names $false
+.names $true
+1
+.names $undef
+.names $abc$8517$new_n299_ $abc$8517$new_n303_ inst[2] regfile_write_enable
+000 1
+001 1
+010 1
+011 1
+110 1
+.names $abc$8517$new_n302_ $abc$8517$new_n301_ $abc$8517$new_n300_ $abc$8517$new_n299_
+000 1
+.names inst[1] inst[0] inst[2] inst[4] inst[3] inst[6] $abc$8517$new_n300_
+111100 1
+.names inst[1] inst[0] inst[4] inst[2] inst[3] inst[6] $abc$8517$new_n301_
+111000 1
+.names inst[1] inst[0] inst[2] inst[6] inst[5] inst[4] $abc$8517$new_n302_
+111110 1
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+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names $abc$8517$new_n1016_ bus_address[5] $abc$8517$new_n1035_
+11 1
+.names $abc$8517$new_n1041_ $abc$8517$new_n1037_ $abc$8517$new_n1036_
+00 1
+11 1
+.names $abc$8517$new_n1039_ $abc$8517$new_n1038_ $abc$8517$new_n1037_
+00 1
+.names singlecycle_datapath.program_counter.value[4] $abc$8517$new_n1032_ $abc$8517$new_n1038_
+10 1
+.names $abc$8517$new_n1040_ singlecycle_datapath.program_counter.value[3] singlecycle_datapath.program_counter.value[2] $abc$8517$new_n1022_ $abc$8517$new_n1021_ $abc$8517$new_n1027_ $abc$8517$new_n1039_
+100000 1
+101000 1
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+110000 1
+110001 1
+110010 1
+110100 1
+110110 1
+111000 1
+111001 1
+111010 1
+111011 1
+111100 1
+111101 1
+111110 1
+.names singlecycle_datapath.program_counter.value[4] $abc$8517$new_n347_ inst[24] inst[11] $abc$8517$new_n1040_
+0010 1
+0011 1
+0101 1
+0111 1
+1000 1
+1001 1
+1100 1
+1101 1
+1110 1
+.names singlecycle_datapath.program_counter.value[5] inst[25] $abc$8517$new_n324_ $abc$8517$new_n1041_
+010 1
+100 1
+101 1
+111 1
+.names singlecycle_datapath.program_counter.value[5] singlecycle_datapath.program_counter.value[4] singlecycle_datapath.program_counter.value[3] singlecycle_datapath.program_counter.value[2] $abc$8517$new_n1042_
+0111 1
+1000 1
+1001 1
+1010 1
+1011 1
+1100 1
+1101 1
+1110 1
+.names reset $abc$8517$new_n1044_ $abc$8517$new_n1048_ $abc$8517$new_n999_ $abc$8517$new_n1045_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][6]
+000010 1
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+001101 1
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+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names $abc$8517$new_n1016_ bus_address[6] $abc$8517$new_n1044_
+11 1
+.names $abc$8517$new_n1047_ $abc$8517$new_n1046_ $abc$8517$new_n1041_ $abc$8517$new_n1037_ $abc$8517$new_n1045_
+0010 1
+0100 1
+0101 1
+0110 1
+0111 1
+1000 1
+1001 1
+1011 1
+.names inst[25] singlecycle_datapath.program_counter.value[5] $abc$8517$new_n324_ $abc$8517$new_n1046_
+110 1
+.names singlecycle_datapath.program_counter.value[6] inst[26] $abc$8517$new_n324_ $abc$8517$new_n1047_
+010 1
+100 1
+101 1
+111 1
+.names singlecycle_datapath.program_counter.value[6] singlecycle_datapath.program_counter.value[5] singlecycle_datapath.program_counter.value[4] singlecycle_datapath.program_counter.value[3] singlecycle_datapath.program_counter.value[2] $abc$8517$new_n1048_
+01111 1
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+10101 1
+10110 1
+10111 1
+11000 1
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+11010 1
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+11101 1
+11110 1
+.names reset $abc$8517$new_n1050_ $abc$8517$new_n1054_ $abc$8517$new_n999_ $abc$8517$new_n1016_ bus_address[7] $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][7]
+000011 1
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+001101 1
+001110 1
+001111 1
+010000 1
+010001 1
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+010110 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names $abc$8517$new_n1051_ $abc$8517$new_n1009_ $abc$8517$new_n1010_ $abc$8517$new_n1000_ bus_address[31] $abc$8517$new_n1012_ $abc$8517$new_n1050_
+100001 1
+100011 1
+100101 1
+100111 1
+101001 1
+101011 1
+101101 1
+101111 1
+110000 1
+110001 1
+110010 1
+110011 1
+110101 1
+110110 1
+110111 1
+111001 1
+111011 1
+111100 1
+111101 1
+111111 1
+.names singlecycle_datapath.program_counter.value[7] $abc$8517$new_n699_ $abc$8517$new_n1052_ $abc$8517$new_n1051_
+000 1
+011 1
+101 1
+110 1
+.names $abc$8517$new_n1047_ $abc$8517$new_n1046_ singlecycle_datapath.program_counter.value[6] $abc$8517$new_n1041_ $abc$8517$new_n1038_ $abc$8517$new_n1039_ $abc$8517$new_n1052_
+000000 1
+000001 1
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+000100 1
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+000111 1
+010000 1
+010001 1
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+100000 1
+100001 1
+100010 1
+100011 1
+100100 1
+101000 1
+101001 1
+101010 1
+101011 1
+101100 1
+.names singlecycle_datapath.program_counter.value[7] singlecycle_datapath.program_counter.value[6] singlecycle_datapath.program_counter.value[5] singlecycle_datapath.program_counter.value[4] singlecycle_datapath.program_counter.value[3] singlecycle_datapath.program_counter.value[2] $abc$8517$new_n1054_
+011111 1
+100000 1
+100001 1
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+100111 1
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+101111 1
+110000 1
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+110101 1
+110110 1
+110111 1
+111000 1
+111001 1
+111010 1
+111011 1
+111100 1
+111101 1
+111110 1
+.names reset $abc$8517$new_n1056_ $abc$8517$new_n1060_ $abc$8517$new_n999_ $abc$8517$new_n1057_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][8]
+000010 1
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+001101 1
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+001111 1
+010000 1
+010001 1
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+010110 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names $abc$8517$new_n1016_ bus_address[8] $abc$8517$new_n1056_
+11 1
+.names singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1059_ $abc$8517$new_n1058_ $abc$8517$new_n1057_
+000 1
+011 1
+101 1
+110 1
+.names singlecycle_datapath.program_counter.value[7] $abc$8517$new_n699_ $abc$8517$new_n1052_ $abc$8517$new_n1058_
+000 1
+001 1
+011 1
+101 1
+.names inst[28] $abc$8517$new_n324_ $abc$8517$new_n1059_
+10 1
+.names singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1061_ $abc$8517$new_n1060_
+01 1
+10 1
+.names singlecycle_datapath.program_counter.value[7] singlecycle_datapath.program_counter.value[6] singlecycle_datapath.program_counter.value[5] singlecycle_datapath.program_counter.value[4] singlecycle_datapath.program_counter.value[3] singlecycle_datapath.program_counter.value[2] $abc$8517$new_n1061_
+111111 1
+.names reset $abc$8517$new_n1063_ $abc$8517$new_n1067_ $abc$8517$new_n999_ $abc$8517$new_n1064_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][9]
+000010 1
+000110 1
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+001100 1
+001101 1
+001110 1
+001111 1
+010000 1
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+010010 1
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+010110 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names $abc$8517$new_n1016_ bus_address[9] $abc$8517$new_n1063_
+11 1
+.names $abc$8517$new_n1066_ $abc$8517$new_n1065_ singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1059_ $abc$8517$new_n1058_ $abc$8517$new_n1064_
+00000 1
+00001 1
+00011 1
+00101 1
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+01110 1
+01111 1
+10010 1
+10100 1
+10110 1
+10111 1
+11010 1
+11100 1
+11110 1
+11111 1
+.names inst[29] singlecycle_datapath.program_counter.value[9] $abc$8517$new_n324_ $abc$8517$new_n1065_
+110 1
+.names singlecycle_datapath.program_counter.value[9] $abc$8517$new_n324_ inst[29] $abc$8517$new_n1066_
+000 1
+010 1
+011 1
+.names singlecycle_datapath.program_counter.value[9] singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1061_ $abc$8517$new_n1067_
+011 1
+100 1
+101 1
+110 1
+.names reset $abc$8517$new_n1069_ $abc$8517$new_n1073_ $abc$8517$new_n999_ $abc$8517$new_n1070_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][10]
+000010 1
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+010000 1
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+010110 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names $abc$8517$new_n1016_ bus_address[10] $abc$8517$new_n1069_
+11 1
+.names $abc$8517$new_n1072_ $abc$8517$new_n1066_ $abc$8517$new_n1071_ $abc$8517$new_n1070_
+000 1
+101 1
+110 1
+111 1
+.names $abc$8517$new_n1065_ singlecycle_datapath.program_counter.value[7] $abc$8517$new_n699_ singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1059_ $abc$8517$new_n1052_ $abc$8517$new_n1071_
+000000 1
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+000010 1
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+000100 1
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+001000 1
+001001 1
+001011 1
+001101 1
+010000 1
+010001 1
+010011 1
+010101 1
+011000 1
+011001 1
+.names singlecycle_datapath.program_counter.value[10] inst[30] $abc$8517$new_n324_ $abc$8517$new_n1072_
+010 1
+100 1
+101 1
+111 1
+.names singlecycle_datapath.program_counter.value[10] singlecycle_datapath.program_counter.value[9] singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1061_ $abc$8517$new_n1073_
+0111 1
+1000 1
+1001 1
+1010 1
+1011 1
+1100 1
+1101 1
+1110 1
+.names reset $abc$8517$new_n1075_ $abc$8517$new_n1079_ $abc$8517$new_n999_ $abc$8517$new_n1016_ bus_address[11] $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][11]
+000011 1
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+001111 1
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+010001 1
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+010110 1
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+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names $abc$8517$new_n1076_ $abc$8517$new_n1009_ $abc$8517$new_n1010_ $abc$8517$new_n1000_ bus_address[31] $abc$8517$new_n1012_ $abc$8517$new_n1075_
+000001 1
+000011 1
+000101 1
+000111 1
+001001 1
+001011 1
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+001111 1
+010000 1
+010001 1
+010010 1
+010011 1
+010101 1
+010110 1
+010111 1
+011001 1
+011011 1
+011100 1
+011101 1
+011111 1
+.names singlecycle_datapath.program_counter.value[11] $abc$8517$new_n1077_ $abc$8517$new_n1078_ $abc$8517$new_n1072_ $abc$8517$new_n1066_ $abc$8517$new_n1071_ $abc$8517$new_n1076_
+000100 1
+001000 1
+001001 1
+001010 1
+001011 1
+001100 1
+001101 1
+001110 1
+001111 1
+010000 1
+010001 1
+010010 1
+010011 1
+010101 1
+010110 1
+010111 1
+100000 1
+100001 1
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+100011 1
+100101 1
+100110 1
+100111 1
+110100 1
+111000 1
+111001 1
+111010 1
+111011 1
+111100 1
+111101 1
+111110 1
+111111 1
+.names $abc$8517$new_n390_ $abc$8517$new_n391_ $abc$8517$new_n389_ inst[31] $abc$8517$new_n1077_
+0000 1
+0010 1
+0011 1
+.names singlecycle_datapath.program_counter.value[10] inst[30] $abc$8517$new_n324_ $abc$8517$new_n1078_
+110 1
+.names singlecycle_datapath.program_counter.value[11] singlecycle_datapath.program_counter.value[10] singlecycle_datapath.program_counter.value[9] singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1061_ $abc$8517$new_n1079_
+01111 1
+10000 1
+10001 1
+10010 1
+10011 1
+10100 1
+10101 1
+10110 1
+10111 1
+11000 1
+11001 1
+11010 1
+11011 1
+11100 1
+11101 1
+11110 1
+.names reset $abc$8517$new_n1081_ $abc$8517$new_n1086_ $abc$8517$new_n999_ $abc$8517$new_n1082_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][12]
+000010 1
+000110 1
+001010 1
+001100 1
+001101 1
+001110 1
+001111 1
+010000 1
+010001 1
+010010 1
+010011 1
+010100 1
+010101 1
+010110 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names $abc$8517$new_n1016_ bus_address[12] $abc$8517$new_n1081_
+11 1
+.names singlecycle_datapath.program_counter.value[12] $abc$8517$new_n1084_ $abc$8517$new_n1083_ $abc$8517$new_n1082_
+000 1
+011 1
+101 1
+110 1
+.names singlecycle_datapath.program_counter.value[11] $abc$8517$new_n1077_ $abc$8517$new_n1072_ $abc$8517$new_n1071_ $abc$8517$new_n1066_ $abc$8517$new_n1078_ $abc$8517$new_n1083_
+000001 1
+000011 1
+000101 1
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+001000 1
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+001101 1
+001111 1
+100000 1
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+101111 1
+110001 1
+110011 1
+110101 1
+110111 1
+111000 1
+111001 1
+111011 1
+111101 1
+111111 1
+.names $abc$8517$new_n1085_ $abc$8517$new_n338_ inst[12] $abc$8517$new_n1084_
+000 1
+010 1
+011 1
+.names inst[31] $abc$8517$new_n312_ $abc$8517$new_n1085_
+10 1
+.names singlecycle_datapath.program_counter.value[12] singlecycle_datapath.program_counter.value[11] singlecycle_datapath.program_counter.value[10] singlecycle_datapath.program_counter.value[9] singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1061_ $abc$8517$new_n1086_
+011111 1
+100000 1
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+100011 1
+100100 1
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+100110 1
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+101000 1
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+101101 1
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+110101 1
+110110 1
+110111 1
+111000 1
+111001 1
+111010 1
+111011 1
+111100 1
+111101 1
+111110 1
+.names reset $abc$8517$new_n1091_ $abc$8517$new_n1092_ $abc$8517$new_n999_ $abc$8517$new_n1088_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][13]
+000010 1
+000110 1
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+001100 1
+001101 1
+001110 1
+001111 1
+010000 1
+010001 1
+010010 1
+010011 1
+010100 1
+010101 1
+010110 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1090_ $abc$8517$new_n1089_ $abc$8517$new_n1088_
+001 1
+010 1
+100 1
+111 1
+.names $abc$8517$new_n1084_ singlecycle_datapath.program_counter.value[12] $abc$8517$new_n1083_ $abc$8517$new_n1089_
+000 1
+100 1
+101 1
+110 1
+.names $abc$8517$new_n383_ $abc$8517$new_n1085_ $abc$8517$new_n1090_
+00 1
+.names $abc$8517$new_n1016_ bus_address[13] $abc$8517$new_n1091_
+11 1
+.names singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1093_ $abc$8517$new_n1092_
+01 1
+10 1
+.names singlecycle_datapath.program_counter.value[12] singlecycle_datapath.program_counter.value[11] singlecycle_datapath.program_counter.value[10] singlecycle_datapath.program_counter.value[9] singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1061_ $abc$8517$new_n1093_
+111111 1
+.names reset $abc$8517$new_n1095_ $abc$8517$new_n1098_ $abc$8517$new_n999_ $abc$8517$new_n1096_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][14]
+000010 1
+000110 1
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+001101 1
+001110 1
+001111 1
+010000 1
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+010100 1
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+010110 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names $abc$8517$new_n1016_ bus_address[14] $abc$8517$new_n1095_
+11 1
+.names singlecycle_datapath.program_counter.value[14] $abc$8517$new_n1097_ singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1090_ $abc$8517$new_n1089_ $abc$8517$new_n1096_
+00001 1
+00010 1
+00011 1
+00111 1
+01000 1
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+01101 1
+01110 1
+10000 1
+10100 1
+10101 1
+10110 1
+11001 1
+11010 1
+11011 1
+11111 1
+.names $abc$8517$new_n1085_ $abc$8517$new_n338_ inst[14] $abc$8517$new_n1097_
+000 1
+010 1
+011 1
+.names singlecycle_datapath.program_counter.value[14] singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1093_ $abc$8517$new_n1098_
+011 1
+100 1
+101 1
+110 1
+.names reset $abc$8517$new_n1106_ $abc$8517$new_n1107_ $abc$8517$new_n999_ $abc$8517$new_n1011_ $abc$8517$new_n1100_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][15]
+000000 1
+000100 1
+001000 1
+001100 1
+001101 1
+001110 1
+001111 1
+010000 1
+010001 1
+010010 1
+010011 1
+010100 1
+010101 1
+010110 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names singlecycle_datapath.program_counter.value[15] $abc$8517$new_n1105_ $abc$8517$new_n1101_ $abc$8517$new_n1100_
+000 1
+011 1
+101 1
+110 1
+.names $abc$8517$new_n1104_ $abc$8517$new_n1102_ $abc$8517$new_n1101_
+00 1
+.names $abc$8517$new_n1103_ singlecycle_datapath.program_counter.value[12] singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1084_ $abc$8517$new_n1090_ $abc$8517$new_n1083_ $abc$8517$new_n1102_
+100001 1
+101000 1
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+110000 1
+110001 1
+110101 1
+111000 1
+111001 1
+111010 1
+111011 1
+111100 1
+111101 1
+111111 1
+.names singlecycle_datapath.program_counter.value[14] $abc$8517$new_n1097_ $abc$8517$new_n1103_
+00 1
+11 1
+.names singlecycle_datapath.program_counter.value[14] $abc$8517$new_n1097_ $abc$8517$new_n1104_
+10 1
+.names $abc$8517$new_n378_ $abc$8517$new_n1085_ $abc$8517$new_n1105_
+00 1
+.names $abc$8517$new_n1016_ bus_address[15] $abc$8517$new_n1106_
+11 1
+.names singlecycle_datapath.program_counter.value[15] singlecycle_datapath.program_counter.value[14] singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1093_ $abc$8517$new_n1107_
+0111 1
+1000 1
+1001 1
+1010 1
+1011 1
+1100 1
+1101 1
+1110 1
+.names reset $abc$8517$new_n1109_ $abc$8517$new_n1112_ $abc$8517$new_n999_ $abc$8517$new_n1110_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][16]
+000010 1
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+001110 1
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+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names $abc$8517$new_n1016_ bus_address[16] $abc$8517$new_n1109_
+11 1
+.names singlecycle_datapath.program_counter.value[16] $abc$8517$new_n1111_ singlecycle_datapath.program_counter.value[15] $abc$8517$new_n1105_ $abc$8517$new_n1101_ $abc$8517$new_n1110_
+00001 1
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+00111 1
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+10000 1
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+.names $abc$8517$new_n1085_ $abc$8517$new_n338_ inst[16] $abc$8517$new_n1111_
+000 1
+010 1
+011 1
+.names singlecycle_datapath.program_counter.value[16] singlecycle_datapath.program_counter.value[15] singlecycle_datapath.program_counter.value[14] singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1093_ $abc$8517$new_n1112_
+01111 1
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+10101 1
+10110 1
+10111 1
+11000 1
+11001 1
+11010 1
+11011 1
+11100 1
+11101 1
+11110 1
+.names reset $abc$8517$new_n1114_ $abc$8517$new_n1118_ $abc$8517$new_n999_ bus_address[17] $abc$8517$new_n1016_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][17]
+000011 1
+000111 1
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+010001 1
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+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names $abc$8517$new_n1115_ $abc$8517$new_n1009_ $abc$8517$new_n1010_ $abc$8517$new_n1000_ bus_address[31] $abc$8517$new_n1012_ $abc$8517$new_n1114_
+000001 1
+000011 1
+000101 1
+000111 1
+001001 1
+001011 1
+001101 1
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+010000 1
+010001 1
+010010 1
+010011 1
+010101 1
+010110 1
+010111 1
+011001 1
+011011 1
+011100 1
+011101 1
+011111 1
+.names singlecycle_datapath.program_counter.value[17] $abc$8517$new_n1117_ $abc$8517$new_n1116_ $abc$8517$new_n1115_
+000 1
+011 1
+101 1
+110 1
+.names $abc$8517$new_n1104_ $abc$8517$new_n1102_ singlecycle_datapath.program_counter.value[16] singlecycle_datapath.program_counter.value[15] $abc$8517$new_n1105_ $abc$8517$new_n1111_ $abc$8517$new_n1116_
+000000 1
+000001 1
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+000011 1
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+000110 1
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+010101 1
+010111 1
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+100001 1
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+100011 1
+100101 1
+100111 1
+101011 1
+110001 1
+110010 1
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+110101 1
+110111 1
+111011 1
+.names $abc$8517$new_n320_ $abc$8517$new_n1085_ $abc$8517$new_n1117_
+00 1
+.names singlecycle_datapath.program_counter.value[17] singlecycle_datapath.program_counter.value[16] singlecycle_datapath.program_counter.value[15] singlecycle_datapath.program_counter.value[14] singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1093_ $abc$8517$new_n1118_
+011111 1
+100000 1
+100001 1
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+100101 1
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+100111 1
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+101111 1
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+110101 1
+110110 1
+110111 1
+111000 1
+111001 1
+111010 1
+111011 1
+111100 1
+111101 1
+111110 1
+.names reset $abc$8517$new_n1123_ $abc$8517$new_n1124_ $abc$8517$new_n999_ $abc$8517$new_n1120_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][18]
+000010 1
+000110 1
+001010 1
+001100 1
+001101 1
+001110 1
+001111 1
+010000 1
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+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names singlecycle_datapath.program_counter.value[18] $abc$8517$new_n1122_ $abc$8517$new_n1121_ $abc$8517$new_n1120_
+000 1
+011 1
+101 1
+110 1
+.names singlecycle_datapath.program_counter.value[17] $abc$8517$new_n1117_ $abc$8517$new_n1116_ $abc$8517$new_n1121_
+000 1
+100 1
+101 1
+110 1
+.names $abc$8517$new_n317_ $abc$8517$new_n1085_ $abc$8517$new_n1122_
+00 1
+.names $abc$8517$new_n1016_ bus_address[18] $abc$8517$new_n1123_
+11 1
+.names singlecycle_datapath.program_counter.value[18] $abc$8517$new_n1125_ $abc$8517$new_n1124_
+01 1
+10 1
+.names singlecycle_datapath.program_counter.value[17] singlecycle_datapath.program_counter.value[16] singlecycle_datapath.program_counter.value[15] singlecycle_datapath.program_counter.value[14] singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1093_ $abc$8517$new_n1125_
+111111 1
+.names reset $abc$8517$new_n1129_ $abc$8517$new_n1130_ $abc$8517$new_n999_ $abc$8517$new_n1011_ $abc$8517$new_n1127_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][19]
+000000 1
+000100 1
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+010101 1
+010110 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names singlecycle_datapath.program_counter.value[19] $abc$8517$new_n1128_ singlecycle_datapath.program_counter.value[18] $abc$8517$new_n1122_ $abc$8517$new_n1121_ $abc$8517$new_n1127_
+00001 1
+00100 1
+00101 1
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+01011 1
+01110 1
+10000 1
+10010 1
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+10110 1
+11001 1
+11100 1
+11101 1
+11111 1
+.names $abc$8517$new_n314_ $abc$8517$new_n1085_ $abc$8517$new_n1128_
+00 1
+.names $abc$8517$new_n1016_ bus_address[19] $abc$8517$new_n1129_
+11 1
+.names singlecycle_datapath.program_counter.value[19] singlecycle_datapath.program_counter.value[18] $abc$8517$new_n1125_ $abc$8517$new_n1130_
+011 1
+100 1
+101 1
+110 1
+.names reset $abc$8517$new_n1132_ $abc$8517$new_n1138_ $abc$8517$new_n999_ $abc$8517$new_n1133_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][20]
+000010 1
+000110 1
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+001111 1
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+010110 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names $abc$8517$new_n1016_ bus_address[20] $abc$8517$new_n1132_
+11 1
+.names singlecycle_datapath.program_counter.value[20] $abc$8517$new_n1137_ $abc$8517$new_n1136_ $abc$8517$new_n1134_ $abc$8517$new_n1133_
+0001 1
+0010 1
+0011 1
+0100 1
+1000 1
+1101 1
+1110 1
+1111 1
+.names $abc$8517$new_n1135_ $abc$8517$new_n1117_ singlecycle_datapath.program_counter.value[17] singlecycle_datapath.program_counter.value[18] $abc$8517$new_n1122_ $abc$8517$new_n1116_ $abc$8517$new_n1134_
+000001 1
+000010 1
+000011 1
+000111 1
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+010000 1
+010001 1
+010010 1
+010011 1
+010110 1
+010111 1
+011001 1
+011010 1
+011011 1
+011111 1
+.names singlecycle_datapath.program_counter.value[19] $abc$8517$new_n1128_ $abc$8517$new_n1135_
+10 1
+.names $abc$8517$new_n1128_ singlecycle_datapath.program_counter.value[19] $abc$8517$new_n1136_
+10 1
+.names $abc$8517$new_n334_ $abc$8517$new_n324_ inst[31] $abc$8517$new_n1137_
+000 1
+010 1
+011 1
+.names singlecycle_datapath.program_counter.value[20] singlecycle_datapath.program_counter.value[19] singlecycle_datapath.program_counter.value[18] $abc$8517$new_n1125_ $abc$8517$new_n1138_
+0111 1
+1000 1
+1001 1
+1010 1
+1011 1
+1100 1
+1101 1
+1110 1
+.names reset $abc$8517$new_n1140_ $abc$8517$new_n1143_ $abc$8517$new_n999_ $abc$8517$new_n1141_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][21]
+000000 1
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+001110 1
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+010110 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names $abc$8517$new_n1016_ bus_address[21] $abc$8517$new_n1140_
+11 1
+.names singlecycle_datapath.program_counter.value[21] $abc$8517$new_n1142_ singlecycle_datapath.program_counter.value[20] $abc$8517$new_n1137_ $abc$8517$new_n1136_ $abc$8517$new_n1134_ $abc$8517$new_n1141_
+000000 1
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+011111 1
+100001 1
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+101101 1
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+101111 1
+110000 1
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+111001 1
+111010 1
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+111100 1
+.names $abc$8517$new_n331_ $abc$8517$new_n324_ inst[31] $abc$8517$new_n1142_
+000 1
+010 1
+011 1
+.names singlecycle_datapath.program_counter.value[21] singlecycle_datapath.program_counter.value[20] singlecycle_datapath.program_counter.value[19] singlecycle_datapath.program_counter.value[18] $abc$8517$new_n1125_ $abc$8517$new_n1143_
+01111 1
+10000 1
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+10100 1
+10101 1
+10110 1
+10111 1
+11000 1
+11001 1
+11010 1
+11011 1
+11100 1
+11101 1
+11110 1
+.names $abc$8517$new_n999_ singlecycle_datapath.program_counter.value[22] $abc$8517$new_n1148_ $abc$8517$new_n1145_ $abc$8517$new_n1146_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][22]
+000000 1
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+011000 1
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+011011 1
+011110 1
+100000 1
+100001 1
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+110011 1
+110100 1
+110101 1
+110110 1
+110111 1
+111000 1
+111001 1
+111010 1
+111011 1
+111110 1
+.names reset bus_address[22] $abc$8517$new_n1016_ $abc$8517$new_n1145_
+000 1
+001 1
+010 1
+.names singlecycle_datapath.program_counter.value[22] $abc$8517$new_n414_ $abc$8517$new_n1147_ $abc$8517$new_n1146_
+000 1
+011 1
+101 1
+110 1
+.names singlecycle_datapath.program_counter.value[21] singlecycle_datapath.program_counter.value[20] $abc$8517$new_n1136_ $abc$8517$new_n1134_ $abc$8517$new_n1137_ $abc$8517$new_n1142_ $abc$8517$new_n1147_
+000000 1
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+100000 1
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+110000 1
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+110011 1
+110100 1
+110101 1
+110110 1
+111000 1
+111001 1
+111010 1
+111100 1
+111101 1
+111110 1
+.names singlecycle_datapath.program_counter.value[21] singlecycle_datapath.program_counter.value[20] singlecycle_datapath.program_counter.value[19] singlecycle_datapath.program_counter.value[18] $abc$8517$new_n1125_ $abc$8517$new_n1148_
+11111 1
+.names reset $abc$8517$new_n1152_ $abc$8517$new_n1153_ $abc$8517$new_n999_ $abc$8517$new_n1011_ $abc$8517$new_n1150_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][23]
+000000 1
+000100 1
+001000 1
+001100 1
+001101 1
+001110 1
+001111 1
+010000 1
+010001 1
+010010 1
+010011 1
+010100 1
+010101 1
+010110 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names singlecycle_datapath.program_counter.value[23] $abc$8517$new_n427_ $abc$8517$new_n1151_ $abc$8517$new_n1150_
+000 1
+011 1
+101 1
+110 1
+.names $abc$8517$new_n414_ singlecycle_datapath.program_counter.value[22] $abc$8517$new_n1147_ $abc$8517$new_n1151_
+000 1
+100 1
+101 1
+110 1
+.names $abc$8517$new_n1016_ bus_address[23] $abc$8517$new_n1152_
+11 1
+.names singlecycle_datapath.program_counter.value[23] $abc$8517$new_n1154_ $abc$8517$new_n1153_
+01 1
+10 1
+.names singlecycle_datapath.program_counter.value[22] $abc$8517$new_n1148_ $abc$8517$new_n1154_
+11 1
+.names reset $abc$8517$new_n1158_ $abc$8517$new_n1159_ $abc$8517$new_n999_ $abc$8517$new_n1156_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][24]
+000010 1
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+001110 1
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+010000 1
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+010110 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1157_ singlecycle_datapath.program_counter.value[23] $abc$8517$new_n427_ $abc$8517$new_n1151_ $abc$8517$new_n1156_
+00001 1
+00010 1
+00011 1
+00111 1
+01000 1
+01100 1
+01101 1
+01110 1
+10000 1
+10100 1
+10101 1
+10110 1
+11001 1
+11010 1
+11011 1
+11111 1
+.names $abc$8517$new_n458_ $abc$8517$new_n324_ inst[31] $abc$8517$new_n1157_
+000 1
+010 1
+011 1
+.names $abc$8517$new_n1016_ bus_address[24] $abc$8517$new_n1158_
+11 1
+.names singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1160_ $abc$8517$new_n1159_
+01 1
+10 1
+.names singlecycle_datapath.program_counter.value[23] $abc$8517$new_n1154_ $abc$8517$new_n1160_
+11 1
+.names reset $abc$8517$new_n1168_ $abc$8517$new_n1169_ $abc$8517$new_n999_ $abc$8517$new_n1162_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][25]
+000010 1
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+001010 1
+001100 1
+001101 1
+001110 1
+001111 1
+010000 1
+010001 1
+010010 1
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+010100 1
+010101 1
+010110 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names singlecycle_datapath.program_counter.value[25] $abc$8517$new_n1167_ $abc$8517$new_n1163_ $abc$8517$new_n1162_
+001 1
+010 1
+100 1
+111 1
+.names $abc$8517$new_n1166_ $abc$8517$new_n1164_ $abc$8517$new_n1163_
+00 1
+.names $abc$8517$new_n1165_ singlecycle_datapath.program_counter.value[22] singlecycle_datapath.program_counter.value[23] $abc$8517$new_n414_ $abc$8517$new_n427_ $abc$8517$new_n1147_ $abc$8517$new_n1164_
+100001 1
+101000 1
+101001 1
+101011 1
+101100 1
+101101 1
+110000 1
+110001 1
+110101 1
+111000 1
+111001 1
+111010 1
+111011 1
+111100 1
+111101 1
+111111 1
+.names singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1157_ $abc$8517$new_n1165_
+00 1
+11 1
+.names singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1157_ $abc$8517$new_n1166_
+10 1
+.names $abc$8517$new_n456_ $abc$8517$new_n324_ inst[31] $abc$8517$new_n1167_
+000 1
+010 1
+011 1
+.names $abc$8517$new_n1016_ bus_address[25] $abc$8517$new_n1168_
+11 1
+.names singlecycle_datapath.program_counter.value[25] singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1160_ $abc$8517$new_n1169_
+011 1
+100 1
+101 1
+110 1
+.names reset $abc$8517$new_n1173_ $abc$8517$new_n1174_ $abc$8517$new_n999_ $abc$8517$new_n1171_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][26]
+000010 1
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+001100 1
+001101 1
+001110 1
+001111 1
+010000 1
+010001 1
+010010 1
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+010100 1
+010101 1
+010110 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names singlecycle_datapath.program_counter.value[26] $abc$8517$new_n1172_ singlecycle_datapath.program_counter.value[25] $abc$8517$new_n1167_ $abc$8517$new_n1163_ $abc$8517$new_n1171_
+00001 1
+00010 1
+00011 1
+00111 1
+01000 1
+01100 1
+01101 1
+01110 1
+10000 1
+10100 1
+10101 1
+10110 1
+11001 1
+11010 1
+11011 1
+11111 1
+.names $abc$8517$new_n448_ $abc$8517$new_n324_ inst[31] $abc$8517$new_n1172_
+000 1
+010 1
+011 1
+.names $abc$8517$new_n1016_ bus_address[26] $abc$8517$new_n1173_
+11 1
+.names singlecycle_datapath.program_counter.value[26] singlecycle_datapath.program_counter.value[25] singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1160_ $abc$8517$new_n1174_
+0111 1
+1000 1
+1001 1
+1010 1
+1011 1
+1100 1
+1101 1
+1110 1
+.names reset $abc$8517$new_n1176_ $abc$8517$new_n1180_ $abc$8517$new_n999_ $abc$8517$new_n1177_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][27]
+000000 1
+000100 1
+001000 1
+001100 1
+001101 1
+001110 1
+001111 1
+010000 1
+010001 1
+010010 1
+010011 1
+010100 1
+010101 1
+010110 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names $abc$8517$new_n1016_ bus_address[27] $abc$8517$new_n1176_
+11 1
+.names singlecycle_datapath.program_counter.value[27] $abc$8517$new_n1179_ $abc$8517$new_n1178_ $abc$8517$new_n1177_
+000 1
+011 1
+101 1
+110 1
+.names $abc$8517$new_n1166_ $abc$8517$new_n1164_ singlecycle_datapath.program_counter.value[26] singlecycle_datapath.program_counter.value[25] $abc$8517$new_n1167_ $abc$8517$new_n1172_ $abc$8517$new_n1178_
+000000 1
+000001 1
+000010 1
+000011 1
+000101 1
+000110 1
+000111 1
+001001 1
+001011 1
+001111 1
+010001 1
+010010 1
+010011 1
+010101 1
+010111 1
+011011 1
+100001 1
+100010 1
+100011 1
+100101 1
+100111 1
+101011 1
+110001 1
+110010 1
+110011 1
+110101 1
+110111 1
+111011 1
+.names $abc$8517$new_n446_ $abc$8517$new_n324_ inst[31] $abc$8517$new_n1179_
+000 1
+010 1
+011 1
+.names singlecycle_datapath.program_counter.value[27] singlecycle_datapath.program_counter.value[26] singlecycle_datapath.program_counter.value[25] singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1160_ $abc$8517$new_n1180_
+01111 1
+10000 1
+10001 1
+10010 1
+10011 1
+10100 1
+10101 1
+10110 1
+10111 1
+11000 1
+11001 1
+11010 1
+11011 1
+11100 1
+11101 1
+11110 1
+.names reset $abc$8517$new_n1182_ $abc$8517$new_n1185_ $abc$8517$new_n999_ bus_address[28] $abc$8517$new_n1016_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][28]
+000011 1
+000111 1
+001011 1
+001100 1
+001101 1
+001110 1
+001111 1
+010000 1
+010001 1
+010010 1
+010011 1
+010100 1
+010101 1
+010110 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names $abc$8517$new_n1183_ $abc$8517$new_n1009_ $abc$8517$new_n1010_ $abc$8517$new_n1000_ bus_address[31] $abc$8517$new_n1012_ $abc$8517$new_n1182_
+100001 1
+100011 1
+100101 1
+100111 1
+101001 1
+101011 1
+101101 1
+101111 1
+110000 1
+110001 1
+110010 1
+110011 1
+110101 1
+110110 1
+110111 1
+111001 1
+111011 1
+111100 1
+111101 1
+111111 1
+.names singlecycle_datapath.program_counter.value[28] $abc$8517$new_n1184_ singlecycle_datapath.program_counter.value[27] $abc$8517$new_n1179_ $abc$8517$new_n1178_ $abc$8517$new_n1183_
+00001 1
+00010 1
+00011 1
+00111 1
+01000 1
+01100 1
+01101 1
+01110 1
+10000 1
+10100 1
+10101 1
+10110 1
+11001 1
+11010 1
+11011 1
+11111 1
+.names $abc$8517$new_n439_ $abc$8517$new_n324_ inst[31] $abc$8517$new_n1184_
+000 1
+010 1
+011 1
+.names singlecycle_datapath.program_counter.value[28] singlecycle_datapath.program_counter.value[27] singlecycle_datapath.program_counter.value[26] singlecycle_datapath.program_counter.value[25] singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1160_ $abc$8517$new_n1185_
+011111 1
+100000 1
+100001 1
+100010 1
+100011 1
+100100 1
+100101 1
+100110 1
+100111 1
+101000 1
+101001 1
+101010 1
+101011 1
+101100 1
+101101 1
+101110 1
+101111 1
+110000 1
+110001 1
+110010 1
+110011 1
+110100 1
+110101 1
+110110 1
+110111 1
+111000 1
+111001 1
+111010 1
+111011 1
+111100 1
+111101 1
+111110 1
+.names reset $abc$8517$new_n1190_ $abc$8517$new_n1191_ $abc$8517$new_n999_ $abc$8517$new_n1011_ $abc$8517$new_n1187_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][29]
+000000 1
+000100 1
+001000 1
+001100 1
+001101 1
+001110 1
+001111 1
+010000 1
+010001 1
+010010 1
+010011 1
+010100 1
+010101 1
+010110 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names singlecycle_datapath.program_counter.value[29] $abc$8517$new_n1189_ $abc$8517$new_n1188_ $abc$8517$new_n1187_
+000 1
+011 1
+101 1
+110 1
+.names $abc$8517$new_n1179_ singlecycle_datapath.program_counter.value[27] singlecycle_datapath.program_counter.value[28] $abc$8517$new_n1184_ $abc$8517$new_n1178_ $abc$8517$new_n1188_
+00001 1
+00010 1
+00011 1
+00111 1
+01010 1
+01011 1
+10000 1
+10001 1
+10010 1
+10011 1
+10110 1
+10111 1
+11001 1
+11010 1
+11011 1
+11111 1
+.names inst[31] $abc$8517$new_n324_ $abc$8517$new_n300_ inst[29] $abc$8517$new_n1189_
+0000 1
+0001 1
+0010 1
+0100 1
+0101 1
+0110 1
+1100 1
+1101 1
+1110 1
+.names $abc$8517$new_n1016_ bus_address[29] $abc$8517$new_n1190_
+11 1
+.names singlecycle_datapath.program_counter.value[29] $abc$8517$new_n1192_ $abc$8517$new_n1191_
+01 1
+10 1
+.names singlecycle_datapath.program_counter.value[28] singlecycle_datapath.program_counter.value[27] singlecycle_datapath.program_counter.value[26] singlecycle_datapath.program_counter.value[25] singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1160_ $abc$8517$new_n1192_
+111111 1
+.names reset $abc$8517$new_n1194_ $abc$8517$new_n1197_ $abc$8517$new_n999_ $abc$8517$new_n1195_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][30]
+000010 1
+000110 1
+001010 1
+001100 1
+001101 1
+001110 1
+001111 1
+010000 1
+010001 1
+010010 1
+010011 1
+010100 1
+010101 1
+010110 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011110 1
+011111 1
+.names $abc$8517$new_n1016_ bus_address[30] $abc$8517$new_n1194_
+11 1
+.names singlecycle_datapath.program_counter.value[30] $abc$8517$new_n1196_ singlecycle_datapath.program_counter.value[29] $abc$8517$new_n1189_ $abc$8517$new_n1188_ $abc$8517$new_n1195_
+00001 1
+00010 1
+00011 1
+00111 1
+01000 1
+01100 1
+01101 1
+01110 1
+10000 1
+10100 1
+10101 1
+10110 1
+11001 1
+11010 1
+11011 1
+11111 1
+.names inst[31] $abc$8517$new_n324_ $abc$8517$new_n300_ inst[30] $abc$8517$new_n1196_
+0000 1
+0001 1
+0010 1
+0100 1
+0101 1
+0110 1
+1100 1
+1101 1
+1110 1
+.names singlecycle_datapath.program_counter.value[30] singlecycle_datapath.program_counter.value[29] $abc$8517$new_n1192_ $abc$8517$new_n1197_
+011 1
+100 1
+101 1
+110 1
+.names reset $abc$8517$new_n999_ singlecycle_datapath.program_counter.value[31] $abc$8517$new_n1203_ $abc$8517$new_n1199_ $abc$8517$new_n1202_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][31]
+000001 1
+000010 1
+000011 1
+000101 1
+000110 1
+000111 1
+001001 1
+001010 1
+001011 1
+001101 1
+001110 1
+001111 1
+010001 1
+010010 1
+010011 1
+010100 1
+010101 1
+010110 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011101 1
+011110 1
+011111 1
+.names $abc$8517$new_n1200_ $abc$8517$new_n1009_ $abc$8517$new_n1010_ $abc$8517$new_n1000_ bus_address[31] $abc$8517$new_n1012_ $abc$8517$new_n1199_
+000001 1
+000011 1
+000101 1
+000111 1
+001001 1
+001011 1
+001101 1
+001111 1
+010000 1
+010001 1
+010010 1
+010011 1
+010101 1
+010110 1
+010111 1
+011001 1
+011011 1
+011100 1
+011101 1
+011111 1
+.names $abc$8517$new_n1201_ $abc$8517$new_n1189_ singlecycle_datapath.program_counter.value[29] singlecycle_datapath.program_counter.value[30] $abc$8517$new_n1196_ $abc$8517$new_n1188_ $abc$8517$new_n1200_
+000001 1
+000010 1
+000011 1
+000111 1
+001010 1
+001011 1
+010000 1
+010001 1
+010010 1
+010011 1
+010110 1
+010111 1
+011001 1
+011010 1
+011011 1
+011111 1
+100000 1
+100100 1
+100101 1
+100110 1
+101000 1
+101001 1
+101100 1
+101101 1
+101110 1
+101111 1
+110100 1
+110101 1
+111000 1
+111100 1
+111101 1
+111110 1
+.names singlecycle_datapath.program_counter.value[31] $abc$8517$new_n494_ $abc$8517$new_n1201_
+00 1
+11 1
+.names $abc$8517$new_n1016_ bus_address[31] $abc$8517$new_n1202_
+11 1
+.names singlecycle_datapath.program_counter.value[30] singlecycle_datapath.program_counter.value[29] $abc$8517$new_n1192_ $abc$8517$new_n1203_
+111 1
+.names $abc$8517$new_n1005_ inst[13] inst[12] bus_byte_enable[0]
+100 1
+101 1
+110 1
+.names inst[12] bus_address[1] inst[13] bus_address[0] bus_byte_enable[1]
+0001 1
+0010 1
+0011 1
+1000 1
+1001 1
+.names inst[13] inst[12] bus_address[0] bus_address[1] bus_byte_enable[2]
+0001 1
+0101 1
+0110 1
+1000 1
+1001 1
+1010 1
+.names inst[12] bus_address[1] inst[13] bus_address[0] bus_byte_enable[3]
+0010 1
+0011 1
+0101 1
+0110 1
+0111 1
+1100 1
+1101 1
+.names $abc$8517$new_n299_ $abc$8517$new_n1209_ bus_address[0] $abc$8517$new_n1210_ singlecycle_datapath.program_counter.value[0] $abc$8517$new_n302_ rd_data[0]
+000011 1
+000111 1
+001000 1
+001001 1
+001010 1
+001011 1
+001111 1
+010011 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011111 1
+100000 1
+100001 1
+100010 1
+100011 1
+100100 1
+100101 1
+100110 1
+100111 1
+101000 1
+101001 1
+101010 1
+101011 1
+101100 1
+101101 1
+101110 1
+101111 1
+110011 1
+110111 1
+111000 1
+111001 1
+111010 1
+111011 1
+111111 1
+.names bus_address[1] bus_address[0] bus_read_data[24] bus_read_data[8] bus_read_data[16] bus_read_data[0] $abc$8517$new_n1209_
+000000 1
+000010 1
+000100 1
+000110 1
+001000 1
+001010 1
+001100 1
+001110 1
+010000 1
+010001 1
+010010 1
+010011 1
+011000 1
+011001 1
+011010 1
+011011 1
+100000 1
+100001 1
+100100 1
+100101 1
+101000 1
+101001 1
+101100 1
+101101 1
+110000 1
+110001 1
+110010 1
+110011 1
+110100 1
+110101 1
+110110 1
+110111 1
+.names $abc$8517$new_n301_ $abc$8517$new_n300_ inst[5] $abc$8517$new_n1210_
+000 1
+001 1
+011 1
+.names $abc$8517$new_n299_ $abc$8517$new_n1212_ bus_address[1] $abc$8517$new_n1210_ singlecycle_datapath.program_counter.value[1] $abc$8517$new_n302_ rd_data[1]
+000011 1
+000111 1
+001000 1
+001001 1
+001010 1
+001011 1
+001111 1
+010011 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011111 1
+100000 1
+100001 1
+100010 1
+100011 1
+100100 1
+100101 1
+100110 1
+100111 1
+101000 1
+101001 1
+101010 1
+101011 1
+101100 1
+101101 1
+101110 1
+101111 1
+110011 1
+110111 1
+111000 1
+111001 1
+111010 1
+111011 1
+111111 1
+.names bus_address[1] bus_address[0] bus_read_data[25] bus_read_data[9] bus_read_data[17] bus_read_data[1] $abc$8517$new_n1212_
+000000 1
+000010 1
+000100 1
+000110 1
+001000 1
+001010 1
+001100 1
+001110 1
+010000 1
+010001 1
+010010 1
+010011 1
+011000 1
+011001 1
+011010 1
+011011 1
+100000 1
+100001 1
+100100 1
+100101 1
+101000 1
+101001 1
+101100 1
+101101 1
+110000 1
+110001 1
+110010 1
+110011 1
+110100 1
+110101 1
+110110 1
+110111 1
+.names $abc$8517$new_n299_ $abc$8517$new_n1214_ bus_address[2] $abc$8517$new_n1210_ $abc$8517$new_n302_ singlecycle_datapath.program_counter.value[2] rd_data[2]
+000010 1
+000110 1
+001000 1
+001001 1
+001010 1
+001011 1
+001110 1
+010010 1
+010110 1
+011000 1
+011001 1
+011010 1
+011011 1
+011110 1
+100000 1
+100001 1
+100010 1
+100011 1
+100100 1
+100101 1
+100110 1
+100111 1
+101000 1
+101001 1
+101010 1
+101011 1
+101100 1
+101101 1
+101110 1
+101111 1
+110010 1
+110110 1
+111000 1
+111001 1
+111010 1
+111011 1
+111110 1
+.names bus_address[1] bus_address[0] bus_read_data[26] bus_read_data[10] bus_read_data[18] bus_read_data[2] $abc$8517$new_n1214_
+000000 1
+000010 1
+000100 1
+000110 1
+001000 1
+001010 1
+001100 1
+001110 1
+010000 1
+010001 1
+010010 1
+010011 1
+011000 1
+011001 1
+011010 1
+011011 1
+100000 1
+100001 1
+100100 1
+100101 1
+101000 1
+101001 1
+101100 1
+101101 1
+110000 1
+110001 1
+110010 1
+110011 1
+110100 1
+110101 1
+110110 1
+110111 1
+.names $abc$8517$new_n299_ $abc$8517$new_n1216_ bus_address[3] $abc$8517$new_n1210_ $abc$8517$new_n1028_ $abc$8517$new_n302_ rd_data[3]
+000011 1
+000111 1
+001000 1
+001001 1
+001010 1
+001011 1
+001111 1
+010011 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011111 1
+100000 1
+100001 1
+100010 1
+100011 1
+100100 1
+100101 1
+100110 1
+100111 1
+101000 1
+101001 1
+101010 1
+101011 1
+101100 1
+101101 1
+101110 1
+101111 1
+110011 1
+110111 1
+111000 1
+111001 1
+111010 1
+111011 1
+111111 1
+.names bus_address[1] bus_address[0] bus_read_data[27] bus_read_data[11] bus_read_data[19] bus_read_data[3] $abc$8517$new_n1216_
+000000 1
+000010 1
+000100 1
+000110 1
+001000 1
+001010 1
+001100 1
+001110 1
+010000 1
+010001 1
+010010 1
+010011 1
+011000 1
+011001 1
+011010 1
+011011 1
+100000 1
+100001 1
+100100 1
+100101 1
+101000 1
+101001 1
+101100 1
+101101 1
+110000 1
+110001 1
+110010 1
+110011 1
+110100 1
+110101 1
+110110 1
+110111 1
+.names $abc$8517$new_n299_ $abc$8517$new_n1218_ bus_address[4] $abc$8517$new_n1210_ $abc$8517$new_n1033_ $abc$8517$new_n302_ rd_data[4]
+000011 1
+000111 1
+001000 1
+001001 1
+001010 1
+001011 1
+001111 1
+010011 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011111 1
+100000 1
+100001 1
+100010 1
+100011 1
+100100 1
+100101 1
+100110 1
+100111 1
+101000 1
+101001 1
+101010 1
+101011 1
+101100 1
+101101 1
+101110 1
+101111 1
+110011 1
+110111 1
+111000 1
+111001 1
+111010 1
+111011 1
+111111 1
+.names bus_address[1] bus_address[0] bus_read_data[28] bus_read_data[12] bus_read_data[20] bus_read_data[4] $abc$8517$new_n1218_
+000000 1
+000010 1
+000100 1
+000110 1
+001000 1
+001010 1
+001100 1
+001110 1
+010000 1
+010001 1
+010010 1
+010011 1
+011000 1
+011001 1
+011010 1
+011011 1
+100000 1
+100001 1
+100100 1
+100101 1
+101000 1
+101001 1
+101100 1
+101101 1
+110000 1
+110001 1
+110010 1
+110011 1
+110100 1
+110101 1
+110110 1
+110111 1
+.names $abc$8517$new_n299_ $abc$8517$new_n1220_ bus_address[5] $abc$8517$new_n1210_ $abc$8517$new_n1042_ $abc$8517$new_n302_ rd_data[5]
+000011 1
+000111 1
+001000 1
+001001 1
+001010 1
+001011 1
+001111 1
+010011 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011111 1
+100000 1
+100001 1
+100010 1
+100011 1
+100100 1
+100101 1
+100110 1
+100111 1
+101000 1
+101001 1
+101010 1
+101011 1
+101100 1
+101101 1
+101110 1
+101111 1
+110011 1
+110111 1
+111000 1
+111001 1
+111010 1
+111011 1
+111111 1
+.names bus_address[1] bus_address[0] bus_read_data[29] bus_read_data[13] bus_read_data[21] bus_read_data[5] $abc$8517$new_n1220_
+000000 1
+000010 1
+000100 1
+000110 1
+001000 1
+001010 1
+001100 1
+001110 1
+010000 1
+010001 1
+010010 1
+010011 1
+011000 1
+011001 1
+011010 1
+011011 1
+100000 1
+100001 1
+100100 1
+100101 1
+101000 1
+101001 1
+101100 1
+101101 1
+110000 1
+110001 1
+110010 1
+110011 1
+110100 1
+110101 1
+110110 1
+110111 1
+.names $abc$8517$new_n299_ $abc$8517$new_n1222_ bus_address[6] $abc$8517$new_n1210_ $abc$8517$new_n1048_ $abc$8517$new_n302_ rd_data[6]
+000011 1
+000111 1
+001000 1
+001001 1
+001010 1
+001011 1
+001111 1
+010011 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011111 1
+100000 1
+100001 1
+100010 1
+100011 1
+100100 1
+100101 1
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+100111 1
+101000 1
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+101011 1
+101100 1
+101101 1
+101110 1
+101111 1
+110011 1
+110111 1
+111000 1
+111001 1
+111010 1
+111011 1
+111111 1
+.names bus_address[1] bus_address[0] bus_read_data[30] bus_read_data[14] bus_read_data[22] bus_read_data[6] $abc$8517$new_n1222_
+000000 1
+000010 1
+000100 1
+000110 1
+001000 1
+001010 1
+001100 1
+001110 1
+010000 1
+010001 1
+010010 1
+010011 1
+011000 1
+011001 1
+011010 1
+011011 1
+100000 1
+100001 1
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+100101 1
+101000 1
+101001 1
+101100 1
+101101 1
+110000 1
+110001 1
+110010 1
+110011 1
+110100 1
+110101 1
+110110 1
+110111 1
+.names $abc$8517$new_n299_ $abc$8517$new_n1224_ bus_address[7] $abc$8517$new_n1210_ $abc$8517$new_n1054_ $abc$8517$new_n302_ rd_data[7]
+000011 1
+000111 1
+001000 1
+001001 1
+001010 1
+001011 1
+001111 1
+010011 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011111 1
+100000 1
+100001 1
+100010 1
+100011 1
+100100 1
+100101 1
+100110 1
+100111 1
+101000 1
+101001 1
+101010 1
+101011 1
+101100 1
+101101 1
+101110 1
+101111 1
+110011 1
+110111 1
+111000 1
+111001 1
+111010 1
+111011 1
+111111 1
+.names bus_address[1] bus_address[0] bus_read_data[31] bus_read_data[15] bus_read_data[23] bus_read_data[7] $abc$8517$new_n1224_
+000000 1
+000010 1
+000100 1
+000110 1
+001000 1
+001010 1
+001100 1
+001110 1
+010000 1
+010001 1
+010010 1
+010011 1
+011000 1
+011001 1
+011010 1
+011011 1
+100000 1
+100001 1
+100100 1
+100101 1
+101000 1
+101001 1
+101100 1
+101101 1
+110000 1
+110001 1
+110010 1
+110011 1
+110100 1
+110101 1
+110110 1
+110111 1
+.names $abc$8517$new_n1226_ $abc$8517$new_n1210_ bus_address[8] $abc$8517$new_n1060_ $abc$8517$new_n302_ rd_data[8]
+00011 1
+00100 1
+00101 1
+00110 1
+00111 1
+01011 1
+01111 1
+10000 1
+10001 1
+10010 1
+10011 1
+10100 1
+10101 1
+10110 1
+10111 1
+11000 1
+11001 1
+11010 1
+11011 1
+11100 1
+11101 1
+11110 1
+11111 1
+.names $abc$8517$new_n299_ inst[12] inst[13] $abc$8517$new_n1228_ $abc$8517$new_n1227_ $abc$8517$new_n1226_
+10001 1
+10011 1
+10100 1
+10101 1
+10111 1
+11000 1
+11001 1
+11011 1
+11101 1
+11111 1
+.names inst[13] inst[12] inst[14] $abc$8517$new_n1224_ $abc$8517$new_n1227_
+0000 1
+1100 1
+.names bus_address[1] bus_address[0] bus_read_data[16] bus_read_data[24] bus_read_data[8] $abc$8517$new_n1228_
+00000 1
+00010 1
+00100 1
+00110 1
+01000 1
+01001 1
+01010 1
+01011 1
+10000 1
+10001 1
+10100 1
+10101 1
+11000 1
+11001 1
+11010 1
+11011 1
+11100 1
+11101 1
+11110 1
+11111 1
+.names $abc$8517$new_n1230_ $abc$8517$new_n1210_ bus_address[9] $abc$8517$new_n1067_ $abc$8517$new_n302_ rd_data[9]
+00011 1
+00100 1
+00101 1
+00110 1
+00111 1
+01011 1
+01111 1
+10000 1
+10001 1
+10010 1
+10011 1
+10100 1
+10101 1
+10110 1
+10111 1
+11000 1
+11001 1
+11010 1
+11011 1
+11100 1
+11101 1
+11110 1
+11111 1
+.names $abc$8517$new_n299_ inst[12] inst[13] $abc$8517$new_n1231_ $abc$8517$new_n1227_ $abc$8517$new_n1230_
+10001 1
+10011 1
+10100 1
+10101 1
+10111 1
+11000 1
+11001 1
+11011 1
+11101 1
+11111 1
+.names bus_address[1] bus_address[0] bus_read_data[17] bus_read_data[25] bus_read_data[9] $abc$8517$new_n1231_
+00000 1
+00010 1
+00100 1
+00110 1
+01000 1
+01001 1
+01010 1
+01011 1
+10000 1
+10001 1
+10100 1
+10101 1
+11000 1
+11001 1
+11010 1
+11011 1
+11100 1
+11101 1
+11110 1
+11111 1
+.names $abc$8517$new_n1233_ $abc$8517$new_n1210_ bus_address[10] $abc$8517$new_n1073_ $abc$8517$new_n302_ rd_data[10]
+00011 1
+00100 1
+00101 1
+00110 1
+00111 1
+01011 1
+01111 1
+10000 1
+10001 1
+10010 1
+10011 1
+10100 1
+10101 1
+10110 1
+10111 1
+11000 1
+11001 1
+11010 1
+11011 1
+11100 1
+11101 1
+11110 1
+11111 1
+.names $abc$8517$new_n299_ inst[12] inst[13] $abc$8517$new_n1234_ $abc$8517$new_n1227_ $abc$8517$new_n1233_
+10001 1
+10011 1
+10100 1
+10101 1
+10111 1
+11000 1
+11001 1
+11011 1
+11101 1
+11111 1
+.names bus_address[1] bus_address[0] bus_read_data[18] bus_read_data[26] bus_read_data[10] $abc$8517$new_n1234_
+00000 1
+00010 1
+00100 1
+00110 1
+01000 1
+01001 1
+01010 1
+01011 1
+10000 1
+10001 1
+10100 1
+10101 1
+11000 1
+11001 1
+11010 1
+11011 1
+11100 1
+11101 1
+11110 1
+11111 1
+.names $abc$8517$new_n1236_ $abc$8517$new_n1210_ bus_address[11] $abc$8517$new_n1079_ $abc$8517$new_n302_ rd_data[11]
+00011 1
+00100 1
+00101 1
+00110 1
+00111 1
+01011 1
+01111 1
+10000 1
+10001 1
+10010 1
+10011 1
+10100 1
+10101 1
+10110 1
+10111 1
+11000 1
+11001 1
+11010 1
+11011 1
+11100 1
+11101 1
+11110 1
+11111 1
+.names $abc$8517$new_n299_ inst[12] inst[13] $abc$8517$new_n1237_ $abc$8517$new_n1227_ $abc$8517$new_n1236_
+10001 1
+10011 1
+10100 1
+10101 1
+10111 1
+11000 1
+11001 1
+11011 1
+11101 1
+11111 1
+.names bus_address[1] bus_address[0] bus_read_data[19] bus_read_data[27] bus_read_data[11] $abc$8517$new_n1237_
+00000 1
+00010 1
+00100 1
+00110 1
+01000 1
+01001 1
+01010 1
+01011 1
+10000 1
+10001 1
+10100 1
+10101 1
+11000 1
+11001 1
+11010 1
+11011 1
+11100 1
+11101 1
+11110 1
+11111 1
+.names $abc$8517$new_n1239_ $abc$8517$new_n302_ $abc$8517$new_n1086_ rd_data[12]
+000 1
+001 1
+010 1
+011 1
+111 1
+.names $abc$8517$new_n1241_ $abc$8517$new_n1227_ inst[12] inst[13] $abc$8517$new_n299_ $abc$8517$new_n1240_ $abc$8517$new_n1239_
+100000 1
+100001 1
+100010 1
+100011 1
+100100 1
+100101 1
+100111 1
+101000 1
+101001 1
+101011 1
+101100 1
+101101 1
+101110 1
+101111 1
+110000 1
+110001 1
+110100 1
+110101 1
+111000 1
+111001 1
+111100 1
+111101 1
+.names bus_address[1] bus_address[0] bus_read_data[20] bus_read_data[28] bus_read_data[12] $abc$8517$new_n1240_
+00000 1
+00010 1
+00100 1
+00110 1
+01000 1
+01001 1
+01010 1
+01011 1
+10000 1
+10001 1
+10100 1
+10101 1
+11000 1
+11001 1
+11010 1
+11011 1
+11100 1
+11101 1
+11110 1
+11111 1
+.names $abc$8517$new_n1210_ bus_address[12] $abc$8517$new_n300_ $abc$8517$new_n1084_ $abc$8517$new_n1241_
+0000 1
+0001 1
+0010 1
+0011 1
+1000 1
+1001 1
+1011 1
+1100 1
+1101 1
+1111 1
+.names $abc$8517$new_n1243_ bus_address[13] $abc$8517$new_n1210_ rd_data[13]
+000 1
+001 1
+010 1
+011 1
+110 1
+.names $abc$8517$new_n1245_ $abc$8517$new_n1227_ inst[12] inst[13] $abc$8517$new_n299_ $abc$8517$new_n1244_ $abc$8517$new_n1243_
+100000 1
+100001 1
+100010 1
+100011 1
+100100 1
+100101 1
+100111 1
+101000 1
+101001 1
+101011 1
+101100 1
+101101 1
+101110 1
+101111 1
+110000 1
+110001 1
+110100 1
+110101 1
+111000 1
+111001 1
+111100 1
+111101 1
+.names bus_address[1] bus_address[0] bus_read_data[21] bus_read_data[29] bus_read_data[13] $abc$8517$new_n1244_
+00000 1
+00010 1
+00100 1
+00110 1
+01000 1
+01001 1
+01010 1
+01011 1
+10000 1
+10001 1
+10100 1
+10101 1
+11000 1
+11001 1
+11010 1
+11011 1
+11100 1
+11101 1
+11110 1
+11111 1
+.names $abc$8517$new_n1092_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1090_ $abc$8517$new_n1245_
+00000 1
+00001 1
+00010 1
+00011 1
+00100 1
+00101 1
+00111 1
+01000 1
+01001 1
+01010 1
+01011 1
+01100 1
+01101 1
+01111 1
+10000 1
+10001 1
+10010 1
+10011 1
+10100 1
+10101 1
+10111 1
+.names $abc$8517$new_n1247_ bus_address[14] $abc$8517$new_n1210_ rd_data[14]
+000 1
+001 1
+010 1
+011 1
+110 1
+.names $abc$8517$new_n1249_ $abc$8517$new_n1227_ inst[12] inst[13] $abc$8517$new_n299_ $abc$8517$new_n1248_ $abc$8517$new_n1247_
+100000 1
+100001 1
+100010 1
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+100111 1
+101000 1
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+101011 1
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+101101 1
+101110 1
+101111 1
+110000 1
+110001 1
+110100 1
+110101 1
+111000 1
+111001 1
+111100 1
+111101 1
+.names bus_address[1] bus_address[0] bus_read_data[22] bus_read_data[30] bus_read_data[14] $abc$8517$new_n1248_
+00000 1
+00010 1
+00100 1
+00110 1
+01000 1
+01001 1
+01010 1
+01011 1
+10000 1
+10001 1
+10100 1
+10101 1
+11000 1
+11001 1
+11010 1
+11011 1
+11100 1
+11101 1
+11110 1
+11111 1
+.names $abc$8517$new_n1098_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1097_ $abc$8517$new_n1249_
+00000 1
+00001 1
+00010 1
+00011 1
+00100 1
+00101 1
+00111 1
+01000 1
+01001 1
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+01100 1
+01101 1
+01111 1
+10000 1
+10001 1
+10010 1
+10011 1
+10100 1
+10101 1
+10111 1
+.names $abc$8517$new_n1251_ bus_address[15] $abc$8517$new_n1210_ rd_data[15]
+000 1
+001 1
+010 1
+011 1
+110 1
+.names $abc$8517$new_n1253_ $abc$8517$new_n1227_ inst[12] inst[13] $abc$8517$new_n299_ $abc$8517$new_n1252_ $abc$8517$new_n1251_
+100000 1
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+101110 1
+101111 1
+110000 1
+110001 1
+110100 1
+110101 1
+111000 1
+111001 1
+111100 1
+111101 1
+.names bus_address[1] bus_address[0] bus_read_data[23] bus_read_data[31] bus_read_data[15] $abc$8517$new_n1252_
+00000 1
+00010 1
+00100 1
+00110 1
+01000 1
+01001 1
+01010 1
+01011 1
+10000 1
+10001 1
+10100 1
+10101 1
+11000 1
+11001 1
+11010 1
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+11100 1
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+11110 1
+11111 1
+.names $abc$8517$new_n1107_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1105_ $abc$8517$new_n1253_
+00000 1
+00001 1
+00010 1
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+00101 1
+00111 1
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+01101 1
+01111 1
+10000 1
+10001 1
+10010 1
+10011 1
+10100 1
+10101 1
+10111 1
+.names $abc$8517$new_n1255_ bus_address[16] $abc$8517$new_n1210_ rd_data[16]
+000 1
+001 1
+010 1
+011 1
+110 1
+.names $abc$8517$new_n1256_ $abc$8517$new_n302_ $abc$8517$new_n1112_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1111_ $abc$8517$new_n1255_
+000000 1
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+000010 1
+000011 1
+000100 1
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+000111 1
+001000 1
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+001101 1
+001111 1
+010000 1
+010001 1
+010010 1
+010011 1
+010100 1
+010101 1
+010111 1
+.names $abc$8517$new_n299_ $abc$8517$new_n1258_ bus_address[0] $abc$8517$new_n1257_ bus_read_data[24] bus_read_data[16] $abc$8517$new_n1256_
+100000 1
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+110011 1
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+110111 1
+111000 1
+111001 1
+111010 1
+111011 1
+111110 1
+111111 1
+.names inst[12] inst[13] inst[14] $abc$8517$new_n1224_ $abc$8517$new_n1252_ $abc$8517$new_n1257_
+00010 1
+00011 1
+00100 1
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+00111 1
+01000 1
+01001 1
+01010 1
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+10100 1
+10101 1
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+10111 1
+11010 1
+11011 1
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+11110 1
+11111 1
+.names inst[13] inst[12] bus_address[1] $abc$8517$new_n1258_
+100 1
+.names $abc$8517$new_n1260_ $abc$8517$new_n302_ $abc$8517$new_n1118_ rd_data[17]
+000 1
+001 1
+010 1
+011 1
+111 1
+.names $abc$8517$new_n1261_ bus_address[17] $abc$8517$new_n1210_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1117_ $abc$8517$new_n1260_
+000000 1
+000001 1
+000010 1
+000011 1
+000100 1
+000101 1
+000111 1
+001000 1
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+001101 1
+001111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011111 1
+.names $abc$8517$new_n299_ $abc$8517$new_n1258_ bus_address[0] $abc$8517$new_n1257_ bus_read_data[25] bus_read_data[17] $abc$8517$new_n1261_
+100000 1
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+110111 1
+111000 1
+111001 1
+111010 1
+111011 1
+111110 1
+111111 1
+.names $abc$8517$new_n1263_ bus_address[18] $abc$8517$new_n1210_ rd_data[18]
+000 1
+001 1
+010 1
+011 1
+110 1
+.names $abc$8517$new_n1264_ $abc$8517$new_n302_ $abc$8517$new_n1124_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1122_ $abc$8517$new_n1263_
+000000 1
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+000010 1
+000011 1
+000100 1
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+000111 1
+001000 1
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+001100 1
+001101 1
+001111 1
+010000 1
+010001 1
+010010 1
+010011 1
+010100 1
+010101 1
+010111 1
+.names $abc$8517$new_n299_ $abc$8517$new_n1258_ bus_address[0] $abc$8517$new_n1257_ bus_read_data[26] bus_read_data[18] $abc$8517$new_n1264_
+100000 1
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+101001 1
+101010 1
+101011 1
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+110001 1
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+110011 1
+110101 1
+110111 1
+111000 1
+111001 1
+111010 1
+111011 1
+111110 1
+111111 1
+.names $abc$8517$new_n1266_ bus_address[19] $abc$8517$new_n1210_ rd_data[19]
+000 1
+001 1
+010 1
+011 1
+110 1
+.names $abc$8517$new_n1267_ $abc$8517$new_n302_ $abc$8517$new_n1130_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1128_ $abc$8517$new_n1266_
+000000 1
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+000100 1
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+001000 1
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+001101 1
+001111 1
+010000 1
+010001 1
+010010 1
+010011 1
+010100 1
+010101 1
+010111 1
+.names $abc$8517$new_n299_ $abc$8517$new_n1258_ bus_address[0] $abc$8517$new_n1257_ bus_read_data[27] bus_read_data[19] $abc$8517$new_n1267_
+100000 1
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+101000 1
+101001 1
+101010 1
+101011 1
+110000 1
+110001 1
+110010 1
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+110111 1
+111000 1
+111001 1
+111010 1
+111011 1
+111110 1
+111111 1
+.names $abc$8517$new_n1269_ bus_address[20] $abc$8517$new_n1210_ rd_data[20]
+000 1
+001 1
+010 1
+011 1
+110 1
+.names $abc$8517$new_n1270_ $abc$8517$new_n302_ $abc$8517$new_n1138_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1137_ $abc$8517$new_n1269_
+000000 1
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+000010 1
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+000100 1
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+000111 1
+001000 1
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+001101 1
+001111 1
+010000 1
+010001 1
+010010 1
+010011 1
+010100 1
+010101 1
+010111 1
+.names $abc$8517$new_n299_ $abc$8517$new_n1258_ bus_address[0] $abc$8517$new_n1257_ bus_read_data[28] bus_read_data[20] $abc$8517$new_n1270_
+100000 1
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+101010 1
+101011 1
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+110010 1
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+110111 1
+111000 1
+111001 1
+111010 1
+111011 1
+111110 1
+111111 1
+.names $abc$8517$new_n1272_ bus_address[21] $abc$8517$new_n1210_ rd_data[21]
+000 1
+001 1
+010 1
+011 1
+110 1
+.names $abc$8517$new_n1273_ $abc$8517$new_n302_ $abc$8517$new_n1143_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1142_ $abc$8517$new_n1272_
+000000 1
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+010101 1
+010111 1
+.names $abc$8517$new_n299_ $abc$8517$new_n1258_ bus_address[0] $abc$8517$new_n1257_ bus_read_data[29] bus_read_data[21] $abc$8517$new_n1273_
+100000 1
+100001 1
+100010 1
+100011 1
+101000 1
+101001 1
+101010 1
+101011 1
+110000 1
+110001 1
+110010 1
+110011 1
+110101 1
+110111 1
+111000 1
+111001 1
+111010 1
+111011 1
+111110 1
+111111 1
+.names $abc$8517$new_n1276_ $abc$8517$new_n1275_ bus_address[22] $abc$8517$new_n1210_ rd_data[22]
+0000 1
+0001 1
+0010 1
+0011 1
+0100 1
+0101 1
+0110 1
+0111 1
+1010 1
+1100 1
+1101 1
+1110 1
+1111 1
+.names $abc$8517$new_n299_ $abc$8517$new_n1258_ bus_address[0] $abc$8517$new_n1257_ bus_read_data[30] bus_read_data[22] $abc$8517$new_n1275_
+100000 1
+100001 1
+100010 1
+100011 1
+101000 1
+101001 1
+101010 1
+101011 1
+110000 1
+110001 1
+110010 1
+110011 1
+110101 1
+110111 1
+111000 1
+111001 1
+111010 1
+111011 1
+111110 1
+111111 1
+.names $abc$8517$new_n302_ singlecycle_datapath.program_counter.value[22] $abc$8517$new_n1148_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n414_ $abc$8517$new_n1276_
+000000 1
+000001 1
+000010 1
+000011 1
+000100 1
+000101 1
+000111 1
+001000 1
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+001100 1
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+001111 1
+010000 1
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+010011 1
+010100 1
+010101 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011111 1
+100000 1
+100001 1
+100010 1
+100011 1
+100100 1
+100101 1
+100111 1
+111000 1
+111001 1
+111010 1
+111011 1
+111100 1
+111101 1
+111111 1
+.names $abc$8517$new_n1278_ bus_address[23] $abc$8517$new_n1210_ rd_data[23]
+000 1
+001 1
+010 1
+011 1
+110 1
+.names $abc$8517$new_n1279_ $abc$8517$new_n302_ $abc$8517$new_n1153_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n427_ $abc$8517$new_n1278_
+000000 1
+000001 1
+000010 1
+000011 1
+000100 1
+000101 1
+000111 1
+001000 1
+001001 1
+001010 1
+001011 1
+001100 1
+001101 1
+001111 1
+010000 1
+010001 1
+010010 1
+010011 1
+010100 1
+010101 1
+010111 1
+.names $abc$8517$new_n299_ $abc$8517$new_n1258_ bus_address[0] $abc$8517$new_n1257_ bus_read_data[31] bus_read_data[23] $abc$8517$new_n1279_
+100000 1
+100001 1
+100010 1
+100011 1
+101000 1
+101001 1
+101010 1
+101011 1
+110000 1
+110001 1
+110010 1
+110011 1
+110101 1
+110111 1
+111000 1
+111001 1
+111010 1
+111011 1
+111110 1
+111111 1
+.names $abc$8517$new_n1281_ bus_address[24] $abc$8517$new_n1210_ rd_data[24]
+000 1
+001 1
+010 1
+011 1
+110 1
+.names $abc$8517$new_n1283_ $abc$8517$new_n1257_ $abc$8517$new_n299_ $abc$8517$new_n1282_ bus_read_data[24] $abc$8517$new_n1281_
+10000 1
+10001 1
+10010 1
+10011 1
+11000 1
+11001 1
+11010 1
+11011 1
+11100 1
+11101 1
+11110 1
+.names $abc$8517$new_n1258_ bus_address[0] $abc$8517$new_n1282_
+10 1
+.names $abc$8517$new_n1159_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1157_ $abc$8517$new_n1283_
+00000 1
+00001 1
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+00100 1
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+01000 1
+01001 1
+01010 1
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+01100 1
+01101 1
+01111 1
+10000 1
+10001 1
+10010 1
+10011 1
+10100 1
+10101 1
+10111 1
+.names $abc$8517$new_n1285_ bus_address[25] $abc$8517$new_n1210_ rd_data[25]
+000 1
+001 1
+010 1
+011 1
+110 1
+.names $abc$8517$new_n1286_ $abc$8517$new_n1257_ $abc$8517$new_n299_ $abc$8517$new_n1282_ bus_read_data[25] $abc$8517$new_n1285_
+10000 1
+10001 1
+10010 1
+10011 1
+11000 1
+11001 1
+11010 1
+11011 1
+11100 1
+11101 1
+11110 1
+.names $abc$8517$new_n1169_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1167_ $abc$8517$new_n1286_
+00000 1
+00001 1
+00010 1
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+00100 1
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+01100 1
+01101 1
+01111 1
+10000 1
+10001 1
+10010 1
+10011 1
+10100 1
+10101 1
+10111 1
+.names $abc$8517$new_n1288_ bus_address[26] $abc$8517$new_n1210_ rd_data[26]
+000 1
+001 1
+010 1
+011 1
+110 1
+.names $abc$8517$new_n1289_ $abc$8517$new_n1257_ $abc$8517$new_n299_ $abc$8517$new_n1282_ bus_read_data[26] $abc$8517$new_n1288_
+10000 1
+10001 1
+10010 1
+10011 1
+11000 1
+11001 1
+11010 1
+11011 1
+11100 1
+11101 1
+11110 1
+.names $abc$8517$new_n1174_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1172_ $abc$8517$new_n1289_
+00000 1
+00001 1
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+01001 1
+01010 1
+01011 1
+01100 1
+01101 1
+01111 1
+10000 1
+10001 1
+10010 1
+10011 1
+10100 1
+10101 1
+10111 1
+.names $abc$8517$new_n1291_ bus_address[27] $abc$8517$new_n1210_ rd_data[27]
+000 1
+001 1
+010 1
+011 1
+110 1
+.names $abc$8517$new_n1292_ $abc$8517$new_n1257_ $abc$8517$new_n299_ $abc$8517$new_n1282_ bus_read_data[27] $abc$8517$new_n1291_
+10000 1
+10001 1
+10010 1
+10011 1
+11000 1
+11001 1
+11010 1
+11011 1
+11100 1
+11101 1
+11110 1
+.names $abc$8517$new_n1180_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1179_ $abc$8517$new_n1292_
+00000 1
+00001 1
+00010 1
+00011 1
+00100 1
+00101 1
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+01000 1
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+01010 1
+01011 1
+01100 1
+01101 1
+01111 1
+10000 1
+10001 1
+10010 1
+10011 1
+10100 1
+10101 1
+10111 1
+.names $abc$8517$new_n1294_ bus_address[28] $abc$8517$new_n1210_ rd_data[28]
+000 1
+001 1
+010 1
+011 1
+110 1
+.names $abc$8517$new_n1295_ $abc$8517$new_n1257_ $abc$8517$new_n299_ $abc$8517$new_n1282_ bus_read_data[28] $abc$8517$new_n1294_
+10000 1
+10001 1
+10010 1
+10011 1
+11000 1
+11001 1
+11010 1
+11011 1
+11100 1
+11101 1
+11110 1
+.names $abc$8517$new_n1185_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1184_ $abc$8517$new_n1295_
+00000 1
+00001 1
+00010 1
+00011 1
+00100 1
+00101 1
+00111 1
+01000 1
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+01010 1
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+01100 1
+01101 1
+01111 1
+10000 1
+10001 1
+10010 1
+10011 1
+10100 1
+10101 1
+10111 1
+.names $abc$8517$new_n1297_ bus_address[29] $abc$8517$new_n1210_ rd_data[29]
+000 1
+001 1
+010 1
+011 1
+110 1
+.names $abc$8517$new_n1298_ $abc$8517$new_n1257_ $abc$8517$new_n299_ $abc$8517$new_n1282_ bus_read_data[29] $abc$8517$new_n1297_
+10000 1
+10001 1
+10010 1
+10011 1
+11000 1
+11001 1
+11010 1
+11011 1
+11100 1
+11101 1
+11110 1
+.names $abc$8517$new_n1191_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1189_ $abc$8517$new_n1298_
+00000 1
+00001 1
+00010 1
+00011 1
+00100 1
+00101 1
+00111 1
+01000 1
+01001 1
+01010 1
+01011 1
+01100 1
+01101 1
+01111 1
+10000 1
+10001 1
+10010 1
+10011 1
+10100 1
+10101 1
+10111 1
+.names $abc$8517$new_n1300_ bus_address[30] $abc$8517$new_n1210_ rd_data[30]
+000 1
+001 1
+010 1
+011 1
+110 1
+.names $abc$8517$new_n1301_ $abc$8517$new_n1257_ $abc$8517$new_n299_ $abc$8517$new_n1282_ bus_read_data[30] $abc$8517$new_n1300_
+10000 1
+10001 1
+10010 1
+10011 1
+11000 1
+11001 1
+11010 1
+11011 1
+11100 1
+11101 1
+11110 1
+.names $abc$8517$new_n1197_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1196_ $abc$8517$new_n1301_
+00000 1
+00001 1
+00010 1
+00011 1
+00100 1
+00101 1
+00111 1
+01000 1
+01001 1
+01010 1
+01011 1
+01100 1
+01101 1
+01111 1
+10000 1
+10001 1
+10010 1
+10011 1
+10100 1
+10101 1
+10111 1
+.names $abc$8517$new_n1304_ $abc$8517$new_n1303_ bus_address[31] $abc$8517$new_n1210_ rd_data[31]
+0000 1
+0001 1
+0010 1
+0011 1
+0100 1
+0101 1
+0110 1
+0111 1
+1010 1
+1100 1
+1101 1
+1110 1
+1111 1
+.names $abc$8517$new_n299_ $abc$8517$new_n1257_ bus_read_data[31] $abc$8517$new_n1282_ $abc$8517$new_n1303_
+1000 1
+1001 1
+1010 1
+1011 1
+1111 1
+.names $abc$8517$new_n302_ singlecycle_datapath.program_counter.value[31] $abc$8517$new_n1203_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n494_ $abc$8517$new_n1304_
+000000 1
+000001 1
+000010 1
+000011 1
+000100 1
+000101 1
+000111 1
+001000 1
+001001 1
+001010 1
+001011 1
+001100 1
+001101 1
+001111 1
+010000 1
+010001 1
+010010 1
+010011 1
+010100 1
+010101 1
+010111 1
+011000 1
+011001 1
+011010 1
+011011 1
+011100 1
+011101 1
+011111 1
+100000 1
+100001 1
+100010 1
+100011 1
+100100 1
+100101 1
+100111 1
+111000 1
+111001 1
+111010 1
+111011 1
+111100 1
+111101 1
+111111 1
+.names $abc$8517$new_n299_ $abc$8517$new_n1009_ $abc$8517$new_n348_ $abc$8517$new_n1307_ $abc$8517$new_n1306_ inst[3] bus_write_enable
+100000 1
+100001 1
+100010 1
+100011 1
+100100 1
+100101 1
+100110 1
+101000 1
+101001 1
+101010 1
+101011 1
+.names inst[2] $abc$8517$new_n313_ $abc$8517$new_n1306_
+11 1
+.names inst[6] inst[5] inst[4] $abc$8517$new_n1307_
+000 1
+.names $abc$8517$new_n299_ $abc$8517$new_n1306_ $abc$8517$new_n346_ $abc$8517$new_n1310_ bus_read_enable
+1010 1
+1011 1
+1100 1
+1110 1
+.names inst[3] $abc$8517$new_n1307_ $abc$8517$new_n1310_
+11 1
+.names rs2_data[0] $abc$8517$new_n1005_ bus_write_data[0]
+11 1
+.names rs2_data[1] $abc$8517$new_n1005_ bus_write_data[1]
+11 1
+.names rs2_data[2] $abc$8517$new_n1005_ bus_write_data[2]
+11 1
+.names rs2_data[3] $abc$8517$new_n1005_ bus_write_data[3]
+11 1
+.names rs2_data[4] $abc$8517$new_n1005_ bus_write_data[4]
+11 1
+.names rs2_data[5] $abc$8517$new_n1005_ bus_write_data[5]
+11 1
+.names rs2_data[6] $abc$8517$new_n1005_ bus_write_data[6]
+11 1
+.names rs2_data[7] $abc$8517$new_n1005_ bus_write_data[7]
+11 1
+.names bus_address[0] bus_address[1] rs2_data[0] rs2_data[8] bus_write_data[8]
+0001 1
+0011 1
+1010 1
+1011 1
+.names bus_address[0] bus_address[1] rs2_data[1] rs2_data[9] bus_write_data[9]
+0001 1
+0011 1
+1010 1
+1011 1
+.names bus_address[0] bus_address[1] rs2_data[2] rs2_data[10] bus_write_data[10]
+0001 1
+0011 1
+1010 1
+1011 1
+.names bus_address[0] bus_address[1] rs2_data[3] rs2_data[11] bus_write_data[11]
+0001 1
+0011 1
+1010 1
+1011 1
+.names bus_address[0] bus_address[1] rs2_data[4] rs2_data[12] bus_write_data[12]
+0001 1
+0011 1
+1010 1
+1011 1
+.names bus_address[0] bus_address[1] rs2_data[5] rs2_data[13] bus_write_data[13]
+0001 1
+0011 1
+1010 1
+1011 1
+.names bus_address[0] bus_address[1] rs2_data[6] rs2_data[14] bus_write_data[14]
+0001 1
+0011 1
+1010 1
+1011 1
+.names bus_address[0] bus_address[1] rs2_data[7] rs2_data[15] bus_write_data[15]
+0001 1
+0011 1
+1010 1
+1011 1
+.names bus_address[1] bus_address[0] rs2_data[8] rs2_data[0] rs2_data[16] bus_write_data[16]
+00001 1
+00011 1
+00101 1
+00111 1
+01100 1
+01101 1
+01110 1
+01111 1
+10010 1
+10011 1
+10110 1
+10111 1
+.names bus_address[1] bus_address[0] rs2_data[9] rs2_data[1] rs2_data[17] bus_write_data[17]
+00001 1
+00011 1
+00101 1
+00111 1
+01100 1
+01101 1
+01110 1
+01111 1
+10010 1
+10011 1
+10110 1
+10111 1
+.names bus_address[1] bus_address[0] rs2_data[10] rs2_data[2] rs2_data[18] bus_write_data[18]
+00001 1
+00011 1
+00101 1
+00111 1
+01100 1
+01101 1
+01110 1
+01111 1
+10010 1
+10011 1
+10110 1
+10111 1
+.names bus_address[1] bus_address[0] rs2_data[11] rs2_data[3] rs2_data[19] bus_write_data[19]
+00001 1
+00011 1
+00101 1
+00111 1
+01100 1
+01101 1
+01110 1
+01111 1
+10010 1
+10011 1
+10110 1
+10111 1
+.names bus_address[1] bus_address[0] rs2_data[12] rs2_data[4] rs2_data[20] bus_write_data[20]
+00001 1
+00011 1
+00101 1
+00111 1
+01100 1
+01101 1
+01110 1
+01111 1
+10010 1
+10011 1
+10110 1
+10111 1
+.names bus_address[1] bus_address[0] rs2_data[13] rs2_data[5] rs2_data[21] bus_write_data[21]
+00001 1
+00011 1
+00101 1
+00111 1
+01100 1
+01101 1
+01110 1
+01111 1
+10010 1
+10011 1
+10110 1
+10111 1
+.names bus_address[1] bus_address[0] rs2_data[14] rs2_data[6] rs2_data[22] bus_write_data[22]
+00001 1
+00011 1
+00101 1
+00111 1
+01100 1
+01101 1
+01110 1
+01111 1
+10010 1
+10011 1
+10110 1
+10111 1
+.names bus_address[1] bus_address[0] rs2_data[15] rs2_data[7] rs2_data[23] bus_write_data[23]
+00001 1
+00011 1
+00101 1
+00111 1
+01100 1
+01101 1
+01110 1
+01111 1
+10010 1
+10011 1
+10110 1
+10111 1
+.names bus_address[1] bus_address[0] rs2_data[0] rs2_data[16] rs2_data[8] rs2_data[24] bus_write_data[24]
+000001 1
+000011 1
+000101 1
+000111 1
+001001 1
+001011 1
+001101 1
+001111 1
+010100 1
+010101 1
+010110 1
+010111 1
+011100 1
+011101 1
+011110 1
+011111 1
+100010 1
+100011 1
+100110 1
+100111 1
+101010 1
+101011 1
+101110 1
+101111 1
+111000 1
+111001 1
+111010 1
+111011 1
+111100 1
+111101 1
+111110 1
+111111 1
+.names bus_address[1] bus_address[0] rs2_data[1] rs2_data[17] rs2_data[9] rs2_data[25] bus_write_data[25]
+000001 1
+000011 1
+000101 1
+000111 1
+001001 1
+001011 1
+001101 1
+001111 1
+010100 1
+010101 1
+010110 1
+010111 1
+011100 1
+011101 1
+011110 1
+011111 1
+100010 1
+100011 1
+100110 1
+100111 1
+101010 1
+101011 1
+101110 1
+101111 1
+111000 1
+111001 1
+111010 1
+111011 1
+111100 1
+111101 1
+111110 1
+111111 1
+.names bus_address[1] bus_address[0] rs2_data[2] rs2_data[18] rs2_data[10] rs2_data[26] bus_write_data[26]
+000001 1
+000011 1
+000101 1
+000111 1
+001001 1
+001011 1
+001101 1
+001111 1
+010100 1
+010101 1
+010110 1
+010111 1
+011100 1
+011101 1
+011110 1
+011111 1
+100010 1
+100011 1
+100110 1
+100111 1
+101010 1
+101011 1
+101110 1
+101111 1
+111000 1
+111001 1
+111010 1
+111011 1
+111100 1
+111101 1
+111110 1
+111111 1
+.names bus_address[1] bus_address[0] rs2_data[3] rs2_data[19] rs2_data[11] rs2_data[27] bus_write_data[27]
+000001 1
+000011 1
+000101 1
+000111 1
+001001 1
+001011 1
+001101 1
+001111 1
+010100 1
+010101 1
+010110 1
+010111 1
+011100 1
+011101 1
+011110 1
+011111 1
+100010 1
+100011 1
+100110 1
+100111 1
+101010 1
+101011 1
+101110 1
+101111 1
+111000 1
+111001 1
+111010 1
+111011 1
+111100 1
+111101 1
+111110 1
+111111 1
+.names bus_address[1] bus_address[0] rs2_data[4] rs2_data[20] rs2_data[12] rs2_data[28] bus_write_data[28]
+000001 1
+000011 1
+000101 1
+000111 1
+001001 1
+001011 1
+001101 1
+001111 1
+010100 1
+010101 1
+010110 1
+010111 1
+011100 1
+011101 1
+011110 1
+011111 1
+100010 1
+100011 1
+100110 1
+100111 1
+101010 1
+101011 1
+101110 1
+101111 1
+111000 1
+111001 1
+111010 1
+111011 1
+111100 1
+111101 1
+111110 1
+111111 1
+.names bus_address[1] bus_address[0] rs2_data[5] rs2_data[21] rs2_data[13] rs2_data[29] bus_write_data[29]
+000001 1
+000011 1
+000101 1
+000111 1
+001001 1
+001011 1
+001101 1
+001111 1
+010100 1
+010101 1
+010110 1
+010111 1
+011100 1
+011101 1
+011110 1
+011111 1
+100010 1
+100011 1
+100110 1
+100111 1
+101010 1
+101011 1
+101110 1
+101111 1
+111000 1
+111001 1
+111010 1
+111011 1
+111100 1
+111101 1
+111110 1
+111111 1
+.names bus_address[1] bus_address[0] rs2_data[6] rs2_data[22] rs2_data[14] rs2_data[30] bus_write_data[30]
+000001 1
+000011 1
+000101 1
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+.names $abc$8517$new_n368_ $abc$8517$new_n362_ $abc$8517$new_n508_ $abc$8517$new_n526_ $abc$8517$new_n521_ $abc$8517$new_n531_ $abc$8517$new_n1377_
+000000 1
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+.names $abc$8517$new_n768_ $abc$8517$new_n772_ $abc$8517$new_n770_ $abc$8517$new_n769_ $abc$8517$new_n711_ $abc$8517$new_n548_ $abc$8517$new_n1378_
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+.names $abc$8517$new_n1378_ $abc$8517$new_n763_ $abc$8517$new_n766_ $abc$8517$new_n549_ $abc$8517$new_n543_ $abc$8517$new_n1377_ $abc$8517$new_n1379_
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+.names $abc$8517$new_n368_ $abc$8517$new_n362_ $abc$8517$new_n572_ $abc$8517$new_n557_ $abc$8517$new_n556_ $abc$8517$new_n649_ $abc$8517$new_n1380_
+000000 1
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+.names $abc$8517$new_n782_ $abc$8517$new_n781_ $abc$8517$new_n777_ $abc$8517$new_n549_ $abc$8517$new_n543_ $abc$8517$new_n1380_ $abc$8517$new_n1381_
+100000 1
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+.names $abc$8517$new_n1381_ $abc$8517$new_n382_ $abc$8517$new_n783_ $abc$8517$new_n775_ $abc$8517$new_n548_ $abc$8517$new_n1382_
+10000 1
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+.names $abc$8517$new_n368_ $abc$8517$new_n345_ $abc$8517$new_n362_ $abc$8517$new_n837_ $abc$8517$new_n838_ $abc$8517$new_n778_ $abc$8517$new_n1383_
+010000 1
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+.names $abc$8517$new_n1383_ $abc$8517$new_n820_ $abc$8517$new_n345_ $abc$8517$new_n840_ $abc$8517$new_n554_ $abc$8517$new_n581_ $abc$8517$new_n1384_
+000100 1
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+.names $abc$8517$new_n368_ $abc$8517$new_n820_ $abc$8517$new_n588_ $abc$8517$new_n345_ $abc$8517$new_n734_ $abc$8517$new_n850_ $abc$8517$new_n1385_
+000100 1
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+.names $abc$8517$new_n853_ $abc$8517$new_n345_ $abc$8517$new_n845_ $abc$8517$new_n1385_ $abc$8517$new_n600_ $abc$8517$new_n583_ $abc$8517$new_n1386_
+100000 1
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+.names $abc$8517$new_n546_ $abc$8517$new_n843_ $abc$8517$new_n316_ $abc$8517$new_n1386_ bus_address[18]
+0000 1
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+.names $abc$8517$new_n368_ $abc$8517$new_n543_ $abc$8517$new_n874_ $abc$8517$new_n819_ $abc$8517$new_n634_ $abc$8517$new_n877_ $abc$8517$new_n1388_
+000000 1
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+111110 1
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+.names $abc$8517$new_n1388_ $abc$8517$new_n878_ $abc$8517$new_n879_ $abc$8517$new_n869_ $abc$8517$new_n333_ $abc$8517$new_n548_ $abc$8517$new_n1389_
+110000 1
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+.names $abc$8517$new_n413_ $abc$8517$new_n329_ $abc$8517$new_n497_ $abc$8517$new_n552_ $abc$8517$new_n547_ $abc$8517$new_n478_ $abc$8517$new_n1390_
+000000 1
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+.names $abc$8517$new_n1390_ $abc$8517$new_n901_ $abc$8517$new_n897_ $abc$8517$new_n896_ $abc$8517$new_n894_ $abc$8517$new_n811_ bus_address[22]
+000000 1
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+111101 1
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+111111 1
+.names $abc$8517$new_n345_ $abc$8517$new_n717_ $abc$8517$new_n933_ $abc$8517$new_n543_ $abc$8517$new_n568_ $abc$8517$new_n434_ $abc$8517$new_n1392_
+000000 1
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+111100 1
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+111110 1
+111111 1
+.names $abc$8517$new_n936_ $abc$8517$new_n1392_ $abc$8517$new_n932_ $abc$8517$new_n929_ $abc$8517$new_n546_ $abc$8517$new_n927_ bus_address[25]
+000000 1
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+000010 1
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+000100 1
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+001000 1
+001001 1
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+110110 1
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+111100 1
+111101 1
+111110 1
+111111 1
+.names $abc$8517$new_n820_ $abc$8517$new_n368_ $abc$8517$new_n863_ $abc$8517$new_n362_ $abc$8517$new_n612_ $abc$8517$new_n1394_
+10011 1
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+11010 1
+11011 1
+.names $abc$8517$new_n345_ $abc$8517$new_n748_ $abc$8517$new_n692_ $abc$8517$new_n1394_ $abc$8517$new_n719_ $abc$8517$new_n747_ $abc$8517$new_n1395_
+000000 1
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+001000 1
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+011011 1
+100000 1
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+100100 1
+100101 1
+100111 1
+.names $abc$8517$new_n959_ $abc$8517$new_n1395_ $abc$8517$new_n956_ $abc$8517$new_n811_ $abc$8517$new_n548_ $abc$8517$new_n952_ $abc$8517$new_n1396_
+110000 1
+110001 1
+110010 1
+.names $abc$8517$new_n368_ $abc$8517$new_n362_ $abc$8517$new_n623_ $abc$8517$new_n620_ $abc$8517$new_n624_ $abc$8517$new_n621_ $abc$8517$new_n1397_
+000000 1
+000010 1
+000100 1
+000110 1
+001000 1
+001010 1
+001100 1
+001110 1
+010000 1
+010001 1
+010010 1
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+011000 1
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+011011 1
+100000 1
+100001 1
+100100 1
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+101001 1
+101100 1
+101101 1
+111000 1
+111001 1
+111010 1
+111011 1
+111100 1
+111101 1
+111110 1
+111111 1
+.names $abc$8517$new_n1355_ $abc$8517$new_n603_ $abc$8517$new_n1397_ $abc$8517$new_n549_ bus_address[3]
+0000 1
+0001 1
+0010 1
+0011 1
+0100 1
+0101 1
+0110 1
+0111 1
+1011 1
+1100 1
+1101 1
+1110 1
+1111 1
+.names $abc$8517$new_n368_ $abc$8517$new_n362_ $abc$8517$new_n503_ $abc$8517$new_n521_ $abc$8517$new_n508_ $abc$8517$new_n526_ $abc$8517$new_n1399_
+000000 1
+000010 1
+000100 1
+000110 1
+001000 1
+001010 1
+001100 1
+001110 1
+010000 1
+010001 1
+010010 1
+010011 1
+011000 1
+011001 1
+011010 1
+011011 1
+100000 1
+100001 1
+100100 1
+100101 1
+101000 1
+101001 1
+101100 1
+101101 1
+110000 1
+110001 1
+110010 1
+110011 1
+110100 1
+110101 1
+110110 1
+110111 1
+.names $abc$8517$new_n1369_ $abc$8517$new_n707_ $abc$8517$new_n703_ $abc$8517$new_n1399_ $abc$8517$new_n549_ bus_address[8]
+00000 1
+00001 1
+00010 1
+00011 1
+00100 1
+00101 1
+00110 1
+00111 1
+01000 1
+01001 1
+01010 1
+01011 1
+01100 1
+01101 1
+01110 1
+01111 1
+10011 1
+10100 1
+10101 1
+10110 1
+10111 1
+11000 1
+11001 1
+11010 1
+11011 1
+11100 1
+11101 1
+11110 1
+11111 1
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][0] singlecycle_datapath.program_counter.value[0] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][1] singlecycle_datapath.program_counter.value[1] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][2] singlecycle_datapath.program_counter.value[2] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][3] singlecycle_datapath.program_counter.value[3] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][4] singlecycle_datapath.program_counter.value[4] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][5] singlecycle_datapath.program_counter.value[5] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][6] singlecycle_datapath.program_counter.value[6] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][7] singlecycle_datapath.program_counter.value[7] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][8] singlecycle_datapath.program_counter.value[8] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][9] singlecycle_datapath.program_counter.value[9] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][10] singlecycle_datapath.program_counter.value[10] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][11] singlecycle_datapath.program_counter.value[11] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][12] singlecycle_datapath.program_counter.value[12] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][13] singlecycle_datapath.program_counter.value[13] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][14] singlecycle_datapath.program_counter.value[14] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][15] singlecycle_datapath.program_counter.value[15] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][16] singlecycle_datapath.program_counter.value[16] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][17] singlecycle_datapath.program_counter.value[17] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][18] singlecycle_datapath.program_counter.value[18] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][19] singlecycle_datapath.program_counter.value[19] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][20] singlecycle_datapath.program_counter.value[20] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][21] singlecycle_datapath.program_counter.value[21] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][22] singlecycle_datapath.program_counter.value[22] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][23] singlecycle_datapath.program_counter.value[23] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][24] singlecycle_datapath.program_counter.value[24] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][25] singlecycle_datapath.program_counter.value[25] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][26] singlecycle_datapath.program_counter.value[26] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][27] singlecycle_datapath.program_counter.value[27] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][28] singlecycle_datapath.program_counter.value[28] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][29] singlecycle_datapath.program_counter.value[29] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][30] singlecycle_datapath.program_counter.value[30] re clock 2
+.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][31] singlecycle_datapath.program_counter.value[31] re clock 2
+.names bus_address[0] address[0]
+1 1
+.names bus_address[1] address[1]
+1 1
+.names bus_address[2] address[2]
+1 1
+.names bus_address[3] address[3]
+1 1
+.names bus_address[4] address[4]
+1 1
+.names bus_address[5] address[5]
+1 1
+.names bus_address[6] address[6]
+1 1
+.names bus_address[7] address[7]
+1 1
+.names bus_address[8] address[8]
+1 1
+.names bus_address[9] address[9]
+1 1
+.names bus_address[10] address[10]
+1 1
+.names bus_address[11] address[11]
+1 1
+.names bus_address[12] address[12]
+1 1
+.names bus_address[13] address[13]
+1 1
+.names bus_address[14] address[14]
+1 1
+.names bus_address[15] address[15]
+1 1
+.names bus_address[16] address[16]
+1 1
+.names bus_address[17] address[17]
+1 1
+.names bus_address[18] address[18]
+1 1
+.names bus_address[19] address[19]
+1 1
+.names bus_address[20] address[20]
+1 1
+.names bus_address[21] address[21]
+1 1
+.names bus_address[22] address[22]
+1 1
+.names bus_address[23] address[23]
+1 1
+.names bus_address[24] address[24]
+1 1
+.names bus_address[25] address[25]
+1 1
+.names bus_address[26] address[26]
+1 1
+.names bus_address[27] address[27]
+1 1
+.names bus_address[28] address[28]
+1 1
+.names bus_address[29] address[29]
+1 1
+.names bus_address[30] address[30]
+1 1
+.names bus_address[31] address[31]
+1 1
+.names $false alu_function[4]
+1 1
+.names bus_address[0] data_memory_interface.address[0]
+1 1
+.names bus_address[1] data_memory_interface.address[1]
+1 1
+.names bus_address[2] data_memory_interface.address[2]
+1 1
+.names bus_address[3] data_memory_interface.address[3]
+1 1
+.names bus_address[4] data_memory_interface.address[4]
+1 1
+.names bus_address[5] data_memory_interface.address[5]
+1 1
+.names bus_address[6] data_memory_interface.address[6]
+1 1
+.names bus_address[7] data_memory_interface.address[7]
+1 1
+.names bus_address[8] data_memory_interface.address[8]
+1 1
+.names bus_address[9] data_memory_interface.address[9]
+1 1
+.names bus_address[10] data_memory_interface.address[10]
+1 1
+.names bus_address[11] data_memory_interface.address[11]
+1 1
+.names bus_address[12] data_memory_interface.address[12]
+1 1
+.names bus_address[13] data_memory_interface.address[13]
+1 1
+.names bus_address[14] data_memory_interface.address[14]
+1 1
+.names bus_address[15] data_memory_interface.address[15]
+1 1
+.names bus_address[16] data_memory_interface.address[16]
+1 1
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+.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[12]
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+1 1
+.names singlecycle_datapath.program_counter.value[1] singlecycle_datapath.adder_pc_plus_4.operand_b[1]
+1 1
+.names singlecycle_datapath.program_counter.value[2] singlecycle_datapath.adder_pc_plus_4.operand_b[2]
+1 1
+.names singlecycle_datapath.program_counter.value[3] singlecycle_datapath.adder_pc_plus_4.operand_b[3]
+1 1
+.names singlecycle_datapath.program_counter.value[4] singlecycle_datapath.adder_pc_plus_4.operand_b[4]
+1 1
+.names singlecycle_datapath.program_counter.value[5] singlecycle_datapath.adder_pc_plus_4.operand_b[5]
+1 1
+.names singlecycle_datapath.program_counter.value[6] singlecycle_datapath.adder_pc_plus_4.operand_b[6]
+1 1
+.names singlecycle_datapath.program_counter.value[7] singlecycle_datapath.adder_pc_plus_4.operand_b[7]
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+.names singlecycle_datapath.program_counter.value[8] singlecycle_datapath.adder_pc_plus_4.operand_b[8]
+1 1
+.names singlecycle_datapath.program_counter.value[9] singlecycle_datapath.adder_pc_plus_4.operand_b[9]
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+1 1
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+1 1
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+1 1
+.names singlecycle_datapath.program_counter.value[14] singlecycle_datapath.adder_pc_plus_4.operand_b[14]
+1 1
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+1 1
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+1 1
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+1 1
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+1 1
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+1 1
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+1 1
+.names singlecycle_datapath.program_counter.value[24] singlecycle_datapath.adder_pc_plus_4.operand_b[24]
+1 1
+.names singlecycle_datapath.program_counter.value[25] singlecycle_datapath.adder_pc_plus_4.operand_b[25]
+1 1
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+1 1
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+1 1
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+1 1
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+1 1
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+1 1
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+1 1
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+1 1
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+1 1
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+1 1
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+1 1
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+1 1
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+1 1
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+1 1
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+1 1
+.names singlecycle_datapath.program_counter.value[31] singlecycle_datapath.adder_pc_plus_immediate.operand_a[31]
+1 1
+.names alu_function[0] singlecycle_datapath.alu.alu_function[0]
+1 1
+.names alu_function[1] singlecycle_datapath.alu.alu_function[1]
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+1 1
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+1 1
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+1 1
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+1 1
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+1 1
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+.names rs1_data[9] singlecycle_datapath.mux_operand_a.in0[9]
+1 1
+.names rs1_data[10] singlecycle_datapath.mux_operand_a.in0[10]
+1 1
+.names rs1_data[11] singlecycle_datapath.mux_operand_a.in0[11]
+1 1
+.names rs1_data[12] singlecycle_datapath.mux_operand_a.in0[12]
+1 1
+.names rs1_data[13] singlecycle_datapath.mux_operand_a.in0[13]
+1 1
+.names rs1_data[14] singlecycle_datapath.mux_operand_a.in0[14]
+1 1
+.names rs1_data[15] singlecycle_datapath.mux_operand_a.in0[15]
+1 1
+.names rs1_data[16] singlecycle_datapath.mux_operand_a.in0[16]
+1 1
+.names rs1_data[17] singlecycle_datapath.mux_operand_a.in0[17]
+1 1
+.names rs1_data[18] singlecycle_datapath.mux_operand_a.in0[18]
+1 1
+.names rs1_data[19] singlecycle_datapath.mux_operand_a.in0[19]
+1 1
+.names rs1_data[20] singlecycle_datapath.mux_operand_a.in0[20]
+1 1
+.names rs1_data[21] singlecycle_datapath.mux_operand_a.in0[21]
+1 1
+.names rs1_data[22] singlecycle_datapath.mux_operand_a.in0[22]
+1 1
+.names rs1_data[23] singlecycle_datapath.mux_operand_a.in0[23]
+1 1
+.names rs1_data[24] singlecycle_datapath.mux_operand_a.in0[24]
+1 1
+.names rs1_data[25] singlecycle_datapath.mux_operand_a.in0[25]
+1 1
+.names rs1_data[26] singlecycle_datapath.mux_operand_a.in0[26]
+1 1
+.names rs1_data[27] singlecycle_datapath.mux_operand_a.in0[27]
+1 1
+.names rs1_data[28] singlecycle_datapath.mux_operand_a.in0[28]
+1 1
+.names rs1_data[29] singlecycle_datapath.mux_operand_a.in0[29]
+1 1
+.names rs1_data[30] singlecycle_datapath.mux_operand_a.in0[30]
+1 1
+.names rs1_data[31] singlecycle_datapath.mux_operand_a.in0[31]
+1 1
+.names singlecycle_datapath.program_counter.value[0] singlecycle_datapath.mux_operand_a.in1[0]
+1 1
+.names singlecycle_datapath.program_counter.value[1] singlecycle_datapath.mux_operand_a.in1[1]
+1 1
+.names singlecycle_datapath.program_counter.value[2] singlecycle_datapath.mux_operand_a.in1[2]
+1 1
+.names singlecycle_datapath.program_counter.value[3] singlecycle_datapath.mux_operand_a.in1[3]
+1 1
+.names singlecycle_datapath.program_counter.value[4] singlecycle_datapath.mux_operand_a.in1[4]
+1 1
+.names singlecycle_datapath.program_counter.value[5] singlecycle_datapath.mux_operand_a.in1[5]
+1 1
+.names singlecycle_datapath.program_counter.value[6] singlecycle_datapath.mux_operand_a.in1[6]
+1 1
+.names singlecycle_datapath.program_counter.value[7] singlecycle_datapath.mux_operand_a.in1[7]
+1 1
+.names singlecycle_datapath.program_counter.value[8] singlecycle_datapath.mux_operand_a.in1[8]
+1 1
+.names singlecycle_datapath.program_counter.value[9] singlecycle_datapath.mux_operand_a.in1[9]
+1 1
+.names singlecycle_datapath.program_counter.value[10] singlecycle_datapath.mux_operand_a.in1[10]
+1 1
+.names singlecycle_datapath.program_counter.value[11] singlecycle_datapath.mux_operand_a.in1[11]
+1 1
+.names singlecycle_datapath.program_counter.value[12] singlecycle_datapath.mux_operand_a.in1[12]
+1 1
+.names singlecycle_datapath.program_counter.value[13] singlecycle_datapath.mux_operand_a.in1[13]
+1 1
+.names singlecycle_datapath.program_counter.value[14] singlecycle_datapath.mux_operand_a.in1[14]
+1 1
+.names singlecycle_datapath.program_counter.value[15] singlecycle_datapath.mux_operand_a.in1[15]
+1 1
+.names singlecycle_datapath.program_counter.value[16] singlecycle_datapath.mux_operand_a.in1[16]
+1 1
+.names singlecycle_datapath.program_counter.value[17] singlecycle_datapath.mux_operand_a.in1[17]
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+.names singlecycle_datapath.program_counter.value[18] singlecycle_datapath.mux_operand_a.in1[18]
+1 1
+.names singlecycle_datapath.program_counter.value[19] singlecycle_datapath.mux_operand_a.in1[19]
+1 1
+.names singlecycle_datapath.program_counter.value[20] singlecycle_datapath.mux_operand_a.in1[20]
+1 1
+.names singlecycle_datapath.program_counter.value[21] singlecycle_datapath.mux_operand_a.in1[21]
+1 1
+.names singlecycle_datapath.program_counter.value[22] singlecycle_datapath.mux_operand_a.in1[22]
+1 1
+.names singlecycle_datapath.program_counter.value[23] singlecycle_datapath.mux_operand_a.in1[23]
+1 1
+.names singlecycle_datapath.program_counter.value[24] singlecycle_datapath.mux_operand_a.in1[24]
+1 1
+.names singlecycle_datapath.program_counter.value[25] singlecycle_datapath.mux_operand_a.in1[25]
+1 1
+.names singlecycle_datapath.program_counter.value[26] singlecycle_datapath.mux_operand_a.in1[26]
+1 1
+.names singlecycle_datapath.program_counter.value[27] singlecycle_datapath.mux_operand_a.in1[27]
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+.names singlecycle_datapath.program_counter.value[28] singlecycle_datapath.mux_operand_a.in1[28]
+1 1
+.names singlecycle_datapath.program_counter.value[29] singlecycle_datapath.mux_operand_a.in1[29]
+1 1
+.names singlecycle_datapath.program_counter.value[30] singlecycle_datapath.mux_operand_a.in1[30]
+1 1
+.names singlecycle_datapath.program_counter.value[31] singlecycle_datapath.mux_operand_a.in1[31]
+1 1
+.names singlecycle_datapath.program_counter.value[0] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[0]
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+.names singlecycle_datapath.program_counter.value[1] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[1]
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+.names singlecycle_datapath.program_counter.value[2] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[2]
+1 1
+.names singlecycle_datapath.program_counter.value[3] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[3]
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+.names singlecycle_datapath.program_counter.value[4] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[4]
+1 1
+.names singlecycle_datapath.program_counter.value[5] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[5]
+1 1
+.names singlecycle_datapath.program_counter.value[6] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[6]
+1 1
+.names singlecycle_datapath.program_counter.value[7] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[7]
+1 1
+.names singlecycle_datapath.program_counter.value[8] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[8]
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+.names singlecycle_datapath.program_counter.value[9] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[9]
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+.names singlecycle_datapath.program_counter.value[10] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[10]
+1 1
+.names singlecycle_datapath.program_counter.value[11] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[11]
+1 1
+.names singlecycle_datapath.program_counter.value[12] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[12]
+1 1
+.names singlecycle_datapath.program_counter.value[13] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[13]
+1 1
+.names singlecycle_datapath.program_counter.value[14] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[14]
+1 1
+.names singlecycle_datapath.program_counter.value[15] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[15]
+1 1
+.names singlecycle_datapath.program_counter.value[16] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[16]
+1 1
+.names singlecycle_datapath.program_counter.value[17] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[17]
+1 1
+.names singlecycle_datapath.program_counter.value[18] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[18]
+1 1
+.names singlecycle_datapath.program_counter.value[19] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[19]
+1 1
+.names singlecycle_datapath.program_counter.value[20] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[20]
+1 1
+.names singlecycle_datapath.program_counter.value[21] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[21]
+1 1
+.names singlecycle_datapath.program_counter.value[22] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[22]
+1 1
+.names singlecycle_datapath.program_counter.value[23] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[23]
+1 1
+.names singlecycle_datapath.program_counter.value[24] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[24]
+1 1
+.names singlecycle_datapath.program_counter.value[25] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[25]
+1 1
+.names singlecycle_datapath.program_counter.value[26] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[26]
+1 1
+.names singlecycle_datapath.program_counter.value[27] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[27]
+1 1
+.names singlecycle_datapath.program_counter.value[28] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[28]
+1 1
+.names singlecycle_datapath.program_counter.value[29] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[29]
+1 1
+.names singlecycle_datapath.program_counter.value[30] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[30]
+1 1
+.names singlecycle_datapath.program_counter.value[31] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[31]
+1 1
+.names rs1_data[0] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[32]
+1 1
+.names rs1_data[1] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[33]
+1 1
+.names rs1_data[2] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[34]
+1 1
+.names rs1_data[3] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[35]
+1 1
+.names rs1_data[4] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[36]
+1 1
+.names rs1_data[5] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[37]
+1 1
+.names rs1_data[6] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[38]
+1 1
+.names rs1_data[7] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[39]
+1 1
+.names rs1_data[8] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[40]
+1 1
+.names rs1_data[9] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[41]
+1 1
+.names rs1_data[10] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[42]
+1 1
+.names rs1_data[11] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[43]
+1 1
+.names rs1_data[12] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[44]
+1 1
+.names rs1_data[13] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[45]
+1 1
+.names rs1_data[14] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[46]
+1 1
+.names rs1_data[15] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[47]
+1 1
+.names rs1_data[16] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[48]
+1 1
+.names rs1_data[17] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[49]
+1 1
+.names rs1_data[18] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[50]
+1 1
+.names rs1_data[19] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[51]
+1 1
+.names rs1_data[20] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[52]
+1 1
+.names rs1_data[21] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[53]
+1 1
+.names rs1_data[22] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[54]
+1 1
+.names rs1_data[23] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[55]
+1 1
+.names rs1_data[24] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[56]
+1 1
+.names rs1_data[25] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[57]
+1 1
+.names rs1_data[26] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[58]
+1 1
+.names rs1_data[27] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[59]
+1 1
+.names rs1_data[28] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[60]
+1 1
+.names rs1_data[29] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[61]
+1 1
+.names rs1_data[30] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[62]
+1 1
+.names rs1_data[31] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[63]
+1 1
+.names rs1_data[0] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][0]
+1 1
+.names rs1_data[1] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][1]
+1 1
+.names rs1_data[2] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][2]
+1 1
+.names rs1_data[3] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][3]
+1 1
+.names rs1_data[4] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][4]
+1 1
+.names rs1_data[5] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][5]
+1 1
+.names rs1_data[6] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][6]
+1 1
+.names rs1_data[7] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][7]
+1 1
+.names rs1_data[8] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][8]
+1 1
+.names rs1_data[9] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][9]
+1 1
+.names rs1_data[10] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][10]
+1 1
+.names rs1_data[11] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][11]
+1 1
+.names rs1_data[12] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][12]
+1 1
+.names rs1_data[13] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][13]
+1 1
+.names rs1_data[14] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][14]
+1 1
+.names rs1_data[15] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][15]
+1 1
+.names rs1_data[16] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][16]
+1 1
+.names rs1_data[17] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][17]
+1 1
+.names rs1_data[18] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][18]
+1 1
+.names rs1_data[19] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][19]
+1 1
+.names rs1_data[20] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][20]
+1 1
+.names rs1_data[21] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][21]
+1 1
+.names rs1_data[22] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][22]
+1 1
+.names rs1_data[23] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][23]
+1 1
+.names rs1_data[24] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][24]
+1 1
+.names rs1_data[25] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][25]
+1 1
+.names rs1_data[26] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][26]
+1 1
+.names rs1_data[27] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][27]
+1 1
+.names rs1_data[28] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][28]
+1 1
+.names rs1_data[29] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][29]
+1 1
+.names rs1_data[30] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][30]
+1 1
+.names rs1_data[31] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][31]
+1 1
+.names singlecycle_datapath.program_counter.value[0] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][0]
+1 1
+.names singlecycle_datapath.program_counter.value[1] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][1]
+1 1
+.names singlecycle_datapath.program_counter.value[2] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][2]
+1 1
+.names singlecycle_datapath.program_counter.value[3] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][3]
+1 1
+.names singlecycle_datapath.program_counter.value[4] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][4]
+1 1
+.names singlecycle_datapath.program_counter.value[5] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][5]
+1 1
+.names singlecycle_datapath.program_counter.value[6] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][6]
+1 1
+.names singlecycle_datapath.program_counter.value[7] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][7]
+1 1
+.names singlecycle_datapath.program_counter.value[8] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][8]
+1 1
+.names singlecycle_datapath.program_counter.value[9] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][9]
+1 1
+.names singlecycle_datapath.program_counter.value[10] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][10]
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+.names singlecycle_datapath.program_counter.value[11] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][11]
+1 1
+.names singlecycle_datapath.program_counter.value[12] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][12]
+1 1
+.names singlecycle_datapath.program_counter.value[13] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][13]
+1 1
+.names singlecycle_datapath.program_counter.value[14] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][14]
+1 1
+.names singlecycle_datapath.program_counter.value[15] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][15]
+1 1
+.names singlecycle_datapath.program_counter.value[16] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][16]
+1 1
+.names singlecycle_datapath.program_counter.value[17] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][17]
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+.names singlecycle_datapath.program_counter.value[18] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][18]
+1 1
+.names singlecycle_datapath.program_counter.value[19] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][19]
+1 1
+.names singlecycle_datapath.program_counter.value[20] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][20]
+1 1
+.names singlecycle_datapath.program_counter.value[21] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][21]
+1 1
+.names singlecycle_datapath.program_counter.value[22] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][22]
+1 1
+.names singlecycle_datapath.program_counter.value[23] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][23]
+1 1
+.names singlecycle_datapath.program_counter.value[24] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][24]
+1 1
+.names singlecycle_datapath.program_counter.value[25] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][25]
+1 1
+.names singlecycle_datapath.program_counter.value[26] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][26]
+1 1
+.names singlecycle_datapath.program_counter.value[27] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][27]
+1 1
+.names singlecycle_datapath.program_counter.value[28] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][28]
+1 1
+.names singlecycle_datapath.program_counter.value[29] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][29]
+1 1
+.names singlecycle_datapath.program_counter.value[30] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][30]
+1 1
+.names singlecycle_datapath.program_counter.value[31] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][31]
+1 1
+.names rs2_data[0] singlecycle_datapath.mux_operand_b.in0[0]
+1 1
+.names rs2_data[1] singlecycle_datapath.mux_operand_b.in0[1]
+1 1
+.names rs2_data[2] singlecycle_datapath.mux_operand_b.in0[2]
+1 1
+.names rs2_data[3] singlecycle_datapath.mux_operand_b.in0[3]
+1 1
+.names rs2_data[4] singlecycle_datapath.mux_operand_b.in0[4]
+1 1
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+.names rs2_data[10] singlecycle_datapath.rs2_data[10]
+1 1
+.names rs2_data[11] singlecycle_datapath.rs2_data[11]
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+.names rs2_data[12] singlecycle_datapath.rs2_data[12]
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+.names rs2_data[13] singlecycle_datapath.rs2_data[13]
+1 1
+.names rs2_data[14] singlecycle_datapath.rs2_data[14]
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+.names rs2_data[15] singlecycle_datapath.rs2_data[15]
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+.names rs2_data[16] singlecycle_datapath.rs2_data[16]
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+.names rs2_data[17] singlecycle_datapath.rs2_data[17]
+1 1
+.names rs2_data[18] singlecycle_datapath.rs2_data[18]
+1 1
+.names rs2_data[19] singlecycle_datapath.rs2_data[19]
+1 1
+.names rs2_data[20] singlecycle_datapath.rs2_data[20]
+1 1
+.names rs2_data[21] singlecycle_datapath.rs2_data[21]
+1 1
+.names rs2_data[22] singlecycle_datapath.rs2_data[22]
+1 1
+.names rs2_data[23] singlecycle_datapath.rs2_data[23]
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+.names rs2_data[24] singlecycle_datapath.rs2_data[24]
+1 1
+.names rs2_data[25] singlecycle_datapath.rs2_data[25]
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+.names rs2_data[26] singlecycle_datapath.rs2_data[26]
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+.names rs2_data[27] singlecycle_datapath.rs2_data[27]
+1 1
+.names rs2_data[28] singlecycle_datapath.rs2_data[28]
+1 1
+.names rs2_data[29] singlecycle_datapath.rs2_data[29]
+1 1
+.names rs2_data[30] singlecycle_datapath.rs2_data[30]
+1 1
+.names rs2_data[31] singlecycle_datapath.rs2_data[31]
+1 1
+.names rs2_data[0] write_data[0]
+1 1
+.names rs2_data[1] write_data[1]
+1 1
+.names rs2_data[2] write_data[2]
+1 1
+.names rs2_data[3] write_data[3]
+1 1
+.names rs2_data[4] write_data[4]
+1 1
+.names rs2_data[5] write_data[5]
+1 1
+.names rs2_data[6] write_data[6]
+1 1
+.names rs2_data[7] write_data[7]
+1 1
+.names rs2_data[8] write_data[8]
+1 1
+.names rs2_data[9] write_data[9]
+1 1
+.names rs2_data[10] write_data[10]
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+1 1
+.names rs2_data[12] write_data[12]
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+.names rs2_data[13] write_data[13]
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+.names rs2_data[14] write_data[14]
+1 1
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+1 1
+.names rs2_data[16] write_data[16]
+1 1
+.names rs2_data[17] write_data[17]
+1 1
+.names rs2_data[18] write_data[18]
+1 1
+.names rs2_data[19] write_data[19]
+1 1
+.names rs2_data[20] write_data[20]
+1 1
+.names rs2_data[21] write_data[21]
+1 1
+.names rs2_data[22] write_data[22]
+1 1
+.names rs2_data[23] write_data[23]
+1 1
+.names rs2_data[24] write_data[24]
+1 1
+.names rs2_data[25] write_data[25]
+1 1
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+1 1
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+1 1
+.names rs2_data[28] write_data[28]
+1 1
+.names rs2_data[29] write_data[29]
+1 1
+.names rs2_data[30] write_data[30]
+1 1
+.names rs2_data[31] write_data[31]
+1 1
+.names bus_write_enable write_enable
+1 1
+.end
diff --git a/openfpga/test_script/riscv_core.openfpga b/openfpga/test_script/riscv_core.openfpga
new file mode 100644
index 000000000..d2614df44
--- /dev/null
+++ b/openfpga/test_script/riscv_core.openfpga
@@ -0,0 +1,2 @@
+# Run VPR for the RISC-V core
+vpr ./test_arch/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ./test_blif/riscv_core_lut6.blif

From 2e41138633257245ad6fa6feb1179a61f0a9ab2f Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 26 Jan 2020 17:56:22 -0700
Subject: [PATCH 023/645] use a micro benchmark for vpr quick-run

---
 openfpga/test_blif/riscv_core_lut6.blif       | 19187 ----------------
 openfpga/test_blif/s298.blif                  |    90 +
 .../{riscv_core.openfpga => s298.openfpga}    |     2 +-
 3 files changed, 91 insertions(+), 19188 deletions(-)
 delete mode 100644 openfpga/test_blif/riscv_core_lut6.blif
 create mode 100644 openfpga/test_blif/s298.blif
 rename openfpga/test_script/{riscv_core.openfpga => s298.openfpga} (74%)

diff --git a/openfpga/test_blif/riscv_core_lut6.blif b/openfpga/test_blif/riscv_core_lut6.blif
deleted file mode 100644
index a313bebc1..000000000
--- a/openfpga/test_blif/riscv_core_lut6.blif
+++ /dev/null
@@ -1,19187 +0,0 @@
-# Generated by Yosys 0.8+599 (git sha1 463f710, gcc 4.8.5 -fPIC -Os)
-
-.model riscv_core
-.inputs clock reset bus_read_data[0] bus_read_data[1] bus_read_data[2] bus_read_data[3] bus_read_data[4] bus_read_data[5] bus_read_data[6] bus_read_data[7] bus_read_data[8] bus_read_data[9] bus_read_data[10] bus_read_data[11] bus_read_data[12] bus_read_data[13] bus_read_data[14] bus_read_data[15] bus_read_data[16] bus_read_data[17] bus_read_data[18] bus_read_data[19] bus_read_data[20] bus_read_data[21] bus_read_data[22] bus_read_data[23] bus_read_data[24] bus_read_data[25] bus_read_data[26] bus_read_data[27] bus_read_data[28] bus_read_data[29] bus_read_data[30] bus_read_data[31] inst[0] inst[1] inst[2] inst[3] inst[4] inst[5] inst[6] inst[7] inst[8] inst[9] inst[10] inst[11] inst[12] inst[13] inst[14] inst[15] inst[16] inst[17] inst[18] inst[19] inst[20] inst[21] inst[22] inst[23] inst[24] inst[25] inst[26] inst[27] inst[28] inst[29] inst[30] inst[31] rs1_data[0] rs1_data[1] rs1_data[2] rs1_data[3] rs1_data[4] rs1_data[5] rs1_data[6] rs1_data[7] rs1_data[8] rs1_data[9] rs1_data[10] rs1_data[11] rs1_data[12] rs1_data[13] rs1_data[14] rs1_data[15] rs1_data[16] rs1_data[17] rs1_data[18] rs1_data[19] rs1_data[20] rs1_data[21] rs1_data[22] rs1_data[23] rs1_data[24] rs1_data[25] rs1_data[26] rs1_data[27] rs1_data[28] rs1_data[29] rs1_data[30] rs1_data[31] rs2_data[0] rs2_data[1] rs2_data[2] rs2_data[3] rs2_data[4] rs2_data[5] rs2_data[6] rs2_data[7] rs2_data[8] rs2_data[9] rs2_data[10] rs2_data[11] rs2_data[12] rs2_data[13] rs2_data[14] rs2_data[15] rs2_data[16] rs2_data[17] rs2_data[18] rs2_data[19] rs2_data[20] rs2_data[21] rs2_data[22] rs2_data[23] rs2_data[24] rs2_data[25] rs2_data[26] rs2_data[27] rs2_data[28] rs2_data[29] rs2_data[30] rs2_data[31]
-.outputs bus_address[0] bus_address[1] bus_address[2] bus_address[3] bus_address[4] bus_address[5] bus_address[6] bus_address[7] bus_address[8] bus_address[9] bus_address[10] bus_address[11] bus_address[12] bus_address[13] bus_address[14] bus_address[15] bus_address[16] bus_address[17] bus_address[18] bus_address[19] bus_address[20] bus_address[21] bus_address[22] bus_address[23] bus_address[24] bus_address[25] bus_address[26] bus_address[27] bus_address[28] bus_address[29] bus_address[30] bus_address[31] bus_write_data[0] bus_write_data[1] bus_write_data[2] bus_write_data[3] bus_write_data[4] bus_write_data[5] bus_write_data[6] bus_write_data[7] bus_write_data[8] bus_write_data[9] bus_write_data[10] bus_write_data[11] bus_write_data[12] bus_write_data[13] bus_write_data[14] bus_write_data[15] bus_write_data[16] bus_write_data[17] bus_write_data[18] bus_write_data[19] bus_write_data[20] bus_write_data[21] bus_write_data[22] bus_write_data[23] bus_write_data[24] bus_write_data[25] bus_write_data[26] bus_write_data[27] bus_write_data[28] bus_write_data[29] bus_write_data[30] bus_write_data[31] bus_byte_enable[0] bus_byte_enable[1] bus_byte_enable[2] bus_byte_enable[3] bus_read_enable bus_write_enable pc[0] pc[1] pc[2] pc[3] pc[4] pc[5] pc[6] pc[7] pc[8] pc[9] pc[10] pc[11] pc[12] pc[13] pc[14] pc[15] pc[16] pc[17] pc[18] pc[19] pc[20] pc[21] pc[22] pc[23] pc[24] pc[25] pc[26] pc[27] pc[28] pc[29] pc[30] pc[31] regfile_write_enable rd_address[0] rd_address[1] rd_address[2] rd_address[3] rd_address[4] rs1_address[0] rs1_address[1] rs1_address[2] rs1_address[3] rs1_address[4] rs2_address[0] rs2_address[1] rs2_address[2] rs2_address[3] rs2_address[4] rd_data[0] rd_data[1] rd_data[2] rd_data[3] rd_data[4] rd_data[5] rd_data[6] rd_data[7] rd_data[8] rd_data[9] rd_data[10] rd_data[11] rd_data[12] rd_data[13] rd_data[14] rd_data[15] rd_data[16] rd_data[17] rd_data[18] rd_data[19] rd_data[20] rd_data[21] rd_data[22] rd_data[23] rd_data[24] rd_data[25] rd_data[26] rd_data[27] rd_data[28] rd_data[29] rd_data[30] rd_data[31]
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-.names bus_write_enable write_enable
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-.end
diff --git a/openfpga/test_blif/s298.blif b/openfpga/test_blif/s298.blif
new file mode 100644
index 000000000..c588a6e0a
--- /dev/null
+++ b/openfpga/test_blif/s298.blif
@@ -0,0 +1,90 @@
+# Benchmark "s298" written by ABC on Tue Mar 12 09:40:31 2019
+.model s298
+.inputs clock G0 G1 G2
+.outputs G117 G132 G66 G118 G133 G67
+
+.latch        n21        G10 re      clock  0
+.latch        n26        G11 re      clock  0
+.latch        n31        G12 re      clock  0
+.latch        n36        G13 re      clock  0
+.latch        n41        G14 re      clock  0
+.latch        n46        G15 re      clock  0
+.latch        n51        G66 re      clock  0
+.latch        n55        G67 re      clock  0
+.latch        n59       G117 re      clock  0
+.latch        n63       G118 re      clock  0
+.latch        n67       G132 re      clock  0
+.latch        n71       G133 re      clock  0
+.latch        n75        G22 re      clock  0
+.latch        n80        G23 re      clock  0
+
+.names n56 n57 G10 n63
+0-0 1
+11- 1
+.names G15 G11 G13 G22 G14 G12 n56
+01---- 1
+0-0--- 1
+0--0-- 1
+0---1- 1
+0----1 1
+-11000 1
+.names G14 G13 G12 G118 G11 n57
+01--- 1
+100-0 1
+1-11- 1
+-1-1- 1
+.names n56 n59_1 G10 n67
+0-0 1
+11- 1
+.names G14 G13 G12 G132 G11 n59_1
+100-0 1
+11-1- 1
+1-11- 1
+.names G0 G10 n21
+00 1
+.names G10 G11 G0 G12 G13 n26
+010-- 1
+1001- 1
+100-0 1
+.names G12 G0 G11 G10 n31
+0011 1
+100- 1
+10-0 1
+.names G13 G0 G11 G12 G10 n36
+00111 1
+1001- 1
+1010- 1
+10--0 1
+.names n65 G14 G0 n41
+000 1
+110 1
+.names G23 G10 G13 G11 G12 n65
+1---- 0
+-1100 0
+.names G0 n56 n46
+00 1
+.names n56 G66 G14 G13 G12 n51
+111-1 1
+11-1- 1
+1-01- 1
+.names n56 G13 G14 G11 G67 G12 n55
+1000-- 1
+10-1-0 1
+111-1- 1
+1-1-11 1
+.names n56 G13 G117 G14 G12 G11 n59
+10-0-- 1
+10--01 1
+1111-- 1
+1-111- 1
+.names n56 G14 G12 G13 G133 G11 n71
+1010-1 1
+111-1- 1
+11-11- 1
+.names G2 G22 G0 n75
+010 1
+100 1
+.names G1 G23 G0 n80
+010 1
+100 1
+.end
diff --git a/openfpga/test_script/riscv_core.openfpga b/openfpga/test_script/s298.openfpga
similarity index 74%
rename from openfpga/test_script/riscv_core.openfpga
rename to openfpga/test_script/s298.openfpga
index d2614df44..d9d1e15ca 100644
--- a/openfpga/test_script/riscv_core.openfpga
+++ b/openfpga/test_script/s298.openfpga
@@ -1,2 +1,2 @@
 # Run VPR for the RISC-V core
-vpr ./test_arch/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ./test_blif/riscv_core_lut6.blif
+vpr ./test_arch/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ./test_blif/s298.blif

From 01c80b9126686504884b3960557ae33f638b0555 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 27 Jan 2020 13:39:13 -0700
Subject: [PATCH 024/645] add sample architecture to be used for Openfpga

---
 .../k6_N10_40nm_openfpga.xml                  | 234 ++++++++++++
 openfpga/test_vpr_arch/k6_N10_40nm.xml        | 308 +++++++++++++++
 openfpga/test_vpr_arch/k6_frac_N10_40nm.xml   | 351 ++++++++++++++++++
 ...rac_N10_frac_chain_depop50_mem32K_40nm.xml |   0
 4 files changed, 893 insertions(+)
 create mode 100644 openfpga/test_openfpga_arch/k6_N10_40nm_openfpga.xml
 create mode 100644 openfpga/test_vpr_arch/k6_N10_40nm.xml
 create mode 100644 openfpga/test_vpr_arch/k6_frac_N10_40nm.xml
 rename openfpga/{test_arch => test_vpr_arch}/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml (100%)

diff --git a/openfpga/test_openfpga_arch/k6_N10_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_N10_40nm_openfpga.xml
new file mode 100644
index 000000000..23607e234
--- /dev/null
+++ b/openfpga/test_openfpga_arch/k6_N10_40nm_openfpga.xml
@@ -0,0 +1,234 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <!--mux2to1 subckt_name="mux2to1"/-->
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <!--mux2to1 subckt_name="mux2to1"/-->
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <!--mux2to1 subckt_name="mux2to1"/-->
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <pass_gate_logic circuit_model_name="TGATE"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="lut5" prefix="lut5" dump_structural_verilog="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="5"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="32"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <pass_gate_logic circuit_model_name="TGATE"/>
+       <port type="input" prefix="pReset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="Qb" size="1"/>
+       <port type="clock" prefix="prog_clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="inout" prefix="pad" size="1"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+      <port type="input" prefix="outpad" size="1"/>
+      <port type="output" prefix="inpad" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut6].ble6.lut6" circuit_model_name="lut6"/>
+    <pb_type name="clb.fle[n1_lut6].ble6.ff" circuit_model_name="static_dff"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>
+<openfpga_simulation_setting>
+  <clock_setting>
+    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
+    <programming frequency="10e6"/>
+  </clock_setting>
+  <simulator_option>
+    <operating_condition temperature="25"/>
+    <output_log verbose="false" captab="false"/>
+    <accuracy type="abs" value="1e-13"/>
+    <runtime fast_simulation="true"/>
+  </simulator_option>
+  <monte_carlo num_simulation_points="2"/>
+  <measurement_setting>
+    <slew>
+      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
+      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
+    </slew>
+    <delay>
+      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
+      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
+    </delay>
+  </measurement_setting>
+  <stimulus>
+    <clock>
+      <rise slew_type="abs" slew_time="20e-12" />
+      <fall slew_type="abs" slew_time="20e-12" />
+    </clock>
+    <input>
+      <rise slew_type="abs" slew_time="25e-12" />
+      <fall slew_type="abs" slew_time="25e-12" />
+    </input>
+  </stimulus>
+</openfpga_simulation_setting>
diff --git a/openfpga/test_vpr_arch/k6_N10_40nm.xml b/openfpga/test_vpr_arch/k6_N10_40nm.xml
new file mode 100644
index 000000000..d2501969d
--- /dev/null
+++ b/openfpga/test_vpr_arch/k6_N10_40nm.xml
@@ -0,0 +1,308 @@
+<!-- 
+  Architecture with no fracturable LUTs
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 6, N = 10
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Details on Modelling:
+
+  Based on flagship k6_frac_N10_mem32K_40nm.xml architecture.  This architecture has no fracturable LUTs nor any heterogeneous blocks.
+
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <tile name="io" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <clock name="clock" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad io.clock</loc>
+        <loc side="top">io.outpad io.inpad io.clock</loc>
+        <loc side="right">io.outpad io.inpad io.clock</loc>
+        <loc side="bottom">io.outpad io.inpad io.clock</loc>
+      </pinlocations>
+    </tile>
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I" num_pins="40" equivalent="full"/>
+      <output name="O" num_pins="10" equivalent="instance"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="spread"/>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout>
+    <auto_layout aspect_ratio="1.0">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </auto_layout>
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	  -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+	       book area formula. This means the mux transistors are about 5x minimum drive strength.
+	       We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+	       mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+	       the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+	       by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+	       buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+	       I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+	       (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+	       The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+	       2.5x when looking up in Jeff's tables.
+	       Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+	       This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+			     With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+			     reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <clock name="clock" num_pins="1"/>
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" disabled_in_pack="true">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I" num_pins="40" equivalent="full"/>
+      <output name="O" num_pins="10" equivalent="instance"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe basic logic element.  
+             Each basic logic element has a 6-LUT that can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="10">
+        <input name="in" num_pins="6"/>
+        <output name="out" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- 6-LUT mode definition begin -->
+        <mode name="n1_lut6">
+          <!-- Define 6-LUT mode -->
+          <pb_type name="ble6" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Define LUT -->
+            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="6" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->
+              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                261e-12
+                261e-12
+                261e-12
+                261e-12
+                261e-12
+                261e-12
+              </delay_matrix>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+              <direct name="direct2" input="lut6.out" output="ff.D">
+                <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
+                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="ble6.in"/>
+            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+          </interconnect>
+        </mode>
+        <!-- 6-LUT mode definition end -->
+      </pb_type>
+      <interconnect>
+        <!-- We use a full crossbar to get logical equivalence at inputs of CLB 
+		     The delays below come from Stratix IV. the delay through a connection block
+		     input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+		     delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+		     delay within the crossbar is 95 ps. 
+		     The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+		     Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+		     25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+		     to get the part that should be marked on the crossbar.	 -->
+        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
+          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
+          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
+        </complete>
+        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+        </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+               By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+               then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+               naive specification).
+          -->
+        <direct name="clbouts1" input="fle[9:0].out" output="clb.O"/>
+      </interconnect>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- Place this general purpose logic block in any unspecified column -->
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+  </complexblocklist>
+  <power>
+    <local_interconnect C_wire="2.5e-10"/>
+    <mux_transistor_size mux_transistor_size="3"/>
+    <FF_size FF_size="4"/>
+    <LUT_transistor_size LUT_transistor_size="4"/>
+  </power>
+  <clocks>
+    <clock buffer_size="auto" C_wire="2.5e-10"/>
+  </clocks>
+</architecture>
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml
new file mode 100644
index 000000000..4da00d67a
--- /dev/null
+++ b/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml
@@ -0,0 +1,351 @@
+<!-- 
+  Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0.
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with all 5 inputs shared) 
+    with optionally registered outputs
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Details on Modelling:
+
+  Based on flagship k6_frac_N10_mem32K_40nm.xml architecture.
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+  </models>
+  <tiles>
+    <tile name="io" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <clock name="clock" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad io.clock</loc>
+        <loc side="top">io.outpad io.inpad io.clock</loc>
+        <loc side="right">io.outpad io.inpad io.clock</loc>
+        <loc side="bottom">io.outpad io.inpad io.clock</loc>
+      </pinlocations>
+    </tile>
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I" num_pins="40" equivalent="full"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="spread"/>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout>
+    <auto_layout aspect_ratio="1.0">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </auto_layout>
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	  -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+	       book area formula. This means the mux transistors are about 5x minimum drive strength.
+	       We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+	       mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+	       the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+	       by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+	       buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+	       I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+	       (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+	       The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+	       2.5x when looking up in Jeff's tables.
+	       Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+	       This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+			     With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+			     reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <segment freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <clock name="clock" num_pins="1"/>
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I" num_pins="40" equivalent="full"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe fracturable logic element.  
+             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
+             The outputs of the fracturable logic element can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="10">
+        <input name="in" num_pins="6"/>
+        <output name="out" num_pins="2"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- Dual 5-LUT mode definition begin -->
+        <mode name="n2_lut5">
+          <pb_type name="lut5inter" num_pb="1">
+            <input name="in" num_pins="5"/>
+            <output name="out" num_pins="2"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="ble5" num_pb="2">
+              <input name="in" num_pins="5"/>
+              <output name="out" num_pins="1"/>
+              <clock name="clk" num_pins="1"/>
+              <!-- Define the LUT -->
+              <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
+                <input name="in" num_pins="5" port_class="lut_in"/>
+                <output name="out" num_pins="1" port_class="lut_out"/>
+                <!-- LUT timing using delay matrix -->
+                <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                           we instead take the average of these numbers to get more stable results
+                      82e-12
+                      173e-12
+                      261e-12
+                      263e-12
+                      398e-12
+                      -->
+                <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
+                  235e-12
+                  235e-12
+                  235e-12
+                  235e-12
+                  235e-12
+                </delay_matrix>
+              </pb_type>
+              <!-- Define the flip-flop -->
+              <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+                <input name="D" num_pins="1" port_class="D"/>
+                <output name="Q" num_pins="1" port_class="Q"/>
+                <clock name="clk" num_pins="1" port_class="clock"/>
+                <T_setup value="66e-12" port="ff.D" clock="clk"/>
+                <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="ble5.in[4:0]" output="lut5[0:0].in[4:0]"/>
+                <direct name="direct2" input="lut5[0:0].out" output="ff[0:0].D">
+                  <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
+                  <pack_pattern name="ble5" in_port="lut5[0:0].out" out_port="ff[0:0].D"/>
+                </direct>
+                <direct name="direct3" input="ble5.clk" output="ff[0:0].clk"/>
+                <mux name="mux1" input="ff[0:0].Q lut5.out[0:0]" output="ble5.out[0:0]">
+                  <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                  <delay_constant max="25e-12" in_port="lut5.out[0:0]" out_port="ble5.out[0:0]"/>
+                  <delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble5.out[0:0]"/>
+                </mux>
+              </interconnect>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="lut5inter.in" output="ble5[0:0].in"/>
+              <direct name="direct2" input="lut5inter.in" output="ble5[1:1].in"/>
+              <direct name="direct3" input="ble5[1:0].out" output="lut5inter.out"/>
+              <complete name="complete1" input="lut5inter.clk" output="ble5[1:0].clk"/>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[4:0]" output="lut5inter.in"/>
+            <direct name="direct2" input="lut5inter.out" output="fle.out"/>
+            <direct name="direct3" input="fle.clk" output="lut5inter.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Dual 5-LUT mode definition end -->
+        <!-- 6-LUT mode definition begin -->
+        <mode name="n1_lut6">
+          <!-- Define 6-LUT mode -->
+          <pb_type name="ble6" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Define LUT -->
+            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="6" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->
+              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                261e-12
+                261e-12
+                261e-12
+                261e-12
+                261e-12
+                261e-12
+              </delay_matrix>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+              <direct name="direct2" input="lut6.out" output="ff.D">
+                <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
+                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="ble6.in"/>
+            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+          </interconnect>
+        </mode>
+        <!-- 6-LUT mode definition end -->
+      </pb_type>
+      <interconnect>
+        <!-- We use a full crossbar to get logical equivalence at inputs of CLB 
+		     The delays below come from Stratix IV. the delay through a connection block
+		     input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+		     delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+		     delay within the crossbar is 95 ps. 
+		     The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+		     Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+		     25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+		     to get the part that should be marked on the crossbar.	 -->
+        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
+          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
+          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
+        </complete>
+        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+        </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+               By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+               then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+               naive specification).
+          -->
+        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
+        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
+      </interconnect>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- Place this general purpose logic block in any unspecified column -->
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+  </complexblocklist>
+  <power>
+    <local_interconnect C_wire="2.5e-10"/>
+    <mux_transistor_size mux_transistor_size="3"/>
+    <FF_size FF_size="4"/>
+    <LUT_transistor_size LUT_transistor_size="4"/>
+  </power>
+  <clocks>
+    <clock buffer_size="auto" C_wire="2.5e-10"/>
+  </clocks>
+</architecture>
diff --git a/openfpga/test_arch/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml
similarity index 100%
rename from openfpga/test_arch/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml
rename to openfpga/test_vpr_arch/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml

From 46b53f20ba8d440e2d523296fe6662d7b3344713 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 27 Jan 2020 13:44:28 -0700
Subject: [PATCH 025/645] add ezgl support in the CMakelist for VPR8

---
 CMakeLists.txt | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/CMakeLists.txt b/CMakeLists.txt
index e1c967e43..f46955c8b 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -46,6 +46,10 @@ project("OPENFPGA" C CXX)
 option(ENABLE_VPR_GRAPHICS "Enables VPR graphics" ON)
 option(ENABLE_VPR_GRAPHICS "Enables build with librtlnumber" OFF)
 
+#Allow the user to decide weather to compile the graphics library
+set(VPR_USE_EZGL "auto" CACHE STRING "Specify whether vpr uses the graphics library")
+set_property(CACHE VPR_USE_EZGL PROPERTY STRINGS auto off on)
+
 # Version number
 set(OPENFPGA_VERSION_MAJOR 1)
 set(OPENFPGA_VERSION_MINOR 0)
@@ -154,6 +158,27 @@ message(STATUS "CMAKE_CXX_FLAGS: ${CMAKE_CXX_FLAGS}")
 #
 enable_testing()
 
+# set VPR_USE_EZGL in the root of VTR to decide whether to add
+# subdirectory of graphics library, which prevents users
+# without gtk/x11 libraries installed to build. VPR_USE_EZGL is
+# being used in both the vpr CMakeLists and libs/EXTERNAL CMakeLists.
+#
+# check if GTK and X11 are installed and turn on/off graphics
+if (VPR_USE_EZGL STREQUAL "auto")
+    find_package(PkgConfig REQUIRED)
+    pkg_check_modules(GTK3 QUIET gtk+-3.0)
+    pkg_check_modules(X11 QUIET x11)
+
+    if(GTK3_FOUND AND X11_FOUND)
+        set(VPR_USE_EZGL "on")
+        message(STATUS "VPR Graphics: Enabled")
+    else()
+        set(VPR_USE_EZGL "off")
+        message(STATUS "VPR Graphics: Disabled (required libraries missing, on debia/ubuntu try: sudo apt install libgtk-3 libx11-dev")
+    endif()
+endif()
+
+
 # 
 # Sub-projects
 #

From a6fbbce33e705b990672aef9f7bf3a554f980243 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 27 Jan 2020 15:31:12 -0700
Subject: [PATCH 026/645] start developing the openfpga arch binding to vpr

---
 libs/libarchfpga/src/physical_types.h        | 16 ++++
 openfpga/src/base/openfpga_context.h         |  5 ++
 openfpga/src/base/openfpga_link_arch.cpp     | 86 ++++++++++++++++++++
 openfpga/src/base/openfpga_link_arch.h       | 22 +++++
 openfpga/src/base/openfpga_setup_command.cpp | 18 +++-
 openfpga/src/base/vpr_pb_type_annotation.cpp | 18 ++++
 openfpga/src/base/vpr_pb_type_annotation.h   | 39 +++++++++
 7 files changed, 203 insertions(+), 1 deletion(-)
 create mode 100644 openfpga/src/base/openfpga_link_arch.cpp
 create mode 100644 openfpga/src/base/openfpga_link_arch.h
 create mode 100644 openfpga/src/base/vpr_pb_type_annotation.cpp
 create mode 100644 openfpga/src/base/vpr_pb_type_annotation.h

diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h
index 36901e6f0..a1e750d69 100644
--- a/libs/libarchfpga/src/physical_types.h
+++ b/libs/libarchfpga/src/physical_types.h
@@ -789,6 +789,22 @@ struct t_pb_type {
     t_pin_to_pin_annotation* annotations = nullptr; /* [0..num_annotations-1] */
     int num_annotations = 0;
 
+    /************************************************************************ 
+     * Xifan Tang: Add useful methods for pb_type 
+     * - A pb_type is considered to be primitive when it has zero modes
+     *   However, this not always true. An exception is the LUT_CLASS
+     *   VPR added two modes by default to a LUT pb_type. Therefore,   
+     *   for LUT_CLASS, it is a primitive when it is binded to a blif model
+     * - A pb_type is the root pb_type when it has no parent mode
+     ************************************************************************/
+    bool is_primitive() const {
+        if (LUT_CLASS == class_type) {
+          return nullptr != blif_model; 
+        }
+        return 0 == num_modes;
+    }
+    bool is_root() const { return parent_mode == nullptr; }
+
     /* Power related members */
     t_pb_type_power* pb_type_power = nullptr;
 
diff --git a/openfpga/src/base/openfpga_context.h b/openfpga/src/base/openfpga_context.h
index c66012615..185a08c5c 100644
--- a/openfpga/src/base/openfpga_context.h
+++ b/openfpga/src/base/openfpga_context.h
@@ -3,6 +3,7 @@
 
 #include "vpr_context.h"
 #include "openfpga_arch.h"
+#include "vpr_pb_type_annotation.h"
 
 /********************************************************************
  * This file includes the declaration of the date structure 
@@ -34,11 +35,15 @@
 class OpenfpgaContext : public Context  {
   public:  /* Public accessors */
     const openfpga::Arch& arch() const { return arch_; }
+    const openfpga::VprPbTypeAnnotation& vpr_pb_type_annotation() const { return vpr_pb_type_annotation_; }
   public:  /* Public mutators */
     openfpga::Arch& mutable_arch() { return arch_; }
+    openfpga::VprPbTypeAnnotation& mutable_vpr_pb_type_annotation() { return vpr_pb_type_annotation_; }
   private: /* Internal data */
     /* Data structure to store information from read_openfpga_arch library */
     openfpga::Arch arch_;
+    /* Annotation to pb_type of VPR */
+    openfpga::VprPbTypeAnnotation vpr_pb_type_annotation_;
 };
 
 #endif
diff --git a/openfpga/src/base/openfpga_link_arch.cpp b/openfpga/src/base/openfpga_link_arch.cpp
new file mode 100644
index 000000000..4af1f00ac
--- /dev/null
+++ b/openfpga/src/base/openfpga_link_arch.cpp
@@ -0,0 +1,86 @@
+/********************************************************************
+ * This file includes functions to read an OpenFPGA architecture file
+ * which are built on the libarchopenfpga library
+ *******************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_log.h"
+
+#include "vpr_pb_type_annotation.h"
+#include "openfpga_link_arch.h"
+
+/* Include global variables of VPR */
+#include "globals.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * This function will recursively traverse pb_type graph to ensure
+ * 1. there is only a physical mode under each pb_type
+ * 2. physical mode appears only when its parent is a physical mode.
+ *******************************************************************/
+static 
+void rec_check_pb_type_physical_mode(const t_pb_type& cur_pb_type) {
+  /* We do not check any primitive pb_type */
+  if (true == cur_pb_type.is_primitive()) {
+    return;
+  }
+
+  /* For non-primitive pb_type: we should iterate over each mode 
+   * Ensure there is only one physical mode
+   */
+
+  /* Traverse all the modes for identifying idle mode */
+  for (int imode = 0; cur_pb_type.num_modes; ++imode) {
+    /* Check each pb_type_child */
+    for (int ichild = 0; ichild < cur_pb_type.modes[imode].num_pb_type_children; ++ichild) { 
+      rec_check_pb_type_physical_mode(cur_pb_type.modes[imode].pb_type_children[ichild]);
+    }
+  }
+}
+
+/********************************************************************
+ * This function will 
+ * - identify the physical pb_type for each multi-mode pb_type in 
+ *   VPR pb_type graph
+ * - identify the physical pb_type for operating pb_types in VPR 
+ *******************************************************************/
+static 
+void build_physical_pb_type_vpr_annotation(const DeviceContext& vpr_device_ctx, 
+                                           const Arch& openfpga_arch,
+                                           VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  /* Walk through the pb_type annotation stored in the openfpga arch */
+  for (const PbTypeAnnotation& pb_type_annotation : openfpga_arch.pb_type_annotations) {
+    /* Pb type information are located at the logic_block_types in the device context of VPR
+     * We iterate over the vectors and annotate the pb_type  
+     */
+    for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
+      /* By pass nullptr for pb_type head */
+      if (nullptr == lb_type.pb_type) {
+        continue;
+      }
+    }
+  } 
+}
+
+/********************************************************************
+ * Top-level function to link openfpga architecture to VPR, including:
+ * - physical pb_type
+ * - idle pb_type 
+ * - circuit models for pb_type, pb interconnect and routing architecture
+ *******************************************************************/
+void link_arch(OpenfpgaContext& openfpga_context) {
+
+  /* Annotate physical pb_type in the VPR pb_type graph */
+  build_physical_pb_type_vpr_annotation(g_vpr_ctx.device(), openfpga_context.arch(),
+                                        openfpga_context.mutable_vpr_pb_type_annotation());
+
+  /* Annotate idle pb_type in the VPR pb_type graph */
+
+  /* Link physical pb_type to circuit model */
+
+  /* Link routing architecture to circuit model */
+} 
+
+} /* end namespace openfpga */
+
diff --git a/openfpga/src/base/openfpga_link_arch.h b/openfpga/src/base/openfpga_link_arch.h
new file mode 100644
index 000000000..be957c5b0
--- /dev/null
+++ b/openfpga/src/base/openfpga_link_arch.h
@@ -0,0 +1,22 @@
+#ifndef OPENFPGA_LINK_ARCH_COMMAND_H
+#define OPENFPGA_LINK_ARCH_COMMAND_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "command.h"
+#include "command_context.h"
+#include "openfpga_context.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void link_arch(OpenfpgaContext& openfpga_context); 
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/base/openfpga_setup_command.cpp b/openfpga/src/base/openfpga_setup_command.cpp
index 322378b07..fdc7a4e98 100644
--- a/openfpga/src/base/openfpga_setup_command.cpp
+++ b/openfpga/src/base/openfpga_setup_command.cpp
@@ -4,6 +4,7 @@
  * - read_openfpga_arch : read OpenFPGA architecture file
  *******************************************************************/
 #include "openfpga_read_arch.h"
+#include "openfpga_link_arch.h"
 #include "openfpga_setup_command.h"
 
 /* begin namespace openfpga */
@@ -36,8 +37,23 @@ void add_openfpga_setup_commands(openfpga::Shell<OpenfpgaContext>& shell) {
   ShellCommandId shell_cmd_write_arch_id = shell.add_command(shell_cmd_write_arch, "write OpenFPGA architecture file");
   shell.set_command_class(shell_cmd_write_arch_id, openfpga_setup_cmd_class);
   shell.set_command_const_execute_function(shell_cmd_write_arch_id, write_arch);
-  /* The 'write_openfpga_arch' command should be executed before 'read_openfpga_arch' */
+  /* The 'write_openfpga_arch' command should NOT be executed before 'read_openfpga_arch' */
   shell.set_command_dependency(shell_cmd_write_arch_id, std::vector<ShellCommandId>(1, shell_cmd_read_arch_id));
+
+  /* Command 'link_openfpga_arch' */
+  Command shell_cmd_link_openfpga_arch("link_openfpga_arch");
+  
+  /* Add command 'link_openfpga_arch' to the Shell */
+  ShellCommandId shell_cmd_link_openfpga_arch_id = shell.add_command(shell_cmd_link_openfpga_arch, "Bind OpenFPGA architecture to VPR");
+  shell.set_command_class(shell_cmd_link_openfpga_arch_id, openfpga_setup_cmd_class);
+  shell.set_command_execute_function(shell_cmd_link_openfpga_arch_id, link_arch);
+  /* The 'link_openfpga_arch' command should NOT be executed before 'read_openfpga_arch' and 'vpr' */
+  const ShellCommandId& shell_cmd_vpr_id = shell.command("vpr");
+  std::vector<ShellCommandId> cmd_dependency_link_openfpga_arch;
+  cmd_dependency_link_openfpga_arch.push_back(shell_cmd_read_arch_id);
+  cmd_dependency_link_openfpga_arch.push_back(shell_cmd_vpr_id);
+  shell.set_command_dependency(shell_cmd_link_openfpga_arch_id, cmd_dependency_link_openfpga_arch);
+
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/base/vpr_pb_type_annotation.cpp b/openfpga/src/base/vpr_pb_type_annotation.cpp
new file mode 100644
index 000000000..70532cae4
--- /dev/null
+++ b/openfpga/src/base/vpr_pb_type_annotation.cpp
@@ -0,0 +1,18 @@
+/************************************************************************
+ * Member functions for class VprPbTypeAnnotation
+ ***********************************************************************/
+#include "vtr_log.h"
+#include "vtr_assert.h"
+#include "vpr_pb_type_annotation.h"
+
+/* namespace openfpga begins */
+namespace openfpga {
+
+/************************************************************************
+ * Constructors
+ ***********************************************************************/
+VprPbTypeAnnotation::VprPbTypeAnnotation() {
+  return;
+}
+
+} /* End namespace openfpga*/
diff --git a/openfpga/src/base/vpr_pb_type_annotation.h b/openfpga/src/base/vpr_pb_type_annotation.h
new file mode 100644
index 000000000..8fb6318b8
--- /dev/null
+++ b/openfpga/src/base/vpr_pb_type_annotation.h
@@ -0,0 +1,39 @@
+#ifndef VPR_PB_TYPE_ANNOTATION_H
+#define VPR_PB_TYPE_ANNOTATION_H
+
+/********************************************************************
+ * Include header files required by the data structure definition
+ *******************************************************************/
+#include <map> 
+
+/* Header from archfpga library */
+#include "physical_types.h"
+
+/* Header from openfpgautil library */
+#include "circuit_library.h"
+
+/* Begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * This is the critical data structure to link the pb_type in VPR
+ * to openfpga annotations
+ * With a given pb_type pointer, it aims to identify:
+ * 1. if the pb_type is a physical pb_type or a operating pb_type
+ * 2. what is the circuit model id linked to a physical pb_type
+ * 3. what is the physical pb_type for an operating pb_type
+ * 4. what is the mode pointer that represents the physical mode for a pb_type
+ *******************************************************************/
+class VprPbTypeAnnotation {
+  public:  /* Constructor */
+    VprPbTypeAnnotation();
+  private: /* Internal data */
+    std::map<t_pb_type*, bool> is_physical_pb_types_;
+    std::map<t_pb_type*, t_pb_type*> physical_pb_types_;
+    std::map<t_pb_type*, t_mode*> physical_pb_modes_;
+    std::map<t_pb_type*, CircuitModelId> pb_type_circuit_models_;
+};
+
+} /* End namespace openfpga*/
+
+#endif

From 5ecb7716736278f322c5156f6b5ec8014c448d2c Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 27 Jan 2020 17:43:22 -0700
Subject: [PATCH 027/645] debugging the annotation to physical mode of pb_types

---
 libopenfpga/libopenfpgashell/src/shell.tpp   |   4 +
 libs/libarchfpga/src/physical_types.h        |  16 ---
 openfpga/src/base/openfpga_link_arch.cpp     | 110 +++++++++++++++++--
 openfpga/src/base/openfpga_link_arch.h       |   2 -
 openfpga/src/base/openfpga_setup_command.cpp |   2 +-
 openfpga/src/base/pb_type_utils.cpp          |  59 ++++++++++
 openfpga/src/base/pb_type_utils.h            |  26 +++++
 openfpga/src/base/vpr_pb_type_annotation.cpp |  26 +++++
 openfpga/src/base/vpr_pb_type_annotation.h   |   4 +
 openfpga/src/vpr_wrapper/vpr_command.cpp     |   4 +-
 openfpga/test_script/s298.openfpga           |  10 +-
 11 files changed, 231 insertions(+), 32 deletions(-)
 create mode 100644 openfpga/src/base/pb_type_utils.cpp
 create mode 100644 openfpga/src/base/pb_type_utils.h

diff --git a/libopenfpga/libopenfpgashell/src/shell.tpp b/libopenfpga/libopenfpgashell/src/shell.tpp
index 0a52fda0b..9d5f8833e 100644
--- a/libopenfpga/libopenfpgashell/src/shell.tpp
+++ b/libopenfpga/libopenfpgashell/src/shell.tpp
@@ -390,6 +390,10 @@ void Shell<T>::execute_command(const char* cmd_line,
       free(argv[itok]);
     }
     free(argv);
+
+    /* Change the status of the command */
+    command_status_[cmd_id] = true;
+
     /* Finish for macro command, return */
     return;
   }
diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h
index a1e750d69..36901e6f0 100644
--- a/libs/libarchfpga/src/physical_types.h
+++ b/libs/libarchfpga/src/physical_types.h
@@ -789,22 +789,6 @@ struct t_pb_type {
     t_pin_to_pin_annotation* annotations = nullptr; /* [0..num_annotations-1] */
     int num_annotations = 0;
 
-    /************************************************************************ 
-     * Xifan Tang: Add useful methods for pb_type 
-     * - A pb_type is considered to be primitive when it has zero modes
-     *   However, this not always true. An exception is the LUT_CLASS
-     *   VPR added two modes by default to a LUT pb_type. Therefore,   
-     *   for LUT_CLASS, it is a primitive when it is binded to a blif model
-     * - A pb_type is the root pb_type when it has no parent mode
-     ************************************************************************/
-    bool is_primitive() const {
-        if (LUT_CLASS == class_type) {
-          return nullptr != blif_model; 
-        }
-        return 0 == num_modes;
-    }
-    bool is_root() const { return parent_mode == nullptr; }
-
     /* Power related members */
     t_pb_type_power* pb_type_power = nullptr;
 
diff --git a/openfpga/src/base/openfpga_link_arch.cpp b/openfpga/src/base/openfpga_link_arch.cpp
index 4af1f00ac..239829e8e 100644
--- a/openfpga/src/base/openfpga_link_arch.cpp
+++ b/openfpga/src/base/openfpga_link_arch.cpp
@@ -3,9 +3,11 @@
  * which are built on the libarchopenfpga library
  *******************************************************************/
 /* Headers from vtrutil library */
+#include "vtr_assert.h"
 #include "vtr_log.h"
 
 #include "vpr_pb_type_annotation.h"
+#include "pb_type_utils.h"
 #include "openfpga_link_arch.h"
 
 /* Include global variables of VPR */
@@ -14,15 +16,57 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
+/********************************************************************
+ * This function will traverse pb_type graph from its top to find
+ * a pb_type with a given name as well as its hierarchy 
+ *******************************************************************/
+static 
+t_pb_type* try_find_pb_type_with_given_path(t_pb_type* top_pb_type, 
+                                            const std::vector<std::string>& target_pb_type_names, 
+                                            const std::vector<std::string>& target_pb_mode_names) {
+  /* Ensure that number of parent names and modes matches */
+  VTR_ASSERT_SAFE(target_pb_type_names.size() == target_pb_mode_names.size() + 1);
+
+  t_pb_type* cur_pb_type = top_pb_type;
+
+  /* We start from the first element of the parent names and parent modes.
+   * If the pb_type does not match in name, we fail 
+   * If we cannot find a mode match the name, we fail 
+   */
+  for (size_t i = 0; i < target_pb_type_names.size() - 1; ++i) {
+    /* If this level does not match, search fail */
+    if (target_pb_type_names[i] != std::string(cur_pb_type->name)) {
+      return nullptr;
+    }
+    /* Find if the mode matches */
+    t_mode* cur_mode = find_pb_type_mode(cur_pb_type, target_pb_mode_names[i].c_str()); 
+    if (nullptr == cur_mode) {
+      return nullptr;
+    }
+    /* Go to the next level of pb_type */
+    cur_pb_type = find_mode_child_pb_type(cur_mode, target_pb_type_names[i + 1].c_str());
+    if (nullptr == cur_pb_type) {
+      return nullptr;
+    }
+    /* If this is already the last pb_type in the list, this is what we want */
+    if (i == target_pb_type_names.size() - 1) {
+      return cur_pb_type;
+    }
+  }
+
+  /* Reach here, it means we find nothing */
+  return nullptr;
+}
+
 /********************************************************************
  * This function will recursively traverse pb_type graph to ensure
  * 1. there is only a physical mode under each pb_type
  * 2. physical mode appears only when its parent is a physical mode.
  *******************************************************************/
 static 
-void rec_check_pb_type_physical_mode(const t_pb_type& cur_pb_type) {
+void rec_check_pb_type_physical_mode(t_pb_type* cur_pb_type) {
   /* We do not check any primitive pb_type */
-  if (true == cur_pb_type.is_primitive()) {
+  if (true == is_primitive_pb_type(cur_pb_type)) {
     return;
   }
 
@@ -31,10 +75,10 @@ void rec_check_pb_type_physical_mode(const t_pb_type& cur_pb_type) {
    */
 
   /* Traverse all the modes for identifying idle mode */
-  for (int imode = 0; cur_pb_type.num_modes; ++imode) {
+  for (int imode = 0; cur_pb_type->num_modes; ++imode) {
     /* Check each pb_type_child */
-    for (int ichild = 0; ichild < cur_pb_type.modes[imode].num_pb_type_children; ++ichild) { 
-      rec_check_pb_type_physical_mode(cur_pb_type.modes[imode].pb_type_children[ichild]);
+    for (int ichild = 0; ichild < cur_pb_type->modes[imode].num_pb_type_children; ++ichild) { 
+      rec_check_pb_type_physical_mode(&(cur_pb_type->modes[imode].pb_type_children[ichild]));
     }
   }
 }
@@ -46,19 +90,68 @@ void rec_check_pb_type_physical_mode(const t_pb_type& cur_pb_type) {
  * - identify the physical pb_type for operating pb_types in VPR 
  *******************************************************************/
 static 
-void build_physical_pb_type_vpr_annotation(const DeviceContext& vpr_device_ctx, 
+void build_vpr_physical_pb_type_annotation(const DeviceContext& vpr_device_ctx, 
                                            const Arch& openfpga_arch,
                                            VprPbTypeAnnotation& vpr_pb_type_annotation) {
   /* Walk through the pb_type annotation stored in the openfpga arch */
   for (const PbTypeAnnotation& pb_type_annotation : openfpga_arch.pb_type_annotations) {
+    /* Since our target is to annotate the physical mode name, 
+     * we can skip those has not physical mode defined
+     */
+    if (true == pb_type_annotation.physical_mode_name().empty()) {
+      continue;
+    } 
+
+    /* Identify if the pb_type is operating or physical,
+     * For operating pb_type, get the full name of operating pb_type    
+     * For physical pb_type, get the full name of physical pb_type    
+     */
+    std::vector<std::string> target_pb_type_names;
+    std::vector<std::string> target_pb_mode_names;
+
+    if (true == pb_type_annotation.is_operating_pb_type()) {
+      target_pb_type_names = pb_type_annotation.operating_parent_pb_type_names();
+      target_pb_type_names.push_back(pb_type_annotation.operating_pb_type_name());
+      target_pb_mode_names = pb_type_annotation.operating_parent_mode_names();
+    } 
+
+    if (true == pb_type_annotation.is_physical_pb_type()) {
+      target_pb_type_names = pb_type_annotation.physical_parent_pb_type_names();
+      target_pb_type_names.push_back(pb_type_annotation.physical_pb_type_name());
+      target_pb_mode_names = pb_type_annotation.physical_parent_mode_names();
+    } 
+
+    /* We must have at least one pb_type in the list */
+    VTR_ASSERT_SAFE(0 < target_pb_type_names.size());
+
     /* Pb type information are located at the logic_block_types in the device context of VPR
-     * We iterate over the vectors and annotate the pb_type  
+     * We iterate over the vectors and find the pb_type matches the parent_pb_type_name
      */
     for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
       /* By pass nullptr for pb_type head */
       if (nullptr == lb_type.pb_type) {
         continue;
       }
+      /* Check the name of the top-level pb_type, if it does not match, we can bypass */
+      if (target_pb_type_names[0] != std::string(lb_type.pb_type->name)) {
+        continue;
+      }
+      /* Match the name in the top-level, we go further to search the pb_type in the graph */
+      t_pb_type* target_pb_type = try_find_pb_type_with_given_path(lb_type.pb_type, target_pb_type_names, 
+                                                                   target_pb_mode_names);
+      if (nullptr == target_pb_type) {
+        /* Not found, error out! */
+        VTR_LOG_ERROR("Unable to find the pb_type '%s' in VPR architecture definition!\n",
+                      target_pb_type_names.back().c_str());
+      }
+
+      /* Found, we update the annotation by assigning the physical mode */
+      t_mode* physical_mode = find_pb_type_mode(target_pb_type, pb_type_annotation.physical_mode_name().c_str());
+      vpr_pb_type_annotation.add_pb_type_physical_mode(target_pb_type, physical_mode);
+      
+      /* Give a message */
+      VTR_LOG("Annotate pb_type '%s' with physical mode '%s'\n",
+              target_pb_type->name, physical_mode->name);
     }
   } 
 }
@@ -72,7 +165,7 @@ void build_physical_pb_type_vpr_annotation(const DeviceContext& vpr_device_ctx,
 void link_arch(OpenfpgaContext& openfpga_context) {
 
   /* Annotate physical pb_type in the VPR pb_type graph */
-  build_physical_pb_type_vpr_annotation(g_vpr_ctx.device(), openfpga_context.arch(),
+  build_vpr_physical_pb_type_annotation(g_vpr_ctx.device(), openfpga_context.arch(),
                                         openfpga_context.mutable_vpr_pb_type_annotation());
 
   /* Annotate idle pb_type in the VPR pb_type graph */
@@ -83,4 +176,3 @@ void link_arch(OpenfpgaContext& openfpga_context) {
 } 
 
 } /* end namespace openfpga */
-
diff --git a/openfpga/src/base/openfpga_link_arch.h b/openfpga/src/base/openfpga_link_arch.h
index be957c5b0..c36c57711 100644
--- a/openfpga/src/base/openfpga_link_arch.h
+++ b/openfpga/src/base/openfpga_link_arch.h
@@ -4,8 +4,6 @@
 /********************************************************************
  * Include header files that are required by function declaration
  *******************************************************************/
-#include "command.h"
-#include "command_context.h"
 #include "openfpga_context.h"
 
 /********************************************************************
diff --git a/openfpga/src/base/openfpga_setup_command.cpp b/openfpga/src/base/openfpga_setup_command.cpp
index fdc7a4e98..af078446a 100644
--- a/openfpga/src/base/openfpga_setup_command.cpp
+++ b/openfpga/src/base/openfpga_setup_command.cpp
@@ -48,7 +48,7 @@ void add_openfpga_setup_commands(openfpga::Shell<OpenfpgaContext>& shell) {
   shell.set_command_class(shell_cmd_link_openfpga_arch_id, openfpga_setup_cmd_class);
   shell.set_command_execute_function(shell_cmd_link_openfpga_arch_id, link_arch);
   /* The 'link_openfpga_arch' command should NOT be executed before 'read_openfpga_arch' and 'vpr' */
-  const ShellCommandId& shell_cmd_vpr_id = shell.command("vpr");
+  const ShellCommandId& shell_cmd_vpr_id = shell.command(std::string("vpr"));
   std::vector<ShellCommandId> cmd_dependency_link_openfpga_arch;
   cmd_dependency_link_openfpga_arch.push_back(shell_cmd_read_arch_id);
   cmd_dependency_link_openfpga_arch.push_back(shell_cmd_vpr_id);
diff --git a/openfpga/src/base/pb_type_utils.cpp b/openfpga/src/base/pb_type_utils.cpp
new file mode 100644
index 000000000..8eb3c42a1
--- /dev/null
+++ b/openfpga/src/base/pb_type_utils.cpp
@@ -0,0 +1,59 @@
+/********************************************************************
+ * This file includes most utilized functions for the pb_type
+ * and pb_graph_node data structure in the OpenFPGA context
+ *******************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_log.h"
+
+#include "pb_type_utils.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/************************************************************************ 
+ * A pb_type is considered to be primitive when it has zero modes
+ * However, this not always true. An exception is the LUT_CLASS
+ * VPR added two modes by default to a LUT pb_type. Therefore,   
+ * for LUT_CLASS, it is a primitive when it is binded to a blif model
+ ************************************************************************/
+bool is_primitive_pb_type(t_pb_type* pb_type) {
+  if (LUT_CLASS == pb_type->class_type) {
+    return nullptr != pb_type->blif_model; 
+  }
+  return 0 == pb_type->num_modes;
+}
+
+/************************************************************************ 
+ * A pb_type is the root pb_type when it has no parent mode
+ ************************************************************************/
+bool is_root_pb_type(t_pb_type* pb_type) { 
+  return pb_type->parent_mode == nullptr; 
+}
+
+/************************************************************************ 
+ * With a given mode name, find the mode pointer
+ ************************************************************************/
+t_mode* find_pb_type_mode(t_pb_type* pb_type, const char* mode_name) {
+  for (int i = 0; i < pb_type->num_modes; ++i) {
+    if (std::string(mode_name) == std::string(pb_type->modes[i].name)) {
+       return &(pb_type->modes[i]);
+    }
+  }
+  /* Note found, return a nullptr */
+  return nullptr;
+}
+
+/************************************************************************ 
+ * With a given pb_type name, find the pb_type pointer
+ ************************************************************************/
+t_pb_type* find_mode_child_pb_type(t_mode* mode, const char* child_name) {
+  for (int i = 0; i < mode->num_pb_type_children; ++i) {
+    if (std::string(child_name) == std::string(mode->pb_type_children[i].name)) {
+       return &(mode->pb_type_children[i]);
+    }
+  }
+  /* Note found, return a nullptr */
+  return nullptr;
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/base/pb_type_utils.h b/openfpga/src/base/pb_type_utils.h
new file mode 100644
index 000000000..c0c1881d5
--- /dev/null
+++ b/openfpga/src/base/pb_type_utils.h
@@ -0,0 +1,26 @@
+#ifndef PB_TYPE_UTILS_H
+#define PB_TYPE_UTILS_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "physical_types.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+bool is_primitive_pb_type(t_pb_type* pb_type); 
+
+bool is_root_pb_type(t_pb_type* pb_type);
+
+t_mode* find_pb_type_mode(t_pb_type* pb_type, const char* mode_name);
+
+t_pb_type* find_mode_child_pb_type(t_mode* mode, const char* child_name);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/base/vpr_pb_type_annotation.cpp b/openfpga/src/base/vpr_pb_type_annotation.cpp
index 70532cae4..1d4beb1ff 100644
--- a/openfpga/src/base/vpr_pb_type_annotation.cpp
+++ b/openfpga/src/base/vpr_pb_type_annotation.cpp
@@ -15,4 +15,30 @@ VprPbTypeAnnotation::VprPbTypeAnnotation() {
   return;
 }
 
+/************************************************************************
+ * Public mutators
+ ***********************************************************************/
+t_mode* VprPbTypeAnnotation::physical_mode(t_pb_type* pb_type) const {
+  /* Ensure that the pb_type is in the list */
+  std::map<t_pb_type*, t_mode*>::const_iterator it = physical_pb_modes_.find(pb_type);
+  if (it == physical_pb_modes_.end()) {
+    return nullptr;
+  }
+  return physical_pb_modes_.at(pb_type);
+}
+
+/************************************************************************
+ * Public mutators
+ ***********************************************************************/
+void VprPbTypeAnnotation::add_pb_type_physical_mode(t_pb_type* pb_type, t_mode* physical_mode) {
+  /* Warn any override attempt */
+  std::map<t_pb_type*, t_mode*>::const_iterator it = physical_pb_modes_.find(pb_type);
+  if (it != physical_pb_modes_.end()) {
+    VTR_LOG_WARN("Override the annotation between pb_type '%s' and it physical mode '%s'!\n",
+                 pb_type->name, physical_mode->name);
+  }
+
+  physical_pb_modes_[pb_type] = physical_mode;
+}
+
 } /* End namespace openfpga*/
diff --git a/openfpga/src/base/vpr_pb_type_annotation.h b/openfpga/src/base/vpr_pb_type_annotation.h
index 8fb6318b8..5410a7ca9 100644
--- a/openfpga/src/base/vpr_pb_type_annotation.h
+++ b/openfpga/src/base/vpr_pb_type_annotation.h
@@ -27,6 +27,10 @@ namespace openfpga {
 class VprPbTypeAnnotation {
   public:  /* Constructor */
     VprPbTypeAnnotation();
+  public:  /* Public accessors */
+    t_mode* physical_mode(t_pb_type* pb_type) const;
+  public:  /* Public mutators */
+    void add_pb_type_physical_mode(t_pb_type* pb_type, t_mode* physical_mode);
   private: /* Internal data */
     std::map<t_pb_type*, bool> is_physical_pb_types_;
     std::map<t_pb_type*, t_pb_type*> physical_pb_types_;
diff --git a/openfpga/src/vpr_wrapper/vpr_command.cpp b/openfpga/src/vpr_wrapper/vpr_command.cpp
index 5baa1ec84..d87ffa32b 100644
--- a/openfpga/src/vpr_wrapper/vpr_command.cpp
+++ b/openfpga/src/vpr_wrapper/vpr_command.cpp
@@ -10,13 +10,13 @@ namespace openfpga {
 
 void add_vpr_commands(openfpga::Shell<OpenfpgaContext>& shell) {
   /* Add a new class of commands */
-  ShellCommandClassId arith_cmd_class = shell.add_command_class("VPR");
+  ShellCommandClassId vpr_cmd_class = shell.add_command_class("VPR");
 
   /* Create a macro command of 'vpr' which will call the main engine of vpr 
    */
   Command shell_cmd_vpr("vpr");
   ShellCommandId shell_cmd_vpr_id = shell.add_command(shell_cmd_vpr, "Start VPR core engine to pack, place and route a BLIF design on a FPGA architecture");
-  shell.set_command_class(shell_cmd_vpr_id, arith_cmd_class);
+  shell.set_command_class(shell_cmd_vpr_id, vpr_cmd_class);
   shell.set_command_execute_function(shell_cmd_vpr_id, vpr::vpr);
 }
 
diff --git a/openfpga/test_script/s298.openfpga b/openfpga/test_script/s298.openfpga
index d9d1e15ca..ad12f4807 100644
--- a/openfpga/test_script/s298.openfpga
+++ b/openfpga/test_script/s298.openfpga
@@ -1,2 +1,8 @@
-# Run VPR for the RISC-V core
-vpr ./test_arch/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ./test_blif/s298.blif
+# Run VPR for the s298 design
+vpr ./test_vpr_arch/k6_N10_40nm.xml ./test_blif/s298.blif
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ./test_openfpga_arch/k6_N10_40nm_openfpga.xml
+
+# Annotate the OpenFPGA architecture to VPR data base
+link_openfpga_arch

From df056f5d70c9cfe67b71efb2ca2077f978664006 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 27 Jan 2020 17:56:24 -0700
Subject: [PATCH 028/645] openfpga shell will stay in interactive mode after
 executing a script

---
 libopenfpga/libopenfpgashell/src/shell.h   |  2 +-
 libopenfpga/libopenfpgashell/src/shell.tpp | 17 +++++++++++------
 openfpga/src/base/openfpga_link_arch.cpp   |  1 +
 3 files changed, 13 insertions(+), 7 deletions(-)

diff --git a/libopenfpga/libopenfpgashell/src/shell.h b/libopenfpga/libopenfpgashell/src/shell.h
index 415fc1b1c..427580010 100644
--- a/libopenfpga/libopenfpgashell/src/shell.h
+++ b/libopenfpga/libopenfpgashell/src/shell.h
@@ -115,7 +115,7 @@ class Shell {
     bool valid_command_class_id(const ShellCommandClassId& cmd_class_id) const;
   public: /* Public executors */
     /* Start the interactive mode, where users will type-in command by command */
-    void run_interactive_mode(T& context);
+    void run_interactive_mode(T& context, const bool& quiet_mode = false);
     /* Start the script mode, where users provide a file which includes all the commands to run */
     void run_script_mode(const char* script_file_name, T& context);
     /* Print all the commands by their classes. This is actually the help desk */
diff --git a/libopenfpga/libopenfpgashell/src/shell.tpp b/libopenfpga/libopenfpgashell/src/shell.tpp
index 9d5f8833e..72ebe5168 100644
--- a/libopenfpga/libopenfpgashell/src/shell.tpp
+++ b/libopenfpga/libopenfpgashell/src/shell.tpp
@@ -239,13 +239,15 @@ ShellCommandClassId Shell<T>::add_command_class(const char* name) {
  * Public executors
  ***********************************************************************/
 template <class T>
-void Shell<T>::run_interactive_mode(T& context) {
-  VTR_LOG("Start interactive mode of %s...\n",
-          name().c_str());
+void Shell<T>::run_interactive_mode(T& context, const bool& quiet_mode) {
+  if (false == quiet_mode) {
+    VTR_LOG("Start interactive mode of %s...\n",
+            name().c_str());
 
-  /* Print the title of the shell */
-  if (!title().empty()) {
-    VTR_LOG("%s\n", title().c_str());
+    /* Print the title of the shell */
+    if (!title().empty()) {
+      VTR_LOG("%s\n", title().c_str());
+    }
   }
 
   /* Wait for users input and execute the command */
@@ -306,6 +308,9 @@ void Shell<T>::run_script_mode(const char* script_file_name, T& context) {
     }
   }
   fp.close();
+
+  /* Return to interactive mode, stay tuned */
+  run_interactive_mode(context, true); 
 }
 
 template <class T>
diff --git a/openfpga/src/base/openfpga_link_arch.cpp b/openfpga/src/base/openfpga_link_arch.cpp
index 239829e8e..e4bf6bbed 100644
--- a/openfpga/src/base/openfpga_link_arch.cpp
+++ b/openfpga/src/base/openfpga_link_arch.cpp
@@ -143,6 +143,7 @@ void build_vpr_physical_pb_type_annotation(const DeviceContext& vpr_device_ctx,
         /* Not found, error out! */
         VTR_LOG_ERROR("Unable to find the pb_type '%s' in VPR architecture definition!\n",
                       target_pb_type_names.back().c_str());
+        break;
       }
 
       /* Found, we update the annotation by assigning the physical mode */

From b8c504f57434dfcbfd46289f92c230d95400843f Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 27 Jan 2020 19:49:05 -0700
Subject: [PATCH 029/645] Do not allow vpr to free everything when it is done.
 So that we can have access to their device data

---
 openfpga/src/base/openfpga_link_arch.cpp | 29 ++++++++++++++++++++----
 openfpga/src/vpr_wrapper/vpr_main.cpp    |  8 ++++---
 2 files changed, 30 insertions(+), 7 deletions(-)

diff --git a/openfpga/src/base/openfpga_link_arch.cpp b/openfpga/src/base/openfpga_link_arch.cpp
index e4bf6bbed..d0da76280 100644
--- a/openfpga/src/base/openfpga_link_arch.cpp
+++ b/openfpga/src/base/openfpga_link_arch.cpp
@@ -29,6 +29,15 @@ t_pb_type* try_find_pb_type_with_given_path(t_pb_type* top_pb_type,
 
   t_pb_type* cur_pb_type = top_pb_type;
 
+  /* If the top pb_type is what we want, we can return here */
+  if (1 == target_pb_type_names.size()) {
+    if (target_pb_type_names[0] == std::string(top_pb_type->name)) {
+      return top_pb_type;
+    }
+    /* Not match, return null pointer */
+    return nullptr;
+  }
+
   /* We start from the first element of the parent names and parent modes.
    * If the pb_type does not match in name, we fail 
    * If we cannot find a mode match the name, we fail 
@@ -124,9 +133,14 @@ void build_vpr_physical_pb_type_annotation(const DeviceContext& vpr_device_ctx,
     /* We must have at least one pb_type in the list */
     VTR_ASSERT_SAFE(0 < target_pb_type_names.size());
 
+    VTR_LOG("Trying to link pb_type '%s' to vpr architecture\n",
+            target_pb_type_names.back().c_str());
+
     /* Pb type information are located at the logic_block_types in the device context of VPR
      * We iterate over the vectors and find the pb_type matches the parent_pb_type_name
      */
+    bool link_success = false;
+
     for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
       /* By pass nullptr for pb_type head */
       if (nullptr == lb_type.pb_type) {
@@ -140,10 +154,7 @@ void build_vpr_physical_pb_type_annotation(const DeviceContext& vpr_device_ctx,
       t_pb_type* target_pb_type = try_find_pb_type_with_given_path(lb_type.pb_type, target_pb_type_names, 
                                                                    target_pb_mode_names);
       if (nullptr == target_pb_type) {
-        /* Not found, error out! */
-        VTR_LOG_ERROR("Unable to find the pb_type '%s' in VPR architecture definition!\n",
-                      target_pb_type_names.back().c_str());
-        break;
+        continue;
       }
 
       /* Found, we update the annotation by assigning the physical mode */
@@ -153,6 +164,16 @@ void build_vpr_physical_pb_type_annotation(const DeviceContext& vpr_device_ctx,
       /* Give a message */
       VTR_LOG("Annotate pb_type '%s' with physical mode '%s'\n",
               target_pb_type->name, physical_mode->name);
+
+      link_success = true;
+      break;
+    }
+
+    if (false == link_success) {
+      /* Not found, error out! */
+      VTR_LOG_ERROR("Unable to find the pb_type '%s' in VPR architecture definition!\n",
+                    target_pb_type_names.back().c_str());
+      return;
     }
   } 
 }
diff --git a/openfpga/src/vpr_wrapper/vpr_main.cpp b/openfpga/src/vpr_wrapper/vpr_main.cpp
index 2af952584..bf0f6de91 100644
--- a/openfpga/src/vpr_wrapper/vpr_main.cpp
+++ b/openfpga/src/vpr_wrapper/vpr_main.cpp
@@ -48,7 +48,7 @@ int vpr(int argc, char** argv) {
         vpr_install_signal_handler();
 
         /* Read options, architecture, and circuit netlist */
-        vpr_init(argc, (const char**)argv, &Options, &vpr_setup, &Arch);
+        vpr_init(argc, const_cast<const char**>(argv), &Options, &vpr_setup, &Arch);
 
         if (Options.show_version) {
             return SUCCESS_EXIT_CODE;
@@ -70,8 +70,10 @@ int vpr(int argc, char** argv) {
                 timing_ctx.stats.num_full_hold_updates,
                 timing_ctx.stats.num_full_setup_hold_updates);
 
-        /* free data structures */
-        vpr_free_all(Arch, vpr_setup);
+        /* TODO: move this to the end of flow 
+         * free data structures 
+         */
+        /* vpr_free_all(Arch, vpr_setup); */
 
         VTR_LOG("VPR suceeded\n");
 

From f99dd4c2614c4e421c940c9bcb0ff15dd831f459 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 27 Jan 2020 20:40:18 -0700
Subject: [PATCH 030/645] debugged pb_type physical mode annotation

---
 openfpga/src/base/openfpga_link_arch.cpp | 156 +++++++++++++++++------
 openfpga/src/base/pb_type_utils.cpp      |  10 +-
 2 files changed, 128 insertions(+), 38 deletions(-)

diff --git a/openfpga/src/base/openfpga_link_arch.cpp b/openfpga/src/base/openfpga_link_arch.cpp
index d0da76280..a3e695345 100644
--- a/openfpga/src/base/openfpga_link_arch.cpp
+++ b/openfpga/src/base/openfpga_link_arch.cpp
@@ -3,6 +3,7 @@
  * which are built on the libarchopenfpga library
  *******************************************************************/
 /* Headers from vtrutil library */
+#include "vtr_time.h"
 #include "vtr_assert.h"
 #include "vtr_log.h"
 
@@ -68,40 +69,14 @@ t_pb_type* try_find_pb_type_with_given_path(t_pb_type* top_pb_type,
 }
 
 /********************************************************************
- * This function will recursively traverse pb_type graph to ensure
- * 1. there is only a physical mode under each pb_type
- * 2. physical mode appears only when its parent is a physical mode.
+ * This function will identify the physical pb_type for each multi-mode 
+ * pb_type in VPR pb_type graph by following the explicit definition 
+ * in OpenFPGA architecture XML
  *******************************************************************/
 static 
-void rec_check_pb_type_physical_mode(t_pb_type* cur_pb_type) {
-  /* We do not check any primitive pb_type */
-  if (true == is_primitive_pb_type(cur_pb_type)) {
-    return;
-  }
-
-  /* For non-primitive pb_type: we should iterate over each mode 
-   * Ensure there is only one physical mode
-   */
-
-  /* Traverse all the modes for identifying idle mode */
-  for (int imode = 0; cur_pb_type->num_modes; ++imode) {
-    /* Check each pb_type_child */
-    for (int ichild = 0; ichild < cur_pb_type->modes[imode].num_pb_type_children; ++ichild) { 
-      rec_check_pb_type_physical_mode(&(cur_pb_type->modes[imode].pb_type_children[ichild]));
-    }
-  }
-}
-
-/********************************************************************
- * This function will 
- * - identify the physical pb_type for each multi-mode pb_type in 
- *   VPR pb_type graph
- * - identify the physical pb_type for operating pb_types in VPR 
- *******************************************************************/
-static 
-void build_vpr_physical_pb_type_annotation(const DeviceContext& vpr_device_ctx, 
-                                           const Arch& openfpga_arch,
-                                           VprPbTypeAnnotation& vpr_pb_type_annotation) {
+void build_vpr_physical_pb_mode_explicit_annotation(const DeviceContext& vpr_device_ctx, 
+                                                    const Arch& openfpga_arch,
+                                                    VprPbTypeAnnotation& vpr_pb_type_annotation) {
   /* Walk through the pb_type annotation stored in the openfpga arch */
   for (const PbTypeAnnotation& pb_type_annotation : openfpga_arch.pb_type_annotations) {
     /* Since our target is to annotate the physical mode name, 
@@ -133,9 +108,6 @@ void build_vpr_physical_pb_type_annotation(const DeviceContext& vpr_device_ctx,
     /* We must have at least one pb_type in the list */
     VTR_ASSERT_SAFE(0 < target_pb_type_names.size());
 
-    VTR_LOG("Trying to link pb_type '%s' to vpr architecture\n",
-            target_pb_type_names.back().c_str());
-
     /* Pb type information are located at the logic_block_types in the device context of VPR
      * We iterate over the vectors and find the pb_type matches the parent_pb_type_name
      */
@@ -178,6 +150,112 @@ void build_vpr_physical_pb_type_annotation(const DeviceContext& vpr_device_ctx,
   } 
 }
 
+/********************************************************************
+ * This function will recursively visit all the pb_type from the top
+ * pb_type in the graph and 
+ * infer the physical pb_type for each multi-mode 
+ * pb_type in VPR pb_type graph without OpenFPGA architecture XML
+ *
+ * The following rule is applied:
+ * if there is only 1 mode under a pb_type, it will be the default 
+ * physical mode for this pb_type
+ *******************************************************************/
+static 
+void rec_infer_vpr_physical_pb_mode_annotation(t_pb_type* cur_pb_type, 
+                                               VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  /* We do not check any primitive pb_type */
+  if (true == is_primitive_pb_type(cur_pb_type)) {
+    return;
+  }
+
+  /* For non-primitive pb_type:
+   * - if there is only one mode, it will be the physical mode
+   *   we just need to make sure that we do not repeatedly annotate this
+   * - if there are multiple modes, we should be able to find a physical mode
+   *   and then go recursively 
+   */
+  t_mode* physical_mode = nullptr;
+
+  if (1 == cur_pb_type->num_modes) {
+    if (nullptr == vpr_pb_type_annotation.physical_mode(cur_pb_type)) {
+      /* Not assigned by explicit annotation, we should infer here */
+      vpr_pb_type_annotation.add_pb_type_physical_mode(cur_pb_type, &(cur_pb_type->modes[0]));
+      VTR_LOG("Implicitly infer physical mode '%s' for pb_type '%s'\n",
+              cur_pb_type->modes[0].name, cur_pb_type->name);
+    }
+  } else {
+    VTR_ASSERT(1 < cur_pb_type->num_modes);
+    if (nullptr == vpr_pb_type_annotation.physical_mode(cur_pb_type)) {
+      /* Not assigned by explicit annotation, we should infer here */
+      vpr_pb_type_annotation.add_pb_type_physical_mode(cur_pb_type, &(cur_pb_type->modes[0]));
+      VTR_LOG_ERROR("Unable to find a physical mode for a multi-mode pb_type '%s'!\n",
+                    cur_pb_type->name);
+      VTR_LOG_ERROR("Please specify in the OpenFPGA architecture\n");
+      return;
+    }
+  }
+
+  /* Get the physical mode from annotation */ 
+  physical_mode = vpr_pb_type_annotation.physical_mode(cur_pb_type);
+
+  VTR_ASSERT(nullptr != physical_mode);
+
+  /* Traverse the pb_type children under the physical mode */
+  for (int ichild = 0; ichild < physical_mode->num_pb_type_children; ++ichild) { 
+    rec_infer_vpr_physical_pb_mode_annotation(&(physical_mode->pb_type_children[ichild]),
+                                              vpr_pb_type_annotation);
+  }
+}
+
+/********************************************************************
+ * This function will infer the physical pb_type for each multi-mode 
+ * pb_type in VPR pb_type graph without OpenFPGA architecture XML
+ *
+ * The following rule is applied:
+ * if there is only 1 mode under a pb_type, it will be the default 
+ * physical mode for this pb_type
+ *
+ * Note: 
+ * This function must be executed AFTER the function
+ *   build_vpr_physical_pb_mode_explicit_annotation()
+ *******************************************************************/
+static 
+void build_vpr_physical_pb_mode_implicit_annotation(const DeviceContext& vpr_device_ctx, 
+                                                    VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
+    /* By pass nullptr for pb_type head */
+    if (nullptr == lb_type.pb_type) {
+      continue;
+    }
+    rec_infer_vpr_physical_pb_mode_annotation(lb_type.pb_type, vpr_pb_type_annotation); 
+  }
+}
+
+/********************************************************************
+ * This function will recursively traverse pb_type graph to ensure
+ * 1. there is only a physical mode under each pb_type
+ * 2. physical mode appears only when its parent is a physical mode.
+ *******************************************************************/
+static 
+void rec_check_pb_type_physical_mode(t_pb_type* cur_pb_type) {
+  /* We do not check any primitive pb_type */
+  if (true == is_primitive_pb_type(cur_pb_type)) {
+    return;
+  }
+
+  /* For non-primitive pb_type: we should iterate over each mode 
+   * Ensure there is only one physical mode
+   */
+
+  /* Traverse all the modes for identifying idle mode */
+  for (int imode = 0; cur_pb_type->num_modes; ++imode) {
+    /* Check each pb_type_child */
+    for (int ichild = 0; ichild < cur_pb_type->modes[imode].num_pb_type_children; ++ichild) { 
+      rec_check_pb_type_physical_mode(&(cur_pb_type->modes[imode].pb_type_children[ichild]));
+    }
+  }
+}
+
 /********************************************************************
  * Top-level function to link openfpga architecture to VPR, including:
  * - physical pb_type
@@ -186,9 +264,13 @@ void build_vpr_physical_pb_type_annotation(const DeviceContext& vpr_device_ctx,
  *******************************************************************/
 void link_arch(OpenfpgaContext& openfpga_context) {
 
+  vtr::ScopedStartFinishTimer timer("Link OpenFPGA architecture to VPR architecture");
+
   /* Annotate physical pb_type in the VPR pb_type graph */
-  build_vpr_physical_pb_type_annotation(g_vpr_ctx.device(), openfpga_context.arch(),
-                                        openfpga_context.mutable_vpr_pb_type_annotation());
+  build_vpr_physical_pb_mode_explicit_annotation(g_vpr_ctx.device(), openfpga_context.arch(),
+                                                 openfpga_context.mutable_vpr_pb_type_annotation());
+  build_vpr_physical_pb_mode_implicit_annotation(g_vpr_ctx.device(), 
+                                                 openfpga_context.mutable_vpr_pb_type_annotation());
 
   /* Annotate idle pb_type in the VPR pb_type graph */
 
diff --git a/openfpga/src/base/pb_type_utils.cpp b/openfpga/src/base/pb_type_utils.cpp
index 8eb3c42a1..7a69ad37c 100644
--- a/openfpga/src/base/pb_type_utils.cpp
+++ b/openfpga/src/base/pb_type_utils.cpp
@@ -3,6 +3,7 @@
  * and pb_graph_node data structure in the OpenFPGA context
  *******************************************************************/
 /* Headers from vtrutil library */
+#include "vtr_assert.h"
 #include "vtr_log.h"
 
 #include "pb_type_utils.h"
@@ -15,10 +16,17 @@ namespace openfpga {
  * However, this not always true. An exception is the LUT_CLASS
  * VPR added two modes by default to a LUT pb_type. Therefore,   
  * for LUT_CLASS, it is a primitive when it is binded to a blif model
+ *
+ * Note: 
+ * - if VPR changes its mode organization for LUT pb_type
+ *   this code should be adapted as well!
  ************************************************************************/
 bool is_primitive_pb_type(t_pb_type* pb_type) {
   if (LUT_CLASS == pb_type->class_type) {
-    return nullptr != pb_type->blif_model; 
+    /* The first mode of LUT is wire, the second is the regular LUT */
+    VTR_ASSERT(std::string("wire") == std::string(pb_type->modes[0].name)); 
+    VTR_ASSERT(std::string(pb_type->name) == std::string(pb_type->modes[1].name)); 
+    return true;
   }
   return 0 == pb_type->num_modes;
 }

From 82f71e82e84e06f644ea3d19f29175d394f31807 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 27 Jan 2020 21:15:32 -0700
Subject: [PATCH 031/645] add check codes for physical mode annotation for
 pb_types

---
 openfpga/src/base/openfpga_link_arch.cpp | 78 +++++++++++++++++++++---
 1 file changed, 69 insertions(+), 9 deletions(-)

diff --git a/openfpga/src/base/openfpga_link_arch.cpp b/openfpga/src/base/openfpga_link_arch.cpp
index a3e695345..d01841074 100644
--- a/openfpga/src/base/openfpga_link_arch.cpp
+++ b/openfpga/src/base/openfpga_link_arch.cpp
@@ -237,22 +237,79 @@ void build_vpr_physical_pb_mode_implicit_annotation(const DeviceContext& vpr_dev
  * 2. physical mode appears only when its parent is a physical mode.
  *******************************************************************/
 static 
-void rec_check_pb_type_physical_mode(t_pb_type* cur_pb_type) {
+void rec_check_vpr_physical_pb_mode_annotation(t_pb_type* cur_pb_type,
+                                               const bool& expect_physical_mode,
+                                               const VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                               size_t& num_err) {
   /* We do not check any primitive pb_type */
   if (true == is_primitive_pb_type(cur_pb_type)) {
     return;
   }
 
-  /* For non-primitive pb_type: we should iterate over each mode 
-   * Ensure there is only one physical mode
+  /* For non-primitive pb_type:
+   * - If we expect a physical mode to exist under this pb_type
+   *   we should be able to find one in the annoation 
+   * - If we do NOT expect a physical mode, make sure we find 
+   *   nothing in the annotation
    */
-
-  /* Traverse all the modes for identifying idle mode */
-  for (int imode = 0; cur_pb_type->num_modes; ++imode) {
-    /* Check each pb_type_child */
-    for (int ichild = 0; ichild < cur_pb_type->modes[imode].num_pb_type_children; ++ichild) { 
-      rec_check_pb_type_physical_mode(&(cur_pb_type->modes[imode].pb_type_children[ichild]));
+  if (true == expect_physical_mode) {
+    if (nullptr == vpr_pb_type_annotation.physical_mode(cur_pb_type)) {
+      VTR_LOG_ERROR("Unable to find a physical mode for a multi-mode pb_type '%s'!\n",
+                    cur_pb_type->name);
+      VTR_LOG_ERROR("Please specify in the OpenFPGA architecture\n");
+      num_err++;
+      return;
     }
+  } else {
+    VTR_ASSERT_SAFE(false == expect_physical_mode);
+    if (nullptr != vpr_pb_type_annotation.physical_mode(cur_pb_type)) {
+      VTR_LOG_ERROR("Find a physical mode '%s' for pb_type '%s' which is not under any physical mode!\n",
+                    vpr_pb_type_annotation.physical_mode(cur_pb_type)->name,
+                    cur_pb_type->name);
+      num_err++;
+      return;
+    }
+  }
+
+  /* Traverse all the modes
+   * - for pb_type children under a physical mode, we expect an physical mode 
+   * - for pb_type children under non-physical mode, we expect no physical mode 
+   */
+  for (int imode = 0; imode < cur_pb_type->num_modes; ++imode) {
+    bool expect_child_physical_mode = false;
+    if (&(cur_pb_type->modes[imode]) == vpr_pb_type_annotation.physical_mode(cur_pb_type)) {
+      expect_child_physical_mode = true && expect_physical_mode; 
+    }
+    for (int ichild = 0; ichild < cur_pb_type->modes[imode].num_pb_type_children; ++ichild) { 
+      rec_check_vpr_physical_pb_mode_annotation(&(cur_pb_type->modes[imode].pb_type_children[ichild]),
+                                                expect_child_physical_mode, vpr_pb_type_annotation,
+                                                num_err);
+    }
+  }
+}
+
+/********************************************************************
+ * This function will check the physical mode annotation for
+ * each pb_type in the device
+ *******************************************************************/
+static 
+void check_vpr_physical_pb_mode_annotation(const DeviceContext& vpr_device_ctx, 
+                                           const VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  size_t num_err = 0;
+
+  for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
+    /* By pass nullptr for pb_type head */
+    if (nullptr == lb_type.pb_type) {
+      continue;
+    }
+    /* Top pb_type should always has a physical mode! */
+    rec_check_vpr_physical_pb_mode_annotation(lb_type.pb_type, true, vpr_pb_type_annotation, num_err);
+  }
+  if (0 == num_err) {
+    VTR_LOG("Check physical mode annotation for pb_types passed.\n");
+  } else {
+    VTR_LOG("Check physical mode annotation for pb_types failed with %ld errors!\n",
+            num_err);
   }
 }
 
@@ -272,6 +329,9 @@ void link_arch(OpenfpgaContext& openfpga_context) {
   build_vpr_physical_pb_mode_implicit_annotation(g_vpr_ctx.device(), 
                                                  openfpga_context.mutable_vpr_pb_type_annotation());
 
+  check_vpr_physical_pb_mode_annotation(g_vpr_ctx.device(), 
+                                        openfpga_context.vpr_pb_type_annotation());
+
   /* Annotate idle pb_type in the VPR pb_type graph */
 
   /* Link physical pb_type to circuit model */

From caeb0bfff89a4b1c09f4dd89be7699618f77aa31 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 28 Jan 2020 14:27:35 -0700
Subject: [PATCH 032/645] add physical pb_type binding for explicit annotations

---
 openfpga/src/base/openfpga_link_arch.cpp     | 167 ++++++++++++++++++-
 openfpga/src/base/pb_type_utils.cpp          |  24 +++
 openfpga/src/base/pb_type_utils.h            |   5 +
 openfpga/src/base/vpr_pb_type_annotation.cpp |  64 +++++++
 openfpga/src/base/vpr_pb_type_annotation.h   |  47 ++++++
 5 files changed, 301 insertions(+), 6 deletions(-)

diff --git a/openfpga/src/base/openfpga_link_arch.cpp b/openfpga/src/base/openfpga_link_arch.cpp
index d01841074..443373d20 100644
--- a/openfpga/src/base/openfpga_link_arch.cpp
+++ b/openfpga/src/base/openfpga_link_arch.cpp
@@ -59,7 +59,7 @@ t_pb_type* try_find_pb_type_with_given_path(t_pb_type* top_pb_type,
       return nullptr;
     }
     /* If this is already the last pb_type in the list, this is what we want */
-    if (i == target_pb_type_names.size() - 1) {
+    if (i + 1 == target_pb_type_names.size() - 1) {
       return cur_pb_type;
     }
   }
@@ -69,7 +69,7 @@ t_pb_type* try_find_pb_type_with_given_path(t_pb_type* top_pb_type,
 }
 
 /********************************************************************
- * This function will identify the physical pb_type for each multi-mode 
+ * This function will identify the physical mode for each multi-mode 
  * pb_type in VPR pb_type graph by following the explicit definition 
  * in OpenFPGA architecture XML
  *******************************************************************/
@@ -153,7 +153,7 @@ void build_vpr_physical_pb_mode_explicit_annotation(const DeviceContext& vpr_dev
 /********************************************************************
  * This function will recursively visit all the pb_type from the top
  * pb_type in the graph and 
- * infer the physical pb_type for each multi-mode 
+ * infer the physical mode for each multi-mode 
  * pb_type in VPR pb_type graph without OpenFPGA architecture XML
  *
  * The following rule is applied:
@@ -208,7 +208,7 @@ void rec_infer_vpr_physical_pb_mode_annotation(t_pb_type* cur_pb_type,
 }
 
 /********************************************************************
- * This function will infer the physical pb_type for each multi-mode 
+ * This function will infer the physical mode for each multi-mode 
  * pb_type in VPR pb_type graph without OpenFPGA architecture XML
  *
  * The following rule is applied:
@@ -313,6 +313,159 @@ void check_vpr_physical_pb_mode_annotation(const DeviceContext& vpr_device_ctx,
   }
 }
 
+/********************************************************************
+ * This function aims to make a pair of operating and physical 
+ * pb_types:
+ * - In addition to pairing the pb_types, it will pair the ports of the pb_types
+ * - For the ports which are explicited annotated as physical pin mapping 
+ *   in the pb_type annotation. 
+ *   We will check the port range and create a pair 
+ * - For the ports which are not specified in the pb_type annotation
+ *   we assume their physical ports share the same as the operating ports
+ *   We will try to find a port in the physical pb_type and check the port range
+ *   If found, we will create a pair 
+ * - All the pairs will be updated in vpr_pb_type_annotation
+ *******************************************************************/
+static 
+bool pair_operating_and_physical_pb_types(t_pb_type* operating_pb_type, 
+                                          t_pb_type* physical_pb_type,
+                                          const PbTypeAnnotation& pb_type_annotation,
+                                          VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  /* Reach here, we should have valid operating and physical pb_types */
+  VTR_ASSERT((nullptr != operating_pb_type) && (nullptr != physical_pb_type));
+  
+  /* Iterate over the ports under the operating pb_type 
+   * For each pin, we will try to find its physical port in the pb_type_annotation
+   * if not found, we assume that the physical port is the same as the operating pb_port
+   */
+  for (t_port* operating_pb_port : pb_type_ports(operating_pb_type)) {
+    /* Try to find the port in the pb_type_annotation */
+    BasicPort expected_physical_pb_port = pb_type_annotation.physical_pb_type_port(std::string(operating_pb_port->name));
+    if (true == expected_physical_pb_port.get_name().empty()) {
+      /* Not found, we reset the port information to be consistent as the operating pb_port */
+      expected_physical_pb_port.set_name(std::string(operating_pb_port->name));
+      expected_physical_pb_port.set_width(operating_pb_port->num_pins);
+    }
+
+    /* Try to find the expected port in the physical pb_type */
+    t_port* physical_pb_port = find_pb_type_port(physical_pb_type, expected_physical_pb_port.get_name());
+    /* Not found, mapping fails */
+    if (nullptr == physical_pb_port) {
+      return false;
+    }
+    /* If the port range does not match, mapping fails */
+    if (false == expected_physical_pb_port.contained(BasicPort(physical_pb_port->name, physical_pb_port->num_pins))) {
+      return false;
+    }
+    /* Now, port mapping should succeed, we update the vpr_pb_type_annotation */
+    vpr_pb_type_annotation.add_physical_pb_port(operating_pb_port, physical_pb_port);
+    vpr_pb_type_annotation.add_physical_pb_port_range(operating_pb_port, expected_physical_pb_port);
+  }
+
+  /* Now, pb_type mapping should succeed, we update the vpr_pb_type_annotation */
+  vpr_pb_type_annotation.add_physical_pb_type(operating_pb_type, physical_pb_type);
+
+  return true;
+}
+
+/********************************************************************
+ * This function will identify the physical pb_type for each operating 
+ * pb_type in VPR pb_type graph by following the explicit definition 
+ * in OpenFPGA architecture XML
+ *
+ * Note:
+ * - This function should be executed only AFTER the physical mode 
+ *   annotation is completed
+ *******************************************************************/
+static 
+void build_vpr_physical_pb_type_annotation(const DeviceContext& vpr_device_ctx, 
+                                           const Arch& openfpga_arch,
+                                           VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  /* Walk through the pb_type annotation stored in the openfpga arch */
+  for (const PbTypeAnnotation& pb_type_annotation : openfpga_arch.pb_type_annotations) {
+    /* Since our target is to annotate the operating pb_type tp physical pb_type 
+     * we can skip those annotation only for physical pb_type
+     */
+    if (true == pb_type_annotation.is_physical_pb_type()) {
+      continue;
+    }
+
+    VTR_ASSERT(true == pb_type_annotation.is_operating_pb_type());
+
+    /* Collect the information about the full hierarchy of operating pb_type to be annotated */
+    std::vector<std::string> target_op_pb_type_names;
+    std::vector<std::string> target_op_pb_mode_names;
+
+    target_op_pb_type_names = pb_type_annotation.operating_parent_pb_type_names();
+    target_op_pb_type_names.push_back(pb_type_annotation.operating_pb_type_name());
+    target_op_pb_mode_names = pb_type_annotation.operating_parent_mode_names();
+
+    /* Collect the information about the full hierarchy of physical pb_type to be annotated */
+    std::vector<std::string> target_phy_pb_type_names;
+    std::vector<std::string> target_phy_pb_mode_names;
+
+    target_phy_pb_type_names = pb_type_annotation.physical_parent_pb_type_names();
+    target_phy_pb_type_names.push_back(pb_type_annotation.physical_pb_type_name());
+    target_phy_pb_mode_names = pb_type_annotation.physical_parent_mode_names();
+
+    /* We must have at least one pb_type in the list */
+    VTR_ASSERT_SAFE(0 < target_op_pb_type_names.size());
+    VTR_ASSERT_SAFE(0 < target_phy_pb_type_names.size());
+
+    /* Pb type information are located at the logic_block_types in the device context of VPR
+     * We iterate over the vectors and find the pb_type matches the parent_pb_type_name
+     */
+    bool link_success = false;
+
+    for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
+      /* By pass nullptr for pb_type head */
+      if (nullptr == lb_type.pb_type) {
+        continue;
+      }
+      /* Check the name of the top-level pb_type, if it does not match, we can bypass */
+      if (target_op_pb_type_names[0] != std::string(lb_type.pb_type->name)) {
+        continue;
+      }
+      /* Match the name in the top-level, we go further to search the operating as well as
+       * physical pb_types in the graph */
+      t_pb_type* target_op_pb_type = try_find_pb_type_with_given_path(lb_type.pb_type, target_op_pb_type_names, 
+                                                                      target_op_pb_mode_names);
+      if (nullptr == target_op_pb_type) {
+        continue;
+      }
+
+      t_pb_type* target_phy_pb_type = try_find_pb_type_with_given_path(lb_type.pb_type, target_phy_pb_type_names, 
+                                                                       target_phy_pb_mode_names);
+      if (nullptr == target_phy_pb_type) {
+        continue;
+      }
+
+      /* Both operating and physical pb_type have been found, 
+       * we update the annotation by assigning the physical mode 
+       */
+      if (true == pair_operating_and_physical_pb_types(target_op_pb_type, target_phy_pb_type,
+                                                       pb_type_annotation, vpr_pb_type_annotation)) {
+      
+        /* Give a message */
+        VTR_LOG("Annotate operating pb_type '%s' to its physical pb_type '%s'\n",
+                target_op_pb_type->name, target_phy_pb_type->name);
+
+        link_success = true;
+        break;
+      }
+    }
+
+    if (false == link_success) {
+      /* Not found, error out! */
+      VTR_LOG_ERROR("Unable to pair the operating pb_type '%s' to its physical pb_type '%s'!\n",
+                    target_op_pb_type_names.back().c_str(),
+                    target_phy_pb_type_names.back().c_str());
+      return;
+    }
+  } 
+}
+
+
 /********************************************************************
  * Top-level function to link openfpga architecture to VPR, including:
  * - physical pb_type
@@ -323,7 +476,7 @@ void link_arch(OpenfpgaContext& openfpga_context) {
 
   vtr::ScopedStartFinishTimer timer("Link OpenFPGA architecture to VPR architecture");
 
-  /* Annotate physical pb_type in the VPR pb_type graph */
+  /* Annotate physical mode to pb_type in the VPR pb_type graph */
   build_vpr_physical_pb_mode_explicit_annotation(g_vpr_ctx.device(), openfpga_context.arch(),
                                                  openfpga_context.mutable_vpr_pb_type_annotation());
   build_vpr_physical_pb_mode_implicit_annotation(g_vpr_ctx.device(), 
@@ -332,7 +485,9 @@ void link_arch(OpenfpgaContext& openfpga_context) {
   check_vpr_physical_pb_mode_annotation(g_vpr_ctx.device(), 
                                         openfpga_context.vpr_pb_type_annotation());
 
-  /* Annotate idle pb_type in the VPR pb_type graph */
+  /* Annotate physical pb_types to operating pb_type in the VPR pb_type graph */
+  build_vpr_physical_pb_type_annotation(g_vpr_ctx.device(), openfpga_context.arch(),
+                                        openfpga_context.mutable_vpr_pb_type_annotation());
 
   /* Link physical pb_type to circuit model */
 
diff --git a/openfpga/src/base/pb_type_utils.cpp b/openfpga/src/base/pb_type_utils.cpp
index 7a69ad37c..1d0c31b6c 100644
--- a/openfpga/src/base/pb_type_utils.cpp
+++ b/openfpga/src/base/pb_type_utils.cpp
@@ -64,4 +64,28 @@ t_pb_type* find_mode_child_pb_type(t_mode* mode, const char* child_name) {
   return nullptr;
 }
 
+/************************************************************************ 
+ * With a given pb_type, provide a list of its ports
+ ************************************************************************/
+std::vector<t_port*> pb_type_ports(t_pb_type* pb_type) {
+  std::vector<t_port*> ports;
+  for (int i = 0; i < pb_type->num_ports; ++i) {
+    ports.push_back(&(pb_type->ports[i]));
+  }
+  return ports;
+}
+
+/************************************************************************ 
+ * Find a port for a pb_type with a given name
+ * If not found, return null pointer
+ ************************************************************************/
+t_port* find_pb_type_port(t_pb_type* pb_type, const std::string& port_name) {
+  for (int i = 0; i < pb_type->num_ports; ++i) {
+    if (port_name == std::string(pb_type->ports[i].name)) {
+      return &(pb_type->ports[i]);
+    }
+  }
+  return nullptr;
+}
+
 } /* end namespace openfpga */
diff --git a/openfpga/src/base/pb_type_utils.h b/openfpga/src/base/pb_type_utils.h
index c0c1881d5..902f203e3 100644
--- a/openfpga/src/base/pb_type_utils.h
+++ b/openfpga/src/base/pb_type_utils.h
@@ -4,6 +4,7 @@
 /********************************************************************
  * Include header files that are required by function declaration
  *******************************************************************/
+#include <vector>
 #include "physical_types.h"
 
 /********************************************************************
@@ -21,6 +22,10 @@ t_mode* find_pb_type_mode(t_pb_type* pb_type, const char* mode_name);
 
 t_pb_type* find_mode_child_pb_type(t_mode* mode, const char* child_name);
 
+std::vector<t_port*> pb_type_ports(t_pb_type* pb_type);
+
+t_port* find_pb_type_port(t_pb_type* pb_type, const std::string& port_name);
+
 } /* end namespace openfpga */
 
 #endif
diff --git a/openfpga/src/base/vpr_pb_type_annotation.cpp b/openfpga/src/base/vpr_pb_type_annotation.cpp
index 1d4beb1ff..e89045307 100644
--- a/openfpga/src/base/vpr_pb_type_annotation.cpp
+++ b/openfpga/src/base/vpr_pb_type_annotation.cpp
@@ -27,6 +27,34 @@ t_mode* VprPbTypeAnnotation::physical_mode(t_pb_type* pb_type) const {
   return physical_pb_modes_.at(pb_type);
 }
 
+t_pb_type* VprPbTypeAnnotation::physical_pb_type(t_pb_type* pb_type) const {
+  /* Ensure that the pb_type is in the list */
+  std::map<t_pb_type*, t_pb_type*>::const_iterator it = physical_pb_types_.find(pb_type);
+  if (it == physical_pb_types_.end()) {
+    return nullptr;
+  }
+  return physical_pb_types_.at(pb_type);
+}
+
+t_port* VprPbTypeAnnotation::physical_pb_port(t_port* pb_port) const {
+  /* Ensure that the pb_type is in the list */
+  std::map<t_port*, t_port*>::const_iterator it = physical_pb_ports_.find(pb_port);
+  if (it == physical_pb_ports_.end()) {
+    return nullptr;
+  }
+  return physical_pb_ports_.at(pb_port);
+}
+
+BasicPort VprPbTypeAnnotation::physical_pb_port_range(t_port* pb_port) const {
+  /* Ensure that the pb_type is in the list */
+  std::map<t_port*, BasicPort>::const_iterator it = physical_pb_port_ranges_.find(pb_port);
+  if (it == physical_pb_port_ranges_.end()) {
+    /* Return an invalid port. As such the port width will be 0, which is an invalid value */
+    return BasicPort();
+  }
+  return physical_pb_port_ranges_.at(pb_port);
+}
+
 /************************************************************************
  * Public mutators
  ***********************************************************************/
@@ -41,4 +69,40 @@ void VprPbTypeAnnotation::add_pb_type_physical_mode(t_pb_type* pb_type, t_mode*
   physical_pb_modes_[pb_type] = physical_mode;
 }
 
+void VprPbTypeAnnotation::add_physical_pb_type(t_pb_type* operating_pb_type, t_pb_type* physical_pb_type) {
+  /* Warn any override attempt */
+  std::map<t_pb_type*, t_pb_type*>::const_iterator it = physical_pb_types_.find(operating_pb_type);
+  if (it != physical_pb_types_.end()) {
+    VTR_LOG_WARN("Override the annotation between operating pb_type '%s' and it physical pb_type '%s'!\n",
+                 operating_pb_type->name, physical_pb_type->name);
+  }
+
+  physical_pb_types_[operating_pb_type] = physical_pb_type;
+}
+
+void VprPbTypeAnnotation::add_physical_pb_port(t_port* operating_pb_port, t_port* physical_pb_port) {
+  /* Warn any override attempt */
+  std::map<t_port*, t_port*>::const_iterator it = physical_pb_ports_.find(operating_pb_port);
+  if (it != physical_pb_ports_.end()) {
+    VTR_LOG_WARN("Override the annotation between operating pb_port '%s' and it physical pb_port '%s'!\n",
+                 operating_pb_port->name, physical_pb_port->name);
+  }
+
+  physical_pb_ports_[operating_pb_port] = physical_pb_port;
+}
+
+void VprPbTypeAnnotation::add_physical_pb_port_range(t_port* operating_pb_port, const BasicPort& port_range) {
+  /* The port range must satify the port width*/
+  VTR_ASSERT((size_t)operating_pb_port->num_pins == port_range.get_width());
+
+  /* Warn any override attempt */
+  std::map<t_port*, BasicPort>::const_iterator it = physical_pb_port_ranges_.find(operating_pb_port);
+  if (it != physical_pb_port_ranges_.end()) {
+    VTR_LOG_WARN("Override the annotation between operating pb_port '%s' and it physical pb_port range '[%ld:%ld]'!\n",
+                 operating_pb_port->name, port_range.get_lsb(), port_range.get_msb());
+  }
+
+  physical_pb_port_ranges_[operating_pb_port] = port_range;
+}
+
 } /* End namespace openfpga*/
diff --git a/openfpga/src/base/vpr_pb_type_annotation.h b/openfpga/src/base/vpr_pb_type_annotation.h
index 5410a7ca9..90b29598f 100644
--- a/openfpga/src/base/vpr_pb_type_annotation.h
+++ b/openfpga/src/base/vpr_pb_type_annotation.h
@@ -10,6 +10,7 @@
 #include "physical_types.h"
 
 /* Header from openfpgautil library */
+#include "openfpga_port.h"
 #include "circuit_library.h"
 
 /* Begin namespace openfpga */
@@ -29,13 +30,59 @@ class VprPbTypeAnnotation {
     VprPbTypeAnnotation();
   public:  /* Public accessors */
     t_mode* physical_mode(t_pb_type* pb_type) const;
+    t_pb_type* physical_pb_type(t_pb_type* pb_type) const;
+    t_port* physical_pb_port(t_port* pb_port) const;
+    BasicPort physical_pb_port_range(t_port* pb_port) const;
   public:  /* Public mutators */
     void add_pb_type_physical_mode(t_pb_type* pb_type, t_mode* physical_mode);
+    void add_physical_pb_type(t_pb_type* operating_pb_type, t_pb_type* physical_pb_type);
+    void add_physical_pb_port(t_port* operating_pb_port, t_port* physical_pb_port);
+    void add_physical_pb_port_range(t_port* operating_pb_port, const BasicPort& port_range);
   private: /* Internal data */
+    /* Flag about if a pb_type is a physical pb_type */
     std::map<t_pb_type*, bool> is_physical_pb_types_;
+
+    /* Pair a regular pb_type to its physical pb_type */
     std::map<t_pb_type*, t_pb_type*> physical_pb_types_;
+
+    /* Pair a physical mode for a pb_type
+     * Note:
+     * - the physical mode MUST be a child mode of the pb_type
+     * - the pb_type MUST be a physical pb_type itself
+     */
     std::map<t_pb_type*, t_mode*> physical_pb_modes_;
+
+    /* Pair a physical pb_type to its circuit model
+     * Note:
+     * - the pb_type MUST be a physical pb_type itself
+     */
     std::map<t_pb_type*, CircuitModelId> pb_type_circuit_models_;
+
+    /* Pair a pb_type to its mode selection bits
+     * - if the pb_type is a physical pb_type, the mode bits are the default mode 
+     *   where the physical pb_type will operate when used
+     * - if the pb_type is an operating pb_type, the mode bits will be applied
+     *   when the operating pb_type is used by packer
+     */
+    std::map<t_pb_type*, std::vector<bool>> pb_type_mode_bits_;
+
+    /* Pair a pb_port to its physical pb_port 
+     * Note:
+     * - the parent of physical pb_port MUST be a physical pb_type
+     */
+    std::map<t_port*, t_port*> physical_pb_ports_;
+
+    /* Pair a pb_port to its LSB and MSB of a physical pb_port 
+     * Note:
+     * - the LSB and MSB MUST be in range of the physical pb_port
+     */
+    std::map<t_port*, BasicPort> physical_pb_port_ranges_;
+
+    /* Pair a pb_graph_node to a physical pb_graph_node
+     * Note:
+     * - the pb_type of physical pb_graph_node must be a physical pb_type
+     */
+    std::map<t_pb_graph_node*, t_pb_graph_node*> physical_pb_graph_nodes_;
 };
 
 } /* End namespace openfpga*/

From fdcc04cca8f3658a61e55d9ef3c4e839e5ff3312 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 28 Jan 2020 14:55:47 -0700
Subject: [PATCH 033/645] add physical pb_type inference

---
 openfpga/src/base/openfpga_link_arch.cpp | 99 ++++++++++++++++++++++--
 1 file changed, 94 insertions(+), 5 deletions(-)

diff --git a/openfpga/src/base/openfpga_link_arch.cpp b/openfpga/src/base/openfpga_link_arch.cpp
index 443373d20..d1b09df85 100644
--- a/openfpga/src/base/openfpga_link_arch.cpp
+++ b/openfpga/src/base/openfpga_link_arch.cpp
@@ -378,9 +378,9 @@ bool pair_operating_and_physical_pb_types(t_pb_type* operating_pb_type,
  *   annotation is completed
  *******************************************************************/
 static 
-void build_vpr_physical_pb_type_annotation(const DeviceContext& vpr_device_ctx, 
-                                           const Arch& openfpga_arch,
-                                           VprPbTypeAnnotation& vpr_pb_type_annotation) {
+void build_vpr_physical_pb_type_explicit_annotation(const DeviceContext& vpr_device_ctx, 
+                                                    const Arch& openfpga_arch,
+                                                    VprPbTypeAnnotation& vpr_pb_type_annotation) {
   /* Walk through the pb_type annotation stored in the openfpga arch */
   for (const PbTypeAnnotation& pb_type_annotation : openfpga_arch.pb_type_annotations) {
     /* Since our target is to annotate the operating pb_type tp physical pb_type 
@@ -465,6 +465,92 @@ void build_vpr_physical_pb_type_annotation(const DeviceContext& vpr_device_ctx,
   } 
 }
 
+/********************************************************************
+ * This function aims to pair a physical pb_type to itself
+ *******************************************************************/
+static 
+bool self_pair_physical_pb_types(t_pb_type* physical_pb_type, 
+                                 VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  /* Reach here, we should have valid physical pb_types */
+  VTR_ASSERT(nullptr != physical_pb_type);
+  
+  /* Iterate over the ports under the operating pb_type 
+   * For each pin, we will try to find its physical port in the pb_type_annotation
+   * if not found, we assume that the physical port is the same as the operating pb_port
+   */
+  for (t_port* physical_pb_port : pb_type_ports(physical_pb_type)) {
+    BasicPort physical_port_range(physical_pb_port->name, physical_pb_port->num_pins);
+    vpr_pb_type_annotation.add_physical_pb_port(physical_pb_port, physical_pb_port);
+    vpr_pb_type_annotation.add_physical_pb_port_range(physical_pb_port, physical_port_range);
+  }
+
+  /* Now, pb_type mapping should succeed, we update the vpr_pb_type_annotation */
+  vpr_pb_type_annotation.add_physical_pb_type(physical_pb_type, physical_pb_type);
+
+  return true;
+}
+
+/********************************************************************
+ * This function will recursively visit all the pb_type from the top
+ * pb_type in the graph (only in the physical mode) and infer the 
+ * physical pb_type 
+ * This is mainly applied to single-mode pb_type graphs, where the 
+ * physical pb_type should be pb_type itself
+ * We can infer this and save the explicit annotation required by users
+ *******************************************************************/
+static 
+void rec_infer_vpr_physical_pb_type_annotation(t_pb_type* cur_pb_type, 
+                                               VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  /* Physical pb_type is mainly for the primitive pb_type */
+  if (true == is_primitive_pb_type(cur_pb_type)) {
+    /* If the physical pb_type has been mapped, we can skip it */
+    if (nullptr != vpr_pb_type_annotation.physical_pb_type(cur_pb_type)) {
+      return;
+    }
+    /* Create the pair here */
+    if (true == self_pair_physical_pb_types(cur_pb_type, vpr_pb_type_annotation)) {
+      /* Give a message */
+      VTR_LOG("Implicitly infer the physical pb_type for pb_type '%s' itself\n",
+              cur_pb_type->name);
+    } else {
+      VTR_LOG_ERROR("Unable to infer the physical pb_type for pb_type '%s' itself!\n",
+                    cur_pb_type->name);
+    }
+    return;
+  }
+
+  /* Get the physical mode from annotation */ 
+  t_mode* physical_mode = vpr_pb_type_annotation.physical_mode(cur_pb_type);
+
+  VTR_ASSERT(nullptr != physical_mode);
+
+  /* Traverse the pb_type children under the physical mode */
+  for (int ichild = 0; ichild < physical_mode->num_pb_type_children; ++ichild) { 
+    rec_infer_vpr_physical_pb_type_annotation(&(physical_mode->pb_type_children[ichild]),
+                                              vpr_pb_type_annotation);
+  }
+}
+
+/********************************************************************
+ * This function will infer the physical pb_type for each operating 
+ * pb_type in VPR pb_type graph which have not been explicitedly defined
+ * in OpenFPGA architecture XML
+ *
+ * Note:
+ * - This function should be executed only AFTER the physical mode 
+ *   annotation is completed
+ *******************************************************************/
+static 
+void build_vpr_physical_pb_type_implicit_annotation(const DeviceContext& vpr_device_ctx, 
+                                                    VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
+    /* By pass nullptr for pb_type head */
+    if (nullptr == lb_type.pb_type) {
+      continue;
+    }
+    rec_infer_vpr_physical_pb_type_annotation(lb_type.pb_type, vpr_pb_type_annotation); 
+  }
+}
 
 /********************************************************************
  * Top-level function to link openfpga architecture to VPR, including:
@@ -486,8 +572,11 @@ void link_arch(OpenfpgaContext& openfpga_context) {
                                         openfpga_context.vpr_pb_type_annotation());
 
   /* Annotate physical pb_types to operating pb_type in the VPR pb_type graph */
-  build_vpr_physical_pb_type_annotation(g_vpr_ctx.device(), openfpga_context.arch(),
-                                        openfpga_context.mutable_vpr_pb_type_annotation());
+  build_vpr_physical_pb_type_explicit_annotation(g_vpr_ctx.device(), openfpga_context.arch(),
+                                                 openfpga_context.mutable_vpr_pb_type_annotation());
+
+  build_vpr_physical_pb_type_implicit_annotation(g_vpr_ctx.device(),
+                                                 openfpga_context.mutable_vpr_pb_type_annotation());
 
   /* Link physical pb_type to circuit model */
 

From 5d9850c2eb84a8dba46df33e0695d535c0dea1ff Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 28 Jan 2020 15:13:14 -0700
Subject: [PATCH 034/645] move pb_type annotation to independent source files
 as they are getting large

---
 openfpga/src/base/annotate_pb_types.cpp  | 531 +++++++++++++++++++++
 openfpga/src/base/annotate_pb_types.h    |  24 +
 openfpga/src/base/openfpga_link_arch.cpp | 566 +----------------------
 openfpga/src/base/openfpga_link_arch.h   |   4 +-
 openfpga/src/base/pb_type_utils.cpp      |  50 ++
 openfpga/src/base/pb_type_utils.h        |   5 +
 6 files changed, 624 insertions(+), 556 deletions(-)
 create mode 100644 openfpga/src/base/annotate_pb_types.cpp
 create mode 100644 openfpga/src/base/annotate_pb_types.h

diff --git a/openfpga/src/base/annotate_pb_types.cpp b/openfpga/src/base/annotate_pb_types.cpp
new file mode 100644
index 000000000..fe7629281
--- /dev/null
+++ b/openfpga/src/base/annotate_pb_types.cpp
@@ -0,0 +1,531 @@
+/********************************************************************
+ * This file includes functions to build links between pb_types
+ * in particular to annotate the physical mode and physical pb_type
+ *******************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_time.h"
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+#include "vpr_pb_type_annotation.h"
+#include "pb_type_utils.h"
+#include "annotate_pb_types.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * This function will identify the physical mode for each multi-mode 
+ * pb_type in VPR pb_type graph by following the explicit definition 
+ * in OpenFPGA architecture XML
+ *******************************************************************/
+static 
+void build_vpr_physical_pb_mode_explicit_annotation(const DeviceContext& vpr_device_ctx, 
+                                                    const Arch& openfpga_arch,
+                                                    VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  /* Walk through the pb_type annotation stored in the openfpga arch */
+  for (const PbTypeAnnotation& pb_type_annotation : openfpga_arch.pb_type_annotations) {
+    /* Since our target is to annotate the physical mode name, 
+     * we can skip those has not physical mode defined
+     */
+    if (true == pb_type_annotation.physical_mode_name().empty()) {
+      continue;
+    } 
+
+    /* Identify if the pb_type is operating or physical,
+     * For operating pb_type, get the full name of operating pb_type    
+     * For physical pb_type, get the full name of physical pb_type    
+     */
+    std::vector<std::string> target_pb_type_names;
+    std::vector<std::string> target_pb_mode_names;
+
+    if (true == pb_type_annotation.is_operating_pb_type()) {
+      target_pb_type_names = pb_type_annotation.operating_parent_pb_type_names();
+      target_pb_type_names.push_back(pb_type_annotation.operating_pb_type_name());
+      target_pb_mode_names = pb_type_annotation.operating_parent_mode_names();
+    } 
+
+    if (true == pb_type_annotation.is_physical_pb_type()) {
+      target_pb_type_names = pb_type_annotation.physical_parent_pb_type_names();
+      target_pb_type_names.push_back(pb_type_annotation.physical_pb_type_name());
+      target_pb_mode_names = pb_type_annotation.physical_parent_mode_names();
+    } 
+
+    /* We must have at least one pb_type in the list */
+    VTR_ASSERT_SAFE(0 < target_pb_type_names.size());
+
+    /* Pb type information are located at the logic_block_types in the device context of VPR
+     * We iterate over the vectors and find the pb_type matches the parent_pb_type_name
+     */
+    bool link_success = false;
+
+    for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
+      /* By pass nullptr for pb_type head */
+      if (nullptr == lb_type.pb_type) {
+        continue;
+      }
+      /* Check the name of the top-level pb_type, if it does not match, we can bypass */
+      if (target_pb_type_names[0] != std::string(lb_type.pb_type->name)) {
+        continue;
+      }
+      /* Match the name in the top-level, we go further to search the pb_type in the graph */
+      t_pb_type* target_pb_type = try_find_pb_type_with_given_path(lb_type.pb_type, target_pb_type_names, 
+                                                                   target_pb_mode_names);
+      if (nullptr == target_pb_type) {
+        continue;
+      }
+
+      /* Found, we update the annotation by assigning the physical mode */
+      t_mode* physical_mode = find_pb_type_mode(target_pb_type, pb_type_annotation.physical_mode_name().c_str());
+      vpr_pb_type_annotation.add_pb_type_physical_mode(target_pb_type, physical_mode);
+      
+      /* Give a message */
+      VTR_LOG("Annotate pb_type '%s' with physical mode '%s'\n",
+              target_pb_type->name, physical_mode->name);
+
+      link_success = true;
+      break;
+    }
+
+    if (false == link_success) {
+      /* Not found, error out! */
+      VTR_LOG_ERROR("Unable to find the pb_type '%s' in VPR architecture definition!\n",
+                    target_pb_type_names.back().c_str());
+      return;
+    }
+  } 
+}
+
+/********************************************************************
+ * This function will recursively visit all the pb_type from the top
+ * pb_type in the graph and 
+ * infer the physical mode for each multi-mode 
+ * pb_type in VPR pb_type graph without OpenFPGA architecture XML
+ *
+ * The following rule is applied:
+ * if there is only 1 mode under a pb_type, it will be the default 
+ * physical mode for this pb_type
+ *******************************************************************/
+static 
+void rec_infer_vpr_physical_pb_mode_annotation(t_pb_type* cur_pb_type, 
+                                               VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  /* We do not check any primitive pb_type */
+  if (true == is_primitive_pb_type(cur_pb_type)) {
+    return;
+  }
+
+  /* For non-primitive pb_type:
+   * - if there is only one mode, it will be the physical mode
+   *   we just need to make sure that we do not repeatedly annotate this
+   * - if there are multiple modes, we should be able to find a physical mode
+   *   and then go recursively 
+   */
+  t_mode* physical_mode = nullptr;
+
+  if (1 == cur_pb_type->num_modes) {
+    if (nullptr == vpr_pb_type_annotation.physical_mode(cur_pb_type)) {
+      /* Not assigned by explicit annotation, we should infer here */
+      vpr_pb_type_annotation.add_pb_type_physical_mode(cur_pb_type, &(cur_pb_type->modes[0]));
+      VTR_LOG("Implicitly infer physical mode '%s' for pb_type '%s'\n",
+              cur_pb_type->modes[0].name, cur_pb_type->name);
+    }
+  } else {
+    VTR_ASSERT(1 < cur_pb_type->num_modes);
+    if (nullptr == vpr_pb_type_annotation.physical_mode(cur_pb_type)) {
+      /* Not assigned by explicit annotation, we should infer here */
+      vpr_pb_type_annotation.add_pb_type_physical_mode(cur_pb_type, &(cur_pb_type->modes[0]));
+      VTR_LOG_ERROR("Unable to find a physical mode for a multi-mode pb_type '%s'!\n",
+                    cur_pb_type->name);
+      VTR_LOG_ERROR("Please specify in the OpenFPGA architecture\n");
+      return;
+    }
+  }
+
+  /* Get the physical mode from annotation */ 
+  physical_mode = vpr_pb_type_annotation.physical_mode(cur_pb_type);
+
+  VTR_ASSERT(nullptr != physical_mode);
+
+  /* Traverse the pb_type children under the physical mode */
+  for (int ichild = 0; ichild < physical_mode->num_pb_type_children; ++ichild) { 
+    rec_infer_vpr_physical_pb_mode_annotation(&(physical_mode->pb_type_children[ichild]),
+                                              vpr_pb_type_annotation);
+  }
+}
+
+/********************************************************************
+ * This function will infer the physical mode for each multi-mode 
+ * pb_type in VPR pb_type graph without OpenFPGA architecture XML
+ *
+ * The following rule is applied:
+ * if there is only 1 mode under a pb_type, it will be the default 
+ * physical mode for this pb_type
+ *
+ * Note: 
+ * This function must be executed AFTER the function
+ *   build_vpr_physical_pb_mode_explicit_annotation()
+ *******************************************************************/
+static 
+void build_vpr_physical_pb_mode_implicit_annotation(const DeviceContext& vpr_device_ctx, 
+                                                    VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
+    /* By pass nullptr for pb_type head */
+    if (nullptr == lb_type.pb_type) {
+      continue;
+    }
+    rec_infer_vpr_physical_pb_mode_annotation(lb_type.pb_type, vpr_pb_type_annotation); 
+  }
+}
+
+/********************************************************************
+ * This function will recursively traverse pb_type graph to ensure
+ * 1. there is only a physical mode under each pb_type
+ * 2. physical mode appears only when its parent is a physical mode.
+ *******************************************************************/
+static 
+void rec_check_vpr_physical_pb_mode_annotation(t_pb_type* cur_pb_type,
+                                               const bool& expect_physical_mode,
+                                               const VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                               size_t& num_err) {
+  /* We do not check any primitive pb_type */
+  if (true == is_primitive_pb_type(cur_pb_type)) {
+    return;
+  }
+
+  /* For non-primitive pb_type:
+   * - If we expect a physical mode to exist under this pb_type
+   *   we should be able to find one in the annoation 
+   * - If we do NOT expect a physical mode, make sure we find 
+   *   nothing in the annotation
+   */
+  if (true == expect_physical_mode) {
+    if (nullptr == vpr_pb_type_annotation.physical_mode(cur_pb_type)) {
+      VTR_LOG_ERROR("Unable to find a physical mode for a multi-mode pb_type '%s'!\n",
+                    cur_pb_type->name);
+      VTR_LOG_ERROR("Please specify in the OpenFPGA architecture\n");
+      num_err++;
+      return;
+    }
+  } else {
+    VTR_ASSERT_SAFE(false == expect_physical_mode);
+    if (nullptr != vpr_pb_type_annotation.physical_mode(cur_pb_type)) {
+      VTR_LOG_ERROR("Find a physical mode '%s' for pb_type '%s' which is not under any physical mode!\n",
+                    vpr_pb_type_annotation.physical_mode(cur_pb_type)->name,
+                    cur_pb_type->name);
+      num_err++;
+      return;
+    }
+  }
+
+  /* Traverse all the modes
+   * - for pb_type children under a physical mode, we expect an physical mode 
+   * - for pb_type children under non-physical mode, we expect no physical mode 
+   */
+  for (int imode = 0; imode < cur_pb_type->num_modes; ++imode) {
+    bool expect_child_physical_mode = false;
+    if (&(cur_pb_type->modes[imode]) == vpr_pb_type_annotation.physical_mode(cur_pb_type)) {
+      expect_child_physical_mode = true && expect_physical_mode; 
+    }
+    for (int ichild = 0; ichild < cur_pb_type->modes[imode].num_pb_type_children; ++ichild) { 
+      rec_check_vpr_physical_pb_mode_annotation(&(cur_pb_type->modes[imode].pb_type_children[ichild]),
+                                                expect_child_physical_mode, vpr_pb_type_annotation,
+                                                num_err);
+    }
+  }
+}
+
+/********************************************************************
+ * This function will check the physical mode annotation for
+ * each pb_type in the device
+ *******************************************************************/
+static 
+void check_vpr_physical_pb_mode_annotation(const DeviceContext& vpr_device_ctx, 
+                                           const VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  size_t num_err = 0;
+
+  for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
+    /* By pass nullptr for pb_type head */
+    if (nullptr == lb_type.pb_type) {
+      continue;
+    }
+    /* Top pb_type should always has a physical mode! */
+    rec_check_vpr_physical_pb_mode_annotation(lb_type.pb_type, true, vpr_pb_type_annotation, num_err);
+  }
+  if (0 == num_err) {
+    VTR_LOG("Check physical mode annotation for pb_types passed.\n");
+  } else {
+    VTR_LOG("Check physical mode annotation for pb_types failed with %ld errors!\n",
+            num_err);
+  }
+}
+
+/********************************************************************
+ * This function aims to make a pair of operating and physical 
+ * pb_types:
+ * - In addition to pairing the pb_types, it will pair the ports of the pb_types
+ * - For the ports which are explicited annotated as physical pin mapping 
+ *   in the pb_type annotation. 
+ *   We will check the port range and create a pair 
+ * - For the ports which are not specified in the pb_type annotation
+ *   we assume their physical ports share the same as the operating ports
+ *   We will try to find a port in the physical pb_type and check the port range
+ *   If found, we will create a pair 
+ * - All the pairs will be updated in vpr_pb_type_annotation
+ *******************************************************************/
+static 
+bool pair_operating_and_physical_pb_types(t_pb_type* operating_pb_type, 
+                                          t_pb_type* physical_pb_type,
+                                          const PbTypeAnnotation& pb_type_annotation,
+                                          VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  /* Reach here, we should have valid operating and physical pb_types */
+  VTR_ASSERT((nullptr != operating_pb_type) && (nullptr != physical_pb_type));
+  
+  /* Iterate over the ports under the operating pb_type 
+   * For each pin, we will try to find its physical port in the pb_type_annotation
+   * if not found, we assume that the physical port is the same as the operating pb_port
+   */
+  for (t_port* operating_pb_port : pb_type_ports(operating_pb_type)) {
+    /* Try to find the port in the pb_type_annotation */
+    BasicPort expected_physical_pb_port = pb_type_annotation.physical_pb_type_port(std::string(operating_pb_port->name));
+    if (true == expected_physical_pb_port.get_name().empty()) {
+      /* Not found, we reset the port information to be consistent as the operating pb_port */
+      expected_physical_pb_port.set_name(std::string(operating_pb_port->name));
+      expected_physical_pb_port.set_width(operating_pb_port->num_pins);
+    }
+
+    /* Try to find the expected port in the physical pb_type */
+    t_port* physical_pb_port = find_pb_type_port(physical_pb_type, expected_physical_pb_port.get_name());
+    /* Not found, mapping fails */
+    if (nullptr == physical_pb_port) {
+      return false;
+    }
+    /* If the port range does not match, mapping fails */
+    if (false == expected_physical_pb_port.contained(BasicPort(physical_pb_port->name, physical_pb_port->num_pins))) {
+      return false;
+    }
+    /* Now, port mapping should succeed, we update the vpr_pb_type_annotation */
+    vpr_pb_type_annotation.add_physical_pb_port(operating_pb_port, physical_pb_port);
+    vpr_pb_type_annotation.add_physical_pb_port_range(operating_pb_port, expected_physical_pb_port);
+  }
+
+  /* Now, pb_type mapping should succeed, we update the vpr_pb_type_annotation */
+  vpr_pb_type_annotation.add_physical_pb_type(operating_pb_type, physical_pb_type);
+
+  return true;
+}
+
+/********************************************************************
+ * This function will identify the physical pb_type for each operating 
+ * pb_type in VPR pb_type graph by following the explicit definition 
+ * in OpenFPGA architecture XML
+ *
+ * Note:
+ * - This function should be executed only AFTER the physical mode 
+ *   annotation is completed
+ *******************************************************************/
+static 
+void build_vpr_physical_pb_type_explicit_annotation(const DeviceContext& vpr_device_ctx, 
+                                                    const Arch& openfpga_arch,
+                                                    VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  /* Walk through the pb_type annotation stored in the openfpga arch */
+  for (const PbTypeAnnotation& pb_type_annotation : openfpga_arch.pb_type_annotations) {
+    /* Since our target is to annotate the operating pb_type tp physical pb_type 
+     * we can skip those annotation only for physical pb_type
+     */
+    if (true == pb_type_annotation.is_physical_pb_type()) {
+      continue;
+    }
+
+    VTR_ASSERT(true == pb_type_annotation.is_operating_pb_type());
+
+    /* Collect the information about the full hierarchy of operating pb_type to be annotated */
+    std::vector<std::string> target_op_pb_type_names;
+    std::vector<std::string> target_op_pb_mode_names;
+
+    target_op_pb_type_names = pb_type_annotation.operating_parent_pb_type_names();
+    target_op_pb_type_names.push_back(pb_type_annotation.operating_pb_type_name());
+    target_op_pb_mode_names = pb_type_annotation.operating_parent_mode_names();
+
+    /* Collect the information about the full hierarchy of physical pb_type to be annotated */
+    std::vector<std::string> target_phy_pb_type_names;
+    std::vector<std::string> target_phy_pb_mode_names;
+
+    target_phy_pb_type_names = pb_type_annotation.physical_parent_pb_type_names();
+    target_phy_pb_type_names.push_back(pb_type_annotation.physical_pb_type_name());
+    target_phy_pb_mode_names = pb_type_annotation.physical_parent_mode_names();
+
+    /* We must have at least one pb_type in the list */
+    VTR_ASSERT_SAFE(0 < target_op_pb_type_names.size());
+    VTR_ASSERT_SAFE(0 < target_phy_pb_type_names.size());
+
+    /* Pb type information are located at the logic_block_types in the device context of VPR
+     * We iterate over the vectors and find the pb_type matches the parent_pb_type_name
+     */
+    bool link_success = false;
+
+    for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
+      /* By pass nullptr for pb_type head */
+      if (nullptr == lb_type.pb_type) {
+        continue;
+      }
+      /* Check the name of the top-level pb_type, if it does not match, we can bypass */
+      if (target_op_pb_type_names[0] != std::string(lb_type.pb_type->name)) {
+        continue;
+      }
+      /* Match the name in the top-level, we go further to search the operating as well as
+       * physical pb_types in the graph */
+      t_pb_type* target_op_pb_type = try_find_pb_type_with_given_path(lb_type.pb_type, target_op_pb_type_names, 
+                                                                      target_op_pb_mode_names);
+      if (nullptr == target_op_pb_type) {
+        continue;
+      }
+
+      t_pb_type* target_phy_pb_type = try_find_pb_type_with_given_path(lb_type.pb_type, target_phy_pb_type_names, 
+                                                                       target_phy_pb_mode_names);
+      if (nullptr == target_phy_pb_type) {
+        continue;
+      }
+
+      /* Both operating and physical pb_type have been found, 
+       * we update the annotation by assigning the physical mode 
+       */
+      if (true == pair_operating_and_physical_pb_types(target_op_pb_type, target_phy_pb_type,
+                                                       pb_type_annotation, vpr_pb_type_annotation)) {
+      
+        /* Give a message */
+        VTR_LOG("Annotate operating pb_type '%s' to its physical pb_type '%s'\n",
+                target_op_pb_type->name, target_phy_pb_type->name);
+
+        link_success = true;
+        break;
+      }
+    }
+
+    if (false == link_success) {
+      /* Not found, error out! */
+      VTR_LOG_ERROR("Unable to pair the operating pb_type '%s' to its physical pb_type '%s'!\n",
+                    target_op_pb_type_names.back().c_str(),
+                    target_phy_pb_type_names.back().c_str());
+      return;
+    }
+  } 
+}
+
+/********************************************************************
+ * This function aims to pair a physical pb_type to itself
+ *******************************************************************/
+static 
+bool self_pair_physical_pb_types(t_pb_type* physical_pb_type, 
+                                 VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  /* Reach here, we should have valid physical pb_types */
+  VTR_ASSERT(nullptr != physical_pb_type);
+  
+  /* Iterate over the ports under the operating pb_type 
+   * For each pin, we will try to find its physical port in the pb_type_annotation
+   * if not found, we assume that the physical port is the same as the operating pb_port
+   */
+  for (t_port* physical_pb_port : pb_type_ports(physical_pb_type)) {
+    BasicPort physical_port_range(physical_pb_port->name, physical_pb_port->num_pins);
+    vpr_pb_type_annotation.add_physical_pb_port(physical_pb_port, physical_pb_port);
+    vpr_pb_type_annotation.add_physical_pb_port_range(physical_pb_port, physical_port_range);
+  }
+
+  /* Now, pb_type mapping should succeed, we update the vpr_pb_type_annotation */
+  vpr_pb_type_annotation.add_physical_pb_type(physical_pb_type, physical_pb_type);
+
+  return true;
+}
+
+/********************************************************************
+ * This function will recursively visit all the pb_type from the top
+ * pb_type in the graph (only in the physical mode) and infer the 
+ * physical pb_type 
+ * This is mainly applied to single-mode pb_type graphs, where the 
+ * physical pb_type should be pb_type itself
+ * We can infer this and save the explicit annotation required by users
+ *******************************************************************/
+static 
+void rec_infer_vpr_physical_pb_type_annotation(t_pb_type* cur_pb_type, 
+                                               VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  /* Physical pb_type is mainly for the primitive pb_type */
+  if (true == is_primitive_pb_type(cur_pb_type)) {
+    /* If the physical pb_type has been mapped, we can skip it */
+    if (nullptr != vpr_pb_type_annotation.physical_pb_type(cur_pb_type)) {
+      return;
+    }
+    /* Create the pair here */
+    if (true == self_pair_physical_pb_types(cur_pb_type, vpr_pb_type_annotation)) {
+      /* Give a message */
+      VTR_LOG("Implicitly infer the physical pb_type for pb_type '%s' itself\n",
+              cur_pb_type->name);
+    } else {
+      VTR_LOG_ERROR("Unable to infer the physical pb_type for pb_type '%s' itself!\n",
+                    cur_pb_type->name);
+    }
+    return;
+  }
+
+  /* Get the physical mode from annotation */ 
+  t_mode* physical_mode = vpr_pb_type_annotation.physical_mode(cur_pb_type);
+
+  VTR_ASSERT(nullptr != physical_mode);
+
+  /* Traverse the pb_type children under the physical mode */
+  for (int ichild = 0; ichild < physical_mode->num_pb_type_children; ++ichild) { 
+    rec_infer_vpr_physical_pb_type_annotation(&(physical_mode->pb_type_children[ichild]),
+                                              vpr_pb_type_annotation);
+  }
+}
+
+/********************************************************************
+ * This function will infer the physical pb_type for each operating 
+ * pb_type in VPR pb_type graph which have not been explicitedly defined
+ * in OpenFPGA architecture XML
+ *
+ * Note:
+ * - This function should be executed only AFTER the physical mode 
+ *   annotation is completed
+ *******************************************************************/
+static 
+void build_vpr_physical_pb_type_implicit_annotation(const DeviceContext& vpr_device_ctx, 
+                                                    VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
+    /* By pass nullptr for pb_type head */
+    if (nullptr == lb_type.pb_type) {
+      continue;
+    }
+    rec_infer_vpr_physical_pb_type_annotation(lb_type.pb_type, vpr_pb_type_annotation); 
+  }
+}
+
+/********************************************************************
+ * Top-level function to link openfpga architecture to VPR, including:
+ * - physical pb_type
+ * - circuit models for pb_type, pb interconnect
+ *******************************************************************/
+void annotate_pb_types(const DeviceContext& vpr_device_ctx, 
+                       const Arch& openfpga_arch,
+                       VprPbTypeAnnotation& vpr_pb_type_annotation) {
+
+  /* Annotate physical mode to pb_type in the VPR pb_type graph */
+  build_vpr_physical_pb_mode_explicit_annotation(vpr_device_ctx, openfpga_arch,
+                                                 vpr_pb_type_annotation);
+  build_vpr_physical_pb_mode_implicit_annotation(vpr_device_ctx,
+                                                 vpr_pb_type_annotation);
+
+  check_vpr_physical_pb_mode_annotation(vpr_device_ctx, 
+                                        const_cast<const VprPbTypeAnnotation&>(vpr_pb_type_annotation));
+
+  /* Annotate physical pb_types to operating pb_type in the VPR pb_type graph */
+  build_vpr_physical_pb_type_explicit_annotation(vpr_device_ctx, openfpga_arch,
+                                                 vpr_pb_type_annotation);
+
+  build_vpr_physical_pb_type_implicit_annotation(vpr_device_ctx,
+                                                 vpr_pb_type_annotation);
+
+  /* Link physical pb_type to circuit model */
+
+  /* Link routing architecture to circuit model */
+} 
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/base/annotate_pb_types.h b/openfpga/src/base/annotate_pb_types.h
new file mode 100644
index 000000000..494b2c771
--- /dev/null
+++ b/openfpga/src/base/annotate_pb_types.h
@@ -0,0 +1,24 @@
+#ifndef ANNOTATE_PB_TYPES_H
+#define ANNOTATE_PB_TYPES_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "vpr_context.h"
+#include "openfpga_context.h"
+#include "vpr_pb_type_annotation.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void annotate_pb_types(const DeviceContext& vpr_device_ctx, 
+                       const Arch& openfpga_arch,
+                       VprPbTypeAnnotation& vpr_pb_type_annotation);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/base/openfpga_link_arch.cpp b/openfpga/src/base/openfpga_link_arch.cpp
index d1b09df85..d10c5d931 100644
--- a/openfpga/src/base/openfpga_link_arch.cpp
+++ b/openfpga/src/base/openfpga_link_arch.cpp
@@ -9,6 +9,7 @@
 
 #include "vpr_pb_type_annotation.h"
 #include "pb_type_utils.h"
+#include "annotate_pb_types.h"
 #include "openfpga_link_arch.h"
 
 /* Include global variables of VPR */
@@ -17,568 +18,25 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-/********************************************************************
- * This function will traverse pb_type graph from its top to find
- * a pb_type with a given name as well as its hierarchy 
- *******************************************************************/
-static 
-t_pb_type* try_find_pb_type_with_given_path(t_pb_type* top_pb_type, 
-                                            const std::vector<std::string>& target_pb_type_names, 
-                                            const std::vector<std::string>& target_pb_mode_names) {
-  /* Ensure that number of parent names and modes matches */
-  VTR_ASSERT_SAFE(target_pb_type_names.size() == target_pb_mode_names.size() + 1);
-
-  t_pb_type* cur_pb_type = top_pb_type;
-
-  /* If the top pb_type is what we want, we can return here */
-  if (1 == target_pb_type_names.size()) {
-    if (target_pb_type_names[0] == std::string(top_pb_type->name)) {
-      return top_pb_type;
-    }
-    /* Not match, return null pointer */
-    return nullptr;
-  }
-
-  /* We start from the first element of the parent names and parent modes.
-   * If the pb_type does not match in name, we fail 
-   * If we cannot find a mode match the name, we fail 
-   */
-  for (size_t i = 0; i < target_pb_type_names.size() - 1; ++i) {
-    /* If this level does not match, search fail */
-    if (target_pb_type_names[i] != std::string(cur_pb_type->name)) {
-      return nullptr;
-    }
-    /* Find if the mode matches */
-    t_mode* cur_mode = find_pb_type_mode(cur_pb_type, target_pb_mode_names[i].c_str()); 
-    if (nullptr == cur_mode) {
-      return nullptr;
-    }
-    /* Go to the next level of pb_type */
-    cur_pb_type = find_mode_child_pb_type(cur_mode, target_pb_type_names[i + 1].c_str());
-    if (nullptr == cur_pb_type) {
-      return nullptr;
-    }
-    /* If this is already the last pb_type in the list, this is what we want */
-    if (i + 1 == target_pb_type_names.size() - 1) {
-      return cur_pb_type;
-    }
-  }
-
-  /* Reach here, it means we find nothing */
-  return nullptr;
-}
-
-/********************************************************************
- * This function will identify the physical mode for each multi-mode 
- * pb_type in VPR pb_type graph by following the explicit definition 
- * in OpenFPGA architecture XML
- *******************************************************************/
-static 
-void build_vpr_physical_pb_mode_explicit_annotation(const DeviceContext& vpr_device_ctx, 
-                                                    const Arch& openfpga_arch,
-                                                    VprPbTypeAnnotation& vpr_pb_type_annotation) {
-  /* Walk through the pb_type annotation stored in the openfpga arch */
-  for (const PbTypeAnnotation& pb_type_annotation : openfpga_arch.pb_type_annotations) {
-    /* Since our target is to annotate the physical mode name, 
-     * we can skip those has not physical mode defined
-     */
-    if (true == pb_type_annotation.physical_mode_name().empty()) {
-      continue;
-    } 
-
-    /* Identify if the pb_type is operating or physical,
-     * For operating pb_type, get the full name of operating pb_type    
-     * For physical pb_type, get the full name of physical pb_type    
-     */
-    std::vector<std::string> target_pb_type_names;
-    std::vector<std::string> target_pb_mode_names;
-
-    if (true == pb_type_annotation.is_operating_pb_type()) {
-      target_pb_type_names = pb_type_annotation.operating_parent_pb_type_names();
-      target_pb_type_names.push_back(pb_type_annotation.operating_pb_type_name());
-      target_pb_mode_names = pb_type_annotation.operating_parent_mode_names();
-    } 
-
-    if (true == pb_type_annotation.is_physical_pb_type()) {
-      target_pb_type_names = pb_type_annotation.physical_parent_pb_type_names();
-      target_pb_type_names.push_back(pb_type_annotation.physical_pb_type_name());
-      target_pb_mode_names = pb_type_annotation.physical_parent_mode_names();
-    } 
-
-    /* We must have at least one pb_type in the list */
-    VTR_ASSERT_SAFE(0 < target_pb_type_names.size());
-
-    /* Pb type information are located at the logic_block_types in the device context of VPR
-     * We iterate over the vectors and find the pb_type matches the parent_pb_type_name
-     */
-    bool link_success = false;
-
-    for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
-      /* By pass nullptr for pb_type head */
-      if (nullptr == lb_type.pb_type) {
-        continue;
-      }
-      /* Check the name of the top-level pb_type, if it does not match, we can bypass */
-      if (target_pb_type_names[0] != std::string(lb_type.pb_type->name)) {
-        continue;
-      }
-      /* Match the name in the top-level, we go further to search the pb_type in the graph */
-      t_pb_type* target_pb_type = try_find_pb_type_with_given_path(lb_type.pb_type, target_pb_type_names, 
-                                                                   target_pb_mode_names);
-      if (nullptr == target_pb_type) {
-        continue;
-      }
-
-      /* Found, we update the annotation by assigning the physical mode */
-      t_mode* physical_mode = find_pb_type_mode(target_pb_type, pb_type_annotation.physical_mode_name().c_str());
-      vpr_pb_type_annotation.add_pb_type_physical_mode(target_pb_type, physical_mode);
-      
-      /* Give a message */
-      VTR_LOG("Annotate pb_type '%s' with physical mode '%s'\n",
-              target_pb_type->name, physical_mode->name);
-
-      link_success = true;
-      break;
-    }
-
-    if (false == link_success) {
-      /* Not found, error out! */
-      VTR_LOG_ERROR("Unable to find the pb_type '%s' in VPR architecture definition!\n",
-                    target_pb_type_names.back().c_str());
-      return;
-    }
-  } 
-}
-
-/********************************************************************
- * This function will recursively visit all the pb_type from the top
- * pb_type in the graph and 
- * infer the physical mode for each multi-mode 
- * pb_type in VPR pb_type graph without OpenFPGA architecture XML
- *
- * The following rule is applied:
- * if there is only 1 mode under a pb_type, it will be the default 
- * physical mode for this pb_type
- *******************************************************************/
-static 
-void rec_infer_vpr_physical_pb_mode_annotation(t_pb_type* cur_pb_type, 
-                                               VprPbTypeAnnotation& vpr_pb_type_annotation) {
-  /* We do not check any primitive pb_type */
-  if (true == is_primitive_pb_type(cur_pb_type)) {
-    return;
-  }
-
-  /* For non-primitive pb_type:
-   * - if there is only one mode, it will be the physical mode
-   *   we just need to make sure that we do not repeatedly annotate this
-   * - if there are multiple modes, we should be able to find a physical mode
-   *   and then go recursively 
-   */
-  t_mode* physical_mode = nullptr;
-
-  if (1 == cur_pb_type->num_modes) {
-    if (nullptr == vpr_pb_type_annotation.physical_mode(cur_pb_type)) {
-      /* Not assigned by explicit annotation, we should infer here */
-      vpr_pb_type_annotation.add_pb_type_physical_mode(cur_pb_type, &(cur_pb_type->modes[0]));
-      VTR_LOG("Implicitly infer physical mode '%s' for pb_type '%s'\n",
-              cur_pb_type->modes[0].name, cur_pb_type->name);
-    }
-  } else {
-    VTR_ASSERT(1 < cur_pb_type->num_modes);
-    if (nullptr == vpr_pb_type_annotation.physical_mode(cur_pb_type)) {
-      /* Not assigned by explicit annotation, we should infer here */
-      vpr_pb_type_annotation.add_pb_type_physical_mode(cur_pb_type, &(cur_pb_type->modes[0]));
-      VTR_LOG_ERROR("Unable to find a physical mode for a multi-mode pb_type '%s'!\n",
-                    cur_pb_type->name);
-      VTR_LOG_ERROR("Please specify in the OpenFPGA architecture\n");
-      return;
-    }
-  }
-
-  /* Get the physical mode from annotation */ 
-  physical_mode = vpr_pb_type_annotation.physical_mode(cur_pb_type);
-
-  VTR_ASSERT(nullptr != physical_mode);
-
-  /* Traverse the pb_type children under the physical mode */
-  for (int ichild = 0; ichild < physical_mode->num_pb_type_children; ++ichild) { 
-    rec_infer_vpr_physical_pb_mode_annotation(&(physical_mode->pb_type_children[ichild]),
-                                              vpr_pb_type_annotation);
-  }
-}
-
-/********************************************************************
- * This function will infer the physical mode for each multi-mode 
- * pb_type in VPR pb_type graph without OpenFPGA architecture XML
- *
- * The following rule is applied:
- * if there is only 1 mode under a pb_type, it will be the default 
- * physical mode for this pb_type
- *
- * Note: 
- * This function must be executed AFTER the function
- *   build_vpr_physical_pb_mode_explicit_annotation()
- *******************************************************************/
-static 
-void build_vpr_physical_pb_mode_implicit_annotation(const DeviceContext& vpr_device_ctx, 
-                                                    VprPbTypeAnnotation& vpr_pb_type_annotation) {
-  for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
-    /* By pass nullptr for pb_type head */
-    if (nullptr == lb_type.pb_type) {
-      continue;
-    }
-    rec_infer_vpr_physical_pb_mode_annotation(lb_type.pb_type, vpr_pb_type_annotation); 
-  }
-}
-
-/********************************************************************
- * This function will recursively traverse pb_type graph to ensure
- * 1. there is only a physical mode under each pb_type
- * 2. physical mode appears only when its parent is a physical mode.
- *******************************************************************/
-static 
-void rec_check_vpr_physical_pb_mode_annotation(t_pb_type* cur_pb_type,
-                                               const bool& expect_physical_mode,
-                                               const VprPbTypeAnnotation& vpr_pb_type_annotation,
-                                               size_t& num_err) {
-  /* We do not check any primitive pb_type */
-  if (true == is_primitive_pb_type(cur_pb_type)) {
-    return;
-  }
-
-  /* For non-primitive pb_type:
-   * - If we expect a physical mode to exist under this pb_type
-   *   we should be able to find one in the annoation 
-   * - If we do NOT expect a physical mode, make sure we find 
-   *   nothing in the annotation
-   */
-  if (true == expect_physical_mode) {
-    if (nullptr == vpr_pb_type_annotation.physical_mode(cur_pb_type)) {
-      VTR_LOG_ERROR("Unable to find a physical mode for a multi-mode pb_type '%s'!\n",
-                    cur_pb_type->name);
-      VTR_LOG_ERROR("Please specify in the OpenFPGA architecture\n");
-      num_err++;
-      return;
-    }
-  } else {
-    VTR_ASSERT_SAFE(false == expect_physical_mode);
-    if (nullptr != vpr_pb_type_annotation.physical_mode(cur_pb_type)) {
-      VTR_LOG_ERROR("Find a physical mode '%s' for pb_type '%s' which is not under any physical mode!\n",
-                    vpr_pb_type_annotation.physical_mode(cur_pb_type)->name,
-                    cur_pb_type->name);
-      num_err++;
-      return;
-    }
-  }
-
-  /* Traverse all the modes
-   * - for pb_type children under a physical mode, we expect an physical mode 
-   * - for pb_type children under non-physical mode, we expect no physical mode 
-   */
-  for (int imode = 0; imode < cur_pb_type->num_modes; ++imode) {
-    bool expect_child_physical_mode = false;
-    if (&(cur_pb_type->modes[imode]) == vpr_pb_type_annotation.physical_mode(cur_pb_type)) {
-      expect_child_physical_mode = true && expect_physical_mode; 
-    }
-    for (int ichild = 0; ichild < cur_pb_type->modes[imode].num_pb_type_children; ++ichild) { 
-      rec_check_vpr_physical_pb_mode_annotation(&(cur_pb_type->modes[imode].pb_type_children[ichild]),
-                                                expect_child_physical_mode, vpr_pb_type_annotation,
-                                                num_err);
-    }
-  }
-}
-
-/********************************************************************
- * This function will check the physical mode annotation for
- * each pb_type in the device
- *******************************************************************/
-static 
-void check_vpr_physical_pb_mode_annotation(const DeviceContext& vpr_device_ctx, 
-                                           const VprPbTypeAnnotation& vpr_pb_type_annotation) {
-  size_t num_err = 0;
-
-  for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
-    /* By pass nullptr for pb_type head */
-    if (nullptr == lb_type.pb_type) {
-      continue;
-    }
-    /* Top pb_type should always has a physical mode! */
-    rec_check_vpr_physical_pb_mode_annotation(lb_type.pb_type, true, vpr_pb_type_annotation, num_err);
-  }
-  if (0 == num_err) {
-    VTR_LOG("Check physical mode annotation for pb_types passed.\n");
-  } else {
-    VTR_LOG("Check physical mode annotation for pb_types failed with %ld errors!\n",
-            num_err);
-  }
-}
-
-/********************************************************************
- * This function aims to make a pair of operating and physical 
- * pb_types:
- * - In addition to pairing the pb_types, it will pair the ports of the pb_types
- * - For the ports which are explicited annotated as physical pin mapping 
- *   in the pb_type annotation. 
- *   We will check the port range and create a pair 
- * - For the ports which are not specified in the pb_type annotation
- *   we assume their physical ports share the same as the operating ports
- *   We will try to find a port in the physical pb_type and check the port range
- *   If found, we will create a pair 
- * - All the pairs will be updated in vpr_pb_type_annotation
- *******************************************************************/
-static 
-bool pair_operating_and_physical_pb_types(t_pb_type* operating_pb_type, 
-                                          t_pb_type* physical_pb_type,
-                                          const PbTypeAnnotation& pb_type_annotation,
-                                          VprPbTypeAnnotation& vpr_pb_type_annotation) {
-  /* Reach here, we should have valid operating and physical pb_types */
-  VTR_ASSERT((nullptr != operating_pb_type) && (nullptr != physical_pb_type));
-  
-  /* Iterate over the ports under the operating pb_type 
-   * For each pin, we will try to find its physical port in the pb_type_annotation
-   * if not found, we assume that the physical port is the same as the operating pb_port
-   */
-  for (t_port* operating_pb_port : pb_type_ports(operating_pb_type)) {
-    /* Try to find the port in the pb_type_annotation */
-    BasicPort expected_physical_pb_port = pb_type_annotation.physical_pb_type_port(std::string(operating_pb_port->name));
-    if (true == expected_physical_pb_port.get_name().empty()) {
-      /* Not found, we reset the port information to be consistent as the operating pb_port */
-      expected_physical_pb_port.set_name(std::string(operating_pb_port->name));
-      expected_physical_pb_port.set_width(operating_pb_port->num_pins);
-    }
-
-    /* Try to find the expected port in the physical pb_type */
-    t_port* physical_pb_port = find_pb_type_port(physical_pb_type, expected_physical_pb_port.get_name());
-    /* Not found, mapping fails */
-    if (nullptr == physical_pb_port) {
-      return false;
-    }
-    /* If the port range does not match, mapping fails */
-    if (false == expected_physical_pb_port.contained(BasicPort(physical_pb_port->name, physical_pb_port->num_pins))) {
-      return false;
-    }
-    /* Now, port mapping should succeed, we update the vpr_pb_type_annotation */
-    vpr_pb_type_annotation.add_physical_pb_port(operating_pb_port, physical_pb_port);
-    vpr_pb_type_annotation.add_physical_pb_port_range(operating_pb_port, expected_physical_pb_port);
-  }
-
-  /* Now, pb_type mapping should succeed, we update the vpr_pb_type_annotation */
-  vpr_pb_type_annotation.add_physical_pb_type(operating_pb_type, physical_pb_type);
-
-  return true;
-}
-
-/********************************************************************
- * This function will identify the physical pb_type for each operating 
- * pb_type in VPR pb_type graph by following the explicit definition 
- * in OpenFPGA architecture XML
- *
- * Note:
- * - This function should be executed only AFTER the physical mode 
- *   annotation is completed
- *******************************************************************/
-static 
-void build_vpr_physical_pb_type_explicit_annotation(const DeviceContext& vpr_device_ctx, 
-                                                    const Arch& openfpga_arch,
-                                                    VprPbTypeAnnotation& vpr_pb_type_annotation) {
-  /* Walk through the pb_type annotation stored in the openfpga arch */
-  for (const PbTypeAnnotation& pb_type_annotation : openfpga_arch.pb_type_annotations) {
-    /* Since our target is to annotate the operating pb_type tp physical pb_type 
-     * we can skip those annotation only for physical pb_type
-     */
-    if (true == pb_type_annotation.is_physical_pb_type()) {
-      continue;
-    }
-
-    VTR_ASSERT(true == pb_type_annotation.is_operating_pb_type());
-
-    /* Collect the information about the full hierarchy of operating pb_type to be annotated */
-    std::vector<std::string> target_op_pb_type_names;
-    std::vector<std::string> target_op_pb_mode_names;
-
-    target_op_pb_type_names = pb_type_annotation.operating_parent_pb_type_names();
-    target_op_pb_type_names.push_back(pb_type_annotation.operating_pb_type_name());
-    target_op_pb_mode_names = pb_type_annotation.operating_parent_mode_names();
-
-    /* Collect the information about the full hierarchy of physical pb_type to be annotated */
-    std::vector<std::string> target_phy_pb_type_names;
-    std::vector<std::string> target_phy_pb_mode_names;
-
-    target_phy_pb_type_names = pb_type_annotation.physical_parent_pb_type_names();
-    target_phy_pb_type_names.push_back(pb_type_annotation.physical_pb_type_name());
-    target_phy_pb_mode_names = pb_type_annotation.physical_parent_mode_names();
-
-    /* We must have at least one pb_type in the list */
-    VTR_ASSERT_SAFE(0 < target_op_pb_type_names.size());
-    VTR_ASSERT_SAFE(0 < target_phy_pb_type_names.size());
-
-    /* Pb type information are located at the logic_block_types in the device context of VPR
-     * We iterate over the vectors and find the pb_type matches the parent_pb_type_name
-     */
-    bool link_success = false;
-
-    for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
-      /* By pass nullptr for pb_type head */
-      if (nullptr == lb_type.pb_type) {
-        continue;
-      }
-      /* Check the name of the top-level pb_type, if it does not match, we can bypass */
-      if (target_op_pb_type_names[0] != std::string(lb_type.pb_type->name)) {
-        continue;
-      }
-      /* Match the name in the top-level, we go further to search the operating as well as
-       * physical pb_types in the graph */
-      t_pb_type* target_op_pb_type = try_find_pb_type_with_given_path(lb_type.pb_type, target_op_pb_type_names, 
-                                                                      target_op_pb_mode_names);
-      if (nullptr == target_op_pb_type) {
-        continue;
-      }
-
-      t_pb_type* target_phy_pb_type = try_find_pb_type_with_given_path(lb_type.pb_type, target_phy_pb_type_names, 
-                                                                       target_phy_pb_mode_names);
-      if (nullptr == target_phy_pb_type) {
-        continue;
-      }
-
-      /* Both operating and physical pb_type have been found, 
-       * we update the annotation by assigning the physical mode 
-       */
-      if (true == pair_operating_and_physical_pb_types(target_op_pb_type, target_phy_pb_type,
-                                                       pb_type_annotation, vpr_pb_type_annotation)) {
-      
-        /* Give a message */
-        VTR_LOG("Annotate operating pb_type '%s' to its physical pb_type '%s'\n",
-                target_op_pb_type->name, target_phy_pb_type->name);
-
-        link_success = true;
-        break;
-      }
-    }
-
-    if (false == link_success) {
-      /* Not found, error out! */
-      VTR_LOG_ERROR("Unable to pair the operating pb_type '%s' to its physical pb_type '%s'!\n",
-                    target_op_pb_type_names.back().c_str(),
-                    target_phy_pb_type_names.back().c_str());
-      return;
-    }
-  } 
-}
-
-/********************************************************************
- * This function aims to pair a physical pb_type to itself
- *******************************************************************/
-static 
-bool self_pair_physical_pb_types(t_pb_type* physical_pb_type, 
-                                 VprPbTypeAnnotation& vpr_pb_type_annotation) {
-  /* Reach here, we should have valid physical pb_types */
-  VTR_ASSERT(nullptr != physical_pb_type);
-  
-  /* Iterate over the ports under the operating pb_type 
-   * For each pin, we will try to find its physical port in the pb_type_annotation
-   * if not found, we assume that the physical port is the same as the operating pb_port
-   */
-  for (t_port* physical_pb_port : pb_type_ports(physical_pb_type)) {
-    BasicPort physical_port_range(physical_pb_port->name, physical_pb_port->num_pins);
-    vpr_pb_type_annotation.add_physical_pb_port(physical_pb_port, physical_pb_port);
-    vpr_pb_type_annotation.add_physical_pb_port_range(physical_pb_port, physical_port_range);
-  }
-
-  /* Now, pb_type mapping should succeed, we update the vpr_pb_type_annotation */
-  vpr_pb_type_annotation.add_physical_pb_type(physical_pb_type, physical_pb_type);
-
-  return true;
-}
-
-/********************************************************************
- * This function will recursively visit all the pb_type from the top
- * pb_type in the graph (only in the physical mode) and infer the 
- * physical pb_type 
- * This is mainly applied to single-mode pb_type graphs, where the 
- * physical pb_type should be pb_type itself
- * We can infer this and save the explicit annotation required by users
- *******************************************************************/
-static 
-void rec_infer_vpr_physical_pb_type_annotation(t_pb_type* cur_pb_type, 
-                                               VprPbTypeAnnotation& vpr_pb_type_annotation) {
-  /* Physical pb_type is mainly for the primitive pb_type */
-  if (true == is_primitive_pb_type(cur_pb_type)) {
-    /* If the physical pb_type has been mapped, we can skip it */
-    if (nullptr != vpr_pb_type_annotation.physical_pb_type(cur_pb_type)) {
-      return;
-    }
-    /* Create the pair here */
-    if (true == self_pair_physical_pb_types(cur_pb_type, vpr_pb_type_annotation)) {
-      /* Give a message */
-      VTR_LOG("Implicitly infer the physical pb_type for pb_type '%s' itself\n",
-              cur_pb_type->name);
-    } else {
-      VTR_LOG_ERROR("Unable to infer the physical pb_type for pb_type '%s' itself!\n",
-                    cur_pb_type->name);
-    }
-    return;
-  }
-
-  /* Get the physical mode from annotation */ 
-  t_mode* physical_mode = vpr_pb_type_annotation.physical_mode(cur_pb_type);
-
-  VTR_ASSERT(nullptr != physical_mode);
-
-  /* Traverse the pb_type children under the physical mode */
-  for (int ichild = 0; ichild < physical_mode->num_pb_type_children; ++ichild) { 
-    rec_infer_vpr_physical_pb_type_annotation(&(physical_mode->pb_type_children[ichild]),
-                                              vpr_pb_type_annotation);
-  }
-}
-
-/********************************************************************
- * This function will infer the physical pb_type for each operating 
- * pb_type in VPR pb_type graph which have not been explicitedly defined
- * in OpenFPGA architecture XML
- *
- * Note:
- * - This function should be executed only AFTER the physical mode 
- *   annotation is completed
- *******************************************************************/
-static 
-void build_vpr_physical_pb_type_implicit_annotation(const DeviceContext& vpr_device_ctx, 
-                                                    VprPbTypeAnnotation& vpr_pb_type_annotation) {
-  for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
-    /* By pass nullptr for pb_type head */
-    if (nullptr == lb_type.pb_type) {
-      continue;
-    }
-    rec_infer_vpr_physical_pb_type_annotation(lb_type.pb_type, vpr_pb_type_annotation); 
-  }
-}
-
 /********************************************************************
  * Top-level function to link openfpga architecture to VPR, including:
  * - physical pb_type
- * - idle pb_type 
- * - circuit models for pb_type, pb interconnect and routing architecture
+ * - mode selection bits for pb_type and pb interconnect
+ * - circuit models for pb_type and pb interconnect
+ * - physical pb_graph nodes and pb_graph pins
+ * - circuit models for global routing architecture
  *******************************************************************/
 void link_arch(OpenfpgaContext& openfpga_context) {
 
   vtr::ScopedStartFinishTimer timer("Link OpenFPGA architecture to VPR architecture");
 
-  /* Annotate physical mode to pb_type in the VPR pb_type graph */
-  build_vpr_physical_pb_mode_explicit_annotation(g_vpr_ctx.device(), openfpga_context.arch(),
-                                                 openfpga_context.mutable_vpr_pb_type_annotation());
-  build_vpr_physical_pb_mode_implicit_annotation(g_vpr_ctx.device(), 
-                                                 openfpga_context.mutable_vpr_pb_type_annotation());
-
-  check_vpr_physical_pb_mode_annotation(g_vpr_ctx.device(), 
-                                        openfpga_context.vpr_pb_type_annotation());
-
-  /* Annotate physical pb_types to operating pb_type in the VPR pb_type graph */
-  build_vpr_physical_pb_type_explicit_annotation(g_vpr_ctx.device(), openfpga_context.arch(),
-                                                 openfpga_context.mutable_vpr_pb_type_annotation());
-
-  build_vpr_physical_pb_type_implicit_annotation(g_vpr_ctx.device(),
-                                                 openfpga_context.mutable_vpr_pb_type_annotation());
-
-  /* Link physical pb_type to circuit model */
+  /* Annotate pb_type graphs
+   * - physical pb_type
+   * - mode selection bits for pb_type and pb interconnect
+   * - circuit models for pb_type and pb interconnect
+   */
+  annotate_pb_types(g_vpr_ctx.device(), openfpga_context.arch(),
+                    openfpga_context.mutable_vpr_pb_type_annotation());
 
   /* Link routing architecture to circuit model */
 } 
diff --git a/openfpga/src/base/openfpga_link_arch.h b/openfpga/src/base/openfpga_link_arch.h
index c36c57711..3775ee789 100644
--- a/openfpga/src/base/openfpga_link_arch.h
+++ b/openfpga/src/base/openfpga_link_arch.h
@@ -1,5 +1,5 @@
-#ifndef OPENFPGA_LINK_ARCH_COMMAND_H
-#define OPENFPGA_LINK_ARCH_COMMAND_H
+#ifndef OPENFPGA_LINK_ARCH_H
+#define OPENFPGA_LINK_ARCH_H
 
 /********************************************************************
  * Include header files that are required by function declaration
diff --git a/openfpga/src/base/pb_type_utils.cpp b/openfpga/src/base/pb_type_utils.cpp
index 1d0c31b6c..980614538 100644
--- a/openfpga/src/base/pb_type_utils.cpp
+++ b/openfpga/src/base/pb_type_utils.cpp
@@ -88,4 +88,54 @@ t_port* find_pb_type_port(t_pb_type* pb_type, const std::string& port_name) {
   return nullptr;
 }
 
+/********************************************************************
+ * This function will traverse pb_type graph from its top to find
+ * a pb_type with a given name as well as its hierarchy 
+ *******************************************************************/
+t_pb_type* try_find_pb_type_with_given_path(t_pb_type* top_pb_type, 
+                                            const std::vector<std::string>& target_pb_type_names, 
+                                            const std::vector<std::string>& target_pb_mode_names) {
+  /* Ensure that number of parent names and modes matches */
+  VTR_ASSERT_SAFE(target_pb_type_names.size() == target_pb_mode_names.size() + 1);
+
+  t_pb_type* cur_pb_type = top_pb_type;
+
+  /* If the top pb_type is what we want, we can return here */
+  if (1 == target_pb_type_names.size()) {
+    if (target_pb_type_names[0] == std::string(top_pb_type->name)) {
+      return top_pb_type;
+    }
+    /* Not match, return null pointer */
+    return nullptr;
+  }
+
+  /* We start from the first element of the parent names and parent modes.
+   * If the pb_type does not match in name, we fail 
+   * If we cannot find a mode match the name, we fail 
+   */
+  for (size_t i = 0; i < target_pb_type_names.size() - 1; ++i) {
+    /* If this level does not match, search fail */
+    if (target_pb_type_names[i] != std::string(cur_pb_type->name)) {
+      return nullptr;
+    }
+    /* Find if the mode matches */
+    t_mode* cur_mode = find_pb_type_mode(cur_pb_type, target_pb_mode_names[i].c_str()); 
+    if (nullptr == cur_mode) {
+      return nullptr;
+    }
+    /* Go to the next level of pb_type */
+    cur_pb_type = find_mode_child_pb_type(cur_mode, target_pb_type_names[i + 1].c_str());
+    if (nullptr == cur_pb_type) {
+      return nullptr;
+    }
+    /* If this is already the last pb_type in the list, this is what we want */
+    if (i + 1 == target_pb_type_names.size() - 1) {
+      return cur_pb_type;
+    }
+  }
+
+  /* Reach here, it means we find nothing */
+  return nullptr;
+}
+
 } /* end namespace openfpga */
diff --git a/openfpga/src/base/pb_type_utils.h b/openfpga/src/base/pb_type_utils.h
index 902f203e3..aa658d9da 100644
--- a/openfpga/src/base/pb_type_utils.h
+++ b/openfpga/src/base/pb_type_utils.h
@@ -4,6 +4,7 @@
 /********************************************************************
  * Include header files that are required by function declaration
  *******************************************************************/
+#include <string>
 #include <vector>
 #include "physical_types.h"
 
@@ -26,6 +27,10 @@ std::vector<t_port*> pb_type_ports(t_pb_type* pb_type);
 
 t_port* find_pb_type_port(t_pb_type* pb_type, const std::string& port_name);
 
+t_pb_type* try_find_pb_type_with_given_path(t_pb_type* top_pb_type, 
+                                            const std::vector<std::string>& target_pb_type_names, 
+                                            const std::vector<std::string>& target_pb_mode_names);
+
 } /* end namespace openfpga */
 
 #endif

From a4a84ca35bdac12a1e7e3c14f49c969bbe88bb3b Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 28 Jan 2020 15:27:00 -0700
Subject: [PATCH 035/645] add check codes for physical pb_type and port
 annotation

---
 openfpga/src/base/annotate_pb_types.cpp | 89 +++++++++++++++++++++++++
 1 file changed, 89 insertions(+)

diff --git a/openfpga/src/base/annotate_pb_types.cpp b/openfpga/src/base/annotate_pb_types.cpp
index fe7629281..ae0106ca5 100644
--- a/openfpga/src/base/annotate_pb_types.cpp
+++ b/openfpga/src/base/annotate_pb_types.cpp
@@ -498,6 +498,92 @@ void build_vpr_physical_pb_type_implicit_annotation(const DeviceContext& vpr_dev
   }
 }
 
+/********************************************************************
+ * This function will check 
+ * - if a primitive pb_type has been mapped to a physical pb_type 
+ * - if every port of the pb_type have been linked a port of a physical pb_type
+ *******************************************************************/
+static 
+void check_vpr_physical_primitive_pb_type_annotation(t_pb_type* cur_pb_type,
+                                                     const VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                                     size_t& num_err) {
+  if (nullptr == vpr_pb_type_annotation.physical_pb_type(cur_pb_type)) {
+    VTR_LOG_ERROR("Find a pb_type '%s' which has not been mapped to any physical pb_type!\n",
+                  cur_pb_type->name);
+    VTR_LOG_ERROR("Please specify in the OpenFPGA architecture\n");
+    num_err++;  
+    return;
+  }
+
+  /* Now we need to check each port of the pb_type */ 
+  for (t_port* pb_port : pb_type_ports(cur_pb_type)) {
+    if (nullptr == vpr_pb_type_annotation.physical_pb_port(pb_port)) {
+      VTR_LOG_ERROR("Find a port '%s' of pb_type '%s' which has not been mapped to any physical port!\n",
+                    pb_port->name, cur_pb_type->name);
+      VTR_LOG_ERROR("Please specify in the OpenFPGA architecture\n");
+      num_err++;
+    }
+  }
+
+  return;
+}
+
+/********************************************************************
+ * This function will recursively traverse pb_type graph to ensure
+ * 1. there is only a physical mode under each pb_type
+ * 2. physical mode appears only when its parent is a physical mode.
+ *******************************************************************/
+static 
+void rec_check_vpr_physical_pb_type_annotation(t_pb_type* cur_pb_type,
+                                               const VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                               size_t& num_err) {
+  /* Primitive pb_type should always been binded to a physical pb_type */
+  if (true == is_primitive_pb_type(cur_pb_type)) {
+    check_vpr_physical_primitive_pb_type_annotation(cur_pb_type, vpr_pb_type_annotation, num_err);
+    return;
+  }
+
+  /* Traverse all the modes
+   * - for pb_type children under a physical mode, we expect an physical mode 
+   * - for pb_type children under non-physical mode, we expect no physical mode 
+   */
+  for (int imode = 0; imode < cur_pb_type->num_modes; ++imode) {
+    for (int ichild = 0; ichild < cur_pb_type->modes[imode].num_pb_type_children; ++ichild) { 
+      rec_check_vpr_physical_pb_type_annotation(&(cur_pb_type->modes[imode].pb_type_children[ichild]),
+                                                vpr_pb_type_annotation,
+                                                num_err);
+    }
+  }
+}
+
+/********************************************************************
+ * This function will check the physical pb_type annotation for
+ * each pb_type in the device
+ * Every pb_type should have been linked to a physical pb_type
+ * and every port of the pb_type have been linked a port of a physical pb_type
+ *******************************************************************/
+static 
+void check_vpr_physical_pb_type_annotation(const DeviceContext& vpr_device_ctx, 
+                                           const VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  size_t num_err = 0;
+
+  for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
+    /* By pass nullptr for pb_type head */
+    if (nullptr == lb_type.pb_type) {
+      continue;
+    }
+    /* Top pb_type should always has a physical mode! */
+    rec_check_vpr_physical_pb_type_annotation(lb_type.pb_type, vpr_pb_type_annotation, num_err);
+  }
+  if (0 == num_err) {
+    VTR_LOG("Check physical pb_type annotation for pb_types passed.\n");
+  } else {
+    VTR_LOG("Check physical pb_type annotation for pb_types failed with %ld errors!\n",
+            num_err);
+  }
+}
+
+
 /********************************************************************
  * Top-level function to link openfpga architecture to VPR, including:
  * - physical pb_type
@@ -523,6 +609,9 @@ void annotate_pb_types(const DeviceContext& vpr_device_ctx,
   build_vpr_physical_pb_type_implicit_annotation(vpr_device_ctx,
                                                  vpr_pb_type_annotation);
 
+  check_vpr_physical_pb_type_annotation(vpr_device_ctx, 
+                                        const_cast<const VprPbTypeAnnotation&>(vpr_pb_type_annotation));
+
   /* Link physical pb_type to circuit model */
 
   /* Link routing architecture to circuit model */

From 1651c9ca188b64a940d4d2412c1108594f9cc28a Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 28 Jan 2020 16:03:02 -0700
Subject: [PATCH 036/645] add binding between physical pb_type and circuit
 models

---
 openfpga/src/base/annotate_pb_types.cpp       | 130 +++++++++++++++++-
 openfpga/src/base/vpr_pb_type_annotation.cpp  |  33 ++++-
 openfpga/src/base/vpr_pb_type_annotation.h    |   6 +-
 .../k6_N10_40nm_openfpga.xml                  |   6 +-
 4 files changed, 166 insertions(+), 9 deletions(-)

diff --git a/openfpga/src/base/annotate_pb_types.cpp b/openfpga/src/base/annotate_pb_types.cpp
index ae0106ca5..3186a896d 100644
--- a/openfpga/src/base/annotate_pb_types.cpp
+++ b/openfpga/src/base/annotate_pb_types.cpp
@@ -583,6 +583,125 @@ void check_vpr_physical_pb_type_annotation(const DeviceContext& vpr_device_ctx,
   }
 }
 
+/********************************************************************
+ * This function aims to link a physical pb_type to a valid circuit model
+ * in the circuit library
+ *******************************************************************/
+static 
+bool link_physical_pb_type_to_circuit_model(t_pb_type* physical_pb_type, 
+                                            const CircuitLibrary& circuit_lib,
+                                            const PbTypeAnnotation& pb_type_annotation,
+                                            VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  /* Reach here, we should have valid operating and physical pb_types */
+  VTR_ASSERT(nullptr != physical_pb_type);
+
+  /* This must be a physical pb_type according to our annotation! */
+  if (false == vpr_pb_type_annotation.is_physical_pb_type(physical_pb_type)) {
+    VTR_LOG_ERROR("An operating pb_type '%s' is not allowed to be linked to any circuit model!\n",
+                  physical_pb_type->name);
+    return false;
+  }
+
+  std::string pb_type_circuit_model_name = pb_type_annotation.circuit_model_name();
+  CircuitModelId circuit_model_id = circuit_lib.model(pb_type_circuit_model_name);
+
+  if (CircuitModelId::INVALID() == circuit_model_id) {
+    return false;
+  }
+
+  /* Now the circuit model is valid, update the vpr_pb_type_annotation */
+  vpr_pb_type_annotation.add_pb_type_circuit_model(physical_pb_type, circuit_model_id);
+  return true;
+}
+
+/********************************************************************
+ * This function will link 
+ * - pb_type to circuit models in circuit library by following 
+ *   the explicit definition in OpenFPGA architecture XML
+ * - interconnect of pb_type to circuit models in circuit library by following 
+ *   the explicit definition in OpenFPGA architecture XML
+ *
+ * Note:
+ * - This function should be executed only AFTER the physical mode and
+ *   physical pb_type annotation is completed
+ *******************************************************************/
+static 
+void link_vpr_pb_type_to_circuit_model_explicit_annotation(const DeviceContext& vpr_device_ctx, 
+                                                           const Arch& openfpga_arch,
+                                                           VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  /* Walk through the pb_type annotation stored in the openfpga arch */
+  for (const PbTypeAnnotation& pb_type_annotation : openfpga_arch.pb_type_annotations) {
+    /* Since our target is to annotate the circuti model for physical pb_type 
+     * we can skip those annotation only for operating pb_type
+     */
+    if (true == pb_type_annotation.is_operating_pb_type()) {
+      continue;
+    }
+
+    /* Bypass those who have no circuit model defined */
+    if (true == pb_type_annotation.circuit_model_name().empty()) {
+      continue;
+    }
+
+    VTR_ASSERT(true == pb_type_annotation.is_physical_pb_type());
+
+    /* Collect the information about the full hierarchy of physical pb_type to be annotated */
+    std::vector<std::string> target_phy_pb_type_names;
+    std::vector<std::string> target_phy_pb_mode_names;
+
+    target_phy_pb_type_names = pb_type_annotation.physical_parent_pb_type_names();
+    target_phy_pb_type_names.push_back(pb_type_annotation.physical_pb_type_name());
+    target_phy_pb_mode_names = pb_type_annotation.physical_parent_mode_names();
+
+    /* We must have at least one pb_type in the list */
+    VTR_ASSERT_SAFE(0 < target_phy_pb_type_names.size());
+
+    /* Pb type information are located at the logic_block_types in the device context of VPR
+     * We iterate over the vectors and find the pb_type matches the parent_pb_type_name
+     */
+    bool link_success = false;
+
+    for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
+      /* By pass nullptr for pb_type head */
+      if (nullptr == lb_type.pb_type) {
+        continue;
+      }
+      /* Check the name of the top-level pb_type, if it does not match, we can bypass */
+      if (target_phy_pb_type_names[0] != std::string(lb_type.pb_type->name)) {
+        continue;
+      }
+      /* Match the name in the top-level, we go further to search the operating as well as
+       * physical pb_types in the graph */
+      t_pb_type* target_phy_pb_type = try_find_pb_type_with_given_path(lb_type.pb_type, target_phy_pb_type_names, 
+                                                                       target_phy_pb_mode_names);
+      if (nullptr == target_phy_pb_type) {
+        continue;
+      }
+
+      /* Both operating and physical pb_type have been found, 
+       * we update the annotation by assigning the physical mode 
+       */
+      if (true == link_physical_pb_type_to_circuit_model(target_phy_pb_type, openfpga_arch.circuit_lib,
+                                                         pb_type_annotation, vpr_pb_type_annotation)) {
+        /* Give a message */
+        VTR_LOG("Bind physical pb_type '%s' to its circuit model '%s'\n",
+                target_phy_pb_type->name,
+                openfpga_arch.circuit_lib.model_name(vpr_pb_type_annotation.pb_type_circuit_model(target_phy_pb_type)).c_str());
+
+        link_success = true;
+        break;
+      }
+    }
+
+    if (false == link_success) {
+      /* Not found, error out! */
+      VTR_LOG_ERROR("Unable to bind physical pb_type '%s' to circuit model '%s'!\n",
+                    target_phy_pb_type_names.back().c_str(),
+                    pb_type_annotation.circuit_model_name().c_str());
+      return;
+    }
+  } 
+}
 
 /********************************************************************
  * Top-level function to link openfpga architecture to VPR, including:
@@ -596,6 +715,7 @@ void annotate_pb_types(const DeviceContext& vpr_device_ctx,
   /* Annotate physical mode to pb_type in the VPR pb_type graph */
   build_vpr_physical_pb_mode_explicit_annotation(vpr_device_ctx, openfpga_arch,
                                                  vpr_pb_type_annotation);
+
   build_vpr_physical_pb_mode_implicit_annotation(vpr_device_ctx,
                                                  vpr_pb_type_annotation);
 
@@ -612,9 +732,15 @@ void annotate_pb_types(const DeviceContext& vpr_device_ctx,
   check_vpr_physical_pb_type_annotation(vpr_device_ctx, 
                                         const_cast<const VprPbTypeAnnotation&>(vpr_pb_type_annotation));
 
-  /* Link physical pb_type to circuit model */
+  /* Link 
+   * - physical pb_type to circuit model
+   * - interconnect of physical pb_type to circuit model 
+   */
+  link_vpr_pb_type_to_circuit_model_explicit_annotation(vpr_device_ctx, openfpga_arch,
+                                                        vpr_pb_type_annotation);
+
+  /* Link physical pb_type to mode_bits */
 
-  /* Link routing architecture to circuit model */
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/base/vpr_pb_type_annotation.cpp b/openfpga/src/base/vpr_pb_type_annotation.cpp
index e89045307..2dedacb28 100644
--- a/openfpga/src/base/vpr_pb_type_annotation.cpp
+++ b/openfpga/src/base/vpr_pb_type_annotation.cpp
@@ -16,8 +16,18 @@ VprPbTypeAnnotation::VprPbTypeAnnotation() {
 }
 
 /************************************************************************
- * Public mutators
+ * Public accessors
  ***********************************************************************/
+bool VprPbTypeAnnotation::is_physical_pb_type(t_pb_type* pb_type) const {
+  /* Ensure that the pb_type is in the list */
+  std::map<t_pb_type*, t_pb_type*>::const_iterator it = physical_pb_types_.find(pb_type);
+  if (it == physical_pb_types_.end()) {
+    return false;
+  }
+  /* A physical pb_type should be mapped to itself! Otherwise, it is an operating pb_type */
+  return pb_type == physical_pb_types_.at(pb_type);
+}
+
 t_mode* VprPbTypeAnnotation::physical_mode(t_pb_type* pb_type) const {
   /* Ensure that the pb_type is in the list */
   std::map<t_pb_type*, t_mode*>::const_iterator it = physical_pb_modes_.find(pb_type);
@@ -55,6 +65,16 @@ BasicPort VprPbTypeAnnotation::physical_pb_port_range(t_port* pb_port) const {
   return physical_pb_port_ranges_.at(pb_port);
 }
 
+CircuitModelId VprPbTypeAnnotation::pb_type_circuit_model(t_pb_type* physical_pb_type) const {
+  /* Ensure that the pb_type is in the list */
+  std::map<t_pb_type*, CircuitModelId>::const_iterator it = pb_type_circuit_models_.find(physical_pb_type);
+  if (it == pb_type_circuit_models_.end()) {
+    /* Return an invalid port. As such the port width will be 0, which is an invalid value */
+    return CircuitModelId::INVALID();
+  }
+  return pb_type_circuit_models_.at(physical_pb_type);
+}
+
 /************************************************************************
  * Public mutators
  ***********************************************************************/
@@ -105,4 +125,15 @@ void VprPbTypeAnnotation::add_physical_pb_port_range(t_port* operating_pb_port,
   physical_pb_port_ranges_[operating_pb_port] = port_range;
 }
 
+void VprPbTypeAnnotation::add_pb_type_circuit_model(t_pb_type* physical_pb_type, const CircuitModelId& circuit_model) {
+  /* Warn any override attempt */
+  std::map<t_pb_type*, CircuitModelId>::const_iterator it = pb_type_circuit_models_.find(physical_pb_type);
+  if (it != pb_type_circuit_models_.end()) {
+    VTR_LOG_WARN("Override the circuit model for physical pb_type '%s'!\n",
+                 physical_pb_type->name);
+  }
+
+  pb_type_circuit_models_[physical_pb_type] = circuit_model;
+}
+
 } /* End namespace openfpga*/
diff --git a/openfpga/src/base/vpr_pb_type_annotation.h b/openfpga/src/base/vpr_pb_type_annotation.h
index 90b29598f..e235538e7 100644
--- a/openfpga/src/base/vpr_pb_type_annotation.h
+++ b/openfpga/src/base/vpr_pb_type_annotation.h
@@ -29,19 +29,19 @@ class VprPbTypeAnnotation {
   public:  /* Constructor */
     VprPbTypeAnnotation();
   public:  /* Public accessors */
+    bool is_physical_pb_type(t_pb_type* pb_type) const;
     t_mode* physical_mode(t_pb_type* pb_type) const;
     t_pb_type* physical_pb_type(t_pb_type* pb_type) const;
     t_port* physical_pb_port(t_port* pb_port) const;
     BasicPort physical_pb_port_range(t_port* pb_port) const;
+    CircuitModelId pb_type_circuit_model(t_pb_type* physical_pb_type) const;
   public:  /* Public mutators */
     void add_pb_type_physical_mode(t_pb_type* pb_type, t_mode* physical_mode);
     void add_physical_pb_type(t_pb_type* operating_pb_type, t_pb_type* physical_pb_type);
     void add_physical_pb_port(t_port* operating_pb_port, t_port* physical_pb_port);
     void add_physical_pb_port_range(t_port* operating_pb_port, const BasicPort& port_range);
+    void add_pb_type_circuit_model(t_pb_type* physical_pb_type, const CircuitModelId& circuit_model);
   private: /* Internal data */
-    /* Flag about if a pb_type is a physical pb_type */
-    std::map<t_pb_type*, bool> is_physical_pb_types_;
-
     /* Pair a regular pb_type to its physical pb_type */
     std::map<t_pb_type*, t_pb_type*> physical_pb_types_;
 
diff --git a/openfpga/test_openfpga_arch/k6_N10_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_N10_40nm_openfpga.xml
index 23607e234..d93495f6b 100644
--- a/openfpga/test_openfpga_arch/k6_N10_40nm_openfpga.xml
+++ b/openfpga/test_openfpga_arch/k6_N10_40nm_openfpga.xml
@@ -134,16 +134,16 @@
        <port type="output" prefix="Q" size="1"/>
        <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
     </circuit_model>
-    <circuit_model type="lut" name="lut5" prefix="lut5" dump_structural_verilog="true">
+    <circuit_model type="lut" name="lut6" prefix="lut6" dump_structural_verilog="true">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
       <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
       <lut_input_buffer exist="true" circuit_model_name="buf4"/>
       <pass_gate_logic circuit_model_name="TGATE"/>
-      <port type="input" prefix="in" size="5"/>
+      <port type="input" prefix="in" size="6"/>
       <port type="output" prefix="out" size="1"/>
-      <port type="sram" prefix="sram" size="32"/>
+      <port type="sram" prefix="sram" size="64"/>
     </circuit_model>
     <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
     <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">

From bb7fa2af77b1df514e70b809133c6cd0f5a992f6 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 28 Jan 2020 17:04:10 -0700
Subject: [PATCH 037/645] add pb interconnect binding to circuit model

---
 openfpga/src/base/annotate_pb_types.cpp      | 154 ++++++++++++++++++-
 openfpga/src/base/pb_type_utils.cpp          |  16 ++
 openfpga/src/base/pb_type_utils.h            |   2 +
 openfpga/src/base/vpr_pb_type_annotation.cpp |  23 ++-
 openfpga/src/base/vpr_pb_type_annotation.h   |   8 +
 openfpga/test_script/s298.openfpga           |   3 +
 6 files changed, 199 insertions(+), 7 deletions(-)

diff --git a/openfpga/src/base/annotate_pb_types.cpp b/openfpga/src/base/annotate_pb_types.cpp
index 3186a896d..e8e7ddab4 100644
--- a/openfpga/src/base/annotate_pb_types.cpp
+++ b/openfpga/src/base/annotate_pb_types.cpp
@@ -606,6 +606,9 @@ bool link_physical_pb_type_to_circuit_model(t_pb_type* physical_pb_type,
   CircuitModelId circuit_model_id = circuit_lib.model(pb_type_circuit_model_name);
 
   if (CircuitModelId::INVALID() == circuit_model_id) {
+    VTR_LOG_ERROR("Unable to find a circuit model '%s' for physical pb_type '%s'!\n",
+                  pb_type_circuit_model_name.c_str(),
+                  physical_pb_type->name); 
     return false;
   }
 
@@ -614,12 +617,68 @@ bool link_physical_pb_type_to_circuit_model(t_pb_type* physical_pb_type,
   return true;
 }
 
+/********************************************************************
+ * This function aims to link an interconnect of a physical mode of 
+ * a pb_type to a valid circuit model in the circuit library
+ *******************************************************************/
+static 
+bool link_physical_pb_interconnect_to_circuit_model(t_pb_type* physical_pb_type, 
+                                                    const std::string& interconnect_name,
+                                                    const CircuitLibrary& circuit_lib,
+                                                    const PbTypeAnnotation& pb_type_annotation,
+                                                    VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  /* The physical pb_type should NOT be a primitive, otherwise it should never contain any interconnect */
+  if (true == is_primitive_pb_type(physical_pb_type)) {
+    VTR_LOG_ERROR("Link interconnect to circuit model is not allowed for a primitive pb_type '%s'!\n",
+                  physical_pb_type->name);
+    return false;
+  }
+
+  /* Get the physical mode from annotation */ 
+  t_mode* physical_mode = vpr_pb_type_annotation.physical_mode(physical_pb_type);
+
+  VTR_ASSERT(nullptr != physical_mode);
+
+  /* Find the interconnect name under the physical mode of a physical pb_type */
+  t_interconnect* pb_interc = find_pb_mode_interconnect(physical_mode, interconnect_name.c_str());
+
+  if (nullptr == pb_interc) {
+    VTR_LOG_ERROR("Unable to find interconnect '%s' under physical mode '%s' of pb_type '%s'!\n",
+                  interconnect_name.c_str(), 
+                  physical_mode->name, 
+                  physical_pb_type->name);
+    return false;
+  }
+
+  /* Try to find the circuit model name */
+  std::string pb_type_circuit_model_name = pb_type_annotation.interconnect_circuit_model_name(interconnect_name);
+  CircuitModelId circuit_model_id = circuit_lib.model(pb_type_circuit_model_name);
+
+  if (CircuitModelId::INVALID() == circuit_model_id) {
+    VTR_LOG_ERROR("Unable to find a circuit model '%s' for interconnect '%s' under physical mode '%s' of pb_type '%s'!\n",
+                  pb_type_circuit_model_name.c_str(),
+                  interconnect_name.c_str(), 
+                  physical_mode->name, 
+                  physical_pb_type->name);
+    return false;
+  }
+
+  /* Now the circuit model is valid, update the vpr_pb_type_annotation */
+  vpr_pb_type_annotation.add_interconnect_circuit_model(pb_interc, circuit_model_id);
+
+  VTR_LOG("Bind pb_type '%s' physical mode '%s' interconnect '%s' to circuit model '%s'\n",
+           physical_pb_type->name,
+           physical_mode->name,
+           pb_interc->name,
+           circuit_lib.model_name(circuit_model_id).c_str());
+
+  return true;
+}
+
 /********************************************************************
  * This function will link 
  * - pb_type to circuit models in circuit library by following 
  *   the explicit definition in OpenFPGA architecture XML
- * - interconnect of pb_type to circuit models in circuit library by following 
- *   the explicit definition in OpenFPGA architecture XML
  *
  * Note:
  * - This function should be executed only AFTER the physical mode and
@@ -638,7 +697,6 @@ void link_vpr_pb_type_to_circuit_model_explicit_annotation(const DeviceContext&
       continue;
     }
 
-    /* Bypass those who have no circuit model defined */
     if (true == pb_type_annotation.circuit_model_name().empty()) {
       continue;
     }
@@ -678,9 +736,7 @@ void link_vpr_pb_type_to_circuit_model_explicit_annotation(const DeviceContext&
         continue;
       }
 
-      /* Both operating and physical pb_type have been found, 
-       * we update the annotation by assigning the physical mode 
-       */
+      /* Only try to bind pb_type to circuit model when it is defined by users */
       if (true == link_physical_pb_type_to_circuit_model(target_phy_pb_type, openfpga_arch.circuit_lib,
                                                          pb_type_annotation, vpr_pb_type_annotation)) {
         /* Give a message */
@@ -703,6 +759,90 @@ void link_vpr_pb_type_to_circuit_model_explicit_annotation(const DeviceContext&
   } 
 }
 
+/********************************************************************
+ * This function will link 
+ * - interconnect of pb_type to circuit models in circuit library by following 
+ *   the explicit definition in OpenFPGA architecture XML
+ *
+ * Note:
+ * - This function should be executed only AFTER the physical mode and
+ *   physical pb_type annotation is completed
+ *******************************************************************/
+static 
+void link_vpr_pb_interconnect_to_circuit_model_explicit_annotation(const DeviceContext& vpr_device_ctx, 
+                                                                   const Arch& openfpga_arch,
+                                                                   VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  /* Walk through the pb_type annotation stored in the openfpga arch */
+  for (const PbTypeAnnotation& pb_type_annotation : openfpga_arch.pb_type_annotations) {
+    /* Since our target is to annotate the circuti model for physical pb_type 
+     * we can skip those annotation only for operating pb_type
+     */
+    if (true == pb_type_annotation.is_operating_pb_type()) {
+      continue;
+    }
+
+    if (0 == pb_type_annotation.interconnect_names().size()) {
+      continue;
+    }
+
+    VTR_ASSERT(true == pb_type_annotation.is_physical_pb_type());
+
+    /* Collect the information about the full hierarchy of physical pb_type to be annotated */
+    std::vector<std::string> target_phy_pb_type_names;
+    std::vector<std::string> target_phy_pb_mode_names;
+
+    target_phy_pb_type_names = pb_type_annotation.physical_parent_pb_type_names();
+    target_phy_pb_type_names.push_back(pb_type_annotation.physical_pb_type_name());
+    target_phy_pb_mode_names = pb_type_annotation.physical_parent_mode_names();
+
+    /* We must have at least one pb_type in the list */
+    VTR_ASSERT_SAFE(0 < target_phy_pb_type_names.size());
+
+    /* Pb type information are located at the logic_block_types in the device context of VPR
+     * We iterate over the vectors and find the pb_type matches the parent_pb_type_name
+     */
+    bool link_success = true;
+
+    for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
+      /* By pass nullptr for pb_type head */
+      if (nullptr == lb_type.pb_type) {
+        continue;
+      }
+      /* Check the name of the top-level pb_type, if it does not match, we can bypass */
+      if (target_phy_pb_type_names[0] != std::string(lb_type.pb_type->name)) {
+        continue;
+      }
+      /* Match the name in the top-level, we go further to search the operating as well as
+       * physical pb_types in the graph */
+      t_pb_type* target_phy_pb_type = try_find_pb_type_with_given_path(lb_type.pb_type, target_phy_pb_type_names, 
+                                                                       target_phy_pb_mode_names);
+      if (nullptr == target_phy_pb_type) {
+        continue;
+      }
+
+      /* Only try to bind interconnect to circuit model when it is defined by users */
+      for (const std::string& interc_name : pb_type_annotation.interconnect_names()) {
+        if (false == link_physical_pb_interconnect_to_circuit_model(target_phy_pb_type, interc_name, openfpga_arch.circuit_lib,
+                                                                    pb_type_annotation, vpr_pb_type_annotation)) {
+           VTR_LOG_ERROR("Unable to bind pb_type '%s' interconnect '%s' to circuit model '%s'!\n",
+                          target_phy_pb_type_names.back().c_str(),
+                          interc_name.c_str(),
+                          pb_type_annotation.circuit_model_name().c_str());
+           link_success = false;
+        } 
+      }
+    }
+
+    if (false == link_success) {
+      /* Not found, error out! */
+      VTR_LOG_ERROR("Unable to bind interconnects of physical pb_type '%s' to circuit model '%s'!\n",
+                    target_phy_pb_type_names.back().c_str(),
+                    pb_type_annotation.circuit_model_name().c_str());
+      return;
+    }
+  } 
+}
+
 /********************************************************************
  * Top-level function to link openfpga architecture to VPR, including:
  * - physical pb_type
@@ -738,6 +878,8 @@ void annotate_pb_types(const DeviceContext& vpr_device_ctx,
    */
   link_vpr_pb_type_to_circuit_model_explicit_annotation(vpr_device_ctx, openfpga_arch,
                                                         vpr_pb_type_annotation);
+  link_vpr_pb_interconnect_to_circuit_model_explicit_annotation(vpr_device_ctx, openfpga_arch,
+                                                                vpr_pb_type_annotation);
 
   /* Link physical pb_type to mode_bits */
 
diff --git a/openfpga/src/base/pb_type_utils.cpp b/openfpga/src/base/pb_type_utils.cpp
index 980614538..93b644b8c 100644
--- a/openfpga/src/base/pb_type_utils.cpp
+++ b/openfpga/src/base/pb_type_utils.cpp
@@ -138,4 +138,20 @@ t_pb_type* try_find_pb_type_with_given_path(t_pb_type* top_pb_type,
   return nullptr;
 }
 
+/********************************************************************
+ * This function will try to find an interconnect defined under a mode
+ * of pb_type with a given name.
+ * If not found, return null pointer
+ *******************************************************************/
+t_interconnect* find_pb_mode_interconnect(t_mode* pb_mode, const char* interc_name) {
+  for (int i = 0; i < pb_mode->num_interconnect; ++i) {
+    if (std::string(interc_name) == std::string(pb_mode->interconnect[i].name)) {
+      return &(pb_mode->interconnect[i]);
+    }
+  } 
+
+  /* Reach here, it means we find nothing */
+  return nullptr;
+}
+
 } /* end namespace openfpga */
diff --git a/openfpga/src/base/pb_type_utils.h b/openfpga/src/base/pb_type_utils.h
index aa658d9da..3e9f9a07f 100644
--- a/openfpga/src/base/pb_type_utils.h
+++ b/openfpga/src/base/pb_type_utils.h
@@ -31,6 +31,8 @@ t_pb_type* try_find_pb_type_with_given_path(t_pb_type* top_pb_type,
                                             const std::vector<std::string>& target_pb_type_names, 
                                             const std::vector<std::string>& target_pb_mode_names);
 
+t_interconnect* find_pb_mode_interconnect(t_mode* pb_mode, const char* interc_name);
+
 } /* end namespace openfpga */
 
 #endif
diff --git a/openfpga/src/base/vpr_pb_type_annotation.cpp b/openfpga/src/base/vpr_pb_type_annotation.cpp
index 2dedacb28..8949d13c3 100644
--- a/openfpga/src/base/vpr_pb_type_annotation.cpp
+++ b/openfpga/src/base/vpr_pb_type_annotation.cpp
@@ -69,12 +69,22 @@ CircuitModelId VprPbTypeAnnotation::pb_type_circuit_model(t_pb_type* physical_pb
   /* Ensure that the pb_type is in the list */
   std::map<t_pb_type*, CircuitModelId>::const_iterator it = pb_type_circuit_models_.find(physical_pb_type);
   if (it == pb_type_circuit_models_.end()) {
-    /* Return an invalid port. As such the port width will be 0, which is an invalid value */
+    /* Return an invalid circuit model id */
     return CircuitModelId::INVALID();
   }
   return pb_type_circuit_models_.at(physical_pb_type);
 }
 
+CircuitModelId VprPbTypeAnnotation::interconnect_circuit_model(t_interconnect* pb_interconnect) const {
+  /* Ensure that the pb_type is in the list */
+  std::map<t_interconnect*, CircuitModelId>::const_iterator it = interconnect_circuit_models_.find(pb_interconnect);
+  if (it == interconnect_circuit_models_.end()) {
+    /* Return an invalid circuit model id */
+    return CircuitModelId::INVALID();
+  }
+  return interconnect_circuit_models_.at(pb_interconnect);
+}
+
 /************************************************************************
  * Public mutators
  ***********************************************************************/
@@ -136,4 +146,15 @@ void VprPbTypeAnnotation::add_pb_type_circuit_model(t_pb_type* physical_pb_type,
   pb_type_circuit_models_[physical_pb_type] = circuit_model;
 }
 
+void VprPbTypeAnnotation::add_interconnect_circuit_model(t_interconnect* pb_interconnect, const CircuitModelId& circuit_model) {
+  /* Warn any override attempt */
+  std::map<t_interconnect*, CircuitModelId>::const_iterator it = interconnect_circuit_models_.find(pb_interconnect);
+  if (it != interconnect_circuit_models_.end()) {
+    VTR_LOG_WARN("Override the circuit model for interconnect '%s'!\n",
+                 pb_interconnect->name);
+  }
+
+  interconnect_circuit_models_[pb_interconnect] = circuit_model;
+}
+
 } /* End namespace openfpga*/
diff --git a/openfpga/src/base/vpr_pb_type_annotation.h b/openfpga/src/base/vpr_pb_type_annotation.h
index e235538e7..7b19c3a29 100644
--- a/openfpga/src/base/vpr_pb_type_annotation.h
+++ b/openfpga/src/base/vpr_pb_type_annotation.h
@@ -35,12 +35,14 @@ class VprPbTypeAnnotation {
     t_port* physical_pb_port(t_port* pb_port) const;
     BasicPort physical_pb_port_range(t_port* pb_port) const;
     CircuitModelId pb_type_circuit_model(t_pb_type* physical_pb_type) const;
+    CircuitModelId interconnect_circuit_model(t_interconnect* pb_interconnect) const;
   public:  /* Public mutators */
     void add_pb_type_physical_mode(t_pb_type* pb_type, t_mode* physical_mode);
     void add_physical_pb_type(t_pb_type* operating_pb_type, t_pb_type* physical_pb_type);
     void add_physical_pb_port(t_port* operating_pb_port, t_port* physical_pb_port);
     void add_physical_pb_port_range(t_port* operating_pb_port, const BasicPort& port_range);
     void add_pb_type_circuit_model(t_pb_type* physical_pb_type, const CircuitModelId& circuit_model);
+    void add_interconnect_circuit_model(t_interconnect* pb_interconnect, const CircuitModelId& circuit_model);
   private: /* Internal data */
     /* Pair a regular pb_type to its physical pb_type */
     std::map<t_pb_type*, t_pb_type*> physical_pb_types_;
@@ -58,6 +60,12 @@ class VprPbTypeAnnotation {
      */
     std::map<t_pb_type*, CircuitModelId> pb_type_circuit_models_;
 
+    /* Pair a interconnect of a physical pb_type to its circuit model
+     * Note:
+     * - the pb_type MUST be a physical pb_type itself
+     */
+    std::map<t_interconnect*, CircuitModelId> interconnect_circuit_models_;
+
     /* Pair a pb_type to its mode selection bits
      * - if the pb_type is a physical pb_type, the mode bits are the default mode 
      *   where the physical pb_type will operate when used
diff --git a/openfpga/test_script/s298.openfpga b/openfpga/test_script/s298.openfpga
index ad12f4807..6d4eaa434 100644
--- a/openfpga/test_script/s298.openfpga
+++ b/openfpga/test_script/s298.openfpga
@@ -6,3 +6,6 @@ read_openfpga_arch -f ./test_openfpga_arch/k6_N10_40nm_openfpga.xml
 
 # Annotate the OpenFPGA architecture to VPR data base
 link_openfpga_arch
+
+# Finish and exit OpenFPGA
+exit

From 8a7a4dc48e20482afaa4052d3be45dab092a01fc Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 28 Jan 2020 21:59:10 -0700
Subject: [PATCH 038/645] add physical type annotation for interconnects and
 inference

---
 libs/libarchfpga/src/physical_types.h        |   3 +-
 openfpga/src/base/annotate_pb_graph.cpp      | 122 +++++++++++++++++++
 openfpga/src/base/annotate_pb_graph.h        |  23 ++++
 openfpga/src/base/annotate_pb_types.cpp      |  97 +++++++++++++++
 openfpga/src/base/openfpga_link_arch.cpp     |   1 +
 openfpga/src/base/pb_graph_utils.cpp         |  41 +++++++
 openfpga/src/base/pb_graph_utils.h           |  23 ++++
 openfpga/src/base/pb_type_utils.cpp          |  78 +++++++++++-
 openfpga/src/base/pb_type_utils.h            |   8 ++
 openfpga/src/base/vpr_pb_type_annotation.cpp |  22 ++++
 openfpga/src/base/vpr_pb_type_annotation.h   |   8 ++
 11 files changed, 423 insertions(+), 3 deletions(-)
 create mode 100644 openfpga/src/base/annotate_pb_graph.cpp
 create mode 100644 openfpga/src/base/annotate_pb_graph.h
 create mode 100644 openfpga/src/base/pb_graph_utils.cpp
 create mode 100644 openfpga/src/base/pb_graph_utils.h

diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h
index 36901e6f0..503427303 100644
--- a/libs/libarchfpga/src/physical_types.h
+++ b/libs/libarchfpga/src/physical_types.h
@@ -162,7 +162,8 @@ enum e_pin_type {
 enum e_interconnect {
     COMPLETE_INTERC = 1,
     DIRECT_INTERC = 2,
-    MUX_INTERC = 3
+    MUX_INTERC = 3,
+    NUM_INTERC_TYPES
 };
 
 /* Orientations. */
diff --git a/openfpga/src/base/annotate_pb_graph.cpp b/openfpga/src/base/annotate_pb_graph.cpp
new file mode 100644
index 000000000..82e214067
--- /dev/null
+++ b/openfpga/src/base/annotate_pb_graph.cpp
@@ -0,0 +1,122 @@
+/********************************************************************
+ * This file includes functions that are used to annotate pb_graph_node
+ * and pb_graph_pins from VPR to OpenFPGA
+ *******************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+#include "pb_type_utils.h"
+#include "pb_graph_utils.h"
+
+#include "annotate_pb_graph.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * This function will recursively walk through all the pb_graph nodes
+ * starting from a top node.
+ * It aims to annotate the physical type of each interconnect.
+ * This is due to that the type of interconnect 'complete' may diverge
+ * in physical implmentation. 
+ *  - When there is only one input driving a 'complete' interconnection, 
+ *    it will be implemented with wires
+ *  - When there are multiple inputs driving a 'complete' interconnection, 
+ *    it will be implemented with routing multiplexers
+ *******************************************************************/
+static 
+void rec_build_vpr_pb_graph_interconnect_physical_type_annotation(t_pb_graph_node* pb_graph_node, 
+                                                                  VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  /* Skip the root node because we start from the inputs of child pb_graph node 
+   *  
+   *   pb_graph_node
+   *   +----------------------------------
+   *   |               child_pb_graph_node
+   *   |             +-----------------
+   *   |             |
+   *   |-------------+-->input_pins
+   *   |             |
+   *   |-------------+-->clock_pins
+   *   |
+   *
+   */
+  if (false == pb_graph_node->is_root()) {
+    /* We only care the physical modes! But we have to find it through the parent node */
+    t_mode* child_physical_mode = vpr_pb_type_annotation.physical_mode(pb_graph_node->parent_pb_graph_node->pb_type);
+    VTR_ASSERT(nullptr != child_physical_mode);
+
+    std::map<t_interconnect*, size_t> interc_num_inputs;
+    /* Initialize the counter */
+    for (t_interconnect* interc : pb_mode_interconnects(child_physical_mode)) {
+      interc_num_inputs[interc] = 0;
+    }
+
+    /* We only care input and clock pins */
+    for (int iport = 0; iport < pb_graph_node->num_input_ports; ++iport) {
+      for (int ipin = 0; ipin < pb_graph_node->num_input_pins[iport]; ++ipin) {
+        /* For each interconnect, we count the total number of inputs */
+        for (t_interconnect* interc : pb_mode_interconnects(child_physical_mode)) {
+          interc_num_inputs[interc] += pb_graph_pin_inputs(&(pb_graph_node->input_pins[iport][ipin]), interc).size(); 
+        }
+      }
+    }
+
+    for (int iport = 0; iport < pb_graph_node->num_clock_ports; ++iport) {
+      for (int ipin = 0; ipin < pb_graph_node->num_clock_pins[iport]; ++ipin) {
+        /* For each interconnect, we count the total number of inputs */
+        for (t_interconnect* interc : pb_mode_interconnects(child_physical_mode)) {
+          interc_num_inputs[interc] += pb_graph_pin_inputs(&(pb_graph_node->clock_pins[iport][ipin]), interc).size(); 
+        }
+      }
+    }
+
+    /* For each interconnect that has more than 1 input, we can infer the physical type */
+    for (t_interconnect* interc : pb_mode_interconnects(child_physical_mode)) {
+      e_interconnect interc_physical_type = pb_interconnect_physical_type(interc, interc_num_inputs[interc]);
+      if (interc_physical_type == vpr_pb_type_annotation.interconnect_physical_type(interc)) {
+        /* Skip annotation if we have already done! */
+        continue;
+      }
+      vpr_pb_type_annotation.add_interconnect_physical_type(interc, interc_physical_type);
+    }
+  }
+
+  /* If we reach a primitive pb_graph node, we return */
+  if (true == is_primitive_pb_type(pb_graph_node->pb_type)) {
+    return;
+  }
+
+  /* Recursively visit all the child pb_graph_nodes */
+  t_mode* physical_mode = vpr_pb_type_annotation.physical_mode(pb_graph_node->pb_type);
+  VTR_ASSERT(nullptr != physical_mode);
+  for (int ipb = 0; ipb < physical_mode->num_pb_type_children; ++ipb) {
+    /* Each child may exist multiple times in the hierarchy*/
+    for (int jpb = 0; jpb < physical_mode->pb_type_children[ipb].num_pb; ++jpb) {
+      rec_build_vpr_pb_graph_interconnect_physical_type_annotation(&(pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb][jpb]), vpr_pb_type_annotation);
+    }
+  }
+}
+
+/********************************************************************
+ * This function aims to annotate the physical type for each interconnect
+ * inside the pb_graph 
+ *
+ * Note:
+ *   - This function should be executed AFTER functions
+ *       build_vpr_physical_pb_mode_explicit_annotation() 
+ *       build_vpr_physical_pb_mode_implicit_annotation() 
+ *******************************************************************/
+void annotate_pb_graph_interconnect_physical_type(const DeviceContext& vpr_device_ctx, 
+                                                  VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
+    /* By pass nullptr for pb_graph head */
+    if (nullptr == lb_type.pb_graph_head) {
+      continue;
+    }
+    rec_build_vpr_pb_graph_interconnect_physical_type_annotation(lb_type.pb_graph_head, vpr_pb_type_annotation); 
+  }
+}
+
+} /* end namespace openfpga */
+
diff --git a/openfpga/src/base/annotate_pb_graph.h b/openfpga/src/base/annotate_pb_graph.h
new file mode 100644
index 000000000..8749cd28f
--- /dev/null
+++ b/openfpga/src/base/annotate_pb_graph.h
@@ -0,0 +1,23 @@
+#ifndef ANNOTATE_PB_GRAPH_H
+#define ANNOTATE_PB_GRAPH_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "vpr_context.h"
+#include "openfpga_context.h"
+#include "vpr_pb_type_annotation.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void annotate_pb_graph_interconnect_physical_type(const DeviceContext& vpr_device_ctx, 
+                                                  VprPbTypeAnnotation& vpr_pb_type_annotation);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/base/annotate_pb_types.cpp b/openfpga/src/base/annotate_pb_types.cpp
index e8e7ddab4..c4605325c 100644
--- a/openfpga/src/base/annotate_pb_types.cpp
+++ b/openfpga/src/base/annotate_pb_types.cpp
@@ -9,6 +9,7 @@
 
 #include "vpr_pb_type_annotation.h"
 #include "pb_type_utils.h"
+#include "annotate_pb_graph.h"
 #include "annotate_pb_types.h"
 
 /* begin namespace openfpga */
@@ -843,6 +844,92 @@ void link_vpr_pb_interconnect_to_circuit_model_explicit_annotation(const DeviceC
   } 
 }
 
+/********************************************************************
+ * This function will recursively visit all the pb_type from the top
+ * pb_type in the graph and infer the circuit model for physical mode 
+ * of pb_types in VPR pb_type graph without OpenFPGA architecture XML
+ *
+ * Because only the interconnect in physical modes need circuit model
+ * annotation, we will skip all the operating modes here
+ *
+ * Note: 
+ *   - This function will automatically infer the type of circuit model
+ *     that is required and find the default circuit model in the type
+ *   - Interconnect type to Circuit mode type assumption:
+ *     - MUX_INTERC -> CIRCUIT_MODEL_MUX
+ *     - DIRECT_INTERC -> CIRCUIT_MODEL_WIRE
+ *     - COMPLETE_INTERC (single input) -> CIRCUIT_MODEL_WIRE
+ *     - COMPLETE_INTERC (multiple input pins) -> CIRCUIT_MODEL_MUX
+ *******************************************************************/
+static 
+void rec_infer_vpr_pb_interconnect_circuit_model_annotation(t_pb_type* cur_pb_type, 
+                                                            const CircuitLibrary& circuit_lib,
+                                                            VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  /* We do not check any primitive pb_type */
+  if (true == is_primitive_pb_type(cur_pb_type)) {
+    return;
+  }
+
+  /* Get the physical mode from annotation */ 
+  t_mode* physical_mode = vpr_pb_type_annotation.physical_mode(cur_pb_type);
+
+  VTR_ASSERT(nullptr != physical_mode);
+
+  /* Annotate the circuit model for each interconnect under this physical mode */
+  for (t_interconnect* pb_interc : pb_mode_interconnects(physical_mode)) {
+    /* If the interconnect has been annotated, we skip it */
+    if (CircuitModelId::INVALID() != vpr_pb_type_annotation.interconnect_circuit_model(pb_interc)) {
+      continue;
+    }
+    /* Infer the circuit model type for a given interconnect */
+    e_circuit_model_type circuit_model_type = pb_interconnect_require_circuit_model_type(vpr_pb_type_annotation.interconnect_physical_type(pb_interc));
+    /* Try to find a default circuit model from the circuit library */
+    CircuitModelId default_circuit_model = circuit_lib.default_model(circuit_model_type);
+    /* Update the annotation if the model id is valid */
+    if (CircuitModelId::INVALID() == default_circuit_model) {
+      VTR_LOG_ERROR("Unable to infer a circuit model for interconnect '%s' under physical mode '%s' of pb_type '%s'!\n",
+                    pb_interc->name,
+                    physical_mode->name, 
+                    cur_pb_type->name);
+    }
+    vpr_pb_type_annotation.add_interconnect_circuit_model(pb_interc, default_circuit_model); 
+    VTR_LOG("Implicitly infer a circuit model '%s' for interconnect '%s' under physical mode '%s' of pb_type '%s'\n",
+            circuit_lib.model_name(default_circuit_model).c_str(),
+            pb_interc->name,
+            physical_mode->name, 
+            cur_pb_type->name);
+  }
+
+  /* Traverse the pb_type children under the physical mode */
+  for (int ichild = 0; ichild < physical_mode->num_pb_type_children; ++ichild) { 
+    rec_infer_vpr_pb_interconnect_circuit_model_annotation(&(physical_mode->pb_type_children[ichild]),
+                                                           circuit_lib, vpr_pb_type_annotation);
+  }
+}
+
+/********************************************************************
+ * This function will infer the circuit model for each interconnect
+ * under a physical mode of a pb_type in VPR pb_type graph without 
+ * OpenFPGA architecture XML
+ *
+ * Note: 
+ * This function must be executed AFTER the function
+ *   build_vpr_physical_pb_mode_explicit_annotation()
+ *   build_vpr_physical_pb_mode_implicit_annotation()
+ *******************************************************************/
+static 
+void link_vpr_pb_interconnect_to_circuit_model_implicit_annotation(const DeviceContext& vpr_device_ctx,
+                                                                   const CircuitLibrary& circuit_lib,
+                                                                   VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
+    /* By pass nullptr for pb_type head */
+    if (nullptr == lb_type.pb_type) {
+      continue;
+    }
+    rec_infer_vpr_pb_interconnect_circuit_model_annotation(lb_type.pb_type, circuit_lib, vpr_pb_type_annotation); 
+  }
+}
+
 /********************************************************************
  * Top-level function to link openfpga architecture to VPR, including:
  * - physical pb_type
@@ -862,6 +949,13 @@ void annotate_pb_types(const DeviceContext& vpr_device_ctx,
   check_vpr_physical_pb_mode_annotation(vpr_device_ctx, 
                                         const_cast<const VprPbTypeAnnotation&>(vpr_pb_type_annotation));
 
+  /* Annotate the physical type for each interconnect under physical modes
+   * Must run AFTER physical mode annotation is done and 
+   * BEFORE inferring the circuit model for interconnect
+   */
+  annotate_pb_graph_interconnect_physical_type(vpr_device_ctx, 
+                                               vpr_pb_type_annotation);
+
   /* Annotate physical pb_types to operating pb_type in the VPR pb_type graph */
   build_vpr_physical_pb_type_explicit_annotation(vpr_device_ctx, openfpga_arch,
                                                  vpr_pb_type_annotation);
@@ -876,10 +970,13 @@ void annotate_pb_types(const DeviceContext& vpr_device_ctx,
    * - physical pb_type to circuit model
    * - interconnect of physical pb_type to circuit model 
    */
+  /* TODO: link the pb_type port to circuit model port here! */
   link_vpr_pb_type_to_circuit_model_explicit_annotation(vpr_device_ctx, openfpga_arch,
                                                         vpr_pb_type_annotation);
   link_vpr_pb_interconnect_to_circuit_model_explicit_annotation(vpr_device_ctx, openfpga_arch,
                                                                 vpr_pb_type_annotation);
+  link_vpr_pb_interconnect_to_circuit_model_implicit_annotation(vpr_device_ctx, openfpga_arch.circuit_lib,
+                                                                vpr_pb_type_annotation);
 
   /* Link physical pb_type to mode_bits */
 
diff --git a/openfpga/src/base/openfpga_link_arch.cpp b/openfpga/src/base/openfpga_link_arch.cpp
index d10c5d931..a30453d1c 100644
--- a/openfpga/src/base/openfpga_link_arch.cpp
+++ b/openfpga/src/base/openfpga_link_arch.cpp
@@ -10,6 +10,7 @@
 #include "vpr_pb_type_annotation.h"
 #include "pb_type_utils.h"
 #include "annotate_pb_types.h"
+#include "annotate_pb_graph.h"
 #include "openfpga_link_arch.h"
 
 /* Include global variables of VPR */
diff --git a/openfpga/src/base/pb_graph_utils.cpp b/openfpga/src/base/pb_graph_utils.cpp
new file mode 100644
index 000000000..84e642bde
--- /dev/null
+++ b/openfpga/src/base/pb_graph_utils.cpp
@@ -0,0 +1,41 @@
+/********************************************************************
+ * This file includes most utilized functions for the pb_graph_node
+ * and pb_graph_pin data structure in the OpenFPGA context
+ *******************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+#include "pb_graph_utils.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * This function aims to find out all the pb_graph_pins that drive 
+ * a given pb_graph pin w.r.t. a given interconnect definition
+ *******************************************************************/
+std::vector<t_pb_graph_pin*> pb_graph_pin_inputs(t_pb_graph_pin* pb_graph_pin,
+                                                 t_interconnect* selected_interconnect) { 
+  std::vector<t_pb_graph_pin*> inputs;
+
+  /* Search the input edges only, stats on the size of MUX we may need (fan-in) */
+  for (int iedge = 0; iedge < pb_graph_pin->num_input_edges; ++iedge) {
+    /* We care the only edges in the selected mode */
+    if (selected_interconnect != pb_graph_pin->input_edges[iedge]->interconnect) {
+      continue;
+    }
+    for (int ipin = 0; ipin < pb_graph_pin->input_edges[iedge]->num_input_pins; ++ipin) {
+      /* Ensure that the pin is unique in the list */
+      if (inputs.end() != std::find(inputs.begin(), inputs.end(), pb_graph_pin->input_edges[iedge]->input_pins[ipin])) {
+        continue;
+      }
+      /* Unique pin, push to the vector */ 
+      inputs.push_back(pb_graph_pin->input_edges[iedge]->input_pins[ipin]);
+    }
+  }
+
+  return inputs;
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/base/pb_graph_utils.h b/openfpga/src/base/pb_graph_utils.h
new file mode 100644
index 000000000..d46457b7d
--- /dev/null
+++ b/openfpga/src/base/pb_graph_utils.h
@@ -0,0 +1,23 @@
+#ifndef PB_GRAPH_UTILS_H
+#define PB_GRAPH_UTILS_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <string>
+#include <vector>
+#include "physical_types.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+std::vector<t_pb_graph_pin*> pb_graph_pin_inputs(t_pb_graph_pin* pb_graph_pin,
+                                                 t_interconnect* selected_interconnect); 
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/base/pb_type_utils.cpp b/openfpga/src/base/pb_type_utils.cpp
index 93b644b8c..090661b50 100644
--- a/openfpga/src/base/pb_type_utils.cpp
+++ b/openfpga/src/base/pb_type_utils.cpp
@@ -1,7 +1,9 @@
 /********************************************************************
- * This file includes most utilized functions for the pb_type
- * and pb_graph_node data structure in the OpenFPGA context
+ * This file includes most utilized functions for the t_pb_type,
+ * t_mode and t_port data structure in the OpenFPGA context
  *******************************************************************/
+#include <map>
+
 /* Headers from vtrutil library */
 #include "vtr_assert.h"
 #include "vtr_log.h"
@@ -138,6 +140,18 @@ t_pb_type* try_find_pb_type_with_given_path(t_pb_type* top_pb_type,
   return nullptr;
 }
 
+/********************************************************************
+ * This function will return all the interconnects defined under a mode
+ * of pb_type
+ *******************************************************************/
+std::vector<t_interconnect*> pb_mode_interconnects(t_mode* pb_mode) {
+  std::vector<t_interconnect*> interc;
+  for (int i = 0; i < pb_mode->num_interconnect; ++i) {
+    interc.push_back(&(pb_mode->interconnect[i]));
+  }
+  return interc;
+}
+
 /********************************************************************
  * This function will try to find an interconnect defined under a mode
  * of pb_type with a given name.
@@ -154,4 +168,64 @@ t_interconnect* find_pb_mode_interconnect(t_mode* pb_mode, const char* interc_na
   return nullptr;
 }
 
+/********************************************************************
+ * This function will automatically infer the actual type of an interconnect
+ * that will be used to implement the physical design:
+ * - MUX_INTERC -> MUX_INTERC
+ * - DIRECT_INTERC -> DIRECT_INTERC
+ * - COMPLETE_INTERC (single input) -> DIRECT_INTERC
+ * - COMPLETE_INTERC (multiple input pins) -> MUX_INTERC
+ *******************************************************************/
+e_interconnect pb_interconnect_physical_type(t_interconnect* pb_interc,
+                                             const size_t& num_inputs) {
+  /* Check */
+  VTR_ASSERT(nullptr != pb_interc); 
+
+  /* Initialize the interconnection type that will be implemented in SPICE netlist*/
+  switch (pb_interc->type) {
+  case DIRECT_INTERC:
+    return DIRECT_INTERC;
+    break;
+  case COMPLETE_INTERC:
+    if (1 == num_inputs) {
+      return DIRECT_INTERC;
+    } else {
+      VTR_ASSERT(1 < num_inputs);
+      return MUX_INTERC;
+    }
+    break;
+  case MUX_INTERC:
+    return MUX_INTERC;
+    break;
+  default:
+    VTR_LOG_ERROR("Invalid type for interconnection '%s'!\n",
+                   pb_interc->name);
+    exit(1);
+  }
+
+  return NUM_INTERC_TYPES;
+}
+
+/********************************************************************
+ * This function will automatically infer the actual type of an interconnect
+ * that will be used to implement the physical design:
+ * - MUX_INTERC -> CIRCUIT_MODEL_MUX
+ * - DIRECT_INTERC -> CIRCUIT_MODEL_WIRE
+ * 
+ * Note: 
+ *   - COMPLETE_INTERC should not appear here!
+ *   - We assume the interconnect type is the physical type
+ *     after interconnect physical type annotation is done! 
+ *******************************************************************/
+e_circuit_model_type pb_interconnect_require_circuit_model_type(const e_interconnect& pb_interc_type) {
+  /* A map from interconnect type to circuit model type */
+  std::map<e_interconnect, e_circuit_model_type> type_mapping;
+  type_mapping[MUX_INTERC] = CIRCUIT_MODEL_MUX;
+  type_mapping[DIRECT_INTERC] = CIRCUIT_MODEL_WIRE;
+
+  VTR_ASSERT((MUX_INTERC == pb_interc_type) || (DIRECT_INTERC == pb_interc_type));
+ 
+  return type_mapping.at(pb_interc_type); 
+}
+
 } /* end namespace openfpga */
diff --git a/openfpga/src/base/pb_type_utils.h b/openfpga/src/base/pb_type_utils.h
index 3e9f9a07f..ac3ade343 100644
--- a/openfpga/src/base/pb_type_utils.h
+++ b/openfpga/src/base/pb_type_utils.h
@@ -7,6 +7,7 @@
 #include <string>
 #include <vector>
 #include "physical_types.h"
+#include "circuit_library.h"
 
 /********************************************************************
  * Function declaration
@@ -31,8 +32,15 @@ t_pb_type* try_find_pb_type_with_given_path(t_pb_type* top_pb_type,
                                             const std::vector<std::string>& target_pb_type_names, 
                                             const std::vector<std::string>& target_pb_mode_names);
 
+std::vector<t_interconnect*> pb_mode_interconnects(t_mode* pb_mode);
+
 t_interconnect* find_pb_mode_interconnect(t_mode* pb_mode, const char* interc_name);
 
+e_interconnect pb_interconnect_physical_type(t_interconnect* pb_interc,
+                                             const size_t& num_inputs);
+
+e_circuit_model_type pb_interconnect_require_circuit_model_type(const e_interconnect& pb_interc_type);
+
 } /* end namespace openfpga */
 
 #endif
diff --git a/openfpga/src/base/vpr_pb_type_annotation.cpp b/openfpga/src/base/vpr_pb_type_annotation.cpp
index 8949d13c3..97dc7354b 100644
--- a/openfpga/src/base/vpr_pb_type_annotation.cpp
+++ b/openfpga/src/base/vpr_pb_type_annotation.cpp
@@ -85,6 +85,16 @@ CircuitModelId VprPbTypeAnnotation::interconnect_circuit_model(t_interconnect* p
   return interconnect_circuit_models_.at(pb_interconnect);
 }
 
+e_interconnect VprPbTypeAnnotation::interconnect_physical_type(t_interconnect* pb_interconnect) const {
+  /* Ensure that the pb_type is in the list */
+  std::map<t_interconnect*, e_interconnect>::const_iterator it = interconnect_physical_types_.find(pb_interconnect);
+  if (it == interconnect_physical_types_.end()) {
+    /* Return an invalid circuit model id */
+    return NUM_INTERC_TYPES;
+  }
+  return interconnect_physical_types_.at(pb_interconnect);
+}
+
 /************************************************************************
  * Public mutators
  ***********************************************************************/
@@ -157,4 +167,16 @@ void VprPbTypeAnnotation::add_interconnect_circuit_model(t_interconnect* pb_inte
   interconnect_circuit_models_[pb_interconnect] = circuit_model;
 }
 
+void VprPbTypeAnnotation::add_interconnect_physical_type(t_interconnect* pb_interconnect,
+                                                         const e_interconnect& physical_type) {
+  /* Warn any override attempt */
+  std::map<t_interconnect*, e_interconnect>::const_iterator it = interconnect_physical_types_.find(pb_interconnect);
+  if (it != interconnect_physical_types_.end()) {
+    VTR_LOG_WARN("Override the physical interconnect for interconnect '%s'!\n",
+                 pb_interconnect->name);
+  }
+
+  interconnect_physical_types_[pb_interconnect] = physical_type;
+}
+
 } /* End namespace openfpga*/
diff --git a/openfpga/src/base/vpr_pb_type_annotation.h b/openfpga/src/base/vpr_pb_type_annotation.h
index 7b19c3a29..824a81e87 100644
--- a/openfpga/src/base/vpr_pb_type_annotation.h
+++ b/openfpga/src/base/vpr_pb_type_annotation.h
@@ -36,6 +36,7 @@ class VprPbTypeAnnotation {
     BasicPort physical_pb_port_range(t_port* pb_port) const;
     CircuitModelId pb_type_circuit_model(t_pb_type* physical_pb_type) const;
     CircuitModelId interconnect_circuit_model(t_interconnect* pb_interconnect) const;
+    e_interconnect interconnect_physical_type(t_interconnect* pb_interconnect) const;
   public:  /* Public mutators */
     void add_pb_type_physical_mode(t_pb_type* pb_type, t_mode* physical_mode);
     void add_physical_pb_type(t_pb_type* operating_pb_type, t_pb_type* physical_pb_type);
@@ -43,6 +44,7 @@ class VprPbTypeAnnotation {
     void add_physical_pb_port_range(t_port* operating_pb_port, const BasicPort& port_range);
     void add_pb_type_circuit_model(t_pb_type* physical_pb_type, const CircuitModelId& circuit_model);
     void add_interconnect_circuit_model(t_interconnect* pb_interconnect, const CircuitModelId& circuit_model);
+    void add_interconnect_physical_type(t_interconnect* pb_interconnect, const e_interconnect& physical_type);
   private: /* Internal data */
     /* Pair a regular pb_type to its physical pb_type */
     std::map<t_pb_type*, t_pb_type*> physical_pb_types_;
@@ -66,6 +68,12 @@ class VprPbTypeAnnotation {
      */
     std::map<t_interconnect*, CircuitModelId> interconnect_circuit_models_;
 
+    /* Physical type of interconnect 
+     * Note:
+     * - only applicable to an interconnect belongs to physical mode
+     */
+    std::map<t_interconnect*, e_interconnect> interconnect_physical_types_;
+
     /* Pair a pb_type to its mode selection bits
      * - if the pb_type is a physical pb_type, the mode bits are the default mode 
      *   where the physical pb_type will operate when used

From cf3c5b5c42e9abbff21eeb4c0850a69b7f2f56c9 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 29 Jan 2020 10:41:02 -0700
Subject: [PATCH 039/645] add circuit model type checking for physical pb_type
 annotation

---
 openfpga/src/base/annotate_pb_types.cpp | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/openfpga/src/base/annotate_pb_types.cpp b/openfpga/src/base/annotate_pb_types.cpp
index c4605325c..dc1618d6e 100644
--- a/openfpga/src/base/annotate_pb_types.cpp
+++ b/openfpga/src/base/annotate_pb_types.cpp
@@ -613,6 +613,8 @@ bool link_physical_pb_type_to_circuit_model(t_pb_type* physical_pb_type,
     return false;
   }
 
+  /* TODO: Ensure that the pb_type ports can be matched in the circuit model ports */
+
   /* Now the circuit model is valid, update the vpr_pb_type_annotation */
   vpr_pb_type_annotation.add_pb_type_circuit_model(physical_pb_type, circuit_model_id);
   return true;
@@ -663,6 +665,19 @@ bool link_physical_pb_interconnect_to_circuit_model(t_pb_type* physical_pb_type,
                   physical_pb_type->name);
     return false;
   }
+  
+  /* Double check the type of circuit model, it should be the same as required physical type */
+  e_circuit_model_type required_circuit_model_type = pb_interconnect_require_circuit_model_type(vpr_pb_type_annotation.interconnect_physical_type(pb_interc));
+  if (circuit_lib.model_type(circuit_model_id) != required_circuit_model_type) {
+    VTR_LOG_ERROR("Circuit model '%s' type '%s' does not match required type '%s' for interconnect '%s' under physical mode '%s' of pb_type '%s'!\n",
+                  circuit_lib.model_name(circuit_model_id).c_str(),
+                  CIRCUIT_MODEL_TYPE_STRING[circuit_lib.model_type(circuit_model_id)],
+                  CIRCUIT_MODEL_TYPE_STRING[required_circuit_model_type],
+                  pb_interc->name,
+                  physical_mode->name, 
+                  physical_pb_type->name);
+    return false;
+  }
 
   /* Now the circuit model is valid, update the vpr_pb_type_annotation */
   vpr_pb_type_annotation.add_interconnect_circuit_model(pb_interc, circuit_model_id);
@@ -977,6 +992,7 @@ void annotate_pb_types(const DeviceContext& vpr_device_ctx,
                                                                 vpr_pb_type_annotation);
   link_vpr_pb_interconnect_to_circuit_model_implicit_annotation(vpr_device_ctx, openfpga_arch.circuit_lib,
                                                                 vpr_pb_type_annotation);
+  /* TODO: check the circuit model annotation */
 
   /* Link physical pb_type to mode_bits */
 

From 399ba8d6481f11a9ad6b4441545e1a6fc2633024 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 29 Jan 2020 11:24:14 -0700
Subject: [PATCH 040/645] add pb type port mapping to circuit model ports

---
 openfpga/src/base/annotate_pb_types.cpp      | 68 +++++++++++++++++++-
 openfpga/src/base/pb_type_utils.cpp          | 26 ++++++++
 openfpga/src/base/pb_type_utils.h            |  2 +
 openfpga/src/base/vpr_pb_type_annotation.cpp | 24 ++++++-
 openfpga/src/base/vpr_pb_type_annotation.h   |  8 +++
 5 files changed, 126 insertions(+), 2 deletions(-)

diff --git a/openfpga/src/base/annotate_pb_types.cpp b/openfpga/src/base/annotate_pb_types.cpp
index dc1618d6e..783447cfb 100644
--- a/openfpga/src/base/annotate_pb_types.cpp
+++ b/openfpga/src/base/annotate_pb_types.cpp
@@ -584,6 +584,69 @@ void check_vpr_physical_pb_type_annotation(const DeviceContext& vpr_device_ctx,
   }
 }
 
+/********************************************************************
+ * This function aims to link all the ports defined under a physical 
+ * pb_type to the ports of circuit model in the circuit library
+ * The binding assumes that pb_type port should be defined with the same name
+ * as the circuit port
+ *******************************************************************/
+static 
+bool link_physical_pb_port_to_circuit_port(t_pb_type* physical_pb_type, 
+                                           const CircuitLibrary& circuit_lib,
+                                           const CircuitModelId& circuit_model,
+                                           VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  bool link_success = true;
+  /* Iterate over the pb_ports
+   * Note: 
+   *   - Not every port defined in the circuit model will appear under the pb_type
+   *     Some circuit ports are just for physical implementation
+   */
+  for (t_port* pb_port : pb_type_ports(physical_pb_type)) {
+    CircuitPortId circuit_port = circuit_lib.model_port(circuit_model, std::string(pb_port->name));
+
+    /* If we cannot find a port with the same name, error out */
+    if (CircuitPortId::INVALID() == circuit_port) {
+      VTR_LOG_ERROR("Pb type port '%s' is not found in any port of circuit model '%s'!\n",
+                    pb_port->name, circuit_lib.model_name(circuit_model).c_str());
+      link_success = false;
+      continue;
+    }
+
+    /* If the port width does not match, error out */
+    if ((size_t)(pb_port->num_pins) != circuit_lib.port_size(circuit_port)) {
+      VTR_LOG_ERROR("Pb type port '%s[%d:%d]' does not match the port '%s[%d:%d]' of circuit model '%s' in size!\n",
+                    pb_port->name, 
+                    0, pb_port->num_pins - 1,
+                    circuit_lib.port_prefix(circuit_port).c_str(),
+                    0, circuit_lib.port_size(circuit_port) - 1,
+                    circuit_lib.model_name(circuit_model).c_str());
+      link_success = false;
+      continue;
+    }
+
+    /* If the port type does not match, error out */
+    if (ERR_PORT == circuit_port_require_pb_port_type(circuit_lib.port_type(circuit_port))) {
+      VTR_LOG_ERROR("Pb type port '%s' type does not match the port type '%s' of circuit model '%s'!\n",
+                    pb_port->name, 
+                    circuit_lib.port_prefix(circuit_port).c_str(),
+                    circuit_lib.model_name(circuit_model).c_str());
+
+      link_success = false;
+      continue;
+    }
+
+    /* Reach here, it means that mapping should be ok, update the vpr_pb_type_annotation */
+    vpr_pb_type_annotation.add_pb_circuit_port(pb_port, circuit_port);
+    VTR_LOG("Bind pb type '%s' port '%s' to circuit model '%s' port '%s'\n",
+            physical_pb_type->name,
+            pb_port->name,
+            circuit_lib.model_name(circuit_model).c_str(),
+            circuit_lib.port_prefix(circuit_port).c_str());
+  }
+
+  return link_success;
+}
+
 /********************************************************************
  * This function aims to link a physical pb_type to a valid circuit model
  * in the circuit library
@@ -613,7 +676,10 @@ bool link_physical_pb_type_to_circuit_model(t_pb_type* physical_pb_type,
     return false;
   }
 
-  /* TODO: Ensure that the pb_type ports can be matched in the circuit model ports */
+  /* Ensure that the pb_type ports can be matched in the circuit model ports */
+  if (false == link_physical_pb_port_to_circuit_port(physical_pb_type, circuit_lib, circuit_model_id, vpr_pb_type_annotation)) {
+    return false;
+  }
 
   /* Now the circuit model is valid, update the vpr_pb_type_annotation */
   vpr_pb_type_annotation.add_pb_type_circuit_model(physical_pb_type, circuit_model_id);
diff --git a/openfpga/src/base/pb_type_utils.cpp b/openfpga/src/base/pb_type_utils.cpp
index 090661b50..b791485a2 100644
--- a/openfpga/src/base/pb_type_utils.cpp
+++ b/openfpga/src/base/pb_type_utils.cpp
@@ -228,4 +228,30 @@ e_circuit_model_type pb_interconnect_require_circuit_model_type(const e_intercon
   return type_mapping.at(pb_interc_type); 
 }
 
+/********************************************************************
+ * This function aims to find the required type for a pb_port
+ * when it is linked to a port of a circuit model
+ * We start from the view of a circuit port here.
+ * This is due to circuit port has more types than a pb_type port
+ * as it is designed for physical implementation
+ * As such, a few types of circuit port may be directed the same type of pb_type port
+ * This is done to make the mapping much simpler than doing in the opposite direction
+ *******************************************************************/
+enum PORTS circuit_port_require_pb_port_type(const e_circuit_model_port_type& circuit_port_type) {
+  std::map<e_circuit_model_port_type, enum PORTS> type_mapping;
+
+  /* These circuit model ports may be founed in the pb_type ports */
+  type_mapping[CIRCUIT_MODEL_PORT_INPUT] = IN_PORT;
+  type_mapping[CIRCUIT_MODEL_PORT_OUTPUT] = OUT_PORT;
+  type_mapping[CIRCUIT_MODEL_PORT_INOUT] = INOUT_PORT;
+  type_mapping[CIRCUIT_MODEL_PORT_CLOCK] = IN_PORT;
+
+  /* Other circuit model ports should not be found when mapping to the pb_type ports */
+  if (type_mapping.end() == type_mapping.find(circuit_port_type)) {
+    return ERR_PORT;
+  }
+  
+  return type_mapping.at(circuit_port_type);
+}
+
 } /* end namespace openfpga */
diff --git a/openfpga/src/base/pb_type_utils.h b/openfpga/src/base/pb_type_utils.h
index ac3ade343..17ec7f78e 100644
--- a/openfpga/src/base/pb_type_utils.h
+++ b/openfpga/src/base/pb_type_utils.h
@@ -41,6 +41,8 @@ e_interconnect pb_interconnect_physical_type(t_interconnect* pb_interc,
 
 e_circuit_model_type pb_interconnect_require_circuit_model_type(const e_interconnect& pb_interc_type);
 
+enum PORTS circuit_port_require_pb_port_type(const e_circuit_model_port_type& circuit_port_type);
+
 } /* end namespace openfpga */
 
 #endif
diff --git a/openfpga/src/base/vpr_pb_type_annotation.cpp b/openfpga/src/base/vpr_pb_type_annotation.cpp
index 97dc7354b..867f40794 100644
--- a/openfpga/src/base/vpr_pb_type_annotation.cpp
+++ b/openfpga/src/base/vpr_pb_type_annotation.cpp
@@ -89,12 +89,23 @@ e_interconnect VprPbTypeAnnotation::interconnect_physical_type(t_interconnect* p
   /* Ensure that the pb_type is in the list */
   std::map<t_interconnect*, e_interconnect>::const_iterator it = interconnect_physical_types_.find(pb_interconnect);
   if (it == interconnect_physical_types_.end()) {
-    /* Return an invalid circuit model id */
+    /* Return an invalid interconnect type */
     return NUM_INTERC_TYPES;
   }
   return interconnect_physical_types_.at(pb_interconnect);
 }
 
+CircuitPortId VprPbTypeAnnotation::pb_circuit_port(t_port* pb_port) const {
+  /* Ensure that the pb_type is in the list */
+  std::map<t_port*, CircuitPortId>::const_iterator it = pb_circuit_ports_.find(pb_port);
+  if (it == pb_circuit_ports_.end()) {
+    /* Return an invalid circuit port id */
+    return CircuitPortId::INVALID();
+  }
+  return pb_circuit_ports_.at(pb_port);
+}
+
+
 /************************************************************************
  * Public mutators
  ***********************************************************************/
@@ -179,4 +190,15 @@ void VprPbTypeAnnotation::add_interconnect_physical_type(t_interconnect* pb_inte
   interconnect_physical_types_[pb_interconnect] = physical_type;
 }
 
+void VprPbTypeAnnotation::add_pb_circuit_port(t_port* pb_port, const CircuitPortId& circuit_port) {
+  /* Warn any override attempt */
+  std::map<t_port*, CircuitPortId>::const_iterator it = pb_circuit_ports_.find(pb_port);
+  if (it != pb_circuit_ports_.end()) {
+    VTR_LOG_WARN("Override the circuit port mapping for pb_type port '%s'!\n",
+                 pb_port->name);
+  }
+
+  pb_circuit_ports_[pb_port] = circuit_port;
+}
+
 } /* End namespace openfpga*/
diff --git a/openfpga/src/base/vpr_pb_type_annotation.h b/openfpga/src/base/vpr_pb_type_annotation.h
index 824a81e87..fb0fec934 100644
--- a/openfpga/src/base/vpr_pb_type_annotation.h
+++ b/openfpga/src/base/vpr_pb_type_annotation.h
@@ -37,6 +37,7 @@ class VprPbTypeAnnotation {
     CircuitModelId pb_type_circuit_model(t_pb_type* physical_pb_type) const;
     CircuitModelId interconnect_circuit_model(t_interconnect* pb_interconnect) const;
     e_interconnect interconnect_physical_type(t_interconnect* pb_interconnect) const;
+    CircuitPortId pb_circuit_port(t_port* pb_port) const;
   public:  /* Public mutators */
     void add_pb_type_physical_mode(t_pb_type* pb_type, t_mode* physical_mode);
     void add_physical_pb_type(t_pb_type* operating_pb_type, t_pb_type* physical_pb_type);
@@ -45,6 +46,7 @@ class VprPbTypeAnnotation {
     void add_pb_type_circuit_model(t_pb_type* physical_pb_type, const CircuitModelId& circuit_model);
     void add_interconnect_circuit_model(t_interconnect* pb_interconnect, const CircuitModelId& circuit_model);
     void add_interconnect_physical_type(t_interconnect* pb_interconnect, const e_interconnect& physical_type);
+    void add_pb_circuit_port(t_port* pb_port, const CircuitPortId& circuit_port);
   private: /* Internal data */
     /* Pair a regular pb_type to its physical pb_type */
     std::map<t_pb_type*, t_pb_type*> physical_pb_types_;
@@ -94,6 +96,12 @@ class VprPbTypeAnnotation {
      */
     std::map<t_port*, BasicPort> physical_pb_port_ranges_;
 
+    /* Pair a pb_port to a circuit port in circuit model
+     * Note:
+     * - the parent of physical pb_port MUST be a physical pb_type
+     */
+    std::map<t_port*, CircuitPortId> pb_circuit_ports_;
+
     /* Pair a pb_graph_node to a physical pb_graph_node
      * Note:
      * - the pb_type of physical pb_graph_node must be a physical pb_type

From 61b487eb75be91e5af9c7d8543e98e9198959d4c Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 29 Jan 2020 11:29:41 -0700
Subject: [PATCH 041/645] show more information in the log file

---
 openfpga/src/base/annotate_pb_types.cpp | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/openfpga/src/base/annotate_pb_types.cpp b/openfpga/src/base/annotate_pb_types.cpp
index 783447cfb..064fc2cc0 100644
--- a/openfpga/src/base/annotate_pb_types.cpp
+++ b/openfpga/src/base/annotate_pb_types.cpp
@@ -1021,6 +1021,8 @@ void annotate_pb_types(const DeviceContext& vpr_device_ctx,
                        VprPbTypeAnnotation& vpr_pb_type_annotation) {
 
   /* Annotate physical mode to pb_type in the VPR pb_type graph */
+  VTR_LOG("\n");
+  VTR_LOG("Building annotation for physical modes in pb_type...\n");
   build_vpr_physical_pb_mode_explicit_annotation(vpr_device_ctx, openfpga_arch,
                                                  vpr_pb_type_annotation);
 
@@ -1034,10 +1036,15 @@ void annotate_pb_types(const DeviceContext& vpr_device_ctx,
    * Must run AFTER physical mode annotation is done and 
    * BEFORE inferring the circuit model for interconnect
    */
+  VTR_LOG("\n");
+  VTR_LOG("Building annotation about physical types for pb_type interconnection...");
   annotate_pb_graph_interconnect_physical_type(vpr_device_ctx, 
                                                vpr_pb_type_annotation);
+  VTR_LOG("Done\n");
 
   /* Annotate physical pb_types to operating pb_type in the VPR pb_type graph */
+  VTR_LOG("\n");
+  VTR_LOG("Building annotation between operating and physical pb_types...\n");
   build_vpr_physical_pb_type_explicit_annotation(vpr_device_ctx, openfpga_arch,
                                                  vpr_pb_type_annotation);
 
@@ -1051,7 +1058,8 @@ void annotate_pb_types(const DeviceContext& vpr_device_ctx,
    * - physical pb_type to circuit model
    * - interconnect of physical pb_type to circuit model 
    */
-  /* TODO: link the pb_type port to circuit model port here! */
+  VTR_LOG("\n");
+  VTR_LOG("Building annotation between physical pb_types and circuit models...\n");
   link_vpr_pb_type_to_circuit_model_explicit_annotation(vpr_device_ctx, openfpga_arch,
                                                         vpr_pb_type_annotation);
   link_vpr_pb_interconnect_to_circuit_model_explicit_annotation(vpr_device_ctx, openfpga_arch,

From 24b180b2983cd85a20d79b62a17e93a5658786a6 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 29 Jan 2020 11:59:20 -0700
Subject: [PATCH 042/645] change the mode bit storage in annotation data
 structure from string to vector of integers

---
 .../src/pb_type_annotation.cpp                |  4 +--
 .../libarchopenfpga/src/pb_type_annotation.h  |  6 ++--
 .../src/read_xml_pb_type_annotation.cpp       | 28 ++++++++++++++++++-
 .../src/write_xml_pb_type_annotation.cpp      |  7 ++++-
 4 files changed, 38 insertions(+), 7 deletions(-)

diff --git a/libopenfpga/libarchopenfpga/src/pb_type_annotation.cpp b/libopenfpga/libarchopenfpga/src/pb_type_annotation.cpp
index da494f77f..d04e39b72 100644
--- a/libopenfpga/libarchopenfpga/src/pb_type_annotation.cpp
+++ b/libopenfpga/libarchopenfpga/src/pb_type_annotation.cpp
@@ -61,7 +61,7 @@ std::string PbTypeAnnotation::idle_mode_name() const {
   return idle_mode_name_;
 }
 
-std::string PbTypeAnnotation::mode_bits() const {
+std::vector<size_t> PbTypeAnnotation::mode_bits() const {
   return mode_bits_;
 }
 
@@ -155,7 +155,7 @@ void PbTypeAnnotation::set_idle_mode_name(const std::string& name) {
   idle_mode_name_ = name;
 }
 
-void PbTypeAnnotation::set_mode_bits(const std::string& mode_bits) {
+void PbTypeAnnotation::set_mode_bits(const std::vector<size_t>& mode_bits) {
   mode_bits_ = mode_bits;
 }
 
diff --git a/libopenfpga/libarchopenfpga/src/pb_type_annotation.h b/libopenfpga/libarchopenfpga/src/pb_type_annotation.h
index e03201cde..a969ee93d 100644
--- a/libopenfpga/libarchopenfpga/src/pb_type_annotation.h
+++ b/libopenfpga/libarchopenfpga/src/pb_type_annotation.h
@@ -43,7 +43,7 @@ class PbTypeAnnotation {
     bool is_physical_pb_type() const;
     std::string physical_mode_name() const;
     std::string idle_mode_name() const;
-    std::string mode_bits() const;
+    std::vector<size_t> mode_bits() const;
     std::string circuit_model_name() const;
     int physical_pb_type_index_factor() const;
     int physical_pb_type_index_offset() const;
@@ -61,7 +61,7 @@ class PbTypeAnnotation {
     void set_physical_parent_mode_names(const std::vector<std::string>& names);
     void set_physical_mode_name(const std::string& name);
     void set_idle_mode_name(const std::string& name);
-    void set_mode_bits(const std::string& mode_bits);
+    void set_mode_bits(const std::vector<size_t>& mode_bits);
     void set_circuit_model_name(const std::string& name);
     void set_physical_pb_type_index_factor(const int& value);
     void set_physical_pb_type_index_offset(const int& value);
@@ -102,7 +102,7 @@ class PbTypeAnnotation {
     std::string idle_mode_name_;
 
     /* Configuration bits to select an operting mode for the circuit mode name */
-    std::string mode_bits_;
+    std::vector<size_t> mode_bits_;
 
     /* Circuit mode name linked to a physical pb_type.
      * This is only applicable to the physical pb_type
diff --git a/libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.cpp b/libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.cpp
index 253053bf5..a17e970b7 100644
--- a/libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.cpp
+++ b/libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.cpp
@@ -63,6 +63,31 @@ void read_xml_pb_port_annotation(pugi::xml_node& xml_port,
   pb_type_annotation.set_physical_pin_rotate_offset(name_attr, get_attribute(xml_port, "physical_mode_pin_rotate_offset", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(0));
 }
 
+/********************************************************************
+ * Parse mode_bits: convert from string to array of digits
+ * We only allow the bit to either '0' or '1'
+ *******************************************************************/
+static 
+std::vector<size_t> parse_mode_bits(pugi::xml_node& xml_mode_bits,
+                                    const pugiutil::loc_data& loc_data,
+                                    const std::string& mode_bit_str) {
+  std::vector<size_t> mode_bits;
+
+  for (const char& bit_char : mode_bit_str) {
+    if ('0' == bit_char) {
+      mode_bits.push_back(0);
+    } else if ('1' == bit_char) {
+      mode_bits.push_back(1);
+    } else {
+      archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_mode_bits),
+                     "Unexpected '%c' character found in the mode bit '%s'! Only allow either '0' or '1'\n",
+                     bit_char, mode_bit_str.c_str());
+    }
+  } 
+
+  return mode_bits;
+}
+
 /********************************************************************
  * Parse XML description for a pb_type annotation under a <pb_type> XML node
  *******************************************************************/
@@ -119,7 +144,8 @@ void read_xml_pb_type_annotation(pugi::xml_node& xml_pb_type,
   pb_type_annotation.set_idle_mode_name(get_attribute(xml_pb_type, "idle_mode_name", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string());
 
   /* Parse mode bits which are applied to both pb_types */
-  pb_type_annotation.set_mode_bits(get_attribute(xml_pb_type, "mode_bits", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string());
+  std::vector<size_t> mode_bit_data = parse_mode_bits(xml_pb_type, loc_data, get_attribute(xml_pb_type, "mode_bits", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string());
+  pb_type_annotation.set_mode_bits(mode_bit_data);
 
   /* If this is a physical pb_type, circuit model name is an optional attribute, 
    * which is applicable to leaf pb_type in the hierarchy 
diff --git a/libopenfpga/libarchopenfpga/src/write_xml_pb_type_annotation.cpp b/libopenfpga/libarchopenfpga/src/write_xml_pb_type_annotation.cpp
index a771c782d..531e117f1 100644
--- a/libopenfpga/libarchopenfpga/src/write_xml_pb_type_annotation.cpp
+++ b/libopenfpga/libarchopenfpga/src/write_xml_pb_type_annotation.cpp
@@ -159,7 +159,12 @@ void write_xml_pb_type_annotation(std::fstream& fp,
 
   /* Output mode_bits */
   if (!pb_type_annotation.mode_bits().empty()) { 
-    write_xml_attribute(fp, "mode_bits", pb_type_annotation.mode_bits().c_str());
+    /* Convert the vector of integer to string */
+    std::string mode_bits_str;
+    for (const size_t& bit : pb_type_annotation.mode_bits()) {
+      mode_bits_str += std::to_string(bit);
+    }
+    write_xml_attribute(fp, "mode_bits", mode_bits_str.c_str());
   }
 
   /* Output circuit model name */

From a722438fa3ab89dc1fe360483905c9d66e9cbec2 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 29 Jan 2020 12:27:55 -0700
Subject: [PATCH 043/645] add mode bits binding to pb_type annotation

---
 openfpga/src/base/annotate_pb_types.cpp      | 116 +++++++++++++++++++
 openfpga/src/base/vpr_pb_type_annotation.cpp |  20 ++++
 openfpga/src/base/vpr_pb_type_annotation.h   |   4 +-
 3 files changed, 139 insertions(+), 1 deletion(-)

diff --git a/openfpga/src/base/annotate_pb_types.cpp b/openfpga/src/base/annotate_pb_types.cpp
index 064fc2cc0..7095855e0 100644
--- a/openfpga/src/base/annotate_pb_types.cpp
+++ b/openfpga/src/base/annotate_pb_types.cpp
@@ -1011,6 +1011,118 @@ void link_vpr_pb_interconnect_to_circuit_model_implicit_annotation(const DeviceC
   }
 }
 
+/********************************************************************
+ * This function will bind mode selection bits to a primitive pb_type
+ * in the vpr_pb_type_annotation
+ *******************************************************************/
+static 
+bool link_primitive_pb_type_to_mode_bits(t_pb_type* primitive_pb_type, 
+                                         const PbTypeAnnotation& pb_type_annotation,
+                                         VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  /* Error out if this is not a primitive pb_type */
+  if (false == is_primitive_pb_type(primitive_pb_type)) {
+    VTR_LOG_ERROR("Mode selection is only applicable to primitive pb_type while pb_type '%s' is not primitve !\n",
+                  primitive_pb_type->name);
+    return false;
+  }
+
+  /* Update the annotation */
+  vpr_pb_type_annotation.add_pb_type_mode_bits(primitive_pb_type, pb_type_annotation.mode_bits());
+
+  return true;
+}
+
+/********************************************************************
+ * This function will link 
+ * - pb_type to mode bits by following 
+ *   the explicit definition in OpenFPGA architecture XML
+ *
+ * Note:
+ * - This function should be executed only AFTER 
+ *   the physical mode and physical pb_type annotation is completed
+ *   the physical pb_type circuit model annotation is completed
+ *******************************************************************/
+static 
+void link_vpr_pb_type_to_mode_bits_explicit_annotation(const DeviceContext& vpr_device_ctx, 
+                                                       const Arch& openfpga_arch,
+                                                       VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  /* Walk through the pb_type annotation stored in the openfpga arch */
+  for (const PbTypeAnnotation& pb_type_annotation : openfpga_arch.pb_type_annotations) {
+    if (true == pb_type_annotation.mode_bits().empty()) {
+      continue;
+    }
+
+    /* Convert the vector of integer to string */
+    std::string mode_bits_str;
+    for (const size_t& bit : pb_type_annotation.mode_bits()) {
+      mode_bits_str += std::to_string(bit);
+    }
+
+    /* Collect the information about the full hierarchy of physical pb_type to be annotated */
+    std::vector<std::string> target_pb_type_names;
+    std::vector<std::string> target_pb_mode_names;
+
+    if (true == pb_type_annotation.is_operating_pb_type()) {
+      target_pb_type_names = pb_type_annotation.operating_parent_pb_type_names();
+      target_pb_type_names.push_back(pb_type_annotation.operating_pb_type_name());
+      target_pb_mode_names = pb_type_annotation.operating_parent_mode_names();
+    }
+
+    if (true == pb_type_annotation.is_physical_pb_type()) {
+      target_pb_type_names = pb_type_annotation.physical_parent_pb_type_names();
+      target_pb_type_names.push_back(pb_type_annotation.physical_pb_type_name());
+      target_pb_mode_names = pb_type_annotation.physical_parent_mode_names();
+    }
+
+    /* We must have at least one pb_type in the list */
+    VTR_ASSERT_SAFE(0 < target_pb_type_names.size());
+
+    /* Pb type information are located at the logic_block_types in the device context of VPR
+     * We iterate over the vectors and find the pb_type matches the parent_pb_type_name
+     */
+    bool link_success = false;
+
+    for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
+      /* By pass nullptr for pb_type head */
+      if (nullptr == lb_type.pb_type) {
+        continue;
+      }
+      /* Check the name of the top-level pb_type, if it does not match, we can bypass */
+      if (target_pb_type_names[0] != std::string(lb_type.pb_type->name)) {
+        continue;
+      }
+      /* Match the name in the top-level, we go further to search the operating as well as
+       * physical pb_types in the graph */
+      t_pb_type* target_pb_type = try_find_pb_type_with_given_path(lb_type.pb_type, target_pb_type_names, 
+                                                                   target_pb_mode_names);
+      if (nullptr == target_pb_type) {
+        continue;
+      }
+
+      /* Only try to bind pb_type to circuit model when it is defined by users */
+      if (true == link_primitive_pb_type_to_mode_bits(target_pb_type,
+                                                      pb_type_annotation, vpr_pb_type_annotation)) {
+        /* Give a message */
+        VTR_LOG("Bind physical pb_type '%s' to mode selection bits '%s'\n",
+                target_pb_type->name,
+                mode_bits_str.c_str());
+
+        link_success = true;
+        break;
+      }
+    }
+
+    if (false == link_success) {
+      /* Not found, error out! */
+      VTR_LOG_ERROR("Unable to bind pb_type '%s' to mode_selection bits '%s'!\n",
+                    target_pb_type_names.back().c_str(),
+                    mode_bits_str.c_str());
+      return;
+    }
+  } 
+}
+
+
 /********************************************************************
  * Top-level function to link openfpga architecture to VPR, including:
  * - physical pb_type
@@ -1069,6 +1181,10 @@ void annotate_pb_types(const DeviceContext& vpr_device_ctx,
   /* TODO: check the circuit model annotation */
 
   /* Link physical pb_type to mode_bits */
+  VTR_LOG("\n");
+  VTR_LOG("Building annotation between physical pb_types and mode selection bits...\n");
+  link_vpr_pb_type_to_mode_bits_explicit_annotation(vpr_device_ctx, openfpga_arch,
+                                                    vpr_pb_type_annotation);
 
 } 
 
diff --git a/openfpga/src/base/vpr_pb_type_annotation.cpp b/openfpga/src/base/vpr_pb_type_annotation.cpp
index 867f40794..435f46be7 100644
--- a/openfpga/src/base/vpr_pb_type_annotation.cpp
+++ b/openfpga/src/base/vpr_pb_type_annotation.cpp
@@ -105,6 +105,15 @@ CircuitPortId VprPbTypeAnnotation::pb_circuit_port(t_port* pb_port) const {
   return pb_circuit_ports_.at(pb_port);
 }
 
+std::vector<size_t> VprPbTypeAnnotation::pb_type_mode_bits(t_pb_type* pb_type) const {
+  /* Ensure that the pb_type is in the list */
+  std::map<t_pb_type*, std::vector<size_t>>::const_iterator it = pb_type_mode_bits_.find(pb_type);
+  if (it == pb_type_mode_bits_.end()) {
+    /* Return an empty vector */
+    return std::vector<size_t>();
+  }
+  return pb_type_mode_bits_.at(pb_type);
+}
 
 /************************************************************************
  * Public mutators
@@ -201,4 +210,15 @@ void VprPbTypeAnnotation::add_pb_circuit_port(t_port* pb_port, const CircuitPort
   pb_circuit_ports_[pb_port] = circuit_port;
 }
 
+void VprPbTypeAnnotation::add_pb_type_mode_bits(t_pb_type* pb_type, const std::vector<size_t>& mode_bits) {
+  /* Warn any override attempt */
+  std::map<t_pb_type*, std::vector<size_t>>::const_iterator it = pb_type_mode_bits_.find(pb_type);
+  if (it != pb_type_mode_bits_.end()) {
+    VTR_LOG_WARN("Override the mode bits mapping for pb_type '%s'!\n",
+                 pb_type->name);
+  }
+
+  pb_type_mode_bits_[pb_type] = mode_bits;
+}
+
 } /* End namespace openfpga*/
diff --git a/openfpga/src/base/vpr_pb_type_annotation.h b/openfpga/src/base/vpr_pb_type_annotation.h
index fb0fec934..24535ee4a 100644
--- a/openfpga/src/base/vpr_pb_type_annotation.h
+++ b/openfpga/src/base/vpr_pb_type_annotation.h
@@ -38,6 +38,7 @@ class VprPbTypeAnnotation {
     CircuitModelId interconnect_circuit_model(t_interconnect* pb_interconnect) const;
     e_interconnect interconnect_physical_type(t_interconnect* pb_interconnect) const;
     CircuitPortId pb_circuit_port(t_port* pb_port) const;
+    std::vector<size_t> pb_type_mode_bits(t_pb_type* pb_type) const;
   public:  /* Public mutators */
     void add_pb_type_physical_mode(t_pb_type* pb_type, t_mode* physical_mode);
     void add_physical_pb_type(t_pb_type* operating_pb_type, t_pb_type* physical_pb_type);
@@ -47,6 +48,7 @@ class VprPbTypeAnnotation {
     void add_interconnect_circuit_model(t_interconnect* pb_interconnect, const CircuitModelId& circuit_model);
     void add_interconnect_physical_type(t_interconnect* pb_interconnect, const e_interconnect& physical_type);
     void add_pb_circuit_port(t_port* pb_port, const CircuitPortId& circuit_port);
+    void add_pb_type_mode_bits(t_pb_type* pb_type, const std::vector<size_t>& mode_bits);
   private: /* Internal data */
     /* Pair a regular pb_type to its physical pb_type */
     std::map<t_pb_type*, t_pb_type*> physical_pb_types_;
@@ -82,7 +84,7 @@ class VprPbTypeAnnotation {
      * - if the pb_type is an operating pb_type, the mode bits will be applied
      *   when the operating pb_type is used by packer
      */
-    std::map<t_pb_type*, std::vector<bool>> pb_type_mode_bits_;
+    std::map<t_pb_type*, std::vector<size_t>> pb_type_mode_bits_;
 
     /* Pair a pb_port to its physical pb_port 
      * Note:

From b67358d2c5e8fe4ebed16c01cf25dfd8f65c8f0d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 29 Jan 2020 12:56:49 -0700
Subject: [PATCH 044/645] add check codes for physical pb_type circuit model
 annotation

---
 openfpga/src/base/annotate_pb_types.cpp | 100 +++++++++++++++++++++++-
 1 file changed, 99 insertions(+), 1 deletion(-)

diff --git a/openfpga/src/base/annotate_pb_types.cpp b/openfpga/src/base/annotate_pb_types.cpp
index 7095855e0..e326cc772 100644
--- a/openfpga/src/base/annotate_pb_types.cpp
+++ b/openfpga/src/base/annotate_pb_types.cpp
@@ -1011,6 +1011,103 @@ void link_vpr_pb_interconnect_to_circuit_model_implicit_annotation(const DeviceC
   }
 }
 
+/********************************************************************
+ * This function will recursively traverse only the physical mode
+ * and physical pb_types in the graph to ensure
+ *  - Every physical pb_type should be linked to a valid circuit model
+ *  - Every port of the pb_type have been linked to a valid port of a circuit model
+ *  - Every interconnect has been linked to a valid circuit model
+ *    in a correct type
+ *******************************************************************/
+static 
+void rec_check_vpr_pb_type_circuit_model_annotation(t_pb_type* cur_pb_type,
+                                                    const CircuitLibrary& circuit_lib,
+                                                    const VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                                    size_t& num_err) {
+  /* Primitive pb_type should always been binded to a physical pb_type */
+  if (true == is_primitive_pb_type(cur_pb_type)) {
+    /* Every physical pb_type should be linked to a valid circuit model */
+    if (CircuitModelId::INVALID() == vpr_pb_type_annotation.pb_type_circuit_model(cur_pb_type)) {
+      VTR_LOG_ERROR("Found a physical pb_type '%s' missing circuit model binding!\n",
+                    cur_pb_type->name);
+      num_err++;
+      return; /* Invalid id already, further check is not applicable */
+    }
+    /* Every port of the pb_type have been linked to a valid port of a circuit model */
+    for (t_port* port : pb_type_ports(cur_pb_type)) {
+      if (CircuitPortId::INVALID() == vpr_pb_type_annotation.pb_circuit_port(port)) {
+        VTR_LOG_ERROR("Found a port '%s' of physical pb_type '%s' missing circuit port binding!\n",
+                      port->name, cur_pb_type->name);
+        num_err++;
+      }
+    }
+    return;
+  }
+
+  /* Every interconnect in the physical mode has been linked to a valid circuit model in a correct type */
+  t_mode* physical_mode = vpr_pb_type_annotation.physical_mode(cur_pb_type);
+  for (t_interconnect* interc : pb_mode_interconnects(physical_mode)) {
+    CircuitModelId interc_circuit_model = vpr_pb_type_annotation.interconnect_circuit_model(interc);
+    if (CircuitModelId::INVALID() == interc_circuit_model) {
+      VTR_LOG_ERROR("Found an interconnect '%s' under physical mode '%s' of pb_type '%s' missing circuit model binding!\n",
+                    interc->name,
+                    physical_mode->name,
+                    cur_pb_type->name);
+      num_err++;
+      continue;
+    }
+    e_circuit_model_type required_circuit_model_type = pb_interconnect_require_circuit_model_type(vpr_pb_type_annotation.interconnect_physical_type(interc));
+    if (circuit_lib.model_type(interc_circuit_model) != required_circuit_model_type) {
+      VTR_LOG_ERROR("Found an interconnect '%s' under physical mode '%s' of pb_type '%s' linked to a circuit model '%s' with a wrong type!\nExpect: '%s' Linked: '%s'\n",
+                    interc->name,
+                    physical_mode->name, 
+                    cur_pb_type->name,
+                    circuit_lib.model_name(interc_circuit_model).c_str(),
+                    CIRCUIT_MODEL_TYPE_STRING[circuit_lib.model_type(interc_circuit_model)],
+                    CIRCUIT_MODEL_TYPE_STRING[required_circuit_model_type]);
+      num_err++;
+    }
+  } 
+
+  /* Traverse only the physical mode */
+  for (int ichild = 0; ichild < physical_mode->num_pb_type_children; ++ichild) { 
+    rec_check_vpr_pb_type_circuit_model_annotation(&(physical_mode->pb_type_children[ichild]),
+                                                   circuit_lib,
+                                                   vpr_pb_type_annotation,
+                                                   num_err);
+  }
+}
+
+/********************************************************************
+ * This function will check the circuit model annotation for
+ * each physical pb_type in the device
+ *  - Every physical pb_type should be linked to a valid circuit model
+ *  - Every port of the pb_type have been linked a valid port of a circuit model
+ *  - Every interconnect has been linked to a valid circuit model
+ *    in a correct type
+ *******************************************************************/
+static 
+void check_vpr_pb_type_circuit_model_annotation(const DeviceContext& vpr_device_ctx, 
+                                                const CircuitLibrary& circuit_lib,
+                                                const VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  size_t num_err = 0;
+
+  for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
+    /* By pass nullptr for pb_type head */
+    if (nullptr == lb_type.pb_type) {
+      continue;
+    }
+    /* Top pb_type should always has a physical mode! */
+    rec_check_vpr_pb_type_circuit_model_annotation(lb_type.pb_type, circuit_lib, vpr_pb_type_annotation, num_err);
+  }
+  if (0 == num_err) {
+    VTR_LOG("Check physical pb_type annotation for circuit model passed.\n");
+  } else {
+    VTR_LOG_ERROR("Check physical pb_type annotation for circuit model failed with %ld errors!\n",
+                  num_err);
+  }
+}
+
 /********************************************************************
  * This function will bind mode selection bits to a primitive pb_type
  * in the vpr_pb_type_annotation
@@ -1178,7 +1275,8 @@ void annotate_pb_types(const DeviceContext& vpr_device_ctx,
                                                                 vpr_pb_type_annotation);
   link_vpr_pb_interconnect_to_circuit_model_implicit_annotation(vpr_device_ctx, openfpga_arch.circuit_lib,
                                                                 vpr_pb_type_annotation);
-  /* TODO: check the circuit model annotation */
+  check_vpr_pb_type_circuit_model_annotation(vpr_device_ctx, openfpga_arch.circuit_lib,
+                                             const_cast<const VprPbTypeAnnotation&>(vpr_pb_type_annotation));
 
   /* Link physical pb_type to mode_bits */
   VTR_LOG("\n");

From a4381563bcfaec676cb6209b8fb9c2a80961e266 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 29 Jan 2020 13:47:59 -0700
Subject: [PATCH 045/645] move check codes to separated source files

---
 openfpga/src/base/annotate_pb_types.cpp       | 266 +----------------
 .../src/base/check_pb_type_annotation.cpp     | 277 ++++++++++++++++++
 openfpga/src/base/check_pb_type_annotation.h  |  30 ++
 3 files changed, 308 insertions(+), 265 deletions(-)
 create mode 100644 openfpga/src/base/check_pb_type_annotation.cpp
 create mode 100644 openfpga/src/base/check_pb_type_annotation.h

diff --git a/openfpga/src/base/annotate_pb_types.cpp b/openfpga/src/base/annotate_pb_types.cpp
index e326cc772..3163813b8 100644
--- a/openfpga/src/base/annotate_pb_types.cpp
+++ b/openfpga/src/base/annotate_pb_types.cpp
@@ -10,6 +10,7 @@
 #include "vpr_pb_type_annotation.h"
 #include "pb_type_utils.h"
 #include "annotate_pb_graph.h"
+#include "check_pb_type_annotation.h"
 #include "annotate_pb_types.h"
 
 /* begin namespace openfpga */
@@ -178,88 +179,6 @@ void build_vpr_physical_pb_mode_implicit_annotation(const DeviceContext& vpr_dev
   }
 }
 
-/********************************************************************
- * This function will recursively traverse pb_type graph to ensure
- * 1. there is only a physical mode under each pb_type
- * 2. physical mode appears only when its parent is a physical mode.
- *******************************************************************/
-static 
-void rec_check_vpr_physical_pb_mode_annotation(t_pb_type* cur_pb_type,
-                                               const bool& expect_physical_mode,
-                                               const VprPbTypeAnnotation& vpr_pb_type_annotation,
-                                               size_t& num_err) {
-  /* We do not check any primitive pb_type */
-  if (true == is_primitive_pb_type(cur_pb_type)) {
-    return;
-  }
-
-  /* For non-primitive pb_type:
-   * - If we expect a physical mode to exist under this pb_type
-   *   we should be able to find one in the annoation 
-   * - If we do NOT expect a physical mode, make sure we find 
-   *   nothing in the annotation
-   */
-  if (true == expect_physical_mode) {
-    if (nullptr == vpr_pb_type_annotation.physical_mode(cur_pb_type)) {
-      VTR_LOG_ERROR("Unable to find a physical mode for a multi-mode pb_type '%s'!\n",
-                    cur_pb_type->name);
-      VTR_LOG_ERROR("Please specify in the OpenFPGA architecture\n");
-      num_err++;
-      return;
-    }
-  } else {
-    VTR_ASSERT_SAFE(false == expect_physical_mode);
-    if (nullptr != vpr_pb_type_annotation.physical_mode(cur_pb_type)) {
-      VTR_LOG_ERROR("Find a physical mode '%s' for pb_type '%s' which is not under any physical mode!\n",
-                    vpr_pb_type_annotation.physical_mode(cur_pb_type)->name,
-                    cur_pb_type->name);
-      num_err++;
-      return;
-    }
-  }
-
-  /* Traverse all the modes
-   * - for pb_type children under a physical mode, we expect an physical mode 
-   * - for pb_type children under non-physical mode, we expect no physical mode 
-   */
-  for (int imode = 0; imode < cur_pb_type->num_modes; ++imode) {
-    bool expect_child_physical_mode = false;
-    if (&(cur_pb_type->modes[imode]) == vpr_pb_type_annotation.physical_mode(cur_pb_type)) {
-      expect_child_physical_mode = true && expect_physical_mode; 
-    }
-    for (int ichild = 0; ichild < cur_pb_type->modes[imode].num_pb_type_children; ++ichild) { 
-      rec_check_vpr_physical_pb_mode_annotation(&(cur_pb_type->modes[imode].pb_type_children[ichild]),
-                                                expect_child_physical_mode, vpr_pb_type_annotation,
-                                                num_err);
-    }
-  }
-}
-
-/********************************************************************
- * This function will check the physical mode annotation for
- * each pb_type in the device
- *******************************************************************/
-static 
-void check_vpr_physical_pb_mode_annotation(const DeviceContext& vpr_device_ctx, 
-                                           const VprPbTypeAnnotation& vpr_pb_type_annotation) {
-  size_t num_err = 0;
-
-  for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
-    /* By pass nullptr for pb_type head */
-    if (nullptr == lb_type.pb_type) {
-      continue;
-    }
-    /* Top pb_type should always has a physical mode! */
-    rec_check_vpr_physical_pb_mode_annotation(lb_type.pb_type, true, vpr_pb_type_annotation, num_err);
-  }
-  if (0 == num_err) {
-    VTR_LOG("Check physical mode annotation for pb_types passed.\n");
-  } else {
-    VTR_LOG("Check physical mode annotation for pb_types failed with %ld errors!\n",
-            num_err);
-  }
-}
-
 /********************************************************************
  * This function aims to make a pair of operating and physical 
  * pb_types:
@@ -499,91 +418,6 @@ void build_vpr_physical_pb_type_implicit_annotation(const DeviceContext& vpr_dev
   }
 }
 
-/********************************************************************
- * This function will check 
- * - if a primitive pb_type has been mapped to a physical pb_type 
- * - if every port of the pb_type have been linked a port of a physical pb_type
- *******************************************************************/
-static 
-void check_vpr_physical_primitive_pb_type_annotation(t_pb_type* cur_pb_type,
-                                                     const VprPbTypeAnnotation& vpr_pb_type_annotation,
-                                                     size_t& num_err) {
-  if (nullptr == vpr_pb_type_annotation.physical_pb_type(cur_pb_type)) {
-    VTR_LOG_ERROR("Find a pb_type '%s' which has not been mapped to any physical pb_type!\n",
-                  cur_pb_type->name);
-    VTR_LOG_ERROR("Please specify in the OpenFPGA architecture\n");
-    num_err++;  
-    return;
-  }
-
-  /* Now we need to check each port of the pb_type */ 
-  for (t_port* pb_port : pb_type_ports(cur_pb_type)) {
-    if (nullptr == vpr_pb_type_annotation.physical_pb_port(pb_port)) {
-      VTR_LOG_ERROR("Find a port '%s' of pb_type '%s' which has not been mapped to any physical port!\n",
-                    pb_port->name, cur_pb_type->name);
-      VTR_LOG_ERROR("Please specify in the OpenFPGA architecture\n");
-      num_err++;
-    }
-  }
-
-  return;
-}
-
-/********************************************************************
- * This function will recursively traverse pb_type graph to ensure
- * 1. there is only a physical mode under each pb_type
- * 2. physical mode appears only when its parent is a physical mode.
- *******************************************************************/
-static 
-void rec_check_vpr_physical_pb_type_annotation(t_pb_type* cur_pb_type,
-                                               const VprPbTypeAnnotation& vpr_pb_type_annotation,
-                                               size_t& num_err) {
-  /* Primitive pb_type should always been binded to a physical pb_type */
-  if (true == is_primitive_pb_type(cur_pb_type)) {
-    check_vpr_physical_primitive_pb_type_annotation(cur_pb_type, vpr_pb_type_annotation, num_err);
-    return;
-  }
-
-  /* Traverse all the modes
-   * - for pb_type children under a physical mode, we expect an physical mode 
-   * - for pb_type children under non-physical mode, we expect no physical mode 
-   */
-  for (int imode = 0; imode < cur_pb_type->num_modes; ++imode) {
-    for (int ichild = 0; ichild < cur_pb_type->modes[imode].num_pb_type_children; ++ichild) { 
-      rec_check_vpr_physical_pb_type_annotation(&(cur_pb_type->modes[imode].pb_type_children[ichild]),
-                                                vpr_pb_type_annotation,
-                                                num_err);
-    }
-  }
-}
-
-/********************************************************************
- * This function will check the physical pb_type annotation for
- * each pb_type in the device
- * Every pb_type should have been linked to a physical pb_type
- * and every port of the pb_type have been linked a port of a physical pb_type
- *******************************************************************/
-static 
-void check_vpr_physical_pb_type_annotation(const DeviceContext& vpr_device_ctx, 
-                                           const VprPbTypeAnnotation& vpr_pb_type_annotation) {
-  size_t num_err = 0;
-
-  for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
-    /* By pass nullptr for pb_type head */
-    if (nullptr == lb_type.pb_type) {
-      continue;
-    }
-    /* Top pb_type should always has a physical mode! */
-    rec_check_vpr_physical_pb_type_annotation(lb_type.pb_type, vpr_pb_type_annotation, num_err);
-  }
-  if (0 == num_err) {
-    VTR_LOG("Check physical pb_type annotation for pb_types passed.\n");
-  } else {
-    VTR_LOG("Check physical pb_type annotation for pb_types failed with %ld errors!\n",
-            num_err);
-  }
-}
-
 /********************************************************************
  * This function aims to link all the ports defined under a physical 
  * pb_type to the ports of circuit model in the circuit library
@@ -1011,103 +845,6 @@ void link_vpr_pb_interconnect_to_circuit_model_implicit_annotation(const DeviceC
   }
 }
 
-/********************************************************************
- * This function will recursively traverse only the physical mode
- * and physical pb_types in the graph to ensure
- *  - Every physical pb_type should be linked to a valid circuit model
- *  - Every port of the pb_type have been linked to a valid port of a circuit model
- *  - Every interconnect has been linked to a valid circuit model
- *    in a correct type
- *******************************************************************/
-static 
-void rec_check_vpr_pb_type_circuit_model_annotation(t_pb_type* cur_pb_type,
-                                                    const CircuitLibrary& circuit_lib,
-                                                    const VprPbTypeAnnotation& vpr_pb_type_annotation,
-                                                    size_t& num_err) {
-  /* Primitive pb_type should always been binded to a physical pb_type */
-  if (true == is_primitive_pb_type(cur_pb_type)) {
-    /* Every physical pb_type should be linked to a valid circuit model */
-    if (CircuitModelId::INVALID() == vpr_pb_type_annotation.pb_type_circuit_model(cur_pb_type)) {
-      VTR_LOG_ERROR("Found a physical pb_type '%s' missing circuit model binding!\n",
-                    cur_pb_type->name);
-      num_err++;
-      return; /* Invalid id already, further check is not applicable */
-    }
-    /* Every port of the pb_type have been linked to a valid port of a circuit model */
-    for (t_port* port : pb_type_ports(cur_pb_type)) {
-      if (CircuitPortId::INVALID() == vpr_pb_type_annotation.pb_circuit_port(port)) {
-        VTR_LOG_ERROR("Found a port '%s' of physical pb_type '%s' missing circuit port binding!\n",
-                      port->name, cur_pb_type->name);
-        num_err++;
-      }
-    }
-    return;
-  }
-
-  /* Every interconnect in the physical mode has been linked to a valid circuit model in a correct type */
-  t_mode* physical_mode = vpr_pb_type_annotation.physical_mode(cur_pb_type);
-  for (t_interconnect* interc : pb_mode_interconnects(physical_mode)) {
-    CircuitModelId interc_circuit_model = vpr_pb_type_annotation.interconnect_circuit_model(interc);
-    if (CircuitModelId::INVALID() == interc_circuit_model) {
-      VTR_LOG_ERROR("Found an interconnect '%s' under physical mode '%s' of pb_type '%s' missing circuit model binding!\n",
-                    interc->name,
-                    physical_mode->name,
-                    cur_pb_type->name);
-      num_err++;
-      continue;
-    }
-    e_circuit_model_type required_circuit_model_type = pb_interconnect_require_circuit_model_type(vpr_pb_type_annotation.interconnect_physical_type(interc));
-    if (circuit_lib.model_type(interc_circuit_model) != required_circuit_model_type) {
-      VTR_LOG_ERROR("Found an interconnect '%s' under physical mode '%s' of pb_type '%s' linked to a circuit model '%s' with a wrong type!\nExpect: '%s' Linked: '%s'\n",
-                    interc->name,
-                    physical_mode->name, 
-                    cur_pb_type->name,
-                    circuit_lib.model_name(interc_circuit_model).c_str(),
-                    CIRCUIT_MODEL_TYPE_STRING[circuit_lib.model_type(interc_circuit_model)],
-                    CIRCUIT_MODEL_TYPE_STRING[required_circuit_model_type]);
-      num_err++;
-    }
-  } 
-
-  /* Traverse only the physical mode */
-  for (int ichild = 0; ichild < physical_mode->num_pb_type_children; ++ichild) { 
-    rec_check_vpr_pb_type_circuit_model_annotation(&(physical_mode->pb_type_children[ichild]),
-                                                   circuit_lib,
-                                                   vpr_pb_type_annotation,
-                                                   num_err);
-  }
-}
-
-/********************************************************************
- * This function will check the circuit model annotation for
- * each physical pb_type in the device
- *  - Every physical pb_type should be linked to a valid circuit model
- *  - Every port of the pb_type have been linked a valid port of a circuit model
- *  - Every interconnect has been linked to a valid circuit model
- *    in a correct type
- *******************************************************************/
-static 
-void check_vpr_pb_type_circuit_model_annotation(const DeviceContext& vpr_device_ctx, 
-                                                const CircuitLibrary& circuit_lib,
-                                                const VprPbTypeAnnotation& vpr_pb_type_annotation) {
-  size_t num_err = 0;
-
-  for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
-    /* By pass nullptr for pb_type head */
-    if (nullptr == lb_type.pb_type) {
-      continue;
-    }
-    /* Top pb_type should always has a physical mode! */
-    rec_check_vpr_pb_type_circuit_model_annotation(lb_type.pb_type, circuit_lib, vpr_pb_type_annotation, num_err);
-  }
-  if (0 == num_err) {
-    VTR_LOG("Check physical pb_type annotation for circuit model passed.\n");
-  } else {
-    VTR_LOG_ERROR("Check physical pb_type annotation for circuit model failed with %ld errors!\n",
-                  num_err);
-  }
-}
-
 /********************************************************************
  * This function will bind mode selection bits to a primitive pb_type
  * in the vpr_pb_type_annotation
@@ -1219,7 +956,6 @@ void link_vpr_pb_type_to_mode_bits_explicit_annotation(const DeviceContext& vpr_
   } 
 }
 
-
 /********************************************************************
  * Top-level function to link openfpga architecture to VPR, including:
  * - physical pb_type
diff --git a/openfpga/src/base/check_pb_type_annotation.cpp b/openfpga/src/base/check_pb_type_annotation.cpp
new file mode 100644
index 000000000..b77e48162
--- /dev/null
+++ b/openfpga/src/base/check_pb_type_annotation.cpp
@@ -0,0 +1,277 @@
+/********************************************************************
+ * This file includes functions to build links between pb_types
+ * in particular to annotate the physical mode and physical pb_type
+ *******************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_time.h"
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+#include "pb_type_utils.h"
+#include "check_pb_type_annotation.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * This function will recursively traverse pb_type graph to ensure
+ * 1. there is only a physical mode under each pb_type
+ * 2. physical mode appears only when its parent is a physical mode.
+ *******************************************************************/
+static 
+void rec_check_vpr_physical_pb_mode_annotation(t_pb_type* cur_pb_type,
+                                               const bool& expect_physical_mode,
+                                               const VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                               size_t& num_err) {
+  /* We do not check any primitive pb_type */
+  if (true == is_primitive_pb_type(cur_pb_type)) {
+    return;
+  }
+
+  /* For non-primitive pb_type:
+   * - If we expect a physical mode to exist under this pb_type
+   *   we should be able to find one in the annoation 
+   * - If we do NOT expect a physical mode, make sure we find 
+   *   nothing in the annotation
+   */
+  if (true == expect_physical_mode) {
+    if (nullptr == vpr_pb_type_annotation.physical_mode(cur_pb_type)) {
+      VTR_LOG_ERROR("Unable to find a physical mode for a multi-mode pb_type '%s'!\n",
+                    cur_pb_type->name);
+      VTR_LOG_ERROR("Please specify in the OpenFPGA architecture\n");
+      num_err++;
+      return;
+    }
+  } else {
+    VTR_ASSERT_SAFE(false == expect_physical_mode);
+    if (nullptr != vpr_pb_type_annotation.physical_mode(cur_pb_type)) {
+      VTR_LOG_ERROR("Find a physical mode '%s' for pb_type '%s' which is not under any physical mode!\n",
+                    vpr_pb_type_annotation.physical_mode(cur_pb_type)->name,
+                    cur_pb_type->name);
+      num_err++;
+      return;
+    }
+  }
+
+  /* Traverse all the modes
+   * - for pb_type children under a physical mode, we expect an physical mode 
+   * - for pb_type children under non-physical mode, we expect no physical mode 
+   */
+  for (int imode = 0; imode < cur_pb_type->num_modes; ++imode) {
+    bool expect_child_physical_mode = false;
+    if (&(cur_pb_type->modes[imode]) == vpr_pb_type_annotation.physical_mode(cur_pb_type)) {
+      expect_child_physical_mode = true && expect_physical_mode; 
+    }
+    for (int ichild = 0; ichild < cur_pb_type->modes[imode].num_pb_type_children; ++ichild) { 
+      rec_check_vpr_physical_pb_mode_annotation(&(cur_pb_type->modes[imode].pb_type_children[ichild]),
+                                                expect_child_physical_mode, vpr_pb_type_annotation,
+                                                num_err);
+    }
+  }
+}
+
+/********************************************************************
+ * This function will check the physical mode annotation for
+ * each pb_type in the device
+ *******************************************************************/
+void check_vpr_physical_pb_mode_annotation(const DeviceContext& vpr_device_ctx, 
+                                           const VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  size_t num_err = 0;
+
+  for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
+    /* By pass nullptr for pb_type head */
+    if (nullptr == lb_type.pb_type) {
+      continue;
+    }
+    /* Top pb_type should always has a physical mode! */
+    rec_check_vpr_physical_pb_mode_annotation(lb_type.pb_type, true, vpr_pb_type_annotation, num_err);
+  }
+  if (0 == num_err) {
+    VTR_LOG("Check physical mode annotation for pb_types passed.\n");
+  } else {
+    VTR_LOG("Check physical mode annotation for pb_types failed with %ld errors!\n",
+            num_err);
+  }
+}
+
+/********************************************************************
+ * This function will check 
+ * - if a primitive pb_type has been mapped to a physical pb_type 
+ * - if every port of the pb_type have been linked a port of a physical pb_type
+ *******************************************************************/
+static 
+void check_vpr_physical_primitive_pb_type_annotation(t_pb_type* cur_pb_type,
+                                                     const VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                                     size_t& num_err) {
+  if (nullptr == vpr_pb_type_annotation.physical_pb_type(cur_pb_type)) {
+    VTR_LOG_ERROR("Find a pb_type '%s' which has not been mapped to any physical pb_type!\n",
+                  cur_pb_type->name);
+    VTR_LOG_ERROR("Please specify in the OpenFPGA architecture\n");
+    num_err++;  
+    return;
+  }
+
+  /* Now we need to check each port of the pb_type */ 
+  for (t_port* pb_port : pb_type_ports(cur_pb_type)) {
+    if (nullptr == vpr_pb_type_annotation.physical_pb_port(pb_port)) {
+      VTR_LOG_ERROR("Find a port '%s' of pb_type '%s' which has not been mapped to any physical port!\n",
+                    pb_port->name, cur_pb_type->name);
+      VTR_LOG_ERROR("Please specify in the OpenFPGA architecture\n");
+      num_err++;
+    }
+  }
+
+  return;
+}
+
+/********************************************************************
+ * This function will recursively traverse pb_type graph to ensure
+ * 1. there is only a physical mode under each pb_type
+ * 2. physical mode appears only when its parent is a physical mode.
+ *******************************************************************/
+static 
+void rec_check_vpr_physical_pb_type_annotation(t_pb_type* cur_pb_type,
+                                               const VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                               size_t& num_err) {
+  /* Primitive pb_type should always been binded to a physical pb_type */
+  if (true == is_primitive_pb_type(cur_pb_type)) {
+    check_vpr_physical_primitive_pb_type_annotation(cur_pb_type, vpr_pb_type_annotation, num_err);
+    return;
+  }
+
+  /* Traverse all the modes
+   * - for pb_type children under a physical mode, we expect an physical mode 
+   * - for pb_type children under non-physical mode, we expect no physical mode 
+   */
+  for (int imode = 0; imode < cur_pb_type->num_modes; ++imode) {
+    for (int ichild = 0; ichild < cur_pb_type->modes[imode].num_pb_type_children; ++ichild) { 
+      rec_check_vpr_physical_pb_type_annotation(&(cur_pb_type->modes[imode].pb_type_children[ichild]),
+                                                vpr_pb_type_annotation,
+                                                num_err);
+    }
+  }
+}
+
+/********************************************************************
+ * This function will check the physical pb_type annotation for
+ * each pb_type in the device
+ * Every pb_type should have been linked to a physical pb_type
+ * and every port of the pb_type have been linked a port of a physical pb_type
+ *******************************************************************/
+void check_vpr_physical_pb_type_annotation(const DeviceContext& vpr_device_ctx, 
+                                           const VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  size_t num_err = 0;
+
+  for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
+    /* By pass nullptr for pb_type head */
+    if (nullptr == lb_type.pb_type) {
+      continue;
+    }
+    /* Top pb_type should always has a physical mode! */
+    rec_check_vpr_physical_pb_type_annotation(lb_type.pb_type, vpr_pb_type_annotation, num_err);
+  }
+  if (0 == num_err) {
+    VTR_LOG("Check physical pb_type annotation for pb_types passed.\n");
+  } else {
+    VTR_LOG("Check physical pb_type annotation for pb_types failed with %ld errors!\n",
+            num_err);
+  }
+}
+
+/********************************************************************
+ * This function will recursively traverse only the physical mode
+ * and physical pb_types in the graph to ensure
+ *  - Every physical pb_type should be linked to a valid circuit model
+ *  - Every port of the pb_type have been linked to a valid port of a circuit model
+ *  - Every interconnect has been linked to a valid circuit model
+ *    in a correct type
+ *******************************************************************/
+static 
+void rec_check_vpr_pb_type_circuit_model_annotation(t_pb_type* cur_pb_type,
+                                                    const CircuitLibrary& circuit_lib,
+                                                    const VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                                    size_t& num_err) {
+  /* Primitive pb_type should always been binded to a physical pb_type */
+  if (true == is_primitive_pb_type(cur_pb_type)) {
+    /* Every physical pb_type should be linked to a valid circuit model */
+    if (CircuitModelId::INVALID() == vpr_pb_type_annotation.pb_type_circuit_model(cur_pb_type)) {
+      VTR_LOG_ERROR("Found a physical pb_type '%s' missing circuit model binding!\n",
+                    cur_pb_type->name);
+      num_err++;
+      return; /* Invalid id already, further check is not applicable */
+    }
+    /* Every port of the pb_type have been linked to a valid port of a circuit model */
+    for (t_port* port : pb_type_ports(cur_pb_type)) {
+      if (CircuitPortId::INVALID() == vpr_pb_type_annotation.pb_circuit_port(port)) {
+        VTR_LOG_ERROR("Found a port '%s' of physical pb_type '%s' missing circuit port binding!\n",
+                      port->name, cur_pb_type->name);
+        num_err++;
+      }
+    }
+    return;
+  }
+
+  /* Every interconnect in the physical mode has been linked to a valid circuit model in a correct type */
+  t_mode* physical_mode = vpr_pb_type_annotation.physical_mode(cur_pb_type);
+  for (t_interconnect* interc : pb_mode_interconnects(physical_mode)) {
+    CircuitModelId interc_circuit_model = vpr_pb_type_annotation.interconnect_circuit_model(interc);
+    if (CircuitModelId::INVALID() == interc_circuit_model) {
+      VTR_LOG_ERROR("Found an interconnect '%s' under physical mode '%s' of pb_type '%s' missing circuit model binding!\n",
+                    interc->name,
+                    physical_mode->name,
+                    cur_pb_type->name);
+      num_err++;
+      continue;
+    }
+    e_circuit_model_type required_circuit_model_type = pb_interconnect_require_circuit_model_type(vpr_pb_type_annotation.interconnect_physical_type(interc));
+    if (circuit_lib.model_type(interc_circuit_model) != required_circuit_model_type) {
+      VTR_LOG_ERROR("Found an interconnect '%s' under physical mode '%s' of pb_type '%s' linked to a circuit model '%s' with a wrong type!\nExpect: '%s' Linked: '%s'\n",
+                    interc->name,
+                    physical_mode->name, 
+                    cur_pb_type->name,
+                    circuit_lib.model_name(interc_circuit_model).c_str(),
+                    CIRCUIT_MODEL_TYPE_STRING[circuit_lib.model_type(interc_circuit_model)],
+                    CIRCUIT_MODEL_TYPE_STRING[required_circuit_model_type]);
+      num_err++;
+    }
+  } 
+
+  /* Traverse only the physical mode */
+  for (int ichild = 0; ichild < physical_mode->num_pb_type_children; ++ichild) { 
+    rec_check_vpr_pb_type_circuit_model_annotation(&(physical_mode->pb_type_children[ichild]),
+                                                   circuit_lib,
+                                                   vpr_pb_type_annotation,
+                                                   num_err);
+  }
+}
+
+/********************************************************************
+ * This function will check the circuit model annotation for
+ * each physical pb_type in the device
+ *  - Every physical pb_type should be linked to a valid circuit model
+ *  - Every port of the pb_type have been linked a valid port of a circuit model
+ *  - Every interconnect has been linked to a valid circuit model
+ *    in a correct type
+ *******************************************************************/
+void check_vpr_pb_type_circuit_model_annotation(const DeviceContext& vpr_device_ctx, 
+                                                const CircuitLibrary& circuit_lib,
+                                                const VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  size_t num_err = 0;
+
+  for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
+    /* By pass nullptr for pb_type head */
+    if (nullptr == lb_type.pb_type) {
+      continue;
+    }
+    /* Top pb_type should always has a physical mode! */
+    rec_check_vpr_pb_type_circuit_model_annotation(lb_type.pb_type, circuit_lib, vpr_pb_type_annotation, num_err);
+  }
+  if (0 == num_err) {
+    VTR_LOG("Check physical pb_type annotation for circuit model passed.\n");
+  } else {
+    VTR_LOG_ERROR("Check physical pb_type annotation for circuit model failed with %ld errors!\n",
+                  num_err);
+  }
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/base/check_pb_type_annotation.h b/openfpga/src/base/check_pb_type_annotation.h
new file mode 100644
index 000000000..25e13fc16
--- /dev/null
+++ b/openfpga/src/base/check_pb_type_annotation.h
@@ -0,0 +1,30 @@
+#ifndef CHECK_PB_TYPE_ANNOTATION_H
+#define CHECK_PB_TYPE_ANNOTATION_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "vpr_context.h"
+#include "openfpga_context.h"
+#include "vpr_pb_type_annotation.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void check_vpr_physical_pb_mode_annotation(const DeviceContext& vpr_device_ctx, 
+                                           const VprPbTypeAnnotation& vpr_pb_type_annotation);
+
+void check_vpr_physical_pb_type_annotation(const DeviceContext& vpr_device_ctx, 
+                                           const VprPbTypeAnnotation& vpr_pb_type_annotation);
+
+void check_vpr_pb_type_circuit_model_annotation(const DeviceContext& vpr_device_ctx, 
+                                                const CircuitLibrary& circuit_lib,
+                                                const VprPbTypeAnnotation& vpr_pb_type_annotation);
+
+} /* end namespace openfpga */
+
+#endif

From d2c47693f61d2c66306741bb496be6a9d036d72f Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 29 Jan 2020 14:29:00 -0700
Subject: [PATCH 046/645] add check codes for mode bits annotation to pb_types
 and clean up utils source files

---
 openfpga/src/base/annotate_pb_types.cpp       |   2 +
 .../src/base/check_pb_type_annotation.cpp     | 120 ++++++++-
 openfpga/src/base/check_pb_type_annotation.h  |   4 +
 openfpga/src/utils/circuit_library_utils.cpp  | 229 ++++++++++++++++++
 openfpga/src/utils/circuit_library_utils.h    |  44 ++++
 .../src/{base => utils}/pb_graph_utils.cpp    |   0
 openfpga/src/{base => utils}/pb_graph_utils.h |   0
 .../src/{base => utils}/pb_type_utils.cpp     |   0
 openfpga/src/{base => utils}/pb_type_utils.h  |   0
 9 files changed, 391 insertions(+), 8 deletions(-)
 create mode 100644 openfpga/src/utils/circuit_library_utils.cpp
 create mode 100644 openfpga/src/utils/circuit_library_utils.h
 rename openfpga/src/{base => utils}/pb_graph_utils.cpp (100%)
 rename openfpga/src/{base => utils}/pb_graph_utils.h (100%)
 rename openfpga/src/{base => utils}/pb_type_utils.cpp (100%)
 rename openfpga/src/{base => utils}/pb_type_utils.h (100%)

diff --git a/openfpga/src/base/annotate_pb_types.cpp b/openfpga/src/base/annotate_pb_types.cpp
index 3163813b8..023154c9b 100644
--- a/openfpga/src/base/annotate_pb_types.cpp
+++ b/openfpga/src/base/annotate_pb_types.cpp
@@ -1019,6 +1019,8 @@ void annotate_pb_types(const DeviceContext& vpr_device_ctx,
   VTR_LOG("Building annotation between physical pb_types and mode selection bits...\n");
   link_vpr_pb_type_to_mode_bits_explicit_annotation(vpr_device_ctx, openfpga_arch,
                                                     vpr_pb_type_annotation);
+  check_vpr_pb_type_mode_bits_annotation(vpr_device_ctx, openfpga_arch.circuit_lib,
+                                         const_cast<const VprPbTypeAnnotation&>(vpr_pb_type_annotation));
 
 } 
 
diff --git a/openfpga/src/base/check_pb_type_annotation.cpp b/openfpga/src/base/check_pb_type_annotation.cpp
index b77e48162..fdebba00c 100644
--- a/openfpga/src/base/check_pb_type_annotation.cpp
+++ b/openfpga/src/base/check_pb_type_annotation.cpp
@@ -8,6 +8,7 @@
 #include "vtr_log.h"
 
 #include "pb_type_utils.h"
+#include "circuit_library_utils.h"
 #include "check_pb_type_annotation.h"
 
 /* begin namespace openfpga */
@@ -89,8 +90,8 @@ void check_vpr_physical_pb_mode_annotation(const DeviceContext& vpr_device_ctx,
   if (0 == num_err) {
     VTR_LOG("Check physical mode annotation for pb_types passed.\n");
   } else {
-    VTR_LOG("Check physical mode annotation for pb_types failed with %ld errors!\n",
-            num_err);
+    VTR_LOG_ERROR("Check physical mode annotation for pb_types failed with %ld errors!\n",
+                  num_err);
   }
 }
 
@@ -139,10 +140,7 @@ void rec_check_vpr_physical_pb_type_annotation(t_pb_type* cur_pb_type,
     return;
   }
 
-  /* Traverse all the modes
-   * - for pb_type children under a physical mode, we expect an physical mode 
-   * - for pb_type children under non-physical mode, we expect no physical mode 
-   */
+  /* Traverse all the modes */
   for (int imode = 0; imode < cur_pb_type->num_modes; ++imode) {
     for (int ichild = 0; ichild < cur_pb_type->modes[imode].num_pb_type_children; ++ichild) { 
       rec_check_vpr_physical_pb_type_annotation(&(cur_pb_type->modes[imode].pb_type_children[ichild]),
@@ -173,8 +171,8 @@ void check_vpr_physical_pb_type_annotation(const DeviceContext& vpr_device_ctx,
   if (0 == num_err) {
     VTR_LOG("Check physical pb_type annotation for pb_types passed.\n");
   } else {
-    VTR_LOG("Check physical pb_type annotation for pb_types failed with %ld errors!\n",
-            num_err);
+    VTR_LOG_ERROR("Check physical pb_type annotation for pb_types failed with %ld errors!\n",
+                  num_err);
   }
 }
 
@@ -274,4 +272,110 @@ void check_vpr_pb_type_circuit_model_annotation(const DeviceContext& vpr_device_
   }
 }
 
+/********************************************************************
+ * This function will recursively traverse all the primitive pb_types 
+ * in the graph to ensure
+ *  - If a primitive pb_type has mode bits, it must have been linked to a physical pb_type
+ *    and the circuit model must have a port for mode selection. 
+ *    And the port size must match the length of mode bits
+ *******************************************************************/
+static 
+void rec_check_vpr_pb_type_mode_bits_annotation(t_pb_type* cur_pb_type,
+                                                const CircuitLibrary& circuit_lib,
+                                                const VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                                size_t& num_err) {
+  /* Primitive pb_type should always been binded to a physical pb_type */
+  if (true == is_primitive_pb_type(cur_pb_type)) {
+    /* Find the physical pb_type
+     * If the physical pb_type has mode selection bits, this pb_type must have as well!
+     */
+    t_pb_type* physical_pb_type = vpr_pb_type_annotation.physical_pb_type(cur_pb_type);
+
+    if (nullptr == physical_pb_type) {
+      VTR_LOG_ERROR("Find a pb_type '%s' which has not been mapped to any physical pb_type!\n",
+                    cur_pb_type->name);
+      VTR_LOG_ERROR("Please specify in the OpenFPGA architecture\n");
+      num_err++;
+      return;
+    }
+
+    if (vpr_pb_type_annotation.pb_type_mode_bits(cur_pb_type).size() != vpr_pb_type_annotation.pb_type_mode_bits(physical_pb_type).size()) {
+      VTR_LOG_ERROR("Found different sizes of mode_bits for pb_type '%s' and its physical pb_type '%s'\n",
+                    cur_pb_type->name,
+                    physical_pb_type->name);
+      num_err++;
+      return;
+    }
+  
+    /* Try to find a mode selection port for the circuit model linked to the circuit model */
+    CircuitModelId circuit_model = vpr_pb_type_annotation.pb_type_circuit_model(physical_pb_type);
+    if (CircuitModelId::INVALID() == vpr_pb_type_annotation.pb_type_circuit_model(physical_pb_type)) {
+      VTR_LOG_ERROR("Found a physical pb_type '%s' missing circuit model binding!\n",
+                    physical_pb_type->name);
+      num_err++;
+      return; /* Invalid id already, further check is not applicable */
+    }
+    
+    if (0 == vpr_pb_type_annotation.pb_type_mode_bits(cur_pb_type).size()) {
+      /* No mode bits to be checked! */
+      return;
+    }
+    /* Search the ports of this circuit model and we must have a mode selection port */
+    std::vector<CircuitPortId> mode_select_ports = find_circuit_mode_select_sram_ports(circuit_lib, circuit_model);
+    size_t port_num_mode_bits = 0;
+    for (const CircuitPortId& mode_select_port : mode_select_ports) {
+      port_num_mode_bits += circuit_lib.port_size(mode_select_port);
+    }
+    if (port_num_mode_bits != vpr_pb_type_annotation.pb_type_mode_bits(cur_pb_type).size()) {
+      VTR_LOG_ERROR("Length of mode bits of pb_type '%s' does not match the size(%ld) of mode selection ports of circuit model '%s'!\n",
+                    cur_pb_type->name,
+                    port_num_mode_bits,
+                    circuit_lib.model_name(circuit_model).c_str());
+      num_err++;
+    }
+
+    return;
+  }
+
+  /* Traverse all the modes */
+  for (int imode = 0; imode < cur_pb_type->num_modes; ++imode) {
+    for (int ichild = 0; ichild < cur_pb_type->modes[imode].num_pb_type_children; ++ichild) { 
+      rec_check_vpr_pb_type_mode_bits_annotation(&(cur_pb_type->modes[imode].pb_type_children[ichild]),
+                                                 circuit_lib, vpr_pb_type_annotation,
+                                                 num_err);
+    }
+  }
+}
+
+/********************************************************************
+ * This function will check the mode_bits annotation for each pb_type 
+ *  - If a primitive pb_type has mode bits, it must have been linked to a physical pb_type
+ *  - If a primitive pb_type has mode bits, the circuit model must have 
+ *    a port for mode selection. And the port size must match the length of mode bits
+ *
+ * Note:
+ *  - This function should be run after circuit mode and mode bits annotation 
+ *    is completed 
+ *******************************************************************/
+void check_vpr_pb_type_mode_bits_annotation(const DeviceContext& vpr_device_ctx, 
+                                            const CircuitLibrary& circuit_lib,
+                                            const VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  size_t num_err = 0;
+
+  for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
+    /* By pass nullptr for pb_type head */
+    if (nullptr == lb_type.pb_type) {
+      continue;
+    }
+    /* Top pb_type should always has a physical mode! */
+    rec_check_vpr_pb_type_mode_bits_annotation(lb_type.pb_type, circuit_lib, vpr_pb_type_annotation, num_err);
+  }
+  if (0 == num_err) {
+    VTR_LOG("Check pb_type annotation for mode selection bits passed.\n");
+  } else {
+    VTR_LOG_ERROR("Check physical pb_type annotation for mode selection bits failed with %ld errors!\n",
+                  num_err);
+  }
+}
+
 } /* end namespace openfpga */
diff --git a/openfpga/src/base/check_pb_type_annotation.h b/openfpga/src/base/check_pb_type_annotation.h
index 25e13fc16..d3d2799aa 100644
--- a/openfpga/src/base/check_pb_type_annotation.h
+++ b/openfpga/src/base/check_pb_type_annotation.h
@@ -25,6 +25,10 @@ void check_vpr_pb_type_circuit_model_annotation(const DeviceContext& vpr_device_
                                                 const CircuitLibrary& circuit_lib,
                                                 const VprPbTypeAnnotation& vpr_pb_type_annotation);
 
+void check_vpr_pb_type_mode_bits_annotation(const DeviceContext& vpr_device_ctx, 
+                                            const CircuitLibrary& circuit_lib,
+                                            const VprPbTypeAnnotation& vpr_pb_type_annotation);
+
 } /* end namespace openfpga */
 
 #endif
diff --git a/openfpga/src/utils/circuit_library_utils.cpp b/openfpga/src/utils/circuit_library_utils.cpp
new file mode 100644
index 000000000..720a0e7c1
--- /dev/null
+++ b/openfpga/src/utils/circuit_library_utils.cpp
@@ -0,0 +1,229 @@
+/************************************************************************
+ * Function to perform fundamental operation for the circuit library 
+ * These functions are not universal methods for the CircuitLibrary class
+ * They are made to ease the development in some specific purposes
+ * Please classify such functions in this file
+ ***********************************************************************/
+#include <algorithm>
+
+/* Headers from vtr util library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+#include "circuit_library_utils.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Get the model id of a SRAM model that is used to configure 
+ * a circuit model
+ *******************************************************************/
+std::vector<CircuitModelId> find_circuit_sram_models(const CircuitLibrary& circuit_lib,
+                                                     const CircuitModelId& circuit_model) {
+  /* SRAM model id is stored in the sram ports of a circuit model */
+  std::vector<CircuitPortId> sram_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_SRAM);
+  std::vector<CircuitModelId> sram_models;
+  
+  /* Create a list of sram models, but avoid duplicated model ids */
+  for (const auto& sram_port : sram_ports) {
+    CircuitModelId sram_model = circuit_lib.port_tri_state_model(sram_port);
+    VTR_ASSERT( true == circuit_lib.valid_model_id(sram_model) );
+    if (sram_models.end() != std::find(sram_models.begin(), sram_models.end(), sram_model)) {
+      continue;  /* Already in the list, skip the addition */
+    }
+    /* Not in the list, add it */
+    sram_models.push_back(sram_model);
+  }
+  
+  return sram_models;
+}
+
+/********************************************************************
+ * Find regular (not mode select) sram ports of a circuit model
+ *******************************************************************/
+std::vector<CircuitPortId> find_circuit_regular_sram_ports(const CircuitLibrary& circuit_lib,
+                                                           const CircuitModelId& circuit_model) {
+  std::vector<CircuitPortId> sram_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_SRAM, true);
+  std::vector<CircuitPortId> regular_sram_ports;
+
+  for (const auto& port : sram_ports) {
+    if (true == circuit_lib.port_is_mode_select(port)) {
+      continue;
+    }
+    regular_sram_ports.push_back(port);
+  }
+
+  return regular_sram_ports;
+}
+
+/********************************************************************
+ * Find mode select sram ports of a circuit model
+ *******************************************************************/
+std::vector<CircuitPortId> find_circuit_mode_select_sram_ports(const CircuitLibrary& circuit_lib,
+                                                               const CircuitModelId& circuit_model) {
+  std::vector<CircuitPortId> sram_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_SRAM, true);
+  std::vector<CircuitPortId> mode_select_sram_ports;
+
+  for (const auto& port : sram_ports) {
+    if (false == circuit_lib.port_is_mode_select(port)) {
+      continue;
+    }
+    mode_select_sram_ports.push_back(port);
+  }
+
+  return mode_select_sram_ports;
+}
+
+
+/********************************************************************
+ * Find the number of shared configuration bits for a ReRAM circuit 
+ * TODO: this function is subjected to be changed due to ReRAM-based SRAM cell design!!!
+ *******************************************************************/
+static 
+size_t find_rram_circuit_num_shared_config_bits(const CircuitLibrary& circuit_lib,
+                                                const CircuitModelId& rram_model,
+                                                const e_config_protocol_type& config_protocol_type) {
+  size_t num_shared_config_bits = 0;
+
+  /* Branch on the organization of configuration protocol */ 
+  switch (config_protocol_type) {
+  case CONFIG_MEM_STANDALONE:
+  case CONFIG_MEM_SCAN_CHAIN:
+    break;
+  case CONFIG_MEM_MEMORY_BANK: {
+    /* Find BL/WL ports */
+    std::vector<CircuitPortId> blb_ports = circuit_lib.model_ports_by_type(rram_model, CIRCUIT_MODEL_PORT_BLB);
+    for (auto blb_port : blb_ports) {
+      num_shared_config_bits = std::max((int)num_shared_config_bits, (int)circuit_lib.port_size(blb_port) - 1);
+    }
+    break;
+  }    
+  default:
+    VTR_LOG_ERROR("Invalid type of configuration protocol!\n");
+    exit(1);
+  }
+
+  return num_shared_config_bits;
+}
+
+/********************************************************************
+ * A generic function to find the number of shared configuration bits 
+ * for circuit model
+ * It will return 0 for CMOS circuits 
+ * It will return the maximum shared configuration bits across ReRAM models
+ *
+ * Note: This function may give WRONG results when all the SRAM ports
+ * are not properly linked to its circuit models!
+ * So, it should be called after the SRAM linking is done!!!
+ *
+ * IMPORTANT: This function should NOT be used to find the number of shared configuration bits
+ * for a multiplexer, because the multiplexer size is determined during 
+ * the FPGA architecture generation (NOT during the XML parsing). 
+ *******************************************************************/
+size_t find_circuit_num_shared_config_bits(const CircuitLibrary& circuit_lib,
+                                           const CircuitModelId& circuit_model,
+                                           const e_config_protocol_type& config_protocol_type) {
+  size_t num_shared_config_bits = 0;
+
+  std::vector<CircuitPortId> sram_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_SRAM);
+  for (auto sram_port : sram_ports) {
+    CircuitModelId sram_model = circuit_lib.port_tri_state_model(sram_port);
+    VTR_ASSERT( true == circuit_lib.valid_model_id(sram_model) );
+
+    /* Depend on the design technolgy of SRAM model, the number of configuration bits will be different */
+    switch (circuit_lib.design_tech_type(sram_model)) {
+    case CIRCUIT_MODEL_DESIGN_CMOS: 
+      /* CMOS circuit do not need shared configuration bits */
+      break;
+    case CIRCUIT_MODEL_DESIGN_RRAM: 
+       /* RRAM circuit do need shared configuration bits, but it is subjected to the largest one among different SRAM models */
+       num_shared_config_bits = std::max((int)num_shared_config_bits, (int)find_rram_circuit_num_shared_config_bits(circuit_lib, sram_model, config_protocol_type));
+       break;
+    default:
+      VTR_LOG_ERROR("Invalid design technology for SRAM circuit model!\n",
+                    circuit_lib.model_name(circuit_model).c_str());
+      exit(1);
+    }
+  } 
+
+  return num_shared_config_bits;
+}
+
+/********************************************************************
+ * A generic function to find the number of configuration bits 
+ * for circuit model
+ * It will sum up the sizes of all the sram ports 
+ * 
+ * IMPORTANT: This function should NOT be used to find the number of configuration bits
+ * for a multiplexer, because the multiplexer size is determined during 
+ * the FPGA architecture generation (NOT during the XML parsing). 
+ *******************************************************************/
+size_t find_circuit_num_config_bits(const CircuitLibrary& circuit_lib,
+                                    const CircuitModelId& circuit_model) {
+  size_t num_config_bits = 0;
+
+  std::vector<CircuitPortId> sram_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_SRAM);
+  for (auto sram_port : sram_ports) {
+    num_config_bits += circuit_lib.port_size(sram_port); 
+  } 
+
+  return num_config_bits;
+}
+
+/********************************************************************
+ * A generic function to find all the global ports in a circuit library
+ * 
+ * IMPORTANT: This function will uniquify the global ports whose share 
+ * share the same name !!!
+ *******************************************************************/
+std::vector<CircuitPortId> find_circuit_library_global_ports(const CircuitLibrary& circuit_lib) {
+  std::vector<CircuitPortId> global_ports;
+
+  for (auto port : circuit_lib.ports()) {
+    /* By pass non-global ports*/
+    if (false == circuit_lib.port_is_global(port)) {
+      continue;
+    }
+    /* Check if a same port with the same name has already been in the list */
+    bool add_to_list = true;
+    for (const auto& global_port : global_ports) {
+      if (0 == circuit_lib.port_prefix(port).compare(circuit_lib.port_prefix(global_port))) {
+        /* Same name, skip list update */
+        add_to_list = false;
+        break;
+      }
+    }
+    if (true == add_to_list) {
+      /* Add the global_port to the list */
+      global_ports.push_back(port);
+    }
+  } 
+
+  return global_ports;
+}
+
+/********************************************************************
+ * A generic function to find all the unique user-defined
+ * Verilog netlists in a circuit library
+ * Netlists with same names will be considered as one
+ *******************************************************************/
+std::vector<std::string> find_circuit_library_unique_verilog_netlists(const CircuitLibrary& circuit_lib) {
+  std::vector<std::string> netlists;
+
+  for (const CircuitModelId& model : circuit_lib.models()) {
+    /* Skip empty netlist names */
+    if (true == circuit_lib.model_verilog_netlist(model).empty()) {
+      continue;
+    }
+    /* See if the netlist name is already in the list */
+    std::vector<std::string>::iterator it = std::find(netlists.begin(), netlists.end(), circuit_lib.model_verilog_netlist(model));
+    if (it == netlists.end()) {
+      netlists.push_back(circuit_lib.model_verilog_netlist(model));
+    }
+  }
+
+ return netlists;
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/utils/circuit_library_utils.h b/openfpga/src/utils/circuit_library_utils.h
new file mode 100644
index 000000000..aad080b72
--- /dev/null
+++ b/openfpga/src/utils/circuit_library_utils.h
@@ -0,0 +1,44 @@
+/********************************************************************
+ * Header file for circuit_library_utils.cpp
+ *******************************************************************/
+#ifndef CIRCUIT_LIBRARY_UTILS_H
+#define CIRCUIT_LIBRARY_UTILS_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+
+#include <vector>
+#include "circuit_types.h"
+#include "circuit_library.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+std::vector<CircuitModelId> find_circuit_sram_models(const CircuitLibrary& circuit_lib,
+                                                     const CircuitModelId& circuit_model);
+
+std::vector<CircuitPortId> find_circuit_regular_sram_ports(const CircuitLibrary& circuit_lib,
+                                                           const CircuitModelId& circuit_model);
+
+std::vector<CircuitPortId> find_circuit_mode_select_sram_ports(const CircuitLibrary& circuit_lib,
+                                                               const CircuitModelId& circuit_model);
+
+size_t find_circuit_num_shared_config_bits(const CircuitLibrary& circuit_lib,
+                                           const CircuitModelId& circuit_model,
+                                           const e_config_protocol_type& sram_orgz_type);
+
+size_t find_circuit_num_config_bits(const CircuitLibrary& circuit_lib,
+                                    const CircuitModelId& circuit_model);
+
+std::vector<CircuitPortId> find_circuit_library_global_ports(const CircuitLibrary& circuit_lib);
+
+std::vector<std::string> find_circuit_library_unique_verilog_netlists(const CircuitLibrary& circuit_lib);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/base/pb_graph_utils.cpp b/openfpga/src/utils/pb_graph_utils.cpp
similarity index 100%
rename from openfpga/src/base/pb_graph_utils.cpp
rename to openfpga/src/utils/pb_graph_utils.cpp
diff --git a/openfpga/src/base/pb_graph_utils.h b/openfpga/src/utils/pb_graph_utils.h
similarity index 100%
rename from openfpga/src/base/pb_graph_utils.h
rename to openfpga/src/utils/pb_graph_utils.h
diff --git a/openfpga/src/base/pb_type_utils.cpp b/openfpga/src/utils/pb_type_utils.cpp
similarity index 100%
rename from openfpga/src/base/pb_type_utils.cpp
rename to openfpga/src/utils/pb_type_utils.cpp
diff --git a/openfpga/src/base/pb_type_utils.h b/openfpga/src/utils/pb_type_utils.h
similarity index 100%
rename from openfpga/src/base/pb_type_utils.h
rename to openfpga/src/utils/pb_type_utils.h

From 8c86c0af042ac0ea52a799c77e837d060b970df3 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 29 Jan 2020 16:23:41 -0700
Subject: [PATCH 047/645] add check netlist naming conflict command and
 functions

---
 .../base/check_netlist_naming_conflict.cpp    | 92 +++++++++++++++++++
 .../src/base/check_netlist_naming_conflict.h  | 23 +++++
 openfpga/src/base/openfpga_setup_command.cpp  | 34 ++++++-
 openfpga/test_script/s298.openfpga            |  3 +
 4 files changed, 148 insertions(+), 4 deletions(-)
 create mode 100644 openfpga/src/base/check_netlist_naming_conflict.cpp
 create mode 100644 openfpga/src/base/check_netlist_naming_conflict.h

diff --git a/openfpga/src/base/check_netlist_naming_conflict.cpp b/openfpga/src/base/check_netlist_naming_conflict.cpp
new file mode 100644
index 000000000..58980687f
--- /dev/null
+++ b/openfpga/src/base/check_netlist_naming_conflict.cpp
@@ -0,0 +1,92 @@
+/********************************************************************
+ * This file includes functions to detect and correct any naming
+ * in the users' BLIF netlist that violates the syntax of OpenFPGA
+ * fabric generator, i.e., Verilog generator and SPICE generator
+ *******************************************************************/
+#include <string>
+
+/* Headers from vtrutil library */
+#include "vtr_time.h"
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+#include "check_netlist_naming_conflict.h"
+
+/* Include global variables of VPR */
+#include "globals.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * This function aims to check if the name contains any of the 
+ * sensitive characters in the list
+ *******************************************************************/
+static 
+bool name_contain_sensitive_chars(const std::string& name, 
+                                  const std::string& sensitive_chars) {
+  for (const char& sensitive_char : sensitive_chars) {
+    /* Return true since we find a characters */
+    if (std::string::npos != name.find(sensitive_char)) {
+      return true;
+    }
+  }
+
+  return false;
+}
+
+/********************************************************************
+ * Detect and report any naming conflict by checking a list of 
+ * sensitive characters
+ * - Iterate over all the blocks and see if any block name contain 
+ *   any sensitive character
+ * - Iterate over all the nets and see if any net name contain 
+ *   any sensitive character
+ *******************************************************************/
+static 
+void detect_netlist_naming_conflict(const AtomNetlist& atom_netlist,
+                                    const std::string& sensitive_chars) {
+  size_t num_conflicts = 0;
+
+  /* Walk through blocks in the netlist */
+  for (const auto& block : atom_netlist.blocks()) {
+    const std::string& block_name = atom_netlist.block_name(block);
+    if (true == name_contain_sensitive_chars(block_name, sensitive_chars)) {
+      VTR_LOG("Block '%s' violates the syntax requirement by OpenFPGA!\n",
+              block_name.c_str());
+      num_conflicts++;
+    }
+  }
+
+  /* Walk through nets in the netlist */
+  for (const auto& net : atom_netlist.nets()) {
+    const std::string& net_name = atom_netlist.net_name(net);
+    if (true == name_contain_sensitive_chars(net_name, sensitive_chars)) {
+      VTR_LOG("Net '%s' violates the syntax requirement by OpenFPGA!\n",
+              net_name.c_str());
+      num_conflicts++;
+    }
+  }
+
+  if (0 < num_conflicts) {
+    VTR_LOG("Found %ld naming conflicts in the netlist. Please correct so as to use any fabric generators.\n",
+            num_conflicts);
+  }
+} 
+
+/********************************************************************
+ * Top-level function to detect and correct any naming
+ * in the users' BLIF netlist that violates the syntax of OpenFPGA
+ * fabric generator, i.e., Verilog generator and SPICE generator
+ *******************************************************************/
+void check_netlist_naming_conflict(OpenfpgaContext& openfpga_context,
+                                   const Command& cmd, const CommandContext& cmd_context) {
+  const std::string& sensitive_chars(".,:;\'\"+-<>()[]{}!@#$%^&*~`?/");
+
+  /* Do the main job first: detect any naming in the BLIF netlist that violates the syntax */
+  detect_netlist_naming_conflict(g_vpr_ctx.atom().nlist, sensitive_chars); 
+  
+} 
+
+} /* end namespace openfpga */
+
diff --git a/openfpga/src/base/check_netlist_naming_conflict.h b/openfpga/src/base/check_netlist_naming_conflict.h
new file mode 100644
index 000000000..54d86bca4
--- /dev/null
+++ b/openfpga/src/base/check_netlist_naming_conflict.h
@@ -0,0 +1,23 @@
+#ifndef CHECK_NETLIST_NAMING_CONFLICT_H
+#define CHECK_NETLIST_NAMING_CONFLICT_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "command.h"
+#include "command_context.h"
+#include "openfpga_context.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void check_netlist_naming_conflict(OpenfpgaContext& openfpga_context,
+                                   const Command& cmd, const CommandContext& cmd_context); 
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/base/openfpga_setup_command.cpp b/openfpga/src/base/openfpga_setup_command.cpp
index af078446a..ba7ad45b6 100644
--- a/openfpga/src/base/openfpga_setup_command.cpp
+++ b/openfpga/src/base/openfpga_setup_command.cpp
@@ -5,16 +5,22 @@
  *******************************************************************/
 #include "openfpga_read_arch.h"
 #include "openfpga_link_arch.h"
+#include "check_netlist_naming_conflict.h"
 #include "openfpga_setup_command.h"
 
 /* begin namespace openfpga */
 namespace openfpga {
 
 void add_openfpga_setup_commands(openfpga::Shell<OpenfpgaContext>& shell) {
+  /* Get the unique id of 'vpr' command which is to be used in creating the dependency graph */
+  const ShellCommandId& shell_cmd_vpr_id = shell.command(std::string("vpr"));
+
   /* Add a new class of commands */
   ShellCommandClassId openfpga_setup_cmd_class = shell.add_command_class("OpenFPGA setup");
 
-  /* Command 'read_openfpga_arch' */
+  /******************************** 
+   * Command 'read_openfpga_arch' 
+   */
   Command shell_cmd_read_arch("read_openfpga_arch");
   /* Add an option '--file' in short '-f'*/
   CommandOptionId read_arch_opt_file = shell_cmd_read_arch.add_option("file", true, "file path to the architecture XML");
@@ -26,7 +32,9 @@ void add_openfpga_setup_commands(openfpga::Shell<OpenfpgaContext>& shell) {
   shell.set_command_class(shell_cmd_read_arch_id, openfpga_setup_cmd_class);
   shell.set_command_execute_function(shell_cmd_read_arch_id, read_arch);
 
-  /* Command 'write_openfpga_arch' */
+  /******************************** 
+   * Command 'write_openfpga_arch' 
+   */
   Command shell_cmd_write_arch("write_openfpga_arch");
   /* Add an option '--file' in short '-f'*/
   CommandOptionId write_arch_opt_file = shell_cmd_write_arch.add_option("file", true, "file path to the architecture XML");
@@ -40,7 +48,9 @@ void add_openfpga_setup_commands(openfpga::Shell<OpenfpgaContext>& shell) {
   /* The 'write_openfpga_arch' command should NOT be executed before 'read_openfpga_arch' */
   shell.set_command_dependency(shell_cmd_write_arch_id, std::vector<ShellCommandId>(1, shell_cmd_read_arch_id));
 
-  /* Command 'link_openfpga_arch' */
+  /******************************** 
+   * Command 'link_openfpga_arch' 
+   */
   Command shell_cmd_link_openfpga_arch("link_openfpga_arch");
   
   /* Add command 'link_openfpga_arch' to the Shell */
@@ -48,12 +58,28 @@ void add_openfpga_setup_commands(openfpga::Shell<OpenfpgaContext>& shell) {
   shell.set_command_class(shell_cmd_link_openfpga_arch_id, openfpga_setup_cmd_class);
   shell.set_command_execute_function(shell_cmd_link_openfpga_arch_id, link_arch);
   /* The 'link_openfpga_arch' command should NOT be executed before 'read_openfpga_arch' and 'vpr' */
-  const ShellCommandId& shell_cmd_vpr_id = shell.command(std::string("vpr"));
   std::vector<ShellCommandId> cmd_dependency_link_openfpga_arch;
   cmd_dependency_link_openfpga_arch.push_back(shell_cmd_read_arch_id);
   cmd_dependency_link_openfpga_arch.push_back(shell_cmd_vpr_id);
   shell.set_command_dependency(shell_cmd_link_openfpga_arch_id, cmd_dependency_link_openfpga_arch);
 
+  /******************************************* 
+   * Command 'check_netlist_naming_conflict'
+   */ 
+  Command shell_cmd_check_netlist_naming_conflict("check_netlist_naming_conflict");
+  /* Add an option '--correction' */
+  shell_cmd_check_netlist_naming_conflict.add_option("correction", false, "Apply correction to any conflicts found");
+  /* Add an option '--report' */
+  CommandOptionId check_netlist_opt_rpt = shell_cmd_check_netlist_naming_conflict.add_option("report", false, "Output a report file about what any correction applied");
+  shell_cmd_check_netlist_naming_conflict.set_option_require_value(check_netlist_opt_rpt, openfpga::OPT_STRING);
+
+  /* Add command 'check_netlist_naming_conflict' to the Shell */
+  ShellCommandId shell_cmd_check_netlist_naming_conflict_id = shell.add_command(shell_cmd_check_netlist_naming_conflict, "Check any block/net naming in users' BLIF netlist violates the syntax of fabric generator");
+  shell.set_command_class(shell_cmd_check_netlist_naming_conflict_id, openfpga_setup_cmd_class);
+  shell.set_command_execute_function(shell_cmd_check_netlist_naming_conflict_id, check_netlist_naming_conflict);
+  /* The 'link_openfpga_arch' command should NOT be executed before 'read_openfpga_arch' and 'vpr' */
+  std::vector<ShellCommandId> cmd_dependency_check_netlist_naming_conflict(1, shell_cmd_vpr_id);
+  shell.set_command_dependency(shell_cmd_link_openfpga_arch_id, cmd_dependency_check_netlist_naming_conflict);
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/test_script/s298.openfpga b/openfpga/test_script/s298.openfpga
index 6d4eaa434..08e4d9ce3 100644
--- a/openfpga/test_script/s298.openfpga
+++ b/openfpga/test_script/s298.openfpga
@@ -7,5 +7,8 @@ read_openfpga_arch -f ./test_openfpga_arch/k6_N10_40nm_openfpga.xml
 # Annotate the OpenFPGA architecture to VPR data base
 link_openfpga_arch
 
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --correction --report ./netlist_renaming.rpt
+
 # Finish and exit OpenFPGA
 exit

From 2dc4c26257cdec0c822c564af4a98c42fa533733 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 29 Jan 2020 17:49:33 -0700
Subject: [PATCH 048/645] add naming fix-up

---
 .../base/check_netlist_naming_conflict.cpp    | 122 +++++++++++++++---
 openfpga/src/base/openfpga_context.h          |   5 +
 openfpga/src/base/openfpga_setup_command.cpp  |   2 +-
 openfpga/src/base/vpr_netlist_annotation.cpp  |  68 ++++++++++
 openfpga/src/base/vpr_netlist_annotation.h    |  43 ++++++
 openfpga/test_script/s298.openfpga            |   2 +-
 6 files changed, 223 insertions(+), 19 deletions(-)
 create mode 100644 openfpga/src/base/vpr_netlist_annotation.cpp
 create mode 100644 openfpga/src/base/vpr_netlist_annotation.h

diff --git a/openfpga/src/base/check_netlist_naming_conflict.cpp b/openfpga/src/base/check_netlist_naming_conflict.cpp
index 58980687f..57056712a 100644
--- a/openfpga/src/base/check_netlist_naming_conflict.cpp
+++ b/openfpga/src/base/check_netlist_naming_conflict.cpp
@@ -21,18 +21,47 @@ namespace openfpga {
 /********************************************************************
  * This function aims to check if the name contains any of the 
  * sensitive characters in the list
+ * Return a string of sensitive characters which are contained
+ * in the name
  *******************************************************************/
 static 
-bool name_contain_sensitive_chars(const std::string& name, 
-                                  const std::string& sensitive_chars) {
+std::string name_contain_sensitive_chars(const std::string& name, 
+                                         const std::string& sensitive_chars) {
+  std::string violation;
+
   for (const char& sensitive_char : sensitive_chars) {
     /* Return true since we find a characters */
     if (std::string::npos != name.find(sensitive_char)) {
-      return true;
+      violation.push_back(sensitive_char);
     }
   }
 
-  return false;
+  return violation;
+}
+
+/********************************************************************
+ * This function aims to fix up a name that contains any of the 
+ * sensitive characters in the list
+ * Return a string the fixed name
+ *******************************************************************/
+static 
+std::string fix_name_contain_sensitive_chars(const std::string& name, 
+                                             const std::string& sensitive_chars,
+                                             const std::string& fix_chars) {
+  std::string fixed_name = name;
+
+  VTR_ASSERT(sensitive_chars.length() == fix_chars.length());
+
+  for (size_t ichar = 0; ichar < sensitive_chars.length(); ++ichar) {
+    /* Keep fixing the characters until we cannot find anymore */
+    std::string::size_type pos = 0u;
+    while (std::string::npos != (pos = fixed_name.find(sensitive_chars[ichar], pos))) {
+      fixed_name.replace(pos, 1, std::string(1, fix_chars[ichar]));
+      pos += 1;
+    }
+  }
+
+  return fixed_name;
 }
 
 /********************************************************************
@@ -44,16 +73,17 @@ bool name_contain_sensitive_chars(const std::string& name,
  *   any sensitive character
  *******************************************************************/
 static 
-void detect_netlist_naming_conflict(const AtomNetlist& atom_netlist,
+size_t detect_netlist_naming_conflict(const AtomNetlist& atom_netlist,
                                     const std::string& sensitive_chars) {
   size_t num_conflicts = 0;
 
   /* Walk through blocks in the netlist */
   for (const auto& block : atom_netlist.blocks()) {
     const std::string& block_name = atom_netlist.block_name(block);
-    if (true == name_contain_sensitive_chars(block_name, sensitive_chars)) {
-      VTR_LOG("Block '%s' violates the syntax requirement by OpenFPGA!\n",
-              block_name.c_str());
+    const std::string& violation = name_contain_sensitive_chars(block_name, sensitive_chars);
+    if (false == violation.empty()) {
+      VTR_LOG("Block '%s' contains illegal characters '%s'\n",
+              block_name.c_str(), violation.c_str());
       num_conflicts++;
     }
   }
@@ -61,19 +91,62 @@ void detect_netlist_naming_conflict(const AtomNetlist& atom_netlist,
   /* Walk through nets in the netlist */
   for (const auto& net : atom_netlist.nets()) {
     const std::string& net_name = atom_netlist.net_name(net);
-    if (true == name_contain_sensitive_chars(net_name, sensitive_chars)) {
-      VTR_LOG("Net '%s' violates the syntax requirement by OpenFPGA!\n",
-              net_name.c_str());
+    const std::string& violation = name_contain_sensitive_chars(net_name, sensitive_chars);
+    if (false == violation.empty()) {
+      VTR_LOG("Net '%s' contains illegal characters '%s'\n",
+              net_name.c_str(), violation.c_str());
       num_conflicts++;
     }
   }
 
-  if (0 < num_conflicts) {
-    VTR_LOG("Found %ld naming conflicts in the netlist. Please correct so as to use any fabric generators.\n",
-            num_conflicts);
-  }
+  return num_conflicts;
 } 
 
+/********************************************************************
+ * Correct and report any naming conflict by checking a list of 
+ * sensitive characters
+ * - Iterate over all the blocks and correct any block name that contains 
+ *   any sensitive character
+ * - Iterate over all the nets and correct any net name that contains
+ *   any sensitive character
+ *******************************************************************/
+static 
+void correct_netlist_naming_conflict(const AtomNetlist& atom_netlist,
+                                     const std::string& sensitive_chars,
+                                     const std::string& fix_chars,
+                                     VprNetlistAnnotation& vpr_netlist_annotation) {
+  size_t num_fixes = 0;
+
+  /* Walk through blocks in the netlist */
+  for (const auto& block : atom_netlist.blocks()) {
+    const std::string& block_name = atom_netlist.block_name(block);
+    const std::string& violation = name_contain_sensitive_chars(block_name, sensitive_chars);
+
+    if (false == violation.empty()) {
+      /* Apply fix-up here */
+      vpr_netlist_annotation.rename_block(block, fix_name_contain_sensitive_chars(block_name, sensitive_chars, fix_chars)); 
+      num_fixes++;
+    }
+  }
+
+  /* Walk through nets in the netlist */
+  for (const auto& net : atom_netlist.nets()) {
+    const std::string& net_name = atom_netlist.net_name(net);
+    const std::string& violation = name_contain_sensitive_chars(net_name, sensitive_chars);
+    if (false == violation.empty()) {
+      /* Apply fix-up here */
+      vpr_netlist_annotation.rename_net(net, fix_name_contain_sensitive_chars(net_name, sensitive_chars, fix_chars)); 
+      num_fixes++;
+    }
+  }
+
+  if (0 < num_fixes) {
+    VTR_LOG("Fixed %ld naming conflicts in the netlist.\n",
+            num_fixes);
+  }
+
+}
+
 /********************************************************************
  * Top-level function to detect and correct any naming
  * in the users' BLIF netlist that violates the syntax of OpenFPGA
@@ -81,11 +154,26 @@ void detect_netlist_naming_conflict(const AtomNetlist& atom_netlist,
  *******************************************************************/
 void check_netlist_naming_conflict(OpenfpgaContext& openfpga_context,
                                    const Command& cmd, const CommandContext& cmd_context) {
+  /* By default, we replace all the illegal characters with '_' */
   const std::string& sensitive_chars(".,:;\'\"+-<>()[]{}!@#$%^&*~`?/");
+  const std::string&       fix_chars("____________________________");
+
+  CommandOptionId opt_fix = cmd.option("fix");
 
   /* Do the main job first: detect any naming in the BLIF netlist that violates the syntax */
-  detect_netlist_naming_conflict(g_vpr_ctx.atom().nlist, sensitive_chars); 
-  
+  size_t num_conflicts = detect_netlist_naming_conflict(g_vpr_ctx.atom().nlist, sensitive_chars); 
+  VTR_LOGV_ERROR((0 < num_conflicts && (false == cmd_context.option_enable(cmd, opt_fix))),
+                "Found %ld naming conflicts in the netlist. Please correct so as to use any fabric generators.\n",
+                num_conflicts);
+  VTR_LOGV(0 == num_conflicts, 
+          "Check naming conflicts in the netlist passed.\n");
+
+
+  /* If the auto correction is enabled, we apply a fix */
+  if (true == cmd_context.option_enable(cmd, opt_fix)) {
+    correct_netlist_naming_conflict(g_vpr_ctx.atom().nlist, sensitive_chars,
+                                    fix_chars, openfpga_context.mutable_vpr_netlist_annotation());
+  } 
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_context.h b/openfpga/src/base/openfpga_context.h
index 185a08c5c..cac5877d5 100644
--- a/openfpga/src/base/openfpga_context.h
+++ b/openfpga/src/base/openfpga_context.h
@@ -3,6 +3,7 @@
 
 #include "vpr_context.h"
 #include "openfpga_arch.h"
+#include "vpr_netlist_annotation.h"
 #include "vpr_pb_type_annotation.h"
 
 /********************************************************************
@@ -36,14 +37,18 @@ class OpenfpgaContext : public Context  {
   public:  /* Public accessors */
     const openfpga::Arch& arch() const { return arch_; }
     const openfpga::VprPbTypeAnnotation& vpr_pb_type_annotation() const { return vpr_pb_type_annotation_; }
+    const openfpga::VprNetlistAnnotation& vpr_netlist_annotation() const { return vpr_netlist_annotation_; }
   public:  /* Public mutators */
     openfpga::Arch& mutable_arch() { return arch_; }
     openfpga::VprPbTypeAnnotation& mutable_vpr_pb_type_annotation() { return vpr_pb_type_annotation_; }
+    openfpga::VprNetlistAnnotation& mutable_vpr_netlist_annotation() { return vpr_netlist_annotation_; }
   private: /* Internal data */
     /* Data structure to store information from read_openfpga_arch library */
     openfpga::Arch arch_;
     /* Annotation to pb_type of VPR */
     openfpga::VprPbTypeAnnotation vpr_pb_type_annotation_;
+    /* Naming fix to netlist */
+    openfpga::VprNetlistAnnotation vpr_netlist_annotation_;
 };
 
 #endif
diff --git a/openfpga/src/base/openfpga_setup_command.cpp b/openfpga/src/base/openfpga_setup_command.cpp
index ba7ad45b6..9a3eee970 100644
--- a/openfpga/src/base/openfpga_setup_command.cpp
+++ b/openfpga/src/base/openfpga_setup_command.cpp
@@ -68,7 +68,7 @@ void add_openfpga_setup_commands(openfpga::Shell<OpenfpgaContext>& shell) {
    */ 
   Command shell_cmd_check_netlist_naming_conflict("check_netlist_naming_conflict");
   /* Add an option '--correction' */
-  shell_cmd_check_netlist_naming_conflict.add_option("correction", false, "Apply correction to any conflicts found");
+  shell_cmd_check_netlist_naming_conflict.add_option("fix", false, "Apply correction to any conflicts found");
   /* Add an option '--report' */
   CommandOptionId check_netlist_opt_rpt = shell_cmd_check_netlist_naming_conflict.add_option("report", false, "Output a report file about what any correction applied");
   shell_cmd_check_netlist_naming_conflict.set_option_require_value(check_netlist_opt_rpt, openfpga::OPT_STRING);
diff --git a/openfpga/src/base/vpr_netlist_annotation.cpp b/openfpga/src/base/vpr_netlist_annotation.cpp
new file mode 100644
index 000000000..0d9d5443d
--- /dev/null
+++ b/openfpga/src/base/vpr_netlist_annotation.cpp
@@ -0,0 +1,68 @@
+/************************************************************************
+ * Member functions for class VprNetlistAnnotation
+ ***********************************************************************/
+#include "vtr_log.h"
+#include "vtr_assert.h"
+#include "vpr_netlist_annotation.h"
+
+/* namespace openfpga begins */
+namespace openfpga {
+
+/************************************************************************
+ * Constructors
+ ***********************************************************************/
+VprNetlistAnnotation::VprNetlistAnnotation() {
+  return;
+}
+
+/************************************************************************
+ * Public accessors
+ ***********************************************************************/
+bool VprNetlistAnnotation::is_block_renamed(const AtomBlockId& block) const {
+  /* Ensure that the pb_type is in the list */
+  std::map<AtomBlockId, std::string>::const_iterator it = block_names_.find(block);
+  return it != block_names_.end();
+}
+
+std::string VprNetlistAnnotation::block_name(const AtomBlockId& block) const {
+  VTR_ASSERT(true == is_block_renamed(block));
+  return block_names_.at(block);
+}
+
+bool VprNetlistAnnotation::is_net_renamed(const AtomNetId& net) const {
+  /* Ensure that the pb_type is in the list */
+  std::map<AtomNetId, std::string>::const_iterator it = net_names_.find(net);
+  return it != net_names_.end();
+}
+
+std::string VprNetlistAnnotation::net_name(const AtomNetId& net) const {
+  VTR_ASSERT(true == is_net_renamed(net));
+  return net_names_.at(net);
+}
+
+/************************************************************************
+ * Public mutators
+ ***********************************************************************/
+void VprNetlistAnnotation::rename_block(const AtomBlockId& block, const std::string& name) {
+  /* Warn any override attempt */
+  std::map<AtomBlockId, std::string>::const_iterator it = block_names_.find(block);
+  if (it != block_names_.end()) {
+    VTR_LOG_WARN("Override the block with name '%s' in netlist annotation!\n",
+                 name.c_str());
+  }
+
+  block_names_[block] = name;
+}
+
+void VprNetlistAnnotation::rename_net(const AtomNetId& net, const std::string& name) {
+  /* Warn any override attempt */
+  std::map<AtomNetId, std::string>::const_iterator it = net_names_.find(net);
+  if (it != net_names_.end()) {
+    VTR_LOG_WARN("Override the net with name '%s' in netlist annotation!\n",
+                 name.c_str());
+  }
+
+  net_names_[net] = name;
+}
+
+} /* End namespace openfpga*/
diff --git a/openfpga/src/base/vpr_netlist_annotation.h b/openfpga/src/base/vpr_netlist_annotation.h
new file mode 100644
index 000000000..3b8bbd16f
--- /dev/null
+++ b/openfpga/src/base/vpr_netlist_annotation.h
@@ -0,0 +1,43 @@
+#ifndef VPR_NETLIST_ANNOTATION_H
+#define VPR_NETLIST_ANNOTATION_H
+
+/********************************************************************
+ * Include header files required by the data structure definition
+ *******************************************************************/
+#include <map> 
+
+/* Header from vpr library */
+#include "atom_netlist.h"
+
+/* Begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * This is the critical data structure to link the pb_type in VPR
+ * to openfpga annotations
+ * With a given pb_type pointer, it aims to identify:
+ * 1. if the pb_type is a physical pb_type or a operating pb_type
+ * 2. what is the circuit model id linked to a physical pb_type
+ * 3. what is the physical pb_type for an operating pb_type
+ * 4. what is the mode pointer that represents the physical mode for a pb_type
+ *******************************************************************/
+class VprNetlistAnnotation {
+  public:  /* Constructor */
+    VprNetlistAnnotation();
+  public:  /* Public accessors */
+    bool is_block_renamed(const AtomBlockId& block) const;
+    std::string block_name(const AtomBlockId& block) const;
+    bool is_net_renamed(const AtomNetId& net) const;
+    std::string net_name(const AtomNetId& net) const;
+  public:  /* Public mutators */
+    void rename_block(const AtomBlockId& block, const std::string& name);
+    void rename_net(const AtomNetId& net, const std::string& name);
+  private: /* Internal data */
+    /* Pair a regular pb_type to its physical pb_type */
+    std::map<AtomBlockId, std::string> block_names_;
+    std::map<AtomNetId, std::string> net_names_;
+};
+
+} /* End namespace openfpga*/
+
+#endif
diff --git a/openfpga/test_script/s298.openfpga b/openfpga/test_script/s298.openfpga
index 08e4d9ce3..cafc16074 100644
--- a/openfpga/test_script/s298.openfpga
+++ b/openfpga/test_script/s298.openfpga
@@ -8,7 +8,7 @@ read_openfpga_arch -f ./test_openfpga_arch/k6_N10_40nm_openfpga.xml
 link_openfpga_arch
 
 # Check and correct any naming conflicts in the BLIF netlist
-check_netlist_naming_conflict --correction --report ./netlist_renaming.rpt
+check_netlist_naming_conflict --fix --report ./netlist_renaming.rpt
 
 # Finish and exit OpenFPGA
 exit

From 87f1ca1151ebbb1216567f761f09eafd8b11acb1 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 29 Jan 2020 18:56:47 -0700
Subject: [PATCH 049/645] add naming fix-up report generation

---
 .../src/write_xml_openfpga_arch.cpp           |  3 +
 .../base/check_netlist_naming_conflict.cpp    | 99 ++++++++++++++++---
 2 files changed, 89 insertions(+), 13 deletions(-)

diff --git a/libopenfpga/libarchopenfpga/src/write_xml_openfpga_arch.cpp b/libopenfpga/libarchopenfpga/src/write_xml_openfpga_arch.cpp
index b71853156..eb999dcd1 100644
--- a/libopenfpga/libarchopenfpga/src/write_xml_openfpga_arch.cpp
+++ b/libopenfpga/libarchopenfpga/src/write_xml_openfpga_arch.cpp
@@ -66,4 +66,7 @@ void write_xml_openfpga_arch(const char* fname,
 
   /* Write the simulation */
   write_xml_simulation_setting(fp, fname, openfpga_arch.sim_setting);
+
+  /* Close the file stream */
+  fp.close();
 }
diff --git a/openfpga/src/base/check_netlist_naming_conflict.cpp b/openfpga/src/base/check_netlist_naming_conflict.cpp
index 57056712a..c3fc50d0b 100644
--- a/openfpga/src/base/check_netlist_naming_conflict.cpp
+++ b/openfpga/src/base/check_netlist_naming_conflict.cpp
@@ -4,12 +4,19 @@
  * fabric generator, i.e., Verilog generator and SPICE generator
  *******************************************************************/
 #include <string>
+#include <fstream>
 
 /* Headers from vtrutil library */
 #include "vtr_time.h"
 #include "vtr_assert.h"
 #include "vtr_log.h"
 
+/* Headers from archopenfpga library */
+#include "write_xml_utils.h" 
+
+/* Headers from openfpgautil library */
+#include "openfpga_digest.h"
+
 #include "check_netlist_naming_conflict.h"
 
 /* Include global variables of VPR */
@@ -111,10 +118,10 @@ size_t detect_netlist_naming_conflict(const AtomNetlist& atom_netlist,
  *   any sensitive character
  *******************************************************************/
 static 
-void correct_netlist_naming_conflict(const AtomNetlist& atom_netlist,
-                                     const std::string& sensitive_chars,
-                                     const std::string& fix_chars,
-                                     VprNetlistAnnotation& vpr_netlist_annotation) {
+void fix_netlist_naming_conflict(const AtomNetlist& atom_netlist,
+                                 const std::string& sensitive_chars,
+                                 const std::string& fix_chars,
+                                 VprNetlistAnnotation& vpr_netlist_annotation) {
   size_t num_fixes = 0;
 
   /* Walk through blocks in the netlist */
@@ -144,7 +151,62 @@ void correct_netlist_naming_conflict(const AtomNetlist& atom_netlist,
     VTR_LOG("Fixed %ld naming conflicts in the netlist.\n",
             num_fixes);
   }
+}
 
+/********************************************************************
+ * Report all the fix-up in the naming of netlist components,
+ * i.e., blocks, nets
+ *******************************************************************/
+static 
+void print_netlist_naming_fix_report(const std::string& fname,
+                                     const AtomNetlist& atom_netlist,
+                                     const VprNetlistAnnotation& vpr_netlist_annotation) {
+  /* Create a file handler */
+  std::fstream fp;
+  /* Open the file stream */
+  fp.open(fname, std::fstream::out | std::fstream::trunc);
+
+  /* Validate the file stream */
+  openfpga::check_file_stream(fname.c_str(), fp);
+
+  fp << "<!-- Netlist naming fix-up report --> " << "\n";
+  fp << "<netlist>" << "\n";
+
+  fp << "\t" << "<blocks>" << "\n";
+  
+  for (const auto& block : atom_netlist.blocks()) {
+    const std::string& block_name = atom_netlist.block_name(block);
+    if (false == vpr_netlist_annotation.is_block_renamed(block)) {
+      continue;
+    }
+    fp << "\t\t" << "<block";
+    write_xml_attribute(fp, "previous", block_name.c_str());
+    write_xml_attribute(fp, "current", vpr_netlist_annotation.block_name(block).c_str());
+    fp << "/>" << "\n";
+  }
+
+  fp << "\t" << "</blocks>" << "\n";
+
+  fp << "\t" << "<nets>" << "\n";
+  
+  for (const auto& net : atom_netlist.nets()) {
+    const std::string& net_name = atom_netlist.net_name(net);
+    if (false == vpr_netlist_annotation.is_net_renamed(net)) {
+      continue;
+    }
+    fp << "\t\t" << "<net";
+    write_xml_attribute(fp, "previous", net_name.c_str());
+    write_xml_attribute(fp, "current", vpr_netlist_annotation.net_name(net).c_str());
+    fp << "/>" << "\n";
+  }
+
+  fp << "\t" << "</nets>" << "\n";
+
+
+  fp << "</netlist>" << "\n";
+
+  /* Close the file stream */
+  fp.close();
 }
 
 /********************************************************************
@@ -154,6 +216,8 @@ void correct_netlist_naming_conflict(const AtomNetlist& atom_netlist,
  *******************************************************************/
 void check_netlist_naming_conflict(OpenfpgaContext& openfpga_context,
                                    const Command& cmd, const CommandContext& cmd_context) {
+  vtr::ScopedStartFinishTimer timer("Check naming violations of netlist blocks and nets");
+
   /* By default, we replace all the illegal characters with '_' */
   const std::string& sensitive_chars(".,:;\'\"+-<>()[]{}!@#$%^&*~`?/");
   const std::string&       fix_chars("____________________________");
@@ -161,18 +225,27 @@ void check_netlist_naming_conflict(OpenfpgaContext& openfpga_context,
   CommandOptionId opt_fix = cmd.option("fix");
 
   /* Do the main job first: detect any naming in the BLIF netlist that violates the syntax */
-  size_t num_conflicts = detect_netlist_naming_conflict(g_vpr_ctx.atom().nlist, sensitive_chars); 
-  VTR_LOGV_ERROR((0 < num_conflicts && (false == cmd_context.option_enable(cmd, opt_fix))),
-                "Found %ld naming conflicts in the netlist. Please correct so as to use any fabric generators.\n",
-                num_conflicts);
-  VTR_LOGV(0 == num_conflicts, 
-          "Check naming conflicts in the netlist passed.\n");
-
+  if (false == cmd_context.option_enable(cmd, opt_fix)) {
+    size_t num_conflicts = detect_netlist_naming_conflict(g_vpr_ctx.atom().nlist, sensitive_chars); 
+    VTR_LOGV_ERROR((0 < num_conflicts && (false == cmd_context.option_enable(cmd, opt_fix))),
+                  "Found %ld naming conflicts in the netlist. Please correct so as to use any fabric generators.\n",
+                  num_conflicts);
+    VTR_LOGV(0 == num_conflicts, 
+             "Check naming conflicts in the netlist passed.\n");
+    return;
+  }
 
   /* If the auto correction is enabled, we apply a fix */
   if (true == cmd_context.option_enable(cmd, opt_fix)) {
-    correct_netlist_naming_conflict(g_vpr_ctx.atom().nlist, sensitive_chars,
-                                    fix_chars, openfpga_context.mutable_vpr_netlist_annotation());
+    fix_netlist_naming_conflict(g_vpr_ctx.atom().nlist, sensitive_chars,
+                                fix_chars, openfpga_context.mutable_vpr_netlist_annotation());
+
+    CommandOptionId opt_report = cmd.option("report");
+    if (true == cmd_context.option_enable(cmd, opt_report)) {
+      print_netlist_naming_fix_report(cmd_context.option_value(cmd, opt_report),
+                                      g_vpr_ctx.atom().nlist, 
+                                      openfpga_context.vpr_netlist_annotation());
+    }
   } 
 } 
 

From f28ca3ffd0c327f2fa92a08b28d443cbb285e47d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 29 Jan 2020 18:58:57 -0700
Subject: [PATCH 050/645] add more echo to log

---
 openfpga/src/base/check_netlist_naming_conflict.cpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/openfpga/src/base/check_netlist_naming_conflict.cpp b/openfpga/src/base/check_netlist_naming_conflict.cpp
index c3fc50d0b..3470c9f0a 100644
--- a/openfpga/src/base/check_netlist_naming_conflict.cpp
+++ b/openfpga/src/base/check_netlist_naming_conflict.cpp
@@ -202,7 +202,6 @@ void print_netlist_naming_fix_report(const std::string& fname,
 
   fp << "\t" << "</nets>" << "\n";
 
-
   fp << "</netlist>" << "\n";
 
   /* Close the file stream */
@@ -245,6 +244,8 @@ void check_netlist_naming_conflict(OpenfpgaContext& openfpga_context,
       print_netlist_naming_fix_report(cmd_context.option_value(cmd, opt_report),
                                       g_vpr_ctx.atom().nlist, 
                                       openfpga_context.vpr_netlist_annotation());
+      VTR_LOG("Naming fix-up report is generated to file '%s'\n",
+              cmd_context.option_value(cmd, opt_report).c_str());
     }
   } 
 } 

From 568ed120c2a6784f4429eec40b30491ab50ad4af Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 29 Jan 2020 21:53:56 -0700
Subject: [PATCH 051/645] change report naming fix-up to be XML format

---
 openfpga/test_script/s298.openfpga | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/openfpga/test_script/s298.openfpga b/openfpga/test_script/s298.openfpga
index cafc16074..216f6d8c4 100644
--- a/openfpga/test_script/s298.openfpga
+++ b/openfpga/test_script/s298.openfpga
@@ -8,7 +8,7 @@ read_openfpga_arch -f ./test_openfpga_arch/k6_N10_40nm_openfpga.xml
 link_openfpga_arch
 
 # Check and correct any naming conflicts in the BLIF netlist
-check_netlist_naming_conflict --fix --report ./netlist_renaming.rpt
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
 
 # Finish and exit OpenFPGA
 exit

From e48ab8cb44a8964acde6866b8e44788db8bdc212 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 30 Jan 2020 13:37:41 -0700
Subject: [PATCH 052/645] move annotation source files to a separated folder

---
 openfpga/src/{base => annotation}/annotate_pb_graph.cpp           | 0
 openfpga/src/{base => annotation}/annotate_pb_graph.h             | 0
 openfpga/src/{base => annotation}/annotate_pb_types.cpp           | 0
 openfpga/src/{base => annotation}/annotate_pb_types.h             | 0
 .../src/{base => annotation}/check_netlist_naming_conflict.cpp    | 0
 openfpga/src/{base => annotation}/check_netlist_naming_conflict.h | 0
 openfpga/src/{base => annotation}/check_pb_type_annotation.cpp    | 0
 openfpga/src/{base => annotation}/check_pb_type_annotation.h      | 0
 openfpga/src/{base => annotation}/vpr_netlist_annotation.cpp      | 0
 openfpga/src/{base => annotation}/vpr_netlist_annotation.h        | 0
 openfpga/src/{base => annotation}/vpr_pb_type_annotation.cpp      | 0
 openfpga/src/{base => annotation}/vpr_pb_type_annotation.h        | 0
 12 files changed, 0 insertions(+), 0 deletions(-)
 rename openfpga/src/{base => annotation}/annotate_pb_graph.cpp (100%)
 rename openfpga/src/{base => annotation}/annotate_pb_graph.h (100%)
 rename openfpga/src/{base => annotation}/annotate_pb_types.cpp (100%)
 rename openfpga/src/{base => annotation}/annotate_pb_types.h (100%)
 rename openfpga/src/{base => annotation}/check_netlist_naming_conflict.cpp (100%)
 rename openfpga/src/{base => annotation}/check_netlist_naming_conflict.h (100%)
 rename openfpga/src/{base => annotation}/check_pb_type_annotation.cpp (100%)
 rename openfpga/src/{base => annotation}/check_pb_type_annotation.h (100%)
 rename openfpga/src/{base => annotation}/vpr_netlist_annotation.cpp (100%)
 rename openfpga/src/{base => annotation}/vpr_netlist_annotation.h (100%)
 rename openfpga/src/{base => annotation}/vpr_pb_type_annotation.cpp (100%)
 rename openfpga/src/{base => annotation}/vpr_pb_type_annotation.h (100%)

diff --git a/openfpga/src/base/annotate_pb_graph.cpp b/openfpga/src/annotation/annotate_pb_graph.cpp
similarity index 100%
rename from openfpga/src/base/annotate_pb_graph.cpp
rename to openfpga/src/annotation/annotate_pb_graph.cpp
diff --git a/openfpga/src/base/annotate_pb_graph.h b/openfpga/src/annotation/annotate_pb_graph.h
similarity index 100%
rename from openfpga/src/base/annotate_pb_graph.h
rename to openfpga/src/annotation/annotate_pb_graph.h
diff --git a/openfpga/src/base/annotate_pb_types.cpp b/openfpga/src/annotation/annotate_pb_types.cpp
similarity index 100%
rename from openfpga/src/base/annotate_pb_types.cpp
rename to openfpga/src/annotation/annotate_pb_types.cpp
diff --git a/openfpga/src/base/annotate_pb_types.h b/openfpga/src/annotation/annotate_pb_types.h
similarity index 100%
rename from openfpga/src/base/annotate_pb_types.h
rename to openfpga/src/annotation/annotate_pb_types.h
diff --git a/openfpga/src/base/check_netlist_naming_conflict.cpp b/openfpga/src/annotation/check_netlist_naming_conflict.cpp
similarity index 100%
rename from openfpga/src/base/check_netlist_naming_conflict.cpp
rename to openfpga/src/annotation/check_netlist_naming_conflict.cpp
diff --git a/openfpga/src/base/check_netlist_naming_conflict.h b/openfpga/src/annotation/check_netlist_naming_conflict.h
similarity index 100%
rename from openfpga/src/base/check_netlist_naming_conflict.h
rename to openfpga/src/annotation/check_netlist_naming_conflict.h
diff --git a/openfpga/src/base/check_pb_type_annotation.cpp b/openfpga/src/annotation/check_pb_type_annotation.cpp
similarity index 100%
rename from openfpga/src/base/check_pb_type_annotation.cpp
rename to openfpga/src/annotation/check_pb_type_annotation.cpp
diff --git a/openfpga/src/base/check_pb_type_annotation.h b/openfpga/src/annotation/check_pb_type_annotation.h
similarity index 100%
rename from openfpga/src/base/check_pb_type_annotation.h
rename to openfpga/src/annotation/check_pb_type_annotation.h
diff --git a/openfpga/src/base/vpr_netlist_annotation.cpp b/openfpga/src/annotation/vpr_netlist_annotation.cpp
similarity index 100%
rename from openfpga/src/base/vpr_netlist_annotation.cpp
rename to openfpga/src/annotation/vpr_netlist_annotation.cpp
diff --git a/openfpga/src/base/vpr_netlist_annotation.h b/openfpga/src/annotation/vpr_netlist_annotation.h
similarity index 100%
rename from openfpga/src/base/vpr_netlist_annotation.h
rename to openfpga/src/annotation/vpr_netlist_annotation.h
diff --git a/openfpga/src/base/vpr_pb_type_annotation.cpp b/openfpga/src/annotation/vpr_pb_type_annotation.cpp
similarity index 100%
rename from openfpga/src/base/vpr_pb_type_annotation.cpp
rename to openfpga/src/annotation/vpr_pb_type_annotation.cpp
diff --git a/openfpga/src/base/vpr_pb_type_annotation.h b/openfpga/src/annotation/vpr_pb_type_annotation.h
similarity index 100%
rename from openfpga/src/base/vpr_pb_type_annotation.h
rename to openfpga/src/annotation/vpr_pb_type_annotation.h

From d62c9fe86f85c307ed70576b357300de9c0600a2 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 30 Jan 2020 16:40:13 -0700
Subject: [PATCH 053/645] adding pb_graph_node annotation

---
 openfpga/src/annotation/annotate_pb_graph.cpp | 145 ++++++++++++++++++
 openfpga/src/annotation/annotate_pb_graph.h   |   3 +
 openfpga/src/annotation/annotate_pb_types.cpp |  22 ++-
 .../src/annotation/vpr_pb_type_annotation.cpp | 132 ++++++++++++++++
 .../src/annotation/vpr_pb_type_annotation.h   |  33 ++++
 openfpga/src/base/openfpga_link_arch.cpp      |   8 +-
 6 files changed, 339 insertions(+), 4 deletions(-)

diff --git a/openfpga/src/annotation/annotate_pb_graph.cpp b/openfpga/src/annotation/annotate_pb_graph.cpp
index 82e214067..bb9ab08c8 100644
--- a/openfpga/src/annotation/annotate_pb_graph.cpp
+++ b/openfpga/src/annotation/annotate_pb_graph.cpp
@@ -118,5 +118,150 @@ void annotate_pb_graph_interconnect_physical_type(const DeviceContext& vpr_devic
   }
 }
 
+/********************************************************************
+ * This function will recursively walk through all the pb_graph nodes
+ * starting from a top node.
+ * It aims to give an unique index to each pb_graph node 
+ *
+ * Therefore, the sequence in visiting the nodes is critical
+ * Here, we will follow the strategy where primitive nodes are visited first 
+ *******************************************************************/
+static 
+void rec_build_vpr_primitive_pb_graph_node_unique_index(t_pb_graph_node* pb_graph_node, 
+                                                        VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  /* Go recursive first until we touch the primitive node */
+  if (false == is_primitive_pb_type(pb_graph_node->pb_type)) {
+    for (int imode = 0; imode < pb_graph_node->pb_type->num_modes; ++imode) {
+      for (int ipb = 0; ipb < pb_graph_node->pb_type->modes[imode].num_pb_type_children; ++ipb) {
+        /* Each child may exist multiple times in the hierarchy*/
+        for (int jpb = 0; jpb < pb_graph_node->pb_type->modes[imode].pb_type_children[ipb].num_pb; ++jpb) {
+          rec_build_vpr_primitive_pb_graph_node_unique_index(&(pb_graph_node->child_pb_graph_nodes[imode][ipb][jpb]), 
+                                                             vpr_pb_type_annotation);
+        }
+      }
+    }
+    return;
+  }
+
+  /* Give a unique index to the pb_graph_node */
+  vpr_pb_type_annotation.add_pb_graph_node_unique_index(pb_graph_node);
+}
+
+/********************************************************************
+ * This function aims to assign an unique index to each 
+ * primitive pb_graph_node by following a recursive way in walking
+ * through the pb_graph
+ *
+ * Note: 
+ * - The unique index is different from the placement_index in VPR's 
+ *   pb_graph_node data structure. The placement index is only unique
+ *   for a node under its parent node. If the parent node is duplicated 
+ *   across the graph, the placement index is not unique.
+ *   For example, a CLB contains 10 LEs and each of LE contains 2 LUTs
+ *   Inside each LE, the placement index of the LUTs are 0 and 1 respectively.
+ *   But these indices are not unique in the graph, as there are 20 LUTs in total
+ *******************************************************************/
+static 
+void annotate_primitive_pb_graph_node_unique_index(const DeviceContext& vpr_device_ctx, 
+                                                   VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
+    /* By pass nullptr for pb_graph head */
+    if (nullptr == lb_type.pb_graph_head) {
+      continue;
+    }
+    rec_build_vpr_primitive_pb_graph_node_unique_index(lb_type.pb_graph_head, vpr_pb_type_annotation); 
+  }
+}
+
+/********************************************************************
+ * This function will recursively walk through all the pb_graph nodes
+ * starting from a top node.
+ * It aims to give an unique index to each pb_graph node 
+ *
+ * Therefore, the sequence in visiting the nodes is critical
+ * Here, we will follow the strategy where primitive nodes are visited first 
+ *******************************************************************/
+static 
+void rec_build_vpr_physical_pb_graph_node_annotation(t_pb_graph_node* pb_graph_node, 
+                                                     VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  /* Go recursive first until we touch the primitive node */
+  if (false == is_primitive_pb_type(pb_graph_node->pb_type)) {
+    for (int imode = 0; imode < pb_graph_node->pb_type->num_modes; ++imode) {
+      for (int ipb = 0; ipb < pb_graph_node->pb_type->modes[imode].num_pb_type_children; ++ipb) {
+        /* Each child may exist multiple times in the hierarchy*/
+        for (int jpb = 0; jpb < pb_graph_node->pb_type->modes[imode].pb_type_children[ipb].num_pb; ++jpb) {
+          rec_build_vpr_physical_pb_graph_node_annotation(&(pb_graph_node->child_pb_graph_nodes[imode][ipb][jpb]), 
+                                                          vpr_pb_type_annotation);
+        }
+      }
+    }
+    return;
+  }
+
+  /* To bind operating pb_graph_node to their physical pb_graph_node:
+   *  - Get the physical pb_type that this type of pb_graph_node should be mapped to 
+   *  - Calculate the unique index of physical pb_graph_node to which
+   *    this pb_graph_node should be binded
+   *  - Find the physical pb_graph_node with the given index 
+   * To bind pins from operating pb_graph_node to their physical pb_graph_node pins
+   */
+  t_pb_type* physical_pb_type = vpr_pb_type_annotation.physical_pb_type(pb_graph_node->pb_type); 
+  VTR_ASSERT(nullptr != physical_pb_type);
+
+  /* Index inference:
+   * physical_pb_graph_node_unique_index = operating_pb_graph_node_unique_index * factor + offset
+   * where factor and offset are provided by users
+   */
+  PbGraphNodeId physical_pb_graph_node_id = PbGraphNodeId(
+                                            vpr_pb_type_annotation.physical_pb_type_index_factor(pb_graph_node->pb_type)
+                                          * (size_t)vpr_pb_type_annotation.pb_graph_node_unique_index(pb_graph_node)
+                                          + vpr_pb_type_annotation.physical_pb_type_index_offset(pb_graph_node->pb_type)
+                                            );
+  t_pb_graph_node* physical_pb_graph_node = vpr_pb_type_annotation.pb_graph_node(pb_graph_node->pb_type, physical_pb_graph_node_id);
+  VTR_ASSERT(nullptr != physical_pb_graph_node);
+  vpr_pb_type_annotation.add_physical_pb_graph_node(pb_graph_node, physical_pb_graph_node);
+
+  VTR_LOG("Bind operating pb_graph_node '%s' to physical pb_graph_node '%s'\n",
+          pb_graph_node->hierarchical_type_name().c_str(),
+          physical_pb_graph_node->hierarchical_type_name().c_str());
+
+  /* Try to bind each pins under this pb_graph_node to physical_pb_graph_node */
+}
+
+/********************************************************************
+ * Find the physical pb_graph_node for  each primitive pb_graph_node
+ * - Bind operating pb_graph_node to their physical pb_graph_node
+ * - Bind pins from operating pb_graph_node to their physical pb_graph_node pins
+ *******************************************************************/
+static 
+void annotate_physical_pb_graph_node(const DeviceContext& vpr_device_ctx, 
+                                     VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
+    /* By pass nullptr for pb_graph head */
+    if (nullptr == lb_type.pb_graph_head) {
+      continue;
+    }
+    rec_build_vpr_physical_pb_graph_node_annotation(lb_type.pb_graph_head, vpr_pb_type_annotation); 
+  }
+}
+
+/********************************************************************
+ * Top-level function to annotate all the pb_graph nodes and pins
+ * - Give unique index to each primitive node in the same type
+ * - Bind operating pb_graph_node to their physical pb_graph_node
+ * - Bind pins from operating pb_graph_node to their physical pb_graph_node pins
+ *******************************************************************/
+void annotate_pb_graph(const DeviceContext& vpr_device_ctx, 
+                       VprPbTypeAnnotation& vpr_pb_type_annotation) {
+
+  VTR_LOG("Assigning unique indices for primitive pb_graph nodes...");
+  annotate_primitive_pb_graph_node_unique_index(vpr_device_ctx, vpr_pb_type_annotation);
+  VTR_LOG("Done\n");
+
+  VTR_LOG("Binding operating pb_graph nodes/pins to physical pb_graph nodes/pins...\n");
+  annotate_physical_pb_graph_node(vpr_device_ctx, vpr_pb_type_annotation);
+  VTR_LOG("Done\n");
+}
+
 } /* end namespace openfpga */
 
diff --git a/openfpga/src/annotation/annotate_pb_graph.h b/openfpga/src/annotation/annotate_pb_graph.h
index 8749cd28f..e809d3cfa 100644
--- a/openfpga/src/annotation/annotate_pb_graph.h
+++ b/openfpga/src/annotation/annotate_pb_graph.h
@@ -18,6 +18,9 @@ namespace openfpga {
 void annotate_pb_graph_interconnect_physical_type(const DeviceContext& vpr_device_ctx, 
                                                   VprPbTypeAnnotation& vpr_pb_type_annotation);
 
+void annotate_pb_graph(const DeviceContext& vpr_device_ctx, 
+                       VprPbTypeAnnotation& vpr_pb_type_annotation);
+
 } /* end namespace openfpga */
 
 #endif
diff --git a/openfpga/src/annotation/annotate_pb_types.cpp b/openfpga/src/annotation/annotate_pb_types.cpp
index 023154c9b..fb2905637 100644
--- a/openfpga/src/annotation/annotate_pb_types.cpp
+++ b/openfpga/src/annotation/annotate_pb_types.cpp
@@ -223,13 +223,24 @@ bool pair_operating_and_physical_pb_types(t_pb_type* operating_pb_type,
     if (false == expected_physical_pb_port.contained(BasicPort(physical_pb_port->name, physical_pb_port->num_pins))) {
       return false;
     }
-    /* Now, port mapping should succeed, we update the vpr_pb_type_annotation */
+    /* Now, port mapping should succeed, we update the vpr_pb_type_annotation 
+     * - port binding
+     * - port range
+     * - port pin rotate offset
+     */
     vpr_pb_type_annotation.add_physical_pb_port(operating_pb_port, physical_pb_port);
     vpr_pb_type_annotation.add_physical_pb_port_range(operating_pb_port, expected_physical_pb_port);
+    vpr_pb_type_annotation.add_physical_pb_pin_rotate_offset(operating_pb_port, pb_type_annotation.physical_pin_rotate_offset(std::string(operating_pb_port->name)));
   }
 
-  /* Now, pb_type mapping should succeed, we update the vpr_pb_type_annotation */
+  /* Now, pb_type mapping should succeed, we update the vpr_pb_type_annotation
+   *   - pb_type binding
+   *   - physical_pb_type_index_factor
+   *   - physical_pb_type_index_offset
+   */
   vpr_pb_type_annotation.add_physical_pb_type(operating_pb_type, physical_pb_type);
+  vpr_pb_type_annotation.add_physical_pb_type_index_factor(operating_pb_type, pb_type_annotation.physical_pb_type_index_factor());
+  vpr_pb_type_annotation.add_physical_pb_type_index_offset(operating_pb_type, pb_type_annotation.physical_pb_type_index_offset());
 
   return true;
 }
@@ -987,7 +998,12 @@ void annotate_pb_types(const DeviceContext& vpr_device_ctx,
                                                vpr_pb_type_annotation);
   VTR_LOG("Done\n");
 
-  /* Annotate physical pb_types to operating pb_type in the VPR pb_type graph */
+  /* Annotate physical pb_types to operating pb_type in the VPR pb_type graph 
+   * This function will also annotate
+   * - pb_type_index_factor 
+   * - pb_type_index_offset
+   * - physical_pin_rotate_offset
+   */
   VTR_LOG("\n");
   VTR_LOG("Building annotation between operating and physical pb_types...\n");
   build_vpr_physical_pb_type_explicit_annotation(vpr_device_ctx, openfpga_arch,
diff --git a/openfpga/src/annotation/vpr_pb_type_annotation.cpp b/openfpga/src/annotation/vpr_pb_type_annotation.cpp
index 435f46be7..407907e59 100644
--- a/openfpga/src/annotation/vpr_pb_type_annotation.cpp
+++ b/openfpga/src/annotation/vpr_pb_type_annotation.cpp
@@ -1,6 +1,8 @@
 /************************************************************************
  * Member functions for class VprPbTypeAnnotation
  ***********************************************************************/
+#include <algorithm>
+
 #include "vtr_log.h"
 #include "vtr_assert.h"
 #include "vpr_pb_type_annotation.h"
@@ -115,6 +117,84 @@ std::vector<size_t> VprPbTypeAnnotation::pb_type_mode_bits(t_pb_type* pb_type) c
   return pb_type_mode_bits_.at(pb_type);
 }
 
+PbGraphNodeId VprPbTypeAnnotation::pb_graph_node_unique_index(t_pb_graph_node* pb_graph_node) const {
+  /* Ensure that the pb_type is in the list */
+  std::map<t_pb_type*, std::vector<t_pb_graph_node*>>::const_iterator it = pb_graph_node_unique_index_.find(pb_graph_node->pb_type);
+  if (it == pb_graph_node_unique_index_.end()) {
+    /* Invalid pb_type, return a null pointer */
+    return PbGraphNodeId::INVALID();
+  }
+
+  /* Try to find the pb_graph_node in the vector */
+  std::vector<t_pb_graph_node*>::const_iterator it_node = std::find(pb_graph_node_unique_index_.at(pb_graph_node->pb_type).begin(),
+                                                                    pb_graph_node_unique_index_.at(pb_graph_node->pb_type).end(),
+                                                                    pb_graph_node);
+  /* If it exists, return the index
+   * Otherwise, return an invalid id
+   */
+  if (it_node == pb_graph_node_unique_index_.at(pb_graph_node->pb_type).end()) {
+    return PbGraphNodeId::INVALID();
+  }
+  return PbGraphNodeId(it_node - pb_graph_node_unique_index_.at(pb_graph_node->pb_type).begin());
+}
+
+t_pb_graph_node* VprPbTypeAnnotation::pb_graph_node(t_pb_type* pb_type, const PbGraphNodeId& unique_index) const {
+  /* Ensure that the pb_type is in the list */
+  std::map<t_pb_type*, std::vector<t_pb_graph_node*>>::const_iterator it = pb_graph_node_unique_index_.find(pb_type);
+  if (it == pb_graph_node_unique_index_.end()) {
+    /* Invalid pb_type, return a null pointer */
+    return nullptr;
+  }
+  /* Check if the unique index is in the range:
+   *  - Out of range: return a null pointer
+   *  - In range: return the pointer
+   */
+  if ((size_t)unique_index > pb_graph_node_unique_index_.at(pb_type).size() - 1) {
+    return nullptr;
+  }
+
+  return pb_graph_node_unique_index_.at(pb_type)[size_t(unique_index)];
+}
+
+t_pb_graph_node* VprPbTypeAnnotation::physical_pb_graph_node(t_pb_graph_node* pb_graph_node) const {
+  /* Ensure that the pb_graph_node is in the list */
+  std::map<t_pb_graph_node*, t_pb_graph_node*>::const_iterator it = physical_pb_graph_nodes_.find(pb_graph_node);
+  if (it == physical_pb_graph_nodes_.end()) {
+    return nullptr;
+  }
+  return physical_pb_graph_nodes_.at(pb_graph_node);
+}
+
+int VprPbTypeAnnotation::physical_pb_type_index_factor(t_pb_type* pb_type) const {
+  /* Ensure that the pb_type is in the list */
+  std::map<t_pb_type*, int>::const_iterator it = physical_pb_type_index_factors_.find(pb_type);
+  if (it == physical_pb_type_index_factors_.end()) {
+    /* Default value is 1 */
+    return 1;
+  }
+  return physical_pb_type_index_factors_.at(pb_type);
+}
+
+int VprPbTypeAnnotation::physical_pb_type_index_offset(t_pb_type* pb_type) const {
+  /* Ensure that the pb_type is in the list */
+  std::map<t_pb_type*, int>::const_iterator it = physical_pb_type_index_offsets_.find(pb_type);
+  if (it == physical_pb_type_index_offsets_.end()) {
+    /* Default value is 0 */
+    return 0;
+  }
+  return physical_pb_type_index_offsets_.at(pb_type);
+}
+
+int VprPbTypeAnnotation::physical_pb_pin_rotate_offset(t_port* pb_port) const {
+  /* Ensure that the pb_type is in the list */
+  std::map<t_port*, int>::const_iterator it = physical_pb_pin_rotate_offsets_.find(pb_port);
+  if (it == physical_pb_pin_rotate_offsets_.end()) {
+    /* Default value is 0 */
+    return 0;
+  }
+  return physical_pb_pin_rotate_offsets_.at(pb_port);
+}
+
 /************************************************************************
  * Public mutators
  ***********************************************************************/
@@ -221,4 +301,56 @@ void VprPbTypeAnnotation::add_pb_type_mode_bits(t_pb_type* pb_type, const std::v
   pb_type_mode_bits_[pb_type] = mode_bits;
 }
 
+void VprPbTypeAnnotation::add_pb_graph_node_unique_index(t_pb_graph_node* pb_graph_node) {
+  pb_graph_node_unique_index_[pb_graph_node->pb_type].push_back(pb_graph_node);
+}
+
+void VprPbTypeAnnotation::add_physical_pb_graph_node(t_pb_graph_node* operating_pb_graph_node, 
+                                                     t_pb_graph_node* physical_pb_graph_node) {
+  /* Warn any override attempt */
+  std::map<t_pb_graph_node*, t_pb_graph_node*>::const_iterator it = physical_pb_graph_nodes_.find(operating_pb_graph_node);
+  if (it != physical_pb_graph_nodes_.end()) {
+    VTR_LOG_WARN("Override the annotation between operating pb_graph_node '%s[%d]' and it physical pb_graph_node '%s[%d]'!\n",
+                 operating_pb_graph_node->pb_type->name, 
+                 operating_pb_graph_node->placement_index,
+                 physical_pb_graph_node->pb_type->name, 
+                 physical_pb_graph_node->placement_index);
+  }
+
+  physical_pb_graph_nodes_[operating_pb_graph_node] = physical_pb_graph_node;
+}
+
+void VprPbTypeAnnotation::add_physical_pb_type_index_factor(t_pb_type* pb_type, const int& factor) {
+  /* Warn any override attempt */
+  std::map<t_pb_type*, int>::const_iterator it = physical_pb_type_index_factors_.find(pb_type);
+  if (it != physical_pb_type_index_factors_.end()) {
+    VTR_LOG_WARN("Override the annotation between operating pb_type '%s' and it physical pb_type index factor '%d'!\n",
+                 pb_type->name, factor);
+  }
+
+  physical_pb_type_index_factors_[pb_type] = factor;
+}
+
+void VprPbTypeAnnotation::add_physical_pb_type_index_offset(t_pb_type* pb_type, const int& offset) {
+  /* Warn any override attempt */
+  std::map<t_pb_type*, int>::const_iterator it = physical_pb_type_index_offsets_.find(pb_type);
+  if (it != physical_pb_type_index_offsets_.end()) {
+    VTR_LOG_WARN("Override the annotation between operating pb_type '%s' and it physical pb_type index offset '%d'!\n",
+                 pb_type->name, offset);
+  }
+
+  physical_pb_type_index_offsets_[pb_type] = offset;
+}
+
+void VprPbTypeAnnotation::add_physical_pb_pin_rotate_offset(t_port* pb_port, const int& offset) {
+  /* Warn any override attempt */
+  std::map<t_port*, int>::const_iterator it = physical_pb_pin_rotate_offsets_.find(pb_port);
+  if (it != physical_pb_pin_rotate_offsets_.end()) {
+    VTR_LOG_WARN("Override the annotation between operating pb_port '%s' and it physical pb_port pin rotate offset '%d'!\n",
+                 pb_port->name, offset);
+  }
+
+  physical_pb_pin_rotate_offsets_[pb_port] = offset;
+}
+
 } /* End namespace openfpga*/
diff --git a/openfpga/src/annotation/vpr_pb_type_annotation.h b/openfpga/src/annotation/vpr_pb_type_annotation.h
index 24535ee4a..bcdff9e3e 100644
--- a/openfpga/src/annotation/vpr_pb_type_annotation.h
+++ b/openfpga/src/annotation/vpr_pb_type_annotation.h
@@ -6,6 +6,9 @@
  *******************************************************************/
 #include <map> 
 
+/* Header from vtrutil library */
+#include "vtr_strong_id.h"
+
 /* Header from archfpga library */
 #include "physical_types.h"
 
@@ -16,6 +19,11 @@
 /* Begin namespace openfpga */
 namespace openfpga {
 
+/* Unique index for pb_graph node */
+struct pb_graph_node_id_tag;
+
+typedef vtr::StrongId<pb_graph_node_id_tag> PbGraphNodeId;
+
 /********************************************************************
  * This is the critical data structure to link the pb_type in VPR
  * to openfpga annotations
@@ -39,6 +47,14 @@ class VprPbTypeAnnotation {
     e_interconnect interconnect_physical_type(t_interconnect* pb_interconnect) const;
     CircuitPortId pb_circuit_port(t_port* pb_port) const;
     std::vector<size_t> pb_type_mode_bits(t_pb_type* pb_type) const;
+    /* Get the unique index of a pb_graph_node */
+    PbGraphNodeId pb_graph_node_unique_index(t_pb_graph_node* pb_graph_node) const;
+    /* Get the pointer to a pb_graph node using an unique index */
+    t_pb_graph_node* pb_graph_node(t_pb_type* pb_type, const PbGraphNodeId& unique_index) const;
+    t_pb_graph_node* physical_pb_graph_node(t_pb_graph_node* pb_graph_node) const;
+    int physical_pb_type_index_factor(t_pb_type* pb_type) const;
+    int physical_pb_type_index_offset(t_pb_type* pb_type) const;
+    int physical_pb_pin_rotate_offset(t_port* pb_port) const;
   public:  /* Public mutators */
     void add_pb_type_physical_mode(t_pb_type* pb_type, t_mode* physical_mode);
     void add_physical_pb_type(t_pb_type* operating_pb_type, t_pb_type* physical_pb_type);
@@ -49,9 +65,17 @@ class VprPbTypeAnnotation {
     void add_interconnect_physical_type(t_interconnect* pb_interconnect, const e_interconnect& physical_type);
     void add_pb_circuit_port(t_port* pb_port, const CircuitPortId& circuit_port);
     void add_pb_type_mode_bits(t_pb_type* pb_type, const std::vector<size_t>& mode_bits);
+    void add_pb_graph_node_unique_index(t_pb_graph_node* pb_graph_node);
+    void add_physical_pb_graph_node(t_pb_graph_node* operating_pb_graph_node, 
+                                    t_pb_graph_node* physical_pb_graph_node);
+    void add_physical_pb_type_index_factor(t_pb_type* pb_type, const int& factor);
+    void add_physical_pb_type_index_offset(t_pb_type* pb_type, const int& offset);
+    void add_physical_pb_pin_rotate_offset(t_port* pb_port, const int& offset);
   private: /* Internal data */
     /* Pair a regular pb_type to its physical pb_type */
     std::map<t_pb_type*, t_pb_type*> physical_pb_types_;
+    std::map<t_pb_type*, int> physical_pb_type_index_factors_;
+    std::map<t_pb_type*, int> physical_pb_type_index_offsets_;
 
     /* Pair a physical mode for a pb_type
      * Note:
@@ -91,6 +115,7 @@ class VprPbTypeAnnotation {
      * - the parent of physical pb_port MUST be a physical pb_type
      */
     std::map<t_port*, t_port*> physical_pb_ports_;
+    std::map<t_port*, int> physical_pb_pin_rotate_offsets_;
 
     /* Pair a pb_port to its LSB and MSB of a physical pb_port 
      * Note:
@@ -104,11 +129,19 @@ class VprPbTypeAnnotation {
      */
     std::map<t_port*, CircuitPortId> pb_circuit_ports_;
 
+    /* Pair each pb_graph_node to an unique index in the graph
+     * The unique index if the index in the array of t_pb_graph_node*
+     */ 
+    std::map<t_pb_type*, std::vector<t_pb_graph_node*>> pb_graph_node_unique_index_;
+
     /* Pair a pb_graph_node to a physical pb_graph_node
      * Note:
      * - the pb_type of physical pb_graph_node must be a physical pb_type
      */
     std::map<t_pb_graph_node*, t_pb_graph_node*> physical_pb_graph_nodes_;
+
+    /* Pair a pb_graph_pin to a physical pb_graph_pin */
+    std::map<t_pb_graph_pin*, t_pb_graph_pin*> physical_pb_graph_pins_;
 };
 
 } /* End namespace openfpga*/
diff --git a/openfpga/src/base/openfpga_link_arch.cpp b/openfpga/src/base/openfpga_link_arch.cpp
index a30453d1c..e6762485e 100644
--- a/openfpga/src/base/openfpga_link_arch.cpp
+++ b/openfpga/src/base/openfpga_link_arch.cpp
@@ -39,7 +39,13 @@ void link_arch(OpenfpgaContext& openfpga_context) {
   annotate_pb_types(g_vpr_ctx.device(), openfpga_context.arch(),
                     openfpga_context.mutable_vpr_pb_type_annotation());
 
-  /* Link routing architecture to circuit model */
+  /* Annotate pb_graph_nodes
+   * - Give unique index to each node in the same type
+   * - Bind operating pb_graph_node to their physical pb_graph_node
+   * - Bind pins from operating pb_graph_node to their physical pb_graph_node pins
+   */
+  annotate_pb_graph(g_vpr_ctx.device(),
+                    openfpga_context.mutable_vpr_pb_type_annotation());
 } 
 
 } /* end namespace openfpga */

From 007e1997e63e2a6b0b028a009e1f64f4262dcb15 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 30 Jan 2020 19:40:40 -0700
Subject: [PATCH 054/645] add pb_graph pin annotation

---
 openfpga/src/annotation/annotate_pb_graph.cpp | 167 ++++++++++++++++++
 .../src/annotation/vpr_pb_type_annotation.cpp |  59 +++++++
 .../src/annotation/vpr_pb_type_annotation.h   |  15 ++
 3 files changed, 241 insertions(+)

diff --git a/openfpga/src/annotation/annotate_pb_graph.cpp b/openfpga/src/annotation/annotate_pb_graph.cpp
index bb9ab08c8..fb94bc238 100644
--- a/openfpga/src/annotation/annotate_pb_graph.cpp
+++ b/openfpga/src/annotation/annotate_pb_graph.cpp
@@ -173,6 +173,172 @@ void annotate_primitive_pb_graph_node_unique_index(const DeviceContext& vpr_devi
   }
 }
 
+/********************************************************************
+ * Evaluate if the two pb_graph pins are matched by
+ *  - pb_type port annotation 
+ *  - LSB/MSB and pin offset
+ *******************************************************************/
+static 
+bool try_match_pb_graph_pin(t_pb_graph_pin* operating_pb_graph_pin, 
+                            t_pb_graph_pin* physical_pb_graph_pin,
+                            const VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  /* If the parent ports of the two pins are not paired, fail */
+  if (physical_pb_graph_pin->port != vpr_pb_type_annotation.physical_pb_port(operating_pb_graph_pin->port)) {
+    return false;
+  }
+  /* Check the pin number of physical pb_graph_pin matches the pin number of 
+   * operating pb_graph_pin plus a rotation offset 
+   *                                              operating port         physical port
+   *                      LSB  port_range.lsb()    pin_number              pin_number      MSB
+   *                                 |                  |                     |
+   *    Operating port     |         |                  +------               |
+   *                                 |                        |<----offset--->|
+   *    Physical port      |         +                        +               +
+   *
+   * Note: 
+   *   - accumulated offset is NOT the pin rotate offset specified by users
+   *     It is an aggregation of the offset during pin pairing
+   *     Each time, we manage to pair two pins, the accumulated offset will be incremented
+   *     by the pin rotate offset value
+   *     The accumulated offset will be reset to 0 when it exceeds the msb() of the physical port
+   */
+  int acc_offset = vpr_pb_type_annotation.physical_pb_pin_offset(operating_pb_graph_pin->port);
+  const BasicPort& physical_port_range = vpr_pb_type_annotation.physical_pb_port_range(operating_pb_graph_pin->port);
+  if (physical_pb_graph_pin->pin_number != operating_pb_graph_pin->pin_number
+                                         + (int)physical_port_range.get_lsb() 
+                                         + acc_offset) {
+    return false;
+  }
+
+  /* Reach here, it means all the requirements have been met */
+  return true;
+}
+
+/********************************************************************
+ * Bind a pb_graph_pin from an operating pb_graph_node to 
+ * a pb_graph_pin from a physical pb_graph_node
+ * - the name matching rules are already defined in the vpr_pb_type_annotation
+ *******************************************************************/
+static 
+void annotate_physical_pb_graph_pin(t_pb_graph_pin* operating_pb_graph_pin, 
+                                    t_pb_graph_node* physical_pb_graph_node, 
+                                    VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  /* Iterate over every port and pin of the operating pb_graph_node 
+   * and find the physical pins 
+   */
+  for (int iport = 0; iport < physical_pb_graph_node->num_input_ports; ++iport) {
+    for (int ipin = 0; ipin < physical_pb_graph_node->num_input_pins[iport]; ++ipin) {
+      if (false == try_match_pb_graph_pin(operating_pb_graph_pin, 
+                                          &(physical_pb_graph_node->input_pins[iport][ipin]),
+                                          vpr_pb_type_annotation)) {
+        continue;
+      }
+      /* Reach here, it means the pins are matched by the annotation requirements 
+       * We can pair the pin and return  
+       */
+      vpr_pb_type_annotation.add_physical_pb_graph_pin(operating_pb_graph_pin, &(physical_pb_graph_node->input_pins[iport][ipin]));
+      VTR_LOG("Bind a pb_graph_node '%s[%d]' pin '%s[%d]' to a pb_graph_node '%s[%d]' pin '%s[%d]'!\n",
+              operating_pb_graph_pin->parent_node->pb_type->name,
+              operating_pb_graph_pin->parent_node->placement_index,
+              operating_pb_graph_pin->port->name,
+              operating_pb_graph_pin->pin_number,
+              physical_pb_graph_node->pb_type->name,
+              physical_pb_graph_node->placement_index,
+              physical_pb_graph_node->input_pins[iport][ipin].port->name,
+              physical_pb_graph_node->input_pins[iport][ipin].pin_number);
+      return;
+    }
+  }
+
+  for (int iport = 0; iport < physical_pb_graph_node->num_output_ports; ++iport) {
+    for (int ipin = 0; ipin < physical_pb_graph_node->num_output_pins[iport]; ++ipin) {
+      if (false == try_match_pb_graph_pin(operating_pb_graph_pin, 
+                                          &(physical_pb_graph_node->output_pins[iport][ipin]),
+                                          vpr_pb_type_annotation)) {
+        continue;
+      }
+      /* Reach here, it means the pins are matched by the annotation requirements 
+       * We can pair the pin and return  
+       */
+      vpr_pb_type_annotation.add_physical_pb_graph_pin(operating_pb_graph_pin, &(physical_pb_graph_node->output_pins[iport][ipin]));
+      VTR_LOG("Bind a pb_graph_node '%s[%d]' pin '%s[%d]' to a pb_graph_node '%s[%d]' pin '%s[%d]'!\n",
+              operating_pb_graph_pin->parent_node->pb_type->name,
+              operating_pb_graph_pin->parent_node->placement_index,
+              operating_pb_graph_pin->port->name,
+              operating_pb_graph_pin->pin_number,
+              physical_pb_graph_node->pb_type->name,
+              physical_pb_graph_node->placement_index,
+              physical_pb_graph_node->output_pins[iport][ipin].port->name,
+              physical_pb_graph_node->output_pins[iport][ipin].pin_number);
+      return;
+    }
+  }
+
+  for (int iport = 0; iport < physical_pb_graph_node->num_clock_ports; ++iport) {
+    for (int ipin = 0; ipin < physical_pb_graph_node->num_clock_pins[iport]; ++ipin) {
+      if (false == try_match_pb_graph_pin(operating_pb_graph_pin, 
+                                          &(physical_pb_graph_node->clock_pins[iport][ipin]),
+                                          vpr_pb_type_annotation)) {
+        continue;
+      }
+      /* Reach here, it means the pins are matched by the annotation requirements 
+       * We can pair the pin and return  
+       */
+      vpr_pb_type_annotation.add_physical_pb_graph_pin(operating_pb_graph_pin, &(physical_pb_graph_node->clock_pins[iport][ipin]));
+      VTR_LOG("Bind a pb_graph_node '%s[%d]' pin '%s[%d]' to a pb_graph_node '%s[%d]' pin '%s[%d]'!\n",
+              operating_pb_graph_pin->parent_node->pb_type->name,
+              operating_pb_graph_pin->parent_node->placement_index,
+              operating_pb_graph_pin->port->name,
+              operating_pb_graph_pin->pin_number,
+              physical_pb_graph_node->pb_type->name,
+              physical_pb_graph_node->placement_index,
+              physical_pb_graph_node->clock_pins[iport][ipin].port->name,
+              physical_pb_graph_node->clock_pins[iport][ipin].pin_number);
+      return;
+    }
+  }
+
+  /* If we reach here, it means that pin pairing fails, error out! */
+  VTR_LOG_ERROR("Fail to match a physical pin for '%s' from pb_graph_node '%s'!\n",
+                operating_pb_graph_pin->port->name,
+                physical_pb_graph_node->hierarchical_type_name().c_str());
+}
+
+/********************************************************************
+ * This function will try bind each pin of the operating pb_graph_node
+ * to a pin of the physical pb_graph_node by following the annotation
+ * available in vpr_pb_type_annotation
+ * It will add the pin bindings to the vpr_pb_type_annotation
+ *******************************************************************/
+static 
+void annotate_physical_pb_graph_node_pins(t_pb_graph_node* operating_pb_graph_node, 
+                                          t_pb_graph_node* physical_pb_graph_node, 
+                                          VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  /* Iterate over every port and pin of the operating pb_graph_node 
+   * and find the physical pins 
+   */
+  for (int iport = 0; iport < operating_pb_graph_node->num_input_ports; ++iport) {
+    for (int ipin = 0; ipin < operating_pb_graph_node->num_input_pins[iport]; ++ipin) {
+      annotate_physical_pb_graph_pin(&(operating_pb_graph_node->input_pins[iport][ipin]),
+                                     physical_pb_graph_node, vpr_pb_type_annotation);
+    }
+  }
+
+  for (int iport = 0; iport < operating_pb_graph_node->num_output_ports; ++iport) {
+    for (int ipin = 0; ipin < operating_pb_graph_node->num_output_pins[iport]; ++ipin) {
+      annotate_physical_pb_graph_pin(&(operating_pb_graph_node->output_pins[iport][ipin]),
+                                     physical_pb_graph_node, vpr_pb_type_annotation);
+    }
+  }
+
+  for (int iport = 0; iport < operating_pb_graph_node->num_clock_ports; ++iport) {
+    for (int ipin = 0; ipin < operating_pb_graph_node->num_clock_pins[iport]; ++ipin) {
+      annotate_physical_pb_graph_pin(&(operating_pb_graph_node->clock_pins[iport][ipin]),
+                                     physical_pb_graph_node, vpr_pb_type_annotation);
+    }
+  }
+}
+
 /********************************************************************
  * This function will recursively walk through all the pb_graph nodes
  * starting from a top node.
@@ -226,6 +392,7 @@ void rec_build_vpr_physical_pb_graph_node_annotation(t_pb_graph_node* pb_graph_n
           physical_pb_graph_node->hierarchical_type_name().c_str());
 
   /* Try to bind each pins under this pb_graph_node to physical_pb_graph_node */
+  annotate_physical_pb_graph_node_pins(pb_graph_node, physical_pb_graph_node, vpr_pb_type_annotation);
 }
 
 /********************************************************************
diff --git a/openfpga/src/annotation/vpr_pb_type_annotation.cpp b/openfpga/src/annotation/vpr_pb_type_annotation.cpp
index 407907e59..3204dd597 100644
--- a/openfpga/src/annotation/vpr_pb_type_annotation.cpp
+++ b/openfpga/src/annotation/vpr_pb_type_annotation.cpp
@@ -195,6 +195,26 @@ int VprPbTypeAnnotation::physical_pb_pin_rotate_offset(t_port* pb_port) const {
   return physical_pb_pin_rotate_offsets_.at(pb_port);
 }
 
+int VprPbTypeAnnotation::physical_pb_pin_offset(t_port* pb_port) const {
+  /* Ensure that the pb_type is in the list */
+  std::map<t_port*, int>::const_iterator it = physical_pb_pin_offsets_.find(pb_port);
+  if (it == physical_pb_pin_offsets_.end()) {
+    /* Default value is 0 */
+    return 0;
+  }
+  return physical_pb_pin_offsets_.at(pb_port);
+}
+
+
+t_pb_graph_pin* VprPbTypeAnnotation::physical_pb_graph_pin(t_pb_graph_pin* pb_graph_pin) const {
+  /* Ensure that the pb_type is in the list */
+  std::map<t_pb_graph_pin*, t_pb_graph_pin*>::const_iterator it = physical_pb_graph_pins_.find(pb_graph_pin);
+  if (it == physical_pb_graph_pins_.end()) {
+    return nullptr;
+  }
+  return physical_pb_graph_pins_.at(pb_graph_pin);
+}
+
 /************************************************************************
  * Public mutators
  ***********************************************************************/
@@ -351,6 +371,45 @@ void VprPbTypeAnnotation::add_physical_pb_pin_rotate_offset(t_port* pb_port, con
   }
 
   physical_pb_pin_rotate_offsets_[pb_port] = offset;
+  /* We initialize the accumulated offset to 0 */
+  physical_pb_pin_offsets_[pb_port] = 0;
+}
+
+void VprPbTypeAnnotation::add_physical_pb_graph_pin(t_pb_graph_pin* operating_pb_graph_pin, 
+                                                    t_pb_graph_pin* physical_pb_graph_pin) {
+  /* Warn any override attempt */
+  std::map<t_pb_graph_pin*, t_pb_graph_pin*>::const_iterator it = physical_pb_graph_pins_.find(operating_pb_graph_pin);
+  if (it != physical_pb_graph_pins_.end()) {
+    VTR_LOG_WARN("Override the annotation between operating pb_graph_pin '%s' and it physical pb_graph_pin '%s'!\n",
+                 operating_pb_graph_pin->port->name, physical_pb_graph_pin->port->name);
+  }
+
+  physical_pb_graph_pins_[operating_pb_graph_pin] = physical_pb_graph_pin;
+
+  /* Update the accumulated offsets for the operating port 
+   * Each time we pair two pins, we update the offset by the pin rotate offset
+   * When the accumulated offset exceeds the MSB of the port range of physical port
+   * we reset it to 0
+   *                                             operating port         physical port
+   *                      LSB  port_range.lsb()    pin_number              pin_number      MSB
+   *                                 |                  |                     |
+   *    Operating port     |         |                  +------               |
+   *                                 |                        |<----offset--->|
+   *    Physical port      |         +                        +               +
+   *
+   */
+  if (0 == physical_pb_pin_rotate_offset(operating_pb_graph_pin->port)) {
+    return;
+  }
+
+  physical_pb_pin_offsets_[operating_pb_graph_pin->port] += physical_pb_pin_rotate_offset(operating_pb_graph_pin->port);
+
+  if (physical_pb_port_range(operating_pb_graph_pin->port).get_msb() 
+    < operating_pb_graph_pin->pin_number
+    + physical_pb_port_range(operating_pb_graph_pin->port).get_lsb() 
+    + physical_pb_pin_offset(operating_pb_graph_pin->port)) {
+    physical_pb_pin_offsets_[operating_pb_graph_pin->port] = 0;
+  }
 }
 
 } /* End namespace openfpga*/
diff --git a/openfpga/src/annotation/vpr_pb_type_annotation.h b/openfpga/src/annotation/vpr_pb_type_annotation.h
index bcdff9e3e..add45e42d 100644
--- a/openfpga/src/annotation/vpr_pb_type_annotation.h
+++ b/openfpga/src/annotation/vpr_pb_type_annotation.h
@@ -54,7 +54,18 @@ class VprPbTypeAnnotation {
     t_pb_graph_node* physical_pb_graph_node(t_pb_graph_node* pb_graph_node) const;
     int physical_pb_type_index_factor(t_pb_type* pb_type) const;
     int physical_pb_type_index_offset(t_pb_type* pb_type) const;
+
     int physical_pb_pin_rotate_offset(t_port* pb_port) const;
+
+    /**This function returns an accumulated offset. Note that the
+     * accumulated offset is NOT the pin rotate offset specified by users
+     * It is an aggregation of the offset during pin pairing
+     * Each time, we manage to pair two pins, the accumulated offset will be incremented
+     * by the pin rotate offset value
+     * The accumulated offset will be reset to 0 when it exceeds the msb() of the physical port
+     */
+    int physical_pb_pin_offset(t_port* pb_port) const;
+    t_pb_graph_pin* physical_pb_graph_pin(t_pb_graph_pin* pb_graph_pin) const;
   public:  /* Public mutators */
     void add_pb_type_physical_mode(t_pb_type* pb_type, t_mode* physical_mode);
     void add_physical_pb_type(t_pb_type* operating_pb_type, t_pb_type* physical_pb_type);
@@ -71,6 +82,7 @@ class VprPbTypeAnnotation {
     void add_physical_pb_type_index_factor(t_pb_type* pb_type, const int& factor);
     void add_physical_pb_type_index_offset(t_pb_type* pb_type, const int& offset);
     void add_physical_pb_pin_rotate_offset(t_port* pb_port, const int& offset);
+    void add_physical_pb_graph_pin(t_pb_graph_pin* operating_pb_graph_pin, t_pb_graph_pin* physical_pb_graph_pin);
   private: /* Internal data */
     /* Pair a regular pb_type to its physical pb_type */
     std::map<t_pb_type*, t_pb_type*> physical_pb_types_;
@@ -117,6 +129,9 @@ class VprPbTypeAnnotation {
     std::map<t_port*, t_port*> physical_pb_ports_;
     std::map<t_port*, int> physical_pb_pin_rotate_offsets_;
 
+    /* Accumulated offsets for a physical pb_type port, just for internal usage */
+    std::map<t_port*, int> physical_pb_pin_offsets_;
+
     /* Pair a pb_port to its LSB and MSB of a physical pb_port 
      * Note:
      * - the LSB and MSB MUST be in range of the physical pb_port

From 02d6256e9559bc8b4af403b8d6b63a797419c9e0 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 30 Jan 2020 21:39:44 -0700
Subject: [PATCH 055/645] pass simple test on pb_type annotation for frac_lut5
 architecture

---
 openfpga/src/annotation/annotate_pb_graph.cpp |   9 +-
 openfpga/src/annotation/annotate_pb_types.cpp |   3 +-
 .../k6_frac_N10_40nm_openfpga.xml             | 265 ++++++++++++++++++
 openfpga/test_script/s298_k6_frac.openfpga    |  14 +
 openfpga/test_vpr_arch/k6_frac_N10_40nm.xml   |  87 ++++++
 5 files changed, 375 insertions(+), 3 deletions(-)
 create mode 100644 openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
 create mode 100644 openfpga/test_script/s298_k6_frac.openfpga

diff --git a/openfpga/src/annotation/annotate_pb_graph.cpp b/openfpga/src/annotation/annotate_pb_graph.cpp
index fb94bc238..92f1b90b2 100644
--- a/openfpga/src/annotation/annotate_pb_graph.cpp
+++ b/openfpga/src/annotation/annotate_pb_graph.cpp
@@ -73,6 +73,13 @@ void rec_build_vpr_pb_graph_interconnect_physical_type_annotation(t_pb_graph_nod
 
     /* For each interconnect that has more than 1 input, we can infer the physical type */
     for (t_interconnect* interc : pb_mode_interconnects(child_physical_mode)) {
+      /* If the number inputs for an interconnect is zero, this is a 0-driver pin
+       * we just set 1 to use direct wires
+       */
+      if (0 == interc_num_inputs[interc]) {
+        interc_num_inputs[interc] = 1;
+      }
+      
       e_interconnect interc_physical_type = pb_interconnect_physical_type(interc, interc_num_inputs[interc]);
       if (interc_physical_type == vpr_pb_type_annotation.interconnect_physical_type(interc)) {
         /* Skip annotation if we have already done! */
@@ -383,7 +390,7 @@ void rec_build_vpr_physical_pb_graph_node_annotation(t_pb_graph_node* pb_graph_n
                                           * (size_t)vpr_pb_type_annotation.pb_graph_node_unique_index(pb_graph_node)
                                           + vpr_pb_type_annotation.physical_pb_type_index_offset(pb_graph_node->pb_type)
                                             );
-  t_pb_graph_node* physical_pb_graph_node = vpr_pb_type_annotation.pb_graph_node(pb_graph_node->pb_type, physical_pb_graph_node_id);
+  t_pb_graph_node* physical_pb_graph_node = vpr_pb_type_annotation.pb_graph_node(physical_pb_type, physical_pb_graph_node_id);
   VTR_ASSERT(nullptr != physical_pb_graph_node);
   vpr_pb_type_annotation.add_physical_pb_graph_node(pb_graph_node, physical_pb_graph_node);
 
diff --git a/openfpga/src/annotation/annotate_pb_types.cpp b/openfpga/src/annotation/annotate_pb_types.cpp
index fb2905637..8dc89251a 100644
--- a/openfpga/src/annotation/annotate_pb_types.cpp
+++ b/openfpga/src/annotation/annotate_pb_types.cpp
@@ -220,7 +220,7 @@ bool pair_operating_and_physical_pb_types(t_pb_type* operating_pb_type,
       return false;
     }
     /* If the port range does not match, mapping fails */
-    if (false == expected_physical_pb_port.contained(BasicPort(physical_pb_port->name, physical_pb_port->num_pins))) {
+    if (false == BasicPort(physical_pb_port->name, physical_pb_port->num_pins).contained(expected_physical_pb_port)) {
       return false;
     }
     /* Now, port mapping should succeed, we update the vpr_pb_type_annotation 
@@ -337,7 +337,6 @@ void build_vpr_physical_pb_type_explicit_annotation(const DeviceContext& vpr_dev
       VTR_LOG_ERROR("Unable to pair the operating pb_type '%s' to its physical pb_type '%s'!\n",
                     target_op_pb_type_names.back().c_str(),
                     target_phy_pb_type_names.back().c_str());
-      return;
     }
   } 
 }
diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
new file mode 100644
index 000000000..b517fa24b
--- /dev/null
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
@@ -0,0 +1,265 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
+      <design_technology type="cmos" topology="OR"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <!--mux2to1 subckt_name="mux2to1"/-->
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <!--mux2to1 subckt_name="mux2to1"/-->
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <!--mux2to1 subckt_name="mux2to1"/-->
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <pass_gate_logic circuit_model_name="TGATE"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="6" tri_state_map="----11" circuit_model_name="OR2"/>
+      <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
+      <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
+      <port type="sram" prefix="sram" size="64"/>
+      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <pass_gate_logic circuit_model_name="TGATE"/>
+       <port type="input" prefix="pReset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="Qb" size="1"/>
+       <port type="clock" prefix="prog_clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="inout" prefix="pad" size="1"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+      <port type="input" prefix="outpad" size="1"/>
+      <port type="output" prefix="inpad" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle" physical_mode_name="physical"/>
+    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="0"/>
+    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
+    <!-- Binding operating pb_type to physical pb_type -->
+    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="1" physical_pb_type_index_factor="0.5">
+      <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:4]"/>
+      <port name="out" physical_mode_port="lut5_out" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="0">
+      <!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:5]"/>
+      <port name="out" physical_mode_port="lut6_out"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="1"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>
+<openfpga_simulation_setting>
+  <clock_setting>
+    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
+    <programming frequency="10e6"/>
+  </clock_setting>
+  <simulator_option>
+    <operating_condition temperature="25"/>
+    <output_log verbose="false" captab="false"/>
+    <accuracy type="abs" value="1e-13"/>
+    <runtime fast_simulation="true"/>
+  </simulator_option>
+  <monte_carlo num_simulation_points="2"/>
+  <measurement_setting>
+    <slew>
+      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
+      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
+    </slew>
+    <delay>
+      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
+      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
+    </delay>
+  </measurement_setting>
+  <stimulus>
+    <clock>
+      <rise slew_type="abs" slew_time="20e-12" />
+      <fall slew_type="abs" slew_time="20e-12" />
+    </clock>
+    <input>
+      <rise slew_type="abs" slew_time="25e-12" />
+      <fall slew_type="abs" slew_time="25e-12" />
+    </input>
+  </stimulus>
+</openfpga_simulation_setting>
diff --git a/openfpga/test_script/s298_k6_frac.openfpga b/openfpga/test_script/s298_k6_frac.openfpga
new file mode 100644
index 000000000..22e74cdb1
--- /dev/null
+++ b/openfpga/test_script/s298_k6_frac.openfpga
@@ -0,0 +1,14 @@
+# Run VPR for the s298 design
+vpr ./test_vpr_arch/k6_frac_N10_40nm.xml ./test_blif/s298.blif
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+
+# Annotate the OpenFPGA architecture to VPR data base
+link_openfpga_arch
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Finish and exit OpenFPGA
+exit
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml
index 4da00d67a..269384cbc 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml
@@ -24,6 +24,25 @@
        that describe them.
   -->
   <models>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="frac_lut6">
+      <input_ports>
+        <port name="in"/>
+      </input_ports>
+      <output_ports>
+        <port name="lut5_out"/>
+        <port name="lut6_out"/>
+      </output_ports>
+    </model>
   </models>
   <tiles>
     <tile name="io" capacity="8" area="0">
@@ -127,6 +146,24 @@
       <input name="outpad" num_pins="1"/>
       <output name="inpad" num_pins="1"/>
       <clock name="clock" num_pins="1"/>
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" disabled_in_pack="true">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+
       <!-- IOs can operate as either inputs or outputs.
 	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
 	     the delays to and from registers in the I/O (and generally I/Os are registered 
@@ -183,6 +220,56 @@
         <input name="in" num_pins="6"/>
         <output name="out" num_pins="2"/>
         <clock name="clk" num_pins="1"/>
+        <!-- Physical mode definition begin (physical implementation of the fle) -->
+        <mode name="physical">
+          <pb_type name="fabric" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="2"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="frac_logic" num_pb="1">
+              <input name="in" num_pins="6"/>
+              <output name="out" num_pins="2"/>
+              <!-- Define LUT -->
+              <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
+                <input name="in" num_pins="6"/>
+                <output name="lut5_out" num_pins="2"/>
+                <output name="lut6_out" num_pins="1"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
+                <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
+              </interconnect>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
+              <complete name="direct3" input="fabric.clk" output="ff[1:0].clk"/>
+              <mux name="mux1" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
+                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
+              </mux>
+              <mux name="mux2" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
+                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="fabric.in"/>
+            <direct name="direct2" input="fabric.out" output="fle.out"/>
+            <direct name="direct3" input="fle.clk" output="fabric.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Physical mode definition end (physical implementation of the fle) -->
         <!-- Dual 5-LUT mode definition begin -->
         <mode name="n2_lut5">
           <pb_type name="lut5inter" num_pb="1">

From fdc304a0fbc17be1195039b3313ec92ff5d8d916 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 30 Jan 2020 22:00:53 -0700
Subject: [PATCH 056/645] fixed a bug in mapping pb_graph pins using rotation
 offset

---
 openfpga/src/annotation/vpr_pb_type_annotation.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/openfpga/src/annotation/vpr_pb_type_annotation.cpp b/openfpga/src/annotation/vpr_pb_type_annotation.cpp
index 3204dd597..f75a91059 100644
--- a/openfpga/src/annotation/vpr_pb_type_annotation.cpp
+++ b/openfpga/src/annotation/vpr_pb_type_annotation.cpp
@@ -404,10 +404,10 @@ void VprPbTypeAnnotation::add_physical_pb_graph_pin(t_pb_graph_pin* operating_pb
 
   physical_pb_pin_offsets_[operating_pb_graph_pin->port] += physical_pb_pin_rotate_offset(operating_pb_graph_pin->port);
 
-  if (physical_pb_port_range(operating_pb_graph_pin->port).get_msb() 
+  if ((size_t)physical_pb_port(operating_pb_graph_pin->port)->num_pins - 1 
     < operating_pb_graph_pin->pin_number
     + physical_pb_port_range(operating_pb_graph_pin->port).get_lsb() 
-    + physical_pb_pin_offset(operating_pb_graph_pin->port)) {
+    + physical_pb_pin_offsets_[operating_pb_graph_pin->port]) {
     physical_pb_pin_offsets_[operating_pb_graph_pin->port] = 0;
   }
 }

From afde9808da3d86f7ef78a7d50825cabcfce4dc4d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 31 Jan 2020 10:47:05 -0700
Subject: [PATCH 057/645] add check codes for physical pb_graph_node and
 pb_graph_pin annotation

---
 openfpga/src/annotation/annotate_pb_graph.cpp |   4 +
 .../annotation/check_pb_graph_annotation.cpp  | 124 ++++++++++++++++++
 .../annotation/check_pb_graph_annotation.h    |  23 ++++
 3 files changed, 151 insertions(+)
 create mode 100644 openfpga/src/annotation/check_pb_graph_annotation.cpp
 create mode 100644 openfpga/src/annotation/check_pb_graph_annotation.h

diff --git a/openfpga/src/annotation/annotate_pb_graph.cpp b/openfpga/src/annotation/annotate_pb_graph.cpp
index 92f1b90b2..d720426cc 100644
--- a/openfpga/src/annotation/annotate_pb_graph.cpp
+++ b/openfpga/src/annotation/annotate_pb_graph.cpp
@@ -10,6 +10,7 @@
 #include "pb_graph_utils.h"
 
 #include "annotate_pb_graph.h"
+#include "check_pb_graph_annotation.h"
 
 /* begin namespace openfpga */
 namespace openfpga {
@@ -435,6 +436,9 @@ void annotate_pb_graph(const DeviceContext& vpr_device_ctx,
   VTR_LOG("Binding operating pb_graph nodes/pins to physical pb_graph nodes/pins...\n");
   annotate_physical_pb_graph_node(vpr_device_ctx, vpr_pb_type_annotation);
   VTR_LOG("Done\n");
+
+  /* Check each primitive pb_graph_node and pin has been binded to a physical node and pin */
+  check_physical_pb_graph_node_annotation(vpr_device_ctx, const_cast<const VprPbTypeAnnotation&>(vpr_pb_type_annotation));
 }
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/annotation/check_pb_graph_annotation.cpp b/openfpga/src/annotation/check_pb_graph_annotation.cpp
new file mode 100644
index 000000000..92cabefb4
--- /dev/null
+++ b/openfpga/src/annotation/check_pb_graph_annotation.cpp
@@ -0,0 +1,124 @@
+/********************************************************************
+ * This file includes functions to check the  annotation on
+ * the physical pb_graph_node and pb_graph_pin
+ *******************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_time.h"
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+#include "pb_type_utils.h"
+#include "check_pb_graph_annotation.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * A function to check if a physical pb_graph_pin for a pb_graph_pin 
+ * Print error to log file/screen when checking fails
+ *******************************************************************/
+static 
+bool check_physical_pb_graph_pin(t_pb_graph_pin* pb_graph_pin,
+                                 const VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  if (nullptr == vpr_pb_type_annotation.physical_pb_graph_pin(pb_graph_pin)) {
+    VTR_LOG_ERROR("Found a pb_graph_pin '%s' missing physical pb_graph_pin binding!\n",
+                  pb_graph_pin->port->name);
+    return false;
+  }
+
+  return true;
+}
+
+/********************************************************************
+ * This function will recursively walk through all the pb_graph nodes
+ * starting from a top node.
+ * It aims to check 
+ * - if each primitive pb_graph node has been binded to a physical 
+ *   pb_graph_node
+ * - if each pin of the primitive pb_graph node has been binded to 
+ *   a physical graph_pin
+ *******************************************************************/
+static 
+void rec_check_vpr_physical_pb_graph_node_annotation(t_pb_graph_node* pb_graph_node, 
+                                                     const VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                                     size_t& num_err) {
+  /* Go recursive first until we touch the primitive node */
+  if (false == is_primitive_pb_type(pb_graph_node->pb_type)) {
+    for (int imode = 0; imode < pb_graph_node->pb_type->num_modes; ++imode) {
+      for (int ipb = 0; ipb < pb_graph_node->pb_type->modes[imode].num_pb_type_children; ++ipb) {
+        /* Each child may exist multiple times in the hierarchy*/
+        for (int jpb = 0; jpb < pb_graph_node->pb_type->modes[imode].pb_type_children[ipb].num_pb; ++jpb) {
+          rec_check_vpr_physical_pb_graph_node_annotation(&(pb_graph_node->child_pb_graph_nodes[imode][ipb][jpb]), 
+                                                          vpr_pb_type_annotation, num_err);
+        }
+      }
+    }
+    return;
+  }
+
+  /* Ensure that the pb_graph_node has been mapped to a physical node */
+  t_pb_graph_node* physical_pb_graph_node = vpr_pb_type_annotation.physical_pb_graph_node(pb_graph_node);
+  if (nullptr == physical_pb_graph_node) { 
+    VTR_LOG_ERROR("Found a pb_graph_node '%s' missing physical pb_graph_node binding!\n",
+                  physical_pb_graph_node->pb_type->name);
+    num_err++;
+    return; /* Invalid pointer already, further check is not applicable */
+  } 
+
+  /* Reach here, we should have a valid pointer to the physical pb_graph_node,
+   * Check the physical pb_graph_pin for each pin 
+   */
+  for (int iport = 0; iport < physical_pb_graph_node->num_input_ports; ++iport) {
+    for (int ipin = 0; ipin < physical_pb_graph_node->num_input_pins[iport]; ++ipin) {
+      if (false == check_physical_pb_graph_pin(&(physical_pb_graph_node->input_pins[iport][ipin]),
+                                               vpr_pb_type_annotation)) {
+        num_err++;
+      }
+    } 
+  }
+
+  for (int iport = 0; iport < physical_pb_graph_node->num_output_ports; ++iport) {
+    for (int ipin = 0; ipin < physical_pb_graph_node->num_output_pins[iport]; ++ipin) {
+      if (false == check_physical_pb_graph_pin(&(physical_pb_graph_node->output_pins[iport][ipin]),
+                                               vpr_pb_type_annotation)) {
+        num_err++;
+      }
+    } 
+  }
+
+  for (int iport = 0; iport < physical_pb_graph_node->num_clock_ports; ++iport) {
+    for (int ipin = 0; ipin < physical_pb_graph_node->num_clock_pins[iport]; ++ipin) {
+      if (false == check_physical_pb_graph_pin(&(physical_pb_graph_node->clock_pins[iport][ipin]),
+                                               vpr_pb_type_annotation)) {
+        num_err++;
+      }
+    } 
+  }
+}
+
+/********************************************************************
+ * Check each primitive pb_graph_node
+ * - It has been binded to an physical pb_graph_node
+ * - Each pin has been binded to a physical pb_graph_node pin
+ *******************************************************************/
+void check_physical_pb_graph_node_annotation(const DeviceContext& vpr_device_ctx, 
+                                             const VprPbTypeAnnotation& vpr_pb_type_annotation) {
+  size_t num_err = 0;
+ 
+  for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
+    /* By pass nullptr for pb_graph head */
+    if (nullptr == lb_type.pb_graph_head) {
+      continue;
+    }
+    rec_check_vpr_physical_pb_graph_node_annotation(lb_type.pb_graph_head, vpr_pb_type_annotation, num_err); 
+  }
+
+  if (0 == num_err) {
+    VTR_LOG("Check pb_graph annotation for physical nodes and pins passed.\n");
+  } else {
+    VTR_LOG_ERROR("Check pb_graph annotation for physical nodes and pins failed with %ld errors!\n",
+                  num_err);
+  }
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/annotation/check_pb_graph_annotation.h b/openfpga/src/annotation/check_pb_graph_annotation.h
new file mode 100644
index 000000000..c482943c5
--- /dev/null
+++ b/openfpga/src/annotation/check_pb_graph_annotation.h
@@ -0,0 +1,23 @@
+#ifndef CHECK_PB_GRAPH_ANNOTATION_H
+#define CHECK_PB_GRAPH_ANNOTATION_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "vpr_context.h"
+#include "openfpga_context.h"
+#include "vpr_pb_type_annotation.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void check_physical_pb_graph_node_annotation(const DeviceContext& vpr_device_ctx, 
+                                             const VprPbTypeAnnotation& vpr_pb_type_annotation);
+
+} /* end namespace openfpga */
+
+#endif

From 392ab0f027470e0a199f8ecdba704fb7d5646f10 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 31 Jan 2020 10:53:41 -0700
Subject: [PATCH 058/645] move duplicated codes on message printing to
 functions

---
 openfpga/src/annotation/annotate_pb_graph.cpp | 48 ++++++++-----------
 1 file changed, 21 insertions(+), 27 deletions(-)

diff --git a/openfpga/src/annotation/annotate_pb_graph.cpp b/openfpga/src/annotation/annotate_pb_graph.cpp
index d720426cc..3a1b17365 100644
--- a/openfpga/src/annotation/annotate_pb_graph.cpp
+++ b/openfpga/src/annotation/annotate_pb_graph.cpp
@@ -222,6 +222,24 @@ bool try_match_pb_graph_pin(t_pb_graph_pin* operating_pb_graph_pin,
   return true;
 }
 
+/********************************************************************
+ * A function to print message to log file/screen when physical pb_graph_pin
+ * binding succeed
+ *******************************************************************/
+static 
+void print_success_bind_pb_graph_pin(t_pb_graph_pin* operating_pb_graph_pin,
+                                     t_pb_graph_pin* physical_pb_graph_pin) {
+  VTR_LOG("Bind a pb_graph_node '%s[%d]' pin '%s[%d]' to a pb_graph_node '%s[%d]' pin '%s[%d]'!\n",
+          operating_pb_graph_pin->parent_node->pb_type->name,
+          operating_pb_graph_pin->parent_node->placement_index,
+          operating_pb_graph_pin->port->name,
+          operating_pb_graph_pin->pin_number,
+          physical_pb_graph_pin->parent_node->pb_type->name,
+          physical_pb_graph_pin->parent_node->placement_index,
+          physical_pb_graph_pin->port->name,
+          physical_pb_graph_pin->pin_number);
+}
+
 /********************************************************************
  * Bind a pb_graph_pin from an operating pb_graph_node to 
  * a pb_graph_pin from a physical pb_graph_node
@@ -245,15 +263,7 @@ void annotate_physical_pb_graph_pin(t_pb_graph_pin* operating_pb_graph_pin,
        * We can pair the pin and return  
        */
       vpr_pb_type_annotation.add_physical_pb_graph_pin(operating_pb_graph_pin, &(physical_pb_graph_node->input_pins[iport][ipin]));
-      VTR_LOG("Bind a pb_graph_node '%s[%d]' pin '%s[%d]' to a pb_graph_node '%s[%d]' pin '%s[%d]'!\n",
-              operating_pb_graph_pin->parent_node->pb_type->name,
-              operating_pb_graph_pin->parent_node->placement_index,
-              operating_pb_graph_pin->port->name,
-              operating_pb_graph_pin->pin_number,
-              physical_pb_graph_node->pb_type->name,
-              physical_pb_graph_node->placement_index,
-              physical_pb_graph_node->input_pins[iport][ipin].port->name,
-              physical_pb_graph_node->input_pins[iport][ipin].pin_number);
+      print_success_bind_pb_graph_pin(operating_pb_graph_pin, vpr_pb_type_annotation.physical_pb_graph_pin(operating_pb_graph_pin)); 
       return;
     }
   }
@@ -269,15 +279,7 @@ void annotate_physical_pb_graph_pin(t_pb_graph_pin* operating_pb_graph_pin,
        * We can pair the pin and return  
        */
       vpr_pb_type_annotation.add_physical_pb_graph_pin(operating_pb_graph_pin, &(physical_pb_graph_node->output_pins[iport][ipin]));
-      VTR_LOG("Bind a pb_graph_node '%s[%d]' pin '%s[%d]' to a pb_graph_node '%s[%d]' pin '%s[%d]'!\n",
-              operating_pb_graph_pin->parent_node->pb_type->name,
-              operating_pb_graph_pin->parent_node->placement_index,
-              operating_pb_graph_pin->port->name,
-              operating_pb_graph_pin->pin_number,
-              physical_pb_graph_node->pb_type->name,
-              physical_pb_graph_node->placement_index,
-              physical_pb_graph_node->output_pins[iport][ipin].port->name,
-              physical_pb_graph_node->output_pins[iport][ipin].pin_number);
+      print_success_bind_pb_graph_pin(operating_pb_graph_pin, vpr_pb_type_annotation.physical_pb_graph_pin(operating_pb_graph_pin)); 
       return;
     }
   }
@@ -293,15 +295,7 @@ void annotate_physical_pb_graph_pin(t_pb_graph_pin* operating_pb_graph_pin,
        * We can pair the pin and return  
        */
       vpr_pb_type_annotation.add_physical_pb_graph_pin(operating_pb_graph_pin, &(physical_pb_graph_node->clock_pins[iport][ipin]));
-      VTR_LOG("Bind a pb_graph_node '%s[%d]' pin '%s[%d]' to a pb_graph_node '%s[%d]' pin '%s[%d]'!\n",
-              operating_pb_graph_pin->parent_node->pb_type->name,
-              operating_pb_graph_pin->parent_node->placement_index,
-              operating_pb_graph_pin->port->name,
-              operating_pb_graph_pin->pin_number,
-              physical_pb_graph_node->pb_type->name,
-              physical_pb_graph_node->placement_index,
-              physical_pb_graph_node->clock_pins[iport][ipin].port->name,
-              physical_pb_graph_node->clock_pins[iport][ipin].pin_number);
+      print_success_bind_pb_graph_pin(operating_pb_graph_pin, vpr_pb_type_annotation.physical_pb_graph_pin(operating_pb_graph_pin)); 
       return;
     }
   }

From 75c3507acf926eb34504574182736838bc652fca Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 31 Jan 2020 11:36:58 -0700
Subject: [PATCH 059/645] add verbose output option for openfpga linking
 architecture

---
 libs/libarchfpga/src/physical_types.h         |   1 +
 openfpga/src/annotation/annotate_pb_graph.cpp |  71 ++++---
 openfpga/src/annotation/annotate_pb_graph.h   |   6 +-
 openfpga/src/annotation/annotate_pb_types.cpp | 176 ++++++++++++------
 openfpga/src/annotation/annotate_pb_types.h   |   3 +-
 openfpga/src/base/openfpga_link_arch.cpp      |  11 +-
 openfpga/src/base/openfpga_link_arch.h        |   5 +-
 openfpga/src/base/openfpga_setup_command.cpp  |   4 +-
 8 files changed, 184 insertions(+), 93 deletions(-)

diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h
index 503427303..153fd981e 100644
--- a/libs/libarchfpga/src/physical_types.h
+++ b/libs/libarchfpga/src/physical_types.h
@@ -165,6 +165,7 @@ enum e_interconnect {
     MUX_INTERC = 3,
     NUM_INTERC_TYPES
 };
+constexpr std::array<const char*, NUM_INTERC_TYPES> INTERCONNECT_TYPE_STRING = {{"complete", "direct", "mux"}}; //String versions of interconnection type
 
 /* Orientations. */
 enum e_side : unsigned char {
diff --git a/openfpga/src/annotation/annotate_pb_graph.cpp b/openfpga/src/annotation/annotate_pb_graph.cpp
index 3a1b17365..2043c2098 100644
--- a/openfpga/src/annotation/annotate_pb_graph.cpp
+++ b/openfpga/src/annotation/annotate_pb_graph.cpp
@@ -28,7 +28,8 @@ namespace openfpga {
  *******************************************************************/
 static 
 void rec_build_vpr_pb_graph_interconnect_physical_type_annotation(t_pb_graph_node* pb_graph_node, 
-                                                                  VprPbTypeAnnotation& vpr_pb_type_annotation) {
+                                                                  VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                                                  const bool& verbose_output) {
   /* Skip the root node because we start from the inputs of child pb_graph node 
    *  
    *   pb_graph_node
@@ -86,6 +87,9 @@ void rec_build_vpr_pb_graph_interconnect_physical_type_annotation(t_pb_graph_nod
         /* Skip annotation if we have already done! */
         continue;
       }
+      VTR_LOGV(verbose_output,
+               "Infer physical type '%s' of interconnect '%s' (was '%s')\n",
+               INTERCONNECT_TYPE_STRING[interc_physical_type], interc->name, INTERCONNECT_TYPE_STRING[interc->type]);
       vpr_pb_type_annotation.add_interconnect_physical_type(interc, interc_physical_type);
     }
   }
@@ -101,7 +105,9 @@ void rec_build_vpr_pb_graph_interconnect_physical_type_annotation(t_pb_graph_nod
   for (int ipb = 0; ipb < physical_mode->num_pb_type_children; ++ipb) {
     /* Each child may exist multiple times in the hierarchy*/
     for (int jpb = 0; jpb < physical_mode->pb_type_children[ipb].num_pb; ++jpb) {
-      rec_build_vpr_pb_graph_interconnect_physical_type_annotation(&(pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb][jpb]), vpr_pb_type_annotation);
+      rec_build_vpr_pb_graph_interconnect_physical_type_annotation(&(pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb][jpb]),
+                                                                   vpr_pb_type_annotation,
+                                                                   verbose_output);
     }
   }
 }
@@ -116,13 +122,14 @@ void rec_build_vpr_pb_graph_interconnect_physical_type_annotation(t_pb_graph_nod
  *       build_vpr_physical_pb_mode_implicit_annotation() 
  *******************************************************************/
 void annotate_pb_graph_interconnect_physical_type(const DeviceContext& vpr_device_ctx, 
-                                                  VprPbTypeAnnotation& vpr_pb_type_annotation) {
+                                                  VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                                  const bool& verbose_output) {
   for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
     /* By pass nullptr for pb_graph head */
     if (nullptr == lb_type.pb_graph_head) {
       continue;
     }
-    rec_build_vpr_pb_graph_interconnect_physical_type_annotation(lb_type.pb_graph_head, vpr_pb_type_annotation); 
+    rec_build_vpr_pb_graph_interconnect_physical_type_annotation(lb_type.pb_graph_head, vpr_pb_type_annotation, verbose_output); 
   }
 }
 
@@ -248,7 +255,8 @@ void print_success_bind_pb_graph_pin(t_pb_graph_pin* operating_pb_graph_pin,
 static 
 void annotate_physical_pb_graph_pin(t_pb_graph_pin* operating_pb_graph_pin, 
                                     t_pb_graph_node* physical_pb_graph_node, 
-                                    VprPbTypeAnnotation& vpr_pb_type_annotation) {
+                                    VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                    const bool& verbose_output) {
   /* Iterate over every port and pin of the operating pb_graph_node 
    * and find the physical pins 
    */
@@ -263,7 +271,9 @@ void annotate_physical_pb_graph_pin(t_pb_graph_pin* operating_pb_graph_pin,
        * We can pair the pin and return  
        */
       vpr_pb_type_annotation.add_physical_pb_graph_pin(operating_pb_graph_pin, &(physical_pb_graph_node->input_pins[iport][ipin]));
-      print_success_bind_pb_graph_pin(operating_pb_graph_pin, vpr_pb_type_annotation.physical_pb_graph_pin(operating_pb_graph_pin)); 
+      if (true == verbose_output) {
+        print_success_bind_pb_graph_pin(operating_pb_graph_pin, vpr_pb_type_annotation.physical_pb_graph_pin(operating_pb_graph_pin)); 
+      }
       return;
     }
   }
@@ -279,7 +289,9 @@ void annotate_physical_pb_graph_pin(t_pb_graph_pin* operating_pb_graph_pin,
        * We can pair the pin and return  
        */
       vpr_pb_type_annotation.add_physical_pb_graph_pin(operating_pb_graph_pin, &(physical_pb_graph_node->output_pins[iport][ipin]));
-      print_success_bind_pb_graph_pin(operating_pb_graph_pin, vpr_pb_type_annotation.physical_pb_graph_pin(operating_pb_graph_pin)); 
+      if (true == verbose_output) {
+        print_success_bind_pb_graph_pin(operating_pb_graph_pin, vpr_pb_type_annotation.physical_pb_graph_pin(operating_pb_graph_pin)); 
+      }
       return;
     }
   }
@@ -295,7 +307,9 @@ void annotate_physical_pb_graph_pin(t_pb_graph_pin* operating_pb_graph_pin,
        * We can pair the pin and return  
        */
       vpr_pb_type_annotation.add_physical_pb_graph_pin(operating_pb_graph_pin, &(physical_pb_graph_node->clock_pins[iport][ipin]));
-      print_success_bind_pb_graph_pin(operating_pb_graph_pin, vpr_pb_type_annotation.physical_pb_graph_pin(operating_pb_graph_pin)); 
+      if (true == verbose_output) {
+        print_success_bind_pb_graph_pin(operating_pb_graph_pin, vpr_pb_type_annotation.physical_pb_graph_pin(operating_pb_graph_pin)); 
+      }
       return;
     }
   }
@@ -315,28 +329,32 @@ void annotate_physical_pb_graph_pin(t_pb_graph_pin* operating_pb_graph_pin,
 static 
 void annotate_physical_pb_graph_node_pins(t_pb_graph_node* operating_pb_graph_node, 
                                           t_pb_graph_node* physical_pb_graph_node, 
-                                          VprPbTypeAnnotation& vpr_pb_type_annotation) {
+                                          VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                          const bool& verbose_output) {
   /* Iterate over every port and pin of the operating pb_graph_node 
    * and find the physical pins 
    */
   for (int iport = 0; iport < operating_pb_graph_node->num_input_ports; ++iport) {
     for (int ipin = 0; ipin < operating_pb_graph_node->num_input_pins[iport]; ++ipin) {
       annotate_physical_pb_graph_pin(&(operating_pb_graph_node->input_pins[iport][ipin]),
-                                     physical_pb_graph_node, vpr_pb_type_annotation);
+                                     physical_pb_graph_node, vpr_pb_type_annotation,
+                                     verbose_output);
     }
   }
 
   for (int iport = 0; iport < operating_pb_graph_node->num_output_ports; ++iport) {
     for (int ipin = 0; ipin < operating_pb_graph_node->num_output_pins[iport]; ++ipin) {
       annotate_physical_pb_graph_pin(&(operating_pb_graph_node->output_pins[iport][ipin]),
-                                     physical_pb_graph_node, vpr_pb_type_annotation);
+                                     physical_pb_graph_node, vpr_pb_type_annotation,
+                                     verbose_output);
     }
   }
 
   for (int iport = 0; iport < operating_pb_graph_node->num_clock_ports; ++iport) {
     for (int ipin = 0; ipin < operating_pb_graph_node->num_clock_pins[iport]; ++ipin) {
       annotate_physical_pb_graph_pin(&(operating_pb_graph_node->clock_pins[iport][ipin]),
-                                     physical_pb_graph_node, vpr_pb_type_annotation);
+                                     physical_pb_graph_node, vpr_pb_type_annotation,
+                                     verbose_output);
     }
   }
 }
@@ -351,7 +369,8 @@ void annotate_physical_pb_graph_node_pins(t_pb_graph_node* operating_pb_graph_no
  *******************************************************************/
 static 
 void rec_build_vpr_physical_pb_graph_node_annotation(t_pb_graph_node* pb_graph_node, 
-                                                     VprPbTypeAnnotation& vpr_pb_type_annotation) {
+                                                     VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                                     const bool& verbose_output) {
   /* Go recursive first until we touch the primitive node */
   if (false == is_primitive_pb_type(pb_graph_node->pb_type)) {
     for (int imode = 0; imode < pb_graph_node->pb_type->num_modes; ++imode) {
@@ -359,7 +378,8 @@ void rec_build_vpr_physical_pb_graph_node_annotation(t_pb_graph_node* pb_graph_n
         /* Each child may exist multiple times in the hierarchy*/
         for (int jpb = 0; jpb < pb_graph_node->pb_type->modes[imode].pb_type_children[ipb].num_pb; ++jpb) {
           rec_build_vpr_physical_pb_graph_node_annotation(&(pb_graph_node->child_pb_graph_nodes[imode][ipb][jpb]), 
-                                                          vpr_pb_type_annotation);
+                                                          vpr_pb_type_annotation,
+                                                          verbose_output);
         }
       }
     }
@@ -389,12 +409,13 @@ void rec_build_vpr_physical_pb_graph_node_annotation(t_pb_graph_node* pb_graph_n
   VTR_ASSERT(nullptr != physical_pb_graph_node);
   vpr_pb_type_annotation.add_physical_pb_graph_node(pb_graph_node, physical_pb_graph_node);
 
-  VTR_LOG("Bind operating pb_graph_node '%s' to physical pb_graph_node '%s'\n",
-          pb_graph_node->hierarchical_type_name().c_str(),
-          physical_pb_graph_node->hierarchical_type_name().c_str());
+  VTR_LOGV(verbose_output,
+           "Bind operating pb_graph_node '%s' to physical pb_graph_node '%s'\n",
+           pb_graph_node->hierarchical_type_name().c_str(),
+           physical_pb_graph_node->hierarchical_type_name().c_str());
 
   /* Try to bind each pins under this pb_graph_node to physical_pb_graph_node */
-  annotate_physical_pb_graph_node_pins(pb_graph_node, physical_pb_graph_node, vpr_pb_type_annotation);
+  annotate_physical_pb_graph_node_pins(pb_graph_node, physical_pb_graph_node, vpr_pb_type_annotation, verbose_output);
 }
 
 /********************************************************************
@@ -404,13 +425,14 @@ void rec_build_vpr_physical_pb_graph_node_annotation(t_pb_graph_node* pb_graph_n
  *******************************************************************/
 static 
 void annotate_physical_pb_graph_node(const DeviceContext& vpr_device_ctx, 
-                                     VprPbTypeAnnotation& vpr_pb_type_annotation) {
+                                     VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                     const bool& verbose_output) {
   for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
     /* By pass nullptr for pb_graph head */
     if (nullptr == lb_type.pb_graph_head) {
       continue;
     }
-    rec_build_vpr_physical_pb_graph_node_annotation(lb_type.pb_graph_head, vpr_pb_type_annotation); 
+    rec_build_vpr_physical_pb_graph_node_annotation(lb_type.pb_graph_head, vpr_pb_type_annotation, verbose_output); 
   }
 }
 
@@ -421,14 +443,17 @@ void annotate_physical_pb_graph_node(const DeviceContext& vpr_device_ctx,
  * - Bind pins from operating pb_graph_node to their physical pb_graph_node pins
  *******************************************************************/
 void annotate_pb_graph(const DeviceContext& vpr_device_ctx, 
-                       VprPbTypeAnnotation& vpr_pb_type_annotation) {
+                       VprPbTypeAnnotation& vpr_pb_type_annotation,
+                       const bool& verbose_output) {
 
   VTR_LOG("Assigning unique indices for primitive pb_graph nodes...");
+  VTR_LOGV(verbose_output, "\n");
   annotate_primitive_pb_graph_node_unique_index(vpr_device_ctx, vpr_pb_type_annotation);
   VTR_LOG("Done\n");
 
-  VTR_LOG("Binding operating pb_graph nodes/pins to physical pb_graph nodes/pins...\n");
-  annotate_physical_pb_graph_node(vpr_device_ctx, vpr_pb_type_annotation);
+  VTR_LOG("Binding operating pb_graph nodes/pins to physical pb_graph nodes/pins...");
+  VTR_LOGV(verbose_output, "\n");
+  annotate_physical_pb_graph_node(vpr_device_ctx, vpr_pb_type_annotation, verbose_output);
   VTR_LOG("Done\n");
 
   /* Check each primitive pb_graph_node and pin has been binded to a physical node and pin */
diff --git a/openfpga/src/annotation/annotate_pb_graph.h b/openfpga/src/annotation/annotate_pb_graph.h
index e809d3cfa..64eced256 100644
--- a/openfpga/src/annotation/annotate_pb_graph.h
+++ b/openfpga/src/annotation/annotate_pb_graph.h
@@ -16,10 +16,12 @@
 namespace openfpga {
 
 void annotate_pb_graph_interconnect_physical_type(const DeviceContext& vpr_device_ctx, 
-                                                  VprPbTypeAnnotation& vpr_pb_type_annotation);
+                                                  VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                                  const bool& verbose_output);
 
 void annotate_pb_graph(const DeviceContext& vpr_device_ctx, 
-                       VprPbTypeAnnotation& vpr_pb_type_annotation);
+                       VprPbTypeAnnotation& vpr_pb_type_annotation,
+                       const bool& verbose_output);
 
 } /* end namespace openfpga */
 
diff --git a/openfpga/src/annotation/annotate_pb_types.cpp b/openfpga/src/annotation/annotate_pb_types.cpp
index 8dc89251a..d70ab7427 100644
--- a/openfpga/src/annotation/annotate_pb_types.cpp
+++ b/openfpga/src/annotation/annotate_pb_types.cpp
@@ -24,7 +24,8 @@ namespace openfpga {
 static 
 void build_vpr_physical_pb_mode_explicit_annotation(const DeviceContext& vpr_device_ctx, 
                                                     const Arch& openfpga_arch,
-                                                    VprPbTypeAnnotation& vpr_pb_type_annotation) {
+                                                    VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                                    const bool& verbose_output) {
   /* Walk through the pb_type annotation stored in the openfpga arch */
   for (const PbTypeAnnotation& pb_type_annotation : openfpga_arch.pb_type_annotations) {
     /* Since our target is to annotate the physical mode name, 
@@ -82,8 +83,9 @@ void build_vpr_physical_pb_mode_explicit_annotation(const DeviceContext& vpr_dev
       vpr_pb_type_annotation.add_pb_type_physical_mode(target_pb_type, physical_mode);
       
       /* Give a message */
-      VTR_LOG("Annotate pb_type '%s' with physical mode '%s'\n",
-              target_pb_type->name, physical_mode->name);
+      VTR_LOGV(verbose_output,
+               "Annotate pb_type '%s' with physical mode '%s'\n",
+               target_pb_type->name, physical_mode->name);
 
       link_success = true;
       break;
@@ -110,7 +112,8 @@ void build_vpr_physical_pb_mode_explicit_annotation(const DeviceContext& vpr_dev
  *******************************************************************/
 static 
 void rec_infer_vpr_physical_pb_mode_annotation(t_pb_type* cur_pb_type, 
-                                               VprPbTypeAnnotation& vpr_pb_type_annotation) {
+                                               VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                               const bool& verbose_output) {
   /* We do not check any primitive pb_type */
   if (true == is_primitive_pb_type(cur_pb_type)) {
     return;
@@ -128,8 +131,9 @@ void rec_infer_vpr_physical_pb_mode_annotation(t_pb_type* cur_pb_type,
     if (nullptr == vpr_pb_type_annotation.physical_mode(cur_pb_type)) {
       /* Not assigned by explicit annotation, we should infer here */
       vpr_pb_type_annotation.add_pb_type_physical_mode(cur_pb_type, &(cur_pb_type->modes[0]));
-      VTR_LOG("Implicitly infer physical mode '%s' for pb_type '%s'\n",
-              cur_pb_type->modes[0].name, cur_pb_type->name);
+      VTR_LOGV(verbose_output,
+               "Implicitly infer physical mode '%s' for pb_type '%s'\n",
+               cur_pb_type->modes[0].name, cur_pb_type->name);
     }
   } else {
     VTR_ASSERT(1 < cur_pb_type->num_modes);
@@ -151,7 +155,8 @@ void rec_infer_vpr_physical_pb_mode_annotation(t_pb_type* cur_pb_type,
   /* Traverse the pb_type children under the physical mode */
   for (int ichild = 0; ichild < physical_mode->num_pb_type_children; ++ichild) { 
     rec_infer_vpr_physical_pb_mode_annotation(&(physical_mode->pb_type_children[ichild]),
-                                              vpr_pb_type_annotation);
+                                              vpr_pb_type_annotation,
+                                              verbose_output);
   }
 }
 
@@ -169,13 +174,14 @@ void rec_infer_vpr_physical_pb_mode_annotation(t_pb_type* cur_pb_type,
  *******************************************************************/
 static 
 void build_vpr_physical_pb_mode_implicit_annotation(const DeviceContext& vpr_device_ctx, 
-                                                    VprPbTypeAnnotation& vpr_pb_type_annotation) {
+                                                    VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                                    const bool& verbose_output) {
   for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
     /* By pass nullptr for pb_type head */
     if (nullptr == lb_type.pb_type) {
       continue;
     }
-    rec_infer_vpr_physical_pb_mode_annotation(lb_type.pb_type, vpr_pb_type_annotation); 
+    rec_infer_vpr_physical_pb_mode_annotation(lb_type.pb_type, vpr_pb_type_annotation, verbose_output); 
   }
 }
 
@@ -257,7 +263,8 @@ bool pair_operating_and_physical_pb_types(t_pb_type* operating_pb_type,
 static 
 void build_vpr_physical_pb_type_explicit_annotation(const DeviceContext& vpr_device_ctx, 
                                                     const Arch& openfpga_arch,
-                                                    VprPbTypeAnnotation& vpr_pb_type_annotation) {
+                                                    VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                                    const bool& verbose_output) {
   /* Walk through the pb_type annotation stored in the openfpga arch */
   for (const PbTypeAnnotation& pb_type_annotation : openfpga_arch.pb_type_annotations) {
     /* Since our target is to annotate the operating pb_type tp physical pb_type 
@@ -324,8 +331,9 @@ void build_vpr_physical_pb_type_explicit_annotation(const DeviceContext& vpr_dev
                                                        pb_type_annotation, vpr_pb_type_annotation)) {
       
         /* Give a message */
-        VTR_LOG("Annotate operating pb_type '%s' to its physical pb_type '%s'\n",
-                target_op_pb_type->name, target_phy_pb_type->name);
+        VTR_LOGV(verbose_output,
+                 "Annotate operating pb_type '%s' to its physical pb_type '%s'\n",
+                 target_op_pb_type->name, target_phy_pb_type->name);
 
         link_success = true;
         break;
@@ -376,7 +384,8 @@ bool self_pair_physical_pb_types(t_pb_type* physical_pb_type,
  *******************************************************************/
 static 
 void rec_infer_vpr_physical_pb_type_annotation(t_pb_type* cur_pb_type, 
-                                               VprPbTypeAnnotation& vpr_pb_type_annotation) {
+                                               VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                               const bool& verbose_output) {
   /* Physical pb_type is mainly for the primitive pb_type */
   if (true == is_primitive_pb_type(cur_pb_type)) {
     /* If the physical pb_type has been mapped, we can skip it */
@@ -386,8 +395,9 @@ void rec_infer_vpr_physical_pb_type_annotation(t_pb_type* cur_pb_type,
     /* Create the pair here */
     if (true == self_pair_physical_pb_types(cur_pb_type, vpr_pb_type_annotation)) {
       /* Give a message */
-      VTR_LOG("Implicitly infer the physical pb_type for pb_type '%s' itself\n",
-              cur_pb_type->name);
+      VTR_LOGV(verbose_output,
+               "Implicitly infer the physical pb_type for pb_type '%s' itself\n",
+               cur_pb_type->name);
     } else {
       VTR_LOG_ERROR("Unable to infer the physical pb_type for pb_type '%s' itself!\n",
                     cur_pb_type->name);
@@ -403,7 +413,8 @@ void rec_infer_vpr_physical_pb_type_annotation(t_pb_type* cur_pb_type,
   /* Traverse the pb_type children under the physical mode */
   for (int ichild = 0; ichild < physical_mode->num_pb_type_children; ++ichild) { 
     rec_infer_vpr_physical_pb_type_annotation(&(physical_mode->pb_type_children[ichild]),
-                                              vpr_pb_type_annotation);
+                                              vpr_pb_type_annotation, 
+                                              verbose_output);
   }
 }
 
@@ -418,13 +429,14 @@ void rec_infer_vpr_physical_pb_type_annotation(t_pb_type* cur_pb_type,
  *******************************************************************/
 static 
 void build_vpr_physical_pb_type_implicit_annotation(const DeviceContext& vpr_device_ctx, 
-                                                    VprPbTypeAnnotation& vpr_pb_type_annotation) {
+                                                    VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                                    const bool& verbose_output) {
   for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
     /* By pass nullptr for pb_type head */
     if (nullptr == lb_type.pb_type) {
       continue;
     }
-    rec_infer_vpr_physical_pb_type_annotation(lb_type.pb_type, vpr_pb_type_annotation); 
+    rec_infer_vpr_physical_pb_type_annotation(lb_type.pb_type, vpr_pb_type_annotation, verbose_output); 
   }
 }
 
@@ -438,7 +450,8 @@ static
 bool link_physical_pb_port_to_circuit_port(t_pb_type* physical_pb_type, 
                                            const CircuitLibrary& circuit_lib,
                                            const CircuitModelId& circuit_model,
-                                           VprPbTypeAnnotation& vpr_pb_type_annotation) {
+                                           VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                           const bool& verbose_output) {
   bool link_success = true;
   /* Iterate over the pb_ports
    * Note: 
@@ -481,11 +494,12 @@ bool link_physical_pb_port_to_circuit_port(t_pb_type* physical_pb_type,
 
     /* Reach here, it means that mapping should be ok, update the vpr_pb_type_annotation */
     vpr_pb_type_annotation.add_pb_circuit_port(pb_port, circuit_port);
-    VTR_LOG("Bind pb type '%s' port '%s' to circuit model '%s' port '%s'\n",
-            physical_pb_type->name,
-            pb_port->name,
-            circuit_lib.model_name(circuit_model).c_str(),
-            circuit_lib.port_prefix(circuit_port).c_str());
+    VTR_LOGV(verbose_output,
+             "Bind pb type '%s' port '%s' to circuit model '%s' port '%s'\n",
+             physical_pb_type->name,
+             pb_port->name,
+             circuit_lib.model_name(circuit_model).c_str(),
+             circuit_lib.port_prefix(circuit_port).c_str());
   }
 
   return link_success;
@@ -499,7 +513,8 @@ static
 bool link_physical_pb_type_to_circuit_model(t_pb_type* physical_pb_type, 
                                             const CircuitLibrary& circuit_lib,
                                             const PbTypeAnnotation& pb_type_annotation,
-                                            VprPbTypeAnnotation& vpr_pb_type_annotation) {
+                                            VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                            const bool& verbose_output) {
   /* Reach here, we should have valid operating and physical pb_types */
   VTR_ASSERT(nullptr != physical_pb_type);
 
@@ -521,7 +536,8 @@ bool link_physical_pb_type_to_circuit_model(t_pb_type* physical_pb_type,
   }
 
   /* Ensure that the pb_type ports can be matched in the circuit model ports */
-  if (false == link_physical_pb_port_to_circuit_port(physical_pb_type, circuit_lib, circuit_model_id, vpr_pb_type_annotation)) {
+  if (false == link_physical_pb_port_to_circuit_port(physical_pb_type, circuit_lib, circuit_model_id, 
+                                                     vpr_pb_type_annotation, verbose_output)) {
     return false;
   }
 
@@ -539,7 +555,8 @@ bool link_physical_pb_interconnect_to_circuit_model(t_pb_type* physical_pb_type,
                                                     const std::string& interconnect_name,
                                                     const CircuitLibrary& circuit_lib,
                                                     const PbTypeAnnotation& pb_type_annotation,
-                                                    VprPbTypeAnnotation& vpr_pb_type_annotation) {
+                                                    VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                                    const bool& verbose_output) {
   /* The physical pb_type should NOT be a primitive, otherwise it should never contain any interconnect */
   if (true == is_primitive_pb_type(physical_pb_type)) {
     VTR_LOG_ERROR("Link interconnect to circuit model is not allowed for a primitive pb_type '%s'!\n",
@@ -592,7 +609,8 @@ bool link_physical_pb_interconnect_to_circuit_model(t_pb_type* physical_pb_type,
   /* Now the circuit model is valid, update the vpr_pb_type_annotation */
   vpr_pb_type_annotation.add_interconnect_circuit_model(pb_interc, circuit_model_id);
 
-  VTR_LOG("Bind pb_type '%s' physical mode '%s' interconnect '%s' to circuit model '%s'\n",
+  VTR_LOGV(verbose_output,
+           "Bind pb_type '%s' physical mode '%s' interconnect '%s' to circuit model '%s'\n",
            physical_pb_type->name,
            physical_mode->name,
            pb_interc->name,
@@ -613,7 +631,8 @@ bool link_physical_pb_interconnect_to_circuit_model(t_pb_type* physical_pb_type,
 static 
 void link_vpr_pb_type_to_circuit_model_explicit_annotation(const DeviceContext& vpr_device_ctx, 
                                                            const Arch& openfpga_arch,
-                                                           VprPbTypeAnnotation& vpr_pb_type_annotation) {
+                                                           VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                                           const bool& verbose_output) {
   /* Walk through the pb_type annotation stored in the openfpga arch */
   for (const PbTypeAnnotation& pb_type_annotation : openfpga_arch.pb_type_annotations) {
     /* Since our target is to annotate the circuti model for physical pb_type 
@@ -664,11 +683,13 @@ void link_vpr_pb_type_to_circuit_model_explicit_annotation(const DeviceContext&
 
       /* Only try to bind pb_type to circuit model when it is defined by users */
       if (true == link_physical_pb_type_to_circuit_model(target_phy_pb_type, openfpga_arch.circuit_lib,
-                                                         pb_type_annotation, vpr_pb_type_annotation)) {
+                                                         pb_type_annotation, vpr_pb_type_annotation, 
+                                                         verbose_output)) {
         /* Give a message */
-        VTR_LOG("Bind physical pb_type '%s' to its circuit model '%s'\n",
-                target_phy_pb_type->name,
-                openfpga_arch.circuit_lib.model_name(vpr_pb_type_annotation.pb_type_circuit_model(target_phy_pb_type)).c_str());
+        VTR_LOGV(verbose_output,
+                 "Bind physical pb_type '%s' to its circuit model '%s'\n",
+                 target_phy_pb_type->name,
+                 openfpga_arch.circuit_lib.model_name(vpr_pb_type_annotation.pb_type_circuit_model(target_phy_pb_type)).c_str());
 
         link_success = true;
         break;
@@ -697,7 +718,8 @@ void link_vpr_pb_type_to_circuit_model_explicit_annotation(const DeviceContext&
 static 
 void link_vpr_pb_interconnect_to_circuit_model_explicit_annotation(const DeviceContext& vpr_device_ctx, 
                                                                    const Arch& openfpga_arch,
-                                                                   VprPbTypeAnnotation& vpr_pb_type_annotation) {
+                                                                   VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                                                   const bool& verbose_output) {
   /* Walk through the pb_type annotation stored in the openfpga arch */
   for (const PbTypeAnnotation& pb_type_annotation : openfpga_arch.pb_type_annotations) {
     /* Since our target is to annotate the circuti model for physical pb_type 
@@ -749,7 +771,8 @@ void link_vpr_pb_interconnect_to_circuit_model_explicit_annotation(const DeviceC
       /* Only try to bind interconnect to circuit model when it is defined by users */
       for (const std::string& interc_name : pb_type_annotation.interconnect_names()) {
         if (false == link_physical_pb_interconnect_to_circuit_model(target_phy_pb_type, interc_name, openfpga_arch.circuit_lib,
-                                                                    pb_type_annotation, vpr_pb_type_annotation)) {
+                                                                    pb_type_annotation, vpr_pb_type_annotation,
+                                                                    verbose_output)) {
            VTR_LOG_ERROR("Unable to bind pb_type '%s' interconnect '%s' to circuit model '%s'!\n",
                           target_phy_pb_type_names.back().c_str(),
                           interc_name.c_str(),
@@ -789,7 +812,8 @@ void link_vpr_pb_interconnect_to_circuit_model_explicit_annotation(const DeviceC
 static 
 void rec_infer_vpr_pb_interconnect_circuit_model_annotation(t_pb_type* cur_pb_type, 
                                                             const CircuitLibrary& circuit_lib,
-                                                            VprPbTypeAnnotation& vpr_pb_type_annotation) {
+                                                            VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                                            const bool& verbose_output) {
   /* We do not check any primitive pb_type */
   if (true == is_primitive_pb_type(cur_pb_type)) {
     return;
@@ -818,17 +842,19 @@ void rec_infer_vpr_pb_interconnect_circuit_model_annotation(t_pb_type* cur_pb_ty
                     cur_pb_type->name);
     }
     vpr_pb_type_annotation.add_interconnect_circuit_model(pb_interc, default_circuit_model); 
-    VTR_LOG("Implicitly infer a circuit model '%s' for interconnect '%s' under physical mode '%s' of pb_type '%s'\n",
-            circuit_lib.model_name(default_circuit_model).c_str(),
-            pb_interc->name,
-            physical_mode->name, 
-            cur_pb_type->name);
+    VTR_LOGV(verbose_output,
+             "Implicitly infer a circuit model '%s' for interconnect '%s' under physical mode '%s' of pb_type '%s'\n",
+             circuit_lib.model_name(default_circuit_model).c_str(),
+             pb_interc->name,
+             physical_mode->name, 
+             cur_pb_type->name);
   }
 
   /* Traverse the pb_type children under the physical mode */
   for (int ichild = 0; ichild < physical_mode->num_pb_type_children; ++ichild) { 
     rec_infer_vpr_pb_interconnect_circuit_model_annotation(&(physical_mode->pb_type_children[ichild]),
-                                                           circuit_lib, vpr_pb_type_annotation);
+                                                           circuit_lib, vpr_pb_type_annotation,
+                                                           verbose_output);
   }
 }
 
@@ -845,13 +871,14 @@ void rec_infer_vpr_pb_interconnect_circuit_model_annotation(t_pb_type* cur_pb_ty
 static 
 void link_vpr_pb_interconnect_to_circuit_model_implicit_annotation(const DeviceContext& vpr_device_ctx,
                                                                    const CircuitLibrary& circuit_lib,
-                                                                   VprPbTypeAnnotation& vpr_pb_type_annotation) {
+                                                                   VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                                                   const bool& verbose_output) {
   for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
     /* By pass nullptr for pb_type head */
     if (nullptr == lb_type.pb_type) {
       continue;
     }
-    rec_infer_vpr_pb_interconnect_circuit_model_annotation(lb_type.pb_type, circuit_lib, vpr_pb_type_annotation); 
+    rec_infer_vpr_pb_interconnect_circuit_model_annotation(lb_type.pb_type, circuit_lib, vpr_pb_type_annotation, verbose_output); 
   }
 }
 
@@ -889,7 +916,8 @@ bool link_primitive_pb_type_to_mode_bits(t_pb_type* primitive_pb_type,
 static 
 void link_vpr_pb_type_to_mode_bits_explicit_annotation(const DeviceContext& vpr_device_ctx, 
                                                        const Arch& openfpga_arch,
-                                                       VprPbTypeAnnotation& vpr_pb_type_annotation) {
+                                                       VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                                       const bool& verbose_output) {
   /* Walk through the pb_type annotation stored in the openfpga arch */
   for (const PbTypeAnnotation& pb_type_annotation : openfpga_arch.pb_type_annotations) {
     if (true == pb_type_annotation.mode_bits().empty()) {
@@ -947,9 +975,10 @@ void link_vpr_pb_type_to_mode_bits_explicit_annotation(const DeviceContext& vpr_
       if (true == link_primitive_pb_type_to_mode_bits(target_pb_type,
                                                       pb_type_annotation, vpr_pb_type_annotation)) {
         /* Give a message */
-        VTR_LOG("Bind physical pb_type '%s' to mode selection bits '%s'\n",
-                target_pb_type->name,
-                mode_bits_str.c_str());
+        VTR_LOGV(verbose_output,
+                 "Bind physical pb_type '%s' to mode selection bits '%s'\n",
+                 target_pb_type->name,
+                 mode_bits_str.c_str());
 
         link_success = true;
         break;
@@ -973,16 +1002,21 @@ void link_vpr_pb_type_to_mode_bits_explicit_annotation(const DeviceContext& vpr_
  *******************************************************************/
 void annotate_pb_types(const DeviceContext& vpr_device_ctx, 
                        const Arch& openfpga_arch,
-                       VprPbTypeAnnotation& vpr_pb_type_annotation) {
+                       VprPbTypeAnnotation& vpr_pb_type_annotation,
+                       const bool& verbose_output) {
 
   /* Annotate physical mode to pb_type in the VPR pb_type graph */
   VTR_LOG("\n");
-  VTR_LOG("Building annotation for physical modes in pb_type...\n");
+  VTR_LOG("Building annotation for physical modes in pb_type...");
+  VTR_LOGV(verbose_output, "\n");
   build_vpr_physical_pb_mode_explicit_annotation(vpr_device_ctx, openfpga_arch,
-                                                 vpr_pb_type_annotation);
+                                                 vpr_pb_type_annotation,
+                                                 verbose_output);
 
   build_vpr_physical_pb_mode_implicit_annotation(vpr_device_ctx,
-                                                 vpr_pb_type_annotation);
+                                                 vpr_pb_type_annotation,
+                                                 verbose_output);
+  VTR_LOG("Done\n");
 
   check_vpr_physical_pb_mode_annotation(vpr_device_ctx, 
                                         const_cast<const VprPbTypeAnnotation&>(vpr_pb_type_annotation));
@@ -993,8 +1027,10 @@ void annotate_pb_types(const DeviceContext& vpr_device_ctx,
    */
   VTR_LOG("\n");
   VTR_LOG("Building annotation about physical types for pb_type interconnection...");
+  VTR_LOGV(verbose_output, "\n");
   annotate_pb_graph_interconnect_physical_type(vpr_device_ctx, 
-                                               vpr_pb_type_annotation);
+                                               vpr_pb_type_annotation,
+                                               verbose_output);
   VTR_LOG("Done\n");
 
   /* Annotate physical pb_types to operating pb_type in the VPR pb_type graph 
@@ -1004,12 +1040,16 @@ void annotate_pb_types(const DeviceContext& vpr_device_ctx,
    * - physical_pin_rotate_offset
    */
   VTR_LOG("\n");
-  VTR_LOG("Building annotation between operating and physical pb_types...\n");
+  VTR_LOG("Building annotation between operating and physical pb_types...");
+  VTR_LOGV(verbose_output, "\n");
   build_vpr_physical_pb_type_explicit_annotation(vpr_device_ctx, openfpga_arch,
-                                                 vpr_pb_type_annotation);
+                                                 vpr_pb_type_annotation,
+                                                 verbose_output);
 
   build_vpr_physical_pb_type_implicit_annotation(vpr_device_ctx,
-                                                 vpr_pb_type_annotation);
+                                                 vpr_pb_type_annotation,
+                                                 verbose_output);
+  VTR_LOG("Done\n");
 
   check_vpr_physical_pb_type_annotation(vpr_device_ctx, 
                                         const_cast<const VprPbTypeAnnotation&>(vpr_pb_type_annotation));
@@ -1019,21 +1059,33 @@ void annotate_pb_types(const DeviceContext& vpr_device_ctx,
    * - interconnect of physical pb_type to circuit model 
    */
   VTR_LOG("\n");
-  VTR_LOG("Building annotation between physical pb_types and circuit models...\n");
+  VTR_LOG("Building annotation between physical pb_types and circuit models...");
+  VTR_LOGV(verbose_output, "\n");
   link_vpr_pb_type_to_circuit_model_explicit_annotation(vpr_device_ctx, openfpga_arch,
-                                                        vpr_pb_type_annotation);
+                                                        vpr_pb_type_annotation,
+                                                        verbose_output);
+
   link_vpr_pb_interconnect_to_circuit_model_explicit_annotation(vpr_device_ctx, openfpga_arch,
-                                                                vpr_pb_type_annotation);
+                                                                vpr_pb_type_annotation,
+                                                                verbose_output);
+
   link_vpr_pb_interconnect_to_circuit_model_implicit_annotation(vpr_device_ctx, openfpga_arch.circuit_lib,
-                                                                vpr_pb_type_annotation);
+                                                                vpr_pb_type_annotation,
+                                                                verbose_output);
+  VTR_LOG("Done\n");
+
   check_vpr_pb_type_circuit_model_annotation(vpr_device_ctx, openfpga_arch.circuit_lib,
                                              const_cast<const VprPbTypeAnnotation&>(vpr_pb_type_annotation));
 
   /* Link physical pb_type to mode_bits */
   VTR_LOG("\n");
-  VTR_LOG("Building annotation between physical pb_types and mode selection bits...\n");
+  VTR_LOG("Building annotation between physical pb_types and mode selection bits...");
+  VTR_LOGV(verbose_output, "\n");
   link_vpr_pb_type_to_mode_bits_explicit_annotation(vpr_device_ctx, openfpga_arch,
-                                                    vpr_pb_type_annotation);
+                                                    vpr_pb_type_annotation,
+                                                    verbose_output);
+  VTR_LOG("Done\n");
+
   check_vpr_pb_type_mode_bits_annotation(vpr_device_ctx, openfpga_arch.circuit_lib,
                                          const_cast<const VprPbTypeAnnotation&>(vpr_pb_type_annotation));
 
diff --git a/openfpga/src/annotation/annotate_pb_types.h b/openfpga/src/annotation/annotate_pb_types.h
index 494b2c771..4be50aed6 100644
--- a/openfpga/src/annotation/annotate_pb_types.h
+++ b/openfpga/src/annotation/annotate_pb_types.h
@@ -17,7 +17,8 @@ namespace openfpga {
 
 void annotate_pb_types(const DeviceContext& vpr_device_ctx, 
                        const Arch& openfpga_arch,
-                       VprPbTypeAnnotation& vpr_pb_type_annotation);
+                       VprPbTypeAnnotation& vpr_pb_type_annotation,
+                       const bool& verbose_output);
 
 } /* end namespace openfpga */
 
diff --git a/openfpga/src/base/openfpga_link_arch.cpp b/openfpga/src/base/openfpga_link_arch.cpp
index e6762485e..8f7b5b54d 100644
--- a/openfpga/src/base/openfpga_link_arch.cpp
+++ b/openfpga/src/base/openfpga_link_arch.cpp
@@ -27,17 +27,21 @@ namespace openfpga {
  * - physical pb_graph nodes and pb_graph pins
  * - circuit models for global routing architecture
  *******************************************************************/
-void link_arch(OpenfpgaContext& openfpga_context) {
+void link_arch(OpenfpgaContext& openfpga_context,
+               const Command& cmd, const CommandContext& cmd_context) { 
 
   vtr::ScopedStartFinishTimer timer("Link OpenFPGA architecture to VPR architecture");
 
+  CommandOptionId opt_verbose = cmd.option("verbose");
+
   /* Annotate pb_type graphs
    * - physical pb_type
    * - mode selection bits for pb_type and pb interconnect
    * - circuit models for pb_type and pb interconnect
    */
   annotate_pb_types(g_vpr_ctx.device(), openfpga_context.arch(),
-                    openfpga_context.mutable_vpr_pb_type_annotation());
+                    openfpga_context.mutable_vpr_pb_type_annotation(),
+                    cmd_context.option_enable(cmd, opt_verbose));
 
   /* Annotate pb_graph_nodes
    * - Give unique index to each node in the same type
@@ -45,7 +49,8 @@ void link_arch(OpenfpgaContext& openfpga_context) {
    * - Bind pins from operating pb_graph_node to their physical pb_graph_node pins
    */
   annotate_pb_graph(g_vpr_ctx.device(),
-                    openfpga_context.mutable_vpr_pb_type_annotation());
+                    openfpga_context.mutable_vpr_pb_type_annotation(),
+                    cmd_context.option_enable(cmd, opt_verbose));
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_link_arch.h b/openfpga/src/base/openfpga_link_arch.h
index 3775ee789..742c29541 100644
--- a/openfpga/src/base/openfpga_link_arch.h
+++ b/openfpga/src/base/openfpga_link_arch.h
@@ -4,6 +4,8 @@
 /********************************************************************
  * Include header files that are required by function declaration
  *******************************************************************/
+#include "command.h"
+#include "command_context.h"
 #include "openfpga_context.h"
 
 /********************************************************************
@@ -13,7 +15,8 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-void link_arch(OpenfpgaContext& openfpga_context); 
+void link_arch(OpenfpgaContext& openfpga_context, 
+               const Command& cmd, const CommandContext& cmd_context); 
 
 } /* end namespace openfpga */
 
diff --git a/openfpga/src/base/openfpga_setup_command.cpp b/openfpga/src/base/openfpga_setup_command.cpp
index 9a3eee970..ef392a4c4 100644
--- a/openfpga/src/base/openfpga_setup_command.cpp
+++ b/openfpga/src/base/openfpga_setup_command.cpp
@@ -52,6 +52,8 @@ void add_openfpga_setup_commands(openfpga::Shell<OpenfpgaContext>& shell) {
    * Command 'link_openfpga_arch' 
    */
   Command shell_cmd_link_openfpga_arch("link_openfpga_arch");
+  /* Add an option '--verbose' */
+  shell_cmd_link_openfpga_arch.add_option("verbose", false, "Show verbose outputs");
   
   /* Add command 'link_openfpga_arch' to the Shell */
   ShellCommandId shell_cmd_link_openfpga_arch_id = shell.add_command(shell_cmd_link_openfpga_arch, "Bind OpenFPGA architecture to VPR");
@@ -67,7 +69,7 @@ void add_openfpga_setup_commands(openfpga::Shell<OpenfpgaContext>& shell) {
    * Command 'check_netlist_naming_conflict'
    */ 
   Command shell_cmd_check_netlist_naming_conflict("check_netlist_naming_conflict");
-  /* Add an option '--correction' */
+  /* Add an option '--fix' */
   shell_cmd_check_netlist_naming_conflict.add_option("fix", false, "Apply correction to any conflicts found");
   /* Add an option '--report' */
   CommandOptionId check_netlist_opt_rpt = shell_cmd_check_netlist_naming_conflict.add_option("report", false, "Output a report file about what any correction applied");

From fb0bcd7a48dd1f70d1ad47c99edf13a8509cdead Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 31 Jan 2020 12:29:50 -0700
Subject: [PATCH 060/645] create rr_graph library to enforce unit test on the
 new data structures as well as compare to legacy rr_node

---
 libs/CMakeLists.txt                           |   1 +
 libs/librrgraph/CMakeLists.txt                |  35 +
 .../librrgraph/src}/check_rr_graph_obj.cpp    |  19 +-
 .../librrgraph/src}/check_rr_graph_obj.h      |   0
 .../librrgraph/src}/rr_graph_fwd.h            |   0
 .../librrgraph/src}/rr_graph_obj.cpp          | 631 ++++++++++--------
 .../librrgraph/src}/rr_graph_obj.h            | 171 +++--
 .../librrgraph/src}/rr_graph_obj_utils.h      |  26 +
 libs/librrgraph/src/rr_graph_types.h          |  43 ++
 .../librrgraph/src}/rr_graph_util.cpp         |   0
 .../librrgraph/src}/rr_graph_util.h           |   0
 libs/librrgraph/test/test_rr_graph.cpp        |   8 +
 libs/libvtrutil/src/vtr_geometry.tpp          |   6 +
 vpr/CMakeLists.txt                            |   1 +
 vpr/src/base/vpr_types.h                      |  32 +-
 15 files changed, 612 insertions(+), 361 deletions(-)
 create mode 100644 libs/librrgraph/CMakeLists.txt
 rename {vpr/src/device => libs/librrgraph/src}/check_rr_graph_obj.cpp (94%)
 rename {vpr/src/device => libs/librrgraph/src}/check_rr_graph_obj.h (100%)
 rename {vpr/src/device => libs/librrgraph/src}/rr_graph_fwd.h (100%)
 rename {vpr/src/device => libs/librrgraph/src}/rr_graph_obj.cpp (65%)
 rename {vpr/src/device => libs/librrgraph/src}/rr_graph_obj.h (85%)
 rename {vpr/src/device => libs/librrgraph/src}/rr_graph_obj_utils.h (87%)
 create mode 100644 libs/librrgraph/src/rr_graph_types.h
 rename {vpr/src/device => libs/librrgraph/src}/rr_graph_util.cpp (100%)
 rename {vpr/src/device => libs/librrgraph/src}/rr_graph_util.h (100%)
 create mode 100644 libs/librrgraph/test/test_rr_graph.cpp

diff --git a/libs/CMakeLists.txt b/libs/CMakeLists.txt
index 8d09c541d..a85d179f8 100644
--- a/libs/CMakeLists.txt
+++ b/libs/CMakeLists.txt
@@ -5,6 +5,7 @@ add_subdirectory(EXTERNAL)
 #  Only add warn flags for VPR internal libraries.
 #add_compile_options(${WARN_FLAGS})
 add_subdirectory(libarchfpga)
+add_subdirectory(librrgraph)
 add_subdirectory(libvtrutil)
 add_subdirectory(liblog)
 add_subdirectory(libpugiutil)
diff --git a/libs/librrgraph/CMakeLists.txt b/libs/librrgraph/CMakeLists.txt
new file mode 100644
index 000000000..52f46a170
--- /dev/null
+++ b/libs/librrgraph/CMakeLists.txt
@@ -0,0 +1,35 @@
+cmake_minimum_required(VERSION 3.9)
+
+project("librrgraph")
+
+file(GLOB_RECURSE EXEC_SOURCE test/test_rr_graph.cpp)
+file(GLOB_RECURSE LIB_SOURCES src/*.cpp)
+file(GLOB_RECURSE LIB_HEADERS src/*.h)
+files_to_dirs(LIB_HEADERS LIB_INCLUDE_DIRS)
+
+#Remove test executable from library
+list(REMOVE_ITEM LIB_SOURCES ${EXEC_SOURCE})
+
+#Create the library
+add_library(librrgraph STATIC
+             ${LIB_HEADERS}
+             ${LIB_SOURCES})
+target_include_directories(librrgraph PUBLIC ${LIB_INCLUDE_DIRS})
+set_target_properties(librrgraph PROPERTIES PREFIX "") #Avoid extra 'lib' prefix
+
+#Specify link-time dependancies
+target_link_libraries(librrgraph
+                      libarchfpga
+                      libvtrutil)
+
+#Create the test executable
+add_executable(test_rr_graph ${EXEC_SOURCE})
+target_link_libraries(test_rr_graph librrgraph)
+
+#Supress IPO link warnings if IPO is enabled
+#get_target_property(READ_ARCH_USES_IPO read_arch_openfpga INTERPROCEDURAL_OPTIMIZATION)
+#if (READ_ARCH_USES_IPO)
+#    set_target_properties(read_arch_openfpga PROPERTIES LINK_FLAGS ${IPO_LINK_WARN_SUPRESS_FLAGS})
+#endif()
+
+#install(TARGETS libarchopenfpga read_arch_openfpga DESTINATION bin)
diff --git a/vpr/src/device/check_rr_graph_obj.cpp b/libs/librrgraph/src/check_rr_graph_obj.cpp
similarity index 94%
rename from vpr/src/device/check_rr_graph_obj.cpp
rename to libs/librrgraph/src/check_rr_graph_obj.cpp
index 253092fb7..69c772fcb 100644
--- a/vpr/src/device/check_rr_graph_obj.cpp
+++ b/libs/librrgraph/src/check_rr_graph_obj.cpp
@@ -107,7 +107,7 @@ static bool check_rr_graph_source_nodes(const RRGraph& rr_graph) {
         }
     }
 
-    return invalid_sources;
+    return !invalid_sources;
 }
 
 /*********************************************************************** 
@@ -136,7 +136,7 @@ static bool check_rr_graph_sink_nodes(const RRGraph& rr_graph) {
         }
     }
 
-    return invalid_sinks;
+    return !invalid_sinks;
 }
 
 /*********************************************************************** 
@@ -153,48 +153,43 @@ static bool check_rr_graph_sink_nodes(const RRGraph& rr_graph) {
  * will work properly.
  **********************************************************************/
 bool check_rr_graph(const RRGraph& rr_graph) {
-    bool check_flag = true;
     size_t num_err = 0;
 
     if (false == check_rr_graph_duplicated_edges(rr_graph)) {
         VTR_LOG_WARN("Fail in checking duplicated edges !\n");
-        check_flag = false;
         num_err++;
     }
 
     if (false == check_rr_graph_dangling_nodes(rr_graph)) {
         VTR_LOG_WARN("Fail in checking dangling nodes !\n");
-        check_flag = false;
         num_err++;
     }
 
     if (false == check_rr_graph_source_nodes(rr_graph)) {
         VTR_LOG_WARN("Fail in checking source nodes!\n");
-        check_flag = false;
         num_err++;
     }
 
     if (false == check_rr_graph_sink_nodes(rr_graph)) {
         VTR_LOG_WARN("Fail in checking sink nodes!\n");
-        check_flag = false;
         num_err++;
     }
 
     if (false == check_rr_graph_source_nodes(rr_graph)) {
         VTR_LOG_WARN("Fail in checking source nodes!\n");
-        check_flag = false;
         num_err++;
     }
 
     if (false == check_rr_graph_sink_nodes(rr_graph)) {
         VTR_LOG_WARN("Fail in checking sink nodes!\n");
-        check_flag = false;
         num_err++;
     }
 
     /* Error out if there is any fatal errors found */
-    VTR_LOG_WARN("Checked Routing Resource graph with %d errors !\n",
-                 num_err);
+    if (0 < num_err) {
+        VTR_LOG_WARN("Checked Routing Resource graph with %d errors !\n",
+                     num_err);
+    }
 
-    return check_flag;
+    return (0 == num_err);
 }
diff --git a/vpr/src/device/check_rr_graph_obj.h b/libs/librrgraph/src/check_rr_graph_obj.h
similarity index 100%
rename from vpr/src/device/check_rr_graph_obj.h
rename to libs/librrgraph/src/check_rr_graph_obj.h
diff --git a/vpr/src/device/rr_graph_fwd.h b/libs/librrgraph/src/rr_graph_fwd.h
similarity index 100%
rename from vpr/src/device/rr_graph_fwd.h
rename to libs/librrgraph/src/rr_graph_fwd.h
diff --git a/vpr/src/device/rr_graph_obj.cpp b/libs/librrgraph/src/rr_graph_obj.cpp
similarity index 65%
rename from vpr/src/device/rr_graph_obj.cpp
rename to libs/librrgraph/src/rr_graph_obj.cpp
index 0cd9c49e8..2df4a77bf 100644
--- a/vpr/src/device/rr_graph_obj.cpp
+++ b/libs/librrgraph/src/rr_graph_obj.cpp
@@ -7,6 +7,7 @@
 #include <map>
 #include <limits>
 
+#include "vtr_geometry.h"
 #include "vtr_vector_map.h"
 #include "vtr_log.h"
 #include "vtr_util.h"
@@ -14,13 +15,26 @@
 #include "rr_graph_obj.h"
 #include "rr_graph_obj_utils.h"
 
-//Accessors
-RRGraph::node_range RRGraph::nodes() const {
-    return vtr::make_range(node_ids_.begin(), node_ids_.end());
+/********************************************************************
+ * Constructors
+ *******************************************************************/
+RRGraph::RRGraph()
+    : num_nodes_(0)
+    , num_edges_(0) {
+    //Pass
 }
 
-RRGraph::edge_range RRGraph::edges() const {
-    return vtr::make_range(edge_ids_.begin(), edge_ids_.end());
+/********************************************************************
+ * Accessors
+ *******************************************************************/
+RRGraph::lazy_node_range RRGraph::nodes() const {
+    return vtr::make_range(lazy_node_iterator(RRNodeId(0), invalid_node_ids_),
+                           lazy_node_iterator(RRNodeId(num_nodes_), invalid_node_ids_));
+}
+
+RRGraph::lazy_edge_range RRGraph::edges() const {
+    return vtr::make_range(lazy_edge_iterator(RREdgeId(0), invalid_edge_ids_),
+                           lazy_edge_iterator(RREdgeId(num_edges_), invalid_edge_ids_));
 }
 
 RRGraph::switch_range RRGraph::switches() const {
@@ -117,11 +131,11 @@ vtr::Point<short> RRGraph::node_end_coordinate(const RRNodeId& node) const {
 }
 
 short RRGraph::node_fan_in(const RRNodeId& node) const {
-    return node_in_edges(node).size();
+    return node_num_in_edges_[node];
 }
 
 short RRGraph::node_fan_out(const RRNodeId& node) const {
-    return node_out_edges(node).size();
+    return node_num_out_edges_[node];
 }
 
 short RRGraph::node_capacity(const RRNodeId& node) const {
@@ -189,118 +203,65 @@ RRSegmentId RRGraph::node_segment(const RRNodeId& node) const {
     return node_segments_[node];
 }
 
-/* 
- * Get the number of configurable input edges of a node
- * TODO: we would use the node_num_configurable_in_edges() 
- * when the rr_graph edges have been partitioned 
- * This can avoid unneccessary walkthrough
- */
-short RRGraph::node_num_configurable_in_edges(const RRNodeId& node) const {
-    return node_configurable_in_edges(node).size();
+RRGraph::edge_range RRGraph::node_edges(const RRNodeId& node) const {
+    VTR_ASSERT_SAFE(valid_node_id(node));
+
+    return vtr::make_range(node_edges_[node].get(),
+                           node_edges_[node].get() + node_num_in_edges_[node] + node_num_out_edges_[node]);
 }
 
-/* 
- * Get the number of configurable output edges of a node
- * TODO: we would use the node_num_configurable_out_edges() 
- * when the rr_graph edges have been partitioned 
- * This can avoid unneccessary walkthrough
- */
-short RRGraph::node_num_configurable_out_edges(const RRNodeId& node) const {
-    return node_configurable_out_edges(node).size();
+RRGraph::edge_range RRGraph::node_in_edges(const RRNodeId& node) const {
+    VTR_ASSERT_SAFE(valid_node_id(node));
+
+    return vtr::make_range(node_edges_[node].get(),
+                           node_edges_[node].get() + node_num_in_edges_[node]);
 }
 
-/* 
- * Get the number of non-configurable input edges of a node
- * TODO: we would use the node_num_configurable_in_edges() 
- * when the rr_graph edges have been partitioned 
- * This can avoid unneccessary walkthrough
- */
-short RRGraph::node_num_non_configurable_in_edges(const RRNodeId& node) const {
-    return node_non_configurable_in_edges(node).size();
-}
+RRGraph::edge_range RRGraph::node_out_edges(const RRNodeId& node) const {
+    VTR_ASSERT_SAFE(valid_node_id(node));
 
-/* 
- * Get the number of non-configurable output edges of a node
- * TODO: we would use the node_num_configurable_out_edges() 
- * when the rr_graph edges have been partitioned 
- * This can avoid unneccessary walkthrough
- */
-short RRGraph::node_num_non_configurable_out_edges(const RRNodeId& node) const {
-    return node_non_configurable_out_edges(node).size();
+    return vtr::make_range((node_edges_[node].get() + node_num_in_edges_[node]),
+                           (node_edges_[node].get() + node_num_in_edges_[node]) + node_num_out_edges_[node]);
 }
 
 /* Get the list of configurable edges from the input edges of a given node 
  * And return the range(iterators) of the list 
  */
 RRGraph::edge_range RRGraph::node_configurable_in_edges(const RRNodeId& node) const {
-    /* Make sure we will access a valid node */
     VTR_ASSERT_SAFE(valid_node_id(node));
 
-    /* By default the configurable edges will be stored at the first part of the edge list (0 to XX) */
-    auto begin = node_in_edges(node).begin();
-
-    /* By default the non-configurable edges will be stored at second part of the edge list (XX to end) */
-    auto end = node_in_edges(node).end() - node_num_non_configurable_in_edges_[node];
-
-    return vtr::make_range(begin, end);
+    return vtr::make_range(node_edges_[node].get(),
+                           node_edges_[node].get() + node_num_in_edges_[node] - node_num_non_configurable_in_edges_[node]);
 }
 
-/* Get the list of configurable edges from the input edges of a given node 
+/* Get the list of non configurable edges from the input edges of a given node 
  * And return the range(iterators) of the list 
  */
 RRGraph::edge_range RRGraph::node_non_configurable_in_edges(const RRNodeId& node) const {
-    /* Make sure we will access a valid node */
     VTR_ASSERT_SAFE(valid_node_id(node));
 
-    /* By default the configurable edges will be stored at the first part of the edge list (0 to XX) */
-    auto begin = node_in_edges(node).end() - node_num_non_configurable_in_edges_[node];
-
-    /* By default the non-configurable edges will be stored at second part of the edge list (XX to end) */
-    auto end = node_in_edges(node).end();
-
-    return vtr::make_range(begin, end);
+    return vtr::make_range(node_edges_[node].get() + node_num_in_edges_[node] - node_num_non_configurable_in_edges_[node],
+                           node_edges_[node].get() + node_num_in_edges_[node]);
 }
 
-/* Get the list of configurable edges from the input edges of a given node 
+/* Get the list of configurable edges from the output edges of a given node 
  * And return the range(iterators) of the list 
  */
 RRGraph::edge_range RRGraph::node_configurable_out_edges(const RRNodeId& node) const {
-    /* Make sure we will access a valid node */
     VTR_ASSERT_SAFE(valid_node_id(node));
 
-    /* By default the configurable edges will be stored at the first part of the edge list (0 to XX) */
-    auto begin = node_out_edges(node).begin();
-
-    /* By default the non-configurable edges will be stored at second part of the edge list (XX to end) */
-    auto end = node_out_edges(node).end() - node_num_non_configurable_out_edges_[node];
-
-    return vtr::make_range(begin, end);
+    return vtr::make_range((node_edges_[node].get() + node_num_in_edges_[node]),
+                           (node_edges_[node].get() + node_num_in_edges_[node]) + node_num_out_edges_[node] - node_num_non_configurable_out_edges_[node]);
 }
 
-/* Get the list of configurable edges from the input edges of a given node 
+/* Get the list of non configurable edges from the output edges of a given node 
  * And return the range(iterators) of the list 
  */
 RRGraph::edge_range RRGraph::node_non_configurable_out_edges(const RRNodeId& node) const {
-    /* Make sure we will access a valid node */
     VTR_ASSERT_SAFE(valid_node_id(node));
 
-    /* By default the configurable edges will be stored at the first part of the edge list (0 to XX) */
-    auto begin = node_out_edges(node).end() - node_num_non_configurable_out_edges_[node];
-
-    /* By default the non-configurable edges will be stored at second part of the edge list (XX to end) */
-    auto end = node_out_edges(node).end();
-
-    return vtr::make_range(begin, end);
-}
-
-RRGraph::edge_range RRGraph::node_out_edges(const RRNodeId& node) const {
-    VTR_ASSERT_SAFE(valid_node_id(node));
-    return vtr::make_range(node_out_edges_[node].begin(), node_out_edges_[node].end());
-}
-
-RRGraph::edge_range RRGraph::node_in_edges(const RRNodeId& node) const {
-    VTR_ASSERT_SAFE(valid_node_id(node));
-    return vtr::make_range(node_in_edges_[node].begin(), node_in_edges_[node].end());
+    return vtr::make_range((node_edges_[node].get() + node_num_in_edges_[node]) + node_num_out_edges_[node] - node_num_non_configurable_out_edges_[node],
+                           (node_edges_[node].get() + node_num_in_edges_[node]) + node_num_out_edges_[node]);
 }
 
 //Edge attributes
@@ -391,22 +352,22 @@ RRNodeId RRGraph::find_node(const short& x, const short& y, const t_rr_type& typ
     size_t iside = side;
 
     /* Check if x, y, type and ptc, side is valid */
-    if ((x < 0)                                     /* See if x is smaller than the index of first element */
-        || (size_t(x) > node_lookup_.size() - 1)) { /* See if x is large than the index of last element */
+    if ((x < 0)                                          /* See if x is smaller than the index of first element */
+        || (size_t(x) > node_lookup_.dim_size(0) - 1)) { /* See if x is large than the index of last element */
         /* Return a zero range! */
         return RRNodeId::INVALID();
     }
 
     /* Check if x, y, type and ptc, side is valid */
-    if ((y < 0)                                        /* See if y is smaller than the index of first element */
-        || (size_t(y) > node_lookup_[x].size() - 1)) { /* See if y is large than the index of last element */
+    if ((y < 0)                                          /* See if y is smaller than the index of first element */
+        || (size_t(y) > node_lookup_.dim_size(1) - 1)) { /* See if y is large than the index of last element */
         /* Return a zero range! */
         return RRNodeId::INVALID();
     }
 
     /* Check if x, y, type and ptc, side is valid */
     /* itype is always larger than -1, we can skip checking */
-    if (itype > node_lookup_[x][y].size() - 1) { /* See if type is large than the index of last element */
+    if (itype > node_lookup_.dim_size(2) - 1) { /* See if type is large than the index of last element */
         /* Return a zero range! */
         return RRNodeId::INVALID();
     }
@@ -436,21 +397,21 @@ short RRGraph::chan_num_tracks(const short& x, const short& y, const t_rr_type&
     initialize_fast_node_lookup();
 
     /* Check if x, y, type and ptc is valid */
-    if ((x < 0)                                     /* See if x is smaller than the index of first element */
-        || (size_t(x) > node_lookup_.size() - 1)) { /* See if x is large than the index of last element */
+    if ((x < 0)                                          /* See if x is smaller than the index of first element */
+        || (size_t(x) > node_lookup_.dim_size(0) - 1)) { /* See if x is large than the index of last element */
         /* Return a zero range! */
         return 0;
     }
 
     /* Check if x, y, type and ptc is valid */
-    if ((y < 0)                                        /* See if y is smaller than the index of first element */
-        || (size_t(y) > node_lookup_[x].size() - 1)) { /* See if y is large than the index of last element */
+    if ((y < 0)                                          /* See if y is smaller than the index of first element */
+        || (size_t(y) > node_lookup_.dim_size(1) - 1)) { /* See if y is large than the index of last element */
         /* Return a zero range! */
         return 0;
     }
 
     /* Check if x, y, type and ptc is valid */
-    if ((size_t(type) > node_lookup_[x][y].size() - 1)) { /* See if type is large than the index of last element */
+    if ((size_t(type) > node_lookup_.dim_size(2) - 1)) { /* See if type is large than the index of last element */
         /* Return a zero range! */
         return 0;
     }
@@ -488,15 +449,20 @@ bool RRGraph::validate_node_segment(const RRNodeId& node) const {
 /* Check if the segment id of every node is in range */
 bool RRGraph::validate_node_segments() const {
     bool all_valid = true;
-    for (auto node : nodes()) {
-        if (true == validate_node_segment(node)) {
+    for (size_t id = 0; id < num_nodes_; ++id) {
+        /* Try to find if this is an invalid id or not */
+        if (!valid_node_id(RRNodeId(id))) {
+            /* Skip this id */
+            continue;
+        }
+        if (true == validate_node_segment(RRNodeId(id))) {
             continue;
         }
         /* Reach here it means we find an invalid segment id */
         all_valid = false;
         /* Print a warning! */
         VTR_LOG_WARN("Node %d has an invalid segment id (%d)!\n",
-                     size_t(node), size_t(node_segment(node)));
+                     id, size_t(node_segment(RRNodeId(id))));
     }
     return all_valid;
 }
@@ -510,15 +476,20 @@ bool RRGraph::validate_edge_switch(const RREdgeId& edge) const {
 /* Check if the switch id of every edge is in range */
 bool RRGraph::validate_edge_switches() const {
     bool all_valid = true;
-    for (auto edge : edges()) {
-        if (true == validate_edge_switch(edge)) {
+    for (size_t id = 0; id < num_edges_; ++id) {
+        /* Try to find if this is an invalid id or not */
+        if (!valid_edge_id(RREdgeId(id))) {
+            /* Skip this id */
+            continue;
+        }
+        if (true == validate_edge_switch(RREdgeId(id))) {
             continue;
         }
         /* Reach here it means we find an invalid segment id */
         all_valid = false;
         /* Print a warning! */
         VTR_LOG_WARN("Edge %d has an invalid switch id (%d)!\n",
-                     size_t(edge), size_t(edge_switch(edge)));
+                     id, size_t(edge_switch(RREdgeId(id))));
     }
     return all_valid;
 }
@@ -622,8 +593,13 @@ bool RRGraph::validate_node_edges(const RRNodeId& node) const {
 /* check if all the nodes' input edges are valid */
 bool RRGraph::validate_nodes_in_edges() const {
     bool all_valid = true;
-    for (auto node : nodes()) {
-        if (true == validate_node_in_edges(node)) {
+    for (size_t id = 0; id < num_nodes_; ++id) {
+        /* Try to find if this is an invalid id or not */
+        if (!valid_node_id(RRNodeId(id))) {
+            /* Skip this id */
+            continue;
+        }
+        if (true == validate_node_in_edges(RRNodeId(id))) {
             continue;
         }
         /* Reach here, it means there is something wrong! 
@@ -637,8 +613,13 @@ bool RRGraph::validate_nodes_in_edges() const {
 /* check if all the nodes' output edges are valid */
 bool RRGraph::validate_nodes_out_edges() const {
     bool all_valid = true;
-    for (auto node : nodes()) {
-        if (true == validate_node_out_edges(node)) {
+    for (size_t id = 0; id < num_nodes_; ++id) {
+        /* Try to find if this is an invalid id or not */
+        if (!valid_node_id(RRNodeId(id))) {
+            /* Skip this id */
+            continue;
+        }
+        if (true == validate_node_out_edges(RRNodeId(id))) {
             continue;
         }
         /* Reach here, it means there is something wrong! 
@@ -676,15 +657,20 @@ bool RRGraph::validate_edge_sink_node(const RREdgeId& edge) const {
 /* Check if source nodes of a edge are all valid */
 bool RRGraph::validate_edge_src_nodes() const {
     bool all_valid = true;
-    for (auto edge : edges()) {
-        if (true == validate_edge_src_node(edge)) {
+    for (size_t id = 0; id < num_edges_; ++id) {
+        /* Try to find if this is an invalid id or not */
+        if (!valid_edge_id(RREdgeId(id))) {
+            /* Skip this id */
+            continue;
+        }
+        if (true == validate_edge_src_node(RREdgeId(id))) {
             continue;
         }
         /* Reach here, it means there is something wrong! 
          * Print a warning  
          */
         VTR_LOG_WARN("Edge %d has a invalid source node %d!\n",
-                     size_t(edge), size_t(edge_src_node(edge)));
+                     id, size_t(edge_src_node(RREdgeId(id))));
         all_valid = false;
     }
     return all_valid;
@@ -693,15 +679,20 @@ bool RRGraph::validate_edge_src_nodes() const {
 /* Check if source nodes of a edge are all valid */
 bool RRGraph::validate_edge_sink_nodes() const {
     bool all_valid = true;
-    for (auto edge : edges()) {
-        if (true == validate_edge_sink_node(edge)) {
+    for (size_t id = 0; id < num_edges_; ++id) {
+        /* Try to find if this is an invalid id or not */
+        if (!valid_edge_id(RREdgeId(id))) {
+            /* Skip this id */
+            continue;
+        }
+        if (true == validate_edge_sink_node(RREdgeId(id))) {
             continue;
         }
         /* Reach here, it means there is something wrong! 
          * Print a warning  
          */
         VTR_LOG_WARN("Edge %d has a invalid sink node %d!\n",
-                     size_t(edge), size_t(edge_sink_node(edge)));
+                     id, size_t(edge_sink_node(RREdgeId(id))));
         all_valid = false;
     }
     return all_valid;
@@ -714,7 +705,6 @@ bool RRGraph::validate_edge_sink_nodes() const {
  * Warnings are thrown if optional checking fails
  */
 bool RRGraph::validate() const {
-    bool check_flag = true;
     size_t num_err = 0;
 
     initialize_fast_node_lookup();
@@ -724,34 +714,32 @@ bool RRGraph::validate() const {
      */
     if (false == validate_sizes()) {
         VTR_LOG_WARN("Fail in validating node- and edge-related vector sizes!\n");
-        check_flag = false;
         num_err++;
     }
 
     /* Fundamental check */
     if (false == validate_nodes_edges()) {
         VTR_LOG_WARN("Fail in validating edges connected to each node!\n");
-        check_flag = false;
         num_err++;
     }
 
     if (false == validate_node_segments()) {
         VTR_LOG_WARN("Fail in validating segment IDs of nodes !\n");
-        check_flag = false;
         num_err++;
     }
 
     if (false == validate_edge_switches()) {
         VTR_LOG_WARN("Fail in validating switch IDs of edges !\n");
-        check_flag = false;
         num_err++;
     }
 
     /* Error out if there is any fatal errors found */
-    VTR_LOG_ERROR("Routing Resource graph is not valid due to %d fatal errors !\n",
-                  num_err);
+    if (0 < num_err) {
+        VTR_LOG_ERROR("Routing Resource graph is not valid due to %d fatal errors !\n",
+                      num_err);
+    }
 
-    return check_flag;
+    return (0 == num_err);
 }
 
 bool RRGraph::is_dirty() const {
@@ -767,55 +755,58 @@ void RRGraph::clear_dirty() {
 }
 
 /* Reserve a list of nodes */
-void RRGraph::reserve_nodes(const int& num_nodes) {
+void RRGraph::reserve_nodes(const unsigned long& num_nodes) {
     /* Reserve the full set of vectors related to nodes */
     /* Basic information */
-    this->node_ids_.reserve(num_nodes);
     this->node_types_.reserve(num_nodes);
+
     this->node_bounding_boxes_.reserve(num_nodes);
+
     this->node_capacities_.reserve(num_nodes);
     this->node_ptc_nums_.reserve(num_nodes);
+    this->node_cost_indices_.reserve(num_nodes);
     this->node_directions_.reserve(num_nodes);
     this->node_sides_.reserve(num_nodes);
     this->node_Rs_.reserve(num_nodes);
     this->node_Cs_.reserve(num_nodes);
     this->node_segments_.reserve(num_nodes);
+
+    /* Edge-related vectors */
+    this->node_num_in_edges_.reserve(num_nodes);
+    this->node_num_out_edges_.reserve(num_nodes);
     this->node_num_non_configurable_in_edges_.reserve(num_nodes);
     this->node_num_non_configurable_out_edges_.reserve(num_nodes);
-
-    /* Edge-relate vectors */
-    this->node_in_edges_.reserve(num_nodes);
-    this->node_out_edges_.reserve(num_nodes);
+    this->node_edges_.reserve(num_nodes);
 }
 
 /* Reserve a list of edges */
-void RRGraph::reserve_edges(const int& num_edges) {
+void RRGraph::reserve_edges(const unsigned long& num_edges) {
     /* Reserve the full set of vectors related to edges */
-    this->edge_ids_.reserve(num_edges);
     this->edge_src_nodes_.reserve(num_edges);
     this->edge_sink_nodes_.reserve(num_edges);
     this->edge_switches_.reserve(num_edges);
 }
 
 /* Reserve a list of switches */
-void RRGraph::reserve_switches(const int& num_switches) {
+void RRGraph::reserve_switches(const size_t& num_switches) {
     this->switch_ids_.reserve(num_switches);
     this->switches_.reserve(num_switches);
 }
 
 /* Reserve a list of segments */
-void RRGraph::reserve_segments(const int& num_segments) {
+void RRGraph::reserve_segments(const size_t& num_segments) {
     this->segment_ids_.reserve(num_segments);
     this->segments_.reserve(num_segments);
 }
 
 /* Mutators */
 RRNodeId RRGraph::create_node(const t_rr_type& type) {
-    //Allocate an ID
-    RRNodeId node_id = RRNodeId(node_ids_.size());
+    /* Allocate an ID */
+    RRNodeId node_id = RRNodeId(num_nodes_);
+    /* Expand range of node ids */
+    num_nodes_++;
 
-    //Initialize the attributes
-    node_ids_.push_back(node_id);
+    /* Initialize the attributes */
     node_types_.push_back(type);
 
     node_bounding_boxes_.emplace_back(-1, -1, -1, -1);
@@ -827,12 +818,14 @@ RRNodeId RRGraph::create_node(const t_rr_type& type) {
     node_sides_.push_back(NUM_SIDES);
     node_Rs_.push_back(0.);
     node_Cs_.push_back(0.);
+    node_segments_.push_back(RRSegmentId::INVALID());
 
-    node_in_edges_.emplace_back();  //Initially empty
-    node_out_edges_.emplace_back(); //Initially empty
+    node_edges_.emplace_back(); //Initially empty
 
-    node_num_non_configurable_in_edges_.emplace_back();  //Initially empty
-    node_num_non_configurable_out_edges_.emplace_back(); //Initially empty
+    node_num_in_edges_.emplace_back(0);
+    node_num_out_edges_.emplace_back(0);
+    node_num_non_configurable_in_edges_.emplace_back(0);
+    node_num_non_configurable_out_edges_.emplace_back(0);
 
     invalidate_fast_node_lookup();
 
@@ -846,19 +839,20 @@ RREdgeId RRGraph::create_edge(const RRNodeId& source, const RRNodeId& sink, cons
     VTR_ASSERT(valid_node_id(sink));
     VTR_ASSERT(valid_switch_id(switch_id));
 
-    //Allocate an ID
-    RREdgeId edge_id = RREdgeId(edge_ids_.size());
-
-    //Initialize the attributes
-    edge_ids_.push_back(edge_id);
+    /* Allocate an ID */
+    RREdgeId edge_id = RREdgeId(num_edges_);
+    /* Expand range of edge ids */
+    num_edges_++;
 
+    /* Initialize the attributes */
     edge_src_nodes_.push_back(source);
     edge_sink_nodes_.push_back(sink);
     edge_switches_.push_back(switch_id);
 
-    //Add the edge to the nodes
-    node_out_edges_[source].push_back(edge_id);
-    node_in_edges_[sink].push_back(edge_id);
+    //We do not create the entry in node_edges_ here!
+    //For memory efficiency this is done when
+    //rebuild_node_edges() is called (i.e. after all
+    //edges have been created).
 
     VTR_ASSERT(validate_sizes());
 
@@ -902,7 +896,7 @@ void RRGraph::remove_node(const RRNodeId& node) {
     }
 
     //Mark node invalid
-    node_ids_[node] = RRNodeId::INVALID();
+    invalid_node_ids_.insert(node);
 
     //Invalidate the node look-up
     invalidate_fast_node_lookup();
@@ -918,23 +912,24 @@ void RRGraph::remove_edge(const RREdgeId& edge) {
     RRNodeId src_node = edge_src_node(edge);
     RRNodeId sink_node = edge_sink_node(edge);
 
-    //Invalidate node to edge references
-    // TODO: consider making this optional (e.g. if called from remove_node)
-    for (size_t i = 0; i < node_out_edges_[src_node].size(); ++i) {
-        if (node_out_edges_[src_node][i] == edge) {
-            node_out_edges_[src_node][i] = RREdgeId::INVALID();
+    /* Invalidate node to edge references
+     * TODO: consider making this optional (e.g. if called from remove_node)
+     */
+    for (size_t i = 0; i < node_num_in_edges_[src_node]; ++i) {
+        if (node_edges_[src_node][i] == edge) {
+            node_edges_[src_node][i] = RREdgeId::INVALID();
             break;
         }
     }
-    for (size_t i = 0; i < node_in_edges_[sink_node].size(); ++i) {
-        if (node_in_edges_[sink_node][i] == edge) {
-            node_in_edges_[sink_node][i] = RREdgeId::INVALID();
+    for (size_t i = node_num_in_edges_[sink_node]; i < node_num_in_edges_[sink_node] + node_num_out_edges_[sink_node]; ++i) {
+        if (node_edges_[sink_node][i] == edge) {
+            node_edges_[sink_node][i] = RREdgeId::INVALID();
             break;
         }
     }
 
-    //Mark edge invalid
-    edge_ids_[edge] = RREdgeId::INVALID();
+    /* Mark edge invalid */
+    invalid_edge_ids_.insert(edge);
 
     set_dirty();
 }
@@ -1047,94 +1042,150 @@ void RRGraph::set_node_segment(const RRNodeId& node, const RRSegmentId& segment_
 
     node_segments_[node] = segment_id;
 }
+void RRGraph::rebuild_node_edges() {
+    node_edges_.resize(nodes().size());
+    node_num_in_edges_.resize(nodes().size(), 0);
+    node_num_out_edges_.resize(nodes().size(), 0);
+    node_num_non_configurable_in_edges_.resize(nodes().size(), 0);
+    node_num_non_configurable_out_edges_.resize(nodes().size(), 0);
 
-/* For a given node in a rr_graph
- * classify the edges of each node to be configurable (1st part) and non-configurable (2nd part) 
- */
-void RRGraph::partition_node_in_edges(const RRNodeId& node) {
-    //Partition the edges so the first set of edges are all configurable, and the later are not
-    auto first_non_config_edge = std::partition(node_in_edges_[node].begin(), node_in_edges_[node].end(),
-                                                [&](const RREdgeId edge) { return edge_is_configurable(edge); }); /* Condition to partition edges */
+    //Count the number of edges of each type
+    for (RREdgeId edge : edges()) {
+        if (!edge) continue;
 
-    size_t num_conf_edges = std::distance(node_in_edges_[node].begin(), first_non_config_edge);
-    size_t num_non_conf_edges = node_in_edges_[node].size() - num_conf_edges; //Note we calculate using the size_t to get full range
+        RRNodeId src_node = edge_src_node(edge);
+        RRNodeId sink_node = edge_sink_node(edge);
+        bool config = edge_is_configurable(edge);
 
-    /* Check that within allowable range (no overflow when stored as num_non_configurable_edges_
-     */
-    VTR_ASSERT_MSG(num_non_conf_edges <= node_in_edges_[node].size(),
-                   "Exceeded RR node maximum number of non-configurable input edges");
-
-    node_num_non_configurable_in_edges_[node] = num_non_conf_edges; //Narrowing
-}
-
-/* For a given node in a rr_graph
- * classify the edges of each node to be configurable (1st part) and non-configurable (2nd part) 
- */
-void RRGraph::partition_node_out_edges(const RRNodeId& node) {
-    //Partition the edges so the first set of edges are all configurable, and the later are not
-    auto first_non_config_edge = std::partition(node_out_edges_[node].begin(), node_out_edges_[node].end(),
-                                                [&](const RREdgeId edge) { return edge_is_configurable(edge); }); /* Condition to partition edges */
-
-    size_t num_conf_edges = std::distance(node_out_edges_[node].begin(), first_non_config_edge);
-    size_t num_non_conf_edges = node_out_edges_[node].size() - num_conf_edges; //Note we calculate using the size_t to get full range
-
-    /* Check that within allowable range (no overflow when stored as num_non_configurable_edges_
-     */
-    VTR_ASSERT_MSG(num_non_conf_edges <= node_out_edges_[node].size(),
-                   "Exceeded RR node maximum number of non-configurable output edges");
-
-    node_num_non_configurable_out_edges_[node] = num_non_conf_edges; //Narrowing
-}
-
-/* For all nodes in a rr_graph  
- * classify the input edges of each node to be configurable (1st part) and non-configurable (2nd part) 
- */
-void RRGraph::partition_in_edges() {
-    /* For each node */
-    for (auto node : nodes()) {
-        this->partition_node_in_edges(node);
+        ++node_num_out_edges_[src_node];
+        ++node_num_in_edges_[sink_node];
+        if (!config) {
+            ++node_num_non_configurable_out_edges_[src_node];
+            ++node_num_non_configurable_in_edges_[sink_node];
+        }
     }
-}
 
-/* For all nodes in a rr_graph  
- * classify the output edges of each node to be configurable (1st part) and non-configurable (2nd part) 
- */
-void RRGraph::partition_out_edges() {
-    /* For each node */
-    for (auto node : nodes()) {
-        this->partition_node_out_edges(node);
+    //Allocate precisely the correct space for each nodes edge list
+    for (RRNodeId node : nodes()) {
+        if (!node) continue;
+
+        node_edges_[node] = std::make_unique<RREdgeId[]>(node_num_in_edges_[node] + node_num_out_edges_[node]);
     }
-}
 
-/* For all nodes in a rr_graph  
- * classify both input and output edges of each node 
- * to be configurable (1st part) and non-configurable (2nd part) 
- */
-void RRGraph::partition_edges() {
-    /* Partition input edges */
-    this->partition_in_edges();
-    /* Partition output edges */
-    this->partition_out_edges();
+    //Insert the edges into the node lists
+    {
+        vtr::vector<RRNodeId, int> inserted_edge_cnt(nodes().size(), 0);
+        for (RREdgeId edge : edges()) {
+            RRNodeId src_node = edge_src_node(edge);
+            RRNodeId sink_node = edge_sink_node(edge);
+
+            node_edges_[src_node][inserted_edge_cnt[src_node]++] = edge;
+            node_edges_[sink_node][inserted_edge_cnt[sink_node]++] = edge;
+        }
+    }
+
+#if 0
+    //TODO: Sanity Check remove!
+    for (RRNodeId node : nodes()) {
+        for (size_t iedge = 0; iedge < node_num_in_edges_[node] + node_num_out_edges_[node]; ++iedge) {
+            RREdgeId edge = node_edges_[node][iedge];
+            VTR_ASSERT(edge_src_node(edge) == node || edge_sink_node(edge) == node);
+        }
+    }
+#endif
+
+    //Partition each node's edge lists according to their type to line up with the counts
+
+    auto is_configurable_edge = [&](const RREdgeId edge) {
+        return edge_is_configurable(edge);
+    };
+
+    for (RRNodeId node : nodes()) {
+        if (!node) continue;
+
+        //We partition the nodes first by incoming/outgoing:
+        //
+        // +---------------------------+-----------------------------+
+        // |             in            |           out               |
+        // +---------------------------+-----------------------------+
+        //
+        //and then the two subsets by configurability. So the final ordering is:
+        //
+        // +-----------+---------------+------------+----------------+
+        // | in_config | in_non_config | out_config | out_non_config |
+        // +-----------+---------------+------------+----------------+
+        //
+
+        //Partition first into incoming/outgoing
+        auto is_incoming_edge = [&](const RREdgeId edge) {
+            return edge_sink_node(edge) == node;
+        };
+        std::partition(node_edges_[node].get(),
+                       node_edges_[node].get() + node_num_in_edges_[node] + node_num_out_edges_[node],
+                       is_incoming_edge);
+
+        //Partition incoming by configurable/non-configurable
+        std::partition(node_edges_[node].get(),
+                       node_edges_[node].get() + node_num_in_edges_[node],
+                       is_configurable_edge);
+
+        //Partition outgoing by configurable/non-configurable
+        std::partition(node_edges_[node].get() + node_num_in_edges_[node],
+                       node_edges_[node].get() + node_num_in_edges_[node] + node_num_out_edges_[node],
+                       is_configurable_edge);
+
+#if 0
+        //TODO: Sanity check remove!
+        size_t nedges = node_num_in_edges_[node] + node_num_out_edges_[node];
+        for (size_t iedge = 0; iedge < nedges; ++iedge) {
+            RREdgeId edge = node_edges_[node][iedge];
+            if (iedge < node_num_in_edges_[node]) { //Incoming
+                VTR_ASSERT(edge_sink_node(edge) == node);
+                if (iedge < node_num_in_edges_[node] - node_num_non_configurable_in_edges_[node]) {
+                    VTR_ASSERT(edge_is_configurable(edge));
+                } else {
+                    VTR_ASSERT(!edge_is_configurable(edge));
+                }
+            } else { //Outgoing
+                VTR_ASSERT(edge_src_node(edge) == node);
+                if (iedge < node_num_in_edges_[node] + node_num_out_edges_[node] - node_num_non_configurable_out_edges_[node]) {
+                    VTR_ASSERT(edge_is_configurable(edge));
+                } else {
+                    VTR_ASSERT(!edge_is_configurable(edge));
+                }
+            }
+        }
+#endif
+    }
 }
 
 void RRGraph::build_fast_node_lookup() const {
+    /* Free the current fast node look-up, we will rebuild a new one here */
     invalidate_fast_node_lookup();
 
-    for (auto node : nodes()) {
+    /* Get the max (x,y) and then we can resize the ndmatrix */
+    vtr::Point<short> max_coord(0, 0);
+    for (size_t id = 0; id < num_nodes_; ++id) {
+        /* Try to find if this is an invalid id or not */
+        if (!valid_node_id(RRNodeId(id))) {
+            /* Skip this id */
+            continue;
+        }
+        max_coord.set_x(std::max(max_coord.x(), node_xlow(RRNodeId(id))));
+        max_coord.set_y(std::max(max_coord.y(), node_ylow(RRNodeId(id))));
+    }
+    node_lookup_.resize({(size_t)max_coord.x() + 1, (size_t)max_coord.y() + 1, NUM_RR_TYPES + 1});
+
+    for (size_t id = 0; id < num_nodes_; ++id) {
+        /* Try to find if this is an invalid id or not */
+        if (!valid_node_id(RRNodeId(id))) {
+            /* Skip this id */
+            continue;
+        }
+        RRNodeId node = RRNodeId(id);
         size_t x = node_xlow(node);
-        if (x >= node_lookup_.size()) {
-            node_lookup_.resize(x + 1);
-        }
-
         size_t y = node_ylow(node);
-        if (y >= node_lookup_[x].size()) {
-            node_lookup_[x].resize(y + 1);
-        }
-
         size_t itype = node_type(node);
-        if (itype >= node_lookup_[x][y].size()) {
-            node_lookup_[x][y].resize(itype + 1);
-        }
 
         size_t ptc = node_ptc_num(node);
         if (ptc >= node_lookup_[x][y][itype].size()) {
@@ -1172,11 +1223,13 @@ void RRGraph::initialize_fast_node_lookup() const {
 }
 
 bool RRGraph::valid_node_id(const RRNodeId& node) const {
-    return size_t(node) < node_ids_.size() && node_ids_[node] == node;
+    return (size_t(node) < num_nodes_)
+           && (!invalid_node_ids_.count(node));
 }
 
 bool RRGraph::valid_edge_id(const RREdgeId& edge) const {
-    return size_t(edge) < edge_ids_.size() && edge_ids_[edge] == edge;
+    return (size_t(edge) < num_edges_)
+           && (!invalid_edge_ids_.count(edge));
 }
 
 /* check if a given switch id is valid or not */
@@ -1205,26 +1258,25 @@ bool RRGraph::validate_sizes() const {
 }
 
 bool RRGraph::validate_node_sizes() const {
-    return node_types_.size() == node_ids_.size()
-           && node_bounding_boxes_.size() == node_ids_.size()
-           && node_capacities_.size() == node_ids_.size()
-           && node_ptc_nums_.size() == node_ids_.size()
-           && node_cost_indices_.size() == node_ids_.size()
-           && node_directions_.size() == node_ids_.size()
-           && node_sides_.size() == node_ids_.size()
-           && node_Rs_.size() == node_ids_.size()
-           && node_Cs_.size() == node_ids_.size()
-           && node_segments_.size() == node_ids_.size()
-           && node_num_non_configurable_in_edges_.size() == node_ids_.size()
-           && node_num_non_configurable_out_edges_.size() == node_ids_.size()
-           && node_in_edges_.size() == node_ids_.size()
-           && node_out_edges_.size() == node_ids_.size();
+    return node_types_.size() == num_nodes_
+           && node_bounding_boxes_.size() == num_nodes_
+           && node_capacities_.size() == num_nodes_
+           && node_ptc_nums_.size() == num_nodes_
+           && node_cost_indices_.size() == num_nodes_
+           && node_directions_.size() == num_nodes_
+           && node_sides_.size() == num_nodes_
+           && node_Rs_.size() == num_nodes_
+           && node_Cs_.size() == num_nodes_
+           && node_segments_.size() == num_nodes_
+           && node_num_non_configurable_in_edges_.size() == num_nodes_
+           && node_num_non_configurable_out_edges_.size() == num_nodes_
+           && node_edges_.size() == num_nodes_;
 }
 
 bool RRGraph::validate_edge_sizes() const {
-    return edge_src_nodes_.size() == edge_ids_.size()
-           && edge_sink_nodes_.size() == edge_ids_.size()
-           && edge_switches_.size() == edge_ids_.size();
+    return edge_src_nodes_.size() == num_edges_
+           && edge_sink_nodes_.size() == num_edges_
+           && edge_switches_.size() == num_edges_;
 }
 
 bool RRGraph::validate_switch_sizes() const {
@@ -1236,8 +1288,8 @@ bool RRGraph::validate_segment_sizes() const {
 }
 
 void RRGraph::compress() {
-    vtr::vector<RRNodeId, RRNodeId> node_id_map(node_ids_.size());
-    vtr::vector<RREdgeId, RREdgeId> edge_id_map(edge_ids_.size());
+    vtr::vector<RRNodeId, RRNodeId> node_id_map(num_nodes_);
+    vtr::vector<RREdgeId, RREdgeId> edge_id_map(num_edges_);
 
     build_id_maps(node_id_map, edge_id_map);
 
@@ -1248,17 +1300,48 @@ void RRGraph::compress() {
 
     invalidate_fast_node_lookup();
 
+    /* Clear invalid node list */
+    invalid_node_ids_.clear();
+
+    /* Clear invalid edge list */
+    invalid_edge_ids_.clear();
+
     clear_dirty();
 }
 
 void RRGraph::build_id_maps(vtr::vector<RRNodeId, RRNodeId>& node_id_map,
                             vtr::vector<RREdgeId, RREdgeId>& edge_id_map) {
-    node_id_map = compress_ids(node_ids_);
-    edge_id_map = compress_ids(edge_ids_);
+    /* Build node ids including invalid ids and compress */
+    vtr::vector<RRNodeId, RRNodeId> node_ids;
+    for (size_t id = 0; id < num_nodes_; ++id) {
+        /* Try to find if this is an invalid id or not */
+        if (!valid_node_id(RRNodeId(id))) {
+            /* Give and invalid id */
+            node_ids.push_back(RRNodeId::INVALID());
+            continue;
+        }
+        /* Reach here, this is a valid id, push to the edge list */
+        node_ids.push_back(RRNodeId(id));
+    }
+    node_id_map = compress_ids(node_ids);
+
+    /* Build edge ids including invalid ids and compress */
+    vtr::vector<RREdgeId, RREdgeId> edge_ids;
+    for (size_t id = 0; id < num_edges_; ++id) {
+        /* Try to find if this is an invalid id or not */
+        if (!valid_edge_id(RREdgeId(id))) {
+            /* Give and invalid id */
+            edge_ids.push_back(RREdgeId::INVALID());
+            continue;
+        }
+        /* Reach here, this is a valid id, push to the edge list */
+        edge_ids.push_back(RREdgeId(id));
+    }
+    edge_id_map = compress_ids(edge_ids);
 }
 
 void RRGraph::clean_nodes(const vtr::vector<RRNodeId, RRNodeId>& node_id_map) {
-    node_ids_ = clean_and_reorder_ids(node_id_map);
+    num_nodes_ = node_id_map.size();
 
     node_types_ = clean_and_reorder_values(node_types_, node_id_map);
 
@@ -1272,39 +1355,46 @@ void RRGraph::clean_nodes(const vtr::vector<RRNodeId, RRNodeId>& node_id_map) {
     node_Rs_ = clean_and_reorder_values(node_Rs_, node_id_map);
     node_Cs_ = clean_and_reorder_values(node_Cs_, node_id_map);
 
-    VTR_ASSERT(validate_node_sizes());
+    node_segments_ = clean_and_reorder_values(node_segments_, node_id_map);
+    node_num_non_configurable_in_edges_ = clean_and_reorder_values(node_num_non_configurable_in_edges_, node_id_map);
+    node_num_non_configurable_out_edges_ = clean_and_reorder_values(node_num_non_configurable_out_edges_, node_id_map);
+    node_num_in_edges_ = clean_and_reorder_values(node_num_in_edges_, node_id_map);
+    node_num_out_edges_ = clean_and_reorder_values(node_num_out_edges_, node_id_map);
+    //node_edges_ = clean_and_reorder_values(node_edges_, node_id_map);
 
-    VTR_ASSERT_MSG(are_contiguous(node_ids_), "Ids should be contiguous");
-    VTR_ASSERT_MSG(all_valid(node_ids_), "All Ids should be valid");
+    VTR_ASSERT(validate_node_sizes());
 }
 
 void RRGraph::clean_edges(const vtr::vector<RREdgeId, RREdgeId>& edge_id_map) {
-    edge_ids_ = clean_and_reorder_ids(edge_id_map);
+    num_edges_ = edge_id_map.size();
 
     edge_src_nodes_ = clean_and_reorder_values(edge_src_nodes_, edge_id_map);
     edge_sink_nodes_ = clean_and_reorder_values(edge_sink_nodes_, edge_id_map);
     edge_switches_ = clean_and_reorder_values(edge_switches_, edge_id_map);
 
     VTR_ASSERT(validate_edge_sizes());
-
-    VTR_ASSERT_MSG(are_contiguous(edge_ids_), "Ids should be contiguous");
-    VTR_ASSERT_MSG(all_valid(edge_ids_), "All Ids should be valid");
 }
 
 void RRGraph::rebuild_node_refs(const vtr::vector<RREdgeId, RREdgeId>& edge_id_map) {
-    for (const auto& node : nodes()) {
-        node_in_edges_[node] = update_valid_refs(node_in_edges_[node], edge_id_map);
-        node_out_edges_[node] = update_valid_refs(node_out_edges_[node], edge_id_map);
+    for (size_t id = 0; id < num_nodes_; ++id) {
+        /* Try to find if this is an invalid id or not */
+        if (!valid_node_id(RRNodeId(id))) {
+            /* Skip this id */
+            continue;
+        }
+        RRNodeId node = RRNodeId(id);
 
-        VTR_ASSERT_MSG(all_valid(node_in_edges_[node]), "All Ids should be valid");
-        VTR_ASSERT_MSG(all_valid(node_out_edges_[node]), "All Ids should be valid");
+        auto begin = node_edges_[node].get();
+        auto end = begin + node_num_in_edges_[node] + node_num_out_edges_[node];
+        update_valid_refs(begin, end, edge_id_map);
+
+        VTR_ASSERT_MSG(all_valid(begin, end), "All Ids should be valid");
     }
 }
 
 /* Empty all the vectors related to nodes */
 void RRGraph::clear_nodes() {
-    node_ids_.clear();
-
+    num_nodes_ = 0;
     node_types_.clear();
     node_bounding_boxes_.clear();
 
@@ -1317,11 +1407,12 @@ void RRGraph::clear_nodes() {
     node_Cs_.clear();
     node_segments_.clear();
 
+    node_num_in_edges_.clear();
+    node_num_out_edges_.clear();
     node_num_non_configurable_in_edges_.clear();
     node_num_non_configurable_out_edges_.clear();
 
-    node_in_edges_.clear();
-    node_out_edges_.clear();
+    node_edges_.clear();
 
     /* clean node_look_up */
     node_lookup_.clear();
@@ -1329,7 +1420,7 @@ void RRGraph::clear_nodes() {
 
 /* Empty all the vectors related to edges */
 void RRGraph::clear_edges() {
-    edge_ids_.clear();
+    num_edges_ = 0;
     edge_src_nodes_.clear();
     edge_sink_nodes_.clear();
     edge_switches_.clear();
diff --git a/vpr/src/device/rr_graph_obj.h b/libs/librrgraph/src/rr_graph_obj.h
similarity index 85%
rename from vpr/src/device/rr_graph_obj.h
rename to libs/librrgraph/src/rr_graph_obj.h
index f34b11162..85bf7de4b 100644
--- a/vpr/src/device/rr_graph_obj.h
+++ b/libs/librrgraph/src/rr_graph_obj.h
@@ -198,30 +198,44 @@
 /* Standard header files required go first */
 #include <limits>
 #include <vector>
+#include <unordered_set>
+#include <unordered_map>
 
 /* EXTERNAL library header files go second*/
+#include "vtr_ndmatrix.h"
 #include "vtr_vector.h"
 #include "vtr_range.h"
 #include "vtr_geometry.h"
 #include "arch_types.h"
 
 /* VPR header files go third */
-#include "vpr_types.h"
+#include "rr_graph_types.h"
 #include "rr_graph_fwd.h"
 
 class RRGraph {
   public: /* Types */
+    //Lazy iterator utility forward declaration
+    template<class ID>
+    class lazy_id_iterator;
+
     /* Iterators used to create iterator-based loop for nodes/edges/switches/segments */
     typedef vtr::vector<RRNodeId, RRNodeId>::const_iterator node_iterator;
     typedef vtr::vector<RREdgeId, RREdgeId>::const_iterator edge_iterator;
     typedef vtr::vector<RRSwitchId, RRSwitchId>::const_iterator switch_iterator;
     typedef vtr::vector<RRSegmentId, RRSegmentId>::const_iterator segment_iterator;
+    typedef lazy_id_iterator<RRNodeId> lazy_node_iterator;
+    typedef lazy_id_iterator<RREdgeId> lazy_edge_iterator;
 
     /* Ranges used to create range-based loop for nodes/edges/switches/segments */
     typedef vtr::Range<node_iterator> node_range;
-    typedef vtr::Range<edge_iterator> edge_range;
+    typedef vtr::Range<RREdgeId*> edge_range;
     typedef vtr::Range<switch_iterator> switch_range;
     typedef vtr::Range<segment_iterator> segment_range;
+    typedef vtr::Range<lazy_node_iterator> lazy_node_range;
+    typedef vtr::Range<lazy_edge_iterator> lazy_edge_range;
+
+  public: /* Constructors */
+    RRGraph();
 
   public: /* Accessors */
     /* Aggregates: create range-based loops for nodes/edges/switches/segments
@@ -247,8 +261,8 @@ class RRGraph {
      *        // Do something with each segment
      *      }
      */
-    node_range nodes() const;
-    edge_range edges() const;
+    lazy_node_range nodes() const;
+    lazy_edge_range edges() const;
     switch_range switches() const;
     segment_range segments() const;
 
@@ -445,23 +459,9 @@ class RRGraph {
      */
     RRSegmentId node_segment(const RRNodeId& node) const;
 
-    /* Get the number of non-configurable incoming edges to a node */
-    short node_num_configurable_in_edges(const RRNodeId& node) const;
-
-    /* Get the number of non-configurable outgoing edges from a node */
-    short node_num_non_configurable_in_edges(const RRNodeId& node) const;
-
-    /* Get the number of configurable output edges of a node */
-    short node_num_configurable_out_edges(const RRNodeId& node) const;
-
-    /* Get the number of non-configurable output edges of a node */
-    short node_num_non_configurable_out_edges(const RRNodeId& node) const;
-
-    /* Get the range (list) of edges related to a given node */
-    edge_range node_configurable_in_edges(const RRNodeId& node) const;
-    edge_range node_non_configurable_in_edges(const RRNodeId& node) const;
-    edge_range node_configurable_out_edges(const RRNodeId& node) const;
-    edge_range node_non_configurable_out_edges(const RRNodeId& node) const;
+    //Returns an iterable range of all edges (incoming & outgoing) for
+    //the specified node
+    edge_range node_edges(const RRNodeId& node) const;
 
     /* Get a list of edge ids, which are incoming edges to a node */
     edge_range node_in_edges(const RRNodeId& node) const;
@@ -469,6 +469,12 @@ class RRGraph {
     /* Get a list of edge ids, which are outgoing edges from a node */
     edge_range node_out_edges(const RRNodeId& node) const;
 
+    /* Get the range (list) of edges related to a given node */
+    edge_range node_configurable_in_edges(const RRNodeId& node) const;
+    edge_range node_non_configurable_in_edges(const RRNodeId& node) const;
+    edge_range node_configurable_out_edges(const RRNodeId& node) const;
+    edge_range node_non_configurable_out_edges(const RRNodeId& node) const;
+
     /* Edge-related attributes 
      * An example to explain the terminology used in RRGraph
      *          edgeA
@@ -583,10 +589,10 @@ class RRGraph {
      *      rr_graph.create_node(CHANX);
      *    }
      */
-    void reserve_nodes(const int& num_nodes);
-    void reserve_edges(const int& num_edges);
-    void reserve_switches(const int& num_switches);
-    void reserve_segments(const int& num_segments);
+    void reserve_nodes(const unsigned long& num_nodes);
+    void reserve_edges(const unsigned long& num_edges);
+    void reserve_switches(const size_t& num_switches);
+    void reserve_segments(const size_t& num_segments);
 
     /* Add new elements (node, edge, switch, etc.) to RRGraph */
     /* Add a node to the RRGraph with a deposited type 
@@ -596,6 +602,7 @@ class RRGraph {
      *   set_node_xlow(node, 0);
      */
     RRNodeId create_node(const t_rr_type& type);
+
     /* Add a edge to the RRGraph, by providing the source and sink node 
      * This function will automatically create a node and
      * configure the nodes and edges in connection   
@@ -690,15 +697,14 @@ class RRGraph {
     /* Set the routing segment linked to a node, only applicable to CHANX and CHANY */
     void set_node_segment(const RRNodeId& node, const RRSegmentId& segment_index);
 
-    /* Edge partitioning is performed for efficiency, 
-     * so we can store configurable and non-configurable edge lists for a node in one vector, 
-     * and efficiently iterate over all edges, or only the configurable or non-configurable subsets.
-     * This function will re-organize the incoming and outgoing edges of each node, 
-     * i.e., node_in_edges() and node_out_edges():
-     * 1. configurable edges (1st part of the vectors) 
-     * 2. non-configurable edges (2nd part of the vectors) 
+    /*
+     * Build the node to edge references to allow iteration through
+     * a node's in/out edges.
+     *
+     * Must be called before any node_*_in_edges() or node_*_out_edges() member
+     * functions can be called.
      */
-    void partition_edges();
+    void rebuild_node_edges();
 
     /* Graph-level Clean-up, remove invalid nodes/edges etc.
      * This will clear the dirty flag (query by is_dirty()) of RRGraph object, if it was set 
@@ -708,18 +714,52 @@ class RRGraph {
     /* top-level function to free, should be called when to delete a RRGraph */
     void clear();
 
-  private: /* Internal Mutators to perform edge partitioning */
-    /* classify the input edges of each node to be configurable (1st part) and non-configurable (2nd part) */
-    void partition_node_in_edges(const RRNodeId& node);
+  public: /* Type implementations */
+    /*
+     * This class (forward delcared above) is a template used to represent a lazily calculated 
+     * iterator of the specified ID type. The key assumption made is that the ID space is 
+     * contiguous and can be walked by incrementing the underlying ID value. To account for 
+     * invalid IDs, it keeps a reference to the invalid ID set and returns ID::INVALID() for
+     * ID values in the set.
+     *
+     * It is used to lazily create an iteration range (e.g. as returned by RRGraph::edges() RRGraph::nodes())
+     * just based on the count of allocated elements (i.e. RRGraph::num_nodes_ or RRGraph::num_edges_),
+     * and the set of any invalid IDs (i.e. RRGraph::invalid_node_ids_, RRGraph::invalid_edge_ids_).
+     */
+    template<class ID>
+    class lazy_id_iterator : public std::iterator<std::bidirectional_iterator_tag, ID> {
+      public:
+        //Since we pass ID as a template to std::iterator we need to use an explicit 'typename'
+        //to bring the value_type and iterator names into scope
+        typedef typename std::iterator<std::bidirectional_iterator_tag, ID>::value_type value_type;
+        typedef typename std::iterator<std::bidirectional_iterator_tag, ID>::iterator iterator;
 
-    /* classify the output edges of each node to be configurable (1st part) and non-configurable (2nd part) */
-    void partition_node_out_edges(const RRNodeId& node);
+        lazy_id_iterator(value_type init, const std::unordered_set<ID>& invalid_ids)
+            : value_(init)
+            , invalid_ids_(invalid_ids) {}
 
-    /* classify the input edges of each node to be configurable (1st part) and non-configurable (2nd part) */
-    void partition_in_edges();
+        //Advance to the next ID value
+        iterator operator++() {
+            value_ = ID(size_t(value_) + 1);
+            return *this;
+        }
 
-    /* classify the output edges of each node to be configurable (1st part) and non-configurable (2nd part) */
-    void partition_out_edges();
+        //Advance to the previous ID value
+        iterator operator--() {
+            value_ = ID(size_t(value_) - 1);
+            return *this;
+        }
+
+        //Dereference the iterator
+        value_type operator*() const { return (invalid_ids_.count(value_)) ? ID::INVALID() : value_; }
+
+        friend bool operator==(const lazy_id_iterator<ID> lhs, const lazy_id_iterator<ID> rhs) { return lhs.value_ == rhs.value_; }
+        friend bool operator!=(const lazy_id_iterator<ID> lhs, const lazy_id_iterator<ID> rhs) { return !(lhs == rhs); }
+
+      private:
+        value_type value_;
+        const std::unordered_set<ID>& invalid_ids_;
+    };
 
   private: /* Internal free functions */
     void clear_nodes();
@@ -787,7 +827,9 @@ class RRGraph {
 
   private: /* Internal Data */
     /* Node related data */
-    vtr::vector<RRNodeId, RRNodeId> node_ids_; /* Unique identifiers for the nodes */
+    size_t num_nodes_;                              /* Range of node ids */
+    std::unordered_set<RRNodeId> invalid_node_ids_; /* Invalid edge ids */
+
     vtr::vector<RRNodeId, t_rr_type> node_types_;
 
     vtr::vector<RRNodeId, vtr::Rect<short>> node_bounding_boxes_;
@@ -800,15 +842,44 @@ class RRGraph {
     vtr::vector<RRNodeId, float> node_Rs_;
     vtr::vector<RRNodeId, float> node_Cs_;
     vtr::vector<RRNodeId, RRSegmentId> node_segments_; /* Segment ids for each node */
-    /* Record the dividing point between configurable and non-configurable edges for each node */
-    vtr::vector<RRNodeId, size_t> node_num_non_configurable_in_edges_;
-    vtr::vector<RRNodeId, size_t> node_num_non_configurable_out_edges_;
 
-    vtr::vector<RRNodeId, std::vector<RREdgeId>> node_in_edges_;
-    vtr::vector<RRNodeId, std::vector<RREdgeId>> node_out_edges_;
+    /*
+     * We store the edges assoicated with each node in a single array per node (for memory efficiency).
+     *
+     * The array of edges is sorted into sub-ranges to allow for easy iteration (with node_in_edges(),
+     * node_non_configurable_out_edges() etc.).
+     *
+     * For a particular 'node' we store the sizes of the various sub-ranges in the node_num_* members,
+     * from which the delimiters for each sub-range can be calculated.
+     *
+     *
+     *  node_edges_[node]:
+     *
+     *  
+     *                   node_num_non_configurable_in_edges_[node]      node_num_non_configurable_out_edges_[node]
+     *                         <------------------->                    <-------------------->
+     *     
+     *     +------------------+---------------------+------------------+----------------------+
+     *     |  in_edges_config | in_edges_non_config | out_edges_config | out_edges_non_config |
+     *     +------------------+---------------------+------------------+----------------------+
+     *                                                                                        
+     *      <--------------------------------------> <--------------------------------------->
+     *              node_num_in_edges_[node]                 node_num_out_edges_[node]        
+     *
+     * All elements of node_edges_ should be initialized after all edges have been created (with create_edge()),
+     * by calling rebuild_node_edges(), which will allocate node_edges_, add the relevant edges and partition
+     * each node's arrays into the appropriate. rebuild_node_edges() also initializes all the node_num_* members
+     * based on the edges (created with create_edge()) in the edge_* members.
+     */
+    vtr::vector<RRNodeId, uint16_t> node_num_in_edges_;
+    vtr::vector<RRNodeId, uint16_t> node_num_out_edges_;
+    vtr::vector<RRNodeId, uint16_t> node_num_non_configurable_in_edges_;
+    vtr::vector<RRNodeId, uint16_t> node_num_non_configurable_out_edges_;
+    vtr::vector<RRNodeId, std::unique_ptr<RREdgeId[]>> node_edges_;
 
     /* Edge related data */
-    vtr::vector<RREdgeId, RREdgeId> edge_ids_; /* unique identifiers for edges */
+    size_t num_edges_;                              /* Range of edge ids */
+    std::unordered_set<RREdgeId> invalid_edge_ids_; /* Invalid edge ids */
     vtr::vector<RREdgeId, RRNodeId> edge_src_nodes_;
     vtr::vector<RREdgeId, RRNodeId> edge_sink_nodes_;
     vtr::vector<RREdgeId, RRSwitchId> edge_switches_;
@@ -836,7 +907,7 @@ class RRGraph {
     /* Fast look-up to search a node by its type, coordinator and ptc_num 
      * Indexing of fast look-up: [0..xmax][0..ymax][0..NUM_TYPES-1][0..ptc_max][0..NUM_SIDES-1] 
      */
-    typedef std::vector<std::vector<std::vector<std::vector<std::vector<RRNodeId>>>>> NodeLookup;
+    typedef vtr::NdMatrix<std::vector<std::vector<RRNodeId>>, 3> NodeLookup;
     mutable NodeLookup node_lookup_;
 };
 
diff --git a/vpr/src/device/rr_graph_obj_utils.h b/libs/librrgraph/src/rr_graph_obj_utils.h
similarity index 87%
rename from vpr/src/device/rr_graph_obj_utils.h
rename to libs/librrgraph/src/rr_graph_obj_utils.h
index 910b0ce3a..5c3a8f6d6 100644
--- a/vpr/src/device/rr_graph_obj_utils.h
+++ b/libs/librrgraph/src/rr_graph_obj_utils.h
@@ -38,6 +38,16 @@ bool all_valid(const Container& values) {
     return true;
 }
 
+template<typename Iterator>
+bool all_valid(Iterator begin, Iterator end) {
+    for (auto itr = begin; itr != end; ++itr) {
+        if (!*itr) {
+            return false;
+        }
+    }
+    return true;
+}
+
 //Builds a mapping from old to new ids by skipping values marked invalid
 template<typename Container>
 Container compress_ids(const Container& ids) {
@@ -162,4 +172,20 @@ ValueContainer update_valid_refs(const ValueContainer& values, const IdContainer
     return updated;
 }
 
+template<typename Iterator, typename IdContainer>
+void update_valid_refs(Iterator begin, Iterator end, const IdContainer& id_map) {
+    for (auto itr = begin; itr != end; ++itr) {
+        auto orig_val = *itr;
+        if (orig_val) {
+            //Original item valid
+
+            auto new_val = id_map[orig_val];
+            if (new_val) {
+                //The original item exists in the new mapping
+                *itr = new_val;
+            }
+        }
+    }
+}
+
 #endif
diff --git a/libs/librrgraph/src/rr_graph_types.h b/libs/librrgraph/src/rr_graph_types.h
new file mode 100644
index 000000000..51cf3a0dd
--- /dev/null
+++ b/libs/librrgraph/src/rr_graph_types.h
@@ -0,0 +1,43 @@
+#ifndef RR_GRAPH_TYPES
+#define RR_GRAPH_TYPES
+
+/********************************************************************
+ * Data types required by routing resource graph (RRGraph) definition
+ *******************************************************************/
+
+/********************************************************************
+ * Directionality of a routing track (node type CHANX and CHANY) in
+ * a routing resource graph
+ *******************************************************************/
+enum e_direction : unsigned char {
+    INC_DIRECTION = 0,
+    DEC_DIRECTION = 1,
+    BI_DIRECTION = 2,
+    NO_DIRECTION = 3,
+    NUM_DIRECTIONS
+};
+
+constexpr std::array<const char*, NUM_DIRECTIONS> DIRECTION_STRING = {{"INC_DIRECTION", "DEC_DIRECTION", "BI_DIRECTION", "NO_DIRECTION"}};
+
+/* Type of a routing resource node.  x-directed channel segment,   *
+ * y-directed channel segment, input pin to a clb to pad, output   *
+ * from a clb or pad (i.e. output pin of a net) and:               *
+ * SOURCE:  A dummy node that is a logical output within a block   *
+ *          -- i.e., the gate that generates a signal.             *
+ * SINK:    A dummy node that is a logical input within a block    *
+ *          -- i.e. the gate that needs a signal.                  */
+typedef enum e_rr_type : unsigned char {
+    SOURCE = 0,
+    SINK,
+    IPIN,
+    OPIN,
+    CHANX,
+    CHANY,
+    NUM_RR_TYPES
+} t_rr_type;
+
+constexpr std::array<t_rr_type, NUM_RR_TYPES> RR_TYPES = {{SOURCE, SINK, IPIN, OPIN, CHANX, CHANY}};
+constexpr std::array<const char*, NUM_RR_TYPES> rr_node_typename{{"SOURCE", "SINK", "IPIN", "OPIN", "CHANX", "CHANY"}};
+
+
+#endif
diff --git a/vpr/src/device/rr_graph_util.cpp b/libs/librrgraph/src/rr_graph_util.cpp
similarity index 100%
rename from vpr/src/device/rr_graph_util.cpp
rename to libs/librrgraph/src/rr_graph_util.cpp
diff --git a/vpr/src/device/rr_graph_util.h b/libs/librrgraph/src/rr_graph_util.h
similarity index 100%
rename from vpr/src/device/rr_graph_util.h
rename to libs/librrgraph/src/rr_graph_util.h
diff --git a/libs/librrgraph/test/test_rr_graph.cpp b/libs/librrgraph/test/test_rr_graph.cpp
new file mode 100644
index 000000000..2bd143b81
--- /dev/null
+++ b/libs/librrgraph/test/test_rr_graph.cpp
@@ -0,0 +1,8 @@
+#include "vtr_geometry.h"
+#include "rr_graph_obj.h"
+
+int main(int argc, char** argv) {
+  RRGraph rr_graph_obj;
+
+  return 0;
+}
diff --git a/libs/libvtrutil/src/vtr_geometry.tpp b/libs/libvtrutil/src/vtr_geometry.tpp
index 608b09c4c..f0151df2a 100644
--- a/libs/libvtrutil/src/vtr_geometry.tpp
+++ b/libs/libvtrutil/src/vtr_geometry.tpp
@@ -79,6 +79,12 @@ Rect<T>::Rect(Point<T> bottom_left_val, Point<T> top_right_val)
     //pass
 }
 
+template<class T>
+Rect<T>::Rect() {
+    //pass
+}
+
+
 template<class T>
 T Rect<T>::xmin() const {
     return bottom_left_.x();
diff --git a/vpr/CMakeLists.txt b/vpr/CMakeLists.txt
index 4d06b1e1a..217a7bb8d 100644
--- a/vpr/CMakeLists.txt
+++ b/vpr/CMakeLists.txt
@@ -58,6 +58,7 @@ set_target_properties(libvpr8 PROPERTIES PREFIX "") #Avoid extra 'lib' prefix
 target_link_libraries(libvpr8
                         libvtrutil
                         libarchfpga
+                        librrgraph
                         libsdcparse
                         libblifparse
                         libtatum
diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h
index e6c010f73..cb38f75ee 100644
--- a/vpr/src/base/vpr_types.h
+++ b/vpr/src/base/vpr_types.h
@@ -40,6 +40,9 @@
 #include "vtr_flat_map.h"
 #include "vtr_cache.h"
 
+/* Header for rr_graph related definition */
+#include "rr_graph_types.h"
+
 /*******************************************************************************
  * Global data types and constants
  ******************************************************************************/
@@ -1011,15 +1014,6 @@ struct t_det_routing_arch {
     std::string write_rr_graph_filename;
 };
 
-enum e_direction : unsigned char {
-    INC_DIRECTION = 0,
-    DEC_DIRECTION = 1,
-    BI_DIRECTION = 2,
-    NO_DIRECTION = 3,
-    NUM_DIRECTIONS
-};
-
-constexpr std::array<const char*, NUM_DIRECTIONS> DIRECTION_STRING = {{"INC_DIRECTION", "DEC_DIRECTION", "BI_DIRECTION", "NO_DIRECTION"}};
 
 /* Lists detailed information about segmentation.  [0 .. W-1].              *
  * length:  length of segment.                                              *
@@ -1132,26 +1126,6 @@ struct t_linked_f_pointer {
 
 typedef std::vector<std::vector<std::vector<std::vector<std::vector<int>>>>> t_rr_node_indices; //[0..num_rr_types-1][0..grid_width-1][0..grid_height-1][0..NUM_SIDES-1][0..max_ptc-1]
 
-/* Type of a routing resource node.  x-directed channel segment,   *
- * y-directed channel segment, input pin to a clb to pad, output   *
- * from a clb or pad (i.e. output pin of a net) and:               *
- * SOURCE:  A dummy node that is a logical output within a block   *
- *          -- i.e., the gate that generates a signal.             *
- * SINK:    A dummy node that is a logical input within a block    *
- *          -- i.e. the gate that needs a signal.                  */
-typedef enum e_rr_type : unsigned char {
-    SOURCE = 0,
-    SINK,
-    IPIN,
-    OPIN,
-    CHANX,
-    CHANY,
-    NUM_RR_TYPES
-} t_rr_type;
-
-constexpr std::array<t_rr_type, NUM_RR_TYPES> RR_TYPES = {{SOURCE, SINK, IPIN, OPIN, CHANX, CHANY}};
-constexpr std::array<const char*, NUM_RR_TYPES> rr_node_typename{{"SOURCE", "SINK", "IPIN", "OPIN", "CHANX", "CHANY"}};
-
 /* Basic element used to store the traceback (routing) of each net.        *
  * index:   Array index (ID) of this routing resource node.                *
  * iswitch: Index of the switch type used to go from this rr_node to       *

From 9269d7106d70ff1344c5522d8922e31e7eda1757 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 31 Jan 2020 15:42:44 -0700
Subject: [PATCH 061/645] move rr_graph back to vpr because the reader and
 writer requires too much dependency on the core engine

---
 libs/CMakeLists.txt                           |   1 -
 libs/librrgraph/CMakeLists.txt                |  35 -
 libs/librrgraph/test/test_rr_graph.cpp        |   8 -
 libs/libvtrutil/stWnhl1a                      |   0
 vpr/CMakeLists.txt                            |   1 -
 .../src/device}/check_rr_graph_obj.cpp        |   0
 .../src/device}/check_rr_graph_obj.h          |   0
 .../src => vpr/src/device}/rr_graph_fwd.h     |   0
 .../src => vpr/src/device}/rr_graph_obj.cpp   |   0
 .../src => vpr/src/device}/rr_graph_obj.h     |   0
 .../src/device}/rr_graph_obj_utils.h          |   0
 .../src => vpr/src/device}/rr_graph_types.h   |   0
 .../src => vpr/src/device}/rr_graph_util.cpp  |   0
 .../src => vpr/src/device}/rr_graph_util.h    |   0
 vpr/src/device/write_xml_rr_graph_obj.cpp     | 222 ++++++
 vpr/src/device/write_xml_rr_graph_obj.h       |  12 +
 vpr/valgrind.supp                             | 711 ------------------
 17 files changed, 234 insertions(+), 756 deletions(-)
 delete mode 100644 libs/librrgraph/CMakeLists.txt
 delete mode 100644 libs/librrgraph/test/test_rr_graph.cpp
 delete mode 100644 libs/libvtrutil/stWnhl1a
 rename {libs/librrgraph/src => vpr/src/device}/check_rr_graph_obj.cpp (100%)
 rename {libs/librrgraph/src => vpr/src/device}/check_rr_graph_obj.h (100%)
 rename {libs/librrgraph/src => vpr/src/device}/rr_graph_fwd.h (100%)
 rename {libs/librrgraph/src => vpr/src/device}/rr_graph_obj.cpp (100%)
 rename {libs/librrgraph/src => vpr/src/device}/rr_graph_obj.h (100%)
 rename {libs/librrgraph/src => vpr/src/device}/rr_graph_obj_utils.h (100%)
 rename {libs/librrgraph/src => vpr/src/device}/rr_graph_types.h (100%)
 rename {libs/librrgraph/src => vpr/src/device}/rr_graph_util.cpp (100%)
 rename {libs/librrgraph/src => vpr/src/device}/rr_graph_util.h (100%)
 create mode 100644 vpr/src/device/write_xml_rr_graph_obj.cpp
 create mode 100644 vpr/src/device/write_xml_rr_graph_obj.h
 delete mode 100644 vpr/valgrind.supp

diff --git a/libs/CMakeLists.txt b/libs/CMakeLists.txt
index a85d179f8..8d09c541d 100644
--- a/libs/CMakeLists.txt
+++ b/libs/CMakeLists.txt
@@ -5,7 +5,6 @@ add_subdirectory(EXTERNAL)
 #  Only add warn flags for VPR internal libraries.
 #add_compile_options(${WARN_FLAGS})
 add_subdirectory(libarchfpga)
-add_subdirectory(librrgraph)
 add_subdirectory(libvtrutil)
 add_subdirectory(liblog)
 add_subdirectory(libpugiutil)
diff --git a/libs/librrgraph/CMakeLists.txt b/libs/librrgraph/CMakeLists.txt
deleted file mode 100644
index 52f46a170..000000000
--- a/libs/librrgraph/CMakeLists.txt
+++ /dev/null
@@ -1,35 +0,0 @@
-cmake_minimum_required(VERSION 3.9)
-
-project("librrgraph")
-
-file(GLOB_RECURSE EXEC_SOURCE test/test_rr_graph.cpp)
-file(GLOB_RECURSE LIB_SOURCES src/*.cpp)
-file(GLOB_RECURSE LIB_HEADERS src/*.h)
-files_to_dirs(LIB_HEADERS LIB_INCLUDE_DIRS)
-
-#Remove test executable from library
-list(REMOVE_ITEM LIB_SOURCES ${EXEC_SOURCE})
-
-#Create the library
-add_library(librrgraph STATIC
-             ${LIB_HEADERS}
-             ${LIB_SOURCES})
-target_include_directories(librrgraph PUBLIC ${LIB_INCLUDE_DIRS})
-set_target_properties(librrgraph PROPERTIES PREFIX "") #Avoid extra 'lib' prefix
-
-#Specify link-time dependancies
-target_link_libraries(librrgraph
-                      libarchfpga
-                      libvtrutil)
-
-#Create the test executable
-add_executable(test_rr_graph ${EXEC_SOURCE})
-target_link_libraries(test_rr_graph librrgraph)
-
-#Supress IPO link warnings if IPO is enabled
-#get_target_property(READ_ARCH_USES_IPO read_arch_openfpga INTERPROCEDURAL_OPTIMIZATION)
-#if (READ_ARCH_USES_IPO)
-#    set_target_properties(read_arch_openfpga PROPERTIES LINK_FLAGS ${IPO_LINK_WARN_SUPRESS_FLAGS})
-#endif()
-
-#install(TARGETS libarchopenfpga read_arch_openfpga DESTINATION bin)
diff --git a/libs/librrgraph/test/test_rr_graph.cpp b/libs/librrgraph/test/test_rr_graph.cpp
deleted file mode 100644
index 2bd143b81..000000000
--- a/libs/librrgraph/test/test_rr_graph.cpp
+++ /dev/null
@@ -1,8 +0,0 @@
-#include "vtr_geometry.h"
-#include "rr_graph_obj.h"
-
-int main(int argc, char** argv) {
-  RRGraph rr_graph_obj;
-
-  return 0;
-}
diff --git a/libs/libvtrutil/stWnhl1a b/libs/libvtrutil/stWnhl1a
deleted file mode 100644
index e69de29bb..000000000
diff --git a/vpr/CMakeLists.txt b/vpr/CMakeLists.txt
index 217a7bb8d..4d06b1e1a 100644
--- a/vpr/CMakeLists.txt
+++ b/vpr/CMakeLists.txt
@@ -58,7 +58,6 @@ set_target_properties(libvpr8 PROPERTIES PREFIX "") #Avoid extra 'lib' prefix
 target_link_libraries(libvpr8
                         libvtrutil
                         libarchfpga
-                        librrgraph
                         libsdcparse
                         libblifparse
                         libtatum
diff --git a/libs/librrgraph/src/check_rr_graph_obj.cpp b/vpr/src/device/check_rr_graph_obj.cpp
similarity index 100%
rename from libs/librrgraph/src/check_rr_graph_obj.cpp
rename to vpr/src/device/check_rr_graph_obj.cpp
diff --git a/libs/librrgraph/src/check_rr_graph_obj.h b/vpr/src/device/check_rr_graph_obj.h
similarity index 100%
rename from libs/librrgraph/src/check_rr_graph_obj.h
rename to vpr/src/device/check_rr_graph_obj.h
diff --git a/libs/librrgraph/src/rr_graph_fwd.h b/vpr/src/device/rr_graph_fwd.h
similarity index 100%
rename from libs/librrgraph/src/rr_graph_fwd.h
rename to vpr/src/device/rr_graph_fwd.h
diff --git a/libs/librrgraph/src/rr_graph_obj.cpp b/vpr/src/device/rr_graph_obj.cpp
similarity index 100%
rename from libs/librrgraph/src/rr_graph_obj.cpp
rename to vpr/src/device/rr_graph_obj.cpp
diff --git a/libs/librrgraph/src/rr_graph_obj.h b/vpr/src/device/rr_graph_obj.h
similarity index 100%
rename from libs/librrgraph/src/rr_graph_obj.h
rename to vpr/src/device/rr_graph_obj.h
diff --git a/libs/librrgraph/src/rr_graph_obj_utils.h b/vpr/src/device/rr_graph_obj_utils.h
similarity index 100%
rename from libs/librrgraph/src/rr_graph_obj_utils.h
rename to vpr/src/device/rr_graph_obj_utils.h
diff --git a/libs/librrgraph/src/rr_graph_types.h b/vpr/src/device/rr_graph_types.h
similarity index 100%
rename from libs/librrgraph/src/rr_graph_types.h
rename to vpr/src/device/rr_graph_types.h
diff --git a/libs/librrgraph/src/rr_graph_util.cpp b/vpr/src/device/rr_graph_util.cpp
similarity index 100%
rename from libs/librrgraph/src/rr_graph_util.cpp
rename to vpr/src/device/rr_graph_util.cpp
diff --git a/libs/librrgraph/src/rr_graph_util.h b/vpr/src/device/rr_graph_util.h
similarity index 100%
rename from libs/librrgraph/src/rr_graph_util.h
rename to vpr/src/device/rr_graph_util.h
diff --git a/vpr/src/device/write_xml_rr_graph_obj.cpp b/vpr/src/device/write_xml_rr_graph_obj.cpp
new file mode 100644
index 000000000..375d1ba52
--- /dev/null
+++ b/vpr/src/device/write_xml_rr_graph_obj.cpp
@@ -0,0 +1,222 @@
+/*********************************************************************
+ * This file defines the writing rr graph function in XML format.
+ * The rr graph is separated into channels, nodes, switches,
+ * grids, edges, block types, and segments. Each tag has several
+ * children tags such as timing, location, or some general
+ * details. Each tag has attributes to describe them 
+ ********************************************************************/
+
+#include <fstream>
+#include <iostream>
+#include <string.h>
+#include <iomanip>
+#include <limits>
+#include "vpr_error.h"
+#include "globals.h"
+#include "read_xml_arch_file.h"
+#include "vtr_version.h"
+#include "rr_graph_obj.h"
+#include "write_xml_rr_graph_obj.h"
+
+using namespace std;
+
+/* All values are printed with this precision value. The higher the
+ * value, the more accurate the read in rr graph is. Using numeric_limits
+ * max_digits10 guarentees that no values change during a sequence of
+ * float -> string -> float conversions */
+constexpr int FLOAT_PRECISION = std::numeric_limits<float>::max_digits10;
+
+/*********************** External Subroutines to this module *******************/
+void add_metadata_to_xml(fstream &fp, const char *tab_prefix, const t_metadata_dict & meta);
+void write_rr_channel(fstream &fp);
+void write_rr_grid(fstream &fp);
+void write_rr_block_types(fstream &fp);
+
+/*********************** Subroutines local to this module *******************/
+void write_rr_graph_node(fstream &fp, const RRGraph& rr_graph);
+void write_rr_graph_switches(fstream &fp, const RRGraph& rr_graph);
+void write_rr_graph_edges(fstream &fp, const RRGraph& rr_graph);
+void write_rr_graph_segments(fstream &fp, const RRGraph& rr_graph);
+
+/************************ Subroutine definitions ****************************/
+
+/* This function is used to write the rr_graph into xml format into a a file with name: file_name */
+void write_xml_rr_graph_obj(const char *file_name, const RRGraph& rr_graph) {
+    fstream fp;
+    fp.open(file_name, fstream::out | fstream::trunc);
+
+    /* Prints out general info for easy error checking*/
+    if (!fp.is_open() || !fp.good()) {
+        vpr_throw(VPR_ERROR_OTHER, __FILE__, __LINE__,
+                "couldn't open file \"%s\" for generating RR graph file\n", file_name);
+    }
+    cout << "Writing RR graph" << endl;
+    fp << "<rr_graph tool_name=\"vpr\" tool_version=\"" << vtr::VERSION <<
+            "\" tool_comment=\"Generated from arch file "
+            << get_arch_file_name() << "\">" << endl;
+
+    /* Write out each individual component
+     * Use existing write_rr_* functions as much as possible
+     * 1. For those using external data structures outside RRGraph, 
+     *    leave as it is.
+     * 2. For those using RRGraph internal data, 
+     *    write new functions 
+     */
+    write_rr_channel(fp);
+    write_rr_graph_switches(fp, rr_graph);
+    write_rr_graph_segments(fp, rr_graph);
+    write_rr_block_types(fp);
+    write_rr_grid(fp);
+    write_rr_graph_node(fp, rr_graph);
+    write_rr_graph_edges(fp, rr_graph);
+    fp << "</rr_graph>";
+
+    fp.close();
+
+    cout << "Finished generating RR graph file named " << file_name << endl << endl;
+}
+
+/* All relevant rr node info is written out to the graph.
+ * This includes location, timing, and segment info
+ */
+void write_rr_graph_node(fstream &fp, const RRGraph& rr_graph) {
+  /* TODO: we should make it function full independent from device_ctx !!! */
+  auto& device_ctx = g_vpr_ctx.device();
+
+  fp << "\t<rr_nodes>" << endl;
+
+  for (auto node : rr_graph.nodes()) {
+    fp << "\t\t<node";
+    fp << " id=\"" << rr_graph.node_index(node);
+    fp << "\" type=\"" << rr_node_typename[rr_graph.node_type(node)];
+    if (CHANX == rr_graph.node_type(node) || CHANY == rr_graph.node_type(node)) {
+      fp << "\" direction=\"" << DIRECTION_STRING[rr_graph.node_direction(node)];
+    }
+    fp << "\" capacity=\"" << rr_graph.node_capacity(node);
+    fp << "\">" << endl;
+    fp << "\t\t\t<loc";
+    fp << " xlow=\"" << rr_graph.node_xlow(node);
+    fp << "\" ylow=\"" << rr_graph.node_ylow(node);
+    fp << "\" xhigh=\"" << rr_graph.node_xhigh(node);
+    fp << "\" yhigh=\"" << rr_graph.node_yhigh(node);
+    if (IPIN == rr_graph.node_type(node) || OPIN == rr_graph.node_type(node)) {
+      fp << "\" side=\"" << SIDE_STRING[rr_graph.node_side(node)];
+    }
+    fp << "\" ptc=\"" << rr_graph.node_ptc_num(node) ;
+    fp << "\"/>" << endl;
+    fp << "\t\t\t<timing R=\"" << setprecision(FLOAT_PRECISION) << rr_graph.node_R(node)
+            << "\" C=\"" << setprecision(FLOAT_PRECISION) << rr_graph.node_C(node) << "\"/>" << endl;
+
+    if (RRSegmentId::INVALID() != rr_graph.node_segment(node)) {
+      fp << "\t\t\t<segment segment_id=\"" << size_t(rr_graph.node_segment(node)) << "\"/>" << endl;
+    }
+
+    const auto iter = device_ctx.rr_node_metadata.find(rr_graph.node_index(node));
+    if(iter != device_ctx.rr_node_metadata.end()) {
+      const t_metadata_dict & meta = iter->second;
+      add_metadata_to_xml(fp, "\t\t\t", meta);
+    }
+
+    fp << "\t\t</node>" << endl;
+  }
+
+  fp << "\t</rr_nodes>" << endl << endl;
+
+  return;
+}
+
+/* Segment information in the t_segment_inf data structure is written out.
+ * Information includes segment id, name, and optional timing parameters
+ */
+void write_rr_graph_segments(fstream &fp, const RRGraph& rr_graph) {
+  fp << "\t<segments>" << endl;
+
+  for (auto seg : rr_graph.segments()) {
+    fp << "\t\t<segment id=\"" << rr_graph.segment_index(seg) <<
+          "\" name=\"" << rr_graph.get_segment(seg).name << "\">" << endl;
+    fp << "\t\t\t<timing R_per_meter=\"" << setprecision(FLOAT_PRECISION) << rr_graph.get_segment(seg).Rmetal <<
+          "\" C_per_meter=\"" <<setprecision(FLOAT_PRECISION) << rr_graph.get_segment(seg).Cmetal << "\"/>" << endl;
+    fp << "\t\t</segment>" << endl;
+  }
+  fp << "\t</segments>" << endl << endl;
+
+  return;
+}
+
+/* Switch info is written out into xml format. This includes
+ * general, sizing, and optional timing information
+ */
+void write_rr_graph_switches(fstream &fp, const RRGraph& rr_graph) {
+  fp << "\t<switches>" << endl;
+
+  for (auto rr_switch : rr_graph.switches()) {
+    fp << "\t\t<switch id=\"" << rr_graph.switch_index(rr_switch);
+    t_rr_switch_inf cur_switch = rr_graph.get_switch(rr_switch);
+
+    if (cur_switch.type() == SwitchType::TRISTATE) {
+      fp << "\" type=\"tristate";
+    } else if (cur_switch.type() == SwitchType::MUX) {
+      fp << "\" type=\"mux";
+    } else if (cur_switch.type() == SwitchType::PASS_GATE) {
+      fp << "\" type=\"pass_gate";
+    } else if (cur_switch.type() == SwitchType::SHORT) {
+      fp << "\" type=\"short";
+    } else if (cur_switch.type() == SwitchType::BUFFER) {
+      fp << "\" type=\"buffer";
+    } else {
+      VPR_THROW(VPR_ERROR_ROUTE, "Invalid switch type %d\n", cur_switch.type());
+    }
+    fp << "\"";
+
+    if (cur_switch.name) {
+      fp << " name=\"" << cur_switch.name << "\"";
+    }
+    fp << ">" << endl;
+
+    fp << "\t\t\t<timing R=\"" << setprecision(FLOAT_PRECISION) << cur_switch.R <<
+          "\" Cin=\"" << setprecision(FLOAT_PRECISION) << cur_switch.Cin <<
+          "\" Cout=\"" << setprecision(FLOAT_PRECISION) << cur_switch.Cout <<
+          "\" Tdel=\"" << setprecision(FLOAT_PRECISION) << cur_switch.Tdel << "\"/>" << endl;
+    fp << "\t\t\t<sizing mux_trans_size=\"" << setprecision(FLOAT_PRECISION) << cur_switch.mux_trans_size <<
+          "\" buf_size=\"" << setprecision(FLOAT_PRECISION) << cur_switch.buf_size << "\"/>" << endl;
+    fp << "\t\t</switch>" << endl;
+  }
+  fp << "\t</switches>" << endl << endl;
+
+  return;
+}
+
+/* Edges connecting to each rr node is printed out. The two nodes
+ * it connects to are also printed
+ */
+void write_rr_graph_edges(fstream &fp, const RRGraph& rr_graph) {
+  auto& device_ctx = g_vpr_ctx.device();
+  fp << "\t<rr_edges>" << endl;
+
+  for (auto node : rr_graph.nodes()) {
+    for (auto edge: rr_graph.node_out_edges(node)) {
+      fp << "\t\t<edge src_node=\"" << rr_graph.node_index(node) <<
+            "\" sink_node=\"" << rr_graph.node_index(rr_graph.edge_sink_node(edge)) <<
+            "\" switch_id=\"" << rr_graph.switch_index(rr_graph.edge_switch(edge)) << "\"";
+
+      bool wrote_edge_metadata = false;
+      const auto iter = device_ctx.rr_edge_metadata.find( std::make_tuple(rr_graph.node_index(node), 
+                                                          rr_graph.node_index(rr_graph.edge_sink_node(edge)),
+                                                          rr_graph.switch_index(rr_graph.edge_switch(edge))) );
+      if(iter != device_ctx.rr_edge_metadata.end()) {
+        fp << ">" << endl;
+
+        const t_metadata_dict & meta = iter->second;
+        add_metadata_to_xml(fp, "\t\t\t", meta);
+        wrote_edge_metadata = true;
+      }
+
+      if(wrote_edge_metadata == false) {
+        fp << "/>" << endl;
+      } else {
+        fp << "\t\t</edge>" << endl;
+      }
+    }
+  }
+  fp << "\t</rr_edges>" << endl << endl;
+}
diff --git a/vpr/src/device/write_xml_rr_graph_obj.h b/vpr/src/device/write_xml_rr_graph_obj.h
new file mode 100644
index 000000000..7337ff958
--- /dev/null
+++ b/vpr/src/device/write_xml_rr_graph_obj.h
@@ -0,0 +1,12 @@
+/*********************************************************************
+ * This function writes the RR_graph generated by VPR into a file in XML format
+ * Information included in the file includes rr nodes, rr switches, 
+ * the grid, block info, node indices
+ ********************************************************************/
+
+#ifndef WRITE_XML_RR_GRAPH_OBJ_H
+#define WRITE_XML_RR_GRAPH_OBJ_H
+
+void write_xml_rr_graph_obj(const char *file_name, const RRGraph& rr_graph);
+
+#endif
diff --git a/vpr/valgrind.supp b/vpr/valgrind.supp
deleted file mode 100644
index 6bd7272c4..000000000
--- a/vpr/valgrind.supp
+++ /dev/null
@@ -1,711 +0,0 @@
-#
-# Valgrind suppression file for EZGL
-#
-
-#pango
-{
-	libpango
-	Memcheck:Leak
-	...
-	obj:/usr/lib*/libpango*
-}
-
-#GTK
-{
-	g_type_register
-	Memcheck:Leak
-	fun:*alloc
-	...
-	fun:g_type_register_*
-	...
-	fun:_dl_init
-	...
-}
-
-{
-	g_quark_from_static_string
-	Memcheck:Leak
-	fun:*alloc
-	...
-	fun:g_quark_from_static_string
-	...
-	fun:_dl_init
-	...
-}
-
-{
-	g_main_thread
-	Memcheck:Leak
-	fun:*alloc
-	...
-	fun:g_main*
-	...
-	fun:start_thread
-	fun:clone
-}
-
-{
-	g_closure
-	Memcheck:Leak
-	match-leak-kinds:possible
-	fun:*alloc
-	...
-	fun:g_cclosure_new
-	fun:g_signal_connect_data
-	...
-}
-
-# 
-{
-	g_object
-	Memcheck:Leak
-	match-leak-kinds:possible
-	...
-	fun:g_object_new
-	...
-}
-
-{
-	g_type_register_static
-	Memcheck:Leak
-	match-leak-kinds:possible
-	...
-	fun:g_type_register_static
-	...
-}
-
-{
-	g_signal_connect_closure
-	Memcheck:Leak
-	match-leak-kinds:possible
-	...
-	fun:g_signal_connect_closure
-	fun:gtk_*group*
-	...
-}
-
-{
-	gtk_module_init
-	Memcheck:Leak
-	
-	fun:*alloc
-	...
-	fun:gtk_module_init
-	...
-}
-
-{
-	g_closure_invoke
-	Memcheck:Leak
-	
-	fun:*alloc
-	...
-	fun:g_closure_invoke
-	...
-}
-
-{
-	gtk_style_context_set_state
-	Memcheck:Leak
-	
-	fun:*alloc
-	...
-	fun:gtk_style_context_set_state
-	...
-}
-
-# 
-{
-	call_init
-	Memcheck:Leak
-	
-	fun:*alloc
-	...
-	fun:call_init
-	fun:_dl_init
-	...
-}
-
-{
-	XML_ParseBuffer
-	Memcheck:Leak
-	fun:*alloc
-	...
-	fun:XML_ParseBuffer
-	...
-}
-
-{
-	FcConfigParseAndLoad
-	Memcheck:Leak
-	fun:*alloc
-	...
-	fun:FcConfigParseAndLoad
-	...
-}
-
-# 
-{
-	g_objectv
-	Memcheck:Leak
-	
-	...
-	fun:g_object_newv
-	...
-}
-
-{
-	g_type_add_interface_static
-	Memcheck:Leak
-	match-leak-kinds:possible
-	...
-	fun:g_type_add_interface_static
-	...
-}
-
-{
-	gtk_container_get_children
-	Memcheck:Leak
-	fun:*alloc
-	...
-	fun:gtk_container_get_children
-	...
-}
-
-{
-	cairo_select_font_face
-	Memcheck:Leak
-	fun:*alloc
-	...
-	fun:cairo_select_font_face
-	...
-}
-
-{
-	libfontconfig
-	Memcheck:Leak
-	fun:*alloc
-	...
-	obj:*libfontconfig.so.*
-	...
-}
-
-{
-	X11_XGetDefault
-	Memcheck:Leak
-	fun:realloc
-	obj:*libX11.so.6.3.0
-	obj:*libX11.so.6.3.0
-	obj:*libX11.so.6.3.0
-	fun:_XlcCreateLC
-	fun:_XlcDefaultLoader
-	fun:_XOpenLC
-	fun:_XrmInitParseInfo
-	obj:*libX11.so.6.3.0
-	fun:XrmGetStringDatabase
-	obj:*libX11.so.6.3.0
-	fun:XGetDefault
-}
-
-{
-	XInternAtom_via_event_loop
-	Memcheck:Leak
-	fun:*alloc
-	fun:_XEnq
-	obj:*libX11.so.6.3.0
-	fun:_XReply
-	fun:XInternAtom
-	...
-}
-
-{
-	cairo_deep_*alloc
-	Memcheck:Leak
-	fun:*alloc
-	obj:*libcairo.*
-	...
-}
-
-#openmp
-{
-	GOMP_parallel
-	Memcheck:Leak
-	
-	fun:*alloc
-	fun:allocate_dtv
-	fun:_dl_allocate_tls
-	fun:allocate_stack
-	fun:pthread_create@@GLIBC_2.2.5
-	...
-}
-
-
-#GTK engines
-{
-	engines
-	Memcheck:Leak
-	fun:*alloc
-	...
-	obj:/usr/lib*/gtk*/*/engines*
-	...
-	obj:/usr/lib*/libgtk*
-}
-
-#nvidia
-{
-	libGL
-	Memcheck:Leak
-	...
-	obj:/usr/lib*/libGL.so*
-}
-{
-   <insert_a_suppression_name_here>
-   Memcheck:Leak
-   fun:*alloc
-   ...
-   fun:g_socket_create_source
-   ...
-   fun:g_main_context_dispatch
-}
-{
-   <insert_a_suppression_name_here>
-   Memcheck:Leak
-   fun:*alloc
-   ...
-   fun:g_type_class_ref
-   ...
-   fun:gtk_init_check
-   fun:gtk_init
-   obj:*libgtk-3*
-}
-{
-   <insert_a_suppression_name_here>
-   Memcheck:Leak
-   fun:*alloc
-   ...
-   fun:g_markup_parse_context_parse
-   obj:*libgtk-3*
-}
-{
-   <insert_a_suppression_name_here>
-   Memcheck:Leak
-   fun:*alloc
-   ...
-   fun:g_socket_new
-   obj:*libgio-2*
-   fun:g_socket_client_connect
-   obj:*libgio-2*
-}
-{
-   <insert_a_suppression_name_here>
-   Memcheck:Leak
-   fun:*alloc
-   ...
-   fun:atk_add_focus_tracker
-   obj:*libgtk-3*
-   ...
-   fun:gtk_parse_args
-   fun:gtk_init_check
-}
-{
-   <insert_a_suppression_name_here>
-   Memcheck:Leak
-   fun:m*alloc
-   ...
-   fun:g_bus_get_sync
-   ...
-   fun:g_application_register
-   obj:*libgio-2*
-   fun:g_application_run
-}
-{
-   <insert_a_suppression_name_here>
-   Memcheck:Leak
-   fun:*alloc
-   ...
-   obj:*libgtk-3*
-   fun:g_closure_invoke
-   ...
-   fun:g_signal_emit_valist
-   fun:g_signal_emit
-}
-{
-   <insert_a_suppression_name_here>
-   Memcheck:Leak
-   fun:*alloc
-   ...
-   fun:g_simple_async_result_complete
-   ...
-   fun:g_main_context_dispatch
-   ...
-}
-{
-   <insert_a_suppression_name_here>
-   Memcheck:Leak
-   fun:*alloc
-   ...
-   fun:g_type_class_ref
-   ...
-   fun:atk_add_focus_tracker
-   obj:*libgtk-3*
-   ...
-   fun:g_option_context_parse
-}
-{
-   <insert_a_suppression_name_here>
-   Memcheck:Leak
-   fun:*alloc
-   ...
-   fun:g_type_class_ref
-   obj:*libgtk-3*
-   fun:atk_add_focus_tracker
-   obj:*libgtk-3*
-}
-{
-   <insert_a_suppression_name_here>
-   Memcheck:Leak
-   fun:*alloc
-   ...
-   fun:g_type_class_ref
-   obj:*libgtk-3*
-}
-{
-   <insert_a_suppression_name_here>
-   Memcheck:Leak
-   fun:*alloc
-   ...
-   fun:g_dbus_proxy_new_sync
-   obj:*libgtk-3*
-}
-{
-   <insert_a_suppression_name_here>
-   Memcheck:Leak
-   fun:*alloc
-   ...
-   fun:g_signal_new
-   ...
-   obj:*libgobject-2*
-   fun:g_type_class_ref
-   fun:g_object_new_valist
-   fun:g_initable_new_valist
-   fun:g_initable_new
-}
-{
-   <insert_a_suppression_name_here>
-   Memcheck:Leak 
-   fun:*alloc
-   ...
-   fun:g_signal_new
-   obj:*libgtk-3*
-   fun:g_type_class_ref
-   obj:*libgtk-3*
-   ...
-}
-{
-   <insert_a_suppression_name_here>
-   Memcheck:Leak
-   fun:*alloc
-   ...
-   fun:g_signal_new
-   obj:*libgtk-3*
-   ...
-   fun:g_type_class_ref
-   obj:*libgtk-3*
-   ...
-}
-{
-   <insert_a_suppression_name_here>
-   Memcheck:Leak
-   
-   fun:*alloc
-   ...
-   fun:g_type_class_ref
-   obj:*libgtk-3*
-   fun:atk_add_focus_tracker
-   obj:*libgtk-3*
-   ...
-   fun:g_option_context_parse
-}
-{
-   <insert_a_suppression_name_here>
-   Memcheck:Leak
-   
-   fun:*alloc
-   ...
-   fun:g_signal_new_class_handler
-   obj:*libgtk-3*
-   ...
-   fun:g_type_class_ref
-   obj:*libgtk-3*
-   ...
-}
-{
-   <insert_a_suppression_name_here>
-   Memcheck:Leak  
-   fun:*alloc
-   ...
-   fun:g_signal_connect_data
-   obj:*libgtk-3*
-   ...
-   fun:gtk_widget_show
-   obj:*libgtk-3*
-   ...
-}
-{
-   <insert_a_suppression_name_here>
-   Memcheck:Leak
-   fun:*alloc
-   ...
-   fun:g_type_class_ref
-   fun:g_object_new_valist
-   fun:g_initable_new_valist
-   fun:g_initable_new
-   fun:gvfs_dbus_mount_tracker_proxy_new_for_bus_sync
-   ...
-   fun:g_type_create_instance
-}
-{
-   <insert_a_suppression_name_here>
-   Memcheck:Leak
-   fun:*alloc
-   fun:g_*alloc
-   ...
-   fun:g_type_class_ref
-   obj:*libgtk-3*
-   ...
-   fun:g_markup_parse_context_parse
-}
-{
-   <insert_a_suppression_name_here>
-   Memcheck:Leak
-   fun:*alloc
-   ...
-   fun:g_type_class_ref
-   obj:*libgtk-3*
-   ...
-   fun:g_option_context_parse
-   fun:gtk_parse_args
-   fun:gtk_init_check
-}
-{
-   <insert_a_suppression_name_here>
-   Memcheck:Leak
-   fun:*alloc
-   ...
-   fun:g_type_class_ref
-   fun:atk_bridge_adaptor_init
-   obj:*libgtk-3*
-   ...
-   fun:g_option_context_parse
-   fun:gtk_parse_args
-   fun:gtk_init_check
-   fun:gtk_init
-}
-{
-   <insert_a_suppression_name_here>
-   Memcheck:Leak
-   fun:*alloc
-   ...
-   fun:g_signal_new
-   ...
-   fun:g_type_class_ref
-   obj:*libgtk-3*
-   fun:atk_add_focus_tracker
-   obj:*libgtk-3*
-}
-{
-   <insert_a_suppression_name_here>
-   Memcheck:Leak
-   
-   fun:*alloc
-   ...
-   fun:g_signal_new
-   ...
-   fun:g_type_class_ref
-   obj:*libgtk-3*
-}
-{
-   <insert_a_suppression_name_here>
-   Memcheck:Leak  
-   fun:*alloc
-   ...
-   fun:g_signal_new
-   ...
-   fun:g_initable_new
-}
-{
-   <insert_a_suppression_name_here>
-   Memcheck:Leak
-   fun:*alloc
-   ...
-   fun:g_signal_new
-   obj:*libgtk-3*
-   fun:g_type_class_ref
-   obj:*libgtk-3*
-   ...
-}
-{
-   <insert_a_suppression_name_here>
-   Memcheck:Leak
-   fun:*alloc
-   ...
-   fun:g_signal_new
-   ...
-   fun:g_type_class_ref
-   obj:*libgtk-3*
-   ...
-}
-{
-   <insert_a_suppression_name_here>
-   Memcheck:Leak 
-   fun:*alloc
-   ...
-   fun:g_signal_new
-   ...
-   fun:g_type_class_ref
-   obj:*libgtk-3*
-   ...
-}
-{
-   <insert_a_suppression_name_here>
-   Memcheck:Leak
-   fun:*alloc
-   ...
-   fun:g_signal_new
-   ...
-   fun:g_type_class_ref
-   obj:*libgtk-3*
-   ...
-}
-{
-   <insert_a_suppression_name_here>
-   Memcheck:Leak 
-   fun:*alloc
-   ...
-   fun:g_signal_new
-   ...
-   fun:g_type_class_ref
-   obj:*libgio-2.0.so.0.4002.0
-   ...
-}
-{
-   <insert_a_suppression_name_here>
-   Memcheck:Leak
-   fun:*alloc
-   ...
-   fun:g_signal_new_class_handler
-   ...
-   fun:g_type_class_ref
-   obj:*libgtk-3*
-   ...
-}
-{
-   <insert_a_suppression_name_here>
-   Memcheck:Leak
-   fun:*alloc
-   ...
-   fun:g_signal_connect_data
-   ...
-   fun:gtk_widget_show
-   obj:*libgtk-3*
-   ...
-}
-{
-   <insert_a_suppression_name_here>
-   Memcheck:Leak
-   fun:*alloc
-   ...
-   fun:g_initable_new
-   ...
-   fun:g_type_create_instance
-}
-{
-   <insert_a_suppression_name_here>
-   Memcheck:Leak
-   fun:*alloc
-   ...
-   fun:g_type_class_ref
-   obj:*libgtk-3*
-   ...
-   fun:g_markup_parse_context_parse
-}
-{
-   <insert_a_suppression_name_here>
-   Memcheck:Leak
-   fun:malloc
-   ...
-   fun:g_type_class_ref
-   obj:*libgtk-3*
-   ...
-   fun:gtk_init_check
-}
-{
-   <insert_a_suppression_name_here>
-   Memcheck:Leak
-   fun:malloc
-   ...
-   fun:atk_bridge_adaptor_init
-   obj:*libgtk-3*
-   ...
-   fun:gtk_init
-}
-{
-   <insert_a_suppression_name_here>
-   Memcheck:Leak
-   fun:*alloc
-   ...
-   fun:g_application_register
-   obj:*libgio-2*
-}
-{
-   <insert_a_suppression_name_here>
-   Memcheck:Leak
-   fun:*alloc
-   ...
-   fun:g_thread_new
-   obj:*libgio-2*
-}
-{
-   <insert_a_suppression_name_here>
-   Memcheck:Leak
-   fun:*alloc
-   ...
-   fun:g_thread_pool_push
-   ...
-   fun:g_bus_get
-   fun:g_bus_watch_name
-}
-{
-   <insert_a_suppression_name_here>
-   Memcheck:Leak
-   match-leak-kinds: possible
-   fun:*alloc
-   ...
-   fun:g_param_spec_enum
-   ...
-   fun:g_bus_get_sync
-   obj:*libgio-*
-   fun:g_application_register
-}
-{
-   <insert_a_suppression_name_here>
-   Memcheck:Leak
-   match-leak-kinds: possible
-   fun:*alloc
-   fun:g_realloc
-   ...
-   fun:gtk_button_set_image_position
-   fun:g_object_setv
-   ...
-   obj:*libgtk-3*
-}
-{
-   <insert_a_suppression_name_here>
-   Memcheck:Leak
-   match-leak-kinds: possible
-   fun:*alloc
-   ...
-   fun:gtk_cell_renderer_render
-   ...
-   obj:*libgtk-3*
-}
\ No newline at end of file

From 5006a4395d116acbfec6e87ab72e28d6f32cda99 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 31 Jan 2020 16:39:40 -0700
Subject: [PATCH 062/645] bring RRGraph object and writer online

---
 libs/libarchfpga/src/physical_types.h      |   5 +-
 openfpga/test_script/s298_k6_frac.openfpga |   2 +-
 vpr/src/base/vpr_context.h                 |   5 +
 vpr/src/device/create_rr_graph.cpp         | 138 ++++
 vpr/src/device/create_rr_graph.h           |  17 +
 vpr/src/device/write_xml_rr_graph_obj.cpp  |  97 +--
 vpr/src/route/rr_graph.cpp                 |  17 +
 vpr/valgrind.supp                          | 711 +++++++++++++++++++++
 8 files changed, 948 insertions(+), 44 deletions(-)
 create mode 100644 vpr/src/device/create_rr_graph.cpp
 create mode 100644 vpr/src/device/create_rr_graph.h
 create mode 100644 vpr/valgrind.supp

diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h
index 153fd981e..c72a57378 100644
--- a/libs/libarchfpga/src/physical_types.h
+++ b/libs/libarchfpga/src/physical_types.h
@@ -163,9 +163,10 @@ enum e_interconnect {
     COMPLETE_INTERC = 1,
     DIRECT_INTERC = 2,
     MUX_INTERC = 3,
-    NUM_INTERC_TYPES
+    NUM_INTERC_TYPES /* Xifan Tang - Invalid types for interconnect */
 };
-constexpr std::array<const char*, NUM_INTERC_TYPES> INTERCONNECT_TYPE_STRING = {{"complete", "direct", "mux"}}; //String versions of interconnection type
+/* Xifan Tang - String versions of interconnection type */
+constexpr std::array<const char*, NUM_INTERC_TYPES> INTERCONNECT_TYPE_STRING = {{"complete", "direct", "mux"}}; 
 
 /* Orientations. */
 enum e_side : unsigned char {
diff --git a/openfpga/test_script/s298_k6_frac.openfpga b/openfpga/test_script/s298_k6_frac.openfpga
index 22e74cdb1..fa3dcf993 100644
--- a/openfpga/test_script/s298_k6_frac.openfpga
+++ b/openfpga/test_script/s298_k6_frac.openfpga
@@ -1,5 +1,5 @@
 # Run VPR for the s298 design
-vpr ./test_vpr_arch/k6_frac_N10_40nm.xml ./test_blif/s298.blif
+vpr ./test_vpr_arch/k6_frac_N10_40nm.xml ./test_blif/s298.blif --write_rr_graph example_rr_graph.xml
 
 # Read OpenFPGA architecture definition
 read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
diff --git a/vpr/src/base/vpr_context.h b/vpr/src/base/vpr_context.h
index b6a1f9859..2a99e9351 100644
--- a/vpr/src/base/vpr_context.h
+++ b/vpr/src/base/vpr_context.h
@@ -22,6 +22,8 @@
 #include "place_macro.h"
 #include "compressed_grid.h"
 
+#include "rr_graph_obj.h"
+
 //A Context is collection of state relating to a particular part of VPR
 //
 //This is a base class who's only purpose is to disable copying of contexts.
@@ -143,6 +145,9 @@ struct DeviceContext : public Context {
     /* chan_width is for x|y-directed channels; i.e. between rows */
     t_chan_width chan_width;
 
+    /* RRGraph object */
+    RRGraph rr_graph;
+
     /* Structures to define the routing architecture of the FPGA.           */
     std::vector<t_rr_node> rr_nodes; /* autogenerated in build_rr_graph */
 
diff --git a/vpr/src/device/create_rr_graph.cpp b/vpr/src/device/create_rr_graph.cpp
new file mode 100644
index 000000000..4ec054a52
--- /dev/null
+++ b/vpr/src/device/create_rr_graph.cpp
@@ -0,0 +1,138 @@
+/* Standard header files required go first */
+#include <map>
+
+/* EXTERNAL library header files go second*/
+#include "vtr_assert.h"
+#include "vtr_time.h"
+#include "vtr_memory.h"
+
+/* VPR header files go then */
+#include "vpr_types.h"
+#include "rr_graph_obj.h"
+#include "check_rr_graph_obj.h"
+#include "create_rr_graph.h"
+
+/* Finally we include global variables */
+#include "globals.h"
+
+/********************************************************************
+ * TODO: remove when this conversion (from traditional to new data structure)
+ * is no longer needed
+ * This function will convert an existing rr_graph in device_ctx to the RRGraph
+ *object
+ * This function is used to test our RRGraph if it is acceptable in downstream
+ *routers
+ ********************************************************************/
+void convert_rr_graph(std::vector<t_segment_inf>& vpr_segments) {
+    /* Release freed memory before start building rr_graph */
+    vtr::malloc_trim(0);
+
+    vtr::ScopedStartFinishTimer timer("Conversion to routing resource graph object");
+
+    /* IMPORTANT: to build clock tree,
+     * vpr added segments to the original arch segments
+     * This is why to use vpr_segments as an inputs!!!
+     */
+    auto& device_ctx = g_vpr_ctx.mutable_device();
+
+    /* The number of switches are in general small,
+     * reserve switches may not bring significant memory efficiency
+     * So, we just use create_switch to push_back each time
+     */
+    device_ctx.rr_graph.reserve_switches(device_ctx.rr_switch_inf.size());
+    // Create the switches
+    for (size_t iswitch = 0; iswitch < device_ctx.rr_switch_inf.size(); ++iswitch) {
+        device_ctx.rr_graph.create_switch(device_ctx.rr_switch_inf[iswitch]);
+    }
+
+    /* The number of segments are in general small, reserve segments may not bring
+     * significant memory efficiency */
+    device_ctx.rr_graph.reserve_segments(vpr_segments.size());
+    // Create the segments
+    for (size_t iseg = 0; iseg < vpr_segments.size(); ++iseg) {
+        device_ctx.rr_graph.create_segment(vpr_segments[iseg]);
+    }
+
+    /* Reserve list of nodes to be memory efficient */
+    device_ctx.rr_graph.reserve_nodes((unsigned long)device_ctx.rr_nodes.size());
+
+    // Create the nodes
+    for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); ++inode) {
+        auto& node = device_ctx.rr_nodes[inode];
+        RRNodeId rr_node = device_ctx.rr_graph.create_node(node.type());
+
+        device_ctx.rr_graph.set_node_xlow(rr_node, node.xlow());
+        device_ctx.rr_graph.set_node_ylow(rr_node, node.ylow());
+        device_ctx.rr_graph.set_node_xhigh(rr_node, node.xhigh());
+        device_ctx.rr_graph.set_node_yhigh(rr_node, node.yhigh());
+
+        device_ctx.rr_graph.set_node_capacity(rr_node, node.capacity());
+
+        device_ctx.rr_graph.set_node_ptc_num(rr_node, node.ptc_num());
+
+        device_ctx.rr_graph.set_node_cost_index(rr_node, node.cost_index());
+
+        if (CHANX == node.type() || CHANY == node.type()) {
+            device_ctx.rr_graph.set_node_direction(rr_node, node.direction());
+        }
+        if (IPIN == node.type() || OPIN == node.type()) {
+            device_ctx.rr_graph.set_node_side(rr_node, node.side());
+        }
+        device_ctx.rr_graph.set_node_R(rr_node, node.R());
+        device_ctx.rr_graph.set_node_C(rr_node, node.C());
+
+        /* Set up segment id */
+        short irc_data = node.cost_index();
+        short iseg = device_ctx.rr_indexed_data[irc_data].seg_index;
+        device_ctx.rr_graph.set_node_segment(rr_node, RRSegmentId(iseg));
+    }
+
+    /* Reserve list of edges to be memory efficient */
+    unsigned long num_edges_to_reserve = 0;
+    for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); ++inode) {
+        const auto& node = device_ctx.rr_nodes[inode];
+        num_edges_to_reserve += node.num_edges();
+    }
+    device_ctx.rr_graph.reserve_edges(num_edges_to_reserve);
+
+    /* Add edges for each node */
+    for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); ++inode) {
+        const auto& node = device_ctx.rr_nodes[inode];
+        for (int iedge = 0; iedge < node.num_edges(); ++iedge) {
+            size_t isink_node = node.edge_sink_node(iedge);
+            int iswitch = node.edge_switch(iedge);
+
+            device_ctx.rr_graph.create_edge(RRNodeId(inode),
+                                            RRNodeId(isink_node),
+                                            RRSwitchId(iswitch));
+        }
+    }
+
+    /* Ensure that we reserved what we want */
+    VTR_ASSERT(num_edges_to_reserve == (unsigned long)device_ctx.rr_graph.edges().size());
+
+    /* Partition edges to be two class: configurable (1st part) and
+     * non-configurable (2nd part)
+     * See how the router will use the edges and determine the strategy
+     * if we want to partition the edges first or depends on the routing needs
+     */
+    device_ctx.rr_graph.rebuild_node_edges();
+
+    /* Essential check for rr_graph, build look-up and  */
+    if (false == device_ctx.rr_graph.validate()) {
+        /* Error out if built-in validator of rr_graph fails */
+        vpr_throw(VPR_ERROR_ROUTE,
+                  __FILE__,
+                  __LINE__,
+                  "Fundamental errors occurred when validating rr_graph object!\n");
+    }
+
+    /* Error out if advanced checker of rr_graph fails */
+    if (false == check_rr_graph(device_ctx.rr_graph)) {
+        vpr_throw(VPR_ERROR_ROUTE,
+                  __FILE__,
+                  __LINE__,
+                  "Advanced checking rr_graph object fails! Routing may still work "
+                  "but not smooth\n");
+    }
+}
diff --git a/vpr/src/device/create_rr_graph.h b/vpr/src/device/create_rr_graph.h
new file mode 100644
index 000000000..5cc57ec92
--- /dev/null
+++ b/vpr/src/device/create_rr_graph.h
@@ -0,0 +1,17 @@
+#ifndef CREATE_RR_GRAPH_H
+#define CREATE_RR_GRAPH_H
+
+/*
+ * Notes in include header files in a head file 
+ * Only include the neccessary header files 
+ * that is required by the data types in the function/class declarations!
+ */
+#include "rr_graph_obj.h"
+
+/* IMPORTANT: to build clock tree,
+ * vpr added segments to the original arch segments  
+ * This is why to use vpr_segments as an inputs!!!
+ */
+void convert_rr_graph(std::vector<t_segment_inf>& vpr_segments);
+
+#endif
diff --git a/vpr/src/device/write_xml_rr_graph_obj.cpp b/vpr/src/device/write_xml_rr_graph_obj.cpp
index 375d1ba52..10cdb273e 100644
--- a/vpr/src/device/write_xml_rr_graph_obj.cpp
+++ b/vpr/src/device/write_xml_rr_graph_obj.cpp
@@ -27,62 +27,36 @@ using namespace std;
 constexpr int FLOAT_PRECISION = std::numeric_limits<float>::max_digits10;
 
 /*********************** External Subroutines to this module *******************/
-void add_metadata_to_xml(fstream &fp, const char *tab_prefix, const t_metadata_dict & meta);
 void write_rr_channel(fstream &fp);
 void write_rr_grid(fstream &fp);
 void write_rr_block_types(fstream &fp);
 
-/*********************** Subroutines local to this module *******************/
-void write_rr_graph_node(fstream &fp, const RRGraph& rr_graph);
-void write_rr_graph_switches(fstream &fp, const RRGraph& rr_graph);
-void write_rr_graph_edges(fstream &fp, const RRGraph& rr_graph);
-void write_rr_graph_segments(fstream &fp, const RRGraph& rr_graph);
-
 /************************ Subroutine definitions ****************************/
+static 
+void add_metadata_to_xml(std::fstream& fp, const char* tab_prefix, const t_metadata_dict& meta) {
+    fp << tab_prefix << "<metadata>" << std::endl;
 
-/* This function is used to write the rr_graph into xml format into a a file with name: file_name */
-void write_xml_rr_graph_obj(const char *file_name, const RRGraph& rr_graph) {
-    fstream fp;
-    fp.open(file_name, fstream::out | fstream::trunc);
-
-    /* Prints out general info for easy error checking*/
-    if (!fp.is_open() || !fp.good()) {
-        vpr_throw(VPR_ERROR_OTHER, __FILE__, __LINE__,
-                "couldn't open file \"%s\" for generating RR graph file\n", file_name);
+    for (const auto& meta_elem : meta) {
+        const std::string& key = meta_elem.first;
+        const std::vector<t_metadata_value>& values = meta_elem.second;
+        for (const auto& value : values) {
+            fp << tab_prefix << "\t<meta name=\"" << key << "\"";
+            fp << ">" << value.as_string() << "</meta>" << std::endl;
+        }
     }
-    cout << "Writing RR graph" << endl;
-    fp << "<rr_graph tool_name=\"vpr\" tool_version=\"" << vtr::VERSION <<
-            "\" tool_comment=\"Generated from arch file "
-            << get_arch_file_name() << "\">" << endl;
-
-    /* Write out each individual component
-     * Use existing write_rr_* functions as much as possible
-     * 1. For those using external data structures outside RRGraph, 
-     *    leave as it is.
-     * 2. For those using RRGraph internal data, 
-     *    write new functions 
-     */
-    write_rr_channel(fp);
-    write_rr_graph_switches(fp, rr_graph);
-    write_rr_graph_segments(fp, rr_graph);
-    write_rr_block_types(fp);
-    write_rr_grid(fp);
-    write_rr_graph_node(fp, rr_graph);
-    write_rr_graph_edges(fp, rr_graph);
-    fp << "</rr_graph>";
-
-    fp.close();
-
-    cout << "Finished generating RR graph file named " << file_name << endl << endl;
+    fp << tab_prefix << "</metadata>" << std::endl;
 }
 
 /* All relevant rr node info is written out to the graph.
  * This includes location, timing, and segment info
  */
+static 
 void write_rr_graph_node(fstream &fp, const RRGraph& rr_graph) {
   /* TODO: we should make it function full independent from device_ctx !!! */
   auto& device_ctx = g_vpr_ctx.device();
 
+  std::array<const char*, NUM_DIRECTIONS> DIRECTION_STRING_WRITE_XML = {{"INC_DIR", "DEC_DIR", "BI_DIR", "NO_DIR"}};
+
   fp << "\t<rr_nodes>" << endl;
 
   for (auto node : rr_graph.nodes()) {
@@ -90,7 +64,7 @@ void write_rr_graph_node(fstream &fp, const RRGraph& rr_graph) {
     fp << " id=\"" << rr_graph.node_index(node);
     fp << "\" type=\"" << rr_node_typename[rr_graph.node_type(node)];
     if (CHANX == rr_graph.node_type(node) || CHANY == rr_graph.node_type(node)) {
-      fp << "\" direction=\"" << DIRECTION_STRING[rr_graph.node_direction(node)];
+      fp << "\" direction=\"" << DIRECTION_STRING_WRITE_XML[rr_graph.node_direction(node)];
     }
     fp << "\" capacity=\"" << rr_graph.node_capacity(node);
     fp << "\">" << endl;
@@ -128,6 +102,7 @@ void write_rr_graph_node(fstream &fp, const RRGraph& rr_graph) {
 /* Segment information in the t_segment_inf data structure is written out.
  * Information includes segment id, name, and optional timing parameters
  */
+static 
 void write_rr_graph_segments(fstream &fp, const RRGraph& rr_graph) {
   fp << "\t<segments>" << endl;
 
@@ -146,6 +121,7 @@ void write_rr_graph_segments(fstream &fp, const RRGraph& rr_graph) {
 /* Switch info is written out into xml format. This includes
  * general, sizing, and optional timing information
  */
+static 
 void write_rr_graph_switches(fstream &fp, const RRGraph& rr_graph) {
   fp << "\t<switches>" << endl;
 
@@ -176,6 +152,7 @@ void write_rr_graph_switches(fstream &fp, const RRGraph& rr_graph) {
     fp << "\t\t\t<timing R=\"" << setprecision(FLOAT_PRECISION) << cur_switch.R <<
           "\" Cin=\"" << setprecision(FLOAT_PRECISION) << cur_switch.Cin <<
           "\" Cout=\"" << setprecision(FLOAT_PRECISION) << cur_switch.Cout <<
+          "\" Cinternal=\"" << setprecision(FLOAT_PRECISION) << cur_switch.Cinternal <<
           "\" Tdel=\"" << setprecision(FLOAT_PRECISION) << cur_switch.Tdel << "\"/>" << endl;
     fp << "\t\t\t<sizing mux_trans_size=\"" << setprecision(FLOAT_PRECISION) << cur_switch.mux_trans_size <<
           "\" buf_size=\"" << setprecision(FLOAT_PRECISION) << cur_switch.buf_size << "\"/>" << endl;
@@ -189,6 +166,7 @@ void write_rr_graph_switches(fstream &fp, const RRGraph& rr_graph) {
 /* Edges connecting to each rr node is printed out. The two nodes
  * it connects to are also printed
  */
+static 
 void write_rr_graph_edges(fstream &fp, const RRGraph& rr_graph) {
   auto& device_ctx = g_vpr_ctx.device();
   fp << "\t<rr_edges>" << endl;
@@ -220,3 +198,40 @@ void write_rr_graph_edges(fstream &fp, const RRGraph& rr_graph) {
   }
   fp << "\t</rr_edges>" << endl << endl;
 }
+
+/* This function is used to write the rr_graph into xml format into a a file with name: file_name */
+void write_xml_rr_graph_obj(const char *file_name, const RRGraph& rr_graph) {
+    fstream fp;
+    fp.open(file_name, fstream::out | fstream::trunc);
+
+    /* Prints out general info for easy error checking*/
+    if (!fp.is_open() || !fp.good()) {
+        vpr_throw(VPR_ERROR_OTHER, __FILE__, __LINE__,
+                "couldn't open file \"%s\" for generating RR graph file\n", file_name);
+    }
+    cout << "Writing RR graph" << endl;
+    fp << "<rr_graph tool_name=\"vpr\" tool_version=\"" << vtr::VERSION <<
+            "\" tool_comment=\"Generated from arch file "
+            << get_arch_file_name() << "\">" << endl;
+
+    /* Write out each individual component
+     * Use existing write_rr_* functions as much as possible
+     * 1. For those using external data structures outside RRGraph, 
+     *    leave as it is.
+     * 2. For those using RRGraph internal data, 
+     *    write new functions 
+     */
+    write_rr_channel(fp);
+    write_rr_graph_switches(fp, rr_graph);
+    write_rr_graph_segments(fp, rr_graph);
+    write_rr_block_types(fp);
+    write_rr_grid(fp);
+    write_rr_graph_node(fp, rr_graph);
+    write_rr_graph_edges(fp, rr_graph);
+    fp << "</rr_graph>";
+
+    fp.close();
+
+    cout << "Finished generating RR graph file named " << file_name << endl << endl;
+}
+
diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp
index df1bb8b09..6bb9892ed 100644
--- a/vpr/src/route/rr_graph.cpp
+++ b/vpr/src/route/rr_graph.cpp
@@ -36,6 +36,9 @@
 
 #include "rr_types.h"
 
+#include "create_rr_graph.h"
+#include "write_xml_rr_graph_obj.h"
+
 //#define VERBOSE
 
 struct t_mux {
@@ -331,6 +334,9 @@ void create_rr_graph(const t_graph_type graph_type,
                          base_cost_type,
                          &det_routing_arch->wire_to_rr_ipin_switch,
                          det_routing_arch->read_rr_graph_filename.c_str());
+
+            /* Xifan Tang - Create rr_graph object: load rr_nodes to the object */
+            convert_rr_graph(segment_inf);
         }
     } else {
         if (channel_widths_unchanged(device_ctx.chan_width, nodes_per_chan) && !device_ctx.rr_nodes.empty()) {
@@ -369,6 +375,9 @@ void create_rr_graph(const t_graph_type graph_type,
                                                                   det_routing_arch->wire_to_rr_ipin_switch,
                                                                   base_cost_type);
         }
+
+        /* Xifan Tang - Create rr_graph object: load rr_nodes to the object */
+        convert_rr_graph(segment_inf);
     }
 
     process_non_config_sets();
@@ -378,6 +387,11 @@ void create_rr_graph(const t_graph_type graph_type,
     //Write out rr graph file if needed
     if (!det_routing_arch->write_rr_graph_filename.empty()) {
         write_rr_graph(det_routing_arch->write_rr_graph_filename.c_str(), segment_inf);
+
+        /* Just to test the writer of rr_graph_obj, give a filename in a fixed style*/
+        std::string rr_graph_obj_filename(det_routing_arch->write_rr_graph_filename);
+        rr_graph_obj_filename += std::string(".obj");
+        write_xml_rr_graph_obj(rr_graph_obj_filename.c_str(), device_ctx.rr_graph);
     }
 }
 
@@ -1391,6 +1405,9 @@ void free_rr_graph() {
     device_ctx.rr_edge_metadata.clear();
 
     invalidate_router_lookahead_cache();
+
+    /* Xifan Tang - Clear the rr_graph object */
+    device_ctx.rr_graph.clear();
 }
 
 static void build_rr_sinks_sources(const int i,
diff --git a/vpr/valgrind.supp b/vpr/valgrind.supp
new file mode 100644
index 000000000..6bd7272c4
--- /dev/null
+++ b/vpr/valgrind.supp
@@ -0,0 +1,711 @@
+#
+# Valgrind suppression file for EZGL
+#
+
+#pango
+{
+	libpango
+	Memcheck:Leak
+	...
+	obj:/usr/lib*/libpango*
+}
+
+#GTK
+{
+	g_type_register
+	Memcheck:Leak
+	fun:*alloc
+	...
+	fun:g_type_register_*
+	...
+	fun:_dl_init
+	...
+}
+
+{
+	g_quark_from_static_string
+	Memcheck:Leak
+	fun:*alloc
+	...
+	fun:g_quark_from_static_string
+	...
+	fun:_dl_init
+	...
+}
+
+{
+	g_main_thread
+	Memcheck:Leak
+	fun:*alloc
+	...
+	fun:g_main*
+	...
+	fun:start_thread
+	fun:clone
+}
+
+{
+	g_closure
+	Memcheck:Leak
+	match-leak-kinds:possible
+	fun:*alloc
+	...
+	fun:g_cclosure_new
+	fun:g_signal_connect_data
+	...
+}
+
+# 
+{
+	g_object
+	Memcheck:Leak
+	match-leak-kinds:possible
+	...
+	fun:g_object_new
+	...
+}
+
+{
+	g_type_register_static
+	Memcheck:Leak
+	match-leak-kinds:possible
+	...
+	fun:g_type_register_static
+	...
+}
+
+{
+	g_signal_connect_closure
+	Memcheck:Leak
+	match-leak-kinds:possible
+	...
+	fun:g_signal_connect_closure
+	fun:gtk_*group*
+	...
+}
+
+{
+	gtk_module_init
+	Memcheck:Leak
+	
+	fun:*alloc
+	...
+	fun:gtk_module_init
+	...
+}
+
+{
+	g_closure_invoke
+	Memcheck:Leak
+	
+	fun:*alloc
+	...
+	fun:g_closure_invoke
+	...
+}
+
+{
+	gtk_style_context_set_state
+	Memcheck:Leak
+	
+	fun:*alloc
+	...
+	fun:gtk_style_context_set_state
+	...
+}
+
+# 
+{
+	call_init
+	Memcheck:Leak
+	
+	fun:*alloc
+	...
+	fun:call_init
+	fun:_dl_init
+	...
+}
+
+{
+	XML_ParseBuffer
+	Memcheck:Leak
+	fun:*alloc
+	...
+	fun:XML_ParseBuffer
+	...
+}
+
+{
+	FcConfigParseAndLoad
+	Memcheck:Leak
+	fun:*alloc
+	...
+	fun:FcConfigParseAndLoad
+	...
+}
+
+# 
+{
+	g_objectv
+	Memcheck:Leak
+	
+	...
+	fun:g_object_newv
+	...
+}
+
+{
+	g_type_add_interface_static
+	Memcheck:Leak
+	match-leak-kinds:possible
+	...
+	fun:g_type_add_interface_static
+	...
+}
+
+{
+	gtk_container_get_children
+	Memcheck:Leak
+	fun:*alloc
+	...
+	fun:gtk_container_get_children
+	...
+}
+
+{
+	cairo_select_font_face
+	Memcheck:Leak
+	fun:*alloc
+	...
+	fun:cairo_select_font_face
+	...
+}
+
+{
+	libfontconfig
+	Memcheck:Leak
+	fun:*alloc
+	...
+	obj:*libfontconfig.so.*
+	...
+}
+
+{
+	X11_XGetDefault
+	Memcheck:Leak
+	fun:realloc
+	obj:*libX11.so.6.3.0
+	obj:*libX11.so.6.3.0
+	obj:*libX11.so.6.3.0
+	fun:_XlcCreateLC
+	fun:_XlcDefaultLoader
+	fun:_XOpenLC
+	fun:_XrmInitParseInfo
+	obj:*libX11.so.6.3.0
+	fun:XrmGetStringDatabase
+	obj:*libX11.so.6.3.0
+	fun:XGetDefault
+}
+
+{
+	XInternAtom_via_event_loop
+	Memcheck:Leak
+	fun:*alloc
+	fun:_XEnq
+	obj:*libX11.so.6.3.0
+	fun:_XReply
+	fun:XInternAtom
+	...
+}
+
+{
+	cairo_deep_*alloc
+	Memcheck:Leak
+	fun:*alloc
+	obj:*libcairo.*
+	...
+}
+
+#openmp
+{
+	GOMP_parallel
+	Memcheck:Leak
+	
+	fun:*alloc
+	fun:allocate_dtv
+	fun:_dl_allocate_tls
+	fun:allocate_stack
+	fun:pthread_create@@GLIBC_2.2.5
+	...
+}
+
+
+#GTK engines
+{
+	engines
+	Memcheck:Leak
+	fun:*alloc
+	...
+	obj:/usr/lib*/gtk*/*/engines*
+	...
+	obj:/usr/lib*/libgtk*
+}
+
+#nvidia
+{
+	libGL
+	Memcheck:Leak
+	...
+	obj:/usr/lib*/libGL.so*
+}
+{
+   <insert_a_suppression_name_here>
+   Memcheck:Leak
+   fun:*alloc
+   ...
+   fun:g_socket_create_source
+   ...
+   fun:g_main_context_dispatch
+}
+{
+   <insert_a_suppression_name_here>
+   Memcheck:Leak
+   fun:*alloc
+   ...
+   fun:g_type_class_ref
+   ...
+   fun:gtk_init_check
+   fun:gtk_init
+   obj:*libgtk-3*
+}
+{
+   <insert_a_suppression_name_here>
+   Memcheck:Leak
+   fun:*alloc
+   ...
+   fun:g_markup_parse_context_parse
+   obj:*libgtk-3*
+}
+{
+   <insert_a_suppression_name_here>
+   Memcheck:Leak
+   fun:*alloc
+   ...
+   fun:g_socket_new
+   obj:*libgio-2*
+   fun:g_socket_client_connect
+   obj:*libgio-2*
+}
+{
+   <insert_a_suppression_name_here>
+   Memcheck:Leak
+   fun:*alloc
+   ...
+   fun:atk_add_focus_tracker
+   obj:*libgtk-3*
+   ...
+   fun:gtk_parse_args
+   fun:gtk_init_check
+}
+{
+   <insert_a_suppression_name_here>
+   Memcheck:Leak
+   fun:m*alloc
+   ...
+   fun:g_bus_get_sync
+   ...
+   fun:g_application_register
+   obj:*libgio-2*
+   fun:g_application_run
+}
+{
+   <insert_a_suppression_name_here>
+   Memcheck:Leak
+   fun:*alloc
+   ...
+   obj:*libgtk-3*
+   fun:g_closure_invoke
+   ...
+   fun:g_signal_emit_valist
+   fun:g_signal_emit
+}
+{
+   <insert_a_suppression_name_here>
+   Memcheck:Leak
+   fun:*alloc
+   ...
+   fun:g_simple_async_result_complete
+   ...
+   fun:g_main_context_dispatch
+   ...
+}
+{
+   <insert_a_suppression_name_here>
+   Memcheck:Leak
+   fun:*alloc
+   ...
+   fun:g_type_class_ref
+   ...
+   fun:atk_add_focus_tracker
+   obj:*libgtk-3*
+   ...
+   fun:g_option_context_parse
+}
+{
+   <insert_a_suppression_name_here>
+   Memcheck:Leak
+   fun:*alloc
+   ...
+   fun:g_type_class_ref
+   obj:*libgtk-3*
+   fun:atk_add_focus_tracker
+   obj:*libgtk-3*
+}
+{
+   <insert_a_suppression_name_here>
+   Memcheck:Leak
+   fun:*alloc
+   ...
+   fun:g_type_class_ref
+   obj:*libgtk-3*
+}
+{
+   <insert_a_suppression_name_here>
+   Memcheck:Leak
+   fun:*alloc
+   ...
+   fun:g_dbus_proxy_new_sync
+   obj:*libgtk-3*
+}
+{
+   <insert_a_suppression_name_here>
+   Memcheck:Leak
+   fun:*alloc
+   ...
+   fun:g_signal_new
+   ...
+   obj:*libgobject-2*
+   fun:g_type_class_ref
+   fun:g_object_new_valist
+   fun:g_initable_new_valist
+   fun:g_initable_new
+}
+{
+   <insert_a_suppression_name_here>
+   Memcheck:Leak 
+   fun:*alloc
+   ...
+   fun:g_signal_new
+   obj:*libgtk-3*
+   fun:g_type_class_ref
+   obj:*libgtk-3*
+   ...
+}
+{
+   <insert_a_suppression_name_here>
+   Memcheck:Leak
+   fun:*alloc
+   ...
+   fun:g_signal_new
+   obj:*libgtk-3*
+   ...
+   fun:g_type_class_ref
+   obj:*libgtk-3*
+   ...
+}
+{
+   <insert_a_suppression_name_here>
+   Memcheck:Leak
+   
+   fun:*alloc
+   ...
+   fun:g_type_class_ref
+   obj:*libgtk-3*
+   fun:atk_add_focus_tracker
+   obj:*libgtk-3*
+   ...
+   fun:g_option_context_parse
+}
+{
+   <insert_a_suppression_name_here>
+   Memcheck:Leak
+   
+   fun:*alloc
+   ...
+   fun:g_signal_new_class_handler
+   obj:*libgtk-3*
+   ...
+   fun:g_type_class_ref
+   obj:*libgtk-3*
+   ...
+}
+{
+   <insert_a_suppression_name_here>
+   Memcheck:Leak  
+   fun:*alloc
+   ...
+   fun:g_signal_connect_data
+   obj:*libgtk-3*
+   ...
+   fun:gtk_widget_show
+   obj:*libgtk-3*
+   ...
+}
+{
+   <insert_a_suppression_name_here>
+   Memcheck:Leak
+   fun:*alloc
+   ...
+   fun:g_type_class_ref
+   fun:g_object_new_valist
+   fun:g_initable_new_valist
+   fun:g_initable_new
+   fun:gvfs_dbus_mount_tracker_proxy_new_for_bus_sync
+   ...
+   fun:g_type_create_instance
+}
+{
+   <insert_a_suppression_name_here>
+   Memcheck:Leak
+   fun:*alloc
+   fun:g_*alloc
+   ...
+   fun:g_type_class_ref
+   obj:*libgtk-3*
+   ...
+   fun:g_markup_parse_context_parse
+}
+{
+   <insert_a_suppression_name_here>
+   Memcheck:Leak
+   fun:*alloc
+   ...
+   fun:g_type_class_ref
+   obj:*libgtk-3*
+   ...
+   fun:g_option_context_parse
+   fun:gtk_parse_args
+   fun:gtk_init_check
+}
+{
+   <insert_a_suppression_name_here>
+   Memcheck:Leak
+   fun:*alloc
+   ...
+   fun:g_type_class_ref
+   fun:atk_bridge_adaptor_init
+   obj:*libgtk-3*
+   ...
+   fun:g_option_context_parse
+   fun:gtk_parse_args
+   fun:gtk_init_check
+   fun:gtk_init
+}
+{
+   <insert_a_suppression_name_here>
+   Memcheck:Leak
+   fun:*alloc
+   ...
+   fun:g_signal_new
+   ...
+   fun:g_type_class_ref
+   obj:*libgtk-3*
+   fun:atk_add_focus_tracker
+   obj:*libgtk-3*
+}
+{
+   <insert_a_suppression_name_here>
+   Memcheck:Leak
+   
+   fun:*alloc
+   ...
+   fun:g_signal_new
+   ...
+   fun:g_type_class_ref
+   obj:*libgtk-3*
+}
+{
+   <insert_a_suppression_name_here>
+   Memcheck:Leak  
+   fun:*alloc
+   ...
+   fun:g_signal_new
+   ...
+   fun:g_initable_new
+}
+{
+   <insert_a_suppression_name_here>
+   Memcheck:Leak
+   fun:*alloc
+   ...
+   fun:g_signal_new
+   obj:*libgtk-3*
+   fun:g_type_class_ref
+   obj:*libgtk-3*
+   ...
+}
+{
+   <insert_a_suppression_name_here>
+   Memcheck:Leak
+   fun:*alloc
+   ...
+   fun:g_signal_new
+   ...
+   fun:g_type_class_ref
+   obj:*libgtk-3*
+   ...
+}
+{
+   <insert_a_suppression_name_here>
+   Memcheck:Leak 
+   fun:*alloc
+   ...
+   fun:g_signal_new
+   ...
+   fun:g_type_class_ref
+   obj:*libgtk-3*
+   ...
+}
+{
+   <insert_a_suppression_name_here>
+   Memcheck:Leak
+   fun:*alloc
+   ...
+   fun:g_signal_new
+   ...
+   fun:g_type_class_ref
+   obj:*libgtk-3*
+   ...
+}
+{
+   <insert_a_suppression_name_here>
+   Memcheck:Leak 
+   fun:*alloc
+   ...
+   fun:g_signal_new
+   ...
+   fun:g_type_class_ref
+   obj:*libgio-2.0.so.0.4002.0
+   ...
+}
+{
+   <insert_a_suppression_name_here>
+   Memcheck:Leak
+   fun:*alloc
+   ...
+   fun:g_signal_new_class_handler
+   ...
+   fun:g_type_class_ref
+   obj:*libgtk-3*
+   ...
+}
+{
+   <insert_a_suppression_name_here>
+   Memcheck:Leak
+   fun:*alloc
+   ...
+   fun:g_signal_connect_data
+   ...
+   fun:gtk_widget_show
+   obj:*libgtk-3*
+   ...
+}
+{
+   <insert_a_suppression_name_here>
+   Memcheck:Leak
+   fun:*alloc
+   ...
+   fun:g_initable_new
+   ...
+   fun:g_type_create_instance
+}
+{
+   <insert_a_suppression_name_here>
+   Memcheck:Leak
+   fun:*alloc
+   ...
+   fun:g_type_class_ref
+   obj:*libgtk-3*
+   ...
+   fun:g_markup_parse_context_parse
+}
+{
+   <insert_a_suppression_name_here>
+   Memcheck:Leak
+   fun:malloc
+   ...
+   fun:g_type_class_ref
+   obj:*libgtk-3*
+   ...
+   fun:gtk_init_check
+}
+{
+   <insert_a_suppression_name_here>
+   Memcheck:Leak
+   fun:malloc
+   ...
+   fun:atk_bridge_adaptor_init
+   obj:*libgtk-3*
+   ...
+   fun:gtk_init
+}
+{
+   <insert_a_suppression_name_here>
+   Memcheck:Leak
+   fun:*alloc
+   ...
+   fun:g_application_register
+   obj:*libgio-2*
+}
+{
+   <insert_a_suppression_name_here>
+   Memcheck:Leak
+   fun:*alloc
+   ...
+   fun:g_thread_new
+   obj:*libgio-2*
+}
+{
+   <insert_a_suppression_name_here>
+   Memcheck:Leak
+   fun:*alloc
+   ...
+   fun:g_thread_pool_push
+   ...
+   fun:g_bus_get
+   fun:g_bus_watch_name
+}
+{
+   <insert_a_suppression_name_here>
+   Memcheck:Leak
+   match-leak-kinds: possible
+   fun:*alloc
+   ...
+   fun:g_param_spec_enum
+   ...
+   fun:g_bus_get_sync
+   obj:*libgio-*
+   fun:g_application_register
+}
+{
+   <insert_a_suppression_name_here>
+   Memcheck:Leak
+   match-leak-kinds: possible
+   fun:*alloc
+   fun:g_realloc
+   ...
+   fun:gtk_button_set_image_position
+   fun:g_object_setv
+   ...
+   obj:*libgtk-3*
+}
+{
+   <insert_a_suppression_name_here>
+   Memcheck:Leak
+   match-leak-kinds: possible
+   fun:*alloc
+   ...
+   fun:gtk_cell_renderer_render
+   ...
+   obj:*libgtk-3*
+}
\ No newline at end of file

From 5e2559dc1411041ac603d53f50da031f32831c7d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 31 Jan 2020 17:27:18 -0700
Subject: [PATCH 063/645] now RRGraph is proven to be correct as rr_node in
 terms of XML output

---
 vpr/src/device/rr_graph_obj.cpp           | 22 +++++++++++++---------
 vpr/src/device/write_xml_rr_graph_obj.cpp |  2 ++
 2 files changed, 15 insertions(+), 9 deletions(-)

diff --git a/vpr/src/device/rr_graph_obj.cpp b/vpr/src/device/rr_graph_obj.cpp
index 2df4a77bf..316bc6e87 100644
--- a/vpr/src/device/rr_graph_obj.cpp
+++ b/vpr/src/device/rr_graph_obj.cpp
@@ -1120,19 +1120,23 @@ void RRGraph::rebuild_node_edges() {
         auto is_incoming_edge = [&](const RREdgeId edge) {
             return edge_sink_node(edge) == node;
         };
-        std::partition(node_edges_[node].get(),
-                       node_edges_[node].get() + node_num_in_edges_[node] + node_num_out_edges_[node],
-                       is_incoming_edge);
+        /* Use stable_partition to keep the relative order,
+         * This is mainly for comparing the RRGraph write with rr_node writer 
+         * so that it is easy to check consistency
+         */
+        std::stable_partition(node_edges_[node].get(),
+                              node_edges_[node].get() + node_num_in_edges_[node] + node_num_out_edges_[node],
+                              is_incoming_edge);
 
         //Partition incoming by configurable/non-configurable
-        std::partition(node_edges_[node].get(),
-                       node_edges_[node].get() + node_num_in_edges_[node],
-                       is_configurable_edge);
+        std::stable_partition(node_edges_[node].get(),
+                              node_edges_[node].get() + node_num_in_edges_[node],
+                              is_configurable_edge);
 
         //Partition outgoing by configurable/non-configurable
-        std::partition(node_edges_[node].get() + node_num_in_edges_[node],
-                       node_edges_[node].get() + node_num_in_edges_[node] + node_num_out_edges_[node],
-                       is_configurable_edge);
+        std::stable_partition(node_edges_[node].get() + node_num_in_edges_[node],
+                              node_edges_[node].get() + node_num_in_edges_[node] + node_num_out_edges_[node],
+                              is_configurable_edge);
 
 #if 0
         //TODO: Sanity check remove!
diff --git a/vpr/src/device/write_xml_rr_graph_obj.cpp b/vpr/src/device/write_xml_rr_graph_obj.cpp
index 10cdb273e..a329b7bc0 100644
--- a/vpr/src/device/write_xml_rr_graph_obj.cpp
+++ b/vpr/src/device/write_xml_rr_graph_obj.cpp
@@ -172,6 +172,8 @@ void write_rr_graph_edges(fstream &fp, const RRGraph& rr_graph) {
   fp << "\t<rr_edges>" << endl;
 
   for (auto node : rr_graph.nodes()) {
+    /* Sort the edges by the ids of sink nodes */
+    std::vector<RREdgeId> sorted_out_edge_ids;
     for (auto edge: rr_graph.node_out_edges(node)) {
       fp << "\t\t<edge src_node=\"" << rr_graph.node_index(node) <<
             "\" sink_node=\"" << rr_graph.node_index(rr_graph.edge_sink_node(edge)) <<

From 35c136d8a4a8a68c8114384a97957e65e3001c6e Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 31 Jan 2020 19:55:32 -0700
Subject: [PATCH 064/645] start deploy RRGraph in the placement engine

---
 vpr/src/base/vpr_types.h              | 10 ++++++++-
 vpr/src/draw/draw.cpp                 |  6 ++---
 vpr/src/place/timing_place_lookup.cpp | 32 +++++++++++++--------------
 vpr/src/place/timing_place_lookup.h   |  3 ++-
 vpr/src/route/route_common.cpp        | 19 ++++++++--------
 vpr/src/route/route_tree_timing.cpp   |  6 ++---
 vpr/src/route/route_tree_type.h       | 13 +++++++++++
 7 files changed, 56 insertions(+), 33 deletions(-)

diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h
index cb38f75ee..617888225 100644
--- a/vpr/src/base/vpr_types.h
+++ b/vpr/src/base/vpr_types.h
@@ -40,8 +40,9 @@
 #include "vtr_flat_map.h"
 #include "vtr_cache.h"
 
-/* Header for rr_graph related definition */
+/* Xifan Tang - Header for rr_graph related definition */
 #include "rr_graph_types.h"
+#include "rr_graph_obj.h"
 
 /*******************************************************************************
  * Global data types and constants
@@ -1137,6 +1138,10 @@ struct t_trace {
     t_trace* next;
     int index;
     short iswitch;
+
+    /* Xifan Tang - RRGraph unique ids */
+    RRNodeId node_id;
+    RRSwitchId switch_id; 
 };
 
 /* Extra information about each rr_node needed only during routing (i.e.    *
@@ -1160,6 +1165,9 @@ struct t_trace {
  * occ:        The current occupancy of the associated rr node              */
 struct t_rr_node_route_inf {
     int prev_node;
+    /* Xifan Tang - prev_node for RRGraph object */
+    RRNodeId prev_node_id;
+
     t_edge_size prev_edge;
 
     float pres_cost;
diff --git a/vpr/src/draw/draw.cpp b/vpr/src/draw/draw.cpp
index 505928cf6..8ba6ca124 100644
--- a/vpr/src/draw/draw.cpp
+++ b/vpr/src/draw/draw.cpp
@@ -880,10 +880,10 @@ void init_draw_coords(float width_val) {
         return; //do not initialize only if --disp off and --save_graphics off
     /* Each time routing is on screen, need to reallocate the color of each *
      * rr_node, as the number of rr_nodes may change.						*/
-    if (device_ctx.rr_nodes.size() != 0) {
+    if (device_ctx.rr_graph.nodes().size() != 0) {
         draw_state->draw_rr_node = (t_draw_rr_node*)vtr::realloc(draw_state->draw_rr_node,
-                                                                 (device_ctx.rr_nodes.size()) * sizeof(t_draw_rr_node));
-        for (size_t i = 0; i < device_ctx.rr_nodes.size(); i++) {
+                                                                 (device_ctx.rr_graph.nodes().size()) * sizeof(t_draw_rr_node));
+        for (size_t i = 0; i < device_ctx.rr_graph.nodes().size(); i++) {
             draw_state->draw_rr_node[i].color = DEFAULT_RR_NODE_COLOR;
             draw_state->draw_rr_node[i].node_highlighted = false;
         }
diff --git a/vpr/src/place/timing_place_lookup.cpp b/vpr/src/place/timing_place_lookup.cpp
index 4aa439aab..4dc907b4c 100644
--- a/vpr/src/place/timing_place_lookup.cpp
+++ b/vpr/src/place/timing_place_lookup.cpp
@@ -304,16 +304,16 @@ static float route_connection_delay(
     for (int driver_ptc : best_driver_ptcs) {
         VTR_ASSERT(driver_ptc != OPEN);
 
-        int source_rr_node = get_rr_node_index(device_ctx.rr_node_indices, source_x, source_y, SOURCE, driver_ptc);
+        RRNodeId source_rr_node = device_ctx.rr_graph.find_node(source_x, source_y, SOURCE, driver_ptc);
 
-        VTR_ASSERT(source_rr_node != OPEN);
+        VTR_ASSERT(source_rr_node != RRNodeId::INVALID());
 
         for (int sink_ptc : best_sink_ptcs) {
             VTR_ASSERT(sink_ptc != OPEN);
 
-            int sink_rr_node = get_rr_node_index(device_ctx.rr_node_indices, sink_x, sink_y, SINK, sink_ptc);
+            RRNodeId sink_rr_node = device_ctx.rr_graph.find_node(sink_x, sink_y, SINK, sink_ptc);
 
-            VTR_ASSERT(sink_rr_node != OPEN);
+            VTR_ASSERT(sink_rr_node != RRNodeId::INVALID());
 
             if (!measure_directconnect && directconnect_exists(source_rr_node, sink_rr_node)) {
                 //Skip if we shouldn't measure direct connects and a direct connect exists
@@ -322,7 +322,7 @@ static float route_connection_delay(
 
             {
                 successfully_routed = route_profiler.calculate_delay(
-                    source_rr_node, sink_rr_node,
+                    size_t(source_rr_node), size_t(sink_rr_node),
                     router_opts,
                     &net_delay_value);
             }
@@ -933,29 +933,29 @@ void OverrideDelayModel::compute_override_delay_model(
     }
 }
 
-bool directconnect_exists(int src_rr_node, int sink_rr_node) {
+bool directconnect_exists(RRNodeId src_rr_node, RRNodeId sink_rr_node) {
     //Returns true if there is a directconnect between the two RR nodes
     //
     //This is checked by looking for a SOURCE -> OPIN -> IPIN -> SINK path
     //which starts at src_rr_node and ends at sink_rr_node
     auto& device_ctx = g_vpr_ctx.device();
-    auto& rr_nodes = device_ctx.rr_nodes;
+    auto& rr_graph = device_ctx.rr_graph;
 
-    VTR_ASSERT(rr_nodes[src_rr_node].type() == SOURCE && rr_nodes[sink_rr_node].type() == SINK);
+    VTR_ASSERT(rr_graph.node_type(src_rr_node) == SOURCE && rr_graph.node_type(sink_rr_node) == SINK);
 
     //TODO: This is a constant depth search, but still may be too slow
-    for (t_edge_size i_src_edge = 0; i_src_edge < rr_nodes[src_rr_node].num_edges(); ++i_src_edge) {
-        int opin_rr_node = rr_nodes[src_rr_node].edge_sink_node(i_src_edge);
+    for (const RREdgeId& src_edge : rr_graph.node_out_edges(src_rr_node)) {
+        RRNodeId opin_rr_node = rr_graph.edge_sink_node(src_edge);
 
-        if (rr_nodes[opin_rr_node].type() != OPIN) continue;
+        if (rr_graph.node_type(opin_rr_node) != OPIN) continue;
 
-        for (t_edge_size i_opin_edge = 0; i_opin_edge < rr_nodes[opin_rr_node].num_edges(); ++i_opin_edge) {
-            int ipin_rr_node = rr_nodes[opin_rr_node].edge_sink_node(i_opin_edge);
+        for (const RREdgeId& opin_edge : rr_graph.node_out_edges(opin_rr_node)) {
+            RRNodeId ipin_rr_node = rr_graph.edge_sink_node(opin_edge);
 
-            if (rr_nodes[ipin_rr_node].type() != IPIN) continue;
+            if (rr_graph.node_type(ipin_rr_node) != IPIN) continue;
 
-            for (t_edge_size i_ipin_edge = 0; i_ipin_edge < rr_nodes[ipin_rr_node].num_edges(); ++i_ipin_edge) {
-                if (sink_rr_node == rr_nodes[ipin_rr_node].edge_sink_node(i_ipin_edge)) {
+            for (const RREdgeId& ipin_edge : rr_graph.node_out_edges(ipin_rr_node)) {
+                if (sink_rr_node == rr_graph.edge_sink_node(ipin_edge)) {
                     return true;
                 }
             }
diff --git a/vpr/src/place/timing_place_lookup.h b/vpr/src/place/timing_place_lookup.h
index 74a20e939..e96bccdab 100644
--- a/vpr/src/place/timing_place_lookup.h
+++ b/vpr/src/place/timing_place_lookup.h
@@ -1,6 +1,7 @@
 #ifndef TIMING_PLACE_LOOKUP_H
 #define TIMING_PLACE_LOOKUP_H
 #include "place_delay_model.h"
+#include "rr_graph_obj.h"
 
 std::unique_ptr<PlaceDelayModel> compute_place_delay_model(const t_placer_opts& placer_opts,
                                                            const t_router_opts& router_opts,
@@ -11,6 +12,6 @@ std::unique_ptr<PlaceDelayModel> compute_place_delay_model(const t_placer_opts&
                                                            const int num_directs);
 
 std::vector<int> get_best_classes(enum e_pin_type pintype, t_physical_tile_type_ptr type);
-bool directconnect_exists(int src_rr_node, int sink_rr_node);
+bool directconnect_exists(RRNodeId src_rr_node, RRNodeId sink_rr_node);
 
 #endif
diff --git a/vpr/src/route/route_common.cpp b/vpr/src/route/route_common.cpp
index 6204dad98..b9a47d2d7 100644
--- a/vpr/src/route/route_common.cpp
+++ b/vpr/src/route/route_common.cpp
@@ -336,7 +336,7 @@ bool feasible_routing() {
     auto& device_ctx = g_vpr_ctx.device();
     auto& route_ctx = g_vpr_ctx.routing();
 
-    for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); inode++) {
+    for (size_t inode = 0; inode < device_ctx.rr_graph.nodes().size(); inode++) {
         if (route_ctx.rr_node_route_inf[inode].occ() > device_ctx.rr_nodes[inode].capacity()) {
             return (false);
         }
@@ -351,7 +351,7 @@ std::vector<int> collect_congested_rr_nodes() {
     auto& route_ctx = g_vpr_ctx.routing();
 
     std::vector<int> congested_rr_nodes;
-    for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); inode++) {
+    for (size_t inode = 0; inode < device_ctx.rr_graph.nodes().size(); inode++) {
         short occ = route_ctx.rr_node_route_inf[inode].occ();
         short capacity = device_ctx.rr_nodes[inode].capacity();
 
@@ -362,14 +362,14 @@ std::vector<int> collect_congested_rr_nodes() {
     return congested_rr_nodes;
 }
 
-/* Returns a vector from [0..device_ctx.rr_nodes.size()-1] containing the set
+/* Returns a vector from [0..device_ctx.rr_graph.nodes().size()-1] containing the set
  * of nets using each RR node */
 std::vector<std::set<ClusterNetId>> collect_rr_node_nets() {
     auto& device_ctx = g_vpr_ctx.device();
     auto& route_ctx = g_vpr_ctx.routing();
     auto& cluster_ctx = g_vpr_ctx.clustering();
 
-    std::vector<std::set<ClusterNetId>> rr_node_nets(device_ctx.rr_nodes.size());
+    std::vector<std::set<ClusterNetId>> rr_node_nets(device_ctx.rr_graph.nodes().size());
     for (ClusterNetId inet : cluster_ctx.clb_nlist.nets()) {
         t_trace* trace_elem = route_ctx.trace[inet].head;
         while (trace_elem) {
@@ -449,7 +449,7 @@ void pathfinder_update_cost(float pres_fac, float acc_fac) {
     auto& device_ctx = g_vpr_ctx.device();
     auto& route_ctx = g_vpr_ctx.mutable_routing();
 
-    for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); inode++) {
+    for (size_t inode = 0; inode < device_ctx.rr_graph.nodes().size(); inode++) {
         occ = route_ctx.rr_node_route_inf[inode].occ();
         capacity = device_ctx.rr_nodes[inode].capacity();
 
@@ -1003,7 +1003,7 @@ void alloc_and_load_rr_node_route_structs() {
     auto& route_ctx = g_vpr_ctx.mutable_routing();
     auto& device_ctx = g_vpr_ctx.device();
 
-    route_ctx.rr_node_route_inf.resize(device_ctx.rr_nodes.size());
+    route_ctx.rr_node_route_inf.resize(device_ctx.rr_graph.nodes().size());
     reset_rr_node_route_structs();
 }
 
@@ -1014,10 +1014,11 @@ void reset_rr_node_route_structs() {
     auto& route_ctx = g_vpr_ctx.mutable_routing();
     auto& device_ctx = g_vpr_ctx.device();
 
-    VTR_ASSERT(route_ctx.rr_node_route_inf.size() == size_t(device_ctx.rr_nodes.size()));
+    VTR_ASSERT(route_ctx.rr_node_route_inf.size() == size_t(device_ctx.rr_graph.nodes().size()));
 
-    for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); inode++) {
+    for (size_t inode = 0; inode < device_ctx.rr_graph.nodes().size(); inode++) {
         route_ctx.rr_node_route_inf[inode].prev_node = NO_PREVIOUS;
+        route_ctx.rr_node_route_inf[inode].prev_node_id = RRNodeId::INVALID();
         route_ctx.rr_node_route_inf[inode].prev_edge = NO_PREVIOUS;
         route_ctx.rr_node_route_inf[inode].pres_cost = 1.0;
         route_ctx.rr_node_route_inf[inode].acc_cost = 1.0;
@@ -1826,7 +1827,7 @@ void print_invalid_routing_info() {
         }
     }
 
-    for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); inode++) {
+    for (size_t inode = 0; inode < device_ctx.rr_graph.nodes().size(); inode++) {
         int occ = route_ctx.rr_node_route_inf[inode].occ();
         int cap = device_ctx.rr_nodes[inode].capacity();
         if (occ > cap) {
diff --git a/vpr/src/route/route_tree_timing.cpp b/vpr/src/route/route_tree_timing.cpp
index 7988d02dc..faf33c7dd 100644
--- a/vpr/src/route/route_tree_timing.cpp
+++ b/vpr/src/route/route_tree_timing.cpp
@@ -27,7 +27,7 @@
 /* Array below allows mapping from any rr_node to any rt_node currently in
  * the rt_tree.                                                              */
 
-static std::vector<t_rt_node*> rr_node_to_rt_node; /* [0..device_ctx.rr_nodes.size()-1] */
+static std::vector<t_rt_node*> rr_node_to_rt_node; /* [0..device_ctx.rr_graph.nodes().size()-1] */
 
 /* Frees lists for fast addition and deletion of nodes and edges. */
 
@@ -73,7 +73,7 @@ bool alloc_route_tree_timing_structs(bool exists_ok) {
 
     auto& device_ctx = g_vpr_ctx.device();
 
-    bool route_tree_structs_are_allocated = (rr_node_to_rt_node.size() == size_t(device_ctx.rr_nodes.size())
+    bool route_tree_structs_are_allocated = (rr_node_to_rt_node.size() == size_t(device_ctx.rr_graph.nodes().size())
                                              || rt_node_free_list != nullptr);
     if (route_tree_structs_are_allocated) {
         if (exists_ok) {
@@ -84,7 +84,7 @@ bool alloc_route_tree_timing_structs(bool exists_ok) {
         }
     }
 
-    rr_node_to_rt_node = std::vector<t_rt_node*>(device_ctx.rr_nodes.size(), nullptr);
+    rr_node_to_rt_node = std::vector<t_rt_node*>(device_ctx.rr_graph.nodes().size(), nullptr);
 
     return true;
 }
diff --git a/vpr/src/route/route_tree_type.h b/vpr/src/route/route_tree_type.h
index 7d663aafb..5e81bd1e4 100644
--- a/vpr/src/route/route_tree_type.h
+++ b/vpr/src/route/route_tree_type.h
@@ -1,4 +1,5 @@
 #pragma once
+#include "rr_graph_obj.h"
 
 /************** Types and defines exported by route_tree_timing.c ************/
 struct t_rt_node;
@@ -11,6 +12,10 @@ struct t_rt_node;
 struct t_linked_rt_edge {
     t_rt_node* child;
     short iswitch;
+
+    /* Xifan Tang - RRGraph switch*/
+    RRSwitchId iswitch_id;
+
     t_linked_rt_edge* next;
 };
 
@@ -41,8 +46,16 @@ struct t_rt_node {
     } u;
     t_rt_node* parent_node;
     short parent_switch;
+   
+    /* Xifan Tang - RRGraph switch*/
+    RRSwitchId parent_switch_id;
+
     bool re_expand;
     int inode;
+
+    /* Xifan Tang - RRGraph node */
+    RRNodeId inode_id;
+
     float C_downstream;
     float R_upstream;
     float Tdel;

From 9d9a2c1402454b1af63bbe9b061d01d7a749ddab Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 31 Jan 2020 21:14:20 -0700
Subject: [PATCH 065/645] deploying RRGraph to placer

---
 vpr/src/base/vpr_context.h                  |   4 +-
 vpr/src/base/vpr_types.h                    |   6 +-
 vpr/src/place/timing_place_lookup.cpp       |   2 +-
 vpr/src/route/route_common.cpp              |  20 +--
 vpr/src/route/route_common.h                |  11 +-
 vpr/src/route/route_timing.cpp              | 167 ++++++++++----------
 vpr/src/route/route_timing.h                |   6 +-
 vpr/src/route/route_tree_timing.cpp         |  19 ++-
 vpr/src/route/route_tree_timing.h           |   3 +-
 vpr/src/route/route_tree_type.h             |   4 +-
 vpr/src/route/router_delay_profiling.cpp    |   7 +-
 vpr/src/route/router_delay_profiling.h      |   2 +-
 vpr/src/route/router_lookahead.cpp          |  40 ++---
 vpr/src/route/router_lookahead.h            |  10 +-
 vpr/src/route/spatial_route_tree_lookup.cpp |  10 +-
 vpr/src/util/vpr_utils.cpp                  |  22 +--
 vpr/src/util/vpr_utils.h                    |   2 +-
 17 files changed, 167 insertions(+), 168 deletions(-)

diff --git a/vpr/src/base/vpr_context.h b/vpr/src/base/vpr_context.h
index 2a99e9351..7f4ba43dc 100644
--- a/vpr/src/base/vpr_context.h
+++ b/vpr/src/base/vpr_context.h
@@ -160,7 +160,7 @@ struct DeviceContext : public Context {
     std::vector<std::vector<int>> rr_non_config_node_sets;
 
     //Reverse look-up from RR node to non-configurably connected node set (index into rr_nonconf_node_sets)
-    std::unordered_map<int, int> rr_node_to_non_config_node_set;
+    std::unordered_map<RRNodeId, RRNodeId> rr_node_to_non_config_node_set;
 
     //The indicies of rr nodes of a given type at a specific x,y grid location
     t_rr_node_indices rr_node_indices; //[0..NUM_RR_TYPES-1][0..grid.width()-1][0..grid.width()-1][0..size-1]
@@ -290,7 +290,7 @@ struct RoutingContext : public Context {
 
     vtr::vector<ClusterBlockId, std::vector<int>> rr_blk_source; /* [0..num_blocks-1][0..num_class-1] */
 
-    std::vector<t_rr_node_route_inf> rr_node_route_inf; /* [0..device_ctx.num_rr_nodes-1] */
+    vtr::vector<RRNodeId, t_rr_node_route_inf> rr_node_route_inf; /* [0..device_ctx.num_rr_nodes-1] */
 
     //Information about current routing status of each net
     vtr::vector<ClusterNetId, t_net_routing_status> net_status; //[0..cluster_ctx.clb_nlist.nets().size()-1]
diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h
index 617888225..bf080539f 100644
--- a/vpr/src/base/vpr_types.h
+++ b/vpr/src/base/vpr_types.h
@@ -1164,11 +1164,9 @@ struct t_trace {
  *               Number of times this node must be reached to fully route.  *
  * occ:        The current occupancy of the associated rr node              */
 struct t_rr_node_route_inf {
-    int prev_node;
     /* Xifan Tang - prev_node for RRGraph object */
-    RRNodeId prev_node_id;
-
-    t_edge_size prev_edge;
+    RRNodeId prev_node;
+    RREdgeId prev_edge;
 
     float pres_cost;
     float acc_cost;
diff --git a/vpr/src/place/timing_place_lookup.cpp b/vpr/src/place/timing_place_lookup.cpp
index 4dc907b4c..d3cdad215 100644
--- a/vpr/src/place/timing_place_lookup.cpp
+++ b/vpr/src/place/timing_place_lookup.cpp
@@ -322,7 +322,7 @@ static float route_connection_delay(
 
             {
                 successfully_routed = route_profiler.calculate_delay(
-                    size_t(source_rr_node), size_t(sink_rr_node),
+                    source_rr_node, sink_rr_node,
                     router_opts,
                     &net_delay_value);
             }
diff --git a/vpr/src/route/route_common.cpp b/vpr/src/route/route_common.cpp
index b9a47d2d7..40eada542 100644
--- a/vpr/src/route/route_common.cpp
+++ b/vpr/src/route/route_common.cpp
@@ -706,26 +706,26 @@ static std::pair<t_trace*, t_trace*> add_trace_non_configurable_recurr(int node,
 
 /* The routine sets the path_cost to HUGE_POSITIVE_FLOAT for  *
  * all channel segments touched by previous routing phases.    */
-void reset_path_costs(const std::vector<int>& visited_rr_nodes) {
+void reset_path_costs(const std::vector<RRNodeId>& visited_rr_nodes) {
     auto& route_ctx = g_vpr_ctx.mutable_routing();
 
     for (auto node : visited_rr_nodes) {
         route_ctx.rr_node_route_inf[node].path_cost = std::numeric_limits<float>::infinity();
         route_ctx.rr_node_route_inf[node].backward_path_cost = std::numeric_limits<float>::infinity();
-        route_ctx.rr_node_route_inf[node].prev_node = NO_PREVIOUS;
-        route_ctx.rr_node_route_inf[node].prev_edge = NO_PREVIOUS;
+        route_ctx.rr_node_route_inf[node].prev_node = RRNodeId::INVALID();
+        route_ctx.rr_node_route_inf[node].prev_edge = RREdgeId::INVALID();
     }
 }
 
 /* Returns the *congestion* cost of using this rr_node. */
-float get_rr_cong_cost(int inode) {
+float get_rr_cong_cost(const RRNodeId& inode) {
     auto& device_ctx = g_vpr_ctx.device();
 
     float cost = get_single_rr_cong_cost(inode);
 
     auto itr = device_ctx.rr_node_to_non_config_node_set.find(inode);
     if (itr != device_ctx.rr_node_to_non_config_node_set.end()) {
-        for (int node : device_ctx.rr_non_config_node_sets[itr->second]) {
+        for (const RRNodeId& node : device_ctx.rr_non_config_node_sets[itr->second]) {
             if (node == inode) {
                 continue; //Already included above
             }
@@ -738,11 +738,11 @@ float get_rr_cong_cost(int inode) {
 
 /* Returns the congestion cost of using this rr_node, *ignoring*
  * non-configurable edges */
-static float get_single_rr_cong_cost(int inode) {
+static float get_single_rr_cong_cost(const RRNodeId& inode) {
     auto& device_ctx = g_vpr_ctx.device();
     auto& route_ctx = g_vpr_ctx.routing();
 
-    auto cost_index = device_ctx.rr_nodes[inode].cost_index();
+    auto cost_index = device_ctx.rr_graph.node_cost_index(inode);
     float cost = device_ctx.rr_indexed_data[cost_index].base_cost
                  * route_ctx.rr_node_route_inf[inode].acc_cost
                  * route_ctx.rr_node_route_inf[inode].pres_cost;
@@ -1265,17 +1265,17 @@ void push_back(t_heap* const hptr) {
     ++heap_tail;
 }
 
-void push_back_node(int inode, float total_cost, int prev_node, int prev_edge, float backward_path_cost, float R_upstream) {
+void push_back_node(const RRNodeId& inode, float total_cost, const RRNodeId& prev_node, const RREdgeId& prev_edge, float backward_path_cost, float R_upstream) {
     /* Puts an rr_node on the heap with the same condition as node_to_heap,
      * but do not fix heap property yet as that is more efficiently done from
      * bottom up with build_heap    */
 
     auto& route_ctx = g_vpr_ctx.routing();
-    if (total_cost >= route_ctx.rr_node_route_inf[inode].path_cost)
+    if (total_cost >= route_ctx.rr_node_route_inf[size_t(inode)].path_cost)
         return;
 
     t_heap* hptr = alloc_heap_data();
-    hptr->index = inode;
+    hptr->index = size_t(inode);
     hptr->cost = total_cost;
     hptr->u.prev.node = prev_node;
     hptr->u.prev.edge = prev_edge;
diff --git a/vpr/src/route/route_common.h b/vpr/src/route/route_common.h
index 147ff9ddc..cfcfb30ce 100644
--- a/vpr/src/route/route_common.h
+++ b/vpr/src/route/route_common.h
@@ -3,6 +3,7 @@
 #include <vector>
 #include "clustered_netlist.h"
 #include "vtr_vector.h"
+#include "rr_graph_obj.h"
 
 /* Used by the heap as its fundamental data structure.
  * Each heap element represents a partial route.
@@ -37,11 +38,11 @@ struct t_heap {
     float backward_path_cost = 0.;
     float R_upstream = 0.;
 
-    int index = OPEN;
+    RRNodeId index = RRNodeId::INVALID();
 
     struct t_prev {
-        int node;
-        int edge;
+        RRNodeId& node;
+        RREdgeId& edge;
     };
 
     union {
@@ -67,7 +68,7 @@ t_trace* update_traceback(t_heap* hptr, ClusterNetId net_id);
 
 void reset_path_costs(const std::vector<int>& visited_rr_nodes);
 
-float get_rr_cong_cost(int inode);
+float get_rr_cong_cost(const RRNodeId& inode);
 
 void mark_ends(ClusterNetId net_id);
 void mark_remaining_ends(const std::vector<int>& remaining_sinks);
@@ -89,7 +90,7 @@ void build_heap();
 void sift_down(size_t hole);
 void sift_up(size_t tail, t_heap* const hptr);
 void push_back(t_heap* const hptr);
-void push_back_node(int inode, float total_cost, int prev_node, int prev_edge, float backward_path_cost, float R_upstream);
+void push_back_node(const RRNodeId& inode, float total_cost, const RRNodeId& prev_node, const RREdgeId& prev_edge, float backward_path_cost, float R_upstream);
 bool is_valid();
 void pop_heap();
 void print_heap();
diff --git a/vpr/src/route/route_timing.cpp b/vpr/src/route/route_timing.cpp
index cc738162b..47d1a3b2c 100644
--- a/vpr/src/route/route_timing.cpp
+++ b/vpr/src/route/route_timing.cpp
@@ -166,11 +166,11 @@ static t_heap* timing_driven_route_connection_from_route_tree_high_fanout(t_rt_n
                                                                           std::vector<int>& modified_rr_node_inf,
                                                                           RouterStats& router_stats);
 
-static t_heap* timing_driven_route_connection_from_heap(int sink_node,
+static t_heap* timing_driven_route_connection_from_heap(const RRNodeId& sink_node,
                                                         const t_conn_cost_params cost_params,
                                                         t_bb bounding_box,
                                                         const RouterLookahead& router_lookahead,
-                                                        std::vector<int>& modified_rr_node_inf,
+                                                        std::vector<RRNodeId>& modified_rr_node_inf,
                                                         RouterStats& router_stats);
 
 static std::vector<t_heap> timing_driven_find_all_shortest_paths_from_heap(const t_conn_cost_params cost_params,
@@ -180,17 +180,17 @@ static std::vector<t_heap> timing_driven_find_all_shortest_paths_from_heap(const
 
 void disable_expansion_and_remove_sink_from_route_tree_nodes(t_rt_node* node);
 static void timing_driven_expand_cheapest(t_heap* cheapest,
-                                          int target_node,
+                                          const RRNodeId& target_node,
                                           const t_conn_cost_params cost_params,
                                           t_bb bounding_box,
                                           const RouterLookahead& router_lookahead,
-                                          std::vector<int>& modified_rr_node_inf,
+                                          std::vector<RRNodeId>& modified_rr_node_inf,
                                           RouterStats& router_stats);
 
 static t_rt_node* setup_routing_resources(int itry, ClusterNetId net_id, unsigned num_sinks, float pres_fac, int min_incremental_reroute_fanout, CBRR& incremental_rerouting_res, t_rt_node** rt_node_of_sink);
 
 static void add_route_tree_to_heap(t_rt_node* rt_node,
-                                   int target_node,
+                                   const RRNodeId& target_node,
                                    const t_conn_cost_params cost_params,
                                    const RouterLookahead& router_lookahead,
                                    RouterStats& router_stats);
@@ -206,7 +206,7 @@ static t_bb add_high_fanout_route_tree_to_heap(t_rt_node* rt_root,
 static t_bb adjust_highfanout_bounding_box(t_bb highfanout_bb);
 
 static void add_route_tree_node_to_heap(t_rt_node* rt_node,
-                                        int target_node,
+                                        const RRNodeId& target_node,
                                         const t_conn_cost_params cost_params,
                                         const RouterLookahead& router_lookahead,
                                         RouterStats& router_stats);
@@ -215,36 +215,36 @@ static void timing_driven_expand_neighbours(t_heap* current,
                                             const t_conn_cost_params cost_params,
                                             t_bb bounding_box,
                                             const RouterLookahead& router_lookahead,
-                                            int target_node,
+                                            const RRNodeId& target_node,
                                             RouterStats& router_stats);
 
 static void timing_driven_expand_neighbour(t_heap* current,
-                                           const int from_node,
-                                           const t_edge_size from_edge,
-                                           const int to_node,
+                                           const RRNodeId& from_node,
+                                           const RREdgeId& from_edge,
+                                           const RRNodeId& to_node,
                                            const t_conn_cost_params cost_params,
                                            const t_bb bounding_box,
                                            const RouterLookahead& router_lookahead,
-                                           int target_node,
+                                           const RRNodeId& target_node,
                                            const t_bb target_bb,
                                            RouterStats& router_stats);
 
 static void timing_driven_add_to_heap(const t_conn_cost_params cost_params,
                                       const RouterLookahead& router_lookahead,
                                       const t_heap* current,
-                                      const int from_node,
-                                      const int to_node,
-                                      const int iconn,
-                                      const int target_node,
+                                      const RRNodeId& from_node,
+                                      const RRNodeId& to_node,
+                                      const RREdgeId& iconn,
+                                      const RRNodeId& target_node,
                                       RouterStats& router_stats);
 
 static void timing_driven_expand_node(const t_conn_cost_params cost_params,
                                       const RouterLookahead& router_lookahead,
                                       t_heap* current,
-                                      const int from_node,
-                                      const int to_node,
-                                      const int iconn,
-                                      const int target_node);
+                                      const RRNodeId& from_node,
+                                      const RRNodeId& to_node,
+                                      const RREdgeId& iconn,
+                                      const RRNodeId& target_node);
 
 static void evaluate_timing_driven_node_costs(t_heap* from,
                                               const t_conn_cost_params cost_params,
@@ -1296,18 +1296,18 @@ static bool timing_driven_route_sink(ClusterNetId net_id,
 //
 //Returns either the last element of the path, or nullptr if no path is found
 t_heap* timing_driven_route_connection_from_route_tree(t_rt_node* rt_root,
-                                                       int sink_node,
+                                                       const RRNodeId& sink_node,
                                                        const t_conn_cost_params cost_params,
                                                        t_bb bounding_box,
                                                        const RouterLookahead& router_lookahead,
-                                                       std::vector<int>& modified_rr_node_inf,
+                                                       std::vector<RRNodeId>& modified_rr_node_inf,
                                                        RouterStats& router_stats) {
     // re-explore route tree from root to add any new nodes (buildheap afterwards)
     // route tree needs to be repushed onto the heap since each node's cost is target specific
     add_route_tree_to_heap(rt_root, sink_node, cost_params, router_lookahead, router_stats);
     heap_::build_heap(); // via sifting down everything
 
-    int source_node = rt_root->inode;
+    RRNodeId source_node = rt_root->inode;
 
     if (is_empty_heap()) {
         VTR_LOG("No source in route tree: %s\n", describe_unrouteable_connection(source_node, sink_node).c_str());
@@ -1454,11 +1454,11 @@ static t_heap* timing_driven_route_connection_from_route_tree_high_fanout(t_rt_n
 //This is the core maze routing routine.
 //
 //Returns either the last element of the path, or nullptr if no path is found
-static t_heap* timing_driven_route_connection_from_heap(int sink_node,
+static t_heap* timing_driven_route_connection_from_heap(const RRNodeId& sink_node,
                                                         const t_conn_cost_params cost_params,
                                                         t_bb bounding_box,
                                                         const RouterLookahead& router_lookahead,
-                                                        std::vector<int>& modified_rr_node_inf,
+                                                        std::vector<RRNodeId>& modified_rr_node_inf,
                                                         RouterStats& router_stats) {
     VTR_ASSERT_SAFE(heap_::is_valid());
 
@@ -1472,13 +1472,13 @@ static t_heap* timing_driven_route_connection_from_heap(int sink_node,
         cheapest = get_heap_head();
         ++router_stats.heap_pops;
 
-        int inode = cheapest->index;
+        RRNodeId inode = cheapest->index;
         VTR_LOGV_DEBUG(f_router_debug, "  Popping node %d (cost: %g)\n",
-                       inode, cheapest->cost);
+                       size_t(inode), cheapest->cost);
 
         //Have we found the target?
         if (inode == sink_node) {
-            VTR_LOGV_DEBUG(f_router_debug, "  Found target %8d (%s)\n", inode, describe_rr_node(inode).c_str());
+            VTR_LOGV_DEBUG(f_router_debug, "  Found target %8d (%s)\n", size_t(inode), describe_rr_node(inode).c_str());
             break;
         }
 
@@ -1584,15 +1584,15 @@ static std::vector<t_heap> timing_driven_find_all_shortest_paths_from_heap(const
 }
 
 static void timing_driven_expand_cheapest(t_heap* cheapest,
-                                          int target_node,
+                                          const RRNodeId& target_node,
                                           const t_conn_cost_params cost_params,
                                           t_bb bounding_box,
                                           const RouterLookahead& router_lookahead,
-                                          std::vector<int>& modified_rr_node_inf,
+                                          std::vector<RRNodeId>& modified_rr_node_inf,
                                           RouterStats& router_stats) {
     auto& route_ctx = g_vpr_ctx.mutable_routing();
 
-    int inode = cheapest->index;
+    RRNodeId inode = cheapest->index;
 
     float best_total_cost = route_ctx.rr_node_route_inf[inode].path_cost;
     float best_back_cost = route_ctx.rr_node_route_inf[inode].backward_path_cost;
@@ -1611,7 +1611,7 @@ static void timing_driven_expand_cheapest(t_heap* cheapest,
     if (best_total_cost > new_total_cost && best_back_cost > new_back_cost) {
         //Explore from this node, since the current/new partial path has the best cost
         //found so far
-        VTR_LOGV_DEBUG(f_router_debug, "    Better cost to %d\n", inode);
+        VTR_LOGV_DEBUG(f_router_debug, "    Better cost to %d\n", size_t(inode));
         VTR_LOGV_DEBUG(f_router_debug, "    New total cost: %g\n", new_total_cost);
         VTR_LOGV_DEBUG(f_router_debug, "    New back cost: %g\n", new_back_cost);
         VTR_LOGV_DEBUG(f_router_debug, "      Setting path costs for assicated node %d (from %d edge %d)\n", cheapest->index, cheapest->u.prev.node, cheapest->u.prev.edge);
@@ -1630,7 +1630,7 @@ static void timing_driven_expand_cheapest(t_heap* cheapest,
     } else {
         //Post-heap prune, do not re-explore from the current/new partial path as it 
         //has worse cost than the best partial path to this node found so far
-        VTR_LOGV_DEBUG(f_router_debug, "    Worse cost to %d\n", inode);
+        VTR_LOGV_DEBUG(f_router_debug, "    Worse cost to %d\n", size_t(inode));
         VTR_LOGV_DEBUG(f_router_debug, "    Old total cost: %g\n", best_total_cost);
         VTR_LOGV_DEBUG(f_router_debug, "    Old back cost: %g\n", best_back_cost);
         VTR_LOGV_DEBUG(f_router_debug, "    New total cost: %g\n", new_total_cost);
@@ -1797,7 +1797,7 @@ void disable_expansion_and_remove_sink_from_route_tree_nodes(t_rt_node* rt_node)
 }
 
 static void add_route_tree_to_heap(t_rt_node* rt_node,
-                                   int target_node,
+                                   const RRNodeId& target_node,
                                    const t_conn_cost_params cost_params,
                                    const RouterLookahead& router_lookahead,
                                    RouterStats& router_stats) {
@@ -1929,11 +1929,11 @@ static t_bb adjust_highfanout_bounding_box(t_bb highfanout_bb) {
 //Note that if you want to respect rt_node->re_expand that is the caller's
 //responsibility.
 static void add_route_tree_node_to_heap(t_rt_node* rt_node,
-                                        int target_node,
+                                        const RRNodeId& target_node,
                                         const t_conn_cost_params cost_params,
                                         const RouterLookahead& router_lookahead,
                                         RouterStats& router_stats) {
-    int inode = rt_node->inode;
+    const RRNodeId& inode = rt_node->inode_id;
     float backward_path_cost = cost_params.criticality * rt_node->Tdel;
 
     float R_upstream = rt_node->R_upstream;
@@ -1955,7 +1955,7 @@ static void add_route_tree_node_to_heap(t_rt_node* rt_node,
 
     VTR_LOGV_DEBUG(f_router_debug, "  Adding node %8d to heap from init route tree with cost %g (%s)\n", inode, tot_cost, describe_rr_node(inode).c_str());
 
-    heap_::push_back_node(inode, tot_cost, NO_PREVIOUS, NO_PREVIOUS,
+    heap_::push_back_node(inode, tot_cost, RRNodeId::INVALID(), RREdgeId::INVALID(),
                           backward_path_cost, R_upstream);
 
     ++router_stats.heap_pushes;
@@ -1965,7 +1965,7 @@ static void timing_driven_expand_neighbours(t_heap* current,
                                             const t_conn_cost_params cost_params,
                                             t_bb bounding_box,
                                             const RouterLookahead& router_lookahead,
-                                            int target_node,
+                                            const RRNodeId& target_node,
                                             RouterStats& router_stats) {
     /* Puts all the rr_nodes adjacent to current on the heap.
      */
@@ -1974,18 +1974,17 @@ static void timing_driven_expand_neighbours(t_heap* current,
 
     t_bb target_bb;
     if (target_node != OPEN) {
-        target_bb.xmin = device_ctx.rr_nodes[target_node].xlow();
-        target_bb.ymin = device_ctx.rr_nodes[target_node].ylow();
-        target_bb.xmax = device_ctx.rr_nodes[target_node].xhigh();
-        target_bb.ymax = device_ctx.rr_nodes[target_node].yhigh();
+        target_bb.xmin = device_ctx.rr_graph.node_xlow(target_node);
+        target_bb.ymin = device_ctx.rr_graph.node_ylow(target_node);
+        target_bb.xmax = device_ctx.rr_graph.node_xhigh(target_node);
+        target_bb.ymax = device_ctx.rr_graph.node_yhigh(target_node);
     }
 
     //For each node associated with the current heap element, expand all of it's neighbours
-    int num_edges = device_ctx.rr_nodes[current->index].num_edges();
-    for (int iconn = 0; iconn < num_edges; iconn++) {
-        int to_node = device_ctx.rr_nodes[current->index].edge_sink_node(iconn);
+    for (const RREdgeId& edge : device_ctx.rr_graph.node_out_edges(current->index)) {
+        const RRNodeId& to_node = device_ctx.rr_graph.edge_sink_node[edge];
         timing_driven_expand_neighbour(current,
-                                       current->index, iconn, to_node,
+                                       current->index, edge, to_node,
                                        cost_params,
                                        bounding_box,
                                        router_lookahead,
@@ -1999,31 +1998,31 @@ static void timing_driven_expand_neighbours(t_heap* current,
 //RR nodes outside the expanded bounding box specified in bounding_box are not added
 //to the heap.
 static void timing_driven_expand_neighbour(t_heap* current,
-                                           const int from_node,
-                                           const t_edge_size from_edge,
-                                           const int to_node,
+                                           const RRNodeId& from_node,
+                                           const RREdgeId& from_edge,
+                                           const RRNodeId& to_node,
                                            const t_conn_cost_params cost_params,
                                            const t_bb bounding_box,
                                            const RouterLookahead& router_lookahead,
-                                           int target_node,
+                                           const RRNodeId& target_node,
                                            const t_bb target_bb,
                                            RouterStats& router_stats) {
     auto& device_ctx = g_vpr_ctx.device();
 
-    int to_xlow = device_ctx.rr_nodes[to_node].xlow();
-    int to_ylow = device_ctx.rr_nodes[to_node].ylow();
-    int to_xhigh = device_ctx.rr_nodes[to_node].xhigh();
-    int to_yhigh = device_ctx.rr_nodes[to_node].yhigh();
+    int to_xlow =  device_ctx.rr_graph.node_xlow(to_node);
+    int to_ylow =  device_ctx.rr_graph.node_ylow(to_node);
+    int to_xhigh = device_ctx.rr_graph.node_xhigh(to_node);
+    int to_yhigh = device_ctx.rr_graph.node_yhigh(to_node);
 
     if (to_xhigh < bounding_box.xmin      //Strictly left of BB left-edge
         || to_xlow > bounding_box.xmax    //Strictly right of BB right-edge
         || to_yhigh < bounding_box.ymin   //Strictly below BB bottom-edge
         || to_ylow > bounding_box.ymax) { //Strictly above BB top-edge
         VTR_LOGV_DEBUG(f_router_debug,
-                       "      Pruned expansion of node %d edge %d -> %d"
+                       "      Pruned expansion of node %ld edge %ld -> %ld"
                        " (to node location %d,%dx%d,%d outside of expanded"
                        " net bounding box %d,%dx%d,%d)\n",
-                       from_node, from_edge, to_node,
+                       size_t(from_node), size_t(from_edge), size_t(to_node),
                        to_xlow, to_ylow, to_xhigh, to_yhigh,
                        bounding_box.xmin, bounding_box.ymin, bounding_box.xmax, bounding_box.ymax);
         return; /* Node is outside (expanded) bounding box. */
@@ -2034,7 +2033,7 @@ static void timing_driven_expand_neighbour(t_heap* current,
      * more promising routes, but makes route-throughs (via CLBs) impossible.   *
      * Change this if you want to investigate route-throughs.                   */
     if (target_node != OPEN) {
-        t_rr_type to_type = device_ctx.rr_nodes[to_node].type();
+        t_rr_type to_type = device_ctx.rr_graph.node_type(to_node);
         if (to_type == IPIN) {
             //Check if this IPIN leads to the target block
             // IPIN's of the target block should be contained within it's bounding box
@@ -2043,10 +2042,10 @@ static void timing_driven_expand_neighbour(t_heap* current,
                 || to_xhigh > target_bb.xmax
                 || to_yhigh > target_bb.ymax) {
                 VTR_LOGV_DEBUG(f_router_debug,
-                               "      Pruned expansion of node %d edge %d -> %d"
+                               "      Pruned expansion of node %ld edge %ld -> %ld"
                                " (to node is IPIN at %d,%dx%d,%d which does not"
                                " lead to target block %d,%dx%d,%d)\n",
-                               from_node, from_edge, to_node,
+                               size_t(from_node), size_t(from_edge), size_t(to_node),
                                to_xlow, to_ylow, to_xhigh, to_yhigh,
                                target_bb.xmin, target_bb.ymin, target_bb.xmax, target_bb.ymax);
                 return;
@@ -2054,8 +2053,8 @@ static void timing_driven_expand_neighbour(t_heap* current,
         }
     }
 
-    VTR_LOGV_DEBUG(f_router_debug, "      Expanding node %d edge %d -> %d\n",
-                   from_node, from_edge, to_node);
+    VTR_LOGV_DEBUG(f_router_debug, "      Expanding node %ld edge %ld -> %ld\n",
+                   size_t(from_node), size_t(from_edge), size_t(to_node));
 
     timing_driven_add_to_heap(cost_params,
                               router_lookahead,
@@ -2066,10 +2065,10 @@ static void timing_driven_expand_neighbour(t_heap* current,
 static void timing_driven_add_to_heap(const t_conn_cost_params cost_params,
                                       const RouterLookahead& router_lookahead,
                                       const t_heap* current,
-                                      const int from_node,
-                                      const int to_node,
-                                      const int iconn,
-                                      const int target_node,
+                                      const RRNodeId& from_node,
+                                      const RRNodeId& to_node,
+                                      const RREdgeId& iconn,
+                                      const RRNodeId& target_node,
                                       RouterStats& router_stats) {
     t_heap* next = alloc_heap_data();
     next->index = to_node;
@@ -2085,8 +2084,8 @@ static void timing_driven_add_to_heap(const t_conn_cost_params cost_params,
 
     auto& route_ctx = g_vpr_ctx.routing();
 
-    float best_total_cost = route_ctx.rr_node_route_inf[to_node].path_cost;
-    float best_back_cost = route_ctx.rr_node_route_inf[to_node].backward_path_cost;
+    float best_total_cost = route_ctx.rr_node_route_inf[size_t(to_node)].path_cost;
+    float best_back_cost = route_ctx.rr_node_route_inf[size_t(to_node)].backward_path_cost;
 
     float new_total_cost = next->cost;
     float new_back_cost = next->backward_path_cost;
@@ -2110,11 +2109,11 @@ static void timing_driven_add_to_heap(const t_conn_cost_params cost_params,
 static void timing_driven_expand_node(const t_conn_cost_params cost_params,
                                       const RouterLookahead& router_lookahead,
                                       t_heap* current,
-                                      const int from_node,
-                                      const int to_node,
-                                      const int iconn,
-                                      const int target_node) {
-    VTR_LOGV_DEBUG(f_router_debug, "      Expanding to node %d (%s)\n", to_node, describe_rr_node(to_node).c_str());
+                                      const RRNodeId& from_node,
+                                      const RRNodeId& to_node,
+                                      const RREdgeId& iconn,
+                                      const RRNodeId& target_node) {
+    VTR_LOGV_DEBUG(f_router_debug, "      Expanding to node %ld (%s)\n", size_t(to_node), describe_rr_node(to_node).c_str());
 
     evaluate_timing_driven_node_costs(current,
                                       cost_params,
@@ -2131,10 +2130,10 @@ static void timing_driven_expand_node(const t_conn_cost_params cost_params,
 static void evaluate_timing_driven_node_costs(t_heap* to,
                                               const t_conn_cost_params cost_params,
                                               const RouterLookahead& router_lookahead,
-                                              const int from_node,
-                                              const int to_node,
-                                              const int iconn,
-                                              const int target_node) {
+                                              const RRNodeId& from_node,
+                                              const RRNodeId& to_node,
+                                              const RREdgeId& iconn,
+                                              const RRNodeId& target_node) {
     /* new_costs.backward_cost: is the "known" part of the cost to this node -- the
      * congestion cost of all the routing resources back to the existing route
      * plus the known delay of the total path back to the source.
@@ -2146,18 +2145,18 @@ static void evaluate_timing_driven_node_costs(t_heap* to,
     auto& device_ctx = g_vpr_ctx.device();
 
     //Info for the switch connecting from_node to_node
-    int iswitch = device_ctx.rr_nodes[from_node].edge_switch(iconn);
+    int iswitch = size_t(device_ctx.rr_graph.edge_switch(iconn));
     bool switch_buffered = device_ctx.rr_switch_inf[iswitch].buffered();
     float switch_R = device_ctx.rr_switch_inf[iswitch].R;
     float switch_Tdel = device_ctx.rr_switch_inf[iswitch].Tdel;
     float switch_Cinternal = device_ctx.rr_switch_inf[iswitch].Cinternal;
 
     //To node info
-    float node_C = device_ctx.rr_nodes[to_node].C();
-    float node_R = device_ctx.rr_nodes[to_node].R();
+    float node_C = device_ctx.rr_graph.node_C(to_node);
+    float node_R = device_ctx.rr_graph.node_R(to_node);
 
     //From node info
-    float from_node_R = device_ctx.rr_nodes[from_node].R();
+    float from_node_R = device_ctx.rr_graph.node_R(from_node);
 
     //Update R_upstream
     if (switch_buffered) {
@@ -2189,7 +2188,7 @@ static void evaluate_timing_driven_node_costs(t_heap* to,
     //Second, we adjust the Tdel to account for the delay caused by the internal capacitance.
     Tdel += Rdel_adjust * switch_Cinternal;
 
-    bool reached_configurably = device_ctx.rr_nodes[from_node].edge_is_configurable(iconn);
+    bool reached_configurably = device_ctx.rr_graph.edge_is_configurable(iconn);
 
     float cong_cost = 0.;
     if (reached_configurably) {
@@ -2211,8 +2210,8 @@ static void evaluate_timing_driven_node_costs(t_heap* to,
     to->backward_path_cost += cost_params.criticality * Tdel;             //Delay cost
 
     if (cost_params.bend_cost != 0.) {
-        t_rr_type from_type = device_ctx.rr_nodes[from_node].type();
-        t_rr_type to_type = device_ctx.rr_nodes[to_node].type();
+        t_rr_type from_type = device_ctx.rr_graph.node_type(from_node);
+        t_rr_type to_type = device_ctx.rr_graph.node_type(to_node);
         if ((from_type == CHANX && to_type == CHANY) || (from_type == CHANY && to_type == CHANX)) {
             to->backward_path_cost += cost_params.bend_cost; //Bend cost
         }
@@ -2736,7 +2735,7 @@ static void print_route_status(int itry, double elapsed_sec, float pres_fac, int
     fflush(stdout);
 }
 
-static std::string describe_unrouteable_connection(const int source_node, const int sink_node) {
+static std::string describe_unrouteable_connection(const RRNodeId& source_node, const RRNodeId& sink_node) {
     std::string msg = vtr::string_fmt(
         "Cannot route from %s (%s) to "
         "%s (%s) -- no possible path",
@@ -3051,7 +3050,7 @@ static void prune_unused_non_configurable_nets(CBRR& connections_inf) {
 }
 
 //Returns true if both nodes are part of the same non-configurable edge set
-static bool same_non_config_node_set(int from_node, int to_node) {
+static bool same_non_config_node_set(const RRNodeId& from_node, const RRNodeId& to_node) {
     auto& device_ctx = g_vpr_ctx.device();
 
     auto from_itr = device_ctx.rr_node_to_non_config_node_set.find(from_node);
diff --git a/vpr/src/route/route_timing.h b/vpr/src/route/route_timing.h
index c356b096c..e7c808627 100644
--- a/vpr/src/route/route_timing.h
+++ b/vpr/src/route/route_timing.h
@@ -56,7 +56,7 @@ void alloc_timing_driven_route_structs(float** pin_criticality_ptr,
                                        t_rt_node*** rt_node_of_sink_ptr);
 void free_timing_driven_route_structs(float* pin_criticality, int* sink_order, t_rt_node** rt_node_of_sink);
 
-void enable_router_debug(const t_router_opts& router_opts, ClusterNetId net, int sink_rr);
+void enable_router_debug(const t_router_opts& router_opts, ClusterNetId net, const RRNodeId& sink_rr);
 
 //Delay budget information for a specific connection
 struct t_conn_delay_budget {
@@ -80,11 +80,11 @@ struct t_conn_cost_params {
 };
 
 t_heap* timing_driven_route_connection_from_route_tree(t_rt_node* rt_root,
-                                                       int sink_node,
+                                                       const RRNodeId& sink_node,
                                                        const t_conn_cost_params cost_params,
                                                        t_bb bounding_box,
                                                        const RouterLookahead& router_lookahead,
-                                                       std::vector<int>& modified_rr_node_inf,
+                                                       std::vector<RRNodeId>& modified_rr_node_inf,
                                                        RouterStats& router_stats);
 
 std::vector<t_heap> timing_driven_find_all_shortest_paths_from_route_tree(t_rt_node* rt_root,
diff --git a/vpr/src/route/route_tree_timing.cpp b/vpr/src/route/route_tree_timing.cpp
index faf33c7dd..3b947ee43 100644
--- a/vpr/src/route/route_tree_timing.cpp
+++ b/vpr/src/route/route_tree_timing.cpp
@@ -536,7 +536,7 @@ void load_route_tree_Tdel(t_rt_node* subtree_rt_root, float Tarrival) {
      * must be correct before this routine is called.  Tarrival is the time at
      * at which the signal arrives at this node's *input*.                      */
 
-    int inode;
+    RRNodeId inode;
     short iswitch;
     t_rt_node* child_node;
     t_linked_rt_edge* linked_rt_edge;
@@ -550,7 +550,7 @@ void load_route_tree_Tdel(t_rt_node* subtree_rt_root, float Tarrival) {
      * along a wire segment's length.  See discussion in net_delay.c if you want
      * to change this.                                                           */
 
-    Tdel = Tarrival + 0.5 * subtree_rt_root->C_downstream * device_ctx.rr_nodes[inode].R();
+    Tdel = Tarrival + 0.5 * subtree_rt_root->C_downstream * device_ctx.rr_graph.node_R(inode);
     subtree_rt_root->Tdel = Tdel;
 
     /* Now expand the children of this node to load their Tdel values (depth-
@@ -1415,7 +1415,7 @@ bool is_uncongested_route_tree(const t_rt_node* root) {
 }
 
 t_rt_node*
-init_route_tree_to_source_no_net(int inode) {
+init_route_tree_to_source_no_net(const RRNodeId& inode) {
     /* Initializes the routing tree to just the net source, and returns the root
      * node of the rt_tree (which is just the net source).                       */
 
@@ -1428,11 +1428,14 @@ init_route_tree_to_source_no_net(int inode) {
     rt_root->parent_node = nullptr;
     rt_root->parent_switch = OPEN;
     rt_root->re_expand = true;
-    rt_root->inode = inode;
-    rt_root->C_downstream = device_ctx.rr_nodes[inode].C();
-    rt_root->R_upstream = device_ctx.rr_nodes[inode].R();
-    rt_root->Tdel = 0.5 * device_ctx.rr_nodes[inode].R() * device_ctx.rr_nodes[inode].C();
-    rr_node_to_rt_node[inode] = rt_root;
+    rt_root->inode = size_t(inode);
+
+    rt_root->inode_id = inode;
+
+    rt_root->C_downstream = device_ctx.rr_graph.node_C(inode);
+    rt_root->R_upstream = device_ctx.rr_graph.node_R(inode);
+    rt_root->Tdel = 0.5 * device_ctx.rr_graph.node_R(inode) * device_ctx.rr_graph.node_C(inode);
+    rr_node_to_rt_node[size_t(inode)] = rt_root;
 
     return (rt_root);
 }
diff --git a/vpr/src/route/route_tree_timing.h b/vpr/src/route/route_tree_timing.h
index 01e4d88a2..781b11e5d 100644
--- a/vpr/src/route/route_tree_timing.h
+++ b/vpr/src/route/route_tree_timing.h
@@ -4,6 +4,7 @@
 #include "connection_based_routing.h"
 #include "route_common.h"
 #include "spatial_route_tree_lookup.h"
+#include "rr_graph_obj.h"
 
 /**************** Subroutines exported by route_tree_timing.c ***************/
 
@@ -30,7 +31,7 @@ void update_remaining_net_delays_from_route_tree(float* net_delay,
 void load_route_tree_Tdel(t_rt_node* rt_root, float Tarrival);
 void load_route_tree_rr_route_inf(t_rt_node* root);
 
-t_rt_node* init_route_tree_to_source_no_net(int inode);
+t_rt_node* init_route_tree_to_source_no_net(const RRNodeId& inode);
 
 void add_route_tree_to_rr_node_lookup(t_rt_node* node);
 
diff --git a/vpr/src/route/route_tree_type.h b/vpr/src/route/route_tree_type.h
index 5e81bd1e4..91fb61296 100644
--- a/vpr/src/route/route_tree_type.h
+++ b/vpr/src/route/route_tree_type.h
@@ -51,10 +51,8 @@ struct t_rt_node {
     RRSwitchId parent_switch_id;
 
     bool re_expand;
-    int inode;
-
     /* Xifan Tang - RRGraph node */
-    RRNodeId inode_id;
+    RRNodeId inode;
 
     float C_downstream;
     float R_upstream;
diff --git a/vpr/src/route/router_delay_profiling.cpp b/vpr/src/route/router_delay_profiling.cpp
index ab0343e43..39dbce7fa 100644
--- a/vpr/src/route/router_delay_profiling.cpp
+++ b/vpr/src/route/router_delay_profiling.cpp
@@ -13,7 +13,7 @@ RouterDelayProfiler::RouterDelayProfiler(
     const RouterLookahead* lookahead)
     : router_lookahead_(lookahead) {}
 
-bool RouterDelayProfiler::calculate_delay(int source_node, int sink_node, const t_router_opts& router_opts, float* net_delay) const {
+bool RouterDelayProfiler::calculate_delay(const RRNodeId& source_node, const RRNodeId& sink_node, const t_router_opts& router_opts, float* net_delay) const {
     /* Returns true as long as found some way to hook up this net, even if that *
      * way resulted in overuse of resources (congestion).  If there is no way   *
      * to route this net, even ignoring congestion, it returns false.  In this  *
@@ -22,7 +22,8 @@ bool RouterDelayProfiler::calculate_delay(int source_node, int sink_node, const
     auto& route_ctx = g_vpr_ctx.routing();
 
     t_rt_node* rt_root = setup_routing_resources_no_net(source_node);
-    enable_router_debug(router_opts, ClusterNetId(), sink_node);
+    /* TODO: This should be changed to RRNodeId */
+    enable_router_debug(router_opts, ClusterNetId(), size_t(sink_node));
 
     /* Update base costs according to fanout and criticality rules */
     update_rr_base_costs(1);
@@ -59,7 +60,7 @@ bool RouterDelayProfiler::calculate_delay(int source_node, int sink_node, const
         //find delay
         *net_delay = rt_node_of_sink->Tdel;
 
-        VTR_ASSERT_MSG(route_ctx.rr_node_route_inf[rt_root->inode].occ() <= device_ctx.rr_nodes[rt_root->inode].capacity(), "SOURCE should never be congested");
+        VTR_ASSERT_MSG(route_ctx.rr_node_route_inf[rt_root->inode].occ() <= device_ctx.rr_graph.node_capacity(rt_root->inode_id), "SOURCE should never be congested");
         free_route_tree(rt_root);
     }
 
diff --git a/vpr/src/route/router_delay_profiling.h b/vpr/src/route/router_delay_profiling.h
index 7bab4e2ed..7f3918685 100644
--- a/vpr/src/route/router_delay_profiling.h
+++ b/vpr/src/route/router_delay_profiling.h
@@ -9,7 +9,7 @@
 class RouterDelayProfiler {
   public:
     RouterDelayProfiler(const RouterLookahead* lookahead);
-    bool calculate_delay(int source_node, int sink_node, const t_router_opts& router_opts, float* net_delay) const;
+    bool calculate_delay(const RRNodeId& source_node, const RRNodeId& sink_node, const t_router_opts& router_opts, float* net_delay) const;
 
   private:
     const RouterLookahead* router_lookahead_;
diff --git a/vpr/src/route/router_lookahead.cpp b/vpr/src/route/router_lookahead.cpp
index 130b862e9..1c31582b6 100644
--- a/vpr/src/route/router_lookahead.cpp
+++ b/vpr/src/route/router_lookahead.cpp
@@ -5,7 +5,7 @@
 #include "globals.h"
 #include "route_timing.h"
 
-static int get_expected_segs_to_target(int inode, int target_node, int* num_segs_ortho_dir_ptr);
+static int get_expected_segs_to_target(const RRNodeId& inode, const RRNodeId& target_node, int* num_segs_ortho_dir_ptr);
 static int round_up(float x);
 
 static std::unique_ptr<RouterLookahead> make_router_lookahead_object(e_router_lookahead router_lookahead_type) {
@@ -41,10 +41,10 @@ std::unique_ptr<RouterLookahead> make_router_lookahead(
     return router_lookahead;
 }
 
-float ClassicLookahead::get_expected_cost(int current_node, int target_node, const t_conn_cost_params& params, float R_upstream) const {
+float ClassicLookahead::get_expected_cost(const RRNodeId& current_node, const RRNodeId& target_node, const t_conn_cost_params& params, float R_upstream) const {
     auto& device_ctx = g_vpr_ctx.device();
 
-    t_rr_type rr_type = device_ctx.rr_nodes[current_node].type();
+    t_rr_type rr_type = device_ctx.rr_graph.node_type(current_node);
 
     if (rr_type == CHANX || rr_type == CHANY) {
         return classic_wire_lookahead_cost(current_node, target_node, params.criticality, R_upstream);
@@ -55,15 +55,15 @@ float ClassicLookahead::get_expected_cost(int current_node, int target_node, con
     }
 }
 
-float ClassicLookahead::classic_wire_lookahead_cost(int inode, int target_node, float criticality, float R_upstream) const {
+float ClassicLookahead::classic_wire_lookahead_cost(const RRNodeId& inode, const RRNodeId& target_node, float criticality, float R_upstream) const {
     auto& device_ctx = g_vpr_ctx.device();
 
-    VTR_ASSERT_SAFE(device_ctx.rr_nodes[inode].type() == CHANX || device_ctx.rr_nodes[inode].type() == CHANY);
+    VTR_ASSERT_SAFE(device_ctx.rr_graph.node_type(inode) == CHANX || device_ctx.rr_graph.node_type(inode) == CHANY);
 
     int num_segs_ortho_dir = 0;
     int num_segs_same_dir = get_expected_segs_to_target(inode, target_node, &num_segs_ortho_dir);
 
-    int cost_index = device_ctx.rr_nodes[inode].cost_index();
+    int cost_index = device_ctx.rr_graph.node_cost_index(inode);
     int ortho_cost_index = device_ctx.rr_indexed_data[cost_index].ortho_cost_index;
 
     const auto& same_data = device_ctx.rr_indexed_data[cost_index];
@@ -87,10 +87,10 @@ float ClassicLookahead::classic_wire_lookahead_cost(int inode, int target_node,
     return (expected_cost);
 }
 
-float MapLookahead::get_expected_cost(int current_node, int target_node, const t_conn_cost_params& params, float /*R_upstream*/) const {
+float MapLookahead::get_expected_cost(const RRNodeId& current_node, const RRNodeId& target_node, const t_conn_cost_params& params, float /*R_upstream*/) const {
     auto& device_ctx = g_vpr_ctx.device();
 
-    t_rr_type rr_type = device_ctx.rr_nodes[current_node].type();
+    t_rr_type rr_type = device_ctx.rr_graph.node_type(current_node);
 
     if (rr_type == CHANX || rr_type == CHANY) {
         return get_lookahead_map_cost(current_node, target_node, params.criticality);
@@ -105,7 +105,7 @@ void MapLookahead::compute(const std::vector<t_segment_inf>& segment_inf) {
     compute_router_lookahead(segment_inf.size());
 }
 
-float NoOpLookahead::get_expected_cost(int /*current_node*/, int /*target_node*/, const t_conn_cost_params& /*params*/, float /*R_upstream*/) const {
+float NoOpLookahead::get_expected_cost(const RRNodeId& /*current_node*/, const RRNodeId& /*target_node*/, const t_conn_cost_params& /*params*/, float /*R_upstream*/) const {
     return 0.;
 }
 
@@ -115,7 +115,7 @@ static int round_up(float x) {
     return std::ceil(x - 0.001);
 }
 
-static int get_expected_segs_to_target(int inode, int target_node, int* num_segs_ortho_dir_ptr) {
+static int get_expected_segs_to_target(const RRNodeId& inode, const RRNodeId& target_node, int* num_segs_ortho_dir_ptr) {
     /* Returns the number of segments the same type as inode that will be needed *
      * to reach target_node (not including inode) in each direction (the same    *
      * direction (horizontal or vertical) as inode and the orthogonal direction).*/
@@ -127,18 +127,18 @@ static int get_expected_segs_to_target(int inode, int target_node, int* num_segs
     int no_need_to_pass_by_clb;
     float inv_length, ortho_inv_length, ylow, yhigh, xlow, xhigh;
 
-    target_x = device_ctx.rr_nodes[target_node].xlow();
-    target_y = device_ctx.rr_nodes[target_node].ylow();
-    cost_index = device_ctx.rr_nodes[inode].cost_index();
+    target_x = device_ctx.rr_graph.node_xlow(target_node);
+    target_y = device_ctx.rr_graph.node_ylow(target_node);
+    cost_index = device_ctx.rr_graph.node_cost_index(inode);
     inv_length = device_ctx.rr_indexed_data[cost_index].inv_length;
     ortho_cost_index = device_ctx.rr_indexed_data[cost_index].ortho_cost_index;
     ortho_inv_length = device_ctx.rr_indexed_data[ortho_cost_index].inv_length;
-    rr_type = device_ctx.rr_nodes[inode].type();
+    rr_type = device_ctx.rr_graph.node_type(inode);
 
     if (rr_type == CHANX) {
-        ylow = device_ctx.rr_nodes[inode].ylow();
-        xhigh = device_ctx.rr_nodes[inode].xhigh();
-        xlow = device_ctx.rr_nodes[inode].xlow();
+        ylow = device_ctx.rr_graph.node_ylow(inode);
+        xhigh = device_ctx.rr_graph.node_xhigh(inode);
+        xlow = device_ctx.rr_graph.node_xlow(inode);
 
         /* Count vertical (orthogonal to inode) segs first. */
 
@@ -163,9 +163,9 @@ static int get_expected_segs_to_target(int inode, int target_node, int* num_segs
             num_segs_same_dir = 0;
         }
     } else { /* inode is a CHANY */
-        ylow = device_ctx.rr_nodes[inode].ylow();
-        yhigh = device_ctx.rr_nodes[inode].yhigh();
-        xlow = device_ctx.rr_nodes[inode].xlow();
+        ylow = device_ctx.rr_graph.node_ylow(inode);
+        yhigh = device_ctx.rr_graph.node_yhigh(inode);
+        xlow = device_ctx.rr_graph.node_xlow(inode);
 
         /* Count horizontal (orthogonal to inode) segs first. */
 
diff --git a/vpr/src/route/router_lookahead.h b/vpr/src/route/router_lookahead.h
index 283df54be..9184bc429 100644
--- a/vpr/src/route/router_lookahead.h
+++ b/vpr/src/route/router_lookahead.h
@@ -12,7 +12,7 @@ class RouterLookahead {
     //
     // Either compute or read methods must be invoked before invoking
     // get_expected_cost.
-    virtual float get_expected_cost(int node, int target_node, const t_conn_cost_params& params, float R_upstream) const = 0;
+    virtual float get_expected_cost(const RRNodeId& node, const RRNodeId& target_node, const t_conn_cost_params& params, float R_upstream) const = 0;
 
     // Compute router lookahead (if needed).
     virtual void compute(const std::vector<t_segment_inf>& segment_inf) = 0;
@@ -53,7 +53,7 @@ const RouterLookahead* get_cached_router_lookahead(
 
 class ClassicLookahead : public RouterLookahead {
   public:
-    float get_expected_cost(int node, int target_node, const t_conn_cost_params& params, float R_upstream) const override;
+    float get_expected_cost(const RRNodeId& node, const RRNodeId& target_node, const t_conn_cost_params& params, float R_upstream) const override;
     void compute(const std::vector<t_segment_inf>& /*segment_inf*/) override {
     }
 
@@ -65,12 +65,12 @@ class ClassicLookahead : public RouterLookahead {
     }
 
   private:
-    float classic_wire_lookahead_cost(int node, int target_node, float criticality, float R_upstream) const;
+    float classic_wire_lookahead_cost(const RRNodeId& node, const RRNodeId& target_node, float criticality, float R_upstream) const;
 };
 
 class MapLookahead : public RouterLookahead {
   protected:
-    float get_expected_cost(int node, int target_node, const t_conn_cost_params& params, float R_upstream) const override;
+    float get_expected_cost(const RRNodeId& node, const RRNodeId& target_node, const t_conn_cost_params& params, float R_upstream) const override;
     void compute(const std::vector<t_segment_inf>& segment_inf) override;
     void read(const std::string& /*file*/) override {
         VPR_THROW(VPR_ERROR_ROUTE, "MapLookahead::read unimplemented");
@@ -82,7 +82,7 @@ class MapLookahead : public RouterLookahead {
 
 class NoOpLookahead : public RouterLookahead {
   protected:
-    float get_expected_cost(int node, int target_node, const t_conn_cost_params& params, float R_upstream) const override;
+    float get_expected_cost(const RRNodeId& node, const RRNodeId& target_node, const t_conn_cost_params& params, float R_upstream) const override;
     void compute(const std::vector<t_segment_inf>& /*segment_inf*/) override {
     }
     void read(const std::string& /*file*/) override {
diff --git a/vpr/src/route/spatial_route_tree_lookup.cpp b/vpr/src/route/spatial_route_tree_lookup.cpp
index 43891de9e..20c9b8524 100644
--- a/vpr/src/route/spatial_route_tree_lookup.cpp
+++ b/vpr/src/route/spatial_route_tree_lookup.cpp
@@ -32,12 +32,10 @@ SpatialRouteTreeLookup build_route_tree_spatial_lookup(ClusterNetId net, t_rt_no
 void update_route_tree_spatial_lookup_recur(t_rt_node* rt_node, SpatialRouteTreeLookup& spatial_lookup) {
     auto& device_ctx = g_vpr_ctx.device();
 
-    auto& rr_node = device_ctx.rr_nodes[rt_node->inode];
-
-    int bin_xlow = grid_to_bin_x(rr_node.xlow(), spatial_lookup);
-    int bin_ylow = grid_to_bin_y(rr_node.ylow(), spatial_lookup);
-    int bin_xhigh = grid_to_bin_x(rr_node.xhigh(), spatial_lookup);
-    int bin_yhigh = grid_to_bin_y(rr_node.yhigh(), spatial_lookup);
+    int bin_xlow =  grid_to_bin_x(device_ctx.rr_graph.node_xlow(rt_node->inode), spatial_lookup);
+    int bin_ylow =  grid_to_bin_y(device_ctx.rr_graph.node_ylow(rt_node->inode), spatial_lookup);
+    int bin_xhigh = grid_to_bin_x(device_ctx.rr_graph.node_xhigh(rt_node->inode), spatial_lookup);
+    int bin_yhigh = grid_to_bin_y(device_ctx.rr_graph.node_yhigh(rt_node->inode), spatial_lookup);
 
     spatial_lookup[bin_xlow][bin_ylow].push_back(rt_node);
 
diff --git a/vpr/src/util/vpr_utils.cpp b/vpr/src/util/vpr_utils.cpp
index e19d17209..dfac49522 100644
--- a/vpr/src/util/vpr_utils.cpp
+++ b/vpr/src/util/vpr_utils.cpp
@@ -235,22 +235,22 @@ std::vector<std::string> block_type_class_index_to_pin_names(t_physical_tile_typ
     return pin_names;
 }
 
-std::string rr_node_arch_name(int inode) {
+std::string rr_node_arch_name(const RRNodeId& inode) {
     auto& device_ctx = g_vpr_ctx.device();
 
-    const t_rr_node& rr_node = device_ctx.rr_nodes[inode];
+    const RRGraph& rr_graph = device_ctx.rr_graph;
 
     std::string rr_node_arch_name;
-    if (rr_node.type() == OPIN || rr_node.type() == IPIN) {
+    if (rr_graph.node_type(inode) == OPIN || rr_graph.node_type(inode) == IPIN) {
         //Pin names
-        auto type = device_ctx.grid[rr_node.xlow()][rr_node.ylow()].type;
-        rr_node_arch_name += block_type_pin_index_to_name(type, rr_node.ptc_num());
-    } else if (rr_node.type() == SOURCE || rr_node.type() == SINK) {
+        auto type = device_ctx.grid[rr_graph.node_xlow(inode)][rr_graph.node_ylow(inode)].type;
+        rr_node_arch_name += block_type_pin_index_to_name(type, rr_graph.node_ptc_num(inode));
+    } else if (rr_graph.node_type(inode) == SOURCE || rr_graph.node_type(inode) == SINK) {
         //Set of pins associated with SOURCE/SINK
-        auto type = device_ctx.grid[rr_node.xlow()][rr_node.ylow()].type;
-        auto pin_names = block_type_class_index_to_pin_names(type, rr_node.ptc_num());
+        auto type = device_ctx.grid[rr_graph.node_xlow(inode)][rr_graph.node_ylow(inode)].type;
+        auto pin_names = block_type_class_index_to_pin_names(type, rr_graph.node_ptc_num(inode));
         if (pin_names.size() > 1) {
-            rr_node_arch_name += rr_node.type_string();
+            rr_node_arch_name += rr_node_typename[rr_graph.node_type(inode)];
             rr_node_arch_name += " connected to ";
             rr_node_arch_name += "{";
             rr_node_arch_name += vtr::join(pin_names, ", ");
@@ -259,9 +259,9 @@ std::string rr_node_arch_name(int inode) {
             rr_node_arch_name += pin_names[0];
         }
     } else {
-        VTR_ASSERT(rr_node.type() == CHANX || rr_node.type() == CHANY);
+        VTR_ASSERT(rr_graph.node_type(inode) == CHANX || rr_graph.node_type(inode) == CHANY);
         //Wire segment name
-        auto cost_index = rr_node.cost_index();
+        auto cost_index = rr_graph.node_cost_index(inode);
         int seg_index = device_ctx.rr_indexed_data[cost_index].seg_index;
 
         rr_node_arch_name += device_ctx.arch->Segments[seg_index].name;
diff --git a/vpr/src/util/vpr_utils.h b/vpr/src/util/vpr_utils.h
index e43cc91da..544fc61af 100644
--- a/vpr/src/util/vpr_utils.h
+++ b/vpr/src/util/vpr_utils.h
@@ -48,7 +48,7 @@ std::string block_type_pin_index_to_name(t_physical_tile_type_ptr type, int pin_
 std::vector<std::string> block_type_class_index_to_pin_names(t_physical_tile_type_ptr type, int class_index);
 
 //Returns a user-friendly architectural identifier for the specified RR node
-std::string rr_node_arch_name(int inode);
+std::string rr_node_arch_name(const RRNodeId& inode);
 
 /**************************************************************
  * Intra-Logic Block Utility Functions

From f3d9067f9b3c409c8c20edebd7bfa22c48c4b37d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 31 Jan 2020 23:25:35 -0700
Subject: [PATCH 066/645] halfway in refactoring the drawer with RRGraph

---
 vpr/src/base/vpr_types.h  |   6 +-
 vpr/src/draw/draw.cpp     | 278 +++++++++++++++++++-------------------
 vpr/src/draw/draw.h       |   7 +-
 vpr/src/draw/draw_types.h |   2 +-
 4 files changed, 141 insertions(+), 152 deletions(-)

diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h
index bf080539f..15508a4f8 100644
--- a/vpr/src/base/vpr_types.h
+++ b/vpr/src/base/vpr_types.h
@@ -1136,12 +1136,8 @@ typedef std::vector<std::vector<std::vector<std::vector<std::vector<int>>>>> t_r
  * next:    Pointer to the next traceback element in this route.           */
 struct t_trace {
     t_trace* next;
-    int index;
+    RRNodeId index;
     short iswitch;
-
-    /* Xifan Tang - RRGraph unique ids */
-    RRNodeId node_id;
-    RRSwitchId switch_id; 
 };
 
 /* Extra information about each rr_node needed only during routing (i.e.    *
diff --git a/vpr/src/draw/draw.cpp b/vpr/src/draw/draw.cpp
index 8ba6ca124..a63e9c51c 100644
--- a/vpr/src/draw/draw.cpp
+++ b/vpr/src/draw/draw.cpp
@@ -25,6 +25,7 @@
 #include "vtr_memory.h"
 #include "vtr_log.h"
 #include "vtr_color_map.h"
+#include "vtr_vector.h"
 
 #include "vpr_utils.h"
 #include "vpr_error.h"
@@ -88,20 +89,20 @@ void act_on_mouse_press(ezgl::application* app, GdkEventButton* event, double x,
 void act_on_mouse_move(ezgl::application* app, GdkEventButton* event, double x, double y);
 
 static void draw_routed_net(ClusterNetId net, ezgl::renderer* g);
-void draw_partial_route(const std::vector<int>& rr_nodes_to_draw, ezgl::renderer* g);
+void draw_partial_route(const std::vector<RRNodeId>& rr_nodes_to_draw, ezgl::renderer* g);
 static void draw_rr(ezgl::renderer* g);
-static void draw_rr_edges(int from_node, ezgl::renderer* g);
-static void draw_rr_pin(int inode, const ezgl::color& color, ezgl::renderer* g);
-static void draw_rr_chan(int inode, const ezgl::color color, ezgl::renderer* g);
-static void draw_rr_src_sink(int inode, ezgl::color color, ezgl::renderer* g);
-static void draw_pin_to_chan_edge(int pin_node, int chan_node, ezgl::renderer* g);
+static void draw_rr_edges(const RRNodeId& from_node, ezgl::renderer* g);
+static void draw_rr_pin(const RRNodeId& inode, const ezgl::color& color, ezgl::renderer* g);
+static void draw_rr_chan(const RRNodeId& inode, const ezgl::color color, ezgl::renderer* g);
+static void draw_rr_src_sink(const RRNodeId& inode, ezgl::color color, ezgl::renderer* g);
+static void draw_pin_to_chan_edge(const RRNodeId& pin_node, const RRNodeId& chan_node, ezgl::renderer* g);
 static void draw_x(float x, float y, float size, ezgl::renderer* g);
-static void draw_pin_to_pin(int opin, int ipin, ezgl::renderer* g);
+static void draw_pin_to_pin(const RRNodeId& opin, const RRNodeId& ipin, ezgl::renderer* g);
 static void draw_rr_switch(float from_x, float from_y, float to_x, float to_y, bool buffered, bool switch_configurable, ezgl::renderer* g);
-static void draw_chany_to_chany_edge(int from_node, int to_node, int to_track, short switch_type, ezgl::renderer* g);
-static void draw_chanx_to_chanx_edge(int from_node, int to_node, int to_track, short switch_type, ezgl::renderer* g);
-static void draw_chanx_to_chany_edge(int chanx_node, int chanx_track, int chany_node, int chany_track, enum e_edge_dir edge_dir, short switch_type, ezgl::renderer* g);
-static int get_track_num(int inode, const vtr::OffsetMatrix<int>& chanx_track, const vtr::OffsetMatrix<int>& chany_track);
+static void draw_chany_to_chany_edge(const RRNodeId& from_node, const RRNodeId& to_node, int to_track, short switch_type, ezgl::renderer* g);
+static void draw_chanx_to_chanx_edge(const RRNodeId& from_node, const RRNodeId& to_node, int to_track, short switch_type, ezgl::renderer* g);
+static void draw_chanx_to_chany_edge(const RRNodeId& chanx_node, int chanx_track, const RRNodeId& chany_node, int chany_track, enum e_edge_dir edge_dir, short switch_type, ezgl::renderer* g);
+static int get_track_num(const RRNodeId& inode, const vtr::OffsetMatrix<int>& chanx_track, const vtr::OffsetMatrix<int>& chany_track);
 static bool draw_if_net_highlighted(ClusterNetId inet);
 static int draw_check_rr_node_hit(float click_x, float click_y);
 
@@ -131,7 +132,7 @@ static void draw_block_pin_util();
 static float get_router_rr_cost(const t_rr_node_route_inf node_inf, e_draw_router_rr_cost draw_router_rr_cost);
 static void draw_router_rr_costs(ezgl::renderer* g);
 
-static void draw_rr_costs(ezgl::renderer* g, const std::vector<float>& rr_costs, bool lowest_cost_first = true);
+static void draw_rr_costs(ezgl::renderer* g, const vtr::vector<RRNodeId, float>& rr_costs, bool lowest_cost_first = true);
 
 void draw_main_canvas(ezgl::renderer* g);
 void initial_setup_NO_PICTURE_to_PLACEMENT(ezgl::application* app, bool is_new_window);
@@ -830,8 +831,7 @@ void alloc_draw_structs(const t_arch* arch) {
 
     /* Space is allocated for draw_rr_node but not initialized because we do *
      * not yet know information about the routing resources.				  */
-    draw_state->draw_rr_node = (t_draw_rr_node*)vtr::malloc(
-        device_ctx.rr_nodes.size() * sizeof(t_draw_rr_node));
+    draw_state->draw_rr_node.resize(device_ctx.rr_graph.nodes().size());
 
     draw_state->arch_info = arch;
 
@@ -860,7 +860,7 @@ void free_draw_structs() {
 
     if (draw_state != nullptr) {
         free(draw_state->draw_rr_node);
-        draw_state->draw_rr_node = nullptr;
+        draw_state->draw_rr_node.clear();
     }
 #else
     ;
@@ -881,11 +881,10 @@ void init_draw_coords(float width_val) {
     /* Each time routing is on screen, need to reallocate the color of each *
      * rr_node, as the number of rr_nodes may change.						*/
     if (device_ctx.rr_graph.nodes().size() != 0) {
-        draw_state->draw_rr_node = (t_draw_rr_node*)vtr::realloc(draw_state->draw_rr_node,
-                                                                 (device_ctx.rr_graph.nodes().size()) * sizeof(t_draw_rr_node));
-        for (size_t i = 0; i < device_ctx.rr_graph.nodes().size(); i++) {
-            draw_state->draw_rr_node[i].color = DEFAULT_RR_NODE_COLOR;
-            draw_state->draw_rr_node[i].node_highlighted = false;
+        draw_state->draw_rr_node.resize(device_ctx.rr_graph.nodes().size());
+        for (const RRNodeId& inode :  device_ctx.rr_graph.nodes()) {
+            draw_state->draw_rr_node[inode].color = DEFAULT_RR_NODE_COLOR;
+            draw_state->draw_rr_node[inode].node_highlighted = false;
         }
     }
     draw_coords->tile_width = width_val;
@@ -1160,8 +1159,8 @@ static void draw_routing_costs(ezgl::renderer* g) {
 
     float min_cost = std::numeric_limits<float>::infinity();
     float max_cost = -min_cost;
-    std::vector<float> rr_node_costs(device_ctx.rr_nodes.size(), 0.);
-    for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); inode++) {
+    std::vector<float> rr_node_costs(device_ctx.rr_graph.nodes().size(), 0.);
+    for (size_t inode = 0; inode < device_ctx.rr_graph.nodes().size(); inode++) {
         float cost = 0.;
         if (draw_state->show_routing_costs == DRAW_TOTAL_ROUTING_COSTS
             || draw_state->show_routing_costs == DRAW_LOG_TOTAL_ROUTING_COSTS) {
@@ -1195,7 +1194,7 @@ static void draw_routing_costs(ezgl::renderer* g) {
     }
 
     //Hide min value, draw_rr_costs() ignores NaN's
-    for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); inode++) {
+    for (size_t inode = 0; inode < device_ctx.rr_graph.nodes().size(); inode++) {
         if (rr_node_costs[inode] == min_cost) {
             rr_node_costs[inode] = NAN;
         }
@@ -1293,7 +1292,7 @@ void draw_rr(ezgl::renderer* g) {
 
     g->set_line_dash(ezgl::line_dash::none);
 
-    for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); inode++) {
+    for (size_t inode = 0; inode < device_ctx.rr_graph.nodes().size(); inode++) {
         if (!draw_state->draw_rr_node[inode].node_highlighted) {
             /* If not highlighted node, assign color based on type. */
             switch (device_ctx.rr_nodes[inode].type()) {
@@ -1346,15 +1345,15 @@ void draw_rr(ezgl::renderer* g) {
     drawroute(HIGHLIGHTED, g);
 }
 
-static void draw_rr_chan(int inode, const ezgl::color color, ezgl::renderer* g) {
+static void draw_rr_chan(const RRNodeId& inode, const ezgl::color color, ezgl::renderer* g) {
     auto& device_ctx = g_vpr_ctx.device();
 
-    t_rr_type type = device_ctx.rr_nodes[inode].type();
+    t_rr_type type = device_ctx.rr_graph.node_type(inode);
 
     VTR_ASSERT(type == CHANX || type == CHANY);
 
     ezgl::rectangle bound_box = draw_get_rr_chan_bbox(inode);
-    e_direction dir = device_ctx.rr_nodes[inode].direction();
+    e_direction dir = device_ctx.rr_graph.node_direction(inode);
 
     //We assume increasing direction, and swap if needed
     ezgl::point2d start = bound_box.bottom_left();
@@ -1380,8 +1379,8 @@ static void draw_rr_chan(int inode, const ezgl::color color, ezgl::renderer* g)
     int coord_min = -1;
     int coord_max = -1;
     if (type == CHANX) {
-        coord_min = device_ctx.rr_nodes[inode].xlow();
-        coord_max = device_ctx.rr_nodes[inode].xhigh();
+        coord_min = device_ctx.rr_graph.node_xlow(inode);
+        coord_max = device_ctx.rr_graph.node_xhigh(inode);
         if (dir == INC_DIRECTION) {
             mux_dir = RIGHT;
         } else {
@@ -1389,8 +1388,8 @@ static void draw_rr_chan(int inode, const ezgl::color color, ezgl::renderer* g)
         }
     } else {
         VTR_ASSERT(type == CHANY);
-        coord_min = device_ctx.rr_nodes[inode].ylow();
-        coord_max = device_ctx.rr_nodes[inode].yhigh();
+        coord_min = device_ctx.rr_graph.node_ylow(inode);
+        coord_max = device_ctx.rr_graph.node_yhigh(inode);
         if (dir == INC_DIRECTION) {
             mux_dir = TOP;
         } else {
@@ -1461,7 +1460,7 @@ static void draw_rr_chan(int inode, const ezgl::color color, ezgl::renderer* g)
         if (switchpoint_max == 0) {
             if (dir != BI_DIRECTION) {
                 //Draw a mux at the start of each wire, labelled with it's size (#inputs)
-                draw_mux_with_size(start, mux_dir, WIRE_DRAWING_WIDTH, device_ctx.rr_nodes[inode].fan_in(), g);
+                draw_mux_with_size(start, mux_dir, WIRE_DRAWING_WIDTH, device_ctx.rr_graph.node_in_edges(inode).size(), g);
             }
         } else {
             //Draw arrows and label with switch point
@@ -1487,30 +1486,31 @@ static void draw_rr_chan(int inode, const ezgl::color color, ezgl::renderer* g)
     g->set_color(color); //Ensure color is still set correctly if we drew any arrows/text
 }
 
-static void draw_rr_edges(int inode, ezgl::renderer* g) {
+static void draw_rr_edges(const RRNodeId& inode, ezgl::renderer* g) {
     /* Draws all the edges that the user wants shown between inode and what it *
      * connects to.  inode is assumed to be a CHANX, CHANY, or IPIN.           */
     t_draw_state* draw_state = get_draw_state_vars();
     auto& device_ctx = g_vpr_ctx.device();
 
     t_rr_type from_type, to_type;
-    int to_node, from_ptc_num, to_ptc_num;
+    RRNodeId to_node;
+    int from_ptc_num, to_ptc_num;
     short switch_type;
 
-    from_type = device_ctx.rr_nodes[inode].type();
+    from_type = device_ctx.rr_graph.node_type(inode);
 
     if ((draw_state->draw_rr_toggle == DRAW_NODES_RR)
         || (draw_state->draw_rr_toggle == DRAW_NODES_AND_SBOX_RR && from_type == OPIN)) {
         return; /* Nothing to draw. */
     }
 
-    from_ptc_num = device_ctx.rr_nodes[inode].ptc_num();
+    from_ptc_num = device_ctx.rr_graph.node_ptc_num(inode);
 
-    for (t_edge_size iedge = 0, l = device_ctx.rr_nodes[inode].num_edges(); iedge < l; iedge++) {
-        to_node = device_ctx.rr_nodes[inode].edge_sink_node(iedge);
-        to_type = device_ctx.rr_nodes[to_node].type();
-        to_ptc_num = device_ctx.rr_nodes[to_node].ptc_num();
-        bool edge_configurable = device_ctx.rr_nodes[inode].edge_is_configurable(iedge);
+    for (const RREdgeId& iedge : device_ctx.rr_graph.node_out_edges(inode)) {
+        to_node = device_ctx.rr_graph.edge_sink_node(iedge);
+        to_type = device_ctx.rr_graph.node_type(to_node);
+        to_ptc_num = device_ctx.rr_graph.node_ptc_num(to_node);
+        bool edge_configurable = device_ctx.rr_graph.edge_is_configurable(iedge);
 
         switch (from_type) {
             case OPIN:
@@ -1707,7 +1707,7 @@ static void draw_x(float x, float y, float size, ezgl::renderer* g) {
     g->draw_line({x - size, y - size}, {x + size, y + size});
 }
 
-static void draw_chanx_to_chany_edge(int chanx_node, int chanx_track, int chany_node, int chany_track, enum e_edge_dir edge_dir, short switch_type, ezgl::renderer* g) {
+static void draw_chanx_to_chany_edge(const RRNodeId& chanx_node, int chanx_track, const RRNodeId& chany_node, int chany_track, enum e_edge_dir edge_dir, short switch_type, ezgl::renderer* g) {
     t_draw_state* draw_state = get_draw_state_vars();
     t_draw_coords* draw_coords = get_draw_coords_vars();
     auto& device_ctx = g_vpr_ctx.device();
@@ -1729,16 +1729,16 @@ static void draw_chanx_to_chany_edge(int chanx_node, int chanx_track, int chany_
     y1 = chanx_bbox.bottom();
     x2 = chany_bbox.left();
 
-    chanx_xlow = device_ctx.rr_nodes[chanx_node].xlow();
-    chanx_y = device_ctx.rr_nodes[chanx_node].ylow();
-    chany_x = device_ctx.rr_nodes[chany_node].xlow();
-    chany_ylow = device_ctx.rr_nodes[chany_node].ylow();
+    chanx_xlow = device_ctx.rr_graph.node_xlow(chanx_node);
+    chanx_y = device_ctx.rr_graph.node_ylow(chanx_node);
+    chany_x = device_ctx.rr_graph.node_xlow(chany_node);
+    chany_ylow = device_ctx.rr_graph.node_ylow(chany_node);
 
     if (chanx_xlow <= chany_x) { /* Can draw connection going right */
         /* Connection not at end of the CHANX segment. */
         x1 = draw_coords->tile_x[chany_x] + draw_coords->get_tile_width();
 
-        if (device_ctx.rr_nodes[chanx_node].direction() != BI_DIRECTION) {
+        if (device_ctx.rr_graph.node_direction(chanx_node) != BI_DIRECTION) {
             if (edge_dir == FROM_X_TO_Y) {
                 if ((chanx_track % 2) == 1) { /* If dec wire, then going left */
                     x1 = draw_coords->tile_x[chany_x + 1];
@@ -1754,7 +1754,7 @@ static void draw_chanx_to_chany_edge(int chanx_node, int chanx_track, int chany_
         /* Connection not at end of the CHANY segment. */
         y2 = draw_coords->tile_y[chanx_y] + draw_coords->get_tile_width();
 
-        if (device_ctx.rr_nodes[chany_node].direction() != BI_DIRECTION) {
+        if (device_ctx.rr_graph.node_direction(chany_node) != BI_DIRECTION) {
             if (edge_dir == FROM_Y_TO_X) {
                 if ((chany_track % 2) == 1) { /* If dec wire, then going down */
                     y2 = draw_coords->tile_y[chanx_y + 1];
@@ -1777,7 +1777,7 @@ static void draw_chanx_to_chany_edge(int chanx_node, int chanx_track, int chany_
     }
 }
 
-static void draw_chanx_to_chanx_edge(int from_node, int to_node, int to_track, short switch_type, ezgl::renderer* g) {
+static void draw_chanx_to_chanx_edge(const RRNodeId& from_node, const RRNodeId& to_node, int to_track, short switch_type, ezgl::renderer* g) {
     /* Draws a connection between two x-channel segments.  Passing in the track *
      * numbers allows this routine to be used for both rr_graph and routing     *
      * drawing->                                                                 */
@@ -1800,10 +1800,10 @@ static void draw_chanx_to_chanx_edge(int from_node, int to_node, int to_track, s
     y1 = from_chan.bottom();
     y2 = to_chan.bottom();
 
-    from_xlow = device_ctx.rr_nodes[from_node].xlow();
-    from_xhigh = device_ctx.rr_nodes[from_node].xhigh();
-    to_xlow = device_ctx.rr_nodes[to_node].xlow();
-    to_xhigh = device_ctx.rr_nodes[to_node].xhigh();
+    from_xlow = device_ctx.rr_graph.node_xlow(from_node);
+    from_xhigh = device_ctx.rr_graph.node_xhigh(from_node);
+    to_xlow = device_ctx.rr_graph.node_xlow(to_node);
+    to_xhigh = device_ctx.rr_graph.node_xhigh(to_node);
     if (to_xhigh < from_xlow) { /* From right to left */
         /* UDSD Note by WMF: could never happen for INC wires, unless U-turn. For DEC
          * wires this handles well */
@@ -1821,7 +1821,7 @@ static void draw_chanx_to_chanx_edge(int from_node, int to_node, int to_track, s
      * will be drawn on top of each other for bidirectional connections.        */
 
     else {
-        if (device_ctx.rr_nodes[to_node].direction() != BI_DIRECTION) {
+        if (device_ctx.rr_graph.node_direction(to_node) != BI_DIRECTION) {
             /* must connect to to_node's wire beginning at x2 */
             if (to_track % 2 == 0) { /* INC wire starts at leftmost edge */
                 VTR_ASSERT(from_xlow < to_xlow);
@@ -1862,7 +1862,7 @@ static void draw_chanx_to_chanx_edge(int from_node, int to_node, int to_track, s
     }
 }
 
-static void draw_chany_to_chany_edge(int from_node, int to_node, int to_track, short switch_type, ezgl::renderer* g) {
+static void draw_chany_to_chany_edge(const RRNodeId& from_node, const RRNodeId& to_node, int to_track, short switch_type, ezgl::renderer* g) {
     t_draw_state* draw_state = get_draw_state_vars();
     t_draw_coords* draw_coords = get_draw_coords_vars();
     auto& device_ctx = g_vpr_ctx.device();
@@ -1882,10 +1882,10 @@ static void draw_chany_to_chany_edge(int from_node, int to_node, int to_track, s
 
     // from_x = device_ctx.rr_nodes[from_node].xlow();
     // to_x = device_ctx.rr_nodes[to_node].xlow();
-    from_ylow = device_ctx.rr_nodes[from_node].ylow();
-    from_yhigh = device_ctx.rr_nodes[from_node].yhigh();
-    to_ylow = device_ctx.rr_nodes[to_node].ylow();
-    to_yhigh = device_ctx.rr_nodes[to_node].yhigh();
+    from_ylow = device_ctx.rr_graph.node_ylow(from_node);
+    from_yhigh = device_ctx.rr_graph.node_yhigh(from_node);
+    to_ylow = device_ctx.rr_graph.node_ylow(to_node);
+    to_yhigh = device_ctx.rr_graph.node_yhigh(to_node);
 
     /* (x1, y1) point on from_node, (x2, y2) point on to_node. */
 
@@ -1906,7 +1906,7 @@ static void draw_chany_to_chany_edge(int from_node, int to_node, int to_track, s
 
     /* UDSD Modification by WMF Begin */
     else {
-        if (device_ctx.rr_nodes[to_node].direction() != BI_DIRECTION) {
+        if (device_ctx.rr_graph.node_direction(to_node) != BI_DIRECTION) {
             if (to_track % 2 == 0) { /* INC wire starts at bottom edge */
 
                 y2 = to_chan.bottom();
@@ -1950,32 +1950,32 @@ static void draw_chany_to_chany_edge(int from_node, int to_node, int to_track, s
  * wire has been clicked on by the user.
  * TODO: Fix this for global routing, currently for detailed only.
  */
-ezgl::rectangle draw_get_rr_chan_bbox(int inode) {
+ezgl::rectangle draw_get_rr_chan_bbox(const RRNodeId& inode) {
     double left = 0, right = 0, top = 0, bottom = 0;
     t_draw_coords* draw_coords = get_draw_coords_vars();
     auto& device_ctx = g_vpr_ctx.device();
 
     switch (device_ctx.rr_nodes[inode].type()) {
         case CHANX:
-            left = draw_coords->tile_x[device_ctx.rr_nodes[inode].xlow()];
-            right = draw_coords->tile_x[device_ctx.rr_nodes[inode].xhigh()]
+            left = draw_coords->tile_x[device_ctx.rr_graph.node_xlow(inode)];
+            right = draw_coords->tile_x[device_ctx.rr_graph.node_xhigh(inode)]
                     + draw_coords->get_tile_width();
-            bottom = draw_coords->tile_y[device_ctx.rr_nodes[inode].ylow()]
+            bottom = draw_coords->tile_y[device_ctx.rr_graph.node_ylow(inode)]
                      + draw_coords->get_tile_width()
-                     + (1. + device_ctx.rr_nodes[inode].ptc_num());
-            top = draw_coords->tile_y[device_ctx.rr_nodes[inode].ylow()]
+                     + (1. + device_ctx.rr_graph.node_ptc_num(inode));
+            top = draw_coords->tile_y[device_ctx.rr_graph.node_ylow(inode)]
                   + draw_coords->get_tile_width()
-                  + (1. + device_ctx.rr_nodes[inode].ptc_num());
+                  + (1. + device_ctx.rr_graph.node_ptc_num(inode));
             break;
         case CHANY:
-            left = draw_coords->tile_x[device_ctx.rr_nodes[inode].xlow()]
+            left = draw_coords->tile_x[device_ctx.rr_graph.node_xlow(inode)]
                    + draw_coords->get_tile_width()
-                   + (1. + device_ctx.rr_nodes[inode].ptc_num());
-            right = draw_coords->tile_x[device_ctx.rr_nodes[inode].xlow()]
+                   + (1. + device_ctx.rr_graph.node_ptc_num(inode));
+            right = draw_coords->tile_x[device_ctx.rr_graph.node_xlow(inode)]
                     + draw_coords->get_tile_width()
-                    + (1. + device_ctx.rr_nodes[inode].ptc_num());
-            bottom = draw_coords->tile_y[device_ctx.rr_nodes[inode].ylow()];
-            top = draw_coords->tile_y[device_ctx.rr_nodes[inode].yhigh()]
+                    + (1. + device_ctx.rr_graph.node_ptc_num(inode));
+            bottom = draw_coords->tile_y[device_ctx.rr_graph.node_ylow(inode)];
+            top = draw_coords->tile_y[device_ctx.rr_graph.node_yhigh(inode)]
                   + draw_coords->get_tile_width();
             break;
         default:
@@ -2012,7 +2012,7 @@ static void draw_rr_switch(float from_x, float from_y, float to_x, float to_y, b
     }
 }
 
-static void draw_rr_pin(int inode, const ezgl::color& color, ezgl::renderer* g) {
+static void draw_rr_pin(RRNodeId& inode, const ezgl::color& color, ezgl::renderer* g) {
     /* Draws an IPIN or OPIN rr_node.  Note that the pin can appear on more    *
      * than one side of a clb.  Also note that this routine can change the     *
      * current color to BLACK.                                                 */
@@ -2023,7 +2023,7 @@ static void draw_rr_pin(int inode, const ezgl::color& color, ezgl::renderer* g)
     char str[vtr::bufsize];
     auto& device_ctx = g_vpr_ctx.device();
 
-    int ipin = device_ctx.rr_nodes[inode].ptc_num();
+    int ipin = device_ctx.rr_graph.node_ptc_num(inode);
 
     g->set_color(color);
 
@@ -2040,26 +2040,21 @@ static void draw_rr_pin(int inode, const ezgl::color& color, ezgl::renderer* g)
 /* Returns the coordinates at which the center of this pin should be drawn. *
  * inode gives the node number, and iside gives the side of the clb or pad  *
  * the physical pin is on.                                                  */
-void draw_get_rr_pin_coords(int inode, float* xcen, float* ycen) {
+void draw_get_rr_pin_coords(const RRNodeId& inode, float* xcen, float* ycen) {
     auto& device_ctx = g_vpr_ctx.device();
-    draw_get_rr_pin_coords(&device_ctx.rr_nodes[inode], xcen, ycen);
-}
-
-void draw_get_rr_pin_coords(const t_rr_node* node, float* xcen, float* ycen) {
     t_draw_coords* draw_coords = get_draw_coords_vars();
 
     int i, j, k, ipin, pins_per_sub_tile;
     float offset, xc, yc, step;
     t_physical_tile_type_ptr type;
-    auto& device_ctx = g_vpr_ctx.device();
 
-    i = node->xlow();
-    j = node->ylow();
+    i = device_ctx.rr_graph.node_xlow(inode);
+    j = device_ctx.rr_graph.node_ylow(inode);
 
     xc = draw_coords->tile_x[i];
     yc = draw_coords->tile_y[j];
 
-    ipin = node->ptc_num();
+    ipin = device_ctx.rr_graph.node_ptc_num(inode);
     type = device_ctx.grid[i][j].type;
     pins_per_sub_tile = type->num_pins / type->capacity;
     k = ipin / pins_per_sub_tile;
@@ -2100,15 +2095,15 @@ void draw_get_rr_pin_coords(const t_rr_node* node, float* xcen, float* ycen) {
     *ycen = yc;
 }
 
-static void draw_rr_src_sink(int inode, ezgl::color color, ezgl::renderer* g) {
+static void draw_rr_src_sink(const RRNodeId& inode, ezgl::color color, ezgl::renderer* g) {
     t_draw_coords* draw_coords = get_draw_coords_vars();
 
     auto& device_ctx = g_vpr_ctx.device();
 
-    int xlow = device_ctx.rr_nodes[inode].xlow();
-    int ylow = device_ctx.rr_nodes[inode].ylow();
-    int xhigh = device_ctx.rr_nodes[inode].xhigh();
-    int yhigh = device_ctx.rr_nodes[inode].yhigh();
+    int xlow = device_ctx.rr_graph.node_xlow(inode);
+    int ylow = device_ctx.rr_graph.node_ylow(inode);
+    int xhigh = device_ctx.rr_graph.node_xhigh(inode);
+    int yhigh = device_ctx.rr_graph.node_yhigh(inode);
 
     g->set_color(color);
 
@@ -2152,9 +2147,9 @@ static void draw_routed_net(ClusterNetId net_id, ezgl::renderer* g) {
         return;                                  /* partially complete routes).            */
 
     t_trace* tptr = route_ctx.trace[net_id].head; /* SOURCE to start */
-    int inode = tptr->index;
+    RRNodeId inode = tptr->index;
 
-    std::vector<int> rr_nodes_to_draw;
+    std::vector<RRNodeId> rr_nodes_to_draw;
     rr_nodes_to_draw.push_back(inode);
     for (;;) {
         tptr = tptr->next;
@@ -2190,7 +2185,7 @@ static void draw_routed_net(ClusterNetId net_id, ezgl::renderer* g) {
 }
 
 //Draws the set of rr_nodes specified, using the colors set in draw_state
-void draw_partial_route(const std::vector<int>& rr_nodes_to_draw, ezgl::renderer* g) {
+void draw_partial_route(const std::vector<RRNodeId>& rr_nodes_to_draw, ezgl::renderer* g) {
     t_draw_state* draw_state = get_draw_state_vars();
     auto& device_ctx = g_vpr_ctx.device();
 
@@ -2218,14 +2213,15 @@ void draw_partial_route(const std::vector<int>& rr_nodes_to_draw, ezgl::renderer
     }
 
     for (size_t i = 1; i < rr_nodes_to_draw.size(); ++i) {
-        int inode = rr_nodes_to_draw[i];
-        auto rr_type = device_ctx.rr_nodes[inode].type();
+        RRNodeId inode = rr_nodes_to_draw[i];
+        auto rr_type = device_ctx.rr_graph.node_type(inode);
 
-        int prev_node = rr_nodes_to_draw[i - 1];
-        auto prev_type = device_ctx.rr_nodes[prev_node].type();
+        RRNodeId prev_node = rr_nodes_to_draw[i - 1];
+        auto prev_type = device_ctx.rr_graph.node_type(prev_node);
 
-        auto iedge = find_edge(prev_node, inode);
-        auto switch_type = device_ctx.rr_nodes[prev_node].edge_switch(iedge);
+        std::vector<RREdgeId> edges = device_ctx.rr_graph.find_edges(prev_node, inode);
+        VTR_ASSERT(1 == edges.size());
+        auto switch_type = device_ctx.rr_graph.edge_switch(edges[0]);
 
         switch (rr_type) {
             case OPIN: {
@@ -2277,7 +2273,7 @@ void draw_partial_route(const std::vector<int>& rr_nodes_to_draw, ezgl::renderer
             }
             case CHANY: {
                 if (draw_state->draw_route_type == GLOBAL)
-                    chany_track[device_ctx.rr_nodes[inode].xlow()][device_ctx.rr_nodes[inode].ylow()]++;
+                    chany_track[device_ctx.rr_graph.node_xlow(inode)][device_ctx.rr_graph.node_ylow(inode)]++;
 
                 int itrack = get_track_num(inode, chanx_track, chany_track);
                 draw_rr_chan(inode, draw_state->draw_rr_node[inode].color, g);
@@ -2316,7 +2312,7 @@ void draw_partial_route(const std::vector<int>& rr_nodes_to_draw, ezgl::renderer
     }
 }
 
-static int get_track_num(int inode, const vtr::OffsetMatrix<int>& chanx_track, const vtr::OffsetMatrix<int>& chany_track) {
+static int get_track_num(const RRNodeId& inode, const vtr::OffsetMatrix<int>& chanx_track, const vtr::OffsetMatrix<int>& chany_track) {
     /* Returns the track number of this routing resource node.   */
 
     int i, j;
@@ -2324,13 +2320,13 @@ static int get_track_num(int inode, const vtr::OffsetMatrix<int>& chanx_track, c
     auto& device_ctx = g_vpr_ctx.device();
 
     if (get_draw_state_vars()->draw_route_type == DETAILED)
-        return (device_ctx.rr_nodes[inode].ptc_num());
+        return (device_ctx.rr_graph.node_ptc_num(inode));
 
     /* GLOBAL route stuff below. */
 
-    rr_type = device_ctx.rr_nodes[inode].type();
-    i = device_ctx.rr_nodes[inode].xlow(); /* NB: Global rr graphs must have only unit */
-    j = device_ctx.rr_nodes[inode].ylow(); /* length channel segments.                 */
+    rr_type = device_ctx.rr_graph.node_type(inode);
+    i = device_ctx.rr_graph.node_xlow(inode); /* NB: Global rr graphs must have only unit */
+    j = device_ctx.rr_graph.node_ylow(inode); /* length channel segments.                 */
 
     switch (rr_type) {
         case CHANX:
@@ -2341,7 +2337,7 @@ static int get_track_num(int inode, const vtr::OffsetMatrix<int>& chanx_track, c
 
         default:
             vpr_throw(VPR_ERROR_OTHER, __FILE__, __LINE__,
-                      "in get_track_num: Unexpected node type %d for node %d.\n", rr_type, inode);
+                      "in get_track_num: Unexpected node type %d for node %ld.\n", rr_type, size_t(inode));
             return OPEN;
     }
 }
@@ -2363,7 +2359,7 @@ static bool draw_if_net_highlighted(ClusterNetId inet) {
 /* If an rr_node has been clicked on, it will be highlighted in MAGENTA.
  * If so, and toggle nets is selected, highlight the whole net in that colour.
  */
-void highlight_nets(char* message, int hit_node) {
+void highlight_nets(char* message, const RRNodeId& hit_node) {
     t_trace* tptr;
     auto& cluster_ctx = g_vpr_ctx.clustering();
     auto& route_ctx = g_vpr_ctx.routing();
@@ -2415,7 +2411,7 @@ void draw_highlight_fan_in_fan_out(const std::set<int>& nodes) {
         }
 
         /* Highlight the nodes that can fanin to this node in blue. */
-        for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); inode++) {
+        for (size_t inode = 0; inode < device_ctx.rr_graph.nodes().size(); inode++) {
             for (t_edge_size iedge = 0, l = device_ctx.rr_nodes[inode].num_edges(); iedge < l; iedge++) {
                 int fanout_node = device_ctx.rr_nodes[inode].edge_sink_node(iedge);
                 if (fanout_node == node) {
@@ -2447,16 +2443,16 @@ static int draw_check_rr_node_hit(float click_x, float click_y) {
     t_draw_coords* draw_coords = get_draw_coords_vars();
     auto& device_ctx = g_vpr_ctx.device();
 
-    for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); inode++) {
-        switch (device_ctx.rr_nodes[inode].type()) {
+    for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) {
+        switch (device_ctx.rr_graph.node_type(inode)) {
             case IPIN:
             case OPIN: {
-                int i = device_ctx.rr_nodes[inode].xlow();
-                int j = device_ctx.rr_nodes[inode].ylow();
+                int i = device_ctx.rr_graph.node_xlow(inode);
+                int j = device_ctx.rr_graph.node_ylow(inode);
                 t_physical_tile_type_ptr type = device_ctx.grid[i][j].type;
                 int width_offset = device_ctx.grid[i][j].width_offset;
                 int height_offset = device_ctx.grid[i][j].height_offset;
-                int ipin = device_ctx.rr_nodes[inode].ptc_num();
+                int ipin = device_ctx.rr_graph.node_ptc_num(inode);
                 float xcen, ycen;
                 int iside;
                 for (iside = 0; iside < 4; iside++) {
@@ -2727,7 +2723,7 @@ void deselect_all() {
     for (auto net_id : cluster_ctx.clb_nlist.nets())
         draw_state->net_color[net_id] = ezgl::BLACK;
 
-    for (size_t i = 0; i < device_ctx.rr_nodes.size(); i++) {
+    for (size_t i = 0; i < device_ctx.rr_graph.nodes().size(); i++) {
         draw_state->draw_rr_node[i].color = DEFAULT_RR_NODE_COLOR;
         draw_state->draw_rr_node[i].node_highlighted = false;
     }
@@ -2800,7 +2796,7 @@ void draw_triangle_along_line(ezgl::renderer* g, float xend, float yend, float x
     g->fill_poly(poly);
 }
 
-static void draw_pin_to_chan_edge(int pin_node, int chan_node, ezgl::renderer* g) {
+static void draw_pin_to_chan_edge(const RRNodeId& pin_node, const RRNodeId& chan_node, ezgl::renderer* g) {
     /* This routine draws an edge from the pin_node to the chan_node (CHANX or   *
      * CHANY).  The connection is made to the nearest end of the track instead   *
      * of perpendicular to the track to symbolize a single-drive connection.     */
@@ -2810,19 +2806,18 @@ static void draw_pin_to_chan_edge(int pin_node, int chan_node, ezgl::renderer* g
     t_draw_coords* draw_coords = get_draw_coords_vars();
     auto& device_ctx = g_vpr_ctx.device();
 
-    const t_rr_node& pin_rr = device_ctx.rr_nodes[pin_node];
-    const t_rr_node& chan_rr = device_ctx.rr_nodes[chan_node];
+    const RRGraph& rr_graph = device_ctx.rr_graph;
 
-    const t_grid_tile& grid_tile = device_ctx.grid[pin_rr.xlow()][pin_rr.ylow()];
+    const t_grid_tile& grid_tile = device_ctx.grid[rr_graph.node_xlow(pin_node)][rr_graph.node_ylow(pin_node)];
     t_physical_tile_type_ptr grid_type = grid_tile.type;
-    VTR_ASSERT_MSG(grid_type->pinloc[grid_tile.width_offset][grid_tile.height_offset][pin_rr.side()][pin_rr.pin_num()],
+    VTR_ASSERT_MSG(grid_type->pinloc[grid_tile.width_offset][grid_tile.height_offset][rr_graph.node_side(pin_node)][rr_graph.node_pin_num(pin_node)],
                    "Pin coordinates should match block type pin locations");
 
     float draw_pin_offset;
-    if (pin_rr.side() == TOP || pin_rr.side() == RIGHT) {
+    if (rr_graph.node_side(pin_node) == TOP || rr_graph.node_side(pin_node) == RIGHT) {
         draw_pin_offset = draw_coords->pin_size;
     } else {
-        VTR_ASSERT(pin_rr.side() == BOTTOM || pin_rr.side() == LEFT);
+        VTR_ASSERT(rr_graph.node_side(pin_node) == BOTTOM || rr_graph.node_side(pin_node) == LEFT);
         draw_pin_offset = -draw_coords->pin_size;
     }
 
@@ -2837,10 +2832,10 @@ static void draw_pin_to_chan_edge(int pin_node, int chan_node, ezgl::renderer* g
             y1 += draw_pin_offset;
             y2 = chan_bbox.bottom();
             x2 = x1;
-            if (is_opin(pin_rr.pin_num(), grid_type)) {
-                if (chan_rr.direction() == INC_DIRECTION) {
+            if (is_opin(rr_graph.node_pin_num(pin_node), grid_type)) {
+                if (rr_graph.node_direction(chan_node) == INC_DIRECTION) {
                     x2 = chan_bbox.left();
-                } else if (chan_rr.direction() == DEC_DIRECTION) {
+                } else if (rr_graph.node_direction(chan_node) == DEC_DIRECTION) {
                     x2 = chan_bbox.right();
                 }
             }
@@ -2850,10 +2845,10 @@ static void draw_pin_to_chan_edge(int pin_node, int chan_node, ezgl::renderer* g
             x1 += draw_pin_offset;
             x2 = chan_bbox.left();
             y2 = y1;
-            if (is_opin(pin_rr.pin_num(), grid_type)) {
-                if (chan_rr.direction() == INC_DIRECTION) {
+            if (is_opin(rr_graph.node_pin_num(pin_node), grid_type)) {
+                if (rr_graph.node_direction(chan_node) == INC_DIRECTION) {
                     y2 = chan_bbox.bottom();
-                } else if (chan_rr.direction() == DEC_DIRECTION) {
+                } else if (rr_graph.node_direction(chan_node) == DEC_DIRECTION) {
                     y2 = chan_bbox.top();
                 }
             }
@@ -2861,13 +2856,13 @@ static void draw_pin_to_chan_edge(int pin_node, int chan_node, ezgl::renderer* g
         }
         default: {
             vpr_throw(VPR_ERROR_OTHER, __FILE__, __LINE__,
-                      "in draw_pin_to_chan_edge: Invalid channel node %d.\n", chan_node);
+                      "in draw_pin_to_chan_edge: Invalid channel node %ld.\n", size_t(chan_node));
         }
     }
     g->draw_line({x1, y1}, {x2, y2});
 
     //don't draw the ex, or triangle unless zoomed in really far
-    if (chan_rr.direction() == BI_DIRECTION || !is_opin(pin_rr.pin_num(), grid_type)) {
+    if (rr_graph.node_direction(chan_node) == BI_DIRECTION || !is_opin(rr_graph.node_pin_num(pin_node), grid_type)) {
         draw_x(x2, y2, 0.7 * draw_coords->pin_size, g);
     } else {
         float xend = x2 + (x1 - x2) / 10.;
@@ -2876,11 +2871,11 @@ static void draw_pin_to_chan_edge(int pin_node, int chan_node, ezgl::renderer* g
     }
 }
 
-static void draw_pin_to_pin(int opin_node, int ipin_node, ezgl::renderer* g) {
+static void draw_pin_to_pin(const RRNodeId& opin_node, const RRNodeId& ipin_node, ezgl::renderer* g) {
     /* This routine draws an edge from the opin rr node to the ipin rr node */
     auto& device_ctx = g_vpr_ctx.device();
-    VTR_ASSERT(device_ctx.rr_nodes[opin_node].type() == OPIN);
-    VTR_ASSERT(device_ctx.rr_nodes[ipin_node].type() == IPIN);
+    VTR_ASSERT(device_ctx.rr_graph.node_type(opin_node) == OPIN);
+    VTR_ASSERT(device_ctx.rr_graph.node_type(ipin_node) == IPIN);
 
     float x1 = 0, y1 = 0;
     draw_get_rr_pin_coords(opin_node, &x1, &y1);
@@ -3499,15 +3494,15 @@ static void draw_router_rr_costs(ezgl::renderer* g) {
     auto& device_ctx = g_vpr_ctx.device();
     auto& routing_ctx = g_vpr_ctx.routing();
 
-    std::vector<float> rr_costs(device_ctx.rr_nodes.size());
+    vtr::vector<RRNodeId, float> rr_costs(device_ctx.rr_graph.nodes().size());
 
-    for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); ++inode) {
+    for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) {
         float cost = get_router_rr_cost(routing_ctx.rr_node_route_inf[inode], draw_state->show_router_rr_cost);
         rr_costs[inode] = cost;
     }
 
     bool all_nan = true;
-    for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); ++inode) {
+    for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) {
         if (std::isinf(rr_costs[inode])) {
             rr_costs[inode] = NAN;
         } else {
@@ -3528,7 +3523,7 @@ static void draw_router_rr_costs(ezgl::renderer* g) {
     }
 }
 
-static void draw_rr_costs(ezgl::renderer* g, const std::vector<float>& rr_costs, bool lowest_cost_first) {
+static void draw_rr_costs(ezgl::renderer* g, const vtr::vector<RRNodeId, float>& rr_costs, bool lowest_cost_first) {
     t_draw_state* draw_state = get_draw_state_vars();
 
     /* Draws routing costs */
@@ -3537,11 +3532,11 @@ static void draw_rr_costs(ezgl::renderer* g, const std::vector<float>& rr_costs,
 
     g->set_line_width(0);
 
-    VTR_ASSERT(rr_costs.size() == device_ctx.rr_nodes.size());
+    VTR_ASSERT(rr_costs.size() == device_ctx.rr_graph.nodes().size());
 
     float min_cost = std::numeric_limits<float>::infinity();
     float max_cost = -min_cost;
-    for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); inode++) {
+    for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) {
         if (std::isnan(rr_costs[inode])) continue;
 
         min_cost = std::min(min_cost, rr_costs[inode]);
@@ -3553,9 +3548,8 @@ static void draw_rr_costs(ezgl::renderer* g, const std::vector<float>& rr_costs,
 
     //Draw the nodes in ascending order of value, this ensures high valued nodes
     //are not overdrawn by lower value ones (e.g-> when zoomed-out far)
-    std::vector<int> nodes(device_ctx.rr_nodes.size());
-    std::iota(nodes.begin(), nodes.end(), 0);
-    auto cmp_ascending_cost = [&](int lhs_node, int rhs_node) {
+    std::vector<RRNodeId> nodes = device_ctx.rr_graph.nodes();
+    auto cmp_ascending_cost = [&](const RRNodeId& lhs_node, const RRNodeId& rhs_node) {
         if (lowest_cost_first) {
             return rr_costs[lhs_node] > rr_costs[rhs_node];
         }
@@ -3563,13 +3557,13 @@ static void draw_rr_costs(ezgl::renderer* g, const std::vector<float>& rr_costs,
     };
     std::sort(nodes.begin(), nodes.end(), cmp_ascending_cost);
 
-    for (int inode : nodes) {
+    for (const RRNodeId& inode : nodes) {
         float cost = rr_costs[inode];
         if (std::isnan(cost)) continue;
 
         ezgl::color color = to_ezgl_color(cmap->color(cost));
 
-        switch (device_ctx.rr_nodes[inode].type()) {
+        switch (device_ctx.rr_graph.node_type(inode)) {
             case CHANX: //fallthrough
             case CHANY:
                 draw_rr_chan(inode, color, g);
diff --git a/vpr/src/draw/draw.h b/vpr/src/draw/draw.h
index acc9d2145..98c908ba4 100644
--- a/vpr/src/draw/draw.h
+++ b/vpr/src/draw/draw.h
@@ -31,8 +31,7 @@ void free_draw_structs();
 
 #ifndef NO_GRAPHICS
 
-void draw_get_rr_pin_coords(int inode, float* xcen, float* ycen);
-void draw_get_rr_pin_coords(const t_rr_node* node, float* xcen, float* ycen);
+void draw_get_rr_pin_coords(const RRNodeId& inode, float* xcen, float* ycen);
 
 void draw_triangle_along_line(ezgl::renderer* g, ezgl::point2d start, ezgl::point2d end, float relative_position = 1., float arrow_size = DEFAULT_ARROW_SIZE);
 void draw_triangle_along_line(ezgl::renderer* g, ezgl::point2d loc, ezgl::point2d start, ezgl::point2d end, float arrow_size = DEFAULT_ARROW_SIZE);
@@ -58,9 +57,9 @@ ezgl::color to_ezgl_color(vtr::Color<float> color);
 void draw_screen();
 
 // search bar related functions
-ezgl::rectangle draw_get_rr_chan_bbox(int inode);
+ezgl::rectangle draw_get_rr_chan_bbox(const RRNodeId& inode);
 void draw_highlight_blocks_color(t_logical_block_type_ptr type, ClusterBlockId blk_id);
-void highlight_nets(char* message, int hit_node);
+void highlight_nets(char* message, const RRNodeId& hit_node);
 void draw_highlight_fan_in_fan_out(const std::set<int>& nodes);
 std::set<int> draw_expand_non_configurable_rr_nodes(int hit_node);
 void deselect_all();
diff --git a/vpr/src/draw/draw_types.h b/vpr/src/draw/draw_types.h
index 1ef320afa..1400221f0 100644
--- a/vpr/src/draw/draw_types.h
+++ b/vpr/src/draw/draw_types.h
@@ -172,7 +172,7 @@ struct t_draw_state {
     e_route_type draw_route_type = GLOBAL;
     char default_message[vtr::bufsize];
     vtr::vector<ClusterNetId, ezgl::color> net_color;
-    t_draw_rr_node* draw_rr_node = nullptr;
+    vtr::vector<RRNodeId, t_draw_rr_node> draw_rr_node;
     std::shared_ptr<const SetupTimingInfo> setup_timing_info;
     const t_arch* arch_info = nullptr;
     std::unique_ptr<const vtr::ColorMap> color_map = nullptr;

From cb98456d7e63a04627aa8624ef765b44a5152c51 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 1 Feb 2020 10:12:11 -0700
Subject: [PATCH 067/645] finish adaption for stats.cpp

---
 vpr/src/base/read_route.cpp | 22 ++++++++++++++--------
 vpr/src/base/stats.cpp      | 27 +++++++++++++--------------
 2 files changed, 27 insertions(+), 22 deletions(-)

diff --git a/vpr/src/base/read_route.cpp b/vpr/src/base/read_route.cpp
index 9ec4069fe..00237603b 100644
--- a/vpr/src/base/read_route.cpp
+++ b/vpr/src/base/read_route.cpp
@@ -231,7 +231,7 @@ static void process_nodes(std::ifstream& fp, ClusterNetId inet, const char* file
         } else if (tokens[0] == "Node:") {
             /*An actual line, go through each node and add it to the route tree*/
             inode = atoi(tokens[1].c_str());
-            auto& node = device_ctx.rr_nodes[inode];
+            const RRNodeId& node = RRNodeId(inode);
 
             /*First node needs to be source. It is isolated to correctly set heap head.*/
             if (node_count == 0 && tokens[2] != "SOURCE") {
@@ -240,7 +240,7 @@ static void process_nodes(std::ifstream& fp, ClusterNetId inet, const char* file
             }
 
             /*Check node types if match rr graph*/
-            if (tokens[2] != node.type_string()) {
+            if (tokens[2] != rr_node_typename[device_ctx.rr_graph.node_type(node)]) {
                 vpr_throw(VPR_ERROR_ROUTE, filename, lineno,
                           "Node %d has a type that does not match the RR graph", inode);
             }
@@ -249,13 +249,19 @@ static void process_nodes(std::ifstream& fp, ClusterNetId inet, const char* file
 
             if (tokens[4] == "to") {
                 format_coordinates(x2, y2, tokens[5], inet, filename, lineno);
-                if (node.xlow() != x || node.xhigh() != x2 || node.yhigh() != y2 || node.ylow() != y) {
+                if (device_ctx.rr_graph.node_xlow(node) != x 
+                 || device_ctx.rr_graph.node_xhigh(node) != x2 
+                 || device_ctx.rr_graph.node_yhigh(node) != y2 
+                 || device_ctx.rr_graph.node_ylow(node) != y) {
                     vpr_throw(VPR_ERROR_ROUTE, filename, lineno,
                               "The coordinates of node %d does not match the rr graph", inode);
                 }
                 offset = 2;
             } else {
-                if (node.xlow() != x || node.xhigh() != x || node.yhigh() != y || node.ylow() != y) {
+                if (device_ctx.rr_graph.node_xlow(node) != x 
+                 || device_ctx.rr_graph.node_xhigh(node) != x 
+                 || device_ctx.rr_graph.node_yhigh(node) != y 
+                 || device_ctx.rr_graph.node_ylow(node) != y) {
                     vpr_throw(VPR_ERROR_ROUTE, filename, lineno,
                               "The coordinates of node %d does not match the rr graph", inode);
                 }
@@ -276,7 +282,7 @@ static void process_nodes(std::ifstream& fp, ClusterNetId inet, const char* file
             }
 
             ptc = atoi(tokens[5 + offset].c_str());
-            if (node.ptc_num() != ptc) {
+            if (device_ctx.rr_graph.node_ptc_num(node) != ptc) {
                 vpr_throw(VPR_ERROR_ROUTE, filename, lineno,
                           "The ptc num of node %d does not match the rr graph", inode);
             }
@@ -285,7 +291,7 @@ static void process_nodes(std::ifstream& fp, ClusterNetId inet, const char* file
             if (tokens[6 + offset] != "Switch:") {
                 /*This is an opin or ipin, process its pin nums*/
                 if (!is_io_type(device_ctx.grid[x][y].type) && (tokens[2] == "IPIN" || tokens[2] == "OPIN")) {
-                    int pin_num = device_ctx.rr_nodes[inode].ptc_num();
+                    int pin_num = device_ctx.rr_graph.node_ptc_num(node);
                     int height_offset = device_ctx.grid[x][y].height_offset;
                     ClusterBlockId iblock = place_ctx.grid_blocks[x][y - height_offset].blocks[0];
                     t_pb_graph_pin* pb_pin = get_pb_graph_node_pin_from_block_pin(iblock, pin_num);
@@ -312,7 +318,7 @@ static void process_nodes(std::ifstream& fp, ClusterNetId inet, const char* file
             /* Allocate and load correct values to trace.head*/
             if (node_count == 0) {
                 route_ctx.trace[inet].head = alloc_trace_data();
-                route_ctx.trace[inet].head->index = inode;
+                route_ctx.trace[inet].head->index = node;
                 route_ctx.trace[inet].head->iswitch = switch_id;
                 route_ctx.trace[inet].head->next = nullptr;
                 tptr = route_ctx.trace[inet].head;
@@ -320,7 +326,7 @@ static void process_nodes(std::ifstream& fp, ClusterNetId inet, const char* file
             } else {
                 tptr->next = alloc_trace_data();
                 tptr = tptr->next;
-                tptr->index = inode;
+                tptr->index = node;
                 tptr->iswitch = switch_id;
                 tptr->next = nullptr;
                 node_count++;
diff --git a/vpr/src/base/stats.cpp b/vpr/src/base/stats.cpp
index 846185ee2..9f36081e4 100644
--- a/vpr/src/base/stats.cpp
+++ b/vpr/src/base/stats.cpp
@@ -215,7 +215,7 @@ static void get_channel_occupancy_stats() {
 /* Loads the two arrays passed in with the total occupancy at each of the  *
  * channel segments in the FPGA.                                           */
 static void load_channel_occupancies(vtr::Matrix<int>& chanx_occ, vtr::Matrix<int>& chany_occ) {
-    int i, j, inode;
+    int i, j;
     t_trace* tptr;
     t_rr_type rr_type;
 
@@ -235,8 +235,8 @@ static void load_channel_occupancies(vtr::Matrix<int>& chanx_occ, vtr::Matrix<in
 
         tptr = route_ctx.trace[net_id].head;
         while (tptr != nullptr) {
-            inode = tptr->index;
-            rr_type = device_ctx.rr_nodes[inode].type();
+            const RRNodeId& inode = tptr->index;
+            rr_type = device_ctx.rr_graph.node_type(inode);
 
             if (rr_type == SINK) {
                 tptr = tptr->next; /* Skip next segment. */
@@ -245,14 +245,14 @@ static void load_channel_occupancies(vtr::Matrix<int>& chanx_occ, vtr::Matrix<in
             }
 
             else if (rr_type == CHANX) {
-                j = device_ctx.rr_nodes[inode].ylow();
-                for (i = device_ctx.rr_nodes[inode].xlow(); i <= device_ctx.rr_nodes[inode].xhigh(); i++)
+                j = device_ctx.rr_graph.node_ylow(inode);
+                for (i = device_ctx.rr_graph.node_xlow(inode); i <= device_ctx.rr_graph.node_xhigh(inode); i++)
                     chanx_occ[i][j]++;
             }
 
             else if (rr_type == CHANY) {
-                i = device_ctx.rr_nodes[inode].xlow();
-                for (j = device_ctx.rr_nodes[inode].ylow(); j <= device_ctx.rr_nodes[inode].yhigh(); j++)
+                i = device_ctx.rr_graph.node_xlow(inode);
+                for (j = device_ctx.rr_graph.node_ylow(inode); j <= device_ctx.rr_graph.node_yhigh(inode); j++)
                     chany_occ[i][j]++;
             }
 
@@ -268,7 +268,6 @@ void get_num_bends_and_length(ClusterNetId inet, int* bends_ptr, int* len_ptr, i
     auto& device_ctx = g_vpr_ctx.device();
 
     t_trace *tptr, *prevptr;
-    int inode;
     t_rr_type curr_type, prev_type;
     int bends, length, segments;
 
@@ -281,27 +280,27 @@ void get_num_bends_and_length(ClusterNetId inet, int* bends_ptr, int* len_ptr, i
         VPR_FATAL_ERROR(VPR_ERROR_OTHER,
                         "in get_num_bends_and_length: net #%lu has no traceback.\n", size_t(inet));
     }
-    inode = prevptr->index;
-    prev_type = device_ctx.rr_nodes[inode].type();
+    RRNodeId inode = prevptr->index;
+    prev_type = device_ctx.rr_graph.node_type(inode);
 
     tptr = prevptr->next;
 
     while (tptr != nullptr) {
         inode = tptr->index;
-        curr_type = device_ctx.rr_nodes[inode].type();
+        curr_type = device_ctx.rr_graph.node_type(inode);
 
         if (curr_type == SINK) { /* Starting a new segment */
             tptr = tptr->next;   /* Link to existing path - don't add to len. */
             if (tptr == nullptr)
                 break;
 
-            curr_type = device_ctx.rr_nodes[tptr->index].type();
+            curr_type = device_ctx.rr_graph.node_type(tptr->index);
         }
 
         else if (curr_type == CHANX || curr_type == CHANY) {
             segments++;
-            length += 1 + device_ctx.rr_nodes[inode].xhigh() - device_ctx.rr_nodes[inode].xlow()
-                      + device_ctx.rr_nodes[inode].yhigh() - device_ctx.rr_nodes[inode].ylow();
+            length += 1 + device_ctx.rr_graph.node_xhigh(inode) - device_ctx.rr_graph.node_xlow(inode)
+                      + device_ctx.rr_graph.node_yhigh(inode) - device_ctx.rr_graph.node_ylow(inode);
 
             if (curr_type != prev_type && (prev_type == CHANX || prev_type == CHANY))
                 bends++;

From 653d7d5aa1dd58205eea8d96a70a69a6c565ffbb Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 1 Feb 2020 11:49:39 -0700
Subject: [PATCH 068/645] placer compilation errors elimated for RRGraph
 deployment

---
 vpr/src/base/vpr_context.h                |   1 +
 vpr/src/device/rr_graph_obj_util.cpp      |  65 +++++++++
 vpr/src/device/rr_graph_obj_util.h        |  21 +++
 vpr/src/device/rr_graph_types.h           |   3 +
 vpr/src/device/rr_graph_util.cpp          |  30 -----
 vpr/src/device/rr_graph_util.h            |  15 ---
 vpr/src/device/write_xml_rr_graph_obj.cpp |   2 -
 vpr/src/draw/draw.cpp                     | 153 +++++++++++-----------
 vpr/src/draw/draw.h                       |   4 +-
 vpr/src/draw/search_bar.cpp               |  18 +--
 vpr/src/draw/search_bar.h                 |   4 +-
 vpr/src/place/timing_place_lookup.cpp     |  42 +++---
 vpr/src/route/route_common.cpp            |  14 +-
 vpr/src/route/route_export.h              |   4 +-
 vpr/src/route/rr_graph.cpp                |  44 +++----
 vpr/src/route/rr_graph.h                  |   2 +-
 16 files changed, 230 insertions(+), 192 deletions(-)
 create mode 100644 vpr/src/device/rr_graph_obj_util.cpp
 create mode 100644 vpr/src/device/rr_graph_obj_util.h
 delete mode 100644 vpr/src/device/rr_graph_util.cpp
 delete mode 100644 vpr/src/device/rr_graph_util.h

diff --git a/vpr/src/base/vpr_context.h b/vpr/src/base/vpr_context.h
index 7f4ba43dc..9a59e89c8 100644
--- a/vpr/src/base/vpr_context.h
+++ b/vpr/src/base/vpr_context.h
@@ -286,6 +286,7 @@ struct RoutingContext : public Context {
     vtr::vector<ClusterNetId, t_traceback> trace;
     vtr::vector<ClusterNetId, std::unordered_set<int>> trace_nodes;
 
+    /* Xifan Tang: this should adopt RRNodeId as well */
     vtr::vector<ClusterNetId, std::vector<int>> net_rr_terminals; /* [0..num_nets-1][0..num_pins-1] */
 
     vtr::vector<ClusterBlockId, std::vector<int>> rr_blk_source; /* [0..num_blocks-1][0..num_class-1] */
diff --git a/vpr/src/device/rr_graph_obj_util.cpp b/vpr/src/device/rr_graph_obj_util.cpp
new file mode 100644
index 000000000..92d27e083
--- /dev/null
+++ b/vpr/src/device/rr_graph_obj_util.cpp
@@ -0,0 +1,65 @@
+/****************************************************************************
+ * This file include most-utilized functions that manipulate on the
+ * RRGraph object
+ ***************************************************************************/
+#include "rr_graph_obj.h"
+#include "rr_graph_obj_util.h"
+
+/****************************************************************************
+ * Find the switches interconnecting two nodes
+ * Return a vector of switch ids
+ ***************************************************************************/
+std::vector<RRSwitchId> find_rr_graph_switches(const RRGraph& rr_graph,
+                                               const RRNodeId& from_node,
+                                               const RRNodeId& to_node) {
+    std::vector<RRSwitchId> switches;
+    std::vector<RREdgeId> edges = rr_graph.find_edges(from_node, to_node);
+    if (true == edges.empty()) {
+        /* edge is open, we return an empty vector of switches */
+        return switches;
+    }
+
+    /* Reach here, edge list is not empty, find switch id one by one
+     * and update the switch list
+     */
+    for (auto edge : edges) {
+        switches.push_back(rr_graph.edge_switch(edge));
+    }
+
+    return switches;
+}
+
+/*********************************************************************
+ * Like the RRGraph.find_node() but returns all matching nodes,
+ * rather than just the first. This is particularly useful for getting all instances
+ * of a specific IPIN/OPIN at a specific gird tile (x,y) location.
+ **********************************************************************/
+std::vector<RRNodeId> find_rr_graph_nodes(const RRGraph& rr_graph,
+                                          const int& x,
+                                          const int& y,
+                                          const t_rr_type& rr_type,
+                                          const int& ptc) {
+    std::vector<RRNodeId> indices;
+
+    if (rr_type == IPIN || rr_type == OPIN) {
+        //For pins we need to look at all the sides of the current grid tile
+
+        for (e_side side : SIDES) {
+            RRNodeId rr_node_index = rr_graph.find_node(x, y, rr_type, ptc, side);
+
+            if (rr_node_index != RRNodeId::INVALID()) {
+                indices.push_back(rr_node_index);
+            }
+        }
+    } else {
+        //Sides do not effect non-pins so there should only be one per ptc
+        RRNodeId rr_node_index = rr_graph.find_node(x, y, rr_type, ptc);
+
+        if (rr_node_index != RRNodeId::INVALID()) {
+            indices.push_back(rr_node_index);
+        }
+    }
+
+    return indices;
+}
+
diff --git a/vpr/src/device/rr_graph_obj_util.h b/vpr/src/device/rr_graph_obj_util.h
new file mode 100644
index 000000000..9a089d68c
--- /dev/null
+++ b/vpr/src/device/rr_graph_obj_util.h
@@ -0,0 +1,21 @@
+#ifndef RR_GRAPH_OBJ_UTIL_H
+#define RR_GRAPH_OBJ_UTIL_H
+
+/* Include header files which include data structures used by
+ * the function declaration
+ */
+#include <vector>
+#include "rr_graph_obj.h"
+
+/* Get node-to-node switches in a RRGraph */
+std::vector<RRSwitchId> find_rr_graph_switches(const RRGraph& rr_graph,
+                                               const RRNodeId& from_node,
+                                               const RRNodeId& to_node);
+
+std::vector<RRNodeId> find_rr_graph_nodes(const RRGraph& rr_graph,
+                                          const int& x,
+                                          const int& y,
+                                          const t_rr_type& rr_type,
+                                          const int& ptc);
+
+#endif
diff --git a/vpr/src/device/rr_graph_types.h b/vpr/src/device/rr_graph_types.h
index 51cf3a0dd..a4df4cd7f 100644
--- a/vpr/src/device/rr_graph_types.h
+++ b/vpr/src/device/rr_graph_types.h
@@ -19,6 +19,9 @@ enum e_direction : unsigned char {
 
 constexpr std::array<const char*, NUM_DIRECTIONS> DIRECTION_STRING = {{"INC_DIRECTION", "DEC_DIRECTION", "BI_DIRECTION", "NO_DIRECTION"}};
 
+/* Xifan Tang - string used in describe_rr_node() and write_xml_rr_graph_obj() */
+constexpr std::array<const char*, NUM_DIRECTIONS> DIRECTION_STRING_WRITE_XML = {{"INC_DIR", "DEC_DIR", "BI_DIR", "NO_DIR"}};
+
 /* Type of a routing resource node.  x-directed channel segment,   *
  * y-directed channel segment, input pin to a clb to pad, output   *
  * from a clb or pad (i.e. output pin of a net) and:               *
diff --git a/vpr/src/device/rr_graph_util.cpp b/vpr/src/device/rr_graph_util.cpp
deleted file mode 100644
index 495a66581..000000000
--- a/vpr/src/device/rr_graph_util.cpp
+++ /dev/null
@@ -1,30 +0,0 @@
-/****************************************************************************
- * This file include most-utilized functions that manipulate on the
- * RRGraph object
- ***************************************************************************/
-#include "rr_graph_util.h"
-#include "rr_graph_obj.h"
-
-/****************************************************************************
- * Find the switches interconnecting two nodes
- * Return a vector of switch ids
- ***************************************************************************/
-std::vector<RRSwitchId> find_rr_graph_switches(const RRGraph& rr_graph,
-                                               const RRNodeId& from_node,
-                                               const RRNodeId& to_node) {
-    std::vector<RRSwitchId> switches;
-    std::vector<RREdgeId> edges = rr_graph.find_edges(from_node, to_node);
-    if (true == edges.empty()) {
-        /* edge is open, we return an empty vector of switches */
-        return switches;
-    }
-
-    /* Reach here, edge list is not empty, find switch id one by one
-     * and update the switch list
-     */
-    for (auto edge : edges) {
-        switches.push_back(rr_graph.edge_switch(edge));
-    }
-
-    return switches;
-}
diff --git a/vpr/src/device/rr_graph_util.h b/vpr/src/device/rr_graph_util.h
deleted file mode 100644
index 027356b86..000000000
--- a/vpr/src/device/rr_graph_util.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifndef RR_GRAPH_UTIL_H
-#define RR_GRAPH_UTIL_H
-
-/* Include header files which include data structures used by
- * the function declaration
- */
-#include <vector>
-#include "rr_graph_fwd.h"
-
-/* Get node-to-node switches in a RRGraph */
-std::vector<RRSwitchId> find_rr_graph_switches(const RRGraph& rr_graph,
-                                               const RRNodeId& from_node,
-                                               const RRNodeId& to_node);
-
-#endif
diff --git a/vpr/src/device/write_xml_rr_graph_obj.cpp b/vpr/src/device/write_xml_rr_graph_obj.cpp
index a329b7bc0..8cd52938e 100644
--- a/vpr/src/device/write_xml_rr_graph_obj.cpp
+++ b/vpr/src/device/write_xml_rr_graph_obj.cpp
@@ -55,8 +55,6 @@ void write_rr_graph_node(fstream &fp, const RRGraph& rr_graph) {
   /* TODO: we should make it function full independent from device_ctx !!! */
   auto& device_ctx = g_vpr_ctx.device();
 
-  std::array<const char*, NUM_DIRECTIONS> DIRECTION_STRING_WRITE_XML = {{"INC_DIR", "DEC_DIR", "BI_DIR", "NO_DIR"}};
-
   fp << "\t<rr_nodes>" << endl;
 
   for (auto node : rr_graph.nodes()) {
diff --git a/vpr/src/draw/draw.cpp b/vpr/src/draw/draw.cpp
index a63e9c51c..03981194c 100644
--- a/vpr/src/draw/draw.cpp
+++ b/vpr/src/draw/draw.cpp
@@ -104,9 +104,9 @@ static void draw_chanx_to_chanx_edge(const RRNodeId& from_node, const RRNodeId&
 static void draw_chanx_to_chany_edge(const RRNodeId& chanx_node, int chanx_track, const RRNodeId& chany_node, int chany_track, enum e_edge_dir edge_dir, short switch_type, ezgl::renderer* g);
 static int get_track_num(const RRNodeId& inode, const vtr::OffsetMatrix<int>& chanx_track, const vtr::OffsetMatrix<int>& chany_track);
 static bool draw_if_net_highlighted(ClusterNetId inet);
-static int draw_check_rr_node_hit(float click_x, float click_y);
+static RRNodeId draw_check_rr_node_hit(float click_x, float click_y);
 
-static void draw_expand_non_configurable_rr_nodes_recurr(int from_node, std::set<int>& expanded_nodes);
+static void draw_expand_non_configurable_rr_nodes_recurr(const RRNodeId& from_node, std::set<RRNodeId>& expanded_nodes);
 static bool highlight_rr_nodes(float x, float y);
 static void highlight_blocks(double x, double y);
 static void draw_reset_blk_colors();
@@ -119,9 +119,8 @@ static inline ezgl::rectangle draw_mux(ezgl::point2d origin, e_side orientation,
 static void draw_flyline_timing_edge(ezgl::point2d start, ezgl::point2d end, float incr_delay, ezgl::renderer* g);
 static void draw_routed_timing_edge(tatum::NodeId start_tnode, tatum::NodeId end_tnode, float incr_delay, ezgl::color color, ezgl::renderer* g);
 static void draw_routed_timing_edge_connection(tatum::NodeId src_tnode, tatum::NodeId sink_tnode, ezgl::color color, ezgl::renderer* g);
-static std::vector<int> trace_routed_connection_rr_nodes(const ClusterNetId net_id, const int driver_pin, const int sink_pin);
-static bool trace_routed_connection_rr_nodes_recurr(const t_rt_node* rt_node, int sink_rr_node, std::vector<int>& rr_nodes_on_path);
-static t_edge_size find_edge(int prev_inode, int inode);
+static std::vector<RRNodeId> trace_routed_connection_rr_nodes(const ClusterNetId net_id, const int driver_pin, const int sink_pin);
+static bool trace_routed_connection_rr_nodes_recurr(const t_rt_node* rt_node, const RRNodeId& sink_rr_node, std::vector<RRNodeId>& rr_nodes_on_path);
 
 static void draw_color_map_legend(const vtr::ColorMap& cmap, ezgl::renderer* g);
 
@@ -859,7 +858,6 @@ void free_draw_structs() {
     }
 
     if (draw_state != nullptr) {
-        free(draw_state->draw_rr_node);
         draw_state->draw_rr_node.clear();
     }
 #else
@@ -1049,10 +1047,10 @@ static void draw_congestion(ezgl::renderer* g) {
     //Record min/max congestion
     float min_congestion_ratio = 1.;
     float max_congestion_ratio = min_congestion_ratio;
-    std::vector<int> congested_rr_nodes = collect_congested_rr_nodes();
-    for (int inode : congested_rr_nodes) {
+    std::vector<RRNodeId> congested_rr_nodes = collect_congested_rr_nodes();
+    for (const RRNodeId& inode : congested_rr_nodes) {
         short occ = route_ctx.rr_node_route_inf[inode].occ();
-        short capacity = device_ctx.rr_nodes[inode].capacity();
+        short capacity = device_ctx.rr_graph.node_capacity(inode);
 
         float congestion_ratio = float(occ) / capacity;
 
@@ -1072,12 +1070,12 @@ static void draw_congestion(ezgl::renderer* g) {
 
     //Sort the nodes in ascending order of value for drawing, this ensures high
     //valued nodes are not overdrawn by lower value ones (e.g-> when zoomed-out far)
-    auto cmp_ascending_acc_cost = [&](int lhs_node, int rhs_node) {
+    auto cmp_ascending_acc_cost = [&](const RRNodeId& lhs_node, const RRNodeId& rhs_node) {
         short lhs_occ = route_ctx.rr_node_route_inf[lhs_node].occ();
-        short lhs_capacity = device_ctx.rr_nodes[lhs_node].capacity();
+        short lhs_capacity = device_ctx.rr_graph.node_capacity(lhs_node);
 
         short rhs_occ = route_ctx.rr_node_route_inf[rhs_node].occ();
-        short rhs_capacity = device_ctx.rr_nodes[rhs_node].capacity();
+        short rhs_capacity = device_ctx.rr_graph.node_capacity(rhs_node);
 
         float lhs_cong_ratio = float(lhs_occ) / lhs_capacity;
         float rhs_cong_ratio = float(rhs_occ) / rhs_capacity;
@@ -1089,7 +1087,7 @@ static void draw_congestion(ezgl::renderer* g) {
     if (draw_state->show_congestion == DRAW_CONGESTED_WITH_NETS) {
         auto rr_node_nets = collect_rr_node_nets();
 
-        for (int inode : congested_rr_nodes) {
+        for (const RRNodeId& inode : congested_rr_nodes) {
             for (ClusterNetId net : rr_node_nets[inode]) {
                 ezgl::color color = kelly_max_contrast_colors[size_t(net) % kelly_max_contrast_colors.size()];
                 draw_state->net_color[net] = color;
@@ -1099,7 +1097,7 @@ static void draw_congestion(ezgl::renderer* g) {
         drawroute(HIGHLIGHTED, g);
 
         //Reset colors
-        for (int inode : congested_rr_nodes) {
+        for (const RRNodeId& inode : congested_rr_nodes) {
             for (ClusterNetId net : rr_node_nets[inode]) {
                 draw_state->net_color[net] = DEFAULT_RR_NODE_COLOR;
             }
@@ -1109,9 +1107,9 @@ static void draw_congestion(ezgl::renderer* g) {
     }
 
     //Draw each congested node
-    for (int inode : congested_rr_nodes) {
+    for (const RRNodeId& inode : congested_rr_nodes) {
         short occ = route_ctx.rr_node_route_inf[inode].occ();
-        short capacity = device_ctx.rr_nodes[inode].capacity();
+        short capacity = device_ctx.rr_graph.node_capacity(inode);
 
         float congestion_ratio = float(occ) / capacity;
 
@@ -1120,7 +1118,7 @@ static void draw_congestion(ezgl::renderer* g) {
 
         ezgl::color color = to_ezgl_color(cmap->color(congestion_ratio));
 
-        switch (device_ctx.rr_nodes[inode].type()) {
+        switch (device_ctx.rr_graph.node_type(inode)) {
             case CHANX: //fallthrough
             case CHANY:
                 draw_rr_chan(inode, color, g);
@@ -1159,18 +1157,18 @@ static void draw_routing_costs(ezgl::renderer* g) {
 
     float min_cost = std::numeric_limits<float>::infinity();
     float max_cost = -min_cost;
-    std::vector<float> rr_node_costs(device_ctx.rr_graph.nodes().size(), 0.);
-    for (size_t inode = 0; inode < device_ctx.rr_graph.nodes().size(); inode++) {
+    vtr::vector<RRNodeId, float> rr_node_costs(device_ctx.rr_graph.nodes().size(), 0.);
+    for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) {
         float cost = 0.;
         if (draw_state->show_routing_costs == DRAW_TOTAL_ROUTING_COSTS
             || draw_state->show_routing_costs == DRAW_LOG_TOTAL_ROUTING_COSTS) {
-            int cost_index = device_ctx.rr_nodes[inode].cost_index();
+            int cost_index = device_ctx.rr_graph.node_cost_index(inode);
             cost = device_ctx.rr_indexed_data[cost_index].base_cost
                    + route_ctx.rr_node_route_inf[inode].acc_cost
                    + route_ctx.rr_node_route_inf[inode].pres_cost;
 
         } else if (draw_state->show_routing_costs == DRAW_BASE_ROUTING_COSTS) {
-            int cost_index = device_ctx.rr_nodes[inode].cost_index();
+            int cost_index = device_ctx.rr_graph.node_cost_index(inode);
             cost = device_ctx.rr_indexed_data[cost_index].base_cost;
 
         } else if (draw_state->show_routing_costs == DRAW_ACC_ROUTING_COSTS
@@ -1194,7 +1192,7 @@ static void draw_routing_costs(ezgl::renderer* g) {
     }
 
     //Hide min value, draw_rr_costs() ignores NaN's
-    for (size_t inode = 0; inode < device_ctx.rr_graph.nodes().size(); inode++) {
+    for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) {
         if (rr_node_costs[inode] == min_cost) {
             rr_node_costs[inode] = NAN;
         }
@@ -1292,10 +1290,10 @@ void draw_rr(ezgl::renderer* g) {
 
     g->set_line_dash(ezgl::line_dash::none);
 
-    for (size_t inode = 0; inode < device_ctx.rr_graph.nodes().size(); inode++) {
+    for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) {
         if (!draw_state->draw_rr_node[inode].node_highlighted) {
             /* If not highlighted node, assign color based on type. */
-            switch (device_ctx.rr_nodes[inode].type()) {
+            switch (device_ctx.rr_graph.node_type(inode)) {
                 case CHANX:
                 case CHANY:
                     draw_state->draw_rr_node[inode].color = DEFAULT_RR_NODE_COLOR;
@@ -1312,7 +1310,7 @@ void draw_rr(ezgl::renderer* g) {
         }
 
         /* Now call drawing routines to draw the node. */
-        switch (device_ctx.rr_nodes[inode].type()) {
+        switch (device_ctx.rr_graph.node_type(inode)) {
             case SOURCE:
             case SINK:
                 break; /* Don't draw. */
@@ -1338,7 +1336,7 @@ void draw_rr(ezgl::renderer* g) {
 
             default:
                 vpr_throw(VPR_ERROR_OTHER, __FILE__, __LINE__,
-                          "in draw_rr: Unexpected rr_node type: %d.\n", device_ctx.rr_nodes[inode].type());
+                          "in draw_rr: Unexpected rr_node type: %d.\n", device_ctx.rr_graph.node_type(inode));
         }
     }
 
@@ -1434,7 +1432,7 @@ static void draw_rr_chan(const RRNodeId& inode, const ezgl::color color, ezgl::r
         if (switchpoint_min == 0) {
             if (dir != BI_DIRECTION) {
                 //Draw a mux at the start of each wire, labelled with it's size (#inputs)
-                draw_mux_with_size(start, mux_dir, WIRE_DRAWING_WIDTH, device_ctx.rr_nodes[inode].fan_in(), g);
+                draw_mux_with_size(start, mux_dir, WIRE_DRAWING_WIDTH, device_ctx.rr_graph.node_in_edges(inode).size(), g);
             }
         } else {
             //Draw arrows and label with switch point
@@ -1590,7 +1588,7 @@ static void draw_rr_edges(const RRNodeId& inode, ezgl::renderer* g) {
                         } else {
                             g->set_color(blk_DARKGREEN);
                         }
-                        switch_type = device_ctx.rr_nodes[inode].edge_switch(iedge);
+                        switch_type = size_t(device_ctx.rr_graph.edge_switch(iedge));
                         draw_chanx_to_chanx_edge(inode, to_node,
                                                  to_ptc_num, switch_type, g);
                         break;
@@ -1607,7 +1605,7 @@ static void draw_rr_edges(const RRNodeId& inode, ezgl::renderer* g) {
                         } else {
                             g->set_color(blk_DARKGREEN);
                         }
-                        switch_type = device_ctx.rr_nodes[inode].edge_switch(iedge);
+                        switch_type = size_t(device_ctx.rr_graph.edge_switch(iedge));
                         draw_chanx_to_chany_edge(inode, from_ptc_num, to_node,
                                                  to_ptc_num, FROM_X_TO_Y, switch_type, g);
                         break;
@@ -1660,7 +1658,7 @@ static void draw_rr_edges(const RRNodeId& inode, ezgl::renderer* g) {
                         } else {
                             g->set_color(blk_DARKGREEN);
                         }
-                        switch_type = device_ctx.rr_nodes[inode].edge_switch(iedge);
+                        switch_type = size_t(device_ctx.rr_graph.edge_switch(iedge));
                         draw_chanx_to_chany_edge(to_node, to_ptc_num, inode,
                                                  from_ptc_num, FROM_Y_TO_X, switch_type, g);
                         break;
@@ -1678,7 +1676,7 @@ static void draw_rr_edges(const RRNodeId& inode, ezgl::renderer* g) {
                         } else {
                             g->set_color(blk_DARKGREEN);
                         }
-                        switch_type = device_ctx.rr_nodes[inode].edge_switch(iedge);
+                        switch_type = size_t(device_ctx.rr_graph.edge_switch(iedge));
                         draw_chany_to_chany_edge(inode, to_node,
                                                  to_ptc_num, switch_type, g);
                         break;
@@ -1955,7 +1953,7 @@ ezgl::rectangle draw_get_rr_chan_bbox(const RRNodeId& inode) {
     t_draw_coords* draw_coords = get_draw_coords_vars();
     auto& device_ctx = g_vpr_ctx.device();
 
-    switch (device_ctx.rr_nodes[inode].type()) {
+    switch (device_ctx.rr_graph.node_type(inode)) {
         case CHANX:
             left = draw_coords->tile_x[device_ctx.rr_graph.node_xlow(inode)];
             right = draw_coords->tile_x[device_ctx.rr_graph.node_xhigh(inode)]
@@ -2012,7 +2010,7 @@ static void draw_rr_switch(float from_x, float from_y, float to_x, float to_y, b
     }
 }
 
-static void draw_rr_pin(RRNodeId& inode, const ezgl::color& color, ezgl::renderer* g) {
+static void draw_rr_pin(const RRNodeId& inode, const ezgl::color& color, ezgl::renderer* g) {
     /* Draws an IPIN or OPIN rr_node.  Note that the pin can appear on more    *
      * than one side of a clb.  Also note that this routine can change the     *
      * current color to BLACK.                                                 */
@@ -2066,7 +2064,7 @@ void draw_get_rr_pin_coords(const RRNodeId& inode, float* xcen, float* ycen) {
     step = (float)(draw_coords->get_tile_width()) / (float)(type->num_pins + type->capacity);
     offset = (ipin + k + 1) * step;
 
-    switch (node->side()) {
+    switch (device_ctx.rr_graph.node_side(inode)) {
         case LEFT:
             yc += offset;
             break;
@@ -2087,7 +2085,8 @@ void draw_get_rr_pin_coords(const RRNodeId& inode, float* xcen, float* ycen) {
 
         default:
             vpr_throw(VPR_ERROR_OTHER, __FILE__, __LINE__,
-                      "in draw_get_rr_pin_coords: Unexpected side %s.\n", node->side_string());
+                      "in draw_get_rr_pin_coords: Unexpected side %s.\n",
+                      SIDE_STRING[device_ctx.rr_graph.node_side(inode)]);
             break;
     }
 
@@ -2221,7 +2220,7 @@ void draw_partial_route(const std::vector<RRNodeId>& rr_nodes_to_draw, ezgl::ren
 
         std::vector<RREdgeId> edges = device_ctx.rr_graph.find_edges(prev_node, inode);
         VTR_ASSERT(1 == edges.size());
-        auto switch_type = device_ctx.rr_graph.edge_switch(edges[0]);
+        auto switch_type = size_t(device_ctx.rr_graph.edge_switch(edges[0]));
 
         switch (rr_type) {
             case OPIN: {
@@ -2230,7 +2229,7 @@ void draw_partial_route(const std::vector<RRNodeId>& rr_nodes_to_draw, ezgl::ren
             }
             case IPIN: {
                 draw_rr_pin(inode, draw_state->draw_rr_node[inode].color, g);
-                if (device_ctx.rr_nodes[prev_node].type() == OPIN) {
+                if (device_ctx.rr_graph.node_type(prev_node) == OPIN) {
                     draw_pin_to_pin(prev_node, inode, g);
                 } else {
                     draw_pin_to_chan_edge(inode, prev_node, g);
@@ -2239,7 +2238,7 @@ void draw_partial_route(const std::vector<RRNodeId>& rr_nodes_to_draw, ezgl::ren
             }
             case CHANX: {
                 if (draw_state->draw_route_type == GLOBAL)
-                    chanx_track[device_ctx.rr_nodes[inode].xlow()][device_ctx.rr_nodes[inode].ylow()]++;
+                    chanx_track[device_ctx.rr_graph.node_xlow(inode)][device_ctx.rr_graph.node_ylow(inode)]++;
 
                 int itrack = get_track_num(inode, chanx_track, chany_track);
                 draw_rr_chan(inode, draw_state->draw_rr_node[inode].color, g);
@@ -2390,14 +2389,14 @@ void highlight_nets(char* message, const RRNodeId& hit_node) {
  * fan_in into the node in blue and fan_out from the node in red. If de-highlighted,
  * de-highlight its fan_in and fan_out.
  */
-void draw_highlight_fan_in_fan_out(const std::set<int>& nodes) {
+void draw_highlight_fan_in_fan_out(const std::set<RRNodeId>& nodes) {
     t_draw_state* draw_state = get_draw_state_vars();
     auto& device_ctx = g_vpr_ctx.device();
 
     for (auto node : nodes) {
         /* Highlight the fanout nodes in red. */
-        for (t_edge_size iedge = 0, l = device_ctx.rr_nodes[node].num_edges(); iedge < l; iedge++) {
-            int fanout_node = device_ctx.rr_nodes[node].edge_sink_node(iedge);
+        for (const RREdgeId& iedge : device_ctx.rr_graph.node_out_edges(node)) {
+            RRNodeId fanout_node = device_ctx.rr_graph.edge_sink_node(iedge);
 
             if (draw_state->draw_rr_node[node].color == ezgl::MAGENTA && draw_state->draw_rr_node[fanout_node].color != ezgl::MAGENTA) {
                 // If node is highlighted, highlight its fanout
@@ -2411,9 +2410,9 @@ void draw_highlight_fan_in_fan_out(const std::set<int>& nodes) {
         }
 
         /* Highlight the nodes that can fanin to this node in blue. */
-        for (size_t inode = 0; inode < device_ctx.rr_graph.nodes().size(); inode++) {
-            for (t_edge_size iedge = 0, l = device_ctx.rr_nodes[inode].num_edges(); iedge < l; iedge++) {
-                int fanout_node = device_ctx.rr_nodes[inode].edge_sink_node(iedge);
+        for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) {
+            for (const RREdgeId& iedge : device_ctx.rr_graph.node_out_edges(node)) {
+                RRNodeId fanout_node = device_ctx.rr_graph.edge_sink_node(iedge);
                 if (fanout_node == node) {
                     if (draw_state->draw_rr_node[node].color == ezgl::MAGENTA && draw_state->draw_rr_node[inode].color != ezgl::MAGENTA) {
                         // If node is highlighted, highlight its fanin
@@ -2436,8 +2435,8 @@ void draw_highlight_fan_in_fan_out(const std::set<int>& nodes) {
  *
  *  It returns the hit RR node's ID (or OPEN if no hit)
  */
-static int draw_check_rr_node_hit(float click_x, float click_y) {
-    int hit_node = OPEN;
+static RRNodeId draw_check_rr_node_hit(float click_x, float click_y) {
+    RRNodeId hit_node = RRNodeId::INVALID();
     ezgl::rectangle bound_box;
 
     t_draw_coords* draw_coords = get_draw_coords_vars();
@@ -2489,20 +2488,20 @@ static int draw_check_rr_node_hit(float click_x, float click_y) {
     return hit_node;
 }
 
-std::set<int> draw_expand_non_configurable_rr_nodes(int from_node) {
-    std::set<int> expanded_nodes;
+std::set<RRNodeId> draw_expand_non_configurable_rr_nodes(const RRNodeId& from_node) {
+    std::set<RRNodeId> expanded_nodes;
     draw_expand_non_configurable_rr_nodes_recurr(from_node, expanded_nodes);
     return expanded_nodes;
 }
 
-void draw_expand_non_configurable_rr_nodes_recurr(int from_node, std::set<int>& expanded_nodes) {
+void draw_expand_non_configurable_rr_nodes_recurr(const RRNodeId& from_node, std::set<RRNodeId>& expanded_nodes) {
     auto& device_ctx = g_vpr_ctx.device();
 
     expanded_nodes.insert(from_node);
 
-    for (t_edge_size iedge = 0; iedge < device_ctx.rr_nodes[from_node].num_edges(); ++iedge) {
-        bool edge_configurable = device_ctx.rr_nodes[from_node].edge_is_configurable(iedge);
-        int to_node = device_ctx.rr_nodes[from_node].edge_sink_node(iedge);
+    for (const RREdgeId& iedge : device_ctx.rr_graph.node_out_edges(from_node)) {
+        bool edge_configurable = device_ctx.rr_graph.edge_is_configurable(iedge);
+        RRNodeId to_node = device_ctx.rr_graph.edge_sink_node(iedge);
 
         if (!edge_configurable && !expanded_nodes.count(to_node)) {
             draw_expand_non_configurable_rr_nodes_recurr(to_node, expanded_nodes);
@@ -2525,7 +2524,7 @@ static bool highlight_rr_nodes(float x, float y) {
     }
 
     // Check which rr_node (if any) was clicked on.
-    int hit_node = draw_check_rr_node_hit(x, y);
+    RRNodeId hit_node = draw_check_rr_node_hit(x, y);
 
     return highlight_rr_nodes(hit_node);
 }
@@ -2629,9 +2628,9 @@ void act_on_mouse_move(ezgl::application* app, GdkEventButton* event, double x,
     t_draw_state* draw_state = get_draw_state_vars();
 
     if (draw_state->draw_rr_toggle != DRAW_NO_RR) {
-        int hit_node = draw_check_rr_node_hit(x, y);
+        RRNodeId hit_node = draw_check_rr_node_hit(x, y);
 
-        if (hit_node != OPEN) {
+        if (hit_node != RRNodeId::INVALID()) {
             //Update message
 
             std::string info = describe_rr_node(hit_node);
@@ -2723,9 +2722,9 @@ void deselect_all() {
     for (auto net_id : cluster_ctx.clb_nlist.nets())
         draw_state->net_color[net_id] = ezgl::BLACK;
 
-    for (size_t i = 0; i < device_ctx.rr_graph.nodes().size(); i++) {
-        draw_state->draw_rr_node[i].color = DEFAULT_RR_NODE_COLOR;
-        draw_state->draw_rr_node[i].node_highlighted = false;
+    for (const RRNodeId& node : device_ctx.rr_graph.nodes()) {
+        draw_state->draw_rr_node[node].color = DEFAULT_RR_NODE_COLOR;
+        draw_state->draw_rr_node[node].node_highlighted = false;
     }
     get_selected_sub_block_info().clear();
 }
@@ -2827,7 +2826,7 @@ static void draw_pin_to_chan_edge(const RRNodeId& pin_node, const RRNodeId& chan
     ezgl::rectangle chan_bbox = draw_get_rr_chan_bbox(chan_node);
 
     float x2 = 0, y2 = 0;
-    switch (chan_rr.type()) {
+    switch (rr_graph.node_type(chan_node)) {
         case CHANX: {
             y1 += draw_pin_offset;
             y2 = chan_bbox.bottom();
@@ -3138,15 +3137,15 @@ static void draw_routed_timing_edge_connection(tatum::NodeId src_tnode, tatum::N
             //Now that we have the CLB source and sink pins, we need to grab all the points on the routing connecting the pins
             VTR_ASSERT(cluster_ctx.clb_nlist.net_driver_block(net_id) == clb_src_block);
 
-            std::vector<int> routed_rr_nodes = trace_routed_connection_rr_nodes(net_id, 0, sink_net_pin_index);
+            std::vector<RRNodeId> routed_rr_nodes = trace_routed_connection_rr_nodes(net_id, 0, sink_net_pin_index);
 
             //Mark all the nodes highlighted
             t_draw_state* draw_state = get_draw_state_vars();
-            for (int inode : routed_rr_nodes) {
+            for (const RRNodeId& inode : routed_rr_nodes) {
                 draw_state->draw_rr_node[inode].color = color;
             }
 
-            draw_partial_route((std::vector<int>)routed_rr_nodes, (ezgl::renderer*)g);
+            draw_partial_route((std::vector<RRNodeId>)routed_rr_nodes, (ezgl::renderer*)g);
         } else {
             //Connection entirely within the CLB, we don't draw the internal routing so treat it as a fly-line
             VTR_ASSERT(clb_src_block == clb_sink_block);
@@ -3157,7 +3156,7 @@ static void draw_routed_timing_edge_connection(tatum::NodeId src_tnode, tatum::N
 }
 
 //Returns the set of rr nodes which connect driver to sink
-static std::vector<int> trace_routed_connection_rr_nodes(const ClusterNetId net_id, const int driver_pin, const int sink_pin) {
+static std::vector<RRNodeId> trace_routed_connection_rr_nodes(const ClusterNetId net_id, const int driver_pin, const int sink_pin) {
     auto& route_ctx = g_vpr_ctx.routing();
 
     bool allocated_route_tree_structs = alloc_route_tree_timing_structs(true); //Needed for traceback_to_route_tree
@@ -3165,11 +3164,11 @@ static std::vector<int> trace_routed_connection_rr_nodes(const ClusterNetId net_
     //Conver the traceback into an easily search-able
     t_rt_node* rt_root = traceback_to_route_tree(net_id);
 
-    VTR_ASSERT(rt_root && rt_root->inode == route_ctx.net_rr_terminals[net_id][driver_pin]);
+    VTR_ASSERT(rt_root && rt_root->inode == RRNodeId(route_ctx.net_rr_terminals[net_id][driver_pin]));
 
-    int sink_rr_node = route_ctx.net_rr_terminals[net_id][sink_pin];
+    RRNodeId sink_rr_node = RRNodeId(route_ctx.net_rr_terminals[net_id][sink_pin]);
 
-    std::vector<int> rr_nodes_on_path;
+    std::vector<RRNodeId> rr_nodes_on_path;
 
     //Collect the rr nodes
     trace_routed_connection_rr_nodes_recurr(rt_root, sink_rr_node, rr_nodes_on_path);
@@ -3188,7 +3187,7 @@ static std::vector<int> trace_routed_connection_rr_nodes(const ClusterNetId net_
 //Helper function for trace_routed_connection_rr_nodes
 //Adds the rr nodes linking rt_node to sink_rr_node to rr_nodes_on_path
 //Returns true if rt_node is on the path
-bool trace_routed_connection_rr_nodes_recurr(const t_rt_node* rt_node, int sink_rr_node, std::vector<int>& rr_nodes_on_path) {
+bool trace_routed_connection_rr_nodes_recurr(const t_rt_node* rt_node, const RRNodeId& sink_rr_node, std::vector<RRNodeId>& rr_nodes_on_path) {
     //DFS from the current rt_node to the sink_rr_node, when the sink is found trace back the used rr nodes
 
     if (rt_node->inode == sink_rr_node) {
@@ -3211,18 +3210,6 @@ bool trace_routed_connection_rr_nodes_recurr(const t_rt_node* rt_node, int sink_
     return false; //Not on path to sink
 }
 
-//Find the edge between two rr nodes
-static t_edge_size find_edge(int prev_inode, int inode) {
-    auto& device_ctx = g_vpr_ctx.device();
-    for (t_edge_size iedge = 0; iedge < device_ctx.rr_nodes[prev_inode].num_edges(); ++iedge) {
-        if (device_ctx.rr_nodes[prev_inode].edge_sink_node(iedge) == inode) {
-            return iedge;
-        }
-    }
-    VTR_ASSERT(false);
-    return OPEN;
-}
-
 ezgl::color to_ezgl_color(vtr::Color<float> color) {
     return ezgl::color(color.r * 255, color.g * 255, color.b * 255);
 }
@@ -3548,7 +3535,13 @@ static void draw_rr_costs(ezgl::renderer* g, const vtr::vector<RRNodeId, float>&
 
     //Draw the nodes in ascending order of value, this ensures high valued nodes
     //are not overdrawn by lower value ones (e.g-> when zoomed-out far)
-    std::vector<RRNodeId> nodes = device_ctx.rr_graph.nodes();
+    std::vector<RRNodeId> nodes;
+    /* Xifan Tang - TODO: This is not efficient, 
+     * we should be able to give a constant vector from rr_graph object directly 
+     */
+    for (const RRNodeId& node : device_ctx.rr_graph.nodes()) {
+      nodes.push_back(node);
+    }
     auto cmp_ascending_cost = [&](const RRNodeId& lhs_node, const RRNodeId& rhs_node) {
         if (lowest_cost_first) {
             return rr_costs[lhs_node] > rr_costs[rhs_node];
diff --git a/vpr/src/draw/draw.h b/vpr/src/draw/draw.h
index 98c908ba4..39458b968 100644
--- a/vpr/src/draw/draw.h
+++ b/vpr/src/draw/draw.h
@@ -60,8 +60,8 @@ void draw_screen();
 ezgl::rectangle draw_get_rr_chan_bbox(const RRNodeId& inode);
 void draw_highlight_blocks_color(t_logical_block_type_ptr type, ClusterBlockId blk_id);
 void highlight_nets(char* message, const RRNodeId& hit_node);
-void draw_highlight_fan_in_fan_out(const std::set<int>& nodes);
-std::set<int> draw_expand_non_configurable_rr_nodes(int hit_node);
+void draw_highlight_fan_in_fan_out(const std::set<RRNodeId>& nodes);
+std::set<RRNodeId> draw_expand_non_configurable_rr_nodes(const RRNodeId& hit_node);
 void deselect_all();
 
 // toggle functions
diff --git a/vpr/src/draw/search_bar.cpp b/vpr/src/draw/search_bar.cpp
index aaa591c20..a7ff3831b 100644
--- a/vpr/src/draw/search_bar.cpp
+++ b/vpr/src/draw/search_bar.cpp
@@ -74,8 +74,8 @@ void search_and_highlight(GtkWidget* /*widget*/, ezgl::application* app) {
             return;
         }
 
-        highlight_rr_nodes(rr_node_id);
-        auto_zoom_rr_node(rr_node_id);
+        highlight_rr_nodes(RRNodeId(rr_node_id));
+        auto_zoom_rr_node(RRNodeId(rr_node_id));
     }
 
     else if (search_type == "Block ID") {
@@ -125,12 +125,12 @@ void search_and_highlight(GtkWidget* /*widget*/, ezgl::application* app) {
     app->refresh_drawing();
 }
 
-bool highlight_rr_nodes(int hit_node) {
+bool highlight_rr_nodes(const RRNodeId& hit_node) {
     t_draw_state* draw_state = get_draw_state_vars();
 
     char message[250] = "";
 
-    if (hit_node != OPEN) {
+    if (hit_node != RRNodeId::INVALID()) {
         auto nodes = draw_expand_non_configurable_rr_nodes(hit_node);
         for (auto node : nodes) {
             if (draw_state->draw_rr_node[node].color != ezgl::MAGENTA) {
@@ -177,21 +177,21 @@ bool highlight_rr_nodes(int hit_node) {
     return true;
 }
 
-void auto_zoom_rr_node(int rr_node_id) {
+void auto_zoom_rr_node(const RRNodeId& rr_node_id) {
     t_draw_coords* draw_coords = get_draw_coords_vars();
     auto& device_ctx = g_vpr_ctx.device();
     ezgl::rectangle rr_node;
 
     // find the location of the node
-    switch (device_ctx.rr_nodes[rr_node_id].type()) {
+    switch (device_ctx.rr_graph.node_type(rr_node_id)) {
         case IPIN:
         case OPIN: {
-            int i = device_ctx.rr_nodes[rr_node_id].xlow();
-            int j = device_ctx.rr_nodes[rr_node_id].ylow();
+            int i = device_ctx.rr_graph.node_xlow(rr_node_id);
+            int j = device_ctx.rr_graph.node_ylow(rr_node_id);
             t_physical_tile_type_ptr type = device_ctx.grid[i][j].type;
             int width_offset = device_ctx.grid[i][j].width_offset;
             int height_offset = device_ctx.grid[i][j].height_offset;
-            int ipin = device_ctx.rr_nodes[rr_node_id].ptc_num();
+            int ipin = device_ctx.rr_graph.node_ptc_num(rr_node_id);
             float xcen, ycen;
 
             int iside;
diff --git a/vpr/src/draw/search_bar.h b/vpr/src/draw/search_bar.h
index c908e78c9..ac3f771cf 100644
--- a/vpr/src/draw/search_bar.h
+++ b/vpr/src/draw/search_bar.h
@@ -11,8 +11,8 @@
 #    include "draw_color.h"
 
 void search_and_highlight(GtkWidget* /*widget*/, ezgl::application* app);
-bool highlight_rr_nodes(int hit_node);
-void auto_zoom_rr_node(int rr_node_id);
+bool highlight_rr_nodes(const RRNodeId& hit_node);
+void auto_zoom_rr_node(const RRNodeId& rr_node_id);
 void highlight_blocks(ClusterBlockId clb_index);
 void highlight_nets(ClusterNetId net_id);
 void highlight_nets(std::string net_name);
diff --git a/vpr/src/place/timing_place_lookup.cpp b/vpr/src/place/timing_place_lookup.cpp
index d3cdad215..dd55adca4 100644
--- a/vpr/src/place/timing_place_lookup.cpp
+++ b/vpr/src/place/timing_place_lookup.cpp
@@ -34,6 +34,8 @@
 #include "router_delay_profiling.h"
 #include "place_delay_model.h"
 
+#include "rr_graph_obj_util.h"
+
 /*To compute delay between blocks we calculate the delay between */
 /*different nodes in the FPGA.  From this procedure we generate
  * a lookup table which tells us the delay between different locations in*/
@@ -113,8 +115,8 @@ static bool find_direct_connect_sample_locations(const t_direct_inf* direct,
                                                  t_physical_tile_type_ptr to_type,
                                                  int to_pin,
                                                  int to_pin_class,
-                                                 int* src_rr,
-                                                 int* sink_rr);
+                                                 RRNodeId& src_rr,
+                                                 RRNodeId& sink_rr);
 
 static bool verify_delta_delays(const vtr::Matrix<float>& delta_delays);
 
@@ -741,8 +743,8 @@ static bool find_direct_connect_sample_locations(const t_direct_inf* direct,
                                                  t_physical_tile_type_ptr to_type,
                                                  int to_pin,
                                                  int to_pin_class,
-                                                 int* src_rr,
-                                                 int* sink_rr) {
+                                                 RRNodeId& src_rr,
+                                                 RRNodeId& sink_rr) {
     VTR_ASSERT(from_type != nullptr);
     VTR_ASSERT(to_type != nullptr);
 
@@ -765,10 +767,10 @@ static bool find_direct_connect_sample_locations(const t_direct_inf* direct,
             //(with multi-width/height blocks pins may not exist at all locations)
             bool from_pin_found = false;
             if (direct->from_side != NUM_SIDES) {
-                int from_pin_rr = get_rr_node_index(device_ctx.rr_node_indices, from_x, from_y, OPIN, from_pin, direct->from_side);
-                from_pin_found = (from_pin_rr != OPEN);
+                RRNodeId from_pin_rr = device_ctx.rr_graph.find_node(from_x, from_y, OPIN, from_pin, direct->from_side);
+                from_pin_found = (from_pin_rr != RRNodeId::INVALID());
             } else {
-                std::vector<int> from_pin_rrs = get_rr_node_indices(device_ctx.rr_node_indices, from_x, from_y, OPIN, from_pin);
+                std::vector<RRNodeId> from_pin_rrs = find_rr_graph_nodes(device_ctx.rr_graph, from_x, from_y, OPIN, from_pin);
                 from_pin_found = !from_pin_rrs.empty();
             }
             if (!from_pin_found) continue;
@@ -782,10 +784,10 @@ static bool find_direct_connect_sample_locations(const t_direct_inf* direct,
             //(with multi-width/height blocks pins may not exist at all locations)
             bool to_pin_found = false;
             if (direct->to_side != NUM_SIDES) {
-                int to_pin_rr = get_rr_node_index(device_ctx.rr_node_indices, to_x, to_y, IPIN, to_pin, direct->to_side);
-                to_pin_found = (to_pin_rr != OPEN);
+                RRNodeId to_pin_rr = device_ctx.rr_graph.find_node(to_x, to_y, IPIN, to_pin, direct->to_side);
+                to_pin_found = (to_pin_rr != RRNodeId::INVALID());
             } else {
-                std::vector<int> to_pin_rrs = get_rr_node_indices(device_ctx.rr_node_indices, to_x, to_y, IPIN, to_pin);
+                std::vector<RRNodeId> to_pin_rrs = find_rr_graph_nodes(device_ctx.rr_graph, to_x, to_y, IPIN, to_pin);
                 to_pin_found = !to_pin_rrs.empty();
             }
             if (!to_pin_found) continue;
@@ -822,14 +824,14 @@ static bool find_direct_connect_sample_locations(const t_direct_inf* direct,
     //Find a source/sink RR node associated with the pins of the direct
     //
 
-    auto source_rr_nodes = get_rr_node_indices(device_ctx.rr_node_indices, from_x, from_y, SOURCE, from_pin_class);
+    std::vector<RRNodeId> source_rr_nodes = find_rr_graph_nodes(device_ctx.rr_graph, from_x, from_y, SOURCE, from_pin_class);
     VTR_ASSERT(source_rr_nodes.size() > 0);
 
-    auto sink_rr_nodes = get_rr_node_indices(device_ctx.rr_node_indices, to_x, to_y, SINK, to_pin_class);
+    std::vector<RRNodeId> sink_rr_nodes = find_rr_graph_nodes(device_ctx.rr_graph, to_x, to_y, SINK, to_pin_class);
     VTR_ASSERT(sink_rr_nodes.size() > 0);
 
-    *src_rr = source_rr_nodes[0];
-    *sink_rr = sink_rr_nodes[0];
+    src_rr = source_rr_nodes[0];
+    sink_rr = sink_rr_nodes[0];
 
     return true;
 }
@@ -884,7 +886,7 @@ void OverrideDelayModel::compute_override_delay_model(
         //sampled_rr_pairs and skipping them if they occur multiple times.
         int missing_instances = 0;
         int missing_paths = 0;
-        std::set<std::pair<int, int>> sampled_rr_pairs;
+        std::set<std::pair<RRNodeId, RRNodeId>> sampled_rr_pairs;
         for (int iconn = 0; iconn < num_conns; ++iconn) {
             //Find the associated pins
             int from_pin = find_pin(from_type, from_port.port_name(), from_port.port_low_index() + iconn);
@@ -899,9 +901,9 @@ void OverrideDelayModel::compute_override_delay_model(
             int to_pin_class = find_pin_class(to_type, to_port.port_name(), to_port.port_low_index() + iconn, RECEIVER);
             VTR_ASSERT(to_pin_class != OPEN);
 
-            int src_rr = OPEN;
-            int sink_rr = OPEN;
-            bool found_sample_points = find_direct_connect_sample_locations(direct, from_type, from_pin, from_pin_class, to_type, to_pin, to_pin_class, &src_rr, &sink_rr);
+            RRNodeId src_rr = RRNodeId::INVALID();
+            RRNodeId sink_rr = RRNodeId::INVALID();
+            bool found_sample_points = find_direct_connect_sample_locations(direct, from_type, from_pin, from_pin_class, to_type, to_pin, to_pin_class, src_rr, sink_rr);
 
             if (!found_sample_points) {
                 ++missing_instances;
@@ -912,8 +914,8 @@ void OverrideDelayModel::compute_override_delay_model(
             //sampled the associated source/sink pair and don't need to do so again
             if (sampled_rr_pairs.count({src_rr, sink_rr})) continue;
 
-            VTR_ASSERT(src_rr != OPEN);
-            VTR_ASSERT(sink_rr != OPEN);
+            VTR_ASSERT(src_rr != RRNodeId::INVALID());
+            VTR_ASSERT(sink_rr != RRNodeId::INVALID());
 
             float direct_connect_delay = std::numeric_limits<float>::quiet_NaN();
             bool found_routing_path = route_profiler.calculate_delay(src_rr, sink_rr, router_opts2, &direct_connect_delay);
diff --git a/vpr/src/route/route_common.cpp b/vpr/src/route/route_common.cpp
index 40eada542..39373cb76 100644
--- a/vpr/src/route/route_common.cpp
+++ b/vpr/src/route/route_common.cpp
@@ -346,14 +346,14 @@ bool feasible_routing() {
 }
 
 //Returns all RR nodes in the current routing which are congested
-std::vector<int> collect_congested_rr_nodes() {
+std::vector<RRNodeId> collect_congested_rr_nodes() {
     auto& device_ctx = g_vpr_ctx.device();
     auto& route_ctx = g_vpr_ctx.routing();
 
-    std::vector<int> congested_rr_nodes;
-    for (size_t inode = 0; inode < device_ctx.rr_graph.nodes().size(); inode++) {
+    std::vector<RRNodeId> congested_rr_nodes;
+    for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) {
         short occ = route_ctx.rr_node_route_inf[inode].occ();
-        short capacity = device_ctx.rr_nodes[inode].capacity();
+        short capacity = device_ctx.rr_graph.node_capacity(inode);
 
         if (occ > capacity) {
             congested_rr_nodes.push_back(inode);
@@ -364,16 +364,16 @@ std::vector<int> collect_congested_rr_nodes() {
 
 /* Returns a vector from [0..device_ctx.rr_graph.nodes().size()-1] containing the set
  * of nets using each RR node */
-std::vector<std::set<ClusterNetId>> collect_rr_node_nets() {
+vtr::vector<RRNodeId, std::set<ClusterNetId>> collect_rr_node_nets() {
     auto& device_ctx = g_vpr_ctx.device();
     auto& route_ctx = g_vpr_ctx.routing();
     auto& cluster_ctx = g_vpr_ctx.clustering();
 
-    std::vector<std::set<ClusterNetId>> rr_node_nets(device_ctx.rr_graph.nodes().size());
+    vtr::vector<RRNodeId, std::set<ClusterNetId>> rr_node_nets(device_ctx.rr_graph.nodes().size());
     for (ClusterNetId inet : cluster_ctx.clb_nlist.nets()) {
         t_trace* trace_elem = route_ctx.trace[inet].head;
         while (trace_elem) {
-            int rr_node = trace_elem->index;
+            const RRNodeId& rr_node = trace_elem->index;
 
             rr_node_nets[rr_node].insert(inet);
 
diff --git a/vpr/src/route/route_export.h b/vpr/src/route/route_export.h
index ec68f83b8..187ca5087 100644
--- a/vpr/src/route/route_export.h
+++ b/vpr/src/route/route_export.h
@@ -29,9 +29,9 @@ bool try_route(int width_fac,
 
 bool feasible_routing();
 
-std::vector<int> collect_congested_rr_nodes();
+std::vector<RRNodeId> collect_congested_rr_nodes();
 
-std::vector<std::set<ClusterNetId>> collect_rr_node_nets();
+vtr::vector<RRNodeId, std::set<ClusterNetId>> collect_rr_node_nets();
 
 t_clb_opins_used alloc_route_structs();
 
diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp
index 6bb9892ed..e70e70d01 100644
--- a/vpr/src/route/rr_graph.cpp
+++ b/vpr/src/route/rr_graph.cpp
@@ -2526,53 +2526,53 @@ static vtr::NdMatrix<std::vector<int>, 4> alloc_and_load_track_to_pin_lookup(vtr
     return track_to_pin_lookup;
 }
 
-std::string describe_rr_node(int inode) {
+std::string describe_rr_node(const RRNodeId& inode) {
     auto& device_ctx = g_vpr_ctx.device();
 
-    std::string msg = vtr::string_fmt("RR node: %d", inode);
+    std::string msg = vtr::string_fmt("RR node: %ld", size_t(inode));
 
-    const auto& rr_node = device_ctx.rr_nodes[inode];
+    const RRGraph& rr_graph = device_ctx.rr_graph;
 
-    msg += vtr::string_fmt(" type: %s", rr_node.type_string());
+    msg += vtr::string_fmt(" type: %s", rr_node_typename[rr_graph.node_type(inode)]);
 
-    msg += vtr::string_fmt(" location: (%d,%d)", rr_node.xlow(), rr_node.ylow());
-    if (rr_node.xlow() != rr_node.xhigh() || rr_node.ylow() != rr_node.yhigh()) {
-        msg += vtr::string_fmt(" <-> (%d,%d)", rr_node.xhigh(), rr_node.yhigh());
+    msg += vtr::string_fmt(" location: (%d,%d)", rr_graph.node_xlow(inode), rr_graph.node_ylow(inode));
+    if (rr_graph.node_xlow(inode) != rr_graph.node_xhigh(inode) || rr_graph.node_ylow(inode) != rr_graph.node_yhigh(inode)) {
+        msg += vtr::string_fmt(" <-> (%d,%d)", rr_graph.node_xhigh(inode), rr_graph.node_yhigh(inode));
     }
 
-    if (rr_node.type() == CHANX || rr_node.type() == CHANY) {
-        int cost_index = rr_node.cost_index();
+    if (rr_graph.node_type(inode) == CHANX || rr_graph.node_type(inode) == CHANY) {
+        int cost_index = rr_graph.node_cost_index(inode);
 
         int seg_index = device_ctx.rr_indexed_data[cost_index].seg_index;
 
         if (seg_index < (int)device_ctx.arch->Segments.size()) {
             msg += vtr::string_fmt(" track: %d len: %d longline: %d seg_type: %s dir: %s",
-                                   rr_node.track_num(),
-                                   rr_node.length(),
+                                   rr_graph.node_track_num(inode),
+                                   rr_graph.node_length(inode),
                                    device_ctx.arch->Segments[seg_index].longline,
                                    device_ctx.arch->Segments[seg_index].name.c_str(),
-                                   rr_node.direction_string());
+                                   DIRECTION_STRING_WRITE_XML[rr_graph.node_direction(inode)]);
         } else {
             msg += vtr::string_fmt(" track: %d len: %d seg_type: ILLEGAL_SEG_INDEX %d dir: %s",
-                                   rr_node.track_num(),
-                                   rr_node.length(),
+                                   rr_graph.node_track_num(inode),
+                                   rr_graph.node_length(inode),
                                    seg_index,
-                                   rr_node.direction_string());
+                                   DIRECTION_STRING_WRITE_XML[rr_graph.node_direction(inode)]);
         }
-    } else if (rr_node.type() == IPIN || rr_node.type() == OPIN) {
-        auto type = device_ctx.grid[rr_node.xlow()][rr_node.ylow()].type;
-        std::string pin_name = block_type_pin_index_to_name(type, rr_node.pin_num());
+    } else if (rr_graph.node_type(inode) == IPIN || rr_graph.node_type(inode) == OPIN) {
+        auto type = device_ctx.grid[rr_graph.node_xlow(inode)][rr_graph.node_ylow(inode)].type;
+        std::string pin_name = block_type_pin_index_to_name(type, rr_graph.node_pin_num(inode));
 
         msg += vtr::string_fmt(" pin: %d pin_name: %s",
-                               rr_node.pin_num(),
+                               rr_graph.node_pin_num(inode),
                                pin_name.c_str());
     } else {
-        VTR_ASSERT(rr_node.type() == SOURCE || rr_node.type() == SINK);
+        VTR_ASSERT(rr_graph.node_type(inode) == SOURCE || rr_graph.node_type(inode) == SINK);
 
-        msg += vtr::string_fmt(" class: %d", rr_node.class_num());
+        msg += vtr::string_fmt(" class: %d", rr_graph.node_class_num(inode));
     }
 
-    msg += vtr::string_fmt(" capacity: %d", rr_node.capacity());
+    msg += vtr::string_fmt(" capacity: %d", rr_graph.node_capacity(inode));
 
     return msg;
 }
diff --git a/vpr/src/route/rr_graph.h b/vpr/src/route/rr_graph.h
index f55a64f7f..1f60b1afc 100644
--- a/vpr/src/route/rr_graph.h
+++ b/vpr/src/route/rr_graph.h
@@ -43,7 +43,7 @@ void create_rr_graph(const t_graph_type graph_type,
 void free_rr_graph();
 
 //Returns a brief one-line summary of an RR node
-std::string describe_rr_node(int inode);
+std::string describe_rr_node(const RRNodeId& inode);
 
 void init_fan_in(std::vector<t_rr_node>& L_rr_node, const int num_rr_nodes);
 

From a2f231452a45b00a5609e0ce057b835fb0bbafac Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 1 Feb 2020 12:26:42 -0700
Subject: [PATCH 069/645] power estimation adapted to use RRGraph object

---
 vpr/src/power/power.cpp | 116 ++++++++++++++++++++--------------------
 1 file changed, 58 insertions(+), 58 deletions(-)

diff --git a/vpr/src/power/power.cpp b/vpr/src/power/power.cpp
index d4e17c0f8..b0071f06c 100644
--- a/vpr/src/power/power.cpp
+++ b/vpr/src/power/power.cpp
@@ -62,7 +62,7 @@ typedef enum {
 } e_power_breakdown_entry_type;
 
 /************************* File Scope **********************************/
-static t_rr_node_power* rr_node_power;
+static vtr::vector<RRNodeId, t_rr_node_power> rr_node_power;
 
 /************************* Function Declarations ********************/
 /* Routing */
@@ -794,7 +794,7 @@ static void power_usage_routing(t_power_usage* power_usage,
     power_ctx.commonly_used->total_cb_buffer_size = 0.;
 
     /* Reset rr graph net indices */
-    for (size_t rr_node_idx = 0; rr_node_idx < device_ctx.rr_nodes.size(); rr_node_idx++) {
+    for (const RRNodeId& rr_node_idx : device_ctx.rr_graph.nodes()) {
         rr_node_power[rr_node_idx].net_num = ClusterNetId::INVALID();
         rr_node_power[rr_node_idx].num_inputs = 0;
         rr_node_power[rr_node_idx].selected_input = 0;
@@ -815,19 +815,20 @@ static void power_usage_routing(t_power_usage* power_usage,
         t_trace* trace;
 
         for (trace = route_ctx.trace[net_id].head; trace != nullptr; trace = trace->next) {
-            auto node = &device_ctx.rr_nodes[trace->index];
+            RRNodeId node = trace->index;
+            const RRGraph& rr_graph = device_ctx.rr_graph;
             t_rr_node_power* node_power = &rr_node_power[trace->index];
 
             if (node_power->visited) {
                 continue;
             }
 
-            for (t_edge_size edge_idx = 0; edge_idx < node->num_edges(); edge_idx++) {
-                if (node->edge_sink_node(edge_idx) != OPEN) {
-                    auto next_node = &device_ctx.rr_nodes[node->edge_sink_node(edge_idx)];
-                    t_rr_node_power* next_node_power = &rr_node_power[node->edge_sink_node(edge_idx)];
+            for (const RREdgeId& edge_idx : rr_graph.node_out_edges(node)) {
+                if (rr_graph.edge_sink_node(edge_idx) != RRNodeId::INVALID()) {
+                    RRNodeId next_node = rr_graph.edge_sink_node(edge_idx);
+                    t_rr_node_power* next_node_power = &rr_node_power[next_node];
 
-                    switch (next_node->type()) {
+                    switch (rr_graph.node_type(next_node)) {
                         case CHANX:
                         case CHANY:
                         case IPIN:
@@ -837,9 +838,9 @@ static void power_usage_routing(t_power_usage* power_usage,
                             next_node_power->in_dens[next_node_power->num_inputs] = clb_net_density(node_power->net_num);
                             next_node_power->in_prob[next_node_power->num_inputs] = clb_net_prob(node_power->net_num);
                             next_node_power->num_inputs++;
-                            if (next_node_power->num_inputs > next_node->fan_in()) {
+                            if (next_node_power->num_inputs > rr_graph.node_in_edges(next_node).size()) {
                                 VTR_LOG("%d %d\n", next_node_power->num_inputs,
-                                        next_node->fan_in());
+                                        rr_graph.node_in_edges(next_node).size());
                                 fflush(nullptr);
                                 VTR_ASSERT(0);
                             }
@@ -855,9 +856,9 @@ static void power_usage_routing(t_power_usage* power_usage,
     }
 
     /* Calculate power of all routing entities */
-    for (size_t rr_node_idx = 0; rr_node_idx < device_ctx.rr_nodes.size(); rr_node_idx++) {
+    for (const RRNodeId& rr_node_idx : device_ctx.rr_graph.nodes()) {
         t_power_usage sub_power_usage;
-        auto node = &device_ctx.rr_nodes[rr_node_idx];
+        const RRGraph& rr_graph = device_ctx.rr_graph;
         t_rr_node_power* node_power = &rr_node_power[rr_node_idx];
         float C_wire;
         float buffer_size;
@@ -866,7 +867,7 @@ static void power_usage_routing(t_power_usage* power_usage,
         //float C_per_seg_split;
         int wire_length;
 
-        switch (node->type()) {
+        switch (rr_graph.node_type(rr_node_idx)) {
             case SOURCE:
             case SINK:
             case OPIN:
@@ -877,13 +878,13 @@ static void power_usage_routing(t_power_usage* power_usage,
                  *  - Driver (accounted for at end of CHANX/Y - see below)
                  *  - Multiplexor */
 
-                if (node->fan_in()) {
+                if (rr_graph.node_in_edges(rr_node_idx).size()) {
                     VTR_ASSERT(node_power->in_dens);
                     VTR_ASSERT(node_power->in_prob);
 
                     /* Multiplexor */
                     power_usage_mux_multilevel(&sub_power_usage,
-                                               power_get_mux_arch(node->fan_in(),
+                                               power_get_mux_arch(rr_graph.node_in_edges(rr_node_idx).size(),
                                                                   power_ctx.arch->mux_transistor_size),
                                                node_power->in_prob, node_power->in_dens,
                                                node_power->selected_input, true,
@@ -904,19 +905,19 @@ static void power_usage_routing(t_power_usage* power_usage,
                 VTR_ASSERT(node_power->in_prob);
 
                 wire_length = 0;
-                if (node->type() == CHANX) {
-                    wire_length = node->xhigh() - node->xlow() + 1;
-                } else if (node->type() == CHANY) {
-                    wire_length = node->yhigh() - node->ylow() + 1;
+                if (rr_graph.node_type(rr_node_idx) == CHANX) {
+                    wire_length = rr_graph.node_xhigh(rr_node_idx) - rr_graph.node_xlow(rr_node_idx) + 1;
+                } else if (rr_graph.node_type(rr_node_idx) == CHANY) {
+                    wire_length = rr_graph.node_yhigh(rr_node_idx) - rr_graph.node_ylow(rr_node_idx) + 1;
                 }
                 C_wire = wire_length
-                         * segment_inf[device_ctx.rr_indexed_data[node->cost_index()].seg_index].Cmetal;
+                         * segment_inf[device_ctx.rr_indexed_data[rr_graph.node_cost_index(rr_node_idx)].seg_index].Cmetal;
                 //(double)power_ctx.commonly_used->tile_length);
-                VTR_ASSERT(node_power->selected_input < node->fan_in());
+                VTR_ASSERT(node_power->selected_input < rr_graph.node_in_edges(rr_node_idx).size());
 
                 /* Multiplexor */
                 power_usage_mux_multilevel(&sub_power_usage,
-                                           power_get_mux_arch(node->fan_in(),
+                                           power_get_mux_arch(rr_graph.node_in_edges(rr_node_idx).size(),
                                                               power_ctx.arch->mux_transistor_size),
                                            node_power->in_prob, node_power->in_dens,
                                            node_power->selected_input, true, power_ctx.solution_inf.T_crit);
@@ -979,10 +980,10 @@ static void power_usage_routing(t_power_usage* power_usage,
                 /* Determine types of switches that this wire drives */
                 connectionbox_fanout = 0;
                 switchbox_fanout = 0;
-                for (t_edge_size iedge = 0; iedge < node->num_edges(); iedge++) {
-                    if (node->edge_switch(iedge) == routing_arch->wire_to_rr_ipin_switch) {
+                for (const RREdgeId& iedge : rr_graph.node_out_edges(rr_node_idx)) {
+                    if ((short)size_t(rr_graph.edge_switch(iedge)) == routing_arch->wire_to_rr_ipin_switch) {
                         connectionbox_fanout++;
-                    } else if (node->edge_switch(iedge) == routing_arch->delayless_switch) {
+                    } else if ((short)size_t(rr_graph.edge_switch(iedge)) == routing_arch->delayless_switch) {
                         /* Do nothing */
                     } else {
                         switchbox_fanout++;
@@ -1191,9 +1192,8 @@ void power_routing_init(const t_det_routing_arch* routing_arch) {
     }
 
     /* Initialize RR Graph Structures */
-    rr_node_power = (t_rr_node_power*)vtr::calloc(device_ctx.rr_nodes.size(),
-                                                  sizeof(t_rr_node_power));
-    for (size_t rr_node_idx = 0; rr_node_idx < device_ctx.rr_nodes.size(); rr_node_idx++) {
+    rr_node_power.resize(device_ctx.rr_graph.nodes().size());
+    for (const RRNodeId& rr_node_idx : device_ctx.rr_graph.nodes()) {
         rr_node_power[rr_node_idx].driver_switch_type = OPEN;
     }
 
@@ -1202,40 +1202,40 @@ void power_routing_init(const t_det_routing_arch* routing_arch) {
     max_IPIN_fanin = 0;
     max_seg_to_seg_fanout = 0;
     max_seg_to_IPIN_fanout = 0;
-    for (size_t rr_node_idx = 0; rr_node_idx < device_ctx.rr_nodes.size(); rr_node_idx++) {
+    for (const RRNodeId& rr_node_idx : device_ctx.rr_graph.nodes()) {
         int fanout_to_IPIN = 0;
         int fanout_to_seg = 0;
-        auto node = &device_ctx.rr_nodes[rr_node_idx];
+        const RRGraph& rr_graph = device_ctx.rr_graph;
         t_rr_node_power* node_power = &rr_node_power[rr_node_idx];
 
-        switch (node->type()) {
+        switch (rr_graph.node_type(rr_node_idx)) {
             case IPIN:
                 max_IPIN_fanin = std::max(max_IPIN_fanin,
-                                          static_cast<int>(node->fan_in()));
-                max_fanin = std::max(max_fanin, static_cast<int>(node->fan_in()));
+                                          static_cast<int>(rr_graph.node_in_edges(rr_node_idx).size()));
+                max_fanin = std::max(max_fanin, static_cast<int>(rr_graph.node_in_edges(rr_node_idx).size()));
 
-                node_power->in_dens = (float*)vtr::calloc(node->fan_in(),
+                node_power->in_dens = (float*)vtr::calloc(rr_graph.node_in_edges(rr_node_idx).size(),
                                                           sizeof(float));
-                node_power->in_prob = (float*)vtr::calloc(node->fan_in(),
+                node_power->in_prob = (float*)vtr::calloc(rr_graph.node_in_edges(rr_node_idx).size(),
                                                           sizeof(float));
                 break;
             case CHANX:
             case CHANY:
-                for (t_edge_size iedge = 0; iedge < node->num_edges(); iedge++) {
-                    if (node->edge_switch(iedge) == routing_arch->wire_to_rr_ipin_switch) {
+                for (const RREdgeId& iedge : rr_graph.node_out_edges(rr_node_idx)) {
+                    if ((short)size_t(rr_graph.edge_switch(iedge)) == routing_arch->wire_to_rr_ipin_switch) {
                         fanout_to_IPIN++;
-                    } else if (node->edge_switch(iedge) != routing_arch->delayless_switch) {
+                    } else if ((short)size_t(rr_graph.edge_switch(iedge)) != routing_arch->delayless_switch) {
                         fanout_to_seg++;
                     }
                 }
                 max_seg_to_IPIN_fanout = std::max(max_seg_to_IPIN_fanout,
                                                   fanout_to_IPIN);
                 max_seg_to_seg_fanout = std::max(max_seg_to_seg_fanout, fanout_to_seg);
-                max_fanin = std::max(max_fanin, static_cast<int>(node->fan_in()));
+                max_fanin = std::max(max_fanin, static_cast<int>(rr_graph.node_in_edges(rr_node_idx).size()));
 
-                node_power->in_dens = (float*)vtr::calloc(node->fan_in(),
+                node_power->in_dens = (float*)vtr::calloc(rr_graph.node_in_edges(rr_node_idx).size(),
                                                           sizeof(float));
-                node_power->in_prob = (float*)vtr::calloc(node->fan_in(),
+                node_power->in_prob = (float*)vtr::calloc(rr_graph.node_in_edges(rr_node_idx).size(),
                                                           sizeof(float));
                 break;
             default:
@@ -1253,15 +1253,15 @@ void power_routing_init(const t_det_routing_arch* routing_arch) {
 #endif
 
     /* Populate driver switch type */
-    for (size_t rr_node_idx = 0; rr_node_idx < device_ctx.rr_nodes.size(); rr_node_idx++) {
-        auto node = &device_ctx.rr_nodes[rr_node_idx];
+    for (const RRNodeId& rr_node_idx : device_ctx.rr_graph.nodes()) {
+        const RRGraph& rr_graph = device_ctx.rr_graph;
 
-        for (t_edge_size edge_idx = 0; edge_idx < node->num_edges(); edge_idx++) {
-            if (node->edge_sink_node(edge_idx) != OPEN) {
-                if (rr_node_power[node->edge_sink_node(edge_idx)].driver_switch_type == OPEN) {
-                    rr_node_power[node->edge_sink_node(edge_idx)].driver_switch_type = node->edge_switch(edge_idx);
+        for (const RREdgeId& edge_idx : rr_graph.node_out_edges(rr_node_idx)) {
+            if (rr_graph.edge_sink_node(edge_idx) != RRNodeId::INVALID()) {
+                if (rr_node_power[rr_graph.edge_sink_node(edge_idx)].driver_switch_type == OPEN) {
+                    rr_node_power[rr_graph.edge_sink_node(edge_idx)].driver_switch_type = (short)size_t(rr_graph.edge_switch(edge_idx));
                 } else {
-                    VTR_ASSERT(rr_node_power[node->edge_sink_node(edge_idx)].driver_switch_type == node->edge_switch(edge_idx));
+                    VTR_ASSERT(rr_node_power[rr_graph.edge_sink_node(edge_idx)].driver_switch_type == (short)size_t(rr_graph.edge_switch(edge_idx)));
                 }
             }
         }
@@ -1269,14 +1269,14 @@ void power_routing_init(const t_det_routing_arch* routing_arch) {
 
     /* Find Max Fanout of Routing Buffer	 */
     t_edge_size max_seg_fanout = 0;
-    for (size_t rr_node_idx = 0; rr_node_idx < device_ctx.rr_nodes.size(); rr_node_idx++) {
-        auto node = &device_ctx.rr_nodes[rr_node_idx];
+    for (const RRNodeId& rr_node_idx : device_ctx.rr_graph.nodes()) {
+        const RRGraph& rr_graph = device_ctx.rr_graph;
 
-        switch (node->type()) {
+        switch (rr_graph.node_type(rr_node_idx)) {
             case CHANX:
             case CHANY:
-                if (node->num_edges() > max_seg_fanout) {
-                    max_seg_fanout = node->num_edges();
+                if (rr_graph.node_out_edges(rr_node_idx).size() > max_seg_fanout) {
+                    max_seg_fanout = rr_graph.node_out_edges(rr_node_idx).size();
                 }
                 break;
             default:
@@ -1357,15 +1357,15 @@ bool power_uninit() {
     auto& power_ctx = g_vpr_ctx.power();
     bool error = false;
 
-    for (size_t rr_node_idx = 0; rr_node_idx < device_ctx.rr_nodes.size(); rr_node_idx++) {
-        auto node = &device_ctx.rr_nodes[rr_node_idx];
+    for (const RRNodeId& rr_node_idx : device_ctx.rr_graph.nodes()) {
+        const RRGraph& rr_graph = device_ctx.rr_graph;
         t_rr_node_power* node_power = &rr_node_power[rr_node_idx];
 
-        switch (node->type()) {
+        switch (rr_graph.node_type(rr_node_idx)) {
             case CHANX:
             case CHANY:
             case IPIN:
-                if (node->fan_in()) {
+                if (rr_graph.node_in_edges(rr_node_idx).size()) {
                     free(node_power->in_dens);
                     free(node_power->in_prob);
                 }
@@ -1375,7 +1375,7 @@ bool power_uninit() {
                 break;
         }
     }
-    free(rr_node_power);
+    rr_node_power.clear();
 
     /* Free mux architectures */
     for (std::map<float, t_power_mux_info*>::iterator it = power_ctx.commonly_used->mux_info.begin();

From bc7988bb9ed011cd98751cc904565c9808cfb6fe Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 1 Feb 2020 13:19:47 -0700
Subject: [PATCH 070/645] check_route adopt RRGraph object

---
 vpr/src/base/vpr_types.h         |  10 +-
 vpr/src/route/check_route.cpp    | 158 ++++++++++++++++---------------
 vpr/src/route/check_rr_graph.cpp |  46 ++++-----
 vpr/src/route/check_rr_graph.h   |   2 +-
 4 files changed, 110 insertions(+), 106 deletions(-)

diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h
index 15508a4f8..dee5fd7e6 100644
--- a/vpr/src/base/vpr_types.h
+++ b/vpr/src/base/vpr_types.h
@@ -1188,13 +1188,13 @@ struct t_net_routing_status {
 };
 
 struct t_node_edge {
-    t_node_edge(int fnode, int tnode) {
+    t_node_edge(const RRNodeId& fnode, const RRNodeId& tnode) {
         from_node = fnode;
         to_node = tnode;
     }
 
-    int from_node;
-    int to_node;
+    RRNodeId from_node;
+    RRNodeId to_node;
 
     //For std::set
     friend bool operator<(const t_node_edge& lhs, const t_node_edge& rhs) {
@@ -1204,7 +1204,7 @@ struct t_node_edge {
 
 //Non-configurably connected nodes and edges in the RR graph
 struct t_non_configurable_rr_sets {
-    std::set<std::set<int>> node_sets;
+    std::set<std::set<RRNodeId>> node_sets;
     std::set<std::set<t_node_edge>> edge_sets;
 };
 
@@ -1290,6 +1290,6 @@ class RouteStatus {
     int chan_width_ = -1;
 };
 
-typedef vtr::vector<ClusterBlockId, std::vector<std::vector<int>>> t_clb_opins_used; //[0..num_blocks-1][0..class-1][0..used_pins-1]
+typedef vtr::vector<ClusterBlockId, std::vector<std::vector<RRNodeId>>> t_clb_opins_used; //[0..num_blocks-1][0..class-1][0..used_pins-1]
 
 #endif
diff --git a/vpr/src/route/check_route.cpp b/vpr/src/route/check_route.cpp
index e9fa20673..9fa3aa2c6 100644
--- a/vpr/src/route/check_route.cpp
+++ b/vpr/src/route/check_route.cpp
@@ -17,13 +17,13 @@
 #include "route_tree_timing.h"
 
 /******************** Subroutines local to this module **********************/
-static void check_node_and_range(int inode, enum e_route_type route_type);
-static void check_source(int inode, ClusterNetId net_id);
-static void check_sink(int inode, ClusterNetId net_id, bool* pin_done);
+static void check_node_and_range(const RRNodeId& inode, enum e_route_type route_type);
+static void check_source(const RRNodeId& inode, ClusterNetId net_id);
+static void check_sink(const RRNodeId& inode, ClusterNetId net_id, bool* pin_done);
 static void check_switch(t_trace* tptr, int num_switch);
-static bool check_adjacent(int from_node, int to_node);
-static int chanx_chany_adjacent(int chanx_node, int chany_node);
-static void reset_flags(ClusterNetId inet, bool* connected_to_route);
+static bool check_adjacent(const RRNodeId& from_node, const RRNodeId& to_node);
+static int chanx_chany_adjacent(const RRNodeId& chanx_node, const RRNodeId& chany_node);
+static void reset_flags(ClusterNetId inet, vtr::vector<RRNodeId, bool>& connected_to_route);
 static void check_locally_used_clb_opins(const t_clb_opins_used& clb_opins_used_locally,
                                          enum e_route_type route_type);
 
@@ -39,10 +39,11 @@ void check_route(enum e_route_type route_type) {
      * oversubscribed (the occupancy of everything is recomputed from        *
      * scratch).                                                             */
 
-    int max_pins, inode, prev_node;
+    int max_pins;
+    RRNodeId inode, prev_node;
     unsigned int ipin;
     bool valid, connects;
-    bool* connected_to_route; /* [0 .. device_ctx.rr_nodes.size()-1] */
+    vtr::vector<RRNodeId, bool> connected_to_route; /* [0 .. device_ctx.rr_nodes.size()-1] */
     t_trace* tptr;
     bool* pin_done;
 
@@ -70,7 +71,7 @@ void check_route(enum e_route_type route_type) {
 
     auto non_configurable_rr_sets = identify_non_configurable_rr_sets();
 
-    connected_to_route = (bool*)vtr::calloc(device_ctx.rr_nodes.size(), sizeof(bool));
+    connected_to_route.resize(device_ctx.rr_graph.nodes().size(), false);
 
     max_pins = 0;
     for (auto net_id : cluster_ctx.clb_nlist.nets())
@@ -115,7 +116,7 @@ void check_route(enum e_route_type route_type) {
             if (prev_switch == OPEN) { //Start of a new branch
                 if (connected_to_route[inode] == false) {
                     VPR_ERROR(VPR_ERROR_ROUTE,
-                              "in check_route: node %d does not link into existing routing for net %d.\n", inode, size_t(net_id));
+                              "in check_route: node %d does not link into existing routing for net %d.\n", size_t(inode), size_t(net_id));
                 }
             } else { //Continuing along existing branch
                 connects = check_adjacent(prev_node, inode);
@@ -131,7 +132,7 @@ void check_route(enum e_route_type route_type) {
 
                 connected_to_route[inode] = true; /* Mark as in path. */
 
-                if (device_ctx.rr_nodes[inode].type() == SINK) {
+                if (device_ctx.rr_graph.node_type(inode) == SINK) {
                     check_sink(inode, net_id, pin_done);
                     num_sinks += 1;
                 }
@@ -165,24 +166,24 @@ void check_route(enum e_route_type route_type) {
     } /* End for each net */
 
     free(pin_done);
-    free(connected_to_route);
+    connected_to_route.clear();
     VTR_LOG("Completed routing consistency check successfully.\n");
     VTR_LOG("\n");
 }
 
 /* Checks that this SINK node is one of the terminals of inet, and marks   *
  * the appropriate pin as being reached.                                   */
-static void check_sink(int inode, ClusterNetId net_id, bool* pin_done) {
+static void check_sink(const RRNodeId& inode, ClusterNetId net_id, bool* pin_done) {
     auto& device_ctx = g_vpr_ctx.device();
     auto& cluster_ctx = g_vpr_ctx.clustering();
     auto& place_ctx = g_vpr_ctx.placement();
 
-    VTR_ASSERT(device_ctx.rr_nodes[inode].type() == SINK);
-    int i = device_ctx.rr_nodes[inode].xlow();
-    int j = device_ctx.rr_nodes[inode].ylow();
+    VTR_ASSERT(device_ctx.rr_graph.node_type(inode) == SINK);
+    int i = device_ctx.rr_graph.node_xlow(inode);
+    int j = device_ctx.rr_graph.node_ylow(inode);
     auto type = device_ctx.grid[i][j].type;
     /* For sinks, ptc_num is the class */
-    int ptc_num = device_ctx.rr_nodes[inode].ptc_num();
+    int ptc_num = device_ctx.rr_graph.node_ptc_num(inode);
     int ifound = 0;
 
     for (int iblk = 0; iblk < type->capacity; iblk++) {
@@ -215,26 +216,26 @@ static void check_sink(int inode, ClusterNetId net_id, bool* pin_done) {
                         "in check_sink: node %d does not connect to any terminal of net %s #%lu.\n"
                         "This error is usually caused by incorrectly specified logical equivalence in your architecture file.\n"
                         "You should try to respecify what pins are equivalent or turn logical equivalence off.\n",
-                        inode, cluster_ctx.clb_nlist.net_name(net_id).c_str(), size_t(net_id));
+                        size_t(inode), cluster_ctx.clb_nlist.net_name(net_id).c_str(), size_t(net_id));
     }
 }
 
 /* Checks that the node passed in is a valid source for this net. */
-static void check_source(int inode, ClusterNetId net_id) {
+static void check_source(const RRNodeId& inode, ClusterNetId net_id) {
     auto& device_ctx = g_vpr_ctx.device();
     auto& cluster_ctx = g_vpr_ctx.clustering();
     auto& place_ctx = g_vpr_ctx.placement();
 
-    t_rr_type rr_type = device_ctx.rr_nodes[inode].type();
+    t_rr_type rr_type = device_ctx.rr_graph.node_type(inode);
     if (rr_type != SOURCE) {
         VPR_FATAL_ERROR(VPR_ERROR_ROUTE,
                         "in check_source: net %d begins with a node of type %d.\n", size_t(net_id), rr_type);
     }
 
-    int i = device_ctx.rr_nodes[inode].xlow();
-    int j = device_ctx.rr_nodes[inode].ylow();
+    int i = device_ctx.rr_graph.node_xlow(inode);
+    int j = device_ctx.rr_graph.node_ylow(inode);
     /* for sinks and sources, ptc_num is class */
-    int ptc_num = device_ctx.rr_nodes[inode].ptc_num();
+    int ptc_num = device_ctx.rr_graph.node_ptc_num(inode);
     /* First node_block for net is the source */
     ClusterBlockId blk_id = cluster_ctx.clb_nlist.net_driver_block(net_id);
     auto type = device_ctx.grid[i][j].type;
@@ -259,7 +260,7 @@ static void check_switch(t_trace* tptr, int num_switch) {
     /* Checks that the switch leading from this traceback element to the next *
      * one is a legal switch type.                                            */
 
-    int inode;
+    RRNodeId inode;
     short switch_type;
 
     auto& device_ctx = g_vpr_ctx.device();
@@ -267,12 +268,12 @@ static void check_switch(t_trace* tptr, int num_switch) {
     inode = tptr->index;
     switch_type = tptr->iswitch;
 
-    if (device_ctx.rr_nodes[inode].type() != SINK) {
+    if (device_ctx.rr_graph.node_type(inode) != SINK) {
         if (switch_type >= num_switch) {
             VPR_FATAL_ERROR(VPR_ERROR_ROUTE,
                             "in check_switch: rr_node %d left via switch type %d.\n"
                             "\tSwitch type is out of range.\n",
-                            inode, switch_type);
+                            size_t(inode), switch_type);
         }
     }
 
@@ -283,19 +284,19 @@ static void check_switch(t_trace* tptr, int num_switch) {
 
         if (switch_type != OPEN) {
             VPR_FATAL_ERROR(VPR_ERROR_ROUTE,
-                            "in check_switch: rr_node %d is a SINK, but attempts to use a switch of type %d.\n", inode, switch_type);
+                            "in check_switch: rr_node %d is a SINK, but attempts to use a switch of type %d.\n", size_t(inode), switch_type);
         }
     }
 }
 
-static void reset_flags(ClusterNetId inet, bool* connected_to_route) {
+static void reset_flags(ClusterNetId inet, vtr::vector<RRNodeId, bool>& connected_to_route) {
     /* This routine resets the flags of all the channel segments contained *
      * in the traceback of net inet to 0.  This allows us to check the     *
      * next net for connectivity (and the default state of the flags       *
      * should always be zero after they have been used).                   */
 
     t_trace* tptr;
-    int inode;
+    RRNodeId inode;
 
     auto& route_ctx = g_vpr_ctx.routing();
 
@@ -308,7 +309,7 @@ static void reset_flags(ClusterNetId inet, bool* connected_to_route) {
     }
 }
 
-static bool check_adjacent(int from_node, int to_node) {
+static bool check_adjacent(const RRNodeId& from_node, const RRNodeId& to_node) {
     /* This routine checks if the rr_node to_node is reachable from from_node.   *
      * It returns true if is reachable and false if it is not.  Check_node has   *
      * already been used to verify that both nodes are valid rr_nodes, so only   *
@@ -327,8 +328,8 @@ static bool check_adjacent(int from_node, int to_node) {
 
     reached = false;
 
-    for (t_edge_size iconn = 0; iconn < device_ctx.rr_nodes[from_node].num_edges(); iconn++) {
-        if (device_ctx.rr_nodes[from_node].edge_sink_node(iconn) == to_node) {
+    for (const RREdgeId& iconn : device_ctx.rr_graph.node_out_edges(from_node)) {
+        if (device_ctx.rr_graph.edge_sink_node(iconn) == to_node) {
             reached = true;
             break;
         }
@@ -343,18 +344,18 @@ static bool check_adjacent(int from_node, int to_node) {
 
     num_adj = 0;
 
-    from_type = device_ctx.rr_nodes[from_node].type();
-    from_xlow = device_ctx.rr_nodes[from_node].xlow();
-    from_ylow = device_ctx.rr_nodes[from_node].ylow();
-    from_xhigh = device_ctx.rr_nodes[from_node].xhigh();
-    from_yhigh = device_ctx.rr_nodes[from_node].yhigh();
-    from_ptc = device_ctx.rr_nodes[from_node].ptc_num();
-    to_type = device_ctx.rr_nodes[to_node].type();
-    to_xlow = device_ctx.rr_nodes[to_node].xlow();
-    to_ylow = device_ctx.rr_nodes[to_node].ylow();
-    to_xhigh = device_ctx.rr_nodes[to_node].xhigh();
-    to_yhigh = device_ctx.rr_nodes[to_node].yhigh();
-    to_ptc = device_ctx.rr_nodes[to_node].ptc_num();
+    from_type = device_ctx.rr_graph.node_type(from_node);
+    from_xlow = device_ctx.rr_graph.node_xlow(from_node);
+    from_ylow = device_ctx.rr_graph.node_ylow(from_node);
+    from_xhigh = device_ctx.rr_graph.node_xhigh(from_node);
+    from_yhigh = device_ctx.rr_graph.node_yhigh(from_node);
+    from_ptc = device_ctx.rr_graph.node_ptc_num(from_node);
+    to_type = device_ctx.rr_graph.node_type(to_node);
+    to_xlow = device_ctx.rr_graph.node_xlow(to_node);
+    to_ylow = device_ctx.rr_graph.node_ylow(to_node);
+    to_xhigh = device_ctx.rr_graph.node_xhigh(to_node);
+    to_yhigh = device_ctx.rr_graph.node_yhigh(to_node);
+    to_ptc = device_ctx.rr_graph.node_ptc_num(to_node);
 
     switch (from_type) {
         case SOURCE:
@@ -411,8 +412,8 @@ static bool check_adjacent(int from_node, int to_node) {
             if (to_type == IPIN) {
                 num_adj += 1; //adjacent
             } else if (to_type == CHANX) {
-                from_xhigh = device_ctx.rr_nodes[from_node].xhigh();
-                to_xhigh = device_ctx.rr_nodes[to_node].xhigh();
+                from_xhigh = device_ctx.rr_graph.node_xhigh(from_node);
+                to_xhigh = device_ctx.rr_graph.node_xhigh(to_node);
                 if (from_ylow == to_ylow) {
                     /* UDSD Modification by WMF Begin */
                     /*For Fs > 3, can connect to overlapping wire segment */
@@ -436,7 +437,7 @@ static bool check_adjacent(int from_node, int to_node) {
                 num_adj += chanx_chany_adjacent(from_node, to_node);
             } else {
                 VPR_FATAL_ERROR(VPR_ERROR_ROUTE,
-                                "in check_adjacent: %d and %d are not adjacent", from_node, to_node);
+                                "in check_adjacent: %d and %d are not adjacent", size_t(from_node), size_t(to_node));
             }
             break;
 
@@ -444,8 +445,8 @@ static bool check_adjacent(int from_node, int to_node) {
             if (to_type == IPIN) {
                 num_adj += 1; //adjacent
             } else if (to_type == CHANY) {
-                from_yhigh = device_ctx.rr_nodes[from_node].yhigh();
-                to_yhigh = device_ctx.rr_nodes[to_node].yhigh();
+                from_yhigh = device_ctx.rr_graph.node_yhigh(from_node);
+                to_yhigh = device_ctx.rr_graph.node_yhigh(to_node);
                 if (from_xlow == to_xlow) {
                     /* UDSD Modification by WMF Begin */
                     if (to_yhigh == from_ylow - 1 || from_yhigh == to_ylow - 1) {
@@ -468,7 +469,7 @@ static bool check_adjacent(int from_node, int to_node) {
                 num_adj += chanx_chany_adjacent(to_node, from_node);
             } else {
                 VPR_FATAL_ERROR(VPR_ERROR_ROUTE,
-                                "in check_adjacent: %d and %d are not adjacent", from_node, to_node);
+                                "in check_adjacent: %d and %d are not adjacent", size_t(from_node), size_t(to_node));
             }
             break;
 
@@ -486,7 +487,7 @@ static bool check_adjacent(int from_node, int to_node) {
     return false; //Should not reach here once thrown
 }
 
-static int chanx_chany_adjacent(int chanx_node, int chany_node) {
+static int chanx_chany_adjacent(const RRNodeId& chanx_node, const RRNodeId& chany_node) {
     /* Returns 1 if the specified CHANX and CHANY nodes are adjacent, 0         *
      * otherwise.                                                               */
 
@@ -495,13 +496,13 @@ static int chanx_chany_adjacent(int chanx_node, int chany_node) {
 
     auto& device_ctx = g_vpr_ctx.device();
 
-    chanx_y = device_ctx.rr_nodes[chanx_node].ylow();
-    chanx_xlow = device_ctx.rr_nodes[chanx_node].xlow();
-    chanx_xhigh = device_ctx.rr_nodes[chanx_node].xhigh();
+    chanx_y =     device_ctx.rr_graph.node_ylow(chanx_node);
+    chanx_xlow =  device_ctx.rr_graph.node_xlow(chanx_node);
+    chanx_xhigh = device_ctx.rr_graph.node_xhigh(chanx_node);
 
-    chany_x = device_ctx.rr_nodes[chany_node].xlow();
-    chany_ylow = device_ctx.rr_nodes[chany_node].ylow();
-    chany_yhigh = device_ctx.rr_nodes[chany_node].yhigh();
+    chany_x =     device_ctx.rr_graph.node_xlow(chany_node);
+    chany_ylow =  device_ctx.rr_graph.node_ylow(chany_node);
+    chany_yhigh = device_ctx.rr_graph.node_yhigh(chany_node);
 
     if (chany_ylow > chanx_y + 1 || chany_yhigh < chanx_y)
         return (0);
@@ -519,7 +520,8 @@ void recompute_occupancy_from_scratch() {
      * brute force recompute from scratch that is useful for sanity checking.
      */
 
-    int inode, iclass, ipin, num_local_opins;
+    int iclass, ipin, num_local_opins;
+    RRNodeId inode;
     t_trace* tptr;
 
     auto& route_ctx = g_vpr_ctx.mutable_routing();
@@ -528,8 +530,9 @@ void recompute_occupancy_from_scratch() {
 
     /* First set the occupancy of everything to zero. */
 
-    for (size_t inode_idx = 0; inode_idx < device_ctx.rr_nodes.size(); inode_idx++)
+    for (const RRNodeId& inode_idx : device_ctx.rr_graph.nodes()) {
         route_ctx.rr_node_route_inf[inode_idx].set_occ(0);
+    }
 
     /* Now go through each net and count the tracks and pins used everywhere */
 
@@ -575,7 +578,8 @@ static void check_locally_used_clb_opins(const t_clb_opins_used& clb_opins_used_
     /* Checks that enough OPINs on CLBs have been set aside (used up) to make a *
      * legal routing if subblocks connect to OPINs directly.                    */
 
-    int iclass, num_local_opins, inode, ipin;
+    int iclass, num_local_opins, ipin;
+    RRNodeId inode;
     t_rr_type rr_type;
 
     auto& cluster_ctx = g_vpr_ctx.clustering();
@@ -592,35 +596,35 @@ static void check_locally_used_clb_opins(const t_clb_opins_used& clb_opins_used_
 
                 /* Now check that node is an OPIN of the right type. */
 
-                rr_type = device_ctx.rr_nodes[inode].type();
+                rr_type = device_ctx.rr_graph.node_type(inode);
                 if (rr_type != OPIN) {
                     VPR_FATAL_ERROR(VPR_ERROR_ROUTE,
                                     "in check_locally_used_opins: block #%lu (%s)\n"
                                     "\tClass %d local OPIN is wrong rr_type -- rr_node #%d of type %d.\n",
-                                    size_t(blk_id), cluster_ctx.clb_nlist.block_name(blk_id).c_str(), iclass, inode, rr_type);
+                                    size_t(blk_id), cluster_ctx.clb_nlist.block_name(blk_id).c_str(), iclass, size_t(inode), rr_type);
                 }
 
-                ipin = device_ctx.rr_nodes[inode].ptc_num();
+                ipin = device_ctx.rr_graph.node_ptc_num(inode);
                 if (physical_tile_type(blk_id)->pin_class[ipin] != iclass) {
                     VPR_FATAL_ERROR(VPR_ERROR_ROUTE,
                                     "in check_locally_used_opins: block #%lu (%s):\n"
                                     "\tExpected class %d local OPIN has class %d -- rr_node #: %d.\n",
-                                    size_t(blk_id), cluster_ctx.clb_nlist.block_name(blk_id).c_str(), iclass, physical_tile_type(blk_id)->pin_class[ipin], inode);
+                                    size_t(blk_id), cluster_ctx.clb_nlist.block_name(blk_id).c_str(), iclass, physical_tile_type(blk_id)->pin_class[ipin], size_t(inode));
                 }
             }
         }
     }
 }
 
-static void check_node_and_range(int inode, enum e_route_type route_type) {
+static void check_node_and_range(const RRNodeId& inode, enum e_route_type route_type) {
     /* Checks that inode is within the legal range, then calls check_node to    *
      * check that everything else about the node is OK.                         */
 
     auto& device_ctx = g_vpr_ctx.device();
 
-    if (inode < 0 || inode >= (int)device_ctx.rr_nodes.size()) {
+    if (false == device_ctx.rr_graph.valid_node_id(inode)) {
         VPR_FATAL_ERROR(VPR_ERROR_ROUTE,
-                        "in check_node_and_range: rr_node #%d is out of legal, range (0 to %d).\n", inode, device_ctx.rr_nodes.size() - 1);
+                        "in check_node_and_range: rr_node #%d is out of legal, range (0 to %d).\n", size_t(inode), device_ctx.rr_graph.nodes().size() - 1);
     }
     check_rr_node(inode, route_type, device_ctx);
 }
@@ -637,16 +641,16 @@ static bool check_non_configurable_edges(ClusterNetId net, const t_non_configura
 
     //Collect all the edges used by this net's routing
     std::set<t_node_edge> routing_edges;
-    std::set<int> routing_nodes;
+    std::set<RRNodeId> routing_nodes;
     for (t_trace* trace = head; trace != nullptr; trace = trace->next) {
-        int inode = trace->index;
+        RRNodeId inode = trace->index;
 
         routing_nodes.insert(inode);
 
         if (trace->iswitch == OPEN) {
             continue; //End of branch
         } else if (trace->next) {
-            int inode_next = trace->next->index;
+            RRNodeId inode_next = trace->next->index;
 
             t_node_edge edge = {inode, inode_next};
 
@@ -668,7 +672,7 @@ static bool check_non_configurable_edges(ClusterNetId net, const t_non_configura
     //within a set is used by the routing
     for (const auto& rr_nodes : non_configurable_rr_sets.node_sets) {
         //Compute the intersection of the routing and current non-configurable nodes set
-        std::vector<int> intersection;
+        std::vector<RRNodeId> intersection;
         std::set_intersection(routing_nodes.begin(), routing_nodes.end(),
                               rr_nodes.begin(), rr_nodes.end(),
                               std::back_inserter(intersection));
@@ -683,7 +687,7 @@ static bool check_non_configurable_edges(ClusterNetId net, const t_non_configura
                 //Compute the difference to identify the missing nodes
                 //for detailed error reporting -- the nodes
                 //which are in rr_nodes but not in routing_nodes.
-                std::vector<int> difference;
+                std::vector<RRNodeId> difference;
                 std::set_difference(rr_nodes.begin(), rr_nodes.end(),
                                     routing_nodes.begin(), routing_nodes.end(),
                                     std::back_inserter(difference));
@@ -762,7 +766,7 @@ static bool check_non_configurable_edges(ClusterNetId net, const t_non_configura
 
                 for (t_node_edge missing_edge : dedupped_difference) {
                     msg += vtr::string_fmt("  Expected RR Node: %d and RR Node: %d to be non-configurably connected, but edge missing from routing:\n",
-                                           missing_edge.from_node, missing_edge.to_node);
+                                           size_t(missing_edge.from_node), size_t(missing_edge.to_node));
                     msg += vtr::string_fmt("    %s\n", describe_rr_node(missing_edge.from_node).c_str());
                     msg += vtr::string_fmt("    %s\n", describe_rr_node(missing_edge.to_node).c_str());
                 }
@@ -786,7 +790,7 @@ class StubFinder {
     bool CheckNet(ClusterNetId net);
 
     // Returns set of stub nodes.
-    const std::set<int>& stub_nodes() {
+    const std::set<RRNodeId>& stub_nodes() {
         return stub_nodes_;
     }
 
@@ -796,7 +800,7 @@ class StubFinder {
     // Set of stub nodes
     // Note this is an ordered set so that node output is sorted by node
     // id.
-    std::set<int> stub_nodes_;
+    std::set<RRNodeId> stub_nodes_;
 };
 
 //Cheks for stubs in a net's routing.
@@ -813,7 +817,7 @@ void check_net_for_stubs(ClusterNetId net) {
         auto& cluster_ctx = g_vpr_ctx.clustering();
         std::string msg = vtr::string_fmt("Route tree for net '%s' (#%zu) contains stub branches rooted at:\n",
                                           cluster_ctx.clb_nlist.net_name(net).c_str(), size_t(net));
-        for (int inode : stub_finder.stub_nodes()) {
+        for (const RRNodeId& inode : stub_finder.stub_nodes()) {
             msg += vtr::string_fmt("    %s\n", describe_rr_node(inode).c_str());
         }
 
@@ -837,7 +841,7 @@ bool StubFinder::RecurseTree(t_rt_node* rt_root) {
 
     if (rt_root->u.child_list == nullptr) {
         //If a leaf of the route tree is not a SINK, then it is a stub
-        if (device_ctx.rr_nodes[rt_root->inode].type() != SINK) {
+        if (device_ctx.rr_graph.node_type(rt_root->inode) != SINK) {
             return true; //It is the current root of this stub
         } else {
             return false;
diff --git a/vpr/src/route/check_rr_graph.cpp b/vpr/src/route/check_rr_graph.cpp
index 666099176..388915b01 100644
--- a/vpr/src/route/check_rr_graph.cpp
+++ b/vpr/src/route/check_rr_graph.cpp
@@ -14,7 +14,7 @@ static bool rr_node_is_global_clb_ipin(int inode);
 
 static void check_unbuffered_edges(int from_node);
 
-static bool has_adjacent_channel(const t_rr_node& node, const DeviceGrid& grid);
+static bool has_adjacent_channel(const RRGraph& rr_graph, const RRNodeId& node, const DeviceGrid& grid);
 
 static void check_rr_edge(int from_node, int from_edge, int to_node);
 
@@ -220,7 +220,7 @@ static bool rr_node_is_global_clb_ipin(int inode) {
     return type->is_ignored_pin[ipin];
 }
 
-void check_rr_node(int inode, enum e_route_type route_type, const DeviceContext& device_ctx) {
+void check_rr_node(const RRNodeId& inode, enum e_route_type route_type, const DeviceContext& device_ctx) {
     /* This routine checks that the rr_node is inside the grid and has a valid
      * pin number, etc.
      */
@@ -231,14 +231,14 @@ void check_rr_node(int inode, enum e_route_type route_type, const DeviceContext&
     int nodes_per_chan, tracks_per_node, num_edges, cost_index;
     float C, R;
 
-    rr_type = device_ctx.rr_nodes[inode].type();
-    xlow = device_ctx.rr_nodes[inode].xlow();
-    xhigh = device_ctx.rr_nodes[inode].xhigh();
-    ylow = device_ctx.rr_nodes[inode].ylow();
-    yhigh = device_ctx.rr_nodes[inode].yhigh();
-    ptc_num = device_ctx.rr_nodes[inode].ptc_num();
-    capacity = device_ctx.rr_nodes[inode].capacity();
-    cost_index = device_ctx.rr_nodes[inode].cost_index();
+    rr_type = device_ctx.rr_graph.node_type(inode);
+    xlow = device_ctx.rr_graph.node_xlow(inode);
+    xhigh = device_ctx.rr_graph.node_xhigh(inode);
+    ylow = device_ctx.rr_graph.node_ylow(inode);
+    yhigh = device_ctx.rr_graph.node_yhigh(inode);
+    ptc_num = device_ctx.rr_graph.node_ptc_num(inode);
+    capacity = device_ctx.rr_graph.node_capacity(inode);
+    cost_index = device_ctx.rr_graph.node_cost_index(inode);
     type = nullptr;
 
     const auto& grid = device_ctx.grid;
@@ -413,7 +413,7 @@ void check_rr_node(int inode, enum e_route_type route_type, const DeviceContext&
     }
 
     /* Check that the number of (out) edges is reasonable. */
-    num_edges = device_ctx.rr_nodes[inode].num_edges();
+    num_edges = device_ctx.rr_graph.node_out_edges(inode).size();
 
     if (rr_type != SINK && rr_type != IPIN) {
         if (num_edges <= 0) {
@@ -424,7 +424,7 @@ void check_rr_node(int inode, enum e_route_type route_type, const DeviceContext&
             //Don't worry about disconnect PINs which have no adjacent channels (i.e. on the device perimeter)
             bool check_for_out_edges = true;
             if (rr_type == IPIN || rr_type == OPIN) {
-                if (!has_adjacent_channel(device_ctx.rr_nodes[inode], device_ctx.grid)) {
+                if (!has_adjacent_channel(device_ctx.rr_graph, inode, device_ctx.grid)) {
                     check_for_out_edges = false;
                 }
             }
@@ -437,23 +437,23 @@ void check_rr_node(int inode, enum e_route_type route_type, const DeviceContext&
     } else if (rr_type == SINK) { /* SINK -- remove this check if feedthroughs allowed */
         if (num_edges != 0) {
             VPR_FATAL_ERROR(VPR_ERROR_ROUTE,
-                            "in check_rr_node: node %d is a sink, but has %d edges.\n", inode, num_edges);
+                            "in check_rr_node: node %d is a sink, but has %d edges.\n", size_t(inode), num_edges);
         }
     }
 
     /* Check that the capacitance and resistance are reasonable. */
-    C = device_ctx.rr_nodes[inode].C();
-    R = device_ctx.rr_nodes[inode].R();
+    C = device_ctx.rr_graph.node_C(inode);
+    R = device_ctx.rr_graph.node_R(inode);
 
     if (rr_type == CHANX || rr_type == CHANY) {
         if (C < 0. || R < 0.) {
             VPR_ERROR(VPR_ERROR_ROUTE,
-                      "in check_rr_node: node %d of type %d has R = %g and C = %g.\n", inode, rr_type, R, C);
+                      "in check_rr_node: node %d of type %d has R = %g and C = %g.\n", size_t(inode), rr_type, R, C);
         }
     } else {
         if (C != 0. || R != 0.) {
             VPR_ERROR(VPR_ERROR_ROUTE,
-                      "in check_rr_node: node %d of type %d has R = %g and C = %g.\n", inode, rr_type, R, C);
+                      "in check_rr_node: node %d of type %d has R = %g and C = %g.\n", size_t(inode), rr_type, R, C);
         }
     }
 }
@@ -513,13 +513,13 @@ static void check_unbuffered_edges(int from_node) {
     } /* End for all from_node edges */
 }
 
-static bool has_adjacent_channel(const t_rr_node& node, const DeviceGrid& grid) {
-    VTR_ASSERT(node.type() == IPIN || node.type() == OPIN);
+static bool has_adjacent_channel(const RRGraph& rr_graph, const RRNodeId& node, const DeviceGrid& grid) {
+    VTR_ASSERT(rr_graph.node_type(node) == IPIN || rr_graph.node_type(node) == OPIN);
 
-    if ((node.xlow() == 0 && node.side() != RIGHT)                          //left device edge connects only along block's right side
-        || (node.ylow() == int(grid.height() - 1) && node.side() != BOTTOM) //top device edge connects only along block's bottom side
-        || (node.xlow() == int(grid.width() - 1) && node.side() != LEFT)    //right deivce edge connects only along block's left side
-        || (node.ylow() == 0 && node.side() != TOP)                         //bottom deivce edge connects only along block's top side
+    if ((rr_graph.node_xlow(node) == 0 && rr_graph.node_side(node) != RIGHT)                          //left device edge connects only along block's right side
+        || (rr_graph.node_ylow(node) == int(grid.height() - 1) && rr_graph.node_side(node) != BOTTOM) //top device edge connects only along block's bottom side
+        || (rr_graph.node_xlow(node) == int(grid.width() - 1) && rr_graph.node_side(node) != LEFT)    //right deivce edge connects only along block's left side
+        || (rr_graph.node_ylow(node) == 0 && rr_graph.node_side(node) != TOP)                         //bottom deivce edge connects only along block's top side
     ) {
         return false;
     }
diff --git a/vpr/src/route/check_rr_graph.h b/vpr/src/route/check_rr_graph.h
index 5e7d69d2c..71d435e70 100644
--- a/vpr/src/route/check_rr_graph.h
+++ b/vpr/src/route/check_rr_graph.h
@@ -6,6 +6,6 @@ void check_rr_graph(const t_graph_type graph_type,
                     const DeviceGrid& grid,
                     const std::vector<t_physical_tile_type>& types);
 
-void check_rr_node(int inode, enum e_route_type route_type, const DeviceContext& device_ctx);
+void check_rr_node(const RRNodeId& inode, enum e_route_type route_type, const DeviceContext& device_ctx);
 
 #endif

From 3536cc8ed54d99c98159c189d07545b3cd235294 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 1 Feb 2020 14:17:02 -0700
Subject: [PATCH 071/645] check rr graph adopt RRGraph object

---
 vpr/src/route/check_rr_graph.cpp | 138 +++++++++++++++----------------
 1 file changed, 65 insertions(+), 73 deletions(-)

diff --git a/vpr/src/route/check_rr_graph.cpp b/vpr/src/route/check_rr_graph.cpp
index 388915b01..e7213a764 100644
--- a/vpr/src/route/check_rr_graph.cpp
+++ b/vpr/src/route/check_rr_graph.cpp
@@ -10,13 +10,13 @@
 
 /*********************** Subroutines local to this module *******************/
 
-static bool rr_node_is_global_clb_ipin(int inode);
+static bool rr_node_is_global_clb_ipin(const RRNodeId& inode);
 
-static void check_unbuffered_edges(int from_node);
+static void check_unbuffered_edges(const RRNodeId& from_node);
 
 static bool has_adjacent_channel(const RRGraph& rr_graph, const RRNodeId& node, const DeviceGrid& grid);
 
-static void check_rr_edge(int from_node, int from_edge, int to_node);
+static void check_rr_edge(const RREdgeId& from_edge, const RRNodeId& to_node);
 
 /************************ Subroutine definitions ****************************/
 
@@ -30,69 +30,67 @@ void check_rr_graph(const t_graph_type graph_type,
 
     auto& device_ctx = g_vpr_ctx.device();
 
-    auto total_edges_to_node = std::vector<int>(device_ctx.rr_nodes.size());
-    auto switch_types_from_current_to_node = std::vector<unsigned char>(device_ctx.rr_nodes.size());
+    auto total_edges_to_node = vtr::vector<RRNodeId, int>(device_ctx.rr_graph.nodes().size());
+    auto switch_types_from_current_to_node = vtr::vector<RRNodeId, unsigned char>(device_ctx.rr_graph.nodes().size());
     const int num_rr_switches = device_ctx.rr_switch_inf.size();
 
-    for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); inode++) {
-        device_ctx.rr_nodes[inode].validate();
+    for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) {
 
         /* Ignore any uninitialized rr_graph nodes */
-        if ((device_ctx.rr_nodes[inode].type() == SOURCE)
-            && (device_ctx.rr_nodes[inode].xlow() == 0) && (device_ctx.rr_nodes[inode].ylow() == 0)
-            && (device_ctx.rr_nodes[inode].xhigh() == 0) && (device_ctx.rr_nodes[inode].yhigh() == 0)) {
+        if ((device_ctx.rr_graph.node_type(inode) == SOURCE)
+            && (device_ctx.rr_graph.node_xlow(inode) == 0) && (device_ctx.rr_graph.node_ylow(inode) == 0)
+            && (device_ctx.rr_graph.node_xhigh(inode) == 0) && (device_ctx.rr_graph.node_yhigh(inode) == 0)) {
             continue;
         }
 
-        t_rr_type rr_type = device_ctx.rr_nodes[inode].type();
-        int num_edges = device_ctx.rr_nodes[inode].num_edges();
+        t_rr_type rr_type = device_ctx.rr_graph.node_type(inode);
 
         check_rr_node(inode, route_type, device_ctx);
 
         /* Check all the connectivity (edges, etc.) information.                    */
 
-        std::map<int, std::vector<int>> edges_from_current_to_node;
-        for (int iedge = 0; iedge < num_edges; iedge++) {
-            int to_node = device_ctx.rr_nodes[inode].edge_sink_node(iedge);
+        std::map<RRNodeId, std::vector<RREdgeId>> edges_from_current_to_node;
+        for (const RREdgeId& iedge : device_ctx.rr_graph.node_out_edges(inode)) {
+            RRNodeId to_node = device_ctx.rr_graph.edge_sink_node(iedge);
 
-            if (to_node < 0 || to_node >= (int)device_ctx.rr_nodes.size()) {
+            if (false == device_ctx.rr_graph.valid_node_id(to_node)) {
                 VPR_FATAL_ERROR(VPR_ERROR_ROUTE,
                                 "in check_rr_graph: node %d has an edge %d.\n"
                                 "\tEdge is out of range.\n",
-                                inode, to_node);
+                                size_t(inode), size_t(to_node));
             }
 
-            check_rr_edge(inode, iedge, to_node);
+            check_rr_edge(iedge, to_node);
 
             edges_from_current_to_node[to_node].push_back(iedge);
             total_edges_to_node[to_node]++;
 
-            auto switch_type = device_ctx.rr_nodes[inode].edge_switch(iedge);
+            auto switch_type = size_t(device_ctx.rr_graph.edge_switch(iedge));
 
-            if (switch_type < 0 || switch_type >= num_rr_switches) {
+            if (switch_type >= (size_t)num_rr_switches) {
                 VPR_FATAL_ERROR(VPR_ERROR_ROUTE,
                                 "in check_rr_graph: node %d has a switch type %d.\n"
                                 "\tSwitch type is out of range.\n",
-                                inode, switch_type);
+                                size_t(inode), switch_type);
             }
         } /* End for all edges of node. */
 
         //Check that multiple edges between the same from/to nodes make sense
-        for (int iedge = 0; iedge < num_edges; iedge++) {
-            int to_node = device_ctx.rr_nodes[inode].edge_sink_node(iedge);
+        for (const RREdgeId& iedge : device_ctx.rr_graph.node_out_edges(inode)) {
+            RRNodeId to_node = device_ctx.rr_graph.edge_sink_node(iedge);
 
             if (edges_from_current_to_node[to_node].size() == 1) continue; //Single edges are always OK
 
             VTR_ASSERT_MSG(edges_from_current_to_node[to_node].size() > 1, "Expect multiple edges");
 
-            t_rr_type to_rr_type = device_ctx.rr_nodes[to_node].type();
+            t_rr_type to_rr_type = device_ctx.rr_graph.node_type(to_node);
 
             //Only expect chan <-> chan connections to have multiple edges
             if ((to_rr_type != CHANX && to_rr_type != CHANY)
                 || (rr_type != CHANX && rr_type != CHANY)) {
                 VPR_ERROR(VPR_ERROR_ROUTE,
                           "in check_rr_graph: node %d (%s) connects to node %d (%s) %zu times - multi-connections only expected for CHAN->CHAN.\n",
-                          inode, rr_node_typename[rr_type], to_node, rr_node_typename[to_rr_type], edges_from_current_to_node[to_node].size());
+                          size_t(inode), rr_node_typename[rr_type], size_t(to_node), rr_node_typename[to_rr_type], edges_from_current_to_node[to_node].size());
             }
 
             //Between two wire segments
@@ -105,7 +103,7 @@ void check_rr_graph(const t_graph_type graph_type,
             //Identify any such edges with identical switches
             std::map<short, int> switch_counts;
             for (auto edge : edges_from_current_to_node[to_node]) {
-                auto edge_switch = device_ctx.rr_nodes[inode].edge_switch(edge);
+                auto edge_switch = size_t(device_ctx.rr_graph.edge_switch(edge));
 
                 switch_counts[edge_switch]++;
             }
@@ -117,7 +115,7 @@ void check_rr_graph(const t_graph_type graph_type,
                 auto switch_type = device_ctx.rr_switch_inf[kv.first].type();
 
                 VPR_ERROR(VPR_ERROR_ROUTE, "in check_rr_graph: node %d has %d redundant connections to node %d of switch type %d (%s)",
-                          inode, kv.second, to_node, kv.first, SWITCH_TYPE_STRINGS[size_t(switch_type)]);
+                          size_t(inode), kv.second, size_t(to_node), kv.first, SWITCH_TYPE_STRINGS[size_t(switch_type)]);
             }
         }
 
@@ -125,17 +123,17 @@ void check_rr_graph(const t_graph_type graph_type,
         check_unbuffered_edges(inode);
 
         //Check that all config/non-config edges are appropriately organized
-        for (auto edge : device_ctx.rr_nodes[inode].configurable_edges()) {
-            if (!device_ctx.rr_nodes[inode].edge_is_configurable(edge)) {
+        for (auto edge : device_ctx.rr_graph.node_configurable_out_edges(inode)) {
+            if (!device_ctx.rr_graph.edge_is_configurable(edge)) {
                 VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "in check_rr_graph: node %d edge %d is non-configurable, but in configurable edges",
-                                inode, edge);
+                                size_t(inode), size_t(edge));
             }
         }
 
-        for (auto edge : device_ctx.rr_nodes[inode].non_configurable_edges()) {
-            if (device_ctx.rr_nodes[inode].edge_is_configurable(edge)) {
+        for (auto edge : device_ctx.rr_graph.node_non_configurable_out_edges(inode)) {
+            if (device_ctx.rr_graph.edge_is_configurable(edge)) {
                 VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "in check_rr_graph: node %d edge %d is configurable, but in non-configurable edges",
-                                inode, edge);
+                                size_t(inode), size_t(edge));
             }
         }
 
@@ -145,8 +143,8 @@ void check_rr_graph(const t_graph_type graph_type,
      * now I check that everything is reachable.                                */
     bool is_fringe_warning_sent = false;
 
-    for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); inode++) {
-        t_rr_type rr_type = device_ctx.rr_nodes[inode].type();
+    for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) {
+        t_rr_type rr_type = device_ctx.rr_graph.node_type(inode);
 
         if (rr_type != SOURCE) {
             if (total_edges_to_node[inode] < 1 && !rr_node_is_global_clb_ipin(inode)) {
@@ -156,7 +154,7 @@ void check_rr_graph(const t_graph_type graph_type,
                  */
                 bool is_chain = false;
                 if (rr_type == IPIN) {
-                    t_physical_tile_type_ptr type = device_ctx.grid[device_ctx.rr_nodes[inode].xlow()][device_ctx.rr_nodes[inode].ylow()].type;
+                    t_physical_tile_type_ptr type = device_ctx.grid[device_ctx.rr_graph.node_xlow(inode)][device_ctx.rr_graph.node_ylow(inode)].type;
                     for (const t_fc_specification& fc_spec : types[type->index].fc_specs) {
                         if (fc_spec.fc_value == 0 && fc_spec.seg_index == 0) {
                             is_chain = true;
@@ -164,45 +162,43 @@ void check_rr_graph(const t_graph_type graph_type,
                     }
                 }
 
-                const auto& node = device_ctx.rr_nodes[inode];
-
-                bool is_fringe = ((device_ctx.rr_nodes[inode].xlow() == 1)
-                                  || (device_ctx.rr_nodes[inode].ylow() == 1)
-                                  || (device_ctx.rr_nodes[inode].xhigh() == int(grid.width()) - 2)
-                                  || (device_ctx.rr_nodes[inode].yhigh() == int(grid.height()) - 2));
-                bool is_wire = (device_ctx.rr_nodes[inode].type() == CHANX
-                                || device_ctx.rr_nodes[inode].type() == CHANY);
+                bool is_fringe = ((device_ctx.rr_graph.node_xlow(inode) == 1)
+                                  || (device_ctx.rr_graph.node_ylow(inode) == 1)
+                                  || (device_ctx.rr_graph.node_xhigh(inode) == int(grid.width()) - 2)
+                                  || (device_ctx.rr_graph.node_yhigh(inode) == int(grid.height()) - 2));
+                bool is_wire = (device_ctx.rr_graph.node_type(inode) == CHANX
+                                || device_ctx.rr_graph.node_type(inode) == CHANY);
 
                 if (!is_chain && !is_fringe && !is_wire) {
-                    if (node.type() == IPIN || node.type() == OPIN) {
-                        if (has_adjacent_channel(node, device_ctx.grid)) {
-                            auto block_type = device_ctx.grid[node.xlow()][node.ylow()].type;
-                            std::string pin_name = block_type_pin_index_to_name(block_type, node.pin_num());
+                    if (device_ctx.rr_graph.node_type(inode) == IPIN || device_ctx.rr_graph.node_type(inode) == OPIN) {
+                        if (has_adjacent_channel(device_ctx.rr_graph, inode, device_ctx.grid)) {
+                            auto block_type = device_ctx.grid[device_ctx.rr_graph.node_xlow(inode)][device_ctx.rr_graph.node_ylow(inode)].type;
+                            std::string pin_name = block_type_pin_index_to_name(block_type, device_ctx.rr_graph.node_pin_num(inode));
                             VTR_LOG_ERROR("in check_rr_graph: node %d (%s) at (%d,%d) block=%s side=%s pin=%s has no fanin.\n",
-                                          inode, node.type_string(), node.xlow(), node.ylow(), block_type->name, node.side_string(), pin_name.c_str());
+                                          size_t(inode), rr_node_typename[device_ctx.rr_graph.node_type(inode)], device_ctx.rr_graph.node_xlow(inode), device_ctx.rr_graph.node_ylow(inode), block_type->name, SIDE_STRING[device_ctx.rr_graph.node_side(inode)], pin_name.c_str());
                         }
                     } else {
                         VTR_LOG_ERROR("in check_rr_graph: node %d (%s) has no fanin.\n",
-                                      inode, device_ctx.rr_nodes[inode].type_string());
+                                      size_t(inode), rr_node_typename[device_ctx.rr_graph.node_type(inode)]);
                     }
                 } else if (!is_chain && !is_fringe_warning_sent) {
                     VTR_LOG_WARN(
                         "in check_rr_graph: fringe node %d %s at (%d,%d) has no fanin.\n"
                         "\t This is possible on a fringe node based on low Fc_out, N, and certain lengths.\n",
-                        inode, device_ctx.rr_nodes[inode].type_string(), device_ctx.rr_nodes[inode].xlow(), device_ctx.rr_nodes[inode].ylow());
+                        size_t(inode), rr_node_typename[device_ctx.rr_graph.node_type(inode)], device_ctx.rr_graph.node_xlow(inode), device_ctx.rr_graph.node_ylow(inode));
                     is_fringe_warning_sent = true;
                 }
             }
         } else { /* SOURCE.  No fanin for now; change if feedthroughs allowed. */
             if (total_edges_to_node[inode] != 0) {
                 VTR_LOG_ERROR("in check_rr_graph: SOURCE node %d has a fanin of %d, expected 0.\n",
-                              inode, total_edges_to_node[inode]);
+                              size_t(inode), total_edges_to_node[inode]);
             }
         }
     }
 }
 
-static bool rr_node_is_global_clb_ipin(int inode) {
+static bool rr_node_is_global_clb_ipin(const RRNodeId& inode) {
     /* Returns true if inode refers to a global CLB input pin node.   */
 
     int ipin;
@@ -210,12 +206,12 @@ static bool rr_node_is_global_clb_ipin(int inode) {
 
     auto& device_ctx = g_vpr_ctx.device();
 
-    type = device_ctx.grid[device_ctx.rr_nodes[inode].xlow()][device_ctx.rr_nodes[inode].ylow()].type;
+    type = device_ctx.grid[device_ctx.rr_graph.node_xlow(inode)][device_ctx.rr_graph.node_ylow(inode)].type;
 
-    if (device_ctx.rr_nodes[inode].type() != IPIN)
+    if (device_ctx.rr_graph.node_type(inode) != IPIN)
         return (false);
 
-    ipin = device_ctx.rr_nodes[inode].ptc_num();
+    ipin = device_ctx.rr_graph.node_ptc_num(inode);
 
     return type->is_ignored_pin[ipin];
 }
@@ -458,31 +454,28 @@ void check_rr_node(const RRNodeId& inode, enum e_route_type route_type, const De
     }
 }
 
-static void check_unbuffered_edges(int from_node) {
+static void check_unbuffered_edges(const RRNodeId& from_node) {
     /* This routine checks that all pass transistors in the routing truly are  *
      * bidirectional.  It may be a slow check, so don't use it all the time.   */
 
-    int from_edge, to_node, to_edge, from_num_edges, to_num_edges;
     t_rr_type from_rr_type, to_rr_type;
     short from_switch_type;
     bool trans_matched;
 
     auto& device_ctx = g_vpr_ctx.device();
 
-    from_rr_type = device_ctx.rr_nodes[from_node].type();
+    from_rr_type = device_ctx.rr_graph.node_type(from_node);
     if (from_rr_type != CHANX && from_rr_type != CHANY)
         return;
 
-    from_num_edges = device_ctx.rr_nodes[from_node].num_edges();
-
-    for (from_edge = 0; from_edge < from_num_edges; from_edge++) {
-        to_node = device_ctx.rr_nodes[from_node].edge_sink_node(from_edge);
-        to_rr_type = device_ctx.rr_nodes[to_node].type();
+    for (const RREdgeId& from_edge : device_ctx.rr_graph.node_out_edges(from_node)) {
+        RRNodeId to_node = device_ctx.rr_graph.edge_sink_node(from_edge);
+        to_rr_type = device_ctx.rr_graph.node_type(to_node);
 
         if (to_rr_type != CHANX && to_rr_type != CHANY)
             continue;
 
-        from_switch_type = device_ctx.rr_nodes[from_node].edge_switch(from_edge);
+        from_switch_type = size_t(device_ctx.rr_graph.edge_switch(from_edge));
 
         if (device_ctx.rr_switch_inf[from_switch_type].buffered())
             continue;
@@ -491,12 +484,11 @@ static void check_unbuffered_edges(int from_node) {
          * check that there is a corresponding edge from to_node back to         *
          * from_node.                                                            */
 
-        to_num_edges = device_ctx.rr_nodes[to_node].num_edges();
         trans_matched = false;
 
-        for (to_edge = 0; to_edge < to_num_edges; to_edge++) {
-            if (device_ctx.rr_nodes[to_node].edge_sink_node(to_edge) == from_node
-                && device_ctx.rr_nodes[to_node].edge_switch(to_edge) == from_switch_type) {
+        for (const RREdgeId& to_edge : device_ctx.rr_graph.node_out_edges(to_node)) {
+            if (device_ctx.rr_graph.edge_sink_node(to_edge) == from_node
+                && (short)size_t(device_ctx.rr_graph.edge_switch(to_edge)) == from_switch_type) {
                 trans_matched = true;
                 break;
             }
@@ -507,7 +499,7 @@ static void check_unbuffered_edges(int from_node) {
                       "in check_unbuffered_edges:\n"
                       "connection from node %d to node %d uses an unbuffered switch (switch type %d '%s')\n"
                       "but there is no corresponding unbuffered switch edge in the other direction.\n",
-                      from_node, to_node, from_switch_type, device_ctx.rr_switch_inf[from_switch_type].name);
+                      size_t(from_node), size_t(to_node), from_switch_type, device_ctx.rr_switch_inf[from_switch_type].name);
         }
 
     } /* End for all from_node edges */
@@ -526,14 +518,14 @@ static bool has_adjacent_channel(const RRGraph& rr_graph, const RRNodeId& node,
     return true; //All other blocks will be surrounded on all sides by channels
 }
 
-static void check_rr_edge(int from_node, int iedge, int to_node) {
+static void check_rr_edge(const RREdgeId& iedge, const RRNodeId& to_node) {
     auto& device_ctx = g_vpr_ctx.device();
 
     //Check that to to_node's fan-in is correct, given the switch type
-    int iswitch = device_ctx.rr_nodes[from_node].edge_switch(iedge);
+    int iswitch = (int)size_t(device_ctx.rr_graph.edge_switch(iedge));
     auto switch_type = device_ctx.rr_switch_inf[iswitch].type();
 
-    int to_fanin = device_ctx.rr_nodes[to_node].fan_in();
+    int to_fanin = device_ctx.rr_graph.node_in_edges(to_node).size();
     switch (switch_type) {
         case SwitchType::BUFFER:
             //Buffer switches are non-configurable, and uni-directional -- they must have only one driver

From 266b4b6fbe4dd8b01652795b8ce948deea7f3242 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 1 Feb 2020 14:45:59 -0700
Subject: [PATCH 072/645] Breadth first router adopt RRGraph object

---
 vpr/src/base/vpr_context.h            |  2 +-
 vpr/src/route/route_breadth_first.cpp | 66 +++++++++++++--------------
 vpr/src/route/route_common.cpp        | 20 ++++----
 vpr/src/route/route_common.h          |  8 ++--
 4 files changed, 47 insertions(+), 49 deletions(-)

diff --git a/vpr/src/base/vpr_context.h b/vpr/src/base/vpr_context.h
index 9a59e89c8..3195226a2 100644
--- a/vpr/src/base/vpr_context.h
+++ b/vpr/src/base/vpr_context.h
@@ -287,7 +287,7 @@ struct RoutingContext : public Context {
     vtr::vector<ClusterNetId, std::unordered_set<int>> trace_nodes;
 
     /* Xifan Tang: this should adopt RRNodeId as well */
-    vtr::vector<ClusterNetId, std::vector<int>> net_rr_terminals; /* [0..num_nets-1][0..num_pins-1] */
+    vtr::vector<ClusterNetId, std::vector<RRNodeId>> net_rr_terminals; /* [0..num_nets-1][0..num_pins-1] */
 
     vtr::vector<ClusterBlockId, std::vector<int>> rr_blk_source; /* [0..num_blocks-1][0..num_class-1] */
 
diff --git a/vpr/src/route/route_breadth_first.cpp b/vpr/src/route/route_breadth_first.cpp
index cd0809a03..4e74ab128 100644
--- a/vpr/src/route/route_breadth_first.cpp
+++ b/vpr/src/route/route_breadth_first.cpp
@@ -17,13 +17,13 @@ static bool breadth_first_route_net(ClusterNetId net_id, float bend_cost);
 
 static void breadth_first_expand_trace_segment(t_trace* start_ptr,
                                                int remaining_connections_to_sink,
-                                               std::vector<int>& modified_rr_node_inf);
+                                               std::vector<RRNodeId>& modified_rr_node_inf);
 
-static void breadth_first_expand_neighbours(int inode, float pcost, ClusterNetId net_id, float bend_cost);
+static void breadth_first_expand_neighbours(const RRNodeId& inode, float pcost, ClusterNetId net_id, float bend_cost);
 
-static void breadth_first_add_to_heap(const float path_cost, const float bend_cost, const int from_node, const int to_node, const int iconn);
+static void breadth_first_add_to_heap(const float path_cost, const float bend_cost, const RRNodeId& from_node, const RRNodeId& to_node, const RREdgeId& iconn);
 
-static float evaluate_node_cost(const float prev_path_cost, const float bend_cost, const int from_node, const int to_node);
+static float evaluate_node_cost(const float prev_path_cost, const float bend_cost, const RRNodeId& from_node, const RRNodeId& to_node);
 
 static void breadth_first_add_source_to_heap(ClusterNetId net_id);
 
@@ -156,7 +156,8 @@ static bool breadth_first_route_net(ClusterNetId net_id, float bend_cost) {
      * lack of potential paths, rather than congestion), it returns false, as    *
      * routing is impossible on this architecture.  Otherwise it returns true.   */
 
-    int inode, remaining_connections_to_sink;
+    int remaining_connections_to_sink;
+    RRNodeId inode;
     float pcost, new_pcost;
     t_heap* current;
     t_trace* tptr;
@@ -178,7 +179,7 @@ static bool breadth_first_route_net(ClusterNetId net_id, float bend_cost) {
 
     auto src_pin_id = cluster_ctx.clb_nlist.net_driver(net_id);
 
-    std::vector<int> modified_rr_node_inf; //RR node indicies with modified rr_node_route_inf
+    std::vector<RRNodeId> modified_rr_node_inf; //RR node indicies with modified rr_node_route_inf
 
     for (auto pin_id : cluster_ctx.clb_nlist.net_sinks(net_id)) { /* Need n-1 wires to connect n pins */
 
@@ -197,7 +198,7 @@ static bool breadth_first_route_net(ClusterNetId net_id, float bend_cost) {
         inode = current->index;
 
 #ifdef ROUTER_DEBUG
-        VTR_LOG("  Popped node %d\n", inode);
+        VTR_LOG("  Popped node %d\n", size_t(inode));
 #endif
 
         while (route_ctx.rr_node_route_inf[inode].target_flag == 0) {
@@ -269,7 +270,7 @@ static bool breadth_first_route_net(ClusterNetId net_id, float bend_cost) {
 
 static void breadth_first_expand_trace_segment(t_trace* start_ptr,
                                                int remaining_connections_to_sink,
-                                               std::vector<int>& modified_rr_node_inf) {
+                                               std::vector<RRNodeId>& modified_rr_node_inf) {
     /* Adds all the rr_nodes in the traceback segment starting at tptr (and     *
      * continuing to the end of the traceback) to the heap with a cost of zero. *
      * This allows expansion to begin from the existing wiring.  The            *
@@ -287,13 +288,13 @@ static void breadth_first_expand_trace_segment(t_trace* start_ptr,
      * this means two connections to the same SINK.                             */
 
     t_trace *tptr, *next_ptr;
-    int inode, sink_node, last_ipin_node;
+    RRNodeId inode, sink_node, last_ipin_node;
 
     auto& device_ctx = g_vpr_ctx.device();
     auto& route_ctx = g_vpr_ctx.mutable_routing();
 
     tptr = start_ptr;
-    if (tptr != nullptr && device_ctx.rr_nodes[tptr->index].type() == SINK) {
+    if (tptr != nullptr && device_ctx.rr_graph.node_type(tptr->index) == SINK) {
         /* During logical equivalence case, only use one opin */
         tptr = tptr->next;
     }
@@ -301,9 +302,9 @@ static void breadth_first_expand_trace_segment(t_trace* start_ptr,
     if (remaining_connections_to_sink == 0) { /* Usual case. */
         while (tptr != nullptr) {
 #ifdef ROUTER_DEBUG
-            VTR_LOG("  Adding previous routing node %d to heap\n", tptr->index);
+            VTR_LOG("  Adding previous routing node %d to heap\n", size_t(tptr->index));
 #endif
-            node_to_heap(tptr->index, 0., NO_PREVIOUS, NO_PREVIOUS, OPEN, OPEN);
+            node_to_heap(tptr->index, 0., RRNodeId::INVALID(), RREdgeId::INVALID(), OPEN, OPEN);
             tptr = tptr->next;
         }
     } else { /* This case never executes for most logic blocks. */
@@ -318,7 +319,7 @@ static void breadth_first_expand_trace_segment(t_trace* start_ptr,
             return; /* No route yet */
 
         next_ptr = tptr->next;
-        last_ipin_node = OPEN; /* Stops compiler from complaining. */
+        last_ipin_node = RRNodeId::INVALID(); /* Stops compiler from complaining. */
 
         /* Can't put last SINK on heap with NO_PREVIOUS, etc, since that won't let  *
          * us reach it again.  Instead, leave the last traceback element (SINK) off *
@@ -327,17 +328,17 @@ static void breadth_first_expand_trace_segment(t_trace* start_ptr,
         while (next_ptr != nullptr) {
             inode = tptr->index;
 #ifdef ROUTER_DEBUG
-            VTR_LOG("  Adding previous routing node %d to heap*\n", tptr->index);
+            VTR_LOG("  Adding previous routing node %d to heap*\n", size_t(tptr->index));
 #endif
-            node_to_heap(inode, 0., NO_PREVIOUS, NO_PREVIOUS, OPEN, OPEN);
+            node_to_heap(inode, 0., RRNodeId::INVALID(), RREdgeId::INVALID(), OPEN, OPEN);
 
-            if (device_ctx.rr_nodes[inode].type() == IPIN)
+            if (device_ctx.rr_graph.node_type(inode) == IPIN)
                 last_ipin_node = inode;
 
             tptr = next_ptr;
             next_ptr = tptr->next;
         }
-        VTR_ASSERT(last_ipin_node >= 0);
+        VTR_ASSERT(true == device_ctx.rr_graph.valid_node_id(last_ipin_node));
 
         /* This will stop the IPIN node used to get to this SINK from being         *
          * reexpanded for the remainder of this net's routing.  This will make us   *
@@ -363,24 +364,21 @@ static void breadth_first_expand_trace_segment(t_trace* start_ptr,
     }
 }
 
-static void breadth_first_expand_neighbours(int inode, float pcost, ClusterNetId net_id, float bend_cost) {
+static void breadth_first_expand_neighbours(const RRNodeId& inode, float pcost, ClusterNetId net_id, float bend_cost) {
     /* Puts all the rr_nodes adjacent to inode on the heap.  rr_nodes outside   *
      * the expanded bounding box specified in route_bb are not added to the     *
      * heap.  pcost is the path_cost to get to inode.                           */
 
-    int iconn, to_node, num_edges;
-
     auto& device_ctx = g_vpr_ctx.device();
     auto& route_ctx = g_vpr_ctx.routing();
 
-    num_edges = device_ctx.rr_nodes[inode].num_edges();
-    for (iconn = 0; iconn < num_edges; iconn++) {
-        to_node = device_ctx.rr_nodes[inode].edge_sink_node(iconn);
+    for (const RREdgeId& iconn : device_ctx.rr_graph.node_out_edges(inode)) {
+        const RRNodeId& to_node = device_ctx.rr_graph.edge_sink_node(iconn);
 
-        if (device_ctx.rr_nodes[to_node].xhigh() < route_ctx.route_bb[net_id].xmin
-            || device_ctx.rr_nodes[to_node].xlow() > route_ctx.route_bb[net_id].xmax
-            || device_ctx.rr_nodes[to_node].yhigh() < route_ctx.route_bb[net_id].ymin
-            || device_ctx.rr_nodes[to_node].ylow() > route_ctx.route_bb[net_id].ymax)
+        if (device_ctx.rr_graph.node_xhigh(to_node) < route_ctx.route_bb[net_id].xmin
+            || device_ctx.rr_graph.node_xlow(to_node) > route_ctx.route_bb[net_id].xmax
+            || device_ctx.rr_graph.node_yhigh(to_node) < route_ctx.route_bb[net_id].ymin
+            || device_ctx.rr_graph.node_ylow(to_node) > route_ctx.route_bb[net_id].ymax)
             continue; /* Node is outside (expanded) bounding box. */
 
         breadth_first_add_to_heap(pcost, bend_cost, inode, to_node, iconn);
@@ -388,9 +386,9 @@ static void breadth_first_expand_neighbours(int inode, float pcost, ClusterNetId
 }
 
 //Add to_node to the heap, and also add any nodes which are connected by non-configurable edges
-static void breadth_first_add_to_heap(const float path_cost, const float bend_cost, const int from_node, const int to_node, const int iconn) {
+static void breadth_first_add_to_heap(const float path_cost, const float bend_cost, const RRNodeId& from_node, const RRNodeId& to_node, const RREdgeId& iconn) {
 #ifdef ROUTER_DEBUG
-    VTR_LOG("      Expanding node %d\n", to_node);
+    VTR_LOG("      Expanding node %d\n", size_t(to_node));
 #endif
 
     //Create a heap element to represent this node (and any non-configurably connected nodes)
@@ -413,14 +411,14 @@ static void breadth_first_add_to_heap(const float path_cost, const float bend_co
     add_to_heap(next);
 }
 
-static float evaluate_node_cost(const float prev_path_cost, const float bend_cost, const int from_node, const int to_node) {
+static float evaluate_node_cost(const float prev_path_cost, const float bend_cost, const RRNodeId& from_node, const RRNodeId& to_node) {
     auto& device_ctx = g_vpr_ctx.device();
 
     float tot_cost = prev_path_cost + get_rr_cong_cost(to_node);
 
     if (bend_cost != 0.) {
-        t_rr_type from_type = device_ctx.rr_nodes[from_node].type();
-        t_rr_type to_type = device_ctx.rr_nodes[to_node].type();
+        t_rr_type from_type = device_ctx.rr_graph.node_type(from_node);
+        t_rr_type to_type = device_ctx.rr_graph.node_type(to_node);
         if ((from_type == CHANX && to_type == CHANY)
             || (from_type == CHANY && to_type == CHANX))
             tot_cost += bend_cost;
@@ -432,7 +430,7 @@ static float evaluate_node_cost(const float prev_path_cost, const float bend_cos
 static void breadth_first_add_source_to_heap(ClusterNetId net_id) {
     /* Adds the SOURCE of this net to the heap.  Used to start a net's routing. */
 
-    int inode;
+    RRNodeId inode;
     float cost;
 
     auto& route_ctx = g_vpr_ctx.routing();
@@ -444,5 +442,5 @@ static void breadth_first_add_source_to_heap(ClusterNetId net_id) {
     VTR_LOG("  Adding Source node %d to heap\n", inode);
 #endif
 
-    node_to_heap(inode, cost, NO_PREVIOUS, NO_PREVIOUS, OPEN, OPEN);
+    node_to_heap(inode, cost, RRNodeId::INVALID(), RREdgeId::INVALID(), OPEN, OPEN);
 }
diff --git a/vpr/src/route/route_common.cpp b/vpr/src/route/route_common.cpp
index 39373cb76..a6ad81a5f 100644
--- a/vpr/src/route/route_common.cpp
+++ b/vpr/src/route/route_common.cpp
@@ -104,7 +104,7 @@ static void adjust_one_rr_occ_and_apcost(int inode, int add_or_sub, float pres_f
 
 bool validate_traceback_recurr(t_trace* trace, std::set<int>& seen_rr_nodes);
 static bool validate_trace_nodes(t_trace* head, const std::unordered_set<int>& trace_nodes);
-static float get_single_rr_cong_cost(int inode);
+static float get_single_rr_cong_cost(const RRNodeId& inode);
 
 /************************** Subroutine definitions ***************************/
 
@@ -774,7 +774,7 @@ void mark_remaining_ends(const std::vector<int>& remaining_sinks) {
         ++route_ctx.rr_node_route_inf[sink_node].target_flag;
 }
 
-void node_to_heap(int inode, float total_cost, int prev_node, int prev_edge, float backward_path_cost, float R_upstream) {
+void node_to_heap(const RRNodeId& inode, float total_cost, const RRNodeId& prev_node, const RREdgeId& prev_edge, float backward_path_cost, float R_upstream) {
     /* Puts an rr_node on the heap, if the new cost given is lower than the     *
      * current path_cost to this channel segment.  The index of its predecessor *
      * is stored to make traceback easy.  The index of the edge used to get     *
@@ -790,8 +790,8 @@ void node_to_heap(int inode, float total_cost, int prev_node, int prev_edge, flo
     t_heap* hptr = alloc_heap_data();
     hptr->index = inode;
     hptr->cost = total_cost;
-    VTR_ASSERT_SAFE(hptr->u.prev.node == NO_PREVIOUS);
-    VTR_ASSERT_SAFE(hptr->u.prev.edge == NO_PREVIOUS);
+    VTR_ASSERT_SAFE(hptr->u.prev.node == RRNodeId::INVALID());
+    VTR_ASSERT_SAFE(hptr->u.prev.edge == RREdgeId::INVALID());
     hptr->u.prev.node = prev_node;
     hptr->u.prev.edge = prev_edge;
     hptr->backward_path_cost = backward_path_cost;
@@ -1193,7 +1193,7 @@ t_bb load_net_route_bb(ClusterNetId net_id, int bb_factor) {
     return bb;
 }
 
-void add_to_mod_list(int inode, std::vector<int>& modified_rr_node_inf) {
+void add_to_mod_list(const RRNodeId& inode, std::vector<RRNodeId>& modified_rr_node_inf) {
     auto& route_ctx = g_vpr_ctx.routing();
 
     if (std::isinf(route_ctx.rr_node_route_inf[inode].path_cost)) {
@@ -1413,7 +1413,7 @@ void free_heap_data(t_heap* hptr) {
     num_heap_allocated--;
 }
 
-void invalidate_heap_entries(int sink_node, int ipin_node) {
+void invalidate_heap_entries(const RRNodeId& sink_node, const RRNodeId& ipin_node) {
     /* Marks all the heap entries consisting of sink_node, where it was reached *
      * via ipin_node, as invalid (OPEN).  Used only by the breadth_first router *
      * and even then only in rare circumstances.                                */
@@ -1421,7 +1421,7 @@ void invalidate_heap_entries(int sink_node, int ipin_node) {
     for (int i = 1; i < heap_tail; i++) {
         if (heap[i]->index == sink_node) {
             if (heap[i]->u.prev.node == ipin_node) {
-                heap[i]->index = OPEN; /* Invalid. */
+                heap[i]->index = RRNodeId::INVALID(); /* Invalid. */
                 break;
             }
         }
@@ -1816,7 +1816,7 @@ void print_invalid_routing_info() {
     auto& route_ctx = g_vpr_ctx.routing();
 
     //Build a look-up of nets using each RR node
-    std::multimap<int, ClusterNetId> rr_node_nets;
+    std::multimap<RRNodeId, ClusterNetId> rr_node_nets;
 
     for (auto net_id : cluster_ctx.clb_nlist.nets()) {
         t_trace* tptr = route_ctx.trace[net_id].head;
@@ -1827,9 +1827,9 @@ void print_invalid_routing_info() {
         }
     }
 
-    for (size_t inode = 0; inode < device_ctx.rr_graph.nodes().size(); inode++) {
+    for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) {
         int occ = route_ctx.rr_node_route_inf[inode].occ();
-        int cap = device_ctx.rr_nodes[inode].capacity();
+        int cap = device_ctx.rr_graph.node_capacity(inode);
         if (occ > cap) {
             VTR_LOG("  %s is overused (occ=%d capacity=%d)\n", describe_rr_node(inode).c_str(), occ, cap);
 
diff --git a/vpr/src/route/route_common.h b/vpr/src/route/route_common.h
index cfcfb30ce..86fb216a5 100644
--- a/vpr/src/route/route_common.h
+++ b/vpr/src/route/route_common.h
@@ -66,7 +66,7 @@ void pathfinder_update_cost(float pres_fac, float acc_fac);
 
 t_trace* update_traceback(t_heap* hptr, ClusterNetId net_id);
 
-void reset_path_costs(const std::vector<int>& visited_rr_nodes);
+void reset_path_costs(const std::vector<RRNodeId>& visited_rr_nodes);
 
 float get_rr_cong_cost(const RRNodeId& inode);
 
@@ -75,7 +75,7 @@ void mark_remaining_ends(const std::vector<int>& remaining_sinks);
 
 void add_to_heap(t_heap* hptr);
 t_heap* alloc_heap_data();
-void node_to_heap(int inode, float cost, int prev_node, int prev_edge, float backward_path_cost, float R_upstream);
+void node_to_heap(const RRNodeId& inode, float cost, const RRNodeId& prev_node, const RREdgeId& prev_edge, float backward_path_cost, float R_upstream);
 
 bool is_empty_heap();
 
@@ -83,7 +83,7 @@ void free_traceback(ClusterNetId net_id);
 void drop_traceback_tail(ClusterNetId net_id);
 void free_traceback(t_trace* tptr);
 
-void add_to_mod_list(int inode, std::vector<int>& modified_rr_node_inf);
+void add_to_mod_list(const RRNodeId& inode, std::vector<RRNodeId>& modified_rr_node_inf);
 
 namespace heap_ {
 void build_heap();
@@ -103,7 +103,7 @@ void empty_heap();
 
 void free_heap_data(t_heap* hptr);
 
-void invalidate_heap_entries(int sink_node, int ipin_node);
+void invalidate_heap_entries(const RRNodeId& sink_node, const RRNodeId& ipin_node);
 
 void init_route_structs(int bb_factor);
 

From 26523f1b63549fb11bc27882c3fb39e497908720 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 1 Feb 2020 16:12:54 -0700
Subject: [PATCH 073/645] route_common functions now adopt RRGraph object

---
 vpr/src/base/vpr_context.h     |   8 +-
 vpr/src/route/route_common.cpp | 300 +++++++++++++++++----------------
 vpr/src/route/route_common.h   |  17 +-
 3 files changed, 168 insertions(+), 157 deletions(-)

diff --git a/vpr/src/base/vpr_context.h b/vpr/src/base/vpr_context.h
index 3195226a2..ecad22007 100644
--- a/vpr/src/base/vpr_context.h
+++ b/vpr/src/base/vpr_context.h
@@ -157,10 +157,10 @@ struct DeviceContext : public Context {
     std::vector<t_rr_rc_data> rr_rc_data;
 
     //Sets of non-configurably connected nodes
-    std::vector<std::vector<int>> rr_non_config_node_sets;
+    std::vector<std::vector<RRNodeId>> rr_non_config_node_sets;
 
     //Reverse look-up from RR node to non-configurably connected node set (index into rr_nonconf_node_sets)
-    std::unordered_map<RRNodeId, RRNodeId> rr_node_to_non_config_node_set;
+    std::unordered_map<RRNodeId, int> rr_node_to_non_config_node_set;
 
     //The indicies of rr nodes of a given type at a specific x,y grid location
     t_rr_node_indices rr_node_indices; //[0..NUM_RR_TYPES-1][0..grid.width()-1][0..grid.width()-1][0..size-1]
@@ -284,12 +284,12 @@ struct PlacementContext : public Context {
 struct RoutingContext : public Context {
     /* [0..num_nets-1] of linked list start pointers.  Defines the routing.  */
     vtr::vector<ClusterNetId, t_traceback> trace;
-    vtr::vector<ClusterNetId, std::unordered_set<int>> trace_nodes;
+    vtr::vector<ClusterNetId, std::unordered_set<RRNodeId>> trace_nodes;
 
     /* Xifan Tang: this should adopt RRNodeId as well */
     vtr::vector<ClusterNetId, std::vector<RRNodeId>> net_rr_terminals; /* [0..num_nets-1][0..num_pins-1] */
 
-    vtr::vector<ClusterBlockId, std::vector<int>> rr_blk_source; /* [0..num_blocks-1][0..num_class-1] */
+    vtr::vector<ClusterBlockId, std::vector<RRNodeId>> rr_blk_source; /* [0..num_blocks-1][0..num_class-1] */
 
     vtr::vector<RRNodeId, t_rr_node_route_inf> rr_node_route_inf; /* [0..device_ctx.num_rr_nodes-1] */
 
diff --git a/vpr/src/route/route_common.cpp b/vpr/src/route/route_common.cpp
index a6ad81a5f..5ae9086c3 100644
--- a/vpr/src/route/route_common.cpp
+++ b/vpr/src/route/route_common.cpp
@@ -92,18 +92,18 @@ static int num_linked_f_pointer_allocated = 0;
  *                                                                          */
 
 /******************** Subroutines local to route_common.c *******************/
-static t_trace_branch traceback_branch(int node, std::unordered_set<int>& main_branch_visited);
-static std::pair<t_trace*, t_trace*> add_trace_non_configurable(t_trace* head, t_trace* tail, int node, std::unordered_set<int>& visited);
-static std::pair<t_trace*, t_trace*> add_trace_non_configurable_recurr(int node, std::unordered_set<int>& visited, int depth = 0);
+static t_trace_branch traceback_branch(const RRNodeId& node, std::unordered_set<RRNodeId>& main_branch_visited);
+static std::pair<t_trace*, t_trace*> add_trace_non_configurable(t_trace* head, t_trace* tail, const RRNodeId& node, std::unordered_set<RRNodeId>& visited);
+static std::pair<t_trace*, t_trace*> add_trace_non_configurable_recurr(const RRNodeId& node, std::unordered_set<RRNodeId>& visited, int depth = 0);
 
-static vtr::vector<ClusterNetId, std::vector<int>> load_net_rr_terminals(const t_rr_node_indices& L_rr_node_indices);
-static vtr::vector<ClusterBlockId, std::vector<int>> load_rr_clb_sources(const t_rr_node_indices& L_rr_node_indices);
+static vtr::vector<ClusterNetId, std::vector<RRNodeId>> load_net_rr_terminals(const RRGraph& rr_graph);
+static vtr::vector<ClusterBlockId, std::vector<RRNodeId>> load_rr_clb_sources(const RRGraph& rr_graph);
 
 static t_clb_opins_used alloc_and_load_clb_opins_used_locally();
-static void adjust_one_rr_occ_and_apcost(int inode, int add_or_sub, float pres_fac, float acc_fac);
+static void adjust_one_rr_occ_and_apcost(const RRNodeId& inode, int add_or_sub, float pres_fac, float acc_fac);
 
-bool validate_traceback_recurr(t_trace* trace, std::set<int>& seen_rr_nodes);
-static bool validate_trace_nodes(t_trace* head, const std::unordered_set<int>& trace_nodes);
+bool validate_traceback_recurr(t_trace* trace, std::set<RRNodeId>& seen_rr_nodes);
+static bool validate_trace_nodes(t_trace* head, const std::unordered_set<RRNodeId>& trace_nodes);
 static float get_single_rr_cong_cost(const RRNodeId& inode);
 
 /************************** Subroutine definitions ***************************/
@@ -179,7 +179,8 @@ void restore_routing(vtr::vector<ClusterNetId, t_trace*>& best_routing,
  * Use this number as a routing serial number to ensure that programming *
  * changes do not break the router.                                      */
 void get_serial_num() {
-    int serial_num, inode;
+    int serial_num;
+    RRNodeId inode;
     t_trace* tptr;
 
     auto& cluster_ctx = g_vpr_ctx.clustering();
@@ -196,11 +197,11 @@ void get_serial_num() {
         while (tptr != nullptr) {
             inode = tptr->index;
             serial_num += (size_t(net_id) + 1)
-                          * (device_ctx.rr_nodes[inode].xlow() * (device_ctx.grid.width()) - device_ctx.rr_nodes[inode].yhigh());
+                          * (device_ctx.rr_graph.node_xlow(inode) * (device_ctx.grid.width()) - device_ctx.rr_graph.node_yhigh(inode));
 
-            serial_num -= device_ctx.rr_nodes[inode].ptc_num() * (size_t(net_id) + 1) * 10;
+            serial_num -= device_ctx.rr_graph.node_ptc_num(inode) * (size_t(net_id) + 1) * 10;
 
-            serial_num -= device_ctx.rr_nodes[inode].type() * (size_t(net_id) + 1) * 100;
+            serial_num -= device_ctx.rr_graph.node_type(inode) * (size_t(net_id) + 1) * 100;
             serial_num %= 2000000000; /* Prevent overflow */
             tptr = tptr->next;
         }
@@ -336,8 +337,8 @@ bool feasible_routing() {
     auto& device_ctx = g_vpr_ctx.device();
     auto& route_ctx = g_vpr_ctx.routing();
 
-    for (size_t inode = 0; inode < device_ctx.rr_graph.nodes().size(); inode++) {
-        if (route_ctx.rr_node_route_inf[inode].occ() > device_ctx.rr_nodes[inode].capacity()) {
+    for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) {
+        if (route_ctx.rr_node_route_inf[inode].occ() > device_ctx.rr_graph.node_capacity(inode)) {
             return (false);
         }
     }
@@ -414,7 +415,7 @@ void pathfinder_update_path_cost(t_trace* route_segment_start,
     } /* End while loop -- did an entire traceback. */
 }
 
-void pathfinder_update_single_node_cost(int inode, int add_or_sub, float pres_fac) {
+void pathfinder_update_single_node_cost(const RRNodeId& inode, int add_or_sub, float pres_fac) {
     /* Updates pathfinder's congestion cost by either adding or removing the
      * usage of a resource node. pres_cost is Pn in the Pathfinder paper.
      * pres_cost is set according to the overuse that would result from having
@@ -428,7 +429,7 @@ void pathfinder_update_single_node_cost(int inode, int add_or_sub, float pres_fa
     // can't have negative occupancy
     VTR_ASSERT(occ >= 0);
 
-    int capacity = device_ctx.rr_nodes[inode].capacity();
+    int capacity = device_ctx.rr_graph.node_capacity(inode);
     if (occ < capacity) {
         route_ctx.rr_node_route_inf[inode].pres_cost = 1.0;
     } else {
@@ -449,9 +450,9 @@ void pathfinder_update_cost(float pres_fac, float acc_fac) {
     auto& device_ctx = g_vpr_ctx.device();
     auto& route_ctx = g_vpr_ctx.mutable_routing();
 
-    for (size_t inode = 0; inode < device_ctx.rr_graph.nodes().size(); inode++) {
+    for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) {
         occ = route_ctx.rr_node_route_inf[inode].occ();
-        capacity = device_ctx.rr_nodes[inode].capacity();
+        capacity = device_ctx.rr_graph.node_capacity(inode);
 
         if (occ > capacity) {
             route_ctx.rr_node_route_inf[inode].acc_cost += (occ - capacity) * acc_fac;
@@ -496,9 +497,9 @@ void init_route_structs(int bb_factor) {
     init_heap(device_ctx.grid);
 
     //Various look-ups
-    route_ctx.net_rr_terminals = load_net_rr_terminals(device_ctx.rr_node_indices);
+    route_ctx.net_rr_terminals = load_net_rr_terminals(device_ctx.rr_graph);
     route_ctx.route_bb = load_route_bb(bb_factor);
-    route_ctx.rr_blk_source = load_rr_clb_sources(device_ctx.rr_node_indices);
+    route_ctx.rr_blk_source = load_rr_clb_sources(device_ctx.rr_graph);
     route_ctx.clb_opins_used_locally = alloc_and_load_clb_opins_used_locally();
     route_ctx.net_status.resize(cluster_ctx.clb_nlist.nets().size());
 
@@ -550,14 +551,15 @@ update_traceback(t_heap* hptr, ClusterNetId net_id) {
 
 //Traces back a new routing branch starting from the specified 'node' and working backwards to any existing routing.
 //Returns the new branch, and also updates trace_nodes for any new nodes which are included in the branches traceback.
-static t_trace_branch traceback_branch(int node, std::unordered_set<int>& trace_nodes) {
+static t_trace_branch traceback_branch(const RRNodeId& node, std::unordered_set<RRNodeId>& trace_nodes) {
     auto& device_ctx = g_vpr_ctx.device();
     auto& route_ctx = g_vpr_ctx.routing();
 
-    auto rr_type = device_ctx.rr_nodes[node].type();
+    auto rr_type = device_ctx.rr_graph.node_type(node);
     if (rr_type != SINK) {
         VPR_FATAL_ERROR(VPR_ERROR_ROUTE,
-                        "in traceback_branch: Expected type = SINK (%d).\n");
+                        "in traceback_branch: Expected type = SINK (%d).\n", 
+                        size_t(node));
     }
 
     //We construct the main traceback by walking from the given node back to the source,
@@ -570,16 +572,16 @@ static t_trace_branch traceback_branch(int node, std::unordered_set<int>& trace_
 
     trace_nodes.insert(node);
 
-    std::vector<int> new_nodes_added_to_traceback = {node};
+    std::vector<RRNodeId> new_nodes_added_to_traceback = {node};
 
-    auto iedge = route_ctx.rr_node_route_inf[node].prev_edge;
-    int inode = route_ctx.rr_node_route_inf[node].prev_node;
+    RREdgeId iedge = route_ctx.rr_node_route_inf[node].prev_edge;
+    RRNodeId inode = route_ctx.rr_node_route_inf[node].prev_node;
 
-    while (inode != NO_PREVIOUS) {
+    while (inode != RRNodeId::INVALID()) {
         //Add the current node to the head of traceback
         t_trace* prev_ptr = alloc_trace_data();
         prev_ptr->index = inode;
-        prev_ptr->iswitch = device_ctx.rr_nodes[inode].edge_switch(iedge);
+        prev_ptr->iswitch = (short)size_t(device_ctx.rr_graph.edge_switch(iedge));
         prev_ptr->next = branch_head;
         branch_head = prev_ptr;
 
@@ -597,7 +599,7 @@ static t_trace_branch traceback_branch(int node, std::unordered_set<int>& trace_
     //We next re-expand all the main-branch nodes to add any non-configurably connected side branches
     // We are careful to do this *after* the main branch is constructed to ensure nodes which are both
     // non-configurably connected *and* part of the main branch are only added to the traceback once.
-    for (int new_node : new_nodes_added_to_traceback) {
+    for (const RRNodeId& new_node : new_nodes_added_to_traceback) {
         //Expand each main branch node
         std::tie(branch_head, branch_tail) = add_trace_non_configurable(branch_head, branch_tail, new_node, trace_nodes);
     }
@@ -608,7 +610,7 @@ static t_trace_branch traceback_branch(int node, std::unordered_set<int>& trace_
 //Traces any non-configurable subtrees from branch_head, returning the new branch_head and updating trace_nodes
 //
 //This effectively does a depth-first traversal
-static std::pair<t_trace*, t_trace*> add_trace_non_configurable(t_trace* head, t_trace* tail, int node, std::unordered_set<int>& trace_nodes) {
+static std::pair<t_trace*, t_trace*> add_trace_non_configurable(t_trace* head, t_trace* tail, const RRNodeId& node, std::unordered_set<RRNodeId>& trace_nodes) {
     //Trace any non-configurable subtrees
     t_trace* subtree_head = nullptr;
     t_trace* subtree_tail = nullptr;
@@ -632,17 +634,17 @@ static std::pair<t_trace*, t_trace*> add_trace_non_configurable(t_trace* head, t
 }
 
 //Recursive helper function for add_trace_non_configurable()
-static std::pair<t_trace*, t_trace*> add_trace_non_configurable_recurr(int node, std::unordered_set<int>& trace_nodes, int depth) {
+static std::pair<t_trace*, t_trace*> add_trace_non_configurable_recurr(const RRNodeId& node, std::unordered_set<RRNodeId>& trace_nodes, int depth) {
     t_trace* head = nullptr;
     t_trace* tail = nullptr;
 
     //Record the non-configurable out-going edges
-    std::vector<t_edge_size> unvisited_non_configurable_edges;
+    std::vector<RREdgeId> unvisited_non_configurable_edges;
     auto& device_ctx = g_vpr_ctx.device();
-    for (auto iedge : device_ctx.rr_nodes[node].non_configurable_edges()) {
-        VTR_ASSERT_SAFE(!device_ctx.rr_nodes[node].edge_is_configurable(iedge));
+    for (auto iedge : device_ctx.rr_graph.node_non_configurable_out_edges(node)) {
+        VTR_ASSERT_SAFE(!device_ctx.rr_graph.edge_is_configurable(iedge));
 
-        int to_node = device_ctx.rr_nodes[node].edge_sink_node(iedge);
+        const RRNodeId& to_node = device_ctx.rr_graph.edge_sink_node(iedge);
 
         if (!trace_nodes.count(to_node)) {
             unvisited_non_configurable_edges.push_back(iedge);
@@ -665,8 +667,8 @@ static std::pair<t_trace*, t_trace*> add_trace_non_configurable_recurr(int node,
     } else {
         //Recursive case: intermediate node with non-configurable edges
         for (auto iedge : unvisited_non_configurable_edges) {
-            int to_node = device_ctx.rr_nodes[node].edge_sink_node(iedge);
-            int iswitch = device_ctx.rr_nodes[node].edge_switch(iedge);
+            const RRNodeId& to_node = device_ctx.rr_graph.edge_sink_node(iedge);
+            int iswitch = (int)size_t(device_ctx.rr_graph.edge_switch(iedge));
 
             VTR_ASSERT(!trace_nodes.count(to_node));
             trace_nodes.insert(node);
@@ -725,7 +727,7 @@ float get_rr_cong_cost(const RRNodeId& inode) {
 
     auto itr = device_ctx.rr_node_to_non_config_node_set.find(inode);
     if (itr != device_ctx.rr_node_to_non_config_node_set.end()) {
-        for (const RRNodeId& node : device_ctx.rr_non_config_node_sets[itr->second]) {
+        for (RRNodeId node : device_ctx.rr_non_config_node_sets[itr->second]) {
             if (node == inode) {
                 continue; //Already included above
             }
@@ -755,22 +757,20 @@ static float get_single_rr_cong_cost(const RRNodeId& inode) {
  * the same net to two inputs of an and-gate (and-gate inputs are logically *
  * equivalent, so both will connect to the same SINK).                      */
 void mark_ends(ClusterNetId net_id) {
-    unsigned int ipin;
-    int inode;
 
     auto& cluster_ctx = g_vpr_ctx.clustering();
     auto& route_ctx = g_vpr_ctx.mutable_routing();
 
-    for (ipin = 1; ipin < cluster_ctx.clb_nlist.net_pins(net_id).size(); ipin++) {
-        inode = route_ctx.net_rr_terminals[net_id][ipin];
+    for (unsigned int ipin = 1; ipin < cluster_ctx.clb_nlist.net_pins(net_id).size(); ipin++) {
+        const RRNodeId& inode = route_ctx.net_rr_terminals[net_id][ipin];
         route_ctx.rr_node_route_inf[inode].target_flag++;
     }
 }
 
-void mark_remaining_ends(const std::vector<int>& remaining_sinks) {
+void mark_remaining_ends(const std::vector<RRNodeId>& remaining_sinks) {
     // like mark_ends, but only performs it for the remaining sinks of a net
     auto& route_ctx = g_vpr_ctx.mutable_routing();
-    for (int sink_node : remaining_sinks)
+    for (const RRNodeId& sink_node : remaining_sinks)
         ++route_ctx.rr_node_route_inf[sink_node].target_flag;
 }
 
@@ -1016,10 +1016,9 @@ void reset_rr_node_route_structs() {
 
     VTR_ASSERT(route_ctx.rr_node_route_inf.size() == size_t(device_ctx.rr_graph.nodes().size()));
 
-    for (size_t inode = 0; inode < device_ctx.rr_graph.nodes().size(); inode++) {
-        route_ctx.rr_node_route_inf[inode].prev_node = NO_PREVIOUS;
-        route_ctx.rr_node_route_inf[inode].prev_node_id = RRNodeId::INVALID();
-        route_ctx.rr_node_route_inf[inode].prev_edge = NO_PREVIOUS;
+    for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) {
+        route_ctx.rr_node_route_inf[inode].prev_node = RRNodeId::INVALID();
+        route_ctx.rr_node_route_inf[inode].prev_edge = RREdgeId::INVALID();
         route_ctx.rr_node_route_inf[inode].pres_cost = 1.0;
         route_ctx.rr_node_route_inf[inode].acc_cost = 1.0;
         route_ctx.rr_node_route_inf[inode].path_cost = std::numeric_limits<float>::infinity();
@@ -1032,8 +1031,8 @@ void reset_rr_node_route_structs() {
 /* Allocates and loads the route_ctx.net_rr_terminals data structure. For each net it stores the rr_node   *
  * index of the SOURCE of the net and all the SINKs of the net [clb_nlist.nets()][clb_nlist.net_pins()].    *
  * Entry [inet][pnum] stores the rr index corresponding to the SOURCE (opin) or SINK (ipin) of the pin.     */
-static vtr::vector<ClusterNetId, std::vector<int>> load_net_rr_terminals(const t_rr_node_indices& L_rr_node_indices) {
-    vtr::vector<ClusterNetId, std::vector<int>> net_rr_terminals;
+static vtr::vector<ClusterNetId, std::vector<RRNodeId>> load_net_rr_terminals(const RRGraph& rr_graph) {
+    vtr::vector<ClusterNetId, std::vector<RRNodeId>> net_rr_terminals;
 
     auto& cluster_ctx = g_vpr_ctx.clustering();
     auto& place_ctx = g_vpr_ctx.placement();
@@ -1059,8 +1058,8 @@ static vtr::vector<ClusterNetId, std::vector<int>> load_net_rr_terminals(const t
 
             int iclass = type->pin_class[phys_pin];
 
-            int inode = get_rr_node_index(L_rr_node_indices, i, j, (pin_count == 0 ? SOURCE : SINK), /* First pin is driver */
-                                          iclass);
+            RRNodeId inode = rr_graph.find_node(i, j, (pin_count == 0 ? SOURCE : SINK), /* First pin is driver */
+                                                iclass);
             net_rr_terminals[net_id][pin_count] = inode;
             pin_count++;
         }
@@ -1074,10 +1073,9 @@ static vtr::vector<ClusterNetId, std::vector<int>> load_net_rr_terminals(const t
  * they are used only to reserve pins for locally used OPINs in the router. *
  * [0..cluster_ctx.clb_nlist.blocks().size()-1][0..num_class-1].            *
  * The values for blocks that are padsare NOT valid.                        */
-static vtr::vector<ClusterBlockId, std::vector<int>> load_rr_clb_sources(const t_rr_node_indices& L_rr_node_indices) {
-    vtr::vector<ClusterBlockId, std::vector<int>> rr_blk_source;
+static vtr::vector<ClusterBlockId, std::vector<RRNodeId>> load_rr_clb_sources(const RRGraph& rr_graph) {
+    vtr::vector<ClusterBlockId, std::vector<RRNodeId>> rr_blk_source;
 
-    int i, j, iclass, inode;
     int class_low, class_high;
     t_rr_type rr_type;
 
@@ -1090,20 +1088,20 @@ static vtr::vector<ClusterBlockId, std::vector<int>> load_rr_clb_sources(const t
         auto type = physical_tile_type(blk_id);
         get_class_range_for_block(blk_id, &class_low, &class_high);
         rr_blk_source[blk_id].resize(type->num_class);
-        for (iclass = 0; iclass < type->num_class; iclass++) {
+        for (int iclass = 0; iclass < type->num_class; iclass++) {
             if (iclass >= class_low && iclass <= class_high) {
-                i = place_ctx.block_locs[blk_id].loc.x;
-                j = place_ctx.block_locs[blk_id].loc.y;
+                int i = place_ctx.block_locs[blk_id].loc.x;
+                int j = place_ctx.block_locs[blk_id].loc.y;
 
                 if (type->class_inf[iclass].type == DRIVER)
                     rr_type = SOURCE;
                 else
                     rr_type = SINK;
 
-                inode = get_rr_node_index(L_rr_node_indices, i, j, rr_type, iclass);
+                const RRNodeId& inode = rr_graph.find_node(i, j, rr_type, iclass);
                 rr_blk_source[blk_id][iclass] = inode;
             } else {
-                rr_blk_source[blk_id][iclass] = OPEN;
+                rr_blk_source[blk_id][iclass] = RRNodeId::INVALID();
             }
         }
     }
@@ -1149,31 +1147,29 @@ t_bb load_net_route_bb(ClusterNetId net_id, int bb_factor) {
     int max_dim = std::max<int>(device_ctx.grid.width() - 1, device_ctx.grid.height() - 1);
     bb_factor = std::min(bb_factor, max_dim);
 
-    int driver_rr = route_ctx.net_rr_terminals[net_id][0];
-    const t_rr_node& source_node = device_ctx.rr_nodes[driver_rr];
-    VTR_ASSERT(source_node.type() == SOURCE);
+    const RRNodeId& driver_rr = route_ctx.net_rr_terminals[net_id][0];
+    VTR_ASSERT(device_ctx.rr_graph.node_type(driver_rr) == SOURCE);
 
-    VTR_ASSERT(source_node.xlow() <= source_node.xhigh());
-    VTR_ASSERT(source_node.ylow() <= source_node.yhigh());
+    VTR_ASSERT(device_ctx.rr_graph.node_xlow(driver_rr) <= device_ctx.rr_graph.node_xhigh(driver_rr));
+    VTR_ASSERT(device_ctx.rr_graph.node_ylow(driver_rr) <= device_ctx.rr_graph.node_yhigh(driver_rr));
 
-    int xmin = source_node.xlow();
-    int ymin = source_node.ylow();
-    int xmax = source_node.xhigh();
-    int ymax = source_node.yhigh();
+    int xmin = device_ctx.rr_graph.node_xlow(driver_rr);
+    int ymin = device_ctx.rr_graph.node_ylow(driver_rr);
+    int xmax = device_ctx.rr_graph.node_xhigh(driver_rr);
+    int ymax = device_ctx.rr_graph.node_yhigh(driver_rr);
 
     auto net_sinks = cluster_ctx.clb_nlist.net_sinks(net_id);
     for (size_t ipin = 1; ipin < net_sinks.size() + 1; ++ipin) { //Start at 1 since looping through sinks
-        int sink_rr = route_ctx.net_rr_terminals[net_id][ipin];
-        const t_rr_node& sink_node = device_ctx.rr_nodes[sink_rr];
-        VTR_ASSERT(sink_node.type() == SINK);
+        const RRNodeId& sink_rr = route_ctx.net_rr_terminals[net_id][ipin];
+        VTR_ASSERT(device_ctx.rr_graph.node_type(sink_rr) == SINK);
 
-        VTR_ASSERT(sink_node.xlow() <= sink_node.xhigh());
-        VTR_ASSERT(sink_node.ylow() <= sink_node.yhigh());
+        VTR_ASSERT(device_ctx.rr_graph.node_xlow(sink_rr) <= device_ctx.rr_graph.node_xhigh(sink_rr));
+        VTR_ASSERT(device_ctx.rr_graph.node_ylow(sink_rr) <= device_ctx.rr_graph.node_yhigh(sink_rr));
 
-        xmin = std::min<int>(xmin, sink_node.xlow());
-        xmax = std::max<int>(xmax, sink_node.xhigh());
-        ymin = std::min<int>(ymin, sink_node.ylow());
-        ymax = std::max<int>(ymax, sink_node.yhigh());
+        xmin = std::min<int>(xmin, device_ctx.rr_graph.node_xlow(sink_rr));
+        xmax = std::max<int>(xmax, device_ctx.rr_graph.node_xhigh(sink_rr));
+        ymin = std::min<int>(ymin, device_ctx.rr_graph.node_ylow(sink_rr));
+        ymax = std::max<int>(ymax, device_ctx.rr_graph.node_yhigh(sink_rr));
     }
 
     /* Want the channels on all 4 sides to be usuable, even if bb_factor = 0. */
@@ -1271,11 +1267,11 @@ void push_back_node(const RRNodeId& inode, float total_cost, const RRNodeId& pre
      * bottom up with build_heap    */
 
     auto& route_ctx = g_vpr_ctx.routing();
-    if (total_cost >= route_ctx.rr_node_route_inf[size_t(inode)].path_cost)
+    if (total_cost >= route_ctx.rr_node_route_inf[inode].path_cost)
         return;
 
     t_heap* hptr = alloc_heap_data();
-    hptr->index = size_t(inode);
+    hptr->index = inode;
     hptr->cost = total_cost;
     hptr->u.prev.node = prev_node;
     hptr->u.prev.edge = prev_edge;
@@ -1317,7 +1313,7 @@ void verify_extract_top() {
     std::cout << "starting to compare top elements\n";
     size_t i = 0;
     while (!is_empty_heap()) {
-        while (heap_copy[i]->index == OPEN)
+        while (heap_copy[i]->index == RRNodeId::INVALID())
             ++i; // skip the ones that won't be extracted
         auto top = get_heap_head();
         if (abs(top->cost - heap_copy[i]->cost) > float_epsilon)
@@ -1372,7 +1368,7 @@ get_heap_head() {
         }
         heap_::sift_up(hole, heap[heap_tail]);
 
-    } while (cheapest->index == OPEN); /* Get another one if invalid entry. */
+    } while (cheapest->index == RRNodeId::INVALID()); /* Get another one if invalid entry. */
 
     return (cheapest);
 }
@@ -1401,9 +1397,9 @@ alloc_heap_data() {
     temp_ptr->cost = 0.;
     temp_ptr->backward_path_cost = 0.;
     temp_ptr->R_upstream = 0.;
-    temp_ptr->index = OPEN;
-    temp_ptr->u.prev.node = NO_PREVIOUS;
-    temp_ptr->u.prev.edge = NO_PREVIOUS;
+    temp_ptr->index = RRNodeId::INVALID();
+    temp_ptr->u.prev.node = RRNodeId::INVALID();
+    temp_ptr->u.prev.edge = RREdgeId::INVALID();
     return (temp_ptr);
 }
 
@@ -1467,18 +1463,18 @@ void print_route(FILE* fp, const vtr::vector<ClusterNetId, t_traceback>& traceba
                 t_trace* tptr = route_ctx.trace[net_id].head;
 
                 while (tptr != nullptr) {
-                    int inode = tptr->index;
-                    t_rr_type rr_type = device_ctx.rr_nodes[inode].type();
-                    int ilow = device_ctx.rr_nodes[inode].xlow();
-                    int jlow = device_ctx.rr_nodes[inode].ylow();
+                    RRNodeId inode = tptr->index;
+                    t_rr_type rr_type = device_ctx.rr_graph.node_type(inode);
+                    int ilow = device_ctx.rr_graph.node_xlow(inode);
+                    int jlow = device_ctx.rr_graph.node_ylow(inode);
 
-                    fprintf(fp, "Node:\t%d\t%6s (%d,%d) ", inode,
-                            device_ctx.rr_nodes[inode].type_string(), ilow, jlow);
+                    fprintf(fp, "Node:\t%ld\t%6s (%d,%d) ", size_t(inode),
+                            rr_node_typename[device_ctx.rr_graph.node_type(inode)], ilow, jlow);
 
-                    if ((ilow != device_ctx.rr_nodes[inode].xhigh())
-                        || (jlow != device_ctx.rr_nodes[inode].yhigh()))
-                        fprintf(fp, "to (%d,%d) ", device_ctx.rr_nodes[inode].xhigh(),
-                                device_ctx.rr_nodes[inode].yhigh());
+                    if ((ilow != device_ctx.rr_graph.node_xhigh(inode))
+                        || (jlow != device_ctx.rr_graph.node_yhigh(inode)))
+                        fprintf(fp, "to (%d,%d) ", device_ctx.rr_graph.node_xhigh(inode),
+                                device_ctx.rr_graph.node_yhigh(inode));
 
                     switch (rr_type) {
                         case IPIN:
@@ -1507,14 +1503,14 @@ void print_route(FILE* fp, const vtr::vector<ClusterNetId, t_traceback>& traceba
                         default:
                             VPR_FATAL_ERROR(VPR_ERROR_ROUTE,
                                             "in print_route: Unexpected traceback element type: %d (%s).\n",
-                                            rr_type, device_ctx.rr_nodes[inode].type_string());
+                                            rr_type, rr_node_typename[device_ctx.rr_graph.node_type(inode)]);
                             break;
                     }
 
-                    fprintf(fp, "%d  ", device_ctx.rr_nodes[inode].ptc_num());
+                    fprintf(fp, "%d  ", device_ctx.rr_graph.node_ptc_num(inode));
 
                     if (!is_io_type(device_ctx.grid[ilow][jlow].type) && (rr_type == IPIN || rr_type == OPIN)) {
-                        int pin_num = device_ctx.rr_nodes[inode].ptc_num();
+                        int pin_num = device_ctx.rr_graph.node_ptc_num(inode);
                         int xoffset = device_ctx.grid[ilow][jlow].width_offset;
                         int yoffset = device_ctx.grid[ilow][jlow].height_offset;
                         ClusterBlockId iblock = place_ctx.grid_blocks[ilow - xoffset][jlow - yoffset].blocks[0];
@@ -1600,8 +1596,7 @@ void print_route(const char* placement_file, const char* route_file) {
 // To model this we 'reserve' these locally used outputs, ensuring that the router will not use them (as if it did
 // this would equate to duplicating a BLE into an already in-use BLE instance, which is clearly incorrect).
 void reserve_locally_used_opins(float pres_fac, float acc_fac, bool rip_up_local_opins) {
-    int num_local_opin, inode, from_node, iconn, num_edges, to_node;
-    int iclass, ipin;
+    int num_local_opin;
     float cost;
     t_heap* heap_head_ptr;
     t_physical_tile_type_ptr type;
@@ -1613,15 +1608,15 @@ void reserve_locally_used_opins(float pres_fac, float acc_fac, bool rip_up_local
     if (rip_up_local_opins) {
         for (auto blk_id : cluster_ctx.clb_nlist.blocks()) {
             type = physical_tile_type(blk_id);
-            for (iclass = 0; iclass < type->num_class; iclass++) {
+            for (int iclass = 0; iclass < type->num_class; iclass++) {
                 num_local_opin = route_ctx.clb_opins_used_locally[blk_id][iclass].size();
 
                 if (num_local_opin == 0) continue;
                 VTR_ASSERT(type->class_inf[iclass].equivalence == PortEquivalence::INSTANCE);
 
                 /* Always 0 for pads and for RECEIVER (IPIN) classes */
-                for (ipin = 0; ipin < num_local_opin; ipin++) {
-                    inode = route_ctx.clb_opins_used_locally[blk_id][iclass][ipin];
+                for (int ipin = 0; ipin < num_local_opin; ipin++) {
+                    const RRNodeId& inode = route_ctx.clb_opins_used_locally[blk_id][iclass][ipin];
                     adjust_one_rr_occ_and_apcost(inode, -1, pres_fac, acc_fac);
                 }
             }
@@ -1630,7 +1625,7 @@ void reserve_locally_used_opins(float pres_fac, float acc_fac, bool rip_up_local
 
     for (auto blk_id : cluster_ctx.clb_nlist.blocks()) {
         type = physical_tile_type(blk_id);
-        for (iclass = 0; iclass < type->num_class; iclass++) {
+        for (int iclass = 0; iclass < type->num_class; iclass++) {
             num_local_opin = route_ctx.clb_opins_used_locally[blk_id][iclass].size();
 
             if (num_local_opin == 0) continue;
@@ -1642,25 +1637,24 @@ void reserve_locally_used_opins(float pres_fac, float acc_fac, bool rip_up_local
             //congestion cost are popped-off/reserved first. (Intuitively, we want
             //the reserved OPINs to move out of the way of congestion, by preferring
             //to reserve OPINs with lower congestion costs).
-            from_node = route_ctx.rr_blk_source[blk_id][iclass];
-            num_edges = device_ctx.rr_nodes[from_node].num_edges();
-            for (iconn = 0; iconn < num_edges; iconn++) {
-                to_node = device_ctx.rr_nodes[from_node].edge_sink_node(iconn);
+            const RRNodeId& from_node = route_ctx.rr_blk_source[blk_id][iclass];
+            for (const RREdgeId& iconn : device_ctx.rr_graph.node_out_edges(from_node)) {
+                const RRNodeId& to_node = device_ctx.rr_graph.edge_sink_node(iconn);
 
-                VTR_ASSERT(device_ctx.rr_nodes[to_node].type() == OPIN);
+                VTR_ASSERT(device_ctx.rr_graph.node_type(to_node) == OPIN);
 
                 //Add the OPIN to the heap according to it's congestion cost
                 cost = get_rr_cong_cost(to_node);
-                node_to_heap(to_node, cost, OPEN, OPEN, 0., 0.);
+                node_to_heap(to_node, cost, RRNodeId::INVALID(), RREdgeId::INVALID(), 0., 0.);
             }
 
-            for (ipin = 0; ipin < num_local_opin; ipin++) {
+            for (int ipin = 0; ipin < num_local_opin; ipin++) {
                 //Pop the nodes off the heap. We get them from the heap so we
                 //reserve those pins with lowest congestion cost first.
                 heap_head_ptr = get_heap_head();
-                inode = heap_head_ptr->index;
+                const RRNodeId& inode = heap_head_ptr->index;
 
-                VTR_ASSERT(device_ctx.rr_nodes[inode].type() == OPIN);
+                VTR_ASSERT(device_ctx.rr_graph.node_type(inode) == OPIN);
 
                 adjust_one_rr_occ_and_apcost(inode, 1, pres_fac, acc_fac);
                 route_ctx.clb_opins_used_locally[blk_id][iclass][ipin] = inode;
@@ -1672,7 +1666,7 @@ void reserve_locally_used_opins(float pres_fac, float acc_fac, bool rip_up_local
     }
 }
 
-static void adjust_one_rr_occ_and_apcost(int inode, int add_or_sub, float pres_fac, float acc_fac) {
+static void adjust_one_rr_occ_and_apcost(const RRNodeId& inode, int add_or_sub, float pres_fac, float acc_fac) {
     /* Increments or decrements (depending on add_or_sub) the occupancy of    *
      * one rr_node, and adjusts the present cost of that node appropriately.  */
 
@@ -1680,7 +1674,7 @@ static void adjust_one_rr_occ_and_apcost(int inode, int add_or_sub, float pres_f
     auto& device_ctx = g_vpr_ctx.device();
 
     int new_occ = route_ctx.rr_node_route_inf[inode].occ() + add_or_sub;
-    int capacity = device_ctx.rr_nodes[inode].capacity();
+    int capacity = device_ctx.rr_graph.node_capacity(inode);
     route_ctx.rr_node_route_inf[inode].set_occ(new_occ);
 
     if (new_occ < capacity) {
@@ -1711,11 +1705,11 @@ void print_traceback(ClusterNetId net_id) {
     VTR_LOG("traceback %zu: ", size_t(net_id));
     t_trace* head = route_ctx.trace[net_id].head;
     while (head) {
-        int inode{head->index};
-        if (device_ctx.rr_nodes[inode].type() == SINK)
-            VTR_LOG("%d(sink)(%d)->", inode, route_ctx.rr_node_route_inf[inode].occ());
+        RRNodeId inode{head->index};
+        if (device_ctx.rr_graph.node_type(inode) == SINK)
+            VTR_LOG("%ld(sink)(%d)->", size_t(inode), route_ctx.rr_node_route_inf[inode].occ());
         else
-            VTR_LOG("%d(%d)->", inode, route_ctx.rr_node_route_inf[inode].occ());
+            VTR_LOG("%ld(%d)->", size_t(inode), route_ctx.rr_node_route_inf[inode].occ());
         head = head->next;
     }
     VTR_LOG("\n");
@@ -1726,8 +1720,8 @@ void print_traceback(const t_trace* trace) {
     auto& route_ctx = g_vpr_ctx.routing();
     const t_trace* prev = nullptr;
     while (trace) {
-        int inode = trace->index;
-        VTR_LOG("%d (%s)", inode, rr_node_typename[device_ctx.rr_nodes[inode].type()]);
+        RRNodeId inode = trace->index;
+        VTR_LOG("%ld (%s)", size_t(inode), rr_node_typename[device_ctx.rr_graph.node_type(inode)]);
 
         if (trace->iswitch == OPEN) {
             VTR_LOG(" !"); //End of branch
@@ -1737,7 +1731,7 @@ void print_traceback(const t_trace* trace) {
             VTR_LOG("*"); //Reached non-configurably
         }
 
-        if (route_ctx.rr_node_route_inf[inode].occ() > device_ctx.rr_nodes[inode].capacity()) {
+        if (route_ctx.rr_node_route_inf[inode].occ() > device_ctx.rr_graph.node_capacity(inode)) {
             VTR_LOG(" x"); //Overused
         }
         VTR_LOG("\n");
@@ -1748,12 +1742,12 @@ void print_traceback(const t_trace* trace) {
 }
 
 bool validate_traceback(t_trace* trace) {
-    std::set<int> seen_rr_nodes;
+    std::set<RRNodeId> seen_rr_nodes;
 
     return validate_traceback_recurr(trace, seen_rr_nodes);
 }
 
-bool validate_traceback_recurr(t_trace* trace, std::set<int>& seen_rr_nodes) {
+bool validate_traceback_recurr(t_trace* trace, std::set<RRNodeId>& seen_rr_nodes) {
     if (!trace) {
         return true;
     }
@@ -1767,7 +1761,7 @@ bool validate_traceback_recurr(t_trace* trace, std::set<int>& seen_rr_nodes) {
 
             //Verify that the next element (branch point) has been already seen in the traceback so far
             if (!seen_rr_nodes.count(next->index)) {
-                VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Traceback branch point %d not found", next->index);
+                VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Traceback branch point %ld not found", size_t(next->index));
             } else {
                 //Recurse along the new branch
                 return validate_traceback_recurr(next, seen_rr_nodes);
@@ -1779,25 +1773,25 @@ bool validate_traceback_recurr(t_trace* trace, std::set<int>& seen_rr_nodes) {
             auto& device_ctx = g_vpr_ctx.device();
 
             bool found = false;
-            for (t_edge_size iedge = 0; iedge < device_ctx.rr_nodes[trace->index].num_edges(); ++iedge) {
-                int to_node = device_ctx.rr_nodes[trace->index].edge_sink_node(iedge);
+            for (const RREdgeId& iedge : device_ctx.rr_graph.node_out_edges(trace->index)) {
+                RRNodeId to_node = device_ctx.rr_graph.edge_sink_node(iedge);
 
                 if (to_node == next->index) {
                     found = true;
 
                     //Verify that the switch matches
-                    int rr_iswitch = device_ctx.rr_nodes[trace->index].edge_switch(iedge);
+                    int rr_iswitch = (int)size_t(device_ctx.rr_graph.edge_switch(iedge));
                     if (trace->iswitch != rr_iswitch) {
-                        VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Traceback mismatched switch type: traceback %d rr_graph %d (RR nodes %d -> %d)\n",
+                        VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Traceback mismatched switch type: traceback %d rr_graph %d (RR nodes %ld -> %ld)\n",
                                         trace->iswitch, rr_iswitch,
-                                        trace->index, to_node);
+                                        size_t(trace->index), size_t(to_node));
                     }
                     break;
                 }
             }
 
             if (!found) {
-                VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Traceback no RR edge between RR nodes %d -> %d\n", trace->index, next->index);
+                VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Traceback no RR edge between RR nodes %ld -> %ld\n", size_t(trace->index), size_t(next->index));
             }
 
             //Recurse
@@ -1845,14 +1839,14 @@ void print_invalid_routing_info() {
 void print_rr_node_route_inf() {
     auto& route_ctx = g_vpr_ctx.routing();
     auto& device_ctx = g_vpr_ctx.device();
-    for (size_t inode = 0; inode < route_ctx.rr_node_route_inf.size(); ++inode) {
+    for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) {
         if (!std::isinf(route_ctx.rr_node_route_inf[inode].path_cost)) {
-            int prev_node = route_ctx.rr_node_route_inf[inode].prev_node;
-            int prev_edge = route_ctx.rr_node_route_inf[inode].prev_edge;
+            RRNodeId prev_node = route_ctx.rr_node_route_inf[inode].prev_node;
+            RREdgeId prev_edge = route_ctx.rr_node_route_inf[inode].prev_edge;
             VTR_LOG("rr_node: %d prev_node: %d prev_edge: %d",
-                    inode, prev_node, prev_edge);
+                    size_t(inode), size_t(prev_node), size_t(prev_edge));
 
-            if (prev_node != OPEN && prev_edge != OPEN && !device_ctx.rr_nodes[prev_node].edge_is_configurable(prev_edge)) {
+            if (prev_node != RRNodeId::INVALID() && prev_edge != RREdgeId::INVALID() && !device_ctx.rr_graph.edge_is_configurable(prev_edge)) {
                 VTR_LOG("*");
             }
 
@@ -1868,23 +1862,24 @@ void print_rr_node_route_inf_dot() {
 
     VTR_LOG("digraph G {\n");
     VTR_LOG("\tnode[shape=record]\n");
-    for (size_t inode = 0; inode < route_ctx.rr_node_route_inf.size(); ++inode) {
+
+    for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) {
         if (!std::isinf(route_ctx.rr_node_route_inf[inode].path_cost)) {
-            VTR_LOG("\tnode%zu[label=\"{%zu (%s)", inode, inode, device_ctx.rr_nodes[inode].type_string());
-            if (route_ctx.rr_node_route_inf[inode].occ() > device_ctx.rr_nodes[inode].capacity()) {
+            VTR_LOG("\tnode%zu[label=\"{%zu (%s)", size_t(inode), size_t(inode), rr_node_typename[device_ctx.rr_graph.node_type(inode)]);
+            if (route_ctx.rr_node_route_inf[inode].occ() > device_ctx.rr_graph.node_capacity(inode)) {
                 VTR_LOG(" x");
             }
             VTR_LOG("}\"]\n");
         }
     }
-    for (size_t inode = 0; inode < route_ctx.rr_node_route_inf.size(); ++inode) {
+    for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) {
         if (!std::isinf(route_ctx.rr_node_route_inf[inode].path_cost)) {
-            int prev_node = route_ctx.rr_node_route_inf[inode].prev_node;
-            int prev_edge = route_ctx.rr_node_route_inf[inode].prev_edge;
+            RRNodeId prev_node = route_ctx.rr_node_route_inf[inode].prev_node;
+            RREdgeId prev_edge = route_ctx.rr_node_route_inf[inode].prev_edge;
 
-            if (prev_node != OPEN && prev_edge != OPEN) {
-                VTR_LOG("\tnode%d -> node%zu [", prev_node, inode);
-                if (prev_node != OPEN && prev_edge != OPEN && !device_ctx.rr_nodes[prev_node].edge_is_configurable(prev_edge)) {
+            if (prev_node != RRNodeId::INVALID() && prev_edge != RREdgeId::INVALID()) {
+                VTR_LOG("\tnode%ld -> node%ld [", size_t(prev_node), size_t(inode));
+                if (prev_node != RRNodeId::INVALID() && prev_edge != RREdgeId::INVALID() && !device_ctx.rr_graph.edge_is_configurable(prev_edge)) {
                     VTR_LOG("label=\"*\"");
                 }
 
@@ -1896,26 +1891,35 @@ void print_rr_node_route_inf_dot() {
     VTR_LOG("}\n");
 }
 
-static bool validate_trace_nodes(t_trace* head, const std::unordered_set<int>& trace_nodes) {
+static bool validate_trace_nodes(t_trace* head, const std::unordered_set<RRNodeId>& trace_nodes) {
     //Verifies that all nodes in the traceback 'head' are conatined in 'trace_nodes'
 
     if (!head) {
         return true;
     }
 
-    std::vector<int> missing_from_trace_nodes;
+    std::vector<RRNodeId> missing_from_trace_nodes;
     for (t_trace* tptr = head; tptr != nullptr; tptr = tptr->next) {
         if (!trace_nodes.count(tptr->index)) {
             missing_from_trace_nodes.push_back(tptr->index);
         }
     }
 
+    
     if (!missing_from_trace_nodes.empty()) {
+        std::string missing_from_trace_nodes_str;
+        for (const RRNodeId& node : missing_from_trace_nodes) {
+          if (&node != &missing_from_trace_nodes[0]) {
+            missing_from_trace_nodes_str += std::string(", ");
+          }
+          missing_from_trace_nodes_str += std::to_string(size_t(node));
+        }
+
         std::string msg = vtr::string_fmt(
             "The following %zu nodes were found in traceback"
             " but were missing from trace_nodes: %s\n",
             missing_from_trace_nodes.size(),
-            vtr::join(missing_from_trace_nodes, ", ").c_str());
+            missing_from_trace_nodes_str.c_str());
 
         VPR_FATAL_ERROR(VPR_ERROR_ROUTE, msg.c_str());
         return false;
diff --git a/vpr/src/route/route_common.h b/vpr/src/route/route_common.h
index 86fb216a5..bf02d76bc 100644
--- a/vpr/src/route/route_common.h
+++ b/vpr/src/route/route_common.h
@@ -41,11 +41,18 @@ struct t_heap {
     RRNodeId index = RRNodeId::INVALID();
 
     struct t_prev {
-        RRNodeId& node;
-        RREdgeId& edge;
+        RRNodeId node;
+        RREdgeId edge;
     };
 
-    union {
+    /* Xifan Tang - type union was used here, 
+     * but it causes an error in vtr_memory.h
+     * when allocating the data structure.
+     * I change to struct here.
+     * TODO: investigate the source of errors
+     * and see if this will cause memory overhead
+     */
+    struct {
         t_heap* next;
         t_prev prev;
     } u;
@@ -60,7 +67,7 @@ t_bb load_net_route_bb(ClusterNetId net_id, int bb_factor);
 void pathfinder_update_path_cost(t_trace* route_segment_start,
                                  int add_or_sub,
                                  float pres_fac);
-void pathfinder_update_single_node_cost(int inode, int add_or_sub, float pres_fac);
+void pathfinder_update_single_node_cost(const RRNodeId& inode, int add_or_sub, float pres_fac);
 
 void pathfinder_update_cost(float pres_fac, float acc_fac);
 
@@ -71,7 +78,7 @@ void reset_path_costs(const std::vector<RRNodeId>& visited_rr_nodes);
 float get_rr_cong_cost(const RRNodeId& inode);
 
 void mark_ends(ClusterNetId net_id);
-void mark_remaining_ends(const std::vector<int>& remaining_sinks);
+void mark_remaining_ends(const std::vector<RRNodeId>& remaining_sinks);
 
 void add_to_heap(t_heap* hptr);
 t_heap* alloc_heap_data();

From 5139b5d194eec67fe2e2ea69a2ca3980ff91d0cb Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 1 Feb 2020 17:16:31 -0700
Subject: [PATCH 074/645] adapt route_timing to use RRGraph object

---
 vpr/src/route/connection_based_routing.h |   2 +-
 vpr/src/route/route_common.cpp           |   6 +-
 vpr/src/route/route_common.h             |   2 +-
 vpr/src/route/route_timing.cpp           | 167 ++++++++++++-----------
 vpr/src/route/route_timing.h             |   4 +-
 5 files changed, 92 insertions(+), 89 deletions(-)

diff --git a/vpr/src/route/connection_based_routing.h b/vpr/src/route/connection_based_routing.h
index 0a4049e8c..d604607f8 100644
--- a/vpr/src/route/connection_based_routing.h
+++ b/vpr/src/route/connection_based_routing.h
@@ -34,7 +34,7 @@ class Connection_based_routing_resources {
     Connection_based_routing_resources();
     // adding to the resources when they are reached during pruning
     // mark rr sink node as something that still needs to be reached
-    void toreach_rr_sink(int rr_sink_node) { remaining_targets.push_back(rr_sink_node); }
+    void toreach_rr_sink(const int& rr_sink_node) { remaining_targets.push_back(rr_sink_node); }
     // mark rt sink node as something that has been legally reached
     void reached_rt_sink(t_rt_node* rt_sink) { reached_rt_sinks.push_back(rt_sink); }
 
diff --git a/vpr/src/route/route_common.cpp b/vpr/src/route/route_common.cpp
index 5ae9086c3..30fd9811a 100644
--- a/vpr/src/route/route_common.cpp
+++ b/vpr/src/route/route_common.cpp
@@ -767,11 +767,11 @@ void mark_ends(ClusterNetId net_id) {
     }
 }
 
-void mark_remaining_ends(const std::vector<RRNodeId>& remaining_sinks) {
+void mark_remaining_ends(const std::vector<int>& remaining_sinks) {
     // like mark_ends, but only performs it for the remaining sinks of a net
     auto& route_ctx = g_vpr_ctx.mutable_routing();
-    for (const RRNodeId& sink_node : remaining_sinks)
-        ++route_ctx.rr_node_route_inf[sink_node].target_flag;
+    for (const int& sink_node : remaining_sinks)
+        ++route_ctx.rr_node_route_inf[RRNodeId(sink_node)].target_flag;
 }
 
 void node_to_heap(const RRNodeId& inode, float total_cost, const RRNodeId& prev_node, const RREdgeId& prev_edge, float backward_path_cost, float R_upstream) {
diff --git a/vpr/src/route/route_common.h b/vpr/src/route/route_common.h
index bf02d76bc..a7aa9503c 100644
--- a/vpr/src/route/route_common.h
+++ b/vpr/src/route/route_common.h
@@ -78,7 +78,7 @@ void reset_path_costs(const std::vector<RRNodeId>& visited_rr_nodes);
 float get_rr_cong_cost(const RRNodeId& inode);
 
 void mark_ends(ClusterNetId net_id);
-void mark_remaining_ends(const std::vector<RRNodeId>& remaining_sinks);
+void mark_remaining_ends(const std::vector<int>& remaining_sinks);
 
 void add_to_heap(t_heap* hptr);
 t_heap* alloc_heap_data();
diff --git a/vpr/src/route/route_timing.cpp b/vpr/src/route/route_timing.cpp
index 47d1a3b2c..156197be7 100644
--- a/vpr/src/route/route_timing.cpp
+++ b/vpr/src/route/route_timing.cpp
@@ -148,7 +148,7 @@ static bool timing_driven_route_sink(ClusterNetId net_id,
 
 static bool timing_driven_pre_route_to_clock_root(
     ClusterNetId net_id,
-    int sink_node,
+    const RRNodeId& sink_node,
     const t_conn_cost_params cost_params,
     float pres_fac,
     int high_fanout_threshold,
@@ -158,12 +158,12 @@ static bool timing_driven_pre_route_to_clock_root(
     RouterStats& router_stats);
 
 static t_heap* timing_driven_route_connection_from_route_tree_high_fanout(t_rt_node* rt_root,
-                                                                          int sink_node,
+                                                                          const RRNodeId& sink_node,
                                                                           const t_conn_cost_params cost_params,
                                                                           t_bb bounding_box,
                                                                           const RouterLookahead& router_lookahead,
                                                                           const SpatialRouteTreeLookup& spatial_rt_lookup,
-                                                                          std::vector<int>& modified_rr_node_inf,
+                                                                          std::vector<RRNodeId>& modified_rr_node_inf,
                                                                           RouterStats& router_stats);
 
 static t_heap* timing_driven_route_connection_from_heap(const RRNodeId& sink_node,
@@ -173,9 +173,9 @@ static t_heap* timing_driven_route_connection_from_heap(const RRNodeId& sink_nod
                                                         std::vector<RRNodeId>& modified_rr_node_inf,
                                                         RouterStats& router_stats);
 
-static std::vector<t_heap> timing_driven_find_all_shortest_paths_from_heap(const t_conn_cost_params cost_params,
+static vtr::vector<RRNodeId, t_heap> timing_driven_find_all_shortest_paths_from_heap(const t_conn_cost_params cost_params,
                                                                            t_bb bounding_box,
-                                                                           std::vector<int>& modified_rr_node_inf,
+                                                                           std::vector<RRNodeId>& modified_rr_node_inf,
                                                                            RouterStats& router_stats);
 
 void disable_expansion_and_remove_sink_from_route_tree_nodes(t_rt_node* node);
@@ -196,7 +196,7 @@ static void add_route_tree_to_heap(t_rt_node* rt_node,
                                    RouterStats& router_stats);
 
 static t_bb add_high_fanout_route_tree_to_heap(t_rt_node* rt_root,
-                                               int target_node,
+                                               const RRNodeId& target_node,
                                                const t_conn_cost_params cost_params,
                                                const RouterLookahead& router_lookahead,
                                                const SpatialRouteTreeLookup& spatial_route_tree_lookup,
@@ -246,13 +246,13 @@ static void timing_driven_expand_node(const t_conn_cost_params cost_params,
                                       const RREdgeId& iconn,
                                       const RRNodeId& target_node);
 
-static void evaluate_timing_driven_node_costs(t_heap* from,
+static void evaluate_timing_driven_node_costs(t_heap* to,
                                               const t_conn_cost_params cost_params,
                                               const RouterLookahead& router_lookahead,
-                                              const int from_node,
-                                              const int to_node,
-                                              const int iconn,
-                                              const int target_node);
+                                              const RRNodeId& from_node,
+                                              const RRNodeId& to_node,
+                                              const RREdgeId& iconn,
+                                              const RRNodeId& target_node);
 
 static bool timing_driven_check_net_delays(vtr::vector<ClusterNetId, float*>& net_delay);
 
@@ -286,7 +286,7 @@ static void print_route_status(int itry,
                                std::shared_ptr<const SetupHoldTimingInfo> timing_info,
                                float est_success_iteration);
 
-static std::string describe_unrouteable_connection(const int source_node, const int sink_node);
+static std::string describe_unrouteable_connection(const RRNodeId& source_node, const RRNodeId& sink_node);
 
 static bool is_high_fanout(int fanout, int fanout_threshold);
 
@@ -310,7 +310,7 @@ static void generate_route_timing_reports(const t_router_opts& router_opts,
 
 static void prune_unused_non_configurable_nets(CBRR& connections_inf);
 
-static bool same_non_config_node_set(int from_node, int to_node);
+static bool same_non_config_node_set(const RRNodeId& from_node, const RRNodeId& to_node);
 
 /************************ Subroutine definitions *****************************/
 bool try_timing_driven_route(const t_router_opts& router_opts,
@@ -1008,7 +1008,7 @@ bool timing_driven_route_net(ClusterNetId net_id,
     // Pre-route to clock source for clock nets (marked as global nets)
     if (cluster_ctx.clb_nlist.net_is_global(net_id) && router_opts.two_stage_clock_routing) {
         VTR_ASSERT(router_opts.clock_modeling == DEDICATED_NETWORK);
-        int sink_node = device_ctx.virtual_clock_network_root_idx;
+        RRNodeId sink_node = RRNodeId(device_ctx.virtual_clock_network_root_idx);
         enable_router_debug(router_opts, net_id, sink_node);
         // Set to the max timing criticality which should intern minimize clock insertion
         // delay by selecting a direct route from the clock source to the virtual sink
@@ -1030,7 +1030,7 @@ bool timing_driven_route_net(ClusterNetId net_id,
     for (unsigned itarget = 0; itarget < remaining_targets.size(); ++itarget) {
         int target_pin = remaining_targets[itarget];
 
-        int sink_rr = route_ctx.net_rr_terminals[net_id][target_pin];
+        RRNodeId sink_rr = route_ctx.net_rr_terminals[net_id][target_pin];
 
         enable_router_debug(router_opts, net_id, sink_rr);
 
@@ -1069,12 +1069,12 @@ bool timing_driven_route_net(ClusterNetId net_id,
     if (!cluster_ctx.clb_nlist.net_is_ignored(net_id)) {
         for (unsigned ipin = 1; ipin < cluster_ctx.clb_nlist.net_pins(net_id).size(); ++ipin) {
             if (net_delay[ipin] == 0) { // should be SOURCE->OPIN->IPIN->SINK
-                VTR_ASSERT(device_ctx.rr_nodes[rt_node_of_sink[ipin]->parent_node->parent_node->inode].type() == OPIN);
+                VTR_ASSERT(device_ctx.rr_graph.node_type(RRNodeId(rt_node_of_sink[ipin]->parent_node->parent_node->inode)) == OPIN);
             }
         }
     }
 
-    VTR_ASSERT_MSG(route_ctx.rr_node_route_inf[rt_root->inode].occ() <= device_ctx.rr_nodes[rt_root->inode].capacity(), "SOURCE should never be congested");
+    VTR_ASSERT_MSG(route_ctx.rr_node_route_inf[rt_root->inode].occ() <= device_ctx.rr_graph.node_capacity(rt_root->inode), "SOURCE should never be congested");
 
     // route tree is not kept persistent since building it from the traceback the next iteration takes almost 0 time
     VTR_LOGV_DEBUG(f_router_debug, "Routed Net %zu (%zu sinks)\n", size_t(net_id), num_sinks);
@@ -1084,7 +1084,7 @@ bool timing_driven_route_net(ClusterNetId net_id,
 
 static bool timing_driven_pre_route_to_clock_root(
     ClusterNetId net_id,
-    int sink_node,
+    const RRNodeId& sink_node,
     const t_conn_cost_params cost_params,
     float pres_fac,
     int high_fanout_threshold,
@@ -1100,7 +1100,7 @@ static bool timing_driven_pre_route_to_clock_root(
 
     VTR_LOGV_DEBUG(f_router_debug, "Net %zu pre-route to (%s)\n", size_t(net_id), describe_rr_node(sink_node).c_str());
 
-    std::vector<int> modified_rr_node_inf;
+    std::vector<RRNodeId> modified_rr_node_inf;
 
     profiling::sink_criticality_start();
 
@@ -1198,13 +1198,13 @@ static bool timing_driven_route_sink(ClusterNetId net_id,
 
     profiling::sink_criticality_start();
 
-    int sink_node = route_ctx.net_rr_terminals[net_id][target_pin];
+    RRNodeId sink_node = route_ctx.net_rr_terminals[net_id][target_pin];
 
     VTR_LOGV_DEBUG(f_router_debug, "Net %zu Target %d (%s)\n", size_t(net_id), itarget, describe_rr_node(sink_node).c_str());
 
     VTR_ASSERT_DEBUG(verify_traceback_route_tree_equivalent(route_ctx.trace[net_id].head, rt_root));
 
-    std::vector<int> modified_rr_node_inf;
+    std::vector<RRNodeId> modified_rr_node_inf;
     t_heap* cheapest = nullptr;
     t_bb bounding_box = route_ctx.route_bb[net_id];
 
@@ -1265,7 +1265,7 @@ static bool timing_driven_route_sink(ClusterNetId net_id,
      * lets me reuse all the routines written for breadth-first routing, which  *
      * all take a traceback structure as input.                                 */
 
-    int inode = cheapest->index;
+    RRNodeId inode = cheapest->index;
     route_ctx.rr_node_route_inf[inode].target_flag--; /* Connected to this SINK. */
     t_trace* new_route_start_tptr = update_traceback(cheapest, net_id);
     VTR_ASSERT_DEBUG(validate_traceback(route_ctx.trace[net_id].head));
@@ -1388,19 +1388,19 @@ t_heap* timing_driven_route_connection_from_route_tree(t_rt_node* rt_root,
 //Unlike timing_driven_route_connection_from_route_tree(), only part of the route tree
 //which is spatially close to the sink is added to the heap.
 static t_heap* timing_driven_route_connection_from_route_tree_high_fanout(t_rt_node* rt_root,
-                                                                          int sink_node,
+                                                                          const RRNodeId& sink_node,
                                                                           const t_conn_cost_params cost_params,
                                                                           t_bb net_bounding_box,
                                                                           const RouterLookahead& router_lookahead,
                                                                           const SpatialRouteTreeLookup& spatial_rt_lookup,
-                                                                          std::vector<int>& modified_rr_node_inf,
+                                                                          std::vector<RRNodeId>& modified_rr_node_inf,
                                                                           RouterStats& router_stats) {
     // re-explore route tree from root to add any new nodes (buildheap afterwards)
     // route tree needs to be repushed onto the heap since each node's cost is target specific
     t_bb high_fanout_bb = add_high_fanout_route_tree_to_heap(rt_root, sink_node, cost_params, router_lookahead, spatial_rt_lookup, net_bounding_box, router_stats);
     heap_::build_heap(); // via sifting down everything
 
-    int source_node = rt_root->inode;
+    RRNodeId source_node = rt_root->inode;
 
     if (is_empty_heap()) {
         VTR_LOG("No source in route tree: %s\n", describe_unrouteable_connection(source_node, sink_node).c_str());
@@ -1409,7 +1409,8 @@ static t_heap* timing_driven_route_connection_from_route_tree_high_fanout(t_rt_n
         return nullptr;
     }
 
-    VTR_LOGV_DEBUG(f_router_debug, "  Routing to %d as high fanout net (BB: %d,%d x %d,%d)\n", sink_node,
+    VTR_LOGV_DEBUG(f_router_debug, "  Routing to %ld as high fanout net (BB: %d,%d x %d,%d)\n", 
+                   size_t(sink_node),
                    high_fanout_bb.xmin, high_fanout_bb.ymin,
                    high_fanout_bb.xmax, high_fanout_bb.ymax);
 
@@ -1423,7 +1424,7 @@ static t_heap* timing_driven_route_connection_from_route_tree_high_fanout(t_rt_n
     if (cheapest == nullptr) {
         //Found no path, that may be due to an unlucky choice of existing route tree sub-set,
         //try again with the full route tree to be sure this is not an artifact of high-fanout routing
-        VTR_LOG_WARN("No routing path found in high-fanout mode for net connection (to sink_rr %d), retrying with full route tree\n", sink_node);
+        VTR_LOG_WARN("No routing path found in high-fanout mode for net connection (to sink_rr %ld), retrying with full route tree\n", size_t(sink_node));
 
         //Reset any previously recorded node costs so timing_driven_route_connection()
         //starts over from scratch.
@@ -1504,13 +1505,13 @@ static t_heap* timing_driven_route_connection_from_heap(const RRNodeId& sink_nod
 }
 
 //Find shortest paths from specified route tree to all nodes in the RR graph
-std::vector<t_heap> timing_driven_find_all_shortest_paths_from_route_tree(t_rt_node* rt_root,
+vtr::vector<RRNodeId, t_heap> timing_driven_find_all_shortest_paths_from_route_tree(t_rt_node* rt_root,
                                                                           const t_conn_cost_params cost_params,
                                                                           t_bb bounding_box,
-                                                                          std::vector<int>& modified_rr_node_inf,
+                                                                          std::vector<RRNodeId>& modified_rr_node_inf,
                                                                           RouterStats& router_stats) {
     //Add the route tree to the heap with no specific target node
-    int target_node = OPEN;
+    RRNodeId target_node = RRNodeId::INVALID();
     auto router_lookahead = make_router_lookahead(e_router_lookahead::NO_OP,
                                                   /*write_lookahead=*/"", /*read_lookahead=*/"",
                                                   /*segment_inf=*/{});
@@ -1529,16 +1530,16 @@ std::vector<t_heap> timing_driven_find_all_shortest_paths_from_route_tree(t_rt_n
 //
 //Note that to re-use code used for the regular A*-based router we use a
 //no-operation lookahead which always returns zero.
-static std::vector<t_heap> timing_driven_find_all_shortest_paths_from_heap(const t_conn_cost_params cost_params,
+static vtr::vector<RRNodeId, t_heap> timing_driven_find_all_shortest_paths_from_heap(const t_conn_cost_params cost_params,
                                                                            t_bb bounding_box,
-                                                                           std::vector<int>& modified_rr_node_inf,
+                                                                           std::vector<RRNodeId>& modified_rr_node_inf,
                                                                            RouterStats& router_stats) {
     auto router_lookahead = make_router_lookahead(e_router_lookahead::NO_OP,
                                                   /*write_lookahead=*/"", /*read_lookahead=*/"",
                                                   /*segment_inf=*/{});
 
     auto& device_ctx = g_vpr_ctx.device();
-    std::vector<t_heap> cheapest_paths(device_ctx.rr_nodes.size());
+    vtr::vector<RRNodeId, t_heap> cheapest_paths(device_ctx.rr_graph.nodes().size());
 
     VTR_ASSERT_SAFE(heap_::is_valid());
 
@@ -1551,16 +1552,16 @@ static std::vector<t_heap> timing_driven_find_all_shortest_paths_from_heap(const
         t_heap* cheapest = get_heap_head();
         ++router_stats.heap_pops;
 
-        int inode = cheapest->index;
-        VTR_LOGV_DEBUG(f_router_debug, "  Popping node %d (cost: %g)\n",
-                       inode, cheapest->cost);
+        RRNodeId inode = cheapest->index;
+        VTR_LOGV_DEBUG(f_router_debug, "  Popping node %ld (cost: %g)\n",
+                       size_t(inode), cheapest->cost);
 
         //Since we want to find shortest paths to all nodes in the graph
         //we do not specify a target node.
         //
         //By setting the target_node to OPEN in combination with the NoOp router
         //lookahead we can re-use the node exploration code from the regular router
-        int target_node = OPEN;
+        RRNodeId target_node = RRNodeId::INVALID();
 
         timing_driven_expand_cheapest(cheapest,
                                       target_node,
@@ -1570,11 +1571,11 @@ static std::vector<t_heap> timing_driven_find_all_shortest_paths_from_heap(const
                                       modified_rr_node_inf,
                                       router_stats);
 
-        if (cheapest_paths[inode].index == OPEN || cheapest_paths[inode].cost >= cheapest->cost) {
-            VTR_LOGV_DEBUG(f_router_debug, "  Better cost to node %d: %g (was %g)\n", inode, cheapest->cost, cheapest_paths[inode].cost);
+        if (cheapest_paths[inode].index == RRNodeId::INVALID() || cheapest_paths[inode].cost >= cheapest->cost) {
+            VTR_LOGV_DEBUG(f_router_debug, "  Better cost to node %ld: %g (was %g)\n", size_t(inode), cheapest->cost, cheapest_paths[inode].cost);
             cheapest_paths[inode] = *cheapest;
         } else {
-            VTR_LOGV_DEBUG(f_router_debug, "  Worse cost to node %d: %g (better %g)\n", inode, cheapest->cost, cheapest_paths[inode].cost);
+            VTR_LOGV_DEBUG(f_router_debug, "  Worse cost to node %ld: %g (better %g)\n", size_t(inode), cheapest->cost, cheapest_paths[inode].cost);
         }
 
         free_heap_data(cheapest);
@@ -1779,9 +1780,9 @@ void disable_expansion_and_remove_sink_from_route_tree_nodes(t_rt_node* rt_node)
 
     while (linked_rt_edge != nullptr) {
         child_node = linked_rt_edge->child;
-        if (device_ctx.rr_nodes[child_node->inode].type() == SINK) {
+        if (device_ctx.rr_graph.node_type(child_node->inode) == SINK) {
             VTR_LOGV_DEBUG(f_router_debug,
-                           "Removing sink %d from route tree\n", child_node->inode);
+                           "Removing sink %ld from route tree\n", size_t(child_node->inode));
             rt_node->u.child_list = nullptr;
             rt_node->u.next = nullptr;
             free(child_node);
@@ -1789,7 +1790,7 @@ void disable_expansion_and_remove_sink_from_route_tree_nodes(t_rt_node* rt_node)
         } else {
             rt_node->re_expand = false;
             VTR_LOGV_DEBUG(f_router_debug,
-                           "unexpanding: %d in route tree\n", rt_node->inode);
+                           "unexpanding: %ld in route tree\n", size_t(rt_node->inode));
         }
         disable_expansion_and_remove_sink_from_route_tree_nodes(child_node);
         linked_rt_edge = linked_rt_edge->next;
@@ -1830,7 +1831,7 @@ static void add_route_tree_to_heap(t_rt_node* rt_node,
     }
 }
 
-static t_bb add_high_fanout_route_tree_to_heap(t_rt_node* rt_root, int target_node, const t_conn_cost_params cost_params, const RouterLookahead& router_lookahead, const SpatialRouteTreeLookup& spatial_rt_lookup, t_bb net_bounding_box, RouterStats& router_stats) {
+static t_bb add_high_fanout_route_tree_to_heap(t_rt_node* rt_root, const RRNodeId& target_node, const t_conn_cost_params cost_params, const RouterLookahead& router_lookahead, const SpatialRouteTreeLookup& spatial_rt_lookup, t_bb net_bounding_box, RouterStats& router_stats) {
     //For high fanout nets we only add those route tree nodes which are spatially close
     //to the sink.
     //
@@ -1844,18 +1845,16 @@ static t_bb add_high_fanout_route_tree_to_heap(t_rt_node* rt_root, int target_no
     auto& device_ctx = g_vpr_ctx.device();
 
     //Determine which bin the target node is located in
-    auto& target_rr_node = device_ctx.rr_nodes[target_node];
-
-    int target_bin_x = grid_to_bin_x(target_rr_node.xlow(), spatial_rt_lookup);
-    int target_bin_y = grid_to_bin_y(target_rr_node.ylow(), spatial_rt_lookup);
+    int target_bin_x = grid_to_bin_x(device_ctx.rr_graph.node_xlow(target_node), spatial_rt_lookup);
+    int target_bin_y = grid_to_bin_y(device_ctx.rr_graph.node_ylow(target_node), spatial_rt_lookup);
 
     int nodes_added = 0;
 
     t_bb highfanout_bb;
-    highfanout_bb.xmin = target_rr_node.xlow();
-    highfanout_bb.xmax = target_rr_node.xhigh();
-    highfanout_bb.ymin = target_rr_node.ylow();
-    highfanout_bb.ymax = target_rr_node.yhigh();
+    highfanout_bb.xmin = device_ctx.rr_graph.node_xlow(target_node);
+    highfanout_bb.xmax = device_ctx.rr_graph.node_xhigh(target_node);
+    highfanout_bb.ymin = device_ctx.rr_graph.node_ylow(target_node);
+    highfanout_bb.ymax = device_ctx.rr_graph.node_yhigh(target_node);
 
     //Add existing routing starting from the target bin.
     //If the target's bin has insufficient existing routing add from the surrounding bins
@@ -1877,11 +1876,11 @@ static t_bb add_high_fanout_route_tree_to_heap(t_rt_node* rt_root, int target_no
                 add_route_tree_node_to_heap(rt_node, target_node, cost_params, router_lookahead, router_stats);
 
                 //Update Bounding Box
-                auto& rr_node = device_ctx.rr_nodes[rt_node->inode];
-                highfanout_bb.xmin = std::min<int>(highfanout_bb.xmin, rr_node.xlow());
-                highfanout_bb.ymin = std::min<int>(highfanout_bb.ymin, rr_node.ylow());
-                highfanout_bb.xmax = std::max<int>(highfanout_bb.xmax, rr_node.xhigh());
-                highfanout_bb.ymax = std::max<int>(highfanout_bb.ymax, rr_node.yhigh());
+                auto& rr_node = rt_node->inode;
+                highfanout_bb.xmin = std::min<int>(highfanout_bb.xmin, device_ctx.rr_graph.node_xlow(rr_node));
+                highfanout_bb.ymin = std::min<int>(highfanout_bb.ymin, device_ctx.rr_graph.node_ylow(rr_node));
+                highfanout_bb.xmax = std::max<int>(highfanout_bb.xmax, device_ctx.rr_graph.node_xhigh(rr_node));
+                highfanout_bb.ymax = std::max<int>(highfanout_bb.ymax, device_ctx.rr_graph.node_yhigh(rr_node));
 
                 ++nodes_added;
             }
@@ -1933,7 +1932,7 @@ static void add_route_tree_node_to_heap(t_rt_node* rt_node,
                                         const t_conn_cost_params cost_params,
                                         const RouterLookahead& router_lookahead,
                                         RouterStats& router_stats) {
-    const RRNodeId& inode = rt_node->inode_id;
+    const RRNodeId& inode = rt_node->inode;
     float backward_path_cost = cost_params.criticality * rt_node->Tdel;
 
     float R_upstream = rt_node->R_upstream;
@@ -1973,7 +1972,7 @@ static void timing_driven_expand_neighbours(t_heap* current,
     auto& device_ctx = g_vpr_ctx.device();
 
     t_bb target_bb;
-    if (target_node != OPEN) {
+    if (target_node != RRNodeId::INVALID()) {
         target_bb.xmin = device_ctx.rr_graph.node_xlow(target_node);
         target_bb.ymin = device_ctx.rr_graph.node_ylow(target_node);
         target_bb.xmax = device_ctx.rr_graph.node_xhigh(target_node);
@@ -1982,7 +1981,7 @@ static void timing_driven_expand_neighbours(t_heap* current,
 
     //For each node associated with the current heap element, expand all of it's neighbours
     for (const RREdgeId& edge : device_ctx.rr_graph.node_out_edges(current->index)) {
-        const RRNodeId& to_node = device_ctx.rr_graph.edge_sink_node[edge];
+        const RRNodeId& to_node = device_ctx.rr_graph.edge_sink_node(edge);
         timing_driven_expand_neighbour(current,
                                        current->index, edge, to_node,
                                        cost_params,
@@ -2032,7 +2031,7 @@ static void timing_driven_expand_neighbour(t_heap* current,
      * the issue of how to cost them properly so they don't get expanded before *
      * more promising routes, but makes route-throughs (via CLBs) impossible.   *
      * Change this if you want to investigate route-throughs.                   */
-    if (target_node != OPEN) {
+    if (target_node != RRNodeId::INVALID()) {
         t_rr_type to_type = device_ctx.rr_graph.node_type(to_node);
         if (to_type == IPIN) {
             //Check if this IPIN leads to the target block
@@ -2084,8 +2083,8 @@ static void timing_driven_add_to_heap(const t_conn_cost_params cost_params,
 
     auto& route_ctx = g_vpr_ctx.routing();
 
-    float best_total_cost = route_ctx.rr_node_route_inf[size_t(to_node)].path_cost;
-    float best_back_cost = route_ctx.rr_node_route_inf[size_t(to_node)].backward_path_cost;
+    float best_total_cost = route_ctx.rr_node_route_inf[to_node].path_cost;
+    float best_back_cost = route_ctx.rr_node_route_inf[to_node].backward_path_cost;
 
     float new_total_cost = next->cost;
     float new_back_cost = next->backward_path_cost;
@@ -2316,9 +2315,9 @@ static bool should_route_net(ClusterNetId net_id, CBRR& connections_inf, bool if
     }
 
     for (;;) {
-        int inode = tptr->index;
+        RRNodeId inode = tptr->index;
         int occ = route_ctx.rr_node_route_inf[inode].occ();
-        int capacity = device_ctx.rr_nodes[inode].capacity();
+        int capacity = device_ctx.rr_graph.node_capacity(inode);
 
         if (occ > capacity) {
             return true; /* overuse detected */
@@ -2327,7 +2326,8 @@ static bool should_route_net(ClusterNetId net_id, CBRR& connections_inf, bool if
         if (tptr->iswitch == OPEN) { //End of a branch
             // even if net is fully routed, not complete if parts of it should get ripped up (EXPERIMENTAL)
             if (if_force_reroute) {
-                if (connections_inf.should_force_reroute_connection(inode)) {
+                /* Xifan Tang - TODO: should use RRNodeId */ 
+                if (connections_inf.should_force_reroute_connection(size_t(inode))) {
                     return true;
                 }
             }
@@ -2405,8 +2405,8 @@ Connection_based_routing_resources::Connection_based_routing_resources()
             // rr sink node index corresponding to this connection terminal
             auto rr_sink_node = route_ctx.net_rr_terminals[net_id][ipin];
 
-            net_node_to_pin.insert({rr_sink_node, ipin});
-            net_forcible_reroute_connection_flag.insert({rr_sink_node, false});
+            net_node_to_pin.insert({size_t(rr_sink_node), ipin});
+            net_forcible_reroute_connection_flag.insert({size_t(rr_sink_node), false});
         }
     }
 }
@@ -2440,7 +2440,8 @@ void Connection_based_routing_resources::put_sink_rt_nodes_in_net_pins_lookup(co
     const auto& node_to_pin_mapping = rr_sink_node_to_pin[current_inet];
 
     for (t_rt_node* rt_node : sink_rt_nodes) {
-        auto mapping = node_to_pin_mapping.find(rt_node->inode);
+        /* Xifan Tang - TODO: should use RRNodeId later */
+        auto mapping = node_to_pin_mapping.find(size_t(rt_node->inode));
 
         if (mapping != node_to_pin_mapping.end()) {
             rt_node_of_sink[mapping->second] = rt_node;
@@ -2463,7 +2464,7 @@ bool Connection_based_routing_resources::sanity_check_lookup() const {
                 VTR_LOG("%d cannot find itself (net %lu)\n", mapping.first, size_t(net_id));
                 return false;
             }
-            VTR_ASSERT(route_ctx.net_rr_terminals[net_id][mapping.second] == mapping.first);
+            VTR_ASSERT(route_ctx.net_rr_terminals[net_id][mapping.second] == RRNodeId(mapping.first));
         }
     }
     return true;
@@ -2506,7 +2507,8 @@ bool Connection_based_routing_resources::forcibly_reroute_connections(float max_
             auto rr_sink_node = route_ctx.net_rr_terminals[net_id][ipin];
 
             //Clear any forced re-routing from the previuos iteration
-            forcible_reroute_connection_flag[net_id][rr_sink_node] = false;
+            /* Xifan Tang - TODO: should use RRNodeId later */
+            forcible_reroute_connection_flag[net_id][size_t(rr_sink_node)] = false;
 
             // skip if connection is internal to a block such that SOURCE->OPIN->IPIN->SINK directly, which would have 0 time delay
             if (lower_bound_connection_delay[net_id][ipin - 1] == 0)
@@ -2527,7 +2529,8 @@ bool Connection_based_routing_resources::forcibly_reroute_connections(float max_
             if (net_delay[net_id][ipin] < (lower_bound_connection_delay[net_id][ipin - 1] * connection_delay_optimality_tolerance))
                 continue;
 
-            forcible_reroute_connection_flag[net_id][rr_sink_node] = true;
+            /* Xifan Tang - TODO: should use RRNodeId later */
+            forcible_reroute_connection_flag[net_id][size_t(rr_sink_node)] = true;
             // note that we don't set forcible_reroute_connection_flag to false when the converse is true
             // resetting back to false will be done during tree pruning, after the sink has been legally reached
             any_connection_rerouted = true;
@@ -2562,7 +2565,7 @@ static OveruseInfo calculate_overuse_info() {
     auto& cluster_ctx = g_vpr_ctx.clustering();
     auto& route_ctx = g_vpr_ctx.routing();
 
-    std::unordered_set<int> checked_nodes;
+    std::unordered_set<RRNodeId> checked_nodes;
 
     size_t overused_nodes = 0;
     size_t total_overuse = 0;
@@ -2578,14 +2581,14 @@ static OveruseInfo calculate_overuse_info() {
     //used by routing, particularly on large devices).
     for (auto net_id : cluster_ctx.clb_nlist.nets()) {
         for (t_trace* tptr = route_ctx.trace[net_id].head; tptr != nullptr; tptr = tptr->next) {
-            int inode = tptr->index;
+            RRNodeId inode = tptr->index;
 
             auto result = checked_nodes.insert(inode);
             if (!result.second) { //Already counted
                 continue;
             }
 
-            int overuse = route_ctx.rr_node_route_inf[inode].occ() - device_ctx.rr_nodes[inode].capacity();
+            int overuse = route_ctx.rr_node_route_inf[inode].occ() - device_ctx.rr_graph.node_capacity(inode);
             if (overuse > 0) {
                 overused_nodes += 1;
 
@@ -2867,15 +2870,15 @@ static t_bb calc_current_bb(const t_trace* head) {
     bb.ymax = 0;
 
     for (const t_trace* elem = head; elem != nullptr; elem = elem->next) {
-        const t_rr_node& node = device_ctx.rr_nodes[elem->index];
+        const RRNodeId& node = elem->index;
         //The router interprets RR nodes which cross the boundary as being
         //'within' of the BB. Only thos which are *strictly* out side the
         //box are exluded, hence we use the nodes xhigh/yhigh for xmin/xmax,
         //and xlow/ylow for xmax/ymax calculations
-        bb.xmin = std::min<int>(bb.xmin, node.xhigh());
-        bb.ymin = std::min<int>(bb.ymin, node.yhigh());
-        bb.xmax = std::max<int>(bb.xmax, node.xlow());
-        bb.ymax = std::max<int>(bb.ymax, node.ylow());
+        bb.xmin = std::min<int>(bb.xmin, device_ctx.rr_graph.node_xhigh(node));
+        bb.ymin = std::min<int>(bb.ymin, device_ctx.rr_graph.node_yhigh(node));
+        bb.xmax = std::max<int>(bb.xmax, device_ctx.rr_graph.node_xlow(node));
+        bb.ymax = std::max<int>(bb.ymax, device_ctx.rr_graph.node_ylow(node));
     }
 
     VTR_ASSERT(bb.xmin <= bb.xmax);
@@ -2884,14 +2887,14 @@ static t_bb calc_current_bb(const t_trace* head) {
     return bb;
 }
 
-void enable_router_debug(const t_router_opts& router_opts, ClusterNetId net, int sink_rr) {
+void enable_router_debug(const t_router_opts& router_opts, ClusterNetId net, const RRNodeId& sink_rr) {
     bool all_net_debug = (router_opts.router_debug_net == -1);
 
     bool specific_net_debug = (router_opts.router_debug_net >= 0);
     bool specific_sink_debug = (router_opts.router_debug_sink_rr >= 0);
 
     bool match_net = (ClusterNetId(router_opts.router_debug_net) == net);
-    bool match_sink = (router_opts.router_debug_sink_rr == sink_rr);
+    bool match_sink = (router_opts.router_debug_sink_rr == (int)size_t(sink_rr));
 
     if (all_net_debug) {
         VTR_ASSERT(!specific_net_debug);
diff --git a/vpr/src/route/route_timing.h b/vpr/src/route/route_timing.h
index e7c808627..a6232bf88 100644
--- a/vpr/src/route/route_timing.h
+++ b/vpr/src/route/route_timing.h
@@ -87,10 +87,10 @@ t_heap* timing_driven_route_connection_from_route_tree(t_rt_node* rt_root,
                                                        std::vector<RRNodeId>& modified_rr_node_inf,
                                                        RouterStats& router_stats);
 
-std::vector<t_heap> timing_driven_find_all_shortest_paths_from_route_tree(t_rt_node* rt_root,
+vtr::vector<RRNodeId, t_heap> timing_driven_find_all_shortest_paths_from_route_tree(t_rt_node* rt_root,
                                                                           const t_conn_cost_params cost_params,
                                                                           t_bb bounding_box,
-                                                                          std::vector<int>& modified_rr_node_inf,
+                                                                          std::vector<RRNodeId>& modified_rr_node_inf,
                                                                           RouterStats& router_stats);
 
 struct timing_driven_route_structs {

From 400bd76bdc89e55ea22dbeb31b9ecb88a6722006 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 1 Feb 2020 17:56:14 -0700
Subject: [PATCH 075/645] route_tree_timing adopt RRGraph object

---
 vpr/src/route/route_tree_timing.cpp | 195 ++++++++++++++--------------
 vpr/src/route/route_tree_timing.h   |   2 +-
 2 files changed, 97 insertions(+), 100 deletions(-)

diff --git a/vpr/src/route/route_tree_timing.cpp b/vpr/src/route/route_tree_timing.cpp
index 3b947ee43..96f59272f 100644
--- a/vpr/src/route/route_tree_timing.cpp
+++ b/vpr/src/route/route_tree_timing.cpp
@@ -27,7 +27,7 @@
 /* Array below allows mapping from any rr_node to any rt_node currently in
  * the rt_tree.                                                              */
 
-static std::vector<t_rt_node*> rr_node_to_rt_node; /* [0..device_ctx.rr_graph.nodes().size()-1] */
+static vtr::vector<RRNodeId, t_rt_node*> rr_node_to_rt_node; /* [0..device_ctx.rr_graph.nodes().size()-1] */
 
 /* Frees lists for fast addition and deletion of nodes and edges. */
 
@@ -47,19 +47,19 @@ static void free_linked_rt_edge(t_linked_rt_edge* rt_edge);
 static t_rt_node* add_subtree_to_route_tree(t_heap* hptr,
                                             t_rt_node** sink_rt_node_ptr);
 
-static t_rt_node* add_non_configurable_to_route_tree(const int rr_node, const bool reached_by_non_configurable_edge, std::unordered_set<int>& visited);
+static t_rt_node* add_non_configurable_to_route_tree(const RRNodeId& rr_node, const bool reached_by_non_configurable_edge, std::unordered_set<RRNodeId>& visited);
 
 static t_rt_node* update_unbuffered_ancestors_C_downstream(t_rt_node* start_of_new_subtree_rt_node);
 
-bool verify_route_tree_recurr(t_rt_node* node, std::set<int>& seen_nodes);
+bool verify_route_tree_recurr(t_rt_node* node, std::set<RRNodeId>& seen_nodes);
 
 static t_rt_node* prune_route_tree_recurr(t_rt_node* node, CBRR& connections_inf, bool congested, std::vector<int>* non_config_node_set_usage);
 
-static t_trace* traceback_to_route_tree_branch(t_trace* trace, std::map<int, t_rt_node*>& rr_node_to_rt, std::vector<int>* non_config_node_set_usage);
+static t_trace* traceback_to_route_tree_branch(t_trace* trace, std::map<RRNodeId, t_rt_node*>& rr_node_to_rt, std::vector<int>* non_config_node_set_usage);
 
 static std::pair<t_trace*, t_trace*> traceback_from_route_tree_recurr(t_trace* head, t_trace* tail, const t_rt_node* node);
 
-void collect_route_tree_connections(const t_rt_node* node, std::set<std::tuple<int, int, int>>& connections);
+void collect_route_tree_connections(const t_rt_node* node, std::set<std::tuple<RRNodeId, int, RRNodeId>>& connections);
 
 /************************** Subroutine definitions ***************************/
 
@@ -84,7 +84,7 @@ bool alloc_route_tree_timing_structs(bool exists_ok) {
         }
     }
 
-    rr_node_to_rt_node = std::vector<t_rt_node*>(device_ctx.rr_graph.nodes().size(), nullptr);
+    rr_node_to_rt_node = vtr::vector<RRNodeId, t_rt_node*>(device_ctx.rr_graph.nodes().size(), nullptr);
 
     return true;
 }
@@ -173,7 +173,7 @@ static void free_linked_rt_edge(t_linked_rt_edge* rt_edge) {
  * node of the rt_tree (which is just the net source).                       */
 t_rt_node* init_route_tree_to_source(ClusterNetId inet) {
     t_rt_node* rt_root;
-    int inode;
+    RRNodeId inode;
 
     auto& route_ctx = g_vpr_ctx.routing();
     auto& device_ctx = g_vpr_ctx.device();
@@ -187,9 +187,9 @@ t_rt_node* init_route_tree_to_source(ClusterNetId inet) {
     inode = route_ctx.net_rr_terminals[inet][0]; /* Net source */
 
     rt_root->inode = inode;
-    rt_root->C_downstream = device_ctx.rr_nodes[inode].C();
-    rt_root->R_upstream = device_ctx.rr_nodes[inode].R();
-    rt_root->Tdel = 0.5 * device_ctx.rr_nodes[inode].R() * device_ctx.rr_nodes[inode].C();
+    rt_root->C_downstream = device_ctx.rr_graph.node_C(inode);
+    rt_root->R_upstream = device_ctx.rr_graph.node_R(inode);
+    rt_root->Tdel = 0.5 * device_ctx.rr_graph.node_R(inode) * device_ctx.rr_graph.node_C(inode);
     rr_node_to_rt_node[inode] = rt_root;
 
     return (rt_root);
@@ -263,7 +263,7 @@ add_subtree_to_route_tree(t_heap* hptr, t_rt_node** sink_rt_node_ptr) {
     auto& device_ctx = g_vpr_ctx.device();
     auto& route_ctx = g_vpr_ctx.routing();
 
-    int inode = hptr->index;
+    RRNodeId inode = hptr->index;
 
     //if (device_ctx.rr_nodes[inode].type() != SINK) {
     //VPR_FATAL_ERROR(VPR_ERROR_ROUTE,
@@ -286,11 +286,11 @@ add_subtree_to_route_tree(t_heap* hptr, t_rt_node** sink_rt_node_ptr) {
 
     downstream_rt_node = sink_rt_node;
 
-    std::unordered_set<int> main_branch_visited;
-    std::unordered_set<int> all_visited;
+    std::unordered_set<RRNodeId> main_branch_visited;
+    std::unordered_set<RRNodeId> all_visited;
     inode = hptr->u.prev.node;
-    t_edge_size iedge = hptr->u.prev.edge;
-    short iswitch = device_ctx.rr_nodes[inode].edge_switch(iedge);
+    RREdgeId iedge = hptr->u.prev.edge;
+    short iswitch = (short)size_t(device_ctx.rr_graph.edge_switch(iedge));
 
     /* For all "new" nodes in the main path */
     // inode is node index of previous node
@@ -319,7 +319,7 @@ add_subtree_to_route_tree(t_heap* hptr, t_rt_node** sink_rt_node_ptr) {
 
         rr_node_to_rt_node[inode] = rt_node;
 
-        if (device_ctx.rr_nodes[inode].type() == IPIN) {
+        if (device_ctx.rr_graph.node_type(inode) == IPIN) {
             rt_node->re_expand = false;
         } else {
             rt_node->re_expand = true;
@@ -328,7 +328,7 @@ add_subtree_to_route_tree(t_heap* hptr, t_rt_node** sink_rt_node_ptr) {
         downstream_rt_node = rt_node;
         iedge = route_ctx.rr_node_route_inf[inode].prev_edge;
         inode = route_ctx.rr_node_route_inf[inode].prev_node;
-        iswitch = device_ctx.rr_nodes[inode].edge_switch(iedge);
+        iswitch = (short)size_t(device_ctx.rr_graph.edge_switch(iedge));
     }
 
     //Inode is now the branch point to the old routing; do not need
@@ -347,7 +347,7 @@ add_subtree_to_route_tree(t_heap* hptr, t_rt_node** sink_rt_node_ptr) {
 
     //Expand (recursively) each of the main-branch nodes adding any
     //non-configurably connected nodes
-    for (int rr_node : main_branch_visited) {
+    for (const RRNodeId& rr_node : main_branch_visited) {
         add_non_configurable_to_route_tree(rr_node, false, all_visited);
     }
 
@@ -355,7 +355,7 @@ add_subtree_to_route_tree(t_heap* hptr, t_rt_node** sink_rt_node_ptr) {
     return (downstream_rt_node);
 }
 
-static t_rt_node* add_non_configurable_to_route_tree(const int rr_node, const bool reached_by_non_configurable_edge, std::unordered_set<int>& visited) {
+static t_rt_node* add_non_configurable_to_route_tree(const RRNodeId& rr_node, const bool reached_by_non_configurable_edge, std::unordered_set<RRNodeId>& visited) {
     t_rt_node* rt_node = nullptr;
 
     if (!visited.count(rr_node) || !reached_by_non_configurable_edge) {
@@ -375,7 +375,7 @@ static t_rt_node* add_non_configurable_to_route_tree(const int rr_node, const bo
                 rt_node->u.child_list = nullptr;
                 rt_node->inode = rr_node;
 
-                if (device_ctx.rr_nodes[rr_node].type() == IPIN) {
+                if (device_ctx.rr_graph.node_type(rr_node) == IPIN) {
                     rt_node->re_expand = false;
                 } else {
                     rt_node->re_expand = true;
@@ -385,18 +385,18 @@ static t_rt_node* add_non_configurable_to_route_tree(const int rr_node, const bo
             }
         }
 
-        for (int iedge : device_ctx.rr_nodes[rr_node].non_configurable_edges()) {
+        for (const RREdgeId& iedge : device_ctx.rr_graph.node_non_configurable_out_edges(rr_node)) {
             //Recursive case: expand children
-            VTR_ASSERT(!device_ctx.rr_nodes[rr_node].edge_is_configurable(iedge));
+            VTR_ASSERT(!device_ctx.rr_graph.edge_is_configurable(iedge));
 
-            int to_rr_node = device_ctx.rr_nodes[rr_node].edge_sink_node(iedge);
+            RRNodeId to_rr_node = device_ctx.rr_graph.edge_sink_node(iedge);
 
             //Recurse
             t_rt_node* child_rt_node = add_non_configurable_to_route_tree(to_rr_node, true, visited);
 
             if (!child_rt_node) continue;
 
-            int iswitch = device_ctx.rr_nodes[rr_node].edge_switch(iedge);
+            int iswitch = (short)size_t(device_ctx.rr_graph.edge_switch(iedge));
 
             //Create the edge
             t_linked_rt_edge* linked_rt_edge = alloc_linked_rt_edge();
@@ -428,7 +428,7 @@ void load_new_subtree_R_upstream(t_rt_node* rt_node) {
     auto& device_ctx = g_vpr_ctx.device();
 
     t_rt_node* parent_rt_node = rt_node->parent_node;
-    int inode = rt_node->inode;
+    RRNodeId inode = rt_node->inode;
 
     //Calculate upstream resistance
     float R_upstream = 0.;
@@ -441,7 +441,7 @@ void load_new_subtree_R_upstream(t_rt_node* rt_node) {
         }
         R_upstream += device_ctx.rr_switch_inf[iswitch].R; //Parent switch R
     }
-    R_upstream += device_ctx.rr_nodes[inode].R(); //Current node R
+    R_upstream += device_ctx.rr_graph.node_R(inode); //Current node R
 
     rt_node->R_upstream = R_upstream;
 
@@ -457,7 +457,7 @@ float load_new_subtree_C_downstream(t_rt_node* rt_node) {
     if (rt_node) {
         auto& device_ctx = g_vpr_ctx.device();
 
-        C_downstream += device_ctx.rr_nodes[rt_node->inode].C();
+        C_downstream += device_ctx.rr_graph.node_C(rt_node->inode);
         for (t_linked_rt_edge* edge = rt_node->u.child_list; edge != nullptr; edge = edge->next) {
             /*Similar to net_delay.cpp, this for loop traverses a rc subtree, whose edges represent enabled switches.
              * When switches such as multiplexers and tristate buffers are enabled, their fanout
@@ -581,9 +581,9 @@ void load_route_tree_rr_route_inf(t_rt_node* root) {
     t_linked_rt_edge* edge{root->u.child_list};
 
     for (;;) {
-        int inode = root->inode;
-        route_ctx.rr_node_route_inf[inode].prev_node = NO_PREVIOUS;
-        route_ctx.rr_node_route_inf[inode].prev_edge = NO_PREVIOUS;
+        RRNodeId inode = root->inode;
+        route_ctx.rr_node_route_inf[inode].prev_node = RRNodeId::INVALID();
+        route_ctx.rr_node_route_inf[inode].prev_edge = RREdgeId::INVALID();
         // path cost should be unset
         VTR_ASSERT(std::isinf(route_ctx.rr_node_route_inf[inode].path_cost));
         VTR_ASSERT(std::isinf(route_ctx.rr_node_route_inf[inode].backward_path_cost));
@@ -606,13 +606,13 @@ void load_route_tree_rr_route_inf(t_rt_node* root) {
 }
 
 bool verify_route_tree(t_rt_node* root) {
-    std::set<int> seen_nodes;
+    std::set<RRNodeId> seen_nodes;
     return verify_route_tree_recurr(root, seen_nodes);
 }
 
-bool verify_route_tree_recurr(t_rt_node* node, std::set<int>& seen_nodes) {
+bool verify_route_tree_recurr(t_rt_node* node, std::set<RRNodeId>& seen_nodes) {
     if (seen_nodes.count(node->inode)) {
-        VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Duplicate route tree nodes found for node %d", node->inode);
+        VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Duplicate route tree nodes found for node %ld", size_t(node->inode));
     }
 
     seen_nodes.insert(node->inode);
@@ -657,7 +657,7 @@ void print_route_tree(const t_rt_node* rt_node, int depth) {
     }
 
     auto& device_ctx = g_vpr_ctx.device();
-    VTR_LOG("%srt_node: %d (%s)", indent.c_str(), rt_node->inode, device_ctx.rr_nodes[rt_node->inode].type_string());
+    VTR_LOG("%srt_node: %ld (%s)", indent.c_str(), size_t(rt_node->inode), rr_node_typename[device_ctx.rr_graph.node_type(rt_node->inode)]);
 
     if (rt_node->parent_switch != OPEN) {
         bool parent_edge_configurable = device_ctx.rr_switch_inf[rt_node->parent_switch].configurable();
@@ -668,7 +668,7 @@ void print_route_tree(const t_rt_node* rt_node, int depth) {
 
     auto& route_ctx = g_vpr_ctx.routing();
 
-    if (route_ctx.rr_node_route_inf[rt_node->inode].occ() > device_ctx.rr_nodes[rt_node->inode].capacity()) {
+    if (route_ctx.rr_node_route_inf[rt_node->inode].occ() > device_ctx.rr_graph.node_capacity(rt_node->inode)) {
         VTR_LOG(" x");
     }
 
@@ -727,7 +727,7 @@ t_rt_node* traceback_to_route_tree(t_trace* head, std::vector<int>* non_config_n
 
     VTR_ASSERT_DEBUG(validate_traceback(head));
 
-    std::map<int, t_rt_node*> rr_node_to_rt;
+    std::map<RRNodeId, t_rt_node*> rr_node_to_rt;
 
     t_trace* trace = head;
     while (trace) { //Each branch
@@ -749,14 +749,14 @@ t_rt_node* traceback_to_route_tree(t_trace* head, std::vector<int>* non_config_n
 //
 //Returns the t_trace defining the start of the next branch
 static t_trace* traceback_to_route_tree_branch(t_trace* trace,
-                                               std::map<int, t_rt_node*>& rr_node_to_rt,
+                                               std::map<RRNodeId, t_rt_node*>& rr_node_to_rt,
                                                std::vector<int>* non_config_node_set_usage) {
     t_trace* next = nullptr;
 
     if (trace) {
         t_rt_node* node = nullptr;
 
-        int inode = trace->index;
+        RRNodeId inode = trace->index;
         int iswitch = trace->iswitch;
 
         auto itr = rr_node_to_rt.find(trace->index);
@@ -773,7 +773,7 @@ static t_trace* traceback_to_route_tree_branch(t_trace* trace,
             node->Tdel = std::numeric_limits<float>::quiet_NaN();
 
             auto& device_ctx = g_vpr_ctx.device();
-            auto node_type = device_ctx.rr_nodes[inode].type();
+            auto node_type = device_ctx.rr_graph.node_type(inode);
             if (node_type == IPIN || node_type == SINK)
                 node->re_expand = false;
             else
@@ -899,7 +899,7 @@ t_trace* traceback_from_route_tree(ClusterNetId inet, const t_rt_node* root, int
 
     t_trace* head;
     t_trace* tail;
-    std::unordered_set<int> nodes;
+    std::unordered_set<RRNodeId> nodes;
 
     std::tie(head, tail) = traceback_from_route_tree_recurr(nullptr, nullptr, root);
 
@@ -912,7 +912,7 @@ t_trace* traceback_from_route_tree(ClusterNetId inet, const t_rt_node* root, int
         nodes.insert(trace->index);
 
         //Sanity check that number of sinks match expected
-        if (device_ctx.rr_nodes[trace->index].type() == SINK) {
+        if (device_ctx.rr_graph.node_type(trace->index) == SINK) {
             num_trace_sinks += 1;
         }
     }
@@ -937,7 +937,7 @@ static t_rt_node* prune_route_tree_recurr(t_rt_node* node, CBRR& connections_inf
     auto& device_ctx = g_vpr_ctx.device();
     auto& route_ctx = g_vpr_ctx.routing();
 
-    bool congested = (route_ctx.rr_node_route_inf[node->inode].occ() > device_ctx.rr_nodes[node->inode].capacity());
+    bool congested = (route_ctx.rr_node_route_inf[node->inode].occ() > device_ctx.rr_graph.node_capacity(node->inode));
     int node_set = -1;
     auto itr = device_ctx.rr_node_to_non_config_node_set.find(node->inode);
     if (itr != device_ctx.rr_node_to_non_config_node_set.end()) {
@@ -949,7 +949,7 @@ static t_rt_node* prune_route_tree_recurr(t_rt_node* node, CBRR& connections_inf
         force_prune = true;
     }
 
-    if (connections_inf.should_force_reroute_connection(node->inode)) {
+    if (connections_inf.should_force_reroute_connection(size_t(node->inode))) {
         //Forcibly re-route (e.g. to improve delay)
         force_prune = true;
     }
@@ -995,7 +995,7 @@ static t_rt_node* prune_route_tree_recurr(t_rt_node* node, CBRR& connections_inf
         }
     }
 
-    if (device_ctx.rr_nodes[node->inode].type() == SINK) {
+    if (device_ctx.rr_graph.node_type(node->inode) == SINK) {
         if (!force_prune) {
             //Valid path to sink
 
@@ -1007,7 +1007,7 @@ static t_rt_node* prune_route_tree_recurr(t_rt_node* node, CBRR& connections_inf
             VTR_ASSERT(force_prune);
 
             //Record as not reached
-            connections_inf.toreach_rr_sink(node->inode);
+            connections_inf.toreach_rr_sink(size_t(node->inode));
 
             free_rt_node(node);
             return nullptr; //Pruned
@@ -1131,9 +1131,9 @@ t_rt_node* prune_route_tree(t_rt_node* rt_root, CBRR& connections_inf, std::vect
     auto& device_ctx = g_vpr_ctx.device();
     auto& route_ctx = g_vpr_ctx.routing();
 
-    VTR_ASSERT_MSG(device_ctx.rr_nodes[rt_root->inode].type() == SOURCE, "Root of route tree must be SOURCE");
+    VTR_ASSERT_MSG(device_ctx.rr_graph.node_type(rt_root->inode) == SOURCE, "Root of route tree must be SOURCE");
 
-    VTR_ASSERT_MSG(route_ctx.rr_node_route_inf[rt_root->inode].occ() <= device_ctx.rr_nodes[rt_root->inode].capacity(),
+    VTR_ASSERT_MSG(route_ctx.rr_node_route_inf[rt_root->inode].occ() <= device_ctx.rr_graph.node_capacity(rt_root->inode),
                    "Route tree root/SOURCE should never be congested");
 
     return prune_route_tree_recurr(rt_root, connections_inf, false, non_config_node_set_usage);
@@ -1206,7 +1206,7 @@ void print_edge(const t_linked_rt_edge* edge) {
         return;
     }
     while (edge) {
-        VTR_LOG("%d(%d) ", edge->child->inode, edge->iswitch);
+        VTR_LOG("%ld(%d) ", size_t(edge->child->inode), edge->iswitch);
         edge = edge->next;
     }
     VTR_LOG("\n");
@@ -1215,31 +1215,30 @@ void print_edge(const t_linked_rt_edge* edge) {
 static void print_node(const t_rt_node* rt_node) {
     auto& device_ctx = g_vpr_ctx.device();
 
-    int inode = rt_node->inode;
-    t_rr_type node_type = device_ctx.rr_nodes[inode].type();
+    RRNodeId inode = rt_node->inode;
+    t_rr_type node_type = device_ctx.rr_graph.node_type(inode);
     VTR_LOG("%5.1e %5.1e %2d%6s|%-6d-> ", rt_node->C_downstream, rt_node->R_upstream,
-            rt_node->re_expand, rr_node_typename[node_type], inode);
+            rt_node->re_expand, rr_node_typename[node_type], size_t(inode));
 }
 
 static void print_node_inf(const t_rt_node* rt_node) {
     auto& route_ctx = g_vpr_ctx.routing();
 
-    int inode = rt_node->inode;
+    RRNodeId inode = rt_node->inode;
     const auto& node_inf = route_ctx.rr_node_route_inf[inode];
     VTR_LOG("%5.1e %5.1e%6d%3d|%-6d-> ", node_inf.path_cost, node_inf.backward_path_cost,
-            node_inf.prev_node, node_inf.prev_edge, inode);
+            node_inf.prev_node, node_inf.prev_edge, size_t(inode));
 }
 
 static void print_node_congestion(const t_rt_node* rt_node) {
     auto& device_ctx = g_vpr_ctx.device();
     auto& route_ctx = g_vpr_ctx.routing();
 
-    int inode = rt_node->inode;
+    RRNodeId inode = rt_node->inode;
     const auto& node_inf = route_ctx.rr_node_route_inf[inode];
-    const auto& node = device_ctx.rr_nodes[inode];
     const auto& node_state = route_ctx.rr_node_route_inf[inode];
     VTR_LOG("%2d %2d|%-6d-> ", node_inf.pres_cost, rt_node->Tdel,
-            node_state.occ(), node.capacity(), inode);
+            node_state.occ(), device_ctx.rr_graph.node_capacity(inode), size_t(inode));
 }
 
 void print_route_tree_inf(const t_rt_node* rt_root) {
@@ -1263,8 +1262,8 @@ bool is_equivalent_route_tree(const t_rt_node* root, const t_rt_node* root_clone
     if (!root && !root_clone) return true;
     if (!root || !root_clone) return false; // one of them is null
     if ((root->inode != root_clone->inode) || (!equal_approx(root->R_upstream, root_clone->R_upstream)) || (!equal_approx(root->C_downstream, root_clone->C_downstream)) || (!equal_approx(root->Tdel, root_clone->Tdel))) {
-        VTR_LOG("mismatch i %d|%d R %e|%e C %e|%e T %e %e\n",
-                root->inode, root_clone->inode,
+        VTR_LOG("mismatch i %ld|%ld R %e|%e C %e|%e T %e %e\n",
+                size_t(root->inode), size_t(root_clone->inode),
                 root->R_upstream, root_clone->R_upstream,
                 root->C_downstream, root_clone->C_downstream,
                 root->Tdel, root_clone->Tdel);
@@ -1274,8 +1273,8 @@ bool is_equivalent_route_tree(const t_rt_node* root, const t_rt_node* root_clone
     t_linked_rt_edge* clone_edge{root_clone->u.child_list};
     while (orig_edge && clone_edge) {
         if (orig_edge->iswitch != clone_edge->iswitch)
-            VTR_LOG("mismatch i %d|%d edge switch %d|%d\n",
-                    root->inode, root_clone->inode,
+            VTR_LOG("mismatch i %ld|%ld edge switch %d|%d\n",
+                    size_t(root->inode), size_t(root_clone->inode),
                     orig_edge->iswitch, clone_edge->iswitch);
         if (!is_equivalent_route_tree(orig_edge->child, clone_edge->child)) return false; // child trees not equivalent
         orig_edge = orig_edge->next;
@@ -1290,23 +1289,23 @@ bool is_equivalent_route_tree(const t_rt_node* root, const t_rt_node* root_clone
 
 // check only the connections are correct, ignore R and C
 bool is_valid_skeleton_tree(const t_rt_node* root) {
-    int inode = root->inode;
+    RRNodeId inode = root->inode;
     t_linked_rt_edge* edge = root->u.child_list;
     while (edge) {
         if (edge->child->parent_node != root) {
-            VTR_LOG("parent-child relationship not mutually acknowledged by parent %d->%d child %d<-%d\n",
-                    inode, edge->child->inode,
-                    edge->child->inode, edge->child->parent_node->inode);
+            VTR_LOG("parent-child relationship not mutually acknowledged by parent %ld->%ld child %ld<-%ld\n",
+                    size_t(inode), size_t(edge->child->inode),
+                    size_t(edge->child->inode), size_t(edge->child->parent_node->inode));
             return false;
         }
         if (edge->iswitch != edge->child->parent_switch) {
-            VTR_LOG("parent(%d)-child(%d) connected switch not equivalent parent %d child %d\n",
-                    inode, edge->child->inode, edge->iswitch, edge->child->parent_switch);
+            VTR_LOG("parent(%ld)-child(%ld) connected switch not equivalent parent %d child %d\n",
+                    size_t(inode), size_t(edge->child->inode), edge->iswitch, edge->child->parent_switch);
             return false;
         }
 
         if (!is_valid_skeleton_tree(edge->child)) {
-            VTR_LOG("subtree %d invalid, propagating up\n", edge->child->inode);
+            VTR_LOG("subtree %ld invalid, propagating up\n", size_t(edge->child->inode));
             return false;
         }
         edge = edge->next;
@@ -1324,24 +1323,24 @@ bool is_valid_route_tree(const t_rt_node* root) {
     constexpr float RES_REL_TOL = 1e-6;
     constexpr float RES_ABS_TOL = vtr::DEFAULT_ABS_TOL;
 
-    int inode = root->inode;
+    RRNodeId inode = root->inode;
     short iswitch = root->parent_switch;
     if (root->parent_node) {
         if (device_ctx.rr_switch_inf[iswitch].buffered()) {
-            float R_upstream_check = device_ctx.rr_nodes[inode].R() + device_ctx.rr_switch_inf[iswitch].R;
+            float R_upstream_check = device_ctx.rr_graph.node_R(inode) + device_ctx.rr_switch_inf[iswitch].R;
             if (!vtr::isclose(root->R_upstream, R_upstream_check, RES_REL_TOL, RES_ABS_TOL)) {
-                VTR_LOG("%d mismatch R upstream %e supposed %e\n", inode, root->R_upstream, R_upstream_check);
+                VTR_LOG("%ld mismatch R upstream %e supposed %e\n", size_t(inode), root->R_upstream, R_upstream_check);
                 return false;
             }
         } else {
-            float R_upstream_check = device_ctx.rr_nodes[inode].R() + root->parent_node->R_upstream + device_ctx.rr_switch_inf[iswitch].R;
+            float R_upstream_check = device_ctx.rr_graph.node_R(inode) + root->parent_node->R_upstream + device_ctx.rr_switch_inf[iswitch].R;
             if (!vtr::isclose(root->R_upstream, R_upstream_check, RES_REL_TOL, RES_ABS_TOL)) {
-                VTR_LOG("%d mismatch R upstream %e supposed %e\n", inode, root->R_upstream, R_upstream_check);
+                VTR_LOG("%ld mismatch R upstream %e supposed %e\n", size_t(inode), root->R_upstream, R_upstream_check);
                 return false;
             }
         }
-    } else if (root->R_upstream != device_ctx.rr_nodes[inode].R()) {
-        VTR_LOG("%d mismatch R upstream %e supposed %e\n", inode, root->R_upstream, device_ctx.rr_nodes[inode].R());
+    } else if (root->R_upstream != device_ctx.rr_graph.node_R(inode)) {
+        VTR_LOG("%ld mismatch R upstream %e supposed %e\n", size_t(inode), root->R_upstream, device_ctx.rr_graph.node_R(inode));
         return false;
     }
 
@@ -1351,22 +1350,22 @@ bool is_valid_route_tree(const t_rt_node* root) {
     // sink, must not be congested
     if (!edge) {
         int occ = route_ctx.rr_node_route_inf[inode].occ();
-        int capacity = device_ctx.rr_nodes[inode].capacity();
+        int capacity = device_ctx.rr_graph.node_capacity(inode);
         if (occ > capacity) {
-            VTR_LOG("SINK %d occ %d > cap %d\n", inode, occ, capacity);
+            VTR_LOG("SINK %ld occ %d > cap %d\n", size_t(inode), occ, capacity);
             return false;
         }
     }
     while (edge) {
         if (edge->child->parent_node != root) {
-            VTR_LOG("parent-child relationship not mutually acknowledged by parent %d->%d child %d<-%d\n",
-                    inode, edge->child->inode,
-                    edge->child->inode, edge->child->parent_node->inode);
+            VTR_LOG("parent-child relationship not mutually acknowledged by parent %ld->%ld child %ld<-%ld\n",
+                    size_t(inode), size_t(edge->child->inode),
+                    size_t(edge->child->inode), size_t(edge->child->parent_node->inode));
             return false;
         }
         if (edge->iswitch != edge->child->parent_switch) {
-            VTR_LOG("parent(%d)-child(%d) connected switch not equivalent parent %d child %d\n",
-                    inode, edge->child->inode, edge->iswitch, edge->child->parent_switch);
+            VTR_LOG("parent(%ld)-child(%ld) connected switch not equivalent parent %d child %d\n",
+                    size_t(inode), size_t(edge->child->inode), edge->iswitch, edge->child->parent_switch);
             return false;
         }
 
@@ -1383,9 +1382,9 @@ bool is_valid_route_tree(const t_rt_node* root) {
         edge = edge->next;
     }
 
-    float C_downstream_check = C_downstream_children + device_ctx.rr_nodes[inode].C();
+    float C_downstream_check = C_downstream_children + device_ctx.rr_graph.node_C(inode);
     if (!vtr::isclose(root->C_downstream, C_downstream_check, CAP_REL_TOL, CAP_ABS_TOL)) {
-        VTR_LOG("%d mismatch C downstream %e supposed %e\n", inode, root->C_downstream, C_downstream_check);
+        VTR_LOG("%ld mismatch C downstream %e supposed %e\n", size_t(inode), root->C_downstream, C_downstream_check);
         return false;
     }
 
@@ -1397,8 +1396,8 @@ bool is_uncongested_route_tree(const t_rt_node* root) {
     auto& route_ctx = g_vpr_ctx.routing();
     auto& device_ctx = g_vpr_ctx.device();
 
-    int inode = root->inode;
-    if (route_ctx.rr_node_route_inf[inode].occ() > device_ctx.rr_nodes[inode].capacity()) {
+    RRNodeId inode = root->inode;
+    if (route_ctx.rr_node_route_inf[inode].occ() > device_ctx.rr_graph.node_capacity(inode)) {
         //This node is congested
         return false;
     }
@@ -1428,30 +1427,28 @@ init_route_tree_to_source_no_net(const RRNodeId& inode) {
     rt_root->parent_node = nullptr;
     rt_root->parent_switch = OPEN;
     rt_root->re_expand = true;
-    rt_root->inode = size_t(inode);
-
-    rt_root->inode_id = inode;
+    rt_root->inode = inode;
 
     rt_root->C_downstream = device_ctx.rr_graph.node_C(inode);
     rt_root->R_upstream = device_ctx.rr_graph.node_R(inode);
     rt_root->Tdel = 0.5 * device_ctx.rr_graph.node_R(inode) * device_ctx.rr_graph.node_C(inode);
-    rr_node_to_rt_node[size_t(inode)] = rt_root;
+    rr_node_to_rt_node[inode] = rt_root;
 
     return (rt_root);
 }
 
 bool verify_traceback_route_tree_equivalent(const t_trace* head, const t_rt_node* rt_root) {
     //Walk the route tree saving all the used connections
-    std::set<std::tuple<int, int, int>> route_tree_connections;
+    std::set<std::tuple<RRNodeId, int, RRNodeId>> route_tree_connections;
     collect_route_tree_connections(rt_root, route_tree_connections);
 
     //Remove the extra parent connection to root (not included in traceback)
-    route_tree_connections.erase(std::make_tuple(OPEN, OPEN, rt_root->inode));
+    route_tree_connections.erase(std::make_tuple(RRNodeId::INVALID(), OPEN, rt_root->inode));
 
     //Walk the traceback and verify that every connection exists in the route tree set
-    int prev_node = OPEN;
+    RRNodeId prev_node = RRNodeId::INVALID();
     int prev_switch = OPEN;
-    int to_node = OPEN;
+    RRNodeId to_node = RRNodeId::INVALID();
     for (const t_trace* trace = head; trace != nullptr; trace = trace->next) {
         to_node = trace->index;
 
@@ -1474,7 +1471,7 @@ bool verify_traceback_route_tree_equivalent(const t_trace* head, const t_rt_node
         std::string msg = "Found route tree connection(s) not in traceback:\n";
         for (auto conn : route_tree_connections) {
             std::tie(prev_node, prev_switch, to_node) = conn;
-            msg += vtr::string_fmt("\tnode %d -> %d (switch %d)\n", prev_node, to_node, prev_switch);
+            msg += vtr::string_fmt("\tnode %ld -> %ld (switch %d)\n", size_t(prev_node), size_t(to_node), prev_switch);
         }
 
         VPR_FATAL_ERROR(VPR_ERROR_ROUTE, msg.c_str());
@@ -1483,12 +1480,12 @@ bool verify_traceback_route_tree_equivalent(const t_trace* head, const t_rt_node
     return true;
 }
 
-void collect_route_tree_connections(const t_rt_node* node, std::set<std::tuple<int, int, int>>& connections) {
+void collect_route_tree_connections(const t_rt_node* node, std::set<std::tuple<RRNodeId, int, RRNodeId>>& connections) {
     if (node) {
         //Record reaching connection
-        int prev_node = OPEN;
+        RRNodeId prev_node = RRNodeId::INVALID();
         int prev_switch = OPEN;
-        int to_node = node->inode;
+        RRNodeId to_node = node->inode;
         if (node->parent_node) {
             prev_node = node->parent_node->inode;
             prev_switch = node->parent_switch;
@@ -1517,13 +1514,13 @@ t_rt_node* find_sink_rt_node(t_rt_node* rt_root, ClusterNetId net_id, ClusterPin
     auto& route_ctx = g_vpr_ctx.routing();
 
     int ipin = cluster_ctx.clb_nlist.pin_net_index(sink_pin);
-    int sink_rr_inode = route_ctx.net_rr_terminals[net_id][ipin]; //obtain the value of the routing resource sink
+    RRNodeId sink_rr_inode = route_ctx.net_rr_terminals[net_id][ipin]; //obtain the value of the routing resource sink
 
     t_rt_node* sink_rt_node = find_sink_rt_node_recurr(rt_root, sink_rr_inode); //find pointer to route tree node corresponding to sink_rr_inode
     VTR_ASSERT(sink_rt_node);
     return sink_rt_node;
 }
-t_rt_node* find_sink_rt_node_recurr(t_rt_node* node, int sink_rr_inode) {
+t_rt_node* find_sink_rt_node_recurr(t_rt_node* node, const RRNodeId& sink_rr_inode) {
     if (node->inode == sink_rr_inode) { //check if current node matches sink_rr_inode
         return node;
     }
diff --git a/vpr/src/route/route_tree_timing.h b/vpr/src/route/route_tree_timing.h
index 781b11e5d..6a3f36c84 100644
--- a/vpr/src/route/route_tree_timing.h
+++ b/vpr/src/route/route_tree_timing.h
@@ -39,7 +39,7 @@ bool verify_route_tree(t_rt_node* root);
 bool verify_traceback_route_tree_equivalent(const t_trace* trace_head, const t_rt_node* rt_root);
 
 t_rt_node* find_sink_rt_node(t_rt_node* rt_root, ClusterNetId net_id, ClusterPinId sink_pin);
-t_rt_node* find_sink_rt_node_recurr(t_rt_node* node, int sink_inode);
+t_rt_node* find_sink_rt_node_recurr(t_rt_node* node, const RRNodeId& sink_inode);
 
 /********** Incremental reroute ***********/
 // instead of ripping up a net that has some congestion, cut the branches

From f139a844ca67f3afff9dcff6ef31abf71c276618 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 1 Feb 2020 18:01:05 -0700
Subject: [PATCH 076/645] route util adopt RRGraph object

---
 vpr/src/route/route_util.cpp | 26 ++++++++++++--------------
 1 file changed, 12 insertions(+), 14 deletions(-)

diff --git a/vpr/src/route/route_util.cpp b/vpr/src/route/route_util.cpp
index b04f0cf12..6d8417963 100644
--- a/vpr/src/route/route_util.cpp
+++ b/vpr/src/route/route_util.cpp
@@ -11,13 +11,13 @@ vtr::Matrix<float> calculate_routing_usage(t_rr_type rr_type) {
     vtr::Matrix<float> usage({{device_ctx.grid.width(), device_ctx.grid.height()}}, 0.);
 
     //Collect all the in-use RR nodes
-    std::set<int> rr_nodes;
+    std::set<RRNodeId> rr_nodes;
     for (auto net : cluster_ctx.clb_nlist.nets()) {
         t_trace* tptr = route_ctx.trace[net].head;
         while (tptr != nullptr) {
-            int inode = tptr->index;
+            RRNodeId inode = tptr->index;
 
-            if (device_ctx.rr_nodes[inode].type() == rr_type) {
+            if (device_ctx.rr_graph.node_type(inode) == rr_type) {
                 rr_nodes.insert(inode);
             }
             tptr = tptr->next;
@@ -25,24 +25,22 @@ vtr::Matrix<float> calculate_routing_usage(t_rr_type rr_type) {
     }
 
     //Record number of used resources in each x/y channel
-    for (int inode : rr_nodes) {
-        auto& rr_node = device_ctx.rr_nodes[inode];
-
+    for (const RRNodeId& inode : rr_nodes) {
         if (rr_type == CHANX) {
-            VTR_ASSERT(rr_node.type() == CHANX);
-            VTR_ASSERT(rr_node.ylow() == rr_node.yhigh());
+            VTR_ASSERT(device_ctx.rr_graph.node_type(inode) == CHANX);
+            VTR_ASSERT(device_ctx.rr_graph.node_ylow(inode) == device_ctx.rr_graph.node_yhigh(inode));
 
-            int y = rr_node.ylow();
-            for (int x = rr_node.xlow(); x <= rr_node.xhigh(); ++x) {
+            int y = device_ctx.rr_graph.node_ylow(inode);
+            for (int x = device_ctx.rr_graph.node_xlow(inode); x <= device_ctx.rr_graph.node_xhigh(inode); ++x) {
                 usage[x][y] += route_ctx.rr_node_route_inf[inode].occ();
             }
         } else {
             VTR_ASSERT(rr_type == CHANY);
-            VTR_ASSERT(rr_node.type() == CHANY);
-            VTR_ASSERT(rr_node.xlow() == rr_node.xhigh());
+            VTR_ASSERT(device_ctx.rr_graph.node_type(inode) == CHANY);
+            VTR_ASSERT(device_ctx.rr_graph.node_xlow(inode) == device_ctx.rr_graph.node_xhigh(inode));
 
-            int x = rr_node.xlow();
-            for (int y = rr_node.ylow(); y <= rr_node.yhigh(); ++y) {
+            int x = device_ctx.rr_graph.node_xlow(inode);
+            for (int y = device_ctx.rr_graph.node_ylow(inode); y <= device_ctx.rr_graph.node_yhigh(inode); ++y) {
                 usage[x][y] += route_ctx.rr_node_route_inf[inode].occ();
             }
         }

From 01a2ba78d4efbbe6b78b8fb1bcd293d1f4646f93 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 1 Feb 2020 20:44:55 -0700
Subject: [PATCH 077/645] router lookahead and delay profiling adopt RRGraph
 object

---
 vpr/src/route/router_delay_profiling.cpp |  24 +++---
 vpr/src/route/router_delay_profiling.h   |   2 +-
 vpr/src/route/router_lookahead_map.cpp   | 103 ++++++++++++-----------
 vpr/src/route/router_lookahead_map.h     |   2 +-
 vpr/src/route/rr_graph.cpp               |   4 +-
 5 files changed, 68 insertions(+), 67 deletions(-)

diff --git a/vpr/src/route/router_delay_profiling.cpp b/vpr/src/route/router_delay_profiling.cpp
index 39dbce7fa..60ef4267f 100644
--- a/vpr/src/route/router_delay_profiling.cpp
+++ b/vpr/src/route/router_delay_profiling.cpp
@@ -7,7 +7,7 @@
 #include "route_export.h"
 #include "rr_graph.h"
 
-static t_rt_node* setup_routing_resources_no_net(int source_node);
+static t_rt_node* setup_routing_resources_no_net(const RRNodeId& source_node);
 
 RouterDelayProfiler::RouterDelayProfiler(
     const RouterLookahead* lookahead)
@@ -23,7 +23,7 @@ bool RouterDelayProfiler::calculate_delay(const RRNodeId& source_node, const RRN
 
     t_rt_node* rt_root = setup_routing_resources_no_net(source_node);
     /* TODO: This should be changed to RRNodeId */
-    enable_router_debug(router_opts, ClusterNetId(), size_t(sink_node));
+    enable_router_debug(router_opts, ClusterNetId(), sink_node);
 
     /* Update base costs according to fanout and criticality rules */
     update_rr_base_costs(1);
@@ -44,7 +44,7 @@ bool RouterDelayProfiler::calculate_delay(const RRNodeId& source_node, const RRN
 
     init_heap(device_ctx.grid);
 
-    std::vector<int> modified_rr_node_inf;
+    std::vector<RRNodeId> modified_rr_node_inf;
     RouterStats router_stats;
     t_heap* cheapest = timing_driven_route_connection_from_route_tree(rt_root,
                                                                       sink_node, cost_params, bounding_box, *router_lookahead_,
@@ -60,7 +60,7 @@ bool RouterDelayProfiler::calculate_delay(const RRNodeId& source_node, const RRN
         //find delay
         *net_delay = rt_node_of_sink->Tdel;
 
-        VTR_ASSERT_MSG(route_ctx.rr_node_route_inf[rt_root->inode].occ() <= device_ctx.rr_graph.node_capacity(rt_root->inode_id), "SOURCE should never be congested");
+        VTR_ASSERT_MSG(route_ctx.rr_node_route_inf[rt_root->inode].occ() <= device_ctx.rr_graph.node_capacity(rt_root->inode), "SOURCE should never be congested");
         free_route_tree(rt_root);
     }
 
@@ -72,10 +72,10 @@ bool RouterDelayProfiler::calculate_delay(const RRNodeId& source_node, const RRN
 }
 
 //Returns the shortest path delay from src_node to all RR nodes in the RR graph, or NaN if no path exists
-std::vector<float> calculate_all_path_delays_from_rr_node(int src_rr_node, const t_router_opts& router_opts) {
+vtr::vector<RRNodeId, float> calculate_all_path_delays_from_rr_node(const RRNodeId& src_rr_node, const t_router_opts& router_opts) {
     auto& device_ctx = g_vpr_ctx.device();
 
-    std::vector<float> path_delays_to(device_ctx.rr_nodes.size(), std::numeric_limits<float>::quiet_NaN());
+    vtr::vector<RRNodeId, float> path_delays_to(device_ctx.rr_graph.nodes().size(), std::numeric_limits<float>::quiet_NaN());
 
     t_rt_node* rt_root = setup_routing_resources_no_net(src_rr_node);
 
@@ -90,12 +90,12 @@ std::vector<float> calculate_all_path_delays_from_rr_node(int src_rr_node, const
     cost_params.astar_fac = router_opts.astar_fac;
     cost_params.bend_cost = router_opts.bend_cost;
 
-    std::vector<int> modified_rr_node_inf;
+    std::vector<RRNodeId> modified_rr_node_inf;
     RouterStats router_stats;
 
     init_heap(device_ctx.grid);
 
-    std::vector<t_heap> shortest_paths = timing_driven_find_all_shortest_paths_from_route_tree(rt_root,
+    vtr::vector<RRNodeId, t_heap> shortest_paths = timing_driven_find_all_shortest_paths_from_route_tree(rt_root,
                                                                                                cost_params,
                                                                                                bounding_box,
                                                                                                modified_rr_node_inf,
@@ -103,12 +103,12 @@ std::vector<float> calculate_all_path_delays_from_rr_node(int src_rr_node, const
 
     free_route_tree(rt_root);
 
-    VTR_ASSERT(shortest_paths.size() == device_ctx.rr_nodes.size());
-    for (int sink_rr_node = 0; sink_rr_node < (int)device_ctx.rr_nodes.size(); ++sink_rr_node) {
+    VTR_ASSERT(shortest_paths.size() == device_ctx.rr_graph.nodes().size());
+    for (const RRNodeId& sink_rr_node : device_ctx.rr_graph.nodes()) {
         if (sink_rr_node == src_rr_node) {
             path_delays_to[sink_rr_node] = 0.;
         } else {
-            if (shortest_paths[sink_rr_node].index == OPEN) continue;
+            if (shortest_paths[sink_rr_node].index == RRNodeId::INVALID()) continue;
 
             VTR_ASSERT(shortest_paths[sink_rr_node].index == sink_rr_node);
 
@@ -155,7 +155,7 @@ std::vector<float> calculate_all_path_delays_from_rr_node(int src_rr_node, const
     return path_delays_to;
 }
 
-static t_rt_node* setup_routing_resources_no_net(int source_node) {
+static t_rt_node* setup_routing_resources_no_net(const RRNodeId& source_node) {
     /* Build and return a partial route tree from the legal connections from last iteration.
      * along the way do:
      * 	update pathfinder costs to be accurate to the partial route tree
diff --git a/vpr/src/route/router_delay_profiling.h b/vpr/src/route/router_delay_profiling.h
index 7f3918685..63b8bed65 100644
--- a/vpr/src/route/router_delay_profiling.h
+++ b/vpr/src/route/router_delay_profiling.h
@@ -15,7 +15,7 @@ class RouterDelayProfiler {
     const RouterLookahead* router_lookahead_;
 };
 
-std::vector<float> calculate_all_path_delays_from_rr_node(int src_rr_node, const t_router_opts& router_opts);
+vtr::vector<RRNodeId, float> calculate_all_path_delays_from_rr_node(int src_rr_node, const t_router_opts& router_opts);
 
 void alloc_routing_structs(t_chan_width chan_width,
                            const t_router_opts& router_opts,
diff --git a/vpr/src/route/router_lookahead_map.cpp b/vpr/src/route/router_lookahead_map.cpp
index c2ad6aad7..42de703b5 100644
--- a/vpr/src/route/router_lookahead_map.cpp
+++ b/vpr/src/route/router_lookahead_map.cpp
@@ -131,7 +131,7 @@ class Expansion_Cost_Entry {
 /* a class that represents an entry in the Dijkstra expansion priority queue */
 class PQ_Entry {
   public:
-    int rr_node_ind; //index in device_ctx.rr_nodes that this entry represents
+    RRNodeId rr_node_ind; //index in device_ctx.rr_nodes that this entry represents
     float cost;      //the cost of the path to get to this node
 
     /* store backward delay, R and congestion info */
@@ -139,7 +139,7 @@ class PQ_Entry {
     float R_upstream;
     float congestion_upstream;
 
-    PQ_Entry(int set_rr_node_ind, int /*switch_ind*/, float parent_delay, float parent_R_upstream, float parent_congestion_upstream, bool starting_node) {
+    PQ_Entry(const RRNodeId& set_rr_node_ind, int /*switch_ind*/, float parent_delay, float parent_R_upstream, float parent_congestion_upstream, bool starting_node) {
         this->rr_node_ind = set_rr_node_ind;
 
         auto& device_ctx = g_vpr_ctx.device();
@@ -147,7 +147,7 @@ class PQ_Entry {
         this->congestion_upstream = parent_congestion_upstream;
         this->R_upstream = parent_R_upstream;
         if (!starting_node) {
-            int cost_index = device_ctx.rr_nodes[set_rr_node_ind].cost_index();
+            int cost_index = device_ctx.rr_graph.node_cost_index(set_rr_node_ind);
             //this->delay += g_rr_nodes[set_rr_node_ind].C() * (g_rr_switch_inf[switch_ind].R + 0.5*g_rr_nodes[set_rr_node_ind].R()) +
             //              g_rr_switch_inf[switch_ind].Tdel;
 
@@ -191,12 +191,12 @@ t_cost_map f_cost_map;
 static void alloc_cost_map(int num_segments);
 static void free_cost_map();
 /* returns index of a node from which to start routing */
-static int get_start_node_ind(int start_x, int start_y, int target_x, int target_y, t_rr_type rr_type, int seg_index, int track_offset);
+static RRNodeId get_start_node_ind(int start_x, int start_y, int target_x, int target_y, t_rr_type rr_type, int seg_index, int track_offset);
 /* runs Dijkstra's algorithm from specified node until all nodes have been visited. Each time a pin is visited, the delay/congestion information
  * to that pin is stored is added to an entry in the routing_cost_map */
-static void run_dijkstra(int start_node_ind, int start_x, int start_y, t_routing_cost_map& routing_cost_map);
+static void run_dijkstra(const RRNodeId& start_node_ind, int start_x, int start_y, t_routing_cost_map& routing_cost_map);
 /* iterates over the children of the specified node and selectively pushes them onto the priority queue */
-static void expand_dijkstra_neighbours(PQ_Entry parent_entry, std::vector<float>& node_visited_costs, std::vector<bool>& node_expanded, std::priority_queue<PQ_Entry>& pq);
+static void expand_dijkstra_neighbours(PQ_Entry parent_entry, vtr::vector<RRNodeId, float>& node_visited_costs, vtr::vector<RRNodeId, bool>& node_expanded, std::priority_queue<PQ_Entry>& pq);
 /* sets the lookahead cost map entries based on representative cost entries from routing_cost_map */
 static void set_lookahead_map_costs(int segment_index, e_rr_type chan_type, t_routing_cost_map& routing_cost_map);
 /* fills in missing lookahead map entries by copying the cost of the closest valid entry */
@@ -204,19 +204,18 @@ static void fill_in_missing_lookahead_entries(int segment_index, e_rr_type chan_
 /* returns a cost entry in the f_cost_map that is near the specified coordinates (and preferably towards (0,0)) */
 static Cost_Entry get_nearby_cost_entry(int x, int y, int segment_index, int chan_index);
 /* returns the absolute delta_x and delta_y offset required to reach to_node from from_node */
-static void get_xy_deltas(int from_node_ind, int to_node_ind, int* delta_x, int* delta_y);
+static void get_xy_deltas(const RRNodeId& from_node_ind, const RRNodeId& to_node_ind, int* delta_x, int* delta_y);
 
 static void print_cost_map();
 
 /******** Function Definitions ********/
 /* queries the lookahead_map (should have been computed prior to routing) to get the expected cost
  * from the specified source to the specified target */
-float get_lookahead_map_cost(int from_node_ind, int to_node_ind, float criticality_fac) {
+float get_lookahead_map_cost(const RRNodeId& from_node_ind, const RRNodeId& to_node_ind, float criticality_fac) {
     auto& device_ctx = g_vpr_ctx.device();
-    auto& from_node = device_ctx.rr_nodes[from_node_ind];
 
-    e_rr_type from_type = from_node.type();
-    int from_cost_index = from_node.cost_index();
+    e_rr_type from_type = device_ctx.rr_graph.node_type(from_node_ind);
+    int from_cost_index = device_ctx.rr_graph.node_cost_index(from_node_ind);
     int from_seg_index = device_ctx.rr_indexed_data[from_cost_index].seg_index;
 
     VTR_ASSERT(from_seg_index >= 0);
@@ -262,11 +261,11 @@ void compute_router_lookahead(int num_segments) {
             for (int ref_inc = 0; ref_inc < 3; ref_inc++) {
                 for (int track_offset = 0; track_offset < MAX_TRACK_OFFSET; track_offset += 2) {
                     /* get the rr node index from which to start routing */
-                    int start_node_ind = get_start_node_ind(REF_X + ref_inc, REF_Y + ref_inc,
+                    RRNodeId start_node_ind = get_start_node_ind(REF_X + ref_inc, REF_Y + ref_inc,
                                                             device_ctx.grid.width() - 2, device_ctx.grid.height() - 2, //non-corner upper right
                                                             chan_type, iseg, track_offset);
 
-                    if (start_node_ind == UNDEFINED) {
+                    if (start_node_ind == RRNodeId::INVALID()) {
                         continue;
                     }
 
@@ -289,8 +288,8 @@ void compute_router_lookahead(int num_segments) {
 }
 
 /* returns index of a node from which to start routing */
-static int get_start_node_ind(int start_x, int start_y, int target_x, int target_y, t_rr_type rr_type, int seg_index, int track_offset) {
-    int result = UNDEFINED;
+static RRNodeId get_start_node_ind(int start_x, int start_y, int target_x, int target_y, t_rr_type rr_type, int seg_index, int track_offset) {
+    RRNodeId result = RRNodeId::INVALID();
 
     if (rr_type != CHANX && rr_type != CHANY) {
         VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Must start lookahead routing from CHANX or CHANY node\n");
@@ -306,14 +305,21 @@ static int get_start_node_ind(int start_x, int start_y, int target_x, int target
 
     VTR_ASSERT(rr_type == CHANX || rr_type == CHANY);
 
-    const std::vector<int>& channel_node_list = device_ctx.rr_node_indices[rr_type][start_x][start_y][0];
+    std::vector<RRNodeId> channel_node_list;
+    /* As rr_node_indices is now an internal data of RRGraph object, 
+     * we can get the number of tracks for a 
+     * routing channel and then get the node one by one 
+     */
+    short num_tracks = device_ctx.rr_graph.chan_num_tracks(start_x, start_y, rr_type); 
+    for (short i = 0; i < num_tracks; ++i) {
+      channel_node_list.push_back(device_ctx.rr_graph.find_node(start_x, start_y, rr_type, i));
+    }
 
     /* find first node in channel that has specified segment index and goes in the desired direction */
-    for (unsigned itrack = 0; itrack < channel_node_list.size(); itrack++) {
-        int node_ind = channel_node_list[itrack];
+    for (const RRNodeId& node_ind : channel_node_list) {
 
-        e_direction node_direction = device_ctx.rr_nodes[node_ind].direction();
-        int node_cost_ind = device_ctx.rr_nodes[node_ind].cost_index();
+        e_direction node_direction = device_ctx.rr_graph.node_direction(node_ind);
+        int node_cost_ind = device_ctx.rr_graph.node_cost_index(node_ind);
         int node_seg_ind = device_ctx.rr_indexed_data[node_cost_ind].seg_index;
 
         if ((node_direction == direction || node_direction == BI_DIRECTION) && node_seg_ind == seg_index) {
@@ -343,14 +349,14 @@ static void free_cost_map() {
 
 /* runs Dijkstra's algorithm from specified node until all nodes have been visited. Each time a pin is visited, the delay/congestion information
  * to that pin is stored is added to an entry in the routing_cost_map */
-static void run_dijkstra(int start_node_ind, int start_x, int start_y, t_routing_cost_map& routing_cost_map) {
+static void run_dijkstra(const RRNodeId& start_node_ind, int start_x, int start_y, t_routing_cost_map& routing_cost_map) {
     auto& device_ctx = g_vpr_ctx.device();
 
     /* a list of boolean flags (one for each rr node) to figure out if a certain node has already been expanded */
-    std::vector<bool> node_expanded(device_ctx.rr_nodes.size(), false);
+    vtr::vector<RRNodeId, bool> node_expanded(device_ctx.rr_graph.nodes().size(), false);
     /* for each node keep a list of the cost with which that node has been visited (used to determine whether to push
      * a candidate node onto the expansion queue */
-    std::vector<float> node_visited_costs(device_ctx.rr_nodes.size(), -1.0);
+    vtr::vector<RRNodeId, float> node_visited_costs(device_ctx.rr_graph.nodes().size(), -1.0);
     /* a priority queue for expansion */
     std::priority_queue<PQ_Entry> pq;
 
@@ -364,7 +370,7 @@ static void run_dijkstra(int start_node_ind, int start_x, int start_y, t_routing
         PQ_Entry current = pq.top();
         pq.pop();
 
-        int node_ind = current.rr_node_ind;
+        RRNodeId node_ind = current.rr_node_ind;
 
         /* check that we haven't already expanded from this node */
         if (node_expanded[node_ind]) {
@@ -372,9 +378,9 @@ static void run_dijkstra(int start_node_ind, int start_x, int start_y, t_routing
         }
 
         /* if this node is an ipin record its congestion/delay in the routing_cost_map */
-        if (device_ctx.rr_nodes[node_ind].type() == IPIN) {
-            int ipin_x = device_ctx.rr_nodes[node_ind].xlow();
-            int ipin_y = device_ctx.rr_nodes[node_ind].ylow();
+        if (device_ctx.rr_graph.node_type(node_ind) == IPIN) {
+            int ipin_x = device_ctx.rr_graph.node_xlow(node_ind);
+            int ipin_y = device_ctx.rr_graph.node_ylow(node_ind);
 
             if (ipin_x >= start_x && ipin_y >= start_y) {
                 int delta_x, delta_y;
@@ -390,16 +396,14 @@ static void run_dijkstra(int start_node_ind, int start_x, int start_y, t_routing
 }
 
 /* iterates over the children of the specified node and selectively pushes them onto the priority queue */
-static void expand_dijkstra_neighbours(PQ_Entry parent_entry, std::vector<float>& node_visited_costs, std::vector<bool>& node_expanded, std::priority_queue<PQ_Entry>& pq) {
+static void expand_dijkstra_neighbours(PQ_Entry parent_entry, vtr::vector<RRNodeId, float>& node_visited_costs, vtr::vector<RRNodeId, bool>& node_expanded, std::priority_queue<PQ_Entry>& pq) {
     auto& device_ctx = g_vpr_ctx.device();
 
-    int parent_ind = parent_entry.rr_node_ind;
+    RRNodeId parent_ind = parent_entry.rr_node_ind;
 
-    auto& parent_node = device_ctx.rr_nodes[parent_ind];
-
-    for (t_edge_size iedge = 0; iedge < parent_node.num_edges(); iedge++) {
-        int child_node_ind = parent_node.edge_sink_node(iedge);
-        int switch_ind = parent_node.edge_switch(iedge);
+    for (const RREdgeId& iedge : device_ctx.rr_graph.node_out_edges(parent_ind)) {
+        RRNodeId child_node_ind = device_ctx.rr_graph.edge_sink_node(iedge);
+        int switch_ind = (int)size_t(device_ctx.rr_graph.edge_switch(iedge));
 
         /* skip this child if it has already been expanded from */
         if (node_expanded[child_node_ind]) {
@@ -595,25 +599,22 @@ Cost_Entry Expansion_Cost_Entry::get_median_entry() {
 }
 
 /* returns the absolute delta_x and delta_y offset required to reach to_node from from_node */
-static void get_xy_deltas(int from_node_ind, int to_node_ind, int* delta_x, int* delta_y) {
+static void get_xy_deltas(const RRNodeId& from_node_ind, const RRNodeId& to_node_ind, int* delta_x, int* delta_y) {
     auto& device_ctx = g_vpr_ctx.device();
 
-    auto& from = device_ctx.rr_nodes[from_node_ind];
-    auto& to = device_ctx.rr_nodes[to_node_ind];
-
     /* get chan/seg coordinates of the from/to nodes. seg coordinate is along the wire,
      * chan coordinate is orthogonal to the wire */
-    int from_seg_low = from.xlow();
-    int from_seg_high = from.xhigh();
-    int from_chan = from.ylow();
-    int to_seg = to.xlow();
-    int to_chan = to.ylow();
-    if (from.type() == CHANY) {
-        from_seg_low = from.ylow();
-        from_seg_high = from.yhigh();
-        from_chan = from.xlow();
-        to_seg = to.ylow();
-        to_chan = to.xlow();
+    int from_seg_low = device_ctx.rr_graph.node_xlow(from_node_ind);
+    int from_seg_high = device_ctx.rr_graph.node_xhigh(from_node_ind);
+    int from_chan = device_ctx.rr_graph.node_ylow(from_node_ind);
+    int to_seg = device_ctx.rr_graph.node_xlow(to_node_ind);
+    int to_chan = device_ctx.rr_graph.node_ylow(to_node_ind);
+    if (device_ctx.rr_graph.node_type(from_node_ind) == CHANY) {
+        from_seg_low = device_ctx.rr_graph.node_ylow(from_node_ind);
+        from_seg_high = device_ctx.rr_graph.node_yhigh(from_node_ind);
+        from_chan = device_ctx.rr_graph.node_xlow(from_node_ind);
+        to_seg = device_ctx.rr_graph.node_ylow(to_node_ind);
+        to_chan = device_ctx.rr_graph.node_xlow(to_node_ind);
     }
 
     /* now we want to count the minimum number of *channel segments* between the from and to nodes */
@@ -649,13 +650,13 @@ static void get_xy_deltas(int from_node_ind, int to_node_ind, int* delta_x, int*
 
     /* account for wire direction. lookahead map was computed by looking up and to the right starting at INC wires. for targets
      * that are opposite of the wire direction, let's add 1 to delta_seg */
-    if ((to_seg < from_seg_low && from.direction() == INC_DIRECTION) || (to_seg > from_seg_high && from.direction() == DEC_DIRECTION)) {
+    if ((to_seg < from_seg_low && device_ctx.rr_graph.node_direction(from_node_ind) == INC_DIRECTION) || (to_seg > from_seg_high && device_ctx.rr_graph.node_direction(from_node_ind) == DEC_DIRECTION)) {
         delta_seg++;
     }
 
     *delta_x = delta_seg;
     *delta_y = delta_chan;
-    if (from.type() == CHANY) {
+    if (device_ctx.rr_graph.node_type(from_node_ind) == CHANY) {
         *delta_x = delta_chan;
         *delta_y = delta_seg;
     }
diff --git a/vpr/src/route/router_lookahead_map.h b/vpr/src/route/router_lookahead_map.h
index 4a31497e5..ac78b0737 100644
--- a/vpr/src/route/router_lookahead_map.h
+++ b/vpr/src/route/router_lookahead_map.h
@@ -6,4 +6,4 @@ void compute_router_lookahead(int num_segments);
 
 /* queries the lookahead_map (should have been computed prior to routing) to get the expected cost
  * from the specified source to the specified target */
-float get_lookahead_map_cost(int from_node_ind, int to_node_ind, float criticality_fac);
+float get_lookahead_map_cost(const RRNodeId& from_node_ind, const RRNodeId& to_node_ind, float criticality_fac);
diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp
index e70e70d01..85934a6d6 100644
--- a/vpr/src/route/rr_graph.cpp
+++ b/vpr/src/route/rr_graph.cpp
@@ -3185,8 +3185,8 @@ class EdgeGroups {
     t_non_configurable_rr_sets output_sets() {
         t_non_configurable_rr_sets sets;
         for (auto& item : rr_non_config_node_sets_map_) {
-            std::set<t_node_edge> edge_set;
-            std::set<int> node_set(item.second.begin(), item.second.end());
+            std::set<RREdgeId> edge_set;
+            std::set<RRNodeId> node_set(item.second.begin(), item.second.end());
 
             for (const auto& edge : node_edges_) {
                 if (node_set.find(edge.first) != node_set.end()) {

From 12a8f798690ac7e50deabcbb3e0f414654dc2d25 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 1 Feb 2020 21:27:33 -0700
Subject: [PATCH 078/645] rr_graph adopt RRGraph object

---
 vpr/src/route/rr_graph.cpp      | 36 ++++++++++++++++-----------------
 vpr/src/route/rr_graph_area.cpp | 25 +++++++++++------------
 2 files changed, 30 insertions(+), 31 deletions(-)

diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp
index 85934a6d6..d9c387cd2 100644
--- a/vpr/src/route/rr_graph.cpp
+++ b/vpr/src/route/rr_graph.cpp
@@ -3093,7 +3093,7 @@ class EdgeGroups {
     // Adds non-configurable edge to be group.
     //
     // Returns true if this is a new edge.
-    bool add_non_config_edge(int from_node, int to_node) {
+    bool add_non_config_edge(const RRNodeId& from_node, const RRNodeId& to_node) {
         auto result = node_edges_.insert(std::make_pair(from_node, to_node));
         return result.second;
     }
@@ -3108,13 +3108,13 @@ class EdgeGroups {
         std::vector<std::pair<int, int>> merges;
 
         VTR_ASSERT(node_count_ != std::numeric_limits<size_t>::max());
-        std::vector<int> node_to_node_set(node_count_, OPEN);
+        vtr::vector<RRNodeId, int> node_to_node_set(node_count_, OPEN);
 
         // First nievely make node groups.  When an edge joins two groups,
         // mark it for cleanup latter.
         for (const auto& edge : node_edges_) {
-            VTR_ASSERT(edge.first >= 0 && static_cast<size_t>(edge.first) < node_count_);
-            VTR_ASSERT(edge.second >= 0 && static_cast<size_t>(edge.second) < node_count_);
+            VTR_ASSERT(size_t(edge.first) < node_count_);
+            VTR_ASSERT(size_t(edge.second) < node_count_);
 
             int& from_set = node_to_node_set[edge.first];
             int& to_set = node_to_node_set[edge.second];
@@ -3175,8 +3175,8 @@ class EdgeGroups {
 
         // Create compact set of sets.
         for (size_t inode = 0; inode < node_to_node_set.size(); ++inode) {
-            if (node_to_node_set[inode] != OPEN) {
-                rr_non_config_node_sets_map_[node_to_node_set[inode]].push_back(inode);
+            if (node_to_node_set[RRNodeId(inode)] != OPEN) {
+                rr_non_config_node_sets_map_[node_to_node_set[RRNodeId(inode)]].push_back(RRNodeId(inode));
             }
         }
     }
@@ -3185,7 +3185,7 @@ class EdgeGroups {
     t_non_configurable_rr_sets output_sets() {
         t_non_configurable_rr_sets sets;
         for (auto& item : rr_non_config_node_sets_map_) {
-            std::set<RREdgeId> edge_set;
+            std::set<t_node_edge> edge_set;
             std::set<RRNodeId> node_set(item.second.begin(), item.second.end());
 
             for (const auto& edge : node_edges_) {
@@ -3203,12 +3203,12 @@ class EdgeGroups {
 
     // Set device context structures for non-configurable node sets.
     void set_device_context() {
-        std::vector<std::vector<int>> rr_non_config_node_sets;
+        std::vector<std::vector<RRNodeId>> rr_non_config_node_sets;
         for (auto& item : rr_non_config_node_sets_map_) {
             rr_non_config_node_sets.emplace_back(std::move(item.second));
         }
 
-        std::unordered_map<int, int> rr_node_to_non_config_node_set;
+        std::unordered_map<RRNodeId, int> rr_node_to_non_config_node_set;
         for (size_t set = 0; set < rr_non_config_node_sets.size(); ++set) {
             for (const auto inode : rr_non_config_node_sets[set]) {
                 rr_node_to_non_config_node_set.insert(
@@ -3244,22 +3244,22 @@ class EdgeGroups {
     size_t node_count_;
 
     // Set of non-configurable edges.
-    std::set<std::pair<int, int>> node_edges_;
+    std::set<std::pair<RRNodeId, RRNodeId>> node_edges_;
 
     // Compact set of node sets. Map key is arbitrary.
-    std::map<int, std::vector<int>> rr_non_config_node_sets_map_;
+    std::map<int, std::vector<RRNodeId>> rr_non_config_node_sets_map_;
 };
 
-static void expand_non_configurable(int inode, EdgeGroups* groups);
+static void expand_non_configurable(const RRNodeId& inode, EdgeGroups* groups);
 
 //Collects the sets of connected non-configurable edges in the RR graph
 static void create_edge_groups(EdgeGroups* groups) {
     //Walk through the RR graph and recursively expand non-configurable edges
     //to collect the sets of non-configurably connected nodes
     auto& device_ctx = g_vpr_ctx.device();
-    groups->set_node_count(device_ctx.rr_nodes.size());
+    groups->set_node_count(device_ctx.rr_graph.nodes().size());
 
-    for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); ++inode) {
+    for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) {
         expand_non_configurable(inode, groups);
     }
 
@@ -3267,14 +3267,14 @@ static void create_edge_groups(EdgeGroups* groups) {
 }
 
 //Builds a set of non-configurably connected RR graph edges
-static void expand_non_configurable(int inode, EdgeGroups* groups) {
+static void expand_non_configurable(const RRNodeId& inode, EdgeGroups* groups) {
     auto& device_ctx = g_vpr_ctx.device();
 
-    for (t_edge_size iedge = 0; iedge < device_ctx.rr_nodes[inode].num_edges(); ++iedge) {
-        bool edge_non_configurable = !device_ctx.rr_nodes[inode].edge_is_configurable(iedge);
+    for (const RREdgeId& iedge : device_ctx.rr_graph.node_out_edges(inode)) {
+        bool edge_non_configurable = !device_ctx.rr_graph.edge_is_configurable(iedge);
 
         if (edge_non_configurable) {
-            int to_node = device_ctx.rr_nodes[inode].edge_sink_node(iedge);
+            const RRNodeId& to_node = device_ctx.rr_graph.edge_sink_node(iedge);
 
             if (groups->add_non_config_edge(inode, to_node)) {
                 expand_non_configurable(to_node, groups);
diff --git a/vpr/src/route/rr_graph_area.cpp b/vpr/src/route/rr_graph_area.cpp
index 963bba43e..056cc1421 100644
--- a/vpr/src/route/rr_graph_area.cpp
+++ b/vpr/src/route/rr_graph_area.cpp
@@ -308,7 +308,8 @@ void count_unidir_routing_transistors(std::vector<t_segment_inf>& /*segment_inf*
     /* corresponding to IPINs will be 0.           */
 
     t_rr_type from_rr_type, to_rr_type;
-    int i, j, iseg, to_node, iedge, num_edges, maxlen;
+    int i, j, iseg, iedge, num_edges, maxlen;
+    RRNodeId to_node;
     int max_inputs_to_cblock;
     float input_cblock_trans;
 
@@ -318,7 +319,7 @@ void count_unidir_routing_transistors(std::vector<t_segment_inf>& /*segment_inf*
      * switches of all rr nodes. Thus we keep track of which muxes we have already
      * counted via the variable below. */
     bool* chan_node_switch_done;
-    chan_node_switch_done = (bool*)vtr::calloc(device_ctx.rr_nodes.size(), sizeof(bool));
+    chan_node_switch_done = (bool*)vtr::calloc(device_ctx.rr_graph.nodes().size(), sizeof(bool));
 
     /* The variable below is an accumulator variable that will add up all the   *
      * transistors in the routing.  Make double so that it doesn't stop         *
@@ -348,28 +349,26 @@ void count_unidir_routing_transistors(std::vector<t_segment_inf>& /*segment_inf*
         trans_track_to_cblock_buf = 0;
     }
 
-    num_inputs_to_cblock = (int*)vtr::calloc(device_ctx.rr_nodes.size(), sizeof(int));
+    num_inputs_to_cblock = (int*)vtr::calloc(device_ctx.rr_graph.nodes().size(), sizeof(int));
     maxlen = std::max(device_ctx.grid.width(), device_ctx.grid.height());
     cblock_counted = (bool*)vtr::calloc(maxlen, sizeof(bool));
 
     ntrans = 0;
-    for (size_t from_node = 0; from_node < device_ctx.rr_nodes.size(); from_node++) {
-        from_rr_type = device_ctx.rr_nodes[from_node].type();
+    for (const RRNodeId& from_node : device_ctx.rr_graph.nodes()) {
+        from_rr_type = device_ctx.rr_graph.node_type(from_node);
 
         switch (from_rr_type) {
             case CHANX:
             case CHANY:
-                num_edges = device_ctx.rr_nodes[from_node].num_edges();
-
                 /* Increment number of inputs per cblock if IPIN */
-                for (iedge = 0; iedge < num_edges; iedge++) {
-                    to_node = device_ctx.rr_nodes[from_node].edge_sink_node(iedge);
-                    to_rr_type = device_ctx.rr_nodes[to_node].type();
+                for (const RREdgeId& iedge : device_ctx.rr_graph.node_out_edges(from_node)) {
+                    RRNodeId to_node = device_ctx.rr_graph.edge_sink_node(iedge);
+                    to_rr_type = device_ctx.rr_graph.node_type(to_node);
 
                     /* Ignore any uninitialized rr_graph nodes */
-                    if ((device_ctx.rr_nodes[to_node].type() == SOURCE)
-                        && (device_ctx.rr_nodes[to_node].xlow() == 0) && (device_ctx.rr_nodes[to_node].ylow() == 0)
-                        && (device_ctx.rr_nodes[to_node].xhigh() == 0) && (device_ctx.rr_nodes[to_node].yhigh() == 0)) {
+                    if ((device_ctx.rr_graph.node_type(to_node) == SOURCE)
+                        && (device_ctx.rr_graph.node_xlow(to_node) == 0) && (device_ctx.rr_graph.node_ylow(to_node) == 0)
+                        && (device_ctx.rr_graph.node_xhigh(to_node) == 0) && (device_ctx.rr_graph.node_yhigh(to_node) == 0)) {
                         continue;
                     }
 

From a99835e1c121bc7052c6201f610046acb4a5d7bc Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 1 Feb 2020 21:53:31 -0700
Subject: [PATCH 079/645] rr_graph area estimator adopted RRGraph object

---
 vpr/src/route/rr_graph_area.cpp | 81 ++++++++++++++++-----------------
 vpr/src/route/rr_graph_util.cpp | 40 ++++++++--------
 vpr/src/route/rr_graph_util.h   |  4 +-
 3 files changed, 60 insertions(+), 65 deletions(-)

diff --git a/vpr/src/route/rr_graph_area.cpp b/vpr/src/route/rr_graph_area.cpp
index 056cc1421..a6e515159 100644
--- a/vpr/src/route/rr_graph_area.cpp
+++ b/vpr/src/route/rr_graph_area.cpp
@@ -33,7 +33,7 @@ static void count_unidir_routing_transistors(std::vector<t_segment_inf>& segment
                                              float R_minW_pmos,
                                              const float trans_sram_bit);
 
-static float get_cblock_trans(int* num_inputs_to_cblock, int wire_to_ipin_switch, int max_inputs_to_cblock, float trans_sram_bit);
+static float get_cblock_trans(const vtr::vector<RRNodeId, int>& num_inputs_to_cblock, int wire_to_ipin_switch, int max_inputs_to_cblock, float trans_sram_bit);
 
 static float* alloc_and_load_unsharable_switch_trans(int num_switch,
                                                      float trans_sram_bit,
@@ -101,7 +101,7 @@ void count_bidir_routing_transistors(int num_switch, int wire_to_ipin_switch, fl
      * optimistic (but I still think it's pretty reasonable).                    */
     auto& device_ctx = g_vpr_ctx.device();
 
-    int* num_inputs_to_cblock; /* [0..device_ctx.rr_nodes.size()-1], but all entries not    */
+    vtr::vector<RRNodeId, int> num_inputs_to_cblock; /* [0..device_ctx.rr_nodes.size()-1], but all entries not    */
 
     /* corresponding to IPINs will be 0.           */
 
@@ -110,7 +110,7 @@ void count_bidir_routing_transistors(int num_switch, int wire_to_ipin_switch, fl
     float *unsharable_switch_trans, *sharable_switch_trans; /* [0..num_switch-1] */
 
     t_rr_type from_rr_type, to_rr_type;
-    int iedge, num_edges, maxlen;
+    int maxlen;
     int iswitch, i, j, iseg, max_inputs_to_cblock;
     float input_cblock_trans, shared_opin_buffer_trans;
 
@@ -144,7 +144,7 @@ void count_bidir_routing_transistors(int num_switch, int wire_to_ipin_switch, fl
         trans_track_to_cblock_buf = 0;
     }
 
-    num_inputs_to_cblock = (int*)vtr::calloc(device_ctx.rr_nodes.size(), sizeof(int));
+    num_inputs_to_cblock.resize(device_ctx.rr_graph.nodes().size(), 0);
 
     maxlen = std::max(device_ctx.grid.width(), device_ctx.grid.height());
     cblock_counted = (bool*)vtr::calloc(maxlen, sizeof(bool));
@@ -156,29 +156,27 @@ void count_bidir_routing_transistors(int num_switch, int wire_to_ipin_switch, fl
     sharable_switch_trans = alloc_and_load_sharable_switch_trans(num_switch,
                                                                  R_minW_nmos, R_minW_pmos);
 
-    for (size_t from_node = 0; from_node < device_ctx.rr_nodes.size(); from_node++) {
-        from_rr_type = device_ctx.rr_nodes[from_node].type();
+    for (const RRNodeId& from_node : device_ctx.rr_graph.nodes()) {
+        from_rr_type = device_ctx.rr_graph.node_type(from_node);
 
         switch (from_rr_type) {
             case CHANX:
             case CHANY:
-                num_edges = device_ctx.rr_nodes[from_node].num_edges();
-
-                for (iedge = 0; iedge < num_edges; iedge++) {
-                    size_t to_node = device_ctx.rr_nodes[from_node].edge_sink_node(iedge);
-                    to_rr_type = device_ctx.rr_nodes[to_node].type();
+                for (const RREdgeId& iedge : device_ctx.rr_graph.node_out_edges(from_node)) {
+                    RRNodeId to_node = device_ctx.rr_graph.edge_sink_node(iedge);
+                    to_rr_type = device_ctx.rr_graph.node_type(to_node);
 
                     /* Ignore any uninitialized rr_graph nodes */
-                    if ((device_ctx.rr_nodes[to_node].type() == SOURCE)
-                        && (device_ctx.rr_nodes[to_node].xlow() == 0) && (device_ctx.rr_nodes[to_node].ylow() == 0)
-                        && (device_ctx.rr_nodes[to_node].xhigh() == 0) && (device_ctx.rr_nodes[to_node].yhigh() == 0)) {
+                    if ((device_ctx.rr_graph.node_type(to_node) == SOURCE)
+                        && (device_ctx.rr_graph.node_xlow(to_node) == 0) && (device_ctx.rr_graph.node_ylow(to_node) == 0)
+                        && (device_ctx.rr_graph.node_xhigh(to_node) == 0) && (device_ctx.rr_graph.node_yhigh(to_node) == 0)) {
                         continue;
                     }
 
                     switch (to_rr_type) {
                         case CHANX:
                         case CHANY:
-                            iswitch = device_ctx.rr_nodes[from_node].edge_switch(iedge);
+                            iswitch = (short)size_t(device_ctx.rr_graph.edge_switch(iedge));
 
                             if (device_ctx.rr_switch_inf[iswitch].buffered()) {
                                 iseg = seg_index_of_sblock(from_node, to_node);
@@ -214,8 +212,8 @@ void count_bidir_routing_transistors(int num_switch, int wire_to_ipin_switch, fl
                         default:
                             VPR_ERROR(VPR_ERROR_ROUTE,
                                       "in count_routing_transistors:\n"
-                                      "\tUnexpected connection from node %d (type %s) to node %d (type %s).\n",
-                                      from_node, rr_node_typename[from_rr_type], to_node, rr_node_typename[to_rr_type]);
+                                      "\tUnexpected connection from node %ld (type %s) to node %ld (type %s).\n",
+                                      size_t(from_node), rr_node_typename[from_rr_type], size_t(to_node), rr_node_typename[to_rr_type]);
                             break;
 
                     } /* End switch on to_rr_type. */
@@ -225,35 +223,34 @@ void count_bidir_routing_transistors(int num_switch, int wire_to_ipin_switch, fl
                 /* Now add in the shared buffer transistors, and reset some flags. */
 
                 if (from_rr_type == CHANX) {
-                    for (i = device_ctx.rr_nodes[from_node].xlow() - 1;
-                         i <= device_ctx.rr_nodes[from_node].xhigh(); i++) {
+                    for (i = device_ctx.rr_graph.node_xlow(from_node) - 1;
+                         i <= device_ctx.rr_graph.node_xhigh(from_node); i++) {
                         ntrans_sharing += shared_buffer_trans[i];
                         shared_buffer_trans[i] = 0.;
                     }
 
-                    for (i = device_ctx.rr_nodes[from_node].xlow(); i <= device_ctx.rr_nodes[from_node].xhigh();
+                    for (i = device_ctx.rr_graph.node_xlow(from_node); i <= device_ctx.rr_graph.node_xhigh(from_node);
                          i++)
                         cblock_counted[i] = false;
 
                 } else { /* CHANY */
-                    for (j = device_ctx.rr_nodes[from_node].ylow() - 1;
-                         j <= device_ctx.rr_nodes[from_node].yhigh(); j++) {
+                    for (j = device_ctx.rr_graph.node_ylow(from_node) - 1;
+                         j <= device_ctx.rr_graph.node_yhigh(from_node); j++) {
                         ntrans_sharing += shared_buffer_trans[j];
                         shared_buffer_trans[j] = 0.;
                     }
 
-                    for (j = device_ctx.rr_nodes[from_node].ylow(); j <= device_ctx.rr_nodes[from_node].yhigh();
+                    for (j = device_ctx.rr_graph.node_ylow(from_node); j <= device_ctx.rr_graph.node_yhigh(from_node);
                          j++)
                         cblock_counted[j] = false;
                 }
                 break;
 
             case OPIN:
-                num_edges = device_ctx.rr_nodes[from_node].num_edges();
                 shared_opin_buffer_trans = 0.;
 
-                for (iedge = 0; iedge < num_edges; iedge++) {
-                    iswitch = device_ctx.rr_nodes[from_node].edge_switch(iedge);
+                for (const RREdgeId& iedge : device_ctx.rr_graph.node_out_edges(from_node)) {
+                    iswitch = (short)size_t(device_ctx.rr_graph.edge_switch(iedge));
                     ntrans_no_sharing += unsharable_switch_trans[iswitch]
                                          + sharable_switch_trans[iswitch];
                     ntrans_sharing += unsharable_switch_trans[iswitch];
@@ -281,7 +278,7 @@ void count_bidir_routing_transistors(int num_switch, int wire_to_ipin_switch, fl
     input_cblock_trans = get_cblock_trans(num_inputs_to_cblock, wire_to_ipin_switch,
                                           max_inputs_to_cblock, trans_sram_bit);
 
-    free(num_inputs_to_cblock);
+    num_inputs_to_cblock.clear();
 
     ntrans_sharing += input_cblock_trans;
     ntrans_no_sharing += input_cblock_trans;
@@ -303,13 +300,12 @@ void count_unidir_routing_transistors(std::vector<t_segment_inf>& /*segment_inf*
     auto& device_ctx = g_vpr_ctx.device();
 
     bool* cblock_counted;      /* [0..max(device_ctx.grid.width(),device_ctx.grid.height())] -- 0th element unused. */
-    int* num_inputs_to_cblock; /* [0..device_ctx.rr_nodes.size()-1], but all entries not    */
+    vtr::vector<RRNodeId, int> num_inputs_to_cblock; /* [0..device_ctx.rr_nodes.size()-1], but all entries not    */
 
     /* corresponding to IPINs will be 0.           */
 
     t_rr_type from_rr_type, to_rr_type;
-    int i, j, iseg, iedge, num_edges, maxlen;
-    RRNodeId to_node;
+    int i, j, iseg, maxlen;
     int max_inputs_to_cblock;
     float input_cblock_trans;
 
@@ -318,8 +314,7 @@ void count_unidir_routing_transistors(std::vector<t_segment_inf>& /*segment_inf*
      * a single mux. We should count this mux only once as we look at the outgoing
      * switches of all rr nodes. Thus we keep track of which muxes we have already
      * counted via the variable below. */
-    bool* chan_node_switch_done;
-    chan_node_switch_done = (bool*)vtr::calloc(device_ctx.rr_graph.nodes().size(), sizeof(bool));
+    vtr::vector<RRNodeId, bool> chan_node_switch_done(device_ctx.rr_graph.nodes().size(), false);
 
     /* The variable below is an accumulator variable that will add up all the   *
      * transistors in the routing.  Make double so that it doesn't stop         *
@@ -349,7 +344,7 @@ void count_unidir_routing_transistors(std::vector<t_segment_inf>& /*segment_inf*
         trans_track_to_cblock_buf = 0;
     }
 
-    num_inputs_to_cblock = (int*)vtr::calloc(device_ctx.rr_graph.nodes().size(), sizeof(int));
+    num_inputs_to_cblock.resize(device_ctx.rr_graph.nodes().size(), 0);
     maxlen = std::max(device_ctx.grid.width(), device_ctx.grid.height());
     cblock_counted = (bool*)vtr::calloc(maxlen, sizeof(bool));
 
@@ -376,10 +371,10 @@ void count_unidir_routing_transistors(std::vector<t_segment_inf>& /*segment_inf*
                         case CHANX:
                         case CHANY:
                             if (!chan_node_switch_done[to_node]) {
-                                int switch_index = device_ctx.rr_nodes[from_node].edge_switch(iedge);
+                                int switch_index = (int)size_t(device_ctx.rr_graph.edge_switch(iedge));
                                 auto switch_type = device_ctx.rr_switch_inf[switch_index].type();
 
-                                int fan_in = device_ctx.rr_nodes[to_node].fan_in();
+                                int fan_in = device_ctx.rr_graph.node_in_edges(to_node).size();
 
                                 if (device_ctx.rr_switch_inf[switch_index].type() == SwitchType::MUX) {
                                     /* Each wire segment begins with a multipexer followed by a driver for unidirectional */
@@ -433,8 +428,8 @@ void count_unidir_routing_transistors(std::vector<t_segment_inf>& /*segment_inf*
                         default:
                             VPR_ERROR(VPR_ERROR_ROUTE,
                                       "in count_routing_transistors:\n"
-                                      "\tUnexpected connection from node %d (type %d) to node %d (type %d).\n",
-                                      from_node, from_rr_type, to_node, to_rr_type);
+                                      "\tUnexpected connection from node %ld (type %d) to node %ld (type %d).\n",
+                                      size_t(from_node), from_rr_type, size_t(to_node), to_rr_type);
                             break;
 
                     } /* End switch on to_rr_type. */
@@ -443,11 +438,11 @@ void count_unidir_routing_transistors(std::vector<t_segment_inf>& /*segment_inf*
 
                 /* Reset some flags */
                 if (from_rr_type == CHANX) {
-                    for (i = device_ctx.rr_nodes[from_node].xlow(); i <= device_ctx.rr_nodes[from_node].xhigh(); i++)
+                    for (i = device_ctx.rr_graph.node_xlow(from_node); i <= device_ctx.rr_graph.node_xhigh(from_node); i++)
                         cblock_counted[i] = false;
 
                 } else { /* CHANY */
-                    for (j = device_ctx.rr_nodes[from_node].ylow(); j <= device_ctx.rr_nodes[from_node].yhigh();
+                    for (j = device_ctx.rr_graph.node_ylow(from_node); j <= device_ctx.rr_graph.node_yhigh(from_node);
                          j++)
                         cblock_counted[j] = false;
                 }
@@ -467,8 +462,8 @@ void count_unidir_routing_transistors(std::vector<t_segment_inf>& /*segment_inf*
                                           max_inputs_to_cblock, trans_sram_bit);
 
     free(cblock_counted);
-    free(num_inputs_to_cblock);
-    free(chan_node_switch_done);
+    num_inputs_to_cblock.clear();
+    chan_node_switch_done.clear();
 
     ntrans += input_cblock_trans;
 
@@ -477,7 +472,7 @@ void count_unidir_routing_transistors(std::vector<t_segment_inf>& /*segment_inf*
     VTR_LOG("\tTotal routing area: %#g, per logic tile: %#g\n", ntrans, ntrans / (float)(device_ctx.grid.width() * device_ctx.grid.height()));
 }
 
-static float get_cblock_trans(int* num_inputs_to_cblock, int wire_to_ipin_switch, int max_inputs_to_cblock, float trans_sram_bit) {
+static float get_cblock_trans(const vtr::vector<RRNodeId, int>& num_inputs_to_cblock, int wire_to_ipin_switch, int max_inputs_to_cblock, float trans_sram_bit) {
     /* Computes the transistors in the input connection block multiplexers and   *
      * the buffers from connection block outputs to the logic block input pins.  *
      * For speed, I precompute the number of transistors in the multiplexers of  *
@@ -505,7 +500,7 @@ static float get_cblock_trans(int* num_inputs_to_cblock, int wire_to_ipin_switch
 
     trans_count = 0.;
 
-    for (size_t i = 0; i < device_ctx.rr_nodes.size(); i++) {
+    for (const RRNodeId& i : device_ctx.rr_graph.nodes()) {
         num_inputs = num_inputs_to_cblock[i];
         trans_count += trans_per_cblock[num_inputs];
     }
diff --git a/vpr/src/route/rr_graph_util.cpp b/vpr/src/route/rr_graph_util.cpp
index c91ef8109..dd808e440 100644
--- a/vpr/src/route/rr_graph_util.cpp
+++ b/vpr/src/route/rr_graph_util.cpp
@@ -6,20 +6,20 @@
 #include "globals.h"
 #include "rr_graph_util.h"
 
-int seg_index_of_cblock(t_rr_type from_rr_type, int to_node) {
+int seg_index_of_cblock(t_rr_type from_rr_type, const RRNodeId& to_node) {
     /* Returns the segment number (distance along the channel) of the connection *
      * box from from_rr_type (CHANX or CHANY) to to_node (IPIN).                 */
 
     auto& device_ctx = g_vpr_ctx.device();
 
     if (from_rr_type == CHANX)
-        return (device_ctx.rr_nodes[to_node].xlow());
+        return (device_ctx.rr_graph.node_xlow(to_node));
     else
         /* CHANY */
-        return (device_ctx.rr_nodes[to_node].ylow());
+        return (device_ctx.rr_graph.node_ylow(to_node));
 }
 
-int seg_index_of_sblock(int from_node, int to_node) {
+int seg_index_of_sblock(const RRNodeId& from_node, const RRNodeId& to_node) {
     /* Returns the segment number (distance along the channel) of the switch box *
      * box from from_node (CHANX or CHANY) to to_node (CHANX or CHANY).  The     *
      * switch box on the left side of a CHANX segment at (i,j) has seg_index =   *
@@ -31,47 +31,47 @@ int seg_index_of_sblock(int from_node, int to_node) {
 
     auto& device_ctx = g_vpr_ctx.device();
 
-    from_rr_type = device_ctx.rr_nodes[from_node].type();
-    to_rr_type = device_ctx.rr_nodes[to_node].type();
+    from_rr_type = device_ctx.rr_graph.node_type(from_node);
+    to_rr_type = device_ctx.rr_graph.node_type(to_node);
 
     if (from_rr_type == CHANX) {
         if (to_rr_type == CHANY) {
-            return (device_ctx.rr_nodes[to_node].xlow());
+            return (device_ctx.rr_graph.node_xlow(to_node));
         } else if (to_rr_type == CHANX) {
-            if (device_ctx.rr_nodes[to_node].xlow() > device_ctx.rr_nodes[from_node].xlow()) { /* Going right */
-                return (device_ctx.rr_nodes[from_node].xhigh());
+            if (device_ctx.rr_graph.node_xlow(to_node) > device_ctx.rr_graph.node_xlow(from_node)) { /* Going right */
+                return (device_ctx.rr_graph.node_xhigh(from_node));
             } else { /* Going left */
-                return (device_ctx.rr_nodes[to_node].xhigh());
+                return (device_ctx.rr_graph.node_xhigh(to_node));
             }
         } else {
             VPR_FATAL_ERROR(VPR_ERROR_ROUTE,
-                            "in seg_index_of_sblock: to_node %d is of type %d.\n",
-                            to_node, to_rr_type);
+                            "in seg_index_of_sblock: to_node %ld is of type %d.\n",
+                            size_t(to_node), to_rr_type);
             return OPEN; //Should not reach here once thrown
         }
     }
     /* End from_rr_type is CHANX */
     else if (from_rr_type == CHANY) {
         if (to_rr_type == CHANX) {
-            return (device_ctx.rr_nodes[to_node].ylow());
+            return (device_ctx.rr_graph.node_ylow(to_node));
         } else if (to_rr_type == CHANY) {
-            if (device_ctx.rr_nodes[to_node].ylow() > device_ctx.rr_nodes[from_node].ylow()) { /* Going up */
-                return (device_ctx.rr_nodes[from_node].yhigh());
+            if (device_ctx.rr_graph.node_ylow(to_node) > device_ctx.rr_graph.node_ylow(from_node)) { /* Going up */
+                return (device_ctx.rr_graph.node_yhigh(from_node));
             } else { /* Going down */
-                return (device_ctx.rr_nodes[to_node].yhigh());
+                return (device_ctx.rr_graph.node_yhigh(to_node));
             }
         } else {
             VPR_FATAL_ERROR(VPR_ERROR_ROUTE,
-                            "in seg_index_of_sblock: to_node %d is of type %d.\n",
-                            to_node, to_rr_type);
+                            "in seg_index_of_sblock: to_node %ld is of type %d.\n",
+                            size_t(to_node), to_rr_type);
             return OPEN; //Should not reach here once thrown
         }
     }
     /* End from_rr_type is CHANY */
     else {
         VPR_FATAL_ERROR(VPR_ERROR_ROUTE,
-                        "in seg_index_of_sblock: from_node %d is of type %d.\n",
-                        from_node, from_rr_type);
+                        "in seg_index_of_sblock: from_node %ld is of type %d.\n",
+                        size_t(from_node), from_rr_type);
         return OPEN; //Should not reach here once thrown
     }
 }
diff --git a/vpr/src/route/rr_graph_util.h b/vpr/src/route/rr_graph_util.h
index c065500bd..14da78eac 100644
--- a/vpr/src/route/rr_graph_util.h
+++ b/vpr/src/route/rr_graph_util.h
@@ -1,8 +1,8 @@
 #ifndef RR_GRAPH_UTIL_H
 #define RR_GRAPH_UTIL_H
 
-int seg_index_of_cblock(t_rr_type from_rr_type, int to_node);
+int seg_index_of_cblock(t_rr_type from_rr_type, const RRNodeId& to_node);
 
-int seg_index_of_sblock(int from_node, int to_node);
+int seg_index_of_sblock(const RRNodeId& from_node, const RRNodeId& to_node);
 
 #endif

From b49b8208d1d3160ac3cf007bebd7e0353f76f4c9 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 1 Feb 2020 22:19:31 -0700
Subject: [PATCH 080/645] rr_graph timing parameter builder adopt RRGraph
 object

---
 vpr/src/device/rr_graph_obj.cpp          | 13 +++++
 vpr/src/device/rr_graph_obj.h            | 12 +++++
 vpr/src/route/rr_graph_timing_params.cpp | 66 ++++++++++++------------
 3 files changed, 58 insertions(+), 33 deletions(-)

diff --git a/vpr/src/device/rr_graph_obj.cpp b/vpr/src/device/rr_graph_obj.cpp
index 316bc6e87..6a05b6a21 100644
--- a/vpr/src/device/rr_graph_obj.cpp
+++ b/vpr/src/device/rr_graph_obj.cpp
@@ -194,6 +194,11 @@ float RRGraph::node_C(const RRNodeId& node) const {
     return node_Cs_[node];
 }
 
+short RRGraph::node_rc_data_index(const RRNodeId& node) const {
+    VTR_ASSERT_SAFE(valid_node_id(node));
+    return node_rc_data_indices_[node];
+}
+
 /*
  * Get a segment id of a node in rr_graph 
  */
@@ -769,6 +774,7 @@ void RRGraph::reserve_nodes(const unsigned long& num_nodes) {
     this->node_sides_.reserve(num_nodes);
     this->node_Rs_.reserve(num_nodes);
     this->node_Cs_.reserve(num_nodes);
+    this->node_rc_data_indices_.reserve(num_nodes);
     this->node_segments_.reserve(num_nodes);
 
     /* Edge-related vectors */
@@ -818,6 +824,7 @@ RRNodeId RRGraph::create_node(const t_rr_type& type) {
     node_sides_.push_back(NUM_SIDES);
     node_Rs_.push_back(0.);
     node_Cs_.push_back(0.);
+    node_rc_data_indices_.push_back(-1);
     node_segments_.push_back(RRSegmentId::INVALID());
 
     node_edges_.emplace_back(); //Initially empty
@@ -1028,6 +1035,12 @@ void RRGraph::set_node_C(const RRNodeId& node, const float& C) {
     node_Cs_[node] = C;
 }
 
+void RRGraph::set_node_rc_data_index(const RRNodeId& node, const short& rc_data_index) {
+    VTR_ASSERT(valid_node_id(node));
+
+    node_rc_data_indices_[node] = rc_data_index;
+}
+
 /*
  * Set a segment id for a node in rr_graph 
  */
diff --git a/vpr/src/device/rr_graph_obj.h b/vpr/src/device/rr_graph_obj.h
index 85bf7de4b..abafa59b6 100644
--- a/vpr/src/device/rr_graph_obj.h
+++ b/vpr/src/device/rr_graph_obj.h
@@ -454,6 +454,13 @@ class RRGraph {
     /* Get capacitance of a node, used to built RC tree for timing analysis */
     float node_C(const RRNodeId& node) const;
 
+    /* Get the index of rc data in the list of rc_data data structure
+     * It contains the RC parasitics for different nodes in the RRGraph
+     * when used in evaluate different routing paths
+     * See cross-reference section in this header file for more details
+     */
+    short node_rc_data_index(const RRNodeId& node) const;
+
     /* Get segment id of a node, containing the information of the routing
      * segment that the node represents. See more details in the data structure t_segment_inf
      */
@@ -694,6 +701,10 @@ class RRGraph {
     void set_node_R(const RRNodeId& node, const float& R);
     void set_node_C(const RRNodeId& node, const float& C);
 
+    /* Set the flyweight RC data index for node, see node_rc_data_index() for details */
+    /* TODO: the cost index should be changed to a StrongId!!! */
+    void set_node_rc_data_index(const RRNodeId& node, const short& rc_data_index);
+
     /* Set the routing segment linked to a node, only applicable to CHANX and CHANY */
     void set_node_segment(const RRNodeId& node, const RRSegmentId& segment_index);
 
@@ -841,6 +852,7 @@ class RRGraph {
     vtr::vector<RRNodeId, e_side> node_sides_;
     vtr::vector<RRNodeId, float> node_Rs_;
     vtr::vector<RRNodeId, float> node_Cs_;
+    vtr::vector<RRNodeId, short> node_rc_data_indices_;
     vtr::vector<RRNodeId, RRSegmentId> node_segments_; /* Segment ids for each node */
 
     /*
diff --git a/vpr/src/route/rr_graph_timing_params.cpp b/vpr/src/route/rr_graph_timing_params.cpp
index 69ea0203a..8d581f957 100644
--- a/vpr/src/route/rr_graph_timing_params.cpp
+++ b/vpr/src/route/rr_graph_timing_params.cpp
@@ -28,14 +28,14 @@ void add_rr_graph_C_from_switches(float C_ipin_cblock) {
      *    INCLUDE_TRACK_BUFFERS)                                    	    */
 
     int switch_index, maxlen;
-    size_t to_node;
+    RRNodeId to_node;
     int icblock, isblock, iseg_low, iseg_high;
     float Cin, Cout;
     t_rr_type from_rr_type, to_rr_type;
     bool* cblock_counted; /* [0..maxlen-1] -- 0th element unused. */
     float* buffer_Cin;    /* [0..maxlen-1] */
     bool buffered;
-    float* Couts_to_add; /* UDSD */
+    vtr::vector<RRNodeId, float> Couts_to_add; /* UDSD */
 
     auto& device_ctx = g_vpr_ctx.device();
     auto& mutable_device_ctx = g_vpr_ctx.mutable_device();
@@ -44,21 +44,21 @@ void add_rr_graph_C_from_switches(float C_ipin_cblock) {
     cblock_counted = (bool*)vtr::calloc(maxlen, sizeof(bool));
     buffer_Cin = (float*)vtr::calloc(maxlen, sizeof(float));
 
-    std::vector<float> rr_node_C(device_ctx.rr_nodes.size(), 0.); //Stores the final C
+    vtr::vector<RRNodeId, float> rr_node_C(device_ctx.rr_graph.nodes().size(), 0.); //Stores the final C
 
-    for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); inode++) {
+    for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) { 
         //The C may have already been partly initialized (e.g. with metal capacitance)
-        rr_node_C[inode] += device_ctx.rr_nodes[inode].C();
+        rr_node_C[inode] += device_ctx.rr_graph.node_C(inode);
 
-        from_rr_type = device_ctx.rr_nodes[inode].type();
+        from_rr_type = device_ctx.rr_graph.node_type(inode);
 
         if (from_rr_type == CHANX || from_rr_type == CHANY) {
-            for (t_edge_size iedge = 0; iedge < device_ctx.rr_nodes[inode].num_edges(); iedge++) {
-                to_node = device_ctx.rr_nodes[inode].edge_sink_node(iedge);
-                to_rr_type = device_ctx.rr_nodes[to_node].type();
+            for (const RREdgeId& iedge : device_ctx.rr_graph.node_out_edges(inode)) {
+                to_node = device_ctx.rr_graph.edge_sink_node(iedge);
+                to_rr_type = device_ctx.rr_graph.node_type(to_node);
 
                 if (to_rr_type == CHANX || to_rr_type == CHANY) {
-                    switch_index = device_ctx.rr_nodes[inode].edge_switch(iedge);
+                    switch_index = (int)size_t(device_ctx.rr_graph.edge_switch(iedge));
                     Cin = device_ctx.rr_switch_inf[switch_index].Cin;
                     Cout = device_ctx.rr_switch_inf[switch_index].Cout;
                     buffered = device_ctx.rr_switch_inf[switch_index].buffered();
@@ -80,14 +80,14 @@ void add_rr_graph_C_from_switches(float C_ipin_cblock) {
                      * the buffers at that location have different sizes, I use the *
                      * input capacitance of the largest one.                        */
 
-                    if (!buffered && inode < to_node) { /* Pass transistor. */
+                    if (!buffered && size_t(inode) < size_t(to_node)) { /* Pass transistor. */
                         rr_node_C[inode] += Cin;
                         rr_node_C[to_node] += Cout;
                     }
 
                     else if (buffered) {
                         /* Prevent double counting of capacitance for UDSD */
-                        if (device_ctx.rr_nodes[to_node].direction() == BI_DIRECTION) {
+                        if (device_ctx.rr_graph.node_direction(to_node) == BI_DIRECTION) {
                             /* For multiple-driver architectures the output capacitance can
                              * be added now since each edge is actually a driver */
                             rr_node_C[to_node] += Cout;
@@ -129,11 +129,11 @@ void add_rr_graph_C_from_switches(float C_ipin_cblock) {
              * }     */
 
             if (from_rr_type == CHANX) {
-                iseg_low = device_ctx.rr_nodes[inode].xlow();
-                iseg_high = device_ctx.rr_nodes[inode].xhigh();
+                iseg_low = device_ctx.rr_graph.node_xlow(inode);
+                iseg_high = device_ctx.rr_graph.node_xhigh(inode);
             } else { /* CHANY */
-                iseg_low = device_ctx.rr_nodes[inode].ylow();
-                iseg_high = device_ctx.rr_nodes[inode].yhigh();
+                iseg_low = device_ctx.rr_graph.node_ylow(inode);
+                iseg_high = device_ctx.rr_graph.node_yhigh(inode);
             }
 
             for (icblock = iseg_low; icblock <= iseg_high; icblock++) {
@@ -148,17 +148,17 @@ void add_rr_graph_C_from_switches(float C_ipin_cblock) {
         }
         /* End node is CHANX or CHANY */
         else if (from_rr_type == OPIN) {
-            for (t_edge_size iedge = 0; iedge < device_ctx.rr_nodes[inode].num_edges(); iedge++) {
-                switch_index = device_ctx.rr_nodes[inode].edge_switch(iedge);
-                to_node = device_ctx.rr_nodes[inode].edge_sink_node(iedge);
-                to_rr_type = device_ctx.rr_nodes[to_node].type();
+            for (const RREdgeId& iedge : device_ctx.rr_graph.node_out_edges(inode)) {
+                switch_index = (int)size_t(device_ctx.rr_graph.edge_switch(iedge));
+                to_node = device_ctx.rr_graph.edge_sink_node(iedge);
+                to_rr_type = device_ctx.rr_graph.node_type(to_node);
 
                 if (to_rr_type != CHANX && to_rr_type != CHANY)
                     continue;
 
-                if (device_ctx.rr_nodes[to_node].direction() == BI_DIRECTION) {
+                if (device_ctx.rr_graph.node_direction(to_node) == BI_DIRECTION) {
                     Cout = device_ctx.rr_switch_inf[switch_index].Cout;
-                    to_node = device_ctx.rr_nodes[inode].edge_sink_node(iedge); /* Will be CHANX or CHANY */
+                    to_node = device_ctx.rr_graph.edge_sink_node(iedge); /* Will be CHANX or CHANY */
                     rr_node_C[to_node] += Cout;
                 }
             }
@@ -170,30 +170,30 @@ void add_rr_graph_C_from_switches(float C_ipin_cblock) {
      * Current structures only keep switch information from a node to the next node and
      * not the reverse.  Therefore I need to go through all the possible edges to figure
      * out what the Cout's should be */
-    Couts_to_add = (float*)vtr::calloc(device_ctx.rr_nodes.size(), sizeof(float));
-    for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); inode++) {
-        for (t_edge_size iedge = 0; iedge < device_ctx.rr_nodes[inode].num_edges(); iedge++) {
-            switch_index = device_ctx.rr_nodes[inode].edge_switch(iedge);
-            to_node = device_ctx.rr_nodes[inode].edge_sink_node(iedge);
-            to_rr_type = device_ctx.rr_nodes[to_node].type();
+    Couts_to_add.resize(device_ctx.rr_graph.nodes().size(), 0.);
+    for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) {
+        for (const RREdgeId& iedge : device_ctx.rr_graph.node_out_edges(inode)) {
+            switch_index = (int)size_t(device_ctx.rr_graph.edge_switch(iedge));
+            to_node = device_ctx.rr_graph.edge_sink_node(iedge);
+            to_rr_type = device_ctx.rr_graph.node_type(to_node);
             if (to_rr_type == CHANX || to_rr_type == CHANY) {
-                if (device_ctx.rr_nodes[to_node].direction() != BI_DIRECTION) {
+                if (device_ctx.rr_graph.node_direction(to_node) != BI_DIRECTION) {
                     /* Cout was not added in these cases */
                     Couts_to_add[to_node] = std::max(Couts_to_add[to_node], device_ctx.rr_switch_inf[switch_index].Cout);
                 }
             }
         }
     }
-    for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); inode++) {
+    for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) {
         rr_node_C[inode] += Couts_to_add[inode];
     }
 
     //Create the final flywieghted t_rr_rc_data
-    for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); inode++) {
-        mutable_device_ctx.rr_nodes[inode].set_rc_index(find_create_rr_rc_data(device_ctx.rr_nodes[inode].R(), rr_node_C[inode]));
+    for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) {
+        mutable_device_ctx.rr_graph.set_node_rc_data_index(inode, find_create_rr_rc_data(device_ctx.rr_graph.node_R(inode), rr_node_C[inode]));
     }
 
-    free(Couts_to_add);
+    Couts_to_add.clear();
     free(cblock_counted);
     free(buffer_Cin);
 }

From 74c532e95392cd14b59e25b45da2b347b4664757 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 1 Feb 2020 22:22:16 -0700
Subject: [PATCH 081/645] segment stats adopt RRGraph object

---
 vpr/src/route/segment_stats.cpp | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/vpr/src/route/segment_stats.cpp b/vpr/src/route/segment_stats.cpp
index 7af48b119..f42231e1b 100644
--- a/vpr/src/route/segment_stats.cpp
+++ b/vpr/src/route/segment_stats.cpp
@@ -43,9 +43,9 @@ void get_segment_usage_stats(std::vector<t_segment_inf>& segment_inf) {
     seg_occ_by_type = (int*)vtr::calloc(segment_inf.size(), sizeof(int));
     seg_cap_by_type = (int*)vtr::calloc(segment_inf.size(), sizeof(int));
 
-    for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); inode++) {
-        if (device_ctx.rr_nodes[inode].type() == CHANX || device_ctx.rr_nodes[inode].type() == CHANY) {
-            cost_index = device_ctx.rr_nodes[inode].cost_index();
+    for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) {
+        if (device_ctx.rr_graph.node_type(inode) == CHANX || device_ctx.rr_graph.node_type(inode) == CHANY) {
+            cost_index = device_ctx.rr_graph.node_cost_index(inode);
             size_t seg_type = device_ctx.rr_indexed_data[cost_index].seg_index;
 
             if (!segment_inf[seg_type].longline)
@@ -54,9 +54,9 @@ void get_segment_usage_stats(std::vector<t_segment_inf>& segment_inf) {
                 length = LONGLINE;
 
             seg_occ_by_length[length] += route_ctx.rr_node_route_inf[inode].occ();
-            seg_cap_by_length[length] += device_ctx.rr_nodes[inode].capacity();
+            seg_cap_by_length[length] += device_ctx.rr_graph.node_capacity(inode);
             seg_occ_by_type[seg_type] += route_ctx.rr_node_route_inf[inode].occ();
-            seg_cap_by_type[seg_type] += device_ctx.rr_nodes[inode].capacity();
+            seg_cap_by_type[seg_type] += device_ctx.rr_graph.node_capacity(inode);
         }
     }
 

From d2485789a4a4b9a3443783fc08582deaf1d10886 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 1 Feb 2020 22:26:13 -0700
Subject: [PATCH 082/645] spatial route tree lookup adopt RRGraph object

---
 vpr/src/route/spatial_route_tree_lookup.cpp | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/vpr/src/route/spatial_route_tree_lookup.cpp b/vpr/src/route/spatial_route_tree_lookup.cpp
index 20c9b8524..e27b6aa32 100644
--- a/vpr/src/route/spatial_route_tree_lookup.cpp
+++ b/vpr/src/route/spatial_route_tree_lookup.cpp
@@ -75,27 +75,27 @@ size_t grid_to_bin_y(size_t grid_y, const SpatialRouteTreeLookup& spatial_lookup
 bool validate_route_tree_spatial_lookup(t_rt_node* rt_node, const SpatialRouteTreeLookup& spatial_lookup) {
     auto& device_ctx = g_vpr_ctx.device();
 
-    auto& rr_node = device_ctx.rr_nodes[rt_node->inode];
+    const RRNodeId& rr_node = rt_node->inode;
 
-    int bin_xlow = grid_to_bin_x(rr_node.xlow(), spatial_lookup);
-    int bin_ylow = grid_to_bin_y(rr_node.ylow(), spatial_lookup);
-    int bin_xhigh = grid_to_bin_x(rr_node.xhigh(), spatial_lookup);
-    int bin_yhigh = grid_to_bin_y(rr_node.yhigh(), spatial_lookup);
+    int bin_xlow = grid_to_bin_x(device_ctx.rr_graph.node_xlow(rr_node), spatial_lookup);
+    int bin_ylow = grid_to_bin_y(device_ctx.rr_graph.node_ylow(rr_node), spatial_lookup);
+    int bin_xhigh = grid_to_bin_x(device_ctx.rr_graph.node_xhigh(rr_node), spatial_lookup);
+    int bin_yhigh = grid_to_bin_y(device_ctx.rr_graph.node_yhigh(rr_node), spatial_lookup);
 
     bool valid = true;
 
     auto& low_bin_rt_nodes = spatial_lookup[bin_xlow][bin_ylow];
     if (std::find(low_bin_rt_nodes.begin(), low_bin_rt_nodes.end(), rt_node) == low_bin_rt_nodes.end()) {
         valid = false;
-        VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Failed to find route tree node %d at (low coord %d,%d) in spatial lookup [bin %d,%d]",
-                        rt_node->inode, rr_node.xlow(), rr_node.ylow(), bin_xlow, bin_ylow);
+        VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Failed to find route tree node %ld at (low coord %d,%d) in spatial lookup [bin %d,%d]",
+                        size_t(rt_node->inode), device_ctx.rr_graph.node_xlow(rr_node), device_ctx.rr_graph.node_ylow(rr_node), bin_xlow, bin_ylow);
     }
 
     auto& high_bin_rt_nodes = spatial_lookup[bin_xhigh][bin_yhigh];
     if (std::find(high_bin_rt_nodes.begin(), high_bin_rt_nodes.end(), rt_node) == high_bin_rt_nodes.end()) {
         valid = false;
-        VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Failed to find route tree node %d at (high coord %d,%d) in spatial lookup [bin %d,%d]",
-                        rt_node->inode, rr_node.xhigh(), rr_node.yhigh(), bin_xhigh, bin_yhigh);
+        VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Failed to find route tree node %ld at (high coord %d,%d) in spatial lookup [bin %d,%d]",
+                        size_t(rt_node->inode), device_ctx.rr_graph.node_xhigh(rr_node), device_ctx.rr_graph.node_yhigh(rr_node), bin_xhigh, bin_yhigh);
     }
 
     //Recurse

From 7b406e28ab4da8d12c2a2217ba085c46d4f172aa Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 1 Feb 2020 22:35:29 -0700
Subject: [PATCH 083/645] Vpr timing graph resolver adopt RRGraph Object

---
 vpr/src/timing/VprTimingGraphResolver.cpp | 46 +++++++++++------------
 1 file changed, 23 insertions(+), 23 deletions(-)

diff --git a/vpr/src/timing/VprTimingGraphResolver.cpp b/vpr/src/timing/VprTimingGraphResolver.cpp
index 39be7cd0c..6a21b2180 100644
--- a/vpr/src/timing/VprTimingGraphResolver.cpp
+++ b/vpr/src/timing/VprTimingGraphResolver.cpp
@@ -280,45 +280,45 @@ void VprTimingGraphResolver::get_detailed_interconnect_components_helper(std::ve
 
     while (node != nullptr) {
         //Process the current interconnect component if it is of type OPIN, CHANX, CHANY, IPIN
-        if (device_ctx.rr_nodes[node->inode].type() == OPIN
-            || device_ctx.rr_nodes[node->inode].type() == IPIN
-            || device_ctx.rr_nodes[node->inode].type() == CHANX
-            || device_ctx.rr_nodes[node->inode].type() == CHANY) {
+        if (device_ctx.rr_graph.node_type(node->inode) == OPIN
+            || device_ctx.rr_graph.node_type(node->inode) == IPIN
+            || device_ctx.rr_graph.node_type(node->inode) == CHANX
+            || device_ctx.rr_graph.node_type(node->inode) == CHANY) {
             tatum::DelayComponent net_component; //declare a new instance of DelayComponent
 
-            net_component.type_name = device_ctx.rr_nodes[node->inode].type_string(); //write the component's type as a routing resource node
-            net_component.type_name += ":" + std::to_string(node->inode) + " ";       //add the index of the routing resource node
-            if (device_ctx.rr_nodes[node->inode].type() == OPIN || device_ctx.rr_nodes[node->inode].type() == IPIN) {
+            net_component.type_name = std::string(rr_node_typename[device_ctx.rr_graph.node_type(node->inode)]); //write the component's type as a routing resource node
+            net_component.type_name += ":" + std::to_string(size_t(node->inode)) + " ";       //add the index of the routing resource node
+            if (device_ctx.rr_graph.node_type(node->inode) == OPIN || device_ctx.rr_graph.node_type(node->inode) == IPIN) {
                 net_component.type_name += "side:";                                        //add the side of the routing resource node
-                net_component.type_name += device_ctx.rr_nodes[node->inode].side_string(); //add the side of the routing resource node
+                net_component.type_name += std::string(SIDE_STRING[device_ctx.rr_graph.node_side(node->inode)]); //add the side of the routing resource node
                 // For OPINs and IPINs the starting and ending coordinate are identical, so we can just arbitrarily assign the start to larger values
                 // and the end to the lower coordinate
-                start_x = " (" + std::to_string(device_ctx.rr_nodes[node->inode].xhigh()) + ","; //start and end coordinates are the same for OPINs and IPINs
-                start_y = std::to_string(device_ctx.rr_nodes[node->inode].yhigh()) + ")";
+                start_x = " (" + std::to_string(device_ctx.rr_graph.node_xhigh(node->inode)) + ","; //start and end coordinates are the same for OPINs and IPINs
+                start_y = std::to_string(device_ctx.rr_graph.node_yhigh(node->inode)) + ")";
                 end_x = "";
                 end_y = "";
                 arrow = "";
             }
-            if (device_ctx.rr_nodes[node->inode].type() == CHANX || device_ctx.rr_nodes[node->inode].type() == CHANY) {                                         //for channels, we would like to describe the component with segment specific information
-                net_component.type_name += device_ctx.arch->Segments[device_ctx.rr_indexed_data[device_ctx.rr_nodes[node->inode].cost_index()].seg_index].name; //Write the segment name
-                net_component.type_name += " length:" + std::to_string(device_ctx.rr_nodes[node->inode].length());                                              //add the length of the segment
+            if (device_ctx.rr_graph.node_type(node->inode) == CHANX || device_ctx.rr_graph.node_type(node->inode) == CHANY) {                                         //for channels, we would like to describe the component with segment specific information
+                net_component.type_name += device_ctx.arch->Segments[device_ctx.rr_indexed_data[device_ctx.rr_graph.node_cost_index(node->inode)].seg_index].name; //Write the segment name
+                net_component.type_name += " length:" + std::to_string(device_ctx.rr_graph.node_length(node->inode));                                              //add the length of the segment
                 //Figure out the starting and ending coordinate of the segment depending on the direction
 
                 arrow = "->"; //we will point the coordinates from start to finish, left to right
 
-                if (device_ctx.rr_nodes[node->inode].direction() == DEC_DIRECTION) {                 //signal travels along decreasing direction
-                    start_x = " (" + std::to_string(device_ctx.rr_nodes[node->inode].xhigh()) + ","; //start coordinates have large value
-                    start_y = std::to_string(device_ctx.rr_nodes[node->inode].yhigh()) + ")";
-                    end_x = "(" + std::to_string(device_ctx.rr_nodes[node->inode].xlow()) + ","; //end coordinates have smaller value
-                    end_y = std::to_string(device_ctx.rr_nodes[node->inode].ylow()) + ")";
+                if (device_ctx.rr_graph.node_direction(node->inode) == DEC_DIRECTION) {                 //signal travels along decreasing direction
+                    start_x = " (" + std::to_string(device_ctx.rr_graph.node_xhigh(node->inode)) + ","; //start coordinates have large value
+                    start_y = std::to_string(device_ctx.rr_graph.node_yhigh(node->inode)) + ")";
+                    end_x = "(" + std::to_string(device_ctx.rr_graph.node_xlow(node->inode)) + ","; //end coordinates have smaller value
+                    end_y = std::to_string(device_ctx.rr_graph.node_ylow(node->inode)) + ")";
                 }
 
                 else {                                                                              // signal travels in increasing direction, stays at same point, or can travel both directions
-                    start_x = " (" + std::to_string(device_ctx.rr_nodes[node->inode].xlow()) + ","; //start coordinates have smaller value
-                    start_y = std::to_string(device_ctx.rr_nodes[node->inode].ylow()) + ")";
-                    end_x = "(" + std::to_string(device_ctx.rr_nodes[node->inode].xhigh()) + ","; //end coordinates have larger value
-                    end_y = std::to_string(device_ctx.rr_nodes[node->inode].yhigh()) + ")";
-                    if (device_ctx.rr_nodes[node->inode].direction() == BI_DIRECTION) {
+                    start_x = " (" + std::to_string(device_ctx.rr_graph.node_xlow(node->inode)) + ","; //start coordinates have smaller value
+                    start_y = std::to_string(device_ctx.rr_graph.node_ylow(node->inode)) + ")";
+                    end_x = "(" + std::to_string(device_ctx.rr_graph.node_xhigh(node->inode)) + ","; //end coordinates have larger value
+                    end_y = std::to_string(device_ctx.rr_graph.node_yhigh(node->inode)) + ")";
+                    if (device_ctx.rr_graph.node_direction(node->inode) == BI_DIRECTION) {
                         arrow = "<->"; //indicate that signal can travel both direction
                     }
                 }

From 6933ff51e92b13eb9aaaacbf57bef6e230a9813b Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 1 Feb 2020 22:38:21 -0700
Subject: [PATCH 084/645] net delay adopt RRGraph object, compile with no
 errors

---
 vpr/src/timing/net_delay.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/vpr/src/timing/net_delay.cpp b/vpr/src/timing/net_delay.cpp
index a2cbc73a3..1bebb173d 100644
--- a/vpr/src/timing/net_delay.cpp
+++ b/vpr/src/timing/net_delay.cpp
@@ -29,7 +29,7 @@
  * associated with that node. The map will be used to store delays while     *
  * traversing the nodes of the route tree in load_one_net_delay_recurr.      */
 
-static std::unordered_map<int, float> inode_to_Tdel_map;
+static std::unordered_map<RRNodeId, float> inode_to_Tdel_map;
 
 /*********************** Subroutines local to this module ********************/
 
@@ -107,7 +107,7 @@ static void load_one_net_delay(vtr::vector<ClusterNetId, float*>& net_delay, Clu
     }
 
     auto& cluster_ctx = g_vpr_ctx.clustering();
-    int inode;
+    RRNodeId inode;
 
     t_rt_node* rt_root = traceback_to_route_tree(net_id); // obtain the root of the tree constructed from the traceback
     load_new_subtree_R_upstream(rt_root);                 // load in the resistance values for the route tree

From 529a7ecab49a14f9cccaba4237d099fc7ca8f84f Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 3 Feb 2020 11:04:56 -0700
Subject: [PATCH 085/645] start refactor rr graph XML reader. Notice that
 rr_indexed_data builder should be signficantly reworked

---
 vpr/src/device/rr_graph_obj.h     |   7 +-
 vpr/src/route/rr_graph_reader.cpp | 148 ++++++++++++++++++------------
 2 files changed, 92 insertions(+), 63 deletions(-)

diff --git a/vpr/src/device/rr_graph_obj.h b/vpr/src/device/rr_graph_obj.h
index abafa59b6..df46df754 100644
--- a/vpr/src/device/rr_graph_obj.h
+++ b/vpr/src/device/rr_graph_obj.h
@@ -890,8 +890,11 @@ class RRGraph {
     vtr::vector<RRNodeId, std::unique_ptr<RREdgeId[]>> node_edges_;
 
     /* Edge related data */
-    size_t num_edges_;                              /* Range of edge ids */
-    std::unordered_set<RREdgeId> invalid_edge_ids_; /* Invalid edge ids */
+    /* Range of edge ids, use the unsigned long as 
+     * the number of edges could be >10 times larger than the number of nodes! 
+     */
+    unsigned long num_edges_;                         
+    std::unordered_set<RREdgeId> invalid_edge_ids_;   /* Invalid edge ids */
     vtr::vector<RREdgeId, RRNodeId> edge_src_nodes_;
     vtr::vector<RREdgeId, RRNodeId> edge_sink_nodes_;
     vtr::vector<RREdgeId, RRSwitchId> edge_switches_;
diff --git a/vpr/src/route/rr_graph_reader.cpp b/vpr/src/route/rr_graph_reader.cpp
index e9380b12d..7200786ad 100644
--- a/vpr/src/route/rr_graph_reader.cpp
+++ b/vpr/src/route/rr_graph_reader.cpp
@@ -142,7 +142,7 @@ void load_rr_file(const t_graph_type graph_type,
 
         int num_rr_nodes = count_children(next_component, "node", loc_data);
 
-        device_ctx.rr_nodes.resize(num_rr_nodes);
+        device_ctx.rr_graph.reserve_nodes(num_rr_nodes);
         process_nodes(next_component, loc_data);
 
         /* Loads edges, switches, and node look up tables*/
@@ -158,17 +158,22 @@ void load_rr_file(const t_graph_type graph_type,
 
         //Partition the rr graph edges for efficient access to configurable/non-configurable
         //edge subsets. Must be done after RR switches have been allocated
-        partition_rr_graph_edges(device_ctx);
+        device_ctx.rr_graph.rebuild_node_edges();
 
-        process_rr_node_indices(grid);
-
-        init_fan_in(device_ctx.rr_nodes, device_ctx.rr_nodes.size());
+        /* Essential check for rr_graph, build look-up */
+        if (false == device_ctx.rr_graph.validate()) {
+            /* Error out if built-in validator of rr_graph fails */
+            vpr_throw(VPR_ERROR_ROUTE,
+                      __FILE__,
+                      __LINE__,
+                      "Fundamental errors occurred when validating rr_graph object!\n");
+        }
 
         //sets the cost index and seg id information
         next_component = get_single_child(rr_graph, "rr_nodes", loc_data);
         set_cost_indices(next_component, loc_data, is_global_graph, segment_inf.size());
 
-        alloc_and_load_rr_indexed_data(segment_inf, device_ctx.rr_node_indices,
+        alloc_and_load_rr_indexed_data(segment_inf, device_ctx.rr_graph,
                                        max_chan_width, *wire_to_rr_ipin_switch, base_cost_type);
 
         process_seg_id(next_component, loc_data);
@@ -177,7 +182,14 @@ void load_rr_file(const t_graph_type graph_type,
         device_ctx.read_rr_graph_filename = std::string(read_rr_graph_name);
 
         check_rr_graph(graph_type, grid, device_ctx.physical_tile_types);
-
+        /* Error out if advanced checker of rr_graph fails */
+        if (false == check_rr_graph(device_ctx.rr_graph)) {
+            vpr_throw(VPR_ERROR_ROUTE,
+                      __FILE__,
+                      __LINE__,
+                      "Advanced checking rr_graph object fails! Routing may still work "
+                      "but not smooth\n");
+        }
     } catch (pugiutil::XmlError& e) {
         vpr_throw(VPR_ERROR_ROUTE, read_rr_graph_name, e.line(), "%s", e.what());
     }
@@ -247,6 +259,13 @@ void process_switches(pugi::xml_node parent, const pugiutil::loc_data& loc_data)
 
         Switch = Switch.next_sibling(Switch.name());
     }
+
+    /* Add the switch to RRGraph local data */
+    device_ctx.rr_graph.reserve_switches(device_ctx.rr_switch_inf.size());
+    // Create the switches
+    for (size_t iswitch = 0; iswitch < device_ctx.rr_switch_inf.size(); ++iswitch) {
+        device_ctx.rr_graph.create_switch(device_ctx.rr_switch_inf[iswitch]);
+    }
 }
 
 /*Only CHANX and CHANY components have a segment id. This function
@@ -289,41 +308,43 @@ void process_nodes(pugi::xml_node parent, const pugiutil::loc_data& loc_data) {
 
     while (rr_node) {
         int inode = get_attribute(rr_node, "id", loc_data).as_int();
-        auto& node = device_ctx.rr_nodes[inode];
+        t_rr_type node_type = NUM_RR_TYPES;
 
         const char* node_type = get_attribute(rr_node, "type", loc_data).as_string();
         if (strcmp(node_type, "CHANX") == 0) {
-            node.set_type(CHANX);
+            node_type = CHANX;
         } else if (strcmp(node_type, "CHANY") == 0) {
-            node.set_type(CHANY);
+            node_type = CHANY;
         } else if (strcmp(node_type, "SOURCE") == 0) {
-            node.set_type(SOURCE);
+            node_type = SOURCE;
         } else if (strcmp(node_type, "SINK") == 0) {
-            node.set_type(SINK);
+            node_type = SINK;
         } else if (strcmp(node_type, "OPIN") == 0) {
-            node.set_type(OPIN);
+            node_type = OPIN;
         } else if (strcmp(node_type, "IPIN") == 0) {
-            node.set_type(IPIN);
+            node_type = IPIN;
         } else {
             VPR_FATAL_ERROR(VPR_ERROR_OTHER,
                             "Valid inputs for class types are \"CHANX\", \"CHANY\",\"SOURCE\", \"SINK\",\"OPIN\", and \"IPIN\".");
         }
 
-        if (node.type() == CHANX || node.type() == CHANY) {
+        const RRNodeId& node = device_ctx.rr_graph.create_node(node_type);
+
+        if (device_ctx.rr_graph.node_type(node) == CHANX || device_ctx.rr_graph.node_type(node) == CHANY) {
             const char* correct_direction = get_attribute(rr_node, "direction", loc_data).as_string();
             if (strcmp(correct_direction, "INC_DIR") == 0) {
-                node.set_direction(INC_DIRECTION);
+                device_ctx.rr_graph.set_node_direction(node, INC_DIRECTION);
             } else if (strcmp(correct_direction, "DEC_DIR") == 0) {
-                node.set_direction(DEC_DIRECTION);
+                device_ctx.rr_graph.set_node_direction(node, DEC_DIRECTION);
             } else if (strcmp(correct_direction, "BI_DIR") == 0) {
-                node.set_direction(BI_DIRECTION);
+                device_ctx.rr_graph.set_node_direction(node, BI_DIRECTION);
             } else {
                 VTR_ASSERT((strcmp(correct_direction, "NO_DIR") == 0));
-                node.set_direction(NO_DIRECTION);
+                device_ctx.rr_graph.set_node_direction(node, NO_DIRECTION);
             }
         }
 
-        node.set_capacity(get_attribute(rr_node, "capacity", loc_data).as_float());
+        device_ctx.rr_graph.set_node_capacity(node, get_attribute(rr_node, "capacity", loc_data).as_float());
 
         //--------------
         locSubnode = get_single_child(rr_node, "loc", loc_data);
@@ -334,7 +355,7 @@ void process_nodes(pugi::xml_node parent, const pugiutil::loc_data& loc_data) {
         y1 = get_attribute(locSubnode, "ylow", loc_data).as_float();
         y2 = get_attribute(locSubnode, "yhigh", loc_data).as_float();
 
-        if (node.type() == IPIN || node.type() == OPIN) {
+        if (device_ctx.rr_graph.node_type(node) == IPIN || device_ctx.rr_graph.node_type(node) == OPIN) {
             e_side side;
             std::string side_str = get_attribute(locSubnode, "side", loc_data).as_string();
             if (side_str == "LEFT") {
@@ -347,11 +368,11 @@ void process_nodes(pugi::xml_node parent, const pugiutil::loc_data& loc_data) {
                 VTR_ASSERT(side_str == "BOTTOM");
                 side = BOTTOM;
             }
-            node.set_side(side);
+            device_ctx.rr_graph.set_node_side(node, side);
         }
 
-        node.set_coordinates(x1, y1, x2, y2);
-        node.set_ptc_num(get_attribute(locSubnode, "ptc", loc_data).as_int());
+        device_ctx.rr_graph.set_node_bouding_box(node, vtr::Rect<short>(x1, y1, x2, y2)); 
+        device_ctx.rr_graph.set_node_ptc_num(node, get_attribute(locSubnode, "ptc", loc_data).as_int());
 
         //-------
         timingSubnode = get_single_child(rr_node, "timing", loc_data, pugiutil::OPTIONAL);
@@ -362,10 +383,7 @@ void process_nodes(pugi::xml_node parent, const pugiutil::loc_data& loc_data) {
             R = get_attribute(timingSubnode, "R", loc_data).as_float();
             C = get_attribute(timingSubnode, "C", loc_data).as_float();
         }
-        node.set_rc_index(find_create_rr_rc_data(R, C));
-
-        //clear each node edge
-        node.set_num_edges(0);
+        device_ctx.rr_graph.set_node_rc_data_index(node, find_create_rr_rc_data(R, C));
 
         //  <metadata>
         //    <meta name='grid_prefix' >CLBLL_L_</meta>
@@ -394,32 +412,42 @@ void process_edges(pugi::xml_node parent, const pugiutil::loc_data& loc_data, in
 
     edges = get_first_child(parent, "edge", loc_data);
     //count the number of edges and store it in a vector
-    std::vector<size_t> num_edges_for_node;
-    num_edges_for_node.resize(device_ctx.rr_nodes.size(), 0);
+    vtr::vector<RRNodeId, size_t> num_edges_for_node;
+    num_edges_for_node.resize(device_ctx.rr_graph.nodes().size(), 0);
+
+    unsigned long num_edges_to_reserve = 0;
 
     while (edges) {
-        size_t source_node = get_attribute(edges, "src_node", loc_data).as_uint();
-        if (source_node >= device_ctx.rr_nodes.size()) {
+        RRNodeId source_node = RRNodeId(get_attribute(edges, "src_node", loc_data).as_uint());
+        if (false == device_ctx.rr_graph.valid_node_id(source_node)) {
             VPR_FATAL_ERROR(VPR_ERROR_OTHER,
                             "source_node %d is larger than rr_nodes.size() %d",
-                            source_node, device_ctx.rr_nodes.size());
+                            size_t(source_node), device_ctx.rr_graph.nodes().size());
         }
 
         num_edges_for_node[source_node]++;
+        num_edges_to_reserve++;
         edges = edges.next_sibling(edges.name());
     }
 
     //reset this vector in order to start count for num edges again
-    for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); inode++) {
-        if (num_edges_for_node[inode] > std::numeric_limits<t_edge_size>::max()) {
+    for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) {
+        /* uint16_t is the data type for each type of edges in RRGraph object 
+         * Multiplied by 4 is due to the fact that each node has 4 groups of edges
+         * and each group is bounded by uint16_t
+         * See rr_graph_obj.h for more details
+         */
+        if (num_edges_for_node[inode] > 4 * std::numeric_limits<uint16_t>::max()) {
             VPR_FATAL_ERROR(VPR_ERROR_OTHER,
                             "source node %d edge count %d is too high",
-                            inode, num_edges_for_node[inode]);
+                            size_t(inode), num_edges_for_node[inode]);
         }
-        device_ctx.rr_nodes[inode].set_num_edges(num_edges_for_node[inode]);
         num_edges_for_node[inode] = 0;
     }
 
+    /* Reserve the memory for edges */
+    device_ctx.rr_graph.reserve_edges(num_edges_to_reserve);
+
     edges = get_first_child(parent, "edge", loc_data);
     /*initialize a vector that keeps track of the number of wire to ipin switches
      * There should be only one wire to ipin switch. In case there are more, make sure to
@@ -430,14 +458,14 @@ void process_edges(pugi::xml_node parent, const pugiutil::loc_data& loc_data, in
     std::pair<int, int> most_frequent_switch(-1, 0);
 
     while (edges) {
-        size_t source_node = get_attribute(edges, "src_node", loc_data).as_uint();
-        size_t sink_node = get_attribute(edges, "sink_node", loc_data).as_uint();
+        RRNodeId source_node = RRNodeId(get_attribute(edges, "src_node", loc_data).as_uint());
+        RRNodeId sink_node = RRNodeId(get_attribute(edges, "sink_node", loc_data).as_uint());
         int switch_id = get_attribute(edges, "switch_id", loc_data).as_int();
 
-        if (sink_node >= device_ctx.rr_nodes.size()) {
+        if (false == device_ctx.rr_graph.valid_node_id(sink_node)) {
             VPR_FATAL_ERROR(VPR_ERROR_OTHER,
                             "sink_node %d is larger than rr_nodes.size() %d",
-                            sink_node, device_ctx.rr_nodes.size());
+                            size_t(sink_node), device_ctx.rr_graph.nodes().size());
         }
 
         if (switch_id >= num_rr_switches) {
@@ -448,8 +476,8 @@ void process_edges(pugi::xml_node parent, const pugiutil::loc_data& loc_data, in
 
         /*Keeps track of the number of the specific type of switch that connects a wire to an ipin
          * use the pair data structure to keep the maximum*/
-        if (device_ctx.rr_nodes[source_node].type() == CHANX || device_ctx.rr_nodes[source_node].type() == CHANY) {
-            if (device_ctx.rr_nodes[sink_node].type() == IPIN) {
+        if (device_ctx.rr_graph.node_type(source_node) == CHANX || device_ctx.rr_graph.node_type(source_node) == CHANY) {
+            if (device_ctx.rr_graph.node_type(sink_node) == IPIN) {
                 count_for_wire_to_ipin_switches[switch_id]++;
                 if (count_for_wire_to_ipin_switches[switch_id] > most_frequent_switch.second) {
                     most_frequent_switch.first = switch_id;
@@ -458,8 +486,7 @@ void process_edges(pugi::xml_node parent, const pugiutil::loc_data& loc_data, in
             }
         }
         //set edge in correct rr_node data structure
-        device_ctx.rr_nodes[source_node].set_edge_sink_node(num_edges_for_node[source_node], sink_node);
-        device_ctx.rr_nodes[source_node].set_edge_switch(num_edges_for_node[source_node], switch_id);
+        device_ctx.rr_graph.create_edge(source_node, sink_node, RRSwitchId(switch_id));
 
         // Read the metadata for the edge
         auto metadata = get_single_child(edges, "metadata", loc_data, pugiutil::OPTIONAL);
@@ -842,15 +869,15 @@ void set_cost_indices(pugi::xml_node parent, const pugiutil::loc_data& loc_data,
     auto& device_ctx = g_vpr_ctx.mutable_device();
 
     //set the cost index in order to load the segment information, rr nodes should be set already
-    for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); inode++) {
-        if (device_ctx.rr_nodes[inode].type() == SOURCE) {
-            device_ctx.rr_nodes[inode].set_cost_index(SOURCE_COST_INDEX);
-        } else if (device_ctx.rr_nodes[inode].type() == SINK) {
-            device_ctx.rr_nodes[inode].set_cost_index(SINK_COST_INDEX);
-        } else if (device_ctx.rr_nodes[inode].type() == IPIN) {
-            device_ctx.rr_nodes[inode].set_cost_index(IPIN_COST_INDEX);
-        } else if (device_ctx.rr_nodes[inode].type() == OPIN) {
-            device_ctx.rr_nodes[inode].set_cost_index(OPIN_COST_INDEX);
+    for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) {
+        if (device_ctx.rr_graph.node_type(inode) == SOURCE) {
+            device_ctx.rr_graph.set_node_cost_index(inode, SOURCE_COST_INDEX);
+        } else if (device_ctx.rr_graph.node_type(inode) == SINK) {
+            device_ctx.rr_graph.set_node_cost_index(inode, SINK_COST_INDEX);
+        } else if (device_ctx.rr_graph.node_type(inode) == IPIN) {
+            device_ctx.rr_graph.set_node_cost_index(inode, IPIN_COST_INDEX);
+        } else if (device_ctx.rr_graph.node_type(inode) == OPIN) {
+            device_ctx.rr_graph.set_node_cost_index(inode, OPIN_COST_INDEX);
         }
     }
 
@@ -862,8 +889,7 @@ void set_cost_indices(pugi::xml_node parent, const pugiutil::loc_data& loc_data,
     rr_node = get_first_child(parent, "node", loc_data);
 
     while (rr_node) {
-        int inode = get_attribute(rr_node, "id", loc_data).as_int();
-        auto& node = device_ctx.rr_nodes[inode];
+        RRNodeId inode = RRNodeId(get_attribute(rr_node, "id", loc_data).as_int());
 
         /*CHANX and CHANY cost index is dependent on the segment id*/
 
@@ -873,11 +899,11 @@ void set_cost_indices(pugi::xml_node parent, const pugiutil::loc_data& loc_data,
             if (attribute) {
                 int seg_id = get_attribute(segmentSubnode, "segment_id", loc_data).as_int(0);
                 if (is_global_graph) {
-                    node.set_cost_index(0);
-                } else if (node.type() == CHANX) {
-                    node.set_cost_index(CHANX_COST_INDEX_START + seg_id);
-                } else if (node.type() == CHANY) {
-                    node.set_cost_index(CHANX_COST_INDEX_START + num_seg_types + seg_id);
+                    device_ctx.rr_graph.set_node_cost_index(0);
+                } else if (device_ctx.rr_graph.node_type(inode) == CHANX) {
+                    device_ctx.rr_graph.set_node_cost_index(inode, CHANX_COST_INDEX_START + seg_id);
+                } else if (device_ctx.rr_graph.node_type(inode) == CHANY) {
+                    device_ctx.rr_graph.set_node_cost_index(inode, CHANX_COST_INDEX_START + num_seg_types + seg_id);
                 }
             }
         }

From 9df76769508457bb372a603c57d1cd3aff73866e Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 3 Feb 2020 11:25:05 -0700
Subject: [PATCH 086/645] refactored rr_graph indexed data builder

---
 vpr/src/route/rr_graph2.cpp             | 34 +++++++-------
 vpr/src/route/rr_graph2.h               | 10 ++---
 vpr/src/route/rr_graph_indexed_data.cpp | 59 +++++++++++++------------
 vpr/src/route/rr_graph_indexed_data.h   |  3 +-
 4 files changed, 54 insertions(+), 52 deletions(-)

diff --git a/vpr/src/route/rr_graph2.cpp b/vpr/src/route/rr_graph2.cpp
index 556a87922..2b7ddb4da 100644
--- a/vpr/src/route/rr_graph2.cpp
+++ b/vpr/src/route/rr_graph2.cpp
@@ -1343,29 +1343,29 @@ int get_rr_node_index(const t_rr_node_indices& L_rr_node_indices,
     return ((unsigned)ptc < lookup.size() ? lookup[ptc] : -1);
 }
 
-int find_average_rr_node_index(int device_width,
-                               int device_height,
-                               t_rr_type rr_type,
-                               int ptc,
-                               const t_rr_node_indices& L_rr_node_indices) {
+RRNodeId find_average_rr_node_index(int device_width,
+                                    int device_height,
+                                    t_rr_type rr_type,
+                                    int ptc,
+                                    const RRGraph& rr_graph) {
     /* Find and return the index to a rr_node that is located at the "center" *
      * of the current grid array, if possible.  In the event the "center" of  *
      * the grid array is an EMPTY or IO node, then retry alterate locations.  *
      * Worst case, this function will simply return the 1st non-EMPTY and     *
      * non-IO node.                                                           */
 
-    int inode = get_rr_node_index(L_rr_node_indices, (device_width) / 2, (device_height) / 2,
-                                  rr_type, ptc);
+    RRNodeId inode = rr_graph.find_node((device_width) / 2, (device_height) / 2,
+                                        rr_type, ptc);
 
-    if (inode == OPEN) {
-        inode = get_rr_node_index(L_rr_node_indices, (device_width) / 4, (device_height) / 4,
-                                  rr_type, ptc);
+    if (inode == RRNodeId::INVALID()) {
+        inode = rr_graph.find_node((device_width) / 4, (device_height) / 4,
+                                   rr_type, ptc);
     }
-    if (inode == OPEN) {
-        inode = get_rr_node_index(L_rr_node_indices, (device_width) / 4 * 3, (device_height) / 4 * 3,
-                                  rr_type, ptc);
+    if (inode == RRNodeId::INVALID()) {
+        inode = rr_graph.find_node((device_width) / 4 * 3, (device_height) / 4 * 3,
+                                   rr_type, ptc);
     }
-    if (inode == OPEN) {
+    if (inode == RRNodeId::INVALID()) {
         auto& device_ctx = g_vpr_ctx.device();
 
         for (int x = 0; x < device_width; ++x) {
@@ -1375,11 +1375,11 @@ int find_average_rr_node_index(int device_width,
                 if (is_io_type(device_ctx.grid[x][y].type))
                     continue;
 
-                inode = get_rr_node_index(L_rr_node_indices, x, y, rr_type, ptc);
-                if (inode != OPEN)
+                inode = rr_graph.find_node(x, y, rr_type, ptc);
+                if (inode != RRNodeId::INVALID())
                     break;
             }
-            if (inode != OPEN)
+            if (inode != RRNodeId::INVALID())
                 break;
         }
     }
diff --git a/vpr/src/route/rr_graph2.h b/vpr/src/route/rr_graph2.h
index 617730a0d..dae44608c 100644
--- a/vpr/src/route/rr_graph2.h
+++ b/vpr/src/route/rr_graph2.h
@@ -73,11 +73,11 @@ int get_rr_node_index(const t_rr_node_indices& L_rr_node_indices,
                       int ptc,
                       e_side side = NUM_SIDES);
 
-int find_average_rr_node_index(int device_width,
-                               int device_height,
-                               t_rr_type rr_type,
-                               int ptc,
-                               const t_rr_node_indices& L_rr_node_indices);
+RRNodeId find_average_rr_node_index(int device_width,
+                                    int device_height,
+                                    t_rr_type rr_type,
+                                    int ptc,
+                                    const RRGraph& rr_graph);
 
 t_seg_details* alloc_and_load_seg_details(int* max_chan_width,
                                           const int max_len,
diff --git a/vpr/src/route/rr_graph_indexed_data.cpp b/vpr/src/route/rr_graph_indexed_data.cpp
index 0d8fc8532..bc73a1511 100644
--- a/vpr/src/route/rr_graph_indexed_data.cpp
+++ b/vpr/src/route/rr_graph_indexed_data.cpp
@@ -16,17 +16,17 @@
 /******************* Subroutines local to this module ************************/
 
 static void load_rr_indexed_data_base_costs(int nodes_per_chan,
-                                            const t_rr_node_indices& L_rr_node_indices,
+                                            const RRGraph& rr_graph,
                                             enum e_base_cost_type base_cost_type);
 
 static float get_delay_normalization_fac(int nodes_per_chan,
-                                         const t_rr_node_indices& L_rr_node_indices);
+                                         const RRGraph& rr_graph);
 
 static void load_rr_indexed_data_T_values(int index_start,
                                           int num_indices_to_load,
                                           t_rr_type rr_type,
                                           int nodes_per_chan,
-                                          const t_rr_node_indices& L_rr_node_indices);
+                                          const RRGraph& rr_graph);
 
 static void fixup_rr_indexed_data_T_values(size_t num_segment);
 
@@ -48,7 +48,7 @@ static std::vector<size_t> count_rr_segment_types();
  * x-channel its own cost_index, and each segment type in a y-channel its    *
  * own cost_index.                                                           */
 void alloc_and_load_rr_indexed_data(const std::vector<t_segment_inf>& segment_inf,
-                                    const t_rr_node_indices& L_rr_node_indices,
+                                    const RRGraph& rr_graph,
                                     const int nodes_per_chan,
                                     int wire_to_ipin_switch,
                                     enum e_base_cost_type base_cost_type) {
@@ -93,7 +93,7 @@ void alloc_and_load_rr_indexed_data(const std::vector<t_segment_inf>& segment_in
         device_ctx.rr_indexed_data[index].seg_index = iseg;
     }
     load_rr_indexed_data_T_values(CHANX_COST_INDEX_START, num_segment, CHANX,
-                                  nodes_per_chan, L_rr_node_indices);
+                                  nodes_per_chan, rr_graph);
 
     /* Y-directed segments. */
     for (iseg = 0; iseg < num_segment; iseg++) {
@@ -114,11 +114,11 @@ void alloc_and_load_rr_indexed_data(const std::vector<t_segment_inf>& segment_in
         device_ctx.rr_indexed_data[index].seg_index = iseg;
     }
     load_rr_indexed_data_T_values((CHANX_COST_INDEX_START + num_segment),
-                                  num_segment, CHANY, nodes_per_chan, L_rr_node_indices);
+                                  num_segment, CHANY, nodes_per_chan, rr_graph);
 
     fixup_rr_indexed_data_T_values(num_segment);
 
-    load_rr_indexed_data_base_costs(nodes_per_chan, L_rr_node_indices,
+    load_rr_indexed_data_base_costs(nodes_per_chan, rr_graph,
                                     base_cost_type);
 }
 
@@ -143,7 +143,7 @@ void load_rr_index_segments(const int num_segment) {
 }
 
 static void load_rr_indexed_data_base_costs(int nodes_per_chan,
-                                            const t_rr_node_indices& L_rr_node_indices,
+                                            const RRGraph& rr_graph,
                                             enum e_base_cost_type base_cost_type) {
     /* Loads the base_cost member of device_ctx.rr_indexed_data according to the specified *
      * base_cost_type.                                                          */
@@ -156,7 +156,7 @@ static void load_rr_indexed_data_base_costs(int nodes_per_chan,
     if (base_cost_type == DEMAND_ONLY || base_cost_type == DEMAND_ONLY_NORMALIZED_LENGTH) {
         delay_normalization_fac = 1.;
     } else {
-        delay_normalization_fac = get_delay_normalization_fac(nodes_per_chan, L_rr_node_indices);
+        delay_normalization_fac = get_delay_normalization_fac(nodes_per_chan, rr_graph);
     }
 
     device_ctx.rr_indexed_data[SOURCE_COST_INDEX].base_cost = delay_normalization_fac;
@@ -240,12 +240,13 @@ static std::vector<size_t> count_rr_segment_types() {
 }
 
 static float get_delay_normalization_fac(int nodes_per_chan,
-                                         const t_rr_node_indices& L_rr_node_indices) {
+                                         const RRGraph& rr_graph) {
     /* Returns the average delay to go 1 CLB distance along a wire.  */
 
     const int clb_dist = 3; /* Number of CLBs I think the average conn. goes. */
 
-    int inode, itrack, cost_index;
+    RRNodeId inode;
+    int itrack, cost_index;
     float Tdel, Tdel_sum, frac_num_seg;
 
     auto& device_ctx = g_vpr_ctx.device();
@@ -254,10 +255,10 @@ static float get_delay_normalization_fac(int nodes_per_chan,
 
     for (itrack = 0; itrack < nodes_per_chan; itrack++) {
         inode = find_average_rr_node_index(device_ctx.grid.width(), device_ctx.grid.height(), CHANX, itrack,
-                                           L_rr_node_indices);
-        if (inode == -1)
+                                           rr_graph);
+        if (inode == RRNodeId::INVALID())
             continue;
-        cost_index = device_ctx.rr_nodes[inode].cost_index();
+        cost_index = device_ctx.rr_graph.node_cost_index(inode);
         frac_num_seg = clb_dist * device_ctx.rr_indexed_data[cost_index].inv_length;
         Tdel = frac_num_seg * device_ctx.rr_indexed_data[cost_index].T_linear
                + frac_num_seg * frac_num_seg
@@ -267,10 +268,10 @@ static float get_delay_normalization_fac(int nodes_per_chan,
 
     for (itrack = 0; itrack < nodes_per_chan; itrack++) {
         inode = find_average_rr_node_index(device_ctx.grid.width(), device_ctx.grid.height(), CHANY, itrack,
-                                           L_rr_node_indices);
-        if (inode == -1)
+                                           rr_graph);
+        if (inode == RRNodeId::INVALID())
             continue;
-        cost_index = device_ctx.rr_nodes[inode].cost_index();
+        cost_index = device_ctx.rr_graph.node_cost_index(inode);
         frac_num_seg = clb_dist * device_ctx.rr_indexed_data[cost_index].inv_length;
         Tdel = frac_num_seg * device_ctx.rr_indexed_data[cost_index].T_linear
                + frac_num_seg * frac_num_seg
@@ -285,7 +286,7 @@ static void load_rr_indexed_data_T_values(int index_start,
                                           int num_indices_to_load,
                                           t_rr_type rr_type,
                                           int nodes_per_chan,
-                                          const t_rr_node_indices& L_rr_node_indices) {
+                                          const RRGraph& rr_graph) {
     /* Loads the average propagation times through segments of each index type   *
      * for either all CHANX segment types or all CHANY segment types.  It does   *
      * this by looking at all the segments in one channel in the middle of the   *
@@ -293,7 +294,8 @@ static void load_rr_indexed_data_T_values(int index_start,
      * same type and using them to compute average delay values for this type of *
      * segment. */
 
-    int itrack, inode, cost_index;
+    int itrack, cost_index;
+    RRNodeId inode;
     float *C_total, *R_total;                                         /* [0..device_ctx.rr_indexed_data.size() - 1] */
     double *switch_R_total, *switch_T_total, *switch_Cinternal_total; /* [0..device_ctx.rr_indexed_data.size() - 1] */
     short* switches_buffered;
@@ -327,26 +329,25 @@ static void load_rr_indexed_data_T_values(int index_start,
 
     for (itrack = 0; itrack < nodes_per_chan; itrack++) {
         inode = find_average_rr_node_index(device_ctx.grid.width(), device_ctx.grid.height(), rr_type, itrack,
-                                           L_rr_node_indices);
-        if (inode == -1)
+                                           rr_graph);
+        if (inode == RRNodeId::INVALID())
             continue;
-        cost_index = device_ctx.rr_nodes[inode].cost_index();
+        cost_index = rr_graph.node_cost_index(inode);
         num_nodes_of_index[cost_index]++;
-        C_total[cost_index] += device_ctx.rr_nodes[inode].C();
-        R_total[cost_index] += device_ctx.rr_nodes[inode].R();
+        C_total[cost_index] += rr_graph.node_C(inode);
+        R_total[cost_index] += rr_graph.node_R(inode);
 
         /* get average switch parameters */
-        int num_edges = device_ctx.rr_nodes[inode].num_edges();
         double avg_switch_R = 0;
         double avg_switch_T = 0;
         double avg_switch_Cinternal = 0;
         int num_switches = 0;
         short buffered = UNDEFINED;
-        for (int iedge = 0; iedge < num_edges; iedge++) {
-            int to_node_index = device_ctx.rr_nodes[inode].edge_sink_node(iedge);
+        for (const RREdgeId& iedge : rr_graph.node_out_edges(inode)) {
+            RRNodeId to_node_index = device_ctx.rr_graph.edge_sink_node(iedge);
             /* want to get C/R/Tdel/Cinternal of switches that connect this track segment to other track segments */
-            if (device_ctx.rr_nodes[to_node_index].type() == CHANX || device_ctx.rr_nodes[to_node_index].type() == CHANY) {
-                int switch_index = device_ctx.rr_nodes[inode].edge_switch(iedge);
+            if (device_ctx.rr_graph.node_type(to_node_index) == CHANX || device_ctx.rr_graph.node_type(to_node_index) == CHANY) {
+                int switch_index = device_ctx.rr_graph.edge_switch(iedge);
                 avg_switch_R += device_ctx.rr_switch_inf[switch_index].R;
                 avg_switch_T += device_ctx.rr_switch_inf[switch_index].Tdel;
                 avg_switch_Cinternal += device_ctx.rr_switch_inf[switch_index].Cinternal;
diff --git a/vpr/src/route/rr_graph_indexed_data.h b/vpr/src/route/rr_graph_indexed_data.h
index 4e5f8e051..fe2a2a141 100644
--- a/vpr/src/route/rr_graph_indexed_data.h
+++ b/vpr/src/route/rr_graph_indexed_data.h
@@ -1,9 +1,10 @@
 #ifndef RR_GRAPH_INDEXED_DATA_H
 #define RR_GRAPH_INDEXED_DATA_H
 #include "physical_types.h"
+#include "rr_graph_obj.h"
 
 void alloc_and_load_rr_indexed_data(const std::vector<t_segment_inf>& segment_inf,
-                                    const t_rr_node_indices& L_rr_node_indices,
+                                    const RRGraph& rr_graph,
                                     int nodes_per_chan,
                                     int wire_to_ipin_switch,
                                     enum e_base_cost_type base_cost_type);

From 4fb6d7e3aeb8207aab968453253689940eb55770 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 3 Feb 2020 13:21:48 -0700
Subject: [PATCH 087/645] halfway in refactoring the rr_graph builder

---
 vpr/src/route/rr_graph.cpp  | 319 +++++++++++++++++++-----------------
 vpr/src/route/rr_graph2.cpp |  80 ++++-----
 vpr/src/route/rr_graph2.h   |  22 +--
 3 files changed, 221 insertions(+), 200 deletions(-)

diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp
index d9c387cd2..5ff1f9f35 100644
--- a/vpr/src/route/rr_graph.cpp
+++ b/vpr/src/route/rr_graph.cpp
@@ -108,7 +108,7 @@ static void build_bidir_rr_opins(const int i,
                                  const int j,
                                  const e_side side,
                                  const t_rr_node_indices& L_rr_node_indices,
-                                 const std::vector<t_rr_node>& rr_nodes,
+                                 const RRGraph& rr_nodes,
                                  const t_pin_to_track_lookup& opin_to_track_map,
                                  const std::vector<vtr::Matrix<int>>& Fc_out,
                                  t_rr_edge_info_set& created_rr_edges,
@@ -139,20 +139,20 @@ static void build_unidir_rr_opins(const int i,
                                   const t_clb_to_clb_directs* clb_to_clb_directs,
                                   const int num_seg_types);
 
-static int get_opin_direct_connecions(int x,
-                                      int y,
-                                      e_side side,
-                                      int opin,
-                                      int from_rr_node,
-                                      t_rr_edge_info_set& rr_edges_to_create,
-                                      const t_rr_node_indices& L_rr_node_indices,
-                                      const std::vector<t_rr_node>& rr_nodes,
-                                      const t_direct_inf* directs,
-                                      const int num_directs,
-                                      const t_clb_to_clb_directs* clb_to_clb_directs);
+static int get_opin_direct_connections(int x,
+                                       int y,
+                                       e_side side,
+                                       int opin,
+                                       const RRNodeId& from_rr_node,
+                                       t_rr_edge_info_set& rr_edges_to_create,
+                                       const t_rr_node_indices& L_rr_node_indices,
+                                       const RRGraph& rr_nodes,
+                                       const t_direct_inf* directs,
+                                       const int num_directs,
+                                       const t_clb_to_clb_directs* clb_to_clb_directs);
 
 static void alloc_and_load_rr_graph(const int num_nodes,
-                                    std::vector<t_rr_node>& L_rr_node,
+                                    RRGraph& rr_graph,
                                     const int num_seg_types,
                                     const t_chan_details& chan_details_x,
                                     const t_chan_details& chan_details_y,
@@ -212,7 +212,7 @@ static std::vector<std::vector<bool>> alloc_and_load_perturb_ipins(const int L_n
 
 static void build_rr_sinks_sources(const int i,
                                    const int j,
-                                   std::vector<t_rr_node>& L_rr_node,
+                                   RRGraph& rr_graph,
                                    t_rr_edge_info_set& rr_edges_to_create,
                                    const t_rr_node_indices& L_rr_node_indices,
                                    const int delayless_switch,
@@ -234,13 +234,13 @@ static void build_rr_chan(const int i,
                           const t_chan_details& chan_details_y,
                           const t_rr_node_indices& L_rr_node_indices,
                           t_rr_edge_info_set& created_rr_edges,
-                          std::vector<t_rr_node>& L_rr_node,
+                          RRGraph& rr_graph,
                           const int wire_to_ipin_switch,
                           const enum e_directionality directionality);
 
 void uniquify_edges(t_rr_edge_info_set& rr_edges_to_create);
 
-void alloc_and_load_edges(std::vector<t_rr_node>& L_rr_node,
+void alloc_and_load_edges(RRGraph& rr_graph,
                           const t_rr_edge_info_set& rr_edges_to_create);
 
 static void alloc_and_load_rr_switch_inf(const int num_arch_switches,
@@ -278,9 +278,9 @@ static std::vector<vtr::Matrix<int>> alloc_and_load_actual_fc(const std::vector<
                                                               const enum e_directionality directionality,
                                                               bool* Fc_clipped);
 
-static int pick_best_direct_connect_target_rr_node(const std::vector<t_rr_node>& rr_nodes,
-                                                   int from_rr,
-                                                   const std::vector<int>& candidate_rr_nodes);
+static RRNodeId pick_best_direct_connect_target_rr_node(const RRGraph& rr_graph,
+                                                        const RRNodeId& from_rr,
+                                                        const std::vector<RRNodeId>& candidate_rr_nodes);
 
 static void process_non_config_sets();
 
@@ -336,7 +336,7 @@ void create_rr_graph(const t_graph_type graph_type,
                          det_routing_arch->read_rr_graph_filename.c_str());
 
             /* Xifan Tang - Create rr_graph object: load rr_nodes to the object */
-            convert_rr_graph(segment_inf);
+            //convert_rr_graph(segment_inf);
         }
     } else {
         if (channel_widths_unchanged(device_ctx.chan_width, nodes_per_chan) && !device_ctx.rr_nodes.empty()) {
@@ -591,9 +591,13 @@ static void build_rr_graph(const t_graph_type graph_type,
     /* Alloc node lookups, count nodes, alloc rr nodes */
     int num_rr_nodes = 0;
 
+    /* Xifan Tang - Keep the node indices here since it counts the number of rr_nodes 
+     * We will simplify this function as indices will be built inside the RRGraph object
+     */
     device_ctx.rr_node_indices = alloc_and_load_rr_node_indices(max_chan_width, grid,
                                                                 &num_rr_nodes, chan_details_x, chan_details_y);
-    device_ctx.rr_nodes.resize(num_rr_nodes);
+    /* Reserve the node for the RRGraph object */
+    device_ctx.rr_graph.reserve_node(num_rr_nodes);
 
     /* These are data structures used by the the unidir opin mapping. They are used
      * to spread connections evenly for each segment type among the available
@@ -692,7 +696,7 @@ static void build_rr_graph(const t_graph_type graph_type,
     /* END OPIN MAP */
 
     bool Fc_clipped = false;
-    alloc_and_load_rr_graph(device_ctx.rr_nodes.size(), device_ctx.rr_nodes, segment_inf.size(),
+    alloc_and_load_rr_graph(device_ctx.rr_graph.nodes().size(), device_ctx.rr_graph, segment_inf.size(),
                             chan_details_x, chan_details_y,
                             track_to_pin_lookup, opin_to_track_map,
                             switch_block_conn, sb_conn_map, grid, Fs, unidir_sb_pattern,
@@ -708,14 +712,14 @@ static void build_rr_graph(const t_graph_type graph_type,
 
     /* Update rr_nodes capacities if global routing */
     if (graph_type == GRAPH_GLOBAL) {
-        for (size_t i = 0; i < device_ctx.rr_nodes.size(); i++) {
-            if (device_ctx.rr_nodes[i].type() == CHANX) {
-                int ylow = device_ctx.rr_nodes[i].ylow();
-                device_ctx.rr_nodes[i].set_capacity(nodes_per_chan.x_list[ylow]);
+        for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) {
+            if (device_ctx.rr_graph.node_type(inode) == CHANX) {
+                int ylow = device_ctx.rr_graph.node_ylow(inode);
+                device_ctx.rr_graph.set_node_capacity(inode, nodes_per_chan.x_list[ylow]);
             }
-            if (device_ctx.rr_nodes[i].type() == CHANY) {
-                int xlow = device_ctx.rr_nodes[i].xlow();
-                device_ctx.rr_nodes[i].set_capacity(nodes_per_chan.y_list[xlow]);
+            if (device_ctx.rr_graph.node_type(inode) == CHANY) {
+                int xlow = device_ctx.rr_graph.node_xlow(inode);
+                device_ctx.rr_graph.set_node_capacity(inode, nodes_per_chan.y_list[xlow]);
             }
         }
     }
@@ -726,7 +730,16 @@ static void build_rr_graph(const t_graph_type graph_type,
 
     //Partition the rr graph edges for efficient access to configurable/non-configurable
     //edge subsets. Must be done after RR switches have been allocated
-    partition_rr_graph_edges(device_ctx);
+    device_ctx.rr_graph.rebuild_node_edges();
+
+    /* Essential check for rr_graph, build look-up and  */
+    if (false == device_ctx.rr_graph.validate()) {
+        /* Error out if built-in validator of rr_graph fails */
+        vpr_throw(VPR_ERROR_ROUTE,
+                  __FILE__,
+                  __LINE__,
+                  "Fundamental errors occurred when validating rr_graph object!\n");
+    }
 
     //Save the channel widths for the newly constructed graph
     device_ctx.chan_width = nodes_per_chan;
@@ -735,6 +748,14 @@ static void build_rr_graph(const t_graph_type graph_type,
                        *wire_to_rr_ipin_switch, base_cost_type);
 
     check_rr_graph(graph_type, grid, types);
+    /* Error out if advanced checker of rr_graph fails */
+    if (false == check_rr_graph(device_ctx.rr_graph)) {
+        vpr_throw(VPR_ERROR_ROUTE,
+                  __FILE__,
+                  __LINE__,
+                  "Advanced checking rr_graph object fails! Routing may still work "
+                  "but not smooth\n");
+    }
 
     /* Free all temp structs */
     if (seg_details) {
@@ -829,11 +850,11 @@ static void alloc_rr_switch_inf(t_arch_switch_fanin& arch_switch_fanins) {
         //
         //Note that since we don't store backward edge info in the RR graph we need to walk
         //the whole graph to get the per-switch-type fanin info
-        std::vector<vtr::flat_map<int, int>> inward_switch_inf(device_ctx.rr_nodes.size()); //[to_node][arch_switch] -> fanin
-        for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); ++inode) {
-            for (auto iedge : device_ctx.rr_nodes[inode].edges()) {
-                int iswitch = device_ctx.rr_nodes[inode].edge_switch(iedge);
-                int to_node = device_ctx.rr_nodes[inode].edge_sink_node(iedge);
+        std::vector<vtr::flat_map<RRNodeId, int>> inward_switch_inf(device_ctx.rr_graph.nodes().size()); //[to_node][arch_switch] -> fanin
+        for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) {
+            for (const RREdgeId& iedge : device_ctx.rr_graph.node_out_edges(inode)) {
+                int iswitch = device_ctx.rr_graph.edge_switch(iedge);
+                const RRNodeId& to_node = device_ctx.rr_graph.edge_sink_node(iedge);
 
                 if (inward_switch_inf[to_node].count(iswitch) == 0) {
                     inward_switch_inf[to_node][iswitch] = 0;
@@ -843,7 +864,7 @@ static void alloc_rr_switch_inf(t_arch_switch_fanin& arch_switch_fanins) {
         }
 
         //Record the unique switch type/fanin combinations
-        for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); ++inode) {
+        for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) {
             for (auto& switch_fanin : inward_switch_inf[inode]) {
                 int iswitch, fanin;
                 std::tie(iswitch, fanin) = switch_fanin;
@@ -891,6 +912,14 @@ static void load_rr_switch_inf(const int num_arch_switches, const float R_minW_n
             load_rr_switch_from_arch_switch(i_arch_switch, i_rr_switch, fanin, R_minW_nmos, R_minW_pmos);
         }
     }
+  
+    /* Create switches as internal data of RRGraph object */
+    device_ctx.rr_graph.reserve_switches(device_ctx.rr_switch_inf.size());
+    // Create the switches
+    for (size_t iswitch = 0; iswitch < device_ctx.rr_switch_inf.size(); ++iswitch) {
+        device_ctx.rr_graph.create_switch(device_ctx.rr_switch_inf[iswitch]);
+    }
+
 }
 
 void load_rr_switch_from_arch_switch(int arch_switch_idx,
@@ -931,14 +960,13 @@ void load_rr_switch_from_arch_switch(int arch_switch_idx,
 static void remap_rr_node_switch_indices(const t_arch_switch_fanin& switch_fanin) {
     auto& device_ctx = g_vpr_ctx.mutable_device();
 
-    for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); inode++) {
-        auto& from_node = device_ctx.rr_nodes[inode];
-        int num_edges = from_node.num_edges();
-        for (int iedge = 0; iedge < num_edges; iedge++) {
-            const t_rr_node& to_node = device_ctx.rr_nodes[from_node.edge_sink_node(iedge)];
+    for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) {
+        const RRNodeId& from_node = inode;
+        for (const RREdgeId& iedge : device_ctx.rr_graph.node_out_edges(from_node)) {
+            const RRNodeId& to_node = device_ctx.rr_graph.edge_sink_node(iedge);
             /* get the switch which this edge uses and its fanin */
-            int switch_index = from_node.edge_switch(iedge);
-            int fanin = to_node.fan_in();
+            int switch_index = device_ctx.rr_graph.edge_switch(iedge);
+            int fanin = device_ctx.rr_graph.node_in_edges(to_node).size();
 
             if (switch_fanin[switch_index].count(UNDEFINED) == 1) {
                 fanin = UNDEFINED;
@@ -949,7 +977,7 @@ static void remap_rr_node_switch_indices(const t_arch_switch_fanin& switch_fanin
 
             int rr_switch_index = itr->second;
 
-            from_node.set_edge_switch(iedge, rr_switch_index);
+            device_ctx.rr_graph.set_edge_switch(iedge, rr_switch_index);
         }
     }
 }
@@ -961,7 +989,7 @@ static void rr_graph_externals(const std::vector<t_segment_inf>& segment_inf,
     auto& device_ctx = g_vpr_ctx.device();
 
     add_rr_graph_C_from_switches(device_ctx.rr_switch_inf[wire_to_rr_ipin_switch].Cin);
-    alloc_and_load_rr_indexed_data(segment_inf, device_ctx.rr_node_indices,
+    alloc_and_load_rr_indexed_data(segment_inf, device_ctx.rr_graph,
                                    max_chan_width, wire_to_rr_ipin_switch, base_cost_type);
     load_rr_index_segments(segment_inf.size());
 }
@@ -1187,7 +1215,7 @@ static void free_type_track_to_pin_map(t_track_to_pin_lookup& track_to_pin_map,
 /* Does the actual work of allocating the rr_graph and filling all the *
  * appropriate values.  Everything up to this was just a prelude!      */
 static void alloc_and_load_rr_graph(const int num_nodes,
-                                    std::vector<t_rr_node>& L_rr_node,
+                                    RRGraph& rr_graph,
                                     const int num_seg_types,
                                     const t_chan_details& chan_details_x,
                                     const t_chan_details& chan_details_y,
@@ -1233,12 +1261,12 @@ static void alloc_and_load_rr_graph(const int num_nodes,
     /* Connection SINKS and SOURCES to their pins. */
     for (size_t i = 0; i < grid.width(); ++i) {
         for (size_t j = 0; j < grid.height(); ++j) {
-            build_rr_sinks_sources(i, j, L_rr_node, rr_edges_to_create, L_rr_node_indices,
+            build_rr_sinks_sources(i, j, rr_graph, rr_edges_to_create, L_rr_node_indices,
                                    delayless_switch, grid);
 
             //Create the actual SOURCE->OPIN, IPIN->SINK edges
             uniquify_edges(rr_edges_to_create);
-            alloc_and_load_edges(L_rr_node, rr_edges_to_create);
+            alloc_and_load_edges(rr_graph, rr_edges_to_create);
             rr_edges_to_create.clear();
         }
     }
@@ -1248,7 +1276,7 @@ static void alloc_and_load_rr_graph(const int num_nodes,
         for (size_t j = 0; j < grid.height(); ++j) {
             for (e_side side : SIDES) {
                 if (BI_DIRECTIONAL == directionality) {
-                    build_bidir_rr_opins(i, j, side, L_rr_node_indices, L_rr_node,
+                    build_bidir_rr_opins(i, j, side, L_rr_node_indices, rr_graph,
                                          opin_to_track_map, Fc_out, rr_edges_to_create, chan_details_x, chan_details_y,
                                          grid,
                                          directs, num_directs, clb_to_clb_directs, num_seg_types);
@@ -1266,7 +1294,7 @@ static void alloc_and_load_rr_graph(const int num_nodes,
 
                 //Create the actual OPIN->CHANX/CHANY edges
                 uniquify_edges(rr_edges_to_create);
-                alloc_and_load_edges(L_rr_node, rr_edges_to_create);
+                alloc_and_load_edges(rr_graph, rr_edges_to_create);
                 rr_edges_to_create.clear();
             }
         }
@@ -1282,13 +1310,13 @@ static void alloc_and_load_rr_graph(const int num_nodes,
                               CHANX_COST_INDEX_START,
                               max_chan_width, grid, tracks_per_chan,
                               sblock_pattern, Fs / 3, chan_details_x, chan_details_y,
-                              L_rr_node_indices, rr_edges_to_create, L_rr_node,
+                              L_rr_node_indices, rr_edges_to_create, rr_graph,
                               wire_to_ipin_switch,
                               directionality);
 
                 //Create the actual CHAN->CHAN edges
                 uniquify_edges(rr_edges_to_create);
-                alloc_and_load_edges(L_rr_node, rr_edges_to_create);
+                alloc_and_load_edges(rr_graph, rr_edges_to_create);
                 rr_edges_to_create.clear();
             }
             if (j > 0) {
@@ -1297,26 +1325,25 @@ static void alloc_and_load_rr_graph(const int num_nodes,
                               CHANX_COST_INDEX_START + num_seg_types,
                               max_chan_width, grid, tracks_per_chan,
                               sblock_pattern, Fs / 3, chan_details_x, chan_details_y,
-                              L_rr_node_indices, rr_edges_to_create, L_rr_node,
+                              L_rr_node_indices, rr_edges_to_create, rr_graph,
                               wire_to_ipin_switch,
                               directionality);
 
                 //Create the actual CHAN->CHAN edges
                 uniquify_edges(rr_edges_to_create);
-                alloc_and_load_edges(L_rr_node, rr_edges_to_create);
+                alloc_and_load_edges(rr_graph, rr_edges_to_create);
                 rr_edges_to_create.clear();
             }
         }
     }
 
-    init_fan_in(L_rr_node, num_nodes);
 }
 
 static void build_bidir_rr_opins(const int i,
                                  const int j,
                                  const e_side side,
                                  const t_rr_node_indices& L_rr_node_indices,
-                                 const std::vector<t_rr_node>& rr_nodes,
+                                 const RRGraph& rr_graph,
                                  const t_pin_to_track_lookup& opin_to_track_map,
                                  const std::vector<vtr::Matrix<int>>& Fc_out,
                                  t_rr_edge_info_set& rr_edges_to_create,
@@ -1358,20 +1385,20 @@ static void build_bidir_rr_opins(const int i,
             total_pin_Fc += Fc[pin_index][iseg];
         }
 
-        int node_index = get_rr_node_index(L_rr_node_indices, i, j, OPIN, pin_index, side);
+        RRNodeId node_index = rr_graph.find_node(i, j, OPIN, pin_index, side);
         VTR_ASSERT(node_index >= 0);
 
         if (total_pin_Fc > 0) {
             get_bidir_opin_connections(i, j, pin_index,
-                                       node_index, rr_edges_to_create, opin_to_track_map, L_rr_node_indices,
+                                       node_index, rr_edges_to_create, opin_to_track_map, rr_graph,
                                        chan_details_x,
                                        chan_details_y);
         }
 
         /* Add in direct connections */
-        get_opin_direct_connecions(i, j, side, pin_index,
-                                   node_index, rr_edges_to_create, L_rr_node_indices, rr_nodes,
-                                   directs, num_directs, clb_to_clb_directs);
+        get_opin_direct_connections(i, j, side, pin_index,
+                                    node_index, rr_edges_to_create, L_rr_node_indices, rr_nodes,
+                                    directs, num_directs, clb_to_clb_directs);
     }
 }
 
@@ -1412,7 +1439,7 @@ void free_rr_graph() {
 
 static void build_rr_sinks_sources(const int i,
                                    const int j,
-                                   std::vector<t_rr_node>& L_rr_node,
+                                   RRGraph& rr_graph,
                                    t_rr_edge_info_set& rr_edges_to_create,
                                    const t_rr_node_indices& L_rr_node_indices,
                                    const int delayless_switch,
@@ -1433,18 +1460,18 @@ static void build_rr_sinks_sources(const int i,
 
     /* SINK and SOURCE-to-OPIN edges */
     for (int iclass = 0; iclass < num_class; ++iclass) {
-        int inode = 0;
+        RRNodeId inode = 0;
         if (class_inf[iclass].type == DRIVER) { /* SOURCE */
-            inode = get_rr_node_index(L_rr_node_indices, i, j, SOURCE, iclass);
+            inode = rr_graph.find_node(i, j, SOURCE, iclass);
 
             //Retrieve all the physical OPINs associated with this source, this includes
             //those at different grid tiles of this block
-            std::vector<int> opin_nodes;
+            std::vector<RRNodeId> opin_nodes;
             for (int width_offset = 0; width_offset < type->width; ++width_offset) {
                 for (int height_offset = 0; height_offset < type->height; ++height_offset) {
                     for (int ipin = 0; ipin < class_inf[iclass].num_pins; ++ipin) {
                         int pin_num = class_inf[iclass].pinlist[ipin];
-                        auto physical_pins = get_rr_node_indices(L_rr_node_indices, i + width_offset, j + height_offset, OPIN, pin_num);
+                        auto physical_pins = find_rr_graph_nodes(rr_graph, i + width_offset, j + height_offset, OPIN, pin_num);
                         opin_nodes.insert(opin_nodes.end(), physical_pins.begin(), physical_pins.end());
                     }
                 }
@@ -1455,11 +1482,10 @@ static void build_rr_sinks_sources(const int i,
                 rr_edges_to_create.emplace_back(inode, opin_nodes[iedge], delayless_switch);
             }
 
-            L_rr_node[inode].set_cost_index(SOURCE_COST_INDEX);
-            L_rr_node[inode].set_type(SOURCE);
+            rr_graph.set_node_cost_index(inode, SOURCE_COST_INDEX);
         } else { /* SINK */
             VTR_ASSERT(class_inf[iclass].type == RECEIVER);
-            inode = get_rr_node_index(L_rr_node_indices, i, j, SINK, iclass);
+            inode = rr_graph.find_node(L_rr_node_indices, i, j, SINK, iclass);
 
             /* NOTE:  To allow route throughs through clbs, change the lines below to  *
              * make an edge from the input SINK to the output SOURCE.  Do for just the *
@@ -1468,19 +1494,16 @@ static void build_rr_sinks_sources(const int i,
              * base cost of OPINs and/or SOURCES so they aren't used excessively.      */
 
             /* Initialize to unconnected */
-            L_rr_node[inode].set_num_edges(0);
-
-            L_rr_node[inode].set_cost_index(SINK_COST_INDEX);
-            L_rr_node[inode].set_type(SINK);
+            rr_graph.set_node_cost_index(RRNodeId(inode), SINK_COST_INDEX);
         }
 
         /* Things common to both SOURCEs and SINKs.   */
-        L_rr_node[inode].set_capacity(class_inf[iclass].num_pins);
-        L_rr_node[inode].set_coordinates(i, j, i + type->width - 1, j + type->height - 1);
+        rr_graph.set_node_capacity(inode, class_inf[iclass].num_pins);
+        rr_graph.set_node_bounding_box(inode, vtr::Rect<short>(i, j, i + type->width - 1, j + type->height - 1));
         float R = 0.;
         float C = 0.;
-        L_rr_node[inode].set_rc_index(find_create_rr_rc_data(R, C));
-        L_rr_node[inode].set_ptc_num(iclass);
+        rr_graph.set_node_rc_index(inode, find_create_rr_rc_data(R, C));
+        rr_graph.set_node_ptc_num(inode, iclass);
     }
 
     /* Connect IPINS to SINKS and initialize OPINS */
@@ -1496,40 +1519,38 @@ static void build_rr_sinks_sources(const int i,
 
                         if (class_inf[iclass].type == RECEIVER) {
                             //Connect the input pin to the sink
-                            inode = get_rr_node_index(L_rr_node_indices, i + width_offset, j + height_offset, IPIN, ipin, side);
+                            inode = rr_graph.find_node(i + width_offset, j + height_offset, IPIN, ipin, side);
 
-                            int to_node = get_rr_node_index(L_rr_node_indices, i, j, SINK, iclass);
+                            RRNodeId to_node = rr_graph.find_node(i, j, SINK, iclass);
 
                             //Add info about the edge to be created
                             rr_edges_to_create.emplace_back(inode, to_node, delayless_switch);
 
                             VTR_ASSERT(inode >= 0);
-                            L_rr_node[inode].set_cost_index(IPIN_COST_INDEX);
-                            L_rr_node[inode].set_type(IPIN);
+                            rr_graph.set_node_cost_index(IPIN_COST_INDEX);
 
                         } else {
                             VTR_ASSERT(class_inf[iclass].type == DRIVER);
                             //Initialize the output pin
                             // Note that we leave it's out-going edges unconnected (they will be hooked up to global routing later)
-                            inode = get_rr_node_index(L_rr_node_indices, i + width_offset, j + height_offset, OPIN, ipin, side);
+                            inode = rr_graph.find_node(i + width_offset, j + height_offset, OPIN, ipin, side);
 
                             //Initially left unconnected
 
-                            L_rr_node[inode].set_cost_index(OPIN_COST_INDEX);
-                            L_rr_node[inode].set_type(OPIN);
+                            rr_graph.set_node_cost_index(inode, OPIN_COST_INDEX);
                         }
 
                         /* Common to both DRIVERs and RECEIVERs */
-                        L_rr_node[inode].set_capacity(1);
+                        rr_graph.set_node_capacity(inode, 1);
                         float R = 0.;
                         float C = 0.;
-                        L_rr_node[inode].set_rc_index(find_create_rr_rc_data(R, C));
-                        L_rr_node[inode].set_ptc_num(ipin);
+                        rr_graph.set_node_rc_index(inode, find_create_rr_rc_data(R, C));
+                        rr_graph.set_node_ptc_num(inode, ipin);
 
                         //Note that we store the grid tile location and side where the pin is located,
                         //which greatly simplifies the drawing code
-                        L_rr_node[inode].set_coordinates(i + width_offset, j + height_offset, i + width_offset, j + height_offset);
-                        L_rr_node[inode].set_side(side);
+                        rr_graph.set_node_bounding_box(inode, vtr::Rect<short>(i + width_offset, j + height_offset, i + width_offset, j + height_offset));
+                        rr_graph.set_node_side(inode, side);
 
                         VTR_ASSERT(type->pinloc[width_offset][height_offset][L_rr_node[inode].side()][L_rr_node[inode].pin_num()]);
                     }
@@ -1577,7 +1598,7 @@ static void build_rr_chan(const int x_coord,
                           const t_chan_details& chan_details_y,
                           const t_rr_node_indices& L_rr_node_indices,
                           t_rr_edge_info_set& rr_edges_to_create,
-                          std::vector<t_rr_node>& L_rr_node,
+                          RRGraph& rr_graph,
                           const int wire_to_ipin_switch,
                           const enum e_directionality directionality) {
     /* this function builds both x and y-directed channel segments, so set up our
@@ -1632,16 +1653,16 @@ static void build_rr_chan(const int x_coord,
             from_seg_details = chan_details_x[start][y_coord].data();
         }
 
-        int node = get_rr_node_index(L_rr_node_indices, x_coord, y_coord, chan_type, track);
+        RRNodeId node = rr_graph.find_node(x_coord, y_coord, chan_type, track);
 
-        if (node == OPEN) {
+        if (node == RRNodeId::INVALID()) {
             continue;
         }
 
         /* Add the edges from this track to all it's connected pins into the list */
         int num_edges = 0;
         num_edges += get_track_to_pins(start, chan_coord, track, tracks_per_chan, node, rr_edges_to_create,
-                                       L_rr_node_indices, track_to_pin_lookup, seg_details, chan_type, seg_dimension,
+                                       rr_graph, track_to_pin_lookup, seg_details, chan_type, seg_dimension,
                                        wire_to_ipin_switch, directionality);
 
         /* get edges going from the current track into channel segments which are perpendicular to it */
@@ -1659,7 +1680,7 @@ static void build_rr_chan(const int x_coord,
                                                  Fs_per_side, sblock_pattern, node, rr_edges_to_create,
                                                  from_seg_details, to_seg_details, opposite_chan_details,
                                                  directionality,
-                                                 L_rr_node_indices,
+                                                 rr_graph,
                                                  switch_block_conn, sb_conn_map);
             }
         }
@@ -1677,7 +1698,7 @@ static void build_rr_chan(const int x_coord,
                                                  Fs_per_side, sblock_pattern, node, rr_edges_to_create,
                                                  from_seg_details, to_seg_details, opposite_chan_details,
                                                  directionality,
-                                                 L_rr_node_indices,
+                                                 rr_graph,
                                                  switch_block_conn, sb_conn_map);
             }
         }
@@ -1707,31 +1728,32 @@ static void build_rr_chan(const int x_coord,
                                                      Fs_per_side, sblock_pattern, node, rr_edges_to_create,
                                                      from_seg_details, to_seg_details, from_chan_details,
                                                      directionality,
-                                                     L_rr_node_indices,
+                                                     rr_graph,
                                                      switch_block_conn, sb_conn_map);
                 }
             }
         }
 
         /* Edge arrays have now been built up.  Do everything else.  */
-        L_rr_node[node].set_cost_index(cost_index_offset + seg_details[track].index());
-        L_rr_node[node].set_capacity(1); /* GLOBAL routing handled elsewhere */
+        rr_graph.node[node].set_node_cost_index(node, cost_index_offset + seg_details[track].index());
+        rr_graph.set_node_capacity(node, 1); /* GLOBAL routing handled elsewhere */
 
         if (chan_type == CHANX) {
-            L_rr_node[node].set_coordinates(start, y_coord, end, y_coord);
+            rr_graph.set_node_bounding_box(node, vtr::Rect<short>(start, y_coord, end, y_coord));
         } else {
             VTR_ASSERT(chan_type == CHANY);
             L_rr_node[node].set_coordinates(x_coord, start, x_coord, end);
+            rr_graph.set_node_bounding_box(node, vtr::Rect<short>(x_coord, start, x_coord, end));
         }
 
         int length = end - start + 1;
         float R = length * seg_details[track].Rmetal();
         float C = length * seg_details[track].Cmetal();
-        L_rr_node[node].set_rc_index(find_create_rr_rc_data(R, C));
+        rr_graph.set_node_rc_index(node, find_create_rr_rc_data(R, C));
 
-        L_rr_node[node].set_ptc_num(track);
-        L_rr_node[node].set_type(chan_type);
-        L_rr_node[node].set_direction(seg_details[track].direction());
+        rr_graph.set_node_ptc_num(node, track);
+        rr_graph.set_node_type(node, chan_type);
+        rr_graph.set_node_direction(node, seg_details[track].direction());
     }
 }
 
@@ -1740,53 +1762,50 @@ void uniquify_edges(t_rr_edge_info_set& rr_edges_to_create) {
     rr_edges_to_create.erase(std::unique(rr_edges_to_create.begin(), rr_edges_to_create.end()), rr_edges_to_create.end());
 }
 
-void alloc_and_load_edges(std::vector<t_rr_node>& L_rr_node,
+void alloc_and_load_edges(RRGraph& rr_graph,
                           const t_rr_edge_info_set& rr_edges_to_create) {
     /* Sets up all the edge related information for rr_node */
 
     struct compare_from_node {
-        auto operator()(const t_rr_edge_info& lhs, const int from_node) {
-            return lhs.from_node < from_node;
+        auto operator()(const t_rr_edge_info& lhs, const RRNodeId& from_node) {
+            return size_t(lhs.from_node) < size_t(from_node);
         }
-        auto operator()(const int from_node, const t_rr_edge_info& rhs) {
-            return from_node < rhs.from_node;
+        auto operator()(const RRNodeId& from_node, const t_rr_edge_info& rhs) {
+            return size_t(from_node) < size_t(rhs.from_node);
         }
     };
 
-    std::set<int> from_nodes;
+    std::set<RRNodeId> from_nodes;
     for (auto& edge : rr_edges_to_create) {
         from_nodes.insert(edge.from_node);
     }
 
     VTR_ASSERT_SAFE(std::is_sorted(rr_edges_to_create.begin(), rr_edges_to_create.end()));
 
-    for (int inode : from_nodes) {
+    for (RRNodeId inode : from_nodes) {
         auto edge_range = std::equal_range(rr_edges_to_create.begin(), rr_edges_to_create.end(), inode, compare_from_node());
 
         size_t edge_count = std::distance(edge_range.first, edge_range.second);
 
-        if (L_rr_node[inode].num_edges() == 0) {
+        if (rr_graph.node_out_edges(inode).size() == 0) {
             //Create initial edges
             //
             //Note that we do this in bulk instead of via add_edge() to reduce
             //memory fragmentation
 
-            L_rr_node[inode].set_num_edges(edge_count);
+            rr_graph.reserve_edges(edge_count + rr_graph.edges().size());
 
-            int iedge = 0;
             for (auto itr = edge_range.first; itr != edge_range.second; ++itr) {
                 VTR_ASSERT(itr->from_node == inode);
 
-                L_rr_node[inode].set_edge_sink_node(iedge, itr->to_node);
-                L_rr_node[inode].set_edge_switch(iedge, itr->switch_type);
-                ++iedge;
+                rr_graph.create_edge(inode, itr->to_node, itr->switch_type);
             }
         } else {
             //Add new edge incrementally
             //
             //This should occur relatively rarely (e.g. a backward bidir edge) so memory fragmentation shouldn't be a big problem
             for (auto itr = edge_range.first; itr != edge_range.second; ++itr) {
-                L_rr_node[inode].add_edge(itr->to_node, itr->switch_type);
+                rr_graph.create_edge(inode, itr->to_node, itr->switch_type);
             }
         }
     }
@@ -2576,7 +2595,7 @@ std::string describe_rr_node(const RRNodeId& inode) {
 
     return msg;
 }
-static void build_unidir_rr_opins(const int i, const int j, const e_side side, const DeviceGrid& grid, const std::vector<vtr::Matrix<int>>& Fc_out, const int max_chan_width, const t_chan_details& chan_details_x, const t_chan_details& chan_details_y, vtr::NdMatrix<int, 3>& Fc_xofs, vtr::NdMatrix<int, 3>& Fc_yofs, t_rr_edge_info_set& rr_edges_to_create, bool* Fc_clipped, const t_rr_node_indices& L_rr_node_indices, const std::vector<t_rr_node>& rr_nodes, const t_direct_inf* directs, const int num_directs, const t_clb_to_clb_directs* clb_to_clb_directs, const int num_seg_types) {
+static void build_unidir_rr_opins(const int i, const int j, const e_side side, const DeviceGrid& grid, const std::vector<vtr::Matrix<int>>& Fc_out, const int max_chan_width, const t_chan_details& chan_details_x, const t_chan_details& chan_details_y, vtr::NdMatrix<int, 3>& Fc_xofs, vtr::NdMatrix<int, 3>& Fc_yofs, t_rr_edge_info_set& rr_edges_to_create, bool* Fc_clipped, const t_rr_node_indices& L_rr_node_indices, const RRGraph& rr_graph, const t_direct_inf* directs, const int num_directs, const t_clb_to_clb_directs* clb_to_clb_directs, const int num_seg_types) {
     /*
      * This routine adds the edges from opins to channels at the specified
      * grid location (i,j) and grid tile side
@@ -2599,8 +2618,8 @@ static void build_unidir_rr_opins(const int i, const int j, const e_side side, c
             continue;
         }
 
-        int opin_node_index = get_rr_node_index(L_rr_node_indices, i, j, OPIN, pin_index, side);
-        if (opin_node_index < 0) continue; //No valid from node
+        RRNodeId opin_node_index = rr_graph.find_node(i, j, OPIN, pin_index, side);
+        if (false == rr_graph.valid_node_id(opin_node_index)) continue; //No valid from node
 
         for (int iseg = 0; iseg < num_seg_types; iseg++) {
             /* get Fc for this segment type */
@@ -2653,15 +2672,15 @@ static void build_unidir_rr_opins(const int i, const int j, const e_side side, c
                                         opin_node_index,
                                         rr_edges_to_create,
                                         Fc_ofs, max_len, max_chan_width,
-                                        L_rr_node_indices, &clipped);
+                                        rr_graph, &clipped);
             if (clipped) {
                 *Fc_clipped = true;
             }
         }
 
         /* Add in direct connections */
-        get_opin_direct_connecions(i, j, side, pin_index, opin_node_index, rr_edges_to_create, L_rr_node_indices, rr_nodes,
-                                   directs, num_directs, clb_to_clb_directs);
+        get_opin_direct_connections(i, j, side, pin_index, opin_node_index, rr_edges_to_create, L_rr_node_indices, rr_graph,
+                                    directs, num_directs, clb_to_clb_directs);
     }
 }
 
@@ -2804,17 +2823,17 @@ static t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const t_direct_in
  *
  * The current opin is located at (x,y) along the specified side
  */
-static int get_opin_direct_connecions(int x,
-                                      int y,
-                                      e_side side,
-                                      int opin,
-                                      int from_rr_node,
-                                      t_rr_edge_info_set& rr_edges_to_create,
-                                      const t_rr_node_indices& L_rr_node_indices,
-                                      const std::vector<t_rr_node>& rr_nodes,
-                                      const t_direct_inf* directs,
-                                      const int num_directs,
-                                      const t_clb_to_clb_directs* clb_to_clb_directs) {
+static int get_opin_direct_connections(int x,
+                                       int y,
+                                       e_side side,
+                                       int opin,
+                                       const RRNodeId& from_rr_node,
+                                       t_rr_edge_info_set& rr_edges_to_create,
+                                       const t_rr_node_indices& L_rr_node_indices,
+                                       const RRGraph& rr_nodes,
+                                       const t_direct_inf* directs,
+                                       const int num_directs,
+                                       const t_clb_to_clb_directs* clb_to_clb_directs) {
     auto& device_ctx = g_vpr_ctx.device();
 
     t_physical_tile_type_ptr curr_type = device_ctx.grid[x][y].type;
@@ -2889,18 +2908,18 @@ static int get_opin_direct_connecions(int x,
                         //if (ipin > target_type->num_pins) continue; //Invalid z-offset
 
                         /* Add new ipin edge to list of edges */
-                        std::vector<int> inodes;
+                        std::vector<RRNodeId> inodes;
 
                         if (directs[i].to_side != NUM_SIDES) {
                             //Explicit side specified, only create if pin exists on that side
-                            int inode = get_rr_node_index(L_rr_node_indices, x + directs[i].x_offset, y + directs[i].y_offset,
+                            RRNodeId inode = rr_graph.find_node(x + directs[i].x_offset, y + directs[i].y_offset,
                                                           IPIN, ipin, directs[i].to_side);
-                            if (inode != OPEN) {
+                            if (inode != RRNodeId::INVALID()) {
                                 inodes.push_back(inode);
                             }
                         } else {
                             //No side specified, get all candidates
-                            inodes = get_rr_node_indices(L_rr_node_indices, x + directs[i].x_offset, y + directs[i].y_offset,
+                            inodes = rr_graph.find_node(x + directs[i].x_offset, y + directs[i].y_offset,
                                                          IPIN, ipin);
                         }
 
@@ -2909,7 +2928,7 @@ static int get_opin_direct_connecions(int x,
                             //target ipin. We only need to connect to one of them (since the physical pins
                             //are logically equivalent). This also ensures the graphics look reasonable and map
                             //back fairly directly to the architecture file in the case of pin equivalence
-                            int inode = pick_best_direct_connect_target_rr_node(rr_nodes, from_rr_node, inodes);
+                            RRNodeId inode = pick_best_direct_connect_target_rr_node(rr_graph, from_rr_node, inodes);
 
                             rr_edges_to_create.emplace_back(from_rr_node, inode, clb_to_clb_directs[i].switch_index);
                             ++num_pins;
@@ -3023,9 +3042,9 @@ static std::vector<bool> alloc_and_load_perturb_opins(const t_physical_tile_type
     return perturb_opins;
 }
 
-static int pick_best_direct_connect_target_rr_node(const std::vector<t_rr_node>& rr_nodes,
-                                                   int from_rr,
-                                                   const std::vector<int>& candidate_rr_nodes) {
+static RRNodeId pick_best_direct_connect_target_rr_node(const RRGraph& rr_nodes,
+                                                        const RRNodeId& from_rr,
+                                                        const std::vector<RRNodeId>& candidate_rr_nodes) {
     //With physically equivalent pins there may be multiple candidate rr nodes (which are equivalent)
     //to connect the direct edge to.
     //As a result it does not matter (from a correctness standpoint) which is picked.
@@ -3035,18 +3054,18 @@ static int pick_best_direct_connect_target_rr_node(const std::vector<t_rr_node>&
     //
     //This function attempts to pick the 'best/closest' of the candidates.
 
-    VTR_ASSERT(rr_nodes[from_rr].type() == OPIN);
-    e_side from_side = rr_nodes[from_rr].side();
+    VTR_ASSERT(rr_graph.node_type(from_rr) == OPIN);
+    e_side from_side = rr_graph.node_side(from_rr);
 
     float best_dist = std::numeric_limits<float>::infinity();
-    int best_rr = OPEN;
+    RRNodeId best_rr = RRNodeId::INVALID();
 
     for (int to_rr : candidate_rr_nodes) {
-        VTR_ASSERT(rr_nodes[to_rr].type() == IPIN);
-        float to_dist = std::abs(rr_nodes[from_rr].xlow() - rr_nodes[to_rr].xlow())
-                        + std::abs(rr_nodes[from_rr].ylow() - rr_nodes[to_rr].ylow());
+        VTR_ASSERT(rr_graph.node_type(to_rr) == IPIN);
+        float to_dist = std::abs(rr_graph.node_xlow(from_rr) - rr_graph.node_xlow(to_rr))
+                        + std::abs(rr_graph.node_ylow(from_rr) - rr_graph.node_ylow(to_rr));
 
-        e_side to_side = rr_nodes[to_rr].side();
+        e_side to_side = rr_graph.node_side(to_rr);
 
         //Include a partial unit of distance based on side alignment to ensure
         //we preferr facing sides
@@ -3072,7 +3091,7 @@ static int pick_best_direct_connect_target_rr_node(const std::vector<t_rr_node>&
         }
     }
 
-    VTR_ASSERT(best_rr != OPEN);
+    VTR_ASSERT(best_rr != RRNodeId::INVALID());
 
     return best_rr;
 }
diff --git a/vpr/src/route/rr_graph2.cpp b/vpr/src/route/rr_graph2.cpp
index 2b7ddb4da..59759b532 100644
--- a/vpr/src/route/rr_graph2.cpp
+++ b/vpr/src/route/rr_graph2.cpp
@@ -39,7 +39,7 @@ static void load_block_rr_indices(const DeviceGrid& grid,
                                   int* index);
 
 static int get_bidir_track_to_chan_seg(const std::vector<int> conn_tracks,
-                                       const t_rr_node_indices& L_rr_node_indices,
+                                       const RRGraph& rr_graph,
                                        const int to_chan,
                                        const int to_seg,
                                        const int to_sb,
@@ -49,7 +49,7 @@ static int get_bidir_track_to_chan_seg(const std::vector<int> conn_tracks,
                                        const int from_switch,
                                        const int switch_override,
                                        const enum e_directionality directionality,
-                                       const int from_rr_node,
+                                       const RRNodeId& from_rr_node,
                                        t_rr_edge_info_set& rr_edges_to_create);
 
 static int get_unidir_track_to_chan_seg(const int from_track,
@@ -64,7 +64,7 @@ static int get_unidir_track_to_chan_seg(const int from_track,
                                         const int Fs_per_side,
                                         t_sblock_pattern& sblock_pattern,
                                         const int switch_override,
-                                        const t_rr_node_indices& L_rr_node_indices,
+                                        const RRGraph& rr_graph,
                                         const t_chan_seg_details* seg_details,
                                         bool* Fs_clipped,
                                         const int from_rr_node,
@@ -77,9 +77,9 @@ static int get_track_to_chan_seg(const int from_track,
                                  const e_side from_side,
                                  const e_side to_side,
                                  const int swtich_override,
-                                 const t_rr_node_indices& L_rr_node_indices,
+                                 const RRGraph& rr_graph,
                                  t_sb_connection_map* sb_conn_map,
-                                 const int from_rr_node,
+                                 const RRNodeId& from_rr_node,
                                  t_rr_edge_info_set& rr_edges_to_create);
 
 static int vpr_to_phy_track(const int itrack,
@@ -664,14 +664,15 @@ int get_seg_end(const t_chan_seg_details* seg_details, const int itrack, const i
 int get_bidir_opin_connections(const int i,
                                const int j,
                                const int ipin,
-                               const int from_rr_node,
+                               const RRNodeId& from_rr_node,
                                t_rr_edge_info_set& rr_edges_to_create,
                                const t_pin_to_track_lookup& opin_to_track_map,
-                               const t_rr_node_indices& L_rr_node_indices,
+                               const RRGraph& rr_graph,
                                const t_chan_details& chan_details_x,
                                const t_chan_details& chan_details_y) {
     int num_conn, tr_i, tr_j, chan, seg;
-    int to_switch, to_node;
+    int to_switch;
+    RRNodeId to_node;
     int is_connected_track;
     t_physical_tile_type_ptr type;
     t_rr_type to_type;
@@ -730,9 +731,9 @@ int get_bidir_opin_connections(const int i,
             /* Only connect to wire if there is a CB */
             if (is_cblock(chan, seg, to_track, seg_details)) {
                 to_switch = seg_details[to_track].arch_wire_switch();
-                to_node = get_rr_node_index(L_rr_node_indices, tr_i, tr_j, to_type, to_track);
+                to_node = rr_graph.find_node(tr_i, tr_j, to_type, to_track);
 
-                if (to_node == OPEN) {
+                if (to_node == RRNodeId::INVALID()) {
                     continue;
                 }
 
@@ -751,12 +752,12 @@ int get_unidir_opin_connections(const int chan,
                                 const int seg_type_index,
                                 const t_rr_type chan_type,
                                 const t_chan_seg_details* seg_details,
-                                const int from_rr_node,
+                                const RRNodeId& from_rr_node,
                                 t_rr_edge_info_set& rr_edges_to_create,
                                 vtr::NdMatrix<int, 3>& Fc_ofs,
                                 const int max_len,
                                 const int max_chan_width,
-                                const t_rr_node_indices& L_rr_node_indices,
+                                const RRGraph& rr_graph,
                                 bool* Fc_clipped) {
     /* Gets a linked list of Fc nodes of specified seg_type_index to connect
      * to in given chan seg. Fc_ofs is used for the opin staggering pattern. */
@@ -808,10 +809,10 @@ int get_unidir_opin_connections(const int chan,
         dec_track = dec_muxes[dec_mux];
 
         /* Figure the inodes of those muxes */
-        inc_inode_index = get_rr_node_index(L_rr_node_indices, x, y, chan_type, inc_track);
-        dec_inode_index = get_rr_node_index(L_rr_node_indices, x, y, chan_type, dec_track);
+        inc_inode_index = rr_graph.find_node(x, y, chan_type, inc_track);
+        dec_inode_index = rr_graph.find_node(x, y, chan_type, dec_track);
 
-        if (inc_inode_index == OPEN || dec_inode_index == OPEN) {
+        if (inc_inode_index == RRNodeId::INVALID() || dec_inode_index == RRNodeId::INVALID()) {
             continue;
         }
 
@@ -1390,9 +1391,9 @@ int get_track_to_pins(int seg,
                       int chan,
                       int track,
                       int tracks_per_chan,
-                      int from_rr_node,
+                      const RRNodeId& from_rr_node,
                       t_rr_edge_info_set& rr_edges_to_create,
-                      const t_rr_node_indices& L_rr_node_indices,
+                      const RRGraph& rr_graph,
                       const t_track_to_pin_lookup& track_to_pin_lookup,
                       const t_chan_seg_details* seg_details,
                       enum e_rr_type chan_type,
@@ -1450,7 +1451,7 @@ int get_track_to_pins(int seg,
 
                     /* Check there is a connection and Fc map isn't wrong */
                     /*int to_node = get_rr_node_index(L_rr_node_indices, x + width_offset, y + height_offset, IPIN, ipin, side);*/
-                    int to_node = get_rr_node_index(L_rr_node_indices, x, y, IPIN, ipin, side);
+                    RRNodeId to_node = rr_graph.find_node(x, y, IPIN, ipin, side);
                     if (to_node >= 0) {
                         rr_edges_to_create.emplace_back(from_rr_node, to_node, wire_to_ipin_switch);
                         ++num_conn;
@@ -1491,13 +1492,13 @@ int get_track_to_tracks(const int from_chan,
                         const DeviceGrid& grid,
                         const int Fs_per_side,
                         t_sblock_pattern& sblock_pattern,
-                        const int from_rr_node,
+                        const RRNodeId& from_rr_node,
                         t_rr_edge_info_set& rr_edges_to_create,
                         const t_chan_seg_details* from_seg_details,
                         const t_chan_seg_details* to_seg_details,
                         const t_chan_details& to_chan_details,
                         const enum e_directionality directionality,
-                        const t_rr_node_indices& L_rr_node_indices,
+                        const RRGraph& rr_graph,
                         const vtr::NdMatrix<std::vector<int>, 3>& switch_block_conn,
                         t_sb_connection_map* sb_conn_map) {
     int to_chan, to_sb;
@@ -1630,7 +1631,7 @@ int get_track_to_tracks(const int from_chan,
                     num_conn += get_track_to_chan_seg(from_track, to_chan, to_seg,
                                                       to_type, from_side_a, to_side,
                                                       switch_override,
-                                                      L_rr_node_indices,
+                                                      rr_graph,
                                                       sb_conn_map, from_rr_node, rr_edges_to_create);
                 }
             } else {
@@ -1639,7 +1640,7 @@ int get_track_to_tracks(const int from_chan,
                      * switchbox, so we follow through regardless of whether the current segment has an SB */
                     conn_tracks = switch_block_conn[from_side_a][to_side][from_track];
                     num_conn += get_bidir_track_to_chan_seg(conn_tracks,
-                                                            L_rr_node_indices, to_chan, to_seg, to_sb, to_type,
+                                                            rr_graph, to_chan, to_seg, to_sb, to_type,
                                                             to_seg_details, from_is_sblock, from_switch,
                                                             switch_override,
                                                             directionality, from_rr_node, rr_edges_to_create);
@@ -1654,7 +1655,7 @@ int get_track_to_tracks(const int from_chan,
                                                                  from_side_a, to_side, Fs_per_side,
                                                                  sblock_pattern,
                                                                  switch_override,
-                                                                 L_rr_node_indices, to_seg_details,
+                                                                 rr_graph, to_seg_details,
                                                                  &Fs_clipped, from_rr_node, rr_edges_to_create);
                     }
                 }
@@ -1669,7 +1670,7 @@ int get_track_to_tracks(const int from_chan,
                     num_conn += get_track_to_chan_seg(from_track, to_chan, to_seg,
                                                       to_type, from_side_b, to_side,
                                                       switch_override,
-                                                      L_rr_node_indices,
+                                                      rr_graph,
                                                       sb_conn_map, from_rr_node, rr_edges_to_create);
                 }
             } else {
@@ -1678,7 +1679,7 @@ int get_track_to_tracks(const int from_chan,
                      * switchbox, so we follow through regardless of whether the current segment has an SB */
                     conn_tracks = switch_block_conn[from_side_b][to_side][from_track];
                     num_conn += get_bidir_track_to_chan_seg(conn_tracks,
-                                                            L_rr_node_indices, to_chan, to_seg, to_sb, to_type,
+                                                            rr_graph, to_chan, to_seg, to_sb, to_type,
                                                             to_seg_details, from_is_sblock, from_switch,
                                                             switch_override,
                                                             directionality, from_rr_node, rr_edges_to_create);
@@ -1694,7 +1695,7 @@ int get_track_to_tracks(const int from_chan,
                                                                  from_side_b, to_side, Fs_per_side,
                                                                  sblock_pattern,
                                                                  switch_override,
-                                                                 L_rr_node_indices, to_seg_details,
+                                                                 rr_graph, to_seg_details,
                                                                  &Fs_clipped, from_rr_node, rr_edges_to_create);
                     }
                 }
@@ -1706,7 +1707,7 @@ int get_track_to_tracks(const int from_chan,
 }
 
 static int get_bidir_track_to_chan_seg(const std::vector<int> conn_tracks,
-                                       const t_rr_node_indices& L_rr_node_indices,
+                                       const RRGraph& rr_graph,
                                        const int to_chan,
                                        const int to_seg,
                                        const int to_sb,
@@ -1716,10 +1717,11 @@ static int get_bidir_track_to_chan_seg(const std::vector<int> conn_tracks,
                                        const int from_switch,
                                        const int switch_override,
                                        const enum e_directionality directionality,
-                                       const int from_rr_node,
+                                       const RRNodeId& from_rr_node,
                                        t_rr_edge_info_set& rr_edges_to_create) {
     unsigned iconn;
-    int to_track, to_node, to_switch, num_conn, to_x, to_y, i;
+    int to_track, to_switch, num_conn, to_x, to_y, i;
+    RRNodeId to_node;
     bool to_is_sblock;
     short switch_types[2];
 
@@ -1737,9 +1739,9 @@ static int get_bidir_track_to_chan_seg(const std::vector<int> conn_tracks,
     num_conn = 0;
     for (iconn = 0; iconn < conn_tracks.size(); ++iconn) {
         to_track = conn_tracks[iconn];
-        to_node = get_rr_node_index(L_rr_node_indices, to_x, to_y, to_type, to_track);
+        to_node = rr_graph.find_node(to_x, to_y, to_type, to_track);
 
-        if (to_node == OPEN) {
+        if (to_node == RRNodeId::INVALID()) {
             continue;
         }
 
@@ -1780,9 +1782,9 @@ static int get_track_to_chan_seg(const int from_wire,
                                  const e_side from_side,
                                  const e_side to_side,
                                  const int switch_override,
-                                 const t_rr_node_indices& L_rr_node_indices,
+                                 const RRGraph& rr_graph,
                                  t_sb_connection_map* sb_conn_map,
-                                 const int from_rr_node,
+                                 const RRNodeId& from_rr_node,
                                  t_rr_edge_info_set& rr_edges_to_create) {
     int edge_count = 0;
     int to_x, to_y;
@@ -1816,9 +1818,9 @@ static int get_track_to_chan_seg(const int from_wire,
             if (conn_vector.at(iconn).from_wire != from_wire) continue;
 
             int to_wire = conn_vector.at(iconn).to_wire;
-            int to_node = get_rr_node_index(L_rr_node_indices, to_x, to_y, to_chan_type, to_wire);
+            RRNodeId to_node = rr_graph.find_node(to_x, to_y, to_chan_type, to_wire);
 
-            if (to_node == OPEN) {
+            if (to_node == RRNodeId::INVALID()) {
                 continue;
             }
 
@@ -1859,10 +1861,10 @@ static int get_unidir_track_to_chan_seg(const int from_track,
                                         const int Fs_per_side,
                                         t_sblock_pattern& sblock_pattern,
                                         const int switch_override,
-                                        const t_rr_node_indices& L_rr_node_indices,
+                                        const RRGraph& rr_graph,
                                         const t_chan_seg_details* seg_details,
                                         bool* Fs_clipped,
-                                        const int from_rr_node,
+                                        const RRNodeId& from_rr_node,
                                         t_rr_edge_info_set& rr_edges_to_create) {
     int num_labels = 0;
     int* mux_labels = nullptr;
@@ -1916,9 +1918,9 @@ static int get_unidir_track_to_chan_seg(const int from_track,
                 sblock_pattern[sb_x][sb_y][from_side][to_side][from_track][j + 1] = to_track;
             }
 
-            int to_node = get_rr_node_index(L_rr_node_indices, to_x, to_y, to_type, to_track);
+            RRNodeId to_node = rr_graph.find_node(to_x, to_y, to_type, to_track);
 
-            if (to_node == OPEN) {
+            if (to_node == RRNodeId::INVALID()) {
                 continue;
             }
 
diff --git a/vpr/src/route/rr_graph2.h b/vpr/src/route/rr_graph2.h
index dae44608c..0bbe884ad 100644
--- a/vpr/src/route/rr_graph2.h
+++ b/vpr/src/route/rr_graph2.h
@@ -15,21 +15,21 @@ enum e_seg_details_type {
 };
 
 struct t_rr_edge_info {
-    t_rr_edge_info(int from, int to, short type) noexcept
+    t_rr_edge_info(const RRNodeId& from, const RRNodeId& to, const short& type) noexcept
         : from_node(from)
         , to_node(to)
         , switch_type(type) {}
 
-    int from_node = OPEN;
-    int to_node = OPEN;
+    RRNodeId from_node = RRNodeId::INVALID();
+    RRNodeId to_node = RRNodeId::INVALID();
     short switch_type = OPEN;
 
     friend bool operator<(const t_rr_edge_info& lhs, const t_rr_edge_info& rhs) {
-        return std::tie(lhs.from_node, lhs.to_node, lhs.switch_type) < std::tie(rhs.from_node, rhs.to_node, rhs.switch_type);
+        return std::tie(size_t(lhs.from_node), size_t(lhs.to_node), lhs.switch_type) < std::tie(size_t(rhs.from_node), size_t(rhs.to_node), rhs.switch_type);
     }
 
     friend bool operator==(const t_rr_edge_info& lhs, const t_rr_edge_info& rhs) {
-        return std::tie(lhs.from_node, lhs.to_node, lhs.switch_type) == std::tie(rhs.from_node, rhs.to_node, rhs.switch_type);
+        return std::tie(size_t(lhs.from_node), size_t(lhs.to_node), lhs.switch_type) == std::tie(size_t(rhs.from_node), size_t(rhs.to_node), rhs.switch_type);
     }
 };
 
@@ -158,21 +158,21 @@ int get_unidir_opin_connections(const int chan,
                                 const int seg_type_index,
                                 const t_rr_type chan_type,
                                 const t_chan_seg_details* seg_details,
-                                const int from_rr_node,
+                                const RRNodeId& from_rr_node,
                                 t_rr_edge_info_set& rr_edges_to_create,
                                 vtr::NdMatrix<int, 3>& Fc_ofs,
                                 const int max_len,
                                 const int max_chan_width,
-                                const t_rr_node_indices& L_rr_node_indices,
+                                const RRGraph& rr_graph,
                                 bool* Fc_clipped);
 
 int get_track_to_pins(int seg,
                       int chan,
                       int track,
                       int tracks_per_chan,
-                      int from_rr_node,
+                      const RRNodeId& from_rr_node,
                       t_rr_edge_info_set& rr_edges_to_create,
-                      const t_rr_node_indices& L_rr_node_indices,
+                      const RRGraph& rr_graph,
                       const t_track_to_pin_lookup& track_to_pin_lookup,
                       const t_chan_seg_details* seg_details,
                       enum e_rr_type chan_type,
@@ -191,13 +191,13 @@ int get_track_to_tracks(const int from_chan,
                         const DeviceGrid& grid,
                         const int Fs_per_side,
                         t_sblock_pattern& sblock_pattern,
-                        const int from_rr_node,
+                        const RRNodeId& from_rr_node,
                         t_rr_edge_info_set& rr_edges_to_create,
                         const t_chan_seg_details* from_seg_details,
                         const t_chan_seg_details* to_seg_details,
                         const t_chan_details& to_chan_details,
                         const enum e_directionality directionality,
-                        const t_rr_node_indices& L_rr_node_indices,
+                        const RRGraph& rr_graph,
                         const vtr::NdMatrix<std::vector<int>, 3>& switch_block_conn,
                         t_sb_connection_map* sb_conn_map);
 

From fc6389b5c0d8dda666c397564738ee4649148c5f Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 3 Feb 2020 14:40:04 -0700
Subject: [PATCH 088/645] refactored RRGraph builder

---
 vpr/src/device/rr_graph_obj.cpp |  68 +++++++++---
 vpr/src/route/rr_graph.cpp      |  10 +-
 vpr/src/route/rr_graph2.cpp     | 186 ++++++++++++++++----------------
 vpr/src/route/rr_graph2.h       |  10 +-
 4 files changed, 154 insertions(+), 120 deletions(-)

diff --git a/vpr/src/device/rr_graph_obj.cpp b/vpr/src/device/rr_graph_obj.cpp
index 6a05b6a21..cb2fb7cd2 100644
--- a/vpr/src/device/rr_graph_obj.cpp
+++ b/vpr/src/device/rr_graph_obj.cpp
@@ -65,10 +65,22 @@ short RRGraph::node_ylow(const RRNodeId& node) const {
 }
 
 short RRGraph::node_xhigh(const RRNodeId& node) const {
+    /* Special for SOURCE and SINK node, we always return the xlow 
+     * This is due to the convention in creating RRGraph 
+     * so that we can guarantee unique SOURCE/SINK nodes searching 
+     */
+    if (  (SOURCE == node_type(node)
+       || (SINK == node_type(node)) {
+      return node_bounding_box(node).xmin();
+    }
     return node_bounding_box(node).xmax();
 }
 
 short RRGraph::node_yhigh(const RRNodeId& node) const {
+    if (  (SOURCE == node_type(node)
+       || (SINK == node_type(node)) {
+      return node_bounding_box(node).ymin();
+    }
     return node_bounding_box(node).ymax();
 }
 
@@ -1200,28 +1212,50 @@ void RRGraph::build_fast_node_lookup() const {
             continue;
         }
         RRNodeId node = RRNodeId(id);
-        size_t x = node_xlow(node);
-        size_t y = node_ylow(node);
-        size_t itype = node_type(node);
+        /* Special for SOURCE and SINK, we should annotate in the look-up 
+         * for all the (x,y) upto (xhigh, yhigh)
+         */
+        std::vector<size_t> xlows;
+        std::vector<size_t> ylows;
 
-        size_t ptc = node_ptc_num(node);
-        if (ptc >= node_lookup_[x][y][itype].size()) {
-            node_lookup_[x][y][itype].resize(ptc + 1);
+        if ( (SOURCE == node_type(node)
+          || (SINK == node_type(node)) {
+            xlows.resize(node_bounding_boxes_[node].xmax() - node_bounding_boxes_[node].xmin() + 1);
+            ylows.resize(node_bounding_boxes_[node].ymax() - node_bounding_boxes_[node].ymin() + 1);
+            std::iota(xlows.begin(), xlows.end(), node_xlow(node));
+            std::iota(ylows.begin(), ylows.end(), node_ylow(node));
+            /* Sanity check */
+            VTR_ASSERT(node_bounding_boxes_[node].xmax() == xlows.back());
+            VTR_ASSERT(node_bounding_boxes_[node].ymax() == ylows.back());
+        } else { 
+            xlows.push_back(node_xlow(node));
+            ylows.push_back(node_ylow(node));
         }
 
-        size_t iside = -1;
-        if (node_type(node) == OPIN || node_type(node) == IPIN) {
-            iside = node_side(node);
-        } else {
-            iside = NUM_SIDES;
-        }
+        for (size_t x : xlows) {
+            for (size_t y : ylows) {
+                size_t itype = node_type(node);
 
-        if (iside >= node_lookup_[x][y][itype][ptc].size()) {
-            node_lookup_[x][y][itype][ptc].resize(iside + 1);
-        }
+                size_t ptc = node_ptc_num(node);
+                if (ptc >= node_lookup_[x][y][itype].size()) {
+                    node_lookup_[x][y][itype].resize(ptc + 1);
+                }
 
-        //Save node in lookup
-        node_lookup_[x][y][itype][ptc][iside] = node;
+                size_t iside = -1;
+                if (node_type(node) == OPIN || node_type(node) == IPIN) {
+                    iside = node_side(node);
+                } else {
+                    iside = NUM_SIDES;
+                }
+
+                if (iside >= node_lookup_[x][y][itype][ptc].size()) {
+                    node_lookup_[x][y][itype][ptc].resize(iside + 1);
+                }
+
+                //Save node in lookup
+                node_lookup_[x][y][itype][ptc][iside] = node;
+            }
+        }
     }
 }
 
diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp
index 5ff1f9f35..f1d5f4929 100644
--- a/vpr/src/route/rr_graph.cpp
+++ b/vpr/src/route/rr_graph.cpp
@@ -591,13 +591,11 @@ static void build_rr_graph(const t_graph_type graph_type,
     /* Alloc node lookups, count nodes, alloc rr nodes */
     int num_rr_nodes = 0;
 
-    /* Xifan Tang - Keep the node indices here since it counts the number of rr_nodes 
-     * We will simplify this function as indices will be built inside the RRGraph object
+    /* Xifan Tang - 
+     * We create all the nodes in the RRGraph object here
      */
-    device_ctx.rr_node_indices = alloc_and_load_rr_node_indices(max_chan_width, grid,
-                                                                &num_rr_nodes, chan_details_x, chan_details_y);
-    /* Reserve the node for the RRGraph object */
-    device_ctx.rr_graph.reserve_node(num_rr_nodes);
+    device_ctx.rr_graph = alloc_and_load_rr_node_indices(max_chan_width, grid,
+                                                         &num_rr_nodes, chan_details_x, chan_details_y);
 
     /* These are data structures used by the the unidir opin mapping. They are used
      * to spread connections evenly for each segment type among the available
diff --git a/vpr/src/route/rr_graph2.cpp b/vpr/src/route/rr_graph2.cpp
index 59759b532..b861be721 100644
--- a/vpr/src/route/rr_graph2.cpp
+++ b/vpr/src/route/rr_graph2.cpp
@@ -31,11 +31,11 @@ static void load_chan_rr_indices(const int max_chan_width,
                                  const int num_chans,
                                  const t_rr_type type,
                                  const t_chan_details& chan_details,
-                                 t_rr_node_indices& indices,
+                                 RRGraph& rr_graph,
                                  int* index);
 
 static void load_block_rr_indices(const DeviceGrid& grid,
-                                  t_rr_node_indices& indices,
+                                  RRGraph& rr_graph,
                                   int* index);
 
 static int get_bidir_track_to_chan_seg(const std::vector<int> conn_tracks,
@@ -1024,25 +1024,43 @@ void dump_sblock_pattern(const t_sblock_pattern& sblock_pattern,
     fclose(fp);
 }
 
+/********************************************************************
+ * Create all the nodes for routing tracks
+ * num_chans : number of routing channels to be created
+ * chan_len : maximum length of routing channels
+ *
+ * X-direction channel 
+ *             |<-------chan_len-------->|
+ *        -----+--------------------------
+ *        ^    |
+ *        |    |
+ *        |    |
+ *   num_chans |         FPGA 
+ *        |    |
+ *        |    |
+ *        v    |
+ *        -----+--------------------------
+ *
+ * Y-direction channel 
+ *             |<-------num_chans-------->|
+ *        -----+--------------------------
+ *        ^    |
+ *        |    |
+ *        |    |
+ *    chan_len |         FPGA 
+ *        |    |
+ *        |    |
+ *        v    |
+ *        -----+--------------------------
+ *
+ *******************************************************************/
 static void load_chan_rr_indices(const int max_chan_width,
                                  const int chan_len,
                                  const int num_chans,
                                  const t_rr_type type,
                                  const t_chan_details& chan_details,
-                                 t_rr_node_indices& indices,
+                                 RRGraph& rr_graph,
                                  int* index) {
-    VTR_ASSERT(indices[type].size() == size_t(num_chans));
-    for (int chan = 0; chan < num_chans - 1; ++chan) {
-        VTR_ASSERT(indices[type][chan].size() == size_t(chan_len));
-
-        for (int seg = 1; seg < chan_len - 1; ++seg) {
-            VTR_ASSERT(indices[type][chan][seg].size() == NUM_SIDES);
-
-            /* Alloc the track inode lookup list */
-            //Since channels have no side, we just use the first side
-            indices[type][chan][seg][0].resize(max_chan_width, OPEN);
-        }
-    }
 
     for (int chan = 0; chan < num_chans - 1; ++chan) {
         for (int seg = 1; seg < chan_len - 1; ++seg) {
@@ -1051,31 +1069,31 @@ static void load_chan_rr_indices(const int max_chan_width,
             int y = (type == CHANX ? chan : seg);
             const t_chan_seg_details* seg_details = chan_details[x][y].data();
 
-            for (unsigned track = 0; track < indices[type][chan][seg][0].size(); ++track) {
+            for (unsigned track = 0; track < num_chans - 1; ++track) {
                 if (seg_details[track].length() <= 0)
                     continue;
 
                 int start = get_seg_start(seg_details, track, chan, seg);
-
-                /* If the start of the wire doesn't have a inode,
-                 * assign one to it. */
-                int inode = indices[type][chan][start][0][track];
-                if (OPEN == inode) {
-                    inode = *index;
-                    ++(*index);
-
-                    indices[type][chan][start][0][track] = inode;
+                 
+                /* If this segment does not start from the current position, we do not allocate any nodes */
+                if (start != seg) {
+                    continue;
                 }
 
-                /* Assign inode of start of wire to current position */
-                indices[type][chan][seg][0][track] = inode;
+                RRNodeId node = rr_graph.create_node(type);
+                short xlow = x;
+                short ylow = y;
+                short xhigh = (type == CHANX ? xlow + seg_details[track].length() - 1 : xlow);
+                short yhigh = (type == CHANY ? ylow + seg_details[track].length() - 1 : ylow);
+                rr_graph.set_node_bounding_box(node, vtr::Rect<short>(xlow, ylow, xhigh, yhigh));
+                rr_graph.set_node_track_num(node, track);
             }
         }
     }
 }
 
 static void load_block_rr_indices(const DeviceGrid& grid,
-                                  t_rr_node_indices& indices,
+                                  RRGraph& rr_graph,
                                   int* index) {
     //Walk through the grid assigning indices to SOURCE/SINK IPIN/OPIN
     for (size_t x = 0; x < grid.width(); x++) {
@@ -1089,17 +1107,17 @@ static void load_block_rr_indices(const DeviceGrid& grid,
                 for (int iclass = 0; iclass < type->num_class; ++iclass) {
                     auto class_type = type->class_inf[iclass].type;
                     if (class_type == DRIVER) {
-                        indices[SOURCE][x][y][0].push_back(*index);
-                        indices[SINK][x][y][0].push_back(OPEN);
+                        RRNodeId node = rr_graph.create_node(SOURCE);
+                        rr_graph.set_node_bounding_box(node, vtr::Rect<size_t>(x, y, x, y));
+                        rr_graph.set_node_class_num(iclass);
                     } else {
                         VTR_ASSERT(class_type == RECEIVER);
-                        indices[SINK][x][y][0].push_back(*index);
-                        indices[SOURCE][x][y][0].push_back(OPEN);
+                        RRNodeId node = rr_graph.create_node(SINK);
+                        rr_graph.set_node_bounding_box(node, vtr::Rect<size_t>(x, y, x, y));
+                        rr_graph.set_node_class_num(iclass);
                     }
                     ++(*index);
                 }
-                VTR_ASSERT(indices[SOURCE][x][y][0].size() == size_t(type->num_class));
-                VTR_ASSERT(indices[SINK][x][y][0].size() == size_t(type->num_class));
 
                 //Assign indicies for IPINs and OPINs at all offsets from root
                 for (int ipin = 0; ipin < type->num_pins; ++ipin) {
@@ -1113,34 +1131,23 @@ static void load_block_rr_indices(const DeviceGrid& grid,
                                     auto class_type = type->class_inf[iclass].type;
 
                                     if (class_type == DRIVER) {
-                                        indices[OPIN][x_tile][y_tile][side].push_back(*index);
-                                        indices[IPIN][x_tile][y_tile][side].push_back(OPEN);
+                                        RRNodeId node = rr_graph.create_node(OPIN);
+                                        rr_graph.set_node_bounding_box(node, vtr::Rect<size_t>(xtile, ytile, xtile, ytile));
+                                        rr_graph.set_node_pin_num(ipin);
+                                        rr_graph.set_node_side(side);
                                     } else {
                                         VTR_ASSERT(class_type == RECEIVER);
-                                        indices[IPIN][x_tile][y_tile][side].push_back(*index);
-                                        indices[OPIN][x_tile][y_tile][side].push_back(OPEN);
+                                        RRNodeId node = rr_graph.create_node(IPIN);
+                                        rr_graph.set_node_bounding_box(node, vtr::Rect<size_t>(xtile, ytile, xtile, ytile));
+                                        rr_graph.set_node_pin_num(ipin);
+                                        rr_graph.set_node_side(side);
                                     }
                                     ++(*index);
-                                } else {
-                                    indices[IPIN][x_tile][y_tile][side].push_back(OPEN);
-                                    indices[OPIN][x_tile][y_tile][side].push_back(OPEN);
                                 }
                             }
                         }
                     }
                 }
-
-                //Sanity check
-                for (int width_offset = 0; width_offset < type->width; ++width_offset) {
-                    int x_tile = x + width_offset;
-                    for (int height_offset = 0; height_offset < type->height; ++height_offset) {
-                        int y_tile = y + height_offset;
-                        for (e_side side : SIDES) {
-                            VTR_ASSERT(indices[IPIN][x_tile][y_tile][side].size() == size_t(type->num_pins));
-                            VTR_ASSERT(indices[OPIN][x_tile][y_tile][side].size() == size_t(type->num_pins));
-                        }
-                    }
-                }
             }
         }
     }
@@ -1151,59 +1158,54 @@ static void load_block_rr_indices(const DeviceGrid& grid,
         for (size_t y = 0; y < grid.height(); y++) {
             int width_offset = grid[x][y].width_offset;
             int height_offset = grid[x][y].height_offset;
-            if (width_offset != 0 || height_offset != 0) {
+            /* We only care the largest offset in both x and y direction
+             * this can avoid runtime cost to rebuild the fast look-up inside RRGraph object
+             */
+            if ( (grid[x][y].type->height == height_offset && grid[x][y].type->width == width_offset)
+              && (0 != height_offset && 0 != width_offset) ) {
                 int root_x = x - width_offset;
                 int root_y = y - height_offset;
 
-                indices[SOURCE][x][y] = indices[SOURCE][root_x][root_y];
-                indices[SINK][x][y] = indices[SINK][root_x][root_y];
+                //Process each block from it's root location
+                auto type = grid[x][y].type;
+
+                //Assign indicies for SINKs and SOURCEs
+                // Note that SINKS/SOURCES have no side, so we always use side 0
+                for (int iclass = 0; iclass < type->num_class; ++iclass) {
+                    auto class_type = type->class_inf[iclass].type;
+                    if (class_type == DRIVER) {
+                        RRNodeId node = rr_graph.find_node(root_x, root_y, SOURCE, iclass);
+                        /* Update the internal look-up so that we can find the SOURCE/SINK node using their offset coordinates */
+                        rr_graph.set_node_bounding_box(node, vtr::Rect<size_t>(root_x, root_y, x, y));
+                    } else {
+                        VTR_ASSERT(class_type == RECEIVER);
+                        RRNodeId node = rr_graph.find_node(root_x, root_y, SINK, iclass);
+                        /* Update the internal look-up so that we can find the SOURCE/SINK node using their offset coordinates */
+                        rr_graph.set_node_bounding_box(node, vtr::Rect<size_t>(root_x, root_y, x, y));
+                    }
+                }
             }
         }
     }
 }
 
-t_rr_node_indices alloc_and_load_rr_node_indices(const int max_chan_width,
-                                                 const DeviceGrid& grid,
-                                                 int* index,
-                                                 const t_chan_details& chan_details_x,
-                                                 const t_chan_details& chan_details_y) {
-    /* Allocates and loads all the structures needed for fast lookups of the   *
-     * index of an rr_node.  rr_node_indices is a matrix containing the index  *
-     * of the *first* rr_node at a given (i,j) location.                       */
-
-    t_rr_node_indices indices;
-
-    /* Alloc the lookup table */
-    indices.resize(NUM_RR_TYPES);
-    for (t_rr_type rr_type : RR_TYPES) {
-        if (rr_type == CHANX) {
-            indices[rr_type].resize(grid.height());
-            for (size_t y = 0; y < grid.height(); ++y) {
-                indices[rr_type][y].resize(grid.width());
-                for (size_t x = 0; x < grid.width(); ++x) {
-                    indices[rr_type][y][x].resize(NUM_SIDES);
-                }
-            }
-        } else {
-            indices[rr_type].resize(grid.width());
-            for (size_t x = 0; x < grid.width(); ++x) {
-                indices[rr_type][x].resize(grid.height());
-                for (size_t y = 0; y < grid.height(); ++y) {
-                    indices[rr_type][x][y].resize(NUM_SIDES);
-                }
-            }
-        }
-    }
+RRGraph alloc_and_load_rr_node_indices(const int max_chan_width,
+                                       const DeviceGrid& grid,
+                                       int* index,
+                                       const t_chan_details& chan_details_x,
+                                       const t_chan_details& chan_details_y) {
+    /* Allocates and loads all the nodes in a RRGraph object */
+    RRGraph rr_graph;
 
     /* Assign indices for block nodes */
-    load_block_rr_indices(grid, indices, index);
+    load_block_rr_indices(grid, rr_graph, index);
 
     /* Load the data for x and y channels */
     load_chan_rr_indices(max_chan_width, grid.width(), grid.height(),
-                         CHANX, chan_details_x, indices, index);
+                         CHANX, chan_details_x, rr_graph, index);
     load_chan_rr_indices(max_chan_width, grid.height(), grid.width(),
-                         CHANY, chan_details_y, indices, index);
-    return indices;
+                         CHANY, chan_details_y, rr_graph, index);
+    return rr_graph;
 }
 
 std::vector<int> get_rr_node_chan_wires_at_location(const t_rr_node_indices& L_rr_node_indices,
diff --git a/vpr/src/route/rr_graph2.h b/vpr/src/route/rr_graph2.h
index 0bbe884ad..55791b8d4 100644
--- a/vpr/src/route/rr_graph2.h
+++ b/vpr/src/route/rr_graph2.h
@@ -39,11 +39,11 @@ typedef vtr::NdMatrix<short, 6> t_sblock_pattern;
 
 /******************* Subroutines exported by rr_graph2.c *********************/
 
-t_rr_node_indices alloc_and_load_rr_node_indices(const int max_chan_width,
-                                                 const DeviceGrid& grid,
-                                                 int* index,
-                                                 const t_chan_details& chan_details_x,
-                                                 const t_chan_details& chan_details_y);
+RRGraph alloc_and_load_rr_node_indices(const int max_chan_width,
+                                       const DeviceGrid& grid,
+                                       int* index,
+                                       const t_chan_details& chan_details_x,
+                                       const t_chan_details& chan_details_y);
 
 int get_rr_node_index(int x,
                       int y,

From 9f3afb5a46a61640691199ac8e086da126f01775 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 3 Feb 2020 15:11:24 -0700
Subject: [PATCH 089/645] refactored rr_graph clock builder

---
 vpr/src/route/clock_connection_builders.cpp |  2 +-
 vpr/src/route/clock_network_builders.cpp    | 45 ++++++++++-----------
 vpr/src/route/rr_graph.cpp                  | 10 ++++-
 vpr/src/route/rr_graph_clock.cpp            | 32 +++++++--------
 vpr/src/route/rr_graph_clock.h              |  4 +-
 vpr/src/route/rr_graph_reader.cpp           |  6 +--
 6 files changed, 53 insertions(+), 46 deletions(-)

diff --git a/vpr/src/route/clock_connection_builders.cpp b/vpr/src/route/clock_connection_builders.cpp
index e8fca6977..5ba6fefea 100644
--- a/vpr/src/route/clock_connection_builders.cpp
+++ b/vpr/src/route/clock_connection_builders.cpp
@@ -137,7 +137,7 @@ void ClockToClockConneciton::set_fc_val(float fc_val) {
 void ClockToClockConneciton::create_switches(const ClockRRGraphBuilder& clock_graph) {
     auto& device_ctx = g_vpr_ctx.mutable_device();
     auto& grid = device_ctx.grid;
-    auto& rr_nodes = device_ctx.rr_nodes;
+    auto& rr_graph = device_ctx.rr_graph;
 
     auto to_locations = clock_graph.get_switch_locations(to_clock, to_switch);
 
diff --git a/vpr/src/route/clock_network_builders.cpp b/vpr/src/route/clock_network_builders.cpp
index ea367bdbb..af04c86d0 100644
--- a/vpr/src/route/clock_network_builders.cpp
+++ b/vpr/src/route/clock_network_builders.cpp
@@ -180,7 +180,7 @@ void ClockRib::create_rr_nodes_and_internal_edges_for_one_instance(ClockRRGraphB
     (void)num_segments;
 
     auto& device_ctx = g_vpr_ctx.mutable_device();
-    auto& rr_nodes = device_ctx.rr_nodes;
+    auto& rr_graph = device_ctx.rr_graph;
     auto& grid = device_ctx.grid;
 
     int ptc_num = clock_graph.get_and_increment_chanx_ptc_num(); // used for drawing
@@ -231,7 +231,7 @@ void ClockRib::create_rr_nodes_and_internal_edges_for_one_instance(ClockRRGraphB
                                                     y,
                                                     ptc_num,
                                                     BI_DIRECTION,
-                                                    rr_nodes);
+                                                    rr_graph);
             clock_graph.add_switch_location(get_name(), drive.name, drive_x, y, drive_node_idx);
 
             // create rib wire to the right and left of the drive point
@@ -240,13 +240,13 @@ void ClockRib::create_rr_nodes_and_internal_edges_for_one_instance(ClockRRGraphB
                                                    y,
                                                    ptc_num,
                                                    DEC_DIRECTION,
-                                                   rr_nodes);
+                                                   rr_graph);
             auto right_node_idx = create_chanx_wire(drive_x + 1,
                                                     x_end,
                                                     y,
                                                     ptc_num,
                                                     INC_DIRECTION,
-                                                    rr_nodes);
+                                                    rr_graph);
             record_tap_locations(x_start + x_offset,
                                  x_end,
                                  y,
@@ -255,28 +255,27 @@ void ClockRib::create_rr_nodes_and_internal_edges_for_one_instance(ClockRRGraphB
                                  clock_graph);
 
             // connect drive point to each half rib using a directed switch
-            rr_nodes[drive_node_idx].add_edge(left_node_idx, drive.switch_idx);
-            rr_nodes[drive_node_idx].add_edge(right_node_idx, drive.switch_idx);
+            rr_graph.create_edge(drive_node_idx, left_node_idx, drive.switch_idx);
+            rr_graph.create_edge(drive_node_idx, right_node_idx, drive.switch_idx);
         }
     }
 }
 
-int ClockRib::create_chanx_wire(int x_start,
-                                int x_end,
-                                int y,
-                                int ptc_num,
-                                e_direction direction,
-                                std::vector<t_rr_node>& rr_nodes) {
-    rr_nodes.emplace_back();
-    auto node_index = rr_nodes.size() - 1;
+RRNodeId ClockRib::create_chanx_wire(int x_start,
+                                     int x_end,
+                                     int y,
+                                     int ptc_num,
+                                     e_direction direction,
+                                     RRGraph& rr_graph) {
+    RRNodeId node_index rr_graph.create_node(CHANX);
 
-    rr_nodes[node_index].set_coordinates(x_start, y, x_end, y);
-    rr_nodes[node_index].set_type(CHANX);
-    rr_nodes[node_index].set_capacity(1);
-    rr_nodes[node_index].set_track_num(ptc_num);
-    rr_nodes[node_index].set_rc_index(find_create_rr_rc_data(
+    rr_graph.set_node_bounding_box(node_index, vtr::Rect<size_t>(x_start, y, x_end, y));
+    rr_graph.set_node_type(node_index, CHANX);
+    rr_graph.set_node_capacity(node_index, 1);
+    rr_graph.set_node_track_num(node_index, ptc_num);
+    rr_graph.set_node_rc_index(node_index, find_create_rr_rc_data(
         x_chan_wire.layer.r_metal, x_chan_wire.layer.c_metal));
-    rr_nodes[node_index].set_direction(direction);
+    rr_graph.set_node_direction(node_index, direction);
 
     short seg_index = 0;
     switch (direction) {
@@ -293,7 +292,7 @@ int ClockRib::create_chanx_wire(int x_start,
             VTR_ASSERT_MSG(false, "Unidentified direction type for clock rib");
             break;
     }
-    rr_nodes[node_index].set_cost_index(CHANX_COST_INDEX_START + seg_index); // Actual value set later
+    rr_graph.set_node_cost_index(node_index, CHANX_COST_INDEX_START + seg_index); // Actual value set later
 
     return node_index;
 }
@@ -301,8 +300,8 @@ int ClockRib::create_chanx_wire(int x_start,
 void ClockRib::record_tap_locations(unsigned x_start,
                                     unsigned x_end,
                                     unsigned y,
-                                    int left_rr_node_idx,
-                                    int right_rr_node_idx,
+                                    const RRNodeId& left_rr_node_idx,
+                                    const RRNodeId& right_rr_node_idx,
                                     ClockRRGraphBuilder& clock_graph) {
     for (unsigned x = x_start + tap.offset; x <= x_end; x += tap.increment) {
         if (x < (x_start + drive.offset - 1)) {
diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp
index f1d5f4929..32f86e2f8 100644
--- a/vpr/src/route/rr_graph.cpp
+++ b/vpr/src/route/rr_graph.cpp
@@ -377,7 +377,7 @@ void create_rr_graph(const t_graph_type graph_type,
         }
 
         /* Xifan Tang - Create rr_graph object: load rr_nodes to the object */
-        convert_rr_graph(segment_inf);
+        //convert_rr_graph(segment_inf);
     }
 
     process_non_config_sets();
@@ -597,6 +597,14 @@ static void build_rr_graph(const t_graph_type graph_type,
     device_ctx.rr_graph = alloc_and_load_rr_node_indices(max_chan_width, grid,
                                                          &num_rr_nodes, chan_details_x, chan_details_y);
 
+    /* The number of segments are in general small, reserve segments may not bring
+     * significant memory efficiency */
+    device_ctx.rr_graph.reserve_segments(segment_inf.size());
+    // Create the segments
+    for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) {
+        device_ctx.rr_graph.create_segment(segment_inf[iseg]);
+    }
+
     /* These are data structures used by the the unidir opin mapping. They are used
      * to spread connections evenly for each segment type among the available
      * wire start points */
diff --git a/vpr/src/route/rr_graph_clock.cpp b/vpr/src/route/rr_graph_clock.cpp
index 47746c0f8..fa9f09e34 100644
--- a/vpr/src/route/rr_graph_clock.cpp
+++ b/vpr/src/route/rr_graph_clock.cpp
@@ -24,22 +24,20 @@ void ClockRRGraphBuilder::create_and_append_clock_rr_graph(std::vector<t_segment
     auto& clock_networks = device_ctx.clock_networks;
     auto& clock_routing = device_ctx.clock_connections;
 
-    size_t clock_nodes_start_idx = device_ctx.rr_nodes.size();
+    size_t clock_nodes_start_idx = device_ctx.rr_graph.nodes().size();
 
     ClockRRGraphBuilder clock_graph = ClockRRGraphBuilder();
     clock_graph.create_clock_networks_wires(clock_networks, segment_inf.size());
     clock_graph.create_clock_networks_switches(clock_routing);
 
     // Reset fanin to account for newly added clock rr_nodes
-    init_fan_in(device_ctx.rr_nodes, device_ctx.rr_nodes.size());
-
     clock_graph.add_rr_switches_and_map_to_nodes(clock_nodes_start_idx, R_minW_nmos, R_minW_pmos);
 
     // "Partition the rr graph edges for efficient access to configurable/non-configurable
     //  edge subsets. Must be done after RR switches have been allocated"
-    partition_rr_graph_edges(device_ctx);
+    device_ctx.rr_graph.rebuild_node_edges();
 
-    alloc_and_load_rr_indexed_data(segment_inf, device_ctx.rr_node_indices,
+    alloc_and_load_rr_indexed_data(segment_inf, device_ctx.rr_graph,
                                    chan_width->max, wire_to_rr_ipin_switch, base_cost_type);
 
     float elapsed_time = (float)(clock() - begin) / CLOCKS_PER_SEC;
@@ -55,8 +53,8 @@ void ClockRRGraphBuilder::create_clock_networks_wires(std::vector<std::unique_pt
     }
 
     // Reduce the capacity of rr_nodes for performance
-    auto& rr_nodes = g_vpr_ctx.mutable_device().rr_nodes;
-    rr_nodes.shrink_to_fit();
+    auto& rr_graph = g_vpr_ctx.mutable_device().rr_graph;
+    rr_graph.compress();
 }
 
 // Clock switch information comes from the arch file
@@ -70,18 +68,18 @@ void ClockRRGraphBuilder::add_rr_switches_and_map_to_nodes(size_t node_start_idx
                                                            const float R_minW_nmos,
                                                            const float R_minW_pmos) {
     auto& device_ctx = g_vpr_ctx.mutable_device();
-    auto& rr_nodes = device_ctx.rr_nodes;
+    auto& rr_graph = device_ctx.rr_graph;
 
     // Check to see that clock nodes were sucessfully appended to rr_nodes
-    VTR_ASSERT(rr_nodes.size() > node_start_idx);
+    VTR_ASSERT(true == rr_graph.valid_node_id(RRNodeId(node_start_idx));
 
     std::unordered_map<int, int> arch_switch_to_rr_switch;
 
     // The following assumes that arch_switch was specified earlier when the edges where added
-    for (size_t node_idx = node_start_idx; node_idx < rr_nodes.size(); node_idx++) {
-        auto& from_node = rr_nodes[node_idx];
-        for (t_edge_size edge_idx = 0; edge_idx < from_node.num_edges(); edge_idx++) {
-            int arch_switch_idx = from_node.edge_switch(edge_idx);
+    for (size_t node_idx = node_start_idx; node_idx < rr_graph.nodes().size(); node_idx++) {
+        const RRNodeId& from_node = RRNodeId(node_idx);
+        for (const RREdgeId& edge_idx : rr_graph.node_out_edges(from_node)) {
+            int arch_switch_idx = rr_graph.edge_switch(edge_idx);
 
             int rr_switch_idx;
             auto itter = arch_switch_to_rr_switch.find(arch_switch_idx);
@@ -94,7 +92,7 @@ void ClockRRGraphBuilder::add_rr_switches_and_map_to_nodes(size_t node_start_idx
                 rr_switch_idx = itter->second;
             }
 
-            from_node.set_edge_switch(edge_idx, rr_switch_idx);
+            rr_graph.set_edge_switch(edge_idx, rr_switch_idx);
         }
     }
 
@@ -125,17 +123,17 @@ void ClockRRGraphBuilder::add_switch_location(std::string clock_name,
                                               std::string switch_point_name,
                                               int x,
                                               int y,
-                                              int node_index) {
+                                              const RRNodeId& node_index) {
     // Note use of operator[] will automatically insert clock name if it doesn't exist
     clock_name_to_switch_points[clock_name].insert_switch_node_idx(switch_point_name, x, y, node_index);
 }
 
-void SwitchPoints::insert_switch_node_idx(std::string switch_point_name, int x, int y, int node_idx) {
+void SwitchPoints::insert_switch_node_idx(std::string switch_point_name, int x, int y, const RRNodeId& node_idx) {
     // Note use of operator[] will automatically insert switch name if it doesn't exit
     switch_point_name_to_switch_location[switch_point_name].insert_node_idx(x, y, node_idx);
 }
 
-void SwitchPoint::insert_node_idx(int x, int y, int node_idx) {
+void SwitchPoint::insert_node_idx(int x, int y, const RRNodeId& node_idx) {
     // allocate 2d vector of grid size
     if (rr_node_indices.empty()) {
         auto& grid = g_vpr_ctx.device().grid;
diff --git a/vpr/src/route/rr_graph_clock.h b/vpr/src/route/rr_graph_clock.h
index ccab33d8b..df6aff1b9 100644
--- a/vpr/src/route/rr_graph_clock.h
+++ b/vpr/src/route/rr_graph_clock.h
@@ -13,6 +13,8 @@
 #include "clock_network_builders.h"
 #include "clock_connection_builders.h"
 
+#include "rr_graph_obj_fwd.h"
+
 class ClockNetwork;
 class ClockConnection;
 
@@ -23,7 +25,7 @@ class SwitchPoint {
      * Examples of SwitchPoint(s) are rib-to-spine, driver-to-spine. */
   public:
     // [grid_width][grid_height][0..nodes_at_this_location-1]
-    std::vector<std::vector<std::vector<int>>> rr_node_indices;
+    std::vector<std::vector<std::vector<RRNodeId>>> rr_node_indices;
     // Set of all the locations for this switch point. Used to quickly find
     // if the switch point exists at a certian location.
     std::set<std::pair<int, int>> locations; // x,y
diff --git a/vpr/src/route/rr_graph_reader.cpp b/vpr/src/route/rr_graph_reader.cpp
index 7200786ad..ccaf6af1b 100644
--- a/vpr/src/route/rr_graph_reader.cpp
+++ b/vpr/src/route/rr_graph_reader.cpp
@@ -281,17 +281,17 @@ void process_seg_id(pugi::xml_node parent, const pugiutil::loc_data& loc_data) {
 
     while (rr_node) {
         id = get_attribute(rr_node, "id", loc_data).as_int();
-        auto& node = device_ctx.rr_nodes[id];
+        auto& node = RRNodeId(id);
 
         segmentSubnode = get_single_child(rr_node, "segment", loc_data, pugiutil::OPTIONAL);
         if (segmentSubnode) {
             attribute = get_attribute(segmentSubnode, "segment_id", loc_data, pugiutil::OPTIONAL);
             if (attribute) {
                 int seg_id = get_attribute(segmentSubnode, "segment_id", loc_data).as_int(0);
-                device_ctx.rr_indexed_data[node.cost_index()].seg_index = seg_id;
+                device_ctx.rr_indexed_data[device_ctx.rr_graph.node_cost_index(node)].seg_index = seg_id;
             } else {
                 //-1 for non chanx or chany nodes
-                device_ctx.rr_indexed_data[node.cost_index()].seg_index = -1;
+                device_ctx.rr_indexed_data[device_ctx.rr_graph.node_cost_index(node)].seg_index = -1;
             }
         }
         rr_node = rr_node.next_sibling(rr_node.name());

From 898ed891d2187b47db0a38c584423fab8cb6d18c Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 3 Feb 2020 19:05:18 -0700
Subject: [PATCH 090/645] midway in debugging the refactored rr_graph builder

---
 vpr/src/base/vpr_context.h                  |  2 +-
 vpr/src/device/rr_graph_obj.cpp             | 32 ++++++-----
 vpr/src/device/rr_graph_obj.h               |  1 +
 vpr/src/device/rr_graph_obj_util.cpp        | 18 +++++++
 vpr/src/device/rr_graph_obj_util.h          |  6 +++
 vpr/src/route/clock_connection_builders.cpp | 47 ++++++++--------
 vpr/src/route/clock_connection_builders.h   |  2 +-
 vpr/src/route/clock_network_builders.cpp    | 57 ++++++++++----------
 vpr/src/route/clock_network_builders.h      | 34 ++++++------
 vpr/src/route/rr_graph.cpp                  | 57 ++++++++++----------
 vpr/src/route/rr_graph2.cpp                 | 60 ++++++++++-----------
 vpr/src/route/rr_graph2.h                   | 18 +++++--
 vpr/src/route/rr_graph_clock.cpp            | 14 ++---
 vpr/src/route/rr_graph_clock.h              | 14 ++---
 vpr/src/route/rr_graph_indexed_data.cpp     |  2 +-
 vpr/src/route/rr_graph_reader.cpp           | 25 +++++----
 16 files changed, 214 insertions(+), 175 deletions(-)

diff --git a/vpr/src/base/vpr_context.h b/vpr/src/base/vpr_context.h
index ecad22007..487382480 100644
--- a/vpr/src/base/vpr_context.h
+++ b/vpr/src/base/vpr_context.h
@@ -178,7 +178,7 @@ struct DeviceContext : public Context {
     // Useful for two stage clock routing
     // XXX: currently only one place to source the clock networks so only storing
     //      a single value
-    int virtual_clock_network_root_idx;
+    RRNodeId virtual_clock_network_root_idx;
 
     /** Attributes for each rr_node.
      * key:     rr_node index
diff --git a/vpr/src/device/rr_graph_obj.cpp b/vpr/src/device/rr_graph_obj.cpp
index cb2fb7cd2..37ab22729 100644
--- a/vpr/src/device/rr_graph_obj.cpp
+++ b/vpr/src/device/rr_graph_obj.cpp
@@ -69,16 +69,16 @@ short RRGraph::node_xhigh(const RRNodeId& node) const {
      * This is due to the convention in creating RRGraph 
      * so that we can guarantee unique SOURCE/SINK nodes searching 
      */
-    if (  (SOURCE == node_type(node)
-       || (SINK == node_type(node)) {
+    if (  (SOURCE == node_type(node))
+       || (SINK == node_type(node)) ) {
       return node_bounding_box(node).xmin();
     }
     return node_bounding_box(node).xmax();
 }
 
 short RRGraph::node_yhigh(const RRNodeId& node) const {
-    if (  (SOURCE == node_type(node)
-       || (SINK == node_type(node)) {
+    if (  (SOURCE == node_type(node))
+       || (SINK == node_type(node)) ) {
       return node_bounding_box(node).ymin();
     }
     return node_bounding_box(node).ymax();
@@ -391,7 +391,8 @@ RRNodeId RRGraph::find_node(const short& x, const short& y, const t_rr_type& typ
 
     /* Check if x, y, type and ptc, side is valid */
     if ((ptc < 0)                                                 /* See if ptc is smaller than the index of first element */
-        || (size_t(ptc) > node_lookup_[x][y][type].size() - 1)) { /* See if ptc is large than the index of last element */
+        || (size_t(ptc) > node_lookup_[x][y][type].size() - 1) /* See if ptc is large than the index of last element */
+        || (0 == node_lookup_[x][y][type].size())) { /* See if ptc is large than the index of last element */
         /* Return a zero range! */
         return RRNodeId::INVALID();
     }
@@ -856,7 +857,7 @@ RRNodeId RRGraph::create_node(const t_rr_type& type) {
 RREdgeId RRGraph::create_edge(const RRNodeId& source, const RRNodeId& sink, const RRSwitchId& switch_id) {
     VTR_ASSERT(valid_node_id(source));
     VTR_ASSERT(valid_node_id(sink));
-    VTR_ASSERT(valid_switch_id(switch_id));
+    //VTR_ASSERT(valid_switch_id(switch_id));
 
     /* Allocate an ID */
     RREdgeId edge_id = RREdgeId(num_edges_);
@@ -878,6 +879,11 @@ RREdgeId RRGraph::create_edge(const RRNodeId& source, const RRNodeId& sink, cons
     return edge_id;
 }
 
+void RRGraph::set_edge_switch(const RREdgeId& edge, const RRSwitchId& switch_id) {
+    VTR_ASSERT(valid_edge_id(edge));
+    edge_switches_[edge] = switch_id;
+}
+
 RRSwitchId RRGraph::create_switch(const t_rr_switch_inf& switch_info) {
     //Allocate an ID
     RRSwitchId switch_id = RRSwitchId(switch_ids_.size());
@@ -1200,8 +1206,8 @@ void RRGraph::build_fast_node_lookup() const {
             /* Skip this id */
             continue;
         }
-        max_coord.set_x(std::max(max_coord.x(), node_xlow(RRNodeId(id))));
-        max_coord.set_y(std::max(max_coord.y(), node_ylow(RRNodeId(id))));
+        max_coord.set_x(std::max(max_coord.x(), std::max(node_bounding_boxes_[RRNodeId(id)].xmax(), node_bounding_boxes_[RRNodeId(id)].xmin())));
+        max_coord.set_y(std::max(max_coord.y(), std::max(node_bounding_boxes_[RRNodeId(id)].ymax(), node_bounding_boxes_[RRNodeId(id)].ymin())));
     }
     node_lookup_.resize({(size_t)max_coord.x() + 1, (size_t)max_coord.y() + 1, NUM_RR_TYPES + 1});
 
@@ -1218,15 +1224,17 @@ void RRGraph::build_fast_node_lookup() const {
         std::vector<size_t> xlows;
         std::vector<size_t> ylows;
 
-        if ( (SOURCE == node_type(node)
-          || (SINK == node_type(node)) {
+        if ( (SOURCE == node_type(node))
+          || (SINK == node_type(node)) 
+          || (CHANX == node_type(node))
+          || (CHANY == node_type(node)) ) {
             xlows.resize(node_bounding_boxes_[node].xmax() - node_bounding_boxes_[node].xmin() + 1);
             ylows.resize(node_bounding_boxes_[node].ymax() - node_bounding_boxes_[node].ymin() + 1);
             std::iota(xlows.begin(), xlows.end(), node_xlow(node));
             std::iota(ylows.begin(), ylows.end(), node_ylow(node));
             /* Sanity check */
-            VTR_ASSERT(node_bounding_boxes_[node].xmax() == xlows.back());
-            VTR_ASSERT(node_bounding_boxes_[node].ymax() == ylows.back());
+            VTR_ASSERT(size_t(node_bounding_boxes_[node].xmax()) == xlows.back());
+            VTR_ASSERT(size_t(node_bounding_boxes_[node].ymax()) == ylows.back());
         } else { 
             xlows.push_back(node_xlow(node));
             ylows.push_back(node_ylow(node));
diff --git a/vpr/src/device/rr_graph_obj.h b/vpr/src/device/rr_graph_obj.h
index df46df754..fedc90612 100644
--- a/vpr/src/device/rr_graph_obj.h
+++ b/vpr/src/device/rr_graph_obj.h
@@ -615,6 +615,7 @@ class RRGraph {
      * configure the nodes and edges in connection   
      */
     RREdgeId create_edge(const RRNodeId& source, const RRNodeId& sink, const RRSwitchId& switch_id);
+    void set_edge_switch(const RREdgeId& edge, const RRSwitchId& switch_id);
     RRSwitchId create_switch(const t_rr_switch_inf& switch_info);
     RRSegmentId create_segment(const t_segment_inf& segment_info);
 
diff --git a/vpr/src/device/rr_graph_obj_util.cpp b/vpr/src/device/rr_graph_obj_util.cpp
index 92d27e083..373c48fa1 100644
--- a/vpr/src/device/rr_graph_obj_util.cpp
+++ b/vpr/src/device/rr_graph_obj_util.cpp
@@ -63,3 +63,21 @@ std::vector<RRNodeId> find_rr_graph_nodes(const RRGraph& rr_graph,
     return indices;
 }
 
+std::vector<RRNodeId> find_rr_graph_chan_nodes(const RRGraph& rr_graph,
+                                               const int& x,
+                                               const int& y,
+                                               const t_rr_type& rr_type) {
+    std::vector<RRNodeId> indices;
+
+    VTR_ASSERT(rr_type == CHANX || rr_type == CHANY);
+
+    for (short track = 0; track < rr_graph.chan_num_tracks(x, y, rr_type); ++track) {
+        RRNodeId rr_node_index = rr_graph.find_node(x, y, rr_type, track);
+
+        if (rr_node_index != RRNodeId::INVALID()) {
+            indices.push_back(rr_node_index);
+        }
+    }
+
+    return indices;
+}
diff --git a/vpr/src/device/rr_graph_obj_util.h b/vpr/src/device/rr_graph_obj_util.h
index 9a089d68c..71d97dcf9 100644
--- a/vpr/src/device/rr_graph_obj_util.h
+++ b/vpr/src/device/rr_graph_obj_util.h
@@ -18,4 +18,10 @@ std::vector<RRNodeId> find_rr_graph_nodes(const RRGraph& rr_graph,
                                           const t_rr_type& rr_type,
                                           const int& ptc);
 
+std::vector<RRNodeId> find_rr_graph_chan_nodes(const RRGraph& rr_graph,
+                                               const int& x,
+                                               const int& y,
+                                               const t_rr_type& rr_type);
+
+
 #endif
diff --git a/vpr/src/route/clock_connection_builders.cpp b/vpr/src/route/clock_connection_builders.cpp
index 5ba6fefea..b36fee966 100644
--- a/vpr/src/route/clock_connection_builders.cpp
+++ b/vpr/src/route/clock_connection_builders.cpp
@@ -2,6 +2,7 @@
 
 #include "globals.h"
 #include "rr_graph2.h"
+#include "rr_graph_obj_util.h"
 
 #include "vtr_assert.h"
 #include "vtr_log.h"
@@ -46,17 +47,16 @@ void RoutingToClockConnection::create_switches(const ClockRRGraphBuilder& clock_
     std::srand(seed);
 
     auto& device_ctx = g_vpr_ctx.mutable_device();
-    auto& rr_nodes = device_ctx.rr_nodes;
-    auto& rr_node_indices = device_ctx.rr_node_indices;
+    auto& rr_graph = device_ctx.rr_graph;
 
-    int virtual_clock_network_root_idx = create_virtual_clock_network_sink_node(switch_location.x, switch_location.y);
+    RRNodeId virtual_clock_network_root_idx = create_virtual_clock_network_sink_node(switch_location.x, switch_location.y);
     device_ctx.virtual_clock_network_root_idx = virtual_clock_network_root_idx;
 
     // rr_node indices for x and y channel routing wires and clock wires to connect to
-    auto x_wire_indices = get_rr_node_chan_wires_at_location(
-        rr_node_indices, CHANX, switch_location.x, switch_location.y);
-    auto y_wire_indices = get_rr_node_chan_wires_at_location(
-        rr_node_indices, CHANY, switch_location.x, switch_location.y);
+    auto x_wire_indices = find_rr_graph_chan_nodes(
+        rr_graph, switch_location.x, switch_location.y, CHANX);
+    auto y_wire_indices = find_rr_graph_chan_nodes(
+        rr_graph, switch_location.x, switch_location.y, CHANY);
     auto clock_indices = clock_graph.get_rr_node_indices_at_switch_location(
         clock_to_connect_to, switch_point_name, switch_location.x, switch_location.y);
 
@@ -68,36 +68,35 @@ void RoutingToClockConnection::create_switches(const ClockRRGraphBuilder& clock_
         // Connect to x-channel wires
         unsigned num_wires_x = x_wire_indices.size() * fc;
         for (size_t i = 0; i < num_wires_x; i++) {
-            rr_nodes[x_wire_indices[i]].add_edge(clock_index, rr_switch_idx);
+            rr_graph.create_edge(x_wire_indices[i], clock_index, RRSwitchId(rr_switch_idx));
         }
 
         // Connect to y-channel wires
         unsigned num_wires_y = y_wire_indices.size() * fc;
         for (size_t i = 0; i < num_wires_y; i++) {
-            rr_nodes[y_wire_indices[i]].add_edge(clock_index, rr_switch_idx);
+            rr_graph.create_edge(y_wire_indices[i], clock_index, RRSwitchId(rr_switch_idx));
         }
 
         // Connect to virtual clock sink node
         // used by the two stage router
-        rr_nodes[clock_index].add_edge(virtual_clock_network_root_idx, rr_switch_idx);
+        rr_graph.create_edge(clock_index, virtual_clock_network_root_idx, RRSwitchId(rr_switch_idx));
     }
 }
 
-int RoutingToClockConnection::create_virtual_clock_network_sink_node(
+RRNodeId RoutingToClockConnection::create_virtual_clock_network_sink_node(
     int x,
     int y) {
     auto& device_ctx = g_vpr_ctx.mutable_device();
-    auto& rr_nodes = device_ctx.rr_nodes;
-    rr_nodes.emplace_back();
-    auto node_index = rr_nodes.size() - 1;
+    auto& rr_graph = device_ctx.rr_graph;
 
-    rr_nodes[node_index].set_coordinates(x, y, x, y);
-    rr_nodes[node_index].set_capacity(1);
-    rr_nodes[node_index].set_cost_index(SINK_COST_INDEX);
-    rr_nodes[node_index].set_type(SINK);
+    RRNodeId node_index = rr_graph.create_node(SINK);
+
+    rr_graph.set_node_bounding_box(node_index, vtr::Rect<short>(x, y, x, y));
+    rr_graph.set_node_capacity(node_index, 1);
+    rr_graph.set_node_cost_index(node_index, SINK_COST_INDEX);
     float R = 0.;
     float C = 0.;
-    rr_nodes[node_index].set_rc_index(find_create_rr_rc_data(R, C));
+    rr_graph.set_node_rc_data_index(node_index, find_create_rr_rc_data(R, C));
 
     return node_index;
 }
@@ -179,7 +178,7 @@ void ClockToClockConneciton::create_switches(const ClockRRGraphBuilder& clock_gr
                 if (from_itter == from_rr_node_indices.end()) {
                     from_itter = from_rr_node_indices.begin();
                 }
-                rr_nodes[*from_itter].add_edge(to_index, rr_switch_idx);
+                rr_graph.create_edge(*from_itter, to_index, RRSwitchId(rr_switch_idx));
                 from_itter++;
             }
         }
@@ -213,8 +212,7 @@ void ClockToPinsConnection::set_fc_val(float fc_val) {
 
 void ClockToPinsConnection::create_switches(const ClockRRGraphBuilder& clock_graph) {
     auto& device_ctx = g_vpr_ctx.mutable_device();
-    auto& rr_nodes = device_ctx.rr_nodes;
-    auto& rr_node_indices = device_ctx.rr_node_indices;
+    auto& rr_graph = device_ctx.rr_graph;
     auto& grid = device_ctx.grid;
 
     for (size_t x = 0; x < grid.width(); x++) {
@@ -274,8 +272,7 @@ void ClockToPinsConnection::create_switches(const ClockRRGraphBuilder& clock_gra
                         clock_y_offset = -1; // pick the chanx below the block
                     }
 
-                    auto clock_pin_node_idx = get_rr_node_index(
-                        rr_node_indices,
+                    auto clock_pin_node_idx = rr_graph.find_node(
                         x,
                         y,
                         IPIN,
@@ -290,7 +287,7 @@ void ClockToPinsConnection::create_switches(const ClockRRGraphBuilder& clock_gra
 
                     //Create edges depending on Fc
                     for (size_t i = 0; i < clock_network_indices.size() * fc; i++) {
-                        rr_nodes[clock_network_indices[i]].add_edge(clock_pin_node_idx, rr_switch_idx);
+                        rr_graph.create_edge(clock_network_indices[i], clock_pin_node_idx, RRSwitchId(rr_switch_idx));
                     }
                 }
             }
diff --git a/vpr/src/route/clock_connection_builders.h b/vpr/src/route/clock_connection_builders.h
index 8076907b6..707f16af7 100644
--- a/vpr/src/route/clock_connection_builders.h
+++ b/vpr/src/route/clock_connection_builders.h
@@ -54,7 +54,7 @@ class RoutingToClockConnection : public ClockConnection {
      */
     /* Connects the inter-block routing to the clock source at the specified coordinates */
     void create_switches(const ClockRRGraphBuilder& clock_graph);
-    int create_virtual_clock_network_sink_node(int x, int y);
+    RRNodeId create_virtual_clock_network_sink_node(int x, int y);
 };
 
 class ClockToClockConneciton : public ClockConnection {
diff --git a/vpr/src/route/clock_network_builders.cpp b/vpr/src/route/clock_network_builders.cpp
index af04c86d0..b90babdae 100644
--- a/vpr/src/route/clock_network_builders.cpp
+++ b/vpr/src/route/clock_network_builders.cpp
@@ -255,8 +255,8 @@ void ClockRib::create_rr_nodes_and_internal_edges_for_one_instance(ClockRRGraphB
                                  clock_graph);
 
             // connect drive point to each half rib using a directed switch
-            rr_graph.create_edge(drive_node_idx, left_node_idx, drive.switch_idx);
-            rr_graph.create_edge(drive_node_idx, right_node_idx, drive.switch_idx);
+            rr_graph.create_edge(drive_node_idx, left_node_idx, RRSwitchId(drive.switch_idx));
+            rr_graph.create_edge(drive_node_idx, right_node_idx, RRSwitchId(drive.switch_idx));
         }
     }
 }
@@ -267,13 +267,12 @@ RRNodeId ClockRib::create_chanx_wire(int x_start,
                                      int ptc_num,
                                      e_direction direction,
                                      RRGraph& rr_graph) {
-    RRNodeId node_index rr_graph.create_node(CHANX);
+    RRNodeId node_index = rr_graph.create_node(CHANX);
 
-    rr_graph.set_node_bounding_box(node_index, vtr::Rect<size_t>(x_start, y, x_end, y));
-    rr_graph.set_node_type(node_index, CHANX);
+    rr_graph.set_node_bounding_box(node_index, vtr::Rect<short>(x_start, y, x_end, y));
     rr_graph.set_node_capacity(node_index, 1);
     rr_graph.set_node_track_num(node_index, ptc_num);
-    rr_graph.set_node_rc_index(node_index, find_create_rr_rc_data(
+    rr_graph.set_node_rc_data_index(node_index, find_create_rr_rc_data(
         x_chan_wire.layer.r_metal, x_chan_wire.layer.c_metal));
     rr_graph.set_node_direction(node_index, direction);
 
@@ -421,7 +420,7 @@ void ClockSpine::create_segments(std::vector<t_segment_inf>& segment_inf) {
 void ClockSpine::create_rr_nodes_and_internal_edges_for_one_instance(ClockRRGraphBuilder& clock_graph,
                                                                      int num_segments) {
     auto& device_ctx = g_vpr_ctx.mutable_device();
-    auto& rr_nodes = device_ctx.rr_nodes;
+    auto& rr_graph = device_ctx.rr_graph;
     auto& grid = device_ctx.grid;
 
     int ptc_num = clock_graph.get_and_increment_chany_ptc_num(); // used for drawing
@@ -472,7 +471,7 @@ void ClockSpine::create_rr_nodes_and_internal_edges_for_one_instance(ClockRRGrap
                                                     x,
                                                     ptc_num,
                                                     BI_DIRECTION,
-                                                    rr_nodes,
+                                                    rr_graph,
                                                     num_segments);
             clock_graph.add_switch_location(get_name(), drive.name, x, drive_y, drive_node_idx);
 
@@ -482,14 +481,14 @@ void ClockSpine::create_rr_nodes_and_internal_edges_for_one_instance(ClockRRGrap
                                                    x,
                                                    ptc_num,
                                                    DEC_DIRECTION,
-                                                   rr_nodes,
+                                                   rr_graph,
                                                    num_segments);
             auto right_node_idx = create_chany_wire(drive_y + 1,
                                                     y_end,
                                                     x,
                                                     ptc_num,
                                                     INC_DIRECTION,
-                                                    rr_nodes,
+                                                    rr_graph,
                                                     num_segments);
 
             // Keep a record of the rr_node idx that we will use to connects switches to at
@@ -502,29 +501,27 @@ void ClockSpine::create_rr_nodes_and_internal_edges_for_one_instance(ClockRRGrap
                                  clock_graph);
 
             // connect drive point to each half spine using a directed switch
-            rr_nodes[drive_node_idx].add_edge(left_node_idx, drive.switch_idx);
-            rr_nodes[drive_node_idx].add_edge(right_node_idx, drive.switch_idx);
+            rr_graph.create_edge(drive_node_idx, left_node_idx, RRSwitchId(drive.switch_idx));
+            rr_graph.create_edge(drive_node_idx, right_node_idx, RRSwitchId(drive.switch_idx));
         }
     }
 }
 
-int ClockSpine::create_chany_wire(int y_start,
-                                  int y_end,
-                                  int x,
-                                  int ptc_num,
-                                  e_direction direction,
-                                  std::vector<t_rr_node>& rr_nodes,
-                                  int num_segments) {
-    rr_nodes.emplace_back();
-    auto node_index = rr_nodes.size() - 1;
+RRNodeId ClockSpine::create_chany_wire(int y_start,
+                                       int y_end,
+                                       int x,
+                                       int ptc_num,
+                                       e_direction direction,
+                                       RRGraph& rr_graph,
+                                       int num_segments) {
+    RRNodeId node_index = rr_graph.create_node(CHANY);
 
-    rr_nodes[node_index].set_coordinates(x, y_start, x, y_end);
-    rr_nodes[node_index].set_type(CHANY);
-    rr_nodes[node_index].set_capacity(1);
-    rr_nodes[node_index].set_track_num(ptc_num);
-    rr_nodes[node_index].set_rc_index(find_create_rr_rc_data(
+    rr_graph.set_node_bounding_box(node_index, vtr::Rect<short>(x, y_start, x, y_end));
+    rr_graph.set_node_capacity(node_index, 1);
+    rr_graph.set_node_track_num(node_index, ptc_num);
+    rr_graph.set_node_rc_data_index(node_index, find_create_rr_rc_data(
         y_chan_wire.layer.r_metal, y_chan_wire.layer.c_metal));
-    rr_nodes[node_index].set_direction(direction);
+    rr_graph.set_node_direction(node_index, direction);
 
     short seg_index = 0;
     switch (direction) {
@@ -541,7 +538,7 @@ int ClockSpine::create_chany_wire(int y_start,
             VTR_ASSERT_MSG(false, "Unidentified direction type for clock rib");
             break;
     }
-    rr_nodes[node_index].set_cost_index(CHANX_COST_INDEX_START + num_segments + seg_index);
+    rr_graph.set_node_cost_index(node_index, CHANX_COST_INDEX_START + num_segments + seg_index);
 
     return node_index;
 }
@@ -549,8 +546,8 @@ int ClockSpine::create_chany_wire(int y_start,
 void ClockSpine::record_tap_locations(unsigned y_start,
                                       unsigned y_end,
                                       unsigned x,
-                                      int left_node_idx,
-                                      int right_node_idx,
+                                      const RRNodeId& left_node_idx,
+                                      const RRNodeId& right_node_idx,
                                       ClockRRGraphBuilder& clock_graph) {
     for (unsigned y = y_start + tap.offset; y <= y_end; y += tap.increment) {
         if (y < (y_start + drive.offset - 1)) {
diff --git a/vpr/src/route/clock_network_builders.h b/vpr/src/route/clock_network_builders.h
index c4db346ae..f768614d6 100644
--- a/vpr/src/route/clock_network_builders.h
+++ b/vpr/src/route/clock_network_builders.h
@@ -155,17 +155,17 @@ class ClockRib : public ClockNetwork {
     void create_segments(std::vector<t_segment_inf>& segment_inf);
     void create_rr_nodes_and_internal_edges_for_one_instance(ClockRRGraphBuilder& clock_graph,
                                                              int num_segments);
-    int create_chanx_wire(int x_start,
-                          int x_end,
-                          int y,
-                          int ptc_num,
-                          e_direction direction,
-                          std::vector<t_rr_node>& rr_nodes);
+    RRNodeId create_chanx_wire(int x_start,
+                               int x_end,
+                               int y,
+                               int ptc_num,
+                               e_direction direction,
+                               RRGraph& rr_graph);
     void record_tap_locations(unsigned x_start,
                               unsigned x_end,
                               unsigned y,
-                              int left_rr_node_idx,
-                              int right_rr_node_idx,
+                              const RRNodeId& left_rr_node_idx,
+                              const RRNodeId& right_rr_node_idx,
                               ClockRRGraphBuilder& clock_graph);
 };
 
@@ -211,18 +211,18 @@ class ClockSpine : public ClockNetwork {
     void create_segments(std::vector<t_segment_inf>& segment_inf);
     void create_rr_nodes_and_internal_edges_for_one_instance(ClockRRGraphBuilder& clock_graph,
                                                              int num_segments);
-    int create_chany_wire(int y_start,
-                          int y_end,
-                          int x,
-                          int ptc_num,
-                          e_direction direction,
-                          std::vector<t_rr_node>& rr_nodes,
-                          int num_segments);
+    RRNodeId create_chany_wire(int y_start,
+                               int y_end,
+                               int x,
+                               int ptc_num,
+                               e_direction direction,
+                               RRGraph& rr_graph,
+                               int num_segments);
     void record_tap_locations(unsigned y_start,
                               unsigned y_end,
                               unsigned x,
-                              int left_node_idx,
-                              int right_node_idx,
+                              const RRNodeId& left_node_idx,
+                              const RRNodeId& right_node_idx,
                               ClockRRGraphBuilder& clock_graph);
 };
 
diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp
index 32f86e2f8..6e5ded8b1 100644
--- a/vpr/src/route/rr_graph.cpp
+++ b/vpr/src/route/rr_graph.cpp
@@ -38,6 +38,8 @@
 
 #include "create_rr_graph.h"
 #include "write_xml_rr_graph_obj.h"
+#include "rr_graph_obj_util.h"
+#include "check_rr_graph_obj.h"
 
 //#define VERBOSE
 
@@ -133,7 +135,7 @@ static void build_unidir_rr_opins(const int i,
                                   t_rr_edge_info_set& created_rr_edges,
                                   bool* Fc_clipped,
                                   const t_rr_node_indices& L_rr_node_indices,
-                                  const std::vector<t_rr_node>& rr_nodes,
+                                  const RRGraph& rr_graph,
                                   const t_direct_inf* directs,
                                   const int num_directs,
                                   const t_clb_to_clb_directs* clb_to_clb_directs,
@@ -146,7 +148,7 @@ static int get_opin_direct_connections(int x,
                                        const RRNodeId& from_rr_node,
                                        t_rr_edge_info_set& rr_edges_to_create,
                                        const t_rr_node_indices& L_rr_node_indices,
-                                       const RRGraph& rr_nodes,
+                                       const RRGraph& rr_graph,
                                        const t_direct_inf* directs,
                                        const int num_directs,
                                        const t_clb_to_clb_directs* clb_to_clb_directs);
@@ -856,11 +858,11 @@ static void alloc_rr_switch_inf(t_arch_switch_fanin& arch_switch_fanins) {
         //
         //Note that since we don't store backward edge info in the RR graph we need to walk
         //the whole graph to get the per-switch-type fanin info
-        std::vector<vtr::flat_map<RRNodeId, int>> inward_switch_inf(device_ctx.rr_graph.nodes().size()); //[to_node][arch_switch] -> fanin
+        vtr::vector<RRNodeId, vtr::flat_map<int, int>> inward_switch_inf(device_ctx.rr_graph.nodes().size()); //[to_node][arch_switch] -> fanin
         for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) {
             for (const RREdgeId& iedge : device_ctx.rr_graph.node_out_edges(inode)) {
-                int iswitch = device_ctx.rr_graph.edge_switch(iedge);
-                const RRNodeId& to_node = device_ctx.rr_graph.edge_sink_node(iedge);
+                int iswitch = (int)size_t(device_ctx.rr_graph.edge_switch(iedge));
+                RRNodeId to_node = device_ctx.rr_graph.edge_sink_node(iedge);
 
                 if (inward_switch_inf[to_node].count(iswitch) == 0) {
                     inward_switch_inf[to_node][iswitch] = 0;
@@ -971,7 +973,7 @@ static void remap_rr_node_switch_indices(const t_arch_switch_fanin& switch_fanin
         for (const RREdgeId& iedge : device_ctx.rr_graph.node_out_edges(from_node)) {
             const RRNodeId& to_node = device_ctx.rr_graph.edge_sink_node(iedge);
             /* get the switch which this edge uses and its fanin */
-            int switch_index = device_ctx.rr_graph.edge_switch(iedge);
+            int switch_index = (int)size_t(device_ctx.rr_graph.edge_switch(iedge));
             int fanin = device_ctx.rr_graph.node_in_edges(to_node).size();
 
             if (switch_fanin[switch_index].count(UNDEFINED) == 1) {
@@ -983,7 +985,7 @@ static void remap_rr_node_switch_indices(const t_arch_switch_fanin& switch_fanin
 
             int rr_switch_index = itr->second;
 
-            device_ctx.rr_graph.set_edge_switch(iedge, rr_switch_index);
+            device_ctx.rr_graph.set_edge_switch(iedge, RRSwitchId(rr_switch_index));
         }
     }
 }
@@ -1291,7 +1293,7 @@ static void alloc_and_load_rr_graph(const int num_nodes,
                     bool clipped;
                     build_unidir_rr_opins(i, j, side, grid, Fc_out, max_chan_width,
                                           chan_details_x, chan_details_y, Fc_xofs, Fc_yofs,
-                                          rr_edges_to_create, &clipped, L_rr_node_indices, L_rr_node,
+                                          rr_edges_to_create, &clipped, L_rr_node_indices, const_cast<const RRGraph&>(rr_graph),
                                           directs, num_directs, clb_to_clb_directs, num_seg_types);
                     if (clipped) {
                         *Fc_clipped = true;
@@ -1392,7 +1394,7 @@ static void build_bidir_rr_opins(const int i,
         }
 
         RRNodeId node_index = rr_graph.find_node(i, j, OPIN, pin_index, side);
-        VTR_ASSERT(node_index >= 0);
+        VTR_ASSERT(true == rr_graph.valid_node_id(node_index));
 
         if (total_pin_Fc > 0) {
             get_bidir_opin_connections(i, j, pin_index,
@@ -1403,7 +1405,7 @@ static void build_bidir_rr_opins(const int i,
 
         /* Add in direct connections */
         get_opin_direct_connections(i, j, side, pin_index,
-                                    node_index, rr_edges_to_create, L_rr_node_indices, rr_nodes,
+                                    node_index, rr_edges_to_create, L_rr_node_indices, rr_graph,
                                     directs, num_directs, clb_to_clb_directs);
     }
 }
@@ -1466,7 +1468,7 @@ static void build_rr_sinks_sources(const int i,
 
     /* SINK and SOURCE-to-OPIN edges */
     for (int iclass = 0; iclass < num_class; ++iclass) {
-        RRNodeId inode = 0;
+        RRNodeId inode = RRNodeId::INVALID();
         if (class_inf[iclass].type == DRIVER) { /* SOURCE */
             inode = rr_graph.find_node(i, j, SOURCE, iclass);
 
@@ -1491,7 +1493,7 @@ static void build_rr_sinks_sources(const int i,
             rr_graph.set_node_cost_index(inode, SOURCE_COST_INDEX);
         } else { /* SINK */
             VTR_ASSERT(class_inf[iclass].type == RECEIVER);
-            inode = rr_graph.find_node(L_rr_node_indices, i, j, SINK, iclass);
+            inode = rr_graph.find_node(i, j, SINK, iclass);
 
             /* NOTE:  To allow route throughs through clbs, change the lines below to  *
              * make an edge from the input SINK to the output SOURCE.  Do for just the *
@@ -1508,7 +1510,7 @@ static void build_rr_sinks_sources(const int i,
         rr_graph.set_node_bounding_box(inode, vtr::Rect<short>(i, j, i + type->width - 1, j + type->height - 1));
         float R = 0.;
         float C = 0.;
-        rr_graph.set_node_rc_index(inode, find_create_rr_rc_data(R, C));
+        rr_graph.set_node_rc_data_index(inode, find_create_rr_rc_data(R, C));
         rr_graph.set_node_ptc_num(inode, iclass);
     }
 
@@ -1520,7 +1522,7 @@ static void build_rr_sinks_sources(const int i,
             for (e_side side : {TOP, BOTTOM, LEFT, RIGHT}) {
                 for (int ipin = 0; ipin < num_pins; ++ipin) {
                     if (type->pinloc[width_offset][height_offset][side][ipin]) {
-                        int inode;
+                        RRNodeId inode;
                         int iclass = pin_class[ipin];
 
                         if (class_inf[iclass].type == RECEIVER) {
@@ -1532,8 +1534,8 @@ static void build_rr_sinks_sources(const int i,
                             //Add info about the edge to be created
                             rr_edges_to_create.emplace_back(inode, to_node, delayless_switch);
 
-                            VTR_ASSERT(inode >= 0);
-                            rr_graph.set_node_cost_index(IPIN_COST_INDEX);
+                            VTR_ASSERT(true == rr_graph.valid_node_id(inode));
+                            rr_graph.set_node_cost_index(inode, IPIN_COST_INDEX);
 
                         } else {
                             VTR_ASSERT(class_inf[iclass].type == DRIVER);
@@ -1550,7 +1552,7 @@ static void build_rr_sinks_sources(const int i,
                         rr_graph.set_node_capacity(inode, 1);
                         float R = 0.;
                         float C = 0.;
-                        rr_graph.set_node_rc_index(inode, find_create_rr_rc_data(R, C));
+                        rr_graph.set_node_rc_data_index(inode, find_create_rr_rc_data(R, C));
                         rr_graph.set_node_ptc_num(inode, ipin);
 
                         //Note that we store the grid tile location and side where the pin is located,
@@ -1558,7 +1560,7 @@ static void build_rr_sinks_sources(const int i,
                         rr_graph.set_node_bounding_box(inode, vtr::Rect<short>(i + width_offset, j + height_offset, i + width_offset, j + height_offset));
                         rr_graph.set_node_side(inode, side);
 
-                        VTR_ASSERT(type->pinloc[width_offset][height_offset][L_rr_node[inode].side()][L_rr_node[inode].pin_num()]);
+                        VTR_ASSERT(type->pinloc[width_offset][height_offset][rr_graph.node_side(inode)][rr_graph.node_pin_num(inode)]);
                     }
                 }
             }
@@ -1741,24 +1743,23 @@ static void build_rr_chan(const int x_coord,
         }
 
         /* Edge arrays have now been built up.  Do everything else.  */
-        rr_graph.node[node].set_node_cost_index(node, cost_index_offset + seg_details[track].index());
+        rr_graph.set_node_cost_index(node, cost_index_offset + seg_details[track].index());
         rr_graph.set_node_capacity(node, 1); /* GLOBAL routing handled elsewhere */
 
         if (chan_type == CHANX) {
             rr_graph.set_node_bounding_box(node, vtr::Rect<short>(start, y_coord, end, y_coord));
         } else {
             VTR_ASSERT(chan_type == CHANY);
-            L_rr_node[node].set_coordinates(x_coord, start, x_coord, end);
             rr_graph.set_node_bounding_box(node, vtr::Rect<short>(x_coord, start, x_coord, end));
         }
 
         int length = end - start + 1;
         float R = length * seg_details[track].Rmetal();
         float C = length * seg_details[track].Cmetal();
-        rr_graph.set_node_rc_index(node, find_create_rr_rc_data(R, C));
+        rr_graph.set_node_rc_data_index(node, find_create_rr_rc_data(R, C));
 
         rr_graph.set_node_ptc_num(node, track);
-        rr_graph.set_node_type(node, chan_type);
+        VTR_ASSERT(chan_type == rr_graph.node_type(node));
         rr_graph.set_node_direction(node, seg_details[track].direction());
     }
 }
@@ -1804,14 +1805,14 @@ void alloc_and_load_edges(RRGraph& rr_graph,
             for (auto itr = edge_range.first; itr != edge_range.second; ++itr) {
                 VTR_ASSERT(itr->from_node == inode);
 
-                rr_graph.create_edge(inode, itr->to_node, itr->switch_type);
+                rr_graph.create_edge(inode, itr->to_node, RRSwitchId(itr->switch_type));
             }
         } else {
             //Add new edge incrementally
             //
             //This should occur relatively rarely (e.g. a backward bidir edge) so memory fragmentation shouldn't be a big problem
             for (auto itr = edge_range.first; itr != edge_range.second; ++itr) {
-                rr_graph.create_edge(inode, itr->to_node, itr->switch_type);
+                rr_graph.create_edge(inode, itr->to_node, RRSwitchId(itr->switch_type));
             }
         }
     }
@@ -2836,7 +2837,7 @@ static int get_opin_direct_connections(int x,
                                        const RRNodeId& from_rr_node,
                                        t_rr_edge_info_set& rr_edges_to_create,
                                        const t_rr_node_indices& L_rr_node_indices,
-                                       const RRGraph& rr_nodes,
+                                       const RRGraph& rr_graph,
                                        const t_direct_inf* directs,
                                        const int num_directs,
                                        const t_clb_to_clb_directs* clb_to_clb_directs) {
@@ -2925,7 +2926,7 @@ static int get_opin_direct_connections(int x,
                             }
                         } else {
                             //No side specified, get all candidates
-                            inodes = rr_graph.find_node(x + directs[i].x_offset, y + directs[i].y_offset,
+                            inodes = find_rr_graph_nodes(rr_graph, x + directs[i].x_offset, y + directs[i].y_offset,
                                                          IPIN, ipin);
                         }
 
@@ -3048,7 +3049,7 @@ static std::vector<bool> alloc_and_load_perturb_opins(const t_physical_tile_type
     return perturb_opins;
 }
 
-static RRNodeId pick_best_direct_connect_target_rr_node(const RRGraph& rr_nodes,
+static RRNodeId pick_best_direct_connect_target_rr_node(const RRGraph& rr_graph,
                                                         const RRNodeId& from_rr,
                                                         const std::vector<RRNodeId>& candidate_rr_nodes) {
     //With physically equivalent pins there may be multiple candidate rr nodes (which are equivalent)
@@ -3066,7 +3067,7 @@ static RRNodeId pick_best_direct_connect_target_rr_node(const RRGraph& rr_nodes,
     float best_dist = std::numeric_limits<float>::infinity();
     RRNodeId best_rr = RRNodeId::INVALID();
 
-    for (int to_rr : candidate_rr_nodes) {
+    for (const RRNodeId& to_rr : candidate_rr_nodes) {
         VTR_ASSERT(rr_graph.node_type(to_rr) == IPIN);
         float to_dist = std::abs(rr_graph.node_xlow(from_rr) - rr_graph.node_xlow(to_rr))
                         + std::abs(rr_graph.node_ylow(from_rr) - rr_graph.node_ylow(to_rr));
diff --git a/vpr/src/route/rr_graph2.cpp b/vpr/src/route/rr_graph2.cpp
index b861be721..21d69f296 100644
--- a/vpr/src/route/rr_graph2.cpp
+++ b/vpr/src/route/rr_graph2.cpp
@@ -67,7 +67,7 @@ static int get_unidir_track_to_chan_seg(const int from_track,
                                         const RRGraph& rr_graph,
                                         const t_chan_seg_details* seg_details,
                                         bool* Fs_clipped,
-                                        const int from_rr_node,
+                                        const RRNodeId& from_rr_node,
                                         t_rr_edge_info_set& rr_edges_to_create);
 
 static int get_track_to_chan_seg(const int from_track,
@@ -765,7 +765,7 @@ int get_unidir_opin_connections(const int chan,
     int* inc_muxes = nullptr;
     int* dec_muxes = nullptr;
     int num_inc_muxes, num_dec_muxes, iconn;
-    int inc_inode_index, dec_inode_index;
+    RRNodeId inc_inode_index, dec_inode_index;
     int inc_mux, dec_mux;
     int inc_track, dec_track;
     int x, y;
@@ -809,8 +809,8 @@ int get_unidir_opin_connections(const int chan,
         dec_track = dec_muxes[dec_mux];
 
         /* Figure the inodes of those muxes */
-        inc_inode_index = rr_graph.find_node(x, y, chan_type, inc_track);
-        dec_inode_index = rr_graph.find_node(x, y, chan_type, dec_track);
+        inc_inode_index = rr_graph.find_node(chan, seg, chan_type, inc_track);
+        dec_inode_index = rr_graph.find_node(chan, seg, chan_type, dec_track);
 
         if (inc_inode_index == RRNodeId::INVALID() || dec_inode_index == RRNodeId::INVALID()) {
             continue;
@@ -1069,24 +1069,24 @@ static void load_chan_rr_indices(const int max_chan_width,
             int y = (type == CHANX ? chan : seg);
             const t_chan_seg_details* seg_details = chan_details[x][y].data();
 
-            for (unsigned track = 0; track < num_chans - 1; ++track) {
+            for (int track = 0; track < num_chans - 1; ++track) {
                 if (seg_details[track].length() <= 0)
                     continue;
 
                 int start = get_seg_start(seg_details, track, chan, seg);
                  
-                /* If this segment does not start from the current position, we do not allocate any nodes */
-                if (start != seg) {
-                    continue;
+                /* We give a fake coordinator here, to ease the downstream builder */
+                short xlow = chan;
+                short ylow = start;
+                RRNodeId node = rr_graph.find_node(xlow, ylow, type, track);
+                if (false == rr_graph.valid_node_id(node)) {
+  
+                    RRNodeId new_node = rr_graph.create_node(type);
+                    rr_graph.set_node_bounding_box(new_node, vtr::Rect<short>(xlow, ylow, xlow, ylow));
+                    rr_graph.set_node_track_num(new_node, track);
+ 
+                    (*index)++;
                 }
-
-                RRNodeId node = rr_graph.create_node(type);
-                short xlow = x;
-                short ylow = y;
-                short xhigh = (type == CHANX ? xlow + seg_details[track].length() - 1 : xlow);
-                short yhigh = (type == CHANY ? ylow + seg_details[track].length() - 1 : ylow);
-                rr_graph.set_node_bounding_box(node, vtr::Rect<short>(xlow, ylow, xhigh, yhigh));
-                rr_graph.set_node_track_num(node, track);
             }
         }
     }
@@ -1108,13 +1108,13 @@ static void load_block_rr_indices(const DeviceGrid& grid,
                     auto class_type = type->class_inf[iclass].type;
                     if (class_type == DRIVER) {
                         RRNodeId node = rr_graph.create_node(SOURCE);
-                        rr_graph.set_node_bounding_box(node, vtr::Rect<size_t>(x, y, x, y));
-                        rr_graph.set_node_class_num(iclass);
+                        rr_graph.set_node_bounding_box(node, vtr::Rect<short>(x, y, x, y));
+                        rr_graph.set_node_class_num(node, iclass);
                     } else {
                         VTR_ASSERT(class_type == RECEIVER);
                         RRNodeId node = rr_graph.create_node(SINK);
-                        rr_graph.set_node_bounding_box(node, vtr::Rect<size_t>(x, y, x, y));
-                        rr_graph.set_node_class_num(iclass);
+                        rr_graph.set_node_bounding_box(node, vtr::Rect<short>(x, y, x, y));
+                        rr_graph.set_node_class_num(node, iclass);
                     }
                     ++(*index);
                 }
@@ -1132,15 +1132,15 @@ static void load_block_rr_indices(const DeviceGrid& grid,
 
                                     if (class_type == DRIVER) {
                                         RRNodeId node = rr_graph.create_node(OPIN);
-                                        rr_graph.set_node_bounding_box(node, vtr::Rect<size_t>(xtile, ytile, xtile, ytile));
-                                        rr_graph.set_node_pin_num(ipin);
-                                        rr_graph.set_node_side(side);
+                                        rr_graph.set_node_bounding_box(node, vtr::Rect<short>(x_tile, y_tile, x_tile, y_tile));
+                                        rr_graph.set_node_pin_num(node, ipin);
+                                        rr_graph.set_node_side(node, side);
                                     } else {
                                         VTR_ASSERT(class_type == RECEIVER);
                                         RRNodeId node = rr_graph.create_node(IPIN);
-                                        rr_graph.set_node_bounding_box(node, vtr::Rect<size_t>(xtile, ytile, xtile, ytile));
-                                        rr_graph.set_node_pin_num(ipin);
-                                        rr_graph.set_node_side(side);
+                                        rr_graph.set_node_bounding_box(node, vtr::Rect<short>(x_tile, y_tile, x_tile, y_tile));
+                                        rr_graph.set_node_pin_num(node, ipin);
+                                        rr_graph.set_node_side(node, side);
                                     }
                                     ++(*index);
                                 }
@@ -1162,7 +1162,7 @@ static void load_block_rr_indices(const DeviceGrid& grid,
              * this can avoid runtime cost to rebuild the fast look-up inside RRGraph object
              */
             if ( (grid[x][y].type->height == height_offset && grid[x][y].type->width == width_offset)
-              && (0 != height_offset && 0 != width_offset) ) {
+              && (0 != height_offset || 0 != width_offset) ) {
                 int root_x = x - width_offset;
                 int root_y = y - height_offset;
 
@@ -1176,12 +1176,12 @@ static void load_block_rr_indices(const DeviceGrid& grid,
                     if (class_type == DRIVER) {
                         RRNodeId node = rr_graph.find_node(root_x, root_y, SOURCE, iclass);
                         /* Update the internal look-up so that we can find the SOURCE/SINK node using their offset coordinates */
-                        rr_graph.set_node_bounding_box(node, vtr::Rect<size_t>(root_x, root_y, x, y));
+                        rr_graph.set_node_bounding_box(node, vtr::Rect<short>(root_x, root_y, x, y));
                     } else {
                         VTR_ASSERT(class_type == RECEIVER);
                         RRNodeId node = rr_graph.find_node(root_x, root_y, SINK, iclass);
                         /* Update the internal look-up so that we can find the SOURCE/SINK node using their offset coordinates */
-                        rr_graph.set_node_bounding_box(node, vtr::Rect<size_t>(root_x, root_y, x, y));
+                        rr_graph.set_node_bounding_box(node, vtr::Rect<short>(root_x, root_y, x, y));
                     }
                 }
             }
@@ -1454,7 +1454,7 @@ int get_track_to_pins(int seg,
                     /* Check there is a connection and Fc map isn't wrong */
                     /*int to_node = get_rr_node_index(L_rr_node_indices, x + width_offset, y + height_offset, IPIN, ipin, side);*/
                     RRNodeId to_node = rr_graph.find_node(x, y, IPIN, ipin, side);
-                    if (to_node >= 0) {
+                    if (rr_graph.valid_node_id(to_node)) {
                         rr_edges_to_create.emplace_back(from_rr_node, to_node, wire_to_ipin_switch);
                         ++num_conn;
                     }
diff --git a/vpr/src/route/rr_graph2.h b/vpr/src/route/rr_graph2.h
index 55791b8d4..6aa5cae68 100644
--- a/vpr/src/route/rr_graph2.h
+++ b/vpr/src/route/rr_graph2.h
@@ -15,7 +15,7 @@ enum e_seg_details_type {
 };
 
 struct t_rr_edge_info {
-    t_rr_edge_info(const RRNodeId& from, const RRNodeId& to, const short& type) noexcept
+    t_rr_edge_info(RRNodeId from, RRNodeId to, short type) noexcept
         : from_node(from)
         , to_node(to)
         , switch_type(type) {}
@@ -25,11 +25,19 @@ struct t_rr_edge_info {
     short switch_type = OPEN;
 
     friend bool operator<(const t_rr_edge_info& lhs, const t_rr_edge_info& rhs) {
-        return std::tie(size_t(lhs.from_node), size_t(lhs.to_node), lhs.switch_type) < std::tie(size_t(rhs.from_node), size_t(rhs.to_node), rhs.switch_type);
+        size_t lhs_from_node = size_t(lhs.from_node);
+        size_t lhs_to_node = size_t(lhs.to_node);
+        size_t rhs_from_node = size_t(rhs.from_node);
+        size_t rhs_to_node = size_t(rhs.to_node);
+        return std::tie(lhs_from_node, lhs_to_node, lhs.switch_type) < std::tie(rhs_from_node, rhs_to_node, rhs.switch_type);
     }
 
     friend bool operator==(const t_rr_edge_info& lhs, const t_rr_edge_info& rhs) {
-        return std::tie(size_t(lhs.from_node), size_t(lhs.to_node), lhs.switch_type) == std::tie(size_t(rhs.from_node), size_t(rhs.to_node), rhs.switch_type);
+        size_t lhs_from_node = size_t(lhs.from_node);
+        size_t lhs_to_node = size_t(lhs.to_node);
+        size_t rhs_from_node = size_t(rhs.from_node);
+        size_t rhs_to_node = size_t(rhs.to_node);
+        return std::tie(lhs_from_node, lhs_to_node, lhs.switch_type) == std::tie(rhs_from_node, rhs_to_node, rhs.switch_type);
     }
 };
 
@@ -145,10 +153,10 @@ bool is_sblock(const int chan,
 int get_bidir_opin_connections(const int i,
                                const int j,
                                const int ipin,
-                               const int from_rr_node,
+                               const RRNodeId& from_rr_node,
                                t_rr_edge_info_set& rr_edges_to_create,
                                const t_pin_to_track_lookup& opin_to_track_map,
-                               const t_rr_node_indices& L_rr_node_indices,
+                               const RRGraph& rr_graph,
                                const t_chan_details& chan_details_x,
                                const t_chan_details& chan_details_y);
 
diff --git a/vpr/src/route/rr_graph_clock.cpp b/vpr/src/route/rr_graph_clock.cpp
index fa9f09e34..3d3a8c27a 100644
--- a/vpr/src/route/rr_graph_clock.cpp
+++ b/vpr/src/route/rr_graph_clock.cpp
@@ -71,7 +71,7 @@ void ClockRRGraphBuilder::add_rr_switches_and_map_to_nodes(size_t node_start_idx
     auto& rr_graph = device_ctx.rr_graph;
 
     // Check to see that clock nodes were sucessfully appended to rr_nodes
-    VTR_ASSERT(true == rr_graph.valid_node_id(RRNodeId(node_start_idx));
+    VTR_ASSERT(true == rr_graph.valid_node_id(RRNodeId(node_start_idx)));
 
     std::unordered_map<int, int> arch_switch_to_rr_switch;
 
@@ -79,7 +79,7 @@ void ClockRRGraphBuilder::add_rr_switches_and_map_to_nodes(size_t node_start_idx
     for (size_t node_idx = node_start_idx; node_idx < rr_graph.nodes().size(); node_idx++) {
         const RRNodeId& from_node = RRNodeId(node_idx);
         for (const RREdgeId& edge_idx : rr_graph.node_out_edges(from_node)) {
-            int arch_switch_idx = rr_graph.edge_switch(edge_idx);
+            int arch_switch_idx = (int)size_t(rr_graph.edge_switch(edge_idx));
 
             int rr_switch_idx;
             auto itter = arch_switch_to_rr_switch.find(arch_switch_idx);
@@ -92,7 +92,7 @@ void ClockRRGraphBuilder::add_rr_switches_and_map_to_nodes(size_t node_start_idx
                 rr_switch_idx = itter->second;
             }
 
-            rr_graph.set_edge_switch(edge_idx, rr_switch_idx);
+            rr_graph.set_edge_switch(edge_idx, RRSwitchId(rr_switch_idx));
         }
     }
 
@@ -148,7 +148,7 @@ void SwitchPoint::insert_node_idx(int x, int y, const RRNodeId& node_idx) {
     locations.insert({x, y});
 }
 
-std::vector<int> ClockRRGraphBuilder::get_rr_node_indices_at_switch_location(std::string clock_name,
+std::vector<RRNodeId> ClockRRGraphBuilder::get_rr_node_indices_at_switch_location(std::string clock_name,
                                                                              std::string switch_point_name,
                                                                              int x,
                                                                              int y) const {
@@ -161,7 +161,7 @@ std::vector<int> ClockRRGraphBuilder::get_rr_node_indices_at_switch_location(std
     return switch_points.get_rr_node_indices_at_location(switch_point_name, x, y);
 }
 
-std::vector<int> SwitchPoints::get_rr_node_indices_at_location(std::string switch_point_name,
+std::vector<RRNodeId> SwitchPoints::get_rr_node_indices_at_location(std::string switch_point_name,
                                                                int x,
                                                                int y) const {
     auto itter = switch_point_name_to_switch_location.find(switch_point_name);
@@ -170,11 +170,11 @@ std::vector<int> SwitchPoints::get_rr_node_indices_at_location(std::string switc
     VTR_ASSERT(itter != switch_point_name_to_switch_location.end());
 
     auto& switch_point = itter->second;
-    std::vector<int> rr_node_indices = switch_point.get_rr_node_indices_at_location(x, y);
+    std::vector<RRNodeId> rr_node_indices = switch_point.get_rr_node_indices_at_location(x, y);
     return rr_node_indices;
 }
 
-std::vector<int> SwitchPoint::get_rr_node_indices_at_location(int x, int y) const {
+std::vector<RRNodeId> SwitchPoint::get_rr_node_indices_at_location(int x, int y) const {
     // assert that switch is connected to nodes at the location
     VTR_ASSERT(!rr_node_indices[x][y].empty());
 
diff --git a/vpr/src/route/rr_graph_clock.h b/vpr/src/route/rr_graph_clock.h
index df6aff1b9..727c9865c 100644
--- a/vpr/src/route/rr_graph_clock.h
+++ b/vpr/src/route/rr_graph_clock.h
@@ -13,7 +13,7 @@
 #include "clock_network_builders.h"
 #include "clock_connection_builders.h"
 
-#include "rr_graph_obj_fwd.h"
+#include "rr_graph_fwd.h"
 
 class ClockNetwork;
 class ClockConnection;
@@ -31,12 +31,12 @@ class SwitchPoint {
     std::set<std::pair<int, int>> locations; // x,y
   public:
     /** Getters **/
-    std::vector<int> get_rr_node_indices_at_location(int x, int y) const;
+    std::vector<RRNodeId> get_rr_node_indices_at_location(int x, int y) const;
 
     std::set<std::pair<int, int>> get_switch_locations() const;
 
     /** Setters **/
-    void insert_node_idx(int x, int y, int node_idx);
+    void insert_node_idx(int x, int y, const RRNodeId& node_idx);
 };
 
 class SwitchPoints {
@@ -52,14 +52,14 @@ class SwitchPoints {
     /* Example: x,y = middle of the chip, switch_point_name == name of main drive
      * of global clock spine, returns the rr_nodes of all the clock spines that
      * start the newtork there*/
-    std::vector<int> get_rr_node_indices_at_location(std::string switch_point_name,
+    std::vector<RRNodeId> get_rr_node_indices_at_location(std::string switch_point_name,
                                                      int x,
                                                      int y) const;
 
     std::set<std::pair<int, int>> get_switch_locations(std::string switch_point_name) const;
 
     /** Setters **/
-    void insert_switch_node_idx(std::string switch_point_name, int x, int y, int node_idx);
+    void insert_switch_node_idx(std::string switch_point_name, int x, int y, const RRNodeId& node_idx);
 };
 
 class ClockRRGraphBuilder {
@@ -80,10 +80,10 @@ class ClockRRGraphBuilder {
                              std::string switch_point_name,
                              int x,
                              int y,
-                             int node_index);
+                             const RRNodeId& node_index);
 
     /* Returns the rr_node idx of the switch at location {x, y} */
-    std::vector<int> get_rr_node_indices_at_switch_location(std::string clock_name,
+    std::vector<RRNodeId> get_rr_node_indices_at_switch_location(std::string clock_name,
                                                             std::string switch_point_name,
                                                             int x,
                                                             int y) const;
diff --git a/vpr/src/route/rr_graph_indexed_data.cpp b/vpr/src/route/rr_graph_indexed_data.cpp
index bc73a1511..3982bcb64 100644
--- a/vpr/src/route/rr_graph_indexed_data.cpp
+++ b/vpr/src/route/rr_graph_indexed_data.cpp
@@ -347,7 +347,7 @@ static void load_rr_indexed_data_T_values(int index_start,
             RRNodeId to_node_index = device_ctx.rr_graph.edge_sink_node(iedge);
             /* want to get C/R/Tdel/Cinternal of switches that connect this track segment to other track segments */
             if (device_ctx.rr_graph.node_type(to_node_index) == CHANX || device_ctx.rr_graph.node_type(to_node_index) == CHANY) {
-                int switch_index = device_ctx.rr_graph.edge_switch(iedge);
+                int switch_index = (int)size_t(device_ctx.rr_graph.edge_switch(iedge));
                 avg_switch_R += device_ctx.rr_switch_inf[switch_index].R;
                 avg_switch_T += device_ctx.rr_switch_inf[switch_index].Tdel;
                 avg_switch_Cinternal += device_ctx.rr_switch_inf[switch_index].Cinternal;
diff --git a/vpr/src/route/rr_graph_reader.cpp b/vpr/src/route/rr_graph_reader.cpp
index ccaf6af1b..51dff1bfe 100644
--- a/vpr/src/route/rr_graph_reader.cpp
+++ b/vpr/src/route/rr_graph_reader.cpp
@@ -44,6 +44,9 @@
 #include "vpr_utils.h"
 #include "vpr_error.h"
 
+#include "rr_graph_obj.h"
+#include "check_rr_graph_obj.h"
+
 #include "rr_graph_reader.h"
 
 /*********************** Subroutines local to this module *******************/
@@ -281,7 +284,7 @@ void process_seg_id(pugi::xml_node parent, const pugiutil::loc_data& loc_data) {
 
     while (rr_node) {
         id = get_attribute(rr_node, "id", loc_data).as_int();
-        auto& node = RRNodeId(id);
+        RRNodeId node = RRNodeId(id);
 
         segmentSubnode = get_single_child(rr_node, "segment", loc_data, pugiutil::OPTIONAL);
         if (segmentSubnode) {
@@ -310,18 +313,18 @@ void process_nodes(pugi::xml_node parent, const pugiutil::loc_data& loc_data) {
         int inode = get_attribute(rr_node, "id", loc_data).as_int();
         t_rr_type node_type = NUM_RR_TYPES;
 
-        const char* node_type = get_attribute(rr_node, "type", loc_data).as_string();
-        if (strcmp(node_type, "CHANX") == 0) {
+        const char* node_type_str = get_attribute(rr_node, "type", loc_data).as_string();
+        if (strcmp(node_type_str, "CHANX") == 0) {
             node_type = CHANX;
-        } else if (strcmp(node_type, "CHANY") == 0) {
+        } else if (strcmp(node_type_str, "CHANY") == 0) {
             node_type = CHANY;
-        } else if (strcmp(node_type, "SOURCE") == 0) {
+        } else if (strcmp(node_type_str, "SOURCE") == 0) {
             node_type = SOURCE;
-        } else if (strcmp(node_type, "SINK") == 0) {
+        } else if (strcmp(node_type_str, "SINK") == 0) {
             node_type = SINK;
-        } else if (strcmp(node_type, "OPIN") == 0) {
+        } else if (strcmp(node_type_str, "OPIN") == 0) {
             node_type = OPIN;
-        } else if (strcmp(node_type, "IPIN") == 0) {
+        } else if (strcmp(node_type_str, "IPIN") == 0) {
             node_type = IPIN;
         } else {
             VPR_FATAL_ERROR(VPR_ERROR_OTHER,
@@ -371,7 +374,7 @@ void process_nodes(pugi::xml_node parent, const pugiutil::loc_data& loc_data) {
             device_ctx.rr_graph.set_node_side(node, side);
         }
 
-        device_ctx.rr_graph.set_node_bouding_box(node, vtr::Rect<short>(x1, y1, x2, y2)); 
+        device_ctx.rr_graph.set_node_bounding_box(node, vtr::Rect<short>(x1, y1, x2, y2)); 
         device_ctx.rr_graph.set_node_ptc_num(node, get_attribute(locSubnode, "ptc", loc_data).as_int());
 
         //-------
@@ -495,7 +498,7 @@ void process_edges(pugi::xml_node parent, const pugiutil::loc_data& loc_data, in
             while (edges_meta) {
                 auto key = get_attribute(edges_meta, "name", loc_data).as_string();
 
-                vpr::add_rr_edge_metadata(source_node, sink_node, switch_id,
+                vpr::add_rr_edge_metadata(size_t(source_node), size_t(sink_node), switch_id,
                                           key, edges_meta.child_value());
 
                 edges_meta = edges_meta.next_sibling(edges_meta.name());
@@ -899,7 +902,7 @@ void set_cost_indices(pugi::xml_node parent, const pugiutil::loc_data& loc_data,
             if (attribute) {
                 int seg_id = get_attribute(segmentSubnode, "segment_id", loc_data).as_int(0);
                 if (is_global_graph) {
-                    device_ctx.rr_graph.set_node_cost_index(0);
+                    device_ctx.rr_graph.set_node_cost_index(inode, 0);
                 } else if (device_ctx.rr_graph.node_type(inode) == CHANX) {
                     device_ctx.rr_graph.set_node_cost_index(inode, CHANX_COST_INDEX_START + seg_id);
                 } else if (device_ctx.rr_graph.node_type(inode) == CHANY) {

From 6bd71f198e4405c643bf8013d8c86ef805b6b8ae Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 3 Feb 2020 21:05:50 -0700
Subject: [PATCH 091/645] keep debugging the rr_graph generator. Definitely
 should rework the RREdge creation functions

---
 vpr/src/device/rr_graph_obj.cpp        | 14 ++--
 vpr/src/device/rr_graph_obj.h          |  4 +-
 vpr/src/route/router_delay_profiling.h |  2 +-
 vpr/src/route/rr_graph.cpp             | 88 +++++++++++++++++++++++---
 4 files changed, 92 insertions(+), 16 deletions(-)

diff --git a/vpr/src/device/rr_graph_obj.cpp b/vpr/src/device/rr_graph_obj.cpp
index 37ab22729..588edb17e 100644
--- a/vpr/src/device/rr_graph_obj.cpp
+++ b/vpr/src/device/rr_graph_obj.cpp
@@ -370,21 +370,24 @@ RRNodeId RRGraph::find_node(const short& x, const short& y, const t_rr_type& typ
 
     /* Check if x, y, type and ptc, side is valid */
     if ((x < 0)                                          /* See if x is smaller than the index of first element */
-        || (size_t(x) > node_lookup_.dim_size(0) - 1)) { /* See if x is large than the index of last element */
+        || (size_t(x) > node_lookup_.dim_size(0) - 1) /* See if x is large than the index of last element */
+        || (0 == node_lookup_.dim_size(0))) { /* See if x is large than the index of last element */
         /* Return a zero range! */
         return RRNodeId::INVALID();
     }
 
     /* Check if x, y, type and ptc, side is valid */
     if ((y < 0)                                          /* See if y is smaller than the index of first element */
-        || (size_t(y) > node_lookup_.dim_size(1) - 1)) { /* See if y is large than the index of last element */
+        || (size_t(y) > node_lookup_.dim_size(1) - 1)  /* See if y is large than the index of last element */
+        || (0 == node_lookup_.dim_size(1))) { /* See if y is large than the index of last element */
         /* Return a zero range! */
         return RRNodeId::INVALID();
     }
 
     /* Check if x, y, type and ptc, side is valid */
     /* itype is always larger than -1, we can skip checking */
-    if (itype > node_lookup_.dim_size(2) - 1) { /* See if type is large than the index of last element */
+    if ( (itype > node_lookup_.dim_size(2) - 1)  /* See if type is large than the index of last element */
+      || (0 == node_lookup_.dim_size(2))) { /* See if type is large than the index of last element */
         /* Return a zero range! */
         return RRNodeId::INVALID();
     }
@@ -399,7 +402,8 @@ RRNodeId RRGraph::find_node(const short& x, const short& y, const t_rr_type& typ
 
     /* Check if x, y, type and ptc, side is valid */
     /* iside is always larger than -1, we can skip checking */
-    if (iside > node_lookup_[x][y][type][ptc].size() - 1) { /* See if side is large than the index of last element */
+    if ((iside > node_lookup_[x][y][type][ptc].size() - 1) /* See if side is large than the index of last element */
+       || (0 == node_lookup_[x][y][type][ptc].size()) ) { /* See if side is large than the index of last element */
         /* Return a zero range! */
         return RRNodeId::INVALID();
     }
@@ -857,7 +861,7 @@ RRNodeId RRGraph::create_node(const t_rr_type& type) {
 RREdgeId RRGraph::create_edge(const RRNodeId& source, const RRNodeId& sink, const RRSwitchId& switch_id) {
     VTR_ASSERT(valid_node_id(source));
     VTR_ASSERT(valid_node_id(sink));
-    //VTR_ASSERT(valid_switch_id(switch_id));
+    VTR_ASSERT(valid_switch_id(switch_id));
 
     /* Allocate an ID */
     RREdgeId edge_id = RREdgeId(num_edges_);
diff --git a/vpr/src/device/rr_graph_obj.h b/vpr/src/device/rr_graph_obj.h
index fedc90612..a81a5b301 100644
--- a/vpr/src/device/rr_graph_obj.h
+++ b/vpr/src/device/rr_graph_obj.h
@@ -725,6 +725,9 @@ class RRGraph {
 
     /* top-level function to free, should be called when to delete a RRGraph */
     void clear();
+    
+    /* Due to the rr_graph builder, we have to make this method public!!!! */
+    void clear_switches();
 
   public: /* Type implementations */
     /*
@@ -776,7 +779,6 @@ class RRGraph {
   private: /* Internal free functions */
     void clear_nodes();
     void clear_edges();
-    void clear_switches();
     void clear_segments();
 
   private: /* Graph Compression related */
diff --git a/vpr/src/route/router_delay_profiling.h b/vpr/src/route/router_delay_profiling.h
index 63b8bed65..0bd5e3296 100644
--- a/vpr/src/route/router_delay_profiling.h
+++ b/vpr/src/route/router_delay_profiling.h
@@ -15,7 +15,7 @@ class RouterDelayProfiler {
     const RouterLookahead* router_lookahead_;
 };
 
-vtr::vector<RRNodeId, float> calculate_all_path_delays_from_rr_node(int src_rr_node, const t_router_opts& router_opts);
+vtr::vector<RRNodeId, float> calculate_all_path_delays_from_rr_node(const RRNodeId& src_rr_node, const t_router_opts& router_opts);
 
 void alloc_routing_structs(t_chan_width chan_width,
                            const t_router_opts& router_opts,
diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp
index 6e5ded8b1..a801098c6 100644
--- a/vpr/src/route/rr_graph.cpp
+++ b/vpr/src/route/rr_graph.cpp
@@ -251,6 +251,11 @@ static void alloc_and_load_rr_switch_inf(const int num_arch_switches,
                                          const int wire_to_arch_ipin_switch,
                                          int* wire_to_rr_ipin_switch);
 
+static 
+t_rr_switch_inf create_rr_switch_from_arch_switch(int arch_switch_idx,
+                                                  const float R_minW_nmos,
+                                                  const float R_minW_pmos);
+
 static void remap_rr_node_switch_indices(const t_arch_switch_fanin& switch_fanin);
 
 static void load_rr_switch_inf(const int num_arch_switches, const float R_minW_nmos, const float R_minW_pmos, const t_arch_switch_fanin& switch_fanin);
@@ -704,6 +709,20 @@ static void build_rr_graph(const t_graph_type graph_type,
     /* END OPIN MAP */
 
     bool Fc_clipped = false;
+
+    /* Draft the switches as internal data of RRGraph object
+     * These are temporary switches copied from arch switches
+     * We use them to build the edges 
+     * We will reset all the switches in the function 
+     *   alloc_and_load_rr_switch_inf()
+     */
+    device_ctx.rr_graph.reserve_switches(device_ctx.num_arch_switches);
+    // Create the switches
+    for (size_t iswitch = 0; iswitch < device_ctx.num_arch_switches; ++iswitch) {
+        const t_rr_switch_inf& temp_rr_switch = create_rr_switch_from_arch_switch(iswitch, R_minW_nmos, R_minW_pmos);
+        device_ctx.rr_graph.create_switch(temp_rr_switch);
+    }
+
     alloc_and_load_rr_graph(device_ctx.rr_graph.nodes().size(), device_ctx.rr_graph, segment_inf.size(),
                             chan_details_x, chan_details_y,
                             track_to_pin_lookup, opin_to_track_map,
@@ -732,13 +751,34 @@ static void build_rr_graph(const t_graph_type graph_type,
         }
     }
 
+    /* First time to build edges so that we can remap the architecture switch to rr_switch
+     * This is a must-do before function alloc_and_load_rr_switch_inf() 
+     */
+    device_ctx.rr_graph.rebuild_node_edges();
+
     /* Allocate and load routing resource switches, which are derived from the switches from the architecture file,
      * based on their fanin in the rr graph. This routine also adjusts the rr nodes to point to these new rr switches */
     alloc_and_load_rr_switch_inf(num_arch_switches, R_minW_nmos, R_minW_pmos, wire_to_arch_ipin_switch, wire_to_rr_ipin_switch);
 
-    //Partition the rr graph edges for efficient access to configurable/non-configurable
-    //edge subsets. Must be done after RR switches have been allocated
-    device_ctx.rr_graph.rebuild_node_edges();
+    //Save the channel widths for the newly constructed graph
+    device_ctx.chan_width = nodes_per_chan;
+
+    rr_graph_externals(segment_inf, max_chan_width,
+                       *wire_to_rr_ipin_switch, base_cost_type);
+
+    /* Rebuild the link between RRGraph node and segments 
+     * Should be called only AFTER the function
+     * rr_graph_externals()
+     */
+    for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) {
+        if ( (CHANX != device_ctx.rr_graph.node_type(inode))
+          && (CHANY != device_ctx.rr_graph.node_type(inode)) ) {
+            continue;
+        }
+        short irc_data = device_ctx.rr_graph.node_cost_index(inode);
+        short iseg = device_ctx.rr_indexed_data[irc_data].seg_index;
+        device_ctx.rr_graph.set_node_segment(inode, RRSegmentId(iseg));
+    }
 
     /* Essential check for rr_graph, build look-up and  */
     if (false == device_ctx.rr_graph.validate()) {
@@ -749,12 +789,6 @@ static void build_rr_graph(const t_graph_type graph_type,
                   "Fundamental errors occurred when validating rr_graph object!\n");
     }
 
-    //Save the channel widths for the newly constructed graph
-    device_ctx.chan_width = nodes_per_chan;
-
-    rr_graph_externals(segment_inf, max_chan_width,
-                       *wire_to_rr_ipin_switch, base_cost_type);
-
     check_rr_graph(graph_type, grid, types);
     /* Error out if advanced checker of rr_graph fails */
     if (false == check_rr_graph(device_ctx.rr_graph)) {
@@ -922,6 +956,7 @@ static void load_rr_switch_inf(const int num_arch_switches, const float R_minW_n
     }
   
     /* Create switches as internal data of RRGraph object */
+    device_ctx.rr_graph.clear_switches();
     device_ctx.rr_graph.reserve_switches(device_ctx.rr_switch_inf.size());
     // Create the switches
     for (size_t iswitch = 0; iswitch < device_ctx.rr_switch_inf.size(); ++iswitch) {
@@ -930,6 +965,41 @@ static void load_rr_switch_inf(const int num_arch_switches, const float R_minW_n
 
 }
 
+static 
+t_rr_switch_inf create_rr_switch_from_arch_switch(int arch_switch_idx,
+                                                  const float R_minW_nmos,
+                                                  const float R_minW_pmos) {
+    auto& device_ctx = g_vpr_ctx.mutable_device();
+    t_rr_switch_inf rr_switch_inf;
+
+    /* figure out, by looking at the arch switch's Tdel map, what the delay of the new
+     * rr switch should be */
+    double rr_switch_Tdel = device_ctx.arch_switch_inf[arch_switch_idx].Tdel(0);
+
+    /* copy over the arch switch to rr_switch_inf[rr_switch_idx], but with the changed Tdel value */
+    rr_switch_inf.set_type(device_ctx.arch_switch_inf[arch_switch_idx].type());
+    rr_switch_inf.R = device_ctx.arch_switch_inf[arch_switch_idx].R;
+    rr_switch_inf.Cin = device_ctx.arch_switch_inf[arch_switch_idx].Cin;
+    rr_switch_inf.Cinternal = device_ctx.arch_switch_inf[arch_switch_idx].Cinternal;
+    rr_switch_inf.Cout = device_ctx.arch_switch_inf[arch_switch_idx].Cout;
+    rr_switch_inf.Tdel = rr_switch_Tdel;
+    rr_switch_inf.mux_trans_size = device_ctx.arch_switch_inf[arch_switch_idx].mux_trans_size;
+    if (device_ctx.arch_switch_inf[arch_switch_idx].buf_size_type == BufferSize::AUTO) {
+        //Size based on resistance
+        rr_switch_inf.buf_size = trans_per_buf(device_ctx.arch_switch_inf[arch_switch_idx].R, R_minW_nmos, R_minW_pmos);
+    } else {
+        VTR_ASSERT(device_ctx.arch_switch_inf[arch_switch_idx].buf_size_type == BufferSize::ABSOLUTE);
+        //Use the specified size
+        rr_switch_inf.buf_size = device_ctx.arch_switch_inf[arch_switch_idx].buf_size;
+    }
+    rr_switch_inf.name = device_ctx.arch_switch_inf[arch_switch_idx].name;
+    rr_switch_inf.power_buffer_type = device_ctx.arch_switch_inf[arch_switch_idx].power_buffer_type;
+    rr_switch_inf.power_buffer_size = device_ctx.arch_switch_inf[arch_switch_idx].power_buffer_size;
+
+    return rr_switch_inf;
+}
+
+
 void load_rr_switch_from_arch_switch(int arch_switch_idx,
                                      int rr_switch_idx,
                                      int fanin,

From b6a2013565cd12106bf8ae41ac9af89fc507151d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 3 Feb 2020 21:50:02 -0700
Subject: [PATCH 092/645] minor bug fix for RRGraph data structure

---
 vpr/src/device/rr_graph_obj.cpp | 1 +
 1 file changed, 1 insertion(+)

diff --git a/vpr/src/device/rr_graph_obj.cpp b/vpr/src/device/rr_graph_obj.cpp
index 588edb17e..cf616538c 100644
--- a/vpr/src/device/rr_graph_obj.cpp
+++ b/vpr/src/device/rr_graph_obj.cpp
@@ -885,6 +885,7 @@ RREdgeId RRGraph::create_edge(const RRNodeId& source, const RRNodeId& sink, cons
 
 void RRGraph::set_edge_switch(const RREdgeId& edge, const RRSwitchId& switch_id) {
     VTR_ASSERT(valid_edge_id(edge));
+    VTR_ASSERT(valid_switch_id(switch_id));
     edge_switches_[edge] = switch_id;
 }
 

From 15167c9bfb42dc1ea2b5b90350956e2e708aafc2 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 4 Feb 2020 11:37:59 -0700
Subject: [PATCH 093/645] bug fixing for building routing channels in
 build_rr_graph()

---
 vpr/src/device/rr_graph_obj.cpp | 11 +++++--
 vpr/src/route/rr_graph.cpp      | 51 ++++++++++++++++++++-------------
 vpr/src/route/rr_graph2.cpp     |  7 +++--
 3 files changed, 44 insertions(+), 25 deletions(-)

diff --git a/vpr/src/device/rr_graph_obj.cpp b/vpr/src/device/rr_graph_obj.cpp
index cf616538c..74ee29667 100644
--- a/vpr/src/device/rr_graph_obj.cpp
+++ b/vpr/src/device/rr_graph_obj.cpp
@@ -68,19 +68,21 @@ short RRGraph::node_xhigh(const RRNodeId& node) const {
     /* Special for SOURCE and SINK node, we always return the xlow 
      * This is due to the convention in creating RRGraph 
      * so that we can guarantee unique SOURCE/SINK nodes searching 
-     */
     if (  (SOURCE == node_type(node))
        || (SINK == node_type(node)) ) {
       return node_bounding_box(node).xmin();
     }
+     */
     return node_bounding_box(node).xmax();
 }
 
 short RRGraph::node_yhigh(const RRNodeId& node) const {
+    /*
     if (  (SOURCE == node_type(node))
        || (SINK == node_type(node)) ) {
       return node_bounding_box(node).ymin();
     }
+     */
     return node_bounding_box(node).ymax();
 }
 
@@ -1229,6 +1231,7 @@ void RRGraph::build_fast_node_lookup() const {
         std::vector<size_t> xlows;
         std::vector<size_t> ylows;
 
+        /*
         if ( (SOURCE == node_type(node))
           || (SINK == node_type(node)) 
           || (CHANX == node_type(node))
@@ -1237,13 +1240,15 @@ void RRGraph::build_fast_node_lookup() const {
             ylows.resize(node_bounding_boxes_[node].ymax() - node_bounding_boxes_[node].ymin() + 1);
             std::iota(xlows.begin(), xlows.end(), node_xlow(node));
             std::iota(ylows.begin(), ylows.end(), node_ylow(node));
-            /* Sanity check */
             VTR_ASSERT(size_t(node_bounding_boxes_[node].xmax()) == xlows.back());
             VTR_ASSERT(size_t(node_bounding_boxes_[node].ymax()) == ylows.back());
-        } else { 
+        } else {
+        */ 
             xlows.push_back(node_xlow(node));
             ylows.push_back(node_ylow(node));
+        /*
         }
+         */
 
         for (size_t x : xlows) {
             for (size_t y : ylows) {
diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp
index a801098c6..b24c2f6ef 100644
--- a/vpr/src/route/rr_graph.cpp
+++ b/vpr/src/route/rr_graph.cpp
@@ -718,7 +718,7 @@ static void build_rr_graph(const t_graph_type graph_type,
      */
     device_ctx.rr_graph.reserve_switches(device_ctx.num_arch_switches);
     // Create the switches
-    for (size_t iswitch = 0; iswitch < device_ctx.num_arch_switches; ++iswitch) {
+    for (int iswitch = 0; iswitch < device_ctx.num_arch_switches; ++iswitch) {
         const t_rr_switch_inf& temp_rr_switch = create_rr_switch_from_arch_switch(iswitch, R_minW_nmos, R_minW_pmos);
         device_ctx.rr_graph.create_switch(temp_rr_switch);
     }
@@ -1864,26 +1864,17 @@ void alloc_and_load_edges(RRGraph& rr_graph,
 
         size_t edge_count = std::distance(edge_range.first, edge_range.second);
 
-        if (rr_graph.node_out_edges(inode).size() == 0) {
-            //Create initial edges
-            //
-            //Note that we do this in bulk instead of via add_edge() to reduce
-            //memory fragmentation
+        //Create initial edges
+        //
+        //Note that we do this in bulk instead of via add_edge() to reduce
+        //memory fragmentation
 
-            rr_graph.reserve_edges(edge_count + rr_graph.edges().size());
+        rr_graph.reserve_edges(edge_count + rr_graph.edges().size());
 
-            for (auto itr = edge_range.first; itr != edge_range.second; ++itr) {
-                VTR_ASSERT(itr->from_node == inode);
+        for (auto itr = edge_range.first; itr != edge_range.second; ++itr) {
+            VTR_ASSERT(itr->from_node == inode);
 
-                rr_graph.create_edge(inode, itr->to_node, RRSwitchId(itr->switch_type));
-            }
-        } else {
-            //Add new edge incrementally
-            //
-            //This should occur relatively rarely (e.g. a backward bidir edge) so memory fragmentation shouldn't be a big problem
-            for (auto itr = edge_range.first; itr != edge_range.second; ++itr) {
-                rr_graph.create_edge(inode, itr->to_node, RRSwitchId(itr->switch_type));
-            }
+            rr_graph.create_edge(inode, itr->to_node, RRSwitchId(itr->switch_type));
         }
     }
 }
@@ -2672,7 +2663,23 @@ std::string describe_rr_node(const RRNodeId& inode) {
 
     return msg;
 }
-static void build_unidir_rr_opins(const int i, const int j, const e_side side, const DeviceGrid& grid, const std::vector<vtr::Matrix<int>>& Fc_out, const int max_chan_width, const t_chan_details& chan_details_x, const t_chan_details& chan_details_y, vtr::NdMatrix<int, 3>& Fc_xofs, vtr::NdMatrix<int, 3>& Fc_yofs, t_rr_edge_info_set& rr_edges_to_create, bool* Fc_clipped, const t_rr_node_indices& L_rr_node_indices, const RRGraph& rr_graph, const t_direct_inf* directs, const int num_directs, const t_clb_to_clb_directs* clb_to_clb_directs, const int num_seg_types) {
+static void build_unidir_rr_opins(const int i, const int j, 
+                                  const e_side side, 
+                                  const DeviceGrid& grid, 
+                                  const std::vector<vtr::Matrix<int>>& Fc_out, 
+                                  const int max_chan_width, 
+                                  const t_chan_details& chan_details_x, 
+                                  const t_chan_details& chan_details_y, 
+                                  vtr::NdMatrix<int, 3>& Fc_xofs, 
+                                  vtr::NdMatrix<int, 3>& Fc_yofs, 
+                                  t_rr_edge_info_set& rr_edges_to_create, 
+                                  bool* Fc_clipped, 
+                                  const t_rr_node_indices& L_rr_node_indices, 
+                                  const RRGraph& rr_graph, 
+                                  const t_direct_inf* directs, 
+                                  const int num_directs, 
+                                  const t_clb_to_clb_directs* clb_to_clb_directs, 
+                                  const int num_seg_types) {
     /*
      * This routine adds the edges from opins to channels at the specified
      * grid location (i,j) and grid tile side
@@ -2696,7 +2703,11 @@ static void build_unidir_rr_opins(const int i, const int j, const e_side side, c
         }
 
         RRNodeId opin_node_index = rr_graph.find_node(i, j, OPIN, pin_index, side);
-        if (false == rr_graph.valid_node_id(opin_node_index)) continue; //No valid from node
+        //if (false == rr_graph.valid_node_id(opin_node_index)) continue; //No valid from node
+
+        if (1 == type->pinloc[width_offset][height_offset][side][pin_index]) {
+            VTR_ASSERT(true == rr_graph.valid_node_id(opin_node_index));
+        }
 
         for (int iseg = 0; iseg < num_seg_types; iseg++) {
             /* get Fc for this segment type */
diff --git a/vpr/src/route/rr_graph2.cpp b/vpr/src/route/rr_graph2.cpp
index 21d69f296..ede1fdff5 100644
--- a/vpr/src/route/rr_graph2.cpp
+++ b/vpr/src/route/rr_graph2.cpp
@@ -809,8 +809,8 @@ int get_unidir_opin_connections(const int chan,
         dec_track = dec_muxes[dec_mux];
 
         /* Figure the inodes of those muxes */
-        inc_inode_index = rr_graph.find_node(chan, seg, chan_type, inc_track);
-        dec_inode_index = rr_graph.find_node(chan, seg, chan_type, dec_track);
+        inc_inode_index = rr_graph.find_node(x, y, chan_type, inc_track);
+        dec_inode_index = rr_graph.find_node(x, y, chan_type, dec_track);
 
         if (inc_inode_index == RRNodeId::INVALID() || dec_inode_index == RRNodeId::INVALID()) {
             continue;
@@ -1078,6 +1078,9 @@ static void load_chan_rr_indices(const int max_chan_width,
                 /* We give a fake coordinator here, to ease the downstream builder */
                 short xlow = chan;
                 short ylow = start;
+                if (CHANX == type) {
+                    std::swap(xlow, ylow);
+                }
                 RRNodeId node = rr_graph.find_node(xlow, ylow, type, track);
                 if (false == rr_graph.valid_node_id(node)) {
   

From 688186350650f5b170010af4448e5f6e9a006e14 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 4 Feb 2020 15:21:45 -0700
Subject: [PATCH 094/645] keep debugging rr_graph builder

---
 vpr/src/device/rr_graph_obj.cpp |  79 ++++-------
 vpr/src/device/rr_graph_obj.h   |   2 +
 vpr/src/route/rr_graph.cpp      |  81 ++++++-----
 vpr/src/route/rr_graph2.cpp     | 244 +++++++++++++++++++++-----------
 vpr/src/route/rr_graph2.h       |  30 +++-
 5 files changed, 260 insertions(+), 176 deletions(-)

diff --git a/vpr/src/device/rr_graph_obj.cpp b/vpr/src/device/rr_graph_obj.cpp
index 74ee29667..1b738d212 100644
--- a/vpr/src/device/rr_graph_obj.cpp
+++ b/vpr/src/device/rr_graph_obj.cpp
@@ -65,24 +65,10 @@ short RRGraph::node_ylow(const RRNodeId& node) const {
 }
 
 short RRGraph::node_xhigh(const RRNodeId& node) const {
-    /* Special for SOURCE and SINK node, we always return the xlow 
-     * This is due to the convention in creating RRGraph 
-     * so that we can guarantee unique SOURCE/SINK nodes searching 
-    if (  (SOURCE == node_type(node))
-       || (SINK == node_type(node)) ) {
-      return node_bounding_box(node).xmin();
-    }
-     */
     return node_bounding_box(node).xmax();
 }
 
 short RRGraph::node_yhigh(const RRNodeId& node) const {
-    /*
-    if (  (SOURCE == node_type(node))
-       || (SINK == node_type(node)) ) {
-      return node_bounding_box(node).ymin();
-    }
-     */
     return node_bounding_box(node).ymax();
 }
 
@@ -966,6 +952,12 @@ void RRGraph::remove_edge(const RREdgeId& edge) {
     set_dirty();
 }
 
+void RRGraph::set_node_type(const RRNodeId& node, const t_rr_type& type) {
+    VTR_ASSERT(valid_node_id(node));
+
+    node_types_[node] = type;
+}
+
 void RRGraph::set_node_xlow(const RRNodeId& node, const short& xlow) {
     VTR_ASSERT(valid_node_id(node));
 
@@ -1228,52 +1220,29 @@ void RRGraph::build_fast_node_lookup() const {
         /* Special for SOURCE and SINK, we should annotate in the look-up 
          * for all the (x,y) upto (xhigh, yhigh)
          */
-        std::vector<size_t> xlows;
-        std::vector<size_t> ylows;
+        size_t x = node_xlow(node);
+        size_t y = node_ylow(node);
 
-        /*
-        if ( (SOURCE == node_type(node))
-          || (SINK == node_type(node)) 
-          || (CHANX == node_type(node))
-          || (CHANY == node_type(node)) ) {
-            xlows.resize(node_bounding_boxes_[node].xmax() - node_bounding_boxes_[node].xmin() + 1);
-            ylows.resize(node_bounding_boxes_[node].ymax() - node_bounding_boxes_[node].ymin() + 1);
-            std::iota(xlows.begin(), xlows.end(), node_xlow(node));
-            std::iota(ylows.begin(), ylows.end(), node_ylow(node));
-            VTR_ASSERT(size_t(node_bounding_boxes_[node].xmax()) == xlows.back());
-            VTR_ASSERT(size_t(node_bounding_boxes_[node].ymax()) == ylows.back());
+        size_t itype = node_type(node);
+
+        size_t ptc = node_ptc_num(node);
+        if (ptc >= node_lookup_[x][y][itype].size()) {
+            node_lookup_[x][y][itype].resize(ptc + 1);
+        }
+
+        size_t iside = -1;
+        if (node_type(node) == OPIN || node_type(node) == IPIN) {
+            iside = node_side(node);
         } else {
-        */ 
-            xlows.push_back(node_xlow(node));
-            ylows.push_back(node_ylow(node));
-        /*
+            iside = NUM_SIDES;
         }
-         */
 
-        for (size_t x : xlows) {
-            for (size_t y : ylows) {
-                size_t itype = node_type(node);
-
-                size_t ptc = node_ptc_num(node);
-                if (ptc >= node_lookup_[x][y][itype].size()) {
-                    node_lookup_[x][y][itype].resize(ptc + 1);
-                }
-
-                size_t iside = -1;
-                if (node_type(node) == OPIN || node_type(node) == IPIN) {
-                    iside = node_side(node);
-                } else {
-                    iside = NUM_SIDES;
-                }
-
-                if (iside >= node_lookup_[x][y][itype][ptc].size()) {
-                    node_lookup_[x][y][itype][ptc].resize(iside + 1);
-                }
-
-                //Save node in lookup
-                node_lookup_[x][y][itype][ptc][iside] = node;
-            }
+        if (iside >= node_lookup_[x][y][itype][ptc].size()) {
+            node_lookup_[x][y][itype][ptc].resize(iside + 1);
         }
+
+        //Save node in lookup
+        node_lookup_[x][y][itype][ptc][iside] = node;
     }
 }
 
diff --git a/vpr/src/device/rr_graph_obj.h b/vpr/src/device/rr_graph_obj.h
index a81a5b301..fd8439868 100644
--- a/vpr/src/device/rr_graph_obj.h
+++ b/vpr/src/device/rr_graph_obj.h
@@ -646,6 +646,8 @@ class RRGraph {
     void remove_edge(const RREdgeId& edge);
 
     /* Set node-level information */
+    void set_node_type(const RRNodeId& node, const t_rr_type& type);
+
     void set_node_xlow(const RRNodeId& node, const short& xlow);
     void set_node_ylow(const RRNodeId& node, const short& ylow);
     void set_node_xhigh(const RRNodeId& node, const short& xhigh);
diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp
index b24c2f6ef..f9a87bfea 100644
--- a/vpr/src/route/rr_graph.cpp
+++ b/vpr/src/route/rr_graph.cpp
@@ -153,8 +153,7 @@ static int get_opin_direct_connections(int x,
                                        const int num_directs,
                                        const t_clb_to_clb_directs* clb_to_clb_directs);
 
-static void alloc_and_load_rr_graph(const int num_nodes,
-                                    RRGraph& rr_graph,
+static void alloc_and_load_rr_graph(RRGraph& rr_graph,
                                     const int num_seg_types,
                                     const t_chan_details& chan_details_x,
                                     const t_chan_details& chan_details_y,
@@ -599,10 +598,19 @@ static void build_rr_graph(const t_graph_type graph_type,
     int num_rr_nodes = 0;
 
     /* Xifan Tang - 
-     * We create all the nodes in the RRGraph object here
+     * Reuse the legacy rr_node indice because it has many out-of-law exceptions during the graph building 
+     * which is not allowed by RRGraph object
      */
-    device_ctx.rr_graph = alloc_and_load_rr_node_indices(max_chan_width, grid,
-                                                         &num_rr_nodes, chan_details_x, chan_details_y);
+    t_rr_node_indices L_rr_node_indices = alloc_and_load_rr_node_indices(max_chan_width, grid,
+                                                                         &num_rr_nodes, chan_details_x, chan_details_y);
+
+    /* Allocate the nodes in RR Graph */
+    device_ctx.rr_graph.reserve_nodes(num_rr_nodes);
+    for (int i = 0; i < num_rr_nodes; ++i) {
+      /* Give a fake node type, will be corrected later in the builder */
+      device_ctx.rr_graph.create_node(SOURCE);
+    }
+   
 
     /* The number of segments are in general small, reserve segments may not bring
      * significant memory efficiency */
@@ -723,11 +731,11 @@ static void build_rr_graph(const t_graph_type graph_type,
         device_ctx.rr_graph.create_switch(temp_rr_switch);
     }
 
-    alloc_and_load_rr_graph(device_ctx.rr_graph.nodes().size(), device_ctx.rr_graph, segment_inf.size(),
+    alloc_and_load_rr_graph(device_ctx.rr_graph, segment_inf.size(),
                             chan_details_x, chan_details_y,
                             track_to_pin_lookup, opin_to_track_map,
                             switch_block_conn, sb_conn_map, grid, Fs, unidir_sb_pattern,
-                            Fc_out, Fc_xofs, Fc_yofs, device_ctx.rr_node_indices,
+                            Fc_out, Fc_xofs, Fc_yofs, L_rr_node_indices,
                             max_chan_width,
                             nodes_per_chan,
                             wire_to_arch_ipin_switch,
@@ -820,6 +828,8 @@ static void build_rr_graph(const t_graph_type graph_type,
     if (clb_to_clb_directs != nullptr) {
         free(clb_to_clb_directs);
     }
+
+    L_rr_node_indices.clear();
 }
 
 /* Allocates and loads the global rr_switch_inf array based on the global
@@ -1292,8 +1302,7 @@ static void free_type_track_to_pin_map(t_track_to_pin_lookup& track_to_pin_map,
 
 /* Does the actual work of allocating the rr_graph and filling all the *
  * appropriate values.  Everything up to this was just a prelude!      */
-static void alloc_and_load_rr_graph(const int num_nodes,
-                                    RRGraph& rr_graph,
+static void alloc_and_load_rr_graph(RRGraph& rr_graph,
                                     const int num_seg_types,
                                     const t_chan_details& chan_details_x,
                                     const t_chan_details& chan_details_y,
@@ -1463,12 +1472,12 @@ static void build_bidir_rr_opins(const int i,
             total_pin_Fc += Fc[pin_index][iseg];
         }
 
-        RRNodeId node_index = rr_graph.find_node(i, j, OPIN, pin_index, side);
+        RRNodeId node_index = RRNodeId(get_rr_node_index(L_rr_node_indices, i, j, OPIN, pin_index, side));
         VTR_ASSERT(true == rr_graph.valid_node_id(node_index));
 
         if (total_pin_Fc > 0) {
             get_bidir_opin_connections(i, j, pin_index,
-                                       node_index, rr_edges_to_create, opin_to_track_map, rr_graph,
+                                       node_index, rr_edges_to_create, opin_to_track_map, L_rr_node_indices,
                                        chan_details_x,
                                        chan_details_y);
         }
@@ -1540,7 +1549,7 @@ static void build_rr_sinks_sources(const int i,
     for (int iclass = 0; iclass < num_class; ++iclass) {
         RRNodeId inode = RRNodeId::INVALID();
         if (class_inf[iclass].type == DRIVER) { /* SOURCE */
-            inode = rr_graph.find_node(i, j, SOURCE, iclass);
+            inode = RRNodeId(get_rr_node_index(L_rr_node_indices, i, j, SOURCE, iclass));
 
             //Retrieve all the physical OPINs associated with this source, this includes
             //those at different grid tiles of this block
@@ -1549,7 +1558,7 @@ static void build_rr_sinks_sources(const int i,
                 for (int height_offset = 0; height_offset < type->height; ++height_offset) {
                     for (int ipin = 0; ipin < class_inf[iclass].num_pins; ++ipin) {
                         int pin_num = class_inf[iclass].pinlist[ipin];
-                        auto physical_pins = find_rr_graph_nodes(rr_graph, i + width_offset, j + height_offset, OPIN, pin_num);
+                        auto physical_pins = get_rr_graph_node_indices(L_rr_node_indices, i + width_offset, j + height_offset, OPIN, pin_num);
                         opin_nodes.insert(opin_nodes.end(), physical_pins.begin(), physical_pins.end());
                     }
                 }
@@ -1560,10 +1569,11 @@ static void build_rr_sinks_sources(const int i,
                 rr_edges_to_create.emplace_back(inode, opin_nodes[iedge], delayless_switch);
             }
 
+            rr_graph.set_node_type(inode, SOURCE);
             rr_graph.set_node_cost_index(inode, SOURCE_COST_INDEX);
         } else { /* SINK */
             VTR_ASSERT(class_inf[iclass].type == RECEIVER);
-            inode = rr_graph.find_node(i, j, SINK, iclass);
+            inode = get_rr_graph_node_index(L_rr_node_indices, i, j, SINK, iclass);
 
             /* NOTE:  To allow route throughs through clbs, change the lines below to  *
              * make an edge from the input SINK to the output SOURCE.  Do for just the *
@@ -1572,7 +1582,8 @@ static void build_rr_sinks_sources(const int i,
              * base cost of OPINs and/or SOURCES so they aren't used excessively.      */
 
             /* Initialize to unconnected */
-            rr_graph.set_node_cost_index(RRNodeId(inode), SINK_COST_INDEX);
+            rr_graph.set_node_type(inode, SINK);
+            rr_graph.set_node_cost_index(inode, SINK_COST_INDEX);
         }
 
         /* Things common to both SOURCEs and SINKs.   */
@@ -1597,24 +1608,29 @@ static void build_rr_sinks_sources(const int i,
 
                         if (class_inf[iclass].type == RECEIVER) {
                             //Connect the input pin to the sink
-                            inode = rr_graph.find_node(i + width_offset, j + height_offset, IPIN, ipin, side);
+                            inode = RRNodeId(get_rr_node_index(L_rr_node_indices, i + width_offset, j + height_offset, IPIN, ipin, side));
 
-                            RRNodeId to_node = rr_graph.find_node(i, j, SINK, iclass);
+                            RRNodeId to_node = RRNodeId(get_rr_node_index(L_rr_node_indices, i, j, SINK, iclass));
+
+                            VTR_ASSERT(true == rr_graph.valid_node_id(inode));
+                            VTR_ASSERT(true == rr_graph.valid_node_id(to_node));
 
                             //Add info about the edge to be created
                             rr_edges_to_create.emplace_back(inode, to_node, delayless_switch);
 
-                            VTR_ASSERT(true == rr_graph.valid_node_id(inode));
+                            rr_graph.set_node_type(inode, IPIN);
                             rr_graph.set_node_cost_index(inode, IPIN_COST_INDEX);
 
                         } else {
                             VTR_ASSERT(class_inf[iclass].type == DRIVER);
                             //Initialize the output pin
                             // Note that we leave it's out-going edges unconnected (they will be hooked up to global routing later)
-                            inode = rr_graph.find_node(i + width_offset, j + height_offset, OPIN, ipin, side);
+                            inode = RRNodeId(get_rr_node_index(L_rr_node_indices, i + width_offset, j + height_offset, OPIN, ipin, side));
+                            VTR_ASSERT(true == rr_graph.valid_node_id(inode));
 
                             //Initially left unconnected
 
+                            rr_graph.set_node_type(inode, OPIN);
                             rr_graph.set_node_cost_index(inode, OPIN_COST_INDEX);
                         }
 
@@ -1731,7 +1747,7 @@ static void build_rr_chan(const int x_coord,
             from_seg_details = chan_details_x[start][y_coord].data();
         }
 
-        RRNodeId node = rr_graph.find_node(x_coord, y_coord, chan_type, track);
+        RRNodeId node = get_rr_graph_node_index(L_rr_node_indices, x_coord, y_coord, chan_type, track);
 
         if (node == RRNodeId::INVALID()) {
             continue;
@@ -1740,7 +1756,7 @@ static void build_rr_chan(const int x_coord,
         /* Add the edges from this track to all it's connected pins into the list */
         int num_edges = 0;
         num_edges += get_track_to_pins(start, chan_coord, track, tracks_per_chan, node, rr_edges_to_create,
-                                       rr_graph, track_to_pin_lookup, seg_details, chan_type, seg_dimension,
+                                       L_rr_node_indices, rr_graph, track_to_pin_lookup, seg_details, chan_type, seg_dimension,
                                        wire_to_ipin_switch, directionality);
 
         /* get edges going from the current track into channel segments which are perpendicular to it */
@@ -1758,7 +1774,7 @@ static void build_rr_chan(const int x_coord,
                                                  Fs_per_side, sblock_pattern, node, rr_edges_to_create,
                                                  from_seg_details, to_seg_details, opposite_chan_details,
                                                  directionality,
-                                                 rr_graph,
+                                                 L_rr_node_indices, rr_graph,
                                                  switch_block_conn, sb_conn_map);
             }
         }
@@ -1776,7 +1792,7 @@ static void build_rr_chan(const int x_coord,
                                                  Fs_per_side, sblock_pattern, node, rr_edges_to_create,
                                                  from_seg_details, to_seg_details, opposite_chan_details,
                                                  directionality,
-                                                 rr_graph,
+                                                 L_rr_node_indices, rr_graph,
                                                  switch_block_conn, sb_conn_map);
             }
         }
@@ -1806,13 +1822,14 @@ static void build_rr_chan(const int x_coord,
                                                      Fs_per_side, sblock_pattern, node, rr_edges_to_create,
                                                      from_seg_details, to_seg_details, from_chan_details,
                                                      directionality,
-                                                     rr_graph,
+                                                     L_rr_node_indices, rr_graph,
                                                      switch_block_conn, sb_conn_map);
                 }
             }
         }
 
         /* Edge arrays have now been built up.  Do everything else.  */
+        rr_graph.set_node_type(node, chan_type); /* GLOBAL routing handled elsewhere */
         rr_graph.set_node_cost_index(node, cost_index_offset + seg_details[track].index());
         rr_graph.set_node_capacity(node, 1); /* GLOBAL routing handled elsewhere */
 
@@ -1869,7 +1886,7 @@ void alloc_and_load_edges(RRGraph& rr_graph,
         //Note that we do this in bulk instead of via add_edge() to reduce
         //memory fragmentation
 
-        rr_graph.reserve_edges(edge_count + rr_graph.edges().size());
+        //rr_graph.reserve_edges(edge_count + rr_graph.edges().size());
 
         for (auto itr = edge_range.first; itr != edge_range.second; ++itr) {
             VTR_ASSERT(itr->from_node == inode);
@@ -2702,12 +2719,8 @@ static void build_unidir_rr_opins(const int i, const int j,
             continue;
         }
 
-        RRNodeId opin_node_index = rr_graph.find_node(i, j, OPIN, pin_index, side);
-        //if (false == rr_graph.valid_node_id(opin_node_index)) continue; //No valid from node
-
-        if (1 == type->pinloc[width_offset][height_offset][side][pin_index]) {
-            VTR_ASSERT(true == rr_graph.valid_node_id(opin_node_index));
-        }
+        RRNodeId opin_node_index = get_rr_graph_node_index(L_rr_node_indices, i, j, OPIN, pin_index, side);
+        if (false == rr_graph.valid_node_id(opin_node_index)) continue; //No valid from node
 
         for (int iseg = 0; iseg < num_seg_types; iseg++) {
             /* get Fc for this segment type */
@@ -2760,7 +2773,7 @@ static void build_unidir_rr_opins(const int i, const int j,
                                         opin_node_index,
                                         rr_edges_to_create,
                                         Fc_ofs, max_len, max_chan_width,
-                                        rr_graph, &clipped);
+                                        L_rr_node_indices, &clipped);
             if (clipped) {
                 *Fc_clipped = true;
             }
@@ -3007,8 +3020,8 @@ static int get_opin_direct_connections(int x,
                             }
                         } else {
                             //No side specified, get all candidates
-                            inodes = find_rr_graph_nodes(rr_graph, x + directs[i].x_offset, y + directs[i].y_offset,
-                                                         IPIN, ipin);
+                            inodes = get_rr_graph_node_indices(L_rr_node_indices, x + directs[i].x_offset, y + directs[i].y_offset,
+                                                               IPIN, ipin);
                         }
 
                         if (inodes.size() > 0) {
diff --git a/vpr/src/route/rr_graph2.cpp b/vpr/src/route/rr_graph2.cpp
index ede1fdff5..6317b53b7 100644
--- a/vpr/src/route/rr_graph2.cpp
+++ b/vpr/src/route/rr_graph2.cpp
@@ -31,14 +31,15 @@ static void load_chan_rr_indices(const int max_chan_width,
                                  const int num_chans,
                                  const t_rr_type type,
                                  const t_chan_details& chan_details,
-                                 RRGraph& rr_graph,
+                                 t_rr_node_indices& indices,
                                  int* index);
 
 static void load_block_rr_indices(const DeviceGrid& grid,
-                                  RRGraph& rr_graph,
+                                  t_rr_node_indices& indices,
                                   int* index);
 
 static int get_bidir_track_to_chan_seg(const std::vector<int> conn_tracks,
+                                       const t_rr_node_indices& L_rr_node_indices,
                                        const RRGraph& rr_graph,
                                        const int to_chan,
                                        const int to_seg,
@@ -64,6 +65,7 @@ static int get_unidir_track_to_chan_seg(const int from_track,
                                         const int Fs_per_side,
                                         t_sblock_pattern& sblock_pattern,
                                         const int switch_override,
+                                        const t_rr_node_indices& L_rr_node_indices,
                                         const RRGraph& rr_graph,
                                         const t_chan_seg_details* seg_details,
                                         bool* Fs_clipped,
@@ -77,6 +79,7 @@ static int get_track_to_chan_seg(const int from_track,
                                  const e_side from_side,
                                  const e_side to_side,
                                  const int swtich_override,
+                                 const t_rr_node_indices& L_rr_node_indices,
                                  const RRGraph& rr_graph,
                                  t_sb_connection_map* sb_conn_map,
                                  const RRNodeId& from_rr_node,
@@ -667,7 +670,7 @@ int get_bidir_opin_connections(const int i,
                                const RRNodeId& from_rr_node,
                                t_rr_edge_info_set& rr_edges_to_create,
                                const t_pin_to_track_lookup& opin_to_track_map,
-                               const RRGraph& rr_graph,
+                               const t_rr_node_indices& L_rr_node_indices,
                                const t_chan_details& chan_details_x,
                                const t_chan_details& chan_details_y) {
     int num_conn, tr_i, tr_j, chan, seg;
@@ -731,7 +734,7 @@ int get_bidir_opin_connections(const int i,
             /* Only connect to wire if there is a CB */
             if (is_cblock(chan, seg, to_track, seg_details)) {
                 to_switch = seg_details[to_track].arch_wire_switch();
-                to_node = rr_graph.find_node(tr_i, tr_j, to_type, to_track);
+                to_node = RRNodeId(get_rr_node_index(L_rr_node_indices, tr_i, tr_j, to_type, to_track));
 
                 if (to_node == RRNodeId::INVALID()) {
                     continue;
@@ -757,7 +760,7 @@ int get_unidir_opin_connections(const int chan,
                                 vtr::NdMatrix<int, 3>& Fc_ofs,
                                 const int max_len,
                                 const int max_chan_width,
-                                const RRGraph& rr_graph,
+                                const t_rr_node_indices& L_rr_node_indices,
                                 bool* Fc_clipped) {
     /* Gets a linked list of Fc nodes of specified seg_type_index to connect
      * to in given chan seg. Fc_ofs is used for the opin staggering pattern. */
@@ -809,8 +812,8 @@ int get_unidir_opin_connections(const int chan,
         dec_track = dec_muxes[dec_mux];
 
         /* Figure the inodes of those muxes */
-        inc_inode_index = rr_graph.find_node(x, y, chan_type, inc_track);
-        dec_inode_index = rr_graph.find_node(x, y, chan_type, dec_track);
+        inc_inode_index = get_rr_graph_node_index(L_rr_node_indices, x, y, chan_type, inc_track);
+        dec_inode_index = get_rr_graph_node_index(L_rr_node_indices, x, y, chan_type, dec_track);
 
         if (inc_inode_index == RRNodeId::INVALID() || dec_inode_index == RRNodeId::INVALID()) {
             continue;
@@ -1059,8 +1062,20 @@ static void load_chan_rr_indices(const int max_chan_width,
                                  const int num_chans,
                                  const t_rr_type type,
                                  const t_chan_details& chan_details,
-                                 RRGraph& rr_graph,
+                                 t_rr_node_indices& indices,
                                  int* index) {
+    VTR_ASSERT(indices[type].size() == size_t(num_chans));
+    for (int chan = 0; chan < num_chans - 1; ++chan) {
+        VTR_ASSERT(indices[type][chan].size() == size_t(chan_len));
+
+        for (int seg = 1; seg < chan_len - 1; ++seg) {
+            VTR_ASSERT(indices[type][chan][seg].size() == NUM_SIDES);
+
+            /* Alloc the track inode lookup list */
+            //Since channels have no side, we just use the first side
+            indices[type][chan][seg][0].resize(max_chan_width, OPEN);
+        }
+    }
 
     for (int chan = 0; chan < num_chans - 1; ++chan) {
         for (int seg = 1; seg < chan_len - 1; ++seg) {
@@ -1069,34 +1084,32 @@ static void load_chan_rr_indices(const int max_chan_width,
             int y = (type == CHANX ? chan : seg);
             const t_chan_seg_details* seg_details = chan_details[x][y].data();
 
-            for (int track = 0; track < num_chans - 1; ++track) {
+            for (unsigned track = 0; track < indices[type][chan][seg][0].size(); ++track) {
                 if (seg_details[track].length() <= 0)
                     continue;
 
                 int start = get_seg_start(seg_details, track, chan, seg);
                  
-                /* We give a fake coordinator here, to ease the downstream builder */
-                short xlow = chan;
-                short ylow = start;
-                if (CHANX == type) {
-                    std::swap(xlow, ylow);
-                }
-                RRNodeId node = rr_graph.find_node(xlow, ylow, type, track);
-                if (false == rr_graph.valid_node_id(node)) {
-  
-                    RRNodeId new_node = rr_graph.create_node(type);
-                    rr_graph.set_node_bounding_box(new_node, vtr::Rect<short>(xlow, ylow, xlow, ylow));
-                    rr_graph.set_node_track_num(new_node, track);
- 
-                    (*index)++;
+                /* If the start of the wire doesn't have a inode,
+                 * assign one to it. */
+                int inode = indices[type][chan][start][0][track];
+                if (OPEN == inode) {
+                    inode = *index;
+                    ++(*index);
+
+                    indices[type][chan][start][0][track] = inode;
                 }
+
+                /* Assign inode of start of wire to current position */
+                indices[type][chan][seg][0][track] = inode;
+
             }
         }
     }
 }
 
 static void load_block_rr_indices(const DeviceGrid& grid,
-                                  RRGraph& rr_graph,
+                                  t_rr_node_indices& indices,
                                   int* index) {
     //Walk through the grid assigning indices to SOURCE/SINK IPIN/OPIN
     for (size_t x = 0; x < grid.width(); x++) {
@@ -1110,14 +1123,12 @@ static void load_block_rr_indices(const DeviceGrid& grid,
                 for (int iclass = 0; iclass < type->num_class; ++iclass) {
                     auto class_type = type->class_inf[iclass].type;
                     if (class_type == DRIVER) {
-                        RRNodeId node = rr_graph.create_node(SOURCE);
-                        rr_graph.set_node_bounding_box(node, vtr::Rect<short>(x, y, x, y));
-                        rr_graph.set_node_class_num(node, iclass);
+                        indices[SOURCE][x][y][0].push_back(*index);
+                        indices[SINK][x][y][0].push_back(OPEN);
                     } else {
                         VTR_ASSERT(class_type == RECEIVER);
-                        RRNodeId node = rr_graph.create_node(SINK);
-                        rr_graph.set_node_bounding_box(node, vtr::Rect<short>(x, y, x, y));
-                        rr_graph.set_node_class_num(node, iclass);
+                        indices[SINK][x][y][0].push_back(*index);
+                        indices[SOURCE][x][y][0].push_back(OPEN);
                     }
                     ++(*index);
                 }
@@ -1134,23 +1145,34 @@ static void load_block_rr_indices(const DeviceGrid& grid,
                                     auto class_type = type->class_inf[iclass].type;
 
                                     if (class_type == DRIVER) {
-                                        RRNodeId node = rr_graph.create_node(OPIN);
-                                        rr_graph.set_node_bounding_box(node, vtr::Rect<short>(x_tile, y_tile, x_tile, y_tile));
-                                        rr_graph.set_node_pin_num(node, ipin);
-                                        rr_graph.set_node_side(node, side);
+                                        indices[OPIN][x_tile][y_tile][side].push_back(*index);
+                                        indices[IPIN][x_tile][y_tile][side].push_back(OPEN);
                                     } else {
                                         VTR_ASSERT(class_type == RECEIVER);
-                                        RRNodeId node = rr_graph.create_node(IPIN);
-                                        rr_graph.set_node_bounding_box(node, vtr::Rect<short>(x_tile, y_tile, x_tile, y_tile));
-                                        rr_graph.set_node_pin_num(node, ipin);
-                                        rr_graph.set_node_side(node, side);
+                                        indices[IPIN][x_tile][y_tile][side].push_back(*index);
+                                        indices[OPIN][x_tile][y_tile][side].push_back(OPEN);
                                     }
                                     ++(*index);
+
+                                } else {
+                                    indices[IPIN][x_tile][y_tile][side].push_back(OPEN);
+                                    indices[OPIN][x_tile][y_tile][side].push_back(OPEN);
                                 }
                             }
                         }
                     }
                 }
+                //Sanity check
+                for (int width_offset = 0; width_offset < type->width; ++width_offset) {
+                    int x_tile = x + width_offset;
+                    for (int height_offset = 0; height_offset < type->height; ++height_offset) {
+                        int y_tile = y + height_offset;
+                        for (e_side side : SIDES) {
+                            VTR_ASSERT(indices[IPIN][x_tile][y_tile][side].size() == size_t(type->num_pins));
+                            VTR_ASSERT(indices[OPIN][x_tile][y_tile][side].size() == size_t(type->num_pins));
+                        }
+                    }
+                }
             }
         }
     }
@@ -1169,46 +1191,56 @@ static void load_block_rr_indices(const DeviceGrid& grid,
                 int root_x = x - width_offset;
                 int root_y = y - height_offset;
 
-                //Process each block from it's root location
-                auto type = grid[x][y].type;
-
-                //Assign indicies for SINKs and SOURCEs
-                // Note that SINKS/SOURCES have no side, so we always use side 0
-                for (int iclass = 0; iclass < type->num_class; ++iclass) {
-                    auto class_type = type->class_inf[iclass].type;
-                    if (class_type == DRIVER) {
-                        RRNodeId node = rr_graph.find_node(root_x, root_y, SOURCE, iclass);
-                        /* Update the internal look-up so that we can find the SOURCE/SINK node using their offset coordinates */
-                        rr_graph.set_node_bounding_box(node, vtr::Rect<short>(root_x, root_y, x, y));
-                    } else {
-                        VTR_ASSERT(class_type == RECEIVER);
-                        RRNodeId node = rr_graph.find_node(root_x, root_y, SINK, iclass);
-                        /* Update the internal look-up so that we can find the SOURCE/SINK node using their offset coordinates */
-                        rr_graph.set_node_bounding_box(node, vtr::Rect<short>(root_x, root_y, x, y));
-                    }
-                }
+                indices[SOURCE][x][y] = indices[SOURCE][root_x][root_y];
+                indices[SINK][x][y] = indices[SINK][root_x][root_y];
             }
         }
     }
 }
 
-RRGraph alloc_and_load_rr_node_indices(const int max_chan_width,
-                                       const DeviceGrid& grid,
-                                       int* index,
-                                       const t_chan_details& chan_details_x,
-                                       const t_chan_details& chan_details_y) {
-    /* Allocates and loads all the nodes in a RRGraph object */
-    RRGraph rr_graph;
+t_rr_node_indices alloc_and_load_rr_node_indices(const int max_chan_width,
+                                                 const DeviceGrid& grid,
+                                                 int* index,
+                                                 const t_chan_details& chan_details_x,
+                                                 const t_chan_details& chan_details_y) {
+    /* Allocates and loads all the structures needed for fast lookups of the   *
+     * index of an rr_node.  rr_node_indices is a matrix containing the index  *
+     * of the *first* rr_node at a given (i,j) location.                       */
+
+    t_rr_node_indices indices;
+
+    /* Alloc the lookup table */
+    indices.resize(NUM_RR_TYPES);
+    for (t_rr_type rr_type : RR_TYPES) {
+        if (rr_type == CHANX) {
+            indices[rr_type].resize(grid.height());
+            for (size_t y = 0; y < grid.height(); ++y) {
+                indices[rr_type][y].resize(grid.width());
+                for (size_t x = 0; x < grid.width(); ++x) {
+                    indices[rr_type][y][x].resize(NUM_SIDES);
+                }
+            }
+        } else {
+            indices[rr_type].resize(grid.width());
+            for (size_t x = 0; x < grid.width(); ++x) {
+                indices[rr_type][x].resize(grid.height());
+                for (size_t y = 0; y < grid.height(); ++y) {
+                    indices[rr_type][x][y].resize(NUM_SIDES);
+                }
+            }
+        }
+    }
+
 
     /* Assign indices for block nodes */
-    load_block_rr_indices(grid, rr_graph, index);
+    load_block_rr_indices(grid, indices, index);
 
     /* Load the data for x and y channels */
     load_chan_rr_indices(max_chan_width, grid.width(), grid.height(),
-                         CHANX, chan_details_x, rr_graph, index);
+                         CHANX, chan_details_x, indices, index);
     load_chan_rr_indices(max_chan_width, grid.height(), grid.width(),
-                         CHANY, chan_details_y, rr_graph, index);
-    return rr_graph;
+                         CHANY, chan_details_y, indices, index);
+    return indices;
 }
 
 std::vector<int> get_rr_node_chan_wires_at_location(const t_rr_node_indices& L_rr_node_indices,
@@ -1225,6 +1257,44 @@ std::vector<int> get_rr_node_chan_wires_at_location(const t_rr_node_indices& L_r
     return L_rr_node_indices[rr_type][x][y][SIDES[0]];
 }
 
+/********************************************************************
+ * A wrapper for the old function to return a vector of RRNodeId
+ *******************************************************************/
+std::vector<RRNodeId> get_rr_graph_node_indices(const t_rr_node_indices& L_rr_node_indices,
+                                                int x,
+                                                int y,
+                                                t_rr_type rr_type,
+                                                int ptc) {
+    /*
+     * Like get_rr_node_index() but returns all matching nodes,
+     * rather than just the first. This is particularly useful for getting all instances
+     * of a specific IPIN/OPIN at a specific gird tile (x,y) location.
+     */
+    std::vector<RRNodeId> indices;
+
+    if (rr_type == IPIN || rr_type == OPIN) {
+        //For pins we need to look at all the sides of the current grid tile
+
+        for (e_side side : SIDES) {
+            int rr_node_index = get_rr_node_index(L_rr_node_indices, x, y, rr_type, ptc, side);
+
+            if (rr_node_index >= 0) {
+                indices.push_back(RRNodeId(rr_node_index));
+            }
+        }
+    } else {
+        //Sides do not effect non-pins so there should only be one per ptc
+        int rr_node_index = get_rr_node_index(L_rr_node_indices, x, y, rr_type, ptc);
+
+        if (rr_node_index != OPEN) {
+            indices.push_back(RRNodeId(rr_node_index));
+        }
+    }
+
+    return indices;
+}
+
+
 std::vector<int> get_rr_node_indices(const t_rr_node_indices& L_rr_node_indices,
                                      int x,
                                      int y,
@@ -1259,6 +1329,15 @@ std::vector<int> get_rr_node_indices(const t_rr_node_indices& L_rr_node_indices,
     return indices;
 }
 
+RRNodeId get_rr_graph_node_index(const t_rr_node_indices& L_rr_node_indices,
+                                 int x,
+                                 int y,
+                                 t_rr_type rr_type,
+                                 int ptc,
+                                 e_side side) {
+  return RRNodeId(get_rr_node_index(L_rr_node_indices, x, y, rr_type, ptc, side));
+}
+
 int get_rr_node_index(const t_rr_node_indices& L_rr_node_indices,
                       int x,
                       int y,
@@ -1398,6 +1477,7 @@ int get_track_to_pins(int seg,
                       int tracks_per_chan,
                       const RRNodeId& from_rr_node,
                       t_rr_edge_info_set& rr_edges_to_create,
+                      const t_rr_node_indices& L_rr_node_indices,
                       const RRGraph& rr_graph,
                       const t_track_to_pin_lookup& track_to_pin_lookup,
                       const t_chan_seg_details* seg_details,
@@ -1456,7 +1536,7 @@ int get_track_to_pins(int seg,
 
                     /* Check there is a connection and Fc map isn't wrong */
                     /*int to_node = get_rr_node_index(L_rr_node_indices, x + width_offset, y + height_offset, IPIN, ipin, side);*/
-                    RRNodeId to_node = rr_graph.find_node(x, y, IPIN, ipin, side);
+                    RRNodeId to_node = RRNodeId(get_rr_node_index(L_rr_node_indices, x, y, IPIN, ipin, side));
                     if (rr_graph.valid_node_id(to_node)) {
                         rr_edges_to_create.emplace_back(from_rr_node, to_node, wire_to_ipin_switch);
                         ++num_conn;
@@ -1503,6 +1583,7 @@ int get_track_to_tracks(const int from_chan,
                         const t_chan_seg_details* to_seg_details,
                         const t_chan_details& to_chan_details,
                         const enum e_directionality directionality,
+                        const t_rr_node_indices& L_rr_node_indices,
                         const RRGraph& rr_graph,
                         const vtr::NdMatrix<std::vector<int>, 3>& switch_block_conn,
                         t_sb_connection_map* sb_conn_map) {
@@ -1636,7 +1717,7 @@ int get_track_to_tracks(const int from_chan,
                     num_conn += get_track_to_chan_seg(from_track, to_chan, to_seg,
                                                       to_type, from_side_a, to_side,
                                                       switch_override,
-                                                      rr_graph,
+                                                      L_rr_node_indices, rr_graph,
                                                       sb_conn_map, from_rr_node, rr_edges_to_create);
                 }
             } else {
@@ -1645,7 +1726,7 @@ int get_track_to_tracks(const int from_chan,
                      * switchbox, so we follow through regardless of whether the current segment has an SB */
                     conn_tracks = switch_block_conn[from_side_a][to_side][from_track];
                     num_conn += get_bidir_track_to_chan_seg(conn_tracks,
-                                                            rr_graph, to_chan, to_seg, to_sb, to_type,
+                                                            L_rr_node_indices, rr_graph, to_chan, to_seg, to_sb, to_type,
                                                             to_seg_details, from_is_sblock, from_switch,
                                                             switch_override,
                                                             directionality, from_rr_node, rr_edges_to_create);
@@ -1660,7 +1741,7 @@ int get_track_to_tracks(const int from_chan,
                                                                  from_side_a, to_side, Fs_per_side,
                                                                  sblock_pattern,
                                                                  switch_override,
-                                                                 rr_graph, to_seg_details,
+                                                                 L_rr_node_indices, rr_graph, to_seg_details,
                                                                  &Fs_clipped, from_rr_node, rr_edges_to_create);
                     }
                 }
@@ -1675,7 +1756,7 @@ int get_track_to_tracks(const int from_chan,
                     num_conn += get_track_to_chan_seg(from_track, to_chan, to_seg,
                                                       to_type, from_side_b, to_side,
                                                       switch_override,
-                                                      rr_graph,
+                                                      L_rr_node_indices, rr_graph,
                                                       sb_conn_map, from_rr_node, rr_edges_to_create);
                 }
             } else {
@@ -1684,7 +1765,7 @@ int get_track_to_tracks(const int from_chan,
                      * switchbox, so we follow through regardless of whether the current segment has an SB */
                     conn_tracks = switch_block_conn[from_side_b][to_side][from_track];
                     num_conn += get_bidir_track_to_chan_seg(conn_tracks,
-                                                            rr_graph, to_chan, to_seg, to_sb, to_type,
+                                                            L_rr_node_indices, rr_graph, to_chan, to_seg, to_sb, to_type,
                                                             to_seg_details, from_is_sblock, from_switch,
                                                             switch_override,
                                                             directionality, from_rr_node, rr_edges_to_create);
@@ -1700,7 +1781,7 @@ int get_track_to_tracks(const int from_chan,
                                                                  from_side_b, to_side, Fs_per_side,
                                                                  sblock_pattern,
                                                                  switch_override,
-                                                                 rr_graph, to_seg_details,
+                                                                 L_rr_node_indices, rr_graph, to_seg_details,
                                                                  &Fs_clipped, from_rr_node, rr_edges_to_create);
                     }
                 }
@@ -1712,6 +1793,7 @@ int get_track_to_tracks(const int from_chan,
 }
 
 static int get_bidir_track_to_chan_seg(const std::vector<int> conn_tracks,
+                                       const t_rr_node_indices& L_rr_node_indices,
                                        const RRGraph& rr_graph,
                                        const int to_chan,
                                        const int to_seg,
@@ -1744,9 +1826,9 @@ static int get_bidir_track_to_chan_seg(const std::vector<int> conn_tracks,
     num_conn = 0;
     for (iconn = 0; iconn < conn_tracks.size(); ++iconn) {
         to_track = conn_tracks[iconn];
-        to_node = rr_graph.find_node(to_x, to_y, to_type, to_track);
+        to_node = get_rr_graph_node_index(L_rr_node_indices, to_x, to_y, to_type, to_track);
 
-        if (to_node == RRNodeId::INVALID()) {
+        if (false == rr_graph.valid_node_id(to_node)) {
             continue;
         }
 
@@ -1787,6 +1869,7 @@ static int get_track_to_chan_seg(const int from_wire,
                                  const e_side from_side,
                                  const e_side to_side,
                                  const int switch_override,
+                                 const t_rr_node_indices& L_rr_node_indices,
                                  const RRGraph& rr_graph,
                                  t_sb_connection_map* sb_conn_map,
                                  const RRNodeId& from_rr_node,
@@ -1823,9 +1906,9 @@ static int get_track_to_chan_seg(const int from_wire,
             if (conn_vector.at(iconn).from_wire != from_wire) continue;
 
             int to_wire = conn_vector.at(iconn).to_wire;
-            RRNodeId to_node = rr_graph.find_node(to_x, to_y, to_chan_type, to_wire);
+            RRNodeId to_node = RRNodeId(get_rr_node_index(L_rr_node_indices, to_x, to_y, to_chan_type, to_wire));
 
-            if (to_node == RRNodeId::INVALID()) {
+            if (false == rr_graph.valid_node_id(to_node)) {
                 continue;
             }
 
@@ -1866,6 +1949,7 @@ static int get_unidir_track_to_chan_seg(const int from_track,
                                         const int Fs_per_side,
                                         t_sblock_pattern& sblock_pattern,
                                         const int switch_override,
+                                        const t_rr_node_indices& L_rr_node_indices,
                                         const RRGraph& rr_graph,
                                         const t_chan_seg_details* seg_details,
                                         bool* Fs_clipped,
@@ -1923,9 +2007,9 @@ static int get_unidir_track_to_chan_seg(const int from_track,
                 sblock_pattern[sb_x][sb_y][from_side][to_side][from_track][j + 1] = to_track;
             }
 
-            RRNodeId to_node = rr_graph.find_node(to_x, to_y, to_type, to_track);
+            RRNodeId to_node = get_rr_graph_node_index(L_rr_node_indices, to_x, to_y, to_type, to_track);
 
-            if (to_node == RRNodeId::INVALID()) {
+            if (false == rr_graph.valid_node_id(to_node)) {
                 continue;
             }
 
diff --git a/vpr/src/route/rr_graph2.h b/vpr/src/route/rr_graph2.h
index 6aa5cae68..30d68d6db 100644
--- a/vpr/src/route/rr_graph2.h
+++ b/vpr/src/route/rr_graph2.h
@@ -47,11 +47,11 @@ typedef vtr::NdMatrix<short, 6> t_sblock_pattern;
 
 /******************* Subroutines exported by rr_graph2.c *********************/
 
-RRGraph alloc_and_load_rr_node_indices(const int max_chan_width,
-                                       const DeviceGrid& grid,
-                                       int* index,
-                                       const t_chan_details& chan_details_x,
-                                       const t_chan_details& chan_details_y);
+t_rr_node_indices alloc_and_load_rr_node_indices(const int max_chan_width,
+                                                 const DeviceGrid& grid,
+                                                 int* index,
+                                                 const t_chan_details& chan_details_x,
+                                                 const t_chan_details& chan_details_y);
 
 int get_rr_node_index(int x,
                       int y,
@@ -59,7 +59,14 @@ int get_rr_node_index(int x,
                       int ptc,
                       const t_rr_node_indices& L_rr_node_indices);
 
+
 //Returns all the rr nodes associated with the specified coordinate (i.e. accross sides)
+std::vector<RRNodeId> get_rr_graph_node_indices(const t_rr_node_indices& L_rr_node_indices,
+                                                int x,
+                                                int y,
+                                                t_rr_type rr_type,
+                                                int ptc);
+
 std::vector<int> get_rr_node_indices(const t_rr_node_indices& L_rr_node_indices,
                                      int x,
                                      int y,
@@ -74,6 +81,13 @@ std::vector<int> get_rr_node_chan_wires_at_location(const t_rr_node_indices& L_r
 
 //Return the first rr node of the specified type and coordinates
 // For non-IPIN/OPIN types 'side' is ignored
+RRNodeId get_rr_graph_node_index(const t_rr_node_indices& L_rr_node_indices,
+                                 int x,
+                                 int y,
+                                 t_rr_type rr_type,
+                                 int ptc,
+                                 e_side side = NUM_SIDES);
+
 int get_rr_node_index(const t_rr_node_indices& L_rr_node_indices,
                       int x,
                       int y,
@@ -156,7 +170,7 @@ int get_bidir_opin_connections(const int i,
                                const RRNodeId& from_rr_node,
                                t_rr_edge_info_set& rr_edges_to_create,
                                const t_pin_to_track_lookup& opin_to_track_map,
-                               const RRGraph& rr_graph,
+                               const t_rr_node_indices& L_rr_node_indices,
                                const t_chan_details& chan_details_x,
                                const t_chan_details& chan_details_y);
 
@@ -171,7 +185,7 @@ int get_unidir_opin_connections(const int chan,
                                 vtr::NdMatrix<int, 3>& Fc_ofs,
                                 const int max_len,
                                 const int max_chan_width,
-                                const RRGraph& rr_graph,
+                                const t_rr_node_indices& L_rr_node_indices,
                                 bool* Fc_clipped);
 
 int get_track_to_pins(int seg,
@@ -180,6 +194,7 @@ int get_track_to_pins(int seg,
                       int tracks_per_chan,
                       const RRNodeId& from_rr_node,
                       t_rr_edge_info_set& rr_edges_to_create,
+                      const t_rr_node_indices& L_rr_node_indices,
                       const RRGraph& rr_graph,
                       const t_track_to_pin_lookup& track_to_pin_lookup,
                       const t_chan_seg_details* seg_details,
@@ -205,6 +220,7 @@ int get_track_to_tracks(const int from_chan,
                         const t_chan_seg_details* to_seg_details,
                         const t_chan_details& to_chan_details,
                         const enum e_directionality directionality,
+                        const t_rr_node_indices& L_rr_node_indices,
                         const RRGraph& rr_graph,
                         const vtr::NdMatrix<std::vector<int>, 3>& switch_block_conn,
                         t_sb_connection_map* sb_conn_map);

From 969dd7c4676dec75cc462640abefdc016ba272e4 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 4 Feb 2020 15:33:15 -0700
Subject: [PATCH 095/645] rr_graph working

---
 vpr/src/route/route_timing.cpp | 12 ++++++------
 vpr/src/route/route_util.cpp   | 27 +++++++++++++--------------
 2 files changed, 19 insertions(+), 20 deletions(-)

diff --git a/vpr/src/route/route_timing.cpp b/vpr/src/route/route_timing.cpp
index 156197be7..131044b68 100644
--- a/vpr/src/route/route_timing.cpp
+++ b/vpr/src/route/route_timing.cpp
@@ -2598,19 +2598,19 @@ static OveruseInfo calculate_overuse_info() {
         }
     }
 
-    return OveruseInfo(device_ctx.rr_nodes.size(), overused_nodes, total_overuse, worst_overuse);
+    return OveruseInfo(device_ctx.rr_graph.nodes().size(), overused_nodes, total_overuse, worst_overuse);
 }
 
 static size_t calculate_wirelength_available() {
     auto& device_ctx = g_vpr_ctx.device();
 
     size_t available_wirelength = 0;
-    for (size_t i = 0; i < device_ctx.rr_nodes.size(); ++i) {
-        if (device_ctx.rr_nodes[i].type() == CHANX || device_ctx.rr_nodes[i].type() == CHANY) {
-            size_t length_x = device_ctx.rr_nodes[i].xhigh() - device_ctx.rr_nodes[i].xlow();
-            size_t length_y = device_ctx.rr_nodes[i].yhigh() - device_ctx.rr_nodes[i].ylow();
+    for (const RRNodeId& node : device_ctx.rr_graph.nodes()) {
+        if (device_ctx.rr_graph.node_type(node) == CHANX || device_ctx.rr_graph.node_type(node) == CHANY) {
+            size_t length_x = device_ctx.rr_graph.node_xhigh(node) - device_ctx.rr_graph.node_xlow(node);
+            size_t length_y = device_ctx.rr_graph.node_yhigh(node) - device_ctx.rr_graph.node_ylow(node);
 
-            available_wirelength += device_ctx.rr_nodes[i].capacity() * (length_x + length_y + 1);
+            available_wirelength += device_ctx.rr_graph.node_capacity(node) * (length_x + length_y + 1);
         }
     }
     return available_wirelength;
diff --git a/vpr/src/route/route_util.cpp b/vpr/src/route/route_util.cpp
index 6d8417963..d61e8d8f6 100644
--- a/vpr/src/route/route_util.cpp
+++ b/vpr/src/route/route_util.cpp
@@ -55,24 +55,23 @@ vtr::Matrix<float> calculate_routing_avail(t_rr_type rr_type) {
     auto& device_ctx = g_vpr_ctx.device();
 
     vtr::Matrix<float> avail({{device_ctx.grid.width(), device_ctx.grid.height()}}, 0.);
-    for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); ++inode) {
-        auto& rr_node = device_ctx.rr_nodes[inode];
+    for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) {
 
-        if (rr_node.type() == CHANX && rr_type == CHANX) {
-            VTR_ASSERT(rr_node.type() == CHANX);
-            VTR_ASSERT(rr_node.ylow() == rr_node.yhigh());
+        if (device_ctx.rr_graph.node_type(inode) == CHANX && rr_type == CHANX) {
+            VTR_ASSERT(device_ctx.rr_graph.node_type(inode) == CHANX);
+            VTR_ASSERT(device_ctx.rr_graph.node_ylow(inode) == device_ctx.rr_graph.node_yhigh(inode));
 
-            int y = rr_node.ylow();
-            for (int x = rr_node.xlow(); x <= rr_node.xhigh(); ++x) {
-                avail[x][y] += rr_node.capacity();
+            int y = device_ctx.rr_graph.node_ylow(inode);
+            for (int x = device_ctx.rr_graph.node_xlow(inode); x <= device_ctx.rr_graph.node_xhigh(inode); ++x) {
+                avail[x][y] += device_ctx.rr_graph.node_capacity(inode);
             }
-        } else if (rr_node.type() == CHANY && rr_type == CHANY) {
-            VTR_ASSERT(rr_node.type() == CHANY);
-            VTR_ASSERT(rr_node.xlow() == rr_node.xhigh());
+        } else if (device_ctx.rr_graph.node_type(inode) == CHANY && rr_type == CHANY) {
+            VTR_ASSERT(device_ctx.rr_graph.node_type(inode) == CHANY);
+            VTR_ASSERT(device_ctx.rr_graph.node_xlow(inode) == device_ctx.rr_graph.node_xhigh(inode));
 
-            int x = rr_node.xlow();
-            for (int y = rr_node.ylow(); y <= rr_node.yhigh(); ++y) {
-                avail[x][y] += rr_node.capacity();
+            int x = device_ctx.rr_graph.node_xlow(inode);
+            for (int y = device_ctx.rr_graph.node_ylow(inode); y <= device_ctx.rr_graph.node_yhigh(inode); ++y) {
+                avail[x][y] += device_ctx.rr_graph.node_capacity(inode);
             }
         }
     }

From e3db937daadb79c6cdbdae0370bf594c766ecf08 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 4 Feb 2020 16:20:25 -0700
Subject: [PATCH 096/645] fixed routing stats

---
 vpr/src/route/rr_graph.cpp | 9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp
index f9a87bfea..1b39dfc35 100644
--- a/vpr/src/route/rr_graph.cpp
+++ b/vpr/src/route/rr_graph.cpp
@@ -404,13 +404,8 @@ void create_rr_graph(const t_graph_type graph_type,
 void print_rr_graph_stats() {
     auto& device_ctx = g_vpr_ctx.device();
 
-    size_t num_rr_edges = 0;
-    for (auto& rr_node : device_ctx.rr_nodes) {
-        num_rr_edges += rr_node.edges().size();
-    }
-
-    VTR_LOG("  RR Graph Nodes: %zu\n", device_ctx.rr_nodes.size());
-    VTR_LOG("  RR Graph Edges: %zu\n", num_rr_edges);
+    VTR_LOG("  RR Graph Nodes: %zu\n", device_ctx.rr_graph.nodes().size());
+    VTR_LOG("  RR Graph Edges: %zu\n", device_ctx.rr_graph.edges().size());
 }
 
 bool channel_widths_unchanged(const t_chan_width& current, const t_chan_width& proposed) {

From f098d40af1b9f54f36cefe12c5888e96d924633d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 4 Feb 2020 16:48:15 -0700
Subject: [PATCH 097/645] correct missing rr_nodes usage to rr_graph obj

---
 vpr/src/draw/search_bar.cpp             |  2 +-
 vpr/src/route/rr_graph.cpp              |  2 --
 vpr/src/route/rr_graph_indexed_data.cpp |  6 +++---
 vpr/src/util/vpr_utils.cpp              | 18 ++++++++----------
 4 files changed, 12 insertions(+), 16 deletions(-)

diff --git a/vpr/src/draw/search_bar.cpp b/vpr/src/draw/search_bar.cpp
index a7ff3831b..be8705ff1 100644
--- a/vpr/src/draw/search_bar.cpp
+++ b/vpr/src/draw/search_bar.cpp
@@ -68,7 +68,7 @@ void search_and_highlight(GtkWidget* /*widget*/, ezgl::application* app) {
         ss >> rr_node_id;
 
         // valid rr node id check
-        if (rr_node_id < 0 || rr_node_id >= int(device_ctx.rr_nodes.size())) {
+        if (rr_node_id < 0 || rr_node_id >= int(device_ctx.rr_graph.nodes().size())) {
             warning_dialog_box("Invalid RR Node ID");
             app->refresh_drawing();
             return;
diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp
index 1b39dfc35..25d4ed387 100644
--- a/vpr/src/route/rr_graph.cpp
+++ b/vpr/src/route/rr_graph.cpp
@@ -1874,8 +1874,6 @@ void alloc_and_load_edges(RRGraph& rr_graph,
     for (RRNodeId inode : from_nodes) {
         auto edge_range = std::equal_range(rr_edges_to_create.begin(), rr_edges_to_create.end(), inode, compare_from_node());
 
-        size_t edge_count = std::distance(edge_range.first, edge_range.second);
-
         //Create initial edges
         //
         //Note that we do this in bulk instead of via add_edge() to reduce
diff --git a/vpr/src/route/rr_graph_indexed_data.cpp b/vpr/src/route/rr_graph_indexed_data.cpp
index 3982bcb64..b131532f8 100644
--- a/vpr/src/route/rr_graph_indexed_data.cpp
+++ b/vpr/src/route/rr_graph_indexed_data.cpp
@@ -219,10 +219,10 @@ static std::vector<size_t> count_rr_segment_types() {
 
     auto& device_ctx = g_vpr_ctx.device();
 
-    for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); ++inode) {
-        if (device_ctx.rr_nodes[inode].type() != CHANX && device_ctx.rr_nodes[inode].type() != CHANY) continue;
+    for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) {
+        if (device_ctx.rr_graph.node_type(inode) != CHANX && device_ctx.rr_graph.node_type(inode) != CHANY) continue;
 
-        int cost_index = device_ctx.rr_nodes[inode].cost_index();
+        int cost_index = device_ctx.rr_graph.node_cost_index(inode);
 
         int seg_index = device_ctx.rr_indexed_data[cost_index].seg_index;
 
diff --git a/vpr/src/util/vpr_utils.cpp b/vpr/src/util/vpr_utils.cpp
index dfac49522..1f28401ca 100644
--- a/vpr/src/util/vpr_utils.cpp
+++ b/vpr/src/util/vpr_utils.cpp
@@ -1951,13 +1951,11 @@ void print_switch_usage() {
     switch_fanin_delay = new std::map<int, float>[device_ctx.num_arch_switches];
     // a node can have multiple inward switches, so
     // map key: switch index; map value: count (fanin)
-    std::map<int, int>* inward_switch_inf = new std::map<int, int>[device_ctx.rr_nodes.size()];
-    for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); inode++) {
-        const t_rr_node& from_node = device_ctx.rr_nodes[inode];
-        int num_edges = from_node.num_edges();
-        for (int iedge = 0; iedge < num_edges; iedge++) {
-            int switch_index = from_node.edge_switch(iedge);
-            int to_node_index = from_node.edge_sink_node(iedge);
+    vtr::vector<RRNodeId, std::map<int, int>> inward_switch_inf(device_ctx.rr_graph.nodes().size());
+    for (const RRNodeId& from_node : device_ctx.rr_graph.nodes()) {
+        for (const RREdgeId& iedge : device_ctx.rr_graph.node_out_edges(from_node)) {
+            int switch_index = (int)size_t(device_ctx.rr_graph.edge_switch(iedge));
+            const RRNodeId& to_node_index = device_ctx.rr_graph.edge_sink_node(iedge);
             // Assumption: suppose for a L4 wire (bi-directional): ----+----+----+----, it can be driven from any point (0, 1, 2, 3).
             //             physically, the switch driving from point 1 & 3 should be the same. But we will assign then different switch
             //             index; or there is no way to differentiate them after abstracting a 2D wire into a 1D node
@@ -1967,7 +1965,7 @@ void print_switch_usage() {
             inward_switch_inf[to_node_index][switch_index]++;
         }
     }
-    for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); inode++) {
+    for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) {
         std::map<int, int>::iterator itr;
         for (itr = inward_switch_inf[inode].begin(); itr != inward_switch_inf[inode].end(); itr++) {
             int switch_index = itr->first;
@@ -1977,7 +1975,7 @@ void print_switch_usage() {
             if (status == -1) {
                 delete[] switch_fanin_count;
                 delete[] switch_fanin_delay;
-                delete[] inward_switch_inf;
+                inward_switch_inf.clear();
                 return;
             }
             if (switch_fanin_count[switch_index].count(fanin) == 0) {
@@ -2003,7 +2001,7 @@ void print_switch_usage() {
     VTR_LOG("\n==================================================\n\n");
     delete[] switch_fanin_count;
     delete[] switch_fanin_delay;
-    delete[] inward_switch_inf;
+    inward_switch_inf.clear();
 }
 
 /*

From 0cce1f4efcc6e3d8fadf7d65a767298122f40161 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 4 Feb 2020 17:31:39 -0700
Subject: [PATCH 098/645] bug fixing for heterogenenous FPGA when using the
 RRGraph object

---
 vpr/src/place/timing_place_lookup.cpp | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/vpr/src/place/timing_place_lookup.cpp b/vpr/src/place/timing_place_lookup.cpp
index dd55adca4..a067c3cc3 100644
--- a/vpr/src/place/timing_place_lookup.cpp
+++ b/vpr/src/place/timing_place_lookup.cpp
@@ -302,18 +302,24 @@ static float route_connection_delay(
     //Get the rr nodes to route between
     auto best_driver_ptcs = get_best_classes(DRIVER, device_ctx.grid[source_x][source_y].type);
     auto best_sink_ptcs = get_best_classes(RECEIVER, device_ctx.grid[sink_x][sink_y].type);
+ 
+    int src_width_offset = device_ctx.grid[source_x][source_y].width_offset;
+    int src_height_offset = device_ctx.grid[source_x][source_y].height_offset;
+
+    int sink_width_offset = device_ctx.grid[sink_x][sink_y].width_offset;
+    int sink_height_offset = device_ctx.grid[sink_x][sink_y].height_offset;
 
     for (int driver_ptc : best_driver_ptcs) {
         VTR_ASSERT(driver_ptc != OPEN);
 
-        RRNodeId source_rr_node = device_ctx.rr_graph.find_node(source_x, source_y, SOURCE, driver_ptc);
+        RRNodeId source_rr_node = device_ctx.rr_graph.find_node(source_x - src_width_offset, source_y - src_height_offset, SOURCE, driver_ptc);
 
         VTR_ASSERT(source_rr_node != RRNodeId::INVALID());
 
         for (int sink_ptc : best_sink_ptcs) {
             VTR_ASSERT(sink_ptc != OPEN);
 
-            RRNodeId sink_rr_node = device_ctx.rr_graph.find_node(sink_x, sink_y, SINK, sink_ptc);
+            RRNodeId sink_rr_node = device_ctx.rr_graph.find_node(sink_x - sink_width_offset, sink_y - sink_height_offset, SINK, sink_ptc);
 
             VTR_ASSERT(sink_rr_node != RRNodeId::INVALID());
 

From a3a85bf259a3f6c6c4a8ab1f5d2d9f861d0566d6 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 4 Feb 2020 20:45:14 -0700
Subject: [PATCH 099/645] bug fix for direct connections in rr_graph builder

---
 vpr/src/route/rr_graph.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp
index 25d4ed387..e17a0c912 100644
--- a/vpr/src/route/rr_graph.cpp
+++ b/vpr/src/route/rr_graph.cpp
@@ -3006,14 +3006,14 @@ static int get_opin_direct_connections(int x,
 
                         if (directs[i].to_side != NUM_SIDES) {
                             //Explicit side specified, only create if pin exists on that side
-                            RRNodeId inode = rr_graph.find_node(x + directs[i].x_offset, y + directs[i].y_offset,
+                            RRNodeId inode = get_rr_graph_node_index(L_rr_node_indices, x + directs[i].x_offset - width_offset, y + directs[i].y_offset - height_offset,
                                                           IPIN, ipin, directs[i].to_side);
                             if (inode != RRNodeId::INVALID()) {
                                 inodes.push_back(inode);
                             }
                         } else {
                             //No side specified, get all candidates
-                            inodes = get_rr_graph_node_indices(L_rr_node_indices, x + directs[i].x_offset, y + directs[i].y_offset,
+                            inodes = get_rr_graph_node_indices(L_rr_node_indices, x + directs[i].x_offset - width_offset, y + directs[i].y_offset - height_offset,
                                                                IPIN, ipin);
                         }
 

From ecc3b8a4f079c64665bdfa13f9ab101dabc25f27 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 4 Feb 2020 21:02:55 -0700
Subject: [PATCH 100/645] bug fix in router lookhead map when find rr_graph
 nodes

---
 vpr/src/route/router_lookahead_map.cpp | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/vpr/src/route/router_lookahead_map.cpp b/vpr/src/route/router_lookahead_map.cpp
index 42de703b5..a4ad36225 100644
--- a/vpr/src/route/router_lookahead_map.cpp
+++ b/vpr/src/route/router_lookahead_map.cpp
@@ -25,6 +25,7 @@
 #include "vtr_log.h"
 #include "vtr_assert.h"
 #include "vtr_time.h"
+#include "rr_graph_obj_util.h"
 #include "router_lookahead_map.h"
 
 /* the cost map is computed by running a Dijkstra search from channel segment rr nodes at the specified reference coordinate */
@@ -310,10 +311,7 @@ static RRNodeId get_start_node_ind(int start_x, int start_y, int target_x, int t
      * we can get the number of tracks for a 
      * routing channel and then get the node one by one 
      */
-    short num_tracks = device_ctx.rr_graph.chan_num_tracks(start_x, start_y, rr_type); 
-    for (short i = 0; i < num_tracks; ++i) {
-      channel_node_list.push_back(device_ctx.rr_graph.find_node(start_x, start_y, rr_type, i));
-    }
+    channel_node_list = find_rr_graph_chan_nodes(device_ctx.rr_graph, start_x, start_y, rr_type);
 
     /* find first node in channel that has specified segment index and goes in the desired direction */
     for (const RRNodeId& node_ind : channel_node_list) {

From e2f408cc2d055fabc665ebb6560116294d04682d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 4 Feb 2020 21:32:05 -0700
Subject: [PATCH 101/645] bug fix for clock network builder using rr_graph
 object

---
 vpr/src/device/rr_graph_obj.cpp          | 6 ++++--
 vpr/src/device/rr_graph_obj.h            | 2 +-
 vpr/src/route/clock_network_builders.cpp | 8 ++++----
 3 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/vpr/src/device/rr_graph_obj.cpp b/vpr/src/device/rr_graph_obj.cpp
index 1b738d212..da528cf26 100644
--- a/vpr/src/device/rr_graph_obj.cpp
+++ b/vpr/src/device/rr_graph_obj.cpp
@@ -846,10 +846,12 @@ RRNodeId RRGraph::create_node(const t_rr_type& type) {
     return node_id;
 }
 
-RREdgeId RRGraph::create_edge(const RRNodeId& source, const RRNodeId& sink, const RRSwitchId& switch_id) {
+RREdgeId RRGraph::create_edge(const RRNodeId& source, const RRNodeId& sink, const RRSwitchId& switch_id, const bool& fake_switch) {
     VTR_ASSERT(valid_node_id(source));
     VTR_ASSERT(valid_node_id(sink));
-    VTR_ASSERT(valid_switch_id(switch_id));
+    if (false == fake_switch) {
+      VTR_ASSERT(valid_switch_id(switch_id));
+    }
 
     /* Allocate an ID */
     RREdgeId edge_id = RREdgeId(num_edges_);
diff --git a/vpr/src/device/rr_graph_obj.h b/vpr/src/device/rr_graph_obj.h
index fd8439868..08abf682c 100644
--- a/vpr/src/device/rr_graph_obj.h
+++ b/vpr/src/device/rr_graph_obj.h
@@ -614,7 +614,7 @@ class RRGraph {
      * This function will automatically create a node and
      * configure the nodes and edges in connection   
      */
-    RREdgeId create_edge(const RRNodeId& source, const RRNodeId& sink, const RRSwitchId& switch_id);
+    RREdgeId create_edge(const RRNodeId& source, const RRNodeId& sink, const RRSwitchId& switch_id, const bool& fake_switch=false);
     void set_edge_switch(const RREdgeId& edge, const RRSwitchId& switch_id);
     RRSwitchId create_switch(const t_rr_switch_inf& switch_info);
     RRSegmentId create_segment(const t_segment_inf& segment_info);
diff --git a/vpr/src/route/clock_network_builders.cpp b/vpr/src/route/clock_network_builders.cpp
index b90babdae..5fbd854ca 100644
--- a/vpr/src/route/clock_network_builders.cpp
+++ b/vpr/src/route/clock_network_builders.cpp
@@ -255,8 +255,8 @@ void ClockRib::create_rr_nodes_and_internal_edges_for_one_instance(ClockRRGraphB
                                  clock_graph);
 
             // connect drive point to each half rib using a directed switch
-            rr_graph.create_edge(drive_node_idx, left_node_idx, RRSwitchId(drive.switch_idx));
-            rr_graph.create_edge(drive_node_idx, right_node_idx, RRSwitchId(drive.switch_idx));
+            rr_graph.create_edge(drive_node_idx, left_node_idx, RRSwitchId(drive.switch_idx), true);
+            rr_graph.create_edge(drive_node_idx, right_node_idx, RRSwitchId(drive.switch_idx), true);
         }
     }
 }
@@ -501,8 +501,8 @@ void ClockSpine::create_rr_nodes_and_internal_edges_for_one_instance(ClockRRGrap
                                  clock_graph);
 
             // connect drive point to each half spine using a directed switch
-            rr_graph.create_edge(drive_node_idx, left_node_idx, RRSwitchId(drive.switch_idx));
-            rr_graph.create_edge(drive_node_idx, right_node_idx, RRSwitchId(drive.switch_idx));
+            rr_graph.create_edge(drive_node_idx, left_node_idx, RRSwitchId(drive.switch_idx), true);
+            rr_graph.create_edge(drive_node_idx, right_node_idx, RRSwitchId(drive.switch_idx), true);
         }
     }
 }

From 7092ddbde658473fa11ba06b1b2504fa69371458 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 4 Feb 2020 21:54:03 -0700
Subject: [PATCH 102/645] bug fix for root node builder by including ptc_num!!

---
 vpr/src/route/clock_connection_builders.cpp | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/vpr/src/route/clock_connection_builders.cpp b/vpr/src/route/clock_connection_builders.cpp
index b36fee966..f27295590 100644
--- a/vpr/src/route/clock_connection_builders.cpp
+++ b/vpr/src/route/clock_connection_builders.cpp
@@ -98,6 +98,11 @@ RRNodeId RoutingToClockConnection::create_virtual_clock_network_sink_node(
     float C = 0.;
     rr_graph.set_node_rc_data_index(node_index, find_create_rr_rc_data(R, C));
 
+    /* Set a ptc_num here as RRGraph object does need it to build fast look-up
+     * Legacy codes fail to do this!
+     */
+    rr_graph.set_node_ptc_num(node_index, device_ctx.grid[x][y].type->num_class);
+
     return node_index;
 }
 

From e89d8e4493abe58a82fd467ddddddb166ca47b57 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 4 Feb 2020 21:56:54 -0700
Subject: [PATCH 103/645] bug fix for clock connection builder by supporting
 fake switch when adding edges to RRGraph object

---
 vpr/src/route/clock_connection_builders.cpp | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/vpr/src/route/clock_connection_builders.cpp b/vpr/src/route/clock_connection_builders.cpp
index f27295590..96e4fd722 100644
--- a/vpr/src/route/clock_connection_builders.cpp
+++ b/vpr/src/route/clock_connection_builders.cpp
@@ -68,18 +68,18 @@ void RoutingToClockConnection::create_switches(const ClockRRGraphBuilder& clock_
         // Connect to x-channel wires
         unsigned num_wires_x = x_wire_indices.size() * fc;
         for (size_t i = 0; i < num_wires_x; i++) {
-            rr_graph.create_edge(x_wire_indices[i], clock_index, RRSwitchId(rr_switch_idx));
+            rr_graph.create_edge(x_wire_indices[i], clock_index, RRSwitchId(rr_switch_idx), true);
         }
 
         // Connect to y-channel wires
         unsigned num_wires_y = y_wire_indices.size() * fc;
         for (size_t i = 0; i < num_wires_y; i++) {
-            rr_graph.create_edge(y_wire_indices[i], clock_index, RRSwitchId(rr_switch_idx));
+            rr_graph.create_edge(y_wire_indices[i], clock_index, RRSwitchId(rr_switch_idx), true);
         }
 
         // Connect to virtual clock sink node
         // used by the two stage router
-        rr_graph.create_edge(clock_index, virtual_clock_network_root_idx, RRSwitchId(rr_switch_idx));
+        rr_graph.create_edge(clock_index, virtual_clock_network_root_idx, RRSwitchId(rr_switch_idx), true);
     }
 }
 
@@ -183,7 +183,7 @@ void ClockToClockConneciton::create_switches(const ClockRRGraphBuilder& clock_gr
                 if (from_itter == from_rr_node_indices.end()) {
                     from_itter = from_rr_node_indices.begin();
                 }
-                rr_graph.create_edge(*from_itter, to_index, RRSwitchId(rr_switch_idx));
+                rr_graph.create_edge(*from_itter, to_index, RRSwitchId(rr_switch_idx), true);
                 from_itter++;
             }
         }
@@ -292,7 +292,7 @@ void ClockToPinsConnection::create_switches(const ClockRRGraphBuilder& clock_gra
 
                     //Create edges depending on Fc
                     for (size_t i = 0; i < clock_network_indices.size() * fc; i++) {
-                        rr_graph.create_edge(clock_network_indices[i], clock_pin_node_idx, RRSwitchId(rr_switch_idx));
+                        rr_graph.create_edge(clock_network_indices[i], clock_pin_node_idx, RRSwitchId(rr_switch_idx), true);
                     }
                 }
             }

From dad204674bcf4cbb803c497d77dfdc599a9eb8aa Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 5 Feb 2020 21:50:52 -0700
Subject: [PATCH 104/645] done an initial version of clustering net fix-up
 based on routing results. Debugging on the way

---
 .../annotation/vpr_clustering_annotation.cpp  |  49 +++++
 .../annotation/vpr_clustering_annotation.h    |  40 ++++
 .../src/annotation/vpr_routing_annotation.cpp |  47 +++++
 .../src/annotation/vpr_routing_annotation.h   |  40 ++++
 openfpga/src/base/openfpga_context.h          |   9 +
 openfpga/src/base/openfpga_link_arch.cpp      |   8 +
 openfpga/src/base/openfpga_pb_pin_fixup.cpp   | 184 ++++++++++++++++++
 openfpga/src/base/openfpga_pb_pin_fixup.h     |  23 +++
 openfpga/src/base/openfpga_setup_command.cpp  |  20 +-
 openfpga/test_script/s298_k6_frac.openfpga    |   3 +
 10 files changed, 422 insertions(+), 1 deletion(-)
 create mode 100644 openfpga/src/annotation/vpr_clustering_annotation.cpp
 create mode 100644 openfpga/src/annotation/vpr_clustering_annotation.h
 create mode 100644 openfpga/src/annotation/vpr_routing_annotation.cpp
 create mode 100644 openfpga/src/annotation/vpr_routing_annotation.h
 create mode 100644 openfpga/src/base/openfpga_pb_pin_fixup.cpp
 create mode 100644 openfpga/src/base/openfpga_pb_pin_fixup.h

diff --git a/openfpga/src/annotation/vpr_clustering_annotation.cpp b/openfpga/src/annotation/vpr_clustering_annotation.cpp
new file mode 100644
index 000000000..747978023
--- /dev/null
+++ b/openfpga/src/annotation/vpr_clustering_annotation.cpp
@@ -0,0 +1,49 @@
+/************************************************************************
+ * Member functions for class VprClusteringAnnotation
+ ***********************************************************************/
+#include "vtr_log.h"
+#include "vtr_assert.h"
+#include "vpr_clustering_annotation.h"
+
+/* namespace openfpga begins */
+namespace openfpga {
+
+/************************************************************************
+ * Constructors
+ ***********************************************************************/
+VprClusteringAnnotation::VprClusteringAnnotation() {
+  return;
+}
+
+/************************************************************************
+ * Public accessors
+ ***********************************************************************/
+bool VprClusteringAnnotation::is_net_renamed(const ClusterBlockId& block_id, const int& pin_index) const {
+  /* Ensure that the block_id is in the list */
+  if (net_names_.end() == net_names_.find(block_id)) {
+    return false;
+  }
+  return (net_names_.at(block_id).end() != net_names_.at(block_id).find(pin_index));
+}
+
+ClusterNetId VprClusteringAnnotation::net(const ClusterBlockId& block_id, const int& pin_index) const {
+  VTR_ASSERT(true == is_net_renamed(block_id, pin_index));
+  return net_names_.at(block_id).at(pin_index);
+}
+
+/************************************************************************
+ * Public mutators
+ ***********************************************************************/
+void VprClusteringAnnotation::rename_net(const ClusterBlockId& block_id, const int& pin_index,
+                                                const ClusterNetId& net_id) {
+  /* Warn any override attempt */
+  if ( (net_names_.end() != net_names_.find(block_id))
+    && (net_names_.at(block_id).end() != net_names_.at(block_id).find(pin_index)) ) {
+    VTR_LOG_WARN("Override the net '%ld' for block '%ld' pin '%d' with in clustering context annotation!\n",
+                 size_t(net_id), size_t(block_id), pin_index);
+  }
+
+  net_names_[block_id][pin_index] = net_id;
+}
+
+} /* End namespace openfpga*/
diff --git a/openfpga/src/annotation/vpr_clustering_annotation.h b/openfpga/src/annotation/vpr_clustering_annotation.h
new file mode 100644
index 000000000..5918a10b8
--- /dev/null
+++ b/openfpga/src/annotation/vpr_clustering_annotation.h
@@ -0,0 +1,40 @@
+#ifndef VPR_CLUSTERING_ANNOTATION_H
+#define VPR_CLUSTERING_ANNOTATION_H
+
+/********************************************************************
+ * Include header files required by the data structure definition
+ *******************************************************************/
+#include <map> 
+
+/* Header from vpr library */
+#include "clustered_netlist.h"
+
+/* Begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * This is the critical data structure to link the pb_type in VPR
+ * to openfpga annotations
+ * With a given pb_type pointer, it aims to identify:
+ * 1. if the pb_type is a physical pb_type or a operating pb_type
+ * 2. what is the circuit model id linked to a physical pb_type
+ * 3. what is the physical pb_type for an operating pb_type
+ * 4. what is the mode pointer that represents the physical mode for a pb_type
+ *******************************************************************/
+class VprClusteringAnnotation {
+  public:  /* Constructor */
+    VprClusteringAnnotation();
+  public:  /* Public accessors */
+    bool is_net_renamed(const ClusterBlockId& block_id, const int& pin_index) const;
+    ClusterNetId net(const ClusterBlockId& block_id, const int& pin_index) const;
+  public:  /* Public mutators */
+    void rename_net(const ClusterBlockId& block_id, const int& pin_index,
+                    const ClusterNetId& net_id);
+  private: /* Internal data */
+    /* Pair a regular pb_type to its physical pb_type */
+    std::map<ClusterBlockId, std::map<int, ClusterNetId>> net_names_;
+};
+
+} /* End namespace openfpga*/
+
+#endif
diff --git a/openfpga/src/annotation/vpr_routing_annotation.cpp b/openfpga/src/annotation/vpr_routing_annotation.cpp
new file mode 100644
index 000000000..0eaa4b5c1
--- /dev/null
+++ b/openfpga/src/annotation/vpr_routing_annotation.cpp
@@ -0,0 +1,47 @@
+/************************************************************************
+ * Member functions for class VprRoutingAnnotation
+ ***********************************************************************/
+#include "vtr_log.h"
+#include "vtr_assert.h"
+#include "vpr_routing_annotation.h"
+
+/* namespace openfpga begins */
+namespace openfpga {
+
+/************************************************************************
+ * Constructors
+ ***********************************************************************/
+VprRoutingAnnotation::VprRoutingAnnotation() {
+  return;
+}
+
+/************************************************************************
+ * Public accessors
+ ***********************************************************************/
+ClusterNetId VprRoutingAnnotation::rr_node_net(const RRNodeId& rr_node) const {
+  /* Ensure that the node_id is in the list */
+  VTR_ASSERT(size_t(rr_node) < rr_node_nets_.size());
+  return rr_node_nets_[rr_node];
+}
+
+/************************************************************************
+ * Public mutators
+ ***********************************************************************/
+void VprRoutingAnnotation::init(const RRGraph& rr_graph) {
+  rr_node_nets_.resize(rr_graph.nodes().size(), ClusterNetId::INVALID());
+}
+
+void VprRoutingAnnotation::set_rr_node_net(const RRNodeId& rr_node,
+                                           const ClusterNetId& net_id) {
+  /* Ensure that the node_id is in the list */
+  VTR_ASSERT(size_t(rr_node) < rr_node_nets_.size());
+  /* Warn any override attempt */
+  if (ClusterNetId::INVALID() != rr_node_nets_[rr_node]) {
+    VTR_LOG_WARN("Override the net '%ld' for node'%ld' with in routing context annotation!\n",
+                 size_t(net_id), size_t(rr_node));
+  }
+
+  rr_node_nets_[rr_node] = net_id;
+}
+
+} /* End namespace openfpga*/
diff --git a/openfpga/src/annotation/vpr_routing_annotation.h b/openfpga/src/annotation/vpr_routing_annotation.h
new file mode 100644
index 000000000..5508ae3b0
--- /dev/null
+++ b/openfpga/src/annotation/vpr_routing_annotation.h
@@ -0,0 +1,40 @@
+#ifndef VPR_ROUTING_ANNOTATION_H
+#define VPR_ROUTING_ANNOTATION_H
+
+/********************************************************************
+ * Include header files required by the data structure definition
+ *******************************************************************/
+#include <map> 
+
+/* Header from vpr library */
+#include "vpr_context.h"
+
+/* Begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * This is the critical data structure to link the pb_type in VPR
+ * to openfpga annotations
+ * With a given pb_type pointer, it aims to identify:
+ * 1. if the pb_type is a physical pb_type or a operating pb_type
+ * 2. what is the circuit model id linked to a physical pb_type
+ * 3. what is the physical pb_type for an operating pb_type
+ * 4. what is the mode pointer that represents the physical mode for a pb_type
+ *******************************************************************/
+class VprRoutingAnnotation {
+  public:  /* Constructor */
+    VprRoutingAnnotation();
+  public:  /* Public accessors */
+    ClusterNetId rr_node_net(const RRNodeId& rr_node) const;
+  public:  /* Public mutators */
+    void init(const RRGraph& rr_graph);
+    void set_rr_node_net(const RRNodeId& rr_node,
+                         const ClusterNetId& net_id);
+  private: /* Internal data */
+    /* Pair a regular pb_type to its physical pb_type */
+    vtr::vector<RRNodeId, ClusterNetId> rr_node_nets_;
+};
+
+} /* End namespace openfpga*/
+
+#endif
diff --git a/openfpga/src/base/openfpga_context.h b/openfpga/src/base/openfpga_context.h
index cac5877d5..74e01d0de 100644
--- a/openfpga/src/base/openfpga_context.h
+++ b/openfpga/src/base/openfpga_context.h
@@ -5,6 +5,8 @@
 #include "openfpga_arch.h"
 #include "vpr_netlist_annotation.h"
 #include "vpr_pb_type_annotation.h"
+#include "vpr_clustering_annotation.h"
+#include "vpr_routing_annotation.h"
 
 /********************************************************************
  * This file includes the declaration of the date structure 
@@ -38,10 +40,14 @@ class OpenfpgaContext : public Context  {
     const openfpga::Arch& arch() const { return arch_; }
     const openfpga::VprPbTypeAnnotation& vpr_pb_type_annotation() const { return vpr_pb_type_annotation_; }
     const openfpga::VprNetlistAnnotation& vpr_netlist_annotation() const { return vpr_netlist_annotation_; }
+    const openfpga::VprClusteringAnnotation& vpr_clustering_annotation() const { return vpr_clustering_annotation_; }
+    const openfpga::VprRoutingAnnotation& vpr_routing_annotation() const { return vpr_routing_annotation_; }
   public:  /* Public mutators */
     openfpga::Arch& mutable_arch() { return arch_; }
     openfpga::VprPbTypeAnnotation& mutable_vpr_pb_type_annotation() { return vpr_pb_type_annotation_; }
     openfpga::VprNetlistAnnotation& mutable_vpr_netlist_annotation() { return vpr_netlist_annotation_; }
+    openfpga::VprClusteringAnnotation& mutable_vpr_clustering_annotation() { return vpr_clustering_annotation_; }
+    openfpga::VprRoutingAnnotation& mutable_vpr_routing_annotation() { return vpr_routing_annotation_; }
   private: /* Internal data */
     /* Data structure to store information from read_openfpga_arch library */
     openfpga::Arch arch_;
@@ -49,6 +55,9 @@ class OpenfpgaContext : public Context  {
     openfpga::VprPbTypeAnnotation vpr_pb_type_annotation_;
     /* Naming fix to netlist */
     openfpga::VprNetlistAnnotation vpr_netlist_annotation_;
+    /* TODO: Pin net fix to cluster results */
+    openfpga::VprClusteringAnnotation vpr_clustering_annotation_;
+    openfpga::VprRoutingAnnotation vpr_routing_annotation_;
 };
 
 #endif
diff --git a/openfpga/src/base/openfpga_link_arch.cpp b/openfpga/src/base/openfpga_link_arch.cpp
index 8f7b5b54d..186f95f22 100644
--- a/openfpga/src/base/openfpga_link_arch.cpp
+++ b/openfpga/src/base/openfpga_link_arch.cpp
@@ -11,6 +11,7 @@
 #include "pb_type_utils.h"
 #include "annotate_pb_types.h"
 #include "annotate_pb_graph.h"
+#include "annotate_routing.h"
 #include "openfpga_link_arch.h"
 
 /* Include global variables of VPR */
@@ -51,6 +52,13 @@ void link_arch(OpenfpgaContext& openfpga_context,
   annotate_pb_graph(g_vpr_ctx.device(),
                     openfpga_context.mutable_vpr_pb_type_annotation(),
                     cmd_context.option_enable(cmd, opt_verbose));
+
+  /* Annotate net mapping to each rr_node 
+   */
+  openfpga_context.mutable_vpr_routing_annotation().init(g_vpr_ctx.device().rr_graph);
+
+  annotate_rr_node_nets(g_vpr_ctx.clustering(), g_vpr_ctx.routing(), 
+                        openfpga_context.mutable_vpr_routing_annotation());
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_pb_pin_fixup.cpp b/openfpga/src/base/openfpga_pb_pin_fixup.cpp
new file mode 100644
index 000000000..4dc5e0b57
--- /dev/null
+++ b/openfpga/src/base/openfpga_pb_pin_fixup.cpp
@@ -0,0 +1,184 @@
+/********************************************************************
+ * This file includes functions to fix up the pb pin mapping results 
+ * after routing optimization
+ *******************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_time.h"
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+/* Headers from vpr library */
+#include "vpr_utils.h"
+
+#include "pb_type_utils.h"
+#include "openfpga_pb_pin_fixup.h"
+
+/* Include global variables of VPR */
+#include "globals.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Give a given pin index, find the side where this pin is located 
+ * on the physical tile
+ * Note:
+ *   - Need to check if the pin_width_offset and pin_height_offset
+ *     are properly set in VPR!!!
+ *******************************************************************/
+static 
+std::vector<e_side> find_logic_tile_pin_side(t_physical_tile_type_ptr physical_tile,
+                                             const int& physical_pin) {
+  std::vector<e_side> pin_sides;
+  for (const e_side& side_cand : {TOP, RIGHT, BOTTOM, LEFT}) {
+    int pin_width_offset = physical_tile->pin_width_offset[physical_pin];
+    int pin_height_offset = physical_tile->pin_height_offset[physical_pin];
+    if (true == physical_tile->pinloc[pin_width_offset][pin_height_offset][side_cand][physical_pin]) {
+      pin_sides.push_back(side_cand);
+    } 
+  }
+
+  return pin_sides;
+}
+
+/********************************************************************
+ * Fix up the pb pin mapping results for a given clustered block
+ * 1. For each input/output pin of a clustered pb, 
+ *    - find a corresponding node in RRGraph object
+ *    - find the net id for the node in routing context
+ *    - find the net id for the node in clustering context
+ *    - if the net id does not match, we update the clustering context
+ *******************************************************************/
+static 
+void update_cluster_pin_with_post_routing_results(const DeviceContext& device_ctx,
+                                                  const ClusteringContext& clustering_ctx,
+                                                  const VprRoutingAnnotation& vpr_routing_annotation,
+                                                  VprClusteringAnnotation& vpr_clustering_annotation,
+                                                  const vtr::Point<size_t>& grid_coord,
+                                                  const ClusterBlockId& blk_id,
+                                                  const bool& verbose) {
+  /* Handle each pin */
+  auto logical_block = clustering_ctx.clb_nlist.block_type(blk_id);
+  auto physical_tile = pick_best_physical_type(logical_block);
+
+  for (int j = 0; j < logical_block->pb_type->num_pins; j++) {
+    /* Get the ptc num for the pin in rr_graph */
+    int physical_pin = get_physical_pin(physical_tile, logical_block, j);
+    auto pin_class = physical_tile->pin_class[physical_pin];
+    auto class_inf = physical_tile->class_inf[pin_class];
+    t_rr_type rr_node_type;
+    if (class_inf.type == DRIVER) {
+      rr_node_type = OPIN;
+    } else {
+      VTR_ASSERT(class_inf.type == RECEIVER);
+      rr_node_type = IPIN;
+    }
+    std::vector<e_side> pin_sides = find_logic_tile_pin_side(physical_tile, physical_pin);
+    /* As some grid go across columns or rows, we may not have the pin on any side */
+    if (0 == pin_sides.size()) {
+      continue;
+    }
+
+    for (const e_side& pin_side : pin_sides) {
+      /* Find the net mapped to this pin in routing results */
+      const RRNodeId& rr_node = device_ctx.rr_graph.find_node(grid_coord.x(), grid_coord.y(), rr_node_type, physical_pin, pin_side); 
+      if (false == device_ctx.rr_graph.valid_node_id(rr_node)) {
+        continue;
+      }
+      /* Get the cluster net id which has been mapped to this net */
+      ClusterNetId routing_net_id = vpr_routing_annotation.rr_node_net(rr_node);
+
+      /* Find the net mapped to this pin in clustering results*/
+      ClusterNetId cluster_net_id = clustering_ctx.clb_nlist.block_net(blk_id, j);
+
+      /* If matched, we finish here */
+      if (routing_net_id == cluster_net_id) {
+         continue;
+      }
+      /* Add to net modification */
+      vpr_clustering_annotation.rename_net(blk_id, j, routing_net_id);
+ 
+      std::string routing_net_name("unmapped");
+      if (ClusterNetId::INVALID() != routing_net_id) {
+        routing_net_name = clustering_ctx.clb_nlist.net_name(routing_net_id);
+      }
+
+      std::string cluster_net_name("unmapped");
+      if (ClusterNetId::INVALID() != cluster_net_id) {
+        cluster_net_name = clustering_ctx.clb_nlist.net_name(cluster_net_id);
+      }
+
+      VTR_LOGV(verbose,
+               "Fixed up net '%s' mapping mismatch at clustered block '%s' pin '%s[%d]' (was net '%s')\n",
+               routing_net_name.c_str(),
+               clustering_ctx.clb_nlist.block_pb(blk_id)->name,
+               get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin)->port->name,
+               get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin)->pin_number,
+               cluster_net_name.c_str()
+               );
+    }
+  }
+}
+
+/********************************************************************
+ * Main function to fix up the pb pin mapping results 
+ * This function will walk through each grid
+ *******************************************************************/
+static 
+void update_pb_pin_with_post_routing_results(const DeviceContext& device_ctx,
+                                             const ClusteringContext& clustering_ctx,
+                                             const PlacementContext& placement_ctx,
+                                             const VprRoutingAnnotation& vpr_routing_annotation,
+                                             VprClusteringAnnotation& vpr_clustering_annotation,
+                                             const bool& verbose) {
+  for (size_t x = 0; x < device_ctx.grid.width(); ++x) {
+    for (size_t y = 0; y < device_ctx.grid.height(); ++y) {
+      /* Bypass the EMPTY tiles */
+      if (device_ctx.EMPTY_PHYSICAL_TILE_TYPE == device_ctx.grid[x][y].type) {
+        continue;
+      }
+      /* Get the mapped blocks to this grid */
+      for (const ClusterBlockId& cluster_blk_id : placement_ctx.grid_blocks[x][y].blocks) {
+        /* Skip invalid ids */ 
+        if (ClusterBlockId::INVALID() == cluster_blk_id) {
+          continue;
+        }
+        /* We know the entrance to grid info and mapping results, do the fix-up for this block */
+        vtr::Point<size_t> grid_coord(x, y);
+        update_cluster_pin_with_post_routing_results(device_ctx, clustering_ctx, 
+                                                     vpr_routing_annotation, vpr_clustering_annotation,
+                                                     grid_coord, cluster_blk_id,
+                                                     verbose);
+      } 
+    }
+  }
+}
+
+/********************************************************************
+ * Top-level function to fix up the pb pin mapping results 
+ * The problem comes from a mismatch between the packing and routing results
+ * When there are equivalent input/output for any grids, router will try
+ * to swap the net mapping among these pins so as to achieve best 
+ * routing optimization.
+ * However, it will cause the packing results out-of-date as the net mapping 
+ * of each grid remain untouched once packing is done.
+ * This function aims to fix the mess after routing so that the net mapping
+ * can be synchronized
+ *******************************************************************/
+void pb_pin_fixup(OpenfpgaContext& openfpga_context,
+                  const Command& cmd, const CommandContext& cmd_context) { 
+
+  vtr::ScopedStartFinishTimer timer("Fix up pb pin mapping results after routing optimization");
+
+  CommandOptionId opt_verbose = cmd.option("verbose");
+
+  /* Apply fix-up to each grid */
+  update_pb_pin_with_post_routing_results(g_vpr_ctx.device(),
+                                          g_vpr_ctx.clustering(),
+                                          g_vpr_ctx.placement(), 
+                                          openfpga_context.vpr_routing_annotation(),
+                                          openfpga_context.mutable_vpr_clustering_annotation(),
+                                          cmd_context.option_enable(cmd, opt_verbose));
+} 
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_pb_pin_fixup.h b/openfpga/src/base/openfpga_pb_pin_fixup.h
new file mode 100644
index 000000000..e924c6067
--- /dev/null
+++ b/openfpga/src/base/openfpga_pb_pin_fixup.h
@@ -0,0 +1,23 @@
+#ifndef OPENFPGA_PB_PIN_FIXUP_H
+#define OPENFPGA_PB_PIN_FIXUP_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "command.h"
+#include "command_context.h"
+#include "openfpga_context.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void pb_pin_fixup(OpenfpgaContext& openfpga_context, 
+                  const Command& cmd, const CommandContext& cmd_context); 
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/base/openfpga_setup_command.cpp b/openfpga/src/base/openfpga_setup_command.cpp
index ef392a4c4..2a1edacbc 100644
--- a/openfpga/src/base/openfpga_setup_command.cpp
+++ b/openfpga/src/base/openfpga_setup_command.cpp
@@ -5,6 +5,7 @@
  *******************************************************************/
 #include "openfpga_read_arch.h"
 #include "openfpga_link_arch.h"
+#include "openfpga_pb_pin_fixup.h"
 #include "check_netlist_naming_conflict.h"
 #include "openfpga_setup_command.h"
 
@@ -79,9 +80,26 @@ void add_openfpga_setup_commands(openfpga::Shell<OpenfpgaContext>& shell) {
   ShellCommandId shell_cmd_check_netlist_naming_conflict_id = shell.add_command(shell_cmd_check_netlist_naming_conflict, "Check any block/net naming in users' BLIF netlist violates the syntax of fabric generator");
   shell.set_command_class(shell_cmd_check_netlist_naming_conflict_id, openfpga_setup_cmd_class);
   shell.set_command_execute_function(shell_cmd_check_netlist_naming_conflict_id, check_netlist_naming_conflict);
-  /* The 'link_openfpga_arch' command should NOT be executed before 'read_openfpga_arch' and 'vpr' */
+  /* The 'link_openfpga_arch' command should NOT be executed before 'vpr' */
   std::vector<ShellCommandId> cmd_dependency_check_netlist_naming_conflict(1, shell_cmd_vpr_id);
   shell.set_command_dependency(shell_cmd_link_openfpga_arch_id, cmd_dependency_check_netlist_naming_conflict);
+
+  /******************************** 
+   * Command 'pb_pin_fixup' 
+   */
+  Command shell_cmd_pb_pin_fixup("pb_pin_fixup");
+  /* Add an option '--verbose' */
+  shell_cmd_pb_pin_fixup.add_option("verbose", false, "Show verbose outputs");
+
+  /* Add command 'pb_pin_fixup' to the Shell */
+  ShellCommandId shell_cmd_pb_pin_fixup_id = shell.add_command(shell_cmd_pb_pin_fixup, "Fix up the packing results due to pin swapping during routing stage");
+  shell.set_command_class(shell_cmd_pb_pin_fixup_id, openfpga_setup_cmd_class);
+  shell.set_command_execute_function(shell_cmd_pb_pin_fixup_id, pb_pin_fixup);
+  /* The 'pb_pin_fixup' command should NOT be executed before 'read_openfpga_arch' and 'vpr' */
+  std::vector<ShellCommandId> cmd_dependency_pb_pin_fixup;
+  cmd_dependency_pb_pin_fixup.push_back(shell_cmd_read_arch_id);
+  cmd_dependency_pb_pin_fixup.push_back(shell_cmd_vpr_id);
+  shell.set_command_dependency(shell_cmd_pb_pin_fixup_id, cmd_dependency_pb_pin_fixup);
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/test_script/s298_k6_frac.openfpga b/openfpga/test_script/s298_k6_frac.openfpga
index fa3dcf993..9681918c4 100644
--- a/openfpga/test_script/s298_k6_frac.openfpga
+++ b/openfpga/test_script/s298_k6_frac.openfpga
@@ -10,5 +10,8 @@ link_openfpga_arch
 # Check and correct any naming conflicts in the BLIF netlist
 check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
 
+# Apply fix-up to clustering nets based on routing results
+pb_pin_fixup --verbose
+
 # Finish and exit OpenFPGA
 exit

From cccbb9fd4942cd54506dc244db6566b44c66bf5b Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 5 Feb 2020 22:12:44 -0700
Subject: [PATCH 105/645] add missing files

---
 openfpga/src/annotation/annotate_routing.cpp | 47 ++++++++++++++++++++
 openfpga/src/annotation/annotate_routing.h   | 24 ++++++++++
 2 files changed, 71 insertions(+)
 create mode 100644 openfpga/src/annotation/annotate_routing.cpp
 create mode 100644 openfpga/src/annotation/annotate_routing.h

diff --git a/openfpga/src/annotation/annotate_routing.cpp b/openfpga/src/annotation/annotate_routing.cpp
new file mode 100644
index 000000000..2f16a2bff
--- /dev/null
+++ b/openfpga/src/annotation/annotate_routing.cpp
@@ -0,0 +1,47 @@
+/********************************************************************
+ * This file includes functions that are used to annotate routing results
+ * from VPR to OpenFPGA
+ *******************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+#include "annotate_routing.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Create a mapping between each rr_node and its mapped nets 
+ * based on VPR routing results
+ * - Unmapped rr_node will use invalid ids 
+ *******************************************************************/
+void annotate_rr_node_nets(const ClusteringContext& vpr_clustering_ctx,
+                           const RoutingContext& vpr_routing_ctx,
+                           VprRoutingAnnotation& vpr_routing_annotation) {
+  size_t counter = 0;
+  VTR_LOG("Annotating rr_node with routed nets...");
+   
+  for (auto net_id : vpr_clustering_ctx.clb_nlist.nets()) {
+    /* Ignore nets that are not routed */
+    if (true == vpr_clustering_ctx.clb_nlist.net_is_ignored(net_id)) {
+      continue;
+    }
+    /* Ignore used in local cluster only, reserved one CLB pin */
+    if (false == vpr_clustering_ctx.clb_nlist.net_sinks(net_id).size()) {
+      continue;
+    }
+    t_trace* tptr = vpr_routing_ctx.trace[net_id].head;
+    while (tptr != nullptr) {
+      RRNodeId rr_node = tptr->index;
+      vpr_routing_annotation.set_rr_node_net(rr_node, net_id);
+      counter++;
+      tptr = tptr->next;
+    }
+  }
+
+  VTR_LOG("Done with %d nodes mapping\n", counter);
+}
+
+} /* end namespace openfpga */
+
diff --git a/openfpga/src/annotation/annotate_routing.h b/openfpga/src/annotation/annotate_routing.h
new file mode 100644
index 000000000..e0c571278
--- /dev/null
+++ b/openfpga/src/annotation/annotate_routing.h
@@ -0,0 +1,24 @@
+#ifndef ANNOTATE_ROUTING_H
+#define ANNOTATE_ROUTING_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "vpr_context.h"
+#include "openfpga_context.h"
+#include "vpr_routing_annotation.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void annotate_rr_node_nets(const ClusteringContext& vpr_clustering_ctx,
+                           const RoutingContext& vpr_routing_ctx,
+                           VprRoutingAnnotation& vpr_routing_annotation);
+
+} /* end namespace openfpga */
+
+#endif

From 99f5a86b49e979a66e7d31d4455cbe4c2c776e29 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 6 Feb 2020 12:54:55 -0700
Subject: [PATCH 106/645] bug fixed for routing annotation and routing net
 fix-up

---
 libopenfpga/libopenfpgautil/CMakeLists.txt    |   1 +
 .../src/openfpga_side_manager.cpp             | 175 ++++++++++++++++++
 .../src/openfpga_side_manager.h               |  49 +++++
 openfpga/src/annotation/annotate_routing.cpp  |  25 ++-
 openfpga/src/annotation/annotate_routing.h    |   8 +-
 .../src/annotation/vpr_routing_annotation.cpp |   2 +-
 openfpga/src/base/openfpga_link_arch.cpp      |   5 +-
 openfpga/src/base/openfpga_pb_pin_fixup.cpp   | 165 ++++++++++++-----
 8 files changed, 373 insertions(+), 57 deletions(-)
 create mode 100644 libopenfpga/libopenfpgautil/src/openfpga_side_manager.cpp
 create mode 100644 libopenfpga/libopenfpgautil/src/openfpga_side_manager.h

diff --git a/libopenfpga/libopenfpgautil/CMakeLists.txt b/libopenfpga/libopenfpgautil/CMakeLists.txt
index 66c3dc471..9cb09e7b4 100644
--- a/libopenfpga/libopenfpgautil/CMakeLists.txt
+++ b/libopenfpga/libopenfpgautil/CMakeLists.txt
@@ -19,6 +19,7 @@ set_target_properties(libopenfpgautil PROPERTIES PREFIX "") #Avoid extra 'lib' p
 
 #Specify link-time dependancies
 target_link_libraries(libopenfpgautil
+                      libarchfpga
                       libvtrutil)
 
 #Create the test executable
diff --git a/libopenfpga/libopenfpgautil/src/openfpga_side_manager.cpp b/libopenfpga/libopenfpgautil/src/openfpga_side_manager.cpp
new file mode 100644
index 000000000..00ff9912c
--- /dev/null
+++ b/libopenfpga/libopenfpgautil/src/openfpga_side_manager.cpp
@@ -0,0 +1,175 @@
+/********************************************************************
+ * Memeber function for class SideManagerManager
+ *******************************************************************/
+#include "openfpga_side_manager.h"
+
+/* namespace openfpga begins */
+namespace openfpga {
+
+/* Constructors */
+SideManager::SideManager(enum e_side side) {
+  side_  = side;
+}
+
+SideManager::SideManager() {
+  side_ = NUM_SIDES;
+}
+
+SideManager::SideManager(size_t side) { 
+  set_side(side); 
+}
+
+/* Public Accessors */
+enum e_side SideManager::get_side() const { 
+  return side_; 
+} 
+
+enum e_side SideManager::get_opposite() const {
+  switch (side_) {
+  case TOP:
+    return BOTTOM; 
+  case RIGHT:
+    return LEFT;
+  case BOTTOM:
+    return TOP;
+  case LEFT:
+    return RIGHT;
+  default:
+    return NUM_SIDES;
+  }
+}
+
+enum e_side SideManager::get_rotate_clockwise() const {
+  switch (side_) {
+  case TOP:
+    return RIGHT; 
+  case RIGHT:
+    return BOTTOM;
+  case BOTTOM:
+    return LEFT;
+  case LEFT:
+    return TOP;
+  default:
+    return NUM_SIDES;
+  }
+}  
+
+enum e_side SideManager::get_rotate_counterclockwise() const {
+  switch (side_) {
+  case TOP:
+    return LEFT;
+  case RIGHT:
+    return TOP;
+  case BOTTOM:
+    return RIGHT; 
+  case LEFT:
+    return BOTTOM;
+  default:
+    return NUM_SIDES;
+  }
+} 
+
+bool SideManager::validate() const {
+  if (NUM_SIDES == side_) {
+    return false;
+  }
+  return true;
+}
+
+size_t SideManager::to_size_t() const {
+  switch (side_) {
+  case TOP:
+    return 0; 
+  case RIGHT:
+    return 1;
+  case BOTTOM:
+    return 2;
+  case LEFT:
+    return 3;
+  default:
+    return 4;
+  }
+}
+
+/* Convert to char* */
+const char* SideManager::c_str() const { 
+  switch (side_) {
+  case TOP:
+    return "top"; 
+  case RIGHT:
+    return "right";
+  case BOTTOM:
+    return "bottom";
+  case LEFT:
+    return "left";
+  default:
+    return "invalid_side";
+  }
+} 
+
+/* Convert to char* */
+std::string SideManager::to_string() const { 
+  std::string ret;
+  switch (side_) {
+  case TOP:
+    ret.assign("top"); 
+    break;
+  case RIGHT:
+    ret.assign("right");
+    break;
+  case BOTTOM:
+    ret.assign("bottom");
+    break;
+  case LEFT:
+    ret.assign("left");
+    break;
+  default:
+    ret.assign("invalid_side");
+    break;
+  }
+
+  return ret;
+} 
+
+/* Public Mutators */
+void SideManager::set_side(size_t side) { 
+  switch (side) {
+  case 0:
+    side_ = TOP;
+    return; 
+  case 1:
+    side_ = RIGHT;
+    return; 
+  case 2:
+    side_ = BOTTOM;
+    return; 
+  case 3:
+    side_ = LEFT;
+    return; 
+  default:
+    side_ = NUM_SIDES;
+    return; 
+  }
+}
+
+void SideManager::set_side(enum e_side side) { 
+  side_ = side; 
+  return;
+}
+
+void SideManager::set_opposite() { 
+  side_ = get_opposite(); 
+  return;
+}
+    
+void SideManager::rotate_clockwise() {
+  side_ = get_rotate_clockwise(); 
+  return;
+}  
+
+void SideManager::rotate_counterclockwise() {
+  side_ = get_rotate_counterclockwise(); 
+  return;
+}  
+
+} /* namespace openfpga ends */
diff --git a/libopenfpga/libopenfpgautil/src/openfpga_side_manager.h b/libopenfpga/libopenfpgautil/src/openfpga_side_manager.h
new file mode 100644
index 000000000..4903f7b4b
--- /dev/null
+++ b/libopenfpga/libopenfpgautil/src/openfpga_side_manager.h
@@ -0,0 +1,49 @@
+#ifndef OPENFPGA_SIDE_MANAGER_H
+#define OPENFPGA_SIDE_MANAGER_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <cstddef>
+#include <string>
+
+/* Header files form archfpga library */
+#include "physical_types.h"
+
+/* namespace openfpga begins */
+namespace openfpga {
+
+/********************************************************************
+ * Define a class for the sides of a physical block in FPGA architecture
+ * Basically, each block has four sides :
+ * TOP, RIGHT, BOTTOM, LEFT  
+ * This class aims to provide a easy proctol for manipulating a side 
+ ********************************************************************/
+
+class SideManager {
+  public: /* Constructor */
+    SideManager(enum e_side side);
+    SideManager();
+    SideManager(size_t side);
+  public: /* Accessors */
+    enum e_side get_side() const;
+    enum e_side get_opposite() const;
+    enum e_side get_rotate_clockwise() const;
+    enum e_side get_rotate_counterclockwise() const;
+    bool validate() const;
+    size_t to_size_t() const;
+    const char* c_str() const;
+    std::string to_string() const;
+  public: /* Mutators */
+    void set_side(size_t side);
+    void set_side(enum e_side side);
+    void set_opposite();
+    void rotate_clockwise();
+    void rotate_counterclockwise();
+  private: /* internal data */
+    enum e_side side_;  
+};
+
+} /* namespace openfpga ends */
+
+#endif
diff --git a/openfpga/src/annotation/annotate_routing.cpp b/openfpga/src/annotation/annotate_routing.cpp
index 2f16a2bff..5e9dc4144 100644
--- a/openfpga/src/annotation/annotate_routing.cpp
+++ b/openfpga/src/annotation/annotate_routing.cpp
@@ -16,26 +16,33 @@ namespace openfpga {
  * based on VPR routing results
  * - Unmapped rr_node will use invalid ids 
  *******************************************************************/
-void annotate_rr_node_nets(const ClusteringContext& vpr_clustering_ctx,
-                           const RoutingContext& vpr_routing_ctx,
-                           VprRoutingAnnotation& vpr_routing_annotation) {
+void annotate_rr_node_nets(const DeviceContext& device_ctx,
+                           const ClusteringContext& clustering_ctx,
+                           const RoutingContext& routing_ctx,
+                           VprRoutingAnnotation& vpr_routing_annotation,
+                           const bool& verbose) {
   size_t counter = 0;
   VTR_LOG("Annotating rr_node with routed nets...");
+  VTR_LOGV(verbose, "\n");
    
-  for (auto net_id : vpr_clustering_ctx.clb_nlist.nets()) {
+  for (auto net_id : clustering_ctx.clb_nlist.nets()) {
     /* Ignore nets that are not routed */
-    if (true == vpr_clustering_ctx.clb_nlist.net_is_ignored(net_id)) {
+    if (true == clustering_ctx.clb_nlist.net_is_ignored(net_id)) {
       continue;
     }
     /* Ignore used in local cluster only, reserved one CLB pin */
-    if (false == vpr_clustering_ctx.clb_nlist.net_sinks(net_id).size()) {
+    if (false == clustering_ctx.clb_nlist.net_sinks(net_id).size()) {
       continue;
     }
-    t_trace* tptr = vpr_routing_ctx.trace[net_id].head;
+    t_trace* tptr = routing_ctx.trace[net_id].head;
     while (tptr != nullptr) {
       RRNodeId rr_node = tptr->index;
-      vpr_routing_annotation.set_rr_node_net(rr_node, net_id);
-      counter++;
+      /* Ignore source and sink nodes, they are the common node multiple starting and ending points */
+      if ( (SOURCE != device_ctx.rr_graph.node_type(rr_node)) 
+        && (SINK != device_ctx.rr_graph.node_type(rr_node)) ) {
+        vpr_routing_annotation.set_rr_node_net(rr_node, net_id);
+        counter++;
+      }
       tptr = tptr->next;
     }
   }
diff --git a/openfpga/src/annotation/annotate_routing.h b/openfpga/src/annotation/annotate_routing.h
index e0c571278..9496c6e81 100644
--- a/openfpga/src/annotation/annotate_routing.h
+++ b/openfpga/src/annotation/annotate_routing.h
@@ -15,9 +15,11 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-void annotate_rr_node_nets(const ClusteringContext& vpr_clustering_ctx,
-                           const RoutingContext& vpr_routing_ctx,
-                           VprRoutingAnnotation& vpr_routing_annotation);
+void annotate_rr_node_nets(const DeviceContext& device_ctx,
+                           const ClusteringContext& clustering_ctx,
+                           const RoutingContext& routing_ctx,
+                           VprRoutingAnnotation& vpr_routing_annotation,
+                           const bool& verbose);
 
 } /* end namespace openfpga */
 
diff --git a/openfpga/src/annotation/vpr_routing_annotation.cpp b/openfpga/src/annotation/vpr_routing_annotation.cpp
index 0eaa4b5c1..1c17450ed 100644
--- a/openfpga/src/annotation/vpr_routing_annotation.cpp
+++ b/openfpga/src/annotation/vpr_routing_annotation.cpp
@@ -37,7 +37,7 @@ void VprRoutingAnnotation::set_rr_node_net(const RRNodeId& rr_node,
   VTR_ASSERT(size_t(rr_node) < rr_node_nets_.size());
   /* Warn any override attempt */
   if (ClusterNetId::INVALID() != rr_node_nets_[rr_node]) {
-    VTR_LOG_WARN("Override the net '%ld' for node'%ld' with in routing context annotation!\n",
+    VTR_LOG_WARN("Override the net '%ld' for node '%ld' with in routing context annotation!\n",
                  size_t(net_id), size_t(rr_node));
   }
 
diff --git a/openfpga/src/base/openfpga_link_arch.cpp b/openfpga/src/base/openfpga_link_arch.cpp
index 186f95f22..dee7662a6 100644
--- a/openfpga/src/base/openfpga_link_arch.cpp
+++ b/openfpga/src/base/openfpga_link_arch.cpp
@@ -57,8 +57,9 @@ void link_arch(OpenfpgaContext& openfpga_context,
    */
   openfpga_context.mutable_vpr_routing_annotation().init(g_vpr_ctx.device().rr_graph);
 
-  annotate_rr_node_nets(g_vpr_ctx.clustering(), g_vpr_ctx.routing(), 
-                        openfpga_context.mutable_vpr_routing_annotation());
+  annotate_rr_node_nets(g_vpr_ctx.device(), g_vpr_ctx.clustering(), g_vpr_ctx.routing(), 
+                        openfpga_context.mutable_vpr_routing_annotation(),
+                        cmd_context.option_enable(cmd, opt_verbose));
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_pb_pin_fixup.cpp b/openfpga/src/base/openfpga_pb_pin_fixup.cpp
index 4dc5e0b57..1c0beee27 100644
--- a/openfpga/src/base/openfpga_pb_pin_fixup.cpp
+++ b/openfpga/src/base/openfpga_pb_pin_fixup.cpp
@@ -10,6 +10,9 @@
 /* Headers from vpr library */
 #include "vpr_utils.h"
 
+/* Headers from openfpgautil library */
+#include "openfpga_side_manager.h"
+
 #include "pb_type_utils.h"
 #include "openfpga_pb_pin_fixup.h"
 
@@ -56,6 +59,7 @@ void update_cluster_pin_with_post_routing_results(const DeviceContext& device_ct
                                                   VprClusteringAnnotation& vpr_clustering_annotation,
                                                   const vtr::Point<size_t>& grid_coord,
                                                   const ClusterBlockId& blk_id,
+                                                  const e_side& border_side,
                                                   const bool& verbose) {
   /* Handle each pin */
   auto logical_block = clustering_ctx.clb_nlist.block_type(blk_id);
@@ -66,6 +70,7 @@ void update_cluster_pin_with_post_routing_results(const DeviceContext& device_ct
     int physical_pin = get_physical_pin(physical_tile, logical_block, j);
     auto pin_class = physical_tile->pin_class[physical_pin];
     auto class_inf = physical_tile->class_inf[pin_class];
+
     t_rr_type rr_node_type;
     if (class_inf.type == DRIVER) {
       rr_node_type = OPIN;
@@ -74,49 +79,74 @@ void update_cluster_pin_with_post_routing_results(const DeviceContext& device_ct
       rr_node_type = IPIN;
     }
     std::vector<e_side> pin_sides = find_logic_tile_pin_side(physical_tile, physical_pin);
-    /* As some grid go across columns or rows, we may not have the pin on any side */
+    /* As some grid has height/width offset, we may not have the pin on any side */
     if (0 == pin_sides.size()) {
       continue;
     }
 
-    for (const e_side& pin_side : pin_sides) {
-      /* Find the net mapped to this pin in routing results */
-      const RRNodeId& rr_node = device_ctx.rr_graph.find_node(grid_coord.x(), grid_coord.y(), rr_node_type, physical_pin, pin_side); 
-      if (false == device_ctx.rr_graph.valid_node_id(rr_node)) {
-        continue;
-      }
-      /* Get the cluster net id which has been mapped to this net */
-      ClusterNetId routing_net_id = vpr_routing_annotation.rr_node_net(rr_node);
-
-      /* Find the net mapped to this pin in clustering results*/
-      ClusterNetId cluster_net_id = clustering_ctx.clb_nlist.block_net(blk_id, j);
-
-      /* If matched, we finish here */
-      if (routing_net_id == cluster_net_id) {
-         continue;
-      }
-      /* Add to net modification */
-      vpr_clustering_annotation.rename_net(blk_id, j, routing_net_id);
- 
-      std::string routing_net_name("unmapped");
-      if (ClusterNetId::INVALID() != routing_net_id) {
-        routing_net_name = clustering_ctx.clb_nlist.net_name(routing_net_id);
-      }
-
-      std::string cluster_net_name("unmapped");
-      if (ClusterNetId::INVALID() != cluster_net_id) {
-        cluster_net_name = clustering_ctx.clb_nlist.net_name(cluster_net_id);
-      }
-
-      VTR_LOGV(verbose,
-               "Fixed up net '%s' mapping mismatch at clustered block '%s' pin '%s[%d]' (was net '%s')\n",
-               routing_net_name.c_str(),
-               clustering_ctx.clb_nlist.block_pb(blk_id)->name,
-               get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin)->port->name,
-               get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin)->pin_number,
-               cluster_net_name.c_str()
-               );
+    /* For regular grid, we should have pin only one side!
+     * I/O grids: VPR creates the grid with duplicated pins on every side 
+     * but the expected side (only used side) will be opposite side of the border side!
+     */
+    e_side pin_side = NUM_SIDES;
+    if (NUM_SIDES == border_side) {
+      VTR_ASSERT(1 == pin_sides.size());
+      pin_side = pin_sides[0];
+    } else {
+      SideManager side_manager(border_side);
+      VTR_ASSERT(pin_sides.end() != std::find(pin_sides.begin(), pin_sides.end(), side_manager.get_opposite()));
+      pin_side = side_manager.get_opposite();
     }
+
+    /* Find the net mapped to this pin in routing results */
+    const RRNodeId& rr_node = device_ctx.rr_graph.find_node(grid_coord.x(), grid_coord.y(), rr_node_type, physical_pin, pin_side); 
+    if (false == device_ctx.rr_graph.valid_node_id(rr_node)) {
+      continue;
+    }
+    /* Get the cluster net id which has been mapped to this net */
+    ClusterNetId routing_net_id = vpr_routing_annotation.rr_node_net(rr_node);
+
+    /* Find the net mapped to this pin in clustering results*/
+    ClusterNetId cluster_net_id = clustering_ctx.clb_nlist.block_net(blk_id, j);
+
+    /* Ignore those net have never been routed */
+    if ( (ClusterNetId::INVALID() != cluster_net_id)
+      && (true == clustering_ctx.clb_nlist.net_is_ignored(cluster_net_id))) {
+      continue;
+    }
+
+    /* Ignore used in local cluster only, reserved one CLB pin */
+    if (false == clustering_ctx.clb_nlist.net_sinks(cluster_net_id).size()) {
+      continue;
+    }
+
+    /* If matched, we finish here */
+    if (routing_net_id == cluster_net_id) {
+       continue;
+    }
+    /* Add to net modification */
+    vpr_clustering_annotation.rename_net(blk_id, j, routing_net_id);
+ 
+    std::string routing_net_name("unmapped");
+    if (ClusterNetId::INVALID() != routing_net_id) {
+      routing_net_name = clustering_ctx.clb_nlist.net_name(routing_net_id);
+    }
+
+    std::string cluster_net_name("unmapped");
+    if (ClusterNetId::INVALID() != cluster_net_id) {
+      cluster_net_name = clustering_ctx.clb_nlist.net_name(cluster_net_id);
+    }
+
+    VTR_LOGV(verbose,
+             "Fixed up net '%s' mapping mismatch at clustered block '%s' pin 'grid[%ld][%ld].%s.%s[%d]' (was net '%s')\n",
+             routing_net_name.c_str(),
+             clustering_ctx.clb_nlist.block_pb(blk_id)->name,
+             grid_coord.x(), grid_coord.y(),
+             clustering_ctx.clb_nlist.block_pb(blk_id)->pb_graph_node->pb_type->name,
+             get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin)->port->name,
+             get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin)->pin_number,
+             cluster_net_name.c_str()
+             );
   }
 }
 
@@ -131,12 +161,15 @@ void update_pb_pin_with_post_routing_results(const DeviceContext& device_ctx,
                                              const VprRoutingAnnotation& vpr_routing_annotation,
                                              VprClusteringAnnotation& vpr_clustering_annotation,
                                              const bool& verbose) {
-  for (size_t x = 0; x < device_ctx.grid.width(); ++x) {
-    for (size_t y = 0; y < device_ctx.grid.height(); ++y) {
+  /* Update the core logic (center blocks of the FPGA) */
+  for (size_t x = 1; x < device_ctx.grid.width() - 1; ++x) {
+    for (size_t y = 1; y < device_ctx.grid.height() - 1; ++y) {
       /* Bypass the EMPTY tiles */
-      if (device_ctx.EMPTY_PHYSICAL_TILE_TYPE == device_ctx.grid[x][y].type) {
+      if (true == is_empty_type(device_ctx.grid[x][y].type)) {
         continue;
       }
+      /* We must have an regular (non-I/O) type here */
+      VTR_ASSERT(false == is_io_type(device_ctx.grid[x][y].type));
       /* Get the mapped blocks to this grid */
       for (const ClusterBlockId& cluster_blk_id : placement_ctx.grid_blocks[x][y].blocks) {
         /* Skip invalid ids */ 
@@ -147,11 +180,59 @@ void update_pb_pin_with_post_routing_results(const DeviceContext& device_ctx,
         vtr::Point<size_t> grid_coord(x, y);
         update_cluster_pin_with_post_routing_results(device_ctx, clustering_ctx, 
                                                      vpr_routing_annotation, vpr_clustering_annotation,
-                                                     grid_coord, cluster_blk_id,
+                                                     grid_coord, cluster_blk_id, NUM_SIDES,
                                                      verbose);
       } 
     }
   }
+
+  /* Update the periperal I/O blocks at fours sides of FPGA */
+  std::vector<e_side> io_sides{TOP, RIGHT, BOTTOM, LEFT};
+  std::map<e_side, std::vector<vtr::Point<size_t>>> io_coords;
+
+  /* TOP side */
+  for (size_t x = 1; x < device_ctx.grid.width() - 1; ++x) {
+    io_coords[TOP].push_back(vtr::Point<size_t>(x, device_ctx.grid.height() -1));
+  } 
+
+  /* RIGHT side */
+  for (size_t y = 1; y < device_ctx.grid.height() - 1; ++y) {
+    io_coords[RIGHT].push_back(vtr::Point<size_t>(device_ctx.grid.width() -1, y));
+  } 
+
+  /* BOTTOM side */
+  for (size_t x = 1; x < device_ctx.grid.width() - 1; ++x) {
+    io_coords[BOTTOM].push_back(vtr::Point<size_t>(x, 0));
+  } 
+
+  /* LEFT side */
+  for (size_t y = 1; y < device_ctx.grid.height() - 1; ++y) {
+    io_coords[LEFT].push_back(vtr::Point<size_t>(0, y));
+  } 
+
+  /* Walk through io grid on by one */
+  for (const e_side& io_side : io_sides) {
+    for (const vtr::Point<size_t>& io_coord : io_coords[io_side]) {
+      /* Bypass EMPTY grid */
+      if (true == is_empty_type(device_ctx.grid[io_coord.x()][io_coord.y()].type)) {
+        continue;
+      }
+      /* We must have an I/O type here */
+      VTR_ASSERT(true == is_io_type(device_ctx.grid[io_coord.x()][io_coord.y()].type));
+      /* Get the mapped blocks to this grid */
+      for (const ClusterBlockId& cluster_blk_id : placement_ctx.grid_blocks[io_coord.x()][io_coord.y()].blocks) {
+        /* Skip invalid ids */ 
+        if (ClusterBlockId::INVALID() == cluster_blk_id) {
+          continue;
+        }
+        /* Update on I/O grid */
+        update_cluster_pin_with_post_routing_results(device_ctx, clustering_ctx, 
+                                                     vpr_routing_annotation, vpr_clustering_annotation,
+                                                     io_coord, cluster_blk_id, io_side,
+                                                     verbose);
+      }
+    }
+  }
 }
 
 /********************************************************************

From ed9e0388450b766a9893f5bab55b4635ec47edd9 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 6 Feb 2020 17:14:29 -0700
Subject: [PATCH 107/645] add functionality of LUT truth table fix-up

---
 .../annotation/vpr_clustering_annotation.cpp  |  21 ++
 .../annotation/vpr_clustering_annotation.h    |   8 +
 .../base/openfpga_lut_truth_table_fixup.cpp   | 185 ++++++++++++++++++
 .../src/base/openfpga_lut_truth_table_fixup.h |  23 +++
 openfpga/src/base/openfpga_setup_command.cpp  |  18 ++
 openfpga/src/utils/lut_utils.cpp              |  93 +++++++++
 openfpga/src/utils/lut_utils.h                |  25 +++
 openfpga/test_script/s298_k6_frac.openfpga    |   3 +
 8 files changed, 376 insertions(+)
 create mode 100644 openfpga/src/base/openfpga_lut_truth_table_fixup.cpp
 create mode 100644 openfpga/src/base/openfpga_lut_truth_table_fixup.h
 create mode 100644 openfpga/src/utils/lut_utils.cpp
 create mode 100644 openfpga/src/utils/lut_utils.h

diff --git a/openfpga/src/annotation/vpr_clustering_annotation.cpp b/openfpga/src/annotation/vpr_clustering_annotation.cpp
index 747978023..cd32fdeac 100644
--- a/openfpga/src/annotation/vpr_clustering_annotation.cpp
+++ b/openfpga/src/annotation/vpr_clustering_annotation.cpp
@@ -31,6 +31,16 @@ ClusterNetId VprClusteringAnnotation::net(const ClusterBlockId& block_id, const
   return net_names_.at(block_id).at(pin_index);
 }
 
+bool VprClusteringAnnotation::is_truth_table_adapted(t_pb* pb) const {
+  /* Ensure that the block_id is in the list */
+  return (block_truth_tables_.end() != block_truth_tables_.find(pb));
+}
+
+AtomNetlist::TruthTable VprClusteringAnnotation::truth_table(t_pb* pb) const {
+  VTR_ASSERT(true == is_truth_table_adapted(pb));
+  return block_truth_tables_.at(pb);
+}
+
 /************************************************************************
  * Public mutators
  ***********************************************************************/
@@ -46,4 +56,15 @@ void VprClusteringAnnotation::rename_net(const ClusterBlockId& block_id, const i
   net_names_[block_id][pin_index] = net_id;
 }
 
+void VprClusteringAnnotation::adapt_truth_table(t_pb* pb,
+                                                const AtomNetlist::TruthTable& tt) {
+  /* Warn any override attempt */
+  if (block_truth_tables_.end() != block_truth_tables_.find(pb)) {
+    VTR_LOG_WARN("Override the truth table for pb '%s' in clustering context annotation!\n",
+                 pb->name);
+  }
+
+  block_truth_tables_[pb] = tt;
+}
+
 } /* End namespace openfpga*/
diff --git a/openfpga/src/annotation/vpr_clustering_annotation.h b/openfpga/src/annotation/vpr_clustering_annotation.h
index 5918a10b8..2951ef226 100644
--- a/openfpga/src/annotation/vpr_clustering_annotation.h
+++ b/openfpga/src/annotation/vpr_clustering_annotation.h
@@ -25,14 +25,22 @@ class VprClusteringAnnotation {
   public:  /* Constructor */
     VprClusteringAnnotation();
   public:  /* Public accessors */
+    /* Xifan Tang: I created two functions for each data query in purpose!
+     * As this is an annotation, some net/block may be changed to invalid id
+     * In this case, return an invalid value does not mean that a net is not renamed
+     */
     bool is_net_renamed(const ClusterBlockId& block_id, const int& pin_index) const;
     ClusterNetId net(const ClusterBlockId& block_id, const int& pin_index) const;
+    bool is_truth_table_adapted(t_pb* pb) const;
+    AtomNetlist::TruthTable truth_table(t_pb* pb) const;
   public:  /* Public mutators */
     void rename_net(const ClusterBlockId& block_id, const int& pin_index,
                     const ClusterNetId& net_id);
+    void adapt_truth_table(t_pb* pb, const AtomNetlist::TruthTable& tt);
   private: /* Internal data */
     /* Pair a regular pb_type to its physical pb_type */
     std::map<ClusterBlockId, std::map<int, ClusterNetId>> net_names_;
+    std::map<t_pb*, AtomNetlist::TruthTable> block_truth_tables_;
 };
 
 } /* End namespace openfpga*/
diff --git a/openfpga/src/base/openfpga_lut_truth_table_fixup.cpp b/openfpga/src/base/openfpga_lut_truth_table_fixup.cpp
new file mode 100644
index 000000000..9280e96bc
--- /dev/null
+++ b/openfpga/src/base/openfpga_lut_truth_table_fixup.cpp
@@ -0,0 +1,185 @@
+/********************************************************************
+ * This file includes functions to fix up the pb pin mapping results 
+ * after routing optimization
+ *******************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_time.h"
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+/* Headers from vpr library */
+#include "vpr_utils.h"
+
+#include "pb_type_utils.h"
+#include "lut_utils.h"
+#include "openfpga_lut_truth_table_fixup.h"
+
+/* Include global variables of VPR */
+#include "globals.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Apply the fix-up to truth table of LUT according to its pin
+ * rotation status by packer
+ *
+ * Note: 
+ *   - pb must represents a LUT pb in the graph and it should be primitive
+ *******************************************************************/
+static 
+void fix_up_lut_atom_block_truth_table(const AtomContext& atom_ctx,
+                                       t_pb* pb,
+                                       const t_pb_routes& pb_route,
+                                       VprClusteringAnnotation& vpr_clustering_annotation,
+                                       const bool& verbose) {
+  t_pb_graph_node* pb_graph_node = pb->pb_graph_node;
+  t_pb_type* pb_type = pb->pb_graph_node->pb_type;
+
+  VTR_ASSERT(LUT_CLASS == pb_type->class_type);
+
+  for (int iport = 0; iport < pb_type->num_ports; ++iport) {
+    /* We only care about input ports whose pins are equivalent */
+    if (IN_PORT != pb_type->ports[iport].type || true == pb_type->ports[iport].is_clock) {
+      continue;
+    }
+    if (pb_type->ports[iport].equivalent == PortEquivalence::NONE) {
+      continue;
+    }
+    /* Reach here, we have to apply a fix-up */
+    AtomBlockId atom_blk = atom_ctx.nlist.find_block(pb->name);
+    VTR_ASSERT(atom_blk);
+
+    /* Port exists (some LUTs may have no input and hence no port in the atom netlist) */
+    AtomPortId atom_port = atom_ctx.nlist.find_atom_port(atom_blk, pb_type->ports[iport].model_port);
+    if (atom_port) { 
+      continue;
+    }
+
+    /* Find the pin rotation status and record it ,
+     * Note that some LUT inputs may not be used, we set them to be open by default
+     */
+    std::vector<int> rotated_pin_map(pb_type->ports[iport].num_pins, -1);
+    for (int ipin = 0; ipin < pb_type->ports[iport].num_pins; ++ipin) {
+      int node_index = pb_graph_node->input_pins[iport][ipin].pin_count_in_cluster;
+      if (pb_route.count(node_index)) {
+        /* The pin is mapped to a net, find the original pin in the atom netlist */
+        AtomNetId atom_net = pb_route[node_index].atom_net_id;
+
+        VTR_ASSERT(atom_net);
+
+        for (AtomPinId atom_pin : atom_ctx.nlist.port_pins(atom_port)) {
+
+          AtomNetId atom_pin_net = atom_ctx.nlist.pin_net(atom_pin);
+
+          if (atom_pin_net == atom_net) {
+            rotated_pin_map[ipin] = atom_ctx.nlist.pin_port_bit(atom_pin);
+            break;
+          }
+        }
+      }
+    }
+
+    /* We can apply truth table adaption now
+     * For unused inputs : insert dont care
+     * For used inputs : find the bit in the truth table rows and move it by the given mapping
+     */
+    const AtomNetlist::TruthTable& orig_tt = atom_ctx.nlist.block_truth_table(atom_blk);
+    const AtomNetlist::TruthTable& adapt_tt = lut_truth_table_adaption(orig_tt, rotated_pin_map); 
+    vpr_clustering_annotation.adapt_truth_table(pb, adapt_tt);
+
+    /* Print info is in the verbose mode */
+    VTR_LOGV(verbose, "Original truth table\n");
+    for (const std::string& tt_line : truth_table_to_string(orig_tt)) {
+      VTR_LOGV(verbose, "\t%s\n", tt_line.c_str());
+    }
+    VTR_LOGV(verbose, "\n");
+    VTR_LOGV(verbose, "Adapt truth table\n");
+    VTR_LOGV(verbose, "-----------------\n");
+    for (const std::string& tt_line : truth_table_to_string(adapt_tt)) {
+      VTR_LOGV(verbose, "\t%s\n", tt_line.c_str());
+    }
+    VTR_LOGV(verbose, "\n");
+  }
+}
+
+/********************************************************************
+ * This function recursively visits the pb graph until we reach a 
+ * LUT pb_type (primitive node in the pb_graph with a class type 
+ * of LUT_CLASS
+ * Once we find a LUT node, we will apply the fix-up
+ *******************************************************************/
+static 
+void rec_adapt_lut_pb_tt(const AtomContext& atom_ctx,
+                         t_pb* pb,
+                         const t_pb_routes& pb_route,
+                         VprClusteringAnnotation& vpr_clustering_annotation,
+                         const bool& verbose) {
+  t_pb_graph_node* pb_graph_node = pb->pb_graph_node; 
+
+  /* If we reach a primitive pb_graph node, we return */
+  if (true == is_primitive_pb_type(pb_graph_node->pb_type)) {
+    if (LUT_CLASS == pb_graph_node->pb_type->class_type) {
+      /* Do fix-up here */
+      fix_up_lut_atom_block_truth_table(atom_ctx, pb, pb_route, vpr_clustering_annotation, verbose);
+    }
+    return;
+  }
+
+  /* Recursively visit all the used pbs in the graph */
+  t_mode* mapped_mode = &(pb_graph_node->pb_type->modes[pb->mode]);
+  for (int ipb = 0; ipb < mapped_mode->num_pb_type_children; ++ipb) {
+    /* Each child may exist multiple times in the hierarchy*/
+    for (int jpb = 0; jpb < mapped_mode->pb_type_children[ipb].num_pb; ++jpb) {
+      /* See if we still have any pb children to walk through */
+      if ((pb->child_pbs[ipb] != nullptr) && (pb->child_pbs[ipb][jpb].name != nullptr)) {
+        rec_adapt_lut_pb_tt(atom_ctx, &(pb->child_pbs[ipb][jpb]), pb_route, vpr_clustering_annotation, verbose);
+      }
+    }
+  }
+}
+
+/********************************************************************
+ * Main function to fix up truth table for each LUT used in FPGA
+ * This function will walk through each clustered block
+ *******************************************************************/
+static 
+void update_lut_tt_with_post_packing_results(const AtomContext& atom_ctx,
+                                             const ClusteringContext& clustering_ctx,
+                                             VprClusteringAnnotation& vpr_clustering_annotation,
+                                             const bool& verbose) {
+  for (auto blk_id : clustering_ctx.clb_nlist.blocks()) {
+    rec_adapt_lut_pb_tt(atom_ctx,
+                        clustering_ctx.clb_nlist.block_pb(blk_id),
+                        clustering_ctx.clb_nlist.block_pb(blk_id)->pb_route,
+                        vpr_clustering_annotation, verbose);
+  }
+}
+
+
+/********************************************************************
+ * Top-level function to fix up the lut truth table results after packing is done
+ * The problem comes from a mismatch between the packing results and 
+ * original truth tables in users' BLIF file
+ * As LUT inputs are equivalent in nature, the router of packer will try
+ * to swap the net mapping among these pins so as to achieve best 
+ * routing optimization.
+ * However, it will cause the original truth table out-of-date when packing is done.
+ * This function aims to fix the mess after packing so that the truth table
+ * can be synchronized
+ *******************************************************************/
+void lut_truth_table_fixup(OpenfpgaContext& openfpga_context,
+                           const Command& cmd, const CommandContext& cmd_context) { 
+
+  vtr::ScopedStartFinishTimer timer("Fix up LUT truth tables after packing optimization");
+
+  CommandOptionId opt_verbose = cmd.option("verbose");
+
+  /* Apply fix-up to each packed block */
+  update_lut_tt_with_post_packing_results(g_vpr_ctx.atom(), 
+                                          g_vpr_ctx.clustering(),
+                                          openfpga_context.mutable_vpr_clustering_annotation(),
+                                          cmd_context.option_enable(cmd, opt_verbose));
+} 
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_lut_truth_table_fixup.h b/openfpga/src/base/openfpga_lut_truth_table_fixup.h
new file mode 100644
index 000000000..f11abc7fb
--- /dev/null
+++ b/openfpga/src/base/openfpga_lut_truth_table_fixup.h
@@ -0,0 +1,23 @@
+#ifndef OPENFPGA_LUT_TRUTH_TABLE_FIXUP_H
+#define OPENFPGA_LUT_TRUTH_TABLE_FIXUP_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "command.h"
+#include "command_context.h"
+#include "openfpga_context.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void lut_truth_table_fixup(OpenfpgaContext& openfpga_context, 
+                           const Command& cmd, const CommandContext& cmd_context); 
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/base/openfpga_setup_command.cpp b/openfpga/src/base/openfpga_setup_command.cpp
index 2a1edacbc..629300bf2 100644
--- a/openfpga/src/base/openfpga_setup_command.cpp
+++ b/openfpga/src/base/openfpga_setup_command.cpp
@@ -6,6 +6,7 @@
 #include "openfpga_read_arch.h"
 #include "openfpga_link_arch.h"
 #include "openfpga_pb_pin_fixup.h"
+#include "openfpga_lut_truth_table_fixup.h"
 #include "check_netlist_naming_conflict.h"
 #include "openfpga_setup_command.h"
 
@@ -100,6 +101,23 @@ void add_openfpga_setup_commands(openfpga::Shell<OpenfpgaContext>& shell) {
   cmd_dependency_pb_pin_fixup.push_back(shell_cmd_read_arch_id);
   cmd_dependency_pb_pin_fixup.push_back(shell_cmd_vpr_id);
   shell.set_command_dependency(shell_cmd_pb_pin_fixup_id, cmd_dependency_pb_pin_fixup);
+
+  /******************************** 
+   * Command 'lut_truth_table_fixup' 
+   */
+  Command shell_cmd_lut_truth_table_fixup("lut_truth_table_fixup");
+  /* Add an option '--verbose' */
+  shell_cmd_lut_truth_table_fixup.add_option("verbose", false, "Show verbose outputs");
+
+  /* Add command 'lut_truth_table_fixup' to the Shell */
+  ShellCommandId shell_cmd_lut_truth_table_fixup_id = shell.add_command(shell_cmd_lut_truth_table_fixup, "Fix up the truth table of Look-Up Tables due to pin swapping during packing stage");
+  shell.set_command_class(shell_cmd_lut_truth_table_fixup_id, openfpga_setup_cmd_class);
+  shell.set_command_execute_function(shell_cmd_lut_truth_table_fixup_id, lut_truth_table_fixup);
+  /* The 'pb_pin_fixup' command should NOT be executed before 'read_openfpga_arch' and 'vpr' */
+  std::vector<ShellCommandId> cmd_dependency_lut_truth_table_fixup;
+  cmd_dependency_lut_truth_table_fixup.push_back(shell_cmd_read_arch_id);
+  cmd_dependency_lut_truth_table_fixup.push_back(shell_cmd_vpr_id);
+  shell.set_command_dependency(shell_cmd_lut_truth_table_fixup_id, cmd_dependency_lut_truth_table_fixup);
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/utils/lut_utils.cpp b/openfpga/src/utils/lut_utils.cpp
new file mode 100644
index 000000000..505502782
--- /dev/null
+++ b/openfpga/src/utils/lut_utils.cpp
@@ -0,0 +1,93 @@
+/********************************************************************
+ * This file includes most utilized functions to manipulate LUTs, 
+ * especially their truth tables, in the OpenFPGA context
+ *******************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+#include "lut_utils.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * This function aims to adapt the truth table to a mapped physical LUT 
+ * subject to a pin rotation map
+ * The modification is applied to line by line
+ *   - For unused inputs : insert dont care
+ *   - For used inputs : find the bit in the truth table rows and move it by the given mapping
+ *
+ * The rotated pin map is the reference to adapt the truth table.
+ * Each element of the map represents the input index in the original truth table
+ * The sequence of the rotate pin map is the final sequence of how
+ * each line of the original truth table should be shuffled
+ * Example: 
+ *                     output_value(we do not modify)
+ *                               |
+ *                               v
+ *   Truth table line:       00111
+ *   rotated_pin_map:        2310
+ *   Adapt truth table line: 11001     
+ *******************************************************************/
+AtomNetlist::TruthTable lut_truth_table_adaption(const AtomNetlist::TruthTable& orig_tt, 
+                                                 const std::vector<int>& rotated_pin_map) {
+  AtomNetlist::TruthTable tt;
+
+  for (auto row : orig_tt) {
+    VTR_ASSERT(row.size() - 1 == rotated_pin_map.size());
+
+    std::vector<vtr::LogicValue> tt_line;
+    /* We do not care about the last digit, which is the output value */
+    for (size_t i = 0; i < row.size() - 1; ++i) {
+      if (-1 == rotated_pin_map[i]) {
+        tt_line.push_back(vtr::LogicValue::DONT_CARE);
+      } else { 
+        /* Ensure we never access the last digit, i.e., the output value! */
+        VTR_ASSERT((size_t)rotated_pin_map[i] < row.size() - 1);
+        tt_line.push_back(row[rotated_pin_map[i]]);
+      }
+    } 
+
+    /* Do not miss the last digit in the final result */
+    tt_line.push_back(row.back());
+    tt.push_back(tt_line);
+  }
+
+  return tt;
+} 
+
+/********************************************************************
+ * Convert a truth table to strings, which are ready to be printed out
+ *******************************************************************/
+std::vector<std::string> truth_table_to_string(const AtomNetlist::TruthTable& tt) { 
+  std::vector<std::string> tt_str;
+  for (auto row : tt) {
+    std::string row_str;
+    for (size_t i = 0; i < row.size(); ++i) {
+      /* Add a gap between inputs and outputs */
+      if (i == row.size() - 1) {
+        row_str += std::string(" ");
+      }
+      switch (row[i]) {
+        case vtr::LogicValue::TRUE:
+          row_str += std::string("1");
+          break;
+        case vtr::LogicValue::FALSE:
+          row_str += std::string("0");
+          break;
+        case vtr::LogicValue::DONT_CARE:
+          row_str += std::string("-");
+          break;
+        default:
+          VTR_ASSERT_MSG(false, "Valid single-output cover logic value");
+      }
+    }
+    tt_str.push_back(row_str);
+  }
+
+  return tt_str;
+}
+
+} /* end namespace openfpga */
+
diff --git a/openfpga/src/utils/lut_utils.h b/openfpga/src/utils/lut_utils.h
new file mode 100644
index 000000000..800c1fc59
--- /dev/null
+++ b/openfpga/src/utils/lut_utils.h
@@ -0,0 +1,25 @@
+#ifndef LUT_UTILS_H
+#define LUT_UTILS_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <string>
+#include <vector>
+#include "atom_netlist.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+AtomNetlist::TruthTable lut_truth_table_adaption(const AtomNetlist::TruthTable& orig_tt, 
+                                                 const std::vector<int>& rotated_pin_map);
+
+std::vector<std::string> truth_table_to_string(const AtomNetlist::TruthTable& tt);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/test_script/s298_k6_frac.openfpga b/openfpga/test_script/s298_k6_frac.openfpga
index 9681918c4..f4a5bc979 100644
--- a/openfpga/test_script/s298_k6_frac.openfpga
+++ b/openfpga/test_script/s298_k6_frac.openfpga
@@ -13,5 +13,8 @@ check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
 # Apply fix-up to clustering nets based on routing results
 pb_pin_fixup --verbose
 
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup --verbose
+
 # Finish and exit OpenFPGA
 exit

From 3d7eff64b997842fb0c6d75d5b367ce3c6658c5f Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 6 Feb 2020 17:47:25 -0700
Subject: [PATCH 108/645] bug fixed for lut truth table fixup. Results look
 good

---
 .../base/openfpga_lut_truth_table_fixup.cpp   | 34 ++++++++++++++++---
 openfpga/src/utils/lut_utils.cpp              |  4 +--
 2 files changed, 32 insertions(+), 6 deletions(-)

diff --git a/openfpga/src/base/openfpga_lut_truth_table_fixup.cpp b/openfpga/src/base/openfpga_lut_truth_table_fixup.cpp
index 9280e96bc..45ecbca31 100644
--- a/openfpga/src/base/openfpga_lut_truth_table_fixup.cpp
+++ b/openfpga/src/base/openfpga_lut_truth_table_fixup.cpp
@@ -52,7 +52,7 @@ void fix_up_lut_atom_block_truth_table(const AtomContext& atom_ctx,
 
     /* Port exists (some LUTs may have no input and hence no port in the atom netlist) */
     AtomPortId atom_port = atom_ctx.nlist.find_atom_port(atom_blk, pb_type->ports[iport].model_port);
-    if (atom_port) { 
+    if (!atom_port) { 
       continue;
     }
 
@@ -90,12 +90,31 @@ void fix_up_lut_atom_block_truth_table(const AtomContext& atom_ctx,
 
     /* Print info is in the verbose mode */
     VTR_LOGV(verbose, "Original truth table\n");
+    VTR_LOGV(verbose, "Index: ");
+    for (size_t i = 0; i < rotated_pin_map.size(); ++i) {
+      if (0 < i) {
+        VTR_LOGV(verbose, ",");
+      }
+      VTR_LOGV(verbose, "%lu", i);
+    }
+    VTR_LOGV(verbose, "\n");
     for (const std::string& tt_line : truth_table_to_string(orig_tt)) {
       VTR_LOGV(verbose, "\t%s\n", tt_line.c_str());
     }
     VTR_LOGV(verbose, "\n");
+    VTR_LOGV(verbose, "Pin rotation map: ");
+    for (size_t i = 0; i < rotated_pin_map.size(); ++i) {
+      if (0 < i) {
+        VTR_LOGV(verbose, ",");
+      }
+      if (-1 == rotated_pin_map[i]) {
+        VTR_LOGV(verbose, "open");
+      } else {
+        VTR_LOGV(verbose, "%lu", rotated_pin_map[i]);
+      }
+    }
+    VTR_LOGV(verbose, "\n");
     VTR_LOGV(verbose, "Adapt truth table\n");
-    VTR_LOGV(verbose, "-----------------\n");
     for (const std::string& tt_line : truth_table_to_string(adapt_tt)) {
       VTR_LOGV(verbose, "\t%s\n", tt_line.c_str());
     }
@@ -120,8 +139,15 @@ void rec_adapt_lut_pb_tt(const AtomContext& atom_ctx,
   /* If we reach a primitive pb_graph node, we return */
   if (true == is_primitive_pb_type(pb_graph_node->pb_type)) {
     if (LUT_CLASS == pb_graph_node->pb_type->class_type) {
-      /* Do fix-up here */
-      fix_up_lut_atom_block_truth_table(atom_ctx, pb, pb_route, vpr_clustering_annotation, verbose);
+      /* Do fix-up here.
+       * Note that LUTs have two modes, 
+       * For wire modes, we should skip the truth table adaption
+       * mode 0 is reserved for wire, see read_xml_arch_file.cpp
+       * mode 1 is the regular mode
+       */
+      if (1 == pb->mode) {
+        fix_up_lut_atom_block_truth_table(atom_ctx, pb->child_pbs[0], pb_route, vpr_clustering_annotation, verbose);
+      }
     }
     return;
   }
diff --git a/openfpga/src/utils/lut_utils.cpp b/openfpga/src/utils/lut_utils.cpp
index 505502782..e2b01edb5 100644
--- a/openfpga/src/utils/lut_utils.cpp
+++ b/openfpga/src/utils/lut_utils.cpp
@@ -35,11 +35,11 @@ AtomNetlist::TruthTable lut_truth_table_adaption(const AtomNetlist::TruthTable&
   AtomNetlist::TruthTable tt;
 
   for (auto row : orig_tt) {
-    VTR_ASSERT(row.size() - 1 == rotated_pin_map.size());
+    VTR_ASSERT(row.size() - 1 <= rotated_pin_map.size());
 
     std::vector<vtr::LogicValue> tt_line;
     /* We do not care about the last digit, which is the output value */
-    for (size_t i = 0; i < row.size() - 1; ++i) {
+    for (size_t i = 0; i < rotated_pin_map.size(); ++i) {
       if (-1 == rotated_pin_map[i]) {
         tt_line.push_back(vtr::LogicValue::DONT_CARE);
       } else { 

From 0b6b3bc0290e3bb7df1c2b740aace60df105f91e Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 7 Feb 2020 11:32:33 -0700
Subject: [PATCH 109/645] start adapting rr_gsb related data structure

---
 openfpga/src/annotation/device_rr_gsb.h | 106 ++++++++++++
 openfpga/src/annotation/rr_chan.cpp     | 221 ++++++++++++++++++++++++
 openfpga/src/annotation/rr_chan.h       |  95 ++++++++++
 openfpga/src/annotation/rr_gsb.h        | 193 +++++++++++++++++++++
 4 files changed, 615 insertions(+)
 create mode 100644 openfpga/src/annotation/device_rr_gsb.h
 create mode 100644 openfpga/src/annotation/rr_chan.cpp
 create mode 100644 openfpga/src/annotation/rr_chan.h
 create mode 100644 openfpga/src/annotation/rr_gsb.h

diff --git a/openfpga/src/annotation/device_rr_gsb.h b/openfpga/src/annotation/device_rr_gsb.h
new file mode 100644
index 000000000..e801417bc
--- /dev/null
+++ b/openfpga/src/annotation/device_rr_gsb.h
@@ -0,0 +1,106 @@
+#ifndef DEVICE_RR_GSB_H
+#define DEVICE_RR_GSB_H
+
+/********************************************************************
+ * Include header files required by the data structure definition
+ *******************************************************************/
+#include "rr_gsb.h"
+
+/********************************************************************
+ * Object Device Routing Resource Switch Block 
+ * This includes:
+ * 1. a collection of RRSwitch blocks, each of which can be used to instance Switch blocks in the top-level netlists
+ * 2. a collection of unique mirrors of RRGSBs, which can be used to output Verilog / SPICE modules
+ * 3. a colleciton of unique rotatable of RRGSBs, which can be used to output Verilog / SPICE modules
+ *    The rotatable RRGSBs are more generic mirrors, which allow SwitchBlocks to be wired by rotating the pins, 
+ *    further reduce the number of Verilog/SPICE modules outputted. This will lead to rapid layout generation  
+ *******************************************************************/
+class DeviceRRGSB {
+  public: /* Contructors */
+  public: /* Accessors */
+    DeviceCoordinator get_gsb_range() const; /* get the max coordinator of the switch block array */
+    const RRGSB get_gsb(const DeviceCoordinator& coordinator) const; /* Get a rr switch block in the array with a coordinator */
+    const RRGSB get_gsb(size_t x, size_t y) const; /* Get a rr switch block in the array with a coordinator */
+    size_t get_num_gsb_unique_module() const; /* get the number of unique mirrors of GSB */
+    size_t get_num_sb_unique_submodule(enum e_side side, size_t seg_index) const; /* get the number of unique mirrors of switch blocks */
+    size_t get_num_sb_unique_module() const; /* get the number of unique mirrors of switch blocks */
+    size_t get_num_cb_unique_module(t_rr_type cb_type) const; /* get the number of unique mirrors of CBs */
+    size_t get_sb_unique_submodule_id(DeviceCoordinator& coordinator, enum e_side side, size_t seg_id) const;
+    const RRGSB get_sb_unique_submodule(size_t index, enum e_side side, size_t seg_id) const; /* Get a rr switch block which a unique mirror */ 
+    const RRGSB get_sb_unique_submodule(DeviceCoordinator& coordinator, enum e_side side, size_t seg_id) const; /* Get a rr switch block which a unique mirror */ 
+    const RRGSB get_sb_unique_module(size_t index) const; /* Get a rr switch block which a unique mirror */ 
+    const RRGSB get_sb_unique_module(const DeviceCoordinator& coordinator) const; /* Get a rr switch block which a unique mirror */ 
+    const RRGSB& get_cb_unique_module(t_rr_type cb_type, size_t index) const; /* Get a rr switch block which a unique mirror */ 
+    const RRGSB& get_cb_unique_module(t_rr_type cb_type, const DeviceCoordinator& coordinator) const;
+    size_t get_max_num_sides() const; /* Get the maximum number of sides across the switch blocks */
+    size_t get_num_segments() const; /* Get the size of segment_ids */
+    size_t get_segment_id(size_t index) const; /* Get a segment id */
+    bool is_two_sb_share_same_submodules(DeviceCoordinator& src, DeviceCoordinator& des) const;
+  public: /* Mutators */ 
+    void set_sb_num_reserved_conf_bits(DeviceCoordinator& coordinator, size_t num_reserved_conf_bits); /* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */
+    void set_sb_conf_bits_lsb(DeviceCoordinator& coordinator, size_t conf_bits_lsb); /* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */
+    void set_sb_conf_bits_msb(DeviceCoordinator& coordinator, size_t conf_bits_msb); /* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */
+    void set_cb_num_reserved_conf_bits(DeviceCoordinator& coordinator, t_rr_type cb_type, size_t num_reserved_conf_bits); /* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */
+    void set_cb_conf_bits_lsb(DeviceCoordinator& coordinator, t_rr_type cb_type, size_t conf_bits_lsb); /* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */
+    void set_cb_conf_bits_msb(DeviceCoordinator& coordinator, t_rr_type cb_type, size_t conf_bits_msb); /* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */
+    void reserve(DeviceCoordinator& coordinator); /* Pre-allocate the rr_switch_block array that the device requires */ 
+    void reserve_sb_unique_submodule_id(DeviceCoordinator& coordinator); /* Pre-allocate the rr_sb_unique_module_id matrix that the device requires */ 
+    void resize_upon_need(const DeviceCoordinator& coordinator); /* Resize the rr_switch_block array if needed */ 
+    void add_rr_gsb(const DeviceCoordinator& coordinator, const RRGSB& rr_gsb); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
+    void build_unique_module(); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
+    void clear(); /* clean the content */
+  private: /* Internal cleaners */
+    void clear_gsb(); /* clean the content */
+    void clear_cb_unique_module(t_rr_type cb_type); /* clean the content */
+    void clear_cb_unique_module_id(t_rr_type cb_type); /* clean the content */
+    void clear_sb_unique_module(); /* clean the content */
+    void clear_sb_unique_module_id(); /* clean the content */
+    void clear_sb_unique_submodule(); /* clean the content */
+    void clear_sb_unique_submodule_id(); /* clean the content */
+    void clear_gsb_unique_module(); /* clean the content */
+    void clear_gsb_unique_module_id(); /* clean the content */
+    void clear_segment_ids();
+  private: /* Validators */
+    bool validate_coordinator(const DeviceCoordinator& coordinator) const; /* Validate if the (x,y) is the range of this device */
+    bool validate_coordinator_edge(DeviceCoordinator& coordinator) const; /* Validate if the (x,y) is the range of this device but takes into consideration the fact that edges are 1 off */
+    bool validate_side(enum e_side side) const; /* validate if side is in the range of unique_side_module_ */
+    bool validate_sb_unique_module_index(size_t index) const; /* Validate if the index in the range of unique_mirror vector*/
+    bool validate_cb_unique_module_index(t_rr_type cb_type, size_t index) const; /* Validate if the index in the range of unique_mirror vector*/
+    bool validate_sb_unique_submodule_index(size_t index, enum e_side side, size_t seg_index) const; /* Validate if the index in the range of unique_module vector */
+    bool validate_segment_index(size_t index) const;
+    bool validate_cb_type(t_rr_type cb_type) const;
+  private: /* Internal builders */
+    void build_segment_ids(); /* build a map of segment_ids */
+    void add_gsb_unique_module(const DeviceCoordinator& coordinator);
+    void add_sb_unique_side_submodule(DeviceCoordinator& coordinator, const RRGSB& rr_sb, enum e_side side);
+    void add_sb_unique_side_segment_submodule(DeviceCoordinator& coordinator, const RRGSB& rr_sb, enum e_side side, size_t seg_id);
+    void add_cb_unique_module(t_rr_type cb_type, const DeviceCoordinator& coordinator);
+    void set_cb_unique_module_id(t_rr_type, const DeviceCoordinator& coordinator, size_t id);
+    void build_sb_unique_submodule(); /* Add a switch block to the array, which will automatically identify and update the lists of unique side module */
+    void build_sb_unique_module(); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
+    void build_cb_unique_module(t_rr_type cb_type); /* Add a switch block to the array, which will automatically identify and update the lists of unique side module */
+    void build_gsb_unique_module(); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
+  private: /* Internal Data */
+    std::vector< std::vector<RRGSB> > rr_gsb_;
+
+    std::vector< std::vector<size_t> > gsb_unique_module_id_; /* A map from rr_gsb to its unique mirror */
+    std::vector<DeviceCoordinator> gsb_unique_module_; 
+
+    std::vector< std::vector<size_t> > sb_unique_module_id_; /* A map from rr_gsb to its unique mirror */
+    std::vector<DeviceCoordinator> sb_unique_module_; 
+
+    std::vector< std::vector< std::vector< std::vector<size_t> > > > sb_unique_submodule_id_; /* A map from rr_switch_block to its unique_side_module [0..x][0..y][0..num_sides][num_seg-1]*/
+    std::vector< std::vector <std::vector<DeviceCoordinator> > > sb_unique_submodule_; /* For each side of switch block, we identify a list of unique modules based on its connection. This is a matrix [0..num_sides-1][0..num_seg-1][0..num_module], num_sides will the max number of sides of all the rr_switch_blocks */
+
+    std::vector< std::vector<size_t> > cbx_unique_module_id_; /* A map from rr_gsb to its unique mirror */
+    std::vector<DeviceCoordinator> cbx_unique_module_; /* For each side of connection block, we identify a list of unique modules based on its connection. This is a matrix [0..num_module] */
+
+    std::vector< std::vector<size_t> > cby_unique_module_id_; /* A map from rr_gsb to its unique mirror */
+    std::vector<DeviceCoordinator> cby_unique_module_; /* For each side of connection block, we identify a list of unique modules based on its connection. This is a matrix [0..num_module] */
+
+    std::vector<size_t> segment_ids_;
+};
+
+} /* End namespace openfpga*/
+
+#endif
diff --git a/openfpga/src/annotation/rr_chan.cpp b/openfpga/src/annotation/rr_chan.cpp
new file mode 100644
index 000000000..84540758e
--- /dev/null
+++ b/openfpga/src/annotation/rr_chan.cpp
@@ -0,0 +1,221 @@
+/************************************************************************
+ * Member functions for class RRChan
+ ***********************************************************************/
+#include "vtr_log.h"
+#include "vtr_assert.h"
+#include "rr_chan.h"
+
+/* namespace openfpga begins */
+namespace openfpga {
+
+/************************************************************************
+ * Constructors
+ ***********************************************************************/
+/* Copy Constructor */
+RRChan::RRChan(const RRChan& rr_chan) {
+  this->set(rr_chan);
+  return;
+}
+
+/* default constructor */
+RRChan::RRChan() {
+  type_ = NUM_RR_TYPES;
+  nodes_.resize(0);
+  node_segments_.resize(0);
+}
+
+/* Accessors */
+t_rr_type RRChan::get_type() const {
+  return type_;
+}
+
+/* get the number of tracks in this channel */
+size_t RRChan::get_chan_width() const { 
+  return nodes_.size();
+}
+
+/* get the track_id of a node */
+int RRChan::get_node_track_id(const RRNodeId& node) const {
+  /* if the given node is NULL, we return an invalid id */
+  if (RRNodeId::INVALID() == node) {
+    return -1;
+  }
+  /* check each member and return if we find a match in content */
+  std::vector<RRNodeId>::const_iterator it = std::find(nodes_.begin(), nodes_.end(), node);
+  if (nodes_.end() == it) {
+    return -1;
+  }
+  return it - nodes_.begin();
+}
+
+/* get the rr_node with the track_id */
+RRNodeId RRChan::get_node(const size_t& track_num) const {
+  if ( false == valid_node_id(track_num) ) {
+    return RRNodeId::INVALID();
+  }
+  return nodes_[track_num];
+} 
+
+/* get the segment id of a node */
+RRSegmentId RRChan::get_node_segment(const RRNodeId& node) const {
+  int node_id = get_node_track_id(node);
+  if ( false == valid_node_id(node_id)) {
+    return RRSegmentId::INVALID();
+  }
+  return get_node_segment(node_id); 
+}
+
+/* get the segment id of a node */
+RRSegmentId RRChan::get_node_segment(const size_t& track_num) const {
+  if ( false == valid_node_id(track_num)) {
+    return RRSegmentId::INVALID();
+  }
+  return node_segments_[track_num]; 
+}
+
+/* evaluate if two RRChan is mirror to each other */
+bool RRChan::is_mirror(const RRGraph& rr_graph, const RRChan& cand) const {
+  /* If any following element does not match, it is not mirror */
+  /* 1. type  */
+  if (this->get_type() != cand.get_type()) {
+    return false;
+  }
+  /* 2. track_width  */
+  if (this->get_chan_width() != cand.get_chan_width()) {
+    return false;
+  }
+  /* 3. for each node */
+  for (size_t inode = 0; inode < this->get_chan_width(); ++inode) {
+    /* 3.1 check node type */
+    if (rr_graph.node_type(this->get_node(inode)) != rr_graph.node_type(cand.get_node(inode))) {
+      return false;
+    }
+    /* 3.2 check node directionality */
+    if (rr_graph.node_direction(this->get_node(inode)) != rr_graph.node_direction(cand.get_node(inode))) {
+      return false;
+    }
+    /* 3.3 check node segment */
+    if (this->get_node_segment(inode) != cand.get_node_segment(inode)) {
+      return false;
+    }
+  }
+ 
+  return true;
+}
+
+/* Get a list of segments used in this routing channel */
+std::vector<RRSegmentId> RRChan::get_segment_ids() const { 
+  std::vector<RRSegmentId> seg_list;
+
+  /* make sure a clean start */
+  seg_list.clear();
+
+  /* Traverse node_segments */
+  for (size_t inode = 0; inode < get_chan_width(); ++inode) {
+    std::vector<RRSegmentId>::iterator it;
+    /* Try to find the node_segment id in the list */
+    it = find(seg_list.begin(), seg_list.end(), node_segments_[inode]);
+    if ( it == seg_list.end() ) {
+      /* Not found, add it to the list */
+      seg_list.push_back(node_segments_[inode]);
+    }
+  }
+
+  return seg_list;
+}
+
+/* Get a list of nodes whose segment_id is specified  */
+std::vector<RRNodeId> RRChan::get_node_ids_by_segment_ids(const RRSegmentId& seg_id) const {
+  std::vector<RRNodeId> node_list;
+
+  /* make sure a clean start */
+  node_list.clear();
+
+  /* Traverse node_segments */
+  for (size_t inode = 0; inode < get_chan_width(); ++inode) {
+    /* Try to find the node_segment id in the list */
+    if ( seg_id == node_segments_[inode] ) {
+      node_list.push_back(nodes_[inode]);
+    }
+  }
+
+  return node_list;
+} 
+
+/* Mutators */
+void RRChan::set(const RRChan& rr_chan) {
+  /* Ensure a clean start */
+  this->clear();
+  /* Assign type of this routing channel */
+  this->type_ = rr_chan.get_type();
+  /* Copy node and node_segments */
+  this->nodes_.resize(rr_chan.get_chan_width());
+  this->node_segments_.resize(rr_chan.get_chan_width());
+  for (size_t inode = 0; inode < rr_chan.get_chan_width(); ++inode) { 
+    this->nodes_[inode] = rr_chan.get_node(inode);
+    this->node_segments_[inode] = rr_chan.get_node_segment(inode);
+  }
+  return;
+}
+
+/* modify type */
+void RRChan::set_type(const t_rr_type& type) {
+  VTR_ASSERT(valid_type(type));
+  type_ = type;
+} 
+
+/* Reserve node list */
+void RRChan::reserve_node(const size_t& node_size) {
+  nodes_.reserve(node_size); /* reserve to the maximum */
+  node_segments_.reserve(node_size); /* reserve to the maximum */
+}
+
+/* add a node to the array */
+void RRChan::add_node(const RRGraph& rr_graph, const RRNodeId& node, const RRSegmentId& node_segment) {
+  /* fill the dedicated element in the vector */
+  nodes_.push_back(node);
+  node_segments_.push_back(node_segment);
+
+  VTR_ASSERT(valid_node_type(rr_graph, node));
+}
+
+/* Clear content */
+void RRChan::clear() {
+  nodes_.clear();
+  node_segments_.clear();
+}
+
+/************************************************************************
+ * Internal functions
+ ***********************************************************************/
+/* for type, only valid type is CHANX and CHANY */
+bool RRChan::valid_type(const t_rr_type& type) const {
+  if ((CHANX == type) || (CHANY == type)) {
+    return true;
+  }
+  return false;
+}  
+
+/* Check each node, see if the node type is consistent with the type */
+bool RRChan::valid_node_type(const RRGraph& rr_graph, const RRNodeId& node) const {
+  valid_type(rr_graph.node_type(node));
+  if (NUM_RR_TYPES == type_) {
+    return true;
+  }
+  valid_type(type_);
+  if (type_ != rr_graph.node_type(node)) {
+    return false;
+  }
+  return true;
+}
+
+/* check if the node id is valid */
+bool RRChan::valid_node_id(const size_t& node_id) const {
+  if (node_id < nodes_.size()) {
+    return true;
+  }
+
+  return false;
+}
+
+} /* End namespace openfpga*/
diff --git a/openfpga/src/annotation/rr_chan.h b/openfpga/src/annotation/rr_chan.h
new file mode 100644
index 000000000..ab8bb6617
--- /dev/null
+++ b/openfpga/src/annotation/rr_chan.h
@@ -0,0 +1,95 @@
+#ifndef RR_CHAN_H
+#define RR_CHAN_H
+
+/********************************************************************
+ * Include header files required by the data structure definition
+ *******************************************************************/
+#include <vector>
+
+/* Headers from vtrutil library */
+#include "vtr_geometry.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_port.h"
+
+/* Headers from vpr library */
+#include "rr_graph_obj.h"
+
+/* Begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * RRChan object aim to describe a routing channel in a routing resource graph 
+ *  - What are the nodes in the RRGraph object, for each routing track
+ *  - What are routing segments used by each node in the channel
+ *  - What are the directions of each routing channel 
+ *    being either X-direction or Y-direction
+ *
+ * Note : 
+ *  - This is a collection of rr_nodes from the RRGraph Object 
+ *    It does not rebuild or contruct any connects between rr_nodes
+ *    It is just an annotation on an existing RRGraph
+ *   -------------   ------
+ *  |             | |      |
+ *  |             | |  Y   |
+ *  |     CLB     | | Chan |
+ *  |             | |      |
+ *  |             | |      |
+ *   -------------   ------
+ *   -------------
+ *  |      X      |
+ *  |    Channel  |
+ *   -------------
+ *******************************************************************/
+class RRChan {
+  public: /* Constructors */
+    RRChan(const RRChan&); /* Copy Constructor */
+    RRChan();
+  public: /* Accessors */
+    t_rr_type get_type() const;
+    size_t get_chan_width() const; /* get the number of tracks in this channel */
+    int get_node_track_id(const RRNodeId& node) const; /* get the track_id of a node */
+    RRNodeId get_node(const size_t& track_num) const; /* get the rr_node with the track_id */
+    RRSegmentId get_node_segment(const RRNodeId& node) const;
+    RRSegmentId get_node_segment(const size_t& track_num) const;
+    bool is_mirror(const RRGraph& rr_graph, const RRChan& cand) const; /* evaluate if two RR_chan is mirror to each other */
+    std::vector<RRSegmentId> get_segment_ids() const; /* Get a list of segments used in this routing channel */
+    std::vector<RRNodeId> get_node_ids_by_segment_ids(const RRSegmentId& seg_id) const; /* Get a list of segments used in this routing channel */
+  public: /* Mutators */
+    /* copy */
+    void set(const RRChan&); 
+
+    /* modify the type of routing channel */
+    void set_type(const t_rr_type& type); 
+
+    /* reseve a number of nodes to the array */
+    void reserve_node(const size_t& node_size); 
+
+    /* add a node to the routing channel */
+    void add_node(const RRGraph& rr_graph, const RRNodeId& node, const RRSegmentId& node_segment); 
+
+    /* clear the content */
+    void clear(); 
+
+  private: /* internal functions */
+
+    /* For the type of a routing channel, only valid type is CHANX and CHANY */
+    bool valid_type(const t_rr_type& type) const;  
+
+    /* Check each node, see if the node type is consistent with the type of routing channel */
+    bool valid_node_type(const RRGraph& rr_graph, const RRNodeId& node) const;  
+
+    /* Validate if the track number in the range */
+    bool valid_node_id(const size_t& node_id) const;  
+
+  private: /* Internal Data */
+    t_rr_type type_; /* channel type: CHANX or CHANY */
+    std::vector<RRNodeId> nodes_; /* rr nodes of each track in the channel */
+    std::vector<RRSegmentId> node_segments_; /* segment of each track */
+};
+
+
+
+} /* End namespace openfpga*/
+
+#endif
diff --git a/openfpga/src/annotation/rr_gsb.h b/openfpga/src/annotation/rr_gsb.h
new file mode 100644
index 000000000..7febeffc7
--- /dev/null
+++ b/openfpga/src/annotation/rr_gsb.h
@@ -0,0 +1,193 @@
+#ifndef RR_GSB_H
+#define RR_GSB_H
+
+/********************************************************************
+ * Include header files required by the data structure definition
+ *******************************************************************/
+#include "rr_chan.h"
+
+/* Begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Object Generic Switch Block 
+ * This block contains
+ * 1. A switch block
+ * 2. A X-direction Connection block locates at the left side of the switch block
+ * 2. A Y-direction Connection block locates at the top side of the switch block
+ * This is a collection of rr_nodes, which may be replaced with RRNodeId in new RRGraph 
+ *
+ *                               +---------------------------------+
+ *                               |          Y-direction CB         |
+ *                               |              [x][y + 1]         |
+ *                               +---------------------------------+
+ *                  
+ *                                          TOP SIDE
+ *  +-------------+              +---------------------------------+
+ *  |             |              | OPIN_NODE CHAN_NODES OPIN_NODES |
+ *  |             |              |                                 |
+ *  |             |              | OPIN_NODES           OPIN_NODES |
+ *  | X-direction |              |                                 |
+ *  |      CB     |  LEFT SIDE   |        Switch Block             |  RIGHT SIDE
+ *  |   [x][y]    |              |              [x][y]             |
+ *  |             |              |                                 |
+ *  |             |              | CHAN_NODES           CHAN_NODES |
+ *  |             |              |                                 |
+ *  |             |              | OPIN_NODES           OPIN_NODES |
+ *  |             |              |                                 |
+ *  |             |              | OPIN_NODE CHAN_NODES OPIN_NODES |
+ *  +-------------+              +---------------------------------+
+ *                                             BOTTOM SIDE
+ * num_sides: number of sides of this switch block
+ * chan_rr_node: a collection of rr_nodes as routing tracks locating at each side of the Switch block <0..num_sides-1><0..chan_width-1>
+ * chan_rr_node_direction: Indicate if this rr_node is an input or an output of the Switch block <0..num_sides-1><0..chan_width-1>
+ * ipin_rr_node: a collection of rr_nodes as IPIN of a GRID locating at each side of the Switch block <0..num_sides-1><0..num_ipin_rr_nodes-1>
+ * ipin_rr_node_grid_side: specify the side of the input pins on which side of a GRID  <0..num_sides-1><0..num_ipin_rr_nodes-1>
+ * opin_rr_node: a collection of rr_nodes as OPIN of a GRID locating at each side of the Switch block <0..num_sides-1><0..num_opin_rr_nodes-1>
+ * opin_rr_node_grid_side: specify the side of the output pins on which side of a GRID  <0..num_sides-1><0..num_opin_rr_nodes-1>
+ * num_reserved_conf_bits: number of reserved configuration bits this switch block requires (mainly due to RRAM-based multiplexers)
+ * num_conf_bits: number of configuration bits this switch block requires
+ *******************************************************************/
+class RRGSB {
+  public: /* Contructors */
+    RRGSB(const RRGSB&);/* Copy constructor */
+    RRGSB();/* Default constructor */
+  public: /* Accessors */
+    size_t get_num_sides() const; /* Get the number of sides of this SB */
+    size_t get_chan_width(enum e_side side) const; /* Get the number of routing tracks on a side */
+    size_t get_cb_chan_width(t_rr_type cb_type) const; /* Get the number of routing tracks of a X/Y-direction CB */
+    std::vector<enum e_side> get_cb_ipin_sides(t_rr_type cb_type) const; /* Get the sides of CB ipins in the array */
+    size_t get_max_chan_width() const; /* Get the maximum number of routing tracks on all sides */
+    enum PORTS get_chan_node_direction(enum e_side side, size_t track_id) const; /* Get the direction of a rr_node at a given side and track_id */
+    RRChan get_chan(enum e_side side) const; /* get a rr_node at a given side and track_id */
+    std::vector<size_t> get_chan_segment_ids(enum e_side side) const; /* Get a list of segments used in this routing channel */
+    std::vector<size_t> get_chan_node_ids_by_segment_ids(enum e_side side, size_t seg_id) const; /* Get a list of segments used in this routing channel */
+    t_rr_node* get_chan_node(enum e_side side, size_t track_id) const; /* get a rr_node at a given side and track_id */
+    size_t get_chan_node_segment(enum e_side side, size_t track_id) const; /* get the segment id of a channel rr_node */
+    size_t get_num_ipin_nodes(enum e_side side) const; /* Get the number of IPIN rr_nodes on a side */
+    t_rr_node* get_ipin_node(enum e_side side, size_t node_id) const; /* get a rr_node at a given side and track_id */
+    enum e_side get_ipin_node_grid_side(enum e_side side, size_t node_id) const; /* get a rr_node at a given side and track_id */
+    enum e_side get_ipin_node_grid_side(t_rr_node* ipin_node) const; /* get a rr_node at a given side and track_id */
+    size_t get_num_opin_nodes(enum e_side side) const; /* Get the number of OPIN rr_nodes on a side */
+    t_rr_node* get_opin_node(enum e_side side, size_t node_id) const; /* get a rr_node at a given side and track_id */
+    enum e_side get_opin_node_grid_side(enum e_side side, size_t node_id) const; /* get a rr_node at a given side and track_id */
+    enum e_side get_opin_node_grid_side(t_rr_node* opin_node) const; /* get a rr_node at a given side and track_id */
+    int get_cb_chan_node_index(t_rr_type cb_type, t_rr_node* node) const;
+    int get_chan_node_index(enum e_side node_side, t_rr_node* node) const;
+    int get_node_index(t_rr_node* node, enum e_side node_side, enum PORTS node_direction) const; /* Get the node index in the array, return -1 if not found */
+    void get_node_side_and_index(t_rr_node* node,  enum PORTS node_direction, enum e_side* node_side, int* node_index) const; /* Given a rr_node, try to find its side and index in the Switch block */
+    bool is_sb_node_exist_opposite_side(t_rr_node* node, enum e_side node_side) const; /* Check if the node exist in the opposite side of this Switch Block */
+  public: /* Accessors: get information about configuration ports */
+    size_t get_sb_num_reserved_conf_bits() const;
+    size_t get_sb_reserved_conf_bits_lsb() const;
+    size_t get_sb_reserved_conf_bits_msb() const;
+    size_t get_sb_num_conf_bits() const;
+    size_t get_sb_conf_bits_lsb() const;
+    size_t get_sb_conf_bits_msb() const;
+    size_t get_cb_num_reserved_conf_bits(t_rr_type cb_type) const;
+    size_t get_cb_reserved_conf_bits_lsb(t_rr_type cb_type) const;
+    size_t get_cb_reserved_conf_bits_msb(t_rr_type cb_type) const;
+    size_t get_cb_num_conf_bits(t_rr_type cb_type) const;
+    size_t get_cb_conf_bits_lsb(t_rr_type cb_type) const;
+    size_t get_cb_conf_bits_msb(t_rr_type cb_type) const;
+    bool is_sb_node_passing_wire(const enum e_side node_side, const size_t track_id) const; /* Check if the node imply a short connection inside the SB, which happens to long wires across a FPGA fabric */
+    bool is_sb_side_mirror(const RRGSB& cand, enum e_side side) const; /* check if a side of candidate SB is a mirror of the current one */
+    bool is_sb_side_segment_mirror(const RRGSB& cand, enum e_side side, size_t seg_id) const; /* check if all the routing segments of a side of candidate SB is a mirror of the current one */
+    bool is_sb_mirror(const RRGSB& cand) const; /* check if the candidate SB is a mirror of the current one */
+    bool is_sb_mirrorable(const RRGSB& cand) const; /* check if the candidate SB satisfy the basic requirements on being a mirror of the current one */
+    bool is_cb_mirror(const RRGSB& cand, t_rr_type cb_type) const; /* check if the candidate SB is a mirror of the current one */
+    bool is_cb_exist(t_rr_type cb_type) const; /* check if the candidate SB is a mirror of the current one */
+    size_t get_hint_rotate_offset(const RRGSB& cand) const; /* Determine an initial offset in rotating the candidate Switch Block to find a mirror matching*/
+  public: /* Cooridinator conversion and output  */
+    size_t get_x() const; /* get the x coordinator of this switch block */
+    size_t get_y() const; /* get the y coordinator of this switch block */
+    size_t get_sb_x() const; /* get the x coordinator of this switch block */
+    size_t get_sb_y() const; /* get the y coordinator of this switch block */
+    DeviceCoordinator get_sb_coordinator() const; /* Get the coordinator of the SB */
+    size_t get_cb_x(t_rr_type cb_type) const; /* get the x coordinator of this X/Y-direction block */
+    size_t get_cb_y(t_rr_type cb_type) const; /* get the y coordinator of this X/Y-direction block */
+    DeviceCoordinator get_cb_coordinator(t_rr_type cb_type) const; /* Get the coordinator of the X/Y-direction CB */
+    enum e_side get_cb_chan_side(t_rr_type cb_type) const; /* get the side of a Connection block */
+    enum e_side get_cb_chan_side(enum e_side ipin_side) const; /* get the side of a Connection block */
+    DeviceCoordinator get_side_block_coordinator(enum e_side side) const;
+    DeviceCoordinator get_grid_coordinator() const;
+  public: /* Verilog writer */
+    const char* gen_gsb_verilog_module_name() const;
+    const char* gen_gsb_verilog_instance_name() const;
+    const char* gen_sb_verilog_module_name() const;
+    const char* gen_sb_verilog_instance_name() const;
+    const char* gen_sb_verilog_side_module_name(enum e_side side, size_t seg_id) const;
+    const char* gen_sb_verilog_side_instance_name(enum e_side side, size_t seg_id) const;
+    const char* gen_cb_verilog_module_name(t_rr_type cb_type) const;
+    const char* gen_cb_verilog_instance_name(t_rr_type cb_type) const;
+    const char* gen_cb_verilog_routing_track_name(t_rr_type cb_type, size_t track_id) const;
+  public: /* Mutators */
+    void set(const RRGSB& src); /* get a copy from a source */
+    void set_coordinator(size_t x, size_t y);
+    void init_num_sides(size_t num_sides); /* Allocate the vectors with the given number of sides */
+    void add_chan_node(enum e_side node_side, RRChan& rr_chan, std::vector<enum PORTS> rr_chan_dir); /* Add a node to the chan_rr_node_ list and also assign its direction in chan_rr_node_direction_ */
+    void add_ipin_node(t_rr_node* node, const enum e_side node_side, const enum e_side grid_side); /* Add a node to the chan_rr_node_ list and also assign its direction in chan_rr_node_direction_ */
+    void add_opin_node(t_rr_node* node, const enum e_side node_side, const enum e_side grid_side); /* Add a node to the chan_rr_node_ list and also assign its direction in chan_rr_node_direction_ */
+    void set_sb_num_reserved_conf_bits(size_t num_reserved_conf_bits);
+    void set_sb_conf_bits_lsb(size_t conf_bits_lsb);
+    void set_sb_conf_bits_msb(size_t conf_bits_msb);
+    void set_cb_num_reserved_conf_bits(t_rr_type cb_type, size_t num_reserved_conf_bits);
+    void set_cb_conf_bits_lsb(t_rr_type cb_type, size_t conf_bits_lsb);
+    void set_cb_conf_bits_msb(t_rr_type cb_type, size_t conf_bits_msb);
+    void rotate_side_chan_node_by_direction(enum e_side side, enum e_direction chan_dir, size_t offset); /* rotate all the channel nodes by a given offset */
+    void counter_rotate_side_chan_node_by_direction(enum e_side side, enum e_direction chan_dir, size_t offset); /* rotate all the channel nodes by a given offset */
+    void rotate_side_chan_node(enum e_side side, size_t offset); /* rotate all the channel nodes by a given offset */
+    void rotate_chan_node(size_t offset); /* rotate all the channel nodes by a given offset */
+    void rotate_chan_node_in_group(size_t offset); /* rotate all the channel nodes by a given offset */
+    void rotate_side_opin_node_in_group(enum e_side side, size_t offset); /* rotate all the opin nodes by a given offset */
+    void rotate_opin_node_in_group(size_t offset); /* rotate all the opin nodes by a given offset */
+    void rotate_side(enum e_side side, size_t offset); /* rotate all the channel and opin nodes by a given offset */
+    void rotate(size_t offset); /* rotate all the channel and opin nodes by a given offset */
+    void swap_chan_node(enum e_side src_side, enum e_side des_side); /* swap the chan rr_nodes on two sides */
+    void swap_opin_node(enum e_side src_side, enum e_side des_side); /* swap the OPIN rr_nodes on two sides */
+    void swap_ipin_node(enum e_side src_side, enum e_side des_side); /* swap the IPIN rr_nodes on two sides */
+    void reverse_opin_node(enum e_side side); /* reverse the OPIN rr_nodes on two sides */
+    void reverse_ipin_node(enum e_side side); /* reverse the IPIN rr_nodes on two sides */
+  public: /* Mutators: cleaners */
+    void clear();
+    void clear_chan_nodes(enum e_side node_side); /* Clean the chan_width of a side */
+    void clear_ipin_nodes(enum e_side node_side); /* Clean the number of IPINs of a side */
+    void clear_opin_nodes(enum e_side node_side); /* Clean the number of OPINs of a side */
+    void clear_one_side(enum e_side node_side); /* Clean chan/opin/ipin nodes at one side */
+  private: /* Internal Mutators */
+    void mirror_side_chan_node_direction(enum e_side side); /* Mirror the node direction and port direction of routing track nodes on a side */
+  private: /* internal functions */
+    bool is_sb_node_mirror (const RRGSB& cand, enum e_side node_side, size_t track_id) const; 
+    bool is_cb_node_mirror (const RRGSB& cand, t_rr_type cb_type, enum e_side node_side, size_t node_id) const; 
+    size_t get_track_id_first_short_connection(enum e_side node_side) const; 
+    bool validate_num_sides() const;
+    bool validate_side(enum e_side side) const;
+    bool validate_track_id(enum e_side side, size_t track_id) const;
+    bool validate_opin_node_id(enum e_side side, size_t node_id) const;
+    bool validate_ipin_node_id(enum e_side side, size_t node_id) const;
+    bool validate_cb_type(t_rr_type cb_type) const;
+  private: /* Internal Data */
+    /* Coordinator */
+    DeviceCoordinator coordinator_;
+    /* Routing channel data */
+    std::vector<RRChan>  chan_node_;
+    std::vector< std::vector<enum PORTS> >  chan_node_direction_; 
+
+    /* Logic Block Inputs data */
+    std::vector< std::vector<t_rr_node*> >  ipin_node_;
+    std::vector< std::vector<enum e_side> > ipin_node_grid_side_;
+
+    /* Logic Block Outputs data */
+    std::vector< std::vector<t_rr_node*> >  opin_node_;
+    std::vector< std::vector<enum e_side> > opin_node_grid_side_;
+    
+    /* Configuration bits */
+    ConfPorts  sb_conf_port_;
+    ConfPorts cbx_conf_port_;
+    ConfPorts cby_conf_port_;
+};
+
+
+} /* End namespace openfpga*/
+
+#endif

From 230c7b709aac11eb0ef9589ea4f4d6de5f6d0fa5 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 9 Feb 2020 00:20:44 -0700
Subject: [PATCH 110/645] put rr_gsb data structure online

---
 openfpga/src/annotation/rr_gsb.cpp            | 1001 +++++++++++++++++
 openfpga/src/annotation/rr_gsb.h              |  275 +++--
 .../src/utils/openfpga_rr_graph_utils.cpp     |   66 ++
 openfpga/src/utils/openfpga_rr_graph_utils.h  |   28 +
 4 files changed, 1251 insertions(+), 119 deletions(-)
 create mode 100644 openfpga/src/annotation/rr_gsb.cpp
 create mode 100644 openfpga/src/utils/openfpga_rr_graph_utils.cpp
 create mode 100644 openfpga/src/utils/openfpga_rr_graph_utils.h

diff --git a/openfpga/src/annotation/rr_gsb.cpp b/openfpga/src/annotation/rr_gsb.cpp
new file mode 100644
index 000000000..54b9fa8f2
--- /dev/null
+++ b/openfpga/src/annotation/rr_gsb.cpp
@@ -0,0 +1,1001 @@
+/************************************************************************
+ * Member functions for class RRGSB
+ ***********************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_log.h"
+#include "vtr_assert.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_side_manager.h"
+
+#include "openfpga_rr_graph_utils.h"
+
+#include "rr_gsb.h"
+
+/* namespace openfpga begins */
+namespace openfpga {
+
+/************************************************************************
+ * Constructors
+ ***********************************************************************/
+/* Constructor for an empty object */
+RRGSB::RRGSB() {
+  /* Set a clean start! */
+  coordinate_.set(0, 0);
+  chan_node_direction_.clear();
+  ipin_node_.clear();
+  opin_node_.clear();
+}
+
+/* Copy constructor */
+RRGSB::RRGSB(const RRGSB& src) {
+  /* Copy coordinate */
+  this->set(src);
+  return;
+}
+
+/************************************************************************
+ * Accessors
+ ***********************************************************************/
+/* Get the number of sides of this SB */
+size_t RRGSB::get_num_sides() const {
+  VTR_ASSERT (validate_num_sides());
+  return chan_node_direction_.size();
+}
+
+/* Get the number of routing tracks on a side */
+size_t RRGSB::get_chan_width(const e_side& side) const {
+  SideManager side_manager(side);
+  VTR_ASSERT(side_manager.validate());
+  return chan_node_[side_manager.to_size_t()].get_chan_width(); 
+}
+
+/* Get the maximum number of routing tracks on all sides */
+size_t RRGSB::get_max_chan_width() const {
+  size_t max_chan_width = 0;
+  for (size_t side = 0; side < get_num_sides(); ++side) {
+    SideManager side_manager(side);
+    max_chan_width = std::max(max_chan_width, get_chan_width(side_manager.get_side()));
+  }
+  return max_chan_width;
+} 
+
+/* Get the number of routing tracks of a X/Y-direction CB */
+size_t RRGSB::get_cb_chan_width(const t_rr_type& cb_type) const {
+  return get_chan_width(get_cb_chan_side(cb_type)); 
+}
+
+/* Get the sides of ipin_nodes belong to the cb */
+std::vector<enum e_side> RRGSB::get_cb_ipin_sides(const t_rr_type& cb_type) const {
+  VTR_ASSERT (validate_cb_type(cb_type));
+  
+  std::vector<enum e_side> ipin_sides;
+
+  /* Make sure a clean start */
+  ipin_sides.clear();
+
+  switch(cb_type) {
+  case CHANX:
+    ipin_sides.push_back(TOP);
+    ipin_sides.push_back(BOTTOM);
+    break;
+  case CHANY:
+    ipin_sides.push_back(RIGHT);
+    ipin_sides.push_back(LEFT);
+    break;
+  default: 
+    VTR_LOG("Invalid type of connection block!\n");
+    exit(1);
+  }
+
+  return ipin_sides;
+}
+
+/* Get the direction of a rr_node at a given side and track_id */
+enum PORTS RRGSB::get_chan_node_direction(const e_side& side, const size_t& track_id) const {
+  SideManager side_manager(side);
+  VTR_ASSERT(side_manager.validate());
+ 
+  /* Ensure the side is valid in the context of this switch block */ 
+  VTR_ASSERT( validate_side(side) );
+
+  /* Ensure the track is valid in the context of this switch block at a specific side */ 
+  VTR_ASSERT( validate_track_id(side, track_id) );
+  
+  return chan_node_direction_[side_manager.to_size_t()][track_id]; 
+}
+
+/* Get a list of segments used in this routing channel */
+std::vector<RRSegmentId> RRGSB::get_chan_segment_ids(const e_side& side) const {
+  SideManager side_manager(side);
+  VTR_ASSERT(side_manager.validate());
+ 
+  /* Ensure the side is valid in the context of this switch block */ 
+  VTR_ASSERT( validate_side(side) );
+
+  return chan_node_[side_manager.to_size_t()].get_segment_ids(); 
+}
+
+/* Get a list of rr_nodes whose sed_id is specified */
+std::vector<RRNodeId> RRGSB::get_chan_node_ids_by_segment_ids(const e_side& side,
+                                                              const RRSegmentId& seg_id) const {
+  return chan_node_[size_t(side)].get_node_ids_by_segment_ids(seg_id);
+} 
+
+/* get a rr_node at a given side and track_id */
+RRNodeId RRGSB::get_chan_node(const e_side& side, const size_t& track_id) const {
+  SideManager side_manager(side);
+  VTR_ASSERT(side_manager.validate());
+ 
+  /* Ensure the side is valid in the context of this switch block */ 
+  VTR_ASSERT( validate_side(side) );
+
+  /* Ensure the track is valid in the context of this switch block at a specific side */ 
+  VTR_ASSERT( validate_track_id(side, track_id) );
+  
+  return chan_node_[side_manager.to_size_t()].get_node(track_id); 
+} 
+
+/* get the segment id of a channel rr_node */
+RRSegmentId RRGSB::get_chan_node_segment(const e_side& side, const size_t& track_id) const {
+  SideManager side_manager(side);
+  VTR_ASSERT(side_manager.validate());
+ 
+  /* Ensure the side is valid in the context of this switch block */ 
+  VTR_ASSERT( validate_side(side) );
+
+  /* Ensure the track is valid in the context of this switch block at a specific side */ 
+  VTR_ASSERT( validate_track_id(side, track_id) );
+  
+  return chan_node_[side_manager.to_size_t()].get_node_segment(track_id); 
+} 
+
+/* Get the number of IPIN rr_nodes on a side */
+size_t RRGSB::get_num_ipin_nodes(const e_side& side) const {
+  SideManager side_manager(side);
+  VTR_ASSERT(side_manager.validate());
+  return ipin_node_[side_manager.to_size_t()].size(); 
+} 
+
+/* get a opin_node at a given side and track_id */
+RRNodeId RRGSB::get_ipin_node(const e_side& side, const size_t& node_id) const {
+  SideManager side_manager(side);
+  VTR_ASSERT(side_manager.validate());
+ 
+  /* Ensure the side is valid in the context of this switch block */ 
+  VTR_ASSERT( validate_side(side) );
+
+  /* Ensure the track is valid in the context of this switch block at a specific side */ 
+  VTR_ASSERT( validate_ipin_node_id(side, node_id) );
+  
+  return ipin_node_[side_manager.to_size_t()][node_id]; 
+} 
+
+/* Get the number of OPIN rr_nodes on a side */
+size_t RRGSB::get_num_opin_nodes(const e_side& side) const {
+  SideManager side_manager(side);
+  VTR_ASSERT(side_manager.validate());
+  return opin_node_[side_manager.to_size_t()].size(); 
+} 
+
+/* get a opin_node at a given side and track_id */
+RRNodeId RRGSB::get_opin_node(const e_side& side, const size_t& node_id) const {
+  SideManager side_manager(side);
+  VTR_ASSERT(side_manager.validate());
+ 
+  /* Ensure the side is valid in the context of this switch block */ 
+  VTR_ASSERT( validate_side(side) );
+
+  /* Ensure the track is valid in the context of this switch block at a specific side */ 
+  VTR_ASSERT( validate_opin_node_id(side, node_id) );
+  
+  return opin_node_[side_manager.to_size_t()][node_id]; 
+} 
+
+/* Get the node index of a routing track of a connection block, return -1 if not found */
+int RRGSB::get_cb_chan_node_index(const t_rr_type& cb_type, const RRNodeId& node) const {
+  enum e_side chan_side = get_cb_chan_side(cb_type);
+  return get_chan_node_index(chan_side, node);
+}
+
+/* Get the node index in the array, return -1 if not found */
+int RRGSB::get_chan_node_index(const e_side& node_side, const RRNodeId& node) const {
+  VTR_ASSERT (validate_side(node_side));
+  return chan_node_[size_t(node_side)].get_node_track_id(node); 
+}
+
+/* Get the node index in the array, return -1 if not found */
+int RRGSB::get_node_index(const RRGraph& rr_graph,
+                          const RRNodeId& node, 
+                          const e_side& node_side, 
+                          const PORTS& node_direction) const {
+  size_t cnt;
+  int ret; 
+
+  cnt = 0;
+  ret = -1;
+
+  /* Depending on the type of rr_node, we search different arrays */
+  switch (rr_graph.node_type(node)) {
+  case CHANX:
+  case CHANY:
+    for (size_t inode = 0; inode < get_chan_width(node_side); ++inode){
+      if ((node == chan_node_[size_t(node_side)].get_node(inode))
+        /* Check if direction meets specification */
+        &&(node_direction == chan_node_direction_[size_t(node_side)][inode])) {
+        cnt++;
+        ret = inode;
+        break;
+      }
+    }
+    break;
+  case IPIN:
+    for (size_t inode = 0; inode < get_num_ipin_nodes(node_side); ++inode) {
+      if (node == ipin_node_[size_t(node_side)][inode]) {
+        cnt++;
+        ret = inode;
+        break;
+      }
+    }
+    break;
+  case OPIN:
+    for (size_t inode = 0; inode < get_num_opin_nodes(node_side); ++inode) {
+      if (node == opin_node_[size_t(node_side)][inode]) {
+        cnt++;
+        ret = inode;
+        break;
+      }
+    }
+    break;
+  default:
+    VTR_LOG("Invalid cur_rr_node type! Should be [CHANX|CHANY|IPIN|OPIN]\n");
+    exit(1);
+  }
+
+  VTR_ASSERT((0 == cnt)||(1 == cnt));
+
+  return ret; /* Return an invalid value: nonthing is found*/
+}
+
+/* Get the side of a node in this SB */
+void RRGSB::get_node_side_and_index(const RRGraph& rr_graph,
+                                    const RRNodeId& node, 
+                                    const PORTS& node_direction,
+                                    e_side& node_side, 
+                                    int& node_index) const {
+  size_t side;
+  SideManager side_manager;
+  
+  /* Count the number of existence of cur_rr_node in cur_sb_info
+   * It could happen that same cur_rr_node appears on different sides of a SB
+   * For example, a routing track go vertically across the SB.
+   * Then its corresponding rr_node appears on both TOP and BOTTOM sides of this SB. 
+   * We need to ensure that the found rr_node has the same direction as user want.
+   * By specifying the direction of rr_node, There should be only one rr_node can satisfy!
+   */
+  for (side = 0; side < get_num_sides(); ++side) {
+    side_manager.set_side(side);
+    node_index = get_node_index(rr_graph, node, side_manager.get_side(), node_direction);
+    if (-1 != node_index) {
+      break;
+    }
+  }
+
+  if (side == get_num_sides()) {
+    /* we find nothing, return NUM_SIDES, and a OPEN node (-1) */
+    node_side = NUM_SIDES;
+    VTR_ASSERT(-1 == node_index);
+    return;
+  }
+
+  node_side = side_manager.get_side();
+  VTR_ASSERT(-1 != node_index);
+
+  return;
+} 
+
+/* Check if the node exist in the opposite side of this Switch Block */
+bool RRGSB::is_sb_node_exist_opposite_side(const RRGraph& rr_graph,
+                                           const RRNodeId& node, 
+                                           const e_side& node_side) const {
+  SideManager side_manager(node_side);
+  int index;
+
+  VTR_ASSERT((CHANX == rr_graph.node_type(node)) || (CHANY == rr_graph.node_type(node)));
+
+  /* See if we can find the same src_rr_node in the opposite chan_side 
+   * if there is one, it means a shorted wire across the SB 
+   */
+  index = get_node_index(rr_graph, node, side_manager.get_opposite(), IN_PORT);
+
+  return (-1 != index);
+}
+
+/* check if the candidate CB is a mirror of the current one */
+bool RRGSB::is_cb_mirror(const RRGraph& rr_graph, const RRGSB& cand, const t_rr_type& cb_type) const { 
+  /* Check if channel width is the same */
+  if ( get_cb_chan_width(cb_type) != cand.get_cb_chan_width(cb_type) ) {
+    return false;
+  }
+
+  enum e_side chan_side = get_cb_chan_side(cb_type);
+
+  /* check the numbers/directionality of channel rr_nodes */
+  if ( false == chan_node_[size_t(chan_side)].is_mirror(rr_graph, cand.chan_node_[size_t(chan_side)]) ) {
+     return false;
+  }
+
+  /* check the equivalence of ipins */
+  std::vector<enum e_side> ipin_side = get_cb_ipin_sides(cb_type);
+  for (size_t side = 0; side < ipin_side.size(); ++side) {
+    /* Ensure we have the same number of IPINs on this side */
+    if ( get_num_ipin_nodes(ipin_side[side]) != cand.get_num_ipin_nodes(ipin_side[side]) ) {
+      return false;
+    }
+    for (size_t inode = 0; inode < get_num_ipin_nodes(ipin_side[side]); ++inode) {
+      if (false == is_cb_node_mirror(rr_graph, cand, cb_type, ipin_side[side], inode)) {
+        return false;
+      }
+    }
+  }
+
+  return true;
+}
+
+/* check if the CB exist in this GSB */
+bool RRGSB::is_cb_exist(const t_rr_type& cb_type) const {
+  /* if channel width is zero, there is no CB */
+  return (0 != get_cb_chan_width(cb_type));
+} 
+
+
+/************************************************************************
+ * Check if the node indicates a passing wire across the Switch Block part of the GSB 
+ * Therefore, we actually do the following check 
+ * Check if a track starts from this GSB or not 
+ * For INC_DIRECTION
+ * (xlow, ylow) should be same as the GSB side coordinate 
+ * For DEC_DIRECTION
+ * (xhigh, yhigh) should be same as the GSB side coordinate 
+ ***********************************************************************/
+bool RRGSB::is_sb_node_passing_wire(const RRGraph& rr_graph,
+                                    const e_side& node_side, 
+                                    const size_t& track_id) const { 
+
+  /* Get the rr_node */
+  RRNodeId track_node = get_chan_node(node_side, track_id);
+  /* Get the coordinates */
+  vtr::Point<size_t> side_coordinate = get_side_block_coordinate(node_side); 
+
+  /* Get the coordinate of where the track starts */
+  vtr::Point<size_t> track_start = get_track_rr_node_start_coordinate(rr_graph, track_node);
+
+  /* INC_DIRECTION start_track: (xlow, ylow) should be same as the GSB side coordinate */
+  /* DEC_DIRECTION start_track: (xhigh, yhigh) should be same as the GSB side coordinate */
+  if (  (track_start.x() == side_coordinate.x())
+     && (track_start.y() == side_coordinate.y()) 
+     && (OUT_PORT == get_chan_node_direction(node_side, track_id)) ) {
+    /* Double check: start track should be an OUTPUT PORT of the GSB */
+    return false; /* This is a starting point */
+  }
+
+  /* Get the coordinate of where the track ends */
+  vtr::Point<size_t> track_end = get_track_rr_node_end_coordinate(rr_graph, track_node);
+
+  /* INC_DIRECTION end_track: (xhigh, yhigh) should be same as the GSB side coordinate */ 
+  /* DEC_DIRECTION end_track: (xlow, ylow) should be same as the GSB side coordinate */ 
+  if (  (track_end.x() == side_coordinate.x())
+     && (track_end.y() == side_coordinate.y()) 
+     && (IN_PORT == get_chan_node_direction(node_side, track_id)) ) {
+    /* Double check: end track should be an INPUT PORT of the GSB */
+    return false; /* This is an ending point */
+  }
+
+  /* Reach here it means that this will be a passing wire, 
+   * we should be able to find the node on the opposite side of the GSB!
+   */
+  VTR_ASSERT (true == is_sb_node_exist_opposite_side(rr_graph, track_node, node_side));
+
+  return true;
+}
+
+/* check if the candidate SB satisfy the basic requirements on being a mirror of the current one */
+/* Idenify mirror Switch blocks 
+ * Check each two switch blocks: 
+ * Number of channel/opin/ipin rr_nodes are same 
+ * If all above are satisfied, the two switch blocks may be mirrors !
+ */
+bool RRGSB::is_sb_mirrorable(const RRGraph& rr_graph, const RRGSB& cand) const {
+  /* check the numbers of sides */
+  if (get_num_sides() != cand.get_num_sides()) {
+    return false;
+  }
+
+  /* check the numbers/directionality of channel rr_nodes */
+  for (size_t side = 0; side < get_num_sides(); ++side) {
+    SideManager side_manager(side);
+
+    /* Ensure we have the same channel width on this side */
+    if (get_chan_width(side_manager.get_side()) != cand.get_chan_width(side_manager.get_side())) {
+      return false;
+    }
+
+    if ( ((size_t(-1) == get_track_id_first_short_connection(rr_graph, side_manager.get_side())) 
+       && (size_t(-1) != cand.get_track_id_first_short_connection(rr_graph, side_manager.get_side())))
+    || ((size_t(-1) != get_track_id_first_short_connection(rr_graph, side_manager.get_side()) )
+       && ( size_t(-1) == cand.get_track_id_first_short_connection(rr_graph, side_manager.get_side()))) ) {
+      return false;
+    }
+  } 
+
+  /* check the numbers of opin_rr_nodes */
+  for (size_t side = 0; side < get_num_sides(); ++side) {
+    SideManager side_manager(side);
+
+    if (get_num_opin_nodes(side_manager.get_side()) != cand.get_num_opin_nodes(side_manager.get_side())) {
+      return false;
+    }
+  }
+
+  return true;
+}
+
+/* check if all the routing segments of a side of candidate SB is a mirror of the current one */
+bool RRGSB::is_sb_side_segment_mirror(const RRGraph& rr_graph, const RRGSB& cand, 
+                                      const e_side& side, const RRSegmentId& seg_id) const {
+  /* Create a side manager */
+  SideManager side_manager(side);
+
+  /* Make sure both Switch blocks has this side!!! */
+  VTR_ASSERT ( side_manager.to_size_t() < get_num_sides() ); 
+  VTR_ASSERT ( side_manager.to_size_t() < cand.get_num_sides() ); 
+
+  /* check the numbers/directionality of channel rr_nodes */
+  /* Ensure we have the same channel width on this side */
+  if (get_chan_width(side) != cand.get_chan_width(side)) {
+    return false;
+  }
+  for (size_t itrack = 0; itrack < get_chan_width(side); ++itrack) {
+    /* Bypass unrelated segments */
+    if (seg_id != get_chan_node_segment(side, itrack)) {
+      continue;
+    }
+    /* Check the directionality of each node */
+    if (get_chan_node_direction(side, itrack) != cand.get_chan_node_direction(side, itrack)) {
+      return false;
+    }
+    /* Check the track_id of each node
+     * ptc is not necessary, we care the connectivity!
+     */
+    /* For OUT_PORT rr_node, we need to check fan-in */
+    if (OUT_PORT != get_chan_node_direction(side, itrack)) {
+      continue; /* skip IN_PORT */
+    }
+
+    if (false == is_sb_node_mirror(rr_graph, cand, side, itrack)) {
+      return false;
+    } 
+  }
+
+  /* check the numbers of opin_rr_nodes */
+  if (get_num_opin_nodes(side) != cand.get_num_opin_nodes(side)) {
+    return false;
+  }
+
+  /* check the numbers of ipin_rr_nodes */
+  if (get_num_ipin_nodes(side) != cand.get_num_ipin_nodes(side)) {
+    return false;
+  }
+
+  return true;
+} 
+
+/* check if a side of candidate SB is a mirror of the current one */
+bool RRGSB::is_sb_side_mirror(const RRGraph& rr_graph, const RRGSB& cand, const e_side& side) const {
+
+  /* get a list of segments */
+  std::vector<RRSegmentId> seg_ids = chan_node_[size_t(side)].get_segment_ids();
+
+  for (size_t iseg = 0; iseg < seg_ids.size(); ++iseg) {
+    if (false == is_sb_side_segment_mirror(rr_graph, cand, side, seg_ids[iseg])) {
+      return false;
+    }
+  }
+
+  return true;
+}
+
+/* check if the candidate SB is a mirror of the current one */
+bool RRGSB::is_sb_mirror(const RRGraph& rr_graph, const RRGSB& cand) const {
+  /* check the numbers of sides */
+  if (get_num_sides() != cand.get_num_sides()) {
+    return false;
+  }
+
+  /* check the numbers/directionality of channel rr_nodes */
+  for (size_t side = 0; side < get_num_sides(); ++side) {
+    SideManager side_manager(side);
+    if (false == is_sb_side_mirror(rr_graph, cand, side_manager.get_side())) {
+      return false;
+    } 
+  }
+
+  return true;
+}
+
+/* Public Accessors: Cooridinator conversion */
+
+/* get the x coordinate of this GSB */
+size_t RRGSB::get_x() const {
+  return coordinate_.x();
+} 
+
+/* get the y coordinate of this GSB */
+size_t RRGSB::get_y() const { 
+  return coordinate_.y();
+}
+
+
+/* get the x coordinate of this switch block */
+size_t RRGSB::get_sb_x() const {
+  return coordinate_.x();
+} 
+
+/* get the y coordinate of this switch block */
+size_t RRGSB::get_sb_y() const { 
+  return coordinate_.y();
+}
+
+/* Get the number of sides of this SB */
+vtr::Point<size_t> RRGSB::get_sb_coordinate() const {
+  return coordinate_;
+} 
+
+/* get the x coordinate of this X/Y-direction block */
+size_t RRGSB::get_cb_x(const t_rr_type& cb_type) const {
+  VTR_ASSERT (validate_cb_type(cb_type));
+  switch(cb_type) {
+  case CHANX:
+    return get_side_block_coordinate(LEFT).x();
+  case CHANY:
+    return get_side_block_coordinate(TOP).x();
+  default: 
+    VTR_LOG("Invalid type of connection block!\n");
+    exit(1);
+  }
+} 
+
+/* get the y coordinate of this X/Y-direction block */
+size_t RRGSB::get_cb_y(const t_rr_type& cb_type) const { 
+  VTR_ASSERT (validate_cb_type(cb_type));
+  switch(cb_type) {
+  case CHANX:
+    return get_side_block_coordinate(LEFT).y();
+  case CHANY:
+    return get_side_block_coordinate(TOP).y();
+  default: 
+    VTR_LOG("Invalid type of connection block!\n");
+    exit(1);
+  }
+}
+
+/* Get the coordinate of the X/Y-direction CB */
+vtr::Point<size_t> RRGSB::get_cb_coordinate(const t_rr_type& cb_type) const {
+  VTR_ASSERT (validate_cb_type(cb_type));
+  switch(cb_type) {
+  case CHANX:
+    return get_side_block_coordinate(LEFT);
+  case CHANY:
+    return get_side_block_coordinate(TOP);
+  default: 
+    VTR_LOG("Invalid type of connection block!\n");
+    exit(1);
+  }
+} 
+
+e_side RRGSB::get_cb_chan_side(const t_rr_type& cb_type) const {
+  VTR_ASSERT (validate_cb_type(cb_type));
+  switch(cb_type) {
+  case CHANX:
+    return LEFT;
+  case CHANY:
+    return TOP;
+  default: 
+    VTR_LOG("Invalid type of connection block!\n");
+    exit(1);
+  }
+}
+
+/* Get the side of routing channel in the GSB according to the side of IPIN */
+e_side RRGSB::get_cb_chan_side(const e_side& ipin_side) const {
+  switch(ipin_side) {
+  case TOP:
+    return LEFT;
+  case RIGHT:
+    return TOP;
+  case BOTTOM:
+    return LEFT;
+  case LEFT:
+    return TOP;
+  default: 
+    VTR_LOG("Invalid type of ipin_side!\n");
+    exit(1);
+  }
+}
+
+vtr::Point<size_t> RRGSB::get_side_block_coordinate(const e_side& side) const {
+  SideManager side_manager(side); 
+  VTR_ASSERT(side_manager.validate());
+  vtr::Point<size_t> ret(get_sb_x(), get_sb_y());
+
+  switch (side_manager.get_side()) {
+  case TOP:
+    /* (0 == side) */
+    /* 1. Channel Y [x][y+1] inputs */
+    ret.set_y(ret.y() + 1);
+    break;
+  case RIGHT:
+    /* 1 == side */
+    /* 2. Channel X [x+1][y] inputs */
+    ret.set_x(ret.x() + 1);
+    break;
+  case BOTTOM:
+    /* 2 == side */
+    /* 3. Channel Y [x][y] inputs */
+    break;
+  case LEFT:
+    /* 3 == side */
+    /* 4. Channel X [x][y] inputs */
+    break;
+  default:
+    VTR_LOG(" Invalid side!\n");
+    exit(1);
+  }
+
+  return ret;
+}
+
+vtr::Point<size_t> RRGSB::get_grid_coordinate() const {
+  vtr::Point<size_t> ret(get_sb_x(), get_sb_y());
+  ret.set_y(ret.y() + 1);
+
+  return ret;
+}
+/* Public mutators */
+
+/* get a copy from a source */
+void RRGSB::set(const RRGSB& src) { 
+  /* Copy coordinate */
+  this->set_coordinate(src.get_sb_coordinate().x(), src.get_sb_coordinate().y());
+
+  /* Initialize sides */ 
+  this->init_num_sides(src.get_num_sides());
+
+  /* Copy vectors */
+  for (size_t side = 0; side < src.get_num_sides(); ++side) {
+    SideManager side_manager(side);
+    /* Copy chan_nodes */
+    /* skip if there is no channel width */
+    if ( 0 < src.get_chan_width(side_manager.get_side()) ) {
+      this->chan_node_[side_manager.get_side()].set(src.chan_node_[side_manager.get_side()]);
+      /* Copy chan_node_direction_*/
+      this->chan_node_direction_[side_manager.get_side()].clear();
+      for (size_t inode = 0; inode < src.get_chan_width(side_manager.get_side()); ++inode) {
+        this->chan_node_direction_[side_manager.get_side()].push_back(src.get_chan_node_direction(side_manager.get_side(), inode));
+      }
+    }
+
+    /* Copy opin_node and opin_node_grid_side_ */
+    this->opin_node_[side_manager.get_side()].clear();
+    for (size_t inode = 0; inode < src.get_num_opin_nodes(side_manager.get_side()); ++inode) {
+      this->opin_node_[side_manager.get_side()].push_back(src.get_opin_node(side_manager.get_side(), inode));
+    }
+
+    /* Copy ipin_node and ipin_node_grid_side_ */
+    this->ipin_node_[side_manager.get_side()].clear();
+    for (size_t inode = 0; inode < src.get_num_ipin_nodes(side_manager.get_side()); ++inode) {
+      this->ipin_node_[side_manager.get_side()].push_back(src.get_ipin_node(side_manager.get_side(), inode));
+    }
+  }
+}
+
+/* Set the coordinate (x,y) for the switch block */
+void RRGSB::set_coordinate(const size_t& x, const size_t& y) {
+  coordinate_.set(x, y);
+}
+
+/* Allocate the vectors with the given number of sides */
+void RRGSB::init_num_sides(const size_t& num_sides) {
+  /* Initialize the vectors */
+  chan_node_.resize(num_sides);
+  chan_node_direction_.resize(num_sides);
+  ipin_node_.resize(num_sides);
+  opin_node_.resize(num_sides);
+}
+
+/* Add a node to the chan_node_ list and also assign its direction in chan_node_direction_ */
+void RRGSB::add_chan_node(const e_side& node_side, RRChan& rr_chan, const std::vector<enum PORTS>& rr_chan_dir) {
+  /* Validate: 1. side is valid, the type of node is valid */
+  VTR_ASSERT(validate_side(node_side));
+
+  /* fill the dedicated element in the vector */
+  chan_node_[size_t(node_side)].set(rr_chan);
+  chan_node_direction_[size_t(node_side)].resize(rr_chan_dir.size());
+  for (size_t inode = 0; inode < rr_chan_dir.size(); ++inode) {
+    chan_node_direction_[size_t(node_side)][inode] = rr_chan_dir[inode];
+  }
+} 
+
+/* Add a node to the chan_node_ list and also assign its direction in chan_node_direction_ */
+void RRGSB::add_ipin_node(const RRNodeId& node, const e_side& node_side) {
+  VTR_ASSERT(validate_side(node_side));
+  /* push pack the dedicated element in the vector */
+  ipin_node_[size_t(node_side)].push_back(node);
+}
+
+/* Add a node to the chan_node_ list and also assign its direction in chan_node_direction_ */
+void RRGSB::add_opin_node(const RRNodeId& node, const e_side& node_side) {
+  VTR_ASSERT(validate_side(node_side));
+  /* push pack the dedicated element in the vector */
+  opin_node_[size_t(node_side)].push_back(node);
+} 
+
+/* Reset the RRGSB to pristine state */
+void RRGSB::clear() {
+  /* Clean all the vectors */
+  VTR_ASSERT(validate_num_sides());
+  /* Clear the inner vector of each matrix */
+  for (size_t side = 0; side < get_num_sides(); ++side) {
+    chan_node_direction_[side].clear();
+    chan_node_[side].clear();
+    ipin_node_[side].clear();
+    opin_node_[side].clear();
+  }  
+  chan_node_direction_.clear();
+  chan_node_.clear();
+  ipin_node_.clear();
+  opin_node_.clear();
+}
+
+/* Clean the chan_width of a side */
+void RRGSB::clear_chan_nodes(const e_side& node_side) {
+  VTR_ASSERT(validate_side(node_side));
+  
+  chan_node_[size_t(node_side)].clear();
+  chan_node_direction_[size_t(node_side)].clear();
+} 
+
+/* Clean the number of IPINs of a side */
+void RRGSB::clear_ipin_nodes(const e_side& node_side) {
+  VTR_ASSERT(validate_side(node_side));
+  
+  ipin_node_[size_t(node_side)].clear();
+} 
+
+/* Clean the number of OPINs of a side */
+void RRGSB::clear_opin_nodes(const e_side& node_side) {
+  VTR_ASSERT(validate_side(node_side));
+  
+  opin_node_[size_t(node_side)].clear();
+}
+
+/* Clean chan/opin/ipin nodes at one side */
+void RRGSB::clear_one_side(const e_side& node_side) {
+  clear_chan_nodes(node_side);
+  clear_ipin_nodes(node_side);
+  clear_opin_nodes(node_side);
+} 
+
+/* Internal functions for validation */
+
+/* check if two rr_nodes have a similar set of drive_rr_nodes 
+ * for each drive_rr_node:
+ * 1. CHANX or CHANY: should have the same side and index
+ * 2. OPIN or IPIN: should have the same side and index
+ * 3. each drive_rr_switch should be the same 
+ */
+bool RRGSB::is_sb_node_mirror(const RRGraph& rr_graph,
+                              const RRGSB& cand, 
+                              const e_side& node_side, 
+                              const size_t& track_id) const {
+  /* Ensure rr_nodes are either the output of short-connection or multiplexer  */
+  RRNodeId node = this->get_chan_node(node_side, track_id);
+  RRNodeId cand_node = cand.get_chan_node(node_side, track_id);
+  bool is_short_conkt = this->is_sb_node_passing_wire(rr_graph, node_side, track_id);
+
+  if (is_short_conkt != cand.is_sb_node_passing_wire(rr_graph, node_side, track_id)) {
+    return false;
+  }
+
+  if (true == is_short_conkt) {
+    /* Since, both are pass wires, 
+     * The two node should be equivalent    
+     * we can return here
+     */
+    return true;
+  }
+
+  /* For non-passing wires, check driving rr_nodes */
+  if (rr_graph.node_in_edges(node).size() != rr_graph.node_in_edges(cand_node).size()) {
+    return false;
+  }
+
+  std::vector<RREdgeId> node_in_edges;
+  for (const RREdgeId& edge : rr_graph.node_in_edges(node)) {
+    node_in_edges.push_back(edge);
+  }
+
+  std::vector<RREdgeId> cand_node_in_edges;
+  for (const RREdgeId& edge : rr_graph.node_in_edges(cand_node)) {
+    cand_node_in_edges.push_back(edge);
+  }
+  VTR_ASSERT(node_in_edges.size() == cand_node_in_edges.size());
+
+  for (size_t iedge = 0; iedge < node_in_edges.size(); ++iedge) {
+    RREdgeId src_edge = node_in_edges[iedge];
+    RREdgeId src_cand_edge = cand_node_in_edges[iedge];
+    RRNodeId src_node = rr_graph.edge_src_node(src_edge);
+    RRNodeId src_cand_node = rr_graph.edge_src_node(src_cand_edge);
+    /* node type should be the same  */
+    if (rr_graph.node_type(src_node) != rr_graph.node_type(cand_node)) {
+      return false;
+    }
+    /* switch type should be the same  */
+    if (rr_graph.edge_switch(src_edge) != rr_graph.edge_switch(src_cand_edge)) {
+      return false;
+    }
+    int src_node_id, des_node_id;
+    enum e_side src_node_side, des_node_side; 
+    this->get_node_side_and_index(rr_graph, src_node, OUT_PORT, src_node_side, src_node_id);
+     cand.get_node_side_and_index(rr_graph, src_cand_node, OUT_PORT, des_node_side, des_node_id);
+    if (src_node_id != des_node_id) {
+      return false;
+    } 
+    if (src_node_side != des_node_side) {
+      return false;
+    } 
+  }
+
+  return true;
+} 
+
+/* check if two ipin_nodes have a similar set of drive_rr_nodes 
+ * for each drive_rr_node:
+ * 1. CHANX or CHANY: should have the same side and index
+ * 2. each drive_rr_switch should be the same 
+ */
+bool RRGSB::is_cb_node_mirror(const RRGraph& rr_graph,
+                              const RRGSB& cand, 
+                              const t_rr_type& cb_type,
+                              const e_side& node_side, 
+                              const size_t& node_id) const {
+  /* Ensure rr_nodes are either the output of short-connection or multiplexer  */
+  RRNodeId node = this->get_ipin_node(node_side, node_id);
+  RRNodeId cand_node = cand.get_ipin_node(node_side, node_id);
+
+  if ( rr_graph.node_in_edges(node).size() != rr_graph.node_in_edges(cand_node).size() ) {
+    return false;
+  }
+
+  std::vector<RREdgeId> node_in_edges;
+  for (const RREdgeId& edge : rr_graph.node_in_edges(node)) {
+    node_in_edges.push_back(edge);
+  }
+
+  std::vector<RREdgeId> cand_node_in_edges;
+  for (const RREdgeId& edge : rr_graph.node_in_edges(cand_node)) {
+    cand_node_in_edges.push_back(edge);
+  }
+  VTR_ASSERT(node_in_edges.size() == cand_node_in_edges.size());
+
+  for (size_t iedge = 0; iedge < node_in_edges.size(); ++iedge) {
+    RREdgeId src_edge = node_in_edges[iedge];
+    RREdgeId src_cand_edge = cand_node_in_edges[iedge];
+    RRNodeId src_node = rr_graph.edge_src_node(src_edge);
+    RRNodeId src_cand_node = rr_graph.edge_src_node(src_cand_edge);
+    /* node type should be the same  */
+    if (rr_graph.node_type(src_node) != rr_graph.node_type(src_cand_node)) {
+      return false;
+    }
+    /* switch type should be the same  */
+    if (rr_graph.edge_switch(src_edge)!= rr_graph.edge_switch(src_cand_edge)) {
+      return false;
+    }
+
+    int src_node_id, des_node_id;
+    enum e_side src_node_side, des_node_side; 
+    enum e_side chan_side = get_cb_chan_side(cb_type);
+    switch (rr_graph.node_type(src_node)) {
+    case CHANX:
+    case CHANY:
+      /* if the drive rr_nodes are routing tracks, find index  */
+      src_node_id = this->get_chan_node_index(chan_side, src_node);
+      des_node_id =  cand.get_chan_node_index(chan_side, src_cand_node);
+      break;
+    case OPIN:
+      this->get_node_side_and_index(rr_graph, src_node, OUT_PORT, src_node_side, src_node_id);
+       cand.get_node_side_and_index(rr_graph, src_cand_node, OUT_PORT, des_node_side, des_node_id);
+      if (src_node_side != des_node_side) {
+        return false;
+      } 
+      break;
+    default:
+      VTR_LOG("Invalid type of drive_rr_nodes for ipin_node!\n");
+      exit(1);
+    }
+    if (src_node_id != des_node_id) {
+      return false;
+    } 
+  }
+
+  return true;
+} 
+
+size_t RRGSB::get_track_id_first_short_connection(const RRGraph& rr_graph, const e_side& node_side) const {
+  VTR_ASSERT(validate_side(node_side));
+
+  /* Walk through chan_nodes and find the first short connection */
+  for (size_t inode = 0; inode < get_chan_width(node_side); ++inode) {
+    if (true == is_sb_node_passing_wire(rr_graph, node_side, inode)) {
+      return inode; 
+    }
+  }
+
+  return size_t(-1);
+}
+
+/* Validate if the number of sides are consistent among internal data arrays ! */
+bool RRGSB::validate_num_sides() const {
+  size_t num_sides = chan_node_direction_.size();
+
+  if ( num_sides != chan_node_.size() ) {
+    return false;
+  }
+
+  if ( num_sides != ipin_node_.size() ) {
+    return false;
+  }
+
+  if ( num_sides != opin_node_.size() ) {
+    return false;
+  }
+
+  return true; 
+}
+
+/* Check if the side valid in the context: does the switch block have the side? */
+bool RRGSB::validate_side(const e_side& side) const {
+  return (size_t(side) < get_num_sides());
+}
+
+/* Check the track_id is valid for chan_node_ and chan_node_direction_ */
+bool RRGSB::validate_track_id(const e_side& side, const size_t& track_id) const {
+  if (false == validate_side(side)) {
+    return false;
+  } 
+  
+  return ( ( track_id < chan_node_[size_t(side)].get_chan_width()) 
+        && ( track_id < chan_node_direction_[size_t(side)].size()) );
+}
+
+/* Check the opin_node_id is valid for opin_node_ and opin_node_grid_side_ */
+bool RRGSB::validate_opin_node_id(const e_side& side, const size_t& node_id) const {
+  if (false == validate_side(side)) {
+    return false;
+  } 
+  return (node_id < opin_node_[size_t(side)].size());
+}
+
+/* Check the ipin_node_id is valid for opin_node_ and opin_node_grid_side_ */
+bool RRGSB::validate_ipin_node_id(const e_side& side, const size_t& node_id) const {
+  if (false == validate_side(side)) {
+    return false;
+  } 
+  return (node_id < ipin_node_[size_t(side)].size());
+}
+
+bool RRGSB::validate_cb_type(const t_rr_type& cb_type) const {
+  return ( (CHANX == cb_type) || (CHANY == cb_type) );
+}
+
+} /* End namespace openfpga*/
diff --git a/openfpga/src/annotation/rr_gsb.h b/openfpga/src/annotation/rr_gsb.h
index 7febeffc7..4f3af9552 100644
--- a/openfpga/src/annotation/rr_gsb.h
+++ b/openfpga/src/annotation/rr_gsb.h
@@ -4,6 +4,9 @@
 /********************************************************************
  * Include header files required by the data structure definition
  *******************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_geometry.h"
+
 #include "rr_chan.h"
 
 /* Begin namespace openfpga */
@@ -15,7 +18,6 @@ namespace openfpga {
  * 1. A switch block
  * 2. A X-direction Connection block locates at the left side of the switch block
  * 2. A Y-direction Connection block locates at the top side of the switch block
- * This is a collection of rr_nodes, which may be replaced with RRNodeId in new RRGraph 
  *
  *                               +---------------------------------+
  *                               |          Y-direction CB         |
@@ -53,141 +55,176 @@ class RRGSB {
     RRGSB(const RRGSB&);/* Copy constructor */
     RRGSB();/* Default constructor */
   public: /* Accessors */
-    size_t get_num_sides() const; /* Get the number of sides of this SB */
-    size_t get_chan_width(enum e_side side) const; /* Get the number of routing tracks on a side */
-    size_t get_cb_chan_width(t_rr_type cb_type) const; /* Get the number of routing tracks of a X/Y-direction CB */
-    std::vector<enum e_side> get_cb_ipin_sides(t_rr_type cb_type) const; /* Get the sides of CB ipins in the array */
-    size_t get_max_chan_width() const; /* Get the maximum number of routing tracks on all sides */
-    enum PORTS get_chan_node_direction(enum e_side side, size_t track_id) const; /* Get the direction of a rr_node at a given side and track_id */
-    RRChan get_chan(enum e_side side) const; /* get a rr_node at a given side and track_id */
-    std::vector<size_t> get_chan_segment_ids(enum e_side side) const; /* Get a list of segments used in this routing channel */
-    std::vector<size_t> get_chan_node_ids_by_segment_ids(enum e_side side, size_t seg_id) const; /* Get a list of segments used in this routing channel */
-    t_rr_node* get_chan_node(enum e_side side, size_t track_id) const; /* get a rr_node at a given side and track_id */
-    size_t get_chan_node_segment(enum e_side side, size_t track_id) const; /* get the segment id of a channel rr_node */
-    size_t get_num_ipin_nodes(enum e_side side) const; /* Get the number of IPIN rr_nodes on a side */
-    t_rr_node* get_ipin_node(enum e_side side, size_t node_id) const; /* get a rr_node at a given side and track_id */
-    enum e_side get_ipin_node_grid_side(enum e_side side, size_t node_id) const; /* get a rr_node at a given side and track_id */
-    enum e_side get_ipin_node_grid_side(t_rr_node* ipin_node) const; /* get a rr_node at a given side and track_id */
-    size_t get_num_opin_nodes(enum e_side side) const; /* Get the number of OPIN rr_nodes on a side */
-    t_rr_node* get_opin_node(enum e_side side, size_t node_id) const; /* get a rr_node at a given side and track_id */
-    enum e_side get_opin_node_grid_side(enum e_side side, size_t node_id) const; /* get a rr_node at a given side and track_id */
-    enum e_side get_opin_node_grid_side(t_rr_node* opin_node) const; /* get a rr_node at a given side and track_id */
-    int get_cb_chan_node_index(t_rr_type cb_type, t_rr_node* node) const;
-    int get_chan_node_index(enum e_side node_side, t_rr_node* node) const;
-    int get_node_index(t_rr_node* node, enum e_side node_side, enum PORTS node_direction) const; /* Get the node index in the array, return -1 if not found */
-    void get_node_side_and_index(t_rr_node* node,  enum PORTS node_direction, enum e_side* node_side, int* node_index) const; /* Given a rr_node, try to find its side and index in the Switch block */
-    bool is_sb_node_exist_opposite_side(t_rr_node* node, enum e_side node_side) const; /* Check if the node exist in the opposite side of this Switch Block */
-  public: /* Accessors: get information about configuration ports */
-    size_t get_sb_num_reserved_conf_bits() const;
-    size_t get_sb_reserved_conf_bits_lsb() const;
-    size_t get_sb_reserved_conf_bits_msb() const;
-    size_t get_sb_num_conf_bits() const;
-    size_t get_sb_conf_bits_lsb() const;
-    size_t get_sb_conf_bits_msb() const;
-    size_t get_cb_num_reserved_conf_bits(t_rr_type cb_type) const;
-    size_t get_cb_reserved_conf_bits_lsb(t_rr_type cb_type) const;
-    size_t get_cb_reserved_conf_bits_msb(t_rr_type cb_type) const;
-    size_t get_cb_num_conf_bits(t_rr_type cb_type) const;
-    size_t get_cb_conf_bits_lsb(t_rr_type cb_type) const;
-    size_t get_cb_conf_bits_msb(t_rr_type cb_type) const;
-    bool is_sb_node_passing_wire(const enum e_side node_side, const size_t track_id) const; /* Check if the node imply a short connection inside the SB, which happens to long wires across a FPGA fabric */
-    bool is_sb_side_mirror(const RRGSB& cand, enum e_side side) const; /* check if a side of candidate SB is a mirror of the current one */
-    bool is_sb_side_segment_mirror(const RRGSB& cand, enum e_side side, size_t seg_id) const; /* check if all the routing segments of a side of candidate SB is a mirror of the current one */
-    bool is_sb_mirror(const RRGSB& cand) const; /* check if the candidate SB is a mirror of the current one */
-    bool is_sb_mirrorable(const RRGSB& cand) const; /* check if the candidate SB satisfy the basic requirements on being a mirror of the current one */
-    bool is_cb_mirror(const RRGSB& cand, t_rr_type cb_type) const; /* check if the candidate SB is a mirror of the current one */
-    bool is_cb_exist(t_rr_type cb_type) const; /* check if the candidate SB is a mirror of the current one */
-    size_t get_hint_rotate_offset(const RRGSB& cand) const; /* Determine an initial offset in rotating the candidate Switch Block to find a mirror matching*/
+    /* Get the number of sides of this SB */
+    size_t get_num_sides() const; 
+
+    /* Get the number of routing tracks on a side */
+    size_t get_chan_width(const e_side& side) const; 
+
+    /* Get the maximum number of routing tracks on all sides */
+    size_t get_max_chan_width() const; 
+
+    /* Get the number of routing tracks of a X/Y-direction CB */
+    size_t get_cb_chan_width(const t_rr_type& cb_type) const; 
+
+    /* Get the sides of CB ipins in the array */
+    std::vector<enum e_side> get_cb_ipin_sides(const t_rr_type& cb_type) const; 
+
+    /* Get the direction of a rr_node at a given side and track_id */
+    enum PORTS get_chan_node_direction(const e_side& side, const size_t& track_id) const; 
+
+    /* Get a list of segments used in this routing channel */
+    std::vector<RRSegmentId> get_chan_segment_ids(const e_side& side) const; 
+
+    /* Get a list of segments used in this routing channel */
+    std::vector<RRNodeId> get_chan_node_ids_by_segment_ids(const e_side& side,
+                                                           const RRSegmentId& seg_id) const; 
+
+    /* get a rr_node at a given side and track_id */
+    RRNodeId get_chan_node(const e_side& side, const size_t& track_id) const; 
+
+    /* get the segment id of a channel rr_node */
+    RRSegmentId get_chan_node_segment(const e_side& side, const size_t& track_id) const; 
+
+    /* Get the number of IPIN rr_nodes on a side */
+    size_t get_num_ipin_nodes(const e_side& side) const; 
+
+    /* get a rr_node at a given side and track_id */
+    RRNodeId get_ipin_node(const e_side& side, const size_t& node_id) const;
+
+    /* Get the number of OPIN rr_nodes on a side */
+    size_t get_num_opin_nodes(const e_side& side) const; 
+
+    /* get a rr_node at a given side and track_id */
+    RRNodeId get_opin_node(const e_side& side, const size_t& node_id) const; 
+
+    int get_cb_chan_node_index(const t_rr_type& cb_type, const RRNodeId& node) const;
+
+    int get_chan_node_index(const e_side& node_side, const RRNodeId& node) const;
+
+    /* Get the node index in the array, return -1 if not found */
+    int get_node_index(const RRGraph& rr_graph, const RRNodeId& node, const e_side& node_side, const PORTS& node_direction) const; 
+
+    /* Given a rr_node, try to find its side and index in the Switch block */
+    void get_node_side_and_index(const RRGraph& rr_graph, const RRNodeId& node, const PORTS& node_direction, e_side& node_side, int& node_index) const; 
+
+    /* Check if the node exist in the opposite side of this Switch Block */
+    bool is_sb_node_exist_opposite_side(const RRGraph& rr_graph, const RRNodeId& node, const e_side& node_side) const;
+  public: /* Accessors: to identify mirrors */
+    /* check if the candidate SB is a mirror of the current one */
+    bool is_cb_mirror(const RRGraph& rr_graph, const RRGSB& cand, const t_rr_type& cb_type) const; 
+
+    /* check if the candidate SB is a mirror of the current one */
+    bool is_cb_exist(const t_rr_type& cb_type) const;
+
+    /* Check if the node imply a short connection inside the SB, which happens to long wires across a FPGA fabric */
+    bool is_sb_node_passing_wire(const RRGraph& rr_graph, const e_side& node_side, const size_t& track_id) const; 
+
+    /* check if the candidate SB satisfy the basic requirements 
+     * on being a mirror of the current one 
+     */
+    bool is_sb_mirrorable(const RRGraph& rr_graph, const RRGSB& cand) const; 
+
+    /* check if all the routing segments of a side of candidate SB is a mirror of the current one */
+    bool is_sb_side_segment_mirror(const RRGraph& rr_graph, const RRGSB& cand, 
+                                   const e_side& side, const RRSegmentId& seg_id) const;
+
+    /* check if a side of candidate SB is a mirror of the current one 
+     * Check the specified side of two switch blocks: 
+     * 1. Number of channel/opin/ipin rr_nodes are same 
+     * For channel rr_nodes
+     * 2. check if their track_ids (ptc_num) are same
+     * 3. Check if the switches (ids) are same
+     * For opin/ipin rr_nodes, 
+     * 4. check if their parent type_descriptors same, 
+     * 5. check if pin class id and pin id are same 
+     * If all above are satisfied, the side of the two switch blocks are mirrors!
+     */
+    bool is_sb_side_mirror(const RRGraph& rr_graph, const RRGSB& cand, const e_side& side) const; 
+
+    /* check if the candidate SB is a mirror of the current one 
+     * Idenify mirror Switch blocks 
+     * Check each two switch blocks: 
+     * 1. Number of channel/opin/ipin rr_nodes are same 
+     * For channel rr_nodes
+     * 2. check if their track_ids (ptc_num) are same
+     * 3. Check if the switches (ids) are same
+     * For opin/ipin rr_nodes, 
+     * 4. check if their parent type_descriptors same, 
+     * 5. check if pin class id and pin id are same 
+     * If all above are satisfied, the two switch blocks are mirrors!
+     */
+    bool is_sb_mirror(const RRGraph& rr_graph, const RRGSB& cand) const; 
+
   public: /* Cooridinator conversion and output  */
-    size_t get_x() const; /* get the x coordinator of this switch block */
-    size_t get_y() const; /* get the y coordinator of this switch block */
-    size_t get_sb_x() const; /* get the x coordinator of this switch block */
-    size_t get_sb_y() const; /* get the y coordinator of this switch block */
-    DeviceCoordinator get_sb_coordinator() const; /* Get the coordinator of the SB */
-    size_t get_cb_x(t_rr_type cb_type) const; /* get the x coordinator of this X/Y-direction block */
-    size_t get_cb_y(t_rr_type cb_type) const; /* get the y coordinator of this X/Y-direction block */
-    DeviceCoordinator get_cb_coordinator(t_rr_type cb_type) const; /* Get the coordinator of the X/Y-direction CB */
-    enum e_side get_cb_chan_side(t_rr_type cb_type) const; /* get the side of a Connection block */
-    enum e_side get_cb_chan_side(enum e_side ipin_side) const; /* get the side of a Connection block */
-    DeviceCoordinator get_side_block_coordinator(enum e_side side) const;
-    DeviceCoordinator get_grid_coordinator() const;
-  public: /* Verilog writer */
-    const char* gen_gsb_verilog_module_name() const;
-    const char* gen_gsb_verilog_instance_name() const;
-    const char* gen_sb_verilog_module_name() const;
-    const char* gen_sb_verilog_instance_name() const;
-    const char* gen_sb_verilog_side_module_name(enum e_side side, size_t seg_id) const;
-    const char* gen_sb_verilog_side_instance_name(enum e_side side, size_t seg_id) const;
-    const char* gen_cb_verilog_module_name(t_rr_type cb_type) const;
-    const char* gen_cb_verilog_instance_name(t_rr_type cb_type) const;
-    const char* gen_cb_verilog_routing_track_name(t_rr_type cb_type, size_t track_id) const;
+    size_t get_x() const; /* get the x coordinate of this switch block */
+    size_t get_y() const; /* get the y coordinate of this switch block */
+    size_t get_sb_x() const; /* get the x coordinate of this switch block */
+    size_t get_sb_y() const; /* get the y coordinate of this switch block */
+    vtr::Point<size_t> get_sb_coordinate() const; /* Get the coordinate of the SB */
+    size_t get_cb_x(const t_rr_type& cb_type) const; /* get the x coordinate of this X/Y-direction block */
+    size_t get_cb_y(const t_rr_type& cb_type) const; /* get the y coordinate of this X/Y-direction block */
+    vtr::Point<size_t> get_cb_coordinate(const t_rr_type& cb_type) const; /* Get the coordinate of the X/Y-direction CB */
+    e_side get_cb_chan_side(const t_rr_type& cb_type) const; /* get the side of a Connection block */
+    e_side get_cb_chan_side(const e_side& ipin_side) const; /* get the side of a Connection block */
+    vtr::Point<size_t> get_side_block_coordinate(const e_side& side) const;
+    vtr::Point<size_t> get_grid_coordinate() const;
   public: /* Mutators */
     void set(const RRGSB& src); /* get a copy from a source */
-    void set_coordinator(size_t x, size_t y);
-    void init_num_sides(size_t num_sides); /* Allocate the vectors with the given number of sides */
-    void add_chan_node(enum e_side node_side, RRChan& rr_chan, std::vector<enum PORTS> rr_chan_dir); /* Add a node to the chan_rr_node_ list and also assign its direction in chan_rr_node_direction_ */
-    void add_ipin_node(t_rr_node* node, const enum e_side node_side, const enum e_side grid_side); /* Add a node to the chan_rr_node_ list and also assign its direction in chan_rr_node_direction_ */
-    void add_opin_node(t_rr_node* node, const enum e_side node_side, const enum e_side grid_side); /* Add a node to the chan_rr_node_ list and also assign its direction in chan_rr_node_direction_ */
-    void set_sb_num_reserved_conf_bits(size_t num_reserved_conf_bits);
-    void set_sb_conf_bits_lsb(size_t conf_bits_lsb);
-    void set_sb_conf_bits_msb(size_t conf_bits_msb);
-    void set_cb_num_reserved_conf_bits(t_rr_type cb_type, size_t num_reserved_conf_bits);
-    void set_cb_conf_bits_lsb(t_rr_type cb_type, size_t conf_bits_lsb);
-    void set_cb_conf_bits_msb(t_rr_type cb_type, size_t conf_bits_msb);
-    void rotate_side_chan_node_by_direction(enum e_side side, enum e_direction chan_dir, size_t offset); /* rotate all the channel nodes by a given offset */
-    void counter_rotate_side_chan_node_by_direction(enum e_side side, enum e_direction chan_dir, size_t offset); /* rotate all the channel nodes by a given offset */
-    void rotate_side_chan_node(enum e_side side, size_t offset); /* rotate all the channel nodes by a given offset */
-    void rotate_chan_node(size_t offset); /* rotate all the channel nodes by a given offset */
-    void rotate_chan_node_in_group(size_t offset); /* rotate all the channel nodes by a given offset */
-    void rotate_side_opin_node_in_group(enum e_side side, size_t offset); /* rotate all the opin nodes by a given offset */
-    void rotate_opin_node_in_group(size_t offset); /* rotate all the opin nodes by a given offset */
-    void rotate_side(enum e_side side, size_t offset); /* rotate all the channel and opin nodes by a given offset */
-    void rotate(size_t offset); /* rotate all the channel and opin nodes by a given offset */
-    void swap_chan_node(enum e_side src_side, enum e_side des_side); /* swap the chan rr_nodes on two sides */
-    void swap_opin_node(enum e_side src_side, enum e_side des_side); /* swap the OPIN rr_nodes on two sides */
-    void swap_ipin_node(enum e_side src_side, enum e_side des_side); /* swap the IPIN rr_nodes on two sides */
-    void reverse_opin_node(enum e_side side); /* reverse the OPIN rr_nodes on two sides */
-    void reverse_ipin_node(enum e_side side); /* reverse the IPIN rr_nodes on two sides */
+    void set_coordinate(const size_t& x, const size_t& y);
+    void init_num_sides(const size_t& num_sides); /* Allocate the vectors with the given number of sides */
+    void add_chan_node(const e_side& node_side, RRChan& rr_chan, const std::vector<enum PORTS>& rr_chan_dir); /* Add a node to the chan_rr_node_ list and also assign its direction in chan_rr_node_direction_ */
+    void add_ipin_node(const RRNodeId& node, const e_side& node_side); /* Add a node to the chan_rr_node_ list and also assign its direction in chan_rr_node_direction_ */
+    void add_opin_node(const RRNodeId& node, const e_side& node_side); /* Add a node to the chan_rr_node_ list and also assign its direction in chan_rr_node_direction_ */
   public: /* Mutators: cleaners */
     void clear();
-    void clear_chan_nodes(enum e_side node_side); /* Clean the chan_width of a side */
-    void clear_ipin_nodes(enum e_side node_side); /* Clean the number of IPINs of a side */
-    void clear_opin_nodes(enum e_side node_side); /* Clean the number of OPINs of a side */
-    void clear_one_side(enum e_side node_side); /* Clean chan/opin/ipin nodes at one side */
-  private: /* Internal Mutators */
-    void mirror_side_chan_node_direction(enum e_side side); /* Mirror the node direction and port direction of routing track nodes on a side */
+
+    /* Clean the chan_width of a side */
+    void clear_chan_nodes(const e_side& node_side); 
+
+    /* Clean the number of IPINs of a side */
+    void clear_ipin_nodes(const e_side& node_side); 
+
+    /* Clean the number of OPINs of a side */
+    void clear_opin_nodes(const e_side& node_side); 
+
+    /* Clean chan/opin/ipin nodes at one side */
+    void clear_one_side(const e_side& node_side); 
   private: /* internal functions */
-    bool is_sb_node_mirror (const RRGSB& cand, enum e_side node_side, size_t track_id) const; 
-    bool is_cb_node_mirror (const RRGSB& cand, t_rr_type cb_type, enum e_side node_side, size_t node_id) const; 
-    size_t get_track_id_first_short_connection(enum e_side node_side) const; 
+    bool is_sb_node_mirror(const RRGraph& rr_graph,
+                           const RRGSB& cand,
+                           const e_side& node_side, 
+                           const size_t& track_id) const; 
+
+    bool is_cb_node_mirror(const RRGraph& rr_graph, 
+                           const RRGSB& cand, 
+                           const t_rr_type& cb_type, 
+                           const e_side& node_side, 
+                           const size_t& node_id) const; 
+
+    size_t get_track_id_first_short_connection(const RRGraph& rr_graph, const e_side& node_side) const; 
+
+  private: /* internal validators */
     bool validate_num_sides() const;
-    bool validate_side(enum e_side side) const;
-    bool validate_track_id(enum e_side side, size_t track_id) const;
-    bool validate_opin_node_id(enum e_side side, size_t node_id) const;
-    bool validate_ipin_node_id(enum e_side side, size_t node_id) const;
-    bool validate_cb_type(t_rr_type cb_type) const;
+    bool validate_side(const e_side& side) const;
+    bool validate_track_id(const e_side& side, const size_t& track_id) const;
+    bool validate_opin_node_id(const e_side& side, const size_t& node_id) const;
+    bool validate_ipin_node_id(const e_side& side, const size_t& node_id) const;
+    bool validate_cb_type(const t_rr_type& cb_type) const;
   private: /* Internal Data */
     /* Coordinator */
-    DeviceCoordinator coordinator_;
+    vtr::Point<size_t> coordinate_;
     /* Routing channel data */
     std::vector<RRChan>  chan_node_;
-    std::vector< std::vector<enum PORTS> >  chan_node_direction_; 
+    std::vector<std::vector<PORTS>>  chan_node_direction_; 
 
     /* Logic Block Inputs data */
-    std::vector< std::vector<t_rr_node*> >  ipin_node_;
-    std::vector< std::vector<enum e_side> > ipin_node_grid_side_;
+    std::vector<std::vector<RRNodeId>>  ipin_node_;
 
     /* Logic Block Outputs data */
-    std::vector< std::vector<t_rr_node*> >  opin_node_;
-    std::vector< std::vector<enum e_side> > opin_node_grid_side_;
-    
-    /* Configuration bits */
-    ConfPorts  sb_conf_port_;
-    ConfPorts cbx_conf_port_;
-    ConfPorts cby_conf_port_;
+    std::vector<std::vector<RRNodeId>>  opin_node_;
 };
 
-
 } /* End namespace openfpga*/
 
 #endif
diff --git a/openfpga/src/utils/openfpga_rr_graph_utils.cpp b/openfpga/src/utils/openfpga_rr_graph_utils.cpp
new file mode 100644
index 000000000..cac7284d5
--- /dev/null
+++ b/openfpga/src/utils/openfpga_rr_graph_utils.cpp
@@ -0,0 +1,66 @@
+/********************************************************************
+ * This file includes most utilized functions for the rr_graph
+ * data structure in the OpenFPGA context
+ *******************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+#include "openfpga_rr_graph_utils.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/************************************************************************
+ * Get the coordinator of a starting point of a routing track 
+ * For routing tracks in INC_DIRECTION
+ * (xlow, ylow) should be the starting point 
+ *
+ * For routing tracks in DEC_DIRECTION
+ * (xhigh, yhigh) should be the starting point 
+ ***********************************************************************/
+vtr::Point<size_t> get_track_rr_node_start_coordinate(const RRGraph& rr_graph,
+                                                      const RRNodeId& track_rr_node) {
+  /* Make sure we have CHANX or CHANY */
+  VTR_ASSERT( (CHANX == rr_graph.node_type(track_rr_node))
+           || (CHANY == rr_graph.node_type(track_rr_node)) );
+ 
+  vtr::Point<size_t> start_coordinator;
+
+  if (INC_DIRECTION == rr_graph.node_direction(track_rr_node)) {
+    start_coordinator.set(rr_graph.node_xlow(track_rr_node), rr_graph.node_ylow(track_rr_node));
+  } else {
+    VTR_ASSERT(DEC_DIRECTION == rr_graph.node_direction(track_rr_node));
+    start_coordinator.set(rr_graph.node_xhigh(track_rr_node), rr_graph.node_yhigh(track_rr_node));
+  }
+
+  return start_coordinator;
+}
+
+/************************************************************************
+ * Get the coordinator of a end point of a routing track 
+ * For routing tracks in INC_DIRECTION
+ * (xhigh, yhigh) should be the starting point 
+ *
+ * For routing tracks in DEC_DIRECTION
+ * (xlow, ylow) should be the starting point 
+ ***********************************************************************/
+vtr::Point<size_t> get_track_rr_node_end_coordinate(const RRGraph& rr_graph,
+                                                    const RRNodeId& track_rr_node) {
+  /* Make sure we have CHANX or CHANY */
+  VTR_ASSERT( (CHANX == rr_graph.node_type(track_rr_node))
+           || (CHANY == rr_graph.node_type(track_rr_node)) );
+ 
+  vtr::Point<size_t> end_coordinator;
+
+  if (INC_DIRECTION == rr_graph.node_direction(track_rr_node)) {
+    end_coordinator.set(rr_graph.node_xhigh(track_rr_node), rr_graph.node_yhigh(track_rr_node));
+  } else {
+    VTR_ASSERT(DEC_DIRECTION == rr_graph.node_direction(track_rr_node));
+    end_coordinator.set(rr_graph.node_xlow(track_rr_node), rr_graph.node_ylow(track_rr_node));
+  }
+
+  return end_coordinator;
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/utils/openfpga_rr_graph_utils.h b/openfpga/src/utils/openfpga_rr_graph_utils.h
new file mode 100644
index 000000000..44306664b
--- /dev/null
+++ b/openfpga/src/utils/openfpga_rr_graph_utils.h
@@ -0,0 +1,28 @@
+#ifndef OPENFPGA_RR_GRAPH_UTILS_H
+#define OPENFPGA_RR_GRAPH_UTILS_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_geometry.h"
+
+/* Headers from vpr library */
+#include "rr_graph_obj.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+vtr::Point<size_t> get_track_rr_node_start_coordinate(const RRGraph& rr_graph, 
+                                                      const RRNodeId& track_rr_node);
+
+vtr::Point<size_t> get_track_rr_node_end_coordinate(const RRGraph& rr_graph,
+                                                    const RRNodeId& track_rr_node);
+
+} /* end namespace openfpga */
+
+#endif

From 85f3826939b058a16c780e2ad42e18f95f37381b Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 9 Feb 2020 14:58:23 -0700
Subject: [PATCH 111/645] put device rr_gsb online. Ready to plug-in

---
 openfpga/src/annotation/device_rr_gsb.cpp | 452 ++++++++++++++++++++++
 openfpga/src/annotation/device_rr_gsb.h   | 106 ++---
 openfpga/src/annotation/rr_chan.cpp       |  10 +-
 openfpga/src/annotation/rr_gsb.cpp        |  15 +-
 4 files changed, 515 insertions(+), 68 deletions(-)
 create mode 100644 openfpga/src/annotation/device_rr_gsb.cpp

diff --git a/openfpga/src/annotation/device_rr_gsb.cpp b/openfpga/src/annotation/device_rr_gsb.cpp
new file mode 100644
index 000000000..9152f209c
--- /dev/null
+++ b/openfpga/src/annotation/device_rr_gsb.cpp
@@ -0,0 +1,452 @@
+/************************************************************************
+ * Member functions for class DeviceRRGSB
+ ***********************************************************************/
+#include "vtr_log.h"
+#include "vtr_assert.h"
+#include "device_rr_gsb.h"
+
+/* namespace openfpga begins */
+namespace openfpga {
+
+/************************************************************************
+ * Constructors
+ ***********************************************************************/
+
+/************************************************************************
+ * Public accessors
+ ***********************************************************************/
+/* get the max coordinate of the switch block array */
+vtr::Point<size_t> DeviceRRGSB::get_gsb_range() const {
+  size_t max_y = 0;
+  /* Get the largest size of sub-arrays */
+  for (size_t x = 0; x < rr_gsb_.size(); ++x) {
+    max_y = std::max(max_y, rr_gsb_[x].size());
+  }
+  
+  vtr::Point<size_t> coordinate(rr_gsb_.size(), max_y);
+  return coordinate;
+} 
+
+/* Get a rr switch block in the array with a coordinate */
+const RRGSB DeviceRRGSB::get_gsb(const vtr::Point<size_t>& coordinate) const {
+  VTR_ASSERT(validate_coordinate(coordinate));
+  return rr_gsb_[coordinate.x()][coordinate.y()];
+} 
+
+/* Get a rr switch block in the array with a coordinate */
+const RRGSB DeviceRRGSB::get_gsb(const size_t& x, const size_t& y) const { 
+  vtr::Point<size_t> coordinate(x, y);  
+  return get_gsb(coordinate);
+}
+
+/* get the number of unique mirrors of switch blocks */
+size_t DeviceRRGSB::get_num_cb_unique_module(const t_rr_type& cb_type) const {
+  VTR_ASSERT (validate_cb_type(cb_type));
+  switch(cb_type) {
+  case CHANX:
+    return cbx_unique_module_.size();
+  case CHANY:
+    return cby_unique_module_.size();
+  default: 
+    VTR_LOG_ERROR("Invalid type of connection block!\n");
+    exit(1);
+  }
+} 
+
+/* get the number of unique mirrors of switch blocks */
+size_t DeviceRRGSB::get_num_sb_unique_module() const {
+  return sb_unique_module_.size();
+} 
+
+/* get the number of unique mirrors of switch blocks */
+size_t DeviceRRGSB::get_num_gsb_unique_module() const {
+  return gsb_unique_module_.size();
+} 
+
+/* Get a rr switch block which a unique mirror */ 
+const RRGSB DeviceRRGSB::get_sb_unique_module(const size_t& index) const {
+  VTR_ASSERT (validate_sb_unique_module_index(index));
+  
+  return rr_gsb_[sb_unique_module_[index].x()][sb_unique_module_[index].y()];
+}
+
+/* Get a rr switch block which a unique mirror */ 
+const RRGSB& DeviceRRGSB::get_cb_unique_module(const t_rr_type& cb_type, const size_t& index) const {
+  VTR_ASSERT (validate_cb_unique_module_index(cb_type, index));
+  VTR_ASSERT (validate_cb_type(cb_type));
+  switch(cb_type) {
+  case CHANX: 
+   return rr_gsb_[cbx_unique_module_[index].x()][cbx_unique_module_[index].y()];
+  case CHANY:
+   return rr_gsb_[cby_unique_module_[index].x()][cby_unique_module_[index].y()];
+  default: 
+    VTR_LOG_ERROR("Invalid type of connection block!\n");
+    exit(1);
+  }  
+}
+
+/* Give a coordinate of a rr switch block, and return its unique mirror */ 
+const RRGSB& DeviceRRGSB::get_cb_unique_module(const t_rr_type& cb_type, const vtr::Point<size_t>& coordinate) const {
+  VTR_ASSERT(validate_cb_type(cb_type));
+  VTR_ASSERT(validate_coordinate(coordinate));
+  size_t cb_unique_module_id;
+
+  switch(cb_type) {
+  case CHANX:
+    cb_unique_module_id = cbx_unique_module_id_[coordinate.x()][coordinate.y()];  
+    break;
+  case CHANY:
+    cb_unique_module_id = cby_unique_module_id_[coordinate.x()][coordinate.y()];  
+    break;
+  default: 
+    VTR_LOG_ERROR("Invalid type of connection block!\n");
+    exit(1);
+  }  
+
+  return get_cb_unique_module(cb_type, cb_unique_module_id);
+} 
+
+/* Give a coordinate of a rr switch block, and return its unique mirror */ 
+const RRGSB DeviceRRGSB::get_sb_unique_module(const vtr::Point<size_t>& coordinate) const {
+  VTR_ASSERT(validate_coordinate(coordinate));
+  size_t sb_unique_module_id = sb_unique_module_id_[coordinate.x()][coordinate.y()];  
+  return get_sb_unique_module(sb_unique_module_id);
+} 
+
+/************************************************************************
+ * Public mutators
+ ***********************************************************************/
+
+/* Pre-allocate the rr_switch_block array that the device requires */ 
+void DeviceRRGSB::reserve(const vtr::Point<size_t>& coordinate) { 
+  rr_gsb_.resize(coordinate.x());
+
+  gsb_unique_module_id_.resize(coordinate.x());
+
+  sb_unique_module_id_.resize(coordinate.x());
+
+  cbx_unique_module_id_.resize(coordinate.x());
+  cby_unique_module_id_.resize(coordinate.x());
+
+  for (size_t x = 0; x < coordinate.x(); ++x) {
+    rr_gsb_[x].resize(coordinate.y()); 
+
+    gsb_unique_module_id_[x].resize(coordinate.y()); 
+
+    sb_unique_module_id_[x].resize(coordinate.y()); 
+
+    cbx_unique_module_id_[x].resize(coordinate.y());
+    cby_unique_module_id_[x].resize(coordinate.y()); 
+  }
+}
+
+/* Resize rr_switch_block array is needed*/
+void DeviceRRGSB::resize_upon_need(const vtr::Point<size_t>& coordinate) { 
+  if (coordinate.x() + 1 > rr_gsb_.size()) {
+    rr_gsb_.resize(coordinate.x() + 1);
+
+    sb_unique_module_id_.resize(coordinate.x() + 1);
+
+    cbx_unique_module_id_.resize(coordinate.x() + 1);
+    cby_unique_module_id_.resize(coordinate.x() + 1);
+  }
+
+  if (coordinate.y() + 1 > rr_gsb_[coordinate.x()].size()) {
+    rr_gsb_[coordinate.x()].resize(coordinate.y() + 1);
+    sb_unique_module_id_[coordinate.x()].resize(coordinate.y() + 1);
+
+    cbx_unique_module_id_[coordinate.x()].resize(coordinate.y() + 1);
+    cby_unique_module_id_[coordinate.x()].resize(coordinate.y() + 1);
+  }
+}
+
+/* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
+void DeviceRRGSB::add_rr_gsb(const vtr::Point<size_t>& coordinate, 
+                             const RRGSB& rr_gsb) {
+  /* Resize upon needs*/
+  resize_upon_need(coordinate);
+
+  /* Add the switch block into array */
+  rr_gsb_[coordinate.x()][coordinate.y()] = rr_gsb; 
+}
+
+/* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
+void DeviceRRGSB::build_cb_unique_module(const RRGraph& rr_graph, const t_rr_type& cb_type) {
+  /* Make sure a clean start */
+  clear_cb_unique_module(cb_type);
+
+  for (size_t ix = 0; ix < rr_gsb_.size(); ++ix) {
+    for (size_t iy = 0; iy < rr_gsb_[ix].size(); ++iy) {
+      bool is_unique_module = true;
+      vtr::Point<size_t> gsb_coordinate(ix, iy);
+
+      /* Bypass non-exist CB */
+      if ( false == rr_gsb_[ix][iy].is_cb_exist(cb_type) ) {
+        continue;
+      }
+
+      /* Traverse the unique_mirror list and check it is an mirror of another */
+      for (size_t id = 0; id < get_num_cb_unique_module(cb_type); ++id) {
+        const RRGSB& unique_module = get_cb_unique_module(cb_type, id);
+        if (true == rr_gsb_[ix][iy].is_cb_mirror(rr_graph, unique_module, cb_type)) {
+          /* This is a mirror, raise the flag and we finish */
+          is_unique_module = false;
+          /* Record the id of unique mirror */
+          set_cb_unique_module_id(cb_type, gsb_coordinate, id); 
+          break;
+        }
+      }
+      /* Add to list if this is a unique mirror*/
+      if (true == is_unique_module) {
+        add_cb_unique_module(cb_type, gsb_coordinate);
+        /* Record the id of unique mirror */
+        set_cb_unique_module_id(cb_type, gsb_coordinate, get_num_cb_unique_module(cb_type) - 1); 
+      }
+    }
+  } 
+}
+
+/* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
+void DeviceRRGSB::build_sb_unique_module(const RRGraph& rr_graph) {
+  /* Make sure a clean start */
+  clear_sb_unique_module();
+
+  /* Build the unique module */
+  for (size_t ix = 0; ix < rr_gsb_.size(); ++ix) {
+    for (size_t iy = 0; iy < rr_gsb_[ix].size(); ++iy) {
+      bool is_unique_module = true;
+      vtr::Point<size_t> sb_coordinate(ix, iy);
+
+      /* Traverse the unique_mirror list and check it is an mirror of another */
+      for (size_t id = 0; id < get_num_sb_unique_module(); ++id) {
+        /* Check if the two modules have the same submodules,
+         * if so, these two modules are the same, indicating the sb is not unique.
+         * else the sb is unique 
+         */
+        const RRGSB& unique_module = get_sb_unique_module(id);
+        if (true == rr_gsb_[ix][iy].is_sb_mirror(rr_graph, unique_module)) {
+          /* This is a mirror, raise the flag and we finish */
+          is_unique_module = false;
+          /* Record the id of unique mirror */
+          sb_unique_module_id_[ix][iy] = id; 
+          break;
+        }
+      }
+      /* Add to list if this is a unique mirror*/
+      if (true == is_unique_module) {
+        sb_unique_module_.push_back(sb_coordinate);
+        /* Record the id of unique mirror */
+        sb_unique_module_id_[ix][iy] = sb_unique_module_.size() - 1; 
+      }
+    }
+  } 
+}
+
+/* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
+
+/* Find repeatable GSB block in the array */
+void DeviceRRGSB::build_gsb_unique_module() {
+  /* Make sure a clean start */
+  clear_gsb_unique_module();
+
+  for (size_t ix = 0; ix < rr_gsb_.size(); ++ix) {
+    for (size_t iy = 0; iy < rr_gsb_[ix].size(); ++iy) {
+      bool is_unique_module = true;
+      vtr::Point<size_t> gsb_coordinate(ix, iy);
+
+      /* Traverse the unique_mirror list and check it is an mirror of another */
+      for (size_t id = 0; id < get_num_gsb_unique_module(); ++id) {
+        /* We have alreay built sb and cb unique module list 
+         * We just need to check if the unique module id of SBs, CBX and CBY are the same or not 
+         */
+        const vtr::Point<size_t>& gsb_unique_module_coordinate = gsb_unique_module_[id];
+        if ((sb_unique_module_id_[ix][iy] == sb_unique_module_id_[gsb_unique_module_coordinate.x()][gsb_unique_module_coordinate.y()])
+         && (cbx_unique_module_id_[ix][iy] == cbx_unique_module_id_[gsb_unique_module_coordinate.x()][gsb_unique_module_coordinate.y()])
+         && (cby_unique_module_id_[ix][iy] == cby_unique_module_id_[gsb_unique_module_coordinate.x()][gsb_unique_module_coordinate.y()])) {
+          /* This is a mirror, raise the flag and we finish */
+          is_unique_module = false;
+          /* Record the id of unique mirror */
+          gsb_unique_module_id_[ix][iy] = id; 
+          break;
+        }
+      }
+      /* Add to list if this is a unique mirror*/
+      if (true == is_unique_module) {
+        add_gsb_unique_module(gsb_coordinate);
+        /* Record the id of unique mirror */
+        gsb_unique_module_id_[ix][iy] = get_num_gsb_unique_module() - 1;
+      }
+    }
+  } 
+}
+
+void DeviceRRGSB::build_unique_module(const RRGraph& rr_graph) {
+  build_sb_unique_module(rr_graph);
+
+  build_cb_unique_module(rr_graph, CHANX);
+  build_cb_unique_module(rr_graph, CHANY);
+
+  build_gsb_unique_module();
+}
+
+void DeviceRRGSB::add_gsb_unique_module(const vtr::Point<size_t>& coordinate) {
+  gsb_unique_module_.push_back(coordinate); 
+}
+
+void DeviceRRGSB::add_cb_unique_module(const t_rr_type& cb_type, const vtr::Point<size_t>& coordinate) {
+  VTR_ASSERT (validate_cb_type(cb_type));
+  switch(cb_type) {
+  case CHANX:
+    cbx_unique_module_.push_back(coordinate); 
+    return;
+  case CHANY:
+    cby_unique_module_.push_back(coordinate); 
+    return;
+  default: 
+    VTR_LOG_ERROR("Invalid type of connection block!\n");
+    exit(1);
+  }
+}
+
+void DeviceRRGSB::set_cb_unique_module_id(const t_rr_type& cb_type, const vtr::Point<size_t>& coordinate, size_t id) {
+  VTR_ASSERT(validate_cb_type(cb_type));
+  size_t x = coordinate.x();
+  size_t y = coordinate.y();
+  switch(cb_type) {
+  case CHANX:
+    cbx_unique_module_id_[x][y] = id; 
+    return;
+  case CHANY:
+    cby_unique_module_id_[x][y] = id; 
+    return;
+  default: 
+    VTR_LOG_ERROR("Invalid type of connection block!\n");
+    exit(1);
+  }
+}
+
+/************************************************************************
+ * Public clean-up functions:
+ ***********************************************************************/
+/* clean the content */
+void DeviceRRGSB::clear() { 
+  clear_gsb();
+
+  clear_gsb_unique_module();
+  clear_gsb_unique_module_id();
+
+  /* clean unique module lists */
+  clear_cb_unique_module(CHANX);
+  clear_cb_unique_module_id(CHANX);
+
+  clear_cb_unique_module(CHANY);
+  clear_cb_unique_module_id(CHANY);
+
+  clear_sb_unique_module();
+  clear_sb_unique_module_id();
+}
+
+void DeviceRRGSB::clear_gsb() {
+  /* clean gsb array */
+  for (size_t x = 0; x < rr_gsb_.size(); ++x) {
+    rr_gsb_[x].clear(); 
+  }
+  rr_gsb_.clear();
+}
+
+void DeviceRRGSB::clear_gsb_unique_module_id() {
+  /* clean rr_switch_block array */
+  for (size_t x = 0; x < rr_gsb_.size(); ++x) {
+    gsb_unique_module_id_[x].clear(); 
+  }
+}
+
+void DeviceRRGSB::clear_sb_unique_module_id() {
+  /* clean rr_switch_block array */
+  for (size_t x = 0; x < rr_gsb_.size(); ++x) {
+    sb_unique_module_id_[x].clear(); 
+  }
+}
+
+void DeviceRRGSB::clear_cb_unique_module_id(const t_rr_type& cb_type) {
+  VTR_ASSERT (validate_cb_type(cb_type));
+  switch(cb_type) {
+  case CHANX:
+    for (size_t x = 0; x < rr_gsb_.size(); ++x) {
+      cbx_unique_module_id_[x].clear(); 
+    }
+    return;
+  case CHANY:
+    for (size_t x = 0; x < rr_gsb_.size(); ++x) {
+      cby_unique_module_id_[x].clear(); 
+    }
+    return;
+  default: 
+    VTR_LOG_ERROR("Invalid type of connection block!\n");
+    exit(1);
+  }
+}
+
+/* clean the content related to unique_mirrors */
+void DeviceRRGSB::clear_gsb_unique_module() {
+  /* clean unique mirror */
+  gsb_unique_module_.clear();
+} 
+
+/* clean the content related to unique_mirrors */
+void DeviceRRGSB::clear_sb_unique_module() {
+  /* clean unique mirror */
+  sb_unique_module_.clear();
+} 
+
+void DeviceRRGSB::clear_cb_unique_module(const t_rr_type& cb_type) {
+  VTR_ASSERT (validate_cb_type(cb_type));
+  switch(cb_type) {
+  case CHANX:
+    cbx_unique_module_.clear(); 
+    return;
+  case CHANY:
+    cby_unique_module_.clear(); 
+    return;
+  default: 
+    VTR_LOG_ERROR("Invalid type of connection block!\n");
+    exit(1);
+  }
+}
+
+/************************************************************************
+ * Internal validators
+ ***********************************************************************/
+/* Validate if the (x,y) is the range of this device */
+bool DeviceRRGSB::validate_coordinate(const vtr::Point<size_t>& coordinate) const {
+  if (coordinate.x() >= rr_gsb_.capacity()) {
+    return false;
+  }
+  return (coordinate.y() < rr_gsb_[coordinate.x()].capacity());
+} 
+
+/* Validate if the index in the range of unique_mirror vector*/
+bool DeviceRRGSB::validate_sb_unique_module_index(const size_t& index) const { 
+  return (index < sb_unique_module_.size());
+}
+
+bool DeviceRRGSB::validate_cb_unique_module_index(const t_rr_type& cb_type, const size_t& index) const {
+  VTR_ASSERT(validate_cb_type(cb_type));
+  switch(cb_type) {
+  case CHANX:
+    return (index < cbx_unique_module_.size());
+  case CHANY:
+    return (index < cby_unique_module_.size());
+  default: 
+    VTR_LOG_ERROR("Invalid type of connection block!\n");
+    exit(1);
+  } 
+
+  return false;
+}
+
+bool DeviceRRGSB::validate_cb_type(const t_rr_type& cb_type) const {
+  return ((CHANX == cb_type) || (CHANY == cb_type));
+}
+
+} /* End namespace openfpga*/
diff --git a/openfpga/src/annotation/device_rr_gsb.h b/openfpga/src/annotation/device_rr_gsb.h
index e801417bc..624492124 100644
--- a/openfpga/src/annotation/device_rr_gsb.h
+++ b/openfpga/src/annotation/device_rr_gsb.h
@@ -4,8 +4,17 @@
 /********************************************************************
  * Include header files required by the data structure definition
  *******************************************************************/
+/* Header files from vtrutil library */
+#include "vtr_geometry.h"
+
+/* Header files from vpr library */
+#include "rr_graph_obj.h"
+
 #include "rr_gsb.h"
 
+/* namespace openfpga begins */
+namespace openfpga {
+
 /********************************************************************
  * Object Device Routing Resource Switch Block 
  * This includes:
@@ -18,87 +27,58 @@
 class DeviceRRGSB {
   public: /* Contructors */
   public: /* Accessors */
-    DeviceCoordinator get_gsb_range() const; /* get the max coordinator of the switch block array */
-    const RRGSB get_gsb(const DeviceCoordinator& coordinator) const; /* Get a rr switch block in the array with a coordinator */
-    const RRGSB get_gsb(size_t x, size_t y) const; /* Get a rr switch block in the array with a coordinator */
+    vtr::Point<size_t> get_gsb_range() const; /* get the max coordinate of the switch block array */
+    const RRGSB get_gsb(const vtr::Point<size_t>& coordinate) const; /* Get a rr switch block in the array with a coordinate */
+    const RRGSB get_gsb(const size_t& x, const size_t& y) const; /* Get a rr switch block in the array with a coordinate */
     size_t get_num_gsb_unique_module() const; /* get the number of unique mirrors of GSB */
-    size_t get_num_sb_unique_submodule(enum e_side side, size_t seg_index) const; /* get the number of unique mirrors of switch blocks */
     size_t get_num_sb_unique_module() const; /* get the number of unique mirrors of switch blocks */
-    size_t get_num_cb_unique_module(t_rr_type cb_type) const; /* get the number of unique mirrors of CBs */
-    size_t get_sb_unique_submodule_id(DeviceCoordinator& coordinator, enum e_side side, size_t seg_id) const;
-    const RRGSB get_sb_unique_submodule(size_t index, enum e_side side, size_t seg_id) const; /* Get a rr switch block which a unique mirror */ 
-    const RRGSB get_sb_unique_submodule(DeviceCoordinator& coordinator, enum e_side side, size_t seg_id) const; /* Get a rr switch block which a unique mirror */ 
-    const RRGSB get_sb_unique_module(size_t index) const; /* Get a rr switch block which a unique mirror */ 
-    const RRGSB get_sb_unique_module(const DeviceCoordinator& coordinator) const; /* Get a rr switch block which a unique mirror */ 
-    const RRGSB& get_cb_unique_module(t_rr_type cb_type, size_t index) const; /* Get a rr switch block which a unique mirror */ 
-    const RRGSB& get_cb_unique_module(t_rr_type cb_type, const DeviceCoordinator& coordinator) const;
-    size_t get_max_num_sides() const; /* Get the maximum number of sides across the switch blocks */
-    size_t get_num_segments() const; /* Get the size of segment_ids */
-    size_t get_segment_id(size_t index) const; /* Get a segment id */
-    bool is_two_sb_share_same_submodules(DeviceCoordinator& src, DeviceCoordinator& des) const;
+    const RRGSB get_sb_unique_module(const size_t& index) const; /* Get a rr switch block which a unique mirror */ 
+    const RRGSB get_sb_unique_module(const vtr::Point<size_t>& coordinate) const; /* Get a rr switch block which a unique mirror */ 
+    const RRGSB& get_cb_unique_module(const t_rr_type& cb_type, const size_t& index) const; /* Get a rr switch block which a unique mirror */ 
+    const RRGSB& get_cb_unique_module(const t_rr_type& cb_type, const vtr::Point<size_t>& coordinate) const;
+    size_t get_num_cb_unique_module(const t_rr_type& cb_type) const; /* get the number of unique mirrors of CBs */
   public: /* Mutators */ 
-    void set_sb_num_reserved_conf_bits(DeviceCoordinator& coordinator, size_t num_reserved_conf_bits); /* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */
-    void set_sb_conf_bits_lsb(DeviceCoordinator& coordinator, size_t conf_bits_lsb); /* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */
-    void set_sb_conf_bits_msb(DeviceCoordinator& coordinator, size_t conf_bits_msb); /* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */
-    void set_cb_num_reserved_conf_bits(DeviceCoordinator& coordinator, t_rr_type cb_type, size_t num_reserved_conf_bits); /* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */
-    void set_cb_conf_bits_lsb(DeviceCoordinator& coordinator, t_rr_type cb_type, size_t conf_bits_lsb); /* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */
-    void set_cb_conf_bits_msb(DeviceCoordinator& coordinator, t_rr_type cb_type, size_t conf_bits_msb); /* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */
-    void reserve(DeviceCoordinator& coordinator); /* Pre-allocate the rr_switch_block array that the device requires */ 
-    void reserve_sb_unique_submodule_id(DeviceCoordinator& coordinator); /* Pre-allocate the rr_sb_unique_module_id matrix that the device requires */ 
-    void resize_upon_need(const DeviceCoordinator& coordinator); /* Resize the rr_switch_block array if needed */ 
-    void add_rr_gsb(const DeviceCoordinator& coordinator, const RRGSB& rr_gsb); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
-    void build_unique_module(); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
+    void reserve(const vtr::Point<size_t>& coordinate); /* Pre-allocate the rr_switch_block array that the device requires */ 
+    void reserve_sb_unique_submodule_id(const vtr::Point<size_t>& coordinate); /* Pre-allocate the rr_sb_unique_module_id matrix that the device requires */ 
+    void resize_upon_need(const vtr::Point<size_t>& coordinate); /* Resize the rr_switch_block array if needed */ 
+    void add_rr_gsb(const vtr::Point<size_t>& coordinate, const RRGSB& rr_gsb); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
+    void build_unique_module(const RRGraph& rr_graph); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
     void clear(); /* clean the content */
   private: /* Internal cleaners */
     void clear_gsb(); /* clean the content */
-    void clear_cb_unique_module(t_rr_type cb_type); /* clean the content */
-    void clear_cb_unique_module_id(t_rr_type cb_type); /* clean the content */
+    void clear_cb_unique_module(const t_rr_type& cb_type); /* clean the content */
+    void clear_cb_unique_module_id(const t_rr_type& cb_type); /* clean the content */
     void clear_sb_unique_module(); /* clean the content */
     void clear_sb_unique_module_id(); /* clean the content */
-    void clear_sb_unique_submodule(); /* clean the content */
-    void clear_sb_unique_submodule_id(); /* clean the content */
     void clear_gsb_unique_module(); /* clean the content */
     void clear_gsb_unique_module_id(); /* clean the content */
-    void clear_segment_ids();
   private: /* Validators */
-    bool validate_coordinator(const DeviceCoordinator& coordinator) const; /* Validate if the (x,y) is the range of this device */
-    bool validate_coordinator_edge(DeviceCoordinator& coordinator) const; /* Validate if the (x,y) is the range of this device but takes into consideration the fact that edges are 1 off */
-    bool validate_side(enum e_side side) const; /* validate if side is in the range of unique_side_module_ */
-    bool validate_sb_unique_module_index(size_t index) const; /* Validate if the index in the range of unique_mirror vector*/
-    bool validate_cb_unique_module_index(t_rr_type cb_type, size_t index) const; /* Validate if the index in the range of unique_mirror vector*/
-    bool validate_sb_unique_submodule_index(size_t index, enum e_side side, size_t seg_index) const; /* Validate if the index in the range of unique_module vector */
-    bool validate_segment_index(size_t index) const;
-    bool validate_cb_type(t_rr_type cb_type) const;
+    bool validate_coordinate(const vtr::Point<size_t>& coordinate) const; /* Validate if the (x,y) is the range of this device */
+    bool validate_side(const e_side& side) const; /* validate if side is in the range of unique_side_module_ */
+    bool validate_sb_unique_module_index(const size_t& index) const; /* Validate if the index in the range of unique_mirror vector*/
+    bool validate_cb_unique_module_index(const t_rr_type& cb_type, const size_t& index) const; /* Validate if the index in the range of unique_mirror vector*/
+    bool validate_cb_type(const t_rr_type& cb_type) const;
   private: /* Internal builders */
-    void build_segment_ids(); /* build a map of segment_ids */
-    void add_gsb_unique_module(const DeviceCoordinator& coordinator);
-    void add_sb_unique_side_submodule(DeviceCoordinator& coordinator, const RRGSB& rr_sb, enum e_side side);
-    void add_sb_unique_side_segment_submodule(DeviceCoordinator& coordinator, const RRGSB& rr_sb, enum e_side side, size_t seg_id);
-    void add_cb_unique_module(t_rr_type cb_type, const DeviceCoordinator& coordinator);
-    void set_cb_unique_module_id(t_rr_type, const DeviceCoordinator& coordinator, size_t id);
-    void build_sb_unique_submodule(); /* Add a switch block to the array, which will automatically identify and update the lists of unique side module */
-    void build_sb_unique_module(); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
-    void build_cb_unique_module(t_rr_type cb_type); /* Add a switch block to the array, which will automatically identify and update the lists of unique side module */
+    void add_gsb_unique_module(const vtr::Point<size_t>& coordinate);
+    void add_cb_unique_module(const t_rr_type& cb_type, const vtr::Point<size_t>& coordinate);
+    void set_cb_unique_module_id(const t_rr_type& cb_type, const vtr::Point<size_t>& coordinate, size_t id);
+    void build_sb_unique_module(const RRGraph& rr_graph); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
+    void build_cb_unique_module(const RRGraph& rr_graph, const t_rr_type& cb_type); /* Add a switch block to the array, which will automatically identify and update the lists of unique side module */
     void build_gsb_unique_module(); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
   private: /* Internal Data */
-    std::vector< std::vector<RRGSB> > rr_gsb_;
+    std::vector<std::vector<RRGSB>> rr_gsb_;
 
-    std::vector< std::vector<size_t> > gsb_unique_module_id_; /* A map from rr_gsb to its unique mirror */
-    std::vector<DeviceCoordinator> gsb_unique_module_; 
+    std::vector<std::vector<size_t>> gsb_unique_module_id_; /* A map from rr_gsb to its unique mirror */
+    std::vector<vtr::Point<size_t>> gsb_unique_module_; 
 
-    std::vector< std::vector<size_t> > sb_unique_module_id_; /* A map from rr_gsb to its unique mirror */
-    std::vector<DeviceCoordinator> sb_unique_module_; 
+    std::vector<std::vector<size_t>> sb_unique_module_id_; /* A map from rr_gsb to its unique mirror */
+    std::vector<vtr::Point<size_t>> sb_unique_module_; 
 
-    std::vector< std::vector< std::vector< std::vector<size_t> > > > sb_unique_submodule_id_; /* A map from rr_switch_block to its unique_side_module [0..x][0..y][0..num_sides][num_seg-1]*/
-    std::vector< std::vector <std::vector<DeviceCoordinator> > > sb_unique_submodule_; /* For each side of switch block, we identify a list of unique modules based on its connection. This is a matrix [0..num_sides-1][0..num_seg-1][0..num_module], num_sides will the max number of sides of all the rr_switch_blocks */
+    std::vector<std::vector<size_t>> cbx_unique_module_id_; /* A map from rr_gsb to its unique mirror */
+    std::vector<vtr::Point<size_t>> cbx_unique_module_; /* For each side of connection block, we identify a list of unique modules based on its connection. This is a matrix [0..num_module] */
 
-    std::vector< std::vector<size_t> > cbx_unique_module_id_; /* A map from rr_gsb to its unique mirror */
-    std::vector<DeviceCoordinator> cbx_unique_module_; /* For each side of connection block, we identify a list of unique modules based on its connection. This is a matrix [0..num_module] */
-
-    std::vector< std::vector<size_t> > cby_unique_module_id_; /* A map from rr_gsb to its unique mirror */
-    std::vector<DeviceCoordinator> cby_unique_module_; /* For each side of connection block, we identify a list of unique modules based on its connection. This is a matrix [0..num_module] */
-
-    std::vector<size_t> segment_ids_;
+    std::vector<std::vector<size_t>> cby_unique_module_id_; /* A map from rr_gsb to its unique mirror */
+    std::vector<vtr::Point<size_t>> cby_unique_module_; /* For each side of connection block, we identify a list of unique modules based on its connection. This is a matrix [0..num_module] */
 };
 
 } /* End namespace openfpga*/
diff --git a/openfpga/src/annotation/rr_chan.cpp b/openfpga/src/annotation/rr_chan.cpp
index 84540758e..b85d1b917 100644
--- a/openfpga/src/annotation/rr_chan.cpp
+++ b/openfpga/src/annotation/rr_chan.cpp
@@ -24,7 +24,9 @@ RRChan::RRChan() {
   node_segments_.resize(0);
 }
 
-/* Accessors */
+/************************************************************************
+ * Accessors
+ ***********************************************************************/
 t_rr_type RRChan::get_type() const {
   return type_;
 }
@@ -142,7 +144,9 @@ std::vector<RRNodeId> RRChan::get_node_ids_by_segment_ids(const RRSegmentId& seg
   return node_list;
 } 
 
-/* Mutators */
+/************************************************************************
+ * Mutators
+ ***********************************************************************/
 void RRChan::set(const RRChan& rr_chan) {
   /* Ensure a clean start */
   this->clear();
@@ -186,7 +190,7 @@ void RRChan::clear() {
 }
 
 /************************************************************************
- * Internal functions
+ * Internal validators
  ***********************************************************************/
 /* for type, only valid type is CHANX and CHANY */
 bool RRChan::valid_type(const t_rr_type& type) const {
diff --git a/openfpga/src/annotation/rr_gsb.cpp b/openfpga/src/annotation/rr_gsb.cpp
index 54b9fa8f2..6b8cd5236 100644
--- a/openfpga/src/annotation/rr_gsb.cpp
+++ b/openfpga/src/annotation/rr_gsb.cpp
@@ -661,8 +661,10 @@ vtr::Point<size_t> RRGSB::get_grid_coordinate() const {
 
   return ret;
 }
-/* Public mutators */
 
+/************************************************************************
+ * Public Mutators
+ ***********************************************************************/
 /* get a copy from a source */
 void RRGSB::set(const RRGSB& src) { 
   /* Copy coordinate */
@@ -740,6 +742,9 @@ void RRGSB::add_opin_node(const RRNodeId& node, const e_side& node_side) {
   opin_node_[size_t(node_side)].push_back(node);
 } 
 
+/************************************************************************
+ * Public Mutators: clean-up functions
+ ***********************************************************************/
 /* Reset the RRGSB to pristine state */
 void RRGSB::clear() {
   /* Clean all the vectors */
@@ -786,7 +791,9 @@ void RRGSB::clear_one_side(const e_side& node_side) {
   clear_opin_nodes(node_side);
 } 
 
-/* Internal functions for validation */
+/************************************************************************
+ * Internal Accessors: identify mirrors
+ ***********************************************************************/
 
 /* check if two rr_nodes have a similar set of drive_rr_nodes 
  * for each drive_rr_node:
@@ -944,6 +951,10 @@ size_t RRGSB::get_track_id_first_short_connection(const RRGraph& rr_graph, const
   return size_t(-1);
 }
 
+
+/************************************************************************
+ * Internal validators
+ ***********************************************************************/
 /* Validate if the number of sides are consistent among internal data arrays ! */
 bool RRGSB::validate_num_sides() const {
   size_t num_sides = chan_node_direction_.size();

From e2e115e6f36b075b7db6845fb4004ae815cf6b08 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 11 Feb 2020 11:33:30 -0700
Subject: [PATCH 112/645] improve rr_node fast look-up in rr_graph object so
 that we have easily find all the channel nodes

---
 vpr/src/device/rr_graph_obj.cpp | 47 +++++++++++++++++++++------------
 1 file changed, 30 insertions(+), 17 deletions(-)

diff --git a/vpr/src/device/rr_graph_obj.cpp b/vpr/src/device/rr_graph_obj.cpp
index da528cf26..9124ffdc7 100644
--- a/vpr/src/device/rr_graph_obj.cpp
+++ b/vpr/src/device/rr_graph_obj.cpp
@@ -1219,32 +1219,45 @@ void RRGraph::build_fast_node_lookup() const {
             continue;
         }
         RRNodeId node = RRNodeId(id);
-        /* Special for SOURCE and SINK, we should annotate in the look-up 
+        /* Special for CHANX and CHANY, we should annotate in the look-up 
          * for all the (x,y) upto (xhigh, yhigh)
          */
-        size_t x = node_xlow(node);
-        size_t y = node_ylow(node);
+        size_t x_start = std::min(node_xlow(node), node_xhigh(node));
+        size_t y_start = std::min(node_ylow(node), node_yhigh(node));
+        std::vector<size_t> node_x(std::abs(node_xlow(node) - node_xhigh(node)) + 1);
+        std::vector<size_t> node_y(std::abs(node_ylow(node) - node_yhigh(node)) + 1);
+        
+        std::iota(node_x.begin(), node_x.end(), x_start);
+        std::iota(node_y.begin(), node_y.end(), y_start);
+        
+        VTR_ASSERT(size_t(std::max(node_xlow(node), node_xhigh(node))) == node_x.back());
+        VTR_ASSERT(size_t(std::max(node_ylow(node), node_yhigh(node))) == node_y.back());
 
         size_t itype = node_type(node);
 
         size_t ptc = node_ptc_num(node);
-        if (ptc >= node_lookup_[x][y][itype].size()) {
-            node_lookup_[x][y][itype].resize(ptc + 1);
-        }
 
-        size_t iside = -1;
-        if (node_type(node) == OPIN || node_type(node) == IPIN) {
-            iside = node_side(node);
-        } else {
-            iside = NUM_SIDES;
-        }
+        for (const size_t& x : node_x) {
+            for (const size_t& y : node_y) {
+                if (ptc >= node_lookup_[x][y][itype].size()) {
+                    node_lookup_[x][y][itype].resize(ptc + 1);
+                }
 
-        if (iside >= node_lookup_[x][y][itype][ptc].size()) {
-            node_lookup_[x][y][itype][ptc].resize(iside + 1);
-        }
+                size_t iside = -1;
+                if (node_type(node) == OPIN || node_type(node) == IPIN) {
+                    iside = node_side(node);
+                } else {
+                    iside = NUM_SIDES;
+                }
 
-        //Save node in lookup
-        node_lookup_[x][y][itype][ptc][iside] = node;
+                if (iside >= node_lookup_[x][y][itype][ptc].size()) {
+                    node_lookup_[x][y][itype][ptc].resize(iside + 1);
+                }
+
+                //Save node in lookup
+                node_lookup_[x][y][itype][ptc][iside] = node;
+            }
+       }
     }
 }
 

From 1372f748f122f84a54ca6b32f6b1ac3dfa44980e Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 11 Feb 2020 16:37:14 -0700
Subject: [PATCH 113/645] put GSB builder online

---
 openfpga/src/annotation/annotate_rr_gsb.cpp | 395 ++++++++++++++++++++
 openfpga/src/annotation/annotate_rr_gsb.h   |  24 ++
 openfpga/src/base/openfpga_context.h        |  11 +
 openfpga/src/base/openfpga_link_arch.cpp    |   9 +
 vpr/src/device/rr_graph_obj_util.cpp        |  48 ++-
 vpr/src/device/rr_graph_obj_util.h          |   8 +
 6 files changed, 494 insertions(+), 1 deletion(-)
 create mode 100644 openfpga/src/annotation/annotate_rr_gsb.cpp
 create mode 100644 openfpga/src/annotation/annotate_rr_gsb.h

diff --git a/openfpga/src/annotation/annotate_rr_gsb.cpp b/openfpga/src/annotation/annotate_rr_gsb.cpp
new file mode 100644
index 000000000..8050110e5
--- /dev/null
+++ b/openfpga/src/annotation/annotate_rr_gsb.cpp
@@ -0,0 +1,395 @@
+/********************************************************************
+ * This file includes functions that are used to annotate device-level
+ * information, in particular the routing resource graph
+ *******************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_time.h"
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_side_manager.h"
+
+/* Headers from vpr library */
+#include "rr_graph_obj_util.h"
+
+#include "annotate_rr_gsb.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/* Build a RRChan Object with the given channel type and coorindators */
+static 
+RRChan build_one_rr_chan(const DeviceContext& vpr_device_ctx,
+                         const t_rr_type& chan_type, 
+                         vtr::Point<size_t>& chan_coord) {
+  std::vector<RRNodeId> chan_rr_nodes;
+
+  /* Create a rr_chan object and check if it is unique in the graph */
+  RRChan rr_chan;
+  /* Fill the information */
+  rr_chan.set_type(chan_type); 
+
+  /* Collect rr_nodes for this channel */
+  chan_rr_nodes = find_rr_graph_chan_nodes(vpr_device_ctx.rr_graph,
+                                           chan_coord.x(), chan_coord.y(),
+                                           chan_type);
+  /* Fill the rr_chan */  
+  for (const RRNodeId& chan_rr_node : chan_rr_nodes) {
+    rr_chan.add_node(vpr_device_ctx.rr_graph, chan_rr_node, 
+                     vpr_device_ctx.rr_graph.node_segment(chan_rr_node));
+  }
+
+  return rr_chan;
+}
+
+/* Build a General Switch Block (GSB) 
+ * which includes:
+ * [I] A Switch Box subckt consists of following ports:
+ * 1. Channel Y [x][y] inputs 
+ * 2. Channel X [x+1][y] inputs
+ * 3. Channel Y [x][y-1] outputs
+ * 4. Channel X [x][y] outputs
+ * 5. Grid[x][y+1] Right side outputs pins
+ * 6. Grid[x+1][y+1] Left side output pins
+ * 7. Grid[x+1][y+1] Bottom side output pins
+ * 8. Grid[x+1][y] Top side output pins
+ * 9. Grid[x+1][y] Left side output pins
+ * 10. Grid[x][y] Right side output pins
+ * 11. Grid[x][y] Top side output pins
+ * 12. Grid[x][y+1] Bottom side output pins
+ *
+ *    --------------          --------------
+ *    |            |   CBY    |            |
+ *    |    Grid    |  ChanY   |    Grid    |
+ *    |  [x][y+1]  | [x][y+1] | [x+1][y+1] |
+ *    |            |          |            |
+ *    --------------          --------------
+ *                  ----------
+ *     ChanX & CBX  | Switch |     ChanX 
+ *       [x][y]     |   Box  |    [x+1][y]
+ *                  | [x][y] |
+ *                  ----------
+ *    --------------          --------------
+ *    |            |          |            |
+ *    |    Grid    |  ChanY   |    Grid    |
+ *    |   [x][y]   |  [x][y]  |  [x+1][y]  |
+ *    |            |          |            |
+ *    --------------          --------------
+ * For channels chanY with INC_DIRECTION on the top side, they should be marked as outputs
+ * For channels chanY with DEC_DIRECTION on the top side, they should be marked as inputs
+ * For channels chanY with INC_DIRECTION on the bottom side, they should be marked as inputs
+ * For channels chanY with DEC_DIRECTION on the bottom side, they should be marked as outputs
+ * For channels chanX with INC_DIRECTION on the left side, they should be marked as inputs
+ * For channels chanX with DEC_DIRECTION on the left side, they should be marked as outputs
+ * For channels chanX with INC_DIRECTION on the right side, they should be marked as outputs
+ * For channels chanX with DEC_DIRECTION on the right side, they should be marked as inputs
+ *
+ * [II] A X-direction Connection Block [x][y]
+ * The connection block shares the same routing channel[x][y] with the Switch Block
+ * We just need to fill the ipin nodes at TOP and BOTTOM sides 
+ * as well as properly fill the ipin_grid_side information
+ * [III] A Y-direction Connection Block [x][y+1]
+ * The connection block shares the same routing channel[x][y+1] with the Switch Block
+ * We just need to fill the ipin nodes at LEFT and RIGHT sides 
+ * as well as properly fill the ipin_grid_side information
+ */
+static 
+RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, 
+                   const vtr::Point<size_t>& gsb_range,
+                   const vtr::Point<size_t>& gsb_coord) {
+  /* Create an object to return */
+  RRGSB rr_gsb;
+
+  VTR_ASSERT(gsb_coord.x() <= gsb_range.x()); 
+  VTR_ASSERT(gsb_coord.y() <= gsb_range.y()); 
+
+  /* Coordinator initialization */
+  rr_gsb.set_coordinate(gsb_coord.x(), gsb_coord.y());
+
+  /* Basic information*/
+  rr_gsb.init_num_sides(4); /* Fixed number of sides */
+
+  /* Find all rr_nodes of channels */
+  /* Side: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */
+  for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
+    /* Local variables inside this for loop */
+    SideManager side_manager(side);
+    vtr::Point<size_t> coordinate = rr_gsb.get_side_block_coordinate(side_manager.get_side());
+    RRChan rr_chan;
+    std::vector<std::vector<RRNodeId>> temp_opin_rr_nodes(2);
+    enum e_side opin_grid_side[2] = {NUM_SIDES, NUM_SIDES};
+    enum PORTS chan_dir_to_port_dir_mapping[2] = {OUT_PORT, IN_PORT}; /* 0: INC_DIRECTION => ?; 1: DEC_DIRECTION => ? */
+
+    switch (side) {
+    case TOP: /* TOP = 0 */
+      /* For the border, we should take special care */
+      if (gsb_coord.y() == gsb_range.y()) {
+        rr_gsb.clear_one_side(side_manager.get_side());
+        break;
+      }
+      /* Routing channels*/
+      /* Side: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */
+      /* Create a rr_chan object and check if it is unique in the graph */
+      rr_chan = build_one_rr_chan(vpr_device_ctx, CHANY, coordinate);
+      chan_dir_to_port_dir_mapping[0] = OUT_PORT; /* INC_DIRECTION => OUT_PORT */
+      chan_dir_to_port_dir_mapping[1] =  IN_PORT; /* DEC_DIRECTION => IN_PORT */
+
+      /* Build the Switch block: opin and opin_grid_side */
+      /* Assign grid side of OPIN */
+      /* Grid[x][y+1] RIGHT side outputs pins */
+      opin_grid_side[0] = RIGHT;
+      /* Grid[x+1][y+1] left side outputs pins */
+      opin_grid_side[1] = LEFT; 
+      /* Include Grid[x][y+1] RIGHT side outputs pins */
+      temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes(vpr_device_ctx.rr_graph, vpr_device_ctx.grid, 
+                                                       gsb_coord.x(), gsb_coord.y() + 1, OPIN, opin_grid_side[0]);
+      /* Include Grid[x+1][y+1] Left side output pins */
+      temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes(vpr_device_ctx.rr_graph, vpr_device_ctx.grid, 
+                                                       gsb_coord.x() + 1, gsb_coord.y() + 1, OPIN, opin_grid_side[1]);
+
+      break;
+    case RIGHT: /* RIGHT = 1 */
+      /* For the border, we should take special care */
+      if (gsb_coord.x() == gsb_range.x()) {
+        rr_gsb.clear_one_side(side_manager.get_side());
+        break;
+      }
+      /* Routing channels*/
+      /* Side: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */
+      /* Collect rr_nodes for Tracks for top: chany[x][y+1] */
+      /* Create a rr_chan object and check if it is unique in the graph */
+      rr_chan = build_one_rr_chan(vpr_device_ctx, CHANX, coordinate);
+      chan_dir_to_port_dir_mapping[0] = OUT_PORT; /* INC_DIRECTION => OUT_PORT */
+      chan_dir_to_port_dir_mapping[1] =  IN_PORT; /* DEC_DIRECTION => IN_PORT */
+
+      /* Build the Switch block: opin and opin_grid_side */
+      /* Assign grid side of OPIN */
+      /* Grid[x+1][y+1] BOTTOM side outputs pins */
+      opin_grid_side[0] = BOTTOM;
+      /* Grid[x+1][y] TOP side outputs pins */
+      opin_grid_side[1] = TOP;
+
+      /* include Grid[x+1][y+1] Bottom side output pins */
+      temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes(vpr_device_ctx.rr_graph, vpr_device_ctx.grid, 
+                                                       gsb_coord.x() + 1, gsb_coord.y() + 1, OPIN, opin_grid_side[0]);
+      /* include Grid[x+1][y] Top side output pins */
+      temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes(vpr_device_ctx.rr_graph, vpr_device_ctx.grid, 
+                                                       gsb_coord.x() + 1, gsb_coord.y(), OPIN, opin_grid_side[1]);
+      break;
+    case BOTTOM: /* BOTTOM = 2*/
+      /* For the border, we should take special care */
+      if (gsb_coord.y() == 0) {
+        rr_gsb.clear_one_side(side_manager.get_side());
+        break;
+      }
+      /* Routing channels*/
+      /* Side: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */
+      /* Collect rr_nodes for Tracks for bottom: chany[x][y] */
+      /* Create a rr_chan object and check if it is unique in the graph */
+      rr_chan = build_one_rr_chan(vpr_device_ctx, CHANY, coordinate);
+      chan_dir_to_port_dir_mapping[0] =  IN_PORT; /* INC_DIRECTION => IN_PORT */
+      chan_dir_to_port_dir_mapping[1] = OUT_PORT; /* DEC_DIRECTION => OUT_PORT */
+
+      /* Build the Switch block: opin and opin_grid_side */
+      /* Assign grid side of OPIN */
+      /* Grid[x+1][y] LEFT side outputs pins */
+      opin_grid_side[0] = LEFT;
+      /* Grid[x][y] RIGHT side outputs pins */
+      opin_grid_side[1] = RIGHT;
+      /* include Grid[x+1][y] Left side output pins */
+      temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes(vpr_device_ctx.rr_graph, vpr_device_ctx.grid, 
+                                                       gsb_coord.x() + 1, gsb_coord.y(), OPIN, opin_grid_side[0]);
+      /* include Grid[x][y] Right side output pins */
+      temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes(vpr_device_ctx.rr_graph, vpr_device_ctx.grid, 
+                                                       gsb_coord.x(), gsb_coord.y(), OPIN, opin_grid_side[1]);
+      break;
+    case LEFT: /* LEFT = 3 */
+      /* For the border, we should take special care */
+      if (gsb_coord.x() == 0) {
+        rr_gsb.clear_one_side(side_manager.get_side());
+        break;
+      }
+      /* Routing channels*/
+      /* Side: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */
+      /* Collect rr_nodes for Tracks for left: chanx[x][y] */
+      /* Create a rr_chan object and check if it is unique in the graph */
+      rr_chan = build_one_rr_chan(vpr_device_ctx, CHANX, coordinate);
+      chan_dir_to_port_dir_mapping[0] =  IN_PORT; /* INC_DIRECTION => IN_PORT */
+      chan_dir_to_port_dir_mapping[1] = OUT_PORT; /* DEC_DIRECTION => OUT_PORT */
+
+      /* Build the Switch block: opin and opin_grid_side */
+      /* Grid[x][y+1] BOTTOM side outputs pins */
+      opin_grid_side[0] = BOTTOM;
+      /* Grid[x][y] TOP side outputs pins */
+      opin_grid_side[1] = TOP;
+      /* include Grid[x][y+1] Bottom side outputs pins */
+      temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes(vpr_device_ctx.rr_graph, vpr_device_ctx.grid, 
+                                                       gsb_coord.x(), gsb_coord.y() + 1, OPIN, opin_grid_side[0]);
+      /* include Grid[x][y] Top side output pins */
+      temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes(vpr_device_ctx.rr_graph, vpr_device_ctx.grid, 
+                                                       gsb_coord.x(), gsb_coord.y(), OPIN, opin_grid_side[1]);
+      break;
+    default:
+      VTR_LOG_ERROR("Invalid side index!\n");
+      exit(1);
+    }
+
+    /* Organize a vector of port direction */
+    if (0 < rr_chan.get_chan_width()) {
+      std::vector<enum PORTS> rr_chan_dir;
+      rr_chan_dir.resize(rr_chan.get_chan_width());
+      for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) {
+        /* Identify the directionality, record it in rr_node_direction */
+        if (INC_DIRECTION == vpr_device_ctx.rr_graph.node_direction(rr_chan.get_node(itrack))) {
+          rr_chan_dir[itrack] = chan_dir_to_port_dir_mapping[0];
+        } else {
+          VTR_ASSERT(DEC_DIRECTION == vpr_device_ctx.rr_graph.node_direction(rr_chan.get_node(itrack)));
+          rr_chan_dir[itrack] = chan_dir_to_port_dir_mapping[1];
+        }
+      }
+      /* Fill chan_rr_nodes */
+      rr_gsb.add_chan_node(side_manager.get_side(), rr_chan, rr_chan_dir);
+    }
+
+    /* Fill opin_rr_nodes */
+    /* Copy from temp_opin_rr_node to opin_rr_node */
+    for (const RRNodeId& inode : temp_opin_rr_nodes[0]) {
+      /* Grid[x+1][y+1] Bottom side outputs pins */
+      rr_gsb.add_opin_node(inode, side_manager.get_side());
+    }
+    for (const RRNodeId& inode : temp_opin_rr_nodes[1]) {
+      /* Grid[x+1][y] TOP side outputs pins */
+      rr_gsb.add_opin_node(inode, side_manager.get_side());
+    }
+
+    /* Clean ipin_rr_nodes */
+    /* We do not have any IPIN for a Switch Block */
+    rr_gsb.clear_ipin_nodes(side_manager.get_side());
+
+    /* Clear the temp data */
+    temp_opin_rr_nodes[0].clear();
+    temp_opin_rr_nodes[1].clear();
+    opin_grid_side[0] = NUM_SIDES;
+    opin_grid_side[1] = NUM_SIDES;
+  }
+
+  /* Side: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */
+  for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
+    /* Local variables inside this for loop */
+    SideManager side_manager(side);
+    size_t ix; 
+    size_t iy; 
+    enum e_side chan_side;
+    std::vector<RRNodeId> temp_ipin_rr_nodes;
+    enum e_side ipin_rr_node_grid_side;
+   
+    switch (side) {
+    case TOP: /* TOP = 0 */
+      /* For the bording, we should take special care */
+      /* Check if left side chan width is 0 or not */
+      chan_side = LEFT;
+      /* Build the connection block: ipin and ipin_grid_side */
+      /* BOTTOM side INPUT Pins of Grid[x][y+1] */
+      ix = rr_gsb.get_sb_x(); 
+      iy = rr_gsb.get_sb_y() + 1; 
+      ipin_rr_node_grid_side = BOTTOM; 
+      break;
+    case RIGHT: /* RIGHT = 1 */
+      /* For the bording, we should take special care */
+      /* Check if TOP side chan width is 0 or not */
+      chan_side = TOP;
+      /* Build the connection block: ipin and ipin_grid_side */
+      /* LEFT side INPUT Pins of Grid[x+1][y+1] */
+      ix = rr_gsb.get_sb_x() + 1; 
+      iy = rr_gsb.get_sb_y() + 1; 
+      ipin_rr_node_grid_side = LEFT; 
+      break;
+    case BOTTOM: /* BOTTOM = 2*/
+      /* For the bording, we should take special care */
+      /* Check if left side chan width is 0 or not */
+      chan_side = LEFT;
+      /* Build the connection block: ipin and ipin_grid_side */
+      /* TOP side INPUT Pins of Grid[x][y] */
+      ix = rr_gsb.get_sb_x(); 
+      iy = rr_gsb.get_sb_y(); 
+      ipin_rr_node_grid_side = TOP; 
+      break;
+    case LEFT: /* LEFT = 3 */
+      /* For the bording, we should take special care */
+      /* Check if left side chan width is 0 or not */
+      chan_side = TOP;
+      /* Build the connection block: ipin and ipin_grid_side */
+      /* RIGHT side INPUT Pins of Grid[x][y+1] */
+      ix = rr_gsb.get_sb_x(); 
+      iy = rr_gsb.get_sb_y() + 1; 
+      ipin_rr_node_grid_side = RIGHT; 
+      break;
+    default:
+      VTR_LOG_ERROR("Invalid side index!\n");
+      exit(1);
+    }
+    
+    /* If there is no channel at this side, we skip ipin_node annotation */
+    if (0 == rr_gsb.get_chan_width(chan_side)) {
+      continue;
+    }
+    /* Collect IPIN rr_nodes*/ 
+    temp_ipin_rr_nodes = find_rr_graph_grid_nodes(vpr_device_ctx.rr_graph, vpr_device_ctx.grid, 
+                                                  ix, iy, IPIN, ipin_rr_node_grid_side);
+    /* Fill the ipin nodes of RRGSB */ 
+    for (const RRNodeId& inode : temp_ipin_rr_nodes) {
+      rr_gsb.add_ipin_node(inode, side_manager.get_side());
+    }
+    /* Clear the temp data */
+    temp_ipin_rr_nodes.clear();
+  }
+
+  return rr_gsb;
+}
+
+/********************************************************************
+ * Build the annotation for the routing resource graph
+ * by collecting the nodes to the General Switch Block context
+ *******************************************************************/
+void annotate_device_rr_gsb(const DeviceContext& vpr_device_ctx, 
+                            DeviceRRGSB& device_rr_gsb,
+                            const bool& verbose_output) {
+
+  vtr::ScopedStartFinishTimer timer("Build General Switch Block(GSB) annotation on top of routing resource graph");
+
+  /* Note that the GSB array is smaller than the grids by 1 column and 1 row!!! */
+  vtr::Point<size_t> gsb_range(vpr_device_ctx.grid.width() - 1, vpr_device_ctx.grid.height() - 1);
+  device_rr_gsb.reserve(gsb_range);
+
+  VTR_LOGV(verbose_output, 
+           "Start annotation GSB up to [%lu][%lu]\n",
+           gsb_range.x(), gsb_range.y());
+
+  size_t gsb_cnt = 0;
+  /* For each switch block, determine the size of array */
+  for (size_t ix = 0; ix < gsb_range.x(); ++ix) {
+    for (size_t iy = 0; iy < gsb_range.y(); ++iy) {
+      /* Here we give the builder the fringe coordinates so that it can handle the GSBs at the borderside correctly */
+      const RRGSB& rr_gsb = build_rr_gsb(vpr_device_ctx, 
+                                         vtr::Point<size_t>(vpr_device_ctx.grid.width() - 2, vpr_device_ctx.grid.height() - 2), 
+                                         vtr::Point<size_t>(ix, iy));
+      /* TODO: sort drive_rr_nodes should be done when building the tileable rr_graph? */
+      //sort_rr_gsb_drive_rr_nodes(rr_gsb);
+ 
+      /* Add to device_rr_gsb */
+      vtr::Point<size_t> gsb_coordinate = rr_gsb.get_sb_coordinate();
+      device_rr_gsb.add_rr_gsb(gsb_coordinate, rr_gsb);
+      gsb_cnt++; /* Update counter */
+      /* Print info */
+      VTR_LOG("[%lu%] Backannotated GSB[%lu][%lu]\r",
+              100 * gsb_cnt / (gsb_range.x() * gsb_range.y()), 
+              ix, iy);
+    }
+  }
+  /* Report number of unique mirrors */
+  VTR_LOG("Backannotated %d General Switch Blocks (GSBs).\n",
+          gsb_range.x() * gsb_range.y());
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/annotation/annotate_rr_gsb.h b/openfpga/src/annotation/annotate_rr_gsb.h
new file mode 100644
index 000000000..abf666c4a
--- /dev/null
+++ b/openfpga/src/annotation/annotate_rr_gsb.h
@@ -0,0 +1,24 @@
+#ifndef ANNOTATE_RR_GSB_H
+#define ANNOTATE_RR_GSB_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "vpr_context.h"
+#include "openfpga_context.h"
+#include "device_rr_gsb.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void annotate_device_rr_gsb(const DeviceContext& vpr_device_ctx, 
+                            DeviceRRGSB& device_rr_gsb,
+                            const bool& verbose_output);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/base/openfpga_context.h b/openfpga/src/base/openfpga_context.h
index 74e01d0de..743847114 100644
--- a/openfpga/src/base/openfpga_context.h
+++ b/openfpga/src/base/openfpga_context.h
@@ -7,6 +7,7 @@
 #include "vpr_pb_type_annotation.h"
 #include "vpr_clustering_annotation.h"
 #include "vpr_routing_annotation.h"
+#include "device_rr_gsb.h"
 
 /********************************************************************
  * This file includes the declaration of the date structure 
@@ -42,22 +43,32 @@ class OpenfpgaContext : public Context  {
     const openfpga::VprNetlistAnnotation& vpr_netlist_annotation() const { return vpr_netlist_annotation_; }
     const openfpga::VprClusteringAnnotation& vpr_clustering_annotation() const { return vpr_clustering_annotation_; }
     const openfpga::VprRoutingAnnotation& vpr_routing_annotation() const { return vpr_routing_annotation_; }
+    const openfpga::DeviceRRGSB& device_rr_gsb() const { return device_rr_gsb_; }
   public:  /* Public mutators */
     openfpga::Arch& mutable_arch() { return arch_; }
     openfpga::VprPbTypeAnnotation& mutable_vpr_pb_type_annotation() { return vpr_pb_type_annotation_; }
     openfpga::VprNetlistAnnotation& mutable_vpr_netlist_annotation() { return vpr_netlist_annotation_; }
     openfpga::VprClusteringAnnotation& mutable_vpr_clustering_annotation() { return vpr_clustering_annotation_; }
     openfpga::VprRoutingAnnotation& mutable_vpr_routing_annotation() { return vpr_routing_annotation_; }
+    openfpga::DeviceRRGSB& mutable_device_rr_gsb() { return device_rr_gsb_; }
   private: /* Internal data */
     /* Data structure to store information from read_openfpga_arch library */
     openfpga::Arch arch_;
+
     /* Annotation to pb_type of VPR */
     openfpga::VprPbTypeAnnotation vpr_pb_type_annotation_;
+
     /* Naming fix to netlist */
     openfpga::VprNetlistAnnotation vpr_netlist_annotation_;
+
     /* TODO: Pin net fix to cluster results */
     openfpga::VprClusteringAnnotation vpr_clustering_annotation_;
+
+    /* Routing results annotation */ 
     openfpga::VprRoutingAnnotation vpr_routing_annotation_;
+
+    /* Device-level annotation */
+    openfpga::DeviceRRGSB device_rr_gsb_;
 };
 
 #endif
diff --git a/openfpga/src/base/openfpga_link_arch.cpp b/openfpga/src/base/openfpga_link_arch.cpp
index dee7662a6..2519be57a 100644
--- a/openfpga/src/base/openfpga_link_arch.cpp
+++ b/openfpga/src/base/openfpga_link_arch.cpp
@@ -12,6 +12,7 @@
 #include "annotate_pb_types.h"
 #include "annotate_pb_graph.h"
 #include "annotate_routing.h"
+#include "annotate_rr_gsb.h"
 #include "openfpga_link_arch.h"
 
 /* Include global variables of VPR */
@@ -60,6 +61,14 @@ void link_arch(OpenfpgaContext& openfpga_context,
   annotate_rr_node_nets(g_vpr_ctx.device(), g_vpr_ctx.clustering(), g_vpr_ctx.routing(), 
                         openfpga_context.mutable_vpr_routing_annotation(),
                         cmd_context.option_enable(cmd, opt_verbose));
+
+  /* Build the routing graph annotation
+   * - RRGSB
+   * - DeviceRRGSB 
+   */
+  annotate_device_rr_gsb(g_vpr_ctx.device(),
+                         openfpga_context.mutable_device_rr_gsb(),
+                         cmd_context.option_enable(cmd, opt_verbose));
 } 
 
 } /* end namespace openfpga */
diff --git a/vpr/src/device/rr_graph_obj_util.cpp b/vpr/src/device/rr_graph_obj_util.cpp
index 373c48fa1..a155eec8f 100644
--- a/vpr/src/device/rr_graph_obj_util.cpp
+++ b/vpr/src/device/rr_graph_obj_util.cpp
@@ -32,7 +32,7 @@ std::vector<RRSwitchId> find_rr_graph_switches(const RRGraph& rr_graph,
 /*********************************************************************
  * Like the RRGraph.find_node() but returns all matching nodes,
  * rather than just the first. This is particularly useful for getting all instances
- * of a specific IPIN/OPIN at a specific gird tile (x,y) location.
+ * of a specific IPIN/OPIN at a specific grid tile (x,y) location.
  **********************************************************************/
 std::vector<RRNodeId> find_rr_graph_nodes(const RRGraph& rr_graph,
                                           const int& x,
@@ -63,6 +63,9 @@ std::vector<RRNodeId> find_rr_graph_nodes(const RRGraph& rr_graph,
     return indices;
 }
 
+/*********************************************************************
+ * Find a list of rr nodes in a routing channel at (x,y)
+ **********************************************************************/
 std::vector<RRNodeId> find_rr_graph_chan_nodes(const RRGraph& rr_graph,
                                                const int& x,
                                                const int& y,
@@ -81,3 +84,46 @@ std::vector<RRNodeId> find_rr_graph_chan_nodes(const RRGraph& rr_graph,
 
     return indices;
 }
+
+/*********************************************************************
+ * Find a list of rr_nodes that locate at a side of a grid
+ **********************************************************************/
+std::vector<RRNodeId> find_rr_graph_grid_nodes(const RRGraph& rr_graph,
+                                               const DeviceGrid& device_grid,
+                                               const int& x,
+                                               const int& y,
+                                               const t_rr_type& rr_type,
+                                               const e_side& side) {
+    std::vector<RRNodeId> indices;
+
+    VTR_ASSERT(rr_type == IPIN || rr_type == OPIN);
+    
+    /* Ensure that (x, y) is a valid location in grids */ 
+    VTR_ASSERT(size_t(x) <= device_grid.width() && size_t(y) <= device_grid.height());
+
+    /* Ensure we have a valid side */
+    VTR_ASSERT(side != NUM_SIDES);
+    
+    /* Find all the pins on the side of the grid */ 
+    int width_offset = device_grid[x][y].width_offset;
+    int height_offset = device_grid[x][y].height_offset;
+    for (int pin = 0; pin < device_grid[x][y].type->num_pins; ++pin) {
+        /* Skip those pins have been ignored during rr_graph build-up */
+        if (true == device_grid[x][y].type->is_ignored_pin[pin]) {
+            continue;
+        }
+        if (false == device_grid[x][y].type->pinloc[width_offset][height_offset][side][pin]) {
+            /* Not the pin on this side, we skip */
+            continue;
+        }
+        /* Try to find the rr node */
+        RRNodeId rr_node_index = rr_graph.find_node(x, y, rr_type, pin, side);
+        if (rr_node_index != RRNodeId::INVALID()) {
+            indices.push_back(rr_node_index);
+        }
+    }
+
+
+    return indices;
+}
+
diff --git a/vpr/src/device/rr_graph_obj_util.h b/vpr/src/device/rr_graph_obj_util.h
index 71d97dcf9..01f753ddc 100644
--- a/vpr/src/device/rr_graph_obj_util.h
+++ b/vpr/src/device/rr_graph_obj_util.h
@@ -6,6 +6,7 @@
  */
 #include <vector>
 #include "rr_graph_obj.h"
+#include "device_grid.h"
 
 /* Get node-to-node switches in a RRGraph */
 std::vector<RRSwitchId> find_rr_graph_switches(const RRGraph& rr_graph,
@@ -23,5 +24,12 @@ std::vector<RRNodeId> find_rr_graph_chan_nodes(const RRGraph& rr_graph,
                                                const int& y,
                                                const t_rr_type& rr_type);
 
+std::vector<RRNodeId> find_rr_graph_grid_nodes(const RRGraph& rr_graph,
+                                               const DeviceGrid& device_grid,
+                                               const int& x,
+                                               const int& y,
+                                               const t_rr_type& rr_type,
+                                               const e_side& side);
+
 
 #endif

From 175bef014a9f8c8850264fef4c23d1e64f3519b3 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 11 Feb 2020 17:40:37 -0700
Subject: [PATCH 114/645] add compact_routing hierarchy command

---
 openfpga/src/annotation/annotate_rr_gsb.cpp   |  2 +-
 openfpga/src/annotation/device_rr_gsb.cpp     | 23 +++++++
 openfpga/src/annotation/device_rr_gsb.h       |  1 +
 openfpga/src/annotation/rr_gsb.cpp            | 15 ++++
 openfpga/src/annotation/rr_gsb.h              |  5 +-
 .../src/base/compact_routing_hierarchy.cpp    | 60 ++++++++++++++++
 openfpga/src/base/compact_routing_hierarchy.h | 23 +++++++
 openfpga/src/base/openfpga_setup_command.cpp  | 20 +++++-
 openfpga/src/utils/device_rr_gsb_utils.cpp    | 68 +++++++++++++++++++
 openfpga/src/utils/device_rr_gsb_utils.h      | 27 ++++++++
 openfpga/test_script/s298_k6_frac.openfpga    |  3 +
 11 files changed, 244 insertions(+), 3 deletions(-)
 create mode 100644 openfpga/src/base/compact_routing_hierarchy.cpp
 create mode 100644 openfpga/src/base/compact_routing_hierarchy.h
 create mode 100644 openfpga/src/utils/device_rr_gsb_utils.cpp
 create mode 100644 openfpga/src/utils/device_rr_gsb_utils.h

diff --git a/openfpga/src/annotation/annotate_rr_gsb.cpp b/openfpga/src/annotation/annotate_rr_gsb.cpp
index 8050110e5..dca399abd 100644
--- a/openfpga/src/annotation/annotate_rr_gsb.cpp
+++ b/openfpga/src/annotation/annotate_rr_gsb.cpp
@@ -374,7 +374,7 @@ void annotate_device_rr_gsb(const DeviceContext& vpr_device_ctx,
       const RRGSB& rr_gsb = build_rr_gsb(vpr_device_ctx, 
                                          vtr::Point<size_t>(vpr_device_ctx.grid.width() - 2, vpr_device_ctx.grid.height() - 2), 
                                          vtr::Point<size_t>(ix, iy));
-      /* TODO: sort drive_rr_nodes should be done when building the tileable rr_graph? */
+      /* TODO: sort drive_rr_nodes should be done when building the tileable rr_graph */
       //sort_rr_gsb_drive_rr_nodes(rr_gsb);
  
       /* Add to device_rr_gsb */
diff --git a/openfpga/src/annotation/device_rr_gsb.cpp b/openfpga/src/annotation/device_rr_gsb.cpp
index 9152f209c..6fa808823 100644
--- a/openfpga/src/annotation/device_rr_gsb.cpp
+++ b/openfpga/src/annotation/device_rr_gsb.cpp
@@ -53,6 +53,29 @@ size_t DeviceRRGSB::get_num_cb_unique_module(const t_rr_type& cb_type) const {
   }
 } 
 
+/* Identify if a GSB actually exists at a location */
+bool DeviceRRGSB::is_gsb_exist(const vtr::Point<size_t> coord) const {
+  /* Out of range, does not exist */
+  if (false == validate_coordinate(coord)) {
+    return false;
+  }
+
+  /* If the GSB is empty, it does not exist */
+  if (true == get_gsb(coord).is_cb_exist(CHANX)) {
+    return true;
+  }
+
+  if (true == get_gsb(coord).is_cb_exist(CHANY)) {
+    return true;
+  }
+
+  if (true == get_gsb(coord).is_sb_exist()) {
+    return true;
+  }
+
+  return false;
+}
+
 /* get the number of unique mirrors of switch blocks */
 size_t DeviceRRGSB::get_num_sb_unique_module() const {
   return sb_unique_module_.size();
diff --git a/openfpga/src/annotation/device_rr_gsb.h b/openfpga/src/annotation/device_rr_gsb.h
index 624492124..eae0afa1d 100644
--- a/openfpga/src/annotation/device_rr_gsb.h
+++ b/openfpga/src/annotation/device_rr_gsb.h
@@ -37,6 +37,7 @@ class DeviceRRGSB {
     const RRGSB& get_cb_unique_module(const t_rr_type& cb_type, const size_t& index) const; /* Get a rr switch block which a unique mirror */ 
     const RRGSB& get_cb_unique_module(const t_rr_type& cb_type, const vtr::Point<size_t>& coordinate) const;
     size_t get_num_cb_unique_module(const t_rr_type& cb_type) const; /* get the number of unique mirrors of CBs */
+    bool is_gsb_exist(const vtr::Point<size_t> coord) const;
   public: /* Mutators */ 
     void reserve(const vtr::Point<size_t>& coordinate); /* Pre-allocate the rr_switch_block array that the device requires */ 
     void reserve_sb_unique_submodule_id(const vtr::Point<size_t>& coordinate); /* Pre-allocate the rr_sb_unique_module_id matrix that the device requires */ 
diff --git a/openfpga/src/annotation/rr_gsb.cpp b/openfpga/src/annotation/rr_gsb.cpp
index 6b8cd5236..cd57d8e6b 100644
--- a/openfpga/src/annotation/rr_gsb.cpp
+++ b/openfpga/src/annotation/rr_gsb.cpp
@@ -348,6 +348,21 @@ bool RRGSB::is_cb_exist(const t_rr_type& cb_type) const {
   return (0 != get_cb_chan_width(cb_type));
 } 
 
+/* check if the SB exist in this GSB */
+bool RRGSB::is_sb_exist() const {
+  /* if all the channel width is zero and number of OPINs are zero, there is no SB */
+  for (size_t side = 0; side < get_num_sides(); ++side) {
+    SideManager side_manager(side);
+    if (0 != get_chan_width(side_manager.get_side())) {
+      return true;
+    }
+    if (0 != get_num_opin_nodes(side_manager.get_side())) {
+      return true;
+    }
+  }
+
+  return false;
+} 
 
 /************************************************************************
  * Check if the node indicates a passing wire across the Switch Block part of the GSB 
diff --git a/openfpga/src/annotation/rr_gsb.h b/openfpga/src/annotation/rr_gsb.h
index 4f3af9552..4541c88dd 100644
--- a/openfpga/src/annotation/rr_gsb.h
+++ b/openfpga/src/annotation/rr_gsb.h
@@ -114,9 +114,12 @@ class RRGSB {
     /* check if the candidate SB is a mirror of the current one */
     bool is_cb_mirror(const RRGraph& rr_graph, const RRGSB& cand, const t_rr_type& cb_type) const; 
 
-    /* check if the candidate SB is a mirror of the current one */
+    /* check if the connect block exists in the GSB */
     bool is_cb_exist(const t_rr_type& cb_type) const;
 
+    /* check if the switch block exists in the GSB */
+    bool is_sb_exist() const;
+
     /* Check if the node imply a short connection inside the SB, which happens to long wires across a FPGA fabric */
     bool is_sb_node_passing_wire(const RRGraph& rr_graph, const e_side& node_side, const size_t& track_id) const; 
 
diff --git a/openfpga/src/base/compact_routing_hierarchy.cpp b/openfpga/src/base/compact_routing_hierarchy.cpp
new file mode 100644
index 000000000..e520b5e3f
--- /dev/null
+++ b/openfpga/src/base/compact_routing_hierarchy.cpp
@@ -0,0 +1,60 @@
+/********************************************************************
+ * This file includes functions to compress the hierachy of routing architecture
+ *******************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_time.h"
+#include "vtr_log.h"
+
+#include "device_rr_gsb.h"
+#include "device_rr_gsb_utils.h"
+#include "compact_routing_hierarchy.h"
+
+/* Include global variables of VPR */
+#include "globals.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Identify the unique GSBs from the Device RR GSB arrays
+ * This function should only be called after the GSB builder is done
+ *******************************************************************/
+void compact_routing_hierarchy(OpenfpgaContext& openfpga_context,
+                               const Command& cmd, const CommandContext& cmd_context) { 
+  vtr::ScopedStartFinishTimer timer("Identify unique General Switch Blocks (GSBs)");
+
+  CommandOptionId opt_verbose = cmd.option("verbose");
+
+  /* Build unique module lists */
+  openfpga_context.mutable_device_rr_gsb().build_unique_module(g_vpr_ctx.device().rr_graph);
+
+  bool verbose_output = cmd_context.option_enable(cmd, opt_verbose);
+
+  /* Report the stats */
+  VTR_LOGV(verbose_output, 
+           "Detected %lu unique X-direction connection blocks from a total of %d (compression rate=%d%)\n",
+           openfpga_context.device_rr_gsb().get_num_cb_unique_module(CHANX),
+           find_device_rr_gsb_num_cb_modules(openfpga_context.device_rr_gsb(), CHANX),
+           100 * (openfpga_context.device_rr_gsb().get_num_cb_unique_module(CHANX) / find_device_rr_gsb_num_cb_modules(openfpga_context.device_rr_gsb(), CHANX) - 1));
+
+  VTR_LOGV(verbose_output,
+           "Detected %lu unique Y-direction connection blocks from a total of %d (compression rate=%d%)\n",
+           openfpga_context.device_rr_gsb().get_num_cb_unique_module(CHANY),
+           find_device_rr_gsb_num_cb_modules(openfpga_context.device_rr_gsb(), CHANY),
+           100 * (openfpga_context.device_rr_gsb().get_num_cb_unique_module(CHANY) / find_device_rr_gsb_num_cb_modules(openfpga_context.device_rr_gsb(), CHANY) - 1));
+
+  VTR_LOGV(verbose_output,
+           "Detected %lu unique switch blocks from a total of %d (compression rate=%d%)\n",
+           openfpga_context.device_rr_gsb().get_num_sb_unique_module(),
+           find_device_rr_gsb_num_sb_modules(openfpga_context.device_rr_gsb()),
+           100 * (openfpga_context.device_rr_gsb().get_num_sb_unique_module() / find_device_rr_gsb_num_sb_modules(openfpga_context.device_rr_gsb()) - 1));
+
+  VTR_LOGV(verbose_output,
+           "Detected %lu unique general switch blocks from a total of %d (compression rate=%d%)\n",
+           openfpga_context.device_rr_gsb().get_num_gsb_unique_module(),
+           find_device_rr_gsb_num_gsb_modules(openfpga_context.device_rr_gsb()),
+           100 * (openfpga_context.device_rr_gsb().get_num_gsb_unique_module() / find_device_rr_gsb_num_gsb_modules(openfpga_context.device_rr_gsb()) - 1));
+
+} 
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/base/compact_routing_hierarchy.h b/openfpga/src/base/compact_routing_hierarchy.h
new file mode 100644
index 000000000..bd3eeefe2
--- /dev/null
+++ b/openfpga/src/base/compact_routing_hierarchy.h
@@ -0,0 +1,23 @@
+#ifndef COMPACT_ROUTING_HIERARCHY_H
+#define COMPACT_ROUTING_HIERARCHY_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "command.h"
+#include "command_context.h"
+#include "openfpga_context.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void compact_routing_hierarchy(OpenfpgaContext& openfpga_context,
+                               const Command& cmd, const CommandContext& cmd_context); 
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/base/openfpga_setup_command.cpp b/openfpga/src/base/openfpga_setup_command.cpp
index 629300bf2..2d08ec38c 100644
--- a/openfpga/src/base/openfpga_setup_command.cpp
+++ b/openfpga/src/base/openfpga_setup_command.cpp
@@ -8,6 +8,8 @@
 #include "openfpga_pb_pin_fixup.h"
 #include "openfpga_lut_truth_table_fixup.h"
 #include "check_netlist_naming_conflict.h"
+#include "annotate_rr_gsb.h"
+#include "compact_routing_hierarchy.h"
 #include "openfpga_setup_command.h"
 
 /* begin namespace openfpga */
@@ -113,11 +115,27 @@ void add_openfpga_setup_commands(openfpga::Shell<OpenfpgaContext>& shell) {
   ShellCommandId shell_cmd_lut_truth_table_fixup_id = shell.add_command(shell_cmd_lut_truth_table_fixup, "Fix up the truth table of Look-Up Tables due to pin swapping during packing stage");
   shell.set_command_class(shell_cmd_lut_truth_table_fixup_id, openfpga_setup_cmd_class);
   shell.set_command_execute_function(shell_cmd_lut_truth_table_fixup_id, lut_truth_table_fixup);
-  /* The 'pb_pin_fixup' command should NOT be executed before 'read_openfpga_arch' and 'vpr' */
+  /* The 'lut_truth_table_fixup' command should NOT be executed before 'read_openfpga_arch' and 'vpr' */
   std::vector<ShellCommandId> cmd_dependency_lut_truth_table_fixup;
   cmd_dependency_lut_truth_table_fixup.push_back(shell_cmd_read_arch_id);
   cmd_dependency_lut_truth_table_fixup.push_back(shell_cmd_vpr_id);
   shell.set_command_dependency(shell_cmd_lut_truth_table_fixup_id, cmd_dependency_lut_truth_table_fixup);
+
+  /******************************** 
+   * Command 'compact_routing_hierarchy' 
+   */
+  Command shell_cmd_compact_routing_hierarchy("compact_routing_hierarchy");
+  /* Add an option '--verbose' */
+  shell_cmd_compact_routing_hierarchy.add_option("verbose", false, "Show verbose outputs");
+
+  /* Add command 'compact_routing_hierarchy' to the Shell */
+  ShellCommandId shell_cmd_compact_routing_hierarchy_id = shell.add_command(shell_cmd_compact_routing_hierarchy, "Identify the unique GSBs in the routing architecture so that the routing hierarchy of fabric can be compressed");
+  shell.set_command_class(shell_cmd_compact_routing_hierarchy_id, openfpga_setup_cmd_class);
+  shell.set_command_execute_function(shell_cmd_compact_routing_hierarchy_id, compact_routing_hierarchy);
+  /* The 'compact_routing_hierarchy' command should NOT be executed before 'link_openfpga_arch' */
+  std::vector<ShellCommandId> cmd_dependency_compact_routing_hierarchy;
+  cmd_dependency_lut_truth_table_fixup.push_back(shell_cmd_link_openfpga_arch_id);
+  shell.set_command_dependency(shell_cmd_compact_routing_hierarchy_id, cmd_dependency_compact_routing_hierarchy);
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/utils/device_rr_gsb_utils.cpp b/openfpga/src/utils/device_rr_gsb_utils.cpp
new file mode 100644
index 000000000..dfda5618a
--- /dev/null
+++ b/openfpga/src/utils/device_rr_gsb_utils.cpp
@@ -0,0 +1,68 @@
+/********************************************************************
+ * This file includes most utilized functions for data structure
+ * DeviceRRGSB
+ *******************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+#include "device_rr_gsb_utils.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * This function aims to find out the number of connection block
+ * modules in the device rr_gsb array
+ *******************************************************************/
+size_t find_device_rr_gsb_num_cb_modules(const DeviceRRGSB& device_rr_gsb,
+                                         const t_rr_type& cb_type) {
+  size_t counter = 0;
+  for (size_t x = 0; x < device_rr_gsb.get_gsb_range().x(); ++x) { 
+    for (size_t y = 0; y < device_rr_gsb.get_gsb_range().y(); ++y) { 
+      const RRGSB& rr_gsb = device_rr_gsb.get_gsb(x, y);
+      if (true == rr_gsb.is_cb_exist(cb_type)) {
+        counter++;
+      }
+    }
+  }
+
+  return counter;
+}
+
+/********************************************************************
+ * This function aims to find out the number of switch block
+ * modules in the device rr_gsb array
+ *******************************************************************/
+size_t find_device_rr_gsb_num_sb_modules(const DeviceRRGSB& device_rr_gsb) {
+  size_t counter = 0;
+  for (size_t x = 0; x < device_rr_gsb.get_gsb_range().x(); ++x) { 
+    for (size_t y = 0; y < device_rr_gsb.get_gsb_range().y(); ++y) { 
+      const RRGSB& rr_gsb = device_rr_gsb.get_gsb(x, y);
+      if (true == rr_gsb.is_sb_exist()) {
+        counter++;
+      }
+    }
+  }
+
+  return counter;
+}
+
+/********************************************************************
+ * This function aims to find out the number of GSBs
+ *******************************************************************/
+size_t find_device_rr_gsb_num_gsb_modules(const DeviceRRGSB& device_rr_gsb) {
+  size_t counter = 0;
+  for (size_t x = 0; x < device_rr_gsb.get_gsb_range().x(); ++x) { 
+    for (size_t y = 0; y < device_rr_gsb.get_gsb_range().y(); ++y) { 
+      if (true == device_rr_gsb.is_gsb_exist(vtr::Point<size_t>(x, y))) {
+        counter++;
+      }
+    }
+  }
+
+  return counter;
+
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/utils/device_rr_gsb_utils.h b/openfpga/src/utils/device_rr_gsb_utils.h
new file mode 100644
index 000000000..7b49839a9
--- /dev/null
+++ b/openfpga/src/utils/device_rr_gsb_utils.h
@@ -0,0 +1,27 @@
+#ifndef DEVICE_RR_GSB_UTILS_H
+#define DEVICE_RR_GSB_UTILS_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <string>
+#include <vector>
+#include "device_rr_gsb.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+size_t find_device_rr_gsb_num_cb_modules(const DeviceRRGSB& device_rr_gsb,
+                                         const t_rr_type& cb_type);
+
+size_t find_device_rr_gsb_num_sb_modules(const DeviceRRGSB& device_rr_gsb);
+
+size_t find_device_rr_gsb_num_gsb_modules(const DeviceRRGSB& device_rr_gsb);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/test_script/s298_k6_frac.openfpga b/openfpga/test_script/s298_k6_frac.openfpga
index f4a5bc979..dd87c77df 100644
--- a/openfpga/test_script/s298_k6_frac.openfpga
+++ b/openfpga/test_script/s298_k6_frac.openfpga
@@ -16,5 +16,8 @@ pb_pin_fixup --verbose
 # Apply fix-up to Look-Up Table truth tables based on packing results
 lut_truth_table_fixup --verbose
 
+# Compress the routing hierarchy
+compact_routing_hierarchy --verbose
+
 # Finish and exit OpenFPGA
 exit

From 4367dba9b713b5734aa6641770dd0b8b9d52bd90 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 11 Feb 2020 21:02:58 -0700
Subject: [PATCH 115/645] move mux graph and decoder builders to vpr8
 integration; ready to link the rr_switch to circuit models

---
 openfpga/src/mux_lib/decoder_library.cpp     |  109 ++
 openfpga/src/mux_lib/decoder_library.h       |   95 ++
 openfpga/src/mux_lib/decoder_library_fwd.h   |   23 +
 openfpga/src/mux_lib/mux_graph.cpp           | 1254 ++++++++++++++++++
 openfpga/src/mux_lib/mux_graph.h             |  213 +++
 openfpga/src/mux_lib/mux_graph_fwd.h         |   33 +
 openfpga/src/mux_lib/mux_library.cpp         |  121 ++
 openfpga/src/mux_lib/mux_library.h           |   64 +
 openfpga/src/mux_lib/mux_library_fwd.h       |   25 +
 openfpga/src/utils/decoder_library_utils.cpp |   60 +
 openfpga/src/utils/decoder_library_utils.h   |   21 +
 openfpga/src/utils/mux_utils.cpp             |  458 +++++++
 openfpga/src/utils/mux_utils.h               |   59 +
 13 files changed, 2535 insertions(+)
 create mode 100644 openfpga/src/mux_lib/decoder_library.cpp
 create mode 100644 openfpga/src/mux_lib/decoder_library.h
 create mode 100644 openfpga/src/mux_lib/decoder_library_fwd.h
 create mode 100644 openfpga/src/mux_lib/mux_graph.cpp
 create mode 100644 openfpga/src/mux_lib/mux_graph.h
 create mode 100644 openfpga/src/mux_lib/mux_graph_fwd.h
 create mode 100644 openfpga/src/mux_lib/mux_library.cpp
 create mode 100644 openfpga/src/mux_lib/mux_library.h
 create mode 100644 openfpga/src/mux_lib/mux_library_fwd.h
 create mode 100644 openfpga/src/utils/decoder_library_utils.cpp
 create mode 100644 openfpga/src/utils/decoder_library_utils.h
 create mode 100644 openfpga/src/utils/mux_utils.cpp
 create mode 100644 openfpga/src/utils/mux_utils.h

diff --git a/openfpga/src/mux_lib/decoder_library.cpp b/openfpga/src/mux_lib/decoder_library.cpp
new file mode 100644
index 000000000..a7c4a8840
--- /dev/null
+++ b/openfpga/src/mux_lib/decoder_library.cpp
@@ -0,0 +1,109 @@
+/***************************************************************************************
+ * This file includes memeber functions for data structure DecoderLibrary
+ **************************************************************************************/
+#include "vtr_assert.h"
+#include "decoder_library.h"
+
+/* Begin namespace openfpga */
+namespace openfpga {
+
+/***************************************************************************************
+ * Public Accessors: Aggregators
+ **************************************************************************************/
+DecoderLibrary::decoder_range DecoderLibrary::decoders() const {
+  return vtr::make_range(decoder_ids_.begin(), decoder_ids_.end());
+}
+
+/***************************************************************************************
+ * Public Accessors: Data query 
+ **************************************************************************************/
+/* Get the size of address input of a decoder */
+size_t DecoderLibrary::addr_size(const DecoderId& decoder) const {
+  VTR_ASSERT_SAFE(valid_decoder_id(decoder));
+  return addr_sizes_[decoder];
+}
+
+/* Get the size of data output of a decoder */
+size_t DecoderLibrary::data_size(const DecoderId& decoder) const { 
+  VTR_ASSERT_SAFE(valid_decoder_id(decoder));
+  return data_sizes_[decoder];
+}
+
+/* Get the flag if a decoder includes an ENABLE signal */
+bool DecoderLibrary::use_enable(const DecoderId& decoder) const {
+  VTR_ASSERT_SAFE(valid_decoder_id(decoder));
+  return use_enable_[decoder];
+}
+
+/* Get the flag if a decoder includes an DATA_IN signal */
+bool DecoderLibrary::use_data_in(const DecoderId& decoder) const {
+  VTR_ASSERT_SAFE(valid_decoder_id(decoder));
+  return use_data_in_[decoder];
+}
+
+/* Get the flag if a decoder includes a data_inv port which is an inversion of the regular data output port */
+bool DecoderLibrary::use_data_inv_port(const DecoderId& decoder) const {
+  VTR_ASSERT_SAFE(valid_decoder_id(decoder));
+  return use_data_inv_port_[decoder];
+}
+
+/* Find a decoder to the library, with the specification.
+ * If found, return the id of decoder.
+ * If not found, return an invalid id of decoder
+ * To avoid duplicated decoders, this function should be used before adding a decoder 
+ * Example: 
+ *   DecoderId decoder_id == decoder_lib.find_decoder();
+ *   if (DecoderId::INVALID() == decoder_id) {
+ *     // Add decoder
+ *   } 
+ */
+DecoderId DecoderLibrary::find_decoder(const size_t& addr_size, 
+                                       const size_t& data_size, 
+                                       const bool& use_enable, 
+                                       const bool& use_data_in, 
+                                       const bool& use_data_inv_port) const {
+  for (auto decoder : decoders()) {
+    if (  (addr_size == addr_sizes_[decoder])
+       && (data_size == data_sizes_[decoder])
+       && (use_enable == use_enable_[decoder])
+       && (use_data_in == use_data_in_[decoder])
+       && (use_data_inv_port == use_data_inv_port_[decoder]) ) {
+      return decoder;
+    }
+  }
+
+  /* Not found, return an invalid id by default */
+  return DecoderId::INVALID();
+}
+
+/***************************************************************************************
+ * Public Validators
+ **************************************************************************************/
+/* Validate ids */
+bool DecoderLibrary::valid_decoder_id(const DecoderId& decoder) const {
+  return size_t(decoder) < decoder_ids_.size() && decoder_ids_[decoder] == decoder;
+}
+
+/***************************************************************************************
+ * Public Mutators : Basic Operations 
+ **************************************************************************************/
+/* Add a decoder to the library */
+DecoderId DecoderLibrary::add_decoder(const size_t& addr_size, 
+                                      const size_t& data_size, 
+                                      const bool& use_enable, 
+                                      const bool& use_data_in, 
+                                      const bool& use_data_inv_port) {
+  DecoderId decoder = DecoderId(decoder_ids_.size());
+  /* Push to the decoder list */
+  decoder_ids_.push_back(decoder);
+  /* Resize the other related vectors */
+  addr_sizes_.push_back(addr_size);
+  data_sizes_.push_back(data_size);
+  use_enable_.push_back(use_enable);
+  use_data_in_.push_back(use_data_in);
+  use_data_inv_port_.push_back(use_data_inv_port);
+
+  return decoder;
+}
+
+} /* End namespace openfpga*/
diff --git a/openfpga/src/mux_lib/decoder_library.h b/openfpga/src/mux_lib/decoder_library.h
new file mode 100644
index 000000000..397308db5
--- /dev/null
+++ b/openfpga/src/mux_lib/decoder_library.h
@@ -0,0 +1,95 @@
+/***************************************************************************************
+ * This file includes key data structures to describe decoders which are used
+ * in FPGA fabrics 
+ * A decoder is a circuit to convert a binary input to one-hot codes
+ * The outputs are assumes to be one-hot codes (at most only one '1' exist)
+ * Therefore, the number of inputs is ceil(log(num_of_outputs)/log(2))
+ * All the decoders are assumed to follow the port map : 
+ *
+ *                     Inputs 
+ *                   | | ... | 
+ *                   v v     v
+ *                 +-----------+
+ *                /             \
+ *               /    Decoder    \
+ *              +-----------------+
+ *                | | | ... | | |
+ *                v v v     v v v
+ *                    Outputs
+
+ ***************************************************************************************/
+
+#ifndef DECODER_LIBRARY_H
+#define DECODER_LIBRARY_H
+
+#include "vtr_vector.h"
+#include "vtr_range.h"
+#include "decoder_library_fwd.h"
+
+/* Begin namespace openfpga */
+namespace openfpga {
+
+class DecoderLibrary {
+  public: /* Types and ranges */
+    typedef vtr::vector<DecoderId, DecoderId>::const_iterator decoder_iterator;
+
+    typedef vtr::Range<decoder_iterator> decoder_range;
+
+  public: /* Public accessors: Aggregates */
+    /* Get all the decoders */
+    decoder_range decoders() const;
+
+  public: /* Public accessors: Data query */
+    /* Get the size of address input of a decoder */
+    size_t addr_size(const DecoderId& decoder) const;
+    /* Get the size of data output of a decoder */
+    size_t data_size(const DecoderId& decoder) const;
+    /* Get the flag if a decoder includes an ENABLE signal */
+    bool use_enable(const DecoderId& decoder) const;
+    /* Get the flag if a decoder includes an DATA_IN signal */
+    bool use_data_in(const DecoderId& decoder) const;
+    /* Get the flag if a decoder includes a data_inv port which is an inversion of the regular data output port */
+    bool use_data_inv_port(const DecoderId& decoder) const;
+    /* Find a decoder to the library, with the specification.
+     * If found, return the id of decoder.
+     * If not found, return an invalid id of decoder
+     * To avoid duplicated decoders, this function should be used before adding a decoder 
+     * Example: 
+     *   DecoderId decoder_id == decoder_lib.find_decoder();
+     *   if (DecoderId::INVALID() == decoder_id) {
+     *     // Add decoder
+     *   } 
+     */
+    DecoderId find_decoder(const size_t& addr_size, 
+                           const size_t& data_size, 
+                           const bool& use_enable, 
+                           const bool& use_data_in, 
+                           const bool& use_data_inv_port) const;
+
+  public: /* Public validators */
+    /* valid ids */
+    bool valid_decoder_id(const DecoderId& decoder) const;
+
+  public: /* Private mutators : basic operations */
+    /* Add a decoder to the library */
+    DecoderId add_decoder(const size_t& addr_size, 
+                          const size_t& data_size, 
+                          const bool& use_enable, 
+                          const bool& use_data_in, 
+                          const bool& use_data_inv_port);
+    
+  private: /* Internal Data */
+    vtr::vector<DecoderId, DecoderId> decoder_ids_;
+    vtr::vector<DecoderId, size_t> addr_sizes_;
+    vtr::vector<DecoderId, size_t> data_sizes_;
+    vtr::vector<DecoderId, bool> use_enable_;
+    vtr::vector<DecoderId, bool> use_data_in_;
+    vtr::vector<DecoderId, bool> use_data_inv_port_;
+};
+
+} /* End namespace openfpga*/
+
+
+
+#endif
+
diff --git a/openfpga/src/mux_lib/decoder_library_fwd.h b/openfpga/src/mux_lib/decoder_library_fwd.h
new file mode 100644
index 000000000..e56a7ce82
--- /dev/null
+++ b/openfpga/src/mux_lib/decoder_library_fwd.h
@@ -0,0 +1,23 @@
+/**************************************************
+ * This file includes only declarations for 
+ * the data structures to describe decoders
+ * Please refer to decoder_library.h for more details
+ *************************************************/
+#ifndef DECODER_LIBRARY_FWD_H
+#define DECODER_LIBRARY_FWD_H
+
+#include "vtr_strong_id.h"
+
+/* Begin namespace openfpga */
+namespace openfpga {
+
+/* Strong Ids for MUXes */
+struct decoder_id_tag;
+
+typedef vtr::StrongId<decoder_id_tag> DecoderId;
+
+class DecoderLibrary;
+
+} /* End namespace openfpga*/
+
+#endif 
diff --git a/openfpga/src/mux_lib/mux_graph.cpp b/openfpga/src/mux_lib/mux_graph.cpp
new file mode 100644
index 000000000..5b0f81828
--- /dev/null
+++ b/openfpga/src/mux_lib/mux_graph.cpp
@@ -0,0 +1,1254 @@
+/**************************************************
+ * This file includes member functions for the 
+ * data structures in mux_graph.h
+ *************************************************/
+#include <cmath>
+#include <list>
+#include <map>
+#include <algorithm>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+#include "mux_utils.h"
+#include "mux_graph.h"
+
+/* Begin namespace openfpga */
+namespace openfpga {
+
+/**************************************************
+ * Member functions for the class MuxGraph
+ *************************************************/
+
+/**************************************************
+ * Public Constructors 
+ *************************************************/
+
+/* Create an object based on a Circuit Model which is MUX */
+MuxGraph::MuxGraph(const CircuitLibrary& circuit_lib, 
+                   const CircuitModelId& circuit_model,
+                   const size_t& mux_size) {
+  /* Build the graph for a given multiplexer model */
+  build_mux_graph(circuit_lib, circuit_model, mux_size);
+} 
+
+/**************************************************
+ * Private Constructors
+ *************************************************/
+/* Create an empty graph */
+MuxGraph::MuxGraph() {
+  return;
+}
+
+/**************************************************
+ * Public Accessors : Aggregates
+ *************************************************/
+//Accessors
+MuxGraph::node_range MuxGraph::nodes() const {
+  return vtr::make_range(node_ids_.begin(), node_ids_.end());
+}
+
+/* Find the non-input nodes */
+std::vector<MuxNodeId> MuxGraph::non_input_nodes() const {
+  /* Must be an valid graph */
+  VTR_ASSERT_SAFE(valid_mux_graph());
+  std::vector<MuxNodeId> node_list;
+  
+  /* Build the node list, level by level */
+  for (size_t level = 0; level < num_node_levels(); ++level) {
+    for (size_t node_type = 0; node_type < size_t(NUM_MUX_NODE_TYPES); ++node_type) {
+      /* Bypass any nodes which are not OUTPUT and INTERNAL */
+      if (size_t(MUX_INPUT_NODE) == node_type) { 
+        continue;
+      }
+      /* Reach here, this is either an OUTPUT or INTERNAL node */ 
+      for (auto node : node_lookup_[level][node_type]) { 
+        node_list.push_back(node); 
+      }
+    }
+  }
+
+  return node_list;
+}
+
+MuxGraph::edge_range MuxGraph::edges() const {
+  return vtr::make_range(edge_ids_.begin(), edge_ids_.end());
+}
+
+MuxGraph::mem_range MuxGraph::memories() const {
+  return vtr::make_range(mem_ids_.begin(), mem_ids_.end());
+}
+
+std::vector<size_t> MuxGraph::levels() const {
+  std::vector<size_t> graph_levels;
+  for (size_t lvl = 0; lvl < num_levels(); ++lvl) {
+    graph_levels.push_back(lvl);
+  }
+  return graph_levels;
+}
+
+std::vector<size_t> MuxGraph::node_levels() const {
+  std::vector<size_t> graph_levels;
+  for (size_t lvl = 0; lvl < num_node_levels(); ++lvl) {
+    graph_levels.push_back(lvl);
+  }
+  return graph_levels;
+}
+
+/**************************************************
+ * Public Accessors: Data query
+ *************************************************/
+
+/* Find the number of inputs in the MUX graph */
+size_t MuxGraph::num_inputs() const {
+  /* need to check if the graph is valid or not */
+  VTR_ASSERT_SAFE(valid_mux_graph());
+  /* Sum up the number of INPUT nodes in each level */
+  size_t num_inputs = 0;
+  for (auto node_per_level : node_lookup_) {
+    num_inputs += node_per_level[MUX_INPUT_NODE].size();
+  }
+  return num_inputs;
+}
+
+/* Return the node ids of all the inputs of the multiplexer */
+std::vector<MuxNodeId> MuxGraph::inputs() const {
+  std::vector<MuxNodeId> input_nodes; 
+  /* need to check if the graph is valid or not */
+  VTR_ASSERT_SAFE(valid_mux_graph());
+  /* Add the input nodes in each level */
+  for (auto node_per_level : node_lookup_) {
+    input_nodes.insert(input_nodes.end(), node_per_level[MUX_INPUT_NODE].begin(), node_per_level[MUX_INPUT_NODE].end());
+  }
+  return input_nodes;
+}
+
+/* Find the number of outputs in the MUX graph */
+size_t MuxGraph::num_outputs() const {
+  /* need to check if the graph is valid or not */
+  VTR_ASSERT_SAFE(valid_mux_graph());
+  /* Sum up the number of INPUT nodes in each level */
+  size_t num_outputs = 0;
+  for (auto node_per_level : node_lookup_) {
+    num_outputs += node_per_level[MUX_OUTPUT_NODE].size();
+  }
+  return num_outputs;
+}
+
+/* Return the node ids of all the outputs of the multiplexer */
+std::vector<MuxNodeId> MuxGraph::outputs() const {
+  std::vector<MuxNodeId> output_nodes; 
+  /* need to check if the graph is valid or not */
+  VTR_ASSERT_SAFE(valid_mux_graph());
+  /* Add the output nodes in each level */
+  for (auto node_per_level : node_lookup_) {
+    output_nodes.insert(output_nodes.end(), node_per_level[MUX_OUTPUT_NODE].begin(), node_per_level[MUX_OUTPUT_NODE].end());
+  }
+  return output_nodes;
+}
+
+/* Find the edge between two MUX nodes */
+std::vector<MuxEdgeId> MuxGraph::find_edges(const MuxNodeId& from_node, const MuxNodeId& to_node) const {
+  std::vector<MuxEdgeId> edges;
+
+  VTR_ASSERT(valid_node_id(from_node));
+  VTR_ASSERT(valid_node_id(to_node));
+
+  for (const auto& edge : node_out_edges_[from_node]) {
+    for (const auto& cand : edge_sink_nodes_[edge]) {
+      if (cand == to_node) {
+        /* This is the wanted edge, add to list */
+        edges.push_back(edge);
+      }
+    }
+  }
+
+  return edges;
+}
+
+/* Find the number of levels in the MUX graph */
+size_t MuxGraph::num_levels() const {
+  /* need to check if the graph is valid or not */
+  VTR_ASSERT_SAFE(valid_mux_graph());
+  /* The num_levels by definition excludes the level for outputs, so a deduection is applied */
+  return node_lookup_.size() - 1; 
+}
+
+/* Find the actual number of levels in the MUX graph */
+size_t MuxGraph::num_node_levels() const {
+  /* need to check if the graph is valid or not */
+  VTR_ASSERT_SAFE(valid_mux_graph());
+  return node_lookup_.size(); 
+}
+
+/* Find the number of configuration memories in the MUX graph */
+size_t MuxGraph::num_memory_bits() const {
+  /* need to check if the graph is valid or not */
+  VTR_ASSERT_SAFE(valid_mux_graph());
+  return mem_ids_.size(); 
+}
+
+/* Find the number of SRAMs at a level in the MUX graph */
+size_t MuxGraph::num_memory_bits_at_level(const size_t& level) const {
+  /* need to check if the graph is valid or not */
+  VTR_ASSERT_SAFE(valid_level(level));
+  VTR_ASSERT_SAFE(valid_mux_graph());
+  return mem_lookup_[level].size(); 
+}
+
+/* Return memory id at level */
+std::vector<MuxMemId> MuxGraph::memories_at_level(const size_t& level) const {
+  /* need to check if the graph is valid or not */
+  VTR_ASSERT_SAFE(valid_level(level));
+  VTR_ASSERT_SAFE(valid_mux_graph());
+  return mem_lookup_[level]; 
+}
+
+/* Find the number of nodes at a given level in the MUX graph */
+size_t MuxGraph::num_nodes_at_level(const size_t& level) const {
+  /* validate the level numbers */
+  VTR_ASSERT_SAFE(valid_level(level));
+  VTR_ASSERT_SAFE(valid_mux_graph());
+  
+  size_t num_nodes = 0;
+  for (size_t node_type = 0; node_type < size_t(NUM_MUX_NODE_TYPES); ++node_type) {
+    num_nodes += node_lookup_[level][node_type].size(); 
+  }
+  return num_nodes; 
+}
+
+/* Find the level of a node */
+size_t MuxGraph::node_level(const MuxNodeId& node) const {
+  /* validate the node */
+  VTR_ASSERT(valid_node_id(node));
+  return node_levels_[node]; 
+}
+
+/* Find the index of a node at its level */
+size_t MuxGraph::node_index_at_level(const MuxNodeId& node) const {
+  /* validate the node */
+  VTR_ASSERT(valid_node_id(node));
+  return node_ids_at_level_[node]; 
+}
+
+/* Find the  input edges for a node */
+std::vector<MuxEdgeId> MuxGraph::node_in_edges(const MuxNodeId& node) const {
+  /* validate the node */
+  VTR_ASSERT(valid_node_id(node));
+  return node_in_edges_[node];
+}
+
+/* Find the input nodes for a edge */
+std::vector<MuxNodeId> MuxGraph::edge_src_nodes(const MuxEdgeId& edge) const {
+  /* validate the edge */
+  VTR_ASSERT(valid_edge_id(edge));
+  return edge_src_nodes_[edge];
+}
+
+/* Find the mem that control the edge */
+MuxMemId MuxGraph::find_edge_mem(const MuxEdgeId& edge) const {
+  /* validate the edge */
+  VTR_ASSERT(valid_edge_id(edge));
+  return edge_mem_ids_[edge];
+}
+
+/* Identify if the edge is controlled by the inverted output of a mem */
+bool MuxGraph::is_edge_use_inv_mem(const MuxEdgeId& edge) const {
+  /* validate the edge */
+  VTR_ASSERT(valid_edge_id(edge));
+  return edge_inv_mem_[edge];
+}
+
+/* Find the sizes of each branch of a MUX */
+std::vector<size_t> MuxGraph::branch_sizes() const {
+  std::vector<size_t> branch;
+  /* Visit each internal nodes/output nodes and find the the number of incoming edges */
+  for (auto node : node_ids_ ) {
+    /* Bypass input nodes */
+    if ( (MUX_OUTPUT_NODE != node_types_[node]) 
+      && (MUX_INTERNAL_NODE != node_types_[node]) ) {
+      continue;
+    }
+
+    size_t branch_size = node_in_edges_[node].size();
+
+    /* make sure the branch size is valid */
+    VTR_ASSERT_SAFE(valid_mux_implementation_num_inputs(branch_size));
+
+    /* Nodes with the same number of incoming edges, indicate the same size of branch circuit */
+    std::vector<size_t>::iterator it; 
+    it = std::find(branch.begin(), branch.end(), branch_size);
+    /* if already exists a branch with the same size, skip updating the vector */
+    if (it != branch.end()) {
+      continue;
+    }
+    branch.push_back(branch_size);
+  }
+
+  /* Sort the branch by size */
+  std::sort(branch.begin(), branch.end());
+
+  return branch;
+}
+
+/* Find the sizes of each branch of a MUX at a given level */
+std::vector<size_t> MuxGraph::branch_sizes(const size_t& level) const {
+  std::vector<size_t> branch;
+  /* Visit each internal nodes/output nodes and find the the number of incoming edges */
+  for (auto node : node_ids_ ) {
+    /* Bypass input nodes */
+    if ( (MUX_OUTPUT_NODE != node_types_[node]) 
+      && (MUX_INTERNAL_NODE != node_types_[node]) ) {
+      continue;
+    }
+    /* Bypass nodes that is not at the level */
+    if ( level != node_levels_[node]) {
+      continue;
+    }
+
+    size_t branch_size = node_in_edges_[node].size();
+
+    /* make sure the branch size is valid */
+    VTR_ASSERT_SAFE(valid_mux_implementation_num_inputs(branch_size));
+
+    /* Nodes with the same number of incoming edges, indicate the same size of branch circuit */
+    std::vector<size_t>::iterator it; 
+    it = std::find(branch.begin(), branch.end(), branch_size);
+    /* if already exists a branch with the same size, skip updating the vector */
+    if (it != branch.end()) {
+      continue;
+    }
+    branch.push_back(branch_size);
+  }
+
+  /* Sort the branch by size */
+  std::sort(branch.begin(), branch.end());
+
+  return branch;
+}
+
+
+/* Build a subgraph from the given node
+ * The strategy is very simple, we just 
+ * extract a 1-level graph from here
+ */
+MuxGraph MuxGraph::subgraph(const MuxNodeId& root_node) const {
+  /* Validate the node */
+  VTR_ASSERT_SAFE(this->valid_node_id(root_node));
+
+  /* Generate an empty graph */
+  MuxGraph mux_graph;
+
+  /* A map to record node-to-node mapping from origin graph to subgraph */
+  std::map<MuxNodeId, MuxNodeId> node2node_map;
+
+  /* A map to record edge-to-edge mapping from origin graph to subgraph */
+  std::map<MuxEdgeId, MuxEdgeId> edge2edge_map;
+
+  /* Add output nodes to subgraph */
+  MuxNodeId to_node_subgraph = mux_graph.add_node(MUX_OUTPUT_NODE);
+  mux_graph.node_levels_[to_node_subgraph] = 1;
+  mux_graph.node_ids_at_level_[to_node_subgraph] = 0; 
+  mux_graph.node_output_ids_[to_node_subgraph] = MuxOutputId(0);
+  /* Update the node-to-node map */
+  node2node_map[root_node] = to_node_subgraph;
+
+  /* Add input nodes and edges to subgraph */
+  size_t input_cnt = 0;
+  for (auto edge_origin : this->node_in_edges_[root_node]) {
+    VTR_ASSERT_SAFE(1 == edge_src_nodes_[edge_origin].size());
+    /* Add nodes */
+    MuxNodeId from_node_origin = this->edge_src_nodes_[edge_origin][0];
+    MuxNodeId from_node_subgraph = mux_graph.add_node(MUX_INPUT_NODE);
+    /* Configure the nodes */
+    mux_graph.node_levels_[from_node_subgraph] = 0;
+    mux_graph.node_ids_at_level_[from_node_subgraph] = input_cnt; 
+    mux_graph.node_input_ids_[from_node_subgraph] = MuxInputId(input_cnt);
+    input_cnt++;
+    /* Update the node-to-node map */
+    node2node_map[from_node_origin] = from_node_subgraph;
+
+    /* Add edges */
+    MuxEdgeId edge_subgraph = mux_graph.add_edge(node2node_map[from_node_origin], node2node_map[root_node]);
+    edge2edge_map[edge_origin] = edge_subgraph; 
+    /* Configure edges */
+    mux_graph.edge_models_[edge_subgraph] = this->edge_models_[edge_origin];
+    mux_graph.edge_inv_mem_[edge_subgraph] = this->edge_inv_mem_[edge_origin];
+  } 
+
+  /* A map to record mem-to-mem mapping from origin graph to subgraph */
+  std::map<MuxMemId, MuxMemId> mem2mem_map;
+
+  /* Add memory bits and configure edges */
+  for (auto edge_origin : this->node_in_edges_[root_node]) {
+    MuxMemId mem_origin = this->edge_mem_ids_[edge_origin];
+    /* Try to find if the mem is already in the list */
+    std::map<MuxMemId, MuxMemId>::iterator it = mem2mem_map.find(mem_origin);
+    if (it != mem2mem_map.end()) {
+      /* Found, we skip mem addition. But make sure we have a valid one */
+      VTR_ASSERT_SAFE(MuxMemId::INVALID() != mem2mem_map[mem_origin]);
+      /* configure the edge */
+      mux_graph.edge_mem_ids_[edge2edge_map[edge_origin]] = mem2mem_map[mem_origin];
+      continue;
+    }
+    /* Not found, we add a memory bit and record in the mem-to-mem map */
+    MuxMemId mem_subgraph = mux_graph.add_mem();
+    mux_graph.set_mem_level(mem_subgraph, 0);
+    mem2mem_map[mem_origin] = mem_subgraph;
+    /* configure the edge */
+    mux_graph.edge_mem_ids_[edge2edge_map[edge_origin]] = mem_subgraph;
+  }
+
+  /* Since the graph is finalized, it is time to build the fast look-up */
+  mux_graph.build_node_lookup();
+  mux_graph.build_mem_lookup();
+
+  return mux_graph; 
+}
+
+/* Generate MUX graphs for its branches
+ * Similar to the branch_sizes() method,
+ * we search all the internal nodes and 
+ * find out what are the input sizes of 
+ * the branches. 
+ * Then we extract unique subgraphs and return 
+ */
+std::vector<MuxGraph> MuxGraph::build_mux_branch_graphs() const {
+  std::map<size_t, bool> branch_done; /* A map showing the status of graph generation */
+
+  std::vector<MuxGraph> branch_graphs;
+
+  /* Visit each internal nodes/output nodes and find the the number of incoming edges */
+  for (auto node : node_ids_ ) {
+    /* Bypass input nodes */
+    if ( (MUX_OUTPUT_NODE != node_types_[node]) 
+      && (MUX_INTERNAL_NODE != node_types_[node]) ) {
+      continue;
+    }
+
+    size_t branch_size = node_in_edges_[node].size();
+
+    /* make sure the branch size is valid */
+    VTR_ASSERT_SAFE(valid_mux_implementation_num_inputs(branch_size));
+
+    /* check if the branch have been done in sub-graph extraction! */
+    std::map<size_t, bool>::iterator it = branch_done.find(branch_size);
+    /* if it is done, we can skip */
+    if (it != branch_done.end()) {
+      VTR_ASSERT(branch_done[branch_size]);
+      continue;
+    }
+
+    /* Generate a subgraph and push back */
+    branch_graphs.push_back(subgraph(node));
+
+    /* Mark it is done for this branch size */
+    branch_done[branch_size] = true;
+  }
+
+  return branch_graphs;
+} 
+
+/* Get the input id of a given node */
+MuxInputId MuxGraph::input_id(const MuxNodeId& node_id) const {
+  /* Validate node id */
+  VTR_ASSERT(valid_node_id(node_id));
+  /* Must be an input */
+  VTR_ASSERT(MUX_INPUT_NODE == node_types_[node_id]);
+  return node_input_ids_[node_id];
+}
+
+/* Identify if the node is an input of the MUX */
+bool MuxGraph::is_node_input(const MuxNodeId& node_id) const {
+  /* Validate node id */
+  VTR_ASSERT(true == valid_node_id(node_id));
+  return (MUX_INPUT_NODE == node_types_[node_id]);
+}
+
+/* Get the output id of a given node */
+MuxOutputId MuxGraph::output_id(const MuxNodeId& node_id) const {
+  /* Validate node id */
+  VTR_ASSERT(valid_node_id(node_id));
+  /* Must be an output */
+  VTR_ASSERT(MUX_OUTPUT_NODE == node_types_[node_id]);
+  return node_output_ids_[node_id];
+}
+
+/* Identify if the node is an output of the MUX */
+bool MuxGraph::is_node_output(const MuxNodeId& node_id) const {
+  /* Validate node id */
+  VTR_ASSERT(true == valid_node_id(node_id));
+  return (MUX_OUTPUT_NODE == node_types_[node_id]);
+}
+
+/* Get the node id of a given input */
+MuxNodeId MuxGraph::node_id(const MuxInputId& input_id) const {
+  /* Use the node_lookup to accelerate the search */
+  for (const auto& lvl : node_lookup_) {
+    for (const auto& cand_node : lvl[MUX_INPUT_NODE]) {
+      if (input_id == node_input_ids_[cand_node]) {
+        return cand_node; 
+      }
+    }
+  } 
+
+  return MuxNodeId::INVALID();
+}
+
+/* Get the node id of a given output */
+MuxNodeId MuxGraph::node_id(const MuxOutputId& output_id) const {
+  /* Use the node_lookup to accelerate the search */
+  for (const auto& lvl : node_lookup_) {
+    for (const auto& cand_node : lvl[MUX_OUTPUT_NODE]) {
+      if (output_id == node_output_ids_[cand_node]) {
+        return cand_node; 
+      }
+    }
+  } 
+
+  return MuxNodeId::INVALID();
+}
+
+
+/* Get the node id w.r.t. the node level and node_index at the level
+ * Return an invalid value if not found 
+ */
+MuxNodeId MuxGraph::node_id(const size_t& node_level, const size_t& node_index_at_level) const {
+  /* Ensure we have a valid node_look-up */
+  VTR_ASSERT_SAFE(valid_node_lookup());
+
+  MuxNodeId ret_node = MuxNodeId::INVALID(); 
+
+  /* Search in the fast look up */
+  if (node_level >= node_lookup_.size()) {
+    return ret_node; 
+  }
+  
+  size_t node_cnt = 0;
+  /* Node level is valid, search in the node list */
+  for (const auto& nodes_by_type : node_lookup_[node_level]) {
+    /* Search the node_index_at_level of each node */
+    for (const auto& node : nodes_by_type) {
+      if (node_index_at_level != node_ids_at_level_[node]) {
+        continue;
+      } 
+      /* Find the node, assign value and update the counter */
+      ret_node = node;
+      node_cnt++; 
+    }
+  }
+
+  /* We should either find a node or nothing */
+  VTR_ASSERT((0 == node_cnt) || (1 == node_cnt));
+
+  return ret_node;
+}
+
+/* Decode memory bits based on an input id and an output id */
+vtr::vector<MuxMemId, bool> MuxGraph::decode_memory_bits(const MuxInputId& input_id,
+                                                         const MuxOutputId& output_id) const {
+  /* initialize the memory bits: TODO: support default value */ 
+  vtr::vector<MuxMemId, bool> mem_bits(mem_ids_.size(), false);
+
+  /* valid the input and output */
+  VTR_ASSERT_SAFE(valid_input_id(input_id));
+  VTR_ASSERT_SAFE(valid_output_id(output_id));
+
+  /* Mark all the nodes as not visited */
+  vtr::vector<MuxNodeId, bool> visited(nodes().size(), false); 
+
+  /* Create a queue for Breadth-First Search */ 
+  std::list<MuxNodeId> queue; 
+
+  /* Mark the input node as visited and enqueue it */
+  visited[node_id(input_id)] = true; 
+  queue.push_back(node_id(input_id)); 
+
+  /* Create a flag to indicate if the route is success or not */
+  bool route_success = false;
+
+  while(!queue.empty()) { 
+    /* Dequeue a mux node from queue, 
+     * we will walk through all the fan-in of this node in this loop
+     */
+    MuxNodeId node_to_expand = queue.front(); 
+    queue.pop_front(); 
+                                                                                                               /* Get all fan-in nodes of the dequeued node
+     * If the node has not been visited,  
+     * then mark it visited and enqueue it
+     */
+    VTR_ASSERT_SAFE (1 == node_out_edges_[node_to_expand].size());
+    MuxEdgeId edge = node_out_edges_[node_to_expand][0];
+
+    /* Configure the mem bits: 
+     * if inv_mem is enabled, it means 0 to enable this edge 
+     * otherwise, it is 1 to enable this edge
+     */
+    MuxMemId mem = edge_mem_ids_[edge];
+    VTR_ASSERT_SAFE (valid_mem_id(mem));
+    if (true == edge_inv_mem_[edge]) {
+      mem_bits[mem] = false;
+    } else {
+      mem_bits[mem] = true;
+    }
+
+    /* each edge must have 1 fan-out */
+    VTR_ASSERT_SAFE (1 == edge_sink_nodes_[edge].size());
+
+    /* Get the fan-out node */
+    MuxNodeId next_node = edge_sink_nodes_[edge][0]; 
+
+    /* If next node is the output node we want, we can finish here */
+    if (next_node == node_id(output_id)) {
+      route_success = true;
+      break;
+    }
+
+    /* Add next node to the queue if not visited yet */
+    if (false == visited[next_node]) { 
+       visited[next_node] = true; 
+       queue.push_back(next_node); 
+    }
+  }
+
+  /* Routing must be success! */
+  VTR_ASSERT(true == route_success);
+
+  return mem_bits;
+}
+
+/* Find the input node that the memory bits will route an output node to 
+ * This function backward propagate from the output node to an input node
+ * assuming the memory bits are applied  
+ */
+MuxInputId MuxGraph::find_input_node_driven_by_output_node(const std::map<MuxMemId, bool>& memory_bits,
+                                                           const MuxOutputId& output_id) const {
+  /* Ensure that the memory bits fit the size of memory bits in this MUX */ 
+  VTR_ASSERT(memory_bits.size() == mem_ids_.size());
+
+  /* valid the output */
+  VTR_ASSERT_SAFE(valid_output_id(output_id));
+
+  /* Start from the output node */
+  /* Mark all the nodes as not visited */
+  vtr::vector<MuxNodeId, bool> visited(nodes().size(), false); 
+
+  /* Create a queue for Breadth-First Search */ 
+  std::list<MuxNodeId> queue; 
+
+  /* Mark the output node as visited and enqueue it */
+  visited[node_id(output_id)] = true; 
+  queue.push_back(node_id(output_id)); 
+
+  /* Record the destination input id */
+  MuxInputId des_input_id = MuxInputId::INVALID();
+
+  while(!queue.empty()) { 
+    /* Dequeue a mux node from queue, 
+     * we will walk through all the fan-in of this node in this loop
+     */
+    MuxNodeId node_to_expand = queue.front(); 
+    queue.pop_front(); 
+                                                                                                               /* Get all fan-in nodes of the dequeued node
+     * If the node has not been visited,  
+     * then mark it visited and enqueue it
+     */
+    MuxEdgeId next_edge = MuxEdgeId::INVALID(); 
+    for (const MuxEdgeId& edge : node_in_edges_[node_to_expand]) {
+      /* Configure the mem bits and find the edge that will propagate the signal 
+       * if inv_mem is enabled, it means false to enable this edge 
+       * otherwise, it is true to enable this edge
+       */
+      MuxMemId mem = edge_mem_ids_[edge];
+      VTR_ASSERT_SAFE (valid_mem_id(mem));
+      if (edge_inv_mem_[edge] ==  !memory_bits.at(mem)) { 
+        next_edge = edge;
+        break;
+      }
+    }
+    /* We must have a valid next edge */
+    VTR_ASSERT(MuxEdgeId::INVALID() != next_edge);
+
+    /* each edge must have 1 fan-out */
+    VTR_ASSERT_SAFE (1 == edge_src_nodes_[next_edge].size());
+
+    /* Get the fan-in node */
+    MuxNodeId next_node = edge_src_nodes_[next_edge][0]; 
+
+    /* If next node is an input node, we can finish here */
+    if (true == is_node_input(next_node)) {
+      des_input_id = input_id(next_node);
+      break;
+    }
+
+    /* Add next node to the queue if not visited yet */
+    if (false == visited[next_node]) { 
+       visited[next_node] = true; 
+       queue.push_back(next_node); 
+    }
+  }
+
+  /* Routing must be success! */
+  VTR_ASSERT(MuxInputId::INVALID() != des_input_id);
+
+  return des_input_id;
+}
+
+/**************************************************
+ * Private mutators: basic operations 
+ *************************************************/
+/* Add a unconfigured node to the MuxGraph */
+MuxNodeId MuxGraph::add_node(const enum e_mux_graph_node_type& node_type) {
+  MuxNodeId node = MuxNodeId(node_ids_.size());
+  /* Push to the node list */
+  node_ids_.push_back(node);
+  /* Resize the other node-related vectors */
+  node_types_.push_back(node_type);
+  node_input_ids_.push_back(MuxInputId::INVALID());
+  node_output_ids_.push_back(MuxOutputId::INVALID());
+  node_levels_.push_back(-1);
+  node_ids_at_level_.push_back(-1);
+  node_in_edges_.emplace_back();
+  node_out_edges_.emplace_back();
+
+  return node;
+}
+
+/* Add a edge connecting two nodes  */
+MuxEdgeId MuxGraph::add_edge(const MuxNodeId& from_node, const MuxNodeId& to_node) {
+  MuxEdgeId edge = MuxEdgeId(edge_ids_.size());
+  /* Push to the node list */
+  edge_ids_.push_back(edge);
+  /* Resize the other node-related vectors */
+  edge_models_.push_back(CircuitModelId::INVALID());
+  edge_mem_ids_.push_back(MuxMemId::INVALID());
+  edge_inv_mem_.push_back(false);
+
+  /* update the edge-node connections */
+  VTR_ASSERT(valid_node_id(from_node));
+  edge_src_nodes_.emplace_back();
+  edge_src_nodes_[edge].push_back(from_node);
+  node_out_edges_[from_node].push_back(edge);
+
+  VTR_ASSERT(valid_node_id(to_node));
+  edge_sink_nodes_.emplace_back();
+  edge_sink_nodes_[edge].push_back(to_node);
+  node_in_edges_[to_node].push_back(edge);
+
+  return edge;
+}
+
+/* Add a memory bit to the MuxGraph */
+MuxMemId MuxGraph::add_mem() {
+  MuxMemId mem = MuxMemId(mem_ids_.size());
+  /* Push to the node list */
+  mem_ids_.push_back(mem);
+  mem_levels_.push_back(size_t(-1));
+  /* Resize the other node-related vectors */
+
+  return mem;
+}
+
+/* Configure the level of a memory */
+void MuxGraph::set_mem_level(const MuxMemId& mem, const size_t& level) {
+  /* Make sure we have valid edge and mem */
+  VTR_ASSERT( valid_mem_id(mem) );
+
+  mem_levels_[mem] = level;
+}
+
+/* Link an edge to a memory bit */
+void MuxGraph::set_edge_mem_id(const MuxEdgeId& edge, const MuxMemId& mem) {
+  /* Make sure we have valid edge and mem */
+  VTR_ASSERT( valid_edge_id(edge) && valid_mem_id(mem) );
+
+  edge_mem_ids_[edge] = mem;
+}
+
+/**************************************************
+ * Private mutators: graph builders  
+ *************************************************/
+
+/* Build a graph for a multi-level multiplexer implementation
+ * support both generic multi-level and tree-like multiplexers
+ *
+ * a N:1 multi-level MUX 
+ * ----------------------
+ * 
+ *  input_node --->+
+ *                 |
+ *  input_node --->|
+ *                 |--->+
+ *             ... |    |
+ *                 |    |
+ *  input_node --->+    |---> ...
+ *                      |
+ *             ...  --->+        --->+
+ *                                   |
+ *                  ...          ... |---> output_node
+ *                                   |
+ *             ...  --->+        --->+
+ *                      |
+ *  input_node --->+    |---> ...
+ *                 |    |
+ *  input_node --->|    |
+ *                 |--->+
+ *             ... |     
+ *                 |     
+ *  input_node --->+     
+ *
+ * tree-like multiplexer graph will look like:
+ * --------------------------------------------
+ *
+ *   input_node --->+
+ *                  |--->+
+ *   input_node --->+    |--->  ...
+ *                       |
+ *                   --->+         --->+
+ *     ...            ...  ...         |----> output_node
+ *              ...  --->+         --->+
+ *                       |---> ...
+ *   input_node --->+    |
+ *                  |--->+
+ *   input_node --->+    
+ *
+ */
+void MuxGraph::build_multilevel_mux_graph(const size_t& mux_size, 
+                                          const size_t& num_levels, const size_t& num_inputs_per_branch,
+                                          const CircuitModelId& pgl_model) {
+  /* Make sure mux_size for each branch is valid */
+  VTR_ASSERT(valid_mux_implementation_num_inputs(num_inputs_per_branch));
+
+  /* In regular cases, there is 1 mem bit for each input of a branch */
+  size_t num_mems_per_level = num_inputs_per_branch;
+  /* For 2-input branch, only 1 mem bit is needed for each level! */
+  if (2 == num_inputs_per_branch) { 
+    num_mems_per_level = 1; 
+  }
+  /* Number of memory bits is definite, add them */
+  for (size_t ilvl = 0; ilvl < num_levels; ++ilvl) {
+    for (size_t imem = 0; imem < num_mems_per_level; ++imem) {
+      MuxMemId mem = add_mem();
+      mem_levels_[mem] = ilvl;
+    }
+  }
+
+  /* Create a fast node lookup locally.
+   * Only used for building the graph
+   * it sorts the nodes by levels and ids at each level
+   */
+  std::vector<std::vector<MuxNodeId>> node_lookup; /* [num_levels][num_nodes_per_level] */
+  node_lookup.resize(num_levels + 1); 
+
+  /* Number of outputs is definite, add and configure */
+  MuxNodeId output_node = add_node(MUX_OUTPUT_NODE);
+  node_levels_[output_node] = num_levels; 
+  node_ids_at_level_[output_node] = 0; 
+  node_output_ids_[output_node] = MuxOutputId(0); 
+  /* Update node lookup */
+  node_lookup[num_levels].push_back(output_node);
+
+  /* keep a list of node ids which can be candidates for input nodes */
+  std::vector<MuxNodeId> input_node_ids;
+ 
+  /* Add internal nodes level by level, 
+   * we start from the last level, following a strategy like tree growing
+   */
+  for (size_t lvl = num_levels - 1; ; --lvl) {
+    /* Expand from the existing nodes 
+     * Last level should expand from output_node 
+     * Other levels will expand from internal nodes!
+     */
+    size_t node_cnt_per_level = 0; /* A counter to record node indices at each level */
+    for (MuxNodeId seed_node : node_lookup[lvl + 1]) {
+      /* Add a new node and connect to seed_node, until we reach the num_inputs_per_branch */
+      for (size_t i = 0; i < num_inputs_per_branch; ++i) {
+        /* We deposite a type of INTERNAL_NODE, 
+         * later it will be configured to INPUT if it is in the input list 
+         */
+        MuxNodeId expand_node = add_node(MUX_INTERNAL_NODE); 
+
+        /* Node level is deterministic */
+        node_levels_[expand_node] = lvl; 
+        node_ids_at_level_[expand_node] = node_cnt_per_level; 
+        /* update level node counter */
+        node_cnt_per_level++;
+       
+        /* Create an edge and connect the two nodes */
+        MuxEdgeId edge = add_edge(expand_node, seed_node); 
+        /* Configure the edge */
+        edge_models_[edge] = pgl_model;
+
+        /* Memory id depends on the level and offset in the current branch 
+         * if number of inputs per branch is 2, it indicates a tree-like multiplexer, 
+         * every two edges will share one memory bit 
+         * otherwise, each edge corresponds to a memory bit
+         */
+        
+        if ( 2 == num_inputs_per_branch) {
+          MuxMemId mem_id = MuxMemId(lvl);
+          set_edge_mem_id(edge, mem_id);
+          /* If this is a second edge in the branch, we will assign it to an inverted edge */
+          if (0 != i % num_inputs_per_branch) {
+            edge_inv_mem_[edge] = true;
+          }
+        } else {
+          MuxMemId mem_id = MuxMemId( lvl * num_inputs_per_branch + i );
+          set_edge_mem_id(edge, mem_id);
+        }
+
+        /* Update node lookup */
+        node_lookup[lvl].push_back(expand_node);
+
+        /* Push the node to input list, and then remove the seed_node from the list */ 
+        input_node_ids.push_back(expand_node);
+        /* Remove the node if the seed node is the list */
+        std::vector<MuxNodeId>::iterator it = find(input_node_ids.begin(), input_node_ids.end(), seed_node);
+        if (it != input_node_ids.end()) {
+          input_node_ids.erase(it);
+        }
+
+        /* Check the number of input nodes, if already meet the demand, we can finish here */
+        if (mux_size != input_node_ids.size()) {
+          continue; /* We need more inputs, keep looping */
+        }
+
+        /* The graph is done, we configure the input nodes and then we can return */
+        /* We must be in level 0 !*/
+        VTR_ASSERT( 0 == lvl ) ;
+        for (MuxNodeId input_node : input_node_ids) {
+          node_types_[input_node] = MUX_INPUT_NODE;
+        }
+
+        /* Sort the nodes by the levels and offset */
+        size_t input_cnt = 0;
+        for (auto lvl_nodes : node_lookup) {
+          for (MuxNodeId cand_node : lvl_nodes) {
+            if (MUX_INPUT_NODE != node_types_[cand_node]) {
+               continue;
+            }
+            /* Update the input node ids */
+            node_input_ids_[cand_node] = MuxInputId(input_cnt);
+            /* Update the counter */
+            input_cnt++;
+          }
+        }
+        /* Make sure we visited all the inputs in the cache */
+        VTR_ASSERT(input_cnt == input_node_ids.size());
+        /* Finish building the graph for a multi-level multiplexer */
+        return;
+      }
+    }
+  } 
+  /* Finish building the graph for a multi-level multiplexer */
+} 
+
+/* Build the graph for a given one-level multiplexer implementation 
+ * a N:1 one-level MUX
+ * 
+ *  input_node --->+
+ *                 |
+ *  input_node --->|
+ *                 |--> output_node
+ *             ... |
+ *                 |
+ *  input_node --->+
+ */
+void MuxGraph::build_onelevel_mux_graph(const size_t& mux_size, 
+                                        const CircuitModelId& pgl_model) {
+  /* Make sure mux_size is valid */
+  VTR_ASSERT(valid_mux_implementation_num_inputs(mux_size));
+
+  /* We definitely know how many nodes we need, 
+   * N inputs, 1 output and 0 internal nodes
+   */
+  MuxNodeId output_node = add_node(MUX_OUTPUT_NODE);
+  node_levels_[output_node] = 1; 
+  node_ids_at_level_[output_node] = 0; 
+  node_output_ids_[output_node] = MuxOutputId(0); 
+
+  for (size_t i = 0; i < mux_size; ++i) {
+    MuxNodeId input_node = add_node(MUX_INPUT_NODE);
+    /* All the node belong to level 0 (we have only 1 level) */
+    node_input_ids_[input_node] = MuxInputId(i);
+    node_levels_[input_node] = 0; 
+    node_ids_at_level_[input_node] = i; 
+
+    /* We definitely know how many edges we need, 
+     * the same as mux_size, add a edge connecting two nodes
+     */
+    MuxEdgeId edge = add_edge(input_node, output_node); 
+    /* Configure the edge */
+    edge_models_[edge] = pgl_model;
+
+    /* Create a memory bit*/
+    MuxMemId mem = add_mem(); 
+    mem_levels_[mem] = 0;
+    /* Link the edge to a memory bit */
+    set_edge_mem_id(edge, mem);
+  }
+  /* Finish building the graph for a one-level multiplexer */
+} 
+
+/* Convert some internal nodes to be additional outputs
+ * according to the fracturable LUT port definition
+ * We will iterate over each output port of a circuit model 
+ * and find the frac_level and output_mask 
+ * Then, the internal nodes at the frac_level will be converted
+ * to output nodes with a given output_mask
+ */
+void MuxGraph::add_fracturable_outputs(const CircuitLibrary& circuit_lib, 
+                                       const CircuitModelId& circuit_model) {
+  /* Iterate over output ports */
+  for (const auto& port : circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true)) {
+    /* Get the fracturable_level */
+    size_t frac_level = circuit_lib.port_lut_frac_level(port);
+    /* Bypass invalid frac_level */
+    if (size_t(-1) == frac_level) {
+      continue;
+    }
+    /* Iterate over output masks */
+    for (const auto& output_idx : circuit_lib.port_lut_output_mask(port)) {
+      size_t num_matched_nodes = 0;
+      /* Iterate over node and find the internal nodes, which match the frac_level and output_idx */
+      for (const auto& node : node_lookup_[frac_level][MUX_INTERNAL_NODE]) {
+        if (node_ids_at_level_[node] != output_idx) {
+          /* Bypass condition */
+          continue;
+        }
+        /* Reach here, this is the node we want
+         * Convert it to output nodes and update the counter   
+         */
+        node_types_[node] = MUX_OUTPUT_NODE;
+        node_output_ids_[node] = MuxOutputId(num_outputs());  
+        num_matched_nodes++;
+      } 
+      /* Either find 1 or 0 matched nodes */
+      if (0 != num_matched_nodes) {
+        /* We should find only one node that matches! */
+        VTR_ASSERT(1 == num_matched_nodes);
+        /* Rebuild the node look-up */
+        build_node_lookup();
+        continue; /* Finish here, go to next */
+      }
+      /* Sometime the wanted node is already an output, do a double check */
+      for (const auto& node : node_lookup_[frac_level][MUX_OUTPUT_NODE]) {
+        if (node_ids_at_level_[node] != output_idx) {
+          /* Bypass condition */
+          continue;
+        }
+        /* Reach here, this is the node we want 
+         * Just update the counter   
+         */
+        num_matched_nodes++;
+      }
+      /* We should find only one node that matches! */
+      VTR_ASSERT(1 == num_matched_nodes);
+    } 
+  }
+}
+
+/* Build the graph for a given multiplexer model */
+void MuxGraph::build_mux_graph(const CircuitLibrary& circuit_lib, 
+                               const CircuitModelId& circuit_model,
+                               const size_t& mux_size) {
+  /* Make sure this model is a MUX */
+  VTR_ASSERT((CIRCUIT_MODEL_MUX == circuit_lib.model_type(circuit_model))
+          || (CIRCUIT_MODEL_LUT == circuit_lib.model_type(circuit_model)) );
+
+  /* Make sure mux_size is valid */
+  VTR_ASSERT(valid_mux_implementation_num_inputs(mux_size));
+
+  size_t impl_mux_size = find_mux_implementation_num_inputs(circuit_lib, circuit_model, mux_size);
+
+  /* Depends on the mux size, the implemented multiplexer structure may change! */
+  enum e_circuit_model_structure impl_structure = find_mux_implementation_structure(circuit_lib, circuit_model, impl_mux_size);
+
+  /* Branch on multiplexer structures, leading to different building strategies */
+  switch (impl_structure) {
+  case CIRCUIT_MODEL_STRUCTURE_TREE: {
+    /* Find the number of levels */
+    size_t num_levels = find_treelike_mux_num_levels(impl_mux_size);
+
+    /* Find the number of inputs per branch, this is not final */
+    size_t num_inputs_per_branch = 2;
+
+    /* Build a multilevel mux graph */
+    build_multilevel_mux_graph(impl_mux_size, num_levels, num_inputs_per_branch, circuit_lib.pass_gate_logic_model(circuit_model));
+    break;
+  }
+  case CIRCUIT_MODEL_STRUCTURE_ONELEVEL: {
+    build_onelevel_mux_graph(impl_mux_size, circuit_lib.pass_gate_logic_model(circuit_model));
+    break;
+  }
+  case CIRCUIT_MODEL_STRUCTURE_MULTILEVEL: {
+    /* Find the number of inputs per branch, this is not final */
+    size_t num_inputs_per_branch = find_multilevel_mux_branch_num_inputs(impl_mux_size, circuit_lib.mux_num_levels(circuit_model));
+
+    /* Build a multilevel mux graph */
+    build_multilevel_mux_graph(impl_mux_size, circuit_lib.mux_num_levels(circuit_model), 
+                               num_inputs_per_branch,
+                               circuit_lib.pass_gate_logic_model(circuit_model));
+    break;
+  }
+  default:
+    VTR_LOG_ERROR("Invalid multiplexer structure for circuit model '%s'!\n",
+                  circuit_lib.model_name(circuit_model).c_str());
+    exit(1);
+  }
+
+  /* Since the graph is finalized, it is time to build the fast look-up */
+  build_node_lookup();
+  build_mem_lookup();
+
+  /* For fracturable LUTs, we need to add more outputs to the MUX graph */
+  if ( (CIRCUIT_MODEL_LUT == circuit_lib.model_type(circuit_model))
+    && (true == circuit_lib.is_lut_fracturable(circuit_model)) ) {
+    add_fracturable_outputs(circuit_lib, circuit_model);
+  }
+}
+
+/* Build fast node lookup */
+void MuxGraph::build_node_lookup() {
+  /* Invalidate the node lookup if necessary */
+  invalidate_node_lookup();
+
+  /* Find the maximum number of levels */
+  size_t num_levels = 0;
+  for (auto node : nodes()) {
+    num_levels = std::max((int)node_levels_[node], (int)num_levels);
+  }
+
+  /* Resize node_lookup */
+  node_lookup_.resize(num_levels + 1);
+  for (size_t lvl = 0; lvl < node_lookup_.size(); ++lvl) {
+    /* Resize by number of node types */
+    node_lookup_[lvl].resize(NUM_MUX_NODE_TYPES);
+  }
+
+  /* Fill the node lookup */
+  for (auto node : nodes()) {
+    node_lookup_[node_levels_[node]][size_t(node_types_[node])].push_back(node);
+  }
+}
+
+/* Build fast mem lookup */
+void MuxGraph::build_mem_lookup() {
+  /* Invalidate the mem lookup if necessary */
+  invalidate_mem_lookup();
+
+  /* Find the maximum number of levels */
+  size_t num_levels = 0;
+  for (auto mem : memories()) {
+    num_levels = std::max((int)mem_levels_[mem], (int)num_levels);
+  }
+
+  /* Resize mem_lookup */
+  mem_lookup_.resize(num_levels + 1);
+  for (auto mem : memories()) {
+    /* Categorize mem nodes into mem_lookup */
+    mem_lookup_[mem_levels_[mem]].push_back(mem);
+  }
+}
+
+/* Invalidate (empty) the node fast lookup*/
+void MuxGraph::invalidate_node_lookup() {
+  node_lookup_.clear();
+}
+
+/* Invalidate (empty) the mem fast lookup*/
+void MuxGraph::invalidate_mem_lookup() {
+  mem_lookup_.clear();
+}
+ 
+/**************************************************
+ * Private validators
+ *************************************************/
+
+/* valid ids */
+bool MuxGraph::valid_node_id(const MuxNodeId& node) const {
+  return size_t(node) < node_ids_.size() && node_ids_[node] == node;
+}
+
+bool MuxGraph::valid_edge_id(const MuxEdgeId& edge) const {
+  return size_t(edge) < edge_ids_.size() && edge_ids_[edge] == edge;
+}
+
+bool MuxGraph::valid_mem_id(const MuxMemId& mem) const {
+  return size_t(mem) < mem_ids_.size() && mem_ids_[mem] == mem;
+}
+
+/* validate an input id (from which data path signal will be progagated to the output) */
+bool MuxGraph::valid_input_id(const MuxInputId& input_id) const {
+  for (const auto& lvl : node_lookup_) {
+    for (const auto& node : lvl[MUX_INPUT_NODE]) {
+      if (size_t(input_id) > size_t(node_input_ids_[node])) {
+        return false;
+      }
+    }
+  } 
+
+  return true;
+}
+
+/* validate an output id */
+bool MuxGraph::valid_output_id(const MuxOutputId& output_id) const {
+  for (const auto& lvl : node_lookup_) {
+    for (const auto& node : lvl[MUX_OUTPUT_NODE]) {
+      if (size_t(output_id) > size_t(node_output_ids_[node])) {
+        return false;
+      }
+    }
+  } 
+
+  return true;
+}
+
+bool MuxGraph::valid_level(const size_t& level) const {
+  return level < num_node_levels(); 
+}
+
+bool MuxGraph::valid_node_lookup() const {
+  return node_lookup_.empty();
+}
+
+/* validate a mux graph and see if it is valid */
+bool MuxGraph::valid_mux_graph() const {
+  /* A valid MUX graph should be
+   * 1. every node has 1 fan-out except output node
+   * 2. every input can be routed to the output node 
+   */
+  for (const auto& node : nodes()) {
+    /* output node has 0 fan-out*/
+    if (MUX_OUTPUT_NODE == node_types_[node]) {
+      continue;
+    }
+    /* other nodes should have 1 fan-out */
+    if (1 != node_out_edges_[node].size()) {
+      return false;
+    }
+  }
+
+  /* Try to route to output */
+  for (const auto& node : nodes()) {
+    if (MUX_INPUT_NODE == node_types_[node]) {
+      MuxNodeId next_node = node;
+      while ( 0 < node_out_edges_[next_node].size() ) {
+        MuxEdgeId edge = node_out_edges_[next_node][0];
+        /* each edge must have 1 fan-out */
+        if (1 != edge_sink_nodes_[edge].size()) {
+          return false;
+        }
+        next_node = edge_sink_nodes_[edge][0]; 
+      }
+      if (MUX_OUTPUT_NODE != node_types_[next_node]) {
+        return false;
+      }
+    }
+  } 
+
+  return true;
+}
+
+} /* End namespace openfpga*/
diff --git a/openfpga/src/mux_lib/mux_graph.h b/openfpga/src/mux_lib/mux_graph.h
new file mode 100644
index 000000000..fd2fbbf6d
--- /dev/null
+++ b/openfpga/src/mux_lib/mux_graph.h
@@ -0,0 +1,213 @@
+#ifndef MUX_GRAPH_H
+#define MUX_GRAPH_H
+
+/********************************************************************
+ * Include header files required by the data structure definition
+ *******************************************************************/
+#include <map>
+#include "vtr_vector.h"
+#include "vtr_range.h"
+#include "mux_graph_fwd.h"
+#include "circuit_library.h"
+
+/* Begin namespace openfpga */
+namespace openfpga {
+
+/**************************************************
+ * This file includes a data structure to describe
+ * the internal structure of a multiplexer
+ * using a generic graph representation  
+ * A Branch is a N:1 MUX in the part of MUX graph 
+ * 
+ *  branch_input --->+
+ *                   |
+ *  branch_input --->|
+ *                   |--> branch_out
+ *               ... |
+ *                   |
+ *  branch_input --->+
+ *
+ *  A short example of how a two-level MUX is organized by branches 
+ *
+ *               +-----------+    +--------+
+ * mux_inputs--->| Branch[0] |--->|        |
+ *               +-----------+    |        |
+ *                 ...            | Branch |---> mux_out
+ *               +-----------+    | [N+1]  |
+ * mux_inputs--->| Branch[N] |--->|        |
+ *               +-----------+    +--------+
+ *
+ *************************************************/
+class MuxGraph {
+  private: /* data types used only in this class */
+    enum e_mux_graph_node_type {
+      MUX_INPUT_NODE,
+      MUX_INTERNAL_NODE,
+      MUX_OUTPUT_NODE,
+      NUM_MUX_NODE_TYPES
+    };
+  public: /* Types and ranges */
+    typedef vtr::vector<MuxNodeId, MuxNodeId>::const_iterator node_iterator;
+    typedef vtr::vector<MuxEdgeId, MuxEdgeId>::const_iterator edge_iterator;
+    typedef vtr::vector<MuxMemId, MuxMemId>::const_iterator mem_iterator;
+
+    typedef vtr::Range<node_iterator> node_range;
+    typedef vtr::Range<edge_iterator> edge_range;
+    typedef vtr::Range<mem_iterator> mem_range;
+  public: /* Public Constructors */
+    /* Create an object based on a Circuit Model which is MUX */
+    MuxGraph(const CircuitLibrary& circuit_lib, 
+             const CircuitModelId& circuit_model,
+             const size_t& mux_size); 
+  private: /* Private Constructors*/
+    /* Create an empty graph */
+    MuxGraph();
+  public: /* Public accessors: Aggregates */
+    node_range nodes() const;
+    /* Find the non-input nodes */
+    std::vector<MuxNodeId> non_input_nodes() const;
+    edge_range edges() const;
+    mem_range memories() const;
+    /* Find the number of levels in terms of the multiplexer */
+    std::vector<size_t> levels() const;
+    /* Find the actual number of levels in the graph */
+    std::vector<size_t> node_levels() const;
+  public: /* Public accessors: Data query */
+    /* Find the number of inputs in the MUX graph */
+    size_t num_inputs() const;
+    std::vector<MuxNodeId> inputs() const;
+    /* Find the number of outputs in the MUX graph */
+    size_t num_outputs() const;
+    std::vector<MuxNodeId> outputs() const;
+    /* Find the edge between two MUX nodes */
+    std::vector<MuxEdgeId> find_edges(const MuxNodeId& from_node, const MuxNodeId& to_node) const;
+    /* Find the number of levels in the MUX graph */
+    size_t num_levels() const;
+    size_t num_node_levels() const;
+    /* Find the number of SRAMs in the MUX graph */
+    size_t num_memory_bits() const;
+    /* Find the number of SRAMs at a level in the MUX graph */
+    size_t num_memory_bits_at_level(const size_t& level) const;
+    /* Return memory id at level */
+    std::vector<MuxMemId> memories_at_level(const size_t& level) const;
+    /* Find the number of nodes at a given level in the MUX graph */
+    size_t num_nodes_at_level(const size_t& level) const;
+    /* Find the level of a node */
+    size_t node_level(const MuxNodeId& node) const;
+    /* Find the index of a node at its level */
+    size_t node_index_at_level(const MuxNodeId& node) const;
+    /* Find the input edges for a node */
+    std::vector<MuxEdgeId> node_in_edges(const MuxNodeId& node) const;
+    /* Find the input nodes for a edge */
+    std::vector<MuxNodeId> edge_src_nodes(const MuxEdgeId& edge) const;
+    /* Find the mem that control the edge */
+    MuxMemId find_edge_mem(const MuxEdgeId& edge) const;
+    /* Identify if the edge is controlled by the inverted output of a mem */
+    bool is_edge_use_inv_mem(const MuxEdgeId& edge) const;
+    /* Find the sizes of each branch of a MUX */
+    std::vector<size_t> branch_sizes() const;
+    /* Find the sizes of each branch of a MUX at a given level */
+    std::vector<size_t> branch_sizes(const size_t& level) const;
+    /* Generate MUX graphs for its branches */
+    MuxGraph subgraph(const MuxNodeId& node) const;
+    std::vector<MuxGraph> build_mux_branch_graphs() const; 
+    /* Get the node id of a given input */
+    MuxNodeId node_id(const MuxInputId& input_id) const;
+    /* Get the node id of a given output */
+    MuxNodeId node_id(const MuxOutputId& output_id) const;
+    /* Get the node id w.r.t. the node level and node_index at the level */
+    MuxNodeId node_id(const size_t& node_level, const size_t& node_index_at_level) const;
+    /* Get the input id of a given node */
+    MuxInputId input_id(const MuxNodeId& node_id) const;
+    /* Identify if the node is an input of the MUX */
+    bool is_node_input(const MuxNodeId& node_id) const;
+    /* Get the output id of a given node */
+    MuxOutputId output_id(const MuxNodeId& node_id) const;
+    /* Identify if the node is an output of the MUX */
+    bool is_node_output(const MuxNodeId& node_id) const;
+    /* Decode memory bits based on an input id and an output id 
+     * This function will start from the input node 
+     * and do a forward propagation until reaching the output node  
+     */
+    vtr::vector<MuxMemId, bool> decode_memory_bits(const MuxInputId& input_id,
+                                                   const MuxOutputId& output_id) const;
+    /* Find the input node that the memory bits will route an output node to 
+     * This function backward propagate from the output node to an input node
+     * assuming the memory bits are applied  
+     * Note: This function is mainly used for decoding LUT MUXes
+     */
+    MuxInputId find_input_node_driven_by_output_node(const std::map<MuxMemId, bool>& memory_bits,
+                                                     const MuxOutputId& output_id) const;
+  private: /* Private mutators : basic operations */
+     /* Add a unconfigured node to the MuxGraph */
+     MuxNodeId add_node(const enum e_mux_graph_node_type& node_type);
+     /* Add a edge connecting two nodes  */
+     MuxEdgeId add_edge(const MuxNodeId& from_node, const MuxNodeId& to_node);
+     /* Add a memory bit to the MuxGraph */
+     MuxMemId add_mem();
+     /* Configure the level of a memory */
+     void set_mem_level(const MuxMemId& mem, const size_t& level);
+     /* Link an edge to a mem */
+     void set_edge_mem_id(const MuxEdgeId& edge, const MuxMemId& mem);
+  private: /* Private mutators : graph builders */
+    void build_multilevel_mux_graph(const size_t& mux_size, 
+                                    const size_t& num_levels, const size_t& num_inputs_per_branch,
+                                    const CircuitModelId& pgl_model) ;
+    /* Build the graph for a given one-level multiplexer implementation */
+    void build_onelevel_mux_graph(const size_t& mux_size, 
+                                  const CircuitModelId& pgl_model) ;
+    /* Build the graph for a given multiplexer model */
+    void build_mux_graph(const CircuitLibrary& circuit_lib, 
+                         const CircuitModelId& circuit_model,
+                         const size_t& mux_size); 
+    /* Convert some internal node to outputs according to fracturable LUT circuit design specifications */
+    void add_fracturable_outputs(const CircuitLibrary& circuit_lib, 
+                                 const CircuitModelId& circuit_model);
+    /* Build fast node lookup */
+    void build_node_lookup();
+    /* Build fast mem lookup */
+    void build_mem_lookup();
+  private: /* Private validators */
+    /* valid ids */
+    bool valid_node_id(const MuxNodeId& node) const;
+    bool valid_edge_id(const MuxEdgeId& edge) const;
+    bool valid_mem_id(const MuxMemId& mem) const;
+    bool valid_input_id(const MuxInputId& input_id) const;
+    bool valid_output_id(const MuxOutputId& output_id) const;
+    bool valid_level(const size_t& level) const;
+    /* validate/invalidate node lookup */
+    bool valid_node_lookup() const;
+    void invalidate_node_lookup();
+    void invalidate_mem_lookup();
+    /* validate graph */
+    bool valid_mux_graph() const;
+  private: /* Internal data */
+    vtr::vector<MuxNodeId, MuxNodeId> node_ids_;                        /* Unique ids for each node */
+    vtr::vector<MuxNodeId, enum e_mux_graph_node_type> node_types_;     /* type of each node, input/output/internal */
+    vtr::vector<MuxNodeId, MuxInputId> node_input_ids_;                 /* Unique ids for each node as an input of the MUX */
+    vtr::vector<MuxNodeId, MuxOutputId> node_output_ids_;                 /* Unique ids for each node as an input of the MUX */
+    vtr::vector<MuxNodeId, size_t> node_levels_;                       /* at which level, each node belongs to */
+    vtr::vector<MuxNodeId, size_t> node_ids_at_level_;                       /* the index at the level that each node belongs to */
+    vtr::vector<MuxNodeId, std::vector<MuxEdgeId>> node_in_edges_;       /* ids of incoming edges to each node */
+    vtr::vector<MuxNodeId, std::vector<MuxEdgeId>> node_out_edges_;      /* ids of outgoing edges from each node */
+
+    vtr::vector<MuxEdgeId, MuxEdgeId> edge_ids_;                        /* Unique ids for each edge */
+    vtr::vector<MuxEdgeId, std::vector<MuxNodeId>> edge_src_nodes_;     /* source nodes drive this edge */
+    vtr::vector<MuxEdgeId, std::vector<MuxNodeId>> edge_sink_nodes_;    /* sink nodes this edge drives */
+    vtr::vector<MuxEdgeId, CircuitModelId> edge_models_; /* type of each edge: tgate/pass-gate */
+    vtr::vector<MuxEdgeId, MuxMemId> edge_mem_ids_;                   /* ids of memory bit that control the edge */
+    vtr::vector<MuxEdgeId, bool> edge_inv_mem_;                       /* if the edge is controlled by an inverted output of a memory bit */
+
+    vtr::vector<MuxMemId, MuxMemId> mem_ids_;                        /* ids of configuration memories */
+    vtr::vector<MuxMemId, size_t> mem_levels_;                        /* ids of configuration memories */
+
+    /* fast look-up */
+    typedef std::vector<std::vector<std::vector<MuxNodeId>>> NodeLookup;
+    mutable NodeLookup node_lookup_; /* [num_levels][num_types][num_nodes_per_level] */ 
+    typedef std::vector<std::vector<MuxMemId>> MemLookup;
+    mutable MemLookup mem_lookup_; /* [num_levels][num_mems_per_level] */ 
+};
+
+} /* End namespace openfpga*/
+
+#endif
diff --git a/openfpga/src/mux_lib/mux_graph_fwd.h b/openfpga/src/mux_lib/mux_graph_fwd.h
new file mode 100644
index 000000000..75fd5b1e1
--- /dev/null
+++ b/openfpga/src/mux_lib/mux_graph_fwd.h
@@ -0,0 +1,33 @@
+/**************************************************
+ * This file includes only declarations for 
+ * the data structures to describe multiplexer structures
+ * Please refer to mux_graph.h for more details
+ *************************************************/
+#ifndef MUX_GRAPH_FWD_H
+#define MUX_GRAPH_FWD_H
+
+#include "vtr_strong_id.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+
+/* Strong Ids for MUXes */
+struct mux_node_id_tag;
+struct mux_edge_id_tag;
+struct mux_mem_id_tag;
+struct mux_input_id_tag;
+struct mux_output_id_tag;
+
+typedef vtr::StrongId<mux_node_id_tag> MuxNodeId;
+typedef vtr::StrongId<mux_edge_id_tag> MuxEdgeId;
+typedef vtr::StrongId<mux_mem_id_tag> MuxMemId;
+typedef vtr::StrongId<mux_input_id_tag> MuxInputId;
+typedef vtr::StrongId<mux_output_id_tag> MuxOutputId;
+
+class MuxGraph;
+
+} /* end namespace openfpga */
+
+
+#endif 
diff --git a/openfpga/src/mux_lib/mux_library.cpp b/openfpga/src/mux_lib/mux_library.cpp
new file mode 100644
index 000000000..20e590fdf
--- /dev/null
+++ b/openfpga/src/mux_lib/mux_library.cpp
@@ -0,0 +1,121 @@
+/**************************************************
+ * This file includes member functions for the 
+ * data structures in mux_library.h
+ *************************************************/
+
+#include "vtr_assert.h"
+
+#include "mux_library.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/**************************************************
+ * Member functions for the class MuxLibrary
+ *************************************************/
+
+/**************************************************
+ * Public accessors: aggregates
+ *************************************************/
+MuxLibrary::mux_range MuxLibrary::muxes() const {
+  return vtr::make_range(mux_ids_.begin(), mux_ids_.end());
+}
+
+/**************************************************
+ * Public accessors: data query
+ *************************************************/
+/* Get a MUX graph (read-only) */
+MuxId MuxLibrary::mux_graph(const CircuitModelId& circuit_model, 
+                            const size_t& mux_size) const {
+  /* Make sure we have a valid mux look-up */
+  VTR_ASSERT_SAFE(valid_mux_lookup());
+  /* Validate circuit model id and mux_size */
+  VTR_ASSERT_SAFE(valid_mux_size(circuit_model, mux_size));
+
+  return mux_lookup_[circuit_model][mux_size];
+}
+
+const MuxGraph& MuxLibrary::mux_graph(const MuxId& mux_id) const {
+  VTR_ASSERT_SAFE(valid_mux_id(mux_id));
+  return mux_graphs_[mux_id];
+}
+
+/* Get a mux circuit model id */
+CircuitModelId MuxLibrary::mux_circuit_model(const MuxId& mux_id) const {
+  VTR_ASSERT_SAFE(valid_mux_id(mux_id));
+  return mux_circuit_models_[mux_id];
+}
+
+/* Find the maximum mux size among the mux graphs */
+size_t MuxLibrary::max_mux_size() const {
+  /* Iterate over all the mux graphs and find their sizes */
+  size_t max_mux_size = 0;
+  for (const auto& mux : mux_ids_) {
+    max_mux_size = std::max(max_mux_size, mux_graphs_[mux].num_inputs());
+  }
+  return max_mux_size;
+}
+
+/**************************************************
+ * Private mutators:
+ *************************************************/
+/* Add a mux to the library */
+void MuxLibrary::add_mux(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, const size_t& mux_size) {
+  /* First, check if there is already an existing graph */
+  if (valid_mux_size(circuit_model, mux_size)) {
+    return;
+  }
+
+  /* create a new id for the mux */
+  MuxId mux = MuxId(mux_ids_.size());
+  /* Push to the node list */
+  mux_ids_.push_back(mux);
+  /* Add a mux graph */
+  mux_graphs_.push_back(MuxGraph(circuit_lib, circuit_model, mux_size));
+  /* Recorde mux cirucit model id */
+  mux_circuit_models_.push_back(circuit_model);
+
+  /* update mux_lookup*/
+  mux_lookup_[circuit_model][mux_size] = mux;
+} 
+
+/**************************************************
+ * Private accessors: validator and invalidators
+ *************************************************/
+bool MuxLibrary::valid_mux_id(const MuxId& mux) const {
+  return size_t(mux) < mux_ids_.size() && mux_ids_[mux] == mux;
+}
+
+bool MuxLibrary::valid_mux_lookup() const {
+  return mux_lookup_.empty();
+}
+
+bool MuxLibrary::valid_mux_circuit_model_id(const CircuitModelId& circuit_model) const {
+  MuxLookup::iterator it = mux_lookup_.find(circuit_model);
+  return (it != mux_lookup_.end());
+}
+
+bool MuxLibrary::valid_mux_size(const CircuitModelId& circuit_model, const size_t& mux_size) const {
+  if (false == valid_mux_circuit_model_id(circuit_model)) {
+    return false;
+  }
+  std::map<size_t, MuxId>::iterator it = mux_lookup_[circuit_model].find(mux_size);
+  return (it != mux_lookup_[circuit_model].end());
+}
+
+/**************************************************
+ * Private mutators: validator and invalidators
+ *************************************************/
+
+/* Build fast node lookup */
+void MuxLibrary::build_mux_lookup() {
+  /* Invalidate the mux lookup if necessary */
+  invalidate_mux_lookup();
+}
+
+/* Invalidate (empty) the mux fast lookup*/
+void MuxLibrary::invalidate_mux_lookup() {
+  mux_lookup_.clear();
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/mux_lib/mux_library.h b/openfpga/src/mux_lib/mux_library.h
new file mode 100644
index 000000000..03f406738
--- /dev/null
+++ b/openfpga/src/mux_lib/mux_library.h
@@ -0,0 +1,64 @@
+/**************************************************
+ * This file includes a data structure to describe
+ * the multiplexer implementations in FPGA architectures
+ * MuxLibrary is a collection of multiplexers 
+ * with various circuit-level description (related to
+ * the information available in CircuitLibrary 
+ * and the input size of multiplexers)
+ *************************************************/
+
+#ifndef MUX_LIBRARY_H
+#define MUX_LIBRARY_H
+
+#include <map>
+#include "mux_graph.h"
+#include "mux_library_fwd.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+class MuxLibrary {
+  public: /* Types and ranges */
+    typedef vtr::vector<MuxId, MuxId>::const_iterator mux_iterator;
+
+    typedef vtr::Range<mux_iterator> mux_range;
+  public: /* Public accessors: Aggregates */
+    mux_range muxes() const;
+  public:  /* Public accessors */
+    /* Get a MUX graph (read-only) */
+    MuxId mux_graph(const CircuitModelId& circuit_model, const size_t& mux_size) const;
+    const MuxGraph& mux_graph(const MuxId& mux_id) const;
+    /* Get a mux circuit model id */
+    CircuitModelId mux_circuit_model(const MuxId& mux_id) const;
+    /* Find the mux sizes */
+    size_t max_mux_size() const;
+  public:  /* Public mutators */
+    /* Add a mux to the library */
+    void add_mux(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, const size_t& mux_size); 
+  public:  /* Public validators */
+    bool valid_mux_id(const MuxId& mux) const;
+  private:  /* Private accessors */
+    bool valid_mux_lookup() const;
+    bool valid_mux_circuit_model_id(const CircuitModelId& circuit_model) const;
+    bool valid_mux_size(const CircuitModelId& circuit_model, const size_t& mux_size) const;
+  private:  /* Private mutators: mux_lookup */
+    void build_mux_lookup();
+    /* Invalidate (empty) the mux fast lookup*/
+    void invalidate_mux_lookup();
+  private:  /* Internal data */
+    /* MUX graph-based desription */
+    vtr::vector<MuxId, MuxId> mux_ids_; /* Unique identifier for each mux graph */
+    vtr::vector<MuxId, MuxGraph> mux_graphs_; /* Graphs describing MUX internal structures */
+    vtr::vector<MuxId, CircuitModelId> mux_circuit_models_; /* circuit model id in circuit library */
+
+    /* Local encoder description */
+    //vtr::vector<MuxLocalDecoderId, Decoder> mux_local_encoders_; /* Graphs describing MUX internal structures */
+
+    /* a fast look-up to search mux_graphs with given circuit model and mux size */
+    typedef std::map<CircuitModelId, std::map<size_t, MuxId>> MuxLookup;
+    mutable MuxLookup mux_lookup_; 
+};
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/mux_lib/mux_library_fwd.h b/openfpga/src/mux_lib/mux_library_fwd.h
new file mode 100644
index 000000000..f9a8697d6
--- /dev/null
+++ b/openfpga/src/mux_lib/mux_library_fwd.h
@@ -0,0 +1,25 @@
+/**************************************************
+ * This file includes only declarations for 
+ * the data structures to describe multiplexer structures
+ * Please refer to mux_library.h for more details
+ *************************************************/
+#ifndef MUX_LIBRARY_FWD_H
+#define MUX_LIBRARY_FWD_H
+
+#include "vtr_strong_id.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/* Strong Ids for MUXes */
+struct mux_id_tag;
+struct mux_local_decoder_id_tag;
+
+typedef vtr::StrongId<mux_id_tag> MuxId;
+typedef vtr::StrongId<mux_local_decoder_id_tag> MuxLocalDecoderId;
+
+class MuxLibrary;
+
+} /* end namespace openfpga */
+
+#endif 
diff --git a/openfpga/src/utils/decoder_library_utils.cpp b/openfpga/src/utils/decoder_library_utils.cpp
new file mode 100644
index 000000000..a41e439ef
--- /dev/null
+++ b/openfpga/src/utils/decoder_library_utils.cpp
@@ -0,0 +1,60 @@
+/***************************************************************************************
+ * This file includes most utilized functions for the DecoderLibrary data structure
+ ***************************************************************************************/
+#include <cmath>
+
+#include "vtr_assert.h"
+
+#include "decoder_library_utils.h"
+
+/* Begin namespace openfpga */
+namespace openfpga {
+
+/***************************************************************************************
+ * NOTE: This function is mainly designed for local decoders inside multiplexers
+ * Find the size of address lines for a decoder with a given data output size
+ *                   Addr lines 
+ *                   | | ... | 
+ *                   v v     v
+ *                 +-----------+
+ *                /    Local    \
+ *               /    Decoder    \
+ *              +-----------------+
+ *                | | | ... | | |
+ *                v v v     v v v
+ *                   Data outputs
+ *               
+ *  The outputs are assumes to be one-hot codes (at most only one '1' exist)
+ *  Considering this fact, there are only num_of_outputs + 1 conditions to be encoded.
+ *  Therefore, the number of inputs is ceil(log(num_of_outputs+1)/log(2))
+ *  We plus 1, which is all-zero condition for outputs
+ ***************************************************************************************/
+size_t find_mux_local_decoder_addr_size(const size_t& data_size) {
+  /* if data size is 1, it is an corner case for the decoder (addr = 1) */
+  if (1 == data_size) {
+    return 1;
+  }
+  VTR_ASSERT (2 <= data_size);
+  return ceil(log(data_size) / log(2));
+}
+
+/***************************************************************************************
+ * Try to find if the decoder already exists in the library, 
+ * If there is no such decoder, add it to the library 
+ ***************************************************************************************/
+DecoderId add_mux_local_decoder_to_library(DecoderLibrary& decoder_lib, 
+                                           const size_t data_size) {
+  size_t addr_size = find_mux_local_decoder_addr_size(data_size);
+
+  DecoderId decoder_id = decoder_lib.find_decoder(addr_size, data_size, false, false, true);
+
+  if (DecoderId::INVALID() == decoder_id) { 
+    /* Add the decoder */
+    return decoder_lib.add_decoder(addr_size, data_size, false, false, true);
+  }
+
+  /* There is already a decoder in the library, return the decoder id */
+  return decoder_id;
+}
+
+} /* End namespace openfpga*/
diff --git a/openfpga/src/utils/decoder_library_utils.h b/openfpga/src/utils/decoder_library_utils.h
new file mode 100644
index 000000000..d55a0750a
--- /dev/null
+++ b/openfpga/src/utils/decoder_library_utils.h
@@ -0,0 +1,21 @@
+/***************************************************************************************
+ * Header file for most utilized functions for the DecoderLibrary data structure
+ ***************************************************************************************/
+#ifndef DECODER_LIBRARY_UTILS_H
+#define DECODER_LIBRARY_UTILS_H
+
+#include "decoder_library.h"
+
+/* Begin namespace openfpga */
+namespace openfpga {
+
+bool need_mux_local_decoder(const size_t& data_size);
+
+size_t find_mux_local_decoder_addr_size(const size_t& data_size);
+
+DecoderId add_mux_local_decoder_to_library(DecoderLibrary& decoder_lib, 
+                                           const size_t data_size);
+
+} /* End namespace openfpga*/
+
+#endif
diff --git a/openfpga/src/utils/mux_utils.cpp b/openfpga/src/utils/mux_utils.cpp
new file mode 100644
index 000000000..b921f0589
--- /dev/null
+++ b/openfpga/src/utils/mux_utils.cpp
@@ -0,0 +1,458 @@
+/**************************************************
+ * This file includes a series of most utilized functions 
+ * that are used to implement a multiplexer 
+ *************************************************/
+#include <cmath>
+#include <algorithm>
+
+/* Headers from vtrutil library */
+#include "vtr_log.h"
+#include "vtr_assert.h"
+
+/* Headers from readarchopenfpga library */
+#include "circuit_types.h"
+
+#include "decoder_library_utils.h"
+#include "mux_utils.h"
+
+/* Begin namespace openfpga */
+namespace openfpga {
+
+/* Validate the number of inputs for a multiplexer implementation,
+ * the minimum supported size is 2
+ * otherwise, there is no need for a MUX  
+ */
+bool valid_mux_implementation_num_inputs(const size_t& mux_size) {
+  return (2 <= mux_size);
+}
+
+/**************************************************
+ * Find the actual number of datapath inputs for a multiplexer implementation
+ * 1. if there are no requirements on constant inputs, mux_size is the actual one
+ * 2. if there exist constant inputs, mux_size should minus 1
+ * This function is mainly used to recover the number of datapath inputs
+ * for MUXGraphs which is a generic representation without labelling datapath inputs
+ *************************************************/
+size_t find_mux_num_datapath_inputs(const CircuitLibrary& circuit_lib,
+                                    const CircuitModelId& circuit_model,
+                                    const size_t& mux_size) {
+  /* Should be either MUX or LUT
+   * LUTs do have an tree-like MUX, but there is no need for a constant input! 
+   */
+  VTR_ASSERT ((CIRCUIT_MODEL_MUX == circuit_lib.model_type(circuit_model)) 
+           || (CIRCUIT_MODEL_LUT == circuit_lib.model_type(circuit_model)) );
+
+  if (CIRCUIT_MODEL_LUT == circuit_lib.model_type(circuit_model)) {
+    return mux_size;
+  }
+
+  if (true == circuit_lib.mux_add_const_input(circuit_model)) {
+    return mux_size - 1;
+  }
+  return mux_size;
+}
+
+/**************************************************
+ * Find the actual number of inputs for a multiplexer implementation
+ * 1. if there are no requirements on constant inputs, mux_size is the actual one
+ * 2. if there exist constant inputs, mux_size should plus 1
+ *************************************************/
+size_t find_mux_implementation_num_inputs(const CircuitLibrary& circuit_lib,
+                                          const CircuitModelId& circuit_model,
+                                          const size_t& mux_size) {
+  /* Should be either MUX or LUT
+   * LUTs do have an tree-like MUX, but there is no need for a constant input! 
+   */
+  VTR_ASSERT ((CIRCUIT_MODEL_MUX == circuit_lib.model_type(circuit_model)) 
+           || (CIRCUIT_MODEL_LUT == circuit_lib.model_type(circuit_model)) );
+
+  if (CIRCUIT_MODEL_LUT == circuit_lib.model_type(circuit_model)) {
+    return mux_size;
+  }
+
+  if (true == circuit_lib.mux_add_const_input(circuit_model)) {
+    return mux_size + 1;
+  }
+  return mux_size;
+}
+
+/**************************************************
+ * Find the structure for a multiplexer implementation
+ * 1. In most cases, the structure should follow the 
+ * mux_structure defined by users in the CircuitLibrary
+ * 2. However, a special case may apply when mux_size is 2 
+ * In such case, we will force a TREE structure
+ * regardless of users' specification as this is the 
+ * most efficient structure  
+ *************************************************/
+enum e_circuit_model_structure find_mux_implementation_structure(const CircuitLibrary& circuit_lib,
+					                                           const CircuitModelId& circuit_model,
+						                                       const size_t& mux_size) {
+  /* Ensure the mux size is valid ! */
+  VTR_ASSERT(valid_mux_implementation_num_inputs(mux_size));
+
+  /* Branch on the mux sizes */  
+  if (2 == mux_size) {
+    /* Tree-like is the best structure of CMOS MUX2 */
+    if (CIRCUIT_MODEL_DESIGN_CMOS == circuit_lib.design_tech_type(circuit_model)) {
+      return CIRCUIT_MODEL_STRUCTURE_TREE;
+    }
+    VTR_ASSERT_SAFE(CIRCUIT_MODEL_DESIGN_RRAM == circuit_lib.design_tech_type(circuit_model));
+    /* One-level is the best structure of RRAM MUX2 */
+    return CIRCUIT_MODEL_STRUCTURE_ONELEVEL;
+  }
+
+  return circuit_lib.mux_structure(circuit_model);
+}
+
+/**************************************************
+ * Find the number of levels for a tree-like multiplexer implementation
+ *************************************************/
+size_t find_treelike_mux_num_levels(const size_t& mux_size) {
+  /* Do log2(mux_size), have a basic number */ 
+  size_t level = (size_t)(log((double)mux_size)/log(2.));
+  /* Fix the error, i.e. mux_size=5, level = 2, we have to complete */
+  while (mux_size > pow(2.,(double)level)) {
+    level++;
+  }
+
+  return level;
+}
+
+/**************************************************
+ * Find the number of inputs for majority of branches 
+ * in a multi-level multiplexer implementation
+ *************************************************/
+size_t find_multilevel_mux_branch_num_inputs(const size_t& mux_size,
+                                             const size_t& mux_level) {
+  /* Special Case: mux_size = 2 */
+  if (2 == mux_size) {
+    return mux_size; 
+  }
+  
+  if (1 == mux_level) {
+    return mux_size;
+  }  
+
+  if (2 == mux_level) {
+    size_t num_input_per_unit = (size_t)sqrt(mux_size);
+    while ( num_input_per_unit * num_input_per_unit < mux_size) {
+      num_input_per_unit++;
+    }
+    return num_input_per_unit;
+  }
+
+  VTR_ASSERT_SAFE(2 < mux_level);
+
+  size_t num_input_per_unit = 2;
+  while (pow((double)num_input_per_unit, (double)mux_level) < mux_size) {
+    num_input_per_unit++;
+  }
+
+  if (!valid_mux_implementation_num_inputs(num_input_per_unit)) {
+    VTR_LOG_ERROR("Number of inputs of each basis should be at least 2!\n");
+    exit(1); 
+  }
+  
+  return num_input_per_unit;
+}
+
+/**************************************************
+ * Build a location map for intermediate buffers
+ * that may appear at the multiplexing structure of a LUT
+ * Here is a tricky thing: 
+ * By default, the first and last stage should not exist any intermediate buffers
+ * For example: 
+ * There are 5 stages in a 4-stage multiplexer is available for buffering
+ * but only 3 stages [1,2,3] are intermedate buffers 
+ * and these are users' specification
+ *  
+ *          +-------+          +-------+           +-------+           +-------+
+ * location | stage | location | stage |  location | stage |  location | stage | location 
+ *    [0]   |  [0]  |   [1]    |  [1]  |    [2]    |  [2]  |    [3]    |  [3]  |    [5]
+ *          +-------+          +-------+           +-------+           +-------+
+ *
+ * We will check if the length of location map matches the number of
+ * multiplexer levels. And then complete a location map
+ * for the given multiplexers
+ *************************************************/
+std::vector<bool> build_mux_intermediate_buffer_location_map(const CircuitLibrary& circuit_lib, 
+                                                             const CircuitModelId& circuit_model,
+                                                             const size_t& num_mux_levels) {
+  /* Deposite a default location map */
+  std::vector<bool> location_map(num_mux_levels, false); 
+  std::string location_map_str;
+
+  /* ONLY for LUTs: intermediate buffers may exist if specified */
+  if (CIRCUIT_MODEL_LUT != circuit_lib.model_type(circuit_model)) {
+    return location_map;
+  }
+
+  /* Get location map when the flag of intermediate buffer is on */
+  if (true == circuit_lib.is_lut_intermediate_buffered(circuit_model)) { 
+    location_map_str = circuit_lib.lut_intermediate_buffer_location_map(circuit_model);
+  }
+
+  /* If no location map is specified, we can return here */
+  if (location_map_str.empty()) {
+    return location_map;
+  }
+
+  /* Check if the user-defined location map matches the number of mux levels*/
+  VTR_ASSERT(num_mux_levels - 2 == location_map_str.length());
+
+  /* Apply the location_map string to the intermediate stages of multiplexers */
+  for (size_t i = 0; i < location_map_str.length(); ++i) {
+    /* '1' indicates that an intermediate buffer is needed at the location */
+    if ('1' == location_map_str[i]) {
+      location_map[i + 1] = true;
+    }
+  }
+  
+  return location_map;
+}
+
+/**************************************************
+ * Find the number of reserved configuration bits for a multiplexer
+ * The reserved configuration bits is only used by ReRAM-based multiplexers
+ * It is actually the shared BL/WLs among ReRAMs
+ *************************************************/
+size_t find_mux_num_reserved_config_bits(const CircuitLibrary& circuit_lib,
+                                         const CircuitModelId& mux_model,
+                                         const MuxGraph& mux_graph) {
+  if (CIRCUIT_MODEL_DESIGN_RRAM != circuit_lib.design_tech_type(mux_model)) {
+    return 0;
+  }
+
+  std::vector<size_t> mux_branch_sizes = mux_graph.branch_sizes(); 
+  /* For tree-like multiplexers: they have two shared configuration bits */
+  if ( (1 == mux_branch_sizes.size()) 
+    && (2 == mux_branch_sizes[0]) ) {
+    return mux_branch_sizes[0];
+  }
+  /* One-level multiplexer */
+  if ( 1 == mux_graph.num_levels() ) {
+    return mux_graph.num_inputs();
+  }
+  /* Multi-level multiplexers: TODO: This should be better tested and clarified 
+   * Now the multi-level multiplexers are treated as cascaded one-level multiplexers 
+   * Use the maximum branch sizes and multiply it by the number of levels 
+   */
+  std::vector<size_t>::iterator max_mux_branch_size = std::max_element(mux_branch_sizes.begin(), mux_branch_sizes.end());
+  return mux_graph.num_levels() * (*max_mux_branch_size);
+}
+
+/**************************************************
+ * Find the number of configuration bits for a CMOS multiplexer
+ * In general, the number of configuration bits is 
+ * the number of memory bits for a mux_graph
+ * However, when local decoders are used, 
+ * the number of configuration bits are reduced to log2(X)
+ *************************************************/
+static 
+size_t find_cmos_mux_num_config_bits(const CircuitLibrary& circuit_lib,
+                                     const CircuitModelId& mux_model,
+                                     const MuxGraph& mux_graph,
+                                     const e_config_protocol_type& sram_orgz_type) {
+  size_t num_config_bits = 0; 
+
+  switch (sram_orgz_type) {
+  case CONFIG_MEM_MEMORY_BANK:
+  case CONFIG_MEM_SCAN_CHAIN:
+  case CONFIG_MEM_STANDALONE:
+    num_config_bits = mux_graph.num_memory_bits();
+    break;
+  default:
+    VTR_LOG_ERROR("Invalid type of SRAM organization!\n"); 
+    exit(1);
+  }
+
+  if (false == circuit_lib.mux_use_local_encoder(mux_model)) {
+    return num_config_bits;
+  }
+
+  num_config_bits = 0;
+  /* Multiplexer local encoders are applied to memory bits at each stage */
+  for (const auto& lvl : mux_graph.levels()) {
+    num_config_bits += find_mux_local_decoder_addr_size(mux_graph.num_memory_bits_at_level(lvl));
+  } 
+
+  return num_config_bits;
+}
+
+/**************************************************
+ * Find the number of configuration bits for a RRAM multiplexer
+ * In general, the number of configuration bits is 
+ * the number of levels for a mux_graph
+ * This is due to only the last BL/WL of the multiplexer is
+ * independent from each other
+ * However, when local decoders are used, 
+ * the number of configuration bits should be consider all the
+ * shared(reserved) configuration bits and independent bits 
+ *************************************************/
+static 
+size_t find_rram_mux_num_config_bits(const CircuitLibrary& circuit_lib,
+                                     const CircuitModelId& mux_model,
+                                     const MuxGraph& mux_graph, 
+                                     const e_config_protocol_type& sram_orgz_type) {
+  size_t num_config_bits = 0; 
+  switch (sram_orgz_type) {
+  case CONFIG_MEM_MEMORY_BANK:
+    /* In memory bank, by intensively share the Bit/Word Lines,
+     * we only need 1 additional BL and WL for each MUX level.
+     */
+    num_config_bits = mux_graph.num_levels();
+    break;
+  case CONFIG_MEM_SCAN_CHAIN:
+  case CONFIG_MEM_STANDALONE:
+    /* Currently we DO NOT SUPPORT THESE, given an invalid number */
+    num_config_bits = size_t(-1);
+    break;
+  default:
+    VTR_LOG_ERROR("Invalid type of SRAM organization!\n"); 
+    exit(1);
+  }
+
+  if (true == circuit_lib.mux_use_local_encoder(mux_model)) {
+    /* TODO: this is a to-do work for ReRAM-based multiplexers and FPGAs 
+     * The number of states of a local decoder only depends on how many 
+     * memory bits that the multiplexer will have
+     * This may NOT be correct!!! 
+     */
+    return find_mux_local_decoder_addr_size(mux_graph.num_memory_bits());
+  }
+
+  return num_config_bits;
+}
+
+/**************************************************
+ * Find the number of configuration bits for 
+ * a routing multiplexer
+ * Two cases are considered here.
+ * They are placed in different branches (sub-functions)
+ * in order to be easy in extending to new technology!
+ *************************************************/
+size_t find_mux_num_config_bits(const CircuitLibrary& circuit_lib,
+                                const CircuitModelId& mux_model,
+                                const MuxGraph& mux_graph, 
+                                const e_config_protocol_type& sram_orgz_type) {
+  size_t num_config_bits = size_t(-1);
+
+  switch (circuit_lib.design_tech_type(mux_model)) {
+  case CIRCUIT_MODEL_DESIGN_CMOS:
+    num_config_bits = find_cmos_mux_num_config_bits(circuit_lib, mux_model, mux_graph, sram_orgz_type);
+    break;
+  case CIRCUIT_MODEL_DESIGN_RRAM:
+    num_config_bits = find_rram_mux_num_config_bits(circuit_lib, mux_model, mux_graph, sram_orgz_type);
+    break;
+  default:
+    VTR_LOG_ERROR("Invalid design_technology of MUX(name: %s)\n",
+                  circuit_lib.model_name(mux_model).c_str()); 
+    exit(1);
+  }
+
+  return num_config_bits;
+}
+
+/**************************************************
+ * Find the number of shared configuration bits for a CMOS multiplexer
+ * Currently, all the supported CMOS multiplexers
+ * do NOT require any shared configuration bits 
+ *************************************************/
+static 
+size_t find_cmos_mux_num_shared_config_bits(const e_config_protocol_type& sram_orgz_type) {
+  size_t num_shared_config_bits = 0; 
+
+  switch (sram_orgz_type) {
+  case CONFIG_MEM_MEMORY_BANK:
+  case CONFIG_MEM_SCAN_CHAIN:
+  case CONFIG_MEM_STANDALONE:
+    num_shared_config_bits = 0;
+    break;
+  default:
+    VTR_LOG_ERROR("Invalid type of SRAM organization!\n"); 
+    exit(1);
+  }
+
+  return num_shared_config_bits;
+}
+
+/**************************************************
+ * Find the number of shared configuration bits for a ReRAM multiplexer
+ *************************************************/
+static 
+size_t find_rram_mux_num_shared_config_bits(const CircuitLibrary& circuit_lib,
+                                            const CircuitModelId& mux_model,
+                                            const MuxGraph& mux_graph, 
+                                            const e_config_protocol_type& sram_orgz_type) {
+  size_t num_shared_config_bits = 0; 
+  switch (sram_orgz_type) {
+  case CONFIG_MEM_MEMORY_BANK: {
+    /* In memory bank, the number of shared configuration bits is
+     * the sum of largest branch size at each level 
+     */
+    for (auto lvl : mux_graph.node_levels()) {
+      /* Find the maximum branch size: 
+       * Note that branch_sizes() returns a sorted vector
+       * The last one is the maximum
+       */
+      num_shared_config_bits += mux_graph.branch_sizes(lvl).back();
+    }
+    break;
+  }
+  case CONFIG_MEM_SCAN_CHAIN:
+  case CONFIG_MEM_STANDALONE:
+    /* Currently we DO NOT SUPPORT THESE, given an invalid number */
+    num_shared_config_bits = size_t(-1);
+    break;
+  default:
+    VTR_LOG_ERROR("Invalid type of SRAM organization!\n"); 
+    exit(1);
+  }
+
+  if (true == circuit_lib.mux_use_local_encoder(mux_model)) {
+    /* TODO: this is a to-do work for ReRAM-based multiplexers and FPGAs 
+     * The number of states of a local decoder only depends on how many 
+     * memory bits that the multiplexer will have
+     * This may NOT be correct!!! 
+     * If local encoders are introduced, zero shared configuration bits are required
+     */
+    return 0;
+  }
+
+  return num_shared_config_bits;
+}
+
+/**************************************************
+ * Find the number of shared configuration bits for 
+ * a routing multiplexer
+ * Two cases are considered here.
+ * They are placed in different branches (sub-functions)
+ * in order to be easy in extending to new technology!
+ *
+ * Note: currently, shared configuration bits are demanded
+ * by ReRAM-based multiplexers only
+ *************************************************/
+size_t find_mux_num_shared_config_bits(const CircuitLibrary& circuit_lib,
+                                       const CircuitModelId& mux_model,
+                                       const MuxGraph& mux_graph, 
+                                       const e_config_protocol_type& sram_orgz_type) {
+  size_t num_shared_config_bits = size_t(-1);
+
+  switch (circuit_lib.design_tech_type(mux_model)) {
+  case CIRCUIT_MODEL_DESIGN_CMOS:
+    num_shared_config_bits = find_cmos_mux_num_shared_config_bits(sram_orgz_type);
+    break;
+  case CIRCUIT_MODEL_DESIGN_RRAM:
+    num_shared_config_bits = find_rram_mux_num_shared_config_bits(circuit_lib, mux_model, mux_graph, sram_orgz_type);
+    break;
+  default:
+    VTR_LOG_ERROR("Invalid design_technology of MUX(name: %s)\n",
+                  circuit_lib.model_name(mux_model).c_str()); 
+    exit(1);
+  }
+
+  return num_shared_config_bits;
+}
+
+} /* End namespace openfpga*/
diff --git a/openfpga/src/utils/mux_utils.h b/openfpga/src/utils/mux_utils.h
new file mode 100644
index 000000000..cf2ce95ad
--- /dev/null
+++ b/openfpga/src/utils/mux_utils.h
@@ -0,0 +1,59 @@
+#ifndef MUX_UTILS_H
+#define MUX_UTILS_H
+
+/********************************************************************
+ * Include header files required by the data structure definition
+ *******************************************************************/
+
+#include <vector>
+
+#include "circuit_library.h"
+#include "mux_library.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* Begin namespace openfpga */
+namespace openfpga {
+
+bool valid_mux_implementation_num_inputs(const size_t& mux_size);
+
+size_t find_mux_num_datapath_inputs(const CircuitLibrary& circuit_lib,
+                                    const CircuitModelId& circuit_model,
+                                    const size_t& mux_size);
+
+size_t find_mux_implementation_num_inputs(const CircuitLibrary& circuit_lib,
+                                          const CircuitModelId& circuit_model,
+                                          const size_t& mux_size);
+
+enum e_circuit_model_structure find_mux_implementation_structure(const CircuitLibrary& circuit_lib,
+					                                           const CircuitModelId& circuit_model,
+						                                       const size_t& mux_size);
+
+size_t find_treelike_mux_num_levels(const size_t& mux_size);
+
+size_t find_multilevel_mux_branch_num_inputs(const size_t& mux_size,
+                                             const size_t& mux_level);
+
+std::vector<bool> build_mux_intermediate_buffer_location_map(const CircuitLibrary& circuit_lib, 
+                                                             const CircuitModelId& circuit_model,
+                                                             const size_t& num_mux_levels);
+
+size_t find_mux_num_reserved_config_bits(const CircuitLibrary& circuit_lib,
+                                         const CircuitModelId& mux_model,
+                                         const MuxGraph& mux_graph);
+
+size_t find_mux_num_config_bits(const CircuitLibrary& circuit_lib,
+                                const CircuitModelId& mux_model,
+                                const MuxGraph& mux_graph, 
+                                const e_config_protocol_type& sram_orgz_type);
+
+size_t find_mux_num_shared_config_bits(const CircuitLibrary& circuit_lib,
+                                       const CircuitModelId& mux_model,
+                                       const MuxGraph& mux_graph, 
+                                       const e_config_protocol_type& sram_orgz_type);
+
+} /* End namespace openfpga*/
+
+#endif

From a31d6c6d1e05597574c93defcd379c285ccb8f52 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 12 Feb 2020 09:52:18 -0700
Subject: [PATCH 116/645] rename pb_type annotation to device annotation

---
 openfpga/src/annotation/annotate_pb_graph.cpp |  98 +++++------
 openfpga/src/annotation/annotate_pb_graph.h   |   6 +-
 openfpga/src/annotation/annotate_pb_types.cpp | 162 +++++++++---------
 openfpga/src/annotation/annotate_pb_types.h   |   4 +-
 .../annotation/check_pb_graph_annotation.cpp  |  20 +--
 .../annotation/check_pb_graph_annotation.h    |   4 +-
 .../annotation/check_pb_type_annotation.cpp   |  70 ++++----
 .../src/annotation/check_pb_type_annotation.h |  10 +-
 ...notation.cpp => vpr_device_annotation.cpp} |  72 ++++----
 ...e_annotation.h => vpr_device_annotation.h} |   8 +-
 openfpga/src/base/openfpga_context.h          |   8 +-
 openfpga/src/base/openfpga_link_arch.cpp      |   6 +-
 12 files changed, 234 insertions(+), 234 deletions(-)
 rename openfpga/src/annotation/{vpr_pb_type_annotation.cpp => vpr_device_annotation.cpp} (87%)
 rename openfpga/src/annotation/{vpr_pb_type_annotation.h => vpr_device_annotation.h} (98%)

diff --git a/openfpga/src/annotation/annotate_pb_graph.cpp b/openfpga/src/annotation/annotate_pb_graph.cpp
index 2043c2098..bf93cf28e 100644
--- a/openfpga/src/annotation/annotate_pb_graph.cpp
+++ b/openfpga/src/annotation/annotate_pb_graph.cpp
@@ -28,7 +28,7 @@ namespace openfpga {
  *******************************************************************/
 static 
 void rec_build_vpr_pb_graph_interconnect_physical_type_annotation(t_pb_graph_node* pb_graph_node, 
-                                                                  VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                                                  VprDeviceAnnotation& vpr_device_annotation,
                                                                   const bool& verbose_output) {
   /* Skip the root node because we start from the inputs of child pb_graph node 
    *  
@@ -45,7 +45,7 @@ void rec_build_vpr_pb_graph_interconnect_physical_type_annotation(t_pb_graph_nod
    */
   if (false == pb_graph_node->is_root()) {
     /* We only care the physical modes! But we have to find it through the parent node */
-    t_mode* child_physical_mode = vpr_pb_type_annotation.physical_mode(pb_graph_node->parent_pb_graph_node->pb_type);
+    t_mode* child_physical_mode = vpr_device_annotation.physical_mode(pb_graph_node->parent_pb_graph_node->pb_type);
     VTR_ASSERT(nullptr != child_physical_mode);
 
     std::map<t_interconnect*, size_t> interc_num_inputs;
@@ -83,14 +83,14 @@ void rec_build_vpr_pb_graph_interconnect_physical_type_annotation(t_pb_graph_nod
       }
       
       e_interconnect interc_physical_type = pb_interconnect_physical_type(interc, interc_num_inputs[interc]);
-      if (interc_physical_type == vpr_pb_type_annotation.interconnect_physical_type(interc)) {
+      if (interc_physical_type == vpr_device_annotation.interconnect_physical_type(interc)) {
         /* Skip annotation if we have already done! */
         continue;
       }
       VTR_LOGV(verbose_output,
                "Infer physical type '%s' of interconnect '%s' (was '%s')\n",
                INTERCONNECT_TYPE_STRING[interc_physical_type], interc->name, INTERCONNECT_TYPE_STRING[interc->type]);
-      vpr_pb_type_annotation.add_interconnect_physical_type(interc, interc_physical_type);
+      vpr_device_annotation.add_interconnect_physical_type(interc, interc_physical_type);
     }
   }
 
@@ -100,13 +100,13 @@ void rec_build_vpr_pb_graph_interconnect_physical_type_annotation(t_pb_graph_nod
   }
 
   /* Recursively visit all the child pb_graph_nodes */
-  t_mode* physical_mode = vpr_pb_type_annotation.physical_mode(pb_graph_node->pb_type);
+  t_mode* physical_mode = vpr_device_annotation.physical_mode(pb_graph_node->pb_type);
   VTR_ASSERT(nullptr != physical_mode);
   for (int ipb = 0; ipb < physical_mode->num_pb_type_children; ++ipb) {
     /* Each child may exist multiple times in the hierarchy*/
     for (int jpb = 0; jpb < physical_mode->pb_type_children[ipb].num_pb; ++jpb) {
       rec_build_vpr_pb_graph_interconnect_physical_type_annotation(&(pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb][jpb]),
-                                                                   vpr_pb_type_annotation,
+                                                                   vpr_device_annotation,
                                                                    verbose_output);
     }
   }
@@ -122,14 +122,14 @@ void rec_build_vpr_pb_graph_interconnect_physical_type_annotation(t_pb_graph_nod
  *       build_vpr_physical_pb_mode_implicit_annotation() 
  *******************************************************************/
 void annotate_pb_graph_interconnect_physical_type(const DeviceContext& vpr_device_ctx, 
-                                                  VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                                  VprDeviceAnnotation& vpr_device_annotation,
                                                   const bool& verbose_output) {
   for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
     /* By pass nullptr for pb_graph head */
     if (nullptr == lb_type.pb_graph_head) {
       continue;
     }
-    rec_build_vpr_pb_graph_interconnect_physical_type_annotation(lb_type.pb_graph_head, vpr_pb_type_annotation, verbose_output); 
+    rec_build_vpr_pb_graph_interconnect_physical_type_annotation(lb_type.pb_graph_head, vpr_device_annotation, verbose_output); 
   }
 }
 
@@ -143,7 +143,7 @@ void annotate_pb_graph_interconnect_physical_type(const DeviceContext& vpr_devic
  *******************************************************************/
 static 
 void rec_build_vpr_primitive_pb_graph_node_unique_index(t_pb_graph_node* pb_graph_node, 
-                                                        VprPbTypeAnnotation& vpr_pb_type_annotation) {
+                                                        VprDeviceAnnotation& vpr_device_annotation) {
   /* Go recursive first until we touch the primitive node */
   if (false == is_primitive_pb_type(pb_graph_node->pb_type)) {
     for (int imode = 0; imode < pb_graph_node->pb_type->num_modes; ++imode) {
@@ -151,7 +151,7 @@ void rec_build_vpr_primitive_pb_graph_node_unique_index(t_pb_graph_node* pb_grap
         /* Each child may exist multiple times in the hierarchy*/
         for (int jpb = 0; jpb < pb_graph_node->pb_type->modes[imode].pb_type_children[ipb].num_pb; ++jpb) {
           rec_build_vpr_primitive_pb_graph_node_unique_index(&(pb_graph_node->child_pb_graph_nodes[imode][ipb][jpb]), 
-                                                             vpr_pb_type_annotation);
+                                                             vpr_device_annotation);
         }
       }
     }
@@ -159,7 +159,7 @@ void rec_build_vpr_primitive_pb_graph_node_unique_index(t_pb_graph_node* pb_grap
   }
 
   /* Give a unique index to the pb_graph_node */
-  vpr_pb_type_annotation.add_pb_graph_node_unique_index(pb_graph_node);
+  vpr_device_annotation.add_pb_graph_node_unique_index(pb_graph_node);
 }
 
 /********************************************************************
@@ -178,13 +178,13 @@ void rec_build_vpr_primitive_pb_graph_node_unique_index(t_pb_graph_node* pb_grap
  *******************************************************************/
 static 
 void annotate_primitive_pb_graph_node_unique_index(const DeviceContext& vpr_device_ctx, 
-                                                   VprPbTypeAnnotation& vpr_pb_type_annotation) {
+                                                   VprDeviceAnnotation& vpr_device_annotation) {
   for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
     /* By pass nullptr for pb_graph head */
     if (nullptr == lb_type.pb_graph_head) {
       continue;
     }
-    rec_build_vpr_primitive_pb_graph_node_unique_index(lb_type.pb_graph_head, vpr_pb_type_annotation); 
+    rec_build_vpr_primitive_pb_graph_node_unique_index(lb_type.pb_graph_head, vpr_device_annotation); 
   }
 }
 
@@ -196,9 +196,9 @@ void annotate_primitive_pb_graph_node_unique_index(const DeviceContext& vpr_devi
 static 
 bool try_match_pb_graph_pin(t_pb_graph_pin* operating_pb_graph_pin, 
                             t_pb_graph_pin* physical_pb_graph_pin,
-                            const VprPbTypeAnnotation& vpr_pb_type_annotation) {
+                            const VprDeviceAnnotation& vpr_device_annotation) {
   /* If the parent ports of the two pins are not paired, fail */
-  if (physical_pb_graph_pin->port != vpr_pb_type_annotation.physical_pb_port(operating_pb_graph_pin->port)) {
+  if (physical_pb_graph_pin->port != vpr_device_annotation.physical_pb_port(operating_pb_graph_pin->port)) {
     return false;
   }
   /* Check the pin number of physical pb_graph_pin matches the pin number of 
@@ -217,8 +217,8 @@ bool try_match_pb_graph_pin(t_pb_graph_pin* operating_pb_graph_pin,
    *     by the pin rotate offset value
    *     The accumulated offset will be reset to 0 when it exceeds the msb() of the physical port
    */
-  int acc_offset = vpr_pb_type_annotation.physical_pb_pin_offset(operating_pb_graph_pin->port);
-  const BasicPort& physical_port_range = vpr_pb_type_annotation.physical_pb_port_range(operating_pb_graph_pin->port);
+  int acc_offset = vpr_device_annotation.physical_pb_pin_offset(operating_pb_graph_pin->port);
+  const BasicPort& physical_port_range = vpr_device_annotation.physical_pb_port_range(operating_pb_graph_pin->port);
   if (physical_pb_graph_pin->pin_number != operating_pb_graph_pin->pin_number
                                          + (int)physical_port_range.get_lsb() 
                                          + acc_offset) {
@@ -250,12 +250,12 @@ void print_success_bind_pb_graph_pin(t_pb_graph_pin* operating_pb_graph_pin,
 /********************************************************************
  * Bind a pb_graph_pin from an operating pb_graph_node to 
  * a pb_graph_pin from a physical pb_graph_node
- * - the name matching rules are already defined in the vpr_pb_type_annotation
+ * - the name matching rules are already defined in the vpr_device_annotation
  *******************************************************************/
 static 
 void annotate_physical_pb_graph_pin(t_pb_graph_pin* operating_pb_graph_pin, 
                                     t_pb_graph_node* physical_pb_graph_node, 
-                                    VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                    VprDeviceAnnotation& vpr_device_annotation,
                                     const bool& verbose_output) {
   /* Iterate over every port and pin of the operating pb_graph_node 
    * and find the physical pins 
@@ -264,15 +264,15 @@ void annotate_physical_pb_graph_pin(t_pb_graph_pin* operating_pb_graph_pin,
     for (int ipin = 0; ipin < physical_pb_graph_node->num_input_pins[iport]; ++ipin) {
       if (false == try_match_pb_graph_pin(operating_pb_graph_pin, 
                                           &(physical_pb_graph_node->input_pins[iport][ipin]),
-                                          vpr_pb_type_annotation)) {
+                                          vpr_device_annotation)) {
         continue;
       }
       /* Reach here, it means the pins are matched by the annotation requirements 
        * We can pair the pin and return  
        */
-      vpr_pb_type_annotation.add_physical_pb_graph_pin(operating_pb_graph_pin, &(physical_pb_graph_node->input_pins[iport][ipin]));
+      vpr_device_annotation.add_physical_pb_graph_pin(operating_pb_graph_pin, &(physical_pb_graph_node->input_pins[iport][ipin]));
       if (true == verbose_output) {
-        print_success_bind_pb_graph_pin(operating_pb_graph_pin, vpr_pb_type_annotation.physical_pb_graph_pin(operating_pb_graph_pin)); 
+        print_success_bind_pb_graph_pin(operating_pb_graph_pin, vpr_device_annotation.physical_pb_graph_pin(operating_pb_graph_pin)); 
       }
       return;
     }
@@ -282,15 +282,15 @@ void annotate_physical_pb_graph_pin(t_pb_graph_pin* operating_pb_graph_pin,
     for (int ipin = 0; ipin < physical_pb_graph_node->num_output_pins[iport]; ++ipin) {
       if (false == try_match_pb_graph_pin(operating_pb_graph_pin, 
                                           &(physical_pb_graph_node->output_pins[iport][ipin]),
-                                          vpr_pb_type_annotation)) {
+                                          vpr_device_annotation)) {
         continue;
       }
       /* Reach here, it means the pins are matched by the annotation requirements 
        * We can pair the pin and return  
        */
-      vpr_pb_type_annotation.add_physical_pb_graph_pin(operating_pb_graph_pin, &(physical_pb_graph_node->output_pins[iport][ipin]));
+      vpr_device_annotation.add_physical_pb_graph_pin(operating_pb_graph_pin, &(physical_pb_graph_node->output_pins[iport][ipin]));
       if (true == verbose_output) {
-        print_success_bind_pb_graph_pin(operating_pb_graph_pin, vpr_pb_type_annotation.physical_pb_graph_pin(operating_pb_graph_pin)); 
+        print_success_bind_pb_graph_pin(operating_pb_graph_pin, vpr_device_annotation.physical_pb_graph_pin(operating_pb_graph_pin)); 
       }
       return;
     }
@@ -300,15 +300,15 @@ void annotate_physical_pb_graph_pin(t_pb_graph_pin* operating_pb_graph_pin,
     for (int ipin = 0; ipin < physical_pb_graph_node->num_clock_pins[iport]; ++ipin) {
       if (false == try_match_pb_graph_pin(operating_pb_graph_pin, 
                                           &(physical_pb_graph_node->clock_pins[iport][ipin]),
-                                          vpr_pb_type_annotation)) {
+                                          vpr_device_annotation)) {
         continue;
       }
       /* Reach here, it means the pins are matched by the annotation requirements 
        * We can pair the pin and return  
        */
-      vpr_pb_type_annotation.add_physical_pb_graph_pin(operating_pb_graph_pin, &(physical_pb_graph_node->clock_pins[iport][ipin]));
+      vpr_device_annotation.add_physical_pb_graph_pin(operating_pb_graph_pin, &(physical_pb_graph_node->clock_pins[iport][ipin]));
       if (true == verbose_output) {
-        print_success_bind_pb_graph_pin(operating_pb_graph_pin, vpr_pb_type_annotation.physical_pb_graph_pin(operating_pb_graph_pin)); 
+        print_success_bind_pb_graph_pin(operating_pb_graph_pin, vpr_device_annotation.physical_pb_graph_pin(operating_pb_graph_pin)); 
       }
       return;
     }
@@ -323,13 +323,13 @@ void annotate_physical_pb_graph_pin(t_pb_graph_pin* operating_pb_graph_pin,
 /********************************************************************
  * This function will try bind each pin of the operating pb_graph_node
  * to a pin of the physical pb_graph_node by following the annotation
- * available in vpr_pb_type_annotation
- * It will add the pin bindings to the vpr_pb_type_annotation
+ * available in vpr_device_annotation
+ * It will add the pin bindings to the vpr_device_annotation
  *******************************************************************/
 static 
 void annotate_physical_pb_graph_node_pins(t_pb_graph_node* operating_pb_graph_node, 
                                           t_pb_graph_node* physical_pb_graph_node, 
-                                          VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                          VprDeviceAnnotation& vpr_device_annotation,
                                           const bool& verbose_output) {
   /* Iterate over every port and pin of the operating pb_graph_node 
    * and find the physical pins 
@@ -337,7 +337,7 @@ void annotate_physical_pb_graph_node_pins(t_pb_graph_node* operating_pb_graph_no
   for (int iport = 0; iport < operating_pb_graph_node->num_input_ports; ++iport) {
     for (int ipin = 0; ipin < operating_pb_graph_node->num_input_pins[iport]; ++ipin) {
       annotate_physical_pb_graph_pin(&(operating_pb_graph_node->input_pins[iport][ipin]),
-                                     physical_pb_graph_node, vpr_pb_type_annotation,
+                                     physical_pb_graph_node, vpr_device_annotation,
                                      verbose_output);
     }
   }
@@ -345,7 +345,7 @@ void annotate_physical_pb_graph_node_pins(t_pb_graph_node* operating_pb_graph_no
   for (int iport = 0; iport < operating_pb_graph_node->num_output_ports; ++iport) {
     for (int ipin = 0; ipin < operating_pb_graph_node->num_output_pins[iport]; ++ipin) {
       annotate_physical_pb_graph_pin(&(operating_pb_graph_node->output_pins[iport][ipin]),
-                                     physical_pb_graph_node, vpr_pb_type_annotation,
+                                     physical_pb_graph_node, vpr_device_annotation,
                                      verbose_output);
     }
   }
@@ -353,7 +353,7 @@ void annotate_physical_pb_graph_node_pins(t_pb_graph_node* operating_pb_graph_no
   for (int iport = 0; iport < operating_pb_graph_node->num_clock_ports; ++iport) {
     for (int ipin = 0; ipin < operating_pb_graph_node->num_clock_pins[iport]; ++ipin) {
       annotate_physical_pb_graph_pin(&(operating_pb_graph_node->clock_pins[iport][ipin]),
-                                     physical_pb_graph_node, vpr_pb_type_annotation,
+                                     physical_pb_graph_node, vpr_device_annotation,
                                      verbose_output);
     }
   }
@@ -369,7 +369,7 @@ void annotate_physical_pb_graph_node_pins(t_pb_graph_node* operating_pb_graph_no
  *******************************************************************/
 static 
 void rec_build_vpr_physical_pb_graph_node_annotation(t_pb_graph_node* pb_graph_node, 
-                                                     VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                                     VprDeviceAnnotation& vpr_device_annotation,
                                                      const bool& verbose_output) {
   /* Go recursive first until we touch the primitive node */
   if (false == is_primitive_pb_type(pb_graph_node->pb_type)) {
@@ -378,7 +378,7 @@ void rec_build_vpr_physical_pb_graph_node_annotation(t_pb_graph_node* pb_graph_n
         /* Each child may exist multiple times in the hierarchy*/
         for (int jpb = 0; jpb < pb_graph_node->pb_type->modes[imode].pb_type_children[ipb].num_pb; ++jpb) {
           rec_build_vpr_physical_pb_graph_node_annotation(&(pb_graph_node->child_pb_graph_nodes[imode][ipb][jpb]), 
-                                                          vpr_pb_type_annotation,
+                                                          vpr_device_annotation,
                                                           verbose_output);
         }
       }
@@ -393,7 +393,7 @@ void rec_build_vpr_physical_pb_graph_node_annotation(t_pb_graph_node* pb_graph_n
    *  - Find the physical pb_graph_node with the given index 
    * To bind pins from operating pb_graph_node to their physical pb_graph_node pins
    */
-  t_pb_type* physical_pb_type = vpr_pb_type_annotation.physical_pb_type(pb_graph_node->pb_type); 
+  t_pb_type* physical_pb_type = vpr_device_annotation.physical_pb_type(pb_graph_node->pb_type); 
   VTR_ASSERT(nullptr != physical_pb_type);
 
   /* Index inference:
@@ -401,13 +401,13 @@ void rec_build_vpr_physical_pb_graph_node_annotation(t_pb_graph_node* pb_graph_n
    * where factor and offset are provided by users
    */
   PbGraphNodeId physical_pb_graph_node_id = PbGraphNodeId(
-                                            vpr_pb_type_annotation.physical_pb_type_index_factor(pb_graph_node->pb_type)
-                                          * (size_t)vpr_pb_type_annotation.pb_graph_node_unique_index(pb_graph_node)
-                                          + vpr_pb_type_annotation.physical_pb_type_index_offset(pb_graph_node->pb_type)
+                                            vpr_device_annotation.physical_pb_type_index_factor(pb_graph_node->pb_type)
+                                          * (size_t)vpr_device_annotation.pb_graph_node_unique_index(pb_graph_node)
+                                          + vpr_device_annotation.physical_pb_type_index_offset(pb_graph_node->pb_type)
                                             );
-  t_pb_graph_node* physical_pb_graph_node = vpr_pb_type_annotation.pb_graph_node(physical_pb_type, physical_pb_graph_node_id);
+  t_pb_graph_node* physical_pb_graph_node = vpr_device_annotation.pb_graph_node(physical_pb_type, physical_pb_graph_node_id);
   VTR_ASSERT(nullptr != physical_pb_graph_node);
-  vpr_pb_type_annotation.add_physical_pb_graph_node(pb_graph_node, physical_pb_graph_node);
+  vpr_device_annotation.add_physical_pb_graph_node(pb_graph_node, physical_pb_graph_node);
 
   VTR_LOGV(verbose_output,
            "Bind operating pb_graph_node '%s' to physical pb_graph_node '%s'\n",
@@ -415,7 +415,7 @@ void rec_build_vpr_physical_pb_graph_node_annotation(t_pb_graph_node* pb_graph_n
            physical_pb_graph_node->hierarchical_type_name().c_str());
 
   /* Try to bind each pins under this pb_graph_node to physical_pb_graph_node */
-  annotate_physical_pb_graph_node_pins(pb_graph_node, physical_pb_graph_node, vpr_pb_type_annotation, verbose_output);
+  annotate_physical_pb_graph_node_pins(pb_graph_node, physical_pb_graph_node, vpr_device_annotation, verbose_output);
 }
 
 /********************************************************************
@@ -425,14 +425,14 @@ void rec_build_vpr_physical_pb_graph_node_annotation(t_pb_graph_node* pb_graph_n
  *******************************************************************/
 static 
 void annotate_physical_pb_graph_node(const DeviceContext& vpr_device_ctx, 
-                                     VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                     VprDeviceAnnotation& vpr_device_annotation,
                                      const bool& verbose_output) {
   for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
     /* By pass nullptr for pb_graph head */
     if (nullptr == lb_type.pb_graph_head) {
       continue;
     }
-    rec_build_vpr_physical_pb_graph_node_annotation(lb_type.pb_graph_head, vpr_pb_type_annotation, verbose_output); 
+    rec_build_vpr_physical_pb_graph_node_annotation(lb_type.pb_graph_head, vpr_device_annotation, verbose_output); 
   }
 }
 
@@ -443,21 +443,21 @@ void annotate_physical_pb_graph_node(const DeviceContext& vpr_device_ctx,
  * - Bind pins from operating pb_graph_node to their physical pb_graph_node pins
  *******************************************************************/
 void annotate_pb_graph(const DeviceContext& vpr_device_ctx, 
-                       VprPbTypeAnnotation& vpr_pb_type_annotation,
+                       VprDeviceAnnotation& vpr_device_annotation,
                        const bool& verbose_output) {
 
   VTR_LOG("Assigning unique indices for primitive pb_graph nodes...");
   VTR_LOGV(verbose_output, "\n");
-  annotate_primitive_pb_graph_node_unique_index(vpr_device_ctx, vpr_pb_type_annotation);
+  annotate_primitive_pb_graph_node_unique_index(vpr_device_ctx, vpr_device_annotation);
   VTR_LOG("Done\n");
 
   VTR_LOG("Binding operating pb_graph nodes/pins to physical pb_graph nodes/pins...");
   VTR_LOGV(verbose_output, "\n");
-  annotate_physical_pb_graph_node(vpr_device_ctx, vpr_pb_type_annotation, verbose_output);
+  annotate_physical_pb_graph_node(vpr_device_ctx, vpr_device_annotation, verbose_output);
   VTR_LOG("Done\n");
 
   /* Check each primitive pb_graph_node and pin has been binded to a physical node and pin */
-  check_physical_pb_graph_node_annotation(vpr_device_ctx, const_cast<const VprPbTypeAnnotation&>(vpr_pb_type_annotation));
+  check_physical_pb_graph_node_annotation(vpr_device_ctx, const_cast<const VprDeviceAnnotation&>(vpr_device_annotation));
 }
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/annotation/annotate_pb_graph.h b/openfpga/src/annotation/annotate_pb_graph.h
index 64eced256..5dd140da8 100644
--- a/openfpga/src/annotation/annotate_pb_graph.h
+++ b/openfpga/src/annotation/annotate_pb_graph.h
@@ -6,7 +6,7 @@
  *******************************************************************/
 #include "vpr_context.h"
 #include "openfpga_context.h"
-#include "vpr_pb_type_annotation.h"
+#include "vpr_device_annotation.h"
 
 /********************************************************************
  * Function declaration
@@ -16,11 +16,11 @@
 namespace openfpga {
 
 void annotate_pb_graph_interconnect_physical_type(const DeviceContext& vpr_device_ctx, 
-                                                  VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                                  VprDeviceAnnotation& vpr_pb_type_annotation,
                                                   const bool& verbose_output);
 
 void annotate_pb_graph(const DeviceContext& vpr_device_ctx, 
-                       VprPbTypeAnnotation& vpr_pb_type_annotation,
+                       VprDeviceAnnotation& vpr_pb_type_annotation,
                        const bool& verbose_output);
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/annotation/annotate_pb_types.cpp b/openfpga/src/annotation/annotate_pb_types.cpp
index d70ab7427..d8701be78 100644
--- a/openfpga/src/annotation/annotate_pb_types.cpp
+++ b/openfpga/src/annotation/annotate_pb_types.cpp
@@ -7,7 +7,7 @@
 #include "vtr_assert.h"
 #include "vtr_log.h"
 
-#include "vpr_pb_type_annotation.h"
+#include "vpr_device_annotation.h"
 #include "pb_type_utils.h"
 #include "annotate_pb_graph.h"
 #include "check_pb_type_annotation.h"
@@ -24,7 +24,7 @@ namespace openfpga {
 static 
 void build_vpr_physical_pb_mode_explicit_annotation(const DeviceContext& vpr_device_ctx, 
                                                     const Arch& openfpga_arch,
-                                                    VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                                    VprDeviceAnnotation& vpr_device_annotation,
                                                     const bool& verbose_output) {
   /* Walk through the pb_type annotation stored in the openfpga arch */
   for (const PbTypeAnnotation& pb_type_annotation : openfpga_arch.pb_type_annotations) {
@@ -80,7 +80,7 @@ void build_vpr_physical_pb_mode_explicit_annotation(const DeviceContext& vpr_dev
 
       /* Found, we update the annotation by assigning the physical mode */
       t_mode* physical_mode = find_pb_type_mode(target_pb_type, pb_type_annotation.physical_mode_name().c_str());
-      vpr_pb_type_annotation.add_pb_type_physical_mode(target_pb_type, physical_mode);
+      vpr_device_annotation.add_pb_type_physical_mode(target_pb_type, physical_mode);
       
       /* Give a message */
       VTR_LOGV(verbose_output,
@@ -112,7 +112,7 @@ void build_vpr_physical_pb_mode_explicit_annotation(const DeviceContext& vpr_dev
  *******************************************************************/
 static 
 void rec_infer_vpr_physical_pb_mode_annotation(t_pb_type* cur_pb_type, 
-                                               VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                               VprDeviceAnnotation& vpr_device_annotation,
                                                const bool& verbose_output) {
   /* We do not check any primitive pb_type */
   if (true == is_primitive_pb_type(cur_pb_type)) {
@@ -128,18 +128,18 @@ void rec_infer_vpr_physical_pb_mode_annotation(t_pb_type* cur_pb_type,
   t_mode* physical_mode = nullptr;
 
   if (1 == cur_pb_type->num_modes) {
-    if (nullptr == vpr_pb_type_annotation.physical_mode(cur_pb_type)) {
+    if (nullptr == vpr_device_annotation.physical_mode(cur_pb_type)) {
       /* Not assigned by explicit annotation, we should infer here */
-      vpr_pb_type_annotation.add_pb_type_physical_mode(cur_pb_type, &(cur_pb_type->modes[0]));
+      vpr_device_annotation.add_pb_type_physical_mode(cur_pb_type, &(cur_pb_type->modes[0]));
       VTR_LOGV(verbose_output,
                "Implicitly infer physical mode '%s' for pb_type '%s'\n",
                cur_pb_type->modes[0].name, cur_pb_type->name);
     }
   } else {
     VTR_ASSERT(1 < cur_pb_type->num_modes);
-    if (nullptr == vpr_pb_type_annotation.physical_mode(cur_pb_type)) {
+    if (nullptr == vpr_device_annotation.physical_mode(cur_pb_type)) {
       /* Not assigned by explicit annotation, we should infer here */
-      vpr_pb_type_annotation.add_pb_type_physical_mode(cur_pb_type, &(cur_pb_type->modes[0]));
+      vpr_device_annotation.add_pb_type_physical_mode(cur_pb_type, &(cur_pb_type->modes[0]));
       VTR_LOG_ERROR("Unable to find a physical mode for a multi-mode pb_type '%s'!\n",
                     cur_pb_type->name);
       VTR_LOG_ERROR("Please specify in the OpenFPGA architecture\n");
@@ -148,14 +148,14 @@ void rec_infer_vpr_physical_pb_mode_annotation(t_pb_type* cur_pb_type,
   }
 
   /* Get the physical mode from annotation */ 
-  physical_mode = vpr_pb_type_annotation.physical_mode(cur_pb_type);
+  physical_mode = vpr_device_annotation.physical_mode(cur_pb_type);
 
   VTR_ASSERT(nullptr != physical_mode);
 
   /* Traverse the pb_type children under the physical mode */
   for (int ichild = 0; ichild < physical_mode->num_pb_type_children; ++ichild) { 
     rec_infer_vpr_physical_pb_mode_annotation(&(physical_mode->pb_type_children[ichild]),
-                                              vpr_pb_type_annotation,
+                                              vpr_device_annotation,
                                               verbose_output);
   }
 }
@@ -174,14 +174,14 @@ void rec_infer_vpr_physical_pb_mode_annotation(t_pb_type* cur_pb_type,
  *******************************************************************/
 static 
 void build_vpr_physical_pb_mode_implicit_annotation(const DeviceContext& vpr_device_ctx, 
-                                                    VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                                    VprDeviceAnnotation& vpr_device_annotation,
                                                     const bool& verbose_output) {
   for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
     /* By pass nullptr for pb_type head */
     if (nullptr == lb_type.pb_type) {
       continue;
     }
-    rec_infer_vpr_physical_pb_mode_annotation(lb_type.pb_type, vpr_pb_type_annotation, verbose_output); 
+    rec_infer_vpr_physical_pb_mode_annotation(lb_type.pb_type, vpr_device_annotation, verbose_output); 
   }
 }
 
@@ -196,13 +196,13 @@ void build_vpr_physical_pb_mode_implicit_annotation(const DeviceContext& vpr_dev
  *   we assume their physical ports share the same as the operating ports
  *   We will try to find a port in the physical pb_type and check the port range
  *   If found, we will create a pair 
- * - All the pairs will be updated in vpr_pb_type_annotation
+ * - All the pairs will be updated in vpr_device_annotation
  *******************************************************************/
 static 
 bool pair_operating_and_physical_pb_types(t_pb_type* operating_pb_type, 
                                           t_pb_type* physical_pb_type,
                                           const PbTypeAnnotation& pb_type_annotation,
-                                          VprPbTypeAnnotation& vpr_pb_type_annotation) {
+                                          VprDeviceAnnotation& vpr_device_annotation) {
   /* Reach here, we should have valid operating and physical pb_types */
   VTR_ASSERT((nullptr != operating_pb_type) && (nullptr != physical_pb_type));
   
@@ -229,24 +229,24 @@ bool pair_operating_and_physical_pb_types(t_pb_type* operating_pb_type,
     if (false == BasicPort(physical_pb_port->name, physical_pb_port->num_pins).contained(expected_physical_pb_port)) {
       return false;
     }
-    /* Now, port mapping should succeed, we update the vpr_pb_type_annotation 
+    /* Now, port mapping should succeed, we update the vpr_device_annotation 
      * - port binding
      * - port range
      * - port pin rotate offset
      */
-    vpr_pb_type_annotation.add_physical_pb_port(operating_pb_port, physical_pb_port);
-    vpr_pb_type_annotation.add_physical_pb_port_range(operating_pb_port, expected_physical_pb_port);
-    vpr_pb_type_annotation.add_physical_pb_pin_rotate_offset(operating_pb_port, pb_type_annotation.physical_pin_rotate_offset(std::string(operating_pb_port->name)));
+    vpr_device_annotation.add_physical_pb_port(operating_pb_port, physical_pb_port);
+    vpr_device_annotation.add_physical_pb_port_range(operating_pb_port, expected_physical_pb_port);
+    vpr_device_annotation.add_physical_pb_pin_rotate_offset(operating_pb_port, pb_type_annotation.physical_pin_rotate_offset(std::string(operating_pb_port->name)));
   }
 
-  /* Now, pb_type mapping should succeed, we update the vpr_pb_type_annotation
+  /* Now, pb_type mapping should succeed, we update the vpr_device_annotation
    *   - pb_type binding
    *   - physical_pb_type_index_factor
    *   - physical_pb_type_index_offset
    */
-  vpr_pb_type_annotation.add_physical_pb_type(operating_pb_type, physical_pb_type);
-  vpr_pb_type_annotation.add_physical_pb_type_index_factor(operating_pb_type, pb_type_annotation.physical_pb_type_index_factor());
-  vpr_pb_type_annotation.add_physical_pb_type_index_offset(operating_pb_type, pb_type_annotation.physical_pb_type_index_offset());
+  vpr_device_annotation.add_physical_pb_type(operating_pb_type, physical_pb_type);
+  vpr_device_annotation.add_physical_pb_type_index_factor(operating_pb_type, pb_type_annotation.physical_pb_type_index_factor());
+  vpr_device_annotation.add_physical_pb_type_index_offset(operating_pb_type, pb_type_annotation.physical_pb_type_index_offset());
 
   return true;
 }
@@ -263,7 +263,7 @@ bool pair_operating_and_physical_pb_types(t_pb_type* operating_pb_type,
 static 
 void build_vpr_physical_pb_type_explicit_annotation(const DeviceContext& vpr_device_ctx, 
                                                     const Arch& openfpga_arch,
-                                                    VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                                    VprDeviceAnnotation& vpr_device_annotation,
                                                     const bool& verbose_output) {
   /* Walk through the pb_type annotation stored in the openfpga arch */
   for (const PbTypeAnnotation& pb_type_annotation : openfpga_arch.pb_type_annotations) {
@@ -328,7 +328,7 @@ void build_vpr_physical_pb_type_explicit_annotation(const DeviceContext& vpr_dev
        * we update the annotation by assigning the physical mode 
        */
       if (true == pair_operating_and_physical_pb_types(target_op_pb_type, target_phy_pb_type,
-                                                       pb_type_annotation, vpr_pb_type_annotation)) {
+                                                       pb_type_annotation, vpr_device_annotation)) {
       
         /* Give a message */
         VTR_LOGV(verbose_output,
@@ -354,7 +354,7 @@ void build_vpr_physical_pb_type_explicit_annotation(const DeviceContext& vpr_dev
  *******************************************************************/
 static 
 bool self_pair_physical_pb_types(t_pb_type* physical_pb_type, 
-                                 VprPbTypeAnnotation& vpr_pb_type_annotation) {
+                                 VprDeviceAnnotation& vpr_device_annotation) {
   /* Reach here, we should have valid physical pb_types */
   VTR_ASSERT(nullptr != physical_pb_type);
   
@@ -364,12 +364,12 @@ bool self_pair_physical_pb_types(t_pb_type* physical_pb_type,
    */
   for (t_port* physical_pb_port : pb_type_ports(physical_pb_type)) {
     BasicPort physical_port_range(physical_pb_port->name, physical_pb_port->num_pins);
-    vpr_pb_type_annotation.add_physical_pb_port(physical_pb_port, physical_pb_port);
-    vpr_pb_type_annotation.add_physical_pb_port_range(physical_pb_port, physical_port_range);
+    vpr_device_annotation.add_physical_pb_port(physical_pb_port, physical_pb_port);
+    vpr_device_annotation.add_physical_pb_port_range(physical_pb_port, physical_port_range);
   }
 
-  /* Now, pb_type mapping should succeed, we update the vpr_pb_type_annotation */
-  vpr_pb_type_annotation.add_physical_pb_type(physical_pb_type, physical_pb_type);
+  /* Now, pb_type mapping should succeed, we update the vpr_device_annotation */
+  vpr_device_annotation.add_physical_pb_type(physical_pb_type, physical_pb_type);
 
   return true;
 }
@@ -384,16 +384,16 @@ bool self_pair_physical_pb_types(t_pb_type* physical_pb_type,
  *******************************************************************/
 static 
 void rec_infer_vpr_physical_pb_type_annotation(t_pb_type* cur_pb_type, 
-                                               VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                               VprDeviceAnnotation& vpr_device_annotation,
                                                const bool& verbose_output) {
   /* Physical pb_type is mainly for the primitive pb_type */
   if (true == is_primitive_pb_type(cur_pb_type)) {
     /* If the physical pb_type has been mapped, we can skip it */
-    if (nullptr != vpr_pb_type_annotation.physical_pb_type(cur_pb_type)) {
+    if (nullptr != vpr_device_annotation.physical_pb_type(cur_pb_type)) {
       return;
     }
     /* Create the pair here */
-    if (true == self_pair_physical_pb_types(cur_pb_type, vpr_pb_type_annotation)) {
+    if (true == self_pair_physical_pb_types(cur_pb_type, vpr_device_annotation)) {
       /* Give a message */
       VTR_LOGV(verbose_output,
                "Implicitly infer the physical pb_type for pb_type '%s' itself\n",
@@ -406,14 +406,14 @@ void rec_infer_vpr_physical_pb_type_annotation(t_pb_type* cur_pb_type,
   }
 
   /* Get the physical mode from annotation */ 
-  t_mode* physical_mode = vpr_pb_type_annotation.physical_mode(cur_pb_type);
+  t_mode* physical_mode = vpr_device_annotation.physical_mode(cur_pb_type);
 
   VTR_ASSERT(nullptr != physical_mode);
 
   /* Traverse the pb_type children under the physical mode */
   for (int ichild = 0; ichild < physical_mode->num_pb_type_children; ++ichild) { 
     rec_infer_vpr_physical_pb_type_annotation(&(physical_mode->pb_type_children[ichild]),
-                                              vpr_pb_type_annotation, 
+                                              vpr_device_annotation, 
                                               verbose_output);
   }
 }
@@ -429,14 +429,14 @@ void rec_infer_vpr_physical_pb_type_annotation(t_pb_type* cur_pb_type,
  *******************************************************************/
 static 
 void build_vpr_physical_pb_type_implicit_annotation(const DeviceContext& vpr_device_ctx, 
-                                                    VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                                    VprDeviceAnnotation& vpr_device_annotation,
                                                     const bool& verbose_output) {
   for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
     /* By pass nullptr for pb_type head */
     if (nullptr == lb_type.pb_type) {
       continue;
     }
-    rec_infer_vpr_physical_pb_type_annotation(lb_type.pb_type, vpr_pb_type_annotation, verbose_output); 
+    rec_infer_vpr_physical_pb_type_annotation(lb_type.pb_type, vpr_device_annotation, verbose_output); 
   }
 }
 
@@ -450,7 +450,7 @@ static
 bool link_physical_pb_port_to_circuit_port(t_pb_type* physical_pb_type, 
                                            const CircuitLibrary& circuit_lib,
                                            const CircuitModelId& circuit_model,
-                                           VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                           VprDeviceAnnotation& vpr_device_annotation,
                                            const bool& verbose_output) {
   bool link_success = true;
   /* Iterate over the pb_ports
@@ -492,8 +492,8 @@ bool link_physical_pb_port_to_circuit_port(t_pb_type* physical_pb_type,
       continue;
     }
 
-    /* Reach here, it means that mapping should be ok, update the vpr_pb_type_annotation */
-    vpr_pb_type_annotation.add_pb_circuit_port(pb_port, circuit_port);
+    /* Reach here, it means that mapping should be ok, update the vpr_device_annotation */
+    vpr_device_annotation.add_pb_circuit_port(pb_port, circuit_port);
     VTR_LOGV(verbose_output,
              "Bind pb type '%s' port '%s' to circuit model '%s' port '%s'\n",
              physical_pb_type->name,
@@ -513,13 +513,13 @@ static
 bool link_physical_pb_type_to_circuit_model(t_pb_type* physical_pb_type, 
                                             const CircuitLibrary& circuit_lib,
                                             const PbTypeAnnotation& pb_type_annotation,
-                                            VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                            VprDeviceAnnotation& vpr_device_annotation,
                                             const bool& verbose_output) {
   /* Reach here, we should have valid operating and physical pb_types */
   VTR_ASSERT(nullptr != physical_pb_type);
 
   /* This must be a physical pb_type according to our annotation! */
-  if (false == vpr_pb_type_annotation.is_physical_pb_type(physical_pb_type)) {
+  if (false == vpr_device_annotation.is_physical_pb_type(physical_pb_type)) {
     VTR_LOG_ERROR("An operating pb_type '%s' is not allowed to be linked to any circuit model!\n",
                   physical_pb_type->name);
     return false;
@@ -537,12 +537,12 @@ bool link_physical_pb_type_to_circuit_model(t_pb_type* physical_pb_type,
 
   /* Ensure that the pb_type ports can be matched in the circuit model ports */
   if (false == link_physical_pb_port_to_circuit_port(physical_pb_type, circuit_lib, circuit_model_id, 
-                                                     vpr_pb_type_annotation, verbose_output)) {
+                                                     vpr_device_annotation, verbose_output)) {
     return false;
   }
 
-  /* Now the circuit model is valid, update the vpr_pb_type_annotation */
-  vpr_pb_type_annotation.add_pb_type_circuit_model(physical_pb_type, circuit_model_id);
+  /* Now the circuit model is valid, update the vpr_device_annotation */
+  vpr_device_annotation.add_pb_type_circuit_model(physical_pb_type, circuit_model_id);
   return true;
 }
 
@@ -555,7 +555,7 @@ bool link_physical_pb_interconnect_to_circuit_model(t_pb_type* physical_pb_type,
                                                     const std::string& interconnect_name,
                                                     const CircuitLibrary& circuit_lib,
                                                     const PbTypeAnnotation& pb_type_annotation,
-                                                    VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                                    VprDeviceAnnotation& vpr_device_annotation,
                                                     const bool& verbose_output) {
   /* The physical pb_type should NOT be a primitive, otherwise it should never contain any interconnect */
   if (true == is_primitive_pb_type(physical_pb_type)) {
@@ -565,7 +565,7 @@ bool link_physical_pb_interconnect_to_circuit_model(t_pb_type* physical_pb_type,
   }
 
   /* Get the physical mode from annotation */ 
-  t_mode* physical_mode = vpr_pb_type_annotation.physical_mode(physical_pb_type);
+  t_mode* physical_mode = vpr_device_annotation.physical_mode(physical_pb_type);
 
   VTR_ASSERT(nullptr != physical_mode);
 
@@ -594,7 +594,7 @@ bool link_physical_pb_interconnect_to_circuit_model(t_pb_type* physical_pb_type,
   }
   
   /* Double check the type of circuit model, it should be the same as required physical type */
-  e_circuit_model_type required_circuit_model_type = pb_interconnect_require_circuit_model_type(vpr_pb_type_annotation.interconnect_physical_type(pb_interc));
+  e_circuit_model_type required_circuit_model_type = pb_interconnect_require_circuit_model_type(vpr_device_annotation.interconnect_physical_type(pb_interc));
   if (circuit_lib.model_type(circuit_model_id) != required_circuit_model_type) {
     VTR_LOG_ERROR("Circuit model '%s' type '%s' does not match required type '%s' for interconnect '%s' under physical mode '%s' of pb_type '%s'!\n",
                   circuit_lib.model_name(circuit_model_id).c_str(),
@@ -606,8 +606,8 @@ bool link_physical_pb_interconnect_to_circuit_model(t_pb_type* physical_pb_type,
     return false;
   }
 
-  /* Now the circuit model is valid, update the vpr_pb_type_annotation */
-  vpr_pb_type_annotation.add_interconnect_circuit_model(pb_interc, circuit_model_id);
+  /* Now the circuit model is valid, update the vpr_device_annotation */
+  vpr_device_annotation.add_interconnect_circuit_model(pb_interc, circuit_model_id);
 
   VTR_LOGV(verbose_output,
            "Bind pb_type '%s' physical mode '%s' interconnect '%s' to circuit model '%s'\n",
@@ -631,7 +631,7 @@ bool link_physical_pb_interconnect_to_circuit_model(t_pb_type* physical_pb_type,
 static 
 void link_vpr_pb_type_to_circuit_model_explicit_annotation(const DeviceContext& vpr_device_ctx, 
                                                            const Arch& openfpga_arch,
-                                                           VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                                           VprDeviceAnnotation& vpr_device_annotation,
                                                            const bool& verbose_output) {
   /* Walk through the pb_type annotation stored in the openfpga arch */
   for (const PbTypeAnnotation& pb_type_annotation : openfpga_arch.pb_type_annotations) {
@@ -683,13 +683,13 @@ void link_vpr_pb_type_to_circuit_model_explicit_annotation(const DeviceContext&
 
       /* Only try to bind pb_type to circuit model when it is defined by users */
       if (true == link_physical_pb_type_to_circuit_model(target_phy_pb_type, openfpga_arch.circuit_lib,
-                                                         pb_type_annotation, vpr_pb_type_annotation, 
+                                                         pb_type_annotation, vpr_device_annotation, 
                                                          verbose_output)) {
         /* Give a message */
         VTR_LOGV(verbose_output,
                  "Bind physical pb_type '%s' to its circuit model '%s'\n",
                  target_phy_pb_type->name,
-                 openfpga_arch.circuit_lib.model_name(vpr_pb_type_annotation.pb_type_circuit_model(target_phy_pb_type)).c_str());
+                 openfpga_arch.circuit_lib.model_name(vpr_device_annotation.pb_type_circuit_model(target_phy_pb_type)).c_str());
 
         link_success = true;
         break;
@@ -718,7 +718,7 @@ void link_vpr_pb_type_to_circuit_model_explicit_annotation(const DeviceContext&
 static 
 void link_vpr_pb_interconnect_to_circuit_model_explicit_annotation(const DeviceContext& vpr_device_ctx, 
                                                                    const Arch& openfpga_arch,
-                                                                   VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                                                   VprDeviceAnnotation& vpr_device_annotation,
                                                                    const bool& verbose_output) {
   /* Walk through the pb_type annotation stored in the openfpga arch */
   for (const PbTypeAnnotation& pb_type_annotation : openfpga_arch.pb_type_annotations) {
@@ -771,7 +771,7 @@ void link_vpr_pb_interconnect_to_circuit_model_explicit_annotation(const DeviceC
       /* Only try to bind interconnect to circuit model when it is defined by users */
       for (const std::string& interc_name : pb_type_annotation.interconnect_names()) {
         if (false == link_physical_pb_interconnect_to_circuit_model(target_phy_pb_type, interc_name, openfpga_arch.circuit_lib,
-                                                                    pb_type_annotation, vpr_pb_type_annotation,
+                                                                    pb_type_annotation, vpr_device_annotation,
                                                                     verbose_output)) {
            VTR_LOG_ERROR("Unable to bind pb_type '%s' interconnect '%s' to circuit model '%s'!\n",
                           target_phy_pb_type_names.back().c_str(),
@@ -812,7 +812,7 @@ void link_vpr_pb_interconnect_to_circuit_model_explicit_annotation(const DeviceC
 static 
 void rec_infer_vpr_pb_interconnect_circuit_model_annotation(t_pb_type* cur_pb_type, 
                                                             const CircuitLibrary& circuit_lib,
-                                                            VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                                            VprDeviceAnnotation& vpr_device_annotation,
                                                             const bool& verbose_output) {
   /* We do not check any primitive pb_type */
   if (true == is_primitive_pb_type(cur_pb_type)) {
@@ -820,18 +820,18 @@ void rec_infer_vpr_pb_interconnect_circuit_model_annotation(t_pb_type* cur_pb_ty
   }
 
   /* Get the physical mode from annotation */ 
-  t_mode* physical_mode = vpr_pb_type_annotation.physical_mode(cur_pb_type);
+  t_mode* physical_mode = vpr_device_annotation.physical_mode(cur_pb_type);
 
   VTR_ASSERT(nullptr != physical_mode);
 
   /* Annotate the circuit model for each interconnect under this physical mode */
   for (t_interconnect* pb_interc : pb_mode_interconnects(physical_mode)) {
     /* If the interconnect has been annotated, we skip it */
-    if (CircuitModelId::INVALID() != vpr_pb_type_annotation.interconnect_circuit_model(pb_interc)) {
+    if (CircuitModelId::INVALID() != vpr_device_annotation.interconnect_circuit_model(pb_interc)) {
       continue;
     }
     /* Infer the circuit model type for a given interconnect */
-    e_circuit_model_type circuit_model_type = pb_interconnect_require_circuit_model_type(vpr_pb_type_annotation.interconnect_physical_type(pb_interc));
+    e_circuit_model_type circuit_model_type = pb_interconnect_require_circuit_model_type(vpr_device_annotation.interconnect_physical_type(pb_interc));
     /* Try to find a default circuit model from the circuit library */
     CircuitModelId default_circuit_model = circuit_lib.default_model(circuit_model_type);
     /* Update the annotation if the model id is valid */
@@ -841,7 +841,7 @@ void rec_infer_vpr_pb_interconnect_circuit_model_annotation(t_pb_type* cur_pb_ty
                     physical_mode->name, 
                     cur_pb_type->name);
     }
-    vpr_pb_type_annotation.add_interconnect_circuit_model(pb_interc, default_circuit_model); 
+    vpr_device_annotation.add_interconnect_circuit_model(pb_interc, default_circuit_model); 
     VTR_LOGV(verbose_output,
              "Implicitly infer a circuit model '%s' for interconnect '%s' under physical mode '%s' of pb_type '%s'\n",
              circuit_lib.model_name(default_circuit_model).c_str(),
@@ -853,7 +853,7 @@ void rec_infer_vpr_pb_interconnect_circuit_model_annotation(t_pb_type* cur_pb_ty
   /* Traverse the pb_type children under the physical mode */
   for (int ichild = 0; ichild < physical_mode->num_pb_type_children; ++ichild) { 
     rec_infer_vpr_pb_interconnect_circuit_model_annotation(&(physical_mode->pb_type_children[ichild]),
-                                                           circuit_lib, vpr_pb_type_annotation,
+                                                           circuit_lib, vpr_device_annotation,
                                                            verbose_output);
   }
 }
@@ -871,25 +871,25 @@ void rec_infer_vpr_pb_interconnect_circuit_model_annotation(t_pb_type* cur_pb_ty
 static 
 void link_vpr_pb_interconnect_to_circuit_model_implicit_annotation(const DeviceContext& vpr_device_ctx,
                                                                    const CircuitLibrary& circuit_lib,
-                                                                   VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                                                   VprDeviceAnnotation& vpr_device_annotation,
                                                                    const bool& verbose_output) {
   for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
     /* By pass nullptr for pb_type head */
     if (nullptr == lb_type.pb_type) {
       continue;
     }
-    rec_infer_vpr_pb_interconnect_circuit_model_annotation(lb_type.pb_type, circuit_lib, vpr_pb_type_annotation, verbose_output); 
+    rec_infer_vpr_pb_interconnect_circuit_model_annotation(lb_type.pb_type, circuit_lib, vpr_device_annotation, verbose_output); 
   }
 }
 
 /********************************************************************
  * This function will bind mode selection bits to a primitive pb_type
- * in the vpr_pb_type_annotation
+ * in the vpr_device_annotation
  *******************************************************************/
 static 
 bool link_primitive_pb_type_to_mode_bits(t_pb_type* primitive_pb_type, 
                                          const PbTypeAnnotation& pb_type_annotation,
-                                         VprPbTypeAnnotation& vpr_pb_type_annotation) {
+                                         VprDeviceAnnotation& vpr_device_annotation) {
   /* Error out if this is not a primitive pb_type */
   if (false == is_primitive_pb_type(primitive_pb_type)) {
     VTR_LOG_ERROR("Mode selection is only applicable to primitive pb_type while pb_type '%s' is not primitve !\n",
@@ -898,7 +898,7 @@ bool link_primitive_pb_type_to_mode_bits(t_pb_type* primitive_pb_type,
   }
 
   /* Update the annotation */
-  vpr_pb_type_annotation.add_pb_type_mode_bits(primitive_pb_type, pb_type_annotation.mode_bits());
+  vpr_device_annotation.add_pb_type_mode_bits(primitive_pb_type, pb_type_annotation.mode_bits());
 
   return true;
 }
@@ -916,7 +916,7 @@ bool link_primitive_pb_type_to_mode_bits(t_pb_type* primitive_pb_type,
 static 
 void link_vpr_pb_type_to_mode_bits_explicit_annotation(const DeviceContext& vpr_device_ctx, 
                                                        const Arch& openfpga_arch,
-                                                       VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                                       VprDeviceAnnotation& vpr_device_annotation,
                                                        const bool& verbose_output) {
   /* Walk through the pb_type annotation stored in the openfpga arch */
   for (const PbTypeAnnotation& pb_type_annotation : openfpga_arch.pb_type_annotations) {
@@ -973,7 +973,7 @@ void link_vpr_pb_type_to_mode_bits_explicit_annotation(const DeviceContext& vpr_
 
       /* Only try to bind pb_type to circuit model when it is defined by users */
       if (true == link_primitive_pb_type_to_mode_bits(target_pb_type,
-                                                      pb_type_annotation, vpr_pb_type_annotation)) {
+                                                      pb_type_annotation, vpr_device_annotation)) {
         /* Give a message */
         VTR_LOGV(verbose_output,
                  "Bind physical pb_type '%s' to mode selection bits '%s'\n",
@@ -1002,7 +1002,7 @@ void link_vpr_pb_type_to_mode_bits_explicit_annotation(const DeviceContext& vpr_
  *******************************************************************/
 void annotate_pb_types(const DeviceContext& vpr_device_ctx, 
                        const Arch& openfpga_arch,
-                       VprPbTypeAnnotation& vpr_pb_type_annotation,
+                       VprDeviceAnnotation& vpr_device_annotation,
                        const bool& verbose_output) {
 
   /* Annotate physical mode to pb_type in the VPR pb_type graph */
@@ -1010,16 +1010,16 @@ void annotate_pb_types(const DeviceContext& vpr_device_ctx,
   VTR_LOG("Building annotation for physical modes in pb_type...");
   VTR_LOGV(verbose_output, "\n");
   build_vpr_physical_pb_mode_explicit_annotation(vpr_device_ctx, openfpga_arch,
-                                                 vpr_pb_type_annotation,
+                                                 vpr_device_annotation,
                                                  verbose_output);
 
   build_vpr_physical_pb_mode_implicit_annotation(vpr_device_ctx,
-                                                 vpr_pb_type_annotation,
+                                                 vpr_device_annotation,
                                                  verbose_output);
   VTR_LOG("Done\n");
 
   check_vpr_physical_pb_mode_annotation(vpr_device_ctx, 
-                                        const_cast<const VprPbTypeAnnotation&>(vpr_pb_type_annotation));
+                                        const_cast<const VprDeviceAnnotation&>(vpr_device_annotation));
 
   /* Annotate the physical type for each interconnect under physical modes
    * Must run AFTER physical mode annotation is done and 
@@ -1029,7 +1029,7 @@ void annotate_pb_types(const DeviceContext& vpr_device_ctx,
   VTR_LOG("Building annotation about physical types for pb_type interconnection...");
   VTR_LOGV(verbose_output, "\n");
   annotate_pb_graph_interconnect_physical_type(vpr_device_ctx, 
-                                               vpr_pb_type_annotation,
+                                               vpr_device_annotation,
                                                verbose_output);
   VTR_LOG("Done\n");
 
@@ -1043,16 +1043,16 @@ void annotate_pb_types(const DeviceContext& vpr_device_ctx,
   VTR_LOG("Building annotation between operating and physical pb_types...");
   VTR_LOGV(verbose_output, "\n");
   build_vpr_physical_pb_type_explicit_annotation(vpr_device_ctx, openfpga_arch,
-                                                 vpr_pb_type_annotation,
+                                                 vpr_device_annotation,
                                                  verbose_output);
 
   build_vpr_physical_pb_type_implicit_annotation(vpr_device_ctx,
-                                                 vpr_pb_type_annotation,
+                                                 vpr_device_annotation,
                                                  verbose_output);
   VTR_LOG("Done\n");
 
   check_vpr_physical_pb_type_annotation(vpr_device_ctx, 
-                                        const_cast<const VprPbTypeAnnotation&>(vpr_pb_type_annotation));
+                                        const_cast<const VprDeviceAnnotation&>(vpr_device_annotation));
 
   /* Link 
    * - physical pb_type to circuit model
@@ -1062,32 +1062,32 @@ void annotate_pb_types(const DeviceContext& vpr_device_ctx,
   VTR_LOG("Building annotation between physical pb_types and circuit models...");
   VTR_LOGV(verbose_output, "\n");
   link_vpr_pb_type_to_circuit_model_explicit_annotation(vpr_device_ctx, openfpga_arch,
-                                                        vpr_pb_type_annotation,
+                                                        vpr_device_annotation,
                                                         verbose_output);
 
   link_vpr_pb_interconnect_to_circuit_model_explicit_annotation(vpr_device_ctx, openfpga_arch,
-                                                                vpr_pb_type_annotation,
+                                                                vpr_device_annotation,
                                                                 verbose_output);
 
   link_vpr_pb_interconnect_to_circuit_model_implicit_annotation(vpr_device_ctx, openfpga_arch.circuit_lib,
-                                                                vpr_pb_type_annotation,
+                                                                vpr_device_annotation,
                                                                 verbose_output);
   VTR_LOG("Done\n");
 
   check_vpr_pb_type_circuit_model_annotation(vpr_device_ctx, openfpga_arch.circuit_lib,
-                                             const_cast<const VprPbTypeAnnotation&>(vpr_pb_type_annotation));
+                                             const_cast<const VprDeviceAnnotation&>(vpr_device_annotation));
 
   /* Link physical pb_type to mode_bits */
   VTR_LOG("\n");
   VTR_LOG("Building annotation between physical pb_types and mode selection bits...");
   VTR_LOGV(verbose_output, "\n");
   link_vpr_pb_type_to_mode_bits_explicit_annotation(vpr_device_ctx, openfpga_arch,
-                                                    vpr_pb_type_annotation,
+                                                    vpr_device_annotation,
                                                     verbose_output);
   VTR_LOG("Done\n");
 
   check_vpr_pb_type_mode_bits_annotation(vpr_device_ctx, openfpga_arch.circuit_lib,
-                                         const_cast<const VprPbTypeAnnotation&>(vpr_pb_type_annotation));
+                                         const_cast<const VprDeviceAnnotation&>(vpr_device_annotation));
 
 } 
 
diff --git a/openfpga/src/annotation/annotate_pb_types.h b/openfpga/src/annotation/annotate_pb_types.h
index 4be50aed6..d2c1b4cf5 100644
--- a/openfpga/src/annotation/annotate_pb_types.h
+++ b/openfpga/src/annotation/annotate_pb_types.h
@@ -6,7 +6,7 @@
  *******************************************************************/
 #include "vpr_context.h"
 #include "openfpga_context.h"
-#include "vpr_pb_type_annotation.h"
+#include "vpr_device_annotation.h"
 
 /********************************************************************
  * Function declaration
@@ -17,7 +17,7 @@ namespace openfpga {
 
 void annotate_pb_types(const DeviceContext& vpr_device_ctx, 
                        const Arch& openfpga_arch,
-                       VprPbTypeAnnotation& vpr_pb_type_annotation,
+                       VprDeviceAnnotation& vpr_device_annotation,
                        const bool& verbose_output);
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/annotation/check_pb_graph_annotation.cpp b/openfpga/src/annotation/check_pb_graph_annotation.cpp
index 92cabefb4..fdfa1394c 100644
--- a/openfpga/src/annotation/check_pb_graph_annotation.cpp
+++ b/openfpga/src/annotation/check_pb_graph_annotation.cpp
@@ -19,8 +19,8 @@ namespace openfpga {
  *******************************************************************/
 static 
 bool check_physical_pb_graph_pin(t_pb_graph_pin* pb_graph_pin,
-                                 const VprPbTypeAnnotation& vpr_pb_type_annotation) {
-  if (nullptr == vpr_pb_type_annotation.physical_pb_graph_pin(pb_graph_pin)) {
+                                 const VprDeviceAnnotation& vpr_device_annotation) {
+  if (nullptr == vpr_device_annotation.physical_pb_graph_pin(pb_graph_pin)) {
     VTR_LOG_ERROR("Found a pb_graph_pin '%s' missing physical pb_graph_pin binding!\n",
                   pb_graph_pin->port->name);
     return false;
@@ -40,7 +40,7 @@ bool check_physical_pb_graph_pin(t_pb_graph_pin* pb_graph_pin,
  *******************************************************************/
 static 
 void rec_check_vpr_physical_pb_graph_node_annotation(t_pb_graph_node* pb_graph_node, 
-                                                     const VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                                     const VprDeviceAnnotation& vpr_device_annotation,
                                                      size_t& num_err) {
   /* Go recursive first until we touch the primitive node */
   if (false == is_primitive_pb_type(pb_graph_node->pb_type)) {
@@ -49,7 +49,7 @@ void rec_check_vpr_physical_pb_graph_node_annotation(t_pb_graph_node* pb_graph_n
         /* Each child may exist multiple times in the hierarchy*/
         for (int jpb = 0; jpb < pb_graph_node->pb_type->modes[imode].pb_type_children[ipb].num_pb; ++jpb) {
           rec_check_vpr_physical_pb_graph_node_annotation(&(pb_graph_node->child_pb_graph_nodes[imode][ipb][jpb]), 
-                                                          vpr_pb_type_annotation, num_err);
+                                                          vpr_device_annotation, num_err);
         }
       }
     }
@@ -57,7 +57,7 @@ void rec_check_vpr_physical_pb_graph_node_annotation(t_pb_graph_node* pb_graph_n
   }
 
   /* Ensure that the pb_graph_node has been mapped to a physical node */
-  t_pb_graph_node* physical_pb_graph_node = vpr_pb_type_annotation.physical_pb_graph_node(pb_graph_node);
+  t_pb_graph_node* physical_pb_graph_node = vpr_device_annotation.physical_pb_graph_node(pb_graph_node);
   if (nullptr == physical_pb_graph_node) { 
     VTR_LOG_ERROR("Found a pb_graph_node '%s' missing physical pb_graph_node binding!\n",
                   physical_pb_graph_node->pb_type->name);
@@ -71,7 +71,7 @@ void rec_check_vpr_physical_pb_graph_node_annotation(t_pb_graph_node* pb_graph_n
   for (int iport = 0; iport < physical_pb_graph_node->num_input_ports; ++iport) {
     for (int ipin = 0; ipin < physical_pb_graph_node->num_input_pins[iport]; ++ipin) {
       if (false == check_physical_pb_graph_pin(&(physical_pb_graph_node->input_pins[iport][ipin]),
-                                               vpr_pb_type_annotation)) {
+                                               vpr_device_annotation)) {
         num_err++;
       }
     } 
@@ -80,7 +80,7 @@ void rec_check_vpr_physical_pb_graph_node_annotation(t_pb_graph_node* pb_graph_n
   for (int iport = 0; iport < physical_pb_graph_node->num_output_ports; ++iport) {
     for (int ipin = 0; ipin < physical_pb_graph_node->num_output_pins[iport]; ++ipin) {
       if (false == check_physical_pb_graph_pin(&(physical_pb_graph_node->output_pins[iport][ipin]),
-                                               vpr_pb_type_annotation)) {
+                                               vpr_device_annotation)) {
         num_err++;
       }
     } 
@@ -89,7 +89,7 @@ void rec_check_vpr_physical_pb_graph_node_annotation(t_pb_graph_node* pb_graph_n
   for (int iport = 0; iport < physical_pb_graph_node->num_clock_ports; ++iport) {
     for (int ipin = 0; ipin < physical_pb_graph_node->num_clock_pins[iport]; ++ipin) {
       if (false == check_physical_pb_graph_pin(&(physical_pb_graph_node->clock_pins[iport][ipin]),
-                                               vpr_pb_type_annotation)) {
+                                               vpr_device_annotation)) {
         num_err++;
       }
     } 
@@ -102,7 +102,7 @@ void rec_check_vpr_physical_pb_graph_node_annotation(t_pb_graph_node* pb_graph_n
  * - Each pin has been binded to a physical pb_graph_node pin
  *******************************************************************/
 void check_physical_pb_graph_node_annotation(const DeviceContext& vpr_device_ctx, 
-                                             const VprPbTypeAnnotation& vpr_pb_type_annotation) {
+                                             const VprDeviceAnnotation& vpr_device_annotation) {
   size_t num_err = 0;
  
   for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
@@ -110,7 +110,7 @@ void check_physical_pb_graph_node_annotation(const DeviceContext& vpr_device_ctx
     if (nullptr == lb_type.pb_graph_head) {
       continue;
     }
-    rec_check_vpr_physical_pb_graph_node_annotation(lb_type.pb_graph_head, vpr_pb_type_annotation, num_err); 
+    rec_check_vpr_physical_pb_graph_node_annotation(lb_type.pb_graph_head, vpr_device_annotation, num_err); 
   }
 
   if (0 == num_err) {
diff --git a/openfpga/src/annotation/check_pb_graph_annotation.h b/openfpga/src/annotation/check_pb_graph_annotation.h
index c482943c5..8416800c0 100644
--- a/openfpga/src/annotation/check_pb_graph_annotation.h
+++ b/openfpga/src/annotation/check_pb_graph_annotation.h
@@ -6,7 +6,7 @@
  *******************************************************************/
 #include "vpr_context.h"
 #include "openfpga_context.h"
-#include "vpr_pb_type_annotation.h"
+#include "vpr_device_annotation.h"
 
 /********************************************************************
  * Function declaration
@@ -16,7 +16,7 @@
 namespace openfpga {
 
 void check_physical_pb_graph_node_annotation(const DeviceContext& vpr_device_ctx, 
-                                             const VprPbTypeAnnotation& vpr_pb_type_annotation);
+                                             const VprDeviceAnnotation& vpr_device_annotation);
 
 } /* end namespace openfpga */
 
diff --git a/openfpga/src/annotation/check_pb_type_annotation.cpp b/openfpga/src/annotation/check_pb_type_annotation.cpp
index fdebba00c..5159ec064 100644
--- a/openfpga/src/annotation/check_pb_type_annotation.cpp
+++ b/openfpga/src/annotation/check_pb_type_annotation.cpp
@@ -22,7 +22,7 @@ namespace openfpga {
 static 
 void rec_check_vpr_physical_pb_mode_annotation(t_pb_type* cur_pb_type,
                                                const bool& expect_physical_mode,
-                                               const VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                               const VprDeviceAnnotation& vpr_device_annotation,
                                                size_t& num_err) {
   /* We do not check any primitive pb_type */
   if (true == is_primitive_pb_type(cur_pb_type)) {
@@ -36,7 +36,7 @@ void rec_check_vpr_physical_pb_mode_annotation(t_pb_type* cur_pb_type,
    *   nothing in the annotation
    */
   if (true == expect_physical_mode) {
-    if (nullptr == vpr_pb_type_annotation.physical_mode(cur_pb_type)) {
+    if (nullptr == vpr_device_annotation.physical_mode(cur_pb_type)) {
       VTR_LOG_ERROR("Unable to find a physical mode for a multi-mode pb_type '%s'!\n",
                     cur_pb_type->name);
       VTR_LOG_ERROR("Please specify in the OpenFPGA architecture\n");
@@ -45,9 +45,9 @@ void rec_check_vpr_physical_pb_mode_annotation(t_pb_type* cur_pb_type,
     }
   } else {
     VTR_ASSERT_SAFE(false == expect_physical_mode);
-    if (nullptr != vpr_pb_type_annotation.physical_mode(cur_pb_type)) {
+    if (nullptr != vpr_device_annotation.physical_mode(cur_pb_type)) {
       VTR_LOG_ERROR("Find a physical mode '%s' for pb_type '%s' which is not under any physical mode!\n",
-                    vpr_pb_type_annotation.physical_mode(cur_pb_type)->name,
+                    vpr_device_annotation.physical_mode(cur_pb_type)->name,
                     cur_pb_type->name);
       num_err++;
       return;
@@ -60,12 +60,12 @@ void rec_check_vpr_physical_pb_mode_annotation(t_pb_type* cur_pb_type,
    */
   for (int imode = 0; imode < cur_pb_type->num_modes; ++imode) {
     bool expect_child_physical_mode = false;
-    if (&(cur_pb_type->modes[imode]) == vpr_pb_type_annotation.physical_mode(cur_pb_type)) {
+    if (&(cur_pb_type->modes[imode]) == vpr_device_annotation.physical_mode(cur_pb_type)) {
       expect_child_physical_mode = true && expect_physical_mode; 
     }
     for (int ichild = 0; ichild < cur_pb_type->modes[imode].num_pb_type_children; ++ichild) { 
       rec_check_vpr_physical_pb_mode_annotation(&(cur_pb_type->modes[imode].pb_type_children[ichild]),
-                                                expect_child_physical_mode, vpr_pb_type_annotation,
+                                                expect_child_physical_mode, vpr_device_annotation,
                                                 num_err);
     }
   }
@@ -76,7 +76,7 @@ void rec_check_vpr_physical_pb_mode_annotation(t_pb_type* cur_pb_type,
  * each pb_type in the device
  *******************************************************************/
 void check_vpr_physical_pb_mode_annotation(const DeviceContext& vpr_device_ctx, 
-                                           const VprPbTypeAnnotation& vpr_pb_type_annotation) {
+                                           const VprDeviceAnnotation& vpr_device_annotation) {
   size_t num_err = 0;
 
   for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
@@ -85,7 +85,7 @@ void check_vpr_physical_pb_mode_annotation(const DeviceContext& vpr_device_ctx,
       continue;
     }
     /* Top pb_type should always has a physical mode! */
-    rec_check_vpr_physical_pb_mode_annotation(lb_type.pb_type, true, vpr_pb_type_annotation, num_err);
+    rec_check_vpr_physical_pb_mode_annotation(lb_type.pb_type, true, vpr_device_annotation, num_err);
   }
   if (0 == num_err) {
     VTR_LOG("Check physical mode annotation for pb_types passed.\n");
@@ -102,9 +102,9 @@ void check_vpr_physical_pb_mode_annotation(const DeviceContext& vpr_device_ctx,
  *******************************************************************/
 static 
 void check_vpr_physical_primitive_pb_type_annotation(t_pb_type* cur_pb_type,
-                                                     const VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                                     const VprDeviceAnnotation& vpr_device_annotation,
                                                      size_t& num_err) {
-  if (nullptr == vpr_pb_type_annotation.physical_pb_type(cur_pb_type)) {
+  if (nullptr == vpr_device_annotation.physical_pb_type(cur_pb_type)) {
     VTR_LOG_ERROR("Find a pb_type '%s' which has not been mapped to any physical pb_type!\n",
                   cur_pb_type->name);
     VTR_LOG_ERROR("Please specify in the OpenFPGA architecture\n");
@@ -114,7 +114,7 @@ void check_vpr_physical_primitive_pb_type_annotation(t_pb_type* cur_pb_type,
 
   /* Now we need to check each port of the pb_type */ 
   for (t_port* pb_port : pb_type_ports(cur_pb_type)) {
-    if (nullptr == vpr_pb_type_annotation.physical_pb_port(pb_port)) {
+    if (nullptr == vpr_device_annotation.physical_pb_port(pb_port)) {
       VTR_LOG_ERROR("Find a port '%s' of pb_type '%s' which has not been mapped to any physical port!\n",
                     pb_port->name, cur_pb_type->name);
       VTR_LOG_ERROR("Please specify in the OpenFPGA architecture\n");
@@ -132,11 +132,11 @@ void check_vpr_physical_primitive_pb_type_annotation(t_pb_type* cur_pb_type,
  *******************************************************************/
 static 
 void rec_check_vpr_physical_pb_type_annotation(t_pb_type* cur_pb_type,
-                                               const VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                               const VprDeviceAnnotation& vpr_device_annotation,
                                                size_t& num_err) {
   /* Primitive pb_type should always been binded to a physical pb_type */
   if (true == is_primitive_pb_type(cur_pb_type)) {
-    check_vpr_physical_primitive_pb_type_annotation(cur_pb_type, vpr_pb_type_annotation, num_err);
+    check_vpr_physical_primitive_pb_type_annotation(cur_pb_type, vpr_device_annotation, num_err);
     return;
   }
 
@@ -144,7 +144,7 @@ void rec_check_vpr_physical_pb_type_annotation(t_pb_type* cur_pb_type,
   for (int imode = 0; imode < cur_pb_type->num_modes; ++imode) {
     for (int ichild = 0; ichild < cur_pb_type->modes[imode].num_pb_type_children; ++ichild) { 
       rec_check_vpr_physical_pb_type_annotation(&(cur_pb_type->modes[imode].pb_type_children[ichild]),
-                                                vpr_pb_type_annotation,
+                                                vpr_device_annotation,
                                                 num_err);
     }
   }
@@ -157,7 +157,7 @@ void rec_check_vpr_physical_pb_type_annotation(t_pb_type* cur_pb_type,
  * and every port of the pb_type have been linked a port of a physical pb_type
  *******************************************************************/
 void check_vpr_physical_pb_type_annotation(const DeviceContext& vpr_device_ctx, 
-                                           const VprPbTypeAnnotation& vpr_pb_type_annotation) {
+                                           const VprDeviceAnnotation& vpr_device_annotation) {
   size_t num_err = 0;
 
   for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
@@ -166,7 +166,7 @@ void check_vpr_physical_pb_type_annotation(const DeviceContext& vpr_device_ctx,
       continue;
     }
     /* Top pb_type should always has a physical mode! */
-    rec_check_vpr_physical_pb_type_annotation(lb_type.pb_type, vpr_pb_type_annotation, num_err);
+    rec_check_vpr_physical_pb_type_annotation(lb_type.pb_type, vpr_device_annotation, num_err);
   }
   if (0 == num_err) {
     VTR_LOG("Check physical pb_type annotation for pb_types passed.\n");
@@ -187,12 +187,12 @@ void check_vpr_physical_pb_type_annotation(const DeviceContext& vpr_device_ctx,
 static 
 void rec_check_vpr_pb_type_circuit_model_annotation(t_pb_type* cur_pb_type,
                                                     const CircuitLibrary& circuit_lib,
-                                                    const VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                                    const VprDeviceAnnotation& vpr_device_annotation,
                                                     size_t& num_err) {
   /* Primitive pb_type should always been binded to a physical pb_type */
   if (true == is_primitive_pb_type(cur_pb_type)) {
     /* Every physical pb_type should be linked to a valid circuit model */
-    if (CircuitModelId::INVALID() == vpr_pb_type_annotation.pb_type_circuit_model(cur_pb_type)) {
+    if (CircuitModelId::INVALID() == vpr_device_annotation.pb_type_circuit_model(cur_pb_type)) {
       VTR_LOG_ERROR("Found a physical pb_type '%s' missing circuit model binding!\n",
                     cur_pb_type->name);
       num_err++;
@@ -200,7 +200,7 @@ void rec_check_vpr_pb_type_circuit_model_annotation(t_pb_type* cur_pb_type,
     }
     /* Every port of the pb_type have been linked to a valid port of a circuit model */
     for (t_port* port : pb_type_ports(cur_pb_type)) {
-      if (CircuitPortId::INVALID() == vpr_pb_type_annotation.pb_circuit_port(port)) {
+      if (CircuitPortId::INVALID() == vpr_device_annotation.pb_circuit_port(port)) {
         VTR_LOG_ERROR("Found a port '%s' of physical pb_type '%s' missing circuit port binding!\n",
                       port->name, cur_pb_type->name);
         num_err++;
@@ -210,9 +210,9 @@ void rec_check_vpr_pb_type_circuit_model_annotation(t_pb_type* cur_pb_type,
   }
 
   /* Every interconnect in the physical mode has been linked to a valid circuit model in a correct type */
-  t_mode* physical_mode = vpr_pb_type_annotation.physical_mode(cur_pb_type);
+  t_mode* physical_mode = vpr_device_annotation.physical_mode(cur_pb_type);
   for (t_interconnect* interc : pb_mode_interconnects(physical_mode)) {
-    CircuitModelId interc_circuit_model = vpr_pb_type_annotation.interconnect_circuit_model(interc);
+    CircuitModelId interc_circuit_model = vpr_device_annotation.interconnect_circuit_model(interc);
     if (CircuitModelId::INVALID() == interc_circuit_model) {
       VTR_LOG_ERROR("Found an interconnect '%s' under physical mode '%s' of pb_type '%s' missing circuit model binding!\n",
                     interc->name,
@@ -221,7 +221,7 @@ void rec_check_vpr_pb_type_circuit_model_annotation(t_pb_type* cur_pb_type,
       num_err++;
       continue;
     }
-    e_circuit_model_type required_circuit_model_type = pb_interconnect_require_circuit_model_type(vpr_pb_type_annotation.interconnect_physical_type(interc));
+    e_circuit_model_type required_circuit_model_type = pb_interconnect_require_circuit_model_type(vpr_device_annotation.interconnect_physical_type(interc));
     if (circuit_lib.model_type(interc_circuit_model) != required_circuit_model_type) {
       VTR_LOG_ERROR("Found an interconnect '%s' under physical mode '%s' of pb_type '%s' linked to a circuit model '%s' with a wrong type!\nExpect: '%s' Linked: '%s'\n",
                     interc->name,
@@ -238,7 +238,7 @@ void rec_check_vpr_pb_type_circuit_model_annotation(t_pb_type* cur_pb_type,
   for (int ichild = 0; ichild < physical_mode->num_pb_type_children; ++ichild) { 
     rec_check_vpr_pb_type_circuit_model_annotation(&(physical_mode->pb_type_children[ichild]),
                                                    circuit_lib,
-                                                   vpr_pb_type_annotation,
+                                                   vpr_device_annotation,
                                                    num_err);
   }
 }
@@ -253,7 +253,7 @@ void rec_check_vpr_pb_type_circuit_model_annotation(t_pb_type* cur_pb_type,
  *******************************************************************/
 void check_vpr_pb_type_circuit_model_annotation(const DeviceContext& vpr_device_ctx, 
                                                 const CircuitLibrary& circuit_lib,
-                                                const VprPbTypeAnnotation& vpr_pb_type_annotation) {
+                                                const VprDeviceAnnotation& vpr_device_annotation) {
   size_t num_err = 0;
 
   for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
@@ -262,7 +262,7 @@ void check_vpr_pb_type_circuit_model_annotation(const DeviceContext& vpr_device_
       continue;
     }
     /* Top pb_type should always has a physical mode! */
-    rec_check_vpr_pb_type_circuit_model_annotation(lb_type.pb_type, circuit_lib, vpr_pb_type_annotation, num_err);
+    rec_check_vpr_pb_type_circuit_model_annotation(lb_type.pb_type, circuit_lib, vpr_device_annotation, num_err);
   }
   if (0 == num_err) {
     VTR_LOG("Check physical pb_type annotation for circuit model passed.\n");
@@ -282,14 +282,14 @@ void check_vpr_pb_type_circuit_model_annotation(const DeviceContext& vpr_device_
 static 
 void rec_check_vpr_pb_type_mode_bits_annotation(t_pb_type* cur_pb_type,
                                                 const CircuitLibrary& circuit_lib,
-                                                const VprPbTypeAnnotation& vpr_pb_type_annotation,
+                                                const VprDeviceAnnotation& vpr_device_annotation,
                                                 size_t& num_err) {
   /* Primitive pb_type should always been binded to a physical pb_type */
   if (true == is_primitive_pb_type(cur_pb_type)) {
     /* Find the physical pb_type
      * If the physical pb_type has mode selection bits, this pb_type must have as well!
      */
-    t_pb_type* physical_pb_type = vpr_pb_type_annotation.physical_pb_type(cur_pb_type);
+    t_pb_type* physical_pb_type = vpr_device_annotation.physical_pb_type(cur_pb_type);
 
     if (nullptr == physical_pb_type) {
       VTR_LOG_ERROR("Find a pb_type '%s' which has not been mapped to any physical pb_type!\n",
@@ -299,7 +299,7 @@ void rec_check_vpr_pb_type_mode_bits_annotation(t_pb_type* cur_pb_type,
       return;
     }
 
-    if (vpr_pb_type_annotation.pb_type_mode_bits(cur_pb_type).size() != vpr_pb_type_annotation.pb_type_mode_bits(physical_pb_type).size()) {
+    if (vpr_device_annotation.pb_type_mode_bits(cur_pb_type).size() != vpr_device_annotation.pb_type_mode_bits(physical_pb_type).size()) {
       VTR_LOG_ERROR("Found different sizes of mode_bits for pb_type '%s' and its physical pb_type '%s'\n",
                     cur_pb_type->name,
                     physical_pb_type->name);
@@ -308,15 +308,15 @@ void rec_check_vpr_pb_type_mode_bits_annotation(t_pb_type* cur_pb_type,
     }
   
     /* Try to find a mode selection port for the circuit model linked to the circuit model */
-    CircuitModelId circuit_model = vpr_pb_type_annotation.pb_type_circuit_model(physical_pb_type);
-    if (CircuitModelId::INVALID() == vpr_pb_type_annotation.pb_type_circuit_model(physical_pb_type)) {
+    CircuitModelId circuit_model = vpr_device_annotation.pb_type_circuit_model(physical_pb_type);
+    if (CircuitModelId::INVALID() == vpr_device_annotation.pb_type_circuit_model(physical_pb_type)) {
       VTR_LOG_ERROR("Found a physical pb_type '%s' missing circuit model binding!\n",
                     physical_pb_type->name);
       num_err++;
       return; /* Invalid id already, further check is not applicable */
     }
     
-    if (0 == vpr_pb_type_annotation.pb_type_mode_bits(cur_pb_type).size()) {
+    if (0 == vpr_device_annotation.pb_type_mode_bits(cur_pb_type).size()) {
       /* No mode bits to be checked! */
       return;
     }
@@ -326,7 +326,7 @@ void rec_check_vpr_pb_type_mode_bits_annotation(t_pb_type* cur_pb_type,
     for (const CircuitPortId& mode_select_port : mode_select_ports) {
       port_num_mode_bits += circuit_lib.port_size(mode_select_port);
     }
-    if (port_num_mode_bits != vpr_pb_type_annotation.pb_type_mode_bits(cur_pb_type).size()) {
+    if (port_num_mode_bits != vpr_device_annotation.pb_type_mode_bits(cur_pb_type).size()) {
       VTR_LOG_ERROR("Length of mode bits of pb_type '%s' does not match the size(%ld) of mode selection ports of circuit model '%s'!\n",
                     cur_pb_type->name,
                     port_num_mode_bits,
@@ -341,7 +341,7 @@ void rec_check_vpr_pb_type_mode_bits_annotation(t_pb_type* cur_pb_type,
   for (int imode = 0; imode < cur_pb_type->num_modes; ++imode) {
     for (int ichild = 0; ichild < cur_pb_type->modes[imode].num_pb_type_children; ++ichild) { 
       rec_check_vpr_pb_type_mode_bits_annotation(&(cur_pb_type->modes[imode].pb_type_children[ichild]),
-                                                 circuit_lib, vpr_pb_type_annotation,
+                                                 circuit_lib, vpr_device_annotation,
                                                  num_err);
     }
   }
@@ -359,7 +359,7 @@ void rec_check_vpr_pb_type_mode_bits_annotation(t_pb_type* cur_pb_type,
  *******************************************************************/
 void check_vpr_pb_type_mode_bits_annotation(const DeviceContext& vpr_device_ctx, 
                                             const CircuitLibrary& circuit_lib,
-                                            const VprPbTypeAnnotation& vpr_pb_type_annotation) {
+                                            const VprDeviceAnnotation& vpr_device_annotation) {
   size_t num_err = 0;
 
   for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
@@ -368,7 +368,7 @@ void check_vpr_pb_type_mode_bits_annotation(const DeviceContext& vpr_device_ctx,
       continue;
     }
     /* Top pb_type should always has a physical mode! */
-    rec_check_vpr_pb_type_mode_bits_annotation(lb_type.pb_type, circuit_lib, vpr_pb_type_annotation, num_err);
+    rec_check_vpr_pb_type_mode_bits_annotation(lb_type.pb_type, circuit_lib, vpr_device_annotation, num_err);
   }
   if (0 == num_err) {
     VTR_LOG("Check pb_type annotation for mode selection bits passed.\n");
diff --git a/openfpga/src/annotation/check_pb_type_annotation.h b/openfpga/src/annotation/check_pb_type_annotation.h
index d3d2799aa..5183c5e10 100644
--- a/openfpga/src/annotation/check_pb_type_annotation.h
+++ b/openfpga/src/annotation/check_pb_type_annotation.h
@@ -6,7 +6,7 @@
  *******************************************************************/
 #include "vpr_context.h"
 #include "openfpga_context.h"
-#include "vpr_pb_type_annotation.h"
+#include "vpr_device_annotation.h"
 
 /********************************************************************
  * Function declaration
@@ -16,18 +16,18 @@
 namespace openfpga {
 
 void check_vpr_physical_pb_mode_annotation(const DeviceContext& vpr_device_ctx, 
-                                           const VprPbTypeAnnotation& vpr_pb_type_annotation);
+                                           const VprDeviceAnnotation& vpr_device_annotation);
 
 void check_vpr_physical_pb_type_annotation(const DeviceContext& vpr_device_ctx, 
-                                           const VprPbTypeAnnotation& vpr_pb_type_annotation);
+                                           const VprDeviceAnnotation& vpr_device_annotation);
 
 void check_vpr_pb_type_circuit_model_annotation(const DeviceContext& vpr_device_ctx, 
                                                 const CircuitLibrary& circuit_lib,
-                                                const VprPbTypeAnnotation& vpr_pb_type_annotation);
+                                                const VprDeviceAnnotation& vpr_device_annotation);
 
 void check_vpr_pb_type_mode_bits_annotation(const DeviceContext& vpr_device_ctx, 
                                             const CircuitLibrary& circuit_lib,
-                                            const VprPbTypeAnnotation& vpr_pb_type_annotation);
+                                            const VprDeviceAnnotation& vpr_device_annotation);
 
 } /* end namespace openfpga */
 
diff --git a/openfpga/src/annotation/vpr_pb_type_annotation.cpp b/openfpga/src/annotation/vpr_device_annotation.cpp
similarity index 87%
rename from openfpga/src/annotation/vpr_pb_type_annotation.cpp
rename to openfpga/src/annotation/vpr_device_annotation.cpp
index f75a91059..8ae8079d5 100644
--- a/openfpga/src/annotation/vpr_pb_type_annotation.cpp
+++ b/openfpga/src/annotation/vpr_device_annotation.cpp
@@ -1,11 +1,11 @@
 /************************************************************************
- * Member functions for class VprPbTypeAnnotation
+ * Member functions for class VprDeviceAnnotation
  ***********************************************************************/
 #include <algorithm>
 
 #include "vtr_log.h"
 #include "vtr_assert.h"
-#include "vpr_pb_type_annotation.h"
+#include "vpr_device_annotation.h"
 
 /* namespace openfpga begins */
 namespace openfpga {
@@ -13,14 +13,14 @@ namespace openfpga {
 /************************************************************************
  * Constructors
  ***********************************************************************/
-VprPbTypeAnnotation::VprPbTypeAnnotation() {
+VprDeviceAnnotation::VprDeviceAnnotation() {
   return;
 }
 
 /************************************************************************
  * Public accessors
  ***********************************************************************/
-bool VprPbTypeAnnotation::is_physical_pb_type(t_pb_type* pb_type) const {
+bool VprDeviceAnnotation::is_physical_pb_type(t_pb_type* pb_type) const {
   /* Ensure that the pb_type is in the list */
   std::map<t_pb_type*, t_pb_type*>::const_iterator it = physical_pb_types_.find(pb_type);
   if (it == physical_pb_types_.end()) {
@@ -30,7 +30,7 @@ bool VprPbTypeAnnotation::is_physical_pb_type(t_pb_type* pb_type) const {
   return pb_type == physical_pb_types_.at(pb_type);
 }
 
-t_mode* VprPbTypeAnnotation::physical_mode(t_pb_type* pb_type) const {
+t_mode* VprDeviceAnnotation::physical_mode(t_pb_type* pb_type) const {
   /* Ensure that the pb_type is in the list */
   std::map<t_pb_type*, t_mode*>::const_iterator it = physical_pb_modes_.find(pb_type);
   if (it == physical_pb_modes_.end()) {
@@ -39,7 +39,7 @@ t_mode* VprPbTypeAnnotation::physical_mode(t_pb_type* pb_type) const {
   return physical_pb_modes_.at(pb_type);
 }
 
-t_pb_type* VprPbTypeAnnotation::physical_pb_type(t_pb_type* pb_type) const {
+t_pb_type* VprDeviceAnnotation::physical_pb_type(t_pb_type* pb_type) const {
   /* Ensure that the pb_type is in the list */
   std::map<t_pb_type*, t_pb_type*>::const_iterator it = physical_pb_types_.find(pb_type);
   if (it == physical_pb_types_.end()) {
@@ -48,7 +48,7 @@ t_pb_type* VprPbTypeAnnotation::physical_pb_type(t_pb_type* pb_type) const {
   return physical_pb_types_.at(pb_type);
 }
 
-t_port* VprPbTypeAnnotation::physical_pb_port(t_port* pb_port) const {
+t_port* VprDeviceAnnotation::physical_pb_port(t_port* pb_port) const {
   /* Ensure that the pb_type is in the list */
   std::map<t_port*, t_port*>::const_iterator it = physical_pb_ports_.find(pb_port);
   if (it == physical_pb_ports_.end()) {
@@ -57,7 +57,7 @@ t_port* VprPbTypeAnnotation::physical_pb_port(t_port* pb_port) const {
   return physical_pb_ports_.at(pb_port);
 }
 
-BasicPort VprPbTypeAnnotation::physical_pb_port_range(t_port* pb_port) const {
+BasicPort VprDeviceAnnotation::physical_pb_port_range(t_port* pb_port) const {
   /* Ensure that the pb_type is in the list */
   std::map<t_port*, BasicPort>::const_iterator it = physical_pb_port_ranges_.find(pb_port);
   if (it == physical_pb_port_ranges_.end()) {
@@ -67,7 +67,7 @@ BasicPort VprPbTypeAnnotation::physical_pb_port_range(t_port* pb_port) const {
   return physical_pb_port_ranges_.at(pb_port);
 }
 
-CircuitModelId VprPbTypeAnnotation::pb_type_circuit_model(t_pb_type* physical_pb_type) const {
+CircuitModelId VprDeviceAnnotation::pb_type_circuit_model(t_pb_type* physical_pb_type) const {
   /* Ensure that the pb_type is in the list */
   std::map<t_pb_type*, CircuitModelId>::const_iterator it = pb_type_circuit_models_.find(physical_pb_type);
   if (it == pb_type_circuit_models_.end()) {
@@ -77,7 +77,7 @@ CircuitModelId VprPbTypeAnnotation::pb_type_circuit_model(t_pb_type* physical_pb
   return pb_type_circuit_models_.at(physical_pb_type);
 }
 
-CircuitModelId VprPbTypeAnnotation::interconnect_circuit_model(t_interconnect* pb_interconnect) const {
+CircuitModelId VprDeviceAnnotation::interconnect_circuit_model(t_interconnect* pb_interconnect) const {
   /* Ensure that the pb_type is in the list */
   std::map<t_interconnect*, CircuitModelId>::const_iterator it = interconnect_circuit_models_.find(pb_interconnect);
   if (it == interconnect_circuit_models_.end()) {
@@ -87,7 +87,7 @@ CircuitModelId VprPbTypeAnnotation::interconnect_circuit_model(t_interconnect* p
   return interconnect_circuit_models_.at(pb_interconnect);
 }
 
-e_interconnect VprPbTypeAnnotation::interconnect_physical_type(t_interconnect* pb_interconnect) const {
+e_interconnect VprDeviceAnnotation::interconnect_physical_type(t_interconnect* pb_interconnect) const {
   /* Ensure that the pb_type is in the list */
   std::map<t_interconnect*, e_interconnect>::const_iterator it = interconnect_physical_types_.find(pb_interconnect);
   if (it == interconnect_physical_types_.end()) {
@@ -97,7 +97,7 @@ e_interconnect VprPbTypeAnnotation::interconnect_physical_type(t_interconnect* p
   return interconnect_physical_types_.at(pb_interconnect);
 }
 
-CircuitPortId VprPbTypeAnnotation::pb_circuit_port(t_port* pb_port) const {
+CircuitPortId VprDeviceAnnotation::pb_circuit_port(t_port* pb_port) const {
   /* Ensure that the pb_type is in the list */
   std::map<t_port*, CircuitPortId>::const_iterator it = pb_circuit_ports_.find(pb_port);
   if (it == pb_circuit_ports_.end()) {
@@ -107,7 +107,7 @@ CircuitPortId VprPbTypeAnnotation::pb_circuit_port(t_port* pb_port) const {
   return pb_circuit_ports_.at(pb_port);
 }
 
-std::vector<size_t> VprPbTypeAnnotation::pb_type_mode_bits(t_pb_type* pb_type) const {
+std::vector<size_t> VprDeviceAnnotation::pb_type_mode_bits(t_pb_type* pb_type) const {
   /* Ensure that the pb_type is in the list */
   std::map<t_pb_type*, std::vector<size_t>>::const_iterator it = pb_type_mode_bits_.find(pb_type);
   if (it == pb_type_mode_bits_.end()) {
@@ -117,7 +117,7 @@ std::vector<size_t> VprPbTypeAnnotation::pb_type_mode_bits(t_pb_type* pb_type) c
   return pb_type_mode_bits_.at(pb_type);
 }
 
-PbGraphNodeId VprPbTypeAnnotation::pb_graph_node_unique_index(t_pb_graph_node* pb_graph_node) const {
+PbGraphNodeId VprDeviceAnnotation::pb_graph_node_unique_index(t_pb_graph_node* pb_graph_node) const {
   /* Ensure that the pb_type is in the list */
   std::map<t_pb_type*, std::vector<t_pb_graph_node*>>::const_iterator it = pb_graph_node_unique_index_.find(pb_graph_node->pb_type);
   if (it == pb_graph_node_unique_index_.end()) {
@@ -138,7 +138,7 @@ PbGraphNodeId VprPbTypeAnnotation::pb_graph_node_unique_index(t_pb_graph_node* p
   return PbGraphNodeId(it_node - pb_graph_node_unique_index_.at(pb_graph_node->pb_type).begin());
 }
 
-t_pb_graph_node* VprPbTypeAnnotation::pb_graph_node(t_pb_type* pb_type, const PbGraphNodeId& unique_index) const {
+t_pb_graph_node* VprDeviceAnnotation::pb_graph_node(t_pb_type* pb_type, const PbGraphNodeId& unique_index) const {
   /* Ensure that the pb_type is in the list */
   std::map<t_pb_type*, std::vector<t_pb_graph_node*>>::const_iterator it = pb_graph_node_unique_index_.find(pb_type);
   if (it == pb_graph_node_unique_index_.end()) {
@@ -156,7 +156,7 @@ t_pb_graph_node* VprPbTypeAnnotation::pb_graph_node(t_pb_type* pb_type, const Pb
   return pb_graph_node_unique_index_.at(pb_type)[size_t(unique_index)];
 }
 
-t_pb_graph_node* VprPbTypeAnnotation::physical_pb_graph_node(t_pb_graph_node* pb_graph_node) const {
+t_pb_graph_node* VprDeviceAnnotation::physical_pb_graph_node(t_pb_graph_node* pb_graph_node) const {
   /* Ensure that the pb_graph_node is in the list */
   std::map<t_pb_graph_node*, t_pb_graph_node*>::const_iterator it = physical_pb_graph_nodes_.find(pb_graph_node);
   if (it == physical_pb_graph_nodes_.end()) {
@@ -165,7 +165,7 @@ t_pb_graph_node* VprPbTypeAnnotation::physical_pb_graph_node(t_pb_graph_node* pb
   return physical_pb_graph_nodes_.at(pb_graph_node);
 }
 
-int VprPbTypeAnnotation::physical_pb_type_index_factor(t_pb_type* pb_type) const {
+int VprDeviceAnnotation::physical_pb_type_index_factor(t_pb_type* pb_type) const {
   /* Ensure that the pb_type is in the list */
   std::map<t_pb_type*, int>::const_iterator it = physical_pb_type_index_factors_.find(pb_type);
   if (it == physical_pb_type_index_factors_.end()) {
@@ -175,7 +175,7 @@ int VprPbTypeAnnotation::physical_pb_type_index_factor(t_pb_type* pb_type) const
   return physical_pb_type_index_factors_.at(pb_type);
 }
 
-int VprPbTypeAnnotation::physical_pb_type_index_offset(t_pb_type* pb_type) const {
+int VprDeviceAnnotation::physical_pb_type_index_offset(t_pb_type* pb_type) const {
   /* Ensure that the pb_type is in the list */
   std::map<t_pb_type*, int>::const_iterator it = physical_pb_type_index_offsets_.find(pb_type);
   if (it == physical_pb_type_index_offsets_.end()) {
@@ -185,7 +185,7 @@ int VprPbTypeAnnotation::physical_pb_type_index_offset(t_pb_type* pb_type) const
   return physical_pb_type_index_offsets_.at(pb_type);
 }
 
-int VprPbTypeAnnotation::physical_pb_pin_rotate_offset(t_port* pb_port) const {
+int VprDeviceAnnotation::physical_pb_pin_rotate_offset(t_port* pb_port) const {
   /* Ensure that the pb_type is in the list */
   std::map<t_port*, int>::const_iterator it = physical_pb_pin_rotate_offsets_.find(pb_port);
   if (it == physical_pb_pin_rotate_offsets_.end()) {
@@ -195,7 +195,7 @@ int VprPbTypeAnnotation::physical_pb_pin_rotate_offset(t_port* pb_port) const {
   return physical_pb_pin_rotate_offsets_.at(pb_port);
 }
 
-int VprPbTypeAnnotation::physical_pb_pin_offset(t_port* pb_port) const {
+int VprDeviceAnnotation::physical_pb_pin_offset(t_port* pb_port) const {
   /* Ensure that the pb_type is in the list */
   std::map<t_port*, int>::const_iterator it = physical_pb_pin_offsets_.find(pb_port);
   if (it == physical_pb_pin_offsets_.end()) {
@@ -206,7 +206,7 @@ int VprPbTypeAnnotation::physical_pb_pin_offset(t_port* pb_port) const {
 }
 
 
-t_pb_graph_pin* VprPbTypeAnnotation::physical_pb_graph_pin(t_pb_graph_pin* pb_graph_pin) const {
+t_pb_graph_pin* VprDeviceAnnotation::physical_pb_graph_pin(t_pb_graph_pin* pb_graph_pin) const {
   /* Ensure that the pb_type is in the list */
   std::map<t_pb_graph_pin*, t_pb_graph_pin*>::const_iterator it = physical_pb_graph_pins_.find(pb_graph_pin);
   if (it == physical_pb_graph_pins_.end()) {
@@ -218,7 +218,7 @@ t_pb_graph_pin* VprPbTypeAnnotation::physical_pb_graph_pin(t_pb_graph_pin* pb_gr
 /************************************************************************
  * Public mutators
  ***********************************************************************/
-void VprPbTypeAnnotation::add_pb_type_physical_mode(t_pb_type* pb_type, t_mode* physical_mode) {
+void VprDeviceAnnotation::add_pb_type_physical_mode(t_pb_type* pb_type, t_mode* physical_mode) {
   /* Warn any override attempt */
   std::map<t_pb_type*, t_mode*>::const_iterator it = physical_pb_modes_.find(pb_type);
   if (it != physical_pb_modes_.end()) {
@@ -229,7 +229,7 @@ void VprPbTypeAnnotation::add_pb_type_physical_mode(t_pb_type* pb_type, t_mode*
   physical_pb_modes_[pb_type] = physical_mode;
 }
 
-void VprPbTypeAnnotation::add_physical_pb_type(t_pb_type* operating_pb_type, t_pb_type* physical_pb_type) {
+void VprDeviceAnnotation::add_physical_pb_type(t_pb_type* operating_pb_type, t_pb_type* physical_pb_type) {
   /* Warn any override attempt */
   std::map<t_pb_type*, t_pb_type*>::const_iterator it = physical_pb_types_.find(operating_pb_type);
   if (it != physical_pb_types_.end()) {
@@ -240,7 +240,7 @@ void VprPbTypeAnnotation::add_physical_pb_type(t_pb_type* operating_pb_type, t_p
   physical_pb_types_[operating_pb_type] = physical_pb_type;
 }
 
-void VprPbTypeAnnotation::add_physical_pb_port(t_port* operating_pb_port, t_port* physical_pb_port) {
+void VprDeviceAnnotation::add_physical_pb_port(t_port* operating_pb_port, t_port* physical_pb_port) {
   /* Warn any override attempt */
   std::map<t_port*, t_port*>::const_iterator it = physical_pb_ports_.find(operating_pb_port);
   if (it != physical_pb_ports_.end()) {
@@ -251,7 +251,7 @@ void VprPbTypeAnnotation::add_physical_pb_port(t_port* operating_pb_port, t_port
   physical_pb_ports_[operating_pb_port] = physical_pb_port;
 }
 
-void VprPbTypeAnnotation::add_physical_pb_port_range(t_port* operating_pb_port, const BasicPort& port_range) {
+void VprDeviceAnnotation::add_physical_pb_port_range(t_port* operating_pb_port, const BasicPort& port_range) {
   /* The port range must satify the port width*/
   VTR_ASSERT((size_t)operating_pb_port->num_pins == port_range.get_width());
 
@@ -265,7 +265,7 @@ void VprPbTypeAnnotation::add_physical_pb_port_range(t_port* operating_pb_port,
   physical_pb_port_ranges_[operating_pb_port] = port_range;
 }
 
-void VprPbTypeAnnotation::add_pb_type_circuit_model(t_pb_type* physical_pb_type, const CircuitModelId& circuit_model) {
+void VprDeviceAnnotation::add_pb_type_circuit_model(t_pb_type* physical_pb_type, const CircuitModelId& circuit_model) {
   /* Warn any override attempt */
   std::map<t_pb_type*, CircuitModelId>::const_iterator it = pb_type_circuit_models_.find(physical_pb_type);
   if (it != pb_type_circuit_models_.end()) {
@@ -276,7 +276,7 @@ void VprPbTypeAnnotation::add_pb_type_circuit_model(t_pb_type* physical_pb_type,
   pb_type_circuit_models_[physical_pb_type] = circuit_model;
 }
 
-void VprPbTypeAnnotation::add_interconnect_circuit_model(t_interconnect* pb_interconnect, const CircuitModelId& circuit_model) {
+void VprDeviceAnnotation::add_interconnect_circuit_model(t_interconnect* pb_interconnect, const CircuitModelId& circuit_model) {
   /* Warn any override attempt */
   std::map<t_interconnect*, CircuitModelId>::const_iterator it = interconnect_circuit_models_.find(pb_interconnect);
   if (it != interconnect_circuit_models_.end()) {
@@ -287,7 +287,7 @@ void VprPbTypeAnnotation::add_interconnect_circuit_model(t_interconnect* pb_inte
   interconnect_circuit_models_[pb_interconnect] = circuit_model;
 }
 
-void VprPbTypeAnnotation::add_interconnect_physical_type(t_interconnect* pb_interconnect,
+void VprDeviceAnnotation::add_interconnect_physical_type(t_interconnect* pb_interconnect,
                                                          const e_interconnect& physical_type) {
   /* Warn any override attempt */
   std::map<t_interconnect*, e_interconnect>::const_iterator it = interconnect_physical_types_.find(pb_interconnect);
@@ -299,7 +299,7 @@ void VprPbTypeAnnotation::add_interconnect_physical_type(t_interconnect* pb_inte
   interconnect_physical_types_[pb_interconnect] = physical_type;
 }
 
-void VprPbTypeAnnotation::add_pb_circuit_port(t_port* pb_port, const CircuitPortId& circuit_port) {
+void VprDeviceAnnotation::add_pb_circuit_port(t_port* pb_port, const CircuitPortId& circuit_port) {
   /* Warn any override attempt */
   std::map<t_port*, CircuitPortId>::const_iterator it = pb_circuit_ports_.find(pb_port);
   if (it != pb_circuit_ports_.end()) {
@@ -310,7 +310,7 @@ void VprPbTypeAnnotation::add_pb_circuit_port(t_port* pb_port, const CircuitPort
   pb_circuit_ports_[pb_port] = circuit_port;
 }
 
-void VprPbTypeAnnotation::add_pb_type_mode_bits(t_pb_type* pb_type, const std::vector<size_t>& mode_bits) {
+void VprDeviceAnnotation::add_pb_type_mode_bits(t_pb_type* pb_type, const std::vector<size_t>& mode_bits) {
   /* Warn any override attempt */
   std::map<t_pb_type*, std::vector<size_t>>::const_iterator it = pb_type_mode_bits_.find(pb_type);
   if (it != pb_type_mode_bits_.end()) {
@@ -321,11 +321,11 @@ void VprPbTypeAnnotation::add_pb_type_mode_bits(t_pb_type* pb_type, const std::v
   pb_type_mode_bits_[pb_type] = mode_bits;
 }
 
-void VprPbTypeAnnotation::add_pb_graph_node_unique_index(t_pb_graph_node* pb_graph_node) {
+void VprDeviceAnnotation::add_pb_graph_node_unique_index(t_pb_graph_node* pb_graph_node) {
   pb_graph_node_unique_index_[pb_graph_node->pb_type].push_back(pb_graph_node);
 }
 
-void VprPbTypeAnnotation::add_physical_pb_graph_node(t_pb_graph_node* operating_pb_graph_node, 
+void VprDeviceAnnotation::add_physical_pb_graph_node(t_pb_graph_node* operating_pb_graph_node, 
                                                      t_pb_graph_node* physical_pb_graph_node) {
   /* Warn any override attempt */
   std::map<t_pb_graph_node*, t_pb_graph_node*>::const_iterator it = physical_pb_graph_nodes_.find(operating_pb_graph_node);
@@ -340,7 +340,7 @@ void VprPbTypeAnnotation::add_physical_pb_graph_node(t_pb_graph_node* operating_
   physical_pb_graph_nodes_[operating_pb_graph_node] = physical_pb_graph_node;
 }
 
-void VprPbTypeAnnotation::add_physical_pb_type_index_factor(t_pb_type* pb_type, const int& factor) {
+void VprDeviceAnnotation::add_physical_pb_type_index_factor(t_pb_type* pb_type, const int& factor) {
   /* Warn any override attempt */
   std::map<t_pb_type*, int>::const_iterator it = physical_pb_type_index_factors_.find(pb_type);
   if (it != physical_pb_type_index_factors_.end()) {
@@ -351,7 +351,7 @@ void VprPbTypeAnnotation::add_physical_pb_type_index_factor(t_pb_type* pb_type,
   physical_pb_type_index_factors_[pb_type] = factor;
 }
 
-void VprPbTypeAnnotation::add_physical_pb_type_index_offset(t_pb_type* pb_type, const int& offset) {
+void VprDeviceAnnotation::add_physical_pb_type_index_offset(t_pb_type* pb_type, const int& offset) {
   /* Warn any override attempt */
   std::map<t_pb_type*, int>::const_iterator it = physical_pb_type_index_offsets_.find(pb_type);
   if (it != physical_pb_type_index_offsets_.end()) {
@@ -362,7 +362,7 @@ void VprPbTypeAnnotation::add_physical_pb_type_index_offset(t_pb_type* pb_type,
   physical_pb_type_index_offsets_[pb_type] = offset;
 }
 
-void VprPbTypeAnnotation::add_physical_pb_pin_rotate_offset(t_port* pb_port, const int& offset) {
+void VprDeviceAnnotation::add_physical_pb_pin_rotate_offset(t_port* pb_port, const int& offset) {
   /* Warn any override attempt */
   std::map<t_port*, int>::const_iterator it = physical_pb_pin_rotate_offsets_.find(pb_port);
   if (it != physical_pb_pin_rotate_offsets_.end()) {
@@ -375,7 +375,7 @@ void VprPbTypeAnnotation::add_physical_pb_pin_rotate_offset(t_port* pb_port, con
   physical_pb_pin_offsets_[pb_port] = 0;
 }
 
-void VprPbTypeAnnotation::add_physical_pb_graph_pin(t_pb_graph_pin* operating_pb_graph_pin, 
+void VprDeviceAnnotation::add_physical_pb_graph_pin(t_pb_graph_pin* operating_pb_graph_pin, 
                                                     t_pb_graph_pin* physical_pb_graph_pin) {
   /* Warn any override attempt */
   std::map<t_pb_graph_pin*, t_pb_graph_pin*>::const_iterator it = physical_pb_graph_pins_.find(operating_pb_graph_pin);
diff --git a/openfpga/src/annotation/vpr_pb_type_annotation.h b/openfpga/src/annotation/vpr_device_annotation.h
similarity index 98%
rename from openfpga/src/annotation/vpr_pb_type_annotation.h
rename to openfpga/src/annotation/vpr_device_annotation.h
index add45e42d..0cd9ac63f 100644
--- a/openfpga/src/annotation/vpr_pb_type_annotation.h
+++ b/openfpga/src/annotation/vpr_device_annotation.h
@@ -1,5 +1,5 @@
-#ifndef VPR_PB_TYPE_ANNOTATION_H
-#define VPR_PB_TYPE_ANNOTATION_H
+#ifndef VPR_DEVICE_ANNOTATION_H
+#define VPR_DEVICE_ANNOTATION_H
 
 /********************************************************************
  * Include header files required by the data structure definition
@@ -33,9 +33,9 @@ typedef vtr::StrongId<pb_graph_node_id_tag> PbGraphNodeId;
  * 3. what is the physical pb_type for an operating pb_type
  * 4. what is the mode pointer that represents the physical mode for a pb_type
  *******************************************************************/
-class VprPbTypeAnnotation {
+class VprDeviceAnnotation {
   public:  /* Constructor */
-    VprPbTypeAnnotation();
+    VprDeviceAnnotation();
   public:  /* Public accessors */
     bool is_physical_pb_type(t_pb_type* pb_type) const;
     t_mode* physical_mode(t_pb_type* pb_type) const;
diff --git a/openfpga/src/base/openfpga_context.h b/openfpga/src/base/openfpga_context.h
index 743847114..aed6b8014 100644
--- a/openfpga/src/base/openfpga_context.h
+++ b/openfpga/src/base/openfpga_context.h
@@ -4,7 +4,7 @@
 #include "vpr_context.h"
 #include "openfpga_arch.h"
 #include "vpr_netlist_annotation.h"
-#include "vpr_pb_type_annotation.h"
+#include "vpr_device_annotation.h"
 #include "vpr_clustering_annotation.h"
 #include "vpr_routing_annotation.h"
 #include "device_rr_gsb.h"
@@ -39,14 +39,14 @@
 class OpenfpgaContext : public Context  {
   public:  /* Public accessors */
     const openfpga::Arch& arch() const { return arch_; }
-    const openfpga::VprPbTypeAnnotation& vpr_pb_type_annotation() const { return vpr_pb_type_annotation_; }
+    const openfpga::VprDeviceAnnotation& vpr_device_annotation() const { return vpr_device_annotation_; }
     const openfpga::VprNetlistAnnotation& vpr_netlist_annotation() const { return vpr_netlist_annotation_; }
     const openfpga::VprClusteringAnnotation& vpr_clustering_annotation() const { return vpr_clustering_annotation_; }
     const openfpga::VprRoutingAnnotation& vpr_routing_annotation() const { return vpr_routing_annotation_; }
     const openfpga::DeviceRRGSB& device_rr_gsb() const { return device_rr_gsb_; }
   public:  /* Public mutators */
     openfpga::Arch& mutable_arch() { return arch_; }
-    openfpga::VprPbTypeAnnotation& mutable_vpr_pb_type_annotation() { return vpr_pb_type_annotation_; }
+    openfpga::VprDeviceAnnotation& mutable_vpr_device_annotation() { return vpr_device_annotation_; }
     openfpga::VprNetlistAnnotation& mutable_vpr_netlist_annotation() { return vpr_netlist_annotation_; }
     openfpga::VprClusteringAnnotation& mutable_vpr_clustering_annotation() { return vpr_clustering_annotation_; }
     openfpga::VprRoutingAnnotation& mutable_vpr_routing_annotation() { return vpr_routing_annotation_; }
@@ -56,7 +56,7 @@ class OpenfpgaContext : public Context  {
     openfpga::Arch arch_;
 
     /* Annotation to pb_type of VPR */
-    openfpga::VprPbTypeAnnotation vpr_pb_type_annotation_;
+    openfpga::VprDeviceAnnotation vpr_device_annotation_;
 
     /* Naming fix to netlist */
     openfpga::VprNetlistAnnotation vpr_netlist_annotation_;
diff --git a/openfpga/src/base/openfpga_link_arch.cpp b/openfpga/src/base/openfpga_link_arch.cpp
index 2519be57a..88f46571a 100644
--- a/openfpga/src/base/openfpga_link_arch.cpp
+++ b/openfpga/src/base/openfpga_link_arch.cpp
@@ -7,7 +7,7 @@
 #include "vtr_assert.h"
 #include "vtr_log.h"
 
-#include "vpr_pb_type_annotation.h"
+#include "vpr_device_annotation.h"
 #include "pb_type_utils.h"
 #include "annotate_pb_types.h"
 #include "annotate_pb_graph.h"
@@ -42,7 +42,7 @@ void link_arch(OpenfpgaContext& openfpga_context,
    * - circuit models for pb_type and pb interconnect
    */
   annotate_pb_types(g_vpr_ctx.device(), openfpga_context.arch(),
-                    openfpga_context.mutable_vpr_pb_type_annotation(),
+                    openfpga_context.mutable_vpr_device_annotation(),
                     cmd_context.option_enable(cmd, opt_verbose));
 
   /* Annotate pb_graph_nodes
@@ -51,7 +51,7 @@ void link_arch(OpenfpgaContext& openfpga_context,
    * - Bind pins from operating pb_graph_node to their physical pb_graph_node pins
    */
   annotate_pb_graph(g_vpr_ctx.device(),
-                    openfpga_context.mutable_vpr_pb_type_annotation(),
+                    openfpga_context.mutable_vpr_device_annotation(),
                     cmd_context.option_enable(cmd, opt_verbose));
 
   /* Annotate net mapping to each rr_node 

From feccbc5780e8202fc3edd965d9d9fbbe9a0f8924 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 12 Feb 2020 10:08:54 -0700
Subject: [PATCH 117/645] add more methods to link routing to circuit models in
 device annotation

---
 .../src/annotation/vpr_device_annotation.cpp  | 40 +++++++++++++++++++
 .../src/annotation/vpr_device_annotation.h    | 13 ++++++
 2 files changed, 53 insertions(+)

diff --git a/openfpga/src/annotation/vpr_device_annotation.cpp b/openfpga/src/annotation/vpr_device_annotation.cpp
index 8ae8079d5..280e4ca38 100644
--- a/openfpga/src/annotation/vpr_device_annotation.cpp
+++ b/openfpga/src/annotation/vpr_device_annotation.cpp
@@ -215,6 +215,24 @@ t_pb_graph_pin* VprDeviceAnnotation::physical_pb_graph_pin(t_pb_graph_pin* pb_gr
   return physical_pb_graph_pins_.at(pb_graph_pin);
 }
 
+CircuitModelId VprDeviceAnnotation::rr_switch_circuit_model(const RRSwitchId& rr_switch) const {
+  /* Ensure that the rr_switch is in the list */
+  std::map<RRSwitchId, CircuitModelId>::const_iterator it = rr_switch_circuit_models_.find(rr_switch);
+  if (it == rr_switch_circuit_models_.end()) {
+    return CircuitModelId::INVALID();
+  }
+  return rr_switch_circuit_models_.at(rr_switch);
+}
+
+CircuitModelId VprDeviceAnnotation::rr_segment_circuit_model(const RRSegmentId& rr_segment) const {
+  /* Ensure that the rr_switch is in the list */
+  std::map<RRSegmentId, CircuitModelId>::const_iterator it = rr_segment_circuit_models_.find(rr_segment);
+  if (it == rr_segment_circuit_models_.end()) {
+    return CircuitModelId::INVALID();
+  }
+  return rr_segment_circuit_models_.at(rr_segment);
+}
+
 /************************************************************************
  * Public mutators
  ***********************************************************************/
@@ -412,4 +430,26 @@ void VprDeviceAnnotation::add_physical_pb_graph_pin(t_pb_graph_pin* operating_pb
   }
 }
 
+void VprDeviceAnnotation::add_rr_switch_circuit_model(const RRSwitchId& rr_switch, const CircuitModelId& circuit_model) {
+  /* Warn any override attempt */
+  std::map<RRSwitchId, CircuitModelId>::const_iterator it = rr_switch_circuit_models_.find(rr_switch);
+  if (it != rr_switch_circuit_models_.end()) {
+    VTR_LOG_WARN("Override the annotation between rr_switch '%ld' and its circuit_model '%ld'!\n",
+                 size_t(rr_switch), size_t(circuit_model));
+  }
+
+  rr_switch_circuit_models_[rr_switch] = circuit_model;
+}
+
+void VprDeviceAnnotation::add_rr_segment_circuit_model(const RRSegmentId& rr_segment, const CircuitModelId& circuit_model) {
+  /* Warn any override attempt */
+  std::map<RRSegmentId, CircuitModelId>::const_iterator it = rr_segment_circuit_models_.find(rr_segment);
+  if (it != rr_segment_circuit_models_.end()) {
+    VTR_LOG_WARN("Override the annotation between rr_segment '%ld' and its circuit_model '%ld'!\n",
+                 size_t(rr_segment), size_t(circuit_model));
+  }
+
+  rr_segment_circuit_models_[rr_segment] = circuit_model;
+}
+
 } /* End namespace openfpga*/
diff --git a/openfpga/src/annotation/vpr_device_annotation.h b/openfpga/src/annotation/vpr_device_annotation.h
index 0cd9ac63f..211676264 100644
--- a/openfpga/src/annotation/vpr_device_annotation.h
+++ b/openfpga/src/annotation/vpr_device_annotation.h
@@ -12,6 +12,9 @@
 /* Header from archfpga library */
 #include "physical_types.h"
 
+/* Header from vpr library */
+#include "rr_graph_obj.h"
+
 /* Header from openfpgautil library */
 #include "openfpga_port.h"
 #include "circuit_library.h"
@@ -66,6 +69,8 @@ class VprDeviceAnnotation {
      */
     int physical_pb_pin_offset(t_port* pb_port) const;
     t_pb_graph_pin* physical_pb_graph_pin(t_pb_graph_pin* pb_graph_pin) const;
+    CircuitModelId rr_switch_circuit_model(const RRSwitchId& rr_switch) const;
+    CircuitModelId rr_segment_circuit_model(const RRSegmentId& rr_segment) const;
   public:  /* Public mutators */
     void add_pb_type_physical_mode(t_pb_type* pb_type, t_mode* physical_mode);
     void add_physical_pb_type(t_pb_type* operating_pb_type, t_pb_type* physical_pb_type);
@@ -83,6 +88,8 @@ class VprDeviceAnnotation {
     void add_physical_pb_type_index_offset(t_pb_type* pb_type, const int& offset);
     void add_physical_pb_pin_rotate_offset(t_port* pb_port, const int& offset);
     void add_physical_pb_graph_pin(t_pb_graph_pin* operating_pb_graph_pin, t_pb_graph_pin* physical_pb_graph_pin);
+    void add_rr_switch_circuit_model(const RRSwitchId& rr_switch, const CircuitModelId& circuit_model);
+    void add_rr_segment_circuit_model(const RRSegmentId& rr_segment, const CircuitModelId& circuit_model);
   private: /* Internal data */
     /* Pair a regular pb_type to its physical pb_type */
     std::map<t_pb_type*, t_pb_type*> physical_pb_types_;
@@ -157,6 +164,12 @@ class VprDeviceAnnotation {
 
     /* Pair a pb_graph_pin to a physical pb_graph_pin */
     std::map<t_pb_graph_pin*, t_pb_graph_pin*> physical_pb_graph_pins_;
+
+    /* Pair a Routing Resource Switch (rr_switch) to a circuit model */
+    std::map<RRSwitchId, CircuitModelId> rr_switch_circuit_models_;
+
+    /* Pair a Routing Segment (rr_segment) to a circuit model */
+    std::map<RRSegmentId, CircuitModelId> rr_segment_circuit_models_;
 };
 
 } /* End namespace openfpga*/

From a736e09c29a4d85e84451b28797308744494efce Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 12 Feb 2020 10:52:20 -0700
Subject: [PATCH 118/645] add rr_switch binding in link openfpga arch command

---
 ...otate_rr_gsb.cpp => annotate_rr_graph.cpp} | 75 ++++++++++++++++++-
 ...{annotate_rr_gsb.h => annotate_rr_graph.h} |  9 ++-
 openfpga/src/base/openfpga_link_arch.cpp      |  8 +-
 openfpga/src/base/openfpga_setup_command.cpp  |  1 -
 4 files changed, 88 insertions(+), 5 deletions(-)
 rename openfpga/src/annotation/{annotate_rr_gsb.cpp => annotate_rr_graph.cpp} (82%)
 rename openfpga/src/annotation/{annotate_rr_gsb.h => annotate_rr_graph.h} (67%)

diff --git a/openfpga/src/annotation/annotate_rr_gsb.cpp b/openfpga/src/annotation/annotate_rr_graph.cpp
similarity index 82%
rename from openfpga/src/annotation/annotate_rr_gsb.cpp
rename to openfpga/src/annotation/annotate_rr_graph.cpp
index dca399abd..efb7bd3a7 100644
--- a/openfpga/src/annotation/annotate_rr_gsb.cpp
+++ b/openfpga/src/annotation/annotate_rr_graph.cpp
@@ -13,11 +13,13 @@
 /* Headers from vpr library */
 #include "rr_graph_obj_util.h"
 
-#include "annotate_rr_gsb.h"
+#include "annotate_rr_graph.h"
 
 /* begin namespace openfpga */
 namespace openfpga {
 
+constexpr char* VPR_DELAYLESS_SWITCH_NAME = "__vpr_delayless_switch__";
+
 /* Build a RRChan Object with the given channel type and coorindators */
 static 
 RRChan build_one_rr_chan(const DeviceContext& vpr_device_ctx,
@@ -392,4 +394,75 @@ void annotate_device_rr_gsb(const DeviceContext& vpr_device_ctx,
           gsb_range.x() * gsb_range.y());
 }
 
+/********************************************************************
+ * Build the link between rr_graph switches to their physical circuit models 
+ * The binding is done based on the name of rr_switches defined in the
+ * OpenFPGA arch XML
+ *******************************************************************/
+static 
+void annotate_rr_switch_circuit_models(const DeviceContext& vpr_device_ctx, 
+                                       const Arch& openfpga_arch,
+                                       VprDeviceAnnotation& vpr_device_annotation,
+                                       const bool& verbose_output) {
+  size_t count = 0;
+
+  for (size_t iswitch = 0; iswitch < vpr_device_ctx.rr_switch_inf.size(); iswitch++) {
+    std::string switch_name(vpr_device_ctx.rr_switch_inf[iswitch].name); 
+    /* Skip the delayless switch, which is only used by the edges between
+     * - SOURCE and OPIN
+     * - IPIN and SINK  
+     */
+    if (switch_name == std::string(VPR_DELAYLESS_SWITCH_NAME)) {
+      continue;
+    }
+
+    CircuitModelId circuit_model = CircuitModelId::INVALID();
+    /* The name-to-circuit mapping is stored in either cb_switch-to-circuit or sb_switch-to-circuit,
+     * Try to find one and update the device annotation
+     */ 
+    if (0 < openfpga_arch.cb_switch2circuit.count(switch_name)) {
+      circuit_model = openfpga_arch.cb_switch2circuit.at(switch_name); 
+    }
+    if (0 < openfpga_arch.sb_switch2circuit.count(switch_name)) {
+      if (CircuitModelId::INVALID() != circuit_model) {
+        VTR_LOG_WARN("Found a connection block and a switch block switch share the same name '%s' and binded to different circuit models '%s' and '%s'!\nWill use the switch block switch binding!\n",
+                     switch_name.c_str(),
+                     openfpga_arch.circuit_lib.model_name(circuit_model).c_str(),
+                     openfpga_arch.circuit_lib.model_name(openfpga_arch.sb_switch2circuit.at(switch_name)).c_str());
+      }
+      circuit_model = openfpga_arch.sb_switch2circuit.at(switch_name); 
+    }
+
+    /* Cannot find a circuit model, error out! */
+    if (CircuitModelId::INVALID() == circuit_model) {
+      VTR_LOG_ERROR("Fail to find a circuit model for a routing resource graph switch '%s'!\nPlease check your OpenFPGA architecture XML!\n",
+                    switch_name.c_str());
+      exit(1);
+    }
+  
+    /* Now update the device annotation */
+    vpr_device_annotation.add_rr_switch_circuit_model(RRSwitchId(iswitch), circuit_model);
+    VTR_LOGV(verbose_output, 
+             "Binded a routing resource graph switch '%s' to circuit model '%s'\n",
+             switch_name.c_str(),
+             openfpga_arch.circuit_lib.model_name(circuit_model).c_str());
+    count++;
+  }
+  
+  VTR_LOG("Binded %lu routing resource graph switches to circuit models\n",
+          count);
+}
+
+/********************************************************************
+ * Build the link between rr_graph switches and segments to their
+ * physical circuit models 
+ *******************************************************************/
+void annotate_rr_graph_circuit_models(const DeviceContext& vpr_device_ctx, 
+                                      const Arch& openfpga_arch,
+                                      VprDeviceAnnotation& vpr_device_annotation,
+                                      const bool& verbose_output) {
+  /* Iterate over each rr_switch in the device context and bind with names */
+  annotate_rr_switch_circuit_models(vpr_device_ctx, openfpga_arch, vpr_device_annotation, verbose_output);
+}
+
 } /* end namespace openfpga */
diff --git a/openfpga/src/annotation/annotate_rr_gsb.h b/openfpga/src/annotation/annotate_rr_graph.h
similarity index 67%
rename from openfpga/src/annotation/annotate_rr_gsb.h
rename to openfpga/src/annotation/annotate_rr_graph.h
index abf666c4a..d4550639f 100644
--- a/openfpga/src/annotation/annotate_rr_gsb.h
+++ b/openfpga/src/annotation/annotate_rr_graph.h
@@ -1,5 +1,5 @@
-#ifndef ANNOTATE_RR_GSB_H
-#define ANNOTATE_RR_GSB_H
+#ifndef ANNOTATE_RR_GRAPH_H
+#define ANNOTATE_RR_GRAPH_H
 
 /********************************************************************
  * Include header files that are required by function declaration
@@ -19,6 +19,11 @@ void annotate_device_rr_gsb(const DeviceContext& vpr_device_ctx,
                             DeviceRRGSB& device_rr_gsb,
                             const bool& verbose_output);
 
+void annotate_rr_graph_circuit_models(const DeviceContext& vpr_device_ctx, 
+                                      const Arch& openfpga_arch,
+                                      VprDeviceAnnotation& vpr_device_annotation,
+                                      const bool& verbose_output);
+
 } /* end namespace openfpga */
 
 #endif
diff --git a/openfpga/src/base/openfpga_link_arch.cpp b/openfpga/src/base/openfpga_link_arch.cpp
index 88f46571a..bffca3682 100644
--- a/openfpga/src/base/openfpga_link_arch.cpp
+++ b/openfpga/src/base/openfpga_link_arch.cpp
@@ -12,7 +12,7 @@
 #include "annotate_pb_types.h"
 #include "annotate_pb_graph.h"
 #include "annotate_routing.h"
-#include "annotate_rr_gsb.h"
+#include "annotate_rr_graph.h"
 #include "openfpga_link_arch.h"
 
 /* Include global variables of VPR */
@@ -54,6 +54,12 @@ void link_arch(OpenfpgaContext& openfpga_context,
                     openfpga_context.mutable_vpr_device_annotation(),
                     cmd_context.option_enable(cmd, opt_verbose));
 
+  /* Annotate routing architecture to circuit library */
+  annotate_rr_graph_circuit_models(g_vpr_ctx.device(),
+                                   openfpga_context.arch(),
+                                   openfpga_context.mutable_vpr_device_annotation(),
+                                   cmd_context.option_enable(cmd, opt_verbose));
+
   /* Annotate net mapping to each rr_node 
    */
   openfpga_context.mutable_vpr_routing_annotation().init(g_vpr_ctx.device().rr_graph);
diff --git a/openfpga/src/base/openfpga_setup_command.cpp b/openfpga/src/base/openfpga_setup_command.cpp
index 2d08ec38c..e992875bd 100644
--- a/openfpga/src/base/openfpga_setup_command.cpp
+++ b/openfpga/src/base/openfpga_setup_command.cpp
@@ -8,7 +8,6 @@
 #include "openfpga_pb_pin_fixup.h"
 #include "openfpga_lut_truth_table_fixup.h"
 #include "check_netlist_naming_conflict.h"
-#include "annotate_rr_gsb.h"
 #include "compact_routing_hierarchy.h"
 #include "openfpga_setup_command.h"
 

From 4a05cec037d90edb083c5c6c501c349809e4f9c0 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 12 Feb 2020 11:21:40 -0700
Subject: [PATCH 119/645] add rr_segment binding to circuit model

---
 openfpga/src/annotation/annotate_rr_graph.cpp | 46 ++++++++++++++++++-
 openfpga/src/vpr_wrapper/vpr_main.cpp         |  7 +--
 openfpga/test_vpr_arch/k6_frac_N10_40nm.xml   |  2 +-
 3 files changed, 50 insertions(+), 5 deletions(-)

diff --git a/openfpga/src/annotation/annotate_rr_graph.cpp b/openfpga/src/annotation/annotate_rr_graph.cpp
index efb7bd3a7..ebca2d398 100644
--- a/openfpga/src/annotation/annotate_rr_graph.cpp
+++ b/openfpga/src/annotation/annotate_rr_graph.cpp
@@ -406,7 +406,7 @@ void annotate_rr_switch_circuit_models(const DeviceContext& vpr_device_ctx,
                                        const bool& verbose_output) {
   size_t count = 0;
 
-  for (size_t iswitch = 0; iswitch < vpr_device_ctx.rr_switch_inf.size(); iswitch++) {
+  for (size_t iswitch = 0; iswitch < vpr_device_ctx.rr_switch_inf.size(); ++iswitch) {
     std::string switch_name(vpr_device_ctx.rr_switch_inf[iswitch].name); 
     /* Skip the delayless switch, which is only used by the edges between
      * - SOURCE and OPIN
@@ -453,6 +453,47 @@ void annotate_rr_switch_circuit_models(const DeviceContext& vpr_device_ctx,
           count);
 }
 
+/********************************************************************
+ * Build the link between rr_graph routing segments to their physical circuit models 
+ * The binding is done based on the name of rr_segment defined in the
+ * OpenFPGA arch XML
+ *******************************************************************/
+static 
+void annotate_rr_segment_circuit_models(const DeviceContext& vpr_device_ctx, 
+                                        const Arch& openfpga_arch,
+                                        VprDeviceAnnotation& vpr_device_annotation,
+                                        const bool& verbose_output) {
+  size_t count = 0;
+
+  for (size_t iseg = 0; iseg < vpr_device_ctx.arch->Segments.size(); ++iseg) {
+    std::string segment_name = vpr_device_ctx.arch->Segments[iseg].name; 
+    CircuitModelId circuit_model = CircuitModelId::INVALID();
+    /* The name-to-circuit mapping is stored in either cb_switch-to-circuit or sb_switch-to-circuit,
+     * Try to find one and update the device annotation
+     */ 
+    if (0 < openfpga_arch.routing_seg2circuit.count(segment_name)) {
+      circuit_model = openfpga_arch.routing_seg2circuit.at(segment_name); 
+    }
+    /* Cannot find a circuit model, error out! */
+    if (CircuitModelId::INVALID() == circuit_model) {
+      VTR_LOG_ERROR("Fail to find a circuit model for a routing segment '%s'!\nPlease check your OpenFPGA architecture XML!\n",
+                    segment_name.c_str());
+      exit(1);
+    }
+  
+    /* Now update the device annotation */
+    vpr_device_annotation.add_rr_segment_circuit_model(RRSegmentId(iseg), circuit_model);
+    VTR_LOGV(verbose_output, 
+             "Binded a routing segment '%s' to circuit model '%s'\n",
+             segment_name.c_str(),
+             openfpga_arch.circuit_lib.model_name(circuit_model).c_str());
+    count++;
+  }
+  
+  VTR_LOG("Binded %lu routing segments to circuit models\n",
+          count);
+}
+
 /********************************************************************
  * Build the link between rr_graph switches and segments to their
  * physical circuit models 
@@ -463,6 +504,9 @@ void annotate_rr_graph_circuit_models(const DeviceContext& vpr_device_ctx,
                                       const bool& verbose_output) {
   /* Iterate over each rr_switch in the device context and bind with names */
   annotate_rr_switch_circuit_models(vpr_device_ctx, openfpga_arch, vpr_device_annotation, verbose_output);
+
+  /* Iterate over each rr_segment in the device context and bind with names */
+  annotate_rr_segment_circuit_models(vpr_device_ctx, openfpga_arch, vpr_device_annotation, verbose_output);
 }
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/vpr_wrapper/vpr_main.cpp b/openfpga/src/vpr_wrapper/vpr_main.cpp
index bf0f6de91..37560b288 100644
--- a/openfpga/src/vpr_wrapper/vpr_main.cpp
+++ b/openfpga/src/vpr_wrapper/vpr_main.cpp
@@ -41,20 +41,21 @@ int vpr(int argc, char** argv) {
     vtr::ScopedFinishTimer t("The entire flow of VPR");
 
     t_options Options = t_options();
-    t_arch Arch = t_arch();
+    /* Arch should NOT be freed once this function is done */
+    t_arch* Arch = new t_arch;
     t_vpr_setup vpr_setup = t_vpr_setup();
 
     try {
         vpr_install_signal_handler();
 
         /* Read options, architecture, and circuit netlist */
-        vpr_init(argc, const_cast<const char**>(argv), &Options, &vpr_setup, &Arch);
+        vpr_init(argc, const_cast<const char**>(argv), &Options, &vpr_setup, Arch);
 
         if (Options.show_version) {
             return SUCCESS_EXIT_CODE;
         }
 
-        bool flow_succeeded = vpr_flow(vpr_setup, Arch);
+        bool flow_succeeded = vpr_flow(vpr_setup, *Arch);
         if (!flow_succeeded) {
             VTR_LOG("VPR failed to implement circuit\n");
             return UNIMPLEMENTABLE_EXIT_CODE;
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml
index 269384cbc..a090fd45b 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml
@@ -132,7 +132,7 @@
     <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
 			     With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
 			     reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
-    <segment freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
       <mux name="0"/>
       <sb type="pattern">1 1 1 1 1</sb>
       <cb type="pattern">1 1 1 1</cb>

From ce63b1cc6288c034f1a85a38229efd94ce7f99dc Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 12 Feb 2020 11:40:20 -0700
Subject: [PATCH 120/645] add circuit model binding for direct connections and
 enhance model type checking

---
 openfpga/src/annotation/annotate_rr_graph.cpp | 75 ++++++++++++++++++-
 .../src/annotation/vpr_device_annotation.cpp  | 20 +++++
 .../src/annotation/vpr_device_annotation.h    |  5 ++
 3 files changed, 98 insertions(+), 2 deletions(-)

diff --git a/openfpga/src/annotation/annotate_rr_graph.cpp b/openfpga/src/annotation/annotate_rr_graph.cpp
index ebca2d398..351c248bb 100644
--- a/openfpga/src/annotation/annotate_rr_graph.cpp
+++ b/openfpga/src/annotation/annotate_rr_graph.cpp
@@ -439,6 +439,14 @@ void annotate_rr_switch_circuit_models(const DeviceContext& vpr_device_ctx,
                     switch_name.c_str());
       exit(1);
     }
+
+    /* Check the circuit model type */
+    if (CIRCUIT_MODEL_MUX != openfpga_arch.circuit_lib.model_type(circuit_model)) {
+      VTR_LOG_ERROR("Require circuit model type '%s' for a routing resource graph switch '%s'!\nPlease check your OpenFPGA architecture XML!\n",
+                    CIRCUIT_MODEL_TYPE_STRING[CIRCUIT_MODEL_MUX],
+                    switch_name.c_str());
+      exit(1);
+    }
   
     /* Now update the device annotation */
     vpr_device_annotation.add_rr_switch_circuit_model(RRSwitchId(iswitch), circuit_model);
@@ -480,6 +488,14 @@ void annotate_rr_segment_circuit_models(const DeviceContext& vpr_device_ctx,
                     segment_name.c_str());
       exit(1);
     }
+
+    /* Check the circuit model type */
+    if (CIRCUIT_MODEL_CHAN_WIRE != openfpga_arch.circuit_lib.model_type(circuit_model)) {
+      VTR_LOG_ERROR("Require circuit model type '%s' for a routing segment '%s'!\nPlease check your OpenFPGA architecture XML!\n",
+                    CIRCUIT_MODEL_TYPE_STRING[CIRCUIT_MODEL_CHAN_WIRE],
+                    segment_name.c_str());
+      exit(1);
+    }
   
     /* Now update the device annotation */
     vpr_device_annotation.add_rr_segment_circuit_model(RRSegmentId(iseg), circuit_model);
@@ -495,8 +511,60 @@ void annotate_rr_segment_circuit_models(const DeviceContext& vpr_device_ctx,
 }
 
 /********************************************************************
- * Build the link between rr_graph switches and segments to their
- * physical circuit models 
+ * Build the link between rr_graph direct connection to their physical circuit models 
+ * The binding is done based on the name of directs defined in the
+ * OpenFPGA arch XML
+ *******************************************************************/
+static 
+void annotate_direct_circuit_models(const DeviceContext& vpr_device_ctx, 
+                                    const Arch& openfpga_arch,
+                                    VprDeviceAnnotation& vpr_device_annotation,
+                                    const bool& verbose_output) {
+  size_t count = 0;
+
+  for (int idirect = 0; idirect < vpr_device_ctx.arch->num_directs; ++idirect) {
+    std::string direct_name = vpr_device_ctx.arch->Directs[idirect].name; 
+    CircuitModelId circuit_model = CircuitModelId::INVALID();
+    /* The name-to-circuit mapping is stored in either cb_switch-to-circuit or sb_switch-to-circuit,
+     * Try to find one and update the device annotation
+     */ 
+    if (0 < openfpga_arch.direct2circuit.count(direct_name)) {
+      circuit_model = openfpga_arch.direct2circuit.at(direct_name); 
+    }
+    /* Cannot find a circuit model, error out! */
+    if (CircuitModelId::INVALID() == circuit_model) {
+      VTR_LOG_ERROR("Fail to find a circuit model for a direct connection '%s'!\nPlease check your OpenFPGA architecture XML!\n",
+                    direct_name.c_str());
+      exit(1);
+    }
+
+    /* Check the circuit model type */
+    if (CIRCUIT_MODEL_WIRE != openfpga_arch.circuit_lib.model_type(circuit_model)) {
+      VTR_LOG_ERROR("Require circuit model type '%s' for a direct connection '%s'!\nPlease check your OpenFPGA architecture XML!\n",
+                    CIRCUIT_MODEL_TYPE_STRING[CIRCUIT_MODEL_WIRE],
+                    direct_name.c_str());
+      exit(1);
+    }
+  
+    /* Now update the device annotation */
+    vpr_device_annotation.add_direct_circuit_model(idirect, circuit_model);
+    VTR_LOGV(verbose_output, 
+             "Binded a direct connection '%s' to circuit model '%s'\n",
+             direct_name.c_str(),
+             openfpga_arch.circuit_lib.model_name(circuit_model).c_str());
+    count++;
+  }
+  
+  VTR_LOG("Binded %lu direct connections to circuit models\n",
+          count);
+}
+
+/********************************************************************
+ * Build the link between 
+ * - rr_graph switches
+ * - rr_graph segments 
+ * - directlist
+ * to their physical circuit models 
  *******************************************************************/
 void annotate_rr_graph_circuit_models(const DeviceContext& vpr_device_ctx, 
                                       const Arch& openfpga_arch,
@@ -507,6 +575,9 @@ void annotate_rr_graph_circuit_models(const DeviceContext& vpr_device_ctx,
 
   /* Iterate over each rr_segment in the device context and bind with names */
   annotate_rr_segment_circuit_models(vpr_device_ctx, openfpga_arch, vpr_device_annotation, verbose_output);
+
+  /* Iterate over each direct connection in the device context and bind with names */
+  annotate_direct_circuit_models(vpr_device_ctx, openfpga_arch, vpr_device_annotation, verbose_output);
 }
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/annotation/vpr_device_annotation.cpp b/openfpga/src/annotation/vpr_device_annotation.cpp
index 280e4ca38..aa2e6fce9 100644
--- a/openfpga/src/annotation/vpr_device_annotation.cpp
+++ b/openfpga/src/annotation/vpr_device_annotation.cpp
@@ -233,6 +233,15 @@ CircuitModelId VprDeviceAnnotation::rr_segment_circuit_model(const RRSegmentId&
   return rr_segment_circuit_models_.at(rr_segment);
 }
 
+CircuitModelId VprDeviceAnnotation::direct_circuit_model(const size_t& direct) const {
+  /* Ensure that the rr_switch is in the list */
+  std::map<size_t, CircuitModelId>::const_iterator it = direct_circuit_models_.find(direct);
+  if (it == direct_circuit_models_.end()) {
+    return CircuitModelId::INVALID();
+  }
+  return direct_circuit_models_.at(direct);
+}
+
 /************************************************************************
  * Public mutators
  ***********************************************************************/
@@ -452,4 +461,15 @@ void VprDeviceAnnotation::add_rr_segment_circuit_model(const RRSegmentId& rr_seg
   rr_segment_circuit_models_[rr_segment] = circuit_model;
 }
 
+void VprDeviceAnnotation::add_direct_circuit_model(const size_t& direct, const CircuitModelId& circuit_model) {
+  /* Warn any override attempt */
+  std::map<size_t, CircuitModelId>::const_iterator it = direct_circuit_models_.find(direct);
+  if (it != direct_circuit_models_.end()) {
+    VTR_LOG_WARN("Override the annotation between direct '%ld' and its circuit_model '%ld'!\n",
+                 size_t(direct), size_t(circuit_model));
+  }
+
+  direct_circuit_models_[direct] = circuit_model;
+}
+
 } /* End namespace openfpga*/
diff --git a/openfpga/src/annotation/vpr_device_annotation.h b/openfpga/src/annotation/vpr_device_annotation.h
index 211676264..74868ae61 100644
--- a/openfpga/src/annotation/vpr_device_annotation.h
+++ b/openfpga/src/annotation/vpr_device_annotation.h
@@ -71,6 +71,7 @@ class VprDeviceAnnotation {
     t_pb_graph_pin* physical_pb_graph_pin(t_pb_graph_pin* pb_graph_pin) const;
     CircuitModelId rr_switch_circuit_model(const RRSwitchId& rr_switch) const;
     CircuitModelId rr_segment_circuit_model(const RRSegmentId& rr_segment) const;
+    CircuitModelId direct_circuit_model(const size_t& direct) const;
   public:  /* Public mutators */
     void add_pb_type_physical_mode(t_pb_type* pb_type, t_mode* physical_mode);
     void add_physical_pb_type(t_pb_type* operating_pb_type, t_pb_type* physical_pb_type);
@@ -90,6 +91,7 @@ class VprDeviceAnnotation {
     void add_physical_pb_graph_pin(t_pb_graph_pin* operating_pb_graph_pin, t_pb_graph_pin* physical_pb_graph_pin);
     void add_rr_switch_circuit_model(const RRSwitchId& rr_switch, const CircuitModelId& circuit_model);
     void add_rr_segment_circuit_model(const RRSegmentId& rr_segment, const CircuitModelId& circuit_model);
+    void add_direct_circuit_model(const size_t& direct, const CircuitModelId& circuit_model);
   private: /* Internal data */
     /* Pair a regular pb_type to its physical pb_type */
     std::map<t_pb_type*, t_pb_type*> physical_pb_types_;
@@ -170,6 +172,9 @@ class VprDeviceAnnotation {
 
     /* Pair a Routing Segment (rr_segment) to a circuit model */
     std::map<RRSegmentId, CircuitModelId> rr_segment_circuit_models_;
+
+    /* Pair a direct connection (direct) to a circuit model */
+    std::map<size_t, CircuitModelId> direct_circuit_models_;
 };
 
 } /* End namespace openfpga*/

From c78d3e9af175441d32d1dbee4aac9ef91e924f7c Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 12 Feb 2020 14:58:23 -0700
Subject: [PATCH 121/645] add mux library builder

---
 openfpga/src/base/openfpga_context.h          |   6 +
 openfpga/src/base/openfpga_link_arch.cpp      |  31 +++
 openfpga/src/mux_lib/mux_library_builder.cpp  | 228 ++++++++++++++++++
 openfpga/src/mux_lib/mux_library_builder.h    |  23 ++
 .../src/utils/openfpga_rr_graph_utils.cpp     |  18 ++
 openfpga/src/utils/openfpga_rr_graph_utils.h  |   3 +
 openfpga/src/utils/pb_graph_utils.cpp         |  25 ++
 openfpga/src/utils/pb_graph_utils.h           |   3 +
 8 files changed, 337 insertions(+)
 create mode 100644 openfpga/src/mux_lib/mux_library_builder.cpp
 create mode 100644 openfpga/src/mux_lib/mux_library_builder.h

diff --git a/openfpga/src/base/openfpga_context.h b/openfpga/src/base/openfpga_context.h
index aed6b8014..4234de5b4 100644
--- a/openfpga/src/base/openfpga_context.h
+++ b/openfpga/src/base/openfpga_context.h
@@ -7,6 +7,7 @@
 #include "vpr_device_annotation.h"
 #include "vpr_clustering_annotation.h"
 #include "vpr_routing_annotation.h"
+#include "mux_library.h"
 #include "device_rr_gsb.h"
 
 /********************************************************************
@@ -44,6 +45,7 @@ class OpenfpgaContext : public Context  {
     const openfpga::VprClusteringAnnotation& vpr_clustering_annotation() const { return vpr_clustering_annotation_; }
     const openfpga::VprRoutingAnnotation& vpr_routing_annotation() const { return vpr_routing_annotation_; }
     const openfpga::DeviceRRGSB& device_rr_gsb() const { return device_rr_gsb_; }
+    const openfpga::MuxLibrary& mux_lib() const { return mux_lib_; }
   public:  /* Public mutators */
     openfpga::Arch& mutable_arch() { return arch_; }
     openfpga::VprDeviceAnnotation& mutable_vpr_device_annotation() { return vpr_device_annotation_; }
@@ -51,6 +53,7 @@ class OpenfpgaContext : public Context  {
     openfpga::VprClusteringAnnotation& mutable_vpr_clustering_annotation() { return vpr_clustering_annotation_; }
     openfpga::VprRoutingAnnotation& mutable_vpr_routing_annotation() { return vpr_routing_annotation_; }
     openfpga::DeviceRRGSB& mutable_device_rr_gsb() { return device_rr_gsb_; }
+    openfpga::MuxLibrary& mutable_mux_lib() { return mux_lib_; }
   private: /* Internal data */
     /* Data structure to store information from read_openfpga_arch library */
     openfpga::Arch arch_;
@@ -69,6 +72,9 @@ class OpenfpgaContext : public Context  {
 
     /* Device-level annotation */
     openfpga::DeviceRRGSB device_rr_gsb_;
+    
+    /* Library of physical implmentation of routing multiplexers */
+    openfpga::MuxLibrary mux_lib_;
 };
 
 #endif
diff --git a/openfpga/src/base/openfpga_link_arch.cpp b/openfpga/src/base/openfpga_link_arch.cpp
index bffca3682..78afc93a2 100644
--- a/openfpga/src/base/openfpga_link_arch.cpp
+++ b/openfpga/src/base/openfpga_link_arch.cpp
@@ -13,6 +13,7 @@
 #include "annotate_pb_graph.h"
 #include "annotate_routing.h"
 #include "annotate_rr_graph.h"
+#include "mux_library_builder.h"
 #include "openfpga_link_arch.h"
 
 /* Include global variables of VPR */
@@ -21,6 +22,28 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
+/********************************************************************
+ * A function to identify if the routing resource graph generated by
+ * VPR is support by OpenFPGA
+ * - Currently we only support uni-directional
+ *   It means every routing tracks must have a direction
+ *******************************************************************/
+static 
+bool is_vpr_rr_graph_supported(const RRGraph& rr_graph) {
+  /* Check if the rr_graph is uni-directional*/
+  for (const RRNodeId& node : rr_graph.nodes()) {
+    if (CHANX != rr_graph.node_type(node) && CHANY != rr_graph.node_type(node)) {
+      continue;
+    }
+    if (BI_DIRECTION == rr_graph.node_direction(node)) {
+      VTR_LOG_ERROR("Routing resource graph is bi-directional. OpenFPGA currently supports uni-directional routing architecture only.\n");
+      return false;
+    }
+  }
+ 
+  return true;
+}
+
 /********************************************************************
  * Top-level function to link openfpga architecture to VPR, including:
  * - physical pb_type
@@ -72,9 +95,17 @@ void link_arch(OpenfpgaContext& openfpga_context,
    * - RRGSB
    * - DeviceRRGSB 
    */
+  if (false == is_vpr_rr_graph_supported(g_vpr_ctx.device().rr_graph)) {
+    return;
+  }
+
   annotate_device_rr_gsb(g_vpr_ctx.device(),
                          openfpga_context.mutable_device_rr_gsb(),
                          cmd_context.option_enable(cmd, opt_verbose));
+
+  /* Build multiplexer library */
+  openfpga_context.mutable_mux_lib() = build_device_mux_library(g_vpr_ctx.device(),
+                                                                const_cast<const OpenfpgaContext&>(openfpga_context)); 
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/mux_lib/mux_library_builder.cpp b/openfpga/src/mux_lib/mux_library_builder.cpp
new file mode 100644
index 000000000..953dbb308
--- /dev/null
+++ b/openfpga/src/mux_lib/mux_library_builder.cpp
@@ -0,0 +1,228 @@
+/********************************************************************
+ * This file includes the functions of builders for MuxLibrary.
+ *******************************************************************/
+#include <cmath>
+
+/* Headers from vtrutil library */
+#include "vtr_time.h"
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+/* Headers from readarchopenfpga library */
+#include "circuit_types.h"
+#include "circuit_library.h"
+
+#include "mux_utils.h"
+#include "pb_type_utils.h"
+#include "pb_graph_utils.h"
+#include "openfpga_rr_graph_utils.h"
+
+#include "mux_library.h"
+#include "mux_library_builder.h"
+
+/* Begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Update MuxLibrary with the unique multiplexer structures
+ * found in the global routing architecture
+ *******************************************************************/
+static 
+void build_routing_arch_mux_library(const DeviceContext& vpr_device_ctx,
+                                    const CircuitLibrary& circuit_lib,
+                                    const VprDeviceAnnotation& vpr_device_annotation, 
+                                    MuxLibrary& mux_lib) {
+  /* The routing path is. 
+   * OPIN ----> CHAN ----> ... ----> CHAN ----> IPIN
+   * Each edge is a switch, for IPIN, the switch is a connection block,
+   * for the rest is a switch box
+   */
+  /* Count the sizes of muliplexers in routing architecture */  
+  for (const RRNodeId& node : vpr_device_ctx.rr_graph.nodes()) {
+    switch (vpr_device_ctx.rr_graph.node_type(node)) {
+    case IPIN: 
+    case CHANX:
+    case CHANY: {
+      /* Have to consider the fan_in only, it is a connection block (multiplexer)*/
+      if ( (0 == vpr_device_ctx.rr_graph.node_in_edges(node).size()) 
+        || (1 == vpr_device_ctx.rr_graph.node_in_edges(node).size()) ) { 
+        break; 
+      }
+      /* Find the circuit_model for multiplexers in connection blocks */
+      std::vector<RRSwitchId> driver_switches = get_rr_graph_driver_switches(vpr_device_ctx.rr_graph, node);
+      VTR_ASSERT(1 == driver_switches.size());
+      const CircuitModelId& rr_switch_circuit_model = vpr_device_annotation.rr_switch_circuit_model(driver_switches[0]);
+      /* we should select a circuit model for the routing resource switch */
+      VTR_ASSERT(CircuitModelId::INVALID() != rr_switch_circuit_model);
+      /* Add the mux to mux_library */
+      mux_lib.add_mux(circuit_lib, rr_switch_circuit_model, vpr_device_ctx.rr_graph.node_in_edges(node).size()); 
+      break;
+    }
+    default:
+      /* We do not care other types of rr_node */
+      break;
+    }
+  }
+}
+
+
+/********************************************************************
+ * For a given pin of a pb_graph_node
+ * - Identify the interconnect implementation 
+ * - Find the number of inputs for the interconnect implementation
+ * - Update the mux_library is the implementation is multiplexers
+ ********************************************************************/
+static 
+void build_pb_graph_pin_interconnect_mux_library(t_pb_graph_pin* pb_graph_pin, 
+                                                 t_mode* interconnect_mode,
+                                                 const CircuitLibrary& circuit_lib,
+                                                 const VprDeviceAnnotation& vpr_device_annotation,
+                                                 MuxLibrary& mux_lib) {
+  /* Find the interconnect in the physical mode that drives this pin */
+  t_interconnect* physical_interc = pb_graph_pin_interc(pb_graph_pin, interconnect_mode);
+  /* Bypass if the interc does not indicate multiplexers */
+  if (MUX_INTERC != vpr_device_annotation.interconnect_physical_type(physical_interc)) {
+    return;
+  }
+  size_t mux_size = pb_graph_pin_inputs(pb_graph_pin, physical_interc).size(); 
+  VTR_ASSERT(true == valid_mux_implementation_num_inputs(mux_size));
+  const CircuitModelId& interc_circuit_model = vpr_device_annotation.interconnect_circuit_model(physical_interc);
+  VTR_ASSERT(CircuitModelId::INVALID() != interc_circuit_model); 
+  /* Add the mux model to library */
+  mux_lib.add_mux(circuit_lib, interc_circuit_model, mux_size);
+}
+
+/********************************************************************
+ * Update MuxLibrary with the unique multiplexer structures 
+ * found in programmable logic blocks
+ ********************************************************************/
+static 
+void rec_build_vpr_physical_pb_graph_node_mux_library(t_pb_graph_node* pb_graph_node,
+                                                      const CircuitLibrary& circuit_lib,
+                                                      const VprDeviceAnnotation& vpr_device_annotation,
+                                                      MuxLibrary& mux_lib) {
+  /* Find the number of inputs for each interconnect of this pb_graph_node
+   * This is only applicable to each interconnect which will be implemented with multiplexers
+   */
+  t_mode* parent_physical_mode = nullptr;
+
+  if (false == pb_graph_node->is_root()) {
+    parent_physical_mode = vpr_device_annotation.physical_mode(pb_graph_node->parent_pb_graph_node->pb_type);
+  }
+
+  for (int iport = 0; iport < pb_graph_node->num_input_ports; ++iport) {
+    for (int ipin = 0; ipin < pb_graph_node->num_input_pins[iport]; ++ipin) {
+      build_pb_graph_pin_interconnect_mux_library(&(pb_graph_node->input_pins[iport][ipin]), 
+                                                  parent_physical_mode,
+                                                  circuit_lib,
+                                                  vpr_device_annotation,
+                                                  mux_lib);
+    }
+  }
+
+  for (int iport = 0; iport < pb_graph_node->num_clock_ports; ++iport) {
+    for (int ipin = 0; ipin < pb_graph_node->num_clock_pins[iport]; ++ipin) {
+      build_pb_graph_pin_interconnect_mux_library(&(pb_graph_node->clock_pins[iport][ipin]), 
+                                                  parent_physical_mode,
+                                                  circuit_lib,
+                                                  vpr_device_annotation,
+                                                  mux_lib);
+    }
+  }
+
+  /* Return if this is a primitive node */
+  if (true == is_primitive_pb_type(pb_graph_node->pb_type)) {
+    return;
+  }
+ 
+  /* Get the physical mode, primitive node does not have physical mode */
+  t_mode* physical_mode = vpr_device_annotation.physical_mode(pb_graph_node->pb_type);
+  VTR_ASSERT(nullptr != physical_mode);
+
+  /* Note that the output port interconnect should be considered for non-primitive nodes */
+  for (int iport = 0; iport < pb_graph_node->num_output_ports; ++iport) {
+    for (int ipin = 0; ipin < pb_graph_node->num_output_pins[iport]; ++ipin) {
+      build_pb_graph_pin_interconnect_mux_library(&(pb_graph_node->output_pins[iport][ipin]), 
+                                                  physical_mode,
+                                                  circuit_lib,
+                                                  vpr_device_annotation,
+                                                  mux_lib);
+    }
+  }
+ 
+  /* Visit all the child nodes in the physical mode */
+  for (int ipb = 0; ipb < physical_mode->num_pb_type_children; ++ipb) {
+    for (int jpb = 0; jpb < physical_mode->pb_type_children[ipb].num_pb; ++jpb) {
+      rec_build_vpr_physical_pb_graph_node_mux_library(&(pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb][jpb]), 
+                                                       circuit_lib, vpr_device_annotation,
+                                                       mux_lib);
+    }
+  }
+}
+
+/********************************************************************
+ * Update MuxLibrary with the unique multiplexers required by
+ * LUTs in the circuit library
+ ********************************************************************/
+static 
+void build_lut_mux_library(MuxLibrary& mux_lib,
+                           const CircuitLibrary& circuit_lib) {
+  /* Find all the circuit models which are LUTs in the circuit library */
+  for (const auto& circuit_model : circuit_lib.models()) {
+    /* Bypass non-LUT circuit models */
+    if (CIRCUIT_MODEL_LUT != circuit_lib.model_type(circuit_model)) {
+      continue;
+    }
+    /* Find the MUX size required by the LUT */
+    /* Get input ports which are not global ports! */
+    std::vector<CircuitPortId> input_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true);
+    VTR_ASSERT(1 == input_ports.size());
+    /* MUX size = 2^lut_size */
+    size_t lut_mux_size = (size_t)pow(2., (double)(circuit_lib.port_size(input_ports[0])));
+    /* Add mux to the mux library */
+    mux_lib.add_mux(circuit_lib, circuit_model, lut_mux_size);
+  }
+}
+
+/* Statistic for all the multiplexers in FPGA
+ * We determine the sizes and its structure (according to spice_model) for each type of multiplexers
+ * We search multiplexers in Switch Blocks, Connection blocks and Configurable Logic Blocks
+ * In additional to multiplexers, this function also consider crossbars.
+ * All the statistics are stored in a linked list, as a return value
+ */
+MuxLibrary build_device_mux_library(const DeviceContext& vpr_device_ctx,
+                                    const OpenfpgaContext& openfpga_ctx) {
+  vtr::ScopedStartFinishTimer timer("Build a library of physical multiplexers");
+
+  /* MuxLibrary to store the information of Multiplexers*/
+  MuxLibrary mux_lib;
+
+  /* Step 1: We should check the multiplexer spice models defined in routing architecture.*/
+  build_routing_arch_mux_library(vpr_device_ctx, openfpga_ctx.arch().circuit_lib, 
+                                 openfpga_ctx.vpr_device_annotation(),
+                                 mux_lib);
+
+  /* Step 2: Count the sizes of multiplexers in complex logic blocks */  
+  for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
+    /* By pass nullptr for pb_graph head */
+    if (nullptr == lb_type.pb_graph_head) {
+      continue;
+    }
+    rec_build_vpr_physical_pb_graph_node_mux_library(lb_type.pb_graph_head,
+                                                     openfpga_ctx.arch().circuit_lib,
+                                                     openfpga_ctx.vpr_device_annotation(),
+                                                     mux_lib); 
+  }
+
+  /* Step 3: count the size of multiplexer that will be used in LUTs*/
+  build_lut_mux_library(mux_lib, openfpga_ctx.arch().circuit_lib); 
+
+  VTR_LOG("Built a multiplexer library of %lu physical multiplexers.\n",
+          mux_lib.muxes().size());
+  VTR_LOG("Maximum multiplexer size is %lu.\n",
+          mux_lib.max_mux_size());
+
+  return mux_lib;
+}
+
+} /* End namespace openfpga*/
diff --git a/openfpga/src/mux_lib/mux_library_builder.h b/openfpga/src/mux_lib/mux_library_builder.h
new file mode 100644
index 000000000..d303e7e76
--- /dev/null
+++ b/openfpga/src/mux_lib/mux_library_builder.h
@@ -0,0 +1,23 @@
+#ifndef MUX_LIBRARY_BUILDER_H
+#define MUX_LIBRARY_BUILDER_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "vpr_context.h"
+#include "openfpga_context.h"
+#include "mux_library.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+MuxLibrary build_device_mux_library(const DeviceContext& vpr_device_ctx,
+                                    const OpenfpgaContext& openfpga_ctx);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/utils/openfpga_rr_graph_utils.cpp b/openfpga/src/utils/openfpga_rr_graph_utils.cpp
index cac7284d5..21ec1b640 100644
--- a/openfpga/src/utils/openfpga_rr_graph_utils.cpp
+++ b/openfpga/src/utils/openfpga_rr_graph_utils.cpp
@@ -2,6 +2,8 @@
  * This file includes most utilized functions for the rr_graph
  * data structure in the OpenFPGA context
  *******************************************************************/
+#include <algorithm>
+
 /* Headers from vtrutil library */
 #include "vtr_assert.h"
 #include "vtr_log.h"
@@ -63,4 +65,20 @@ vtr::Point<size_t> get_track_rr_node_end_coordinate(const RRGraph& rr_graph,
   return end_coordinator;
 }
 
+/************************************************************************
+ * Find the driver switches for a node in the rr_graph
+ * This function only return unique driver switches
+ ***********************************************************************/
+std::vector<RRSwitchId> get_rr_graph_driver_switches(const RRGraph& rr_graph,
+                                                     const RRNodeId& node) {
+  std::vector<RRSwitchId> driver_switches;
+  for (const RREdgeId& edge : rr_graph.node_in_edges(node)) {
+    if (driver_switches.end() == std::find(driver_switches.begin(), driver_switches.end(), rr_graph.edge_switch(edge))) {
+      driver_switches.push_back(rr_graph.edge_switch(edge));
+    }
+  }
+
+  return driver_switches;
+}
+
 } /* end namespace openfpga */
diff --git a/openfpga/src/utils/openfpga_rr_graph_utils.h b/openfpga/src/utils/openfpga_rr_graph_utils.h
index 44306664b..0c4d174c6 100644
--- a/openfpga/src/utils/openfpga_rr_graph_utils.h
+++ b/openfpga/src/utils/openfpga_rr_graph_utils.h
@@ -23,6 +23,9 @@ vtr::Point<size_t> get_track_rr_node_start_coordinate(const RRGraph& rr_graph,
 vtr::Point<size_t> get_track_rr_node_end_coordinate(const RRGraph& rr_graph,
                                                     const RRNodeId& track_rr_node);
 
+std::vector<RRSwitchId> get_rr_graph_driver_switches(const RRGraph& rr_graph,
+                                                     const RRNodeId& node);
+
 } /* end namespace openfpga */
 
 #endif
diff --git a/openfpga/src/utils/pb_graph_utils.cpp b/openfpga/src/utils/pb_graph_utils.cpp
index 84e642bde..a3d6a999e 100644
--- a/openfpga/src/utils/pb_graph_utils.cpp
+++ b/openfpga/src/utils/pb_graph_utils.cpp
@@ -38,4 +38,29 @@ std::vector<t_pb_graph_pin*> pb_graph_pin_inputs(t_pb_graph_pin* pb_graph_pin,
   return inputs;
 }
 
+/********************************************************************
+ * This function aims to find out the interconnect that drives
+ * a given pb_graph pin when operating in a select mode
+ *******************************************************************/
+t_interconnect* pb_graph_pin_interc(t_pb_graph_pin* pb_graph_pin, 
+                                    t_mode* selected_mode) {
+  t_interconnect* interc = nullptr;
+
+  /* Search the input edges only, stats on the size of MUX we may need (fan-in) */
+  for (int iedge = 0; iedge < pb_graph_pin->num_input_edges; ++iedge) {
+    /* We care the only edges in the selected mode */
+    if (selected_mode != pb_graph_pin->input_edges[iedge]->interconnect->parent_mode) {
+      continue;
+    }
+    /* There should be one unique interconnect to be found! */
+    if (nullptr != interc) {
+      VTR_ASSERT(interc == pb_graph_pin->input_edges[iedge]->interconnect);
+    } else {
+      interc = pb_graph_pin->input_edges[iedge]->interconnect;
+    }
+  }
+  
+  return interc; 
+} 
+
 } /* end namespace openfpga */
diff --git a/openfpga/src/utils/pb_graph_utils.h b/openfpga/src/utils/pb_graph_utils.h
index d46457b7d..8c1c3064a 100644
--- a/openfpga/src/utils/pb_graph_utils.h
+++ b/openfpga/src/utils/pb_graph_utils.h
@@ -18,6 +18,9 @@ namespace openfpga {
 std::vector<t_pb_graph_pin*> pb_graph_pin_inputs(t_pb_graph_pin* pb_graph_pin,
                                                  t_interconnect* selected_interconnect); 
 
+t_interconnect* pb_graph_pin_interc(t_pb_graph_pin* pb_graph_pin, 
+                                    t_mode* selected_mode); 
+
 } /* end namespace openfpga */
 
 #endif

From df3ae60954849c7bf83d799b0c37abd3f23a75cb Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 12 Feb 2020 15:19:40 -0700
Subject: [PATCH 122/645] add default configurable memory model set-up when
 reading openfpga architecture XML

---
 .../src/openfpga_arch_linker.cpp              | 47 +++++++++++++++++++
 .../src/openfpga_arch_linker.h                |  3 ++
 .../src/read_xml_openfpga_arch.cpp            |  7 +++
 3 files changed, 57 insertions(+)

diff --git a/libopenfpga/libarchopenfpga/src/openfpga_arch_linker.cpp b/libopenfpga/libarchopenfpga/src/openfpga_arch_linker.cpp
index 27b065053..90ae1aad3 100644
--- a/libopenfpga/libarchopenfpga/src/openfpga_arch_linker.cpp
+++ b/libopenfpga/libarchopenfpga/src/openfpga_arch_linker.cpp
@@ -3,6 +3,8 @@
  * data structures inside the openfpga arch data structure
  *******************************************************************/
 #include "vtr_log.h"
+#include "vtr_assert.h"
+
 #include "openfpga_arch_linker.h"
 
 /********************************************************************
@@ -21,3 +23,48 @@ void link_config_protocol_to_circuit_library(openfpga::Arch& openfpga_arch) {
 
   openfpga_arch.config_protocol.set_memory_model(config_memory_model); 
 }
+
+/********************************************************************
+ * Link the circuit model of SRAM ports of each circuit model
+ * to a default SRAM circuit model.
+ * This function aims to ease the XML writing, allowing users to skip
+ * the circuit model definition for SRAM ports that are used by default
+ * TODO: Maybe deprecated as we prefer strict definition 
+ *******************************************************************/
+void config_circuit_models_sram_port_to_default_sram_model(CircuitLibrary& circuit_lib,
+                                                           const CircuitModelId& default_sram_model) {
+  VTR_ASSERT(CircuitModelId::INVALID() != default_sram_model);
+
+  for (const auto& model : circuit_lib.models()) {
+    for (const auto& port : circuit_lib.model_ports(model)) {
+      /* Bypass non SRAM ports */
+      if (CIRCUIT_MODEL_PORT_SRAM != circuit_lib.port_type(port)) {
+        continue;
+      }
+
+      /* Write for the default SRAM SPICE model! */
+      circuit_lib.set_port_tri_state_model_id(port, default_sram_model);
+
+      /* Only show warning when we try to override the given spice_model_name ! */ 
+      if (true == circuit_lib.port_tri_state_model_name(port).empty()) { 
+        VTR_LOG("Use the default configurable memory model '%s' for circuit model '%s' port '%s')\n",
+                circuit_lib.model_name(default_sram_model).c_str(),
+                circuit_lib.model_name(model).c_str(),
+                circuit_lib.port_prefix(port).c_str());
+        continue;
+      }
+
+      /* Give a warning !!! */
+      if (circuit_lib.model_name(default_sram_model) != circuit_lib.port_tri_state_model_name(port)) {
+        VTR_LOG_WARN("Overwrite SRAM circuit model for circuit model port (name:%s, port:%s) to be the correct one (name:%s)!\n",
+                     circuit_lib.model_name(model).c_str(),
+                     circuit_lib.port_prefix(port).c_str(),
+                     circuit_lib.model_name(default_sram_model).c_str());
+      }
+    }
+  }
+  /* Rebuild the submodels for circuit_library
+   * because we have created links for ports 
+   */
+  circuit_lib.build_model_links();
+}
diff --git a/libopenfpga/libarchopenfpga/src/openfpga_arch_linker.h b/libopenfpga/libarchopenfpga/src/openfpga_arch_linker.h
index fea97330a..52e49cb66 100644
--- a/libopenfpga/libarchopenfpga/src/openfpga_arch_linker.h
+++ b/libopenfpga/libarchopenfpga/src/openfpga_arch_linker.h
@@ -5,4 +5,7 @@
 
 void link_config_protocol_to_circuit_library(openfpga::Arch& openfpga_arch);
 
+void config_circuit_models_sram_port_to_default_sram_model(CircuitLibrary& circuit_lib,
+                                                           const CircuitModelId& default_sram_model);
+
 #endif
diff --git a/libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.cpp b/libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.cpp
index f30ff4f1e..b35955f97 100644
--- a/libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.cpp
+++ b/libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.cpp
@@ -70,6 +70,13 @@ openfpga::Arch read_xml_openfpga_arch(const char* arch_file_name) {
     /* Build the internal link between configuration protocol and circuit library */
     link_config_protocol_to_circuit_library(openfpga_arch);
 
+    /* Now, we can know the default configurable memory model 
+     * Apply it to all the SRAM ports of circuit models
+     */
+    config_circuit_models_sram_port_to_default_sram_model(openfpga_arch.circuit_lib,
+                                                          openfpga_arch.config_protocol.memory_model());
+    
+
     /* Parse the connection block circuit definition */
     openfpga_arch.cb_switch2circuit = read_xml_cb_switch_circuit(xml_openfpga_arch, loc_data,
                                                                  openfpga_arch.circuit_lib);

From 13fadd0f910adf89bc99be90fcbfcce72260035b Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 12 Feb 2020 15:49:47 -0700
Subject: [PATCH 123/645] move compact routing hierarchy to build_fabric
 command

---
 ...ierarchy.cpp => openfpga_build_fabric.cpp} | 29 ++++++++++++++-----
 ...ng_hierarchy.h => openfpga_build_fabric.h} |  8 ++---
 openfpga/src/base/openfpga_setup_command.cpp  | 22 +++++++-------
 openfpga/test_script/s298_k6_frac.openfpga    | 10 ++++---
 4 files changed, 44 insertions(+), 25 deletions(-)
 rename openfpga/src/base/{compact_routing_hierarchy.cpp => openfpga_build_fabric.cpp} (77%)
 rename openfpga/src/base/{compact_routing_hierarchy.h => openfpga_build_fabric.h} (70%)

diff --git a/openfpga/src/base/compact_routing_hierarchy.cpp b/openfpga/src/base/openfpga_build_fabric.cpp
similarity index 77%
rename from openfpga/src/base/compact_routing_hierarchy.cpp
rename to openfpga/src/base/openfpga_build_fabric.cpp
index e520b5e3f..4671f3169 100644
--- a/openfpga/src/base/compact_routing_hierarchy.cpp
+++ b/openfpga/src/base/openfpga_build_fabric.cpp
@@ -7,7 +7,8 @@
 
 #include "device_rr_gsb.h"
 #include "device_rr_gsb_utils.h"
-#include "compact_routing_hierarchy.h"
+//#include "build_device_module.h"
+#include "openfpga_build_fabric.h"
 
 /* Include global variables of VPR */
 #include "globals.h"
@@ -19,17 +20,14 @@ namespace openfpga {
  * Identify the unique GSBs from the Device RR GSB arrays
  * This function should only be called after the GSB builder is done
  *******************************************************************/
-void compact_routing_hierarchy(OpenfpgaContext& openfpga_context,
-                               const Command& cmd, const CommandContext& cmd_context) { 
+static 
+void compress_routing_hierarchy(OpenfpgaContext& openfpga_context,
+                                const bool& verbose_output) {
   vtr::ScopedStartFinishTimer timer("Identify unique General Switch Blocks (GSBs)");
 
-  CommandOptionId opt_verbose = cmd.option("verbose");
-
   /* Build unique module lists */
   openfpga_context.mutable_device_rr_gsb().build_unique_module(g_vpr_ctx.device().rr_graph);
 
-  bool verbose_output = cmd_context.option_enable(cmd, opt_verbose);
-
   /* Report the stats */
   VTR_LOGV(verbose_output, 
            "Detected %lu unique X-direction connection blocks from a total of %d (compression rate=%d%)\n",
@@ -54,7 +52,24 @@ void compact_routing_hierarchy(OpenfpgaContext& openfpga_context,
            openfpga_context.device_rr_gsb().get_num_gsb_unique_module(),
            find_device_rr_gsb_num_gsb_modules(openfpga_context.device_rr_gsb()),
            100 * (openfpga_context.device_rr_gsb().get_num_gsb_unique_module() / find_device_rr_gsb_num_gsb_modules(openfpga_context.device_rr_gsb()) - 1));
+}
 
+/********************************************************************
+ * Build the module graph for FPGA device
+ *******************************************************************/
+void build_fabric(OpenfpgaContext& openfpga_context,
+                  const Command& cmd, const CommandContext& cmd_context) { 
+
+  CommandOptionId opt_compress_routing = cmd.option("compress_routing");
+  CommandOptionId opt_verbose = cmd.option("verbose");
+  
+  if (true == cmd_context.option_enable(cmd, opt_compress_routing)) {
+    compress_routing_hierarchy(openfpga_context, cmd_context.option_enable(cmd, opt_verbose));
+  }
+
+  /*
+  openfpga_context.mutable_module_graph() = build_device_module_graph();
+   */
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/base/compact_routing_hierarchy.h b/openfpga/src/base/openfpga_build_fabric.h
similarity index 70%
rename from openfpga/src/base/compact_routing_hierarchy.h
rename to openfpga/src/base/openfpga_build_fabric.h
index bd3eeefe2..44aa3632c 100644
--- a/openfpga/src/base/compact_routing_hierarchy.h
+++ b/openfpga/src/base/openfpga_build_fabric.h
@@ -1,5 +1,5 @@
-#ifndef COMPACT_ROUTING_HIERARCHY_H
-#define COMPACT_ROUTING_HIERARCHY_H
+#ifndef OPENFPGA_BUILD_FABRIC_H
+#define OPENFPGA_BUILD_FABRIC_H
 
 /********************************************************************
  * Include header files that are required by function declaration
@@ -15,8 +15,8 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-void compact_routing_hierarchy(OpenfpgaContext& openfpga_context,
-                               const Command& cmd, const CommandContext& cmd_context); 
+void build_fabric(OpenfpgaContext& openfpga_context,
+                  const Command& cmd, const CommandContext& cmd_context); 
 
 } /* end namespace openfpga */
 
diff --git a/openfpga/src/base/openfpga_setup_command.cpp b/openfpga/src/base/openfpga_setup_command.cpp
index e992875bd..1b6971167 100644
--- a/openfpga/src/base/openfpga_setup_command.cpp
+++ b/openfpga/src/base/openfpga_setup_command.cpp
@@ -8,7 +8,7 @@
 #include "openfpga_pb_pin_fixup.h"
 #include "openfpga_lut_truth_table_fixup.h"
 #include "check_netlist_naming_conflict.h"
-#include "compact_routing_hierarchy.h"
+#include "openfpga_build_fabric.h"
 #include "openfpga_setup_command.h"
 
 /* begin namespace openfpga */
@@ -121,20 +121,22 @@ void add_openfpga_setup_commands(openfpga::Shell<OpenfpgaContext>& shell) {
   shell.set_command_dependency(shell_cmd_lut_truth_table_fixup_id, cmd_dependency_lut_truth_table_fixup);
 
   /******************************** 
-   * Command 'compact_routing_hierarchy' 
+   * Command 'build_fabric' 
    */
-  Command shell_cmd_compact_routing_hierarchy("compact_routing_hierarchy");
+  Command shell_cmd_build_fabric("build_fabric");
   /* Add an option '--verbose' */
-  shell_cmd_compact_routing_hierarchy.add_option("verbose", false, "Show verbose outputs");
+  shell_cmd_build_fabric.add_option("compress_routing", false, "Compress the number of unique routing modules by identifying the unique GSBs");
+  shell_cmd_build_fabric.add_option("duplicate_grid_pin", false, "Duplicate the pins on the same side of a grid");
+  shell_cmd_build_fabric.add_option("verbose", false, "Show verbose outputs");
 
   /* Add command 'compact_routing_hierarchy' to the Shell */
-  ShellCommandId shell_cmd_compact_routing_hierarchy_id = shell.add_command(shell_cmd_compact_routing_hierarchy, "Identify the unique GSBs in the routing architecture so that the routing hierarchy of fabric can be compressed");
-  shell.set_command_class(shell_cmd_compact_routing_hierarchy_id, openfpga_setup_cmd_class);
-  shell.set_command_execute_function(shell_cmd_compact_routing_hierarchy_id, compact_routing_hierarchy);
-  /* The 'compact_routing_hierarchy' command should NOT be executed before 'link_openfpga_arch' */
-  std::vector<ShellCommandId> cmd_dependency_compact_routing_hierarchy;
+  ShellCommandId shell_cmd_build_fabric_id = shell.add_command(shell_cmd_build_fabric, "Build the FPGA fabric in a graph of modules");
+  shell.set_command_class(shell_cmd_build_fabric_id, openfpga_setup_cmd_class);
+  shell.set_command_execute_function(shell_cmd_build_fabric_id, build_fabric);
+  /* The 'build_fabric' command should NOT be executed before 'link_openfpga_arch' */
+  std::vector<ShellCommandId> cmd_dependency_build_fabric;
   cmd_dependency_lut_truth_table_fixup.push_back(shell_cmd_link_openfpga_arch_id);
-  shell.set_command_dependency(shell_cmd_compact_routing_hierarchy_id, cmd_dependency_compact_routing_hierarchy);
+  shell.set_command_dependency(shell_cmd_build_fabric_id, cmd_dependency_build_fabric);
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/test_script/s298_k6_frac.openfpga b/openfpga/test_script/s298_k6_frac.openfpga
index dd87c77df..9d4edcced 100644
--- a/openfpga/test_script/s298_k6_frac.openfpga
+++ b/openfpga/test_script/s298_k6_frac.openfpga
@@ -11,13 +11,15 @@ link_openfpga_arch
 check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
 
 # Apply fix-up to clustering nets based on routing results
-pb_pin_fixup --verbose
+pb_pin_fixup #--verbose
 
 # Apply fix-up to Look-Up Table truth tables based on packing results
-lut_truth_table_fixup --verbose
+lut_truth_table_fixup #--verbose
 
-# Compress the routing hierarchy
-compact_routing_hierarchy --verbose
+# Build the module graph 
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules 
+build_fabric --compress_routing --duplicate_grid_pin --verbose
 
 # Finish and exit OpenFPGA
 exit

From f11832b8cf8c8faa1fc8fd6f93244a92a57d12c6 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 12 Feb 2020 17:53:23 -0700
Subject: [PATCH 124/645] start integrating module graph builder

---
 openfpga/src/base/openfpga_build_fabric.cpp   |    9 +-
 openfpga/src/base/openfpga_context.h          |    6 +
 openfpga/src/base/openfpga_naming.cpp         | 1386 +++++++++++++++++
 openfpga/src/base/openfpga_naming.h           |  262 ++++
 openfpga/src/fabric/build_device_module.cpp   |  104 ++
 openfpga/src/fabric/build_device_module.h     |   22 +
 .../src/fabric/build_essential_modules.cpp    |  271 ++++
 openfpga/src/fabric/build_essential_modules.h |   30 +
 openfpga/src/fabric/module_manager.cpp        |  777 +++++++++
 openfpga/src/fabric/module_manager.h          |  238 +++
 openfpga/src/fabric/module_manager_fwd.h      |   35 +
 openfpga/src/utils/circuit_library_utils.cpp  |   16 +-
 openfpga/src/utils/circuit_library_utils.h    |    1 -
 openfpga/src/utils/memory_utils.cpp           |  385 +++++
 openfpga/src/utils/memory_utils.h             |   42 +
 openfpga/src/utils/module_manager_utils.cpp   | 1147 ++++++++++++++
 openfpga/src/utils/module_manager_utils.h     |  128 ++
 openfpga/src/utils/pb_type_utils.cpp          |   48 +
 openfpga/src/utils/pb_type_utils.h            |    5 +
 19 files changed, 4899 insertions(+), 13 deletions(-)
 create mode 100644 openfpga/src/base/openfpga_naming.cpp
 create mode 100644 openfpga/src/base/openfpga_naming.h
 create mode 100644 openfpga/src/fabric/build_device_module.cpp
 create mode 100644 openfpga/src/fabric/build_device_module.h
 create mode 100644 openfpga/src/fabric/build_essential_modules.cpp
 create mode 100644 openfpga/src/fabric/build_essential_modules.h
 create mode 100644 openfpga/src/fabric/module_manager.cpp
 create mode 100644 openfpga/src/fabric/module_manager.h
 create mode 100644 openfpga/src/fabric/module_manager_fwd.h
 create mode 100644 openfpga/src/utils/memory_utils.cpp
 create mode 100644 openfpga/src/utils/memory_utils.h
 create mode 100644 openfpga/src/utils/module_manager_utils.cpp
 create mode 100644 openfpga/src/utils/module_manager_utils.h

diff --git a/openfpga/src/base/openfpga_build_fabric.cpp b/openfpga/src/base/openfpga_build_fabric.cpp
index 4671f3169..f8fde4a31 100644
--- a/openfpga/src/base/openfpga_build_fabric.cpp
+++ b/openfpga/src/base/openfpga_build_fabric.cpp
@@ -7,7 +7,7 @@
 
 #include "device_rr_gsb.h"
 #include "device_rr_gsb_utils.h"
-//#include "build_device_module.h"
+#include "build_device_module.h"
 #include "openfpga_build_fabric.h"
 
 /* Include global variables of VPR */
@@ -67,9 +67,10 @@ void build_fabric(OpenfpgaContext& openfpga_context,
     compress_routing_hierarchy(openfpga_context, cmd_context.option_enable(cmd, opt_verbose));
   }
 
-  /*
-  openfpga_context.mutable_module_graph() = build_device_module_graph();
-   */
+  VTR_LOG("\n");
+
+  openfpga_context.mutable_module_graph() = build_device_module_graph(g_vpr_ctx.device(),
+                                                                      const_cast<const OpenfpgaContext&>(openfpga_context));
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_context.h b/openfpga/src/base/openfpga_context.h
index 4234de5b4..6f9ee0910 100644
--- a/openfpga/src/base/openfpga_context.h
+++ b/openfpga/src/base/openfpga_context.h
@@ -8,6 +8,7 @@
 #include "vpr_clustering_annotation.h"
 #include "vpr_routing_annotation.h"
 #include "mux_library.h"
+#include "module_manager.h"
 #include "device_rr_gsb.h"
 
 /********************************************************************
@@ -46,6 +47,7 @@ class OpenfpgaContext : public Context  {
     const openfpga::VprRoutingAnnotation& vpr_routing_annotation() const { return vpr_routing_annotation_; }
     const openfpga::DeviceRRGSB& device_rr_gsb() const { return device_rr_gsb_; }
     const openfpga::MuxLibrary& mux_lib() const { return mux_lib_; }
+    const openfpga::ModuleManager& module_graph() const { return module_graph_; }
   public:  /* Public mutators */
     openfpga::Arch& mutable_arch() { return arch_; }
     openfpga::VprDeviceAnnotation& mutable_vpr_device_annotation() { return vpr_device_annotation_; }
@@ -54,6 +56,7 @@ class OpenfpgaContext : public Context  {
     openfpga::VprRoutingAnnotation& mutable_vpr_routing_annotation() { return vpr_routing_annotation_; }
     openfpga::DeviceRRGSB& mutable_device_rr_gsb() { return device_rr_gsb_; }
     openfpga::MuxLibrary& mutable_mux_lib() { return mux_lib_; }
+    openfpga::ModuleManager& mutable_module_graph() { return module_graph_; }
   private: /* Internal data */
     /* Data structure to store information from read_openfpga_arch library */
     openfpga::Arch arch_;
@@ -75,6 +78,9 @@ class OpenfpgaContext : public Context  {
     
     /* Library of physical implmentation of routing multiplexers */
     openfpga::MuxLibrary mux_lib_;
+
+    /* Fabric module graph */
+    openfpga::ModuleManager module_graph_;
 };
 
 #endif
diff --git a/openfpga/src/base/openfpga_naming.cpp b/openfpga/src/base/openfpga_naming.cpp
new file mode 100644
index 000000000..19c58a1bc
--- /dev/null
+++ b/openfpga/src/base/openfpga_naming.cpp
@@ -0,0 +1,1386 @@
+/********************************************************************
+ * This file includes functions to generate module/port names for 
+ * Verilog and SPICE netlists 
+ *
+ * IMPORTANT: keep all the naming functions in this file to be 
+ * generic for both Verilog and SPICE generators 
+ ********************************************************************/
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+#include "openfpga_side_manager.h"
+#include "pb_type_utils.h"
+#include "circuit_library_utils.h"
+#include "openfpga_naming.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/************************************************
+ * Generate the node name for a multiplexing structure 
+ * Case 1 : If there is an intermediate buffer followed by,
+ *          the node name will be mux_l<node_level>_in_buf
+ * Case 1 : If there is NO intermediate buffer followed by,
+ *          the node name will be mux_l<node_level>_in
+ ***********************************************/
+std::string generate_mux_node_name(const size_t& node_level, 
+                                   const bool& add_buffer_postfix) {
+  /* Generate the basic node_name */
+  std::string node_name = "mux_l" + std::to_string(node_level) + "_in";
+
+  /* Add a postfix upon requests */
+  if (true == add_buffer_postfix)  {
+    /* '1' indicates that the location is needed */
+    node_name += "_buf";
+  }
+
+  return node_name;
+}
+
+ /************************************************
+ * Generate the instance name for a branch circuit in multiplexing structure 
+ * Case 1 : If there is an intermediate buffer followed by,
+ *          the node name will be mux_l<node_level>_in_buf
+ * Case 1 : If there is NO intermediate buffer followed by,
+ *          the node name will be mux_l<node_level>_in
+ ***********************************************/
+std::string generate_mux_branch_instance_name(const size_t& node_level, 
+                                              const size_t& node_index_at_level,
+                                              const bool& add_buffer_postfix) {
+  return std::string(generate_mux_node_name(node_level, add_buffer_postfix) + "_" + std::to_string(node_index_at_level) + "_");
+}
+
+/************************************************
+ * Generate the module name for a multiplexer in Verilog format
+ * Different circuit model requires different names: 
+ * 1. LUTs are named as <model_name>_mux
+ * 2. MUXes are named as <model_name>_size<num_inputs>
+ ***********************************************/
+std::string generate_mux_subckt_name(const CircuitLibrary& circuit_lib, 
+                                     const CircuitModelId& circuit_model, 
+                                     const size_t& mux_size, 
+                                     const std::string& postfix) {
+  std::string module_name = circuit_lib.model_name(circuit_model); 
+  /* Check the model type and give different names */
+  if (CIRCUIT_MODEL_MUX == circuit_lib.model_type(circuit_model)) {
+    module_name += "_size";
+    module_name += std::to_string(mux_size);
+  } else {  
+    VTR_ASSERT(CIRCUIT_MODEL_LUT == circuit_lib.model_type(circuit_model));
+    module_name += "_mux";
+  }
+
+  /* Add postfix if it is not empty */
+  if (!postfix.empty()) {
+    module_name += postfix;
+  }
+
+  return module_name;
+}
+
+/************************************************
+ * Generate the module name of a branch for a
+ * multiplexer in Verilog format
+ ***********************************************/
+std::string generate_mux_branch_subckt_name(const CircuitLibrary& circuit_lib, 
+                                            const CircuitModelId& circuit_model, 
+                                            const size_t& mux_size, 
+                                            const size_t& branch_mux_size, 
+                                            const std::string& postfix) {
+  /* If the tgate circuit model of this MUX is a MUX2 standard cell,
+   * the mux_subckt name will be the name of the standard cell
+   */
+  CircuitModelId subckt_model = circuit_lib.pass_gate_logic_model(circuit_model);
+  if (CIRCUIT_MODEL_GATE == circuit_lib.model_type(subckt_model)) {
+    VTR_ASSERT (CIRCUIT_MODEL_GATE_MUX2 == circuit_lib.gate_type(subckt_model));
+    return circuit_lib.model_name(subckt_model);
+  }
+  std::string branch_postfix = postfix + "_size" + std::to_string(branch_mux_size);
+
+  return generate_mux_subckt_name(circuit_lib, circuit_model, mux_size, branch_postfix);
+}
+
+/************************************************
+ * Generate the module name of a local decoder
+ * for multiplexer
+ ***********************************************/
+std::string generate_mux_local_decoder_subckt_name(const size_t& addr_size, 
+                                                   const size_t& data_size) {
+  std::string subckt_name = "decoder";
+  subckt_name += std::to_string(addr_size);
+  subckt_name += "to";
+  subckt_name += std::to_string(data_size);
+
+  return subckt_name;
+} 
+
+/************************************************
+ * Generate the module name of a routing track wire
+ ***********************************************/
+std::string generate_segment_wire_subckt_name(const std::string& wire_model_name, 
+                                              const size_t& segment_id) {
+  std::string segment_wire_subckt_name = wire_model_name + "_seg" + std::to_string(segment_id);
+
+  return segment_wire_subckt_name;
+} 
+
+/*********************************************************************
+ * Generate the port name for the mid-output of a routing track wire
+ * Mid-output is the output that is wired to a Connection block multiplexer.
+ *      
+ *                  |    CLB     |
+ *                  +------------+
+ *                        ^
+ *                        |
+ *           +------------------------------+
+ *           | Connection block multiplexer |
+ *           +------------------------------+
+ *                        ^
+ *                        |  mid-output         +--------------
+ *              +--------------------+          |
+ *    input --->| Routing track wire |--------->| Switch Block
+ *              +--------------------+  output  |
+ *                                              +--------------
+ *
+ ********************************************************************/
+std::string generate_segment_wire_mid_output_name(const std::string& regular_output_name) {
+  /* TODO: maybe have a postfix? */
+  return std::string("mid_" + regular_output_name);
+} 
+
+/*********************************************************************
+ * Generate the module name for a memory sub-circuit 
+ ********************************************************************/
+std::string generate_memory_module_name(const CircuitLibrary& circuit_lib,
+                                        const CircuitModelId& circuit_model, 
+                                        const CircuitModelId& sram_model, 
+                                        const std::string& postfix) {
+  return std::string( circuit_lib.model_name(circuit_model) + "_" + circuit_lib.model_name(sram_model) + postfix );
+}
+
+/*********************************************************************
+ * Generate the netlist name for a unique routing block 
+ * It could be 
+ * 1. Routing channel
+ * 2. Connection block
+ * 3. Switch block
+ * A unique block id should be given
+ *********************************************************************/
+std::string generate_routing_block_netlist_name(const std::string& prefix, 
+                                                const size_t& block_id,
+                                                const std::string& postfix) {
+  return std::string( prefix + std::to_string(block_id) + postfix );
+}
+
+/*********************************************************************
+ * Generate the netlist name for a routing block with a given coordinate
+ * It could be 
+ * 1. Routing channel
+ * 2. Connection block
+ * 3. Switch block
+ *********************************************************************/
+std::string generate_routing_block_netlist_name(const std::string& prefix, 
+                                                const vtr::Point<size_t>& coordinate,
+                                                const std::string& postfix) {
+  return std::string( prefix + std::to_string(coordinate.x()) + std::string("_") + std::to_string(coordinate.y()) + postfix );
+}
+
+/*********************************************************************
+ * Generate the netlist name for a connection block with a given coordinate
+ *********************************************************************/
+std::string generate_connection_block_netlist_name(const t_rr_type& cb_type, 
+                                                   const vtr::Point<size_t>& coordinate,
+                                                   const std::string& postfix) {
+  std::string prefix("cb");
+  switch (cb_type) {
+  case CHANX:
+    prefix += std::string("x_");
+    break;
+  case CHANY:
+    prefix += std::string("y_");
+    break;
+  default:
+    VTR_LOG_ERROR("Invalid type of connection block!\n");
+    exit(1);
+  }
+
+  return generate_routing_block_netlist_name(prefix, coordinate, postfix);
+}
+
+/*********************************************************************
+ * Generate the module name for a unique routing channel
+ *********************************************************************/
+std::string generate_routing_channel_module_name(const t_rr_type& chan_type, 
+                                                 const size_t& block_id) {
+  /* Channel must be either CHANX or CHANY */
+  VTR_ASSERT( (CHANX == chan_type) || (CHANY == chan_type) );
+
+  /* Create a map between chan_type and module_prefix */
+  std::map<t_rr_type, std::string> module_prefix_map;
+  /* TODO: use a constexpr string to replace the fixed name? */
+  module_prefix_map[CHANX] = std::string("chanx");
+  module_prefix_map[CHANY] = std::string("chany");
+
+  return std::string( module_prefix_map[chan_type] + std::string("_") + std::to_string(block_id) + std::string("_") );
+}
+
+/*********************************************************************
+ * Generate the module name for a routing channel with a given coordinate
+ *********************************************************************/
+std::string generate_routing_channel_module_name(const t_rr_type& chan_type, 
+                                                 const vtr::Point<size_t>& coordinate) {
+  /* Channel must be either CHANX or CHANY */
+  VTR_ASSERT( (CHANX == chan_type) || (CHANY == chan_type) );
+
+  /* Create a map between chan_type and module_prefix */
+  std::map<t_rr_type, std::string> module_prefix_map;
+  /* TODO: use a constexpr string to replace the fixed name? */
+  module_prefix_map[CHANX] = std::string("chanx");
+  module_prefix_map[CHANY] = std::string("chany");
+
+  return std::string( module_prefix_map[chan_type] + std::to_string(coordinate.x()) + std::string("_") + std::to_string(coordinate.y()) + std::string("_") );
+}
+
+/*********************************************************************
+ * Generate the port name for a routing track with a given coordinate
+ * and port direction
+ * This function is mainly used in naming routing tracks in the top-level netlists
+ * where we do need unique names (with coordinates) for each routing tracks
+ *********************************************************************/
+std::string generate_routing_track_port_name(const t_rr_type& chan_type, 
+                                             const vtr::Point<size_t>& coordinate,
+                                             const size_t& track_id,
+                                             const PORTS& port_direction) {
+  /* Channel must be either CHANX or CHANY */
+  VTR_ASSERT( (CHANX == chan_type) || (CHANY == chan_type) );
+
+  /* Create a map between chan_type and module_prefix */
+  std::map<t_rr_type, std::string> module_prefix_map;
+  /* TODO: use a constexpr string to replace the fixed name? */
+  module_prefix_map[CHANX] = std::string("chanx");
+  module_prefix_map[CHANY] = std::string("chany");
+
+  std::string port_name = module_prefix_map[chan_type]; 
+  port_name += std::string("_" + std::to_string(coordinate.x()) + std::string("__") + std::to_string(coordinate.y()) + std::string("__"));
+
+  switch (port_direction) {
+  case OUT_PORT:
+    port_name += std::string("out_"); 
+    break;
+  case IN_PORT:
+    port_name += std::string("in_"); 
+    break;
+  default:
+    VTR_LOG_ERROR("Invalid direction of chan_rr_node!\n");
+    exit(1);
+  }
+
+  /* Add the track id to the port name */
+  port_name += std::to_string(track_id) + std::string("_");
+
+  return port_name;
+}
+
+/*********************************************************************
+ * Generate the port name for a routing track in a Switch Block module
+ * This function is created to ease the PnR for each unique routing module
+ * So it is mainly used when creating non-top-level modules!
+ * Note that this function does not include any port coordinate
+ * Instead, we use the relative location of the pins in the context of routing modules
+ * so that each module can be instanciated across the fabric
+ * Even though, port direction must be provided!
+ *********************************************************************/
+std::string generate_sb_module_track_port_name(const t_rr_type& chan_type, 
+                                               const e_side& module_side,
+                                               const size_t& track_id,
+                                               const PORTS& port_direction) {
+  /* Channel must be either CHANX or CHANY */
+  VTR_ASSERT( (CHANX == chan_type) || (CHANY == chan_type) );
+
+  /* Create a map between chan_type and module_prefix */
+  std::map<t_rr_type, std::string> module_prefix_map;
+  /* TODO: use a constexpr string to replace the fixed name? */
+  module_prefix_map[CHANX] = std::string("chanx");
+  module_prefix_map[CHANY] = std::string("chany");
+
+  std::string port_name = module_prefix_map[chan_type]; 
+  port_name += std::string("_");
+
+  SideManager side_manager(module_side);
+  port_name += std::string(side_manager.to_string());
+  port_name += std::string("_");
+
+  switch (port_direction) {
+  case OUT_PORT:
+    port_name += std::string("out_"); 
+    break;
+  case IN_PORT:
+    port_name += std::string("in_"); 
+    break;
+  default:
+    VTR_LOG_ERROR("Invalid direction of chan_rr_node!\n");
+    exit(1);
+  }
+
+  /* Add the track id to the port name */
+  port_name += std::to_string(track_id) + std::string("_");
+
+  return port_name;
+}
+
+/*********************************************************************
+ * Generate the port name for a routing track in a Connection Block module
+ * This function is created to ease the PnR for each unique routing module
+ * So it is mainly used when creating non-top-level modules!
+ * Note that this function does not include any port coordinate
+ * Instead, we use the relative location of the pins in the context of routing modules
+ * so that each module can be instanciated across the fabric
+ * Even though, port direction must be provided!
+ *********************************************************************/
+std::string generate_cb_module_track_port_name(const t_rr_type& chan_type, 
+                                               const size_t& track_id,
+                                               const PORTS& port_direction) {
+  /* Channel must be either CHANX or CHANY */
+  VTR_ASSERT( (CHANX == chan_type) || (CHANY == chan_type) );
+
+  /* Create a map between chan_type and module_prefix */
+  std::map<t_rr_type, std::string> module_prefix_map;
+  /* TODO: use a constexpr string to replace the fixed name? */
+  module_prefix_map[CHANX] = std::string("chanx");
+  module_prefix_map[CHANY] = std::string("chany");
+
+  std::string port_name = module_prefix_map[chan_type]; 
+  port_name += std::string("_");
+
+  switch (port_direction) {
+  case OUT_PORT:
+    port_name += std::string("out_"); 
+    break;
+  case IN_PORT:
+    port_name += std::string("in_"); 
+    break;
+  default:
+    VTR_LOG_ERROR("Invalid direction of chan_rr_node!\n");
+    exit(1);
+  }
+
+  /* Add the track id to the port name */
+  port_name += std::to_string(track_id) + std::string("_");
+
+  return port_name;
+}
+
+/*********************************************************************
+ * Generate the middle output port name for a routing track 
+ * with a given coordinate
+ *********************************************************************/
+std::string generate_routing_track_middle_output_port_name(const t_rr_type& chan_type, 
+                                                           const vtr::Point<size_t>& coordinate,
+                                                           const size_t& track_id) {
+  /* Channel must be either CHANX or CHANY */
+  VTR_ASSERT( (CHANX == chan_type) || (CHANY == chan_type) );
+
+  /* Create a map between chan_type and module_prefix */
+  std::map<t_rr_type, std::string> module_prefix_map;
+  /* TODO: use a constexpr string to replace the fixed name? */
+  module_prefix_map[CHANX] = std::string("chanx");
+  module_prefix_map[CHANY] = std::string("chany");
+
+  std::string port_name = module_prefix_map[chan_type]; 
+  port_name += std::string("_" + std::to_string(coordinate.x()) + std::string("__") + std::to_string(coordinate.y()) + std::string("__"));
+
+  port_name += std::string("midout_"); 
+
+  /* Add the track id to the port name */
+  port_name += std::to_string(track_id) + std::string("_");
+
+  return port_name;
+}
+
+/*********************************************************************
+ * Generate the module name for a switch block with a given coordinate
+ *********************************************************************/
+std::string generate_switch_block_module_name(const vtr::Point<size_t>& coordinate) {
+  return std::string( "sb_" + std::to_string(coordinate.x()) + std::string("__") + std::to_string(coordinate.y()) + std::string("_") );
+}
+
+/*********************************************************************
+ * Generate the module name for a connection block with a given coordinate
+ *********************************************************************/
+std::string generate_connection_block_module_name(const t_rr_type& cb_type, 
+                                                  const vtr::Point<size_t>& coordinate) {
+  std::string prefix("cb");
+  switch (cb_type) {
+  case CHANX:
+    prefix += std::string("x_");
+    break;
+  case CHANY:
+    prefix += std::string("y_");
+    break;
+  default:
+    VTR_LOG_ERROR("Invalid type of connection block!\n");
+    exit(1);
+  }
+
+  return std::string( prefix + std::to_string(coordinate.x()) + std::string("__") + std::to_string(coordinate.y()) + std::string("_") );
+}
+
+/*********************************************************************
+ * Generate the port name for a grid in top-level netlists, i.e., full FPGA fabric
+ * This function will generate a full port name including coordinates
+ * so that each pin in top-level netlists is unique!
+ *********************************************************************/
+std::string generate_grid_port_name(const vtr::Point<size_t>& coordinate,
+                                    const size_t& width, 
+                                    const size_t& height, 
+                                    const e_side& side, 
+                                    const size_t& pin_id,
+                                    const bool& for_top_netlist) {
+  if (true == for_top_netlist) {
+    std::string port_name = std::string("grid_");
+    port_name += std::to_string(coordinate.x());
+    port_name += std::string("__");
+    port_name += std::to_string(coordinate.y());
+    port_name += std::string("__pin_");
+    port_name += std::to_string(height);
+    port_name += std::string("__");
+    port_name += std::to_string(size_t(side));
+    port_name += std::string("__");
+    port_name += std::to_string(pin_id);
+    port_name += std::string("_");
+    return port_name;
+  } 
+  /* For non-top netlist */
+  VTR_ASSERT( false == for_top_netlist );
+  SideManager side_manager(side);
+  std::string port_name = std::string(side_manager.to_string());
+  port_name += std::string("_width_");
+  port_name += std::to_string(width);
+  port_name += std::string("_height_");
+  port_name += std::to_string(height);
+  port_name += std::string("__pin_");
+  port_name += std::to_string(pin_id);
+  port_name += std::string("_");
+  return port_name;
+}
+
+/*********************************************************************
+ * Generate the port name for a grid with duplication 
+ * This function will generate two types of port names.
+ * One with a postfix of "upper"
+ * The other with a postfix of "lower"
+ *********************************************************************/
+std::string generate_grid_duplicated_port_name(const size_t& width,
+                                               const size_t& height, 
+                                               const e_side& side, 
+                                               const size_t& pin_id,
+                                               const bool& upper_port) {
+  /* For non-top netlist */
+  SideManager side_manager(side);
+  std::string port_name = std::string(side_manager.to_string());
+  port_name += std::string("_width_");
+  port_name += std::to_string(width);
+  port_name += std::string("_height_");
+  port_name += std::to_string(height);
+  port_name += std::string("_pin_");
+  port_name += std::to_string(pin_id);
+  port_name += std::string("_");
+
+  if (true == upper_port) {
+    port_name += std::string("upper");
+  } else {
+    VTR_ASSERT_SAFE(false == upper_port);
+    port_name += std::string("lower");
+  }  
+
+  return port_name;
+}
+
+
+/*********************************************************************
+ * Generate the port name for a grid in the context of a module
+ * To keep a short and simple name, this function will not 
+ * include any grid coorindate information!
+ *********************************************************************/
+std::string generate_grid_module_port_name(const size_t& pin_id) {
+  /* For non-top netlist */
+  std::string port_name = std::string("grid_");
+  port_name += std::string("pin_");
+  port_name += std::to_string(pin_id);
+  port_name += std::string("_");
+  return port_name;
+}
+
+/*********************************************************************
+ * Generate the port name for a Grid
+ * This is a wrapper function for generate_port_name()
+ * which can automatically decode the port name by the pin side and height
+ *********************************************************************/
+std::string generate_grid_side_port_name(const DeviceGrid& grids,
+                                         const vtr::Point<size_t>& coordinate,
+                                         const e_side& side, 
+                                         const size_t& pin_id) {
+  /* Output the pins on the side*/ 
+  size_t width = grids[coordinate.x()][coordinate.y()].type->pin_width_offset[pin_id];
+  size_t height = grids[coordinate.x()][coordinate.y()].type->pin_height_offset[pin_id];
+  if (true != grids[coordinate.x()][coordinate.y()].type->pinloc[width][height][side][pin_id]) {
+    SideManager side_manager(side);
+    VTR_LOG_ERROR("Fail to generate a grid pin (x=%lu, y=%lu, width=%lu, height=%lu, side=%s, index=%d)\n",
+                  coordinate.x(), coordinate.y(), width, height, side_manager.c_str(), pin_id);
+    exit(1);
+  } 
+  return generate_grid_port_name(coordinate, width, height, side, pin_id, true);
+}
+
+/*********************************************************************
+ * Generate the port name of a grid pin for a routing module,
+ * which could be a switch block or a connection block
+ * Note that to ensure unique grid port name in the context of a routing module,
+ * we need a prefix which denotes the relative location of the port in the routing module
+ *
+ * The prefix is created by considering the the grid coordinate 
+ * and switch block coordinate
+ * Detailed rules in conversion is as follows:
+ *
+ *             top_left         top_right
+ *             +------------------------+
+ *    left_top |                        | right_top
+ *             |      Switch Block      |
+ *             |         [x][y]         |
+ *             |                        |
+ *             |                        |
+ *  left_right |                        | right_bottom
+ *             +------------------------+
+ *              bottom_left  bottom_right
+ *
+ *  +--------------------------------------------------------
+ *  | Grid Coordinate | Pin side of grid | module side 
+ *  +--------------------------------------------------------
+ *  | [x][y+1]        | right            | top_left
+ *  +--------------------------------------------------------
+ *  | [x][y+1]        | bottom           | left_top
+ *  +--------------------------------------------------------
+ *  | [x+1][y+1]      | left             | top_right
+ *  +--------------------------------------------------------
+ *  | [x+1][y+1]      | bottom           | right_top
+ *  +--------------------------------------------------------
+ *  | [x][y]          | top              | left_right
+ *  +--------------------------------------------------------
+ *  | [x][y]          | right            | bottom_left
+ *  +--------------------------------------------------------
+ *  | [x+1][y]        | top              | right_bottom
+ *  +--------------------------------------------------------
+ *  | [x+1][y]        | left             | bottom_right
+ *  +--------------------------------------------------------
+ *
+ *********************************************************************/
+std::string generate_sb_module_grid_port_name(const e_side& sb_side,
+                                              const e_side& grid_side, 
+                                              const size_t& pin_id) {
+  SideManager sb_side_manager(sb_side);
+  SideManager grid_side_manager(grid_side);
+  /* Relative location is opposite to the side in grid context */
+  grid_side_manager.set_opposite();
+  std::string prefix = sb_side_manager.to_string() + std::string("_") + grid_side_manager.to_string();
+  return prefix + std::string("_") + generate_grid_module_port_name(pin_id);
+}
+
+/*********************************************************************
+ * Generate the port name of a grid pin for a routing module,
+ * which could be a switch block or a connection block
+ * Note that to ensure unique grid port name in the context of a routing module,
+ * we need a prefix which denotes the relative location of the port in the routing module
+ *********************************************************************/
+std::string generate_cb_module_grid_port_name(const e_side& cb_side, 
+                                              const size_t& pin_id) {
+  SideManager side_manager(cb_side);
+  std::string prefix = side_manager.to_string();
+  return prefix + std::string("_") + generate_grid_module_port_name(pin_id);
+}
+
+/*********************************************************************
+ * Generate the port name for a reserved sram port, i.e., BLB/WL port
+ * When port_type is BLB, a string denoting to the reserved BLB port is generated
+ * When port_type is WL, a string denoting to the reserved WL port is generated
+ *
+ * DO NOT put any SRAM organization check codes HERE!!!
+ * Even though the reserved BLB/WL ports are used by RRAM-based FPGA only, 
+ * try to keep this function does simple job. 
+ * Check codes should be added outside, when print the ports to files!!!  
+ *********************************************************************/
+std::string generate_reserved_sram_port_name(const e_circuit_model_port_type& port_type) {
+  VTR_ASSERT( (port_type == CIRCUIT_MODEL_PORT_BLB) || (port_type == CIRCUIT_MODEL_PORT_WL) ); 
+
+  if (CIRCUIT_MODEL_PORT_BLB == port_type) {
+    return std::string("reserved_blb");
+  }
+  return std::string("reserved_wl");
+}
+
+/*********************************************************************
+ * Generate the port name for a sram port, used for formal verification
+ * The port name is named after the cell name of SRAM in circuit library
+ *********************************************************************/
+std::string generate_formal_verification_sram_port_name(const CircuitLibrary& circuit_lib,
+                                                        const CircuitModelId& sram_model) {
+  std::string port_name = circuit_lib.model_name(sram_model) + std::string("_out_fm");
+
+  return port_name;
+}
+
+/*********************************************************************
+ * Generate the head port name of a configuration chain
+ * TODO: This could be replaced as a constexpr string
+ *********************************************************************/
+std::string generate_configuration_chain_head_name() {
+  return std::string("ccff_head");
+}
+
+/*********************************************************************
+ * Generate the tail port name of a configuration chain
+ * TODO: This could be replaced as a constexpr string
+ *********************************************************************/
+std::string generate_configuration_chain_tail_name() {
+  return std::string("ccff_tail");
+}
+
+/*********************************************************************
+ * Generate the memory output port name of a configuration chain
+ * TODO: This could be replaced as a constexpr string
+ *********************************************************************/
+std::string generate_configuration_chain_data_out_name() {
+  return std::string("mem_out");
+}
+
+/*********************************************************************
+ * Generate the inverted memory output port name of a configuration chain
+ * TODO: This could be replaced as a constexpr string
+ *********************************************************************/
+std::string generate_configuration_chain_inverted_data_out_name() {
+  return std::string("mem_outb");
+}
+
+/*********************************************************************
+ * Generate the addr port (input) for a local decoder of a multiplexer
+ * TODO: This could be replaced as a constexpr string
+ *********************************************************************/
+std::string generate_mux_local_decoder_addr_port_name() {
+  return std::string("addr");
+}
+
+/*********************************************************************
+ * Generate the data port (output) for a local decoder of a multiplexer
+ * TODO: This could be replaced as a constexpr string
+ *********************************************************************/
+std::string generate_mux_local_decoder_data_port_name() {
+  return std::string("data");
+}
+
+/*********************************************************************
+ * Generate the inverted data port (output) for a local decoder of a multiplexer
+ * TODO: This could be replaced as a constexpr string
+ *********************************************************************/
+std::string generate_mux_local_decoder_data_inv_port_name() {
+  return std::string("data_inv");
+}
+
+/*********************************************************************
+ * Generate the port name of a local configuration bus
+ * TODO: This could be replaced as a constexpr string
+ *********************************************************************/
+std::string generate_local_config_bus_port_name() {
+  return std::string("config_bus");
+}
+
+/*********************************************************************
+ * Generate the port name for a regular sram port which appears in the
+ * port list of a module
+ * The port name is named after the cell name of SRAM in circuit library
+ *********************************************************************/
+std::string generate_sram_port_name(const e_config_protocol_type& sram_orgz_type,
+                                    const e_circuit_model_port_type& port_type) {
+  std::string port_name;
+
+  switch (sram_orgz_type) {
+  case CONFIG_MEM_STANDALONE: {
+    /* Two types of ports are available:  
+     * (1) Regular output of a SRAM, enabled by port type of INPUT
+     * (2) Inverted output of a SRAM, enabled by port type of OUTPUT
+     */
+    if (CIRCUIT_MODEL_PORT_INPUT == port_type) {
+      port_name = std::string("mem_out"); 
+    } else {
+      VTR_ASSERT( CIRCUIT_MODEL_PORT_OUTPUT == port_type );
+      port_name = std::string("mem_outb"); 
+    }
+    break;
+  }
+  case CONFIG_MEM_SCAN_CHAIN:
+    /* Two types of ports are available:  
+     * (1) Head of a chain of Configuration-chain Flip-Flops (CCFFs), enabled by port type of INPUT
+     * (2) Tail of a chian of Configuration-chain Flip-flops (CCFFs), enabled by port type of OUTPUT
+     *           +------+    +------+    +------+
+     *  Head --->| CCFF |--->| CCFF |--->| CCFF |---> Tail
+     *           +------+    +------+    +------+
+     */
+    if (CIRCUIT_MODEL_PORT_INPUT == port_type) {
+      port_name = std::string("ccff_head"); 
+    } else {
+      VTR_ASSERT( CIRCUIT_MODEL_PORT_OUTPUT == port_type );
+      port_name = std::string("ccff_tail"); 
+    }
+    break;
+  case CONFIG_MEM_MEMORY_BANK:
+    /* Four types of ports are available:  
+     * (1) Bit Lines (BLs) of a SRAM cell, enabled by port type of BL
+     * (2) Word Lines (WLs) of a SRAM cell, enabled by port type of WL
+     * (3) Inverted Bit Lines (BLBs) of a SRAM cell, enabled by port type of BLB
+     * (4) Inverted Word Lines (WLBs) of a SRAM cell, enabled by port type of WLB
+     *
+     *           BL BLB WL WLB    BL BLB WL WLB    BL BLB WL WLB
+     *          [0] [0] [0] [0]  [1] [1] [1] [1]  [i] [i] [i] [i]
+     *            ^  ^  ^  ^       ^  ^  ^  ^       ^  ^  ^  ^
+     *            |  |  |  |       |  |  |  |       |  |  |  |
+     *           +----------+     +----------+     +----------+
+     *           |   SRAM   |     |   SRAM   | ... |   SRAM   |         
+     *           +----------+     +----------+     +----------+
+     */
+    if (CIRCUIT_MODEL_PORT_BL == port_type) {
+      port_name = std::string("bl"); 
+    } else if (CIRCUIT_MODEL_PORT_WL == port_type) {
+      port_name = std::string("wl"); 
+    } else if (CIRCUIT_MODEL_PORT_BLB == port_type) {
+      port_name = std::string("blb"); 
+    } else {
+      VTR_ASSERT( CIRCUIT_MODEL_PORT_WLB == port_type );
+      port_name = std::string("wlb"); 
+    }
+    break;
+  default:
+    VTR_LOG_ERROR("Invalid type of SRAM organization !\n");
+    exit(1);
+  }
+
+  return port_name;
+}
+
+/*********************************************************************
+ * Generate the port name for a regular sram port which is an internal
+ * wire of a module
+ * The port name is named after the cell name of SRAM in circuit library
+ *********************************************************************/
+std::string generate_sram_local_port_name(const CircuitLibrary& circuit_lib,
+                                          const CircuitModelId& sram_model,
+                                          const e_config_protocol_type& sram_orgz_type,
+                                          const e_circuit_model_port_type& port_type) {
+  std::string port_name = circuit_lib.model_name(sram_model) + std::string("_");
+
+  switch (sram_orgz_type) {
+  case CONFIG_MEM_STANDALONE: {
+    /* Two types of ports are available:  
+     * (1) Regular output of a SRAM, enabled by port type of INPUT
+     * (2) Inverted output of a SRAM, enabled by port type of OUTPUT
+     */
+    if (CIRCUIT_MODEL_PORT_INPUT == port_type) {
+      port_name += std::string("out_local_bus"); 
+    } else {
+      VTR_ASSERT( CIRCUIT_MODEL_PORT_OUTPUT == port_type );
+      port_name += std::string("outb_local_bus"); 
+    }
+    break;
+  }
+  case CONFIG_MEM_SCAN_CHAIN:
+    /* Three types of ports are available:  
+     * (1) Input of Configuration-chain Flip-Flops (CCFFs), enabled by port type of INPUT
+     * (2) Output of a chian of Configuration-chain Flip-flops (CCFFs), enabled by port type of OUTPUT
+     * (2) Inverted output of a chian of Configuration-chain Flip-flops (CCFFs), enabled by port type of INOUT
+     *           +------+    +------+    +------+
+     *  Head --->| CCFF |--->| CCFF |--->| CCFF |---> Tail
+     *           +------+    +------+    +------+
+     */
+    if (CIRCUIT_MODEL_PORT_INPUT == port_type) {
+      port_name += std::string("ccff_in_local_bus"); 
+    } else if ( CIRCUIT_MODEL_PORT_OUTPUT == port_type ) {
+      port_name += std::string("ccff_out_local_bus"); 
+    } else {
+      VTR_ASSERT( CIRCUIT_MODEL_PORT_INOUT == port_type );
+      port_name += std::string("ccff_outb_local_bus"); 
+    }
+    break;
+  case CONFIG_MEM_MEMORY_BANK: {
+    /* Two types of ports are available:  
+     * (1) Regular output of a SRAM, enabled by port type of INPUT
+     * (2) Inverted output of a SRAM, enabled by port type of OUTPUT
+     */
+    if (CIRCUIT_MODEL_PORT_INPUT == port_type) {
+      port_name += std::string("out_local_bus"); 
+    } else {
+      VTR_ASSERT( CIRCUIT_MODEL_PORT_OUTPUT == port_type );
+      port_name += std::string("outb_local_bus"); 
+    }
+    break;
+  }
+  default:
+    VTR_LOG_ERROR("Invalid type of SRAM organization !\n");
+    exit(1);
+  }
+
+  return port_name;
+}
+
+/*********************************************************************
+ * Generate the port name for the input bus of a routing multiplexer
+ * This is very useful in Verilog code generation where the inputs of 
+ * a routing multiplexer may come from different ports. 
+ * On the other side, the datapath input of a routing multiplexer
+ * is defined as a bus port. 
+ * Therefore, to interface, a bus port is required, and this function
+ * give a name to the bus port
+ * To keep the bus port name unique to each multiplexer we will instance,
+ * a mux_instance_id should be provided by user
+ *********************************************************************/
+std::string generate_mux_input_bus_port_name(const CircuitLibrary& circuit_lib,
+                                             const CircuitModelId& mux_model,
+                                             const size_t& mux_size, 
+                                             const size_t& mux_instance_id) {
+  std::string postfix = std::string("_") + std::to_string(mux_instance_id) + std::string("_inbus");
+  return generate_mux_subckt_name(circuit_lib, mux_model, mux_size, postfix);
+}
+
+/*********************************************************************
+ * Generate the name of a bus port which is wired to the configuration
+ * ports of a routing multiplexer
+ * This port is supposed to be used locally inside a Verilog/SPICE module 
+ *********************************************************************/
+std::string generate_mux_config_bus_port_name(const CircuitLibrary& circuit_lib,
+                                              const CircuitModelId& mux_model,
+                                              const size_t& mux_size, 
+                                              const size_t& bus_id,
+                                              const bool& inverted) {
+  std::string postfix = std::string("_configbus") + std::to_string(bus_id);
+  /* Add a bar to the end of the name for inverted bus ports */
+  if (true == inverted) {
+     postfix += std::string("_b");  
+  }
+
+  return generate_mux_subckt_name(circuit_lib, mux_model, mux_size, postfix);
+}
+
+/*********************************************************************
+ * Generate the port name for a SRAM port of a circuit
+ * This name is used for local wires that connecting SRAM ports
+ * of a circuit model inside a Verilog/SPICE module
+ * Note that the SRAM ports share the same naming
+ * convention regardless of their configuration style
+ *********************************************************************/
+std::string generate_local_sram_port_name(const std::string& port_prefix, 
+                                          const size_t& instance_id,
+                                          const e_circuit_model_port_type& port_type) {
+  std::string port_name = port_prefix + std::string("_") + std::to_string(instance_id) + std::string("_");
+
+  if (CIRCUIT_MODEL_PORT_INPUT == port_type) {
+    port_name += std::string("out"); 
+  } else {
+    VTR_ASSERT( CIRCUIT_MODEL_PORT_OUTPUT == port_type );
+    port_name += std::string("outb"); 
+  }
+
+  return port_name;
+}
+
+/*********************************************************************
+ * Generate the port name for a SRAM port of a routing multiplexer
+ * This name is used for local wires that connecting SRAM ports
+ * of routing multiplexers inside a Verilog/SPICE module
+ * Note that the SRAM ports of routing multiplexers share the same naming
+ * convention regardless of their configuration style
+ **********************************************************************/
+std::string generate_mux_sram_port_name(const CircuitLibrary& circuit_lib,
+                                        const CircuitModelId& mux_model,
+                                        const size_t& mux_size, 
+                                        const size_t& mux_instance_id,
+                                        const e_circuit_model_port_type& port_type) {
+  std::string prefix = generate_mux_subckt_name(circuit_lib, mux_model, mux_size, std::string());
+  return generate_local_sram_port_name(prefix, mux_instance_id, port_type);
+}
+
+/*********************************************************************
+ * Generate the prefix for naming a grid block netlist or a grid module
+ * This function will consider the io side and add it to the prefix 
+ **********************************************************************/
+std::string generate_grid_block_prefix(const std::string& prefix,
+                                       const e_side& io_side) {
+  std::string block_prefix(prefix);
+
+  if (NUM_SIDES != io_side) {
+    SideManager side_manager(io_side);
+    block_prefix += std::string(side_manager.to_string());
+    block_prefix += std::string("_");
+  }
+  
+  return block_prefix;
+}
+
+/*********************************************************************
+ * Generate the netlist name of a grid block
+ **********************************************************************/
+std::string generate_grid_block_netlist_name(const std::string& block_name,
+                                             const bool& is_block_io,
+                                             const e_side& io_side,
+                                             const std::string& postfix) {
+  /* Add the name of physical block */
+  std::string module_name(block_name);
+
+  if (true == is_block_io) {
+    SideManager side_manager(io_side);
+    module_name += std::string("_");
+    module_name += std::string(side_manager.to_string());
+  }
+
+  module_name += postfix;
+
+  return module_name;
+}
+
+/*********************************************************************
+ * Generate the module name of a grid block
+ **********************************************************************/
+std::string generate_grid_block_module_name(const std::string& prefix,
+                                            const std::string& block_name,
+                                            const bool& is_block_io,
+                                            const e_side& io_side) {
+  std::string module_name(prefix);
+
+  module_name += generate_grid_block_netlist_name(block_name, is_block_io, io_side, std::string());
+
+  return module_name;
+}
+
+/*********************************************************************
+ * Generate the instance name for a programmable routing multiplexer module 
+ * in a Switch Block
+ * To keep a unique name in each module and also consider unique routing modules,
+ * please do NOT include any coordinates in the naming!!!
+ * Consider only relative coordinate, such as side!
+ ********************************************************************/
+std::string generate_sb_mux_instance_name(const std::string& prefix,
+                                          const e_side& sb_side, 
+                                          const size_t& track_id, 
+                                          const std::string& postfix) {
+  std::string instance_name(prefix);
+  instance_name += SideManager(sb_side).to_string();
+  instance_name += std::string("_track_") + std::to_string(track_id);
+  instance_name += postfix;
+
+  return instance_name;
+}
+
+/*********************************************************************
+ * Generate the instance name for a configurable memory module in a Switch Block
+ * To keep a unique name in each module and also consider unique routing modules,
+ * please do NOT include any coordinates in the naming!!!
+ * Consider only relative coordinate, such as side!
+ ********************************************************************/
+std::string generate_sb_memory_instance_name(const std::string& prefix,
+                                             const e_side& sb_side, 
+                                             const size_t& track_id, 
+                                             const std::string& postfix) {
+  std::string instance_name(prefix);
+  instance_name += SideManager(sb_side).to_string();
+  instance_name += std::string("_track_") + std::to_string(track_id);
+  instance_name += postfix;
+
+  return instance_name;
+}
+
+/*********************************************************************
+ * Generate the instance name for a programmable routing multiplexer module 
+ * in a Connection Block
+ * To keep a unique name in each module and also consider unique routing modules,
+ * please do NOT include any coordinates in the naming!!!
+ * Consider only relative coordinate, such as side!
+ ********************************************************************/
+std::string generate_cb_mux_instance_name(const std::string& prefix,
+                                          const e_side& cb_side, 
+                                          const size_t& pin_id, 
+                                          const std::string& postfix) {
+  std::string instance_name(prefix);
+
+  instance_name += SideManager(cb_side).to_string();
+  instance_name += std::string("_ipin_") + std::to_string(pin_id);
+  instance_name += postfix;
+
+  return instance_name;
+}
+
+/*********************************************************************
+ * Generate the instance name for a configurable memory module in a Connection Block
+ * To keep a unique name in each module and also consider unique routing modules,
+ * please do NOT include any coordinates in the naming!!!
+ * Consider only relative coordinate, such as side!
+ ********************************************************************/
+std::string generate_cb_memory_instance_name(const std::string& prefix,
+                                             const e_side& cb_side, 
+                                             const size_t& pin_id, 
+                                             const std::string& postfix) {
+  std::string instance_name(prefix);
+
+  instance_name += SideManager(cb_side).to_string();
+  instance_name += std::string("_ipin_") + std::to_string(pin_id);
+  instance_name += postfix;
+
+  return instance_name;
+}
+
+/*********************************************************************
+ * Generate the instance name for a programmable routing multiplexer
+ * module in a physical block of a grid
+ * To guarentee a unique name for pb_graph pin,
+ * the instance name includes the index of parent node
+ * as well as the port name and pin index of this pin
+ *
+ * Exceptions: 
+ * For OUTPUT ports, due to hierarchical module organization, 
+ * their parent nodes will be uniquified
+ * So, we should not add any index here
+ ********************************************************************/
+std::string generate_pb_mux_instance_name(const std::string& prefix,
+                                          t_pb_graph_pin* pb_graph_pin, 
+                                          const std::string& postfix) {
+  std::string instance_name(prefix);
+  instance_name += std::string(pb_graph_pin->parent_node->pb_type->name);
+
+  if (IN_PORT == pb_graph_pin->port->type) {
+    instance_name += std::string("_");
+    instance_name += std::to_string(pb_graph_pin->parent_node->placement_index);
+  }
+
+  instance_name += std::string("_");
+  instance_name += std::string(pb_graph_pin->port->name);
+  instance_name += std::string("_");
+  instance_name += std::to_string(pb_graph_pin->pin_number);
+  instance_name += postfix;
+
+  return instance_name;
+}
+
+/*********************************************************************
+ * Generate the instance name for a configurable memory module in a 
+ * physical block of a grid
+ * To guarentee a unique name for pb_graph pin,
+ * the instance name includes the index of parent node
+ * as well as the port name and pin index of this pin
+ *
+ * Exceptions: 
+ * For OUTPUT ports, due to hierarchical module organization, 
+ * their parent nodes will be uniquified
+ * So, we should not add any index here
+ ********************************************************************/
+std::string generate_pb_memory_instance_name(const std::string& prefix,
+                                             t_pb_graph_pin* pb_graph_pin, 
+                                             const std::string& postfix) {
+  std::string instance_name(prefix);
+  instance_name += std::string(pb_graph_pin->parent_node->pb_type->name);
+
+  if (IN_PORT == pb_graph_pin->port->type) {
+    instance_name += std::string("_");
+    instance_name += std::to_string(pb_graph_pin->parent_node->placement_index);
+  }
+
+  instance_name += std::string("_");
+  instance_name += std::string(pb_graph_pin->port->name);
+  instance_name += std::string("_");
+  instance_name += std::to_string(pb_graph_pin->pin_number);
+  instance_name += postfix;
+
+  return instance_name;
+}
+
+/*********************************************************************
+ * Generate the instance name of a grid block
+ **********************************************************************/
+std::string generate_grid_block_instance_name(const std::string& prefix,
+                                              const std::string& block_name,
+                                              const bool& is_block_io,
+                                              const e_side& io_side,
+                                              const vtr::Point<size_t>& grid_coord) {
+  std::string module_name(prefix);
+
+  module_name += generate_grid_block_netlist_name(block_name, is_block_io, io_side, std::string());
+  module_name += std::string("_");
+  module_name += std::to_string(grid_coord.x());
+  module_name += std::string("_");
+  module_name += std::to_string(grid_coord.y());
+
+  return module_name;
+}
+
+/*********************************************************************
+ * Generate the module name of a physical block
+ * To ensure a unique name for each physical block inside the graph of complex blocks
+ * (pb_graph_nodes), this function trace backward to the top-level node
+ * in the graph and add the name of these parents 
+ * The final name will be in the following format:
+ * <top_physical_block_name>_<mode_name>_<parent_physical_block_name> ... <current_physical_block_name>
+ *
+ * TODO: to make sure the length of this name does not exceed the size of
+ * chars in a line of a file!!! 
+ **********************************************************************/
+std::string generate_physical_block_module_name(const std::string& prefix,
+                                                t_pb_type* physical_pb_type) {
+  std::string module_name(physical_pb_type->name);
+
+  t_pb_type* parent_pb_type = physical_pb_type;
+
+  /* Backward trace until we meet the top-level pb_type */
+  while (1) {
+    /* If there is no parent mode, this is a top-level pb_type, quit the loop here */
+    t_mode* parent_mode = parent_pb_type->parent_mode;
+    if (NULL == parent_mode) {
+      break;
+    }
+    
+    /* Add the mode name to the module name */
+    module_name = std::string("mode_") + std::string(parent_mode->name) + std::string("__") + module_name;
+
+    /* Backtrace to the upper level */
+    parent_pb_type = parent_mode->parent_pb_type;
+
+    /* If there is no parent pb_type, this is a top-level pb_type, quit the loop here */
+    if (NULL == parent_pb_type) {
+      break;
+    }
+
+    /* Add the current pb_type name to the module name */
+    module_name = std::string(parent_pb_type->name) + std::string("_") + module_name;
+  }
+
+  /* Exception for top-level pb_type: add an virtual mode name (same name as the pb_type) 
+   * This is to follow the naming convention as non top-level pb_types
+   * In addition, the name can be really unique, being different than the grid blocks
+   */
+  if (NULL == physical_pb_type->parent_mode) {
+    module_name += std::string("_mode_") + std::string(physical_pb_type->name) + std::string("_");
+  }
+
+  /* Add the prefix */
+  module_name = prefix + module_name;
+
+  return module_name;
+}
+
+
+/*********************************************************************
+ * Generate the instance name for physical block with a given index 
+ **********************************************************************/
+std::string generate_physical_block_instance_name(const std::string& prefix,
+                                                  t_pb_type* pb_type,
+                                                  const size_t& index) {
+  std::string instance_name = generate_physical_block_module_name(prefix, pb_type);
+  /* Add index to the name */
+  instance_name += std::string("_");
+  instance_name += std::to_string(index);
+
+  return instance_name;
+}
+
+/*********************************************************************
+ * This function is a wrapper for the function generate_physical_block_module_name()
+ * which can automatically decode the io_side and add a prefix 
+ **********************************************************************/
+std::string generate_grid_physical_block_module_name(const std::string& prefix, 
+                                                     t_pb_type* pb_type, 
+                                                     const e_side& border_side) {
+  std::string module_name_prefix = generate_grid_block_prefix(prefix, border_side);
+  return generate_physical_block_module_name(module_name_prefix, pb_type); 
+}
+
+/*********************************************************************
+ * Generate the instance name for physical block in Grid with a given index 
+ **********************************************************************/
+std::string generate_grid_physical_block_instance_name(const std::string& prefix, 
+                                                       t_pb_type* pb_type, 
+                                                       const e_side& border_side,
+                                                       const size_t& index) {
+  std::string module_name_prefix = generate_grid_block_prefix(prefix, border_side);
+  std::string instance_name = generate_physical_block_module_name(module_name_prefix, pb_type);
+  /* Add index to the name */
+  instance_name += std::string("_");
+  instance_name += std::to_string(index);
+
+  return instance_name;
+}
+
+/********************************************************************
+ * This function try to infer if a grid locates at the border of a 
+ * FPGA fabric, i.e., TOP/RIGHT/BOTTOM/LEFT sides
+ * 1. if this grid is on the border, it will return the side it locates,
+ * 2. if this grid is in the center, it will return an valid value NUM_SIDES 
+ *
+ * In this function, we assume that the corner grids are actually empty!
+ *
+ *   +-------+  +----------------------------+  +-------+
+ *   | EMPTY |  |      TOP side I/O          |  | EMPTY |
+ *   +-------+  +----------------------------+  +-------+
+ *
+ *   +-------+  +----------------------------+  +-------+
+ *   |       |  |                            |  |       |
+ *   |       |  |                            |  |       |
+ *   |       |  |                            |  |       |
+ *   | LEFT  |  |                            |  | RIGHT |
+ *   | side  |  |         Core grids         |  | side  |
+ *   | I/O   |  |                            |  |  I/O  |
+ *   |       |  |                            |  |       |
+ *   |       |  |                            |  |       |
+ *   |       |  |                            |  |       |
+ *   |       |  |                            |  |       |
+ *   +-------+  +----------------------------+  +-------+
+ *
+ *   +-------+  +----------------------------+  +-------+
+ *   | EMPTY |  |    BOTTOM side I/O         |  | EMPTY |
+ *   +-------+  +----------------------------+  +-------+
+ *******************************************************************/
+e_side find_grid_border_side(const vtr::Point<size_t>& device_size,
+                             const vtr::Point<size_t>& grid_coordinate) {
+  e_side grid_side = NUM_SIDES;
+
+  if (device_size.y() - 1 == grid_coordinate.y()) {
+    return TOP;
+  }
+  if (device_size.x() - 1 == grid_coordinate.x()) {
+    return RIGHT;
+  }
+  if (0 == grid_coordinate.y()) {
+    return BOTTOM;
+  }
+  if (0 == grid_coordinate.x()) {
+    return LEFT;
+  }
+
+  return grid_side;
+}
+
+/********************************************************************
+ * This function try to infer if a grid locates at the border of the
+ * core FPGA fabric, i.e., TOP/RIGHT/BOTTOM/LEFT sides
+ * 1. if this grid is on the border and it matches the given side, return true,
+ * 2. if this grid is in the center, return false 
+ *
+ * In this function, we assume that the corner grids are actually empty!
+ *
+ *   +-------+  +----------------------------+  +-------+
+ *   | EMPTY |  |      TOP side I/O          |  | EMPTY |
+ *   +-------+  +----------------------------+  +-------+
+ *
+ *   +-------+  +----------------------------+  +-------+
+ *   |       |  |          TOP               |  |       |
+ *   |       |  |----------------------------|  |       |
+ *   |       |  |      |              |      |  |       |
+ *   | LEFT  |  |      |              |      |  | RIGHT |
+ *   | side  |  | LEFT |  Core grids  | RIGHT|  | side  |
+ *   | I/O   |  |      |              |      |  |  I/O  |
+ *   |       |  |      |              |      |  |       |
+ *   |       |  |      |              |      |  |       |
+ *   |       |  |---------------------|      |  |       |
+ *   |       |  |          BOTTOM     |      |  |       |
+ *   +-------+  +----------------------------+  +-------+
+ *
+ *   +-------+  +----------------------------+  +-------+
+ *   | EMPTY |  |    BOTTOM side I/O         |  | EMPTY |
+ *   +-------+  +----------------------------+  +-------+
+ *
+ *   Note: for the blocks on the four corners of the core grids
+ *   Please refer to the figure above to infer its border_side
+ *******************************************************************/
+bool is_core_grid_on_given_border_side(const vtr::Point<size_t>& device_size,
+                                       const vtr::Point<size_t>& grid_coordinate,
+                                       const e_side& border_side) {
+
+  if ( (device_size.y() - 2 == grid_coordinate.y())
+    && (TOP == border_side) ) {
+    return true;
+  }
+  if ( (device_size.x() - 2 == grid_coordinate.x())
+    && (RIGHT == border_side) ) {
+    return true;
+  }
+  if ( (1 == grid_coordinate.y())
+    && (BOTTOM == border_side) ) {
+    return true;
+  }
+  if ( (1 == grid_coordinate.x())
+    && (LEFT == border_side) ) {
+    return true;
+  }
+
+  return false;
+}
+
+
+/*********************************************************************
+ * Generate the port name of a Verilog module describing a pb_type
+ * The name convention is 
+ * <pb_type_name>_<port_name>
+ ********************************************************************/
+std::string generate_pb_type_port_name(t_port* pb_type_port) {
+  std::string port_name;
+  
+  port_name = std::string(pb_type_port->parent_pb_type->name) + std::string("_") + std::string(pb_type_port->name);
+   
+  return port_name;
+}
+
+/*********************************************************************
+ * Generate the global I/O port name of a Verilog module
+ * This is mainly used by I/O circuit models
+ ********************************************************************/
+std::string generate_fpga_global_io_port_name(const std::string& prefix, 
+                                              const CircuitLibrary& circuit_lib,
+                                              const CircuitModelId& circuit_model) {
+  std::string port_name(prefix);
+  
+  port_name += circuit_lib.model_name(circuit_model);
+   
+  return port_name;
+}
+
+/*********************************************************************
+ * Generate the module name for the top-level module 
+ * The top-level module is actually the FPGA fabric
+ * We give a fixed name here, because it is independent from benchmark file
+ ********************************************************************/
+std::string generate_fpga_top_module_name() {
+  return std::string("fpga_top");
+}
+
+/*********************************************************************
+ * Generate the netlist name for the top-level module 
+ * The top-level module is actually the FPGA fabric
+ * We give a fixed name here, because it is independent from benchmark file
+ ********************************************************************/
+std::string generate_fpga_top_netlist_name(const std::string& postfix) {
+  return std::string("fpga_top" + postfix);
+}
+
+/*********************************************************************
+ * Generate the module name for a constant generator
+ * either VDD or GND, depending on the input argument
+ ********************************************************************/
+std::string generate_const_value_module_name(const size_t& const_val) {
+  if (0 == const_val) {
+    return std::string("const0");
+  }
+
+  VTR_ASSERT (1 == const_val); 
+  return std::string("const1");
+}
+
+/*********************************************************************
+ * Generate the output port name for a constant generator module
+ * either VDD or GND, depending on the input argument
+ ********************************************************************/
+std::string generate_const_value_module_output_port_name(const size_t& const_val) {
+  return generate_const_value_module_name(const_val);
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_naming.h b/openfpga/src/base/openfpga_naming.h
new file mode 100644
index 000000000..0c0c640ca
--- /dev/null
+++ b/openfpga/src/base/openfpga_naming.h
@@ -0,0 +1,262 @@
+/************************************************
+ * Header file for fpga_x2p_naming.cpp
+ * Include functions to generate module/port names
+ * for Verilog and SPICE netlists 
+ ***********************************************/
+
+#ifndef OPENFPGA_NAMING_H
+#define OPENFPGA_NAMING_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <string>
+
+#include "vtr_geometry.h"
+#include "circuit_library.h"
+#include "device_grid.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+std::string generate_mux_node_name(const size_t& node_level, 
+                                   const bool& add_buffer_postfix);
+
+std::string generate_mux_branch_instance_name(const size_t& node_level, 
+                                              const size_t& node_index_at_level,
+                                              const bool& add_buffer_postfix);
+
+std::string generate_mux_subckt_name(const CircuitLibrary& circuit_lib, 
+                                     const CircuitModelId& circuit_model, 
+                                     const size_t& mux_size, 
+                                     const std::string& posfix) ;
+
+std::string generate_mux_branch_subckt_name(const CircuitLibrary& circuit_lib, 
+                                            const CircuitModelId& circuit_model, 
+                                            const size_t& mux_size, 
+                                            const size_t& branch_mux_size, 
+                                            const std::string& posfix);
+
+std::string generate_mux_local_decoder_subckt_name(const size_t& addr_size, 
+                                                   const size_t& data_size); 
+
+std::string generate_segment_wire_subckt_name(const std::string& wire_model_name, 
+                                              const size_t& segment_id); 
+
+std::string generate_segment_wire_mid_output_name(const std::string& regular_output_name); 
+
+std::string generate_memory_module_name(const CircuitLibrary& circuit_lib,
+                                        const CircuitModelId& circuit_model, 
+                                        const CircuitModelId& sram_model, 
+                                        const std::string& postfix);
+
+std::string generate_routing_block_netlist_name(const std::string& prefix, 
+                                                const size_t& block_id,
+                                                const std::string& postfix);
+
+std::string generate_routing_block_netlist_name(const std::string& prefix, 
+                                                const vtr::Point<size_t>& block_id,
+                                                const std::string& postfix);
+
+std::string generate_connection_block_netlist_name(const t_rr_type& cb_type, 
+                                                   const vtr::Point<size_t>& coordinate,
+                                                   const std::string& postfix);
+
+std::string generate_routing_channel_module_name(const t_rr_type& chan_type, 
+                                                 const size_t& block_id);
+
+std::string generate_routing_channel_module_name(const t_rr_type& chan_type, 
+                                                 const vtr::Point<size_t>& coordinate);
+
+std::string generate_routing_track_port_name(const t_rr_type& chan_type, 
+                                             const vtr::Point<size_t>& coordinate,
+                                             const size_t& track_id,
+                                             const PORTS& port_direction);
+
+std::string generate_sb_module_track_port_name(const t_rr_type& chan_type, 
+                                               const e_side& module_side,
+                                               const size_t& track_id,
+                                               const PORTS& port_direction);
+
+std::string generate_cb_module_track_port_name(const t_rr_type& chan_type, 
+                                               const size_t& track_id,
+                                               const PORTS& port_direction);
+
+std::string generate_routing_track_middle_output_port_name(const t_rr_type& chan_type, 
+                                                           const vtr::Point<size_t>& coordinate,
+                                                           const size_t& track_id);
+
+std::string generate_switch_block_module_name(const vtr::Point<size_t>& coordinate);
+
+std::string generate_connection_block_module_name(const t_rr_type& cb_type, 
+                                                  const vtr::Point<size_t>& coordinate);
+
+std::string generate_sb_mux_instance_name(const std::string& prefix,
+                                          const e_side& sb_side, 
+                                          const size_t& track_id, 
+                                          const std::string& postfix);
+
+std::string generate_sb_memory_instance_name(const std::string& prefix,
+                                             const e_side& sb_side, 
+                                             const size_t& track_id, 
+                                             const std::string& postfix);
+
+std::string generate_cb_mux_instance_name(const std::string& prefix,
+                                          const e_side& cb_side, 
+                                          const size_t& pin_id, 
+                                          const std::string& postfix);
+
+std::string generate_cb_memory_instance_name(const std::string& prefix,
+                                             const e_side& cb_side, 
+                                             const size_t& pin_id, 
+                                             const std::string& postfix);
+
+std::string generate_pb_mux_instance_name(const std::string& prefix,
+                                          t_pb_graph_pin* pb_graph_pin, 
+                                          const std::string& postfix);
+
+std::string generate_pb_memory_instance_name(const std::string& prefix,
+                                             t_pb_graph_pin* pb_graph_pin, 
+                                             const std::string& postfix);
+
+std::string generate_grid_port_name(const vtr::Point<size_t>& coordinate,
+                                    const size_t& width, 
+                                    const size_t& height, 
+                                    const e_side& side, 
+                                    const size_t& pin_id,
+                                    const bool& for_top_netlist);
+
+std::string generate_grid_duplicated_port_name(const size_t& width,
+                                               const size_t& height, 
+                                               const e_side& side, 
+                                               const size_t& pin_id,
+                                               const bool& upper_port);
+
+std::string generate_grid_module_port_name(const size_t& pin_id);
+
+std::string generate_grid_side_port_name(const DeviceGrid& grids,
+                                         const vtr::Point<size_t>& coordinate,
+                                         const e_side& side, 
+                                         const size_t& pin_id);
+
+std::string generate_sb_module_grid_port_name(const e_side& sb_side,
+                                              const e_side& grid_side, 
+                                              const size_t& pin_id);
+
+std::string generate_cb_module_grid_port_name(const e_side& cb_side, 
+                                              const size_t& pin_id);
+
+std::string generate_reserved_sram_port_name(const e_circuit_model_port_type& port_type);
+
+std::string generate_formal_verification_sram_port_name(const CircuitLibrary& circuit_lib,
+                                                        const CircuitModelId& sram_model);
+
+std::string generate_configuration_chain_head_name();
+
+std::string generate_configuration_chain_tail_name();
+
+std::string generate_configuration_chain_data_out_name();
+
+std::string generate_configuration_chain_inverted_data_out_name();
+
+std::string generate_mux_local_decoder_addr_port_name();
+
+std::string generate_mux_local_decoder_data_port_name();
+
+std::string generate_mux_local_decoder_data_inv_port_name();
+
+std::string generate_local_config_bus_port_name();
+
+std::string generate_sram_port_name(const e_config_protocol_type& sram_orgz_type,
+                                    const e_circuit_model_port_type& port_type);
+
+std::string generate_sram_local_port_name(const CircuitLibrary& circuit_lib,
+                                          const CircuitModelId& sram_model,
+                                          const e_config_protocol_type& sram_orgz_type,
+                                          const e_circuit_model_port_type& port_type);
+
+std::string generate_mux_input_bus_port_name(const CircuitLibrary& circuit_lib,
+                                             const CircuitModelId& mux_model,
+                                             const size_t& mux_size, 
+                                             const size_t& mux_instance_id);
+
+std::string generate_mux_config_bus_port_name(const CircuitLibrary& circuit_lib,
+                                              const CircuitModelId& mux_model,
+                                              const size_t& mux_size, 
+                                              const size_t& bus_id,
+                                              const bool& inverted);
+
+std::string generate_local_sram_port_name(const std::string& port_prefix, 
+                                          const size_t& instance_id,
+                                          const e_circuit_model_port_type& port_type);
+
+std::string generate_mux_sram_port_name(const CircuitLibrary& circuit_lib,
+                                        const CircuitModelId& mux_model,
+                                        const size_t& mux_size, 
+                                        const size_t& mux_instance_id,
+                                        const e_circuit_model_port_type& port_type);
+
+std::string generate_grid_block_prefix(const std::string& prefix,
+                                       const e_side& io_side);
+
+std::string generate_grid_block_netlist_name(const std::string& block_name,
+                                             const bool& is_block_io,
+                                             const e_side& io_side,
+                                             const std::string& postfix);
+
+std::string generate_grid_block_module_name(const std::string& prefix,
+                                            const std::string& block_name,
+                                            const bool& is_block_io,
+                                            const e_side& io_side);
+
+std::string generate_grid_block_instance_name(const std::string& prefix,
+                                              const std::string& block_name,
+                                              const bool& is_block_io,
+                                              const e_side& io_side,
+                                              const vtr::Point<size_t>& grid_coord);
+
+std::string generate_physical_block_module_name(const std::string& prefix,
+                                                t_pb_type* physical_pb_type);
+
+std::string generate_physical_block_instance_name(const std::string& prefix,
+                                                  t_pb_type* pb_type,
+                                                  const size_t& index);
+
+std::string generate_grid_physical_block_module_name(const std::string& prefix,
+                                                     t_pb_type* pb_type,
+                                                     const e_side& border_side);
+
+std::string generate_grid_physical_block_instance_name(const std::string& prefix, 
+                                                       t_pb_type* pb_type, 
+                                                       const e_side& border_side,
+                                                       const size_t& index);
+
+
+e_side find_grid_border_side(const vtr::Point<size_t>& device_size,
+                             const vtr::Point<size_t>& grid_coordinate);
+
+bool is_core_grid_on_given_border_side(const vtr::Point<size_t>& device_size,
+                                       const vtr::Point<size_t>& grid_coordinate,
+                                       const e_side& border_side);
+
+std::string generate_pb_type_port_name(t_port* pb_type_port);
+
+std::string generate_fpga_global_io_port_name(const std::string& prefix, 
+                                              const CircuitLibrary& circuit_lib,
+                                              const CircuitModelId& circuit_model);
+
+std::string generate_fpga_top_module_name();
+
+std::string generate_fpga_top_netlist_name(const std::string& postfix);
+
+std::string generate_const_value_module_name(const size_t& const_val);
+
+std::string generate_const_value_module_output_port_name(const size_t& const_val);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/fabric/build_device_module.cpp b/openfpga/src/fabric/build_device_module.cpp
new file mode 100644
index 000000000..bf664048f
--- /dev/null
+++ b/openfpga/src/fabric/build_device_module.cpp
@@ -0,0 +1,104 @@
+/********************************************************************
+ * This file includes the main function to build module graphs
+ * for the FPGA fabric
+ *******************************************************************/
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+#include "vtr_time.h"
+
+#include "build_essential_modules.h"
+//#include "build_decoder_modules.h"
+//#include "build_mux_modules.h"
+//#include "build_lut_modules.h"
+//#include "build_wire_modules.h"
+//#include "build_memory_modules.h"
+//#include "build_grid_modules.h"
+//#include "build_routing_modules.h"
+//#include "build_top_module.h"
+#include "build_device_module.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * The main function to be called for building module graphs 
+ * for a FPGA fabric
+ *******************************************************************/
+ModuleManager build_device_module_graph(const DeviceContext& vpr_device_ctx,
+                                        const OpenfpgaContext& openfpga_ctx) {
+  vtr::ScopedStartFinishTimer timer("Build fabric module graph");
+
+  /* Module manager to be built */
+  ModuleManager module_manager;
+
+  CircuitModelId sram_model = openfpga_ctx.arch().config_protocol.memory_model();  
+  VTR_ASSERT(true == openfpga_ctx.arch().circuit_lib.valid_model_id(sram_model));
+
+  /* Add constant generator modules: VDD and GND */
+  build_constant_generator_modules(module_manager);
+
+  /* Register all the user-defined modules in the module manager
+   * This should be done prior to other steps in this function, 
+   * because they will be instanciated by other primitive modules
+   */
+  build_user_defined_modules(module_manager, openfpga_ctx.arch().circuit_lib);
+
+  /* Build elmentary modules */
+  build_essential_modules(module_manager, openfpga_ctx.arch().circuit_lib);
+
+  /* Build local encoders for multiplexers, this MUST be called before multiplexer building */
+  //build_mux_local_decoder_modules(module_manager, mux_lib, arch.spice->circuit_lib);
+
+  /* Build multiplexer modules */
+  //build_mux_modules(module_manager, mux_lib, arch.spice->circuit_lib);
+
+  /* Build LUT modules */
+  //build_lut_modules(module_manager, arch.spice->circuit_lib);
+
+  /* Build wire modules */
+  //build_wire_modules(module_manager, arch.spice->circuit_lib);
+
+  /* Build memory modules */
+  //build_memory_modules(module_manager, mux_lib, arch.spice->circuit_lib,
+  //                     arch.sram_inf.verilog_sram_inf_orgz->type);
+
+  /* Build grid and programmable block modules */
+  //build_grid_modules(module_manager, arch.spice->circuit_lib, mux_lib,  
+  //                   arch.sram_inf.verilog_sram_inf_orgz->type, sram_model,
+  //                   TRUE == vpr_setup.FPGA_SPICE_Opts.duplicate_grid_pin);
+
+  //if (TRUE == vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy) {
+  //  build_unique_routing_modules(module_manager, L_device_rr_gsb, arch.spice->circuit_lib, 
+  //                               arch.sram_inf.verilog_sram_inf_orgz->type, sram_model, 
+  //                               vpr_setup.RoutingArch, rr_switches);
+  //} else {
+  //  VTR_ASSERT(FALSE == vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy);
+  //  build_flatten_routing_modules(module_manager, L_device_rr_gsb, arch.spice->circuit_lib, 
+  //                                arch.sram_inf.verilog_sram_inf_orgz->type, sram_model, 
+  //                                vpr_setup.RoutingArch, rr_switches);
+  //}
+
+
+  /* Build FPGA fabric top-level module */
+  //build_top_module(module_manager, arch.spice->circuit_lib, 
+  //                 device_size, grids, L_device_rr_gsb, 
+  //                 clb2clb_directs, 
+  //                 arch.sram_inf.verilog_sram_inf_orgz->type, sram_model, 
+  //                 TRUE == vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy,
+  //                 TRUE == vpr_setup.FPGA_SPICE_Opts.duplicate_grid_pin);
+
+  /* Now a critical correction has to be done!
+   * In the module construction, we always use prefix of ports because they are binded
+   * to the ports in architecture description (logic blocks etc.)
+   * To interface with standard cell, we should
+   * rename the ports of primitive modules using lib_name instead of prefix
+   * (which have no children and are probably linked to a standard cell!)
+   */
+  //rename_primitive_module_port_names(module_manager, arch.spice->circuit_lib);
+
+  return module_manager;
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fabric/build_device_module.h b/openfpga/src/fabric/build_device_module.h
new file mode 100644
index 000000000..1e6bb2226
--- /dev/null
+++ b/openfpga/src/fabric/build_device_module.h
@@ -0,0 +1,22 @@
+#ifndef BUILD_DEVICE_MODULE_H
+#define BUILD_DEVICE_MODULE_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "vpr_context.h"
+#include "openfpga_context.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+ModuleManager build_device_module_graph(const DeviceContext& vpr_device_ctx,
+                                        const OpenfpgaContext& openfpga_ctx);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/fabric/build_essential_modules.cpp b/openfpga/src/fabric/build_essential_modules.cpp
new file mode 100644
index 000000000..07a00a788
--- /dev/null
+++ b/openfpga/src/fabric/build_essential_modules.cpp
@@ -0,0 +1,271 @@
+/********************************************************************
+ * This function includes the module builders for essential logic gates
+ * which are the leaf circuit model in the circuit library
+ *******************************************************************/
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+#include "vtr_time.h"
+
+#include "openfpga_naming.h"
+#include "module_manager_utils.h"
+#include "build_essential_modules.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/************************************************
+ * Build a module of inverter or buffer 
+ * or tapered buffer to a file 
+ ***********************************************/
+static 
+void build_invbuf_module(ModuleManager& module_manager, 
+                         const CircuitLibrary& circuit_lib,
+                         const CircuitModelId& circuit_model) {
+  /* Find the input port, output port and global inputs*/
+  std::vector<CircuitPortId> input_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true);
+  std::vector<CircuitPortId> output_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
+  std::vector<CircuitPortId> global_ports = circuit_lib.model_global_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true, true);
+
+  /* Make sure:
+   * There is only 1 input port and 1 output port, 
+   * each size of which is 1
+   */
+  VTR_ASSERT( (1 == input_ports.size()) && (1 == circuit_lib.port_size(input_ports[0])) );
+  VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) );
+
+  /* TODO: move the check codes to check_circuit_library.h */
+  /* If the circuit model is power-gated, we need to find at least one global config_enable signals */
+  if (true == circuit_lib.is_power_gated(circuit_model)) { 
+    /* Check all the ports we have are good for a power-gated circuit model */
+    size_t num_err = 0;
+    /* We need at least one global port */
+    if (0 == global_ports.size())  {
+      num_err++;
+    }
+    /* All the global ports should be config_enable */
+    for (const auto& port : global_ports) {
+      if (false == circuit_lib.port_is_config_enable(port)) {
+        num_err++;
+      }
+    }
+    /* Report errors if there are any */
+    if (0 < num_err) {
+      VTR_LOG_ERROR("Inverter/buffer circuit model '%s' is power-gated. At least one config-enable global port is required!\n",
+                 circuit_lib.model_name(circuit_model).c_str()); 
+      exit(1);
+    }
+  }
+
+  /* Create a Verilog Module based on the circuit model, and add to module manager */
+  ModuleId module_id = add_circuit_model_to_module_manager(module_manager, circuit_lib, circuit_model); 
+  VTR_ASSERT(true == module_manager.valid_module_id(module_id));
+}
+
+/************************************************
+ * Build a module of a pass-gate,
+ * either transmission-gate or pass-transistor
+ ***********************************************/
+static 
+void build_passgate_module(ModuleManager& module_manager, 
+                           const CircuitLibrary& circuit_lib,
+                           const CircuitModelId& circuit_model) {
+  /* Find the input port, output port*/
+  std::vector<CircuitPortId> input_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true);
+  std::vector<CircuitPortId> output_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
+  std::vector<CircuitPortId> global_ports = circuit_lib.model_global_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true, true);
+
+  switch (circuit_lib.pass_gate_logic_type(circuit_model)) {
+  case CIRCUIT_MODEL_PASS_GATE_TRANSMISSION:
+    /* Make sure:
+     * There is only 3 input port (in, sel, selb), 
+     * each size of which is 1
+     */
+    VTR_ASSERT( 3 == input_ports.size() );
+    for (const auto& input_port : input_ports) {
+      VTR_ASSERT(1 == circuit_lib.port_size(input_port));
+    }
+    break;
+  case CIRCUIT_MODEL_PASS_GATE_TRANSISTOR:
+    /* Make sure:
+     * There is only 2 input port (in, sel), 
+     * each size of which is 1
+     */
+    VTR_ASSERT( 2 == input_ports.size() );
+    for (const auto& input_port : input_ports) {
+      VTR_ASSERT(1 == circuit_lib.port_size(input_port));
+    }
+    break;
+  default:
+    VTR_LOG_ERROR("Invalid topology for circuit model '%s'!\n",
+                  circuit_lib.model_name(circuit_model).c_str());
+    exit(1);
+  }
+
+  /* Make sure:
+   * There is only 1 output port, 
+   * each size of which is 1
+   */
+  VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) );
+
+  /* Create a Verilog Module based on the circuit model, and add to module manager */
+  ModuleId module_id = add_circuit_model_to_module_manager(module_manager, circuit_lib, circuit_model); 
+  VTR_ASSERT(true == module_manager.valid_module_id(module_id));
+}
+
+/************************************************
+ * Build a module of a logic gate
+ * which are standard cells
+ * Supported gate types: 
+ * 1. N-input AND 
+ * 2. N-input OR
+ * 3. 2-input MUX
+ ***********************************************/
+static 
+void build_gate_module(ModuleManager& module_manager, 
+                       const CircuitLibrary& circuit_lib,
+                       const CircuitModelId& circuit_model) {
+  /* Find the input port, output port*/
+  std::vector<CircuitPortId> input_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true);
+  std::vector<CircuitPortId> output_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
+  std::vector<CircuitPortId> global_ports = circuit_lib.model_global_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true, true);
+
+  /* Make sure:
+   * There is only 1 output port, 
+   * each size of which is 1
+   */
+  VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) );
+
+  /* Create a Verilog Module based on the circuit model, and add to module manager */
+  ModuleId module_id = add_circuit_model_to_module_manager(module_manager, circuit_lib, circuit_model); 
+  VTR_ASSERT(true == module_manager.valid_module_id(module_id));
+}
+
+
+/************************************************
+ * Generate the modules for essential gates
+ * include inverters, buffers, transmission-gates,
+ * etc.
+ ***********************************************/
+void build_essential_modules(ModuleManager& module_manager, 
+                             const CircuitLibrary& circuit_lib) {
+  vtr::ScopedStartFinishTimer timer("Build essential (inverter/buffer/logic gate) modules...");
+
+  for (const auto& circuit_model : circuit_lib.models()) {
+    /* Add essential modules upon on demand: only when it is not yet in the module library */
+    ModuleId module = module_manager.find_module(circuit_lib.model_name(circuit_model));
+    if (true == module_manager.valid_module_id(module)) {
+      continue;
+    }
+
+    if (CIRCUIT_MODEL_INVBUF == circuit_lib.model_type(circuit_model)) {
+      build_invbuf_module(module_manager, circuit_lib, circuit_model);
+      continue;
+    }
+    if (CIRCUIT_MODEL_PASSGATE == circuit_lib.model_type(circuit_model)) {
+      build_passgate_module(module_manager, circuit_lib, circuit_model);
+      continue;
+    }
+    if (CIRCUIT_MODEL_GATE == circuit_lib.model_type(circuit_model)) {
+      build_gate_module(module_manager, circuit_lib, circuit_model);
+      continue;
+    }
+  }
+}
+
+/*********************************************************************
+ * Register all the user-defined modules in the module manager
+ * Walk through the circuit library and add user-defined circuit models
+ * to the module_manager
+ ********************************************************************/
+void build_user_defined_modules(ModuleManager& module_manager, 
+                                const CircuitLibrary& circuit_lib) {
+  vtr::ScopedStartFinishTimer timer("Build user-defined modules");
+
+  /* Iterate over Verilog modules */
+  for (const auto& model : circuit_lib.models()) {
+    /* We only care about user-defined models */
+    if ( (true == circuit_lib.model_verilog_netlist(model).empty())
+      && (true == circuit_lib.model_circuit_netlist(model).empty()) ) {
+      continue;
+    }
+    /* Skip Routing channel wire models because they need a different name. Do it later */
+    if (CIRCUIT_MODEL_CHAN_WIRE == circuit_lib.model_type(model)) {
+      continue;
+    }
+    /* Reach here, the model requires a user-defined Verilog netlist, 
+     * Register it in the module_manager  
+     */
+    add_circuit_model_to_module_manager(module_manager, circuit_lib, model);
+  }
+}
+
+/*********************************************************************
+ * This function will build a constant generator modules 
+ * and add it to the module manager
+ * It could be either
+ * 1. VDD or 2. GND
+ * Each module will have only one output port
+ ********************************************************************/
+static 
+void build_constant_generator_module(ModuleManager& module_manager, 
+                                     const size_t& const_value) {
+  ModuleId const_module = module_manager.add_module(generate_const_value_module_name(const_value));
+  /* Add one output port */
+  BasicPort const_output_port(generate_const_value_module_output_port_name(const_value), 1);
+  module_manager.add_port(const_module, const_output_port, ModuleManager::MODULE_OUTPUT_PORT);
+}
+
+/*********************************************************************
+ * This function will add two constant generator modules 
+ * to the module manager
+ * 1. VDD
+ * 2. GND
+ ********************************************************************/
+void build_constant_generator_modules(ModuleManager& module_manager) {
+  vtr::ScopedStartFinishTimer timer("Build constant generator modules");
+
+  /* VDD */
+  build_constant_generator_module(module_manager, 1);
+
+  /* GND */
+  build_constant_generator_module(module_manager, 0);
+}
+
+/*********************************************************************
+ * This function will rename the ports of primitive modules 
+ * using lib_name instead of prefix
+ * Primitive modules are defined as those modules in the module manager 
+ * which have user defined netlists
+ ********************************************************************/
+void rename_primitive_module_port_names(ModuleManager& module_manager, 
+                                        const CircuitLibrary& circuit_lib) {
+  for (const CircuitModelId& model : circuit_lib.models()) {
+    /* We only care about user-defined models */
+    if ( (true == circuit_lib.model_verilog_netlist(model).empty())
+      && (true == circuit_lib.model_circuit_netlist(model).empty()) ) {
+      continue;
+    }
+    /* Skip Routing channel wire models because they need a different name. Do it later */
+    if (CIRCUIT_MODEL_CHAN_WIRE == circuit_lib.model_type(model)) {
+      continue;
+    }
+    /* Find the module in module manager */
+    ModuleId module = module_manager.find_module(circuit_lib.model_name(model));
+    /* We must find one! */
+    VTR_ASSERT(true == module_manager.valid_module_id(module));
+
+    /* Rename all the ports to use lib_name! */
+    for (const CircuitPortId& model_port : circuit_lib.model_ports(model)) {
+      /* Find the module port in module manager. We used prefix when creating the ports */
+      ModulePortId module_port = module_manager.find_module_port(module, circuit_lib.port_prefix(model_port));
+      /* We must find one! */
+      VTR_ASSERT(true == module_manager.valid_module_port_id(module, module_port));
+      /* Name it with lib_name */
+      module_manager.set_module_port_name(module, module_port, circuit_lib.port_lib_name(model_port));
+    }
+  }
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fabric/build_essential_modules.h b/openfpga/src/fabric/build_essential_modules.h
new file mode 100644
index 000000000..e7d348bc6
--- /dev/null
+++ b/openfpga/src/fabric/build_essential_modules.h
@@ -0,0 +1,30 @@
+#ifndef BUILD_ESSENTIAL_MODULES_H
+#define BUILD_ESSENTIAL_MODULES_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "circuit_library.h"
+#include "module_manager.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void build_essential_modules(ModuleManager& module_manager, 
+                             const CircuitLibrary& circuit_lib);
+
+void build_user_defined_modules(ModuleManager& module_manager, 
+                                const CircuitLibrary& circuit_lib);
+
+void build_constant_generator_modules(ModuleManager& module_manager);
+
+void rename_primitive_module_port_names(ModuleManager& module_manager, 
+                                        const CircuitLibrary& circuit_lib);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/fabric/module_manager.cpp b/openfpga/src/fabric/module_manager.cpp
new file mode 100644
index 000000000..40f672194
--- /dev/null
+++ b/openfpga/src/fabric/module_manager.cpp
@@ -0,0 +1,777 @@
+/******************************************************************************
+ * Memember functions for data structure ModuleManager
+ ******************************************************************************/
+#include <string>
+#include <numeric>
+#include <algorithm>
+#include "vtr_assert.h"
+
+#include "circuit_library.h"
+#include "module_manager.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/******************************************************************************
+ * Public Constructors
+ ******************************************************************************/
+
+/**************************************************
+ * Public Accessors : Aggregates
+ *************************************************/
+/* Find all the modules */
+ModuleManager::module_range ModuleManager::modules() const {
+  return vtr::make_range(ids_.begin(), ids_.end());
+}
+
+/* Find all the ports belonging to a module */
+ModuleManager::module_port_range ModuleManager::module_ports(const ModuleId& module) const {
+  /* Validate the module_id */
+  VTR_ASSERT(valid_module_id(module));
+  return vtr::make_range(port_ids_[module].begin(), port_ids_[module].end());
+}
+
+/* Find all the nets belonging to a module */
+ModuleManager::module_net_range ModuleManager::module_nets(const ModuleId& module) const {
+  /* Validate the module_id */
+  VTR_ASSERT(valid_module_id(module));
+  return vtr::make_range(net_ids_[module].begin(), net_ids_[module].end());
+}
+
+/* Find all the child modules under a parent module */
+std::vector<ModuleId> ModuleManager::child_modules(const ModuleId& parent_module) const {
+  /* Validate the module_id */
+  VTR_ASSERT(valid_module_id(parent_module));
+  return children_[parent_module];
+}
+
+/* Find all the instances under a parent module */
+std::vector<size_t> ModuleManager::child_module_instances(const ModuleId& parent_module, const ModuleId& child_module) const {
+  /* Validate the module_id */
+  VTR_ASSERT(valid_module_id(parent_module));
+  /* Ensure that the child module is in the child list of parent module */
+  size_t child_index = children_[parent_module].size();
+  for (size_t i = 0; i < children_[parent_module].size(); ++i) {
+    if (child_module == children_[parent_module][i]) {
+      child_index = i;
+      break;
+    } 
+  }
+  VTR_ASSERT(child_index != children_[parent_module].size());
+  
+  /* Create a vector, with sequentially increasing numbers */
+  std::vector<size_t> instance_range(num_child_instances_[parent_module][child_index], 0);
+  std::iota(instance_range.begin(), instance_range.end(), 0);
+
+  return instance_range;
+}
+
+/* Find all the configurable child modules under a parent module */
+std::vector<ModuleId> ModuleManager::configurable_children(const ModuleId& parent_module) const {
+  /* Validate the module_id */
+  VTR_ASSERT(valid_module_id(parent_module));
+
+  return configurable_children_[parent_module];
+}
+
+/* Find all the instances of configurable child modules under a parent module */
+std::vector<size_t> ModuleManager::configurable_child_instances(const ModuleId& parent_module) const {
+  /* Validate the module_id */
+  VTR_ASSERT(valid_module_id(parent_module));
+
+  return configurable_child_instances_[parent_module];
+}
+
+/* Find the source ids of modules */
+ModuleManager::module_net_src_range ModuleManager::module_net_sources(const ModuleId& module, const ModuleNetId& net) const {
+  /* Validate the module_id */
+  VTR_ASSERT(valid_module_net_id(module, net));
+  return vtr::make_range(net_src_ids_[module][net].begin(), net_src_ids_[module][net].end());
+}
+
+/* Find the sink ids of modules */
+ModuleManager::module_net_sink_range ModuleManager::module_net_sinks(const ModuleId& module, const ModuleNetId& net) const {
+  /* Validate the module_id */
+  VTR_ASSERT(valid_module_net_id(module, net));
+  return vtr::make_range(net_sink_ids_[module][net].begin(), net_sink_ids_[module][net].end());
+}
+
+/******************************************************************************
+ * Public Accessors
+ ******************************************************************************/
+/* Return number of modules */
+size_t ModuleManager::num_modules() const {
+  return ids_.size();
+}
+
+/* Return number of net of a module */
+size_t ModuleManager::num_nets(const ModuleId& module) const {
+  /* Validate the module_id */
+  VTR_ASSERT(valid_module_id(module));
+  return net_ids_[module].size();
+}
+
+/* Find the name of a module */
+std::string ModuleManager::module_name(const ModuleId& module_id) const {
+  /* Validate the module_id */
+  VTR_ASSERT(valid_module_id(module_id));
+  return names_[module_id];
+}
+
+/* Get the string of a module port type */
+std::string ModuleManager::module_port_type_str(const enum e_module_port_type& port_type) const {
+  std::array<const char*, NUM_MODULE_PORT_TYPES> MODULE_PORT_TYPE_STRING = {{"GLOBAL PORTS", "GPIO PORTS", "INOUT PORTS", "INPUT PORTS", "OUTPUT PORTS", "CLOCK PORTS"}};
+  return MODULE_PORT_TYPE_STRING[port_type];
+}
+
+/* Find a list of ports of a module by a given types */
+std::vector<BasicPort> ModuleManager::module_ports_by_type(const ModuleId& module_id, const enum e_module_port_type& port_type) const {
+  /* Validate the module_id */
+  VTR_ASSERT(valid_module_id(module_id));
+
+  std::vector<BasicPort> ports;
+  for (const auto& port : port_ids_[module_id]) {
+    /* Skip unmatched ports */
+    if (port_type != port_types_[module_id][port]) {
+      continue;
+    }
+    ports.push_back(ports_[module_id][port]);
+  }
+
+  return ports;
+}
+
+/* Find a list of port ids of a module by a given types */
+std::vector<ModulePortId> ModuleManager::module_port_ids_by_type(const ModuleId& module_id, const enum e_module_port_type& port_type) const {
+  /* Validate the module_id */
+  VTR_ASSERT(valid_module_id(module_id));
+
+  std::vector<ModulePortId> port_ids;
+  for (const auto& port : port_ids_[module_id]) {
+    /* Skip unmatched ports */
+    if (port_type != port_types_[module_id][port]) {
+      continue;
+    }
+    port_ids.push_back(port_ids_[module_id][port]);
+  }
+
+  return port_ids;
+}
+
+
+/* Find a port of a module by a given name */
+ModulePortId ModuleManager::find_module_port(const ModuleId& module_id, const std::string& port_name) const {
+  /* Validate the module id */
+  VTR_ASSERT(valid_module_id(module_id));
+
+  /* Iterate over the ports of the module */
+  for (const auto& port : port_ids_[module_id]) {
+    if (0 == port_name.compare(ports_[module_id][port].get_name())) {
+      /* Find it, return the id */
+      return port; 
+    }
+  }
+  /* Not found, return an invalid id */
+  return ModulePortId::INVALID();
+}
+
+/* Find the Port information with a given port id */
+BasicPort ModuleManager::module_port(const ModuleId& module_id, const ModulePortId& port_id) const {
+  /* Validate the module and port id */
+  VTR_ASSERT(valid_module_port_id(module_id, port_id));
+  return ports_[module_id][port_id]; 
+}
+
+/* Find the module id by a given name, return invalid if not found */
+ModuleId ModuleManager::find_module(const std::string& name) const {
+  if (name_id_map_.find(name) != name_id_map_.end()) {
+    /* Find it, return the id */
+    return name_id_map_.at(name); 
+  }
+  /* Not found, return an invalid id */
+  return ModuleId::INVALID();
+}
+
+/* Find the number of instances of a child module in the parent module */
+size_t ModuleManager::num_instance(const ModuleId& parent_module, const ModuleId& child_module) const {
+  size_t child_index = find_child_module_index_in_parent_module(parent_module, child_module);
+  if (size_t(-1) == child_index) {
+    /* Not found, return a zero */
+    return 0;
+  }
+
+  return num_child_instances_[parent_module][child_index]; 
+}
+
+/* Find the instance name of a child module */
+std::string ModuleManager::instance_name(const ModuleId& parent_module, const ModuleId& child_module,
+                                         const size_t& instance_id) const {
+  /* Validate the id of both parent and child modules */
+  VTR_ASSERT ( valid_module_id(parent_module) );
+  VTR_ASSERT ( valid_module_id(child_module) );
+
+  /* Find the index of child module in the child list of parent module */
+  size_t child_index = find_child_module_index_in_parent_module(parent_module, child_module);
+  VTR_ASSERT (child_index < children_[parent_module].size());
+  /* Ensure that instance id is valid */
+  VTR_ASSERT (instance_id < num_instance(parent_module, child_module));
+  return child_instance_names_[parent_module][child_index][instance_id];
+}
+
+/* Find the instance id of a given instance name */
+size_t ModuleManager::instance_id(const ModuleId& parent_module, const ModuleId& child_module,
+                                  const std::string& instance_name) const {
+  /* Validate the id of both parent and child modules */
+  VTR_ASSERT ( valid_module_id(parent_module) );
+  VTR_ASSERT ( valid_module_id(child_module) );
+
+  /* Find the index of child module in the child list of parent module */
+  size_t child_index = find_child_module_index_in_parent_module(parent_module, child_module);
+  VTR_ASSERT (child_index < children_[parent_module].size());
+
+  /* Search the instance name list and try to find a match */
+  for (size_t name_id = 0; name_id < child_instance_names_[parent_module][child_index].size(); ++name_id) {
+    const std::string& name = child_instance_names_[parent_module][child_index][name_id];
+    if (0 == name.compare(instance_name)) {
+      return name_id;
+    }
+  }
+  
+  /* Not found, return an invalid name */
+  return size_t(-1);
+}
+
+/* Find if a port is a wire connection */
+bool ModuleManager::port_is_wire(const ModuleId& module, const ModulePortId& port) const {
+  /* validate both module id and port id*/
+  VTR_ASSERT(valid_module_port_id(module, port));
+  return port_is_wire_[module][port];
+}
+
+/* Find if a port is register */
+bool ModuleManager::port_is_register(const ModuleId& module, const ModulePortId& port) const {
+  /* validate both module id and port id*/
+  VTR_ASSERT(valid_module_port_id(module, port));
+  return port_is_register_[module][port];
+}
+
+/* Return the pre-processing flag of a port */
+std::string ModuleManager::port_preproc_flag(const ModuleId& module, const ModulePortId& port) const {
+  /* validate both module id and port id*/
+  VTR_ASSERT(valid_module_port_id(module, port));
+  return port_preproc_flags_[module][port];
+}
+
+/* Find a net from an instance of a module */
+ModuleNetId ModuleManager::module_instance_port_net(const ModuleId& parent_module, 
+                                                    const ModuleId& child_module, const size_t& child_instance,
+                                                    const ModulePortId& child_port, const size_t& child_pin) const {
+  /* Validate parent_module */
+  VTR_ASSERT(valid_module_id(parent_module));
+  
+  /* Validate child_module */
+  VTR_ASSERT(valid_module_id(child_module));
+
+  /* Validate instance id */
+  if (child_module == parent_module) {
+    /* Assume a default instance id as zero */
+    VTR_ASSERT(0 == child_instance);
+  } else {
+    VTR_ASSERT(child_instance < num_instance(parent_module, child_module));
+  }
+
+  /* Validate child_port */
+  VTR_ASSERT(valid_module_port_id(child_module, child_port));
+
+  /* Validate child_pin */
+  VTR_ASSERT(child_pin < module_port(child_module, child_port).get_width());
+  
+  return net_lookup_[parent_module][child_module][child_instance][child_port][child_pin];
+}
+
+/* Find the name of net */
+std::string ModuleManager::net_name(const ModuleId& module, const ModuleNetId& net) const {
+  /* Validate module net */
+  VTR_ASSERT(valid_module_net_id(module, net));
+
+  return net_names_[module][net];
+}
+
+/* Find the source modules of a net */
+vtr::vector<ModuleNetSrcId, ModuleId> ModuleManager::net_source_modules(const ModuleId& module, const ModuleNetId& net) const {
+  /* Validate module net */
+  VTR_ASSERT(valid_module_net_id(module, net));
+
+  return net_src_module_ids_[module][net];
+}
+
+/* Find the ids of source instances of a net */
+vtr::vector<ModuleNetSrcId, size_t> ModuleManager::net_source_instances(const ModuleId& module, const ModuleNetId& net) const {
+  /* Validate module net */
+  VTR_ASSERT(valid_module_net_id(module, net));
+
+  return net_src_instance_ids_[module][net];
+}
+
+/* Find the source ports of a net */
+vtr::vector<ModuleNetSrcId, ModulePortId> ModuleManager::net_source_ports(const ModuleId& module, const ModuleNetId& net) const {
+  /* Validate module net */
+  VTR_ASSERT(valid_module_net_id(module, net));
+
+  return net_src_port_ids_[module][net];
+}
+
+/* Find the source pin indices of a net */
+vtr::vector<ModuleNetSrcId, size_t> ModuleManager::net_source_pins(const ModuleId& module, const ModuleNetId& net) const {
+  /* Validate module net */
+  VTR_ASSERT(valid_module_net_id(module, net));
+
+  return net_src_pin_ids_[module][net];
+}
+
+/* Identify if a pin of a port in a module already exists in the net source list*/
+bool ModuleManager::net_source_exist(const ModuleId& module, const ModuleNetId& net,
+                                     const ModuleId& src_module, const size_t& instance_id,
+                                     const ModulePortId& src_port, const size_t& src_pin) {
+  /* Validate module net */
+  VTR_ASSERT(valid_module_net_id(module, net));
+
+  /* Iterate over each source of the net.
+   * If a net source has the same src_module, instance_id, src_port and src_pin,
+   * we can say that the source has already been added to this net!
+   */
+  for (const ModuleNetSrcId& net_src : module_net_sources(module, net)) {
+    if ( (src_module == net_source_modules(module, net)[net_src]) 
+      && (instance_id == net_source_instances(module, net)[net_src])   
+      && (src_port == net_source_ports(module, net)[net_src])   
+      && (src_pin == net_source_pins(module, net)[net_src]) ) {
+      return true;
+    }
+  }
+
+  /* Reach here, it means nothing has been found. Return false */
+  return false;
+}
+
+/* Find the sink modules of a net */
+vtr::vector<ModuleNetSinkId, ModuleId> ModuleManager::net_sink_modules(const ModuleId& module, const ModuleNetId& net) const {
+  /* Validate module net */
+  VTR_ASSERT(valid_module_net_id(module, net));
+
+  return net_sink_module_ids_[module][net];
+}
+
+/* Find the ids of sink instances of a net */
+vtr::vector<ModuleNetSinkId, size_t> ModuleManager::net_sink_instances(const ModuleId& module, const ModuleNetId& net) const {
+  /* Validate module net */
+  VTR_ASSERT(valid_module_net_id(module, net));
+
+  return net_sink_instance_ids_[module][net];
+}
+
+/* Find the sink ports of a net */
+vtr::vector<ModuleNetSinkId, ModulePortId> ModuleManager::net_sink_ports(const ModuleId& module, const ModuleNetId& net) const {
+  /* Validate module net */
+  VTR_ASSERT(valid_module_net_id(module, net));
+
+  return net_sink_port_ids_[module][net];
+}
+
+/* Find the sink pin indices of a net */
+vtr::vector<ModuleNetSinkId, size_t> ModuleManager::net_sink_pins(const ModuleId& module, const ModuleNetId& net) const {
+  /* Validate module net */
+  VTR_ASSERT(valid_module_net_id(module, net));
+
+  return net_sink_pin_ids_[module][net];
+}
+
+/* Identify if a pin of a port in a module already exists in the net sink list*/
+bool ModuleManager::net_sink_exist(const ModuleId& module, const ModuleNetId& net,
+                                     const ModuleId& sink_module, const size_t& instance_id,
+                                     const ModulePortId& sink_port, const size_t& sink_pin) {
+  /* Validate module net */
+  VTR_ASSERT(valid_module_net_id(module, net));
+
+  /* Iterate over each sink of the net.
+   * If a net sink has the same sink_module, instance_id, sink_port and sink_pin,
+   * we can say that the sink has already been added to this net!
+   */
+  for (const ModuleNetSinkId& net_sink : module_net_sinks(module, net)) {
+    if ( (sink_module == net_sink_modules(module, net)[net_sink]) 
+      && (instance_id == net_sink_instances(module, net)[net_sink])   
+      && (sink_port == net_sink_ports(module, net)[net_sink])   
+      && (sink_pin == net_sink_pins(module, net)[net_sink]) ) {
+      return true;
+    }
+  }
+
+  /* Reach here, it means nothing has been found. Return false */
+  return false;
+}
+
+/******************************************************************************
+ * Private Accessors
+ ******************************************************************************/
+size_t ModuleManager::find_child_module_index_in_parent_module(const ModuleId& parent_module, const ModuleId& child_module) const {
+  /* validate both module ids */
+  VTR_ASSERT(valid_module_id(parent_module));
+  VTR_ASSERT(valid_module_id(child_module));
+  /* Try to find the child_module in the children list of parent_module*/
+  for (size_t i = 0; i < children_[parent_module].size(); ++i) {
+    if (child_module == children_[parent_module][i]) {
+      /* Found, return the number of instances */
+      return i; 
+    }
+  }
+  /* Not found: return an valid value */
+  return size_t(-1);
+}
+
+/******************************************************************************
+ * Public Mutators
+ ******************************************************************************/
+/* Add a module */
+ModuleId ModuleManager::add_module(const std::string& name) {
+  /* Find if the name has been used. If used, return an invalid Id and report error! */
+  std::map<std::string, ModuleId>::iterator it = name_id_map_.find(name);
+  if (it != name_id_map_.end()) {
+    return ModuleId::INVALID();
+  }
+
+  /* Create an new id */
+  ModuleId module = ModuleId(ids_.size());
+  ids_.push_back(module);
+
+  /* Allocate other attributes */
+  names_.push_back(name);
+  parents_.emplace_back();
+  children_.emplace_back();
+  num_child_instances_.emplace_back();
+  child_instance_names_.emplace_back();
+  configurable_children_.emplace_back();
+  configurable_child_instances_.emplace_back();
+
+  port_ids_.emplace_back();
+  ports_.emplace_back();
+  port_types_.emplace_back();
+  port_is_wire_.emplace_back();
+  port_is_register_.emplace_back();
+  port_preproc_flags_.emplace_back();
+
+  net_ids_.emplace_back();
+  net_names_.emplace_back();
+  net_src_ids_.emplace_back();
+  net_src_module_ids_.emplace_back();
+  net_src_instance_ids_.emplace_back();
+  net_src_port_ids_.emplace_back();
+  net_src_pin_ids_.emplace_back();
+
+  net_sink_ids_.emplace_back();
+  net_sink_module_ids_.emplace_back();
+  net_sink_instance_ids_.emplace_back();
+  net_sink_port_ids_.emplace_back();
+  net_sink_pin_ids_.emplace_back();
+
+  /* Register in the name-to-id map */
+  name_id_map_[name] = module;
+
+  /* Build port lookup */
+  port_lookup_.emplace_back();
+  port_lookup_[module].resize(NUM_MODULE_PORT_TYPES);
+
+  /* Build fast look-up for nets */
+  net_lookup_.emplace_back();
+  /* Reserve the instance 0 for the module */
+  net_lookup_[module][module].emplace_back();
+
+  /* Return the new id */
+  return module;
+}
+
+/* Add a port to a module */
+ModulePortId ModuleManager::add_port(const ModuleId& module, 
+                                     const BasicPort& port_info, const enum e_module_port_type& port_type) {
+  /* Validate the id of module */
+  VTR_ASSERT( valid_module_id(module) );
+
+  /* Add port and fill port attributes */
+  ModulePortId port = ModulePortId(port_ids_[module].size());
+  port_ids_[module].push_back(port);
+  ports_[module].push_back(port_info);
+  port_types_[module].push_back(port_type);
+  port_is_wire_[module].push_back(false);
+  port_is_register_[module].push_back(false);
+  port_preproc_flags_[module].emplace_back(); /* Create an empty string for the pre-processing flags */
+
+  /* Update fast look-up for port */
+  port_lookup_[module][port_type].push_back(port);
+
+  /* Update fast look-up for nets */
+  VTR_ASSERT_SAFE(1 == net_lookup_[module][module].size());
+  net_lookup_[module][module][0][port].resize(port_info.get_width(), ModuleNetId::INVALID());
+
+  return port;
+}
+
+/* Set a name for a module port */
+void ModuleManager::set_module_port_name(const ModuleId& module, const ModulePortId& module_port, 
+                                         const std::string& port_name) {
+  /* Validate the id of module port */
+  VTR_ASSERT( valid_module_port_id(module, module_port) );
+  
+  ports_[module][module_port].set_name(port_name);
+}
+
+/* Set a name for a module */
+void ModuleManager::set_module_name(const ModuleId& module, const std::string& name) {
+  /* Validate the id of module */
+  VTR_ASSERT( valid_module_id(module) );
+  names_[module] = name;
+}
+
+/* Set a port to be a wire */
+void ModuleManager::set_port_is_wire(const ModuleId& module, const std::string& port_name, const bool& is_wire) {
+  /* Find the port */
+  ModulePortId port = find_module_port(module, port_name);
+  /* Must find something, otherwise drop an error */
+  VTR_ASSERT(ModulePortId::INVALID() != port);
+  port_is_wire_[module][port] = is_wire;
+}
+
+/* Set a port to be a register */
+void ModuleManager::set_port_is_register(const ModuleId& module, const std::string& port_name, const bool& is_register) {
+  /* Find the port */
+  ModulePortId port = find_module_port(module, port_name);
+  /* Must find something, otherwise drop an error */
+  VTR_ASSERT(ModulePortId::INVALID() != port);
+  port_is_register_[module][port] = is_register;
+}
+
+/* Set the preprocessing flag for a port */
+void ModuleManager::set_port_preproc_flag(const ModuleId& module, const ModulePortId& port, const std::string& preproc_flag) {
+  /* Must find something, otherwise drop an error */
+  VTR_ASSERT(valid_module_port_id(module, port));
+  port_preproc_flags_[module][port] = preproc_flag;
+}
+
+/* Add a child module to a parent module */
+void ModuleManager::add_child_module(const ModuleId& parent_module, const ModuleId& child_module) {
+  /* Validate the id of both parent and child modules */
+  VTR_ASSERT ( valid_module_id(parent_module) );
+  VTR_ASSERT ( valid_module_id(child_module) );
+
+  /* Try to find if the parent module is already in the list */
+  std::vector<ModuleId>::iterator parent_it = std::find(parents_[child_module].begin(), parents_[child_module].end(), parent_module);
+  if (parent_it == parents_[child_module].end()) {
+    /* Update the parent module of child module */
+    parents_[child_module].push_back(parent_module);
+  }
+
+  std::vector<ModuleId>::iterator child_it = std::find(children_[parent_module].begin(), children_[parent_module].end(), child_module);
+  if (child_it == children_[parent_module].end()) {
+    /* Update the child module of parent module */
+    children_[parent_module].push_back(child_module);
+    num_child_instances_[parent_module].push_back(1); /* By default give one */
+    /* Update the instance name list */
+    child_instance_names_[parent_module].emplace_back();
+    child_instance_names_[parent_module].back().emplace_back();
+  } else {
+    /* Increase the counter of instances */
+    num_child_instances_[parent_module][child_it - children_[parent_module].begin()]++;
+    child_instance_names_[parent_module][child_it - children_[parent_module].begin()].emplace_back();
+  }
+
+  /* Update fast look-up for nets */
+  size_t instance_id = net_lookup_[parent_module][child_module].size();
+  net_lookup_[parent_module][child_module].emplace_back();
+  /* Find the ports for the child module and update the fast look-up */
+  for (ModulePortId child_port : port_ids_[child_module]) {
+    net_lookup_[parent_module][child_module][instance_id][child_port].resize(ports_[child_module][child_port].get_width(), ModuleNetId::INVALID());
+  } 
+}
+
+/* Set the instance name of a child module */
+void ModuleManager::set_child_instance_name(const ModuleId& parent_module, 
+                                            const ModuleId& child_module, 
+                                            const size_t& instance_id, 
+                                            const std::string& instance_name) {
+  /* Validate the id of both parent and child modules */
+  VTR_ASSERT ( valid_module_id(parent_module) );
+  VTR_ASSERT ( valid_module_id(child_module) );
+  /* Ensure that the instance id is in range */
+  VTR_ASSERT ( instance_id < num_instance(parent_module, child_module));
+  /* Try to find the child_module in the children list of parent_module*/
+  size_t child_index = find_child_module_index_in_parent_module(parent_module, child_module);
+  /* We must find something! */
+  VTR_ASSERT(size_t(-1) != child_index);
+  /* Set the name */
+  child_instance_names_[parent_module][child_index][instance_id] = instance_name;
+}
+
+/* Add a configurable child module to module
+ * Note: this function should be called after add_child_module!
+ * It will check if the child module does exist in the parent module
+ * And the instance id is in range or not
+ */
+void ModuleManager::add_configurable_child(const ModuleId& parent_module, 
+                                           const ModuleId& child_module, 
+                                           const size_t& child_instance) {
+  /* Validate the id of both parent and child modules */
+  VTR_ASSERT ( valid_module_id(parent_module) );
+  VTR_ASSERT ( valid_module_id(child_module) );
+  /* Ensure that the instance id is in range */
+  VTR_ASSERT ( child_instance < num_instance(parent_module, child_module));
+
+  configurable_children_[parent_module].push_back(child_module);
+  configurable_child_instances_[parent_module].push_back(child_instance);
+}
+
+/* Add a net to the connection graph of the module */ 
+ModuleNetId ModuleManager::create_module_net(const ModuleId& module) {
+  /* Validate the module id */
+  VTR_ASSERT ( valid_module_id(module) );
+
+  /* Create an new id */
+  ModuleNetId net = ModuleNetId(net_ids_[module].size());
+  net_ids_[module].push_back(net);
+  
+  /* Allocate net-related data structures */
+  net_names_[module].emplace_back();
+  net_src_ids_[module].emplace_back();
+  net_src_module_ids_[module].emplace_back();
+  net_src_instance_ids_[module].emplace_back();
+  net_src_port_ids_[module].emplace_back();
+  net_src_pin_ids_[module].emplace_back();
+
+  net_sink_ids_[module].emplace_back();
+  net_sink_module_ids_[module].emplace_back();
+  net_sink_instance_ids_[module].emplace_back();
+  net_sink_port_ids_[module].emplace_back();
+  net_sink_pin_ids_[module].emplace_back();
+
+  return net;
+}
+
+/* Set the name of net */
+void ModuleManager::set_net_name(const ModuleId& module, const ModuleNetId& net,
+                                 const std::string& name) {
+  /* Validate module net */
+  VTR_ASSERT(valid_module_net_id(module, net));
+
+  net_names_[module][net] = name;
+}
+
+/* Add a source to a net in the connection graph */
+ModuleNetSrcId ModuleManager::add_module_net_source(const ModuleId& module, const ModuleNetId& net,
+                                                    const ModuleId& src_module, const size_t& instance_id,
+                                                    const ModulePortId& src_port, const size_t& src_pin) {
+  /* Validate the module and net id */
+  VTR_ASSERT(valid_module_net_id(module, net));
+
+  /* Create a new id for src node */
+  ModuleNetSrcId net_src = ModuleNetSrcId(net_src_ids_[module][net].size());
+  net_src_ids_[module][net].push_back(net_src);
+
+  /* Validate the source module */
+  VTR_ASSERT(valid_module_id(src_module));
+  net_src_module_ids_[module][net].push_back(src_module);
+
+  /* if it has the same id as module, our instance id will be by default 0 */
+  size_t src_instance_id = instance_id;
+  if (src_module == module) {
+    src_instance_id = 0;
+    net_src_instance_ids_[module][net].push_back(src_instance_id);
+  } else {
+    /* Check the instance id of the src module */
+    VTR_ASSERT (src_instance_id < num_instance(module, src_module));
+    net_src_instance_ids_[module][net].push_back(src_instance_id);
+  } 
+
+  /* Validate the port exists in the src module */
+  VTR_ASSERT(valid_module_port_id(src_module, src_port));
+  net_src_port_ids_[module][net].push_back(src_port);
+
+  /* Validate the pin id is in the range of the port width */
+  VTR_ASSERT(src_pin < module_port(src_module, src_port).get_width());
+  net_src_pin_ids_[module][net].push_back(src_pin);
+
+  /* Update fast look-up for nets */
+  net_lookup_[module][src_module][src_instance_id][src_port][src_pin] = net;
+
+  return net_src;
+}
+
+/* Add a sink to a net in the connection graph */
+ModuleNetSinkId ModuleManager::add_module_net_sink(const ModuleId& module, const ModuleNetId& net,
+                                                   const ModuleId& sink_module, const size_t& instance_id,
+                                                   const ModulePortId& sink_port, const size_t& sink_pin) {
+  /* Validate the module and net id */
+  VTR_ASSERT(valid_module_net_id(module, net));
+
+  /* Create a new id for sink node */
+  ModuleNetSinkId net_sink = ModuleNetSinkId(net_sink_ids_[module][net].size());
+  net_sink_ids_[module][net].push_back(net_sink);
+
+  /* Validate the source module */
+  VTR_ASSERT(valid_module_id(sink_module));
+  net_sink_module_ids_[module][net].push_back(sink_module);
+
+  /* if it has the same id as module, our instance id will be by default 0 */
+  size_t sink_instance_id = instance_id;
+  if (sink_module == module) {
+    sink_instance_id = 0;
+    net_sink_instance_ids_[module][net].push_back(sink_instance_id);
+  } else {
+    /* Check the instance id of the src module */
+    VTR_ASSERT (sink_instance_id < num_instance(module, sink_module));
+    net_sink_instance_ids_[module][net].push_back(sink_instance_id);
+  } 
+
+  /* Validate the port exists in the sink module */
+  VTR_ASSERT(valid_module_port_id(sink_module, sink_port));
+  net_sink_port_ids_[module][net].push_back(sink_port);
+
+  /* Validate the pin id is in the range of the port width */
+  VTR_ASSERT(sink_pin < module_port(sink_module, sink_port).get_width());
+  net_sink_pin_ids_[module][net].push_back(sink_pin);
+
+  /* Update fast look-up for nets */
+  net_lookup_[module][sink_module][sink_instance_id][sink_port][sink_pin] = net;
+
+  return net_sink;
+}
+
+/******************************************************************************
+ * Private validators/invalidators
+ ******************************************************************************/
+bool ModuleManager::valid_module_id(const ModuleId& module) const {
+  return ( size_t(module) < ids_.size() ) && ( module == ids_[module] ); 
+}
+
+bool ModuleManager::valid_module_port_id(const ModuleId& module, const ModulePortId& port) const {
+  if (false == valid_module_id(module)) {
+    return false;
+  }
+  return ( size_t(port) < port_ids_[module].size() ) && ( port == port_ids_[module][port] ); 
+}
+
+bool ModuleManager::valid_module_net_id(const ModuleId& module, const ModuleNetId& net) const {
+  if (false == valid_module_id(module)) {
+    return false;
+  }
+  return ( size_t(net) < net_ids_[module].size() ) && ( net == net_ids_[module][net] ); 
+}
+
+void ModuleManager::invalidate_name2id_map() {
+  name_id_map_.clear();
+}
+
+void ModuleManager::invalidate_port_lookup() {
+  port_lookup_.clear();
+}
+
+void ModuleManager::invalidate_net_lookup() {
+  net_lookup_.clear();
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fabric/module_manager.h b/openfpga/src/fabric/module_manager.h
new file mode 100644
index 000000000..425b7a072
--- /dev/null
+++ b/openfpga/src/fabric/module_manager.h
@@ -0,0 +1,238 @@
+#ifndef MODULE_MANAGER_H
+#define MODULE_MANAGER_H
+
+#include <string>
+#include <map>
+#include "vtr_vector.h"
+#include "module_manager_fwd.h"
+#include "openfpga_port.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/******************************************************************************
+ * This files includes data structures for module management.
+ * It keeps a list of modules that have been generated, the port map of the modules,
+ * parents and children of each modules. This will ease instanciation of modules 
+ * with explicit port map and outputting a hierarchy of modules 
+ *
+ * Module includes the basic information:
+ * 1. unique identifier
+ * 2. module name: which should be unique 
+ * 3. port list: basic information of all the ports belonging to the module
+ * 4. port types: types of each port, which will matter how we output the ports
+ * 5. parent modules: ids of parent modules
+ * 6. children modules: ids of child modules 
+ ******************************************************************************/
+class ModuleManager {
+  public: /* Private data structures */
+    enum e_module_port_type {
+      MODULE_GLOBAL_PORT, /* Global inputs */
+      MODULE_GPIO_PORT,   /* General-purpose IOs, which are data IOs of the fabric */
+      MODULE_INOUT_PORT,  /* Normal (non-global) inout ports */
+      MODULE_INPUT_PORT,  /* Normal (non-global) input ports */
+      MODULE_OUTPUT_PORT, /* Normal (non-global) output ports */
+      MODULE_CLOCK_PORT,  /* Nromal (non-global) clock ports*/
+      NUM_MODULE_PORT_TYPES 
+    };
+
+  public: /* Public Constructors */
+
+  public: /* Types and ranges */
+    typedef vtr::vector<ModuleId, ModuleId>::const_iterator module_iterator;
+    typedef vtr::vector<ModulePortId, ModulePortId>::const_iterator module_port_iterator;
+    typedef vtr::vector<ModuleNetId, ModuleNetId>::const_iterator module_net_iterator;
+    typedef vtr::vector<ModuleNetSrcId, ModuleNetSrcId>::const_iterator module_net_src_iterator;
+    typedef vtr::vector<ModuleNetSinkId, ModuleNetSinkId>::const_iterator module_net_sink_iterator;
+
+    typedef vtr::Range<module_iterator> module_range;
+    typedef vtr::Range<module_port_iterator> module_port_range;
+    typedef vtr::Range<module_net_iterator> module_net_range;
+    typedef vtr::Range<module_net_src_iterator> module_net_src_range;
+    typedef vtr::Range<module_net_sink_iterator> module_net_sink_range;
+
+  public: /* Public aggregators */
+    /* Find all the modules */
+    module_range modules() const;
+    /* Find all the ports belonging to a module */
+    module_port_range module_ports(const ModuleId& module) const;
+    /* Find all the nets belonging to a module */
+    module_net_range module_nets(const ModuleId& module) const;
+    /* Find all the child modules under a parent module */
+    std::vector<ModuleId> child_modules(const ModuleId& parent_module) const;
+    /* Find all the instances under a parent module */
+    std::vector<size_t> child_module_instances(const ModuleId& parent_module, const ModuleId& child_module) const;
+    /* Find all the configurable child modules under a parent module */
+    std::vector<ModuleId> configurable_children(const ModuleId& parent_module) const;
+    /* Find all the instances of configurable child modules under a parent module */
+    std::vector<size_t> configurable_child_instances(const ModuleId& parent_module) const;
+    /* Find the source ids of modules */
+    module_net_src_range module_net_sources(const ModuleId& module, const ModuleNetId& net) const;
+    /* Find the sink ids of modules */
+    module_net_sink_range module_net_sinks(const ModuleId& module, const ModuleNetId& net) const;
+
+  public: /* Public accessors */
+    size_t num_modules() const;
+    size_t num_nets(const ModuleId& module) const;
+    std::string module_name(const ModuleId& module_id) const;
+    std::string module_port_type_str(const enum e_module_port_type& port_type) const;
+    std::vector<BasicPort> module_ports_by_type(const ModuleId& module_id, const enum e_module_port_type& port_type) const;
+    std::vector<ModulePortId> module_port_ids_by_type(const ModuleId& module_id, const enum e_module_port_type& port_type) const;
+    /* Find a port of a module by a given name */
+    ModulePortId find_module_port(const ModuleId& module_id, const std::string& port_name) const;
+    /* Find the Port information with a given port id */
+    BasicPort module_port(const ModuleId& module_id, const ModulePortId& port_id) const;
+    /* Find a module by a given name */
+    ModuleId find_module(const std::string& name) const;
+    /* Find the number of instances of a child module in the parent module */
+    size_t num_instance(const ModuleId& parent_module, const ModuleId& child_module) const;
+    /* Find the instance name of a child module */
+    std::string instance_name(const ModuleId& parent_module, const ModuleId& child_module,
+                              const size_t& instance_id) const;
+    /* Find the instance id of a given instance name */
+    size_t instance_id(const ModuleId& parent_module, const ModuleId& child_module,
+                       const std::string& instance_name) const;
+    /* Find if a port is a wire connection */
+    bool port_is_wire(const ModuleId& module, const ModulePortId& port) const;
+    /* Find if a port is register */
+    bool port_is_register(const ModuleId& module, const ModulePortId& port) const;
+    /* Return the pre-processing flag of a port */
+    std::string port_preproc_flag(const ModuleId& module, const ModulePortId& port) const;
+    /* Find a net from an instance of a module */
+    ModuleNetId module_instance_port_net(const ModuleId& parent_module, 
+                                         const ModuleId& child_module, const size_t& child_instance,
+                                         const ModulePortId& child_port, const size_t& child_pin) const;
+    /* Find the name of net */
+    std::string net_name(const ModuleId& module, const ModuleNetId& net) const;
+    /* Find the source modules of a net */
+    vtr::vector<ModuleNetSrcId, ModuleId> net_source_modules(const ModuleId& module, const ModuleNetId& net) const;
+    /* Find the ids of source instances of a net */
+    vtr::vector<ModuleNetSrcId, size_t> net_source_instances(const ModuleId& module, const ModuleNetId& net) const;
+    /* Find the source ports of a net */
+    vtr::vector<ModuleNetSrcId, ModulePortId> net_source_ports(const ModuleId& module, const ModuleNetId& net) const;
+    /* Find the source pin indices of a net */
+    vtr::vector<ModuleNetSrcId, size_t> net_source_pins(const ModuleId& module, const ModuleNetId& net) const;
+    /* Identify if a pin of a port in a module already exists in the net source list*/
+    bool net_source_exist(const ModuleId& module, const ModuleNetId& net,
+                          const ModuleId& src_module, const size_t& instance_id,
+                          const ModulePortId& src_port, const size_t& src_pin);
+
+    /* Find the sink modules of a net */
+    vtr::vector<ModuleNetSinkId, ModuleId> net_sink_modules(const ModuleId& module, const ModuleNetId& net) const;
+    /* Find the ids of sink instances of a net */
+    vtr::vector<ModuleNetSinkId, size_t> net_sink_instances(const ModuleId& module, const ModuleNetId& net) const;
+    /* Find the sink ports of a net */
+    vtr::vector<ModuleNetSinkId, ModulePortId> net_sink_ports(const ModuleId& module, const ModuleNetId& net) const;
+    /* Find the sink pin indices of a net */
+    vtr::vector<ModuleNetSinkId, size_t> net_sink_pins(const ModuleId& module, const ModuleNetId& net) const;
+    /* Identify if a pin of a port in a module already exists in the net sink list*/
+    bool net_sink_exist(const ModuleId& module, const ModuleNetId& net,
+                        const ModuleId& sink_module, const size_t& instance_id,
+                        const ModulePortId& sink_port, const size_t& sink_pin);
+
+  private: /* Private accessors */
+    size_t find_child_module_index_in_parent_module(const ModuleId& parent_module, const ModuleId& child_module) const;
+  public: /* Public mutators */
+    /* Add a module */
+    ModuleId add_module(const std::string& name);
+    /* Add a port to a module */
+    ModulePortId add_port(const ModuleId& module, 
+                          const BasicPort& port_info, const enum e_module_port_type& port_type);
+    /* Set a name for a module port */
+    void set_module_port_name(const ModuleId& module, const ModulePortId& module_port, const std::string& port_name);
+    /* Set a name for a module */
+    void set_module_name(const ModuleId& module, const std::string& name);
+    /* Set a port to be a wire */
+    void set_port_is_wire(const ModuleId& module, const std::string& port_name, const bool& is_wire);
+    /* Set a port to be a register */
+    void set_port_is_register(const ModuleId& module, const std::string& port_name, const bool& is_register);
+    /* Set the preprocessing flag for a port */
+    void set_port_preproc_flag(const ModuleId& module, const ModulePortId& port, const std::string& preproc_flag);
+    /* Add a child module to a parent module */
+    void add_child_module(const ModuleId& parent_module, const ModuleId& child_module);
+    /* Set the instance name of a child module */
+    void set_child_instance_name(const ModuleId& parent_module, const ModuleId& child_module, const size_t& instance_id, const std::string& instance_name);
+    /* Add a configurable child module to module */
+    void add_configurable_child(const ModuleId& module, const ModuleId& child_module, const size_t& child_instance);
+    /* Add a net to the connection graph of the module */ 
+    ModuleNetId create_module_net(const ModuleId& module);
+    /* Set the name of net */
+    void set_net_name(const ModuleId& module, const ModuleNetId& net,
+                      const std::string& name);
+    /* Add a source to a net in the connection graph */
+    ModuleNetSrcId add_module_net_source(const ModuleId& module, const ModuleNetId& net,
+                                         const ModuleId& src_module, const size_t& instance_id,
+                                         const ModulePortId& src_port, const size_t& src_pin);
+    /* Add a sink to a net in the connection graph */
+    ModuleNetSinkId add_module_net_sink(const ModuleId& module, const ModuleNetId& net,
+                                        const ModuleId& sink_module, const size_t& instance_id,
+                                        const ModulePortId& sink_port, const size_t& sink_pin);
+  public: /* Public validators/invalidators */
+    bool valid_module_id(const ModuleId& module) const;
+    bool valid_module_port_id(const ModuleId& module, const ModulePortId& port) const;
+    bool valid_module_net_id(const ModuleId& module, const ModuleNetId& net) const;
+  private: /* Private validators/invalidators */
+    void invalidate_name2id_map();
+    void invalidate_port_lookup();
+    void invalidate_net_lookup();
+  private: /* Internal data */
+    /* Module-level data */
+    vtr::vector<ModuleId, ModuleId> ids_;                                  /* Unique identifier for each Module */
+    vtr::vector<ModuleId, std::string> names_;                                  /* Unique identifier for each Module */
+    vtr::vector<ModuleId, std::vector<ModuleId>> parents_;                 /* Parent modules that include the module */
+    vtr::vector<ModuleId, std::vector<ModuleId>> children_;                /* Child modules that this module contain */
+    vtr::vector<ModuleId, std::vector<size_t>> num_child_instances_;          /* Number of children instance in each child module */
+    vtr::vector<ModuleId, std::vector<std::vector<std::string>>> child_instance_names_;          /* Number of children instance in each child module */
+
+    /* Configurable child modules are used to record the position of configurable modules in bitstream
+     * The sequence of children in the list denotes which one is configured first, etc. 
+     * Note that the sequence can be totally different from the children_ list
+     * This is really dependent how the configuration protocol is organized
+     * which should be made by users/designers 
+     */
+    vtr::vector<ModuleId, std::vector<ModuleId>> configurable_children_;                /* Child modules with configurable memory bits that this module contain */
+    vtr::vector<ModuleId, std::vector<size_t>> configurable_child_instances_;           /* Instances of child modules with configurable memory bits that this module contain */
+
+    /* Port-level data */
+    vtr::vector<ModuleId, vtr::vector<ModulePortId, ModulePortId>> port_ids_;    /* List of ports for each Module */ 
+    vtr::vector<ModuleId, vtr::vector<ModulePortId, BasicPort>> ports_;    /* List of ports for each Module */ 
+    vtr::vector<ModuleId, vtr::vector<ModulePortId, enum e_module_port_type>> port_types_; /* Type of ports */ 
+    vtr::vector<ModuleId, vtr::vector<ModulePortId, bool>> port_is_wire_; /* If the port is a wire, use for Verilog port definition. If enabled: <port_type> reg <port_name>  */ 
+    vtr::vector<ModuleId, vtr::vector<ModulePortId, bool>> port_is_register_; /* If the port is a register, use for Verilog port definition. If enabled: <port_type> reg <port_name>  */ 
+    vtr::vector<ModuleId, vtr::vector<ModulePortId, std::string>> port_preproc_flags_; /* If a port is available only when a pre-processing flag is enabled. This is to record the pre-processing flags */ 
+
+    /* Graph-level data: 
+     * We use nets to model the connection between pins of modules and instances.  
+     * To avoid large memory footprint, we do NOT create pins,   
+     * To enable fast look-up on pins, we create a fast look-up
+     */
+    vtr::vector<ModuleId, vtr::vector<ModuleNetId, ModuleNetId>> net_ids_;    /* List of nets for each Module */ 
+    vtr::vector<ModuleId, vtr::vector<ModuleNetId, std::string>> net_names_;    /* Name of net */ 
+
+    vtr::vector<ModuleId, vtr::vector<ModuleNetId, vtr::vector<ModuleNetSrcId, ModuleNetSrcId>>> net_src_ids_;  /* Unique id of the source that drive the net */ 
+    vtr::vector<ModuleId, vtr::vector<ModuleNetId, vtr::vector<ModuleNetSrcId, ModuleId>>> net_src_module_ids_;  /* Pin ids that drive the net */ 
+    vtr::vector<ModuleId, vtr::vector<ModuleNetId, vtr::vector<ModuleNetSrcId, size_t>>> net_src_instance_ids_;  /* Pin ids that drive the net */ 
+    vtr::vector<ModuleId, vtr::vector<ModuleNetId, vtr::vector<ModuleNetSrcId, ModulePortId>>> net_src_port_ids_;  /* Pin ids that drive the net */ 
+    vtr::vector<ModuleId, vtr::vector<ModuleNetId, vtr::vector<ModuleNetSrcId, size_t>>> net_src_pin_ids_;  /* Pin ids that drive the net */ 
+
+
+    vtr::vector<ModuleId, vtr::vector<ModuleNetId, vtr::vector<ModuleNetSinkId, ModuleNetSinkId>>> net_sink_ids_;  /* Unique ids of the sink that the net drives */ 
+    vtr::vector<ModuleId, vtr::vector<ModuleNetId, vtr::vector<ModuleNetSinkId, ModuleId>>> net_sink_module_ids_;  /* Pin ids that the net drives */ 
+    vtr::vector<ModuleId, vtr::vector<ModuleNetId, vtr::vector<ModuleNetSinkId, size_t>>> net_sink_instance_ids_;  /* Pin ids that drive the net */ 
+    vtr::vector<ModuleId, vtr::vector<ModuleNetId, vtr::vector<ModuleNetSinkId, ModulePortId>>> net_sink_port_ids_;  /* Pin ids that drive the net */ 
+    vtr::vector<ModuleId, vtr::vector<ModuleNetId, vtr::vector<ModuleNetSinkId, size_t>>> net_sink_pin_ids_;  /* Pin ids that drive the net */ 
+
+    /* fast look-up for module */
+    std::map<std::string, ModuleId> name_id_map_;
+    /* fast look-up for ports */
+    typedef vtr::vector<ModuleId, std::vector<std::vector<ModulePortId>>> PortLookup;
+    mutable PortLookup port_lookup_; /* [module_ids][port_types][port_ids] */ 
+
+    /* fast look-up for nets */
+    typedef vtr::vector<ModuleId, std::map<ModuleId, std::vector<std::map<ModulePortId, std::vector<ModuleNetId>>>>> NetLookup;
+    mutable NetLookup net_lookup_; /* [module_ids][module_ids][instance_ids][port_ids][pin_ids] */ 
+};
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/fabric/module_manager_fwd.h b/openfpga/src/fabric/module_manager_fwd.h
new file mode 100644
index 000000000..695ce1024
--- /dev/null
+++ b/openfpga/src/fabric/module_manager_fwd.h
@@ -0,0 +1,35 @@
+/**************************************************
+ * This file includes only declarations for 
+ * the data structures for module managers
+ * Please refer to module_manager.h for more details
+ *************************************************/
+#ifndef MODULE_MANAGER_FWD_H
+#define MODULE_MANAGER_FWD_H
+
+#include "vtr_strong_id.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/* Strong Ids for ModuleManager */
+struct module_id_tag;
+struct instance_id_tag; /* TODO: use instance id in module_manager */
+struct module_port_id_tag;
+struct module_pin_id_tag;
+struct module_net_id_tag;
+struct module_net_src_id_tag;
+struct module_net_sink_id_tag;
+
+typedef vtr::StrongId<module_id_tag> ModuleId;
+typedef vtr::StrongId<instance_id_tag> InstanceId;
+typedef vtr::StrongId<module_port_id_tag> ModulePortId;
+typedef vtr::StrongId<module_pin_id_tag> ModulePinId;
+typedef vtr::StrongId<module_net_id_tag> ModuleNetId;
+typedef vtr::StrongId<module_net_src_id_tag> ModuleNetSrcId;
+typedef vtr::StrongId<module_net_sink_id_tag> ModuleNetSinkId;
+
+class ModuleManager;
+
+} /* end namespace openfpga */
+
+#endif 
diff --git a/openfpga/src/utils/circuit_library_utils.cpp b/openfpga/src/utils/circuit_library_utils.cpp
index 720a0e7c1..cecbcafed 100644
--- a/openfpga/src/utils/circuit_library_utils.cpp
+++ b/openfpga/src/utils/circuit_library_utils.cpp
@@ -4,9 +4,10 @@
  * They are made to ease the development in some specific purposes
  * Please classify such functions in this file
  ***********************************************************************/
+
 #include <algorithm>
 
-/* Headers from vtr util library */
+/* Headers from vtrutil library */
 #include "vtr_assert.h"
 #include "vtr_log.h"
 
@@ -83,11 +84,11 @@ std::vector<CircuitPortId> find_circuit_mode_select_sram_ports(const CircuitLibr
 static 
 size_t find_rram_circuit_num_shared_config_bits(const CircuitLibrary& circuit_lib,
                                                 const CircuitModelId& rram_model,
-                                                const e_config_protocol_type& config_protocol_type) {
+                                                const e_config_protocol_type& sram_orgz_type) {
   size_t num_shared_config_bits = 0;
 
   /* Branch on the organization of configuration protocol */ 
-  switch (config_protocol_type) {
+  switch (sram_orgz_type) {
   case CONFIG_MEM_STANDALONE:
   case CONFIG_MEM_SCAN_CHAIN:
     break;
@@ -100,7 +101,7 @@ size_t find_rram_circuit_num_shared_config_bits(const CircuitLibrary& circuit_li
     break;
   }    
   default:
-    VTR_LOG_ERROR("Invalid type of configuration protocol!\n");
+    VTR_LOG_ERROR("Invalid type of SRAM organization!\n");
     exit(1);
   }
 
@@ -123,7 +124,7 @@ size_t find_rram_circuit_num_shared_config_bits(const CircuitLibrary& circuit_li
  *******************************************************************/
 size_t find_circuit_num_shared_config_bits(const CircuitLibrary& circuit_lib,
                                            const CircuitModelId& circuit_model,
-                                           const e_config_protocol_type& config_protocol_type) {
+                                           const e_config_protocol_type& sram_orgz_type) {
   size_t num_shared_config_bits = 0;
 
   std::vector<CircuitPortId> sram_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_SRAM);
@@ -138,11 +139,10 @@ size_t find_circuit_num_shared_config_bits(const CircuitLibrary& circuit_lib,
       break;
     case CIRCUIT_MODEL_DESIGN_RRAM: 
        /* RRAM circuit do need shared configuration bits, but it is subjected to the largest one among different SRAM models */
-       num_shared_config_bits = std::max((int)num_shared_config_bits, (int)find_rram_circuit_num_shared_config_bits(circuit_lib, sram_model, config_protocol_type));
+       num_shared_config_bits = std::max((int)num_shared_config_bits, (int)find_rram_circuit_num_shared_config_bits(circuit_lib, sram_model, sram_orgz_type));
        break;
     default:
-      VTR_LOG_ERROR("Invalid design technology for SRAM circuit model!\n",
-                    circuit_lib.model_name(circuit_model).c_str());
+      VTR_LOG_ERROR("Invalid design technology for SRAM model!\n");
       exit(1);
     }
   } 
diff --git a/openfpga/src/utils/circuit_library_utils.h b/openfpga/src/utils/circuit_library_utils.h
index aad080b72..7c5552304 100644
--- a/openfpga/src/utils/circuit_library_utils.h
+++ b/openfpga/src/utils/circuit_library_utils.h
@@ -7,7 +7,6 @@
 /********************************************************************
  * Include header files that are required by function declaration
  *******************************************************************/
-
 #include <vector>
 #include "circuit_types.h"
 #include "circuit_library.h"
diff --git a/openfpga/src/utils/memory_utils.cpp b/openfpga/src/utils/memory_utils.cpp
new file mode 100644
index 000000000..8452626d8
--- /dev/null
+++ b/openfpga/src/utils/memory_utils.cpp
@@ -0,0 +1,385 @@
+/*********************************************************************
+ * This file includes functions that are used for 
+ * generating ports for memory modules 
+ *********************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+#include "openfpga_naming.h"
+#include "memory_utils.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/*********************************************************************
+ * Create a port-to-port map for a CMOS memory module 
+ *
+ * Configuration Chain 
+ * -------------------
+ *
+ *        config_bus (head)   config_bus (tail) 
+ *            |                   ^
+ *            v                   |
+ *      +-------------------------------------+
+ *      |        CMOS-based Memory Module     |
+ *      +-------------------------------------+
+ *            |                   |
+ *            v                   v
+ *         sram_out             sram_outb
+ *
+ *
+ * Memory bank 
+ * -----------
+ *
+ *        config_bus (BL)   config_bus (WL) 
+ *            |                   |
+ *            v                   v
+ *      +-------------------------------------+
+ *      |        CMOS-based Memory Module     |
+ *      +-------------------------------------+
+ *            |                   |
+ *            v                   v
+ *         sram_out             sram_outb
+ *
+ **********************************************************************/
+static 
+std::map<std::string, BasicPort> generate_cmos_mem_module_port2port_map(const BasicPort& config_bus,
+                                                                        const std::vector<BasicPort>& mem_output_bus_ports,
+                                                                        const e_config_protocol_type& sram_orgz_type) {
+  std::map<std::string, BasicPort> port2port_name_map;
+
+  switch (sram_orgz_type) {
+  case CONFIG_MEM_STANDALONE:
+    /* Nothing to do */
+    break;
+  case CONFIG_MEM_SCAN_CHAIN: {
+    /* Link the head port of the memory module: 
+     * the LSB of config bus port is the head port index
+     */
+    std::vector<BasicPort> config_bus_ports;
+    config_bus_ports.push_back(BasicPort(generate_local_config_bus_port_name(), config_bus.get_msb(), config_bus.get_msb() + 1));
+    BasicPort head_port(config_bus_ports[0].get_name(), config_bus_ports[0].get_lsb(), config_bus_ports[0].get_lsb()); 
+    port2port_name_map[generate_configuration_chain_head_name()] = head_port;
+
+    /* Link the tail port of the memory module: 
+     * the MSB of config bus port is the tail port index 
+     */
+    BasicPort tail_port(config_bus_ports[0].get_name(), config_bus_ports[0].get_msb(), config_bus_ports[0].get_msb()); 
+    port2port_name_map[generate_configuration_chain_tail_name()] = tail_port;
+
+    /* Link the SRAM output ports of the memory module */ 
+    VTR_ASSERT( 2 == mem_output_bus_ports.size() );
+    port2port_name_map[generate_configuration_chain_data_out_name()] = mem_output_bus_ports[0];
+    port2port_name_map[generate_configuration_chain_inverted_data_out_name()] = mem_output_bus_ports[1];
+    break;
+  }
+  case CONFIG_MEM_MEMORY_BANK:
+    /* TODO: */
+    break;
+  default:
+    VTR_LOG_ERROR("Invalid type of SRAM organization!\n");
+    exit(1);
+  }
+
+  return port2port_name_map;
+}
+
+/*********************************************************************
+ * Create a port-to-port map for a ReRAM-based memory module 
+ * Memory bank 
+ * -----------
+ *
+ *        config_bus (BL)   config_bus (WL) 
+ *            |                   |
+ *            v                   v
+ *      +-------------------------------------+
+ *      |        ReRAM-based Memory Module    |
+ *      +-------------------------------------+
+ *            |                   |
+ *            v                   v
+ *         Mem_out              Mem_outb
+ **********************************************************************/
+static 
+std::map<std::string, BasicPort> generate_rram_mem_module_port2port_map(const BasicPort& config_bus,
+                                                                        const std::vector<BasicPort>& mem_output_bus_ports,
+                                                                        const e_config_protocol_type& sram_orgz_type) {
+  std::map<std::string, BasicPort> port2port_name_map;
+
+  switch (sram_orgz_type) {
+  case CONFIG_MEM_STANDALONE:
+    /* Not supported */
+    break;
+  case CONFIG_MEM_SCAN_CHAIN: {
+    /* Link the head port of the memory module: 
+     * the LSB of config bus port is the head port index
+     */
+    std::vector<BasicPort> config_bus_ports;
+    config_bus_ports.push_back(BasicPort(generate_local_config_bus_port_name(), config_bus.get_msb(), config_bus.get_msb() + 1));
+    BasicPort head_port(config_bus_ports[0].get_name(), config_bus_ports[0].get_lsb(), config_bus_ports[0].get_lsb()); 
+    port2port_name_map[generate_configuration_chain_head_name()] = head_port;
+
+    /* Link the tail port of the memory module: 
+     * the MSB of config bus port is the tail port index 
+     */
+    BasicPort tail_port(config_bus_ports[0].get_name(), config_bus_ports[0].get_msb(), config_bus_ports[0].get_msb()); 
+    port2port_name_map[generate_configuration_chain_tail_name()] = tail_port;
+
+    /* Link the SRAM output ports of the memory module */ 
+    VTR_ASSERT( 2 == mem_output_bus_ports.size() );
+    port2port_name_map[generate_configuration_chain_data_out_name()] = mem_output_bus_ports[0];
+    port2port_name_map[generate_configuration_chain_inverted_data_out_name()] = mem_output_bus_ports[1];
+    break;
+  }
+  case CONFIG_MEM_MEMORY_BANK:
+    /* TODO: link BL/WL/Reserved Ports to the inputs of a memory module */
+    break;
+  default:
+    VTR_LOG_ERROR("Invalid type of SRAM organization!\n");
+    exit(1);
+  }
+
+  return port2port_name_map;
+}
+
+/*********************************************************************
+ * Create a port-to-port map for a memory module 
+ * The content of the port-to-port map will depend not only 
+ * the design technology of the memory cells but also the 
+ * configuration styles of FPGA fabric.
+ * Here we will branch on the design technology
+ **********************************************************************/
+std::map<std::string, BasicPort> generate_mem_module_port2port_map(const BasicPort& config_bus,
+                                                                   const std::vector<BasicPort>& mem_output_bus_ports,
+                                                                   const e_circuit_model_design_tech& mem_design_tech,
+                                                                   const e_config_protocol_type& sram_orgz_type) {
+  std::map<std::string, BasicPort> port2port_name_map;
+
+  switch (mem_design_tech) {
+  case CIRCUIT_MODEL_DESIGN_CMOS:
+    port2port_name_map = generate_cmos_mem_module_port2port_map(config_bus, mem_output_bus_ports, sram_orgz_type);
+    break;
+  case CIRCUIT_MODEL_DESIGN_RRAM:
+    port2port_name_map = generate_rram_mem_module_port2port_map(config_bus, mem_output_bus_ports, sram_orgz_type);
+    break;
+  default:
+    VTR_LOG_ERROR("Invalid type of memory design technology!\n");
+    exit(1);
+  }
+
+  return port2port_name_map;
+}
+
+/*********************************************************************
+ * Update the LSB and MSB of a configuration bus based on the number of 
+ * memory bits of a CMOS memory module. 
+ **********************************************************************/
+static 
+void update_cmos_mem_module_config_bus(const e_config_protocol_type& sram_orgz_type,
+                                       const size_t& num_config_bits,
+                                       BasicPort& config_bus) {
+  switch (sram_orgz_type) {
+  case CONFIG_MEM_STANDALONE:
+    /* Not supported */
+    break;
+  case CONFIG_MEM_SCAN_CHAIN:
+    /* Scan-chain of a memory module only has a head and a tail.
+     * LSB and MSB of configuration bus will be shifted to the next head. 
+     */
+    VTR_ASSERT(true == config_bus.rotate(1));
+    break;
+  case CONFIG_MEM_MEMORY_BANK:
+    /* In this case, a memory module has a number of BL/WL and BLB/WLB (possibly).
+     * LSB and MSB of configuration bus will be shifted by the number of BL/WL/BLB/WLB. 
+     */
+    VTR_ASSERT(true == config_bus.rotate(num_config_bits));
+    break;
+  default:
+    VTR_LOG_ERROR("Invalid type of SRAM organization!\n");
+    exit(1);
+  }
+}
+
+/*********************************************************************
+ * Update the LSB and MSB of a configuration bus based on the number of 
+ * memory bits of a ReRAM memory module. 
+ **********************************************************************/
+static 
+void update_rram_mem_module_config_bus(const e_config_protocol_type& sram_orgz_type,
+                                       BasicPort& config_bus) {
+  switch (sram_orgz_type) {
+  case CONFIG_MEM_STANDALONE:
+    /* Not supported */
+    break;
+  case CONFIG_MEM_SCAN_CHAIN:
+    /* Scan-chain of a memory module only has a head and a tail.
+     * LSB and MSB of configuration bus will be shifted to the next head. 
+     * TODO: this may be changed later!!!
+     */
+    VTR_ASSERT(true == config_bus.rotate(1));
+    break;
+  case CONFIG_MEM_MEMORY_BANK:
+    /* In this case, a memory module contains unique BL/WL or BLB/WLB,
+     * which are not shared with other modules   
+     * TODO: this may be changed later!!!
+     */
+    VTR_ASSERT(true == config_bus.rotate(1));
+    break;
+  default:
+    VTR_LOG_ERROR("Invalid type of SRAM organization!\n");
+    exit(1);
+  }
+}
+
+/*********************************************************************
+ * Update the LSB and MSB of a configuration bus based on the number of 
+ * memory bits of a module. 
+ * Note that this function is designed to do such simple job, in purpose of
+ * being independent from adding ports or printing ports.
+ * As such, this function can be re-used in bitstream generation 
+ * when Verilog generation is not needed.  
+ * DO NOT update the configuration bus in the function of adding/printing ports
+ **********************************************************************/
+void update_mem_module_config_bus(const e_config_protocol_type& sram_orgz_type,
+                                  const e_circuit_model_design_tech& mem_design_tech,
+                                  const size_t& num_config_bits,
+                                  BasicPort& config_bus) {
+  switch (mem_design_tech) {
+  case CIRCUIT_MODEL_DESIGN_CMOS:
+    update_cmos_mem_module_config_bus(sram_orgz_type, num_config_bits, config_bus);
+    break;
+  case CIRCUIT_MODEL_DESIGN_RRAM:
+    update_rram_mem_module_config_bus(sram_orgz_type, config_bus);
+    break;
+  default:
+    VTR_LOG_ERROR("Invalid type of memory design technology!\n");
+    exit(1);
+  }
+}
+
+/********************************************************************
+ * Check if the MSB of a configuration bus of a switch block
+ * matches the expected value
+ ********************************************************************/
+bool check_mem_config_bus(const e_config_protocol_type& sram_orgz_type, 
+                          const BasicPort& config_bus, 
+                          const size_t& local_expected_msb) {
+  switch (sram_orgz_type) {
+  case CONFIG_MEM_STANDALONE:
+    /* Not supported */
+    return false;
+    break;
+  case CONFIG_MEM_SCAN_CHAIN:
+    /* TODO: comment on why
+     */
+    return (local_expected_msb == config_bus.get_msb());
+    break;
+  case CONFIG_MEM_MEMORY_BANK:
+    /* TODO: comment on why
+     */
+    return (local_expected_msb == config_bus.get_msb());
+    break;
+  default:
+    VTR_LOG_ERROR("Invalid type of SRAM organization!\n");
+    exit(1);
+  }
+  /* Reach here, it means something goes wrong, return a false value */
+  return false;
+}
+
+/********************************************************************
+ * Generate a list of ports that are used for SRAM configuration to a module
+ * The type and names of added ports strongly depend on the 
+ * organization of SRAMs.
+ * 1. Standalone SRAMs: 
+ *    two ports will be added, which are regular output and inverted output 
+ * 2. Scan-chain Flip-flops:
+ *    two ports will be added, which are the head of scan-chain 
+ *    and the tail of scan-chain
+ *    IMPORTANT: the port size will be forced to 1 in this case 
+ *               because the head and tail are both 1-bit ports!!!
+ * 3. Memory decoders:
+ *    2-4 ports will be added, depending on the ports available in the SRAM
+ *    Among these, two ports are mandatory: BL and WL 
+ *    The other two ports are optional: BLB and WLB
+ *    Note that the constraints are correletated to the checking rules 
+ *    in check_circuit_library()
+ ********************************************************************/
+std::vector<std::string> generate_sram_port_names(const CircuitLibrary& circuit_lib,
+                                                  const CircuitModelId& sram_model,
+                                                  const e_config_protocol_type sram_orgz_type) {
+  std::vector<std::string> sram_port_names;
+  /* Prepare a list of port types to be added, the port type will be used to create port names */
+  std::vector<e_circuit_model_port_type> model_port_types; 
+
+  switch (sram_orgz_type) {
+  case CONFIG_MEM_STANDALONE: 
+    model_port_types.push_back(CIRCUIT_MODEL_PORT_INPUT);
+    model_port_types.push_back(CIRCUIT_MODEL_PORT_OUTPUT);
+    break;
+  case CONFIG_MEM_SCAN_CHAIN: 
+    model_port_types.push_back(CIRCUIT_MODEL_PORT_INPUT);
+    model_port_types.push_back(CIRCUIT_MODEL_PORT_OUTPUT);
+    break;
+  case CONFIG_MEM_MEMORY_BANK: {
+    std::vector<e_circuit_model_port_type> ports_to_search;
+    ports_to_search.push_back(CIRCUIT_MODEL_PORT_BL);
+    ports_to_search.push_back(CIRCUIT_MODEL_PORT_WL);
+    ports_to_search.push_back(CIRCUIT_MODEL_PORT_BLB);
+    ports_to_search.push_back(CIRCUIT_MODEL_PORT_WLB);
+    /* Try to find a BL/WL/BLB/WLB port and update the port types/module port types to be added */
+    for (const auto& port_to_search : ports_to_search) {
+      std::vector<CircuitPortId> found_port = circuit_lib.model_ports_by_type(sram_model, port_to_search);
+      if (0 == found_port.size()) {
+        continue;
+      }
+      model_port_types.push_back(port_to_search);
+    }
+    break;
+  }
+  default:
+    VTR_LOG_ERROR("Invalid type of SRAM organization !\n");
+    exit(1);
+  }
+
+  /* Add ports to the module manager */
+  for (size_t iport = 0; iport < model_port_types.size(); ++iport) {
+    /* Create a port */
+    std::string port_name = generate_sram_port_name(sram_orgz_type, model_port_types[iport]);
+    sram_port_names.push_back(port_name);
+  }
+
+  return sram_port_names;
+}
+
+/********************************************************************
+ * Generate a list of ports that are used for SRAM configuration to a module
+ * 1. Standalone SRAMs: 
+ *    use the suggested port_size 
+ * 2. Scan-chain Flip-flops:
+ *    IMPORTANT: the port size will be forced to 1 in this case 
+ * 3. Memory decoders:
+ *    use the suggested port_size 
+ ********************************************************************/
+size_t generate_sram_port_size(const e_config_protocol_type sram_orgz_type,
+                               const size_t& num_config_bits) {
+  size_t sram_port_size = num_config_bits;
+
+  switch (sram_orgz_type) {
+  case CONFIG_MEM_STANDALONE: 
+    break;
+  case CONFIG_MEM_SCAN_CHAIN: 
+    /* CCFF head/tail are single-bit ports */
+    sram_port_size = 1;
+    break;
+  case CONFIG_MEM_MEMORY_BANK:
+    break;
+  default:
+    VTR_LOG_ERROR("Invalid type of SRAM organization !\n");
+    exit(1);
+  }
+
+  return sram_port_size;
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/utils/memory_utils.h b/openfpga/src/utils/memory_utils.h
new file mode 100644
index 000000000..1c1eed257
--- /dev/null
+++ b/openfpga/src/utils/memory_utils.h
@@ -0,0 +1,42 @@
+#ifndef MEMORY_UTILS_H
+#define MEMORY_UTILS_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <vector>
+#include "openfpga_port.h"
+#include "circuit_types.h"
+#include "module_manager.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+std::map<std::string, BasicPort> generate_mem_module_port2port_map(const BasicPort& config_bus,
+                                                                   const std::vector<BasicPort>& mem_output_bus_ports,
+                                                                   const e_circuit_model_design_tech& mem_design_tech,
+                                                                   const e_config_protocol_type& sram_orgz_type);
+
+void update_mem_module_config_bus(const e_config_protocol_type& sram_orgz_type,
+                                  const e_circuit_model_design_tech& mem_design_tech,
+                                  const size_t& num_config_bits,
+                                  BasicPort& config_bus);
+
+bool check_mem_config_bus(const e_config_protocol_type& sram_orgz_type, 
+                          const BasicPort& config_bus, 
+                          const size_t& local_expected_msb);
+
+std::vector<std::string> generate_sram_port_names(const CircuitLibrary& circuit_lib,
+                                                  const CircuitModelId& sram_model,
+                                                  const e_config_protocol_type sram_orgz_type);
+
+size_t generate_sram_port_size(const e_config_protocol_type sram_orgz_type,
+                               const size_t& num_config_bits);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/utils/module_manager_utils.cpp b/openfpga/src/utils/module_manager_utils.cpp
new file mode 100644
index 000000000..25a77a752
--- /dev/null
+++ b/openfpga/src/utils/module_manager_utils.cpp
@@ -0,0 +1,1147 @@
+/******************************************************************************
+ * This files includes most utilized functions 
+ * for data structures for module management.
+ ******************************************************************************/
+
+#include <map>
+#include <algorithm>
+
+/* Headers from vtrutil library */
+#include "vtr_log.h"
+#include "vtr_assert.h"
+
+#include "openfpga_naming.h"
+#include "memory_utils.h"
+#include "pb_type_utils.h"
+
+#include "circuit_library_utils.h"
+#include "module_manager_utils.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/******************************************************************************
+ * Add a module to the module manager based on the circuit-level
+ * description of a circuit model
+ * This function add a module with a given customized name
+ * as well as add the ports of circuit model to the module manager
+ ******************************************************************************/
+ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager, 
+                                             const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model,
+                                             const std::string& module_name) {
+  ModuleId module = module_manager.add_module(module_name); 
+  VTR_ASSERT(ModuleId::INVALID() != module);
+
+  /* Add ports */
+  /* Find global ports and add one by one */
+  for (const auto& port : circuit_lib.model_global_ports(circuit_model, false)) {
+    BasicPort port_info(circuit_lib.port_prefix(port), circuit_lib.port_size(port));
+    module_manager.add_port(module, port_info, ModuleManager::MODULE_GLOBAL_PORT);  
+  }
+
+  /* Find other ports and add one by one */
+  /* Create a type-to-type map for ports */
+  std::map<enum e_circuit_model_port_type, ModuleManager::e_module_port_type> port_type2type_map;
+  port_type2type_map[CIRCUIT_MODEL_PORT_INOUT] = ModuleManager::MODULE_INOUT_PORT;
+  port_type2type_map[CIRCUIT_MODEL_PORT_INPUT] = ModuleManager::MODULE_INPUT_PORT;
+  port_type2type_map[CIRCUIT_MODEL_PORT_CLOCK] = ModuleManager::MODULE_INPUT_PORT;
+  port_type2type_map[CIRCUIT_MODEL_PORT_SRAM] = ModuleManager::MODULE_INPUT_PORT;
+  port_type2type_map[CIRCUIT_MODEL_PORT_BL] = ModuleManager::MODULE_INPUT_PORT;
+  port_type2type_map[CIRCUIT_MODEL_PORT_BLB] = ModuleManager::MODULE_INPUT_PORT;
+  port_type2type_map[CIRCUIT_MODEL_PORT_WL] = ModuleManager::MODULE_INPUT_PORT;
+  port_type2type_map[CIRCUIT_MODEL_PORT_WLB] = ModuleManager::MODULE_INPUT_PORT;
+  port_type2type_map[CIRCUIT_MODEL_PORT_OUTPUT] = ModuleManager::MODULE_OUTPUT_PORT;
+
+  /* Input ports (ignore all the global ports when searching the circuit_lib */
+  for (const auto& kv : port_type2type_map) {
+    for (const auto& port : circuit_lib.model_ports_by_type(circuit_model, kv.first, true)) {
+      BasicPort port_info(circuit_lib.port_prefix(port), circuit_lib.port_size(port));
+      module_manager.add_port(module, port_info, kv.second);  
+    }
+  }
+
+  /* Return the new id */
+  return module;
+}
+
+/******************************************************************************
+ * Add a module to the module manager based on the circuit-level
+ * description of a circuit model
+ * This function add a module in the name of the circuit model
+ * as well as add the ports of circuit model to the module manager
+ *
+ * This function is a wrapper of a more customizable function in the same name
+ ******************************************************************************/
+ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager, 
+                                             const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model) {
+ 
+  return add_circuit_model_to_module_manager(module_manager, circuit_lib, circuit_model, circuit_lib.model_name(circuit_model));
+}
+
+/********************************************************************
+ * Add a list of ports that are used for reserved SRAM ports to a module
+ * in the module manager
+ * The reserved SRAM ports are mainly designed for RRAM-based FPGA,
+ * which are shared across modules.
+ * Note that different modules may require different size of reserved
+ * SRAM ports but their LSB must all start from 0 
+ *                                +---------+
+ *    reserved_sram_port[0:X] --->| ModuleA |
+ *                                +---------+
+ *
+ *                                +---------+
+ *    reserved_sram_port[0:Y] --->| ModuleB |
+ *                                +---------+
+ *
+ ********************************************************************/
+void add_reserved_sram_ports_to_module_manager(ModuleManager& module_manager, 
+                                               const ModuleId& module_id,
+                                               const size_t& port_size) {
+  /* Add a reserved BLB port to the module */
+  std::string blb_port_name = generate_reserved_sram_port_name(CIRCUIT_MODEL_PORT_BLB);
+  BasicPort blb_module_port(blb_port_name, port_size); 
+  /* Add generated ports to the ModuleManager */
+  module_manager.add_port(module_id, blb_module_port, ModuleManager::MODULE_INPUT_PORT);
+
+  /* Add a reserved BLB port to the module */
+  std::string wl_port_name = generate_reserved_sram_port_name(CIRCUIT_MODEL_PORT_WL);
+  BasicPort wl_module_port(wl_port_name, port_size); 
+  /* Add generated ports to the ModuleManager */
+  module_manager.add_port(module_id, wl_module_port, ModuleManager::MODULE_INPUT_PORT);
+}
+
+/********************************************************************
+ * Add a list of ports that are used for formal verification to a module
+ * in the module manager
+ *
+ * The formal verification port will appear only when a pre-processing flag is defined
+ * This function will add the pre-processing flag along with the port
+ ********************************************************************/
+void add_formal_verification_sram_ports_to_module_manager(ModuleManager& module_manager, 
+                                                          const ModuleId& module_id,
+                                                          const CircuitLibrary& circuit_lib,
+                                                          const CircuitModelId& sram_model,
+                                                          const std::string& preproc_flag,
+                                                          const size_t& port_size) {
+  /* Create a port */
+  std::string port_name = generate_formal_verification_sram_port_name(circuit_lib, sram_model);
+  BasicPort module_port(port_name, port_size); 
+  /* Add generated ports to the ModuleManager */
+  ModulePortId port_id = module_manager.add_port(module_id, module_port, ModuleManager::MODULE_INPUT_PORT);
+  /* Add pre-processing flag if defined */
+  module_manager.set_port_preproc_flag(module_id, port_id, preproc_flag);
+}
+
+
+/********************************************************************
+ * Add a list of ports that are used for SRAM configuration to a module
+ * in the module manager
+ * The type and names of added ports strongly depend on the 
+ * organization of SRAMs.
+ * 1. Standalone SRAMs: 
+ *    two ports will be added, which are regular output and inverted output 
+ * 2. Scan-chain Flip-flops:
+ *    two ports will be added, which are the head of scan-chain 
+ *    and the tail of scan-chain
+ *    IMPORTANT: the port size will be forced to 1 in this case 
+ *               because the head and tail are both 1-bit ports!!!
+ * 3. Memory decoders:
+ *    2-4 ports will be added, depending on the ports available in the SRAM
+ *    Among these, two ports are mandatory: BL and WL 
+ *    The other two ports are optional: BLB and WLB
+ *    Note that the constraints are correletated to the checking rules 
+ *    in check_circuit_library()
+ ********************************************************************/
+void add_sram_ports_to_module_manager(ModuleManager& module_manager, 
+                                      const ModuleId& module_id,
+                                      const CircuitLibrary& circuit_lib,
+                                      const CircuitModelId& sram_model,
+                                      const e_config_protocol_type sram_orgz_type,
+                                      const size_t& num_config_bits) {
+  std::vector<std::string> sram_port_names = generate_sram_port_names(circuit_lib, sram_model, sram_orgz_type);
+  size_t sram_port_size = generate_sram_port_size(sram_orgz_type, num_config_bits); 
+
+  /* Add ports to the module manager */
+  switch (sram_orgz_type) {
+  case CONFIG_MEM_STANDALONE: 
+  case CONFIG_MEM_MEMORY_BANK: {
+    for (const std::string& sram_port_name : sram_port_names) {
+      /* Add generated ports to the ModuleManager */
+      BasicPort sram_port(sram_port_name, sram_port_size);
+      module_manager.add_port(module_id, sram_port, ModuleManager::MODULE_INPUT_PORT);
+    }
+    break;
+  }
+  case CONFIG_MEM_SCAN_CHAIN: { 
+    /* Note that configuration chain tail is an output while head is an input 
+     * IMPORTANT: this is co-designed with function generate_sram_port_names()
+     * If the return vector is changed, the following codes MUST be adapted!
+     */
+    VTR_ASSERT(2 == sram_port_names.size());
+    size_t port_counter = 0;
+    for (const std::string& sram_port_name : sram_port_names) {
+      /* Add generated ports to the ModuleManager */
+      BasicPort sram_port(sram_port_name, sram_port_size);
+      if (0 == port_counter) { 
+        module_manager.add_port(module_id, sram_port, ModuleManager::MODULE_INPUT_PORT);
+      } else {
+        VTR_ASSERT(1 == port_counter);
+        module_manager.add_port(module_id, sram_port, ModuleManager::MODULE_OUTPUT_PORT);
+      }
+      port_counter++;
+    }
+    break;
+  }
+  default:
+    VTR_LOG_ERROR("Invalid type of SRAM organization !\n");
+    exit(1);
+  }
+}
+
+/********************************************************************
+ * Add ports of a pb_type block to module manager
+ * Port addition will follow the sequence: inout, input, output, clock
+ * This will help use to keep a clean module definition when printing out
+ * To avoid port mismatch between the pb_type and its linked circuit model
+ * This function will also check that each pb_type port is actually exist
+ * in the linked circuit model
+ *******************************************************************/
+void add_primitive_pb_type_ports_to_module_manager(ModuleManager& module_manager, 
+                                                   const ModuleId& module_id,
+                                                   t_pb_type* cur_pb_type,
+                                                   const VprDeviceAnnotation& vpr_device_annotation) {
+   
+  /* Find the inout ports required by the primitive pb_type, and add them to the module */
+  std::vector<t_port*> pb_type_inout_ports = find_pb_type_ports_match_circuit_model_port_type(cur_pb_type, CIRCUIT_MODEL_PORT_INOUT, vpr_device_annotation);
+  for (auto port : pb_type_inout_ports) {
+    BasicPort module_port(generate_pb_type_port_name(port), port->num_pins);
+    module_manager.add_port(module_id, module_port, ModuleManager::MODULE_INOUT_PORT);
+    /* Set the port to be wire-connection */
+    module_manager.set_port_is_wire(module_id, module_port.get_name(), true);
+  }
+
+  /* Find the input ports required by the primitive pb_type, and add them to the module */
+  std::vector<t_port*> pb_type_input_ports = find_pb_type_ports_match_circuit_model_port_type(cur_pb_type, CIRCUIT_MODEL_PORT_INPUT, vpr_device_annotation);
+  for (auto port : pb_type_input_ports) {
+    BasicPort module_port(generate_pb_type_port_name(port), port->num_pins);
+    module_manager.add_port(module_id, module_port, ModuleManager::MODULE_INPUT_PORT);
+    /* Set the port to be wire-connection */
+    module_manager.set_port_is_wire(module_id, module_port.get_name(), true);
+  }
+
+  /* Find the output ports required by the primitive pb_type, and add them to the module */
+  std::vector<t_port*> pb_type_output_ports = find_pb_type_ports_match_circuit_model_port_type(cur_pb_type, CIRCUIT_MODEL_PORT_OUTPUT, vpr_device_annotation);
+  for (auto port : pb_type_output_ports) {
+    BasicPort module_port(generate_pb_type_port_name(port), port->num_pins);
+    module_manager.add_port(module_id, module_port, ModuleManager::MODULE_OUTPUT_PORT);
+    /* Set the port to be wire-connection */
+    module_manager.set_port_is_wire(module_id, module_port.get_name(), true);
+  }
+
+  /* Find the clock ports required by the primitive pb_type, and add them to the module */
+  std::vector<t_port*> pb_type_clock_ports = find_pb_type_ports_match_circuit_model_port_type(cur_pb_type, CIRCUIT_MODEL_PORT_CLOCK, vpr_device_annotation);
+  for (auto port : pb_type_clock_ports) {
+    BasicPort module_port(generate_pb_type_port_name(port), port->num_pins);
+    module_manager.add_port(module_id, module_port, ModuleManager::MODULE_CLOCK_PORT);
+    /* Set the port to be wire-connection */
+    module_manager.set_port_is_wire(module_id, module_port.get_name(), true);
+  }
+}
+
+/********************************************************************
+ * Add ports of a pb_type block to module manager
+ * This function is designed for non-primitive pb_types, which are
+ * NOT linked to any circuit model.
+ * Actually, this makes things much simpler.
+ * We just iterate over all the ports and add it to the module
+ * with the naming convention
+ *******************************************************************/
+void add_pb_type_ports_to_module_manager(ModuleManager& module_manager, 
+                                         const ModuleId& module_id,
+                                         t_pb_type* cur_pb_type) {
+  /* Create a type-to-type mapping between module ports and pb_type ports */
+  std::map<PORTS, ModuleManager::e_module_port_type> port_type2type_map;
+  port_type2type_map[IN_PORT] = ModuleManager::MODULE_INPUT_PORT;
+  port_type2type_map[OUT_PORT] = ModuleManager::MODULE_OUTPUT_PORT;
+  port_type2type_map[INOUT_PORT] = ModuleManager::MODULE_INOUT_PORT;
+
+  for (int port = 0; port < cur_pb_type->num_ports; ++port) {
+    t_port* pb_type_port = &(cur_pb_type->ports[port]);
+    BasicPort module_port(generate_pb_type_port_name(pb_type_port), pb_type_port->num_pins);
+    module_manager.add_port(module_id, module_port, port_type2type_map[pb_type_port->type]);
+    /* Set the port to be wire-connection */
+    module_manager.set_port_is_wire(module_id, module_port.get_name(), true);
+  }
+}
+
+/********************************************************************
+ * Identify if a net is a local wire inside a module: 
+ * A net is a local wire if it connects between two instances,
+ * It means that any of its source and sink modules should not include current module_id
+ *******************************************************************/
+bool module_net_is_local_wire(const ModuleManager& module_manager, 
+                              const ModuleId& module_id, const ModuleNetId& module_net) {
+  /* Check all the sink modules of the net, 
+   * if we have a source module is the current module, this is not local wire 
+   */
+  for (ModuleId src_module : module_manager.net_source_modules(module_id, module_net)) {
+    if (module_id == src_module) {
+      /* Here, this is not a local wire */
+      return false;
+    }
+  }
+
+  /* Check all the sink modules of the net */
+  for (ModuleId sink_module : module_manager.net_sink_modules(module_id, module_net)) {
+    if (module_id == sink_module) {
+      /* Here, this is not a local wire */
+      return false;
+    }
+  }
+
+  return true;
+}
+
+/********************************************************************
+ * Identify if a net is an output short connection inside a module: 
+ * The short connection is defined as the direct connection
+ * between two outputs port of the module
+ *
+ *            module
+ *            +-----------------------------+
+ *                                          |
+ *               src------>+--------------->|--->outputA
+ *                         |                |
+ *                         |                |
+ *                         +--------------->|--->outputB
+ *            +-----------------------------+
+
+ *******************************************************************/
+bool module_net_include_output_short_connection(const ModuleManager& module_manager, 
+                                                const ModuleId& module_id, const ModuleNetId& module_net) {
+  /* Check all the sink modules of the net */
+  size_t contain_num_module_output = 0;
+  for (ModuleId sink_module : module_manager.net_sink_modules(module_id, module_net)) {
+    if (module_id == sink_module) {
+      contain_num_module_output++;
+    }
+  }
+ 
+  /* If we have found more than 1 module outputs, it indicated output short connection! */
+  return (1 < contain_num_module_output);
+}
+
+/********************************************************************
+ * Identify if a net is a local short connection inside a module: 
+ * The short connection is defined as the direct connection
+ * between an input port of the module and an output port of the module
+ *
+ *             module
+ *            +-----------------------------+
+ *            |                             |
+ *  inputA--->|---------------------------->|--->outputB
+ *            |                             |
+ *            |                             |
+ *            |                             |
+ *            +-----------------------------+
+ *******************************************************************/
+bool module_net_include_local_short_connection(const ModuleManager& module_manager, 
+                                               const ModuleId& module_id, const ModuleNetId& module_net) {
+  /* Check all the sink modules of the net, 
+   * if we have a source module is the current module, this is not local wire 
+   */
+  bool contain_module_input = false;
+  for (ModuleId src_module : module_manager.net_source_modules(module_id, module_net)) {
+    if (module_id == src_module) {
+      contain_module_input = true;
+      break;
+    }
+  }
+
+  /* Check all the sink modules of the net */
+  bool contain_module_output = false;
+  for (ModuleId sink_module : module_manager.net_sink_modules(module_id, module_net)) {
+    if (module_id == sink_module) {
+      contain_module_output = true;
+      break;
+    }
+  }
+
+  return contain_module_input & contain_module_output;
+}
+
+/********************************************************************
+ * Add the port-to-port connection between a pb_type and its linked circuit model 
+ * This function is mainly used to create instance of the module for a pb_type
+ *
+ * Note: this function SHOULD be called after the pb_type_module is created
+ * and its child module is created! 
+ *******************************************************************/
+void add_primitive_pb_type_module_nets(ModuleManager& module_manager,
+                                       const ModuleId& pb_type_module,
+                                       const ModuleId& child_module,
+                                       const size_t& child_instance_id,
+                                       const CircuitLibrary& circuit_lib,
+                                       t_pb_type* cur_pb_type,
+                                       const VprDeviceAnnotation& vpr_device_annotation) {
+  for (int iport = 0; iport < cur_pb_type->num_ports; ++iport) {
+    t_port* pb_type_port = &(cur_pb_type->ports[iport]);
+    /* Must have a linked circuit model port */
+    VTR_ASSERT( CircuitPortId::INVALID() != vpr_device_annotation.pb_circuit_port(pb_type_port));
+
+    /* Find the source port in pb_type module */
+    /* Get the src module port id */
+    ModulePortId src_module_port_id = module_manager.find_module_port(pb_type_module, generate_pb_type_port_name(pb_type_port));
+    VTR_ASSERT(ModulePortId::INVALID() != src_module_port_id);
+    BasicPort src_port = module_manager.module_port(pb_type_module, src_module_port_id);
+
+    /* Get the des module port id */
+    std::string des_module_port_name = circuit_lib.port_prefix(vpr_device_annotation.pb_circuit_port(pb_type_port));
+    ModulePortId des_module_port_id = module_manager.find_module_port(child_module, des_module_port_name);
+    VTR_ASSERT(ModulePortId::INVALID() != des_module_port_id);
+    BasicPort des_port = module_manager.module_port(child_module, des_module_port_id);
+
+    /* Port size must match */
+    if (src_port.get_width() != des_port.get_width()) 
+    VTR_ASSERT(src_port.get_width() == des_port.get_width());
+
+    /* For each pin, generate the nets.
+     * For non-output ports (input ports, inout ports and clock ports),
+     * src_port is the source of the net   
+     * For output ports
+     * src_port is the sink of the net
+     */
+    switch (pb_type_port->type) {
+    case IN_PORT:
+    case INOUT_PORT:
+      for (size_t pin_id = 0; pin_id < src_port.pins().size(); ++pin_id) {
+        ModuleNetId net = module_manager.create_module_net(pb_type_module);
+        /* Add net source */
+        module_manager.add_module_net_source(pb_type_module, net, pb_type_module, 0, src_module_port_id, src_port.pins()[pin_id]);
+        /* Add net sink */
+        module_manager.add_module_net_sink(pb_type_module, net, child_module, child_instance_id, des_module_port_id, des_port.pins()[pin_id]);
+      }
+      break;
+    case OUT_PORT: 
+      for (size_t pin_id = 0; pin_id < src_port.pins().size(); ++pin_id) {
+        ModuleNetId net = module_manager.create_module_net(pb_type_module);
+        /* Add net source */
+        module_manager.add_module_net_sink(pb_type_module, net, pb_type_module, 0, src_module_port_id, src_port.pins()[pin_id]);
+        /* Add net sink */
+        module_manager.add_module_net_source(pb_type_module, net, child_module, child_instance_id, des_module_port_id, des_port.pins()[pin_id]);
+      }
+      break;
+    default:
+      VTR_LOG_ERROR("Invalid port of pb_type!\n");
+      exit(1);
+    }
+  } 
+}
+
+/********************************************************************
+ * Add the port-to-port connection between a logic module 
+ * and a memory module 
+ * Create nets to wire SRAM ports between logic module and memory module  
+ *
+ * The information about SRAM ports of logic module are stored in the
+ * mem_output_bus_ports, where element [0] denotes the SRAM port while
+ * element [1] denotes the SRAMb port
+ *
+ *         +---------+                          +--------+
+ *         |         | regular SRAM port        |        |
+ *         |  Logic  |-----------------------+  | Memory |
+ *         | Module  | mode-select SRAM port |->| Module |
+ *         |         |-----------------------+  |        |
+ *         +---------+                          +--------+
+ *
+ * There could be multiple SRAM ports of logic module, which are wired to
+ * the SRAM ports of memory module
+ *
+ * Note: this function SHOULD be called after the pb_type_module is created
+ * and its child module (logic_module and memory_module) is created! 
+ *
+ * Note: this function only handle either SRAM or SRAMb ports.
+ *       So, this function may be called twice to complete the wiring 
+ *******************************************************************/
+static 
+void add_module_nets_between_logic_and_memory_sram_ports(ModuleManager& module_manager,
+                                                         const ModuleId& parent_module,
+                                                         const ModuleId& logic_module,
+                                                         const size_t& logic_instance_id,
+                                                         const ModuleId& memory_module,
+                                                         const size_t& memory_instance_id, 
+                                                         const std::vector<ModulePortId>& logic_module_sram_port_ids,
+                                                         const ModulePortId& mem_module_sram_port_id) {
+  /* Find mem_output_bus ports in logic module */
+  std::vector<BasicPort> logic_module_sram_ports;
+  for (const ModulePortId& logic_module_sram_port_id : logic_module_sram_port_ids) {
+    logic_module_sram_ports.push_back(module_manager.module_port(logic_module, logic_module_sram_port_id));
+  }
+ 
+  /* Create a list of virtual ports to align with the SRAM port of logic module
+   * Physical ports:
+   *
+   *      logic_module_sram_port[0]   logic_module_sram_port[1]
+   *
+   *      LSB[0]------------>MSB[0]   LSB------------------>MSB 
+   *
+   *      memory_sram_port
+   *      LSBY---------------------------------------------->MSBY  
+   *
+   * Virtual ports:
+   *      mem_module_sram_port[0]     mem_module_sram_port[1]
+   *      LSBY--------------->MSBX    MSBX+1------------------>MSBY 
+   *
+   */
+  BasicPort mem_module_port = module_manager.module_port(memory_module, mem_module_sram_port_id);
+  std::vector<BasicPort> virtual_mem_module_ports;
+
+  /* Create a counter for the LSB of virtual ports */
+  size_t port_lsb = 0;
+  for (const BasicPort& logic_module_sram_port : logic_module_sram_ports) {
+    BasicPort virtual_port;
+    virtual_port.set_name(mem_module_port.get_name());
+    virtual_port.set_width(port_lsb, port_lsb + logic_module_sram_port.get_width() - 1);
+    virtual_mem_module_ports.push_back(virtual_port);
+    port_lsb = virtual_port.get_msb() + 1;
+  }
+  /* port_lsb should be aligned with the MSB of memory_sram_port */
+  VTR_ASSERT(port_lsb == mem_module_port.get_msb() + 1);
+
+  /* Wire port to port */
+  for (size_t port_index = 0; port_index < logic_module_sram_ports.size(); ++port_index) {
+    /* Create a net for each pin */
+    for (size_t pin_id = 0; pin_id < logic_module_sram_ports[port_index].pins().size(); ++pin_id) {
+      ModuleNetId net = module_manager.create_module_net(parent_module);
+      /* TODO: Give a name to make it clear */
+      std::string net_name = module_manager.module_name(logic_module) + std::string("_") + std::to_string(logic_instance_id) + std::string("_") + logic_module_sram_ports[port_index].get_name();
+      module_manager.set_net_name(parent_module, net, net_name);
+      /* Add net source */
+      module_manager.add_module_net_source(parent_module, net, logic_module, logic_instance_id, logic_module_sram_port_ids[port_index], logic_module_sram_ports[port_index].pins()[pin_id]);
+      /* Add net sink */
+      module_manager.add_module_net_sink(parent_module, net, memory_module, memory_instance_id, mem_module_sram_port_id, virtual_mem_module_ports[port_index].pins()[pin_id]);
+    }
+  }
+}
+
+/********************************************************************
+ * Add the port-to-port connection between a logic module 
+ * and a memory module 
+ * Create nets to wire SRAM ports between logic module and memory module  
+ *
+ *
+ *         +---------+                        +--------+
+ *         |         |  SRAM ports            |        |
+ *         |  Logic  |----------------------->| Memory |
+ *         | Module  |  SRAMb ports           | Module |
+ *         |         |----------------------->|        |
+ *         +---------+                        +--------+
+ *
+ * Note: this function SHOULD be called after the pb_type_module is created
+ * and its child module (logic_module and memory_module) is created! 
+ *
+ *******************************************************************/
+void add_module_nets_between_logic_and_memory_sram_bus(ModuleManager& module_manager,
+                                                       const ModuleId& parent_module,
+                                                       const ModuleId& logic_module,
+                                                       const size_t& logic_instance_id,
+                                                       const ModuleId& memory_module,
+                                                       const size_t& memory_instance_id, 
+                                                       const CircuitLibrary& circuit_lib,
+                                                       const CircuitModelId& logic_model) {
+
+  /* Connect SRAM port */
+  /* Find SRAM ports in the circuit model for logic module */
+  std::vector<std::string> logic_model_sram_port_names;
+  /* Regular sram port goes first */
+  for (CircuitPortId regular_sram_port : find_circuit_regular_sram_ports(circuit_lib, logic_model)) {
+    logic_model_sram_port_names.push_back(circuit_lib.port_prefix(regular_sram_port));
+  }
+  /* Mode-select sram port goes first */
+  for (CircuitPortId mode_select_sram_port : find_circuit_mode_select_sram_ports(circuit_lib, logic_model)) {
+    logic_model_sram_port_names.push_back(circuit_lib.port_prefix(mode_select_sram_port));
+  }
+  /* Find the port ids in the memory */
+  std::vector<ModulePortId> logic_module_sram_port_ids;
+  for (const std::string& logic_model_sram_port_name : logic_model_sram_port_names) {
+    /* Skip non-exist ports */
+    if (ModulePortId::INVALID() == module_manager.find_module_port(logic_module, logic_model_sram_port_name)) {
+      continue;
+    }
+    logic_module_sram_port_ids.push_back(module_manager.find_module_port(logic_module, logic_model_sram_port_name));
+  }
+
+  /* Get the SRAM port name of memory model */
+  /* TODO: this should be a constant expression and it should be the same for all the memory module! */
+  std::string memory_model_sram_port_name = generate_configuration_chain_data_out_name();
+  /* Find the corresponding ports in memory module */ 
+  ModulePortId mem_module_sram_port_id = module_manager.find_module_port(memory_module, memory_model_sram_port_name);
+
+  /* Do wiring only when we have sram ports */
+  if ( (false == logic_module_sram_port_ids.empty())
+    || (ModulePortId::INVALID() == mem_module_sram_port_id) ) {
+    add_module_nets_between_logic_and_memory_sram_ports(module_manager, parent_module, 
+                                                        logic_module, logic_instance_id,
+                                                        memory_module, memory_instance_id,
+                                                        logic_module_sram_port_ids, mem_module_sram_port_id);
+  }
+
+  /* Connect SRAMb port */
+  /* Find SRAM ports in the circuit model for logic module */
+  std::vector<std::string> logic_model_sramb_port_names;
+  /* Regular sram port goes first */
+  for (CircuitPortId regular_sram_port : find_circuit_regular_sram_ports(circuit_lib, logic_model)) {
+    logic_model_sramb_port_names.push_back(circuit_lib.port_prefix(regular_sram_port) + std::string("_inv"));
+  }
+  /* Mode-select sram port goes first */
+  for (CircuitPortId mode_select_sram_port : find_circuit_mode_select_sram_ports(circuit_lib, logic_model)) {
+    logic_model_sramb_port_names.push_back(circuit_lib.port_prefix(mode_select_sram_port) + std::string("_inv"));
+  }
+  /* Find the port ids in the memory */
+  std::vector<ModulePortId> logic_module_sramb_port_ids;
+  for (const std::string& logic_model_sramb_port_name : logic_model_sramb_port_names) {
+    /* Skip non-exist ports */
+    if (ModulePortId::INVALID() == module_manager.find_module_port(logic_module, logic_model_sramb_port_name)) {
+      continue;
+    }
+    logic_module_sramb_port_ids.push_back(module_manager.find_module_port(logic_module, logic_model_sramb_port_name));
+  }
+
+  /* Get the SRAM port name of memory model */
+  std::string memory_model_sramb_port_name = generate_configuration_chain_inverted_data_out_name();
+  /* Find the corresponding ports in memory module */ 
+  ModulePortId mem_module_sramb_port_id = module_manager.find_module_port(memory_module, memory_model_sramb_port_name);
+
+  /* Do wiring only when we have sramb ports */
+  if ( (false == logic_module_sramb_port_ids.empty())
+    || (ModulePortId::INVALID() == mem_module_sramb_port_id) ) {
+    add_module_nets_between_logic_and_memory_sram_ports(module_manager, parent_module, 
+                                                        logic_module, logic_instance_id,
+                                                        memory_module, memory_instance_id,
+                                                        logic_module_sramb_port_ids, mem_module_sramb_port_id);
+  }
+}
+
+/********************************************************************
+ * Connect all the memory modules under the parent module in a chain
+ * 
+ *                +--------+    +--------+            +--------+
+ *  ccff_head --->| Memory |--->| Memory |--->... --->| Memory |----> ccff_tail
+ *                | Module |    | Module |            | Module |
+ *                |   [0]  |    |   [1]  |            |  [N-1] |             
+ *                +--------+    +--------+            +--------+
+ *  For the 1st memory module:
+ *    net source is the configuration chain head of the primitive module
+ *    net sink is the configuration chain head of the next memory module
+ *
+ *  For the rest of memory modules:
+ *    net source is the configuration chain tail of the previous memory module
+ *    net sink is the configuration chain head of the next memory module
+ *********************************************************************/
+void add_module_nets_cmos_memory_chain_config_bus(ModuleManager& module_manager,
+                                                  const ModuleId& parent_module,
+                                                  const e_config_protocol_type& sram_orgz_type) {
+  for (size_t mem_index = 0; mem_index < module_manager.configurable_children(parent_module).size(); ++mem_index) {
+    ModuleId net_src_module_id;
+    size_t net_src_instance_id;
+    ModulePortId net_src_port_id;
+
+    ModuleId net_sink_module_id;
+    size_t net_sink_instance_id;
+    ModulePortId net_sink_port_id;
+
+    if (0 == mem_index) {
+      /* Find the port name of configuration chain head */
+      std::string src_port_name = generate_sram_port_name(sram_orgz_type, CIRCUIT_MODEL_PORT_INPUT);
+      net_src_module_id = parent_module; 
+      net_src_instance_id = 0;
+      net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name); 
+
+      /* Find the port name of next memory module */
+      std::string sink_port_name = generate_configuration_chain_head_name();
+      net_sink_module_id = module_manager.configurable_children(parent_module)[mem_index]; 
+      net_sink_instance_id = module_manager.configurable_child_instances(parent_module)[mem_index];
+      net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name); 
+    } else {
+      /* Find the port name of previous memory module */
+      std::string src_port_name = generate_configuration_chain_tail_name();
+      net_src_module_id = module_manager.configurable_children(parent_module)[mem_index - 1]; 
+      net_src_instance_id = module_manager.configurable_child_instances(parent_module)[mem_index - 1];
+      net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name); 
+
+      /* Find the port name of next memory module */
+      std::string sink_port_name = generate_configuration_chain_head_name();
+      net_sink_module_id = module_manager.configurable_children(parent_module)[mem_index]; 
+      net_sink_instance_id = module_manager.configurable_child_instances(parent_module)[mem_index];
+      net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name); 
+    }
+
+    /* Get the pin id for source port */
+    BasicPort net_src_port = module_manager.module_port(net_src_module_id, net_src_port_id); 
+    /* Get the pin id for sink port */
+    BasicPort net_sink_port = module_manager.module_port(net_sink_module_id, net_sink_port_id); 
+    /* Port sizes of source and sink should match */
+    VTR_ASSERT(net_src_port.get_width() == net_sink_port.get_width());
+    
+    /* Create a net for each pin */
+    for (size_t pin_id = 0; pin_id < net_src_port.pins().size(); ++pin_id) {
+      /* Create a net and add source and sink to it */
+      ModuleNetId net = module_manager.create_module_net(parent_module);
+      /* Add net source */
+      module_manager.add_module_net_source(parent_module, net, net_src_module_id, net_src_instance_id, net_src_port_id, net_src_port.pins()[pin_id]);
+      /* Add net sink */
+      module_manager.add_module_net_sink(parent_module, net, net_sink_module_id, net_sink_instance_id, net_sink_port_id, net_sink_port.pins()[pin_id]);
+    }
+  }
+
+  /* For the last memory module:
+   *    net source is the configuration chain tail of the previous memory module
+   *    net sink is the configuration chain tail of the primitive module
+   */
+  /* Find the port name of previous memory module */
+  std::string src_port_name = generate_configuration_chain_tail_name();
+  ModuleId net_src_module_id = module_manager.configurable_children(parent_module).back(); 
+  size_t net_src_instance_id = module_manager.configurable_child_instances(parent_module).back();
+  ModulePortId net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name); 
+
+  /* Find the port name of next memory module */
+  std::string sink_port_name = generate_sram_port_name(sram_orgz_type, CIRCUIT_MODEL_PORT_OUTPUT);
+  ModuleId net_sink_module_id = parent_module; 
+  size_t net_sink_instance_id = 0;
+  ModulePortId net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name); 
+
+  /* Get the pin id for source port */
+  BasicPort net_src_port = module_manager.module_port(net_src_module_id, net_src_port_id); 
+  /* Get the pin id for sink port */
+  BasicPort net_sink_port = module_manager.module_port(net_sink_module_id, net_sink_port_id); 
+  /* Port sizes of source and sink should match */
+  VTR_ASSERT(net_src_port.get_width() == net_sink_port.get_width());
+  
+  /* Create a net for each pin */
+  for (size_t pin_id = 0; pin_id < net_src_port.pins().size(); ++pin_id) {
+    /* Create a net and add source and sink to it */
+    ModuleNetId net = module_manager.create_module_net(parent_module);
+    /* Add net source */
+    module_manager.add_module_net_source(parent_module, net, net_src_module_id, net_src_instance_id, net_src_port_id, net_src_port.pins()[pin_id]);
+    /* Add net sink */
+    module_manager.add_module_net_sink(parent_module, net, net_sink_module_id, net_sink_instance_id, net_sink_port_id, net_sink_port.pins()[pin_id]);
+  }
+}
+
+/*********************************************************************
+ * Add the port-to-port connection between all the memory modules 
+ * and their parent module
+ *
+ * Create nets to wire the control signals of memory module to 
+ *    the configuration ports of primitive module
+ *
+ * Configuration Chain 
+ * -------------------
+ *
+ *        config_bus (head)   config_bus (tail) 
+ *            |                   ^
+ * primitive  |                   |
+ *   +---------------------------------------------+
+ *   |        |                   |                |
+ *   |        v                   |                |
+ *   |  +-------------------------------------+    |
+ *   |  |        CMOS-based Memory Modules    |    |
+ *   |  +-------------------------------------+    |
+ *   |        |                   |                |
+ *   |        v                   v                |
+ *   |     sram_out             sram_outb          |
+ *   |                                             |
+ *   +---------------------------------------------+
+ *
+ * Memory bank 
+ * -----------
+ *
+ *        config_bus (BL)   config_bus (WL) 
+ *            |                   |
+ * primitive  |                   |
+ *   +---------------------------------------------+
+ *   |        |                   |                |
+ *   |        v                   v                |
+ *   |  +-------------------------------------+    |
+ *   |  |        CMOS-based Memory Modules    |    |
+ *   |  +-------------------------------------+    |
+ *   |        |                   |                |
+ *   |        v                   v                |
+ *   |     sram_out             sram_outb          |
+ *   |                                             |
+ *   +---------------------------------------------+
+ *
+ **********************************************************************/
+static 
+void add_module_nets_cmos_memory_config_bus(ModuleManager& module_manager,
+                                            const ModuleId& parent_module,
+                                            const e_config_protocol_type& sram_orgz_type) {
+  switch (sram_orgz_type) {
+  case CONFIG_MEM_STANDALONE:
+    /* Nothing to do */
+    break;
+  case CONFIG_MEM_SCAN_CHAIN: {
+    add_module_nets_cmos_memory_chain_config_bus(module_manager, parent_module, sram_orgz_type);
+    break;
+  }
+  case CONFIG_MEM_MEMORY_BANK:
+    /* TODO: */
+    break;
+  default:
+    VTR_LOG_ERROR("Invalid type of SRAM organization!\n");
+    exit(1);
+  }
+}
+
+/*********************************************************************
+ * TODO:
+ * Add the port-to-port connection between a logic module 
+ * and a memory module inside a primitive module
+ *
+ * Memory bank 
+ * -----------
+ *        config_bus (BL)   config_bus (WL) shared_config_bugs(shared_BL/WLs) 
+ *            |                   |              |        |
+ * primitive  |                   |              |        |
+ *   +------------------------------------------------------------+
+ *   |        |                   |              |        |       |
+ *   |        v                   v              v        v       |
+ *   |  +----------------------------------------------------+    |
+ *   |  |              ReRAM-based Memory Module             |    |
+ *   |  +----------------------------------------------------+    |
+ *   |        |                   |                               |
+ *   |        v                   v                               |
+ *   |      mem_out              mem_outb                         |
+ *   |                                                            |
+ *   +------------------------------------------------------------+
+ *
+ **********************************************************************/
+
+/********************************************************************
+ * TODO:
+ * Add the port-to-port connection between a memory module 
+ * and the configuration bus of a primitive module
+ *
+ * Create nets to wire the control signals of memory module to 
+ *    the configuration ports of primitive module
+ *
+ *              Primitive module
+ *             +----------------------------+
+ *             |                +--------+  |
+ *  config     |                |        |  |
+ *   ports --->|--------------->| Memory |  |
+ *             |                | Module |  |
+ *             |                |        |  |
+ *             |                +--------+  |
+ *             +----------------------------+
+ *     The detailed config ports really depend on the type
+ *     of SRAM organization. 
+ *
+ * The config_bus in the argument is the reserved address of configuration
+ * bus in the parent_module for this memory module
+ *
+ * The configuration bus connection will depend not only 
+ * the design technology of the memory cells but also the 
+ * configuration styles of FPGA fabric.
+ * Here we will branch on the design technology
+ *
+ * Note: this function SHOULD be called after the pb_type_module is created
+ * and its child module (logic_module and memory_module) is created! 
+ *******************************************************************/
+void add_module_nets_memory_config_bus(ModuleManager& module_manager,
+                                       const ModuleId& parent_module,
+                                       const e_config_protocol_type& sram_orgz_type, 
+                                       const e_circuit_model_design_tech& mem_tech) {
+  switch (mem_tech) {
+  case CIRCUIT_MODEL_DESIGN_CMOS:
+    add_module_nets_cmos_memory_config_bus(module_manager, parent_module, 
+                                           sram_orgz_type);
+    break;
+  case CIRCUIT_MODEL_DESIGN_RRAM:
+    /* TODO: */
+    break;
+  default:
+    VTR_LOG_ERROR("Invalid type of memory design technology !\n");
+    exit(1);
+  }
+}
+
+/********************************************************************
+ * Find the size of shared(reserved) configuration ports for module 
+ *******************************************************************/
+size_t find_module_num_shared_config_bits(const ModuleManager& module_manager,
+                                          const ModuleId& module_id) {
+  std::vector<std::string> shared_config_port_names;
+  shared_config_port_names.push_back(generate_reserved_sram_port_name(CIRCUIT_MODEL_PORT_BLB));
+  shared_config_port_names.push_back(generate_reserved_sram_port_name(CIRCUIT_MODEL_PORT_WL));
+  size_t num_shared_config_bits = 0; /* By default it has zero configuration bits*/
+
+  /* Try to find these ports in the module manager */
+  for (const std::string& shared_config_port_name : shared_config_port_names) {
+    ModulePortId module_port_id = module_manager.find_module_port(module_id, shared_config_port_name);
+    /* If the port does not exist, go to the next */
+    if (false == module_manager.valid_module_port_id(module_id, module_port_id)) {
+      continue;
+    }
+    /* The port exist, find the port size and update the num_config_bits if the size is larger */
+    BasicPort module_port = module_manager.module_port(module_id, module_port_id);
+    num_shared_config_bits = std::max((int)num_shared_config_bits, (int)module_port.get_width());
+  }
+
+  return num_shared_config_bits;
+}
+
+/********************************************************************
+ * Find the size of configuration ports for module 
+ *******************************************************************/
+size_t find_module_num_config_bits(const ModuleManager& module_manager,
+                                   const ModuleId& module_id,
+                                   const CircuitLibrary& circuit_lib,
+                                   const CircuitModelId& sram_model,
+                                   const e_config_protocol_type& sram_orgz_type) {
+  std::vector<std::string> config_port_names = generate_sram_port_names(circuit_lib, sram_model, sram_orgz_type);
+  size_t num_config_bits = 0; /* By default it has zero configuration bits*/
+
+  /* Try to find these ports in the module manager */
+  for (const std::string& config_port_name : config_port_names) {
+    ModulePortId module_port_id = module_manager.find_module_port(module_id, config_port_name);
+    /* If the port does not exist, go to the next */
+    if (false == module_manager.valid_module_port_id(module_id, module_port_id)) {
+      continue;
+    }
+    /* The port exist, find the port size and update the num_config_bits if the size is larger */
+    BasicPort module_port = module_manager.module_port(module_id, module_port_id);
+    num_config_bits = std::max((int)num_config_bits, (int)module_port.get_width());
+  }
+
+  return num_config_bits;
+}
+
+/********************************************************************
+ * Add GPIO ports to the module:
+ * In this function, the following tasks are done: 
+ * 1. find all the GPIO ports from the child modules and build a list of it,
+ * 2. Merge all the GPIO ports with the same name
+ * 3. add the ports to the pb_module
+ * 4. add module nets to connect to the GPIO ports of each sub module 
+ *
+ * Note: This function should be call ONLY after all the sub modules (instances)
+ * have been added to the pb_module!
+ * Otherwise, some GPIO ports of the sub modules may be missed!
+ *******************************************************************/
+void add_module_gpio_ports_from_child_modules(ModuleManager& module_manager, 
+                                              const ModuleId& module_id) {
+  std::vector<BasicPort> gpio_ports_to_add;
+
+  /* Iterate over the child modules */
+  for (const ModuleId& child : module_manager.child_modules(module_id)) {
+    /* Iterate over the child instances */
+    for (size_t i = 0; i < module_manager.num_instance(module_id, child); ++i) {
+      /* Find all the global ports, whose port type is special */
+      for (BasicPort gpio_port : module_manager.module_ports_by_type(child, ModuleManager::MODULE_GPIO_PORT)) {
+        /* If this port is not mergeable, we update the list */
+        bool is_mergeable = false;
+        for (BasicPort& gpio_port_to_add : gpio_ports_to_add) {
+          if (false == gpio_port_to_add.mergeable(gpio_port)) {
+            continue;
+          }
+          is_mergeable = true;
+          /* For mergeable ports, we combine the port
+           * Note: do NOT use the merge() method!
+           * the GPIO ports should be accumulated by the sizes of ports
+           * not by the LSB/MSB range !!! 
+           */
+          gpio_port_to_add.combine(gpio_port);
+          break;
+        }
+        if (false == is_mergeable) {
+          /* Reach here, this is an unique gpio port, update the list */
+          gpio_ports_to_add.push_back(gpio_port);
+        }
+      }
+    }
+  } 
+
+  /* Record the port id for each type of GPIO port */
+  std::vector<ModulePortId> gpio_port_ids;
+  /* Add the gpio ports for the module */
+  for (const BasicPort& gpio_port_to_add : gpio_ports_to_add) {
+    ModulePortId port_id = module_manager.add_port(module_id, gpio_port_to_add, ModuleManager::MODULE_GPIO_PORT);
+    gpio_port_ids.push_back(port_id);
+  } 
+
+  /* Set up a counter for each type of GPIO port */
+  std::vector<size_t> gpio_port_lsb(gpio_ports_to_add.size(), 0);
+  /* Add module nets to connect the GPIOs of the module to the GPIOs of the sub module */
+  for (const ModuleId& child : module_manager.child_modules(module_id)) {
+    /* Iterate over the child instances */
+    for (const size_t& child_instance : module_manager.child_module_instances(module_id, child)) {
+      /* Find all the global ports, whose port type is special */
+      for (ModulePortId child_gpio_port_id : module_manager.module_port_ids_by_type(child, ModuleManager::MODULE_GPIO_PORT)) {
+        BasicPort child_gpio_port = module_manager.module_port(child, child_gpio_port_id);
+        /* Find the port with the same name! */
+        for (size_t iport = 0; iport < gpio_ports_to_add.size(); ++iport) {
+          if (false == gpio_ports_to_add[iport].mergeable(child_gpio_port)) {
+            continue;
+          }
+          /* For each pin of the child port, create a net and do wiring */
+          for (const size_t& pin_id : child_gpio_port.pins()) {
+            /* Reach here, it means this is the port we want, create a net and configure its source and sink */
+            ModuleNetId net = module_manager.create_module_net(module_id);
+            module_manager.add_module_net_source(module_id, net, module_id, 0, gpio_port_ids[iport], gpio_port_lsb[iport]); 
+            module_manager.add_module_net_sink(module_id, net, child, child_instance, child_gpio_port_id, pin_id); 
+            /* Update the LSB counter */
+            gpio_port_lsb[iport]++;
+          }
+          /* We finish for this child gpio port */
+          break;
+        }
+      }
+    }
+  }
+
+  /* Check: all the lsb should now match the size of each GPIO port */
+  for (size_t iport = 0; iport < gpio_ports_to_add.size(); ++iport) {
+    if (gpio_ports_to_add[iport].get_width() != gpio_port_lsb[iport]) 
+    VTR_ASSERT(gpio_ports_to_add[iport].get_width() == gpio_port_lsb[iport]);
+  }
+}
+
+/********************************************************************
+ * Add global ports to the module:
+ * In this function, the following tasks are done: 
+ * 1. find all the global ports from the child modules and build a list of it,
+ * 2. add the ports to the pb_module
+ * 3. add the module nets to connect the pb_module global ports to those of child modules
+ *
+ * Note: This function should be call ONLY after all the sub modules (instances)
+ * have been added to the pb_module!
+ * Otherwise, some global ports of the sub modules may be missed!
+ *******************************************************************/
+void add_module_global_ports_from_child_modules(ModuleManager& module_manager, 
+                                                const ModuleId& module_id) {
+  std::vector<BasicPort> global_ports_to_add;
+
+  /* Iterate over the child modules */
+  for (const ModuleId& child : module_manager.child_modules(module_id)) {
+    /* Iterate over the child instances */
+    for (size_t i = 0; i < module_manager.num_instance(module_id, child); ++i) {
+      /* Find all the global ports, whose port type is special */
+      for (BasicPort global_port : module_manager.module_ports_by_type(child, ModuleManager::MODULE_GLOBAL_PORT)) {
+        /* Search in the global port list to be added, if this is unique, we update the list */
+        std::vector<BasicPort>::iterator it = std::find(global_ports_to_add.begin(), global_ports_to_add.end(), global_port);
+        if (it != global_ports_to_add.end()) {
+          continue;
+        }
+        /* Reach here, this is an unique global port, update the list */
+        global_ports_to_add.push_back(global_port);
+      }
+    }
+  } 
+
+  /* Record the port id for each type of global port */
+  std::vector<ModulePortId> global_port_ids;
+  /* Add the global ports for the module */
+  for (const BasicPort& global_port_to_add : global_ports_to_add) {
+    ModulePortId port_id = module_manager.add_port(module_id, global_port_to_add, ModuleManager::MODULE_GLOBAL_PORT);
+    global_port_ids.push_back(port_id);
+  } 
+
+  /* Add module nets to connect the global ports of the module to the global ports of the sub module */
+  /* Iterate over the child modules */
+  for (const ModuleId& child : module_manager.child_modules(module_id)) {
+    /* Iterate over the child instances */
+    for (const size_t& child_instance : module_manager.child_module_instances(module_id, child)) {
+      /* Find all the global ports, whose port type is special */
+      for (ModulePortId child_global_port_id : module_manager.module_port_ids_by_type(child, ModuleManager::MODULE_GLOBAL_PORT)) {
+        BasicPort child_global_port = module_manager.module_port(child, child_global_port_id);
+        /* Search in the global port list to be added, find the port id */
+        std::vector<BasicPort>::iterator it = std::find(global_ports_to_add.begin(), global_ports_to_add.end(), child_global_port);
+        VTR_ASSERT(it != global_ports_to_add.end());
+        ModulePortId module_global_port_id = global_port_ids[it - global_ports_to_add.begin()];
+        BasicPort module_global_port = module_manager.module_port(module_id, module_global_port_id);
+        /* The global ports should match in size */
+        VTR_ASSERT(module_global_port.get_width() == child_global_port.get_width());
+        /* For each pin of the child port, create a net and do wiring */
+        for (size_t pin_id = 0; pin_id < child_global_port.pins().size(); ++pin_id) {
+          /* Reach here, it means this is the port we want, create a net and configure its source and sink */
+          ModuleNetId net = module_manager.create_module_net(module_id);
+          module_manager.add_module_net_source(module_id, net, module_id, 0, module_global_port_id, module_global_port.pins()[pin_id]); 
+          module_manager.add_module_net_sink(module_id, net, child, child_instance, child_global_port_id, child_global_port.pins()[pin_id]); 
+          /* We finish for this child gpio port */
+        }
+      }
+    }
+  } 
+}
+
+/********************************************************************
+ * Find the number of shared configuration bits for a module 
+ * by selected the maximum number of shared configuration bits of child modules
+ *
+ * Note: This function should be call ONLY after all the sub modules (instances)
+ * have been added to the pb_module!
+ * Otherwise, some global ports of the sub modules may be missed!
+ *******************************************************************/
+size_t find_module_num_shared_config_bits_from_child_modules(ModuleManager& module_manager, 
+                                                             const ModuleId& module_id) {
+  size_t num_shared_config_bits = 0;
+
+  /* Iterate over the child modules */
+  for (const ModuleId& child : module_manager.child_modules(module_id)) {
+    num_shared_config_bits = std::max((int)num_shared_config_bits, (int)find_module_num_shared_config_bits(module_manager, child));
+  } 
+
+  return num_shared_config_bits;
+}
+
+/********************************************************************
+ * Find the number of configuration bits for a module 
+ * by summing up the number of configuration bits of child modules
+ *
+ * Note: This function should be call ONLY after all the sub modules (instances)
+ * have been added to the pb_module!
+ * Otherwise, some global ports of the sub modules may be missed!
+ *******************************************************************/
+size_t find_module_num_config_bits_from_child_modules(ModuleManager& module_manager, 
+                                                      const ModuleId& module_id,
+                                                      const CircuitLibrary& circuit_lib,
+                                                      const CircuitModelId& sram_model,
+                                                      const e_config_protocol_type& sram_orgz_type) {
+  size_t num_config_bits = 0;
+
+  /* Iterate over the child modules */
+  for (const ModuleId& child : module_manager.child_modules(module_id)) {
+    num_config_bits += find_module_num_config_bits(module_manager, child, circuit_lib, sram_model, sram_orgz_type);
+  } 
+
+  return num_config_bits;
+}
+
+
+/********************************************************************
+ * TODO:
+ * Add the port-to-port connection between a logic module 
+ * and a memory module inside a primitive module
+ *
+ * Create nets to wire the formal verification ports of 
+ * primitive module to SRAM ports of logic module 
+ * 
+ *    Primitive module
+ *
+ *                     formal_port_sram
+ *    +-----------------------------------------------+
+ *    |                       ^                       |
+ *    |    +---------+        |    +--------+         |
+ *    |    |         | SRAM   |    |        |         |
+ *    |    |  Logic  |--------+--->| Memory |         |
+ *    |    | Module  | SRAMb       | Module |         |
+ *    |    |         |--------+--->|        |         |
+ *    |    +---------+        |    +--------+         |
+ *    |                       v                       |
+ *    +-----------------------------------------------+
+ *                     formal_port_sramb
+ *
+ *******************************************************************/
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/utils/module_manager_utils.h b/openfpga/src/utils/module_manager_utils.h
new file mode 100644
index 000000000..6198701ad
--- /dev/null
+++ b/openfpga/src/utils/module_manager_utils.h
@@ -0,0 +1,128 @@
+/******************************************************************************
+ * This files includes declarations for most utilized functions 
+ * for data structures for module management.
+ ******************************************************************************/
+#ifndef MODULE_MANAGER_UTILS_H
+#define MODULE_MANAGER_UTILS_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <vector>
+
+/* Headers from readarch library */
+#include "physical_types.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_port.h"
+
+/* Headers from readarchopenfpga library */
+#include "circuit_types.h"
+#include "circuit_library.h"
+
+#include "module_manager.h"
+#include "vpr_device_annotation.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager, 
+                                             const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model,
+                                             const std::string& module_name);
+
+ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager, 
+                                             const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model);
+
+void add_reserved_sram_ports_to_module_manager(ModuleManager& module_manager, 
+                                               const ModuleId& module_id,
+                                               const size_t& port_size);
+
+void add_formal_verification_sram_ports_to_module_manager(ModuleManager& module_manager, 
+                                                          const ModuleId& module_id,
+                                                          const CircuitLibrary& circuit_lib,
+                                                          const CircuitModelId& sram_model,
+                                                          const std::string& preproc_flag,
+                                                          const size_t& port_size);
+
+void add_sram_ports_to_module_manager(ModuleManager& module_manager, 
+                                      const ModuleId& module_id,
+                                      const CircuitLibrary& circuit_lib,
+                                      const CircuitModelId& sram_model,
+                                      const e_config_protocol_type sram_orgz_type,
+                                      const size_t& num_config_bits);
+
+void add_primitive_pb_type_ports_to_module_manager(ModuleManager& module_manager, 
+                                                   const ModuleId& module_id,
+                                                   t_pb_type* cur_pb_type,
+                                                   const VprDeviceAnnotation& vpr_device_annotation);
+
+void add_pb_type_ports_to_module_manager(ModuleManager& module_manager, 
+                                         const ModuleId& module_id,
+                                         t_pb_type* cur_pb_type);
+
+bool module_net_is_local_wire(const ModuleManager& module_manager, 
+                              const ModuleId& module_id, const ModuleNetId& module_net);
+
+bool module_net_include_output_short_connection(const ModuleManager& module_manager, 
+                                                const ModuleId& module_id, const ModuleNetId& module_net);
+
+bool module_net_include_local_short_connection(const ModuleManager& module_manager, 
+                                               const ModuleId& module_id, const ModuleNetId& module_net);
+
+void add_primitive_pb_type_module_nets(ModuleManager& module_manager,
+                                       const ModuleId& pb_type_module,
+                                       const ModuleId& child_module,
+                                       const size_t& child_instance_id,
+                                       const CircuitLibrary& circuit_lib,
+                                       t_pb_type* cur_pb_type,
+                                       const VprDeviceAnnotation& vpr_device_annotation);
+
+void add_module_nets_between_logic_and_memory_sram_bus(ModuleManager& module_manager,
+                                                       const ModuleId& parent_module,
+                                                       const ModuleId& logic_module,
+                                                       const size_t& logic_instance_id,
+                                                       const ModuleId& memory_module,
+                                                       const size_t& memory_instance_id, 
+                                                       const CircuitLibrary& circuit_lib,
+                                                       const CircuitModelId& logic_model);
+
+void add_module_nets_cmos_memory_chain_config_bus(ModuleManager& module_manager,
+                                                  const ModuleId& parent_module,
+                                                  const e_config_protocol_type& sram_orgz_type);
+
+void add_module_nets_memory_config_bus(ModuleManager& module_manager,
+                                       const ModuleId& parent_module,
+                                       const e_config_protocol_type& sram_orgz_type, 
+                                       const e_circuit_model_design_tech& mem_tech);
+
+size_t find_module_num_shared_config_bits(const ModuleManager& module_manager,
+                                          const ModuleId& module_id);
+
+size_t find_module_num_config_bits(const ModuleManager& module_manager,
+                                   const ModuleId& module_id,
+                                   const CircuitLibrary& circuit_lib,
+                                   const CircuitModelId& sram_model,
+                                   const e_config_protocol_type& sram_orgz_type);
+
+void add_module_global_ports_from_child_modules(ModuleManager& module_manager, 
+                                                const ModuleId& module_id);
+
+void add_module_gpio_ports_from_child_modules(ModuleManager& module_manager, 
+                                              const ModuleId& module_id);
+
+size_t find_module_num_shared_config_bits_from_child_modules(ModuleManager& module_manager, 
+                                                             const ModuleId& module_id);
+
+size_t find_module_num_config_bits_from_child_modules(ModuleManager& module_manager, 
+                                                      const ModuleId& module_id,
+                                                      const CircuitLibrary& circuit_lib,
+                                                      const CircuitModelId& sram_model,
+                                                      const e_config_protocol_type& sram_orgz_type);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/utils/pb_type_utils.cpp b/openfpga/src/utils/pb_type_utils.cpp
index b791485a2..9f52c01da 100644
--- a/openfpga/src/utils/pb_type_utils.cpp
+++ b/openfpga/src/utils/pb_type_utils.cpp
@@ -254,4 +254,52 @@ enum PORTS circuit_port_require_pb_port_type(const e_circuit_model_port_type& ci
   return type_mapping.at(circuit_port_type);
 }
 
+/********************************************************************
+ * Return a list of ports of a pb_type which matches the ports defined
+ * in its linked circuit model 
+ * This function will only care if the port type matches  
+ *******************************************************************/
+std::vector<t_port*> find_pb_type_ports_match_circuit_model_port_type(t_pb_type* pb_type,
+                                                                      const e_circuit_model_port_type& port_type,
+                                                                      const VprDeviceAnnotation& vpr_device_annotation) {
+  std::vector<t_port*> ports;
+
+  for (int iport = 0; iport < pb_type->num_ports; ++iport) {
+    /* Check the circuit_port id of the port ? */
+    VTR_ASSERT(CircuitPortId::INVALID() != vpr_device_annotation.pb_circuit_port(&(pb_type->ports[iport])));
+    switch (port_type) {
+    case CIRCUIT_MODEL_PORT_INPUT:
+      if ( (IN_PORT == pb_type->ports[iport].type)
+        && (0 == pb_type->ports[iport].is_clock) ) {
+        ports.push_back(&pb_type->ports[iport]);
+      }
+      break;
+    case CIRCUIT_MODEL_PORT_OUTPUT: 
+      if ( (OUT_PORT == pb_type->ports[iport].type)
+        && (0 == pb_type->ports[iport].is_clock) ) {
+        ports.push_back(&pb_type->ports[iport]);
+      }
+      break;
+    case CIRCUIT_MODEL_PORT_INOUT: 
+      if ( (INOUT_PORT == pb_type->ports[iport].type)
+        && (0 == pb_type->ports[iport].is_clock) ) {
+        ports.push_back(&pb_type->ports[iport]);
+      }
+      break;
+    case CIRCUIT_MODEL_PORT_CLOCK: 
+      if ( (IN_PORT == pb_type->ports[iport].type)
+        && (1 == pb_type->ports[iport].is_clock) ) {
+        ports.push_back(&pb_type->ports[iport]);
+      }
+      break;
+    /* Configuration ports are not in pb_type definition */
+    default:
+      VTR_LOG_ERROR("Invalid type for port!\n");
+      exit(1);
+    }
+  }
+ 
+  return ports;
+}
+
 } /* end namespace openfpga */
diff --git a/openfpga/src/utils/pb_type_utils.h b/openfpga/src/utils/pb_type_utils.h
index 17ec7f78e..6a4dd91be 100644
--- a/openfpga/src/utils/pb_type_utils.h
+++ b/openfpga/src/utils/pb_type_utils.h
@@ -7,6 +7,7 @@
 #include <string>
 #include <vector>
 #include "physical_types.h"
+#include "vpr_device_annotation.h"
 #include "circuit_library.h"
 
 /********************************************************************
@@ -43,6 +44,10 @@ e_circuit_model_type pb_interconnect_require_circuit_model_type(const e_intercon
 
 enum PORTS circuit_port_require_pb_port_type(const e_circuit_model_port_type& circuit_port_type);
 
+std::vector<t_port*> find_pb_type_ports_match_circuit_model_port_type(t_pb_type* pb_type,
+                                                                      const e_circuit_model_port_type& port_type,
+                                                                      const VprDeviceAnnotation& vpr_device_annotation);
+
 } /* end namespace openfpga */
 
 #endif

From ea7d879b4f397be5632da8510defb2708140c34d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 12 Feb 2020 18:28:50 -0700
Subject: [PATCH 125/645] add decoder module builder

---
 openfpga/src/fabric/build_decoder_modules.cpp | 140 ++++++++++++++++++
 openfpga/src/fabric/build_decoder_modules.h   |  24 +++
 openfpga/src/fabric/build_device_module.cpp   |   5 +-
 .../src/fabric/build_essential_modules.cpp    |   2 +-
 4 files changed, 168 insertions(+), 3 deletions(-)
 create mode 100644 openfpga/src/fabric/build_decoder_modules.cpp
 create mode 100644 openfpga/src/fabric/build_decoder_modules.h

diff --git a/openfpga/src/fabric/build_decoder_modules.cpp b/openfpga/src/fabric/build_decoder_modules.cpp
new file mode 100644
index 000000000..06defc007
--- /dev/null
+++ b/openfpga/src/fabric/build_decoder_modules.cpp
@@ -0,0 +1,140 @@
+/***************************************************************************************
+ * This file includes functions that are used to build modules for decoders, including:
+ * 1. Local decoders used by multiplexers ONLY
+ * 2. Decoders used by grid/routing/top-level module for memory address decoding
+ ***************************************************************************************/
+
+/* Headers from vtrutil library */
+#include "vtr_log.h"
+#include "vtr_assert.h"
+#include "vtr_time.h"
+
+#include "openfpga_naming.h"
+#include "decoder_library_utils.h"
+#include "module_manager_utils.h"
+
+#include "build_decoder_modules.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/***************************************************************************************
+ * Create a module for a decoder with a given output size
+ *
+ *                     Inputs 
+ *                   | | ... | 
+ *                   v v     v
+ *                 +-----------+
+ *                /             \
+ *               /    Decoder    \
+ *              +-----------------+
+ *                | | | ... | | |
+ *                v v v     v v v
+ *                    Outputs
+ *               
+ *  The outputs are assumes to be one-hot codes (at most only one '1' exist)
+ *  Considering this fact, there are only num_of_outputs conditions to be encoded.
+ *  Therefore, the number of inputs is ceil(log(num_of_outputs)/log(2))
+ ***************************************************************************************/
+static 
+void build_mux_local_decoder_module(ModuleManager& module_manager,
+                                    const DecoderLibrary& decoder_lib,
+                                    const DecoderId& decoder) {
+  /* Get the number of inputs */
+  size_t addr_size = decoder_lib.addr_size(decoder);
+  size_t data_size = decoder_lib.data_size(decoder);
+
+  /* TODO: create a name for the local encoder */
+  std::string module_name = generate_mux_local_decoder_subckt_name(addr_size, data_size);
+
+  /* Create a Verilog Module based on the circuit model, and add to module manager */
+  ModuleId module_id = module_manager.add_module(module_name); 
+  VTR_ASSERT(true == module_manager.valid_module_id(module_id));
+  /* Add module ports */
+  /* Add each input port */
+  BasicPort addr_port(generate_mux_local_decoder_addr_port_name(), addr_size);
+  module_manager.add_port(module_id, addr_port, ModuleManager::MODULE_INPUT_PORT);
+  /* Add each output port */
+  BasicPort data_port(generate_mux_local_decoder_data_port_name(), data_size);
+  module_manager.add_port(module_id, data_port, ModuleManager::MODULE_OUTPUT_PORT);
+  /* Data port is registered. It should be outputted as 
+   *   output reg [lsb:msb] data 
+   */
+  module_manager.set_port_is_register(module_id, data_port.get_name(), true);
+  /* Add data_in port */
+  BasicPort data_inv_port(generate_mux_local_decoder_data_inv_port_name(), data_size);
+  VTR_ASSERT(true == decoder_lib.use_data_inv_port(decoder));
+  module_manager.add_port(module_id, data_inv_port, ModuleManager::MODULE_OUTPUT_PORT);
+}
+
+
+/***************************************************************************************
+ * This function will generate all the unique Verilog modules of local decoders for 
+ * the multiplexers used in a FPGA fabric
+ * It will reach the goal in two steps:
+ * 1. Find the unique local decoders w.r.t. the number of inputs/outputs 
+ *    We will generate the subgraphs from the multiplexing graph of each multiplexers
+ *    The number of memory bits is the number of outputs.
+ *    From that we can infer the number of inputs of each local decoders.
+ *    Here is an illustrative example of how local decoders are interfaced with multi-level MUXes
+ *
+ *        +---------+         +---------+
+ *        |  Local  |         |  Local  |
+ *        | Decoder |         | Decoder |
+ *        |    A    |         |    B    |
+ *        +---------+         +---------+
+ *          | ... |             | ... |
+ *          v     v             v     v
+ *      +--------------+    +--------------+
+ *      |  MUX Level 0 |--->|  MUX Level 1 |
+ *      +--------------+    +--------------+
+ * 2. Generate local decoder Verilog modules using behavioral description.
+ *    Note that the implementation of local decoders can be dependent on the technology
+ *    and standard cell libraries.
+ *    Therefore, behavioral Verilog is used and the local decoders should be synthesized 
+ *    before running the back-end flow for FPGA fabric 
+ *    See more details in the function print_verilog_mux_local_decoder() for more details
+ ***************************************************************************************/
+void build_mux_local_decoder_modules(ModuleManager& module_manager,
+                                     const MuxLibrary& mux_lib,
+                                     const CircuitLibrary& circuit_lib) {
+  vtr::ScopedStartFinishTimer timer("Build local encoder (for multiplexers) modules");
+
+  /* Create a library for local encoders with different sizes */
+  DecoderLibrary decoder_lib;
+  
+  /* Find unique local decoders for unique branches shared by the multiplexers */
+  for (auto mux : mux_lib.muxes()) {
+    /* Local decoders are need only when users specify them */
+    CircuitModelId mux_circuit_model = mux_lib.mux_circuit_model(mux); 
+    /* If this MUX does not need local decoder, we skip it */
+    if (false == circuit_lib.mux_use_local_encoder(mux_circuit_model)) {
+      continue;
+    }
+
+    const MuxGraph& mux_graph = mux_lib.mux_graph(mux);
+    /* Create a mux graph for the branch circuit */
+    std::vector<MuxGraph> branch_mux_graphs = mux_graph.build_mux_branch_graphs();
+    /* Add the decoder to the decoder library */
+    for (auto branch_mux_graph : branch_mux_graphs) {
+      /* The decoder size depends on the number of memories of a branch MUX.
+       * Note that only when there are >=2 memories, a decoder is needed
+       */
+      size_t decoder_data_size = branch_mux_graph.num_memory_bits();
+      if (0 == decoder_data_size) {
+        continue;
+      }
+      /* Try to find if the decoder already exists in the library, 
+       * If there is no such decoder, add it to the library 
+       */
+      add_mux_local_decoder_to_library(decoder_lib, decoder_data_size);
+    }
+  }
+
+  /* Generate Verilog modules for the found unique local encoders */
+  for (const auto& decoder : decoder_lib.decoders()) {
+    build_mux_local_decoder_module(module_manager, decoder_lib, decoder);
+  }
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fabric/build_decoder_modules.h b/openfpga/src/fabric/build_decoder_modules.h
new file mode 100644
index 000000000..842aef8c4
--- /dev/null
+++ b/openfpga/src/fabric/build_decoder_modules.h
@@ -0,0 +1,24 @@
+#ifndef BUILD_DECODER_MODULES_H
+#define BUILD_DECODER_MODULES_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "module_manager.h"
+#include "mux_library.h"
+#include "circuit_library.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void build_mux_local_decoder_modules(ModuleManager& module_manager,
+                                     const MuxLibrary& mux_lib,
+                                     const CircuitLibrary& circuit_lib);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/fabric/build_device_module.cpp b/openfpga/src/fabric/build_device_module.cpp
index bf664048f..71966937a 100644
--- a/openfpga/src/fabric/build_device_module.cpp
+++ b/openfpga/src/fabric/build_device_module.cpp
@@ -9,7 +9,7 @@
 #include "vtr_time.h"
 
 #include "build_essential_modules.h"
-//#include "build_decoder_modules.h"
+#include "build_decoder_modules.h"
 //#include "build_mux_modules.h"
 //#include "build_lut_modules.h"
 //#include "build_wire_modules.h"
@@ -49,7 +49,8 @@ ModuleManager build_device_module_graph(const DeviceContext& vpr_device_ctx,
   build_essential_modules(module_manager, openfpga_ctx.arch().circuit_lib);
 
   /* Build local encoders for multiplexers, this MUST be called before multiplexer building */
-  //build_mux_local_decoder_modules(module_manager, mux_lib, arch.spice->circuit_lib);
+  build_mux_local_decoder_modules(module_manager, openfpga_ctx.mux_lib(), 
+                                  openfpga_ctx.arch().circuit_lib);
 
   /* Build multiplexer modules */
   //build_mux_modules(module_manager, mux_lib, arch.spice->circuit_lib);
diff --git a/openfpga/src/fabric/build_essential_modules.cpp b/openfpga/src/fabric/build_essential_modules.cpp
index 07a00a788..a66a52979 100644
--- a/openfpga/src/fabric/build_essential_modules.cpp
+++ b/openfpga/src/fabric/build_essential_modules.cpp
@@ -150,7 +150,7 @@ void build_gate_module(ModuleManager& module_manager,
  ***********************************************/
 void build_essential_modules(ModuleManager& module_manager, 
                              const CircuitLibrary& circuit_lib) {
-  vtr::ScopedStartFinishTimer timer("Build essential (inverter/buffer/logic gate) modules...");
+  vtr::ScopedStartFinishTimer timer("Build essential (inverter/buffer/logic gate) modules");
 
   for (const auto& circuit_model : circuit_lib.models()) {
     /* Add essential modules upon on demand: only when it is not yet in the module library */

From fddd3c94637e0be39e54be03f49396ad9c790b3c Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 12 Feb 2020 19:45:14 -0700
Subject: [PATCH 126/645] add mux module builder

---
 openfpga/src/base/openfpga_reserved_words.h   |   28 +
 openfpga/src/fabric/build_device_module.cpp   |    4 +-
 .../src/fabric/build_module_graph_utils.cpp   |   89 ++
 .../src/fabric/build_module_graph_utils.h     |   38 +
 openfpga/src/fabric/build_mux_modules.cpp     | 1408 +++++++++++++++++
 openfpga/src/fabric/build_mux_modules.h       |   24 +
 .../k6_frac_N10_40nm_openfpga.xml             |    2 +-
 7 files changed, 1590 insertions(+), 3 deletions(-)
 create mode 100644 openfpga/src/base/openfpga_reserved_words.h
 create mode 100644 openfpga/src/fabric/build_module_graph_utils.cpp
 create mode 100644 openfpga/src/fabric/build_module_graph_utils.h
 create mode 100644 openfpga/src/fabric/build_mux_modules.cpp
 create mode 100644 openfpga/src/fabric/build_mux_modules.h

diff --git a/openfpga/src/base/openfpga_reserved_words.h b/openfpga/src/base/openfpga_reserved_words.h
new file mode 100644
index 000000000..6e761de87
--- /dev/null
+++ b/openfpga/src/base/openfpga_reserved_words.h
@@ -0,0 +1,28 @@
+/********************************************************************
+ * This file includes all the reserved words that are used in
+ * naming module, blocks, instances and cells in FPGA X2P support,
+ * including:
+ * Verilog generation, SPICE generation and bitstream generation
+ *******************************************************************/
+#ifndef OPENFPGA_RESERVED_WORDS_H
+#define OPENFPGA_RESERVED_WORDS_H
+
+/* Grid naming constant strings */
+constexpr char* GRID_MODULE_NAME_PREFIX = "grid_"; 
+
+/* Memory naming constant strings */
+constexpr char* GRID_MEM_INSTANCE_PREFIX = "mem_"; 
+constexpr char* SWITCH_BLOCK_MEM_INSTANCE_PREFIX = "mem_"; 
+constexpr char* CONNECTION_BLOCK_MEM_INSTANCE_PREFIX = "mem_"; 
+constexpr char* MEMORY_MODULE_POSTFIX = "_mem";
+
+/* Multiplexer naming constant strings */
+constexpr char* MUX_BASIS_MODULE_POSTFIX = "_basis";
+constexpr char* GRID_MUX_INSTANCE_PREFIX = "mux_"; 
+constexpr char* SWITCH_BLOCK_MUX_INSTANCE_PREFIX = "mux_"; 
+constexpr char* CONNECTION_BLOCK_MUX_INSTANCE_PREFIX = "mux_"; 
+
+/* Bitstream file strings */
+constexpr char* BITSTREAM_XML_FILE_NAME_POSTFIX = "_bitstream.xml";
+
+#endif
diff --git a/openfpga/src/fabric/build_device_module.cpp b/openfpga/src/fabric/build_device_module.cpp
index 71966937a..a322422df 100644
--- a/openfpga/src/fabric/build_device_module.cpp
+++ b/openfpga/src/fabric/build_device_module.cpp
@@ -10,7 +10,7 @@
 
 #include "build_essential_modules.h"
 #include "build_decoder_modules.h"
-//#include "build_mux_modules.h"
+#include "build_mux_modules.h"
 //#include "build_lut_modules.h"
 //#include "build_wire_modules.h"
 //#include "build_memory_modules.h"
@@ -53,7 +53,7 @@ ModuleManager build_device_module_graph(const DeviceContext& vpr_device_ctx,
                                   openfpga_ctx.arch().circuit_lib);
 
   /* Build multiplexer modules */
-  //build_mux_modules(module_manager, mux_lib, arch.spice->circuit_lib);
+  build_mux_modules(module_manager, openfpga_ctx.mux_lib(), openfpga_ctx.arch().circuit_lib);
 
   /* Build LUT modules */
   //build_lut_modules(module_manager, arch.spice->circuit_lib);
diff --git a/openfpga/src/fabric/build_module_graph_utils.cpp b/openfpga/src/fabric/build_module_graph_utils.cpp
new file mode 100644
index 000000000..617a156a6
--- /dev/null
+++ b/openfpga/src/fabric/build_module_graph_utils.cpp
@@ -0,0 +1,89 @@
+/********************************************************************
+ * This file includes most utilized functions that are used to
+ * build module graphs
+ ********************************************************************/
+#include <vector>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+
+#include "openfpga_naming.h" 
+#include "build_module_graph_utils.h" 
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Find input port of a buffer/inverter module
+ ********************************************************************/
+ModulePortId find_inverter_buffer_module_port(const ModuleManager& module_manager, 
+                                              const ModuleId& module_id, 
+                                              const CircuitLibrary& circuit_lib, 
+                                              const CircuitModelId& model_id,
+                                              const e_circuit_model_port_type& port_type) {
+  /* We must have a valid module id */
+  VTR_ASSERT(true == module_manager.valid_module_id(module_id));
+  /* Check the type of model */ 
+  VTR_ASSERT(CIRCUIT_MODEL_INVBUF == circuit_lib.model_type(model_id));
+
+  /* Add module nets to wire to the buffer module */
+  /* To match the context, Buffer should have only 2 non-global ports: 1 input port and 1 output port */
+  std::vector<CircuitPortId> model_ports = circuit_lib.model_ports_by_type(model_id, port_type, true);
+  VTR_ASSERT(1 == model_ports.size());
+
+  /* Find the input and output module ports */
+  ModulePortId module_port_id = module_manager.find_module_port(module_id, circuit_lib.port_prefix(model_ports[0]));
+  VTR_ASSERT(true == module_manager.valid_module_port_id(module_id, module_port_id));
+
+  return module_port_id;  
+}
+
+/********************************************************************
+ * Add inverter/buffer module to a parent module
+ * and complete the wiring to the input port of inverter/buffer
+ * This function will return the wire created for the output port of inverter/buffer
+ *
+ *  parent_module
+ *  +-----------------------------------------------------------------
+ *  |       
+ *  |                 input_net                    output_net
+ *  |                    |                           |
+ *  |                    v      +---------------+    v
+ *  | src_module_port --------->|  child_module |--------> 
+ *  |                           +---------------+
+ *
+ ********************************************************************/
+ModuleNetId add_inverter_buffer_child_module_and_nets(ModuleManager& module_manager,
+                                                      const ModuleId& parent_module, 
+                                                      const CircuitLibrary& circuit_lib, 
+                                                      const CircuitModelId& model_id, 
+                                                      const ModuleNetId& input_net) {
+  /* We must have a valid module id */
+  VTR_ASSERT(true == module_manager.valid_module_id(parent_module));
+
+  std::string module_name = circuit_lib.model_name(model_id);
+  ModuleId child_module = module_manager.find_module(module_name);
+  VTR_ASSERT(true == module_manager.valid_module_id(child_module));
+
+  ModulePortId module_input_port_id = find_inverter_buffer_module_port(module_manager, child_module, circuit_lib, model_id, CIRCUIT_MODEL_PORT_INPUT);
+  ModulePortId module_output_port_id = find_inverter_buffer_module_port(module_manager, child_module, circuit_lib, model_id, CIRCUIT_MODEL_PORT_OUTPUT);
+
+  /* Port size should be 1 ! */
+  VTR_ASSERT(1 == module_manager.module_port(child_module, module_input_port_id).get_width());
+  VTR_ASSERT(1 == module_manager.module_port(child_module, module_output_port_id).get_width());
+
+  /* Instanciate a child module */
+  size_t child_instance = module_manager.num_instance(parent_module, child_module);
+  module_manager.add_child_module(parent_module, child_module);
+
+  /* Use the net to connect to the input net of buffer */
+  module_manager.add_module_net_sink(parent_module, input_net, child_module, child_instance, module_input_port_id, 0);
+
+  /* Create a net to bridge the input inverter and LUT MUX */ 
+  ModuleNetId output_net = module_manager.create_module_net(parent_module);
+  module_manager.add_module_net_source(parent_module, output_net, child_module, child_instance, module_output_port_id, 0);
+
+  return output_net;
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fabric/build_module_graph_utils.h b/openfpga/src/fabric/build_module_graph_utils.h
new file mode 100644
index 000000000..dee44140a
--- /dev/null
+++ b/openfpga/src/fabric/build_module_graph_utils.h
@@ -0,0 +1,38 @@
+#ifndef BUILD_MODULE_GRAPH_UTILS_H
+#define BUILD_MODULE_GRAPH_UTILS_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <string>
+#include <vector>
+#include "vtr_geometry.h" 
+
+#include "circuit_library.h" 
+#include "openfpga_side_manager.h" 
+
+#include "vpr_types.h" 
+#include "module_manager.h" 
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+ModulePortId find_inverter_buffer_module_port(const ModuleManager& module_manager, 
+                                              const ModuleId& module_id, 
+                                              const CircuitLibrary& circuit_lib, 
+                                              const CircuitModelId& model_id,
+                                              const e_circuit_model_port_type& port_type);
+
+ModuleNetId add_inverter_buffer_child_module_and_nets(ModuleManager& module_manager,
+                                                      const ModuleId& parent_module, 
+                                                      const CircuitLibrary& circuit_lib, 
+                                                      const CircuitModelId& model_id, 
+                                                      const ModuleNetId& input_net);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/fabric/build_mux_modules.cpp b/openfpga/src/fabric/build_mux_modules.cpp
new file mode 100644
index 000000000..0f430c4d3
--- /dev/null
+++ b/openfpga/src/fabric/build_mux_modules.cpp
@@ -0,0 +1,1408 @@
+/***********************************************
+ * This file includes functions to generate
+ * Verilog submodules for multiplexers.
+ * including both fundamental submodules
+ * such as a branch in a multiplexer 
+ * and the full multiplexer
+ **********************************************/
+#include <string>
+#include <algorithm>
+
+/* Headers from vtrutil library */
+#include "vtr_log.h"
+#include "vtr_assert.h"
+#include "vtr_time.h"
+
+#include "mux_graph.h"
+#include "module_manager.h"
+#include "mux_utils.h"
+#include "circuit_library_utils.h"
+#include "decoder_library_utils.h"
+#include "module_manager_utils.h"
+#include "build_module_graph_utils.h"
+#include "openfpga_reserved_words.h"
+#include "openfpga_naming.h"
+
+#include "build_mux_modules.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/*********************************************************************
+ * Generate structural Verilog codes (consist of transmission-gates or
+ * pass-transistor) modeling an branch circuit 
+ * for a multiplexer with the given size 
+ *
+ *                +----------+
+ *   input[0] --->| tgate[0] |-+
+ *                +----------+ |
+ *                             |
+ *                +----------+ |
+ *   input[1] --->| tgate[1] |-+--->output[0]
+ *                +----------+ |
+ *                             |
+ *     ...            ...      |
+ *                             |
+ *                +----------+ |
+ *   input[i] --->| tgate[i] |-+
+ *                +----------+
+ *********************************************************************/
+static 
+void build_cmos_mux_branch_body(ModuleManager& module_manager,
+                                const CircuitLibrary& circuit_lib, 
+                                const CircuitModelId& tgate_model, 
+                                const ModuleId& mux_module, 
+                                const ModulePortId& module_input_port,
+                                const ModulePortId& module_output_port,
+                                const ModulePortId& module_mem_port,
+                                const ModulePortId& module_mem_inv_port,
+                                const MuxGraph& mux_graph) {
+  /* Get the module id of tgate in Module manager */
+  ModuleId tgate_module_id = module_manager.find_module(circuit_lib.model_name(tgate_model));
+  VTR_ASSERT(ModuleId::INVALID() != tgate_module_id);
+
+  /* Get model ports of tgate */
+  std::vector<CircuitPortId> tgate_input_ports = circuit_lib.model_ports_by_type(tgate_model, CIRCUIT_MODEL_PORT_INPUT, true);
+  std::vector<CircuitPortId> tgate_output_ports = circuit_lib.model_ports_by_type(tgate_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
+  VTR_ASSERT(3 == tgate_input_ports.size());
+  VTR_ASSERT(1 == tgate_output_ports.size());
+
+  /* Find the module ports of tgate module */
+  /* Input port is the data path input of the tgate, whose size must be 1 ! */
+  ModulePortId tgate_module_input = module_manager.find_module_port(tgate_module_id, circuit_lib.port_prefix(tgate_input_ports[0]));
+  VTR_ASSERT(true == module_manager.valid_module_port_id(tgate_module_id, tgate_module_input));
+  BasicPort tgate_module_input_port = module_manager.module_port(tgate_module_id, tgate_module_input);
+  VTR_ASSERT(1 == tgate_module_input_port.get_width());
+
+  /* Mem port is the memory of the tgate, whose size must be 1 ! */
+  ModulePortId tgate_module_mem = module_manager.find_module_port(tgate_module_id, circuit_lib.port_prefix(tgate_input_ports[1]));
+  VTR_ASSERT(true == module_manager.valid_module_port_id(tgate_module_id, tgate_module_mem));
+  BasicPort tgate_module_mem_port = module_manager.module_port(tgate_module_id, tgate_module_mem);
+  VTR_ASSERT(1 == tgate_module_mem_port.get_width());
+
+  /* Mem inv port is the inverted memory of the tgate, whose size must be 1 ! */
+  ModulePortId tgate_module_mem_inv = module_manager.find_module_port(tgate_module_id, circuit_lib.port_prefix(tgate_input_ports[2]));
+  VTR_ASSERT(true == module_manager.valid_module_port_id(tgate_module_id, tgate_module_mem_inv));
+  BasicPort tgate_module_mem_inv_port = module_manager.module_port(tgate_module_id, tgate_module_mem_inv);
+  VTR_ASSERT(1 == tgate_module_mem_inv_port.get_width());
+
+  /* Output port is the data path output of the tgate, whose size must be 1 ! */
+  ModulePortId tgate_module_output = module_manager.find_module_port(tgate_module_id, circuit_lib.port_prefix(tgate_output_ports[0]));
+  VTR_ASSERT(true == module_manager.valid_module_port_id(tgate_module_id, tgate_module_output));
+  BasicPort tgate_module_output_port = module_manager.module_port(tgate_module_id, tgate_module_output);
+  VTR_ASSERT(1 == tgate_module_output_port.get_width());
+
+  /* Ensure that input port size does match mux inputs */
+  BasicPort input_port = module_manager.module_port(mux_module, module_input_port); 
+  VTR_ASSERT(input_port.get_width() == mux_graph.num_inputs());
+  
+  /* Add module nets for each mux inputs */
+  std::vector<ModuleNetId> mux_input_nets;
+  for (const size_t& pin : input_port.pins()) {
+    ModuleNetId input_net = module_manager.create_module_net(mux_module);
+    mux_input_nets.push_back(input_net);
+    /* Configure the source for each net */
+    module_manager.add_module_net_source(mux_module, input_net, mux_module, 0, module_input_port, pin);
+  }
+
+  /* Ensure that output port size does match mux outputs */
+  BasicPort output_port = module_manager.module_port(mux_module, module_output_port); 
+  VTR_ASSERT(output_port.get_width() == mux_graph.num_outputs());
+
+  /* Add module nets for each mux outputs */
+  std::vector<ModuleNetId> mux_output_nets;
+  for (const size_t& pin : output_port.pins()) {
+    ModuleNetId output_net = module_manager.create_module_net(mux_module);
+    mux_output_nets.push_back(output_net);
+    /* Configure the sink for each net */
+    module_manager.add_module_net_sink(mux_module, output_net, mux_module, 0, module_output_port, pin);
+  }
+
+  /* Ensure that mem port size does match mux outputs */
+  BasicPort mem_port = module_manager.module_port(mux_module, module_mem_port); 
+  VTR_ASSERT(mem_port.get_width() == mux_graph.num_memory_bits());
+
+  /* Add module nets for each mem inputs */
+  std::vector<ModuleNetId> mux_mem_nets;
+  for (const size_t& pin : mem_port.pins()) {
+    ModuleNetId mem_net = module_manager.create_module_net(mux_module);
+    mux_mem_nets.push_back(mem_net);
+    /* Configure the source for each net */
+    module_manager.add_module_net_source(mux_module, mem_net, mux_module, 0, module_mem_port, pin);
+  }
+
+  /* Ensure that mem_inv port size does match mux outputs */
+  BasicPort mem_inv_port = module_manager.module_port(mux_module, module_mem_inv_port); 
+  VTR_ASSERT(mem_inv_port.get_width() == mux_graph.num_memory_bits());
+
+  /* Add module nets for each mem inverted inputs */
+  std::vector<ModuleNetId> mux_mem_inv_nets;
+  for (const size_t& pin : mem_inv_port.pins()) {
+    ModuleNetId mem_net = module_manager.create_module_net(mux_module);
+    mux_mem_inv_nets.push_back(mem_net);
+    /* Configure the source for each net */
+    module_manager.add_module_net_source(mux_module, mem_net, mux_module, 0, module_mem_inv_port, pin);
+  }
+
+  /* Build a module following the connections in mux_graph */
+  /* Iterate over the inputs */
+  for (const auto& mux_input : mux_graph.inputs()) {
+    /* Iterate over the outputs */
+    for (const auto& mux_output : mux_graph.outputs()) {
+      /* Add the a tgate to bridge the mux input and output */
+      size_t tgate_instance = module_manager.num_instance(mux_module, tgate_module_id);
+      module_manager.add_child_module(mux_module, tgate_module_id);
+
+      /* Add module nets to connect the mux input and tgate input */
+      module_manager.add_module_net_sink(mux_module, mux_input_nets[size_t(mux_graph.input_id(mux_input))], tgate_module_id, tgate_instance, tgate_module_input, tgate_module_input_port.get_lsb());
+
+      /* if there is a connection between the input and output, a tgate will be outputted */
+      std::vector<MuxEdgeId> edges = mux_graph.find_edges(mux_input, mux_output);
+      /* There should be only one edge or no edge*/
+      VTR_ASSERT((1 == edges.size()) || (0 == edges.size()));
+      /* No need to output tgates if there are no edges between two nodes */
+      if (0 == edges.size()) {
+        continue;
+      }
+
+      /* Add module nets to connect the mux output and tgate output */
+      module_manager.add_module_net_source(mux_module, mux_output_nets[size_t(mux_graph.output_id(mux_output))], tgate_module_id, tgate_instance, tgate_module_output, tgate_module_output_port.get_lsb());
+
+      MuxMemId mux_mem = mux_graph.find_edge_mem(edges[0]);
+      /* Add module nets to connect the mem input and tgate mem input */
+      if (false == mux_graph.is_edge_use_inv_mem(edges[0])) {
+        /* wire mem to mem of module, and wire mem_inv to mem_inv of module */
+        module_manager.add_module_net_sink(mux_module, mux_mem_nets[size_t(mux_mem)], tgate_module_id, tgate_instance, tgate_module_mem, tgate_module_mem_port.get_lsb());
+        module_manager.add_module_net_sink(mux_module, mux_mem_inv_nets[size_t(mux_mem)], tgate_module_id, tgate_instance, tgate_module_mem_inv, tgate_module_mem_inv_port.get_lsb());
+      } else {
+        /* wire mem_inv to mem of module, wire mem to mem_inv of module */
+        module_manager.add_module_net_sink(mux_module, mux_mem_inv_nets[size_t(mux_mem)], tgate_module_id, tgate_instance, tgate_module_mem, tgate_module_mem_port.get_lsb());
+        module_manager.add_module_net_sink(mux_module, mux_mem_nets[size_t(mux_mem)], tgate_module_id, tgate_instance, tgate_module_mem_inv, tgate_module_mem_inv_port.get_lsb());
+      }  
+    }
+  }
+}
+
+/*********************************************************************
+ * Generate  Verilog codes modeling an branch circuit 
+ * for a CMOS multiplexer with the given size 
+ * Support structural and behavioral Verilog codes
+ *********************************************************************/
+static 
+void build_cmos_mux_branch_module(ModuleManager& module_manager,
+                                  const CircuitLibrary& circuit_lib, 
+                                  const CircuitModelId& mux_model, 
+                                  const std::string& module_name, 
+                                  const MuxGraph& mux_graph) {
+  /* Get the tgate model */
+  CircuitModelId tgate_model = circuit_lib.pass_gate_logic_model(mux_model);
+
+  /* Skip output if the tgate model is a MUX2, it is handled by essential-gate generator */
+  if (CIRCUIT_MODEL_GATE == circuit_lib.model_type(tgate_model)) {
+    VTR_ASSERT(CIRCUIT_MODEL_GATE_MUX2 == circuit_lib.gate_type(tgate_model));
+    return;
+  }
+
+  std::vector<CircuitPortId> tgate_global_ports = circuit_lib.model_global_ports_by_type(tgate_model, CIRCUIT_MODEL_PORT_INPUT, true, true);
+
+  /* Generate the Verilog netlist according to the mux_graph */
+  /* Find out the number of inputs */ 
+  size_t num_inputs = mux_graph.num_inputs();
+  /* Find out the number of outputs */ 
+  size_t num_outputs = mux_graph.num_outputs();
+  /* Find out the number of memory bits */ 
+  size_t num_mems = mux_graph.num_memory_bits();
+
+  /* Check codes to ensure the port of Verilog netlists will match */
+  /* MUX graph must have only 1 output */
+  VTR_ASSERT(1 == num_outputs);
+  /* MUX graph must have only 1 level*/
+  VTR_ASSERT(1 == mux_graph.num_levels());
+
+  /* Create a Verilog Module based on the circuit model, and add to module manager */
+  ModuleId mux_module = module_manager.add_module(module_name); 
+  VTR_ASSERT(true == module_manager.valid_module_id(mux_module));
+  /* Add module ports */
+  /* Add each input port */
+  BasicPort input_port("in", num_inputs);
+  ModulePortId module_input_port = module_manager.add_port(mux_module, input_port, ModuleManager::MODULE_INPUT_PORT);
+  /* Add each output port */
+  BasicPort output_port("out", num_outputs);
+  ModulePortId module_output_port = module_manager.add_port(mux_module, output_port, ModuleManager::MODULE_OUTPUT_PORT);
+  /* Add each memory port */
+  BasicPort mem_port("mem", num_mems);
+  ModulePortId module_mem_port = module_manager.add_port(mux_module, mem_port, ModuleManager::MODULE_INPUT_PORT);
+  BasicPort mem_inv_port("mem_inv", num_mems);
+  ModulePortId module_mem_inv_port = module_manager.add_port(mux_module, mem_inv_port, ModuleManager::MODULE_INPUT_PORT);
+
+  /* By default we give a structural description, 
+   * Writers can freely write the module in their styles 
+   * For instance, Verilog writer can ignore the internal structure and write in behavioral codes 
+   */
+  build_cmos_mux_branch_body(module_manager, circuit_lib, tgate_model, mux_module, module_input_port, module_output_port, module_mem_port, module_mem_inv_port, mux_graph);
+
+  /* Add global ports to the mux module:
+   * This is a much easier job after adding sub modules (instances), 
+   * we just need to find all the global ports from the child modules and build a list of it
+   */
+  add_module_global_ports_from_child_modules(module_manager, mux_module);
+}
+
+/*********************************************************************
+ * Generate  Verilog codes modeling an branch circuit 
+ * for a RRAM-based multiplexer with the given size 
+ * Support structural and behavioral Verilog codes
+ *********************************************************************/
+static 
+void build_rram_mux_branch_module(ModuleManager& module_manager,
+                                  const CircuitLibrary& circuit_lib, 
+                                  const CircuitModelId& mux_model, 
+                                  const std::string& module_name, 
+                                  const MuxGraph& mux_graph) {
+  /* Get the input ports from the mux */
+  std::vector<CircuitPortId> mux_input_ports = circuit_lib.model_ports_by_type(mux_model, CIRCUIT_MODEL_PORT_INPUT, true);
+  /* Get the output ports from the mux */
+  std::vector<CircuitPortId> mux_output_ports = circuit_lib.model_ports_by_type(mux_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
+  /* Get the BL and WL ports from the mux */
+  std::vector<CircuitPortId> mux_blb_ports = circuit_lib.model_ports_by_type(mux_model, CIRCUIT_MODEL_PORT_BLB, true);
+  std::vector<CircuitPortId> mux_wl_ports = circuit_lib.model_ports_by_type(mux_model, CIRCUIT_MODEL_PORT_WL, true);
+
+  /* Generate the Verilog netlist according to the mux_graph */
+  /* Find out the number of inputs */ 
+  size_t num_inputs = mux_graph.num_inputs();
+  /* Find out the number of outputs */ 
+  size_t num_outputs = mux_graph.num_outputs();
+  /* Find out the number of memory bits */ 
+  size_t num_mems = mux_graph.num_memory_bits();
+
+  /* Check codes to ensure the port of Verilog netlists will match */
+  /* MUX graph must have only 1 output */
+  VTR_ASSERT(1 == num_outputs);
+  /* MUX graph must have only 1 level*/
+  VTR_ASSERT(1 == mux_graph.num_levels());
+  /* MUX graph must have only 1 input and 1 BLB and 1 WL port */
+  VTR_ASSERT(1 == mux_input_ports.size());
+  VTR_ASSERT(1 == mux_output_ports.size());
+  VTR_ASSERT(1 == mux_blb_ports.size());
+  VTR_ASSERT(1 == mux_wl_ports.size());
+
+  /* Create a Verilog Module based on the circuit model, and add to module manager */
+  ModuleId mux_module = module_manager.add_module(module_name); 
+  VTR_ASSERT(ModuleId::INVALID() != mux_module);
+
+  /* Add module ports */
+  /* Add each global programming enable/disable ports */
+  std::vector<CircuitPortId> prog_enable_ports = circuit_lib.model_global_ports_by_type(mux_model, CIRCUIT_MODEL_PORT_INPUT, true, true);
+  for (const auto& port : prog_enable_ports) {
+    /* Configure each global port */
+    BasicPort global_port(circuit_lib.port_prefix(port), circuit_lib.port_size(port));
+    module_manager.add_port(mux_module, global_port, ModuleManager::MODULE_GLOBAL_PORT);
+  }
+
+  /* Add each input port */
+  BasicPort input_port(circuit_lib.port_prefix(mux_input_ports[0]), num_inputs);
+  module_manager.add_port(mux_module, input_port, ModuleManager::MODULE_INPUT_PORT);
+
+  /* Add each output port */
+  BasicPort output_port(circuit_lib.port_prefix(mux_output_ports[0]), num_outputs);
+  module_manager.add_port(mux_module, output_port, ModuleManager::MODULE_OUTPUT_PORT);
+
+  /* Add RRAM programming ports, 
+   * RRAM MUXes require one more pair of BLB and WL 
+   * to configure the memories. See schematic for details
+   */
+  BasicPort blb_port(circuit_lib.port_prefix(mux_blb_ports[0]), num_mems + 1);
+  module_manager.add_port(mux_module, blb_port, ModuleManager::MODULE_INPUT_PORT);
+
+  BasicPort wl_port(circuit_lib.port_prefix(mux_wl_ports[0]), num_mems + 1);
+  module_manager.add_port(mux_module, wl_port, ModuleManager::MODULE_INPUT_PORT);
+
+  /* Note: we do not generate the internal structure of the ReRAM-based MUX
+   * circuit as a module graph! 
+   * This is mainly due to that the internal structure could be different
+   * in Verilog or SPICE netlists
+   * Leave the writers to customize this 
+   */
+}
+
+/***********************************************
+ * Generate Verilog codes modeling an branch circuit 
+ * for a multiplexer with the given size 
+ **********************************************/
+static 
+void build_mux_branch_module(ModuleManager& module_manager,
+                             const CircuitLibrary& circuit_lib, 
+                             const CircuitModelId& mux_model, 
+                             const size_t& mux_size, 
+                             const MuxGraph& mux_graph) {
+  std::string module_name = generate_mux_branch_subckt_name(circuit_lib, mux_model, mux_size, mux_graph.num_inputs(), MUX_BASIS_MODULE_POSTFIX);
+
+  /* Multiplexers built with different technology is in different organization */
+  switch (circuit_lib.design_tech_type(mux_model)) {
+  case CIRCUIT_MODEL_DESIGN_CMOS:
+    build_cmos_mux_branch_module(module_manager, circuit_lib, mux_model, module_name, mux_graph);
+    break;
+  case CIRCUIT_MODEL_DESIGN_RRAM:
+    build_rram_mux_branch_module(module_manager, circuit_lib, mux_model, module_name, mux_graph);
+    break;
+  default:
+    VTR_LOG_ERROR("Invalid design technology of multiplexer '%s'\n",
+                  circuit_lib.model_name(mux_model).c_str()); 
+    exit(1);
+  }
+}
+
+/********************************************************************
+ * Generate the standard-cell-based internal logic (multiplexing structure) 
+ * for a multiplexer or LUT in Verilog codes 
+ * This function will : 
+ * 1. build a multiplexing structure by instanciating standard cells MUX2
+ * 2. add intermediate buffers between multiplexing stages if specified.
+ *******************************************************************/
+static 
+void build_cmos_mux_module_mux2_multiplexing_structure(ModuleManager& module_manager,
+                                                       const CircuitLibrary& circuit_lib, 
+                                                       const ModuleId& mux_module, 
+                                                       const CircuitModelId& mux_model, 
+                                                       const CircuitModelId& std_cell_model, 
+                                                       const vtr::vector<MuxInputId, ModuleNetId>& mux_module_input_nets, 
+                                                       const vtr::vector<MuxOutputId, ModuleNetId>& mux_module_output_nets, 
+                                                       const vtr::vector<MuxMemId, ModuleNetId>& mux_module_mem_nets, 
+                                                       const MuxGraph& mux_graph) {
+  /* Get the regular (non-mode-select) sram ports from the mux */
+  std::vector<CircuitPortId> mux_regular_sram_ports = find_circuit_regular_sram_ports(circuit_lib, mux_model);
+  VTR_ASSERT(1 == mux_regular_sram_ports.size());
+
+  /* Find the input ports and output ports of the standard cell */
+  std::vector<CircuitPortId> std_cell_input_ports = circuit_lib.model_ports_by_type(std_cell_model, CIRCUIT_MODEL_PORT_INPUT, true);
+  std::vector<CircuitPortId> std_cell_output_ports = circuit_lib.model_ports_by_type(std_cell_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
+  /* Quick check the requirements on port map */
+  VTR_ASSERT(3 == std_cell_input_ports.size());
+  VTR_ASSERT(1 == std_cell_output_ports.size());
+
+  /* Find module information of the standard cell MUX2 */
+  std::string std_cell_module_name = circuit_lib.model_name(std_cell_model);
+  /* Get the moduleId for the submodule */
+  ModuleId std_cell_module_id = module_manager.find_module(std_cell_module_name);
+  /* We must have one */
+  VTR_ASSERT(ModuleId::INVALID() != std_cell_module_id);
+
+  /* Find the module ports of the standard cell MUX2 module */
+  std::vector<ModulePortId> std_cell_module_inputs;
+  std::vector<BasicPort> std_cell_module_input_ports;
+  /* Input 0 port is the first data path input of the tgate, whose size must be 1 ! */
+  for (size_t port_id = 0; port_id < 2; ++port_id) {
+    std_cell_module_inputs.push_back(module_manager.find_module_port(std_cell_module_id, circuit_lib.port_prefix(std_cell_input_ports[port_id])));
+    VTR_ASSERT(true == module_manager.valid_module_port_id(std_cell_module_id, std_cell_module_inputs[port_id]));
+    std_cell_module_input_ports.push_back(module_manager.module_port(std_cell_module_id, std_cell_module_inputs[port_id]));
+    VTR_ASSERT(1 == std_cell_module_input_ports[port_id].get_width());
+  }
+
+  /* Mem port is the memory of the standard cell MUX2, whose size must be 1 ! */
+  ModulePortId std_cell_module_mem = module_manager.find_module_port(std_cell_module_id, circuit_lib.port_prefix(std_cell_input_ports[2]));
+  VTR_ASSERT(true == module_manager.valid_module_port_id(std_cell_module_id, std_cell_module_mem));
+  BasicPort std_cell_module_mem_port = module_manager.module_port(std_cell_module_id, std_cell_module_mem);
+  VTR_ASSERT(1 == std_cell_module_mem_port.get_width());
+
+  /* Output port is the data path output of the standard cell MUX2, whose size must be 1 ! */
+  ModulePortId std_cell_module_output = module_manager.find_module_port(std_cell_module_id, circuit_lib.port_prefix(std_cell_output_ports[0]));
+  VTR_ASSERT(true == module_manager.valid_module_port_id(std_cell_module_id, std_cell_module_output));
+  BasicPort std_cell_module_output_port = module_manager.module_port(std_cell_module_id, std_cell_module_output);
+  VTR_ASSERT(1 == std_cell_module_output_port.get_width());
+
+  /* Cache Net ids for each level of the multiplexer */
+  std::vector<std::vector<ModuleNetId>> module_nets_by_level;
+  module_nets_by_level.resize(mux_graph.num_node_levels());
+  for (size_t level = 0; level < mux_graph.num_node_levels(); ++level) {
+    /* Print the internal wires located at this level */
+    module_nets_by_level[level].resize(mux_graph.num_nodes_at_level(level));
+  }
+
+  /* Build the location map of intermediate buffers */
+  std::vector<bool> inter_buffer_location_map = build_mux_intermediate_buffer_location_map(circuit_lib, mux_model, mux_graph.num_node_levels());
+ 
+  /* Add all the branch modules and intermediate buffers */
+  for (const auto& node : mux_graph.non_input_nodes()) {
+    /* Get the size of branch circuit 
+     * Instanciate an branch circuit by the size (fan-in) of the node 
+     */
+    size_t branch_size = mux_graph.node_in_edges(node).size();
+    /* To match the standard cell MUX2: We should have only 2 input_nodes */
+    VTR_ASSERT(2 == branch_size);
+
+    /* Find the instance id */
+    size_t std_cell_instance_id = module_manager.num_instance(mux_module, std_cell_module_id);
+    /* Add the module to mux_module */
+    module_manager.add_child_module(mux_module, std_cell_module_id);
+
+    /* Get the node level and index in the current level */
+    size_t output_node_level = mux_graph.node_level(node);
+    size_t output_node_index_at_level = mux_graph.node_index_at_level(node);
+    /* Set a name for the instance */
+    std::string std_cell_instance_name = generate_mux_branch_instance_name(output_node_level, output_node_index_at_level, false);
+    module_manager.set_child_instance_name(mux_module, std_cell_module_id, std_cell_instance_id, std_cell_instance_name);
+
+    /* Add module nets to wire to next stage modules */
+    ModuleNetId branch_net; 
+    if (true == mux_graph.is_node_output(node)) {
+      /* This is an output node, we should use existing output nets */
+      MuxOutputId output_id = mux_graph.output_id(node);
+      branch_net = mux_module_output_nets[output_id];
+    } else {
+      VTR_ASSERT(false == mux_graph.is_node_output(node));
+      branch_net = module_manager.create_module_net(mux_module);
+    }
+    module_manager.add_module_net_source(mux_module, branch_net, std_cell_module_id, std_cell_instance_id, std_cell_module_output, std_cell_module_output_port.get_lsb());
+
+    /* Record the module net id in the cache */
+    module_nets_by_level[output_node_level][output_node_index_at_level] = branch_net;
+
+    /* Wire the branch module memory ports to the nets of MUX memory ports */
+    /* Get the mems in the branch circuits */
+    std::vector<MuxMemId> mems; 
+    for (const auto& edge : mux_graph.node_in_edges(node)) {
+      /* Get the mem control the edge */
+      MuxMemId mem = mux_graph.find_edge_mem(edge);
+      /* Add the mem if it is not in the list */
+      if (mems.end() == std::find(mems.begin(), mems.end(), mem)) {
+        mems.push_back(mem);
+      }
+    }
+    /* Connect mem to mem net one by one 
+     * Note that standard cell MUX2 only needs mem but NOT mem_inv
+     */
+    for (const MuxMemId& mem : mems) {
+      module_manager.add_module_net_sink(mux_module, mux_module_mem_nets[mem], std_cell_module_id, std_cell_instance_id, std_cell_module_mem, std_cell_module_mem_port.get_lsb());
+    }
+
+    /* Wire the branch module inputs to the nets in previous stage */
+    /* Get the nodes which drive the root_node */
+    std::vector<MuxNodeId> input_nodes; 
+    for (const auto& edge : mux_graph.node_in_edges(node)) {
+      /* Get the nodes drive the edge */
+      for (const auto& src_node : mux_graph.edge_src_nodes(edge)) {
+        input_nodes.push_back(src_node);
+      }
+    }
+    /* Number of inputs should match the branch_input_size!!! */
+    VTR_ASSERT(input_nodes.size() == branch_size);
+    /* To match the standard cell MUX2: We should have only 2 input_nodes */
+    VTR_ASSERT(2 == input_nodes.size());
+    /* build the link between input_node[0] and std_cell_input_port[0] 
+     * build the link between input_node[1] and std_cell_input_port[1] 
+     */
+    for (size_t node_id = 0; node_id < input_nodes.size(); ++node_id) {
+      /* Find the port info of each input node */
+      size_t input_node_level = mux_graph.node_level(input_nodes[node_id]);
+      size_t input_node_index_at_level = mux_graph.node_index_at_level(input_nodes[node_id]);
+      /* For inputs of mux, the net id is reserved */
+      if (true == mux_graph.is_node_input(input_nodes[node_id])) {
+        /* Get node input id */
+        MuxInputId input_id = mux_graph.input_id(input_nodes[node_id]);
+        module_manager.add_module_net_sink(mux_module, mux_module_input_nets[input_id], std_cell_module_id, std_cell_instance_id, std_cell_module_inputs[node_id], std_cell_module_input_ports[node_id].get_lsb());
+      } else {
+        VTR_ASSERT (false == mux_graph.is_node_input(input_nodes[node_id]));
+        /* Find the input port of standard cell */
+        module_manager.add_module_net_sink(mux_module, module_nets_by_level[input_node_level][input_node_index_at_level], std_cell_module_id, std_cell_instance_id, std_cell_module_inputs[node_id], std_cell_module_input_ports[node_id].get_lsb());
+      }
+    }
+
+    /* Identify if an intermediate buffer is needed */
+    if (false == inter_buffer_location_map[output_node_level]) { 
+      continue;
+    }
+    /* Add an intermediate buffer to mux_module if needed */
+    if (true == mux_graph.is_node_output(node)) {
+      /* Output node does not need buffer addition here, it is handled outside this function */
+      continue; 
+    }
+    /* Now we need to add intermediate buffers by instanciating the modules */
+    CircuitModelId buffer_model = circuit_lib.lut_intermediate_buffer_model(mux_model);
+    /* We must have a valid model id */
+    VTR_ASSERT(CircuitModelId::INVALID() != buffer_model);
+
+    /* Create a module net which sources from buffer output */
+    ModuleNetId buffer_net = add_inverter_buffer_child_module_and_nets(module_manager, mux_module, circuit_lib, buffer_model, branch_net); 
+
+    /* Record the module net id in the cache */
+    module_nets_by_level[output_node_level][output_node_index_at_level] = buffer_net;
+  }
+}
+
+/********************************************************************
+ * Generate the pass-transistor/transmission-gate -based internal logic 
+ * (multiplexing structure) for a multiplexer or LUT in Verilog codes 
+ * This function will : 
+ * 1. build a multiplexing structure by instanciating the branch circuits
+ *    generated before
+ * 2. add intermediate buffers between multiplexing stages if specified.
+ *******************************************************************/
+static 
+void build_cmos_mux_module_tgate_multiplexing_structure(ModuleManager& module_manager,
+                                                        const CircuitLibrary& circuit_lib, 
+                                                        const ModuleId& mux_module, 
+                                                        const CircuitModelId& circuit_model, 
+                                                        const vtr::vector<MuxInputId, ModuleNetId>& mux_module_input_nets, 
+                                                        const vtr::vector<MuxOutputId, ModuleNetId>& mux_module_output_nets, 
+                                                        const vtr::vector<MuxMemId, ModuleNetId>& mux_module_mem_nets, 
+                                                        const vtr::vector<MuxMemId, ModuleNetId>& mux_module_mem_inv_nets, 
+                                                        const MuxGraph& mux_graph) {
+  /* Find the actual mux size */
+  size_t mux_size = find_mux_num_datapath_inputs(circuit_lib, circuit_model, mux_graph.num_inputs());
+
+  /* Get the regular (non-mode-select) sram ports from the mux */
+  std::vector<CircuitPortId> mux_regular_sram_ports = find_circuit_regular_sram_ports(circuit_lib, circuit_model);
+  VTR_ASSERT(1 == mux_regular_sram_ports.size());
+
+  /* Cache Net ids for each level of the multiplexer */
+  std::vector<std::vector<ModuleNetId>> module_nets_by_level;
+  module_nets_by_level.resize(mux_graph.num_node_levels());
+  for (size_t level = 0; level < mux_graph.num_node_levels(); ++level) {
+    /* Print the internal wires located at this level */
+    module_nets_by_level[level].resize(mux_graph.num_nodes_at_level(level));
+  }
+
+  /* Build the location map of intermediate buffers */
+  std::vector<bool> inter_buffer_location_map = build_mux_intermediate_buffer_location_map(circuit_lib, circuit_model, mux_graph.num_node_levels());
+ 
+  /* Add all the branch modules and intermediate buffers */
+  for (const auto& node : mux_graph.non_input_nodes()) {
+    /* Get the size of branch circuit 
+     * Instanciate an branch circuit by the size (fan-in) of the node 
+     */
+    size_t branch_size = mux_graph.node_in_edges(node).size();
+
+    /* Instanciate the branch module which is a tgate-based module  
+     */
+    std::string branch_module_name= generate_mux_branch_subckt_name(circuit_lib, circuit_model, mux_size, branch_size, MUX_BASIS_MODULE_POSTFIX);
+    /* Get the moduleId for the submodule */
+    ModuleId branch_module_id = module_manager.find_module(branch_module_name);
+    /* We must have one */
+    VTR_ASSERT(ModuleId::INVALID() != branch_module_id);
+
+    /* Find the instance id */
+    size_t branch_instance_id = module_manager.num_instance(mux_module, branch_module_id);
+    /* Add the module to mux_module */
+    module_manager.add_child_module(mux_module, branch_module_id);
+
+    /* Get the node level and index in the current level */
+    size_t output_node_level = mux_graph.node_level(node);
+    size_t output_node_index_at_level = mux_graph.node_index_at_level(node);
+    /* Set a name for the instance */
+    std::string branch_instance_name = generate_mux_branch_instance_name(output_node_level, output_node_index_at_level, false);
+    module_manager.set_child_instance_name(mux_module, branch_module_id, branch_instance_id, branch_instance_name);
+
+    /* Get the output port id of branch module */
+    ModulePortId branch_module_output_port_id = module_manager.find_module_port(branch_module_id, std::string("out")); 
+    BasicPort branch_module_output_port = module_manager.module_port(branch_module_id, branch_module_output_port_id);
+
+    /* Add module nets to wire to next stage modules */
+    ModuleNetId branch_net; 
+    if (true == mux_graph.is_node_output(node)) {
+      /* This is an output node, we should use existing output nets */
+      MuxOutputId output_id = mux_graph.output_id(node);
+      branch_net = mux_module_output_nets[output_id];
+    } else {
+      VTR_ASSERT(false == mux_graph.is_node_output(node));
+      branch_net = module_manager.create_module_net(mux_module);
+    }
+    module_manager.add_module_net_source(mux_module, branch_net, branch_module_id, branch_instance_id, branch_module_output_port_id, branch_module_output_port.get_lsb());
+
+    /* Record the module net id in the cache */
+    module_nets_by_level[output_node_level][output_node_index_at_level] = branch_net;
+
+    /* Wire the branch module memory ports to the nets of MUX memory ports */
+    /* Get the mems in the branch circuits */
+    std::vector<MuxMemId> mems; 
+    for (const auto& edge : mux_graph.node_in_edges(node)) {
+      /* Get the mem control the edge */
+      MuxMemId mem = mux_graph.find_edge_mem(edge);
+      /* Add the mem if it is not in the list */
+      if (mems.end() == std::find(mems.begin(), mems.end(), mem)) {
+        mems.push_back(mem);
+      }
+    }
+
+    /* Get mem/mem_inv ports of branch module */
+    ModulePortId branch_module_mem_port_id = module_manager.find_module_port(branch_module_id, std::string("mem")); 
+    BasicPort branch_module_mem_port = module_manager.module_port(branch_module_id, branch_module_mem_port_id);
+    ModulePortId branch_module_mem_inv_port_id = module_manager.find_module_port(branch_module_id, std::string("mem_inv")); 
+    BasicPort branch_module_mem_inv_port = module_manager.module_port(branch_module_id, branch_module_mem_inv_port_id);
+
+    /* Note that we do NOT care inverted edge-to-mem connection. 
+     * It is handled in branch module generation!!!
+     */
+    /* Connect mem/mem_inv to mem/mem_inv net one by one */
+    for (size_t mem_id = 0; mem_id < mems.size(); ++mem_id) {
+      module_manager.add_module_net_sink(mux_module, mux_module_mem_nets[mems[mem_id]], branch_module_id, branch_instance_id, branch_module_mem_port_id, branch_module_mem_port.pins()[mem_id]);
+      module_manager.add_module_net_sink(mux_module, mux_module_mem_inv_nets[mems[mem_id]], branch_module_id, branch_instance_id, branch_module_mem_inv_port_id, branch_module_mem_inv_port.pins()[mem_id]);
+    }
+
+    /* Wire the branch module inputs to the nets in previous stage */
+    /* Get the input port id of branch module */
+    ModulePortId branch_module_input_port_id = module_manager.find_module_port(branch_module_id, std::string("in")); 
+    BasicPort branch_module_input_port = module_manager.module_port(branch_module_id, branch_module_input_port_id);
+
+    /* Get the nodes which drive the root_node */
+    std::vector<MuxNodeId> input_nodes; 
+    for (const auto& edge : mux_graph.node_in_edges(node)) {
+      /* Get the nodes drive the edge */
+      for (const auto& src_node : mux_graph.edge_src_nodes(edge)) {
+        input_nodes.push_back(src_node);
+      }
+    }
+    /* Number of inputs should match the branch_input_size!!! */
+    VTR_ASSERT(input_nodes.size() == branch_size);
+    /* build the link between input_node and branch circuit input_port[0] 
+     */
+    for (size_t node_id = 0; node_id < input_nodes.size(); ++node_id) {
+      /* Find the port info of each input node */
+      size_t input_node_level = mux_graph.node_level(input_nodes[node_id]);
+      size_t input_node_index_at_level = mux_graph.node_index_at_level(input_nodes[node_id]);
+      /* For inputs of mux, the net id is reserved */
+      if (true == mux_graph.is_node_input(input_nodes[node_id])) {
+        /* Get node input id */
+        MuxInputId input_id = mux_graph.input_id(input_nodes[node_id]);
+        module_manager.add_module_net_sink(mux_module, mux_module_input_nets[input_id], branch_module_id, branch_instance_id, branch_module_input_port_id, branch_module_input_port.pins()[node_id]);
+      } else {
+        VTR_ASSERT (false == mux_graph.is_node_input(input_nodes[node_id]));
+        module_manager.add_module_net_sink(mux_module, module_nets_by_level[input_node_level][input_node_index_at_level], branch_module_id, branch_instance_id, branch_module_input_port_id, branch_module_input_port.pins()[node_id]);
+      }
+    }
+
+    /* Identify if an intermediate buffer is needed */
+    if (false == inter_buffer_location_map[output_node_level]) { 
+      continue;
+    }
+    /* Add an intermediate buffer to mux_module if needed */
+    if (true == mux_graph.is_node_output(node)) {
+      /* Output node does not need buffer addition here, it is handled outside this function */
+      continue; 
+    }
+    /* Now we need to add intermediate buffers by instanciating the modules */
+    CircuitModelId buffer_model = circuit_lib.lut_intermediate_buffer_model(circuit_model);
+    /* We must have a valid model id */
+    VTR_ASSERT(CircuitModelId::INVALID() != buffer_model);
+
+    ModuleNetId buffer_net = add_inverter_buffer_child_module_and_nets(module_manager, mux_module, circuit_lib, buffer_model, branch_net); 
+
+    /* Record the module net id in the cache */
+    module_nets_by_level[output_node_level][output_node_index_at_level] = buffer_net;
+  }
+}
+
+/*********************************************************************
+ * This function will add nets and input buffers (if needed) 
+ * to a mux module 
+ * Module net represents the connections when there are no input buffers
+ *             mux_input_net[0]
+ *                  |
+ *                  v    +------------
+ * mux_in[0] ----------->|
+ *                       |
+ *                       | 
+ *                       |
+ *                       |  Multiplexing
+ *     mux_input_net[i]  |  Structure
+ *                  |    |   
+ *                  v    |
+ * mux_in[0] ----------->|
+ *                       |
+ *
+ *
+ * Module net represents the connections when there are input buffers
+ *                           mux_input_net[0]
+ *                                      |
+ *                 +-----------------+  v    +------------
+ * mux_in[0] ----->| input_buffer[0] |-----> |
+ *                 +-----------------+       |
+ *                                           | 
+ *                       ...                 |
+ *                                           |  Multiplexing
+ *                          mux_input_net[i] |   Structure
+ *                                      |    |   
+ *                 +-----------------+  v    |
+ * mux_in[0] ----->| input_buffer[0] |-----> |
+ *                 +-----------------+       |
+ *********************************************************************/
+static 
+vtr::vector<MuxInputId, ModuleNetId> build_mux_module_input_buffers(ModuleManager& module_manager, 
+                                                                    const CircuitLibrary& circuit_lib, 
+                                                                    const ModuleId& mux_module, 
+                                                                    const CircuitModelId& mux_model, 
+                                                                    const MuxGraph& mux_graph) {
+  vtr::vector<MuxInputId, ModuleNetId> mux_input_nets(mux_graph.num_inputs(), ModuleNetId::INVALID());
+
+  /* Get the input ports from the mux */
+  std::vector<CircuitPortId> mux_input_ports = circuit_lib.model_ports_by_type(mux_model, CIRCUIT_MODEL_PORT_INPUT, true);
+  /* We should have only 1 input port! */
+  VTR_ASSERT(1 == mux_input_ports.size());
+
+  /* Get the input port from MUX module */
+  ModulePortId module_input_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_prefix(mux_input_ports[0]));
+  VTR_ASSERT(ModulePortId::INVALID() != module_input_port_id);
+  /* Get the port from module */
+  BasicPort module_input_port = module_manager.module_port(mux_module, module_input_port_id);
+
+  /* Iterate over all the inputs in the MUX graph */
+  for (const auto& input_node : mux_graph.inputs()) {
+    /* Fetch fundamental information from MUX graph w.r.t. the input node */
+    MuxInputId input_index = mux_graph.input_id(input_node);
+    VTR_ASSERT(MuxInputId::INVALID() != input_index);   
+ 
+    /* For last input:
+     * Add a constant value to the last input, if this MUX needs a constant input
+     */
+    if (  (MuxInputId(mux_graph.num_inputs() - 1) == mux_graph.input_id(input_node)) 
+       && (true == circuit_lib.mux_add_const_input(mux_model)) ) {
+      /* Get the constant input value */
+      size_t const_value = circuit_lib.mux_const_input_value(mux_model);
+      VTR_ASSERT( (0 == const_value) || (1 == const_value) ); 
+      /* Instanciate a VDD module (default module)
+       * and build a net between VDD and the MUX input
+       */
+      /* Get the moduleId for the buffer module */
+      ModuleId const_val_module_id = module_manager.find_module(generate_const_value_module_name(const_value));
+      /* We must have one */
+      VTR_ASSERT(ModuleId::INVALID() != const_val_module_id);
+      size_t const_val_instance = module_manager.num_instance(mux_module, const_val_module_id);
+      module_manager.add_child_module(mux_module, const_val_module_id);
+      ModulePortId const_port_id = module_manager.find_module_port(const_val_module_id, generate_const_value_module_output_port_name(const_value));
+
+      ModuleNetId input_net = module_manager.create_module_net(mux_module);
+      module_manager.add_module_net_source(mux_module, input_net, const_val_module_id, const_val_instance, const_port_id, 0);
+      mux_input_nets[input_index] = input_net;
+      continue;
+    }
+
+    /* When we do not need any buffer, create a net for the input directly */
+    if (false == circuit_lib.is_input_buffered(mux_model)) {
+      ModuleNetId input_net = module_manager.create_module_net(mux_module);
+      module_manager.add_module_net_source(mux_module, input_net, mux_module, 0, module_input_port_id, size_t(input_index));
+      mux_input_nets[input_index] = input_net;
+      continue;
+    }
+    
+    /* Now we need to add intermediate buffers by instanciating the modules */
+    CircuitModelId buffer_model = circuit_lib.input_buffer_model(mux_model);
+    /* We must have a valid model id */
+    VTR_ASSERT(CircuitModelId::INVALID() != buffer_model);
+
+    /* Connect the module net from branch output to buffer input */
+    ModuleNetId buffer_net = module_manager.create_module_net(mux_module);
+    module_manager.add_module_net_source(mux_module, buffer_net, mux_module, 0, module_input_port_id, size_t(input_index));
+
+    /* Create a module net which sources from buffer output */
+    ModuleNetId input_net = add_inverter_buffer_child_module_and_nets(module_manager, mux_module, circuit_lib, buffer_model, buffer_net); 
+    mux_input_nets[input_index] = input_net;
+  }
+
+  return mux_input_nets;
+}
+
+/*********************************************************************
+ * This function will add nets and input buffers (if needed) 
+ * to a mux module 
+ * Module net represents the connections when there are no output buffers
+ *
+ *             mux_output_net[0]
+ * ------------+   |
+ *             |   v
+ *             |--------> mux_output[0]
+ *             |
+ *             |
+ * Multiplexer | ...
+ * Strcuture   |
+ *             |--------> mux_output[i]
+ *             |   ^
+ *             |   |
+ * ------------+  mux_output_net[i]
+ *
+ * Module net represents the connections when there are output buffers
+ *
+ *              mux_output_net[0]
+ * ------------+    |
+ *             |    |
+ *             |    v   +------------------+   
+ *             |------->| output_buffer[0] |------> mux_output[0]
+ *             |        +------------------+  
+ *             |
+ * Multiplexer |        ...
+ * Strcuture   |
+ *             |        +------------------+   
+ *             |------->| output_buffer[i] |------> mux_output[i]
+ *             |    ^   +------------------+    
+ *             |    |
+ *             |    |
+ * ------------+   mux_output_net[i]
+
+ *
+ *********************************************************************/
+static 
+vtr::vector<MuxOutputId, ModuleNetId> build_mux_module_output_buffers(ModuleManager& module_manager, 
+                                                                      const CircuitLibrary& circuit_lib, 
+                                                                      const ModuleId& mux_module, 
+                                                                      const CircuitModelId& mux_model, 
+                                                                      const MuxGraph& mux_graph) {
+
+  /* Create module nets for output ports */
+  vtr::vector<MuxOutputId, ModuleNetId> mux_output_nets(mux_graph.num_outputs(), ModuleNetId::INVALID());
+
+  /* Get the output ports from the mux */
+  std::vector<CircuitPortId> mux_output_ports = circuit_lib.model_ports_by_type(mux_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
+
+  /* Iterate over all the outputs in the MUX module */
+  for (const auto& output_port : mux_output_ports) {
+    /* Get the output port from MUX module */
+    ModulePortId module_output_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_prefix(output_port));
+    VTR_ASSERT(ModulePortId::INVALID() != module_output_port_id);
+    /* Get the port from module */
+    BasicPort module_output_port = module_manager.module_port(mux_module, module_output_port_id);
+
+    /* Iterate over each pin of the output port */
+    for (const size_t& pin : circuit_lib.pins(output_port)) {
+      /* Fetch fundamental information from MUX graph w.r.t. the input node */
+      /* Deposite the last level of the graph, which is a default value */
+      size_t output_node_level = mux_graph.num_node_levels() - 1; 
+      /* If there is a fracturable level specified for the output, we find the exact level */
+      if (size_t(-1) != circuit_lib.port_lut_frac_level(output_port)) {
+        output_node_level = circuit_lib.port_lut_frac_level(output_port);
+      }
+      /* Deposite a zero, which is a default value */
+      size_t output_node_index_at_level = 0; 
+      /* If there are output masks, we find the node_index */
+      if (!circuit_lib.port_lut_output_mask(output_port).empty()) {
+        output_node_index_at_level = circuit_lib.port_lut_output_mask(output_port).at(pin);
+      } 
+      /* Double check the node exists in the Mux Graph */
+      MuxNodeId node_id = mux_graph.node_id(output_node_level, output_node_index_at_level);
+      VTR_ASSERT(MuxNodeId::INVALID() != node_id);
+      MuxOutputId output_index = mux_graph.output_id(node_id);
+
+      /* Create the port information of the module output at the given pin range, which is the output of buffer instance */
+      BasicPort instance_output_port(module_output_port.get_name(), pin, pin);
+
+      /* If the output is not supposed to be buffered, create a net for the input directly */
+      if (false == circuit_lib.is_output_buffered(mux_model)) {
+        ModuleNetId output_net = module_manager.create_module_net(mux_module);
+        module_manager.add_module_net_sink(mux_module, output_net, mux_module, 0, module_output_port_id, pin);
+        mux_output_nets[output_index] = output_net;
+        continue; /* Finish here */
+      }
+
+      /* Reach here, we need a buffer, create a port-to-port map and output the buffer instance */
+      /* Now we need to add intermediate buffers by instanciating the modules */
+      CircuitModelId buffer_model = circuit_lib.output_buffer_model(mux_model);
+      /* We must have a valid model id */
+      VTR_ASSERT(CircuitModelId::INVALID() != buffer_model);
+
+      /* Create a module net which sinks at buffer input */
+      ModuleNetId input_net = module_manager.create_module_net(mux_module);
+      ModuleNetId output_net = add_inverter_buffer_child_module_and_nets(module_manager, mux_module, circuit_lib, buffer_model, input_net); 
+      module_manager.add_module_net_sink(mux_module, output_net, mux_module, 0, module_output_port_id, pin);
+      mux_output_nets[output_index] = input_net;
+    }
+  }
+
+  return mux_output_nets;
+}
+
+/*********************************************************************
+ * This function will 
+ * 1. Build local encoders for a MUX module (if specified)
+ * 2. Build nets between memory ports of a MUX module and branch circuits
+ *    This happens when local encoders are not needed
+ *
+ *               MUX module     
+ *             +---------------------
+ *             | mux_mem_nets/mux_mem_inv_nets
+ *             |   |
+ *             |   v     +---------
+ *         mem-+-------->|
+ *             |         | Branch Module 
+ *             |         |
+ *
+ * 3. Build nets between local encoders and memory ports of a MUX module
+ *    This happens when local encoders are needed
+ * 4. Build nets between local encoders and branch circuits
+ *    This happens when local encoders are needed
+ *
+ *               MUX module
+ *             +---------------------
+ *             |
+ *             |       +-------+  mux_mem_nets/mux_mem_inv_nets
+ *             |       |       |    |
+ *        mem--+------>|       |    v    +---------
+ *             |       | Local |-------->|
+ *             |       |Encoder|         | Branch
+ *             |       |       |         | Module
+ *             |       |       |         |
+ *             |       |       |         |
+ *
+ *********************************************************************/
+static 
+void build_mux_module_local_encoders_and_memory_nets(ModuleManager& module_manager, 
+                                                     const ModuleId& mux_module, 
+                                                     const CircuitLibrary& circuit_lib, 
+                                                     const CircuitModelId& mux_model, 
+                                                     const std::vector<CircuitPortId>& mux_sram_ports, 
+                                                     const MuxGraph& mux_graph,
+                                                     vtr::vector<MuxMemId, ModuleNetId>& mux_mem_nets,
+                                                     vtr::vector<MuxMemId, ModuleNetId>& mux_mem_inv_nets) {
+
+  /* Create nets here, and we will configure the net source later */
+  for (size_t mem = 0; mem < mux_graph.num_memory_bits(); ++mem) {
+    ModuleNetId mem_net = module_manager.create_module_net(mux_module);
+    mux_mem_nets.push_back(mem_net);
+    ModuleNetId mem_inv_net = module_manager.create_module_net(mux_module);
+    mux_mem_inv_nets.push_back(mem_inv_net);
+  }
+
+  if (false == circuit_lib.mux_use_local_encoder(mux_model)) {
+    /* Add mem and mem_inv nets here */
+    size_t mem_net_cnt = 0;
+    for (const auto& port : mux_sram_ports) {
+      ModulePortId mem_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_prefix(port));
+      BasicPort mem_port = module_manager.module_port(mux_module, mem_port_id);
+      for (const size_t& pin : mem_port.pins()) {
+        MuxMemId mem_id = MuxMemId(mem_net_cnt);
+        /* Set the module net source */
+        module_manager.add_module_net_source(mux_module, mux_mem_nets[mem_id], mux_module, 0, mem_port_id, pin);
+        /* Update counter */
+        mem_net_cnt++;
+      }
+    }
+    VTR_ASSERT(mem_net_cnt == mux_graph.num_memory_bits());
+
+    /* Add mem and mem_inv nets here */
+    size_t mem_inv_net_cnt = 0;
+    for (const auto& port : mux_sram_ports) {
+      ModulePortId mem_inv_port_id = module_manager.find_module_port(mux_module, std::string(circuit_lib.port_prefix(port) + "_inv"));
+      BasicPort mem_inv_port = module_manager.module_port(mux_module, mem_inv_port_id);
+      for (const size_t& pin : mem_inv_port.pins()) {
+        MuxMemId mem_id = MuxMemId(mem_inv_net_cnt);
+        /* Set the module net source */
+        module_manager.add_module_net_source(mux_module, mux_mem_inv_nets[mem_id], mux_module, 0, mem_inv_port_id, pin);
+        /* Update counter */
+        mem_inv_net_cnt++;
+      }
+    }
+    VTR_ASSERT(mem_inv_net_cnt == mux_graph.num_memory_bits());
+    return; /* Finish here if local encoders are not required */
+  }
+
+  /* Add local decoder instance here */
+  VTR_ASSERT(true == circuit_lib.mux_use_local_encoder(mux_model));
+  BasicPort decoder_data_port(generate_mux_local_decoder_data_port_name(), mux_graph.num_memory_bits());
+  BasicPort decoder_data_inv_port(generate_mux_local_decoder_data_inv_port_name(), mux_graph.num_memory_bits());
+
+  /* Local port to record the LSB and MSB of each level, here, we deposite (0, 0) */
+  ModulePortId mux_module_sram_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_prefix(mux_sram_ports[0]));
+  ModulePortId mux_module_sram_inv_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_prefix(mux_sram_ports[0]) + "_inv");
+  BasicPort lvl_addr_port(circuit_lib.port_prefix(mux_sram_ports[0]), 0);
+  BasicPort lvl_data_port(decoder_data_port.get_name(), 0);
+  BasicPort lvl_data_inv_port(decoder_data_inv_port.get_name(), 0);
+
+  /* Counter for mem index */
+  size_t mem_net_cnt = 0;
+  size_t mem_inv_net_cnt = 0;
+
+  for (const auto& lvl : mux_graph.levels()) {
+    size_t addr_size = find_mux_local_decoder_addr_size(mux_graph.num_memory_bits_at_level(lvl));
+    size_t data_size = mux_graph.num_memory_bits_at_level(lvl);
+    /* Update the LSB and MSB of addr and data port for the current level */
+    lvl_addr_port.rotate(addr_size);
+    lvl_data_port.rotate(data_size);
+    lvl_data_inv_port.rotate(data_size);
+
+    /* Exception: if the data size is one, we just need wires! */
+    if (1 == data_size) {
+      for (size_t pin_id = 0; pin_id < lvl_addr_port.pins().size(); ++pin_id) {
+        MuxMemId mem_id = MuxMemId(mem_net_cnt);
+        /* Set the module net source */
+        module_manager.add_module_net_source(mux_module, mux_mem_nets[mem_id], mux_module, 0, mux_module_sram_port_id, lvl_addr_port.pins()[pin_id]);
+        /* Update counter */
+        mem_net_cnt++;
+
+        MuxMemId mem_inv_id = MuxMemId(mem_inv_net_cnt);
+        /* Set the module net source */
+        module_manager.add_module_net_source(mux_module, mux_mem_inv_nets[mem_inv_id], mux_module, 0, mux_module_sram_inv_port_id, lvl_addr_port.pins()[pin_id]);
+        /* Update counter */
+        mem_inv_net_cnt++;
+      }
+      continue;
+    }
+
+    std::string decoder_module_name = generate_mux_local_decoder_subckt_name(addr_size, data_size);
+    ModuleId decoder_module = module_manager.find_module(decoder_module_name); 
+    VTR_ASSERT(ModuleId::INVALID() != decoder_module);
+
+    size_t decoder_instance = module_manager.num_instance(mux_module, decoder_module);
+    module_manager.add_child_module(mux_module, decoder_module);
+  
+    /* Add module nets to connect sram ports of MUX to address port */
+    ModulePortId decoder_module_addr_port_id = module_manager.find_module_port(decoder_module, generate_mux_local_decoder_addr_port_name());
+    BasicPort decoder_module_addr_port = module_manager.module_port(decoder_module, decoder_module_addr_port_id);
+    VTR_ASSERT(decoder_module_addr_port.get_width() == lvl_addr_port.get_width());
+
+    /* Build pin-to-pin net connection */
+    for (size_t pin_id = 0; pin_id < lvl_addr_port.pins().size(); ++pin_id) {
+      ModuleNetId net = module_manager.create_module_net(mux_module);
+      module_manager.add_module_net_source(mux_module, net, mux_module, 0, mux_module_sram_port_id, lvl_addr_port.pins()[pin_id]);
+      module_manager.add_module_net_sink(mux_module, net, decoder_module, decoder_instance, decoder_module_addr_port_id, decoder_module_addr_port.pins()[pin_id]);
+    }
+
+    /* Add module nets to connect data port to MUX mem ports */
+    ModulePortId decoder_module_data_port_id = module_manager.find_module_port(decoder_module, generate_mux_local_decoder_data_port_name());
+    BasicPort decoder_module_data_port = module_manager.module_port(decoder_module, decoder_module_data_port_id);
+    
+    /* Build pin-to-pin net connection */
+    for (const size_t& pin : decoder_module_data_port.pins()) {
+      ModuleNetId net = mux_mem_nets[MuxMemId(mem_net_cnt)];
+      module_manager.add_module_net_source(mux_module, net, decoder_module, decoder_instance, decoder_module_data_port_id, pin);
+      /* Add the module nets to mux_mem_nets cache */
+      mem_net_cnt++;
+    }
+
+    ModulePortId decoder_module_data_inv_port_id = module_manager.find_module_port(decoder_module, generate_mux_local_decoder_data_inv_port_name());
+    BasicPort decoder_module_data_inv_port = module_manager.module_port(decoder_module, decoder_module_data_inv_port_id);
+
+    /* Build pin-to-pin net connection */
+    for (const size_t& pin : decoder_module_data_inv_port.pins()) {
+      ModuleNetId net = mux_mem_inv_nets[MuxMemId(mem_inv_net_cnt)];
+      module_manager.add_module_net_source(mux_module, net, decoder_module, decoder_instance, decoder_module_data_inv_port_id, pin);
+      /* Add the module nets to mux_mem_inv_nets cache */
+      mem_inv_net_cnt++;
+    }
+  } 
+  VTR_ASSERT(mem_net_cnt == mux_graph.num_memory_bits());
+  VTR_ASSERT(mem_inv_net_cnt == mux_graph.num_memory_bits());
+}
+
+/*********************************************************************
+ * Generate module of a CMOS multiplexer with the given size 
+ * The module will consist of three parts:
+ * 1. instances of the branch circuits of multiplexers which are generated before  
+ *    This builds up the multiplexing structure
+ * 2. Input buffers/inverters
+ * 3. Output buffers/inverters
+ *********************************************************************/
+static 
+void build_cmos_mux_module(ModuleManager& module_manager,
+                           const CircuitLibrary& circuit_lib, 
+                           const CircuitModelId& mux_model, 
+                           const std::string& module_name, 
+                           const MuxGraph& mux_graph) {
+  /* Get the global ports required by MUX (and any submodules) */
+  std::vector<CircuitPortId> mux_global_ports = circuit_lib.model_global_ports_by_type(mux_model, CIRCUIT_MODEL_PORT_INPUT, true, true);
+  /* Get the input ports from the mux */
+  std::vector<CircuitPortId> mux_input_ports = circuit_lib.model_ports_by_type(mux_model, CIRCUIT_MODEL_PORT_INPUT, true);
+  /* Get the output ports from the mux */
+  std::vector<CircuitPortId> mux_output_ports = circuit_lib.model_ports_by_type(mux_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
+  /* Get the sram ports from the mux 
+   * Multiplexing structure does not mode_sram_ports, they are handled in LUT modules
+   * Here we just bypass it.
+   */
+  std::vector<CircuitPortId> mux_sram_ports = find_circuit_regular_sram_ports(circuit_lib, mux_model);
+
+  /* Generate the Verilog netlist according to the mux_graph */
+  /* Find out the number of data-path inputs */ 
+  size_t num_inputs = find_mux_num_datapath_inputs(circuit_lib, mux_model, mux_graph.num_inputs());
+  /* Find out the number of outputs */ 
+  size_t num_outputs = mux_graph.num_outputs();
+  /* Find out the number of memory bits */ 
+  size_t num_mems = mux_graph.num_memory_bits();
+
+  /* The size of of memory ports depend on 
+   * if a local encoder is used for the mux or not 
+   * Multiplexer local encoders are applied to memory bits at each stage 
+   */
+  if (true == circuit_lib.mux_use_local_encoder(mux_model)) {
+    num_mems = 0;
+    for (const auto& lvl : mux_graph.levels()) {
+      size_t data_size = mux_graph.num_memory_bits_at_level(lvl);
+      num_mems += find_mux_local_decoder_addr_size(data_size);
+    } 
+  }
+
+  /* Check codes to ensure the port of Verilog netlists will match */
+  /* MUX graph must have only 1 output */
+  VTR_ASSERT(1 == mux_input_ports.size());
+  /* A quick check on the model ports */
+  if ((CIRCUIT_MODEL_MUX == circuit_lib.model_type(mux_model))
+    || ((CIRCUIT_MODEL_LUT == circuit_lib.model_type(mux_model))
+       && (false == circuit_lib.is_lut_fracturable(mux_model))) ) {
+    VTR_ASSERT(1 == mux_output_ports.size());
+    VTR_ASSERT(1 == circuit_lib.port_size(mux_output_ports[0])); 
+  } else {
+    VTR_ASSERT_SAFE( (CIRCUIT_MODEL_LUT == circuit_lib.model_type(mux_model)) 
+                 && (true == circuit_lib.is_lut_fracturable(mux_model)) );
+    for (const auto& port : mux_output_ports) {
+      VTR_ASSERT(0 < circuit_lib.port_size(port));
+    }
+  }
+
+  /* Create a Verilog Module based on the circuit model, and add to module manager */
+  ModuleId mux_module = module_manager.add_module(module_name); 
+  VTR_ASSERT(ModuleId::INVALID() != mux_module);
+  /* Add module ports */
+  /* Add each input port
+   * Treat MUX and LUT differently 
+   * 1. MUXes: we do not have a specific input/output sizes, it is inferred by architecture 
+   * 2. LUTes: we do have specific input/output sizes, 
+   *           but the inputs of MUXes are the SRAM ports of LUTs
+   *           and the SRAM ports of MUXes are the inputs of LUTs
+   */
+  size_t input_port_cnt = 0;
+  for (const auto& port : mux_input_ports) {
+    BasicPort input_port(circuit_lib.port_prefix(port), num_inputs);
+    module_manager.add_port(mux_module, input_port, ModuleManager::MODULE_INPUT_PORT);
+    /* Update counter */
+    input_port_cnt++;
+  }
+  /* Double check: We should have only 1 input port generated here! */
+  VTR_ASSERT(1 == input_port_cnt);
+
+  /* Add input buffers and update module nets for inputs */
+  vtr::vector<MuxInputId, ModuleNetId> mux_input_nets = build_mux_module_input_buffers(module_manager, circuit_lib, mux_module, mux_model, mux_graph);
+
+  for (const auto& port : mux_output_ports) {
+    BasicPort output_port(circuit_lib.port_prefix(port), num_outputs);
+    if (CIRCUIT_MODEL_LUT == circuit_lib.model_type(mux_model)) {
+      output_port.set_width(circuit_lib.port_size(port));
+    }
+    module_manager.add_port(mux_module, output_port, ModuleManager::MODULE_OUTPUT_PORT);
+  }
+
+  /* TODO: Add output buffers and update module nets for outputs */
+  vtr::vector<MuxOutputId, ModuleNetId> mux_output_nets = build_mux_module_output_buffers(module_manager, circuit_lib, mux_module, mux_model, mux_graph);
+
+  size_t sram_port_cnt = 0;
+  for (const auto& port : mux_sram_ports) {
+    BasicPort mem_port(circuit_lib.port_prefix(port), num_mems);
+    module_manager.add_port(mux_module, mem_port, ModuleManager::MODULE_INPUT_PORT);
+    BasicPort mem_inv_port(std::string(circuit_lib.port_prefix(port) + "_inv"), num_mems);
+    module_manager.add_port(mux_module, mem_inv_port, ModuleManager::MODULE_INPUT_PORT);
+    /* Update counter */
+    sram_port_cnt++;
+  }
+  VTR_ASSERT(1 == sram_port_cnt);
+
+  /* Create module nets for mem and mem_inv ports */
+  vtr::vector<MuxMemId, ModuleNetId> mux_mem_nets;
+  vtr::vector<MuxMemId, ModuleNetId> mux_mem_inv_nets;
+  
+  build_mux_module_local_encoders_and_memory_nets(module_manager, mux_module, 
+                                                  circuit_lib, mux_model, mux_sram_ports, 
+                                                  mux_graph,
+                                                  mux_mem_nets, mux_mem_inv_nets);
+  
+  /* Print the internal logic in Verilog codes */
+  /* Print the Multiplexing structure in Verilog codes 
+   * Separated generation strategy on using standard cell MUX2 or TGATE,
+   * 1. MUX2 has a fixed port map: input_port[0] and input_port[1] is the data_path input 
+   * 2. Branch TGATE-based module has a fixed port name  
+   * TODO: the naming could be more flexible? 
+   */
+  /* Get the tgate model */
+  CircuitModelId tgate_model = circuit_lib.pass_gate_logic_model(mux_model);
+  /* Instanciate the branch module: 
+   * Case 1: the branch module is a standard cell MUX2
+   * Case 2: the branch module is a tgate-based module  
+   */
+  std::string branch_module_name;
+  if (CIRCUIT_MODEL_GATE == circuit_lib.model_type(tgate_model)) {
+    VTR_ASSERT(CIRCUIT_MODEL_GATE_MUX2 == circuit_lib.gate_type(tgate_model));
+    build_cmos_mux_module_mux2_multiplexing_structure(module_manager, circuit_lib, mux_module, mux_model, tgate_model, mux_input_nets, mux_output_nets, mux_mem_nets, mux_graph);
+  } else {
+    VTR_ASSERT(CIRCUIT_MODEL_PASSGATE == circuit_lib.model_type(tgate_model));
+    build_cmos_mux_module_tgate_multiplexing_structure(module_manager, circuit_lib, mux_module, mux_model, mux_input_nets, mux_output_nets, mux_mem_nets, mux_mem_inv_nets, mux_graph);
+  }
+
+  /* Add global ports to the pb_module:
+   * This is a much easier job after adding sub modules (instances), 
+   * we just need to find all the global ports from the child modules and build a list of it
+   */
+  add_module_global_ports_from_child_modules(module_manager, mux_module);
+}
+
+/*********************************************************************
+ * Generate a module of a RRAM-based multiplexer with the given size 
+ * The module will consist of three parts:
+ * 1. instances of the branch circuits of multiplexers which are generated before  
+ *    This builds up the 4T1R-based multiplexing structure
+ *
+ *                    BLB   WL
+ *                     |    |       ...
+ *                     v    v
+ *                   +--------+            
+ *           in[0]-->|        |            BLB   WL 
+ *                ...| Branch |-----+       |    |
+ *             in -->|   0    |     |       v    v
+ *            [N-1]  +--------+     |     +--------+
+ *                      ...            -->|        |
+ *                    BLBs WLs         ...| Branch |
+ *                     |    |    ...   -->|   X    |
+ *                     v    v             +--------+
+ *                   +--------+    |
+ *                -->|        |    |
+ *                ...| Branch |----+
+ *                -->|   i    |
+ *                   +--------+
+ *
+ * 2. Input buffers/inverters
+ * 3. Output buffers/inverters
+ *********************************************************************/
+static 
+void build_rram_mux_module(ModuleManager& module_manager,
+                           const CircuitLibrary& circuit_lib, 
+                           const CircuitModelId& circuit_model, 
+                           const std::string& module_name, 
+                           const MuxGraph& mux_graph) {
+  /* Error out for the conditions where we are not yet supported! */
+  if (CIRCUIT_MODEL_LUT == circuit_lib.model_type(circuit_model)) {
+    /* RRAM LUT is not supported now... */
+    VTR_LOG_ERROR("RRAM-based LUT is not supported for circuit model '%s')!\n",
+                  circuit_lib.model_name(circuit_model).c_str());
+    exit(1);
+  }
+
+  /* Get the global ports required by MUX (and any submodules) */
+  std::vector<CircuitPortId> mux_global_ports = circuit_lib.model_global_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true, true);
+  /* Get the input ports from the mux */
+  std::vector<CircuitPortId> mux_input_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true);
+  /* Get the output ports from the mux */
+  std::vector<CircuitPortId> mux_output_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
+  /* Get the BL and WL ports from the mux */
+  std::vector<CircuitPortId> mux_blb_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_BLB, true);
+  std::vector<CircuitPortId> mux_wl_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_WL, true);
+
+  /* Generate the Verilog netlist according to the mux_graph */
+  /* Find out the number of data-path inputs */ 
+  size_t num_inputs = find_mux_num_datapath_inputs(circuit_lib, circuit_model, mux_graph.num_inputs());
+  /* Find out the number of outputs */ 
+  size_t num_outputs = mux_graph.num_outputs();
+  /* Find out the number of memory bits */ 
+  size_t num_mems = mux_graph.num_memory_bits();
+
+  /* Check codes to ensure the port of Verilog netlists will match */
+  /* MUX graph must have only 1 input and 1 BLB and 1 WL port */
+  VTR_ASSERT(1 == mux_input_ports.size());
+  VTR_ASSERT(1 == mux_blb_ports.size());
+  VTR_ASSERT(1 == mux_wl_ports.size());
+
+  /* Create a Verilog Module based on the circuit model, and add to module manager */
+  ModuleId module_id = module_manager.add_module(module_name); 
+  VTR_ASSERT(ModuleId::INVALID() != module_id);
+  /* Add module ports */
+  /* Add each global port */
+  for (const auto& port : mux_global_ports) {
+    /* Configure each global port */
+    BasicPort global_port(circuit_lib.port_prefix(port), circuit_lib.port_size(port));
+    module_manager.add_port(module_id, global_port, ModuleManager::MODULE_GLOBAL_PORT);
+  }
+  /* Add each input port */
+  size_t input_port_cnt = 0;
+  for (const auto& port : mux_input_ports) {
+    BasicPort input_port(circuit_lib.port_prefix(port), num_inputs);
+    module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT);
+    /* Update counter */
+    input_port_cnt++;
+  }
+  /* Double check: We should have only 1 input port generated here! */
+  VTR_ASSERT(1 == input_port_cnt);
+
+  for (const auto& port : mux_output_ports) {
+    BasicPort output_port(circuit_lib.port_prefix(port), num_outputs);
+    if (CIRCUIT_MODEL_LUT == circuit_lib.model_type(circuit_model)) {
+      output_port.set_width(circuit_lib.port_size(port));
+    }
+    module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT);
+  }
+
+  /* BLB port */
+  for (const auto& port : mux_blb_ports) {
+    /* IMPORTANT: RRAM-based MUX has an additional BLB pin per level 
+     * So, the actual port width of BLB should be added by the number of levels of the MUX graph 
+     */
+    BasicPort blb_port(circuit_lib.port_prefix(port), num_mems + mux_graph.num_levels());
+    module_manager.add_port(module_id, blb_port, ModuleManager::MODULE_INPUT_PORT);
+  }
+
+  /* WL port */
+  for (const auto& port : mux_wl_ports) {
+    /* IMPORTANT: RRAM-based MUX has an additional WL pin per level 
+     * So, the actual port width of WL should be added by the number of levels of the MUX graph 
+     */
+    BasicPort wl_port(circuit_lib.port_prefix(port), num_mems + mux_graph.num_levels());
+    module_manager.add_port(module_id, wl_port, ModuleManager::MODULE_INPUT_PORT);
+  }
+
+  /* TODO: Add the input and output buffers in Verilog codes */
+ 
+  /* TODO: Print the internal logic in Verilog codes */
+}
+
+/***********************************************
+ * Generate Verilog codes modeling a multiplexer 
+ * with the given graph-level description
+ **********************************************/
+static 
+void build_mux_module(ModuleManager& module_manager,
+                      const CircuitLibrary& circuit_lib, 
+                      const CircuitModelId& circuit_model, 
+                      const MuxGraph& mux_graph) {
+  std::string module_name = generate_mux_subckt_name(circuit_lib, circuit_model, 
+                                                     find_mux_num_datapath_inputs(circuit_lib, circuit_model, mux_graph.num_inputs()), 
+                                                     std::string(""));
+ 
+  /* Multiplexers built with different technology is in different organization */
+  switch (circuit_lib.design_tech_type(circuit_model)) {
+  case CIRCUIT_MODEL_DESIGN_CMOS:
+    /* SRAM-based Multiplexer Verilog module generation */
+    build_cmos_mux_module(module_manager, circuit_lib, circuit_model, module_name, mux_graph);
+    break;
+  case CIRCUIT_MODEL_DESIGN_RRAM:
+    /* TODO: RRAM-based Multiplexer Verilog module generation */
+    build_rram_mux_module(module_manager, circuit_lib, circuit_model, module_name, mux_graph);
+    break;
+  default:
+    VTR_LOG_ERROR("Invalid design technology of multiplexer '%s'\n",
+                 circuit_lib.model_name(circuit_model).c_str()); 
+    exit(1);
+  }
+}
+
+/***********************************************
+ * Generate Verilog modules for all the unique
+ * multiplexers in the FPGA device
+ **********************************************/
+void build_mux_modules(ModuleManager& module_manager,
+                       const MuxLibrary& mux_lib,
+                       const CircuitLibrary& circuit_lib) {
+  vtr::ScopedStartFinishTimer timer("Building multiplexer modules");
+
+  /* Generate basis sub-circuit for unique branches shared by the multiplexers */
+  for (auto mux : mux_lib.muxes()) {
+    const MuxGraph& mux_graph = mux_lib.mux_graph(mux);
+    CircuitModelId mux_circuit_model = mux_lib.mux_circuit_model(mux); 
+    /* Create a mux graph for the branch circuit */
+    std::vector<MuxGraph> branch_mux_graphs = mux_graph.build_mux_branch_graphs();
+    /* Create branch circuits, which are N:1 one-level or 2:1 tree-like MUXes */
+    for (auto branch_mux_graph : branch_mux_graphs) {
+      build_mux_branch_module(module_manager, circuit_lib, mux_circuit_model, 
+                              find_mux_num_datapath_inputs(circuit_lib, mux_circuit_model, mux_graph.num_inputs()), 
+                              branch_mux_graph);
+    }
+  }
+
+  /* Generate unique Verilog modules for the multiplexers */
+  for (auto mux : mux_lib.muxes()) {
+    const MuxGraph& mux_graph = mux_lib.mux_graph(mux);
+    CircuitModelId mux_circuit_model = mux_lib.mux_circuit_model(mux); 
+    /* Create MUX circuits */
+    build_mux_module(module_manager, circuit_lib, mux_circuit_model, mux_graph);
+  }
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fabric/build_mux_modules.h b/openfpga/src/fabric/build_mux_modules.h
new file mode 100644
index 000000000..8326eeb74
--- /dev/null
+++ b/openfpga/src/fabric/build_mux_modules.h
@@ -0,0 +1,24 @@
+#ifndef BUILD_MUX_MODULES_H
+#define BUILD_MUX_MODULES_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "circuit_library.h"
+#include "mux_library.h"
+#include "module_manager.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void build_mux_modules(ModuleManager& module_manager,
+                       const MuxLibrary& mux_lib,
+                       const CircuitLibrary& circuit_lib);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
index b517fa24b..2a4bb1b02 100644
--- a/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
@@ -149,7 +149,7 @@
        <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
     </circuit_model>
     <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
-      <design_technology type="cmos"/>
+      <design_technology type="cmos" fracturable_lut="true"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
       <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>

From e842150cc5dfdf929d1c2bc5be404d62ef0556fd Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 12 Feb 2020 19:52:41 -0700
Subject: [PATCH 127/645] add lut module builder

---
 openfpga/src/fabric/build_device_module.cpp   |   4 +-
 openfpga/src/fabric/build_lut_modules.cpp     | 406 ++++++++++++++++++
 openfpga/src/fabric/build_lut_modules.h       |  22 +
 .../k6_frac_N10_40nm_openfpga.xml             |   2 +-
 4 files changed, 431 insertions(+), 3 deletions(-)
 create mode 100644 openfpga/src/fabric/build_lut_modules.cpp
 create mode 100644 openfpga/src/fabric/build_lut_modules.h

diff --git a/openfpga/src/fabric/build_device_module.cpp b/openfpga/src/fabric/build_device_module.cpp
index a322422df..5e8b090f2 100644
--- a/openfpga/src/fabric/build_device_module.cpp
+++ b/openfpga/src/fabric/build_device_module.cpp
@@ -11,7 +11,7 @@
 #include "build_essential_modules.h"
 #include "build_decoder_modules.h"
 #include "build_mux_modules.h"
-//#include "build_lut_modules.h"
+#include "build_lut_modules.h"
 //#include "build_wire_modules.h"
 //#include "build_memory_modules.h"
 //#include "build_grid_modules.h"
@@ -56,7 +56,7 @@ ModuleManager build_device_module_graph(const DeviceContext& vpr_device_ctx,
   build_mux_modules(module_manager, openfpga_ctx.mux_lib(), openfpga_ctx.arch().circuit_lib);
 
   /* Build LUT modules */
-  //build_lut_modules(module_manager, arch.spice->circuit_lib);
+  build_lut_modules(module_manager, openfpga_ctx.arch().circuit_lib);
 
   /* Build wire modules */
   //build_wire_modules(module_manager, arch.spice->circuit_lib);
diff --git a/openfpga/src/fabric/build_lut_modules.cpp b/openfpga/src/fabric/build_lut_modules.cpp
new file mode 100644
index 000000000..c799fe75a
--- /dev/null
+++ b/openfpga/src/fabric/build_lut_modules.cpp
@@ -0,0 +1,406 @@
+/******************************************************************** 
+ * This file include functions that create modules for 
+ * the Look-Up Tables (LUTs) 
+ ********************************************************************/
+#include <string>
+#include <vector>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+#include "vtr_time.h"
+
+#include "openfpga_naming.h"
+#include "circuit_library_utils.h"
+#include "module_manager.h"
+#include "module_manager_utils.h"
+
+#include "build_module_graph_utils.h"
+#include "build_lut_modules.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Build a module for a LUT circuit model
+ * This function supports both single-output and fracturable LUTs
+ * The module will be organized in a connected graph of the following instances:
+ * 1. Multiplexer used inside LUT
+ * 2. Input buffers 
+ * 3. Input inverters
+ * 4. Output buffers.
+ * 6. AND/OR gates to tri-state LUT inputs
+ ********************************************************************/
+static 
+void build_lut_module(ModuleManager& module_manager,
+                      const CircuitLibrary& circuit_lib,
+                      const CircuitModelId& lut_model) {
+  /* Get the global ports required by LUT
+   * Note that this function will only add global ports from LUT circuit model definition itself
+   * We should NOT go recursively here. 
+   * The global ports of sub module will be handled by another function !!! 
+   *   add_module_global_ports_from_child_modules(module_manager, lut_module);
+   */
+  std::vector<CircuitPortId> lut_global_ports = circuit_lib.model_global_ports_by_type(lut_model, CIRCUIT_MODEL_PORT_INPUT, false, true);
+  /* Get the input ports from the mux */
+  std::vector<CircuitPortId> lut_input_ports = circuit_lib.model_ports_by_type(lut_model, CIRCUIT_MODEL_PORT_INPUT, true);
+  /* Get the output ports from the mux */
+  std::vector<CircuitPortId> lut_output_ports = circuit_lib.model_ports_by_type(lut_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
+
+  /* Classify SRAM ports into two categories: regular (not for mode select) and mode-select */
+  std::vector<CircuitPortId> lut_regular_sram_ports = find_circuit_regular_sram_ports(circuit_lib, lut_model);
+  std::vector<CircuitPortId> lut_mode_select_sram_ports = find_circuit_mode_select_sram_ports(circuit_lib, lut_model);
+
+  /*********************************************** 
+   * Model Port Sanity Check
+   ***********************************************/  
+  /* Make sure that the number of ports and sizes of ports are what we want */
+  if (false == circuit_lib.is_lut_fracturable(lut_model)) {
+    /* Single-output LUTs: 
+     * We should have only 1 input port, 1 output port and 1 SRAM port
+     */
+    VTR_ASSERT (1 == lut_input_ports.size());
+    VTR_ASSERT (1 == lut_output_ports.size());
+    VTR_ASSERT (1 == lut_regular_sram_ports.size()); 
+    VTR_ASSERT (0 == lut_mode_select_sram_ports.size()); 
+  } else {
+    VTR_ASSERT (true == circuit_lib.is_lut_fracturable(lut_model));
+    /* Fracturable LUT:
+     * We should have only 1 input port, a few output ports (fracturable outputs)
+     * and two SRAM ports
+     */
+    VTR_ASSERT (1 == lut_input_ports.size());
+    VTR_ASSERT (1 <= lut_output_ports.size());
+    VTR_ASSERT (1 == lut_regular_sram_ports.size()); 
+    VTR_ASSERT (1 == lut_mode_select_sram_ports.size()); 
+  }
+
+  /*********************************************** 
+   * Module Port addition
+   ***********************************************/  
+  /* Create a Verilog Module based on the circuit model, and add to module manager */
+  ModuleId lut_module = module_manager.add_module(circuit_lib.model_name(lut_model)); 
+  VTR_ASSERT(true == module_manager.valid_module_id(lut_module));
+  /* Add module ports */
+  /* Add each global port */
+  for (const auto& port : lut_global_ports) {
+    /* Configure each global port */
+    BasicPort global_port(circuit_lib.port_prefix(port), circuit_lib.port_size(port));
+    module_manager.add_port(lut_module, global_port, ModuleManager::MODULE_GLOBAL_PORT);
+  }
+  /* Add each input port */
+  for (const auto& port : lut_input_ports) {
+    BasicPort input_port(circuit_lib.port_prefix(port), circuit_lib.port_size(port));
+    module_manager.add_port(lut_module, input_port, ModuleManager::MODULE_INPUT_PORT);
+    /* Set the port to be wire-connection */
+    module_manager.set_port_is_wire(lut_module, input_port.get_name(), true);
+  }
+  /* Add each output port */
+  for (const auto& port : lut_output_ports) {
+    BasicPort output_port(circuit_lib.port_prefix(port), circuit_lib.port_size(port));
+    module_manager.add_port(lut_module, output_port, ModuleManager::MODULE_OUTPUT_PORT);
+    /* Set the port to be wire-connection */
+    module_manager.set_port_is_wire(lut_module, output_port.get_name(), true);
+  }
+  /* Add each regular (not mode select) SRAM port */
+  for (const auto& port : lut_regular_sram_ports) {
+    BasicPort mem_port(circuit_lib.port_prefix(port), circuit_lib.port_size(port));
+    module_manager.add_port(lut_module, mem_port, ModuleManager::MODULE_INPUT_PORT);
+    BasicPort mem_inv_port(std::string(circuit_lib.port_prefix(port) + "_inv"), circuit_lib.port_size(port));
+    module_manager.add_port(lut_module, mem_inv_port, ModuleManager::MODULE_INPUT_PORT);
+  }
+
+  /* Add each mode-select SRAM port */
+  for (const auto& port : lut_mode_select_sram_ports) {
+    BasicPort mem_port(circuit_lib.port_prefix(port), circuit_lib.port_size(port));
+    module_manager.add_port(lut_module, mem_port, ModuleManager::MODULE_INPUT_PORT);
+    BasicPort mem_inv_port(std::string(circuit_lib.port_prefix(port) + "_inv"), circuit_lib.port_size(port));
+    module_manager.add_port(lut_module, mem_inv_port, ModuleManager::MODULE_INPUT_PORT);
+  }
+
+  /*********************************************** 
+   * Child module addition: Model-select gates
+   ***********************************************/  
+  /* Module nets after the mode-selection circuit, this could include LUT inputs */
+  std::vector<ModuleNetId> mode_selected_nets;
+  /* Instanciate mode selecting circuit: AND/OR gate 
+   * By following the tri-state map of LUT input port
+   * The wiring of input ports will be organized as follows
+   *
+   *                   LUT input
+   *                       |
+   *                       v
+   *                  +----------+
+   *                  |   mode   |
+   *                  | selector |
+   *                  +----------+
+   *                       | mode_selected_nets
+   *                       v
+   *     +-----------------+------------+
+   *     |                              |
+   *     v                              v
+   *  +----------+                 +---------+
+   *  | Inverter |                 |  Buffer |
+   *  +----------+                 +---------+
+   *       | inverter_output_net        | buffered_output_net
+   *       v                            v
+   *  +--------------------------------------+
+   *  |      LUT Multiplexing Structure      |
+   *  +--------------------------------------+
+   */
+  /* Get the tri-state port map for the input ports*/
+  std::string tri_state_map = circuit_lib.port_tri_state_map(lut_input_ports[0]);
+  size_t mode_select_port_lsb = 0;
+  for (const auto& pin : circuit_lib.pins(lut_input_ports[0])) {
+    ModulePortId lut_module_input_port_id = module_manager.find_module_port(lut_module, circuit_lib.port_prefix(lut_input_ports[0]));
+    VTR_ASSERT(true == module_manager.valid_module_port_id(lut_module, lut_module_input_port_id));
+
+    /* Create a module net for the connection */
+    ModuleNetId net = module_manager.create_module_net(lut_module);
+    /* Set the source of the net to an lut input port */
+    module_manager.add_module_net_source(lut_module, net, lut_module, 0, lut_module_input_port_id, pin);
+    
+    /* For an empty tri-state map or a '-' sign in tri-state map, we can short-wire mode select_output_ports */
+    if (tri_state_map.empty() || ('-' == tri_state_map[pin]) ) {
+      /* Update the output nets of the mode-select layer */
+      mode_selected_nets.push_back(net); 
+      continue; /* Finish here */
+    }
+
+    e_circuit_model_gate_type required_gate_type = NUM_CIRCUIT_MODEL_GATE_TYPES;
+    /* Reach here, it means that we need a circuit for mode selection */
+    if ('0' == tri_state_map[pin]) {
+      /* We need a 2-input AND gate, in order to tri-state the input 
+       * Detailed circuit is as follow:
+       *              +---------+
+       *     SRAM --->| 2-input |----> mode_select_output_port
+       * LUT input--->|   AND   |
+       *              +---------+
+       * When SRAM is set to logic 0, the LUT input is tri-stated
+       * When SRAM is set to logic 1, the LUT input is effective to the downstream circuits
+       */
+       required_gate_type = CIRCUIT_MODEL_GATE_AND;
+    } else {
+      VTR_ASSERT ('1' == tri_state_map[pin]);
+      /* We need a 2-input OR gate, in order to tri-state the input 
+       * Detailed circuit is as follow:
+       *              +---------+
+       *     SRAM --->| 2-input |----> mode_select_output_port
+       * LUT input--->|   OR    |
+       *              +---------+
+       * When SRAM is set to logic 1, the LUT input is tri-stated
+       * When SRAM is set to logic 0, the LUT input is effective to the downstream circuits
+       */
+       required_gate_type = CIRCUIT_MODEL_GATE_OR;
+    } 
+    /* Get the circuit model of the gate */
+    CircuitModelId gate_model = circuit_lib.port_tri_state_model(lut_input_ports[0]);
+    /* Check this is the gate we want ! */
+    VTR_ASSERT (required_gate_type == circuit_lib.gate_type(gate_model));
+
+    /* Prepare for the gate instanciation */
+    /* Get the input ports from the gate */
+    std::vector<CircuitPortId> gate_input_ports = circuit_lib.model_ports_by_type(gate_model, CIRCUIT_MODEL_PORT_INPUT, true);
+    /* Get the output ports from the gate */
+    std::vector<CircuitPortId> gate_output_ports = circuit_lib.model_ports_by_type(gate_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
+    /* Check the port sizes and width: 
+     * we should have only 2 input ports, each of which has a size of 1 
+     * we should have only 1 output port, each of which has a size of 1 
+     */
+    VTR_ASSERT (2 == gate_input_ports.size());
+    VTR_ASSERT (1 == gate_output_ports.size());
+    /* Find the module id of gate_model in the module manager */
+    ModuleId gate_module = module_manager.find_module(circuit_lib.model_name(gate_model));
+    /* We must have a valid id */
+    VTR_ASSERT (true == module_manager.valid_module_id(gate_module));
+    size_t gate_instance = module_manager.num_instance(lut_module, gate_module);
+    module_manager.add_child_module(lut_module, gate_module);
+
+    /* Create a port-to-port net connection:
+     * Input[0] of the gate is wired to a SRAM mode-select port 
+     * Input[1] of the gate is wired to the input port of LUT
+     * Output[0] of the gate is wired to the mode_select_output_port 
+     */
+    /* Create a module net for the connection */
+    ModuleNetId gate_sram_net = module_manager.create_module_net(lut_module);
+
+    /* Find the module port id of the SRAM port of LUT module */
+    ModulePortId lut_module_mode_select_port_id = module_manager.find_module_port(lut_module, circuit_lib.port_prefix(lut_mode_select_sram_ports[0]));
+    VTR_ASSERT(true == module_manager.valid_module_port_id(lut_module, lut_module_mode_select_port_id));
+    /* Set the source of the net to an mode-select SRAM port of the LUT module */
+    module_manager.add_module_net_source(lut_module, gate_sram_net, lut_module, 0, lut_module_mode_select_port_id, mode_select_port_lsb);
+
+    /* Find the module port id of the SRAM port of LUT module */
+    ModulePortId gate_module_input0_port_id = module_manager.find_module_port(gate_module, circuit_lib.port_prefix(gate_input_ports[0]));
+    VTR_ASSERT(true == module_manager.valid_module_port_id(gate_module, gate_module_input0_port_id));
+    /* Set the sink of the net to an input[0] port of the gate module */
+    VTR_ASSERT(1 == module_manager.module_port(gate_module, gate_module_input0_port_id).get_width());
+    for (const size_t& gate_pin : module_manager.module_port(gate_module, gate_module_input0_port_id).pins()) {
+      module_manager.add_module_net_sink(lut_module, gate_sram_net, gate_module, gate_instance, gate_module_input0_port_id, gate_pin);
+    }
+
+    /* Use the existing net to connect to the input[1] port of the gate module */
+    ModulePortId gate_module_input1_port_id = module_manager.find_module_port(gate_module, circuit_lib.port_prefix(gate_input_ports[1]));
+    VTR_ASSERT(true == module_manager.valid_module_port_id(gate_module, gate_module_input1_port_id));
+    VTR_ASSERT(1 == module_manager.module_port(gate_module, gate_module_input1_port_id).get_width());
+    for (const size_t& gate_pin : module_manager.module_port(gate_module, gate_module_input1_port_id).pins()) {
+      module_manager.add_module_net_sink(lut_module, net, gate_module, gate_instance, gate_module_input1_port_id, gate_pin);
+    }
+
+    /* Create a module net for the output connection */
+    ModuleNetId gate_output_net = module_manager.create_module_net(lut_module);
+    ModulePortId gate_module_output_port_id = module_manager.find_module_port(gate_module, circuit_lib.port_prefix(gate_output_ports[0]));
+    VTR_ASSERT(true == module_manager.valid_module_port_id(gate_module, gate_module_output_port_id));
+    BasicPort gate_module_output_port = module_manager.module_port(gate_module, gate_module_output_port_id);
+    VTR_ASSERT(1 == gate_module_output_port.get_width());
+    module_manager.add_module_net_source(lut_module, gate_output_net, gate_module, gate_instance, gate_module_output_port_id, gate_module_output_port.get_lsb());
+
+    /* Update the output nets of the mode-select layer */
+    mode_selected_nets.push_back(gate_output_net); 
+
+    /* update the lsb of mode select port size */
+    mode_select_port_lsb++;
+  }
+
+  /* Sanitity check */
+  if ( true == circuit_lib.is_lut_fracturable(lut_model) ) {
+    if (mode_select_port_lsb != circuit_lib.port_size(lut_mode_select_sram_ports[0])) {
+      VTR_LOG_ERROR("(ircuit model '%s' has a unmatched tri-state map '%s' implied by mode_port size='%d'!\n",
+                    circuit_lib.model_name(lut_model).c_str(), 
+                    tri_state_map.c_str(), 
+                    circuit_lib.port_size(lut_mode_select_sram_ports[0])); 
+      exit(1);
+    }
+  }
+
+  /*********************************************** 
+   * Child module addition: Input inverters
+   ***********************************************/  
+  /* Find the circuit model of the input inverter */
+  CircuitModelId input_inverter_model = circuit_lib.lut_input_inverter_model(lut_model);
+  VTR_ASSERT( CircuitModelId::INVALID() != input_inverter_model );
+
+  std::vector<ModuleNetId> lut_mux_sram_inv_nets;
+  /* Now we need to add inverters by instanciating the modules */
+  for (size_t pin = 0; pin < circuit_lib.port_size(lut_input_ports[0]); ++pin) {
+    ModuleNetId lut_mux_sram_inv_net = add_inverter_buffer_child_module_and_nets(module_manager, lut_module, 
+                                                                                 circuit_lib, input_inverter_model,
+                                                                                 mode_selected_nets[pin]); 
+    /* Update the net vector */ 
+    lut_mux_sram_inv_nets.push_back(lut_mux_sram_inv_net);
+  }
+
+  /*********************************************** 
+   * Child module addition: Input buffers
+   ***********************************************/  
+  /* Add buffers to mode_select output ports  */
+  /* Find the circuit model of the input inverter */
+  CircuitModelId input_buffer_model = circuit_lib.lut_input_buffer_model(lut_model);
+  VTR_ASSERT( CircuitModelId::INVALID() != input_buffer_model );
+
+  std::vector<ModuleNetId> lut_mux_sram_nets;
+  /* Now we need to add inverters by instanciating the modules and add module nets */
+  for (size_t pin = 0; pin < circuit_lib.port_size(lut_input_ports[0]); ++pin) {
+    ModuleNetId lut_mux_sram_net = add_inverter_buffer_child_module_and_nets(module_manager, lut_module, 
+                                                                             circuit_lib, input_buffer_model,
+                                                                             mode_selected_nets[pin]); 
+    /* Update the net vector */ 
+    lut_mux_sram_nets.push_back(lut_mux_sram_net);
+  }
+
+  /*********************************************** 
+   * Child module addition: LUT MUX 
+   ***********************************************/  
+  /* Find the name of LUT MUX: no need to provide a mux size, just give an invalid number (=-1) */
+  std::string lut_mux_module_name = generate_mux_subckt_name(circuit_lib, lut_model, size_t(-1), std::string(""));
+  /* Find the module id of LUT MUX in the module manager */
+  ModuleId lut_mux_module = module_manager.find_module(lut_mux_module_name);
+  /* We must have a valid id */
+  VTR_ASSERT (ModuleId::INVALID() != lut_mux_module);
+  /* Instanciate a LUT MUX as child module */
+  size_t lut_mux_instance = module_manager.num_instance(lut_module, lut_mux_module);
+  module_manager.add_child_module(lut_module, lut_mux_module);
+
+  /* TODO: Build module nets to connect
+   * 1. SRAM ports of LUT MUX module to output ports of input buffer
+   * 2. Inverted SRAM ports of LUT MUX module to output ports of input inverters
+   * 3. Data input of LUT MUX module to SRAM port of LUT
+   * 4. Data output of LUT MUX module to output ports of LUT
+   */
+  ModulePortId lut_mux_sram_port_id = module_manager.find_module_port(lut_mux_module, circuit_lib.port_prefix(lut_regular_sram_ports[0]));
+  BasicPort lut_mux_sram_port = module_manager.module_port(lut_mux_module, lut_mux_sram_port_id);
+  VTR_ASSERT(lut_mux_sram_port.get_width() == lut_mux_sram_nets.size());
+  /* Wire the port to lut_mux_sram_net */
+  for (const size_t& pin : lut_mux_sram_port.pins()) {
+    module_manager.add_module_net_sink(lut_module, lut_mux_sram_nets[pin], lut_mux_module, lut_mux_instance, lut_mux_sram_port_id, pin);
+  } 
+
+  ModulePortId lut_mux_sram_inv_port_id = module_manager.find_module_port(lut_mux_module, std::string(circuit_lib.port_prefix(lut_regular_sram_ports[0]) + "_inv"));
+  BasicPort lut_mux_sram_inv_port = module_manager.module_port(lut_mux_module, lut_mux_sram_inv_port_id);
+  VTR_ASSERT(lut_mux_sram_inv_port.get_width() == lut_mux_sram_inv_nets.size());
+  /* Wire the port to lut_mux_sram_net */
+  for (const size_t& pin : lut_mux_sram_inv_port.pins()) {
+    module_manager.add_module_net_sink(lut_module, lut_mux_sram_inv_nets[pin], lut_mux_module, lut_mux_instance, lut_mux_sram_inv_port_id, pin);
+  } 
+  
+  /*           lut_module
+   *          +------------
+   *          |     +------
+   *  sram -->|---->| (lut_mux_input_port)
+   *          |  ^  |  LUT MUX
+   *          |  |  |
+   *             |
+   *            net
+   */  
+  ModulePortId lut_sram_port_id = module_manager.find_module_port(lut_module, circuit_lib.port_prefix(lut_regular_sram_ports[0]));
+  BasicPort lut_sram_port = module_manager.module_port(lut_module, lut_sram_port_id);
+  ModulePortId lut_mux_input_port_id = module_manager.find_module_port(lut_mux_module, circuit_lib.port_prefix(lut_input_ports[0]));
+  BasicPort lut_mux_input_port = module_manager.module_port(lut_mux_module, lut_mux_input_port_id);
+  VTR_ASSERT(lut_mux_input_port.get_width() == lut_sram_port.get_width());
+  /* Wire the port to lut_mux_sram_net */
+  for (size_t pin_id = 0; pin_id < lut_mux_input_port.pins().size(); ++pin_id) {
+    ModuleNetId net = module_manager.create_module_net(lut_module);
+    module_manager.add_module_net_source(lut_module, net, lut_module, 0, lut_sram_port_id, lut_sram_port.pins()[pin_id]);
+    module_manager.add_module_net_sink(lut_module, net, lut_mux_module, lut_mux_instance, lut_mux_input_port_id, lut_mux_input_port.pins()[pin_id]);
+  } 
+
+  for (const auto& port : lut_output_ports) {
+    ModulePortId lut_output_port_id = module_manager.find_module_port(lut_module, circuit_lib.port_prefix(port));
+    BasicPort lut_output_port = module_manager.module_port(lut_module, lut_output_port_id);
+    ModulePortId lut_mux_output_port_id = module_manager.find_module_port(lut_mux_module, circuit_lib.port_prefix(port));
+    BasicPort lut_mux_output_port = module_manager.module_port(lut_mux_module, lut_mux_output_port_id);
+    VTR_ASSERT(lut_mux_output_port.get_width() == lut_output_port.get_width());
+    /* Wire the port to lut_mux_sram_net */
+    for (size_t pin_id = 0; pin_id < lut_output_port.pins().size(); ++pin_id) {
+      ModuleNetId net = module_manager.create_module_net(lut_module);
+      module_manager.add_module_net_source(lut_module, net, lut_mux_module, lut_mux_instance, lut_mux_output_port_id, lut_mux_output_port.pins()[pin_id]);
+      module_manager.add_module_net_sink(lut_module, net, lut_module, 0, lut_output_port_id, lut_output_port.pins()[pin_id]);
+    } 
+  }
+
+  /* Add global ports to the pb_module:
+   * This is a much easier job after adding sub modules (instances), 
+   * we just need to find all the global ports from the child modules and build a list of it
+   */
+  add_module_global_ports_from_child_modules(module_manager, lut_module);
+}
+
+/******************************************************************** 
+ * Print Verilog modules for the Look-Up Tables (LUTs) 
+ * in the circuit library
+ ********************************************************************/
+void build_lut_modules(ModuleManager& module_manager,
+                       const CircuitLibrary& circuit_lib) {
+  vtr::ScopedStartFinishTimer timer("Build Look-Up Table (LUT) modules");
+
+  /* Search for each LUT circuit model */
+  for (const auto& lut_model : circuit_lib.models()) {
+    /* Bypas non-LUT modules */
+    if (CIRCUIT_MODEL_LUT != circuit_lib.model_type(lut_model)) {
+      continue;
+    }
+    build_lut_module(module_manager, circuit_lib, lut_model);
+  }
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fabric/build_lut_modules.h b/openfpga/src/fabric/build_lut_modules.h
new file mode 100644
index 000000000..5b43a742b
--- /dev/null
+++ b/openfpga/src/fabric/build_lut_modules.h
@@ -0,0 +1,22 @@
+#ifndef BUILD_LUT_MODULES_H
+#define BUILD_LUT_MODULES_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "circuit_library.h"
+#include "module_manager.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void build_lut_modules(ModuleManager& module_manager,
+                       const CircuitLibrary& circuit_lib);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
index 2a4bb1b02..829deb1a9 100644
--- a/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
@@ -156,7 +156,7 @@
       <lut_input_buffer exist="true" circuit_model_name="buf4"/>
       <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
       <pass_gate_logic circuit_model_name="TGATE"/>
-      <port type="input" prefix="in" size="6" tri_state_map="----11" circuit_model_name="OR2"/>
+      <port type="input" prefix="in" size="6" tri_state_map="-----1" circuit_model_name="OR2"/>
       <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
       <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
       <port type="sram" prefix="sram" size="64"/>

From 8e381f05815a9917ded35b172398a2f16310ec35 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 12 Feb 2020 19:57:15 -0700
Subject: [PATCH 128/645] add wire module builder

---
 openfpga/src/fabric/build_device_module.cpp |  4 +-
 openfpga/src/fabric/build_wire_modules.cpp  | 73 +++++++++++++++++++++
 openfpga/src/fabric/build_wire_modules.h    | 22 +++++++
 3 files changed, 97 insertions(+), 2 deletions(-)
 create mode 100644 openfpga/src/fabric/build_wire_modules.cpp
 create mode 100644 openfpga/src/fabric/build_wire_modules.h

diff --git a/openfpga/src/fabric/build_device_module.cpp b/openfpga/src/fabric/build_device_module.cpp
index 5e8b090f2..a7c82f351 100644
--- a/openfpga/src/fabric/build_device_module.cpp
+++ b/openfpga/src/fabric/build_device_module.cpp
@@ -12,7 +12,7 @@
 #include "build_decoder_modules.h"
 #include "build_mux_modules.h"
 #include "build_lut_modules.h"
-//#include "build_wire_modules.h"
+#include "build_wire_modules.h"
 //#include "build_memory_modules.h"
 //#include "build_grid_modules.h"
 //#include "build_routing_modules.h"
@@ -59,7 +59,7 @@ ModuleManager build_device_module_graph(const DeviceContext& vpr_device_ctx,
   build_lut_modules(module_manager, openfpga_ctx.arch().circuit_lib);
 
   /* Build wire modules */
-  //build_wire_modules(module_manager, arch.spice->circuit_lib);
+  build_wire_modules(module_manager, openfpga_ctx.arch().circuit_lib);
 
   /* Build memory modules */
   //build_memory_modules(module_manager, mux_lib, arch.spice->circuit_lib,
diff --git a/openfpga/src/fabric/build_wire_modules.cpp b/openfpga/src/fabric/build_wire_modules.cpp
new file mode 100644
index 000000000..da3b03e23
--- /dev/null
+++ b/openfpga/src/fabric/build_wire_modules.cpp
@@ -0,0 +1,73 @@
+/***********************************************
+ * This file includes functions to generate
+ * Verilog submodules for wires.
+ **********************************************/
+#include <string>
+#include <algorithm>
+
+/* Headers from vtrutil library */
+#include "vtr_log.h"
+#include "vtr_assert.h"
+#include "vtr_time.h"
+
+/* Device-level header files */
+#include "module_manager.h"
+#include "module_manager_utils.h"
+
+#include "openfpga_naming.h"
+
+#include "build_wire_modules.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Print a Verilog module of a regular wire segment
+ * Regular wire, which is 1-input and 1-output
+ * This type of wires are used in the local routing architecture
+ *              +------+
+ *    input --->| wire |---> output
+ *              +------+
+ *
+ *******************************************************************/
+static 
+void build_wire_module(ModuleManager& module_manager, 
+                       const CircuitLibrary& circuit_lib,
+                       const CircuitModelId& wire_model) {
+  /* Find the input port, output port*/
+  std::vector<CircuitPortId> input_ports = circuit_lib.model_ports_by_type(wire_model, CIRCUIT_MODEL_PORT_INPUT, true);
+  std::vector<CircuitPortId> output_ports = circuit_lib.model_ports_by_type(wire_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
+  std::vector<CircuitPortId> global_ports = circuit_lib.model_global_ports_by_type(wire_model, CIRCUIT_MODEL_PORT_INPUT, true, true);
+
+  /* Makre sure the port size is what we want */
+  VTR_ASSERT (1 == input_ports.size());
+  VTR_ASSERT (1 == output_ports.size());
+  VTR_ASSERT (1 == circuit_lib.port_size(input_ports[0]));
+  VTR_ASSERT (1 == circuit_lib.port_size(output_ports[0]));
+
+  /* Create a Verilog Module based on the circuit model, and add to module manager */
+  add_circuit_model_to_module_manager(module_manager, circuit_lib, wire_model); 
+}
+
+/********************************************************************
+ * This function will only create wire modules with a number of 
+ * ports that are defined by users.
+ * It will NOT insert any internal logic, which should be handled 
+ * by Verilog/SPICE writers
+ *******************************************************************/
+void build_wire_modules(ModuleManager& module_manager,
+                        const CircuitLibrary& circuit_lib) {
+  vtr::ScopedStartFinishTimer timer("Build wire modules");
+
+  /* Print Verilog models for regular wires*/
+  for (const auto& wire_model : circuit_lib.models_by_type(CIRCUIT_MODEL_WIRE)) { 
+    /* Bypass user-defined circuit models */
+    if ( (!circuit_lib.model_circuit_netlist(wire_model).empty()) 
+      && (!circuit_lib.model_verilog_netlist(wire_model).empty()) ) {
+      continue;
+    }
+    build_wire_module(module_manager, circuit_lib, wire_model);
+  }
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fabric/build_wire_modules.h b/openfpga/src/fabric/build_wire_modules.h
new file mode 100644
index 000000000..845f5f532
--- /dev/null
+++ b/openfpga/src/fabric/build_wire_modules.h
@@ -0,0 +1,22 @@
+#ifndef BUILD_WIRE_MODULES_H
+#define BUILD_WIRE_MODULES_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "circuit_library.h"
+#include "module_manager.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void build_wire_modules(ModuleManager& module_manager,
+                        const CircuitLibrary& circuit_lib);
+
+} /* end namespace openfpga */
+
+#endif

From 002c2795fe505f2fb25d1f4c8d96fdd163b0d556 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 12 Feb 2020 20:06:38 -0700
Subject: [PATCH 129/645] add memory module builder

---
 openfpga/src/fabric/build_device_module.cpp  |   7 +-
 openfpga/src/fabric/build_memory_modules.cpp | 715 +++++++++++++++++++
 openfpga/src/fabric/build_memory_modules.h   |  25 +
 3 files changed, 744 insertions(+), 3 deletions(-)
 create mode 100644 openfpga/src/fabric/build_memory_modules.cpp
 create mode 100644 openfpga/src/fabric/build_memory_modules.h

diff --git a/openfpga/src/fabric/build_device_module.cpp b/openfpga/src/fabric/build_device_module.cpp
index a7c82f351..40d856022 100644
--- a/openfpga/src/fabric/build_device_module.cpp
+++ b/openfpga/src/fabric/build_device_module.cpp
@@ -13,7 +13,7 @@
 #include "build_mux_modules.h"
 #include "build_lut_modules.h"
 #include "build_wire_modules.h"
-//#include "build_memory_modules.h"
+#include "build_memory_modules.h"
 //#include "build_grid_modules.h"
 //#include "build_routing_modules.h"
 //#include "build_top_module.h"
@@ -62,8 +62,9 @@ ModuleManager build_device_module_graph(const DeviceContext& vpr_device_ctx,
   build_wire_modules(module_manager, openfpga_ctx.arch().circuit_lib);
 
   /* Build memory modules */
-  //build_memory_modules(module_manager, mux_lib, arch.spice->circuit_lib,
-  //                     arch.sram_inf.verilog_sram_inf_orgz->type);
+  build_memory_modules(module_manager, openfpga_ctx.mux_lib(), 
+                       openfpga_ctx.arch().circuit_lib,
+                       openfpga_ctx.arch().config_protocol.type());
 
   /* Build grid and programmable block modules */
   //build_grid_modules(module_manager, arch.spice->circuit_lib, mux_lib,  
diff --git a/openfpga/src/fabric/build_memory_modules.cpp b/openfpga/src/fabric/build_memory_modules.cpp
new file mode 100644
index 000000000..26b463377
--- /dev/null
+++ b/openfpga/src/fabric/build_memory_modules.cpp
@@ -0,0 +1,715 @@
+/*********************************************************************
+ * This file includes functions to generate Verilog submodules for 
+ * the memories that are affiliated to multiplexers and other programmable
+ * circuit models, such as IOPADs, LUTs, etc.
+ ********************************************************************/
+#include <ctime>
+#include <string>
+#include <algorithm>
+
+/* Headers from vtrutil library */
+#include "vtr_log.h"
+#include "vtr_time.h"
+#include "vtr_assert.h"
+
+#include "mux_graph.h"
+#include "module_manager.h"
+#include "circuit_library_utils.h"
+#include "module_manager_utils.h"
+#include "mux_utils.h"
+
+#include "openfpga_reserved_words.h"
+#include "openfpga_naming.h"
+
+#include "build_memory_modules.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/*********************************************************************
+ * Add module nets to connect an input port of a memory module to 
+ * an input port of its child module
+ * Restriction: this function is really designed for memory modules
+ * 1. It assumes that input port name of child module is the same as memory module
+ * 2. It assumes exact pin-to-pin mapping: 
+ *     j-th pin of input port of the i-th child module is wired to the j + i*W -th
+ *     pin of input port of the memory module, where W is the size of port 
+ ********************************************************************/
+static 
+void add_module_input_nets_to_mem_modules(ModuleManager& module_manager,
+                                          const ModuleId& mem_module,
+                                          const CircuitLibrary& circuit_lib,
+                                          const std::vector<CircuitPortId>& circuit_ports,
+                                          const ModuleId& child_module,
+                                          const size_t& child_index,
+                                          const size_t& child_instance) {
+  /* Wire inputs of parent module to inputs of child modules */
+  for (const auto& port : circuit_ports) {
+    ModulePortId src_port_id = module_manager.find_module_port(mem_module, circuit_lib.port_prefix(port));
+    ModulePortId sink_port_id = module_manager.find_module_port(child_module, circuit_lib.port_prefix(port));
+    for (size_t pin_id = 0; pin_id < module_manager.module_port(mem_module, sink_port_id).pins().size(); ++pin_id) {
+      ModuleNetId net = module_manager.create_module_net(mem_module);
+      /* Source pin is shifted by the number of memories */
+      size_t src_pin_id = child_index * circuit_lib.port_size(port) + module_manager.module_port(mem_module, src_port_id).pins()[pin_id];
+      /* Source node of the input net is the input of memory module */
+      module_manager.add_module_net_source(mem_module, net, mem_module, 0, src_port_id, src_pin_id);
+      /* Sink node of the input net is the input of sram module */
+      size_t sink_pin_id = module_manager.module_port(child_module, sink_port_id).pins()[pin_id];
+      module_manager.add_module_net_sink(mem_module, net, child_module, child_instance, sink_port_id, sink_pin_id);
+    }
+  }
+}
+
+/*********************************************************************
+ * Add module nets to connect an output port of a memory module to 
+ * an output port of its child module
+ * Restriction: this function is really designed for memory modules
+ * 1. It assumes that output port name of child module is the same as memory module
+ * 2. It assumes exact pin-to-pin mapping: 
+ *     j-th pin of output port of the i-th child module is wired to the j + i*W -th
+ *     pin of output port of the memory module, where W is the size of port 
+ ********************************************************************/
+static 
+void add_module_output_nets_to_mem_modules(ModuleManager& module_manager,
+                                           const ModuleId& mem_module,
+                                           const CircuitLibrary& circuit_lib,
+                                           const std::vector<CircuitPortId>& circuit_ports,
+                                           const ModuleId& child_module,
+                                           const size_t& child_index,
+                                           const size_t& child_instance) {
+  /* Wire inputs of parent module to inputs of child modules */
+  for (const auto& port : circuit_ports) {
+    ModulePortId src_port_id = module_manager.find_module_port(child_module, circuit_lib.port_prefix(port));
+    ModulePortId sink_port_id = module_manager.find_module_port(mem_module, circuit_lib.port_prefix(port));
+    for (size_t pin_id = 0; pin_id < module_manager.module_port(child_module, src_port_id).pins().size(); ++pin_id) {
+      ModuleNetId net = module_manager.create_module_net(mem_module);
+      /* Source pin is shifted by the number of memories */
+      size_t src_pin_id = module_manager.module_port(child_module, src_port_id).pins()[pin_id];
+      /* Source node of the input net is the input of memory module */
+      module_manager.add_module_net_source(mem_module, net, child_module, child_instance, src_port_id, src_pin_id);
+      /* Sink node of the input net is the input of sram module */
+      size_t sink_pin_id = child_index * circuit_lib.port_size(port) + module_manager.module_port(mem_module, sink_port_id).pins()[pin_id];
+      module_manager.add_module_net_sink(mem_module, net, mem_module, 0, sink_port_id, sink_pin_id);
+    }
+  }
+}
+
+/*********************************************************************
+ * Add module nets to connect an output port of a configuration-chain
+ * memory module to an output port of its child module
+ * Restriction: this function is really designed for memory modules
+ * 1. It assumes that output port name of child module is the same as memory module
+ * 2. It assumes exact pin-to-pin mapping: 
+ *     j-th pin of output port of the i-th child module is wired to the j + i*W -th
+ *     pin of output port of the memory module, where W is the size of port 
+ * 3. It assumes fixed port name for output ports
+ * 
+ * We cache the module nets that have been created because they will be used later
+ ********************************************************************/
+static 
+std::vector<ModuleNetId> add_module_output_nets_to_chain_mem_modules(ModuleManager& module_manager,
+                                                                     const ModuleId& mem_module,
+                                                                     const std::string& mem_module_output_name,
+                                                                     const CircuitLibrary& circuit_lib,
+                                                                     const CircuitPortId& circuit_port,
+                                                                     const ModuleId& child_module,
+                                                                     const size_t& child_index,
+                                                                     const size_t& child_instance) {
+  std::vector<ModuleNetId> module_nets;
+
+  /* Wire inputs of parent module to inputs of child modules */
+  ModulePortId src_port_id = module_manager.find_module_port(child_module, circuit_lib.port_prefix(circuit_port));
+  ModulePortId sink_port_id = module_manager.find_module_port(mem_module, mem_module_output_name);
+  for (size_t pin_id = 0; pin_id < module_manager.module_port(child_module, src_port_id).pins().size(); ++pin_id) {
+    ModuleNetId net = module_manager.create_module_net(mem_module);
+    /* Source pin is shifted by the number of memories */
+    size_t src_pin_id = module_manager.module_port(child_module, src_port_id).pins()[pin_id];
+    /* Source node of the input net is the input of memory module */
+    module_manager.add_module_net_source(mem_module, net, child_module, child_instance, src_port_id, src_pin_id);
+    /* Sink node of the input net is the input of sram module */
+    size_t sink_pin_id = child_index * circuit_lib.port_size(circuit_port) + module_manager.module_port(mem_module, sink_port_id).pins()[pin_id];
+    module_manager.add_module_net_sink(mem_module, net, mem_module, 0, sink_port_id, sink_pin_id);
+
+    /* Cache the nets */
+    module_nets.push_back(net);
+  }
+
+  return module_nets;
+}
+
+/********************************************************************
+ * Connect all the memory modules under the parent module in a chain
+ * 
+ *                +--------+    +--------+            +--------+
+ *  ccff_head --->| Memory |--->| Memory |--->... --->| Memory |----> ccff_tail
+ *                | Module |    | Module |            | Module |
+ *                |   [0]  |    |   [1]  |            |  [N-1] |             
+ *                +--------+    +--------+            +--------+
+ *  For the 1st memory module:
+ *    net source is the configuration chain head of the primitive module
+ *    net sink is the configuration chain head of the next memory module
+ *
+ *  For the rest of memory modules:
+ *    net source is the configuration chain tail of the previous memory module
+ *    net sink is the configuration chain head of the next memory module
+ *
+ *  Note that:
+ *    This function is designed for memory modules ONLY!
+ *    Do not use it to replace the 
+ *      add_module_nets_cmos_memory_chain_config_bus() !!!
+ *********************************************************************/
+static 
+void add_module_nets_to_cmos_memory_chain_module(ModuleManager& module_manager,
+                                                 const ModuleId& parent_module,
+                                                 const std::vector<ModuleNetId>& output_nets,
+                                                 const CircuitLibrary& circuit_lib,
+                                                 const CircuitPortId& model_input_port,
+                                                 const CircuitPortId& model_output_port) {
+  /* Counter for the nets */
+  size_t net_counter = 0;
+
+  for (size_t mem_index = 0; mem_index < module_manager.configurable_children(parent_module).size(); ++mem_index) {
+    ModuleId net_src_module_id;
+    size_t net_src_instance_id;
+    ModulePortId net_src_port_id;
+
+    ModuleId net_sink_module_id;
+    size_t net_sink_instance_id;
+    ModulePortId net_sink_port_id;
+
+    if (0 == mem_index) {
+      /* Find the port name of configuration chain head */
+      std::string src_port_name = generate_configuration_chain_head_name();
+      net_src_module_id = parent_module; 
+      net_src_instance_id = 0;
+      net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name); 
+
+      /* Find the port name of next memory module */
+      std::string sink_port_name = circuit_lib.port_prefix(model_input_port);
+      net_sink_module_id = module_manager.configurable_children(parent_module)[mem_index]; 
+      net_sink_instance_id = module_manager.configurable_child_instances(parent_module)[mem_index];
+      net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name); 
+    } else {
+      /* Find the port name of previous memory module */
+      std::string src_port_name = circuit_lib.port_prefix(model_output_port);
+      net_src_module_id = module_manager.configurable_children(parent_module)[mem_index - 1]; 
+      net_src_instance_id = module_manager.configurable_child_instances(parent_module)[mem_index - 1];
+      net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name); 
+
+      /* Find the port name of next memory module */
+      std::string sink_port_name = circuit_lib.port_prefix(model_input_port);
+      net_sink_module_id = module_manager.configurable_children(parent_module)[mem_index]; 
+      net_sink_instance_id = module_manager.configurable_child_instances(parent_module)[mem_index];
+      net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name); 
+    }
+
+    /* Get the pin id for source port */
+    BasicPort net_src_port = module_manager.module_port(net_src_module_id, net_src_port_id); 
+    /* Get the pin id for sink port */
+    BasicPort net_sink_port = module_manager.module_port(net_sink_module_id, net_sink_port_id); 
+    /* Port sizes of source and sink should match */
+    VTR_ASSERT(net_src_port.get_width() == net_sink_port.get_width());
+    
+    /* Create a net for each pin */
+    for (size_t pin_id = 0; pin_id < net_src_port.pins().size(); ++pin_id) {
+      /* Create a net and add source and sink to it */
+      ModuleNetId net;
+      if (0 == mem_index) {
+        net = module_manager.create_module_net(parent_module);
+      } else {
+        net = output_nets[net_counter];
+      }
+      /* Add net source */
+      module_manager.add_module_net_source(parent_module, net, net_src_module_id, net_src_instance_id, net_src_port_id, net_src_port.pins()[pin_id]);
+      /* Add net sink */
+      module_manager.add_module_net_sink(parent_module, net, net_sink_module_id, net_sink_instance_id, net_sink_port_id, net_sink_port.pins()[pin_id]);
+
+      /* Update net counter */
+      if (0 < mem_index) {
+        net_counter++;
+      }
+    }
+  }
+
+  /* For the last memory module:
+   *    net source is the configuration chain tail of the previous memory module
+   *    net sink is the configuration chain tail of the primitive module
+   */
+  /* Find the port name of previous memory module */
+  std::string src_port_name = circuit_lib.port_prefix(model_output_port);
+  ModuleId net_src_module_id = module_manager.configurable_children(parent_module).back(); 
+  size_t net_src_instance_id = module_manager.configurable_child_instances(parent_module).back();
+  ModulePortId net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name); 
+
+  /* Find the port name of next memory module */
+  std::string sink_port_name = generate_configuration_chain_tail_name();
+  ModuleId net_sink_module_id = parent_module; 
+  size_t net_sink_instance_id = 0;
+  ModulePortId net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name); 
+
+  /* Get the pin id for source port */
+  BasicPort net_src_port = module_manager.module_port(net_src_module_id, net_src_port_id); 
+  /* Get the pin id for sink port */
+  BasicPort net_sink_port = module_manager.module_port(net_sink_module_id, net_sink_port_id); 
+  /* Port sizes of source and sink should match */
+  VTR_ASSERT(net_src_port.get_width() == net_sink_port.get_width());
+  
+  /* Create a net for each pin */
+  for (size_t pin_id = 0; pin_id < net_src_port.pins().size(); ++pin_id) {
+    /* Create a net and add source and sink to it */
+    ModuleNetId net = output_nets[net_counter];
+    /* Add net source */
+    module_manager.add_module_net_source(parent_module, net, net_src_module_id, net_src_instance_id, net_src_port_id, net_src_port.pins()[pin_id]);
+    /* Add net sink */
+    module_manager.add_module_net_sink(parent_module, net, net_sink_module_id, net_sink_instance_id, net_sink_port_id, net_sink_port.pins()[pin_id]);
+
+    /* Update net counter */
+    net_counter++;
+  }
+
+  VTR_ASSERT(net_counter == output_nets.size());
+}
+
+/*********************************************************************
+ * Flat memory modules 
+ *
+ *        in[0]        in[1]           in[N]
+ *          |            |               |
+ *          v            v               v
+ *      +-------+    +-------+       +-------+
+ *      | SRAM  |    | SRAM  |  ...  | SRAM  |
+ *      |  [0]  |    |  [1]  |       | [N-1] |
+ *      +-------+    +-------+       +-------+
+ *          |            |      ...      |
+ *          v            v               v
+ *      +------------------------------------+
+ *      |   Multiplexer Configuration port   |
+ *
+ ********************************************************************/
+static 
+void build_memory_standalone_module(ModuleManager& module_manager,
+                                    const CircuitLibrary& circuit_lib,
+                                    const std::string& module_name,
+                                    const CircuitModelId& sram_model,
+                                    const size_t& num_mems) {
+  /* Get the global ports required by the SRAM */
+  std::vector<enum e_circuit_model_port_type> global_port_types;
+  global_port_types.push_back(CIRCUIT_MODEL_PORT_CLOCK);
+  global_port_types.push_back(CIRCUIT_MODEL_PORT_INPUT);
+  std::vector<CircuitPortId> sram_global_ports = circuit_lib.model_global_ports_by_type(sram_model, global_port_types, true, false);
+  /* Get the input ports from the SRAM */
+  std::vector<CircuitPortId> sram_input_ports = circuit_lib.model_ports_by_type(sram_model, CIRCUIT_MODEL_PORT_INPUT, true);
+  /* Get the output ports from the SRAM */
+  std::vector<CircuitPortId> sram_output_ports = circuit_lib.model_ports_by_type(sram_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
+
+  /* Create a module and add to the module manager */
+  ModuleId mem_module = module_manager.add_module(module_name); 
+  VTR_ASSERT(true == module_manager.valid_module_id(mem_module));
+  
+  /* Add each input port */
+  for (const auto& port : sram_input_ports) {
+    BasicPort input_port(circuit_lib.port_prefix(port), num_mems);
+    module_manager.add_port(mem_module, input_port, ModuleManager::MODULE_INPUT_PORT);
+  }
+  /* Add each output port: port width should match the number of memories */
+  for (const auto& port : sram_output_ports) {
+    BasicPort output_port(circuit_lib.port_prefix(port), num_mems);
+    module_manager.add_port(mem_module, output_port, ModuleManager::MODULE_OUTPUT_PORT);
+  }
+
+  /* Find the sram module in the module manager */
+  ModuleId sram_mem_module = module_manager.find_module(circuit_lib.model_name(sram_model));
+
+  /* Instanciate each submodule */
+  for (size_t i = 0; i < num_mems; ++i) {
+    size_t sram_mem_instance = module_manager.num_instance(mem_module, sram_mem_module);
+    module_manager.add_child_module(mem_module, sram_mem_module);
+    module_manager.add_configurable_child(mem_module, sram_mem_module, sram_mem_instance);
+
+    /* Build module nets */
+    /* Wire inputs of parent module to inputs of child modules */
+    add_module_input_nets_to_mem_modules(module_manager, mem_module, circuit_lib, sram_input_ports, sram_mem_module, i, sram_mem_instance);
+    /* Wire inputs of parent module to outputs of child modules */
+    add_module_output_nets_to_mem_modules(module_manager, mem_module, circuit_lib, sram_output_ports, sram_mem_module, i, sram_mem_instance);
+  }
+
+  /* Add global ports to the pb_module:
+   * This is a much easier job after adding sub modules (instances), 
+   * we just need to find all the global ports from the child modules and build a list of it
+   */
+  add_module_global_ports_from_child_modules(module_manager, mem_module);
+}
+
+/*********************************************************************
+ * Scan-chain organization
+ *              
+ *                +-------+    +-------+            +-------+
+ *  scan-chain--->| CCFF  |--->| CCFF  |--->... --->| CCFF  |---->scan-chain
+ *  input&clock   |  [0]  |    |  [1]  |            | [N-1] |       output
+ *                +-------+    +-------+            +-------+
+ *                    |            |      ...           |
+ *                    v            v                    v
+ *                +-----------------------------------------+
+ *                |   Multiplexer Configuration port        |
+ *
+ ********************************************************************/
+static 
+void build_memory_chain_module(ModuleManager& module_manager,
+                               const CircuitLibrary& circuit_lib,
+                               const std::string& module_name,
+                               const CircuitModelId& sram_model,
+                               const size_t& num_mems) {
+
+  /* Get the input ports from the SRAM */
+  std::vector<CircuitPortId> sram_input_ports = circuit_lib.model_ports_by_type(sram_model, CIRCUIT_MODEL_PORT_INPUT, true);
+  /* Should have only 1 input port */
+  VTR_ASSERT( 1 == sram_input_ports.size() );
+  /* Get the output ports from the SRAM */
+  std::vector<CircuitPortId> sram_output_ports = circuit_lib.model_ports_by_type(sram_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
+  /* Should have only 1 or 2 output port */
+  VTR_ASSERT( (1 == sram_output_ports.size()) || ( 2 == sram_output_ports.size()) );
+
+  /* Create a module and add to the module manager */
+  ModuleId mem_module = module_manager.add_module(module_name); 
+  VTR_ASSERT(true == module_manager.valid_module_id(mem_module));
+  
+  /* Add an input port, which is the head of configuration chain in the module */
+  /* TODO: restriction!!!
+   * consider only the first input of the CCFF model as the D port,
+   * which will be connected to the head of the chain
+   */
+  BasicPort chain_head_port(generate_configuration_chain_head_name(), 
+                            circuit_lib.port_size(sram_input_ports[0]));
+  module_manager.add_port(mem_module, chain_head_port, ModuleManager::MODULE_INPUT_PORT);
+  /* Add an output port, which is the tail of configuration chain in the module */
+  /* TODO: restriction!!!
+   * consider only the first output of the CCFF model as the Q port,
+   * which will be connected to the tail of the chain
+   */
+  BasicPort chain_tail_port(generate_configuration_chain_tail_name(), 
+                            circuit_lib.port_size(sram_output_ports[0]));
+  module_manager.add_port(mem_module, chain_tail_port, ModuleManager::MODULE_OUTPUT_PORT);
+
+  /* Add each output port: port width should match the number of memories */
+  for (size_t iport = 0; iport < sram_output_ports.size(); ++iport) {
+    std::string port_name;
+    if (0 == iport) {
+      port_name = generate_configuration_chain_data_out_name();
+    } else {
+      VTR_ASSERT( 1 == iport);
+      port_name = generate_configuration_chain_inverted_data_out_name();
+    }
+    BasicPort output_port(port_name, num_mems);
+    module_manager.add_port(mem_module, output_port, ModuleManager::MODULE_OUTPUT_PORT);
+  }
+
+  /* Find the sram module in the module manager */
+  ModuleId sram_mem_module = module_manager.find_module(circuit_lib.model_name(sram_model));
+
+  /* Cache the output nets for non-inverted data output */
+  std::vector<ModuleNetId> mem_output_nets; 
+
+  /* Instanciate each submodule */
+  for (size_t i = 0; i < num_mems; ++i) {
+    size_t sram_mem_instance = module_manager.num_instance(mem_module, sram_mem_module);
+    module_manager.add_child_module(mem_module, sram_mem_module);
+    module_manager.add_configurable_child(mem_module, sram_mem_module, sram_mem_instance);
+
+    /* Build module nets to wire outputs of sram modules to outputs of memory module */
+    for (size_t iport = 0; iport < sram_output_ports.size(); ++iport) {
+      std::string port_name;
+      if (0 == iport) {
+        port_name = generate_configuration_chain_data_out_name();
+      } else {
+        VTR_ASSERT( 1 == iport);
+        port_name = generate_configuration_chain_inverted_data_out_name();
+      }
+      std::vector<ModuleNetId> output_nets = add_module_output_nets_to_chain_mem_modules(module_manager, mem_module, 
+                                                                                         port_name, circuit_lib, sram_output_ports[iport],
+                                                                                         sram_mem_module, i, sram_mem_instance);
+      /* Cache only for regular data outputs */
+      if (0 == iport) { 
+        mem_output_nets.insert(mem_output_nets.end(), output_nets.begin(), output_nets.end());
+      } 
+    }
+  }
+
+  /* Build module nets to wire the configuration chain */
+  add_module_nets_to_cmos_memory_chain_module(module_manager, mem_module, mem_output_nets, 
+                                              circuit_lib, sram_input_ports[0], sram_output_ports[0]);
+
+
+  /* Add global ports to the pb_module:
+   * This is a much easier job after adding sub modules (instances), 
+   * we just need to find all the global ports from the child modules and build a list of it
+   */
+  add_module_global_ports_from_child_modules(module_manager, mem_module);
+}
+
+/*********************************************************************
+ * Memory bank organization
+ *
+ *           Bit lines(BL/BLB) Word lines (WL/WLB)
+ *               |               |
+ *               v               v
+ *      +------------------------------------+
+ *      |   Memory Module Configuration port |
+ *      +------------------------------------+
+ *          |            |               |
+ *          v            v               v
+ *      +-------+    +-------+       +-------+
+ *      | SRAM  |    | SRAM  |  ...  | SRAM  |
+ *      |  [0]  |    |  [1]  |       | [N-1] |
+ *      +-------+    +-------+       +-------+
+ *          |            |      ...      |
+ *          v            v               v
+ *      +------------------------------------+
+ *      |   Multiplexer Configuration port   |
+ *
+ ********************************************************************/
+static 
+void build_memory_bank_module(ModuleManager& module_manager,
+                              const CircuitLibrary& circuit_lib,
+                              const std::string& module_name,
+                              const CircuitModelId& sram_model,
+                              const size_t& num_mems) {
+  /* Get the global ports required by the SRAM */
+  std::vector<enum e_circuit_model_port_type> global_port_types;
+  global_port_types.push_back(CIRCUIT_MODEL_PORT_CLOCK);
+  global_port_types.push_back(CIRCUIT_MODEL_PORT_INPUT);
+  std::vector<CircuitPortId> sram_global_ports = circuit_lib.model_global_ports_by_type(sram_model, global_port_types, true, false);
+  /* Get the input ports from the SRAM */
+  std::vector<CircuitPortId> sram_input_ports = circuit_lib.model_ports_by_type(sram_model, CIRCUIT_MODEL_PORT_INPUT, true);
+  /* A SRAM cell with BL/WL should not have any input */
+  VTR_ASSERT( 0 == sram_input_ports.size() );
+  /* Get the output ports from the SRAM */
+  std::vector<CircuitPortId> sram_output_ports = circuit_lib.model_ports_by_type(sram_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
+  /* Get the BL/WL ports from the SRAM */
+  std::vector<CircuitPortId> sram_bl_ports  = circuit_lib.model_ports_by_type(sram_model, CIRCUIT_MODEL_PORT_BL, true);
+  std::vector<CircuitPortId> sram_blb_ports = circuit_lib.model_ports_by_type(sram_model, CIRCUIT_MODEL_PORT_BLB, true);
+  std::vector<CircuitPortId> sram_wl_ports  = circuit_lib.model_ports_by_type(sram_model, CIRCUIT_MODEL_PORT_WL, true);
+  std::vector<CircuitPortId> sram_wlb_ports = circuit_lib.model_ports_by_type(sram_model, CIRCUIT_MODEL_PORT_WLB, true);
+
+  /* Create a module and add to the module manager */
+  ModuleId mem_module = module_manager.add_module(module_name); 
+  VTR_ASSERT(true == module_manager.valid_module_id(mem_module));
+  
+  /* Add module ports: the ports come from the SRAM modules */
+  /* Add each input port */
+  for (const auto& port : sram_input_ports) {
+    BasicPort input_port(circuit_lib.port_prefix(port), num_mems * circuit_lib.port_size(port));
+    module_manager.add_port(mem_module, input_port, ModuleManager::MODULE_INPUT_PORT);
+  }
+  /* Add each output port: port width should match the number of memories */
+  for (const auto& port : sram_output_ports) {
+    BasicPort output_port(circuit_lib.port_prefix(port), num_mems * circuit_lib.port_size(port));
+    module_manager.add_port(mem_module, output_port, ModuleManager::MODULE_OUTPUT_PORT);
+  }
+  /* Add each output port: port width should match the number of memories */
+  for (const auto& port : sram_bl_ports) {
+    BasicPort bl_port(circuit_lib.port_prefix(port), num_mems * circuit_lib.port_size(port));
+    module_manager.add_port(mem_module, bl_port, ModuleManager::MODULE_INPUT_PORT);
+  }
+  for (const auto& port : sram_blb_ports) {
+    BasicPort blb_port(circuit_lib.port_prefix(port), num_mems * circuit_lib.port_size(port));
+    module_manager.add_port(mem_module, blb_port, ModuleManager::MODULE_INPUT_PORT);
+  }
+  for (const auto& port : sram_wl_ports) {
+    BasicPort wl_port(circuit_lib.port_prefix(port), num_mems * circuit_lib.port_size(port));
+    module_manager.add_port(mem_module, wl_port, ModuleManager::MODULE_INPUT_PORT);
+  }
+  for (const auto& port : sram_wlb_ports) {
+    BasicPort wlb_port(circuit_lib.port_prefix(port), num_mems * circuit_lib.port_size(port));
+    module_manager.add_port(mem_module, wlb_port, ModuleManager::MODULE_INPUT_PORT);
+  }
+
+  /* Find the sram module in the module manager */
+  ModuleId sram_mem_module = module_manager.find_module(circuit_lib.model_name(sram_model));
+
+  /* Instanciate each submodule */
+  for (size_t i = 0; i < num_mems; ++i) {
+    /* Memory seed module instanciation */
+    size_t sram_instance = module_manager.num_instance(mem_module, sram_mem_module);
+    module_manager.add_child_module(mem_module, sram_mem_module);
+
+    /* Build module nets */
+    /* Wire inputs of parent module to inputs of child modules */
+    add_module_input_nets_to_mem_modules(module_manager, mem_module, circuit_lib, sram_input_ports, sram_mem_module, i, sram_instance);
+    /* Wire inputs of parent module to outputs of child modules */
+    add_module_output_nets_to_mem_modules(module_manager, mem_module, circuit_lib, sram_output_ports, sram_mem_module, i, sram_instance);
+    /* Wire BL/WLs of parent module to BL/WLs of child modules */
+    add_module_input_nets_to_mem_modules(module_manager, mem_module, circuit_lib, sram_bl_ports, sram_mem_module, i, sram_instance);
+    add_module_input_nets_to_mem_modules(module_manager, mem_module, circuit_lib, sram_blb_ports, sram_mem_module, i, sram_instance);
+    add_module_input_nets_to_mem_modules(module_manager, mem_module, circuit_lib, sram_wl_ports, sram_mem_module, i, sram_instance);
+    add_module_input_nets_to_mem_modules(module_manager, mem_module, circuit_lib, sram_wlb_ports, sram_mem_module, i, sram_instance);
+  }
+
+  /* TODO: if a local memory decoder is required, instanciate it here */
+
+  /* Add global ports to the pb_module:
+   * This is a much easier job after adding sub modules (instances), 
+   * we just need to find all the global ports from the child modules and build a list of it
+   */
+  add_module_global_ports_from_child_modules(module_manager, mem_module);
+}
+
+
+/*********************************************************************
+ * Generate Verilog modules for the memories that are used
+ * by a circuit model 
+ * The organization of memory circuit will depend on the style of
+ * configuration protocols
+ * Currently, we support 
+ * 1. Flat SRAM organization
+ * 2. Configuration chain
+ * 3. Memory bank (memory decoders)
+ ********************************************************************/
+static 
+void build_memory_module(ModuleManager& module_manager,
+                         const CircuitLibrary& circuit_lib,
+                         const e_config_protocol_type& sram_orgz_type,
+                         const std::string& module_name,
+                         const CircuitModelId& sram_model,
+                         const size_t& num_mems) {
+  switch (sram_orgz_type) {
+  case CONFIG_MEM_STANDALONE:
+    build_memory_standalone_module(module_manager, circuit_lib, 
+                                           module_name, sram_model, num_mems);
+    break;
+  case CONFIG_MEM_SCAN_CHAIN:
+    build_memory_chain_module(module_manager, circuit_lib,  
+                              module_name, sram_model, num_mems);
+    break;
+  case CONFIG_MEM_MEMORY_BANK:
+    build_memory_bank_module(module_manager, circuit_lib,
+                             module_name, sram_model, num_mems);
+    break;
+  default:
+    VTR_LOG_ERROR("Invalid SRAM organization!\n");
+    exit(1);
+  }
+}
+
+
+/*********************************************************************
+ * Generate Verilog modules for the memories that are used
+ * by multiplexers  
+ *
+ *            +----------------+
+ * mem_in --->|  Memory Module |---> mem_out
+ *            +----------------+
+ *              |  |  ... |  | 
+ *              v  v      v  v SRAM ports of multiplexer
+ *          +---------------------+
+ *    in--->|  Multiplexer Module |---> out
+ *          +---------------------+
+ ********************************************************************/
+static 
+void build_mux_memory_module(ModuleManager& module_manager,
+                             const CircuitLibrary& circuit_lib,
+                             const e_config_protocol_type& sram_orgz_type,
+                             const CircuitModelId& mux_model,
+                             const MuxGraph& mux_graph) {
+  /* Find the actual number of configuration bits, based on the mux graph 
+   * Due to the use of local decoders inside mux, this may be 
+   */
+  size_t num_config_bits = find_mux_num_config_bits(circuit_lib, mux_model, mux_graph, sram_orgz_type);
+  /* Multiplexers built with different technology is in different organization */
+  switch (circuit_lib.design_tech_type(mux_model)) {
+  case CIRCUIT_MODEL_DESIGN_CMOS: {
+    /* Generate module name */
+    std::string module_name = generate_mux_subckt_name(circuit_lib, mux_model, 
+                                                       find_mux_num_datapath_inputs(circuit_lib, mux_model, mux_graph.num_inputs()), 
+                                                       std::string(MEMORY_MODULE_POSTFIX));
+
+    /* Get the sram ports from the mux */
+    std::vector<CircuitModelId> sram_models = find_circuit_sram_models(circuit_lib, mux_model);
+    VTR_ASSERT( 1 == sram_models.size() );
+
+    build_memory_module(module_manager, circuit_lib, sram_orgz_type, module_name, sram_models[0], num_config_bits);
+    break;
+  }
+  case CIRCUIT_MODEL_DESIGN_RRAM:
+    /* We do not need a memory submodule for RRAM MUX,
+     * RRAM are embedded in the datapath  
+     * TODO: generate local encoders for RRAM-based multiplexers here!!!
+     */ 
+    break;
+  default:
+    VTR_LOG_ERROR("Invalid design technology of multiplexer '%s'\n",
+                  circuit_lib.model_name(mux_model).c_str()); 
+    exit(1);
+  }
+}
+
+/*********************************************************************
+ * Build modules for 
+ * the memories that are affiliated to multiplexers and other programmable
+ * circuit models, such as IOPADs, LUTs, etc.
+ *
+ * We keep the memory modules separated from the multiplexers and other 
+ * programmable circuit models, for the sake of supporting
+ * various configuration schemes.
+ * By following such organiztion, the Verilog modules of the circuit models
+ * implements the functionality (circuit logic) only, while the memory Verilog
+ * modules implements the memory circuits as well as configuration protocols.
+ * For example, the local decoders of multiplexers are implemented in the
+ * memory modules. 
+ * Take another example, the memory circuit can implement the scan-chain or 
+ * memory-bank organization for the memories.
+ ********************************************************************/
+void build_memory_modules(ModuleManager& module_manager,
+                          const MuxLibrary& mux_lib,
+                          const CircuitLibrary& circuit_lib,
+                          const e_config_protocol_type& sram_orgz_type) {
+  vtr::ScopedStartFinishTimer timer("Build memory modules");
+  
+  /* Create the memory circuits for the multiplexer */
+  for (auto mux : mux_lib.muxes()) {
+    const MuxGraph& mux_graph = mux_lib.mux_graph(mux);
+    CircuitModelId mux_model = mux_lib.mux_circuit_model(mux); 
+    /* Bypass the non-MUX circuit models (i.e., LUTs). 
+     * They should be handled in a different way 
+     * Memory circuits of LUT includes both regular and mode-select ports
+     */
+    if (CIRCUIT_MODEL_MUX != circuit_lib.model_type(mux_model)) {
+      continue;
+    }
+    /* Create a Verilog module for the memories used by the multiplexer */
+    build_mux_memory_module(module_manager, circuit_lib, sram_orgz_type, mux_model, mux_graph);
+  }
+
+  /* Create the memory circuits for non-MUX circuit models.
+   * In this case, the memory modules are designed to interface
+   * the mode-select ports 
+   */
+  for (const auto& model : circuit_lib.models()) {
+    /* Bypass MUXes, they have already been considered */
+    if (CIRCUIT_MODEL_MUX == circuit_lib.model_type(model)) {
+      continue;
+    }
+    /* Bypass those modules without any SRAM ports */
+    std::vector<CircuitPortId> sram_ports = circuit_lib.model_ports_by_type(model, CIRCUIT_MODEL_PORT_SRAM, true);
+    if (0 == sram_ports.size()) {
+      continue;
+    }
+    /* Find the name of memory module */
+    /* Get the total number of SRAMs */
+    size_t num_mems = 0; 
+    for (const auto& port : sram_ports) {
+      num_mems += circuit_lib.port_size(port);
+    }
+    /* Get the circuit model for the memory circuit used by the multiplexer */
+    std::vector<CircuitModelId> sram_models = find_circuit_sram_models(circuit_lib, model);
+    /* Should have only 1 SRAM model */
+    VTR_ASSERT( 1 == sram_models.size() );
+  
+    /* Create the module name for the memory block */
+    std::string module_name = generate_memory_module_name(circuit_lib, model, sram_models[0], std::string(MEMORY_MODULE_POSTFIX));
+
+    /* Create a Verilog module for the memories used by the circuit model */
+    build_memory_module(module_manager, circuit_lib, sram_orgz_type, module_name, sram_models[0], num_mems);
+  }
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fabric/build_memory_modules.h b/openfpga/src/fabric/build_memory_modules.h
new file mode 100644
index 000000000..2728d1d81
--- /dev/null
+++ b/openfpga/src/fabric/build_memory_modules.h
@@ -0,0 +1,25 @@
+#ifndef BUILD_MEMORY_MODULES_H
+#define BUILD_MEMORY_MODULES_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "circuit_library.h"
+#include "mux_library.h"
+#include "module_manager.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void build_memory_modules(ModuleManager& module_manager,
+                          const MuxLibrary& mux_lib,
+                          const CircuitLibrary& circuit_lib,
+                          const e_config_protocol_type& sram_orgz_type);
+
+} /* end namespace openfpga */
+
+#endif

From 895d5b5a0a756bc1b297a982df03ebf9e8f44168 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 12 Feb 2020 20:25:05 -0700
Subject: [PATCH 130/645] add utils for grid module builder

---
 .../src/base/openfpga_interconnect_types.h    |  15 +++
 openfpga/src/base/openfpga_reserved_words.h   |   6 +
 .../src/fabric/build_grid_module_utils.cpp    | 111 ++++++++++++++++++
 openfpga/src/fabric/build_grid_module_utils.h |  34 ++++++
 4 files changed, 166 insertions(+)
 create mode 100644 openfpga/src/base/openfpga_interconnect_types.h
 create mode 100644 openfpga/src/fabric/build_grid_module_utils.cpp
 create mode 100644 openfpga/src/fabric/build_grid_module_utils.h

diff --git a/openfpga/src/base/openfpga_interconnect_types.h b/openfpga/src/base/openfpga_interconnect_types.h
new file mode 100644
index 000000000..cbdd1535e
--- /dev/null
+++ b/openfpga/src/base/openfpga_interconnect_types.h
@@ -0,0 +1,15 @@
+#ifndef OPENFPGA_INTERCONNECT_TYPES_H
+#define OPENFPGA_INTERCONNECT_TYPES_H
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+enum e_pin2pin_interc_type {
+  INPUT2INPUT_INTERC,
+  OUTPUT2OUTPUT_INTERC,
+  NUM_PIN2PIN_INTERC_TYPES
+};
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/base/openfpga_reserved_words.h b/openfpga/src/base/openfpga_reserved_words.h
index 6e761de87..345c1183b 100644
--- a/openfpga/src/base/openfpga_reserved_words.h
+++ b/openfpga/src/base/openfpga_reserved_words.h
@@ -7,6 +7,10 @@
 #ifndef OPENFPGA_RESERVED_WORDS_H
 #define OPENFPGA_RESERVED_WORDS_H
 
+/* begin namespace openfpga */
+namespace openfpga {
+
+
 /* Grid naming constant strings */
 constexpr char* GRID_MODULE_NAME_PREFIX = "grid_"; 
 
@@ -25,4 +29,6 @@ constexpr char* CONNECTION_BLOCK_MUX_INSTANCE_PREFIX = "mux_";
 /* Bitstream file strings */
 constexpr char* BITSTREAM_XML_FILE_NAME_POSTFIX = "_bitstream.xml";
 
+} /* end namespace openfpga */
+
 #endif
diff --git a/openfpga/src/fabric/build_grid_module_utils.cpp b/openfpga/src/fabric/build_grid_module_utils.cpp
new file mode 100644
index 000000000..1386e93fe
--- /dev/null
+++ b/openfpga/src/fabric/build_grid_module_utils.cpp
@@ -0,0 +1,111 @@
+/********************************************************************
+ * This file includes most utilized functions for grid module builders
+ *******************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_side_manager.h"
+
+/* Headers from vpr library */
+#include "vpr_utils.h"
+
+#include "openfpga_naming.h"
+
+#include "build_grid_module_utils.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Find the side where I/O pins locate on a grid I/O block
+ * 1. I/O grids on the top    side of FPGA only have ports on its bottom side
+ * 2. I/O grids on the right  side of FPGA only have ports on its left   side
+ * 3. I/O grids on the bottom side of FPGA only have ports on its top    side
+ * 4. I/O grids on the left   side of FPGA only have ports on its right side
+ *******************************************************************/
+e_side find_grid_module_pin_side(t_physical_tile_type_ptr grid_type_descriptor,
+                                 const e_side& border_side) {
+  /* We must have an regular (non-I/O) type here */
+  VTR_ASSERT(true == is_io_type(grid_type_descriptor));
+  SideManager side_manager(border_side);
+  return side_manager.get_opposite(); 
+}
+
+/********************************************************************
+ * Add module nets to connect a port of child pb_module
+ * to the grid module 
+ *******************************************************************/
+void add_grid_module_net_connect_pb_graph_pin(ModuleManager& module_manager,
+                                              const ModuleId& grid_module,
+                                              const ModuleId& child_module,
+                                              const size_t& child_instance,
+                                              t_physical_tile_type_ptr grid_type_descriptor,
+                                              t_pb_graph_pin* pb_graph_pin,
+                                              const e_side& border_side,
+                                              const e_pin2pin_interc_type& pin2pin_interc_type) {
+  /* Find the pin side for I/O grids*/
+  std::vector<e_side> grid_pin_sides;
+  /* For I/O grids, we care only one side
+   * Otherwise, we will iterate all the 4 sides  
+   */
+  if (true == is_io_type(grid_type_descriptor)) {
+    grid_pin_sides.push_back(find_grid_module_pin_side(grid_type_descriptor, border_side));
+  } else {
+    grid_pin_sides.push_back(TOP); 
+    grid_pin_sides.push_back(RIGHT); 
+    grid_pin_sides.push_back(BOTTOM); 
+    grid_pin_sides.push_back(LEFT); 
+  }
+
+  /* num_pins/capacity = the number of pins that each type_descriptor has.
+   * Capacity defines the number of type_descriptors in each grid
+   * so the pin index at grid level = pin_index_in_type_descriptor 
+   *                                + type_descriptor_index_in_capacity * num_pins_per_type_descriptor
+   */
+  size_t grid_pin_index = pb_graph_pin->pin_count_in_cluster 
+                        + child_instance * grid_type_descriptor->num_pins / grid_type_descriptor->capacity;
+  int pin_height = grid_type_descriptor->pin_height_offset[grid_pin_index];
+  int pin_width = grid_type_descriptor->pin_width_offset[grid_pin_index];
+  for (const e_side& side : grid_pin_sides) {
+    if (true != grid_type_descriptor->pinloc[pin_width][pin_height][side][grid_pin_index]) {
+      continue;
+    }
+    /* Reach here, it means this pin is on this side */
+    /* Create a net to connect the grid pin to child module pin */
+    ModuleNetId net = module_manager.create_module_net(grid_module);
+    /* Find the port in grid_module */
+    vtr::Point<size_t> dummy_coordinate;
+    std::string grid_port_name = generate_grid_port_name(dummy_coordinate, pin_width, pin_height, side, grid_pin_index, false);
+    ModulePortId grid_module_port_id = module_manager.find_module_port(grid_module, grid_port_name);
+    VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_module_port_id));
+    /* Grid port always has only 1 pin, it is assumed when adding these ports to the module
+     * if you need a change, please also change the port adding codes  
+     */
+    size_t grid_module_pin_id = 0;
+    /* Find the port in child module */
+    std::string child_module_port_name = generate_pb_type_port_name(pb_graph_pin->port);
+    ModulePortId child_module_port_id = module_manager.find_module_port(child_module, child_module_port_name);
+    VTR_ASSERT(true == module_manager.valid_module_port_id(child_module, child_module_port_id));
+    size_t child_module_pin_id = pb_graph_pin->pin_number;
+    /* Add net sources and sinks:
+     * For input-to-input connection, net_source is grid pin, while net_sink is pb_graph_pin   
+     * For output-to-output connection, net_source is pb_graph_pin, while net_sink is grid pin   
+     */
+    switch (pin2pin_interc_type) {
+    case INPUT2INPUT_INTERC:
+      module_manager.add_module_net_source(grid_module, net, grid_module, 0, grid_module_port_id, grid_module_pin_id);
+      module_manager.add_module_net_sink(grid_module, net, child_module, child_instance, child_module_port_id, child_module_pin_id);
+      break;
+    case OUTPUT2OUTPUT_INTERC:
+      module_manager.add_module_net_source(grid_module, net, child_module, child_instance, child_module_port_id, child_module_pin_id);
+      module_manager.add_module_net_sink(grid_module, net, grid_module, 0, grid_module_port_id, grid_module_pin_id);
+      break;
+    default:
+      VTR_LOG_ERROR("Invalid pin-to-pin interconnection type!\n");
+      exit(1);
+    }
+  }
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fabric/build_grid_module_utils.h b/openfpga/src/fabric/build_grid_module_utils.h
new file mode 100644
index 000000000..654551fc5
--- /dev/null
+++ b/openfpga/src/fabric/build_grid_module_utils.h
@@ -0,0 +1,34 @@
+#ifndef BUILD_GRID_MODULE_UTILS_H
+#define BUILD_GRID_MODULE_UTILS_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+/* Headers from readarch library */
+#include "physical_types.h"
+
+#include "openfpga_interconnect_types.h"
+#include "module_manager.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+e_side find_grid_module_pin_side(t_physical_tile_type_ptr grid_type_descriptor,
+                                 const e_side& border_side);
+
+void add_grid_module_net_connect_pb_graph_pin(ModuleManager& module_manager,
+                                              const ModuleId& grid_module,
+                                              const ModuleId& child_module,
+                                              const size_t& child_instance,
+                                              t_physical_tile_type_ptr grid_type_descriptor,
+                                              t_pb_graph_pin* pb_graph_pin,
+                                              const e_side& border_side,
+                                              const enum e_pin2pin_interc_type& pin2pin_interc_type);
+
+} /* end namespace openfpga */
+
+#endif

From 59d579425efb511d1d31c7050765660524d56534 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 12 Feb 2020 20:48:07 -0700
Subject: [PATCH 131/645] add utils for duplicate pins in grid module builder

---
 .../build_grid_module_duplicated_pins.cpp     | 283 ++++++++++++++++++
 .../build_grid_module_duplicated_pins.h       |  32 ++
 2 files changed, 315 insertions(+)
 create mode 100644 openfpga/src/fabric/build_grid_module_duplicated_pins.cpp
 create mode 100644 openfpga/src/fabric/build_grid_module_duplicated_pins.h

diff --git a/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp b/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp
new file mode 100644
index 000000000..fc1f754df
--- /dev/null
+++ b/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp
@@ -0,0 +1,283 @@
+/********************************************************************
+ * This file includes functions that are used to add duplicated 
+ * pins to each side of a grid
+ *
+ * These functions are located in this file, being separated from
+ * the default functions in build_grid_module.cpp
+ * This allows us to keep new features easy to be maintained.
+ *
+ * Please follow this rules when creating new features!
+ *******************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+
+/* Headers from vpr library */
+#include "vpr_utils.h"
+
+#include "openfpga_naming.h"
+#include "openfpga_interconnect_types.h"
+
+#include "build_grid_module_utils.h"
+#include "build_grid_module_duplicated_pins.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * This function adds pb_type ports to top-level grid module with duplication
+ * For each pin at each side, we create two pins which are short-wired
+ * They are driven by the same pin, e.g., pinA in the child module
+ * But in this top module, we will create two pins, each of which indicates
+ * the physical location of pin.
+ * Take the following example: 
+ * One is called pinA_upper which is located close to the top side of this grid
+ * The other is called pinA_lower which is located close to the bottom side of this grid
+ *
+ * Similarly, we duplicate pins at TOP, RIGHT, BOTTOM and LEFT sides.
+ * For LEFT side, upper and lower pins carry the indication in physical location as RIGHT side.
+ * For TOP and BOTTOM side, upper pin is located close to the left side of a grid, while lower
+ * pin is located close to the right side of a grid  
+ *
+ *             pinB_upper   pinB_lower
+ *                 ^          ^
+ *                 |          |
+ *               ---------------+
+ *                              |--->pinA_upper
+ *                              |
+ *                       Grid   |  
+ *                              |
+ *                              |--->pinA_lower
+ *               ---------------+
+ *******************************************************************/
+void add_grid_module_duplicated_pb_type_ports(ModuleManager& module_manager,
+                                              const ModuleId& grid_module,
+                                              t_physical_tile_type_ptr grid_type_descriptor,
+                                              const e_side& border_side) {
+  /* Ensure that we have a valid grid_type_descriptor */
+  VTR_ASSERT(false == is_empty_type(grid_type_descriptor));
+
+  /* Find the pin side for I/O grids*/
+  std::vector<e_side> grid_pin_sides;
+  /* For I/O grids, we care only one side
+   * Otherwise, we will iterate all the 4 sides  
+   */
+  if (true == is_io_type(grid_type_descriptor)) {
+    grid_pin_sides.push_back(find_grid_module_pin_side(grid_type_descriptor, border_side));
+  } else {
+    grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT}; 
+  }
+
+  /* Create a map between pin class type and grid pin direction */
+  std::map<e_pin_type, ModuleManager::e_module_port_type> pin_type2type_map;
+  pin_type2type_map[RECEIVER] = ModuleManager::MODULE_INPUT_PORT;
+  pin_type2type_map[DRIVER] = ModuleManager::MODULE_OUTPUT_PORT;
+
+  /* Iterate over sides, height and pins */
+  for (const e_side& side : grid_pin_sides) {
+    for (int iwidth = 0; iwidth < grid_type_descriptor->width; ++iwidth) {
+      for (int iheight = 0; iheight < grid_type_descriptor->height; ++iheight) {
+        for (int ipin = 0; ipin < grid_type_descriptor->num_pins; ++ipin) {
+          if (true != grid_type_descriptor->pinloc[iwidth][iheight][side][ipin]) {
+            continue;
+          }
+          /* Reach here, it means this pin is on this side */
+          int class_id = grid_type_descriptor->pin_class[ipin];
+          e_pin_type pin_class_type = grid_type_descriptor->class_inf[class_id].type;
+          /* Generate the pin name 
+           * For each RECEIVER PIN or DRIVER PIN for direct connection, 
+           * we do not duplicate in these cases */
+          if ( (RECEIVER == pin_class_type)
+            /* Xifan: I assume that each direct connection pin must have Fc=0. */
+            || ( (DRIVER == pin_class_type) && (0. == grid_type_descriptor->fc_specs[ipin].fc_value) ) ) {
+            vtr::Point<size_t> dummy_coordinate;
+            std::string port_name = generate_grid_port_name(dummy_coordinate, iwidth, iheight, side, ipin, false);
+            BasicPort grid_port(port_name, 0, 0);
+            /* Add the port to the module */
+            module_manager.add_port(grid_module, grid_port, pin_type2type_map[pin_class_type]);
+          } else {
+            /* For each DRIVER pin, we create two copies.
+             * One with a postfix of upper, indicating it is located on the upper part of a side
+             * The other with a postfix of lower, indicating it is located on the lower part of a side
+             */
+            VTR_ASSERT(DRIVER == pin_class_type);
+            std::string upper_port_name = generate_grid_duplicated_port_name(iwidth, iheight, side, ipin, true);
+            BasicPort grid_upper_port(upper_port_name, 0, 0);
+            /* Add the port to the module */
+            module_manager.add_port(grid_module, grid_upper_port, pin_type2type_map[pin_class_type]);
+
+            std::string lower_port_name = generate_grid_duplicated_port_name(iwidth, iheight, side, ipin, false);
+            BasicPort grid_lower_port(lower_port_name, 0, 0);
+            /* Add the port to the module */
+            module_manager.add_port(grid_module, grid_lower_port, pin_type2type_map[pin_class_type]);
+          }
+        }  
+      }
+    }
+  }
+}
+
+/********************************************************************
+ * Add module nets to connect a port of child pb_module
+ * to the duplicated pins of grid module 
+ * Note: This function SHOULD be ONLY applied to pb_graph output pins 
+ * of the child module.
+ * For each such pin, we connect it to two outputs of the grid module
+ * one is named after "upper", and the other is named after "lower"
+ *******************************************************************/
+static 
+void add_grid_module_net_connect_duplicated_pb_graph_pin(ModuleManager& module_manager,
+                                                         const ModuleId& grid_module,
+                                                         const ModuleId& child_module,
+                                                         const size_t& child_instance,
+                                                         t_physical_tile_type_ptr grid_type_descriptor,
+                                                         t_pb_graph_pin* pb_graph_pin,
+                                                         const e_side& border_side,
+                                                         const e_pin2pin_interc_type& pin2pin_interc_type) {
+  /* Make sure this is ONLY applied to output pins */
+  VTR_ASSERT(OUTPUT2OUTPUT_INTERC == pin2pin_interc_type);
+  
+  /* Find the pin side for I/O grids*/
+  std::vector<e_side> grid_pin_sides;
+  /* For I/O grids, we care only one side
+   * Otherwise, we will iterate all the 4 sides  
+   */
+  if (true == is_io_type(grid_type_descriptor)) {
+    grid_pin_sides.push_back(find_grid_module_pin_side(grid_type_descriptor, border_side));
+  } else {
+    grid_pin_sides.push_back(TOP); 
+    grid_pin_sides.push_back(RIGHT); 
+    grid_pin_sides.push_back(BOTTOM); 
+    grid_pin_sides.push_back(LEFT); 
+  }
+
+  /* num_pins/capacity = the number of pins that each type_descriptor has.
+   * Capacity defines the number of type_descriptors in each grid
+   * so the pin index at grid level = pin_index_in_type_descriptor 
+   *                                + type_descriptor_index_in_capacity * num_pins_per_type_descriptor
+   */
+  size_t grid_pin_index = pb_graph_pin->pin_count_in_cluster 
+                        + child_instance * grid_type_descriptor->num_pins / grid_type_descriptor->capacity;
+  int pin_width = grid_type_descriptor->pin_height_offset[grid_pin_index];
+  int pin_height = grid_type_descriptor->pin_height_offset[grid_pin_index];
+  for (const e_side& side : grid_pin_sides) {
+    if (true != grid_type_descriptor->pinloc[pin_width][pin_height][side][grid_pin_index]) {
+      continue;
+    }
+
+    /* Pins for direct connection are NOT duplicated.
+     * Follow the traditional recipe when adding nets!  
+     * Xifan: I assume that each direct connection pin must have Fc=0. 
+     */
+    if (0. == grid_type_descriptor->fc_specs[grid_pin_index].fc_value) {
+      /* Create a net to connect the grid pin to child module pin */
+      ModuleNetId net = module_manager.create_module_net(grid_module);
+      /* Find the port in grid_module */
+      vtr::Point<size_t> dummy_coordinate;
+      std::string grid_port_name = generate_grid_port_name(dummy_coordinate, pin_width, pin_height, side, grid_pin_index, false);
+      ModulePortId grid_module_port_id = module_manager.find_module_port(grid_module, grid_port_name);
+      VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_module_port_id));
+
+      /* Grid port always has only 1 pin, it is assumed when adding these ports to the module
+       * if you need a change, please also change the port adding codes  
+       */
+      size_t grid_module_pin_id = 0;
+      /* Find the port in child module */
+      std::string child_module_port_name = generate_pb_type_port_name(pb_graph_pin->port);
+      ModulePortId child_module_port_id = module_manager.find_module_port(child_module, child_module_port_name);
+      VTR_ASSERT(true == module_manager.valid_module_port_id(child_module, child_module_port_id));
+      size_t child_module_pin_id = pb_graph_pin->pin_number;
+      /* Add net sources and sinks:
+       * For output-to-output connection, net_source is pb_graph_pin, while net_sink is grid pin   
+       */
+      module_manager.add_module_net_source(grid_module, net, child_module, child_instance, child_module_port_id, child_module_pin_id);
+      module_manager.add_module_net_sink(grid_module, net, grid_module, 0, grid_module_port_id, grid_module_pin_id);
+      continue;
+    }
+    /* Reach here, it means this pin is on this side */
+    /* Create a net to connect the grid pin to child module pin */
+    ModuleNetId net = module_manager.create_module_net(grid_module);
+    /* Find the upper port in grid_module */
+    std::string grid_upper_port_name = generate_grid_duplicated_port_name(pin_width, pin_height, side, grid_pin_index, true);
+    ModulePortId grid_module_upper_port_id = module_manager.find_module_port(grid_module, grid_upper_port_name);
+    VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_module_upper_port_id));
+
+    /* Find the lower port in grid_module */
+    std::string grid_lower_port_name = generate_grid_duplicated_port_name(pin_width, pin_height, side, grid_pin_index, false);
+    ModulePortId grid_module_lower_port_id = module_manager.find_module_port(grid_module, grid_lower_port_name);
+    VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_module_lower_port_id));
+
+    /* Grid port always has only 1 pin, it is assumed when adding these ports to the module
+     * if you need a change, please also change the port adding codes  
+     */
+    size_t grid_module_pin_id = 0;
+    /* Find the port in child module */
+    std::string child_module_port_name = generate_pb_type_port_name(pb_graph_pin->port);
+    ModulePortId child_module_port_id = module_manager.find_module_port(child_module, child_module_port_name);
+    VTR_ASSERT(true == module_manager.valid_module_port_id(child_module, child_module_port_id));
+    size_t child_module_pin_id = pb_graph_pin->pin_number;
+
+    /* Add net sources and sinks:
+     * For output-to-output connection, 
+     * net_source is pb_graph_pin, 
+     * while net_sinks are grid upper pin and grid lower pin
+     */
+    module_manager.add_module_net_source(grid_module, net, child_module, child_instance, child_module_port_id, child_module_pin_id);
+    module_manager.add_module_net_sink(grid_module, net, grid_module, 0, grid_module_upper_port_id, grid_module_pin_id);
+    module_manager.add_module_net_sink(grid_module, net, grid_module, 0, grid_module_lower_port_id, grid_module_pin_id);
+  }
+}
+
+/********************************************************************
+ * Add module nets to connect a port of child pb_module
+ * to the duplicated ports of grid module 
+ *******************************************************************/
+void add_grid_module_nets_connect_duplicated_pb_type_ports(ModuleManager& module_manager,
+                                                           const ModuleId& grid_module,
+                                                           const ModuleId& child_module,
+                                                           const size_t& child_instance,
+                                                           t_physical_tile_type_ptr grid_type_descriptor,
+                                                           const e_side& border_side) {
+  /* Ensure that we have a valid grid_type_descriptor */
+  VTR_ASSERT(false == is_empty_type(grid_type_descriptor));
+
+  for (t_logical_block_type_ptr lb_type : grid_type_descriptor->equivalent_sites) {
+    t_pb_graph_node* top_pb_graph_node = lb_type->pb_graph_head;
+    VTR_ASSERT(nullptr != top_pb_graph_node); 
+
+    for (int iport = 0; iport < top_pb_graph_node->num_input_ports; ++iport) {
+      for (int ipin = 0; ipin < top_pb_graph_node->num_input_pins[iport]; ++ipin) {
+        add_grid_module_net_connect_pb_graph_pin(module_manager, grid_module,
+                                                 child_module, child_instance,
+                                                 grid_type_descriptor,
+                                                 &(top_pb_graph_node->input_pins[iport][ipin]),
+                                                 border_side,
+                                                 INPUT2INPUT_INTERC);
+
+      }
+    }
+
+    for (int iport = 0; iport < top_pb_graph_node->num_output_ports; ++iport) {
+      for (int ipin = 0; ipin < top_pb_graph_node->num_output_pins[iport]; ++ipin) {
+        add_grid_module_net_connect_duplicated_pb_graph_pin(module_manager, grid_module,
+                                                            child_module, child_instance,
+                                                            grid_type_descriptor,
+                                                            &(top_pb_graph_node->output_pins[iport][ipin]),
+                                                            border_side,
+                                                            OUTPUT2OUTPUT_INTERC);
+      }
+    }
+
+    for (int iport = 0; iport < top_pb_graph_node->num_clock_ports; ++iport) {
+      for (int ipin = 0; ipin < top_pb_graph_node->num_clock_pins[iport]; ++ipin) {
+        add_grid_module_net_connect_pb_graph_pin(module_manager, grid_module,
+                                                 child_module, child_instance,
+                                                 grid_type_descriptor,
+                                                 &(top_pb_graph_node->clock_pins[iport][ipin]),
+                                                 border_side,
+                                                 INPUT2INPUT_INTERC);
+      } 
+    }
+  }
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fabric/build_grid_module_duplicated_pins.h b/openfpga/src/fabric/build_grid_module_duplicated_pins.h
new file mode 100644
index 000000000..2bdd56dea
--- /dev/null
+++ b/openfpga/src/fabric/build_grid_module_duplicated_pins.h
@@ -0,0 +1,32 @@
+#ifndef BUILD_GRID_MODULE_DUPLICATED_PINS_H
+#define BUILD_GRID_MODULE_DUPLICATED_PINS_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "physical_types.h"
+#include "module_manager.h"
+#include "openfpga_side_manager.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void add_grid_module_duplicated_pb_type_ports(ModuleManager& module_manager,
+                                              const ModuleId& grid_module,
+                                              t_physical_tile_type_ptr grid_type_descriptor,
+                                              const e_side& border_side);
+
+void add_grid_module_nets_connect_duplicated_pb_type_ports(ModuleManager& module_manager,
+                                                           const ModuleId& grid_module,
+                                                           const ModuleId& child_module,
+                                                           const size_t& child_instance,
+                                                           t_physical_tile_type_ptr grid_type_descriptor,
+                                                           const e_side& border_side);
+
+} /* end namespace openfpga */
+
+#endif

From 072965cd64ffa237fada1210bdfe1471e49c6dcd Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 13 Feb 2020 15:27:16 -0700
Subject: [PATCH 132/645] make grid module builder online; basic support on
 physical tiles

---
 openfpga/src/base/openfpga_build_fabric.cpp   |    4 +-
 .../src/base/openfpga_interconnect_types.h    |    7 +
 openfpga/src/base/openfpga_naming.cpp         |   42 +-
 openfpga/src/base/openfpga_naming.h           |   16 +-
 openfpga/src/base/openfpga_reserved_words.h   |    4 +
 openfpga/src/fabric/build_device_module.cpp   |   14 +-
 openfpga/src/fabric/build_device_module.h     |    3 +-
 .../build_grid_module_duplicated_pins.cpp     |    1 +
 openfpga/src/fabric/build_grid_modules.cpp    | 1107 +++++++++++++++++
 openfpga/src/fabric/build_grid_modules.h      |   30 +
 10 files changed, 1173 insertions(+), 55 deletions(-)
 create mode 100644 openfpga/src/fabric/build_grid_modules.cpp
 create mode 100644 openfpga/src/fabric/build_grid_modules.h

diff --git a/openfpga/src/base/openfpga_build_fabric.cpp b/openfpga/src/base/openfpga_build_fabric.cpp
index f8fde4a31..c15cf548f 100644
--- a/openfpga/src/base/openfpga_build_fabric.cpp
+++ b/openfpga/src/base/openfpga_build_fabric.cpp
@@ -61,6 +61,7 @@ void build_fabric(OpenfpgaContext& openfpga_context,
                   const Command& cmd, const CommandContext& cmd_context) { 
 
   CommandOptionId opt_compress_routing = cmd.option("compress_routing");
+  CommandOptionId opt_duplicate_grid_pin = cmd.option("duplicate_grid_pin");
   CommandOptionId opt_verbose = cmd.option("verbose");
   
   if (true == cmd_context.option_enable(cmd, opt_compress_routing)) {
@@ -70,7 +71,8 @@ void build_fabric(OpenfpgaContext& openfpga_context,
   VTR_LOG("\n");
 
   openfpga_context.mutable_module_graph() = build_device_module_graph(g_vpr_ctx.device(),
-                                                                      const_cast<const OpenfpgaContext&>(openfpga_context));
+                                                                      const_cast<const OpenfpgaContext&>(openfpga_context),
+                                                                      cmd_context.option_enable(cmd, opt_duplicate_grid_pin));
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_interconnect_types.h b/openfpga/src/base/openfpga_interconnect_types.h
index cbdd1535e..a402323f0 100644
--- a/openfpga/src/base/openfpga_interconnect_types.h
+++ b/openfpga/src/base/openfpga_interconnect_types.h
@@ -10,6 +10,13 @@ enum e_pin2pin_interc_type {
   NUM_PIN2PIN_INTERC_TYPES
 };
 
+enum e_circuit_pb_port_type {
+  CIRCUIT_PB_PORT_INPUT,
+  CIRCUIT_PB_PORT_OUTPUT,
+  CIRCUIT_PB_PORT_CLOCK,
+  NUM_CIRCUIT_PB_PORT_TYPES 
+};
+
 } /* end namespace openfpga */
 
 #endif
diff --git a/openfpga/src/base/openfpga_naming.cpp b/openfpga/src/base/openfpga_naming.cpp
index 19c58a1bc..7aaafff5d 100644
--- a/openfpga/src/base/openfpga_naming.cpp
+++ b/openfpga/src/base/openfpga_naming.cpp
@@ -11,6 +11,7 @@
 #include "openfpga_side_manager.h"
 #include "pb_type_utils.h"
 #include "circuit_library_utils.h"
+#include "openfpga_reserved_words.h"
 #include "openfpga_naming.h"
 
 /* begin namespace openfpga */
@@ -1116,7 +1117,9 @@ std::string generate_grid_block_instance_name(const std::string& prefix,
 }
 
 /*********************************************************************
- * Generate the module name of a physical block
+ * Generate the module name of a logical block type (pb_type)
+ * Since the logical block does not carry any physical attributes,
+ * this logical block will have a common prefix 'logical_type'
  * To ensure a unique name for each physical block inside the graph of complex blocks
  * (pb_graph_nodes), this function trace backward to the top-level node
  * in the graph and add the name of these parents 
@@ -1126,8 +1129,7 @@ std::string generate_grid_block_instance_name(const std::string& prefix,
  * TODO: to make sure the length of this name does not exceed the size of
  * chars in a line of a file!!! 
  **********************************************************************/
-std::string generate_physical_block_module_name(const std::string& prefix,
-                                                t_pb_type* physical_pb_type) {
+std::string generate_physical_block_module_name(t_pb_type* physical_pb_type) {
   std::string module_name(physical_pb_type->name);
 
   t_pb_type* parent_pb_type = physical_pb_type;
@@ -1164,7 +1166,7 @@ std::string generate_physical_block_module_name(const std::string& prefix,
   }
 
   /* Add the prefix */
-  module_name = prefix + module_name;
+  module_name = LOGICAL_MODULE_NAME_PREFIX + module_name;
 
   return module_name;
 }
@@ -1173,37 +1175,9 @@ std::string generate_physical_block_module_name(const std::string& prefix,
 /*********************************************************************
  * Generate the instance name for physical block with a given index 
  **********************************************************************/
-std::string generate_physical_block_instance_name(const std::string& prefix,
-                                                  t_pb_type* pb_type,
+std::string generate_physical_block_instance_name(t_pb_type* pb_type,
                                                   const size_t& index) {
-  std::string instance_name = generate_physical_block_module_name(prefix, pb_type);
-  /* Add index to the name */
-  instance_name += std::string("_");
-  instance_name += std::to_string(index);
-
-  return instance_name;
-}
-
-/*********************************************************************
- * This function is a wrapper for the function generate_physical_block_module_name()
- * which can automatically decode the io_side and add a prefix 
- **********************************************************************/
-std::string generate_grid_physical_block_module_name(const std::string& prefix, 
-                                                     t_pb_type* pb_type, 
-                                                     const e_side& border_side) {
-  std::string module_name_prefix = generate_grid_block_prefix(prefix, border_side);
-  return generate_physical_block_module_name(module_name_prefix, pb_type); 
-}
-
-/*********************************************************************
- * Generate the instance name for physical block in Grid with a given index 
- **********************************************************************/
-std::string generate_grid_physical_block_instance_name(const std::string& prefix, 
-                                                       t_pb_type* pb_type, 
-                                                       const e_side& border_side,
-                                                       const size_t& index) {
-  std::string module_name_prefix = generate_grid_block_prefix(prefix, border_side);
-  std::string instance_name = generate_physical_block_module_name(module_name_prefix, pb_type);
+  std::string instance_name = generate_physical_block_module_name(pb_type);
   /* Add index to the name */
   instance_name += std::string("_");
   instance_name += std::to_string(index);
diff --git a/openfpga/src/base/openfpga_naming.h b/openfpga/src/base/openfpga_naming.h
index 0c0c640ca..4bc22f3c9 100644
--- a/openfpga/src/base/openfpga_naming.h
+++ b/openfpga/src/base/openfpga_naming.h
@@ -219,23 +219,11 @@ std::string generate_grid_block_instance_name(const std::string& prefix,
                                               const e_side& io_side,
                                               const vtr::Point<size_t>& grid_coord);
 
-std::string generate_physical_block_module_name(const std::string& prefix,
-                                                t_pb_type* physical_pb_type);
+std::string generate_physical_block_module_name(t_pb_type* physical_pb_type);
 
-std::string generate_physical_block_instance_name(const std::string& prefix,
-                                                  t_pb_type* pb_type,
+std::string generate_physical_block_instance_name(t_pb_type* pb_type,
                                                   const size_t& index);
 
-std::string generate_grid_physical_block_module_name(const std::string& prefix,
-                                                     t_pb_type* pb_type,
-                                                     const e_side& border_side);
-
-std::string generate_grid_physical_block_instance_name(const std::string& prefix, 
-                                                       t_pb_type* pb_type, 
-                                                       const e_side& border_side,
-                                                       const size_t& index);
-
-
 e_side find_grid_border_side(const vtr::Point<size_t>& device_size,
                              const vtr::Point<size_t>& grid_coordinate);
 
diff --git a/openfpga/src/base/openfpga_reserved_words.h b/openfpga/src/base/openfpga_reserved_words.h
index 345c1183b..f04490c0d 100644
--- a/openfpga/src/base/openfpga_reserved_words.h
+++ b/openfpga/src/base/openfpga_reserved_words.h
@@ -10,9 +10,13 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
+/* IO PORT */
+/* Prefix of global input, output and inout ports of FPGA fabric */
+constexpr char* GIO_INOUT_PREFIX = "gfpga_pad_";
 
 /* Grid naming constant strings */
 constexpr char* GRID_MODULE_NAME_PREFIX = "grid_"; 
+constexpr char* LOGICAL_MODULE_NAME_PREFIX = "logical_tile_"; 
 
 /* Memory naming constant strings */
 constexpr char* GRID_MEM_INSTANCE_PREFIX = "mem_"; 
diff --git a/openfpga/src/fabric/build_device_module.cpp b/openfpga/src/fabric/build_device_module.cpp
index 40d856022..d6f759b30 100644
--- a/openfpga/src/fabric/build_device_module.cpp
+++ b/openfpga/src/fabric/build_device_module.cpp
@@ -14,7 +14,7 @@
 #include "build_lut_modules.h"
 #include "build_wire_modules.h"
 #include "build_memory_modules.h"
-//#include "build_grid_modules.h"
+#include "build_grid_modules.h"
 //#include "build_routing_modules.h"
 //#include "build_top_module.h"
 #include "build_device_module.h"
@@ -27,7 +27,8 @@ namespace openfpga {
  * for a FPGA fabric
  *******************************************************************/
 ModuleManager build_device_module_graph(const DeviceContext& vpr_device_ctx,
-                                        const OpenfpgaContext& openfpga_ctx) {
+                                        const OpenfpgaContext& openfpga_ctx,
+                                        const bool& duplicate_grid_pin) {
   vtr::ScopedStartFinishTimer timer("Build fabric module graph");
 
   /* Module manager to be built */
@@ -67,9 +68,12 @@ ModuleManager build_device_module_graph(const DeviceContext& vpr_device_ctx,
                        openfpga_ctx.arch().config_protocol.type());
 
   /* Build grid and programmable block modules */
-  //build_grid_modules(module_manager, arch.spice->circuit_lib, mux_lib,  
-  //                   arch.sram_inf.verilog_sram_inf_orgz->type, sram_model,
-  //                   TRUE == vpr_setup.FPGA_SPICE_Opts.duplicate_grid_pin);
+  build_grid_modules(module_manager, vpr_device_ctx,
+                     openfpga_ctx.vpr_device_annotation(),
+                     openfpga_ctx.arch().circuit_lib,
+                     openfpga_ctx.mux_lib(),
+                     openfpga_ctx.arch().config_protocol.type(),
+                     sram_model, duplicate_grid_pin);
 
   //if (TRUE == vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy) {
   //  build_unique_routing_modules(module_manager, L_device_rr_gsb, arch.spice->circuit_lib, 
diff --git a/openfpga/src/fabric/build_device_module.h b/openfpga/src/fabric/build_device_module.h
index 1e6bb2226..fd646844f 100644
--- a/openfpga/src/fabric/build_device_module.h
+++ b/openfpga/src/fabric/build_device_module.h
@@ -15,7 +15,8 @@
 namespace openfpga {
 
 ModuleManager build_device_module_graph(const DeviceContext& vpr_device_ctx,
-                                        const OpenfpgaContext& openfpga_ctx);
+                                        const OpenfpgaContext& openfpga_ctx,
+                                        const bool& duplicate_grid_pin);
 
 } /* end namespace openfpga */
 
diff --git a/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp b/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp
index fc1f754df..d63b85998 100644
--- a/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp
+++ b/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp
@@ -157,6 +157,7 @@ void add_grid_module_net_connect_duplicated_pb_graph_pin(ModuleManager& module_m
    */
   size_t grid_pin_index = pb_graph_pin->pin_count_in_cluster 
                         + child_instance * grid_type_descriptor->num_pins / grid_type_descriptor->capacity;
+
   int pin_width = grid_type_descriptor->pin_height_offset[grid_pin_index];
   int pin_height = grid_type_descriptor->pin_height_offset[grid_pin_index];
   for (const e_side& side : grid_pin_sides) {
diff --git a/openfpga/src/fabric/build_grid_modules.cpp b/openfpga/src/fabric/build_grid_modules.cpp
new file mode 100644
index 000000000..df0a63d03
--- /dev/null
+++ b/openfpga/src/fabric/build_grid_modules.cpp
@@ -0,0 +1,1107 @@
+/********************************************************************
+ * This file includes functions to print Verilog modules for a Grid
+ * (CLBs, I/Os, heterogeneous blocks etc.) 
+ *******************************************************************/
+#include <ctime>
+#include <vector>
+
+/* Headers from vtrutil library */
+#include "vtr_geometry.h"
+#include "vtr_log.h"
+#include "vtr_assert.h"
+#include "vtr_time.h"
+
+/* Headers from vpr library */
+#include "vpr_utils.h"
+
+#include "circuit_library_utils.h"
+#include "openfpga_reserved_words.h"
+#include "openfpga_naming.h"
+#include "openfpga_interconnect_types.h"
+#include "pb_type_utils.h"
+#include "pb_graph_utils.h"
+#include "module_manager_utils.h"
+
+#include "build_grid_module_utils.h"
+#include "build_grid_module_duplicated_pins.h"
+#include "build_grid_modules.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Add ports/pins to a grid module 
+ * This function will iterate over all the pins that are defined 
+ * in type_descripter and give a name by its height, side and index
+ *
+ * In particular, for I/O grid, only part of the ports on required
+ * on a specific side.
+ *******************************************************************/
+static 
+void add_grid_module_pb_type_ports(ModuleManager& module_manager,
+                                   const ModuleId& grid_module,
+                                   t_physical_tile_type_ptr grid_type_descriptor,
+                                   const e_side& border_side) {
+  /* Ensure that we have a valid grid_type_descriptor */
+  VTR_ASSERT(nullptr != grid_type_descriptor);
+
+  /* Find the pin side for I/O grids*/
+  std::vector<e_side> grid_pin_sides;
+  /* For I/O grids, we care only one side
+   * Otherwise, we will iterate all the 4 sides  
+   */
+  if (true == is_io_type(grid_type_descriptor)) {
+    grid_pin_sides.push_back(find_grid_module_pin_side(grid_type_descriptor, border_side));
+  } else {
+    grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT}; 
+  }
+
+  /* Create a map between pin class type and grid pin direction */
+  std::map<e_pin_type, ModuleManager::e_module_port_type> pin_type2type_map;
+  pin_type2type_map[RECEIVER] = ModuleManager::MODULE_INPUT_PORT;
+  pin_type2type_map[DRIVER] = ModuleManager::MODULE_OUTPUT_PORT;
+
+  /* Iterate over sides, height and pins */
+  for (const e_side& side : grid_pin_sides) {
+    for (int iwidth = 0; iwidth < grid_type_descriptor->width; ++iwidth) {
+      for (int iheight = 0; iheight < grid_type_descriptor->height; ++iheight) {
+        for (int ipin = 0; ipin < grid_type_descriptor->num_pins; ++ipin) {
+          if (true != grid_type_descriptor->pinloc[iwidth][iheight][side][ipin]) {
+            continue;
+          }
+          /* Reach here, it means this pin is on this side */
+          int class_id = grid_type_descriptor->pin_class[ipin];
+          e_pin_type pin_class_type = grid_type_descriptor->class_inf[class_id].type;
+          /* Generate the pin name, 
+           * we give a empty coordinate but it will not be used (see details in the function 
+           */
+          vtr::Point<size_t> dummy_coordinate;
+          std::string port_name = generate_grid_port_name(dummy_coordinate, iwidth, iheight, side, ipin, false);
+          BasicPort grid_port(port_name, 0, 0);
+          /* Add the port to the module */
+          module_manager.add_port(grid_module, grid_port, pin_type2type_map[pin_class_type]);
+        }  
+      }
+    }
+  }
+}
+
+/********************************************************************
+ * Add module nets to connect ports/pins of a grid module 
+ * to its child modules
+ * This function will iterate over all the pins that are defined 
+ * in type_descripter and find the corresponding pin in the top
+ * pb_graph_node of the grid 
+ *******************************************************************/
+static 
+void add_grid_module_nets_connect_pb_type_ports(ModuleManager& module_manager,
+                                                const ModuleId& grid_module,
+                                                const ModuleId& child_module,
+                                                const size_t& child_instance,
+                                                t_physical_tile_type_ptr grid_type_descriptor,
+                                                const e_side& border_side) {
+  /* Ensure that we have a valid grid_type_descriptor */
+  VTR_ASSERT(nullptr != grid_type_descriptor);
+
+  for (t_logical_block_type_ptr lb_type : grid_type_descriptor->equivalent_sites) {
+    t_pb_graph_node* top_pb_graph_node = lb_type->pb_graph_head;
+    VTR_ASSERT(nullptr != top_pb_graph_node); 
+
+    for (int iport = 0; iport < top_pb_graph_node->num_input_ports; ++iport) {
+      for (int ipin = 0; ipin < top_pb_graph_node->num_input_pins[iport]; ++ipin) {
+        add_grid_module_net_connect_pb_graph_pin(module_manager, grid_module,
+                                                 child_module, child_instance,
+                                                 grid_type_descriptor,
+                                                 &(top_pb_graph_node->input_pins[iport][ipin]),
+                                                 border_side,
+                                                 INPUT2INPUT_INTERC);
+
+      }
+    }
+
+    for (int iport = 0; iport < top_pb_graph_node->num_output_ports; ++iport) {
+      for (int ipin = 0; ipin < top_pb_graph_node->num_output_pins[iport]; ++ipin) {
+        add_grid_module_net_connect_pb_graph_pin(module_manager, grid_module,
+                                                 child_module, child_instance,
+                                                 grid_type_descriptor,
+                                                 &(top_pb_graph_node->output_pins[iport][ipin]),
+                                                 border_side,
+                                                 OUTPUT2OUTPUT_INTERC);
+      }
+    }
+
+    for (int iport = 0; iport < top_pb_graph_node->num_clock_ports; ++iport) {
+      for (int ipin = 0; ipin < top_pb_graph_node->num_clock_pins[iport]; ++ipin) {
+        add_grid_module_net_connect_pb_graph_pin(module_manager, grid_module,
+                                                 child_module, child_instance,
+                                                 grid_type_descriptor,
+                                                 &(top_pb_graph_node->clock_pins[iport][ipin]),
+                                                 border_side,
+                                                 INPUT2INPUT_INTERC);
+      } 
+    }
+  }
+}
+
+/********************************************************************
+ * Print Verilog modules of a primitive node in the pb_graph_node graph
+ * This generic function can support all the different types of primitive nodes
+ * i.e., Look-Up Tables (LUTs), Flip-flops (FFs) and hard logic blocks such as adders.
+ *
+ * The Verilog module will consist of two parts:
+ * 1. Logic module of the primitive node
+ *    This module performs the logic function of the block
+ * 2. Memory module of the primitive node
+ *    This module stores the configuration bits for the logic module
+ *    if the logic module is a programmable resource, such as LUT
+ *
+ * Verilog module structure:
+ *
+ *       Primitive block
+ *     +---------------------------------------+
+ *     |                                       | 
+ *     |      +---------+    +---------+       |
+ *  in |----->|         |--->|         |<------|configuration lines
+ *     |      |  Logic  |... |  Memory |       |
+ *  out|<-----|         |--->|         |       |
+ *     |      +---------+    +---------+       |
+ *     |                                       | 
+ *     +---------------------------------------+
+ *
+ *******************************************************************/
+static 
+void build_primitive_block_module(ModuleManager& module_manager,
+                                  const VprDeviceAnnotation& device_annotation,
+                                  const CircuitLibrary& circuit_lib,
+                                  const e_config_protocol_type& sram_orgz_type,
+                                  const CircuitModelId& sram_model,
+                                  t_pb_graph_node* primitive_pb_graph_node) {
+  /* Ensure a valid pb_graph_node */ 
+  VTR_ASSERT(nullptr != primitive_pb_graph_node);
+
+  /* Find the circuit model id linked to the pb_graph_node */
+  const CircuitModelId& primitive_model = device_annotation.pb_type_circuit_model(primitive_pb_graph_node->pb_type);
+
+  /* Generate the module name for this primitive pb_graph_node*/
+  std::string primitive_module_name = generate_physical_block_module_name(primitive_pb_graph_node->pb_type);
+
+  /* Create a module of the primitive LUT and register it to module manager */
+  ModuleId primitive_module = module_manager.add_module(primitive_module_name);
+  /* Ensure that the module has been created and thus unique! */
+  VTR_ASSERT(ModuleId::INVALID() != primitive_module);
+
+  /* Note: to cooperate with the pb_type hierarchy and connections, we add the port of primitive pb_type here.
+   * Since we have linked pb_type ports to circuit models when setting up FPGA-X2P,
+   * no ports of the circuit model will be missing here  
+   */
+  add_primitive_pb_type_ports_to_module_manager(module_manager, primitive_module,
+                                                primitive_pb_graph_node->pb_type, device_annotation); 
+
+  /* Add configuration ports */
+  /* Shared SRAM ports*/
+  size_t num_shared_config_bits = find_circuit_num_shared_config_bits(circuit_lib, primitive_model, sram_orgz_type);
+  if (0 < num_shared_config_bits) {
+    /* Check: this SRAM organization type must be memory-bank ! */
+    VTR_ASSERT( CONFIG_MEM_MEMORY_BANK == sram_orgz_type );
+    /* Generate a list of ports */
+    add_reserved_sram_ports_to_module_manager(module_manager, primitive_module, 
+                                              num_shared_config_bits); 
+  }
+
+  /* Regular (independent) SRAM ports */
+  size_t num_config_bits = find_circuit_num_config_bits(circuit_lib, primitive_model);
+  if (0 < num_config_bits) {
+    add_sram_ports_to_module_manager(module_manager, primitive_module,
+                                     circuit_lib, sram_model, sram_orgz_type,
+                                     num_config_bits);
+  }
+
+  /* Find the module id in the module manager */
+  ModuleId logic_module = module_manager.find_module(circuit_lib.model_name(primitive_model));
+  VTR_ASSERT(ModuleId::INVALID() != logic_module);
+  size_t logic_instance_id = module_manager.num_instance(primitive_module, logic_module); 
+  /* Add the logic module as a child of primitive module */
+  module_manager.add_child_module(primitive_module, logic_module);
+
+  /* Add nets to connect the logic model ports to pb_type ports */
+  add_primitive_pb_type_module_nets(module_manager, primitive_module, 
+                                    logic_module, logic_instance_id, 
+                                    circuit_lib, primitive_pb_graph_node->pb_type,
+                                    device_annotation);
+
+  /* Add the associated memory module as a child of primitive module */
+  std::string memory_module_name = generate_memory_module_name(circuit_lib, primitive_model, sram_model, std::string(MEMORY_MODULE_POSTFIX));
+  ModuleId memory_module = module_manager.find_module(memory_module_name);
+
+  /* Vectors to record all the memory modules have been added
+   * They are used to add module nets of configuration bus
+   */
+  std::vector<ModuleId> memory_modules;
+  std::vector<size_t> memory_instances;
+
+  /* If there is no memory module required, we can skip the assocated net addition */
+  if (ModuleId::INVALID() != memory_module) {
+    size_t memory_instance_id = module_manager.num_instance(primitive_module, memory_module); 
+    /* Add the memory module as a child of primitive module */
+    module_manager.add_child_module(primitive_module, memory_module);
+    /* Set an instance name to bind to a block in bitstream generation */
+    module_manager.set_child_instance_name(primitive_module, memory_module, memory_instance_id, memory_module_name);
+  
+    /* Add nets to connect regular and mode-select SRAM ports to the SRAM port of memory module */
+    add_module_nets_between_logic_and_memory_sram_bus(module_manager, primitive_module, 
+                                                      logic_module, logic_instance_id,
+                                                      memory_module, memory_instance_id,
+                                                      circuit_lib, primitive_model);
+    /* Record memory-related information */
+    module_manager.add_configurable_child(primitive_module, memory_module, memory_instance_id);
+  }
+  /* Add all the nets to connect configuration ports from memory module to primitive modules
+   * This is a one-shot addition that covers all the memory modules in this primitive module!
+   */
+  if (false == memory_modules.empty()) {
+    add_module_nets_memory_config_bus(module_manager, primitive_module, 
+                                      sram_orgz_type, circuit_lib.design_tech_type(sram_model));
+  }
+
+  /* Add global ports to the pb_module:
+   * This is a much easier job after adding sub modules (instances), 
+   * we just need to find all the global ports from the child modules and build a list of it
+   */
+  add_module_global_ports_from_child_modules(module_manager, primitive_module);
+
+  /* Find the inout ports required by the primitive node, and add them to the module
+   * This is mainly due to the I/O blocks, which have inout ports for the top-level fabric
+   */
+  if (CIRCUIT_MODEL_IOPAD == circuit_lib.model_type(primitive_model)) {
+    std::vector<CircuitPortId> primitive_model_inout_ports = circuit_lib.model_ports_by_type(primitive_model, CIRCUIT_MODEL_PORT_INOUT);
+    for (auto port : primitive_model_inout_ports) {
+      BasicPort module_port(generate_fpga_global_io_port_name(std::string(GIO_INOUT_PREFIX), circuit_lib, primitive_model), circuit_lib.port_size(port));
+      ModulePortId primitive_gpio_port_id = module_manager.add_port(primitive_module, module_port, ModuleManager::MODULE_GPIO_PORT);
+      ModulePortId logic_gpio_port_id = module_manager.find_module_port(logic_module, circuit_lib.port_prefix(port));
+      BasicPort logic_gpio_port = module_manager.module_port(logic_module, logic_gpio_port_id);
+      VTR_ASSERT(logic_gpio_port.get_width() == module_port.get_width());
+
+      /* Wire the GPIO port form primitive_module to the logic module!*/
+      for (size_t pin_id = 0; pin_id < module_port.pins().size(); ++pin_id) {      
+        ModuleNetId net = module_manager.create_module_net(primitive_module);
+        module_manager.add_module_net_source(primitive_module, net, primitive_module, 0, primitive_gpio_port_id, module_port.pins()[pin_id]);
+        module_manager.add_module_net_sink(primitive_module, net, logic_module, logic_instance_id, logic_gpio_port_id, logic_gpio_port.pins()[pin_id]);
+      }
+    }
+  }
+}
+
+/********************************************************************
+ * This function add a net for a pin-to-pin connection defined in pb_graph
+ * It supports two cases for the pin-to-pin connection
+ * 1. The net source is a pb_graph_pin while the net sink is a pin of an interconnection
+ * 2. The net source is a pin of an interconnection while the net sink a pb_graph_pin
+ * The type is enabled by an argument pin2pin_interc_type
+ *******************************************************************/
+static 
+void add_module_pb_graph_pin2pin_net(ModuleManager& module_manager,
+                                     const ModuleId& pb_module,
+                                     const ModuleId& interc_module,
+                                     const size_t& interc_instance,
+                                     const std::string& interc_port_name,
+                                     const size_t& interc_pin_id,
+                                     t_pb_graph_pin* pb_graph_pin,
+                                     const enum e_pin2pin_interc_type& pin2pin_interc_type) {
+
+  ModuleNetId pin2pin_net = module_manager.create_module_net(pb_module);
+
+  /* Find port and pin ids for the module, which is the parent of pb_graph_pin  */
+  t_pb_type* pin_pb_type = pb_graph_pin->parent_node->pb_type;
+  /* Find the module contains the source pin */
+  ModuleId pin_pb_type_module = module_manager.find_module(generate_physical_block_module_name(pin_pb_type));
+  VTR_ASSERT(true == module_manager.valid_module_id(pin_pb_type_module));
+  size_t pin_pb_type_instance = 0; /* Deposite the instance with a zero, which is the default value is the source module is actually pb_module itself */
+  if (pin_pb_type_module != pb_module) {
+    pin_pb_type_instance = pb_graph_pin->parent_node->placement_index;
+    /* Ensure this is an valid instance */
+    VTR_ASSERT(pin_pb_type_instance < module_manager.num_instance(pb_module, pin_pb_type_module));
+  }
+  ModulePortId pin_module_port_id = module_manager.find_module_port(pin_pb_type_module, generate_pb_type_port_name(pb_graph_pin->port)); 
+  VTR_ASSERT(true == module_manager.valid_module_port_id(pin_pb_type_module, pin_module_port_id));
+  size_t pin_module_pin_id = pb_graph_pin->pin_number;
+  /* Ensure this is an valid pin index */
+  VTR_ASSERT(pin_module_pin_id < module_manager.module_port(pin_pb_type_module, pin_module_port_id).get_width());
+
+  /* Find port and pin ids for the interconnection module */
+  ModulePortId interc_port_id = module_manager.find_module_port(interc_module, interc_port_name); 
+  VTR_ASSERT(true == module_manager.valid_module_port_id(interc_module, interc_port_id));
+  /* Ensure this is an valid pin index */
+  VTR_ASSERT(interc_pin_id < module_manager.module_port(interc_module, interc_port_id).get_width());
+  
+  /* Add net sources and sinks:
+   * For input-to-input connection, net_source is pin_graph_pin, while net_sink is interc pin   
+   * For output-to-output connection, net_source is interc pin, while net_sink is pin_graph pin   
+   */
+  switch (pin2pin_interc_type) {
+  case INPUT2INPUT_INTERC:
+    module_manager.add_module_net_source(pb_module, pin2pin_net, pin_pb_type_module, pin_pb_type_instance, pin_module_port_id, pin_module_pin_id);
+    module_manager.add_module_net_sink(pb_module, pin2pin_net, interc_module, interc_instance, interc_port_id, interc_pin_id);
+    break;
+  case OUTPUT2OUTPUT_INTERC:
+    module_manager.add_module_net_source(pb_module, pin2pin_net, interc_module, interc_instance, interc_port_id, interc_pin_id);
+    module_manager.add_module_net_sink(pb_module, pin2pin_net, pin_pb_type_module, pin_pb_type_instance, pin_module_port_id, pin_module_pin_id);
+    break;
+  default:
+    VTR_LOG_ERROR("Invalid pin-to-pin interconnection type!\n");
+    exit(1);
+  }
+}
+
+/********************************************************************
+ * We check output_pins of cur_pb_graph_node and its the input_edges
+ * Built the interconnections between outputs of cur_pb_graph_node and outputs of child_pb_graph_node
+ *   src_pb_graph_node.[in|out]_pins -----------------> des_pb_graph_node.[in|out]pins
+ *                                        /|\
+ *                                         |
+ *                         input_pins,   edges,       output_pins
+ *
+ * This function does the following task:
+ * 1. identify pin interconnection type, 
+ * 2. Identify the number of fan-in (Consider interconnection edges of only selected mode)
+ * 3. Add mux/direct connection as a child module to pb_module
+ * 4. Add nets related to the mux/direction 
+ *******************************************************************/
+static 
+void add_module_pb_graph_pin_interc(ModuleManager& module_manager,
+                                    const ModuleId& pb_module,
+                                    std::vector<ModuleId>& memory_modules,
+                                    std::vector<size_t>& memory_instances,
+                                    const VprDeviceAnnotation& device_annotation,
+                                    const CircuitLibrary& circuit_lib,
+                                    t_pb_graph_pin* des_pb_graph_pin,
+                                    t_mode* physical_mode) {
+  /* Find the number of fan-in and detailed interconnection information 
+   * related to the destination pb_graph_pin 
+   */
+  t_interconnect* cur_interc = pb_graph_pin_interc(des_pb_graph_pin, physical_mode);
+  size_t fan_in = pb_graph_pin_inputs(des_pb_graph_pin, cur_interc).size();
+  
+  /* If no interconnection is needed, we can return early */
+  if ((nullptr == cur_interc) || (0 == fan_in)) { 
+    return;
+  }
+
+  /* Initialize the interconnection type that will be physically implemented in module */
+  enum e_interconnect interc_type = device_annotation.interconnect_physical_type(cur_interc);
+  const CircuitModelId& interc_circuit_model = device_annotation.interconnect_circuit_model(cur_interc);
+
+  /* Find input ports of the wire module */
+  std::vector<CircuitPortId> interc_model_inputs = circuit_lib.model_ports_by_type(interc_circuit_model, CIRCUIT_MODEL_PORT_INPUT, true); /* the last argument to guarantee that we ignore any global inputs */
+  /* Find output ports of the wire module */
+  std::vector<CircuitPortId> interc_model_outputs = circuit_lib.model_ports_by_type(interc_circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true); /* the last argument to guarantee that we ignore any global ports */
+
+  /* Ensure that we have only 1 input port and 1 output port, this is valid for both wire and MUX */
+  VTR_ASSERT(1 == interc_model_inputs.size());
+  VTR_ASSERT(1 == interc_model_outputs.size());
+
+  /* Branch on the type of physical implementation,
+   * We add instances of programmable interconnection 
+   */ 
+  switch (interc_type) {
+  case DIRECT_INTERC: {
+    /* Ensure direct interc has only one fan-in */
+    VTR_ASSERT(1 == fan_in);
+
+    /* For more than one mode defined, the direct interc has more than one input_edge ,
+     * We need to find which edge is connected the pin we want
+     */
+    t_pb_graph_pin* src_pb_graph_pin = pb_graph_pin_inputs(des_pb_graph_pin, cur_interc)[0];
+
+    /* Ensure that circuit model is a wire */ 
+    VTR_ASSERT(CIRCUIT_MODEL_WIRE == circuit_lib.model_type(interc_circuit_model));
+    /* Find the wire module in the module manager */
+    ModuleId wire_module = module_manager.find_module(circuit_lib.model_name(interc_circuit_model));
+    VTR_ASSERT(true == module_manager.valid_module_id(wire_module));
+    /* Get the instance id and add an instance of wire */
+    size_t wire_instance = module_manager.num_instance(pb_module, wire_module);
+    module_manager.add_child_module(pb_module, wire_module);
+
+    /* Ensure input and output ports of the wire model has only 1 pin respectively */
+    VTR_ASSERT(1 == circuit_lib.port_size(interc_model_inputs[0]));
+    VTR_ASSERT(1 == circuit_lib.port_size(interc_model_outputs[0]));
+
+    /* Add nets to connect the wires to ports of pb_module */
+    /* First net is to connect input of src_pb_graph_node to input of the wire module */ 
+    add_module_pb_graph_pin2pin_net(module_manager, pb_module, 
+                                    wire_module, wire_instance, 
+                                    circuit_lib.port_prefix(interc_model_inputs[0]),
+                                    0, /* wire input port has only 1 pin */
+                                    src_pb_graph_pin, 
+                                    INPUT2INPUT_INTERC);
+
+    /* Second net is to connect output of the wire module to output of des_pb_graph_pin */ 
+    add_module_pb_graph_pin2pin_net(module_manager, pb_module, 
+                                    wire_module, wire_instance, 
+                                    circuit_lib.port_prefix(interc_model_outputs[0]),
+                                    0, /* wire output port has only 1 pin */
+                                    des_pb_graph_pin, 
+                                    OUTPUT2OUTPUT_INTERC);
+    break;
+  }
+  case COMPLETE_INTERC:
+  case MUX_INTERC: {
+    /* Check: MUX should have at least 2 fan_in */
+    VTR_ASSERT((2 == fan_in)||(2 < fan_in));
+    /* Ensure that circuit model is a MUX */ 
+    VTR_ASSERT(CIRCUIT_MODEL_MUX == circuit_lib.model_type(interc_circuit_model));
+    /* Find the wire module in the module manager */
+    ModuleId mux_module = module_manager.find_module(generate_mux_subckt_name(circuit_lib, interc_circuit_model, fan_in, std::string()));
+    VTR_ASSERT(true == module_manager.valid_module_id(mux_module));
+
+    /* Instanciate the MUX */
+    size_t mux_instance = module_manager.num_instance(pb_module, mux_module);
+    module_manager.add_child_module(pb_module, mux_module);
+    /* Give an instance name: this name should be consistent with the block name given in SDC generator,
+     * If you want to bind the SDC generation to modules
+     */
+    std::string mux_instance_name = generate_pb_mux_instance_name(GRID_MUX_INSTANCE_PREFIX, des_pb_graph_pin, std::string(""));
+    module_manager.set_child_instance_name(pb_module, mux_module, mux_instance, mux_instance_name);
+
+    /* Instanciate a memory module for the MUX */
+    std::string mux_mem_module_name = generate_mux_subckt_name(circuit_lib, 
+                                                               interc_circuit_model, 
+                                                               fan_in, 
+                                                               std::string(MEMORY_MODULE_POSTFIX));
+    ModuleId mux_mem_module = module_manager.find_module(mux_mem_module_name);
+    VTR_ASSERT(true == module_manager.valid_module_id(mux_mem_module));
+    size_t mux_mem_instance = module_manager.num_instance(pb_module, mux_mem_module);
+    module_manager.add_child_module(pb_module, mux_mem_module);
+    /* Give an instance name: this name should be consistent with the block name given in bitstream manager,
+     * If you want to bind the bitstream generation to modules
+     */
+    std::string mux_mem_instance_name = generate_pb_memory_instance_name(GRID_MEM_INSTANCE_PREFIX, des_pb_graph_pin, std::string(""));
+    module_manager.set_child_instance_name(pb_module, mux_mem_module, mux_mem_instance, mux_mem_instance_name);
+    /* Add this MUX as a configurable child to the pb_module */
+    module_manager.add_configurable_child(pb_module, mux_mem_module, mux_mem_instance);
+
+    /* Add nets to connect SRAM ports of the MUX to the SRAM port of memory module */
+    add_module_nets_between_logic_and_memory_sram_bus(module_manager, pb_module, 
+                                                      mux_module, mux_instance,
+                                                      mux_mem_module, mux_mem_instance,
+                                                      circuit_lib, interc_circuit_model);
+
+    /* Update memory modules and memory instance list */
+    memory_modules.push_back(mux_mem_module);
+    memory_instances.push_back(mux_mem_instance);
+
+    /* Ensure output port of the MUX model has only 1 pin, 
+     * while the input port size is dependent on the architecture conext, 
+     * no constaints on the circuit model definition 
+     */
+    VTR_ASSERT(1 == circuit_lib.port_size(interc_model_outputs[0]));
+
+    /* Create nets to wire between the MUX and PB module */
+    /* Add a net to wire the inputs of the multiplexer to its source pb_graph_pin inside pb_module 
+     * Here is a tricky part. 
+     * Not every input edges from the destination pb_graph_pin is used in the physical_model of pb_type
+     * So, we will skip these input edges when building nets 
+     */
+    size_t mux_input_pin_id = 0;
+    for (t_pb_graph_pin* src_pb_graph_pin : pb_graph_pin_inputs(des_pb_graph_pin, cur_interc)) {
+      /* Add a net, set its source and sink */
+      add_module_pb_graph_pin2pin_net(module_manager, pb_module, 
+                                      mux_module, mux_instance, 
+                                      circuit_lib.port_prefix(interc_model_inputs[0]),
+                                      mux_input_pin_id,
+                                      src_pb_graph_pin, 
+                                      INPUT2INPUT_INTERC);
+      mux_input_pin_id++;
+    }
+    /* Ensure all the fan_in has been covered */
+    VTR_ASSERT(mux_input_pin_id == fan_in);
+
+    /* Add a net to wire the output of the multiplexer to des_pb_graph_pin */
+    add_module_pb_graph_pin2pin_net(module_manager, pb_module, 
+                                    mux_module, mux_instance, 
+                                    circuit_lib.port_prefix(interc_model_outputs[0]),
+                                    0, /* MUX should have only 1 pin in its output port */
+                                    des_pb_graph_pin, 
+                                    OUTPUT2OUTPUT_INTERC);
+    break;
+  }
+  default:
+    VTR_LOG_ERROR("Invalid interconnection type for %s [at Architecture XML LINE%d]!\n",
+                  cur_interc->name, cur_interc->line_num);
+    exit(1);
+  }
+}
+
+/********************************************************************
+ * Add modules and nets for programmable/non-programmable interconnections 
+ * which end to a port of pb_module
+ * This function will add the following elements to a module
+ * 1. Instances of direct connections
+ * 2. Instances of programmable routing multiplexers
+ * 3. nets to connect direct connections/multiplexer 
+ *
+ *  +-----------------------------------------+
+ *  |                                        
+ *  |    +--------------+    +------------+
+ *  |--->|              |--->|            |
+ *  |... | Multiplexers |... |            |
+ *  |--->|              |--->|            |
+ *  |    +--------------+    |   des_pb_  | 
+ *  |                        | graph_node |                      
+ *  |    +--------------+    |            |
+ *  |--->|              |--->|            |
+ *  | ...|    Direct    |... |            |
+ *  |--->|  Connections |--->|            |
+ *  |    +--------------+    +------------+
+ *  |                                        
+ *  +----------------------------------------+
+
+ *
+ *  Note: this function should be run after ALL the child pb_modules
+ *  have been added to the pb_module and ALL the ports defined 
+ *  in pb_type have been added to the pb_module!!!
+ *
+ ********************************************************************/
+static 
+void add_module_pb_graph_port_interc(ModuleManager& module_manager,
+                                     const ModuleId& pb_module,
+                                     std::vector<ModuleId>& memory_modules,
+                                     std::vector<size_t>& memory_instances,
+                                     const VprDeviceAnnotation& device_annotation,
+                                     const CircuitLibrary& circuit_lib,
+                                     t_pb_graph_node* des_pb_graph_node,
+                                     const e_circuit_pb_port_type& pb_port_type,
+                                     t_mode* physical_mode) {
+  switch (pb_port_type) {
+  case CIRCUIT_PB_PORT_INPUT: {
+    for (int iport = 0; iport < des_pb_graph_node->num_input_ports; ++iport) {
+      for (int ipin = 0; ipin < des_pb_graph_node->num_input_pins[iport]; ++ipin) {
+        /* Get the selected edge of current pin*/
+        add_module_pb_graph_pin_interc(module_manager, pb_module,
+                                       memory_modules, memory_instances,
+                                       device_annotation,
+                                       circuit_lib,
+                                       &(des_pb_graph_node->input_pins[iport][ipin]),
+                                       physical_mode);
+      }
+    }
+    break;
+  }
+  case CIRCUIT_PB_PORT_OUTPUT: {
+    for (int iport = 0; iport < des_pb_graph_node->num_output_ports; ++iport) {
+      for (int ipin = 0; ipin < des_pb_graph_node->num_output_pins[iport]; ++ipin) {
+        add_module_pb_graph_pin_interc(module_manager, pb_module,
+                                       memory_modules, memory_instances,
+                                       device_annotation,
+                                       circuit_lib,
+                                       &(des_pb_graph_node->output_pins[iport][ipin]),
+                                       physical_mode);
+      }
+    }
+    break;
+  }
+  case CIRCUIT_PB_PORT_CLOCK: {
+    for (int iport = 0; iport < des_pb_graph_node->num_clock_ports; ++iport) {
+      for (int ipin = 0; ipin < des_pb_graph_node->num_clock_pins[iport]; ++ipin) {
+        add_module_pb_graph_pin_interc(module_manager, pb_module,
+                                       memory_modules, memory_instances,
+                                       device_annotation,
+                                       circuit_lib,
+                                       &(des_pb_graph_node->clock_pins[iport][ipin]),
+                                       physical_mode);
+      }
+    }
+    break;
+  }
+  default:
+    VTR_LOG_ERROR("Invalid pb port type!\n");
+    exit(1);
+  }
+}
+
+/********************************************************************
+ * TODO: 
+ * Add modules and nets for programmable/non-programmable interconnections 
+ * inside a module of pb_type
+ * This function will add the following elements to a module
+ * 1. Instances of direct connections
+ * 2. Instances of programmable routing multiplexers
+ * 3. nets to connect direct connections/multiplexer 
+ *
+ *   Pb_module
+ *  +--------------------------------------------------------------+
+ *  |                                                              |
+ *  |    +--------------+    +------------+    +--------------+    |
+ *  |--->|              |--->|            |--->|              |--->|
+ *  |... | Multiplexers |... |            |... | Multiplexers |... |
+ *  |--->|              |--->|            |--->|              |--->|
+ *  |    +--------------+    |   Child    |    +--------------+    |
+ *  |                        | Pb_modules |                        |
+ *  |    +--------------+    |            |    +--------------+    |
+ *  |--->|              |--->|            |--->|              |--->|
+ *  | ...|    Direct    |... |            |... |    Direct    |... |
+ *  |--->|  Connections |--->|            |--->|  Connections |--->|
+ *  |    +--------------+    +------------+    +--------------+    |
+ *  |                                                              |
+ *  +--------------------------------------------------------------+
+ *
+ *  Note: this function should be run after ALL the child pb_modules
+ *  have been added to the pb_module and ALL the ports defined 
+ *  in pb_type have been added to the pb_module!!!
+ *
+ ********************************************************************/
+static 
+void add_module_pb_graph_interc(ModuleManager& module_manager,
+                                const ModuleId& pb_module,
+                                std::vector<ModuleId>& memory_modules,
+                                std::vector<size_t>& memory_instances,
+                                const VprDeviceAnnotation& device_annotation,
+                                const CircuitLibrary& circuit_lib,
+                                t_pb_graph_node* physical_pb_graph_node,
+                                const int& physical_mode_index) {
+  /* Check cur_pb_graph_node*/
+  VTR_ASSERT(nullptr != physical_pb_graph_node);
+  
+  /* Assign physical mode */
+  t_mode* physical_mode = &(physical_pb_graph_node->pb_type->modes[physical_mode_index]);
+
+  /* We check output_pins of cur_pb_graph_node and its the input_edges
+   * Built the interconnections between outputs of cur_pb_graph_node and outputs of child_pb_graph_node
+   *   child_pb_graph_node.output_pins -----------------> cur_pb_graph_node.outpins
+   *                                        /|\
+   *                                         |
+   *                         input_pins,   edges,       output_pins
+   */ 
+  add_module_pb_graph_port_interc(module_manager, pb_module,
+                                  memory_modules, memory_instances,
+                                  device_annotation, 
+                                  circuit_lib, 
+                                  physical_pb_graph_node, 
+                                  CIRCUIT_PB_PORT_OUTPUT,
+                                  physical_mode);
+  
+  /* We check input_pins of child_pb_graph_node and its the input_edges
+   * Built the interconnections between inputs of cur_pb_graph_node and inputs of child_pb_graph_node
+   *   cur_pb_graph_node.input_pins -----------------> child_pb_graph_node.input_pins
+   *                                        /|\
+   *                                         |
+   *                         input_pins,   edges,       output_pins
+   */ 
+  for (int child = 0; child < physical_pb_graph_node->pb_type->modes[physical_mode_index].num_pb_type_children; ++child) {
+    for (int inst = 0; inst < physical_pb_graph_node->pb_type->modes[physical_mode_index].pb_type_children[child].num_pb; ++inst) {
+      t_pb_graph_node* child_pb_graph_node = &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode_index][child][inst]);
+      /* For each child_pb_graph_node input pins*/
+      add_module_pb_graph_port_interc(module_manager, pb_module,
+                                      memory_modules, memory_instances,
+                                      device_annotation, 
+                                      circuit_lib, 
+                                      child_pb_graph_node, 
+                                      CIRCUIT_PB_PORT_INPUT,
+                                      physical_mode);
+
+      /* For each child_pb_graph_node clock pins*/
+      add_module_pb_graph_port_interc(module_manager, pb_module,
+                                      memory_modules, memory_instances,
+                                      device_annotation, 
+                                      circuit_lib, 
+                                      child_pb_graph_node, 
+                                      CIRCUIT_PB_PORT_CLOCK,
+                                      physical_mode);
+    }
+  }
+}
+
+/********************************************************************
+ * Print Verilog modules of physical blocks inside a grid (CLB, I/O. etc.)
+ * This function will traverse the graph of complex logic block (t_pb_graph_node)
+ * in a recursive way, using a Depth First Search (DFS) algorithm.
+ * As such, primitive physical blocks (LUTs, FFs, etc.), leaf node of the pb_graph
+ * will be printed out first, while the top-level will be printed out in the last
+ *
+ * Note: this function will print a unique Verilog module for each type of 
+ * t_pb_graph_node, i.e., t_pb_type, in the graph, in order to enable highly 
+ * hierarchical Verilog organization as well as simplify the Verilog file sizes.
+ *
+ * Note: DFS is the right way. Do NOT use BFS.
+ * DFS can guarantee that all the sub-modules can be registered properly
+ * to its parent in module manager  
+ *******************************************************************/
+static 
+void rec_build_logical_tile_modules(ModuleManager& module_manager,
+                                    const VprDeviceAnnotation& device_annotation,
+                                    const CircuitLibrary& circuit_lib,
+                                    const MuxLibrary& mux_lib,
+                                    const e_config_protocol_type& sram_orgz_type,
+                                    const CircuitModelId& sram_model,
+                                    t_pb_graph_node* physical_pb_graph_node) {
+  /* Check cur_pb_graph_node*/
+  VTR_ASSERT(nullptr != physical_pb_graph_node);
+
+  /* Get the pb_type definition related to the node */
+  t_pb_type* physical_pb_type = physical_pb_graph_node->pb_type; 
+
+  /* Find the mode that physical implementation of a pb_type */
+  t_mode* physical_mode = device_annotation.physical_mode(physical_pb_type);
+
+  /* For non-leaf node in the pb_type graph: 
+   * Recursively Depth-First Generate all the child pb_type at the level 
+   */
+  if (false == is_primitive_pb_type(physical_pb_type)) { 
+    for (int ipb = 0; ipb < physical_mode->num_pb_type_children; ++ipb) {
+      /* Go recursive to visit the children */
+      rec_build_logical_tile_modules(module_manager, device_annotation,
+                                     circuit_lib, mux_lib, 
+                                     sram_orgz_type, sram_model, 
+                                     &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb][0]));
+    }
+  }
+
+  /* For leaf node, a primitive Verilog module will be generated */
+  if (true == is_primitive_pb_type(physical_pb_type)) { 
+    build_primitive_block_module(module_manager, device_annotation,
+                                 circuit_lib,
+                                 sram_orgz_type, sram_model, 
+                                 physical_pb_graph_node); 
+    /* Finish for primitive node, return */
+    return;
+  }
+
+  /* Generate the name of the Verilog module for this pb_type */
+  std::string pb_module_name = generate_physical_block_module_name(physical_pb_type);
+
+  /* Register the Verilog module in module manager */
+  ModuleId pb_module = module_manager.add_module(pb_module_name);
+  VTR_ASSERT(true == module_manager.valid_module_id(pb_module));
+
+  /* Add ports to the Verilog module */
+  add_pb_type_ports_to_module_manager(module_manager, pb_module, physical_pb_type); 
+
+  /* Vectors to record all the memory modules have been added
+   * They are used to add module nets of configuration bus
+   */
+  std::vector<ModuleId> memory_modules;
+  std::vector<size_t> memory_instances;
+
+  /* Add all the child Verilog modules as instances */
+  for (int ichild = 0; ichild < physical_mode->num_pb_type_children; ++ichild) {
+    /* Get the name and module id for this child pb_type */
+    std::string child_pb_module_name = generate_physical_block_module_name(&(physical_mode->pb_type_children[ichild]));
+    ModuleId child_pb_module = module_manager.find_module(child_pb_module_name);
+    /* We must have one valid id! */
+    VTR_ASSERT(true == module_manager.valid_module_id(child_pb_module));
+
+    /* Each child may exist multiple times in the hierarchy*/
+    for (int inst = 0; inst < physical_mode->pb_type_children[ichild].num_pb; ++inst) {
+      size_t child_instance_id = module_manager.num_instance(pb_module, child_pb_module); 
+      /* Ensure the instance of this child module is the same as placement index,
+       * This check is necessary because placement_index is used to identify instance id for children 
+       * when adding local interconnection for this pb_type 
+       */
+      VTR_ASSERT(child_instance_id == (size_t)physical_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ichild][inst].placement_index);
+
+      /* Add the memory module as a child of primitive module */
+      module_manager.add_child_module(pb_module, child_pb_module); 
+
+      /* Set an instance name to bind to a block in bitstream generation and SDC generation! */
+      std::string child_pb_instance_name = generate_physical_block_instance_name(&(physical_pb_type->modes[physical_mode->index].pb_type_children[ichild]), inst);
+      module_manager.set_child_instance_name(pb_module, child_pb_module, child_instance_id, child_pb_instance_name);
+
+      /* Identify if this sub module includes configuration bits, 
+       * we will update the memory module and instance list
+       */
+      if (0 < find_module_num_config_bits(module_manager, child_pb_module,
+                                          circuit_lib, sram_model, 
+                                          sram_orgz_type)) {
+        module_manager.add_configurable_child(pb_module, child_pb_module, child_instance_id);
+      }
+    }
+  }
+
+  /* Add modules and nets for programmable/non-programmable interconnections 
+   * inside the Verilog module 
+   */
+  add_module_pb_graph_interc(module_manager, pb_module,
+                             memory_modules, memory_instances,
+                             device_annotation,
+                             circuit_lib, physical_pb_graph_node,
+                             physical_mode->index);
+
+  /* Add global ports to the pb_module:
+   * This is a much easier job after adding sub modules (instances), 
+   * we just need to find all the global ports from the child modules and build a list of it
+   */
+  add_module_global_ports_from_child_modules(module_manager, pb_module);
+
+  /* Count GPIO ports from the sub-modules under this Verilog module 
+   * This is a much easier job after adding sub modules (instances), 
+   * we just need to find all the I/O ports from the child modules and build a list of it
+   */
+  add_module_gpio_ports_from_child_modules(module_manager, pb_module);
+
+  /* Count shared SRAM ports from the sub-modules under this Verilog module
+   * This is a much easier job after adding sub modules (instances), 
+   * we just need to find all the I/O ports from the child modules and build a list of it
+   */
+  size_t module_num_shared_config_bits = find_module_num_shared_config_bits_from_child_modules(module_manager, pb_module); 
+  if (0 < module_num_shared_config_bits) {
+    add_reserved_sram_ports_to_module_manager(module_manager, pb_module, module_num_shared_config_bits);
+  }
+
+  /* Count SRAM ports from the sub-modules under this Verilog module
+   * This is a much easier job after adding sub modules (instances), 
+   * we just need to find all the I/O ports from the child modules and build a list of it
+   */
+  size_t module_num_config_bits = find_module_num_config_bits_from_child_modules(module_manager, pb_module, circuit_lib, sram_model, sram_orgz_type); 
+  if (0 < module_num_config_bits) {
+    add_sram_ports_to_module_manager(module_manager, pb_module, circuit_lib, sram_model, sram_orgz_type, module_num_config_bits);
+  }
+
+  /* Add module nets to connect memory cells inside
+   * This is a one-shot addition that covers all the memory modules in this pb module!
+   */
+  if (false == memory_modules.empty()) {
+    add_module_nets_memory_config_bus(module_manager, pb_module, 
+                                      sram_orgz_type, circuit_lib.design_tech_type(sram_model));
+  }
+}
+
+/*****************************************************************************
+ * This function will create a Verilog file and print out a Verilog netlist 
+ * for a type of physical block 
+ *
+ * For IO blocks: 
+ * The param 'border_side' is required, which is specify which side of fabric
+ * the I/O block locates at.
+ *****************************************************************************/
+static 
+void build_physical_tile_module(ModuleManager& module_manager,
+                                const CircuitLibrary& circuit_lib,
+                                const e_config_protocol_type& sram_orgz_type,
+                                const CircuitModelId& sram_model,
+                                t_physical_tile_type_ptr phy_block_type,
+                                const e_side& border_side,
+                                const bool& duplicate_grid_pin) {
+  /* Check code: if this is an IO block, the border side MUST be valid */
+  if (true == is_io_type(phy_block_type)) {
+    VTR_ASSERT(NUM_SIDES != border_side);
+  }
+
+  /* Create a Module for the top-level physical block, and add to module manager */
+  std::string grid_module_name = generate_grid_block_module_name(std::string(GRID_MODULE_NAME_PREFIX), 
+                                                                 std::string(phy_block_type->name),
+                                                                 is_io_type(phy_block_type),
+                                                                 border_side);
+  ModuleId grid_module = module_manager.add_module(grid_module_name); 
+  VTR_ASSERT(true == module_manager.valid_module_id(grid_module));
+
+  /* Now each physical tile may have a number of diffrent logical blocks
+   * We assume the following organization:
+   *     
+   *    Physical tile
+   *    +----------------------- 
+   *    |
+   *    |   pb_typeA[0] - from equivalent site[A]
+   *    |   +--------------------
+   *    |   |
+   *    |   +--------------------
+   *    |
+   *    |   pb_typeB[0] - from equivalent site[B] 
+   *    |   +--------------------
+   *    |   |
+   *    |   +--------------------
+   *   ...           ...
+   *    |   pb_typeA[capacity - 1] - from equivalent site[A]
+   *    |   +--------------------
+   *    |   |
+   *    |   +--------------------
+   *    |
+   *    |   pb_typeB[capacity - 1] - from equivalent site[B] 
+   *    |   +--------------------
+   *    |   |
+   *    |   +--------------------
+   *    | 
+   *    +----------------------- 
+   */
+  for (int iz = 0; iz < phy_block_type->capacity; ++iz) {
+    for (t_logical_block_type_ptr lb_type : phy_block_type->equivalent_sites) {
+      /* Bypass empty pb_graph */
+      if (nullptr == lb_type->pb_graph_head) {
+        continue;
+      }
+      std::string pb_module_name = generate_physical_block_module_name(lb_type->pb_graph_head->pb_type);
+      ModuleId pb_module = module_manager.find_module(pb_module_name);
+      VTR_ASSERT(true == module_manager.valid_module_id(pb_module));
+
+      /* Add all the sub modules */
+      size_t pb_instance_id = module_manager.num_instance(grid_module, pb_module);
+      module_manager.add_child_module(grid_module, pb_module);
+
+      /* Give the child module with a unique instance name */
+      std::string instance_name = generate_physical_block_instance_name(lb_type->pb_graph_head->pb_type, iz);
+      /* Set an instance name to bind to a block in bitstream generation */
+      module_manager.set_child_instance_name(grid_module, pb_module, pb_instance_id, instance_name);
+
+      /* Identify if this sub module includes configuration bits, 
+       * we will update the memory module and instance list
+       */
+      if (0 < find_module_num_config_bits(module_manager, pb_module,
+                                          circuit_lib, sram_model, 
+                                          sram_orgz_type)) {
+        module_manager.add_configurable_child(grid_module, pb_module, pb_instance_id);
+      }
+    }
+  }
+
+  /* Add grid ports(pins) to the module */
+  if (false == duplicate_grid_pin) {
+    /* Default way to add these ports by following the definition in pb_types */
+    add_grid_module_pb_type_ports(module_manager, grid_module,
+                                  phy_block_type, border_side);
+    /* Add module nets to connect the pb_type ports to sub modules */
+    for (t_logical_block_type_ptr lb_type : phy_block_type->equivalent_sites) {
+      /* Bypass empty pb_graph */
+      if (nullptr == lb_type->pb_graph_head) {
+        continue;
+      }
+      std::string pb_module_name = generate_physical_block_module_name(lb_type->pb_graph_head->pb_type);
+      ModuleId pb_module = module_manager.find_module(pb_module_name);
+      VTR_ASSERT(true == module_manager.valid_module_id(pb_module));
+      for (const size_t& child_instance : module_manager.child_module_instances(grid_module, pb_module)) {
+        add_grid_module_nets_connect_pb_type_ports(module_manager, grid_module,
+                                                   pb_module, child_instance,
+                                                   phy_block_type, border_side);
+      }
+    }
+  } else {
+    VTR_ASSERT_SAFE(true == duplicate_grid_pin);
+    /* Add these ports with duplication */
+    add_grid_module_duplicated_pb_type_ports(module_manager, grid_module,
+                                             phy_block_type, border_side);
+    
+    /* Add module nets to connect the duplicated pb_type ports to sub modules */
+    for (t_logical_block_type_ptr lb_type : phy_block_type->equivalent_sites) {
+      /* Bypass empty pb_graph */
+      if (nullptr == lb_type->pb_graph_head) {
+        continue;
+      }
+      std::string pb_module_name = generate_physical_block_module_name(lb_type->pb_graph_head->pb_type);
+      ModuleId pb_module = module_manager.find_module(pb_module_name);
+      VTR_ASSERT(true == module_manager.valid_module_id(pb_module));
+      for (const size_t& child_instance : module_manager.child_module_instances(grid_module, pb_module)) {
+        add_grid_module_nets_connect_duplicated_pb_type_ports(module_manager, grid_module,
+                                                              pb_module, child_instance,
+                                                              phy_block_type, border_side);
+      }
+    }
+  }
+
+  /* Add global ports to the pb_module:
+   * This is a much easier job after adding sub modules (instances), 
+   * we just need to find all the global ports from the child modules and build a list of it
+   */
+  add_module_global_ports_from_child_modules(module_manager, grid_module);
+
+  /* Count GPIO ports from the sub-modules under this Verilog module 
+   * This is a much easier job after adding sub modules (instances), 
+   * we just need to find all the I/O ports from the child modules and build a list of it
+   */
+  add_module_gpio_ports_from_child_modules(module_manager, grid_module);
+
+  /* Count shared SRAM ports from the sub-modules under this Verilog module
+   * This is a much easier job after adding sub modules (instances), 
+   * we just need to find all the I/O ports from the child modules and build a list of it
+   */
+  size_t module_num_shared_config_bits = find_module_num_shared_config_bits_from_child_modules(module_manager, grid_module); 
+  if (0 < module_num_shared_config_bits) {
+    add_reserved_sram_ports_to_module_manager(module_manager, grid_module, module_num_shared_config_bits);
+  }
+
+  /* Count SRAM ports from the sub-modules under this Verilog module
+   * This is a much easier job after adding sub modules (instances), 
+   * we just need to find all the I/O ports from the child modules and build a list of it
+   */
+  size_t module_num_config_bits = find_module_num_config_bits_from_child_modules(module_manager, grid_module, circuit_lib, sram_model, sram_orgz_type); 
+  if (0 < module_num_config_bits) {
+    add_sram_ports_to_module_manager(module_manager, grid_module, circuit_lib, sram_model, sram_orgz_type, module_num_config_bits);
+  }
+
+  /* Add module nets to connect memory cells inside
+   * This is a one-shot addition that covers all the memory modules in this pb module!
+   */
+  if (0 < module_manager.configurable_children(grid_module).size()) {
+    add_module_nets_memory_config_bus(module_manager, grid_module, 
+                                      sram_orgz_type, circuit_lib.design_tech_type(sram_model));
+  }
+}
+
+/*****************************************************************************
+ * Create logic block modules in a compact way
+ * This function will achieve this goal in two step:
+ * - Build the modules for each logical tile which is based on pb_graph
+ *   Note that there the pin/port does not carry any fixed physical location
+ * - Build the modules for each physical tile which is based on physical_tile_type_ptr
+ *   Here, multiple logical tiles can be considered and each port/pin has a fixed
+ *   physical location. This is where the feature of duplicate_pin_pin will be applied
+ *   - Only one module for each I/O on each border side (IO_TYPE)
+ *   - Only one module for each CLB (FILL_TYPE)
+ *   - Only one module for each heterogeneous block
+ ****************************************************************************/
+void build_grid_modules(ModuleManager& module_manager,
+                        const DeviceContext& device_ctx,
+                        const VprDeviceAnnotation& device_annotation,
+                        const CircuitLibrary& circuit_lib,
+                        const MuxLibrary& mux_lib,
+                        const e_config_protocol_type& sram_orgz_type,
+                        const CircuitModelId& sram_model,
+                        const bool& duplicate_grid_pin) {
+  /* Start time count */
+  vtr::ScopedStartFinishTimer timer("Build grid modules");
+
+  /* Enumerate the types of logical tiles, and build a module for each 
+   * Build modules for all the pb_types/pb_graph_nodes
+   * use a Depth-First Search Algorithm to print the sub-modules 
+   * Note: DFS is the right way. Do NOT use BFS.
+   * DFS can guarantee that all the sub-modules can be registered properly
+   * to its parent in module manager  
+   */
+  /* Build modules starting from the top-level pb_type/pb_graph_node, and traverse the graph in a recursive way */
+  for (const t_logical_block_type& logical_tile : device_ctx.logical_block_types) {
+    /* Bypass empty pb_graph */
+    if (nullptr == logical_tile.pb_graph_head) {
+      continue;
+    }
+    rec_build_logical_tile_modules(module_manager, device_annotation,
+                                   circuit_lib, mux_lib, 
+                                   sram_orgz_type, sram_model, 
+                                   logical_tile.pb_graph_head);
+  }
+
+  /* Enumerate the types of physical tiles
+   * Use the logical tile module to build the physical tiles
+   */
+  for (const t_physical_tile_type& physical_tile : device_ctx.physical_tile_types) {
+    /* Bypass empty type or nullptr */
+    if (true == is_empty_type(&physical_tile)) {
+      continue;
+    } else if (true == is_io_type(&physical_tile)) {
+      /* Special for I/O block, generate one module for each border side */
+      for (int iside = 0; iside < NUM_SIDES; iside++) {
+        SideManager side_manager(iside);
+        build_physical_tile_module(module_manager, circuit_lib,
+                                   sram_orgz_type, sram_model,
+                                   &physical_tile,
+                                   side_manager.get_side(),
+                                   duplicate_grid_pin);
+      } 
+      continue;
+    } else {
+      /* For CLB and heterogenenous blocks */
+      build_physical_tile_module(module_manager, circuit_lib,
+                                 sram_orgz_type, sram_model,
+                                 &physical_tile,
+                                 NUM_SIDES,
+                                 duplicate_grid_pin);
+    }
+  }
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fabric/build_grid_modules.h b/openfpga/src/fabric/build_grid_modules.h
new file mode 100644
index 000000000..4c02f3783
--- /dev/null
+++ b/openfpga/src/fabric/build_grid_modules.h
@@ -0,0 +1,30 @@
+#ifndef BUILD_GRID_MODULES_H
+#define BUILD_GRID_MODULES_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "vpr_context.h"
+#include "vpr_device_annotation.h"
+#include "module_manager.h"
+#include "mux_library.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void build_grid_modules(ModuleManager& module_manager,
+                        const DeviceContext& device_ctx,
+                        const VprDeviceAnnotation& device_annotation,
+                        const CircuitLibrary& circuit_lib,
+                        const MuxLibrary& mux_lib,
+                        const e_config_protocol_type& sram_orgz_type,
+                        const CircuitModelId& sram_model,
+                        const bool& duplicate_grid_pin);
+
+} /* end namespace openfpga */
+
+#endif

From 89086ed08087e2e148afd282c46d410a2aee9173 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 13 Feb 2020 15:38:26 -0700
Subject: [PATCH 133/645] add verbose output to build grid module

---
 openfpga/src/base/openfpga_build_fabric.cpp |  3 +-
 openfpga/src/fabric/build_device_module.cpp |  5 +-
 openfpga/src/fabric/build_device_module.h   |  3 +-
 openfpga/src/fabric/build_grid_modules.cpp  | 51 +++++++++++++++++----
 openfpga/src/fabric/build_grid_modules.h    |  3 +-
 5 files changed, 51 insertions(+), 14 deletions(-)

diff --git a/openfpga/src/base/openfpga_build_fabric.cpp b/openfpga/src/base/openfpga_build_fabric.cpp
index c15cf548f..879c127d6 100644
--- a/openfpga/src/base/openfpga_build_fabric.cpp
+++ b/openfpga/src/base/openfpga_build_fabric.cpp
@@ -72,7 +72,8 @@ void build_fabric(OpenfpgaContext& openfpga_context,
 
   openfpga_context.mutable_module_graph() = build_device_module_graph(g_vpr_ctx.device(),
                                                                       const_cast<const OpenfpgaContext&>(openfpga_context),
-                                                                      cmd_context.option_enable(cmd, opt_duplicate_grid_pin));
+                                                                      cmd_context.option_enable(cmd, opt_duplicate_grid_pin),
+                                                                      cmd_context.option_enable(cmd, opt_verbose));
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/fabric/build_device_module.cpp b/openfpga/src/fabric/build_device_module.cpp
index d6f759b30..fd7f1f31e 100644
--- a/openfpga/src/fabric/build_device_module.cpp
+++ b/openfpga/src/fabric/build_device_module.cpp
@@ -28,7 +28,8 @@ namespace openfpga {
  *******************************************************************/
 ModuleManager build_device_module_graph(const DeviceContext& vpr_device_ctx,
                                         const OpenfpgaContext& openfpga_ctx,
-                                        const bool& duplicate_grid_pin) {
+                                        const bool& duplicate_grid_pin,
+                                        const bool& verbose) {
   vtr::ScopedStartFinishTimer timer("Build fabric module graph");
 
   /* Module manager to be built */
@@ -73,7 +74,7 @@ ModuleManager build_device_module_graph(const DeviceContext& vpr_device_ctx,
                      openfpga_ctx.arch().circuit_lib,
                      openfpga_ctx.mux_lib(),
                      openfpga_ctx.arch().config_protocol.type(),
-                     sram_model, duplicate_grid_pin);
+                     sram_model, duplicate_grid_pin, verbose);
 
   //if (TRUE == vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy) {
   //  build_unique_routing_modules(module_manager, L_device_rr_gsb, arch.spice->circuit_lib, 
diff --git a/openfpga/src/fabric/build_device_module.h b/openfpga/src/fabric/build_device_module.h
index fd646844f..6830ca82b 100644
--- a/openfpga/src/fabric/build_device_module.h
+++ b/openfpga/src/fabric/build_device_module.h
@@ -16,7 +16,8 @@ namespace openfpga {
 
 ModuleManager build_device_module_graph(const DeviceContext& vpr_device_ctx,
                                         const OpenfpgaContext& openfpga_ctx,
-                                        const bool& duplicate_grid_pin);
+                                        const bool& duplicate_grid_pin,
+                                        const bool& verbose);
 
 } /* end namespace openfpga */
 
diff --git a/openfpga/src/fabric/build_grid_modules.cpp b/openfpga/src/fabric/build_grid_modules.cpp
index df0a63d03..bbddd4964 100644
--- a/openfpga/src/fabric/build_grid_modules.cpp
+++ b/openfpga/src/fabric/build_grid_modules.cpp
@@ -175,7 +175,8 @@ void build_primitive_block_module(ModuleManager& module_manager,
                                   const CircuitLibrary& circuit_lib,
                                   const e_config_protocol_type& sram_orgz_type,
                                   const CircuitModelId& sram_model,
-                                  t_pb_graph_node* primitive_pb_graph_node) {
+                                  t_pb_graph_node* primitive_pb_graph_node,
+                                  const bool& verbose) {
   /* Ensure a valid pb_graph_node */ 
   VTR_ASSERT(nullptr != primitive_pb_graph_node);
 
@@ -185,6 +186,10 @@ void build_primitive_block_module(ModuleManager& module_manager,
   /* Generate the module name for this primitive pb_graph_node*/
   std::string primitive_module_name = generate_physical_block_module_name(primitive_pb_graph_node->pb_type);
 
+  VTR_LOGV(verbose,
+           "Building module '%s'...",
+           primitive_module_name.c_str());
+
   /* Create a module of the primitive LUT and register it to module manager */
   ModuleId primitive_module = module_manager.add_module(primitive_module_name);
   /* Ensure that the module has been created and thus unique! */
@@ -289,6 +294,8 @@ void build_primitive_block_module(ModuleManager& module_manager,
       }
     }
   }
+
+  VTR_LOGV(verbose, "Done\n");
 }
 
 /********************************************************************
@@ -732,7 +739,8 @@ void rec_build_logical_tile_modules(ModuleManager& module_manager,
                                     const MuxLibrary& mux_lib,
                                     const e_config_protocol_type& sram_orgz_type,
                                     const CircuitModelId& sram_model,
-                                    t_pb_graph_node* physical_pb_graph_node) {
+                                    t_pb_graph_node* physical_pb_graph_node,
+                                    const bool& verbose) {
   /* Check cur_pb_graph_node*/
   VTR_ASSERT(nullptr != physical_pb_graph_node);
 
@@ -751,7 +759,8 @@ void rec_build_logical_tile_modules(ModuleManager& module_manager,
       rec_build_logical_tile_modules(module_manager, device_annotation,
                                      circuit_lib, mux_lib, 
                                      sram_orgz_type, sram_model, 
-                                     &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb][0]));
+                                     &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb][0]),
+                                     verbose);
     }
   }
 
@@ -760,7 +769,8 @@ void rec_build_logical_tile_modules(ModuleManager& module_manager,
     build_primitive_block_module(module_manager, device_annotation,
                                  circuit_lib,
                                  sram_orgz_type, sram_model, 
-                                 physical_pb_graph_node); 
+                                 physical_pb_graph_node,
+                                 verbose); 
     /* Finish for primitive node, return */
     return;
   }
@@ -768,6 +778,10 @@ void rec_build_logical_tile_modules(ModuleManager& module_manager,
   /* Generate the name of the Verilog module for this pb_type */
   std::string pb_module_name = generate_physical_block_module_name(physical_pb_type);
 
+  VTR_LOGV(verbose,
+           "Building module '%s'...",
+           pb_module_name.c_str());
+
   /* Register the Verilog module in module manager */
   ModuleId pb_module = module_manager.add_module(pb_module_name);
   VTR_ASSERT(true == module_manager.valid_module_id(pb_module));
@@ -862,6 +876,8 @@ void rec_build_logical_tile_modules(ModuleManager& module_manager,
     add_module_nets_memory_config_bus(module_manager, pb_module, 
                                       sram_orgz_type, circuit_lib.design_tech_type(sram_model));
   }
+
+  VTR_LOGV(verbose, "Done\n");
 }
 
 /*****************************************************************************
@@ -879,7 +895,8 @@ void build_physical_tile_module(ModuleManager& module_manager,
                                 const CircuitModelId& sram_model,
                                 t_physical_tile_type_ptr phy_block_type,
                                 const e_side& border_side,
-                                const bool& duplicate_grid_pin) {
+                                const bool& duplicate_grid_pin,
+                                const bool& verbose) {
   /* Check code: if this is an IO block, the border side MUST be valid */
   if (true == is_io_type(phy_block_type)) {
     VTR_ASSERT(NUM_SIDES != border_side);
@@ -890,6 +907,10 @@ void build_physical_tile_module(ModuleManager& module_manager,
                                                                  std::string(phy_block_type->name),
                                                                  is_io_type(phy_block_type),
                                                                  border_side);
+  VTR_LOGV(verbose, 
+           "Building physical tile '%s'...",
+           grid_module_name.c_str());
+
   ModuleId grid_module = module_manager.add_module(grid_module_name); 
   VTR_ASSERT(true == module_manager.valid_module_id(grid_module));
 
@@ -1031,6 +1052,8 @@ void build_physical_tile_module(ModuleManager& module_manager,
     add_module_nets_memory_config_bus(module_manager, grid_module, 
                                       sram_orgz_type, circuit_lib.design_tech_type(sram_model));
   }
+
+  VTR_LOG("Done\n");
 }
 
 /*****************************************************************************
@@ -1052,7 +1075,8 @@ void build_grid_modules(ModuleManager& module_manager,
                         const MuxLibrary& mux_lib,
                         const e_config_protocol_type& sram_orgz_type,
                         const CircuitModelId& sram_model,
-                        const bool& duplicate_grid_pin) {
+                        const bool& duplicate_grid_pin,
+                        const bool& verbose) {
   /* Start time count */
   vtr::ScopedStartFinishTimer timer("Build grid modules");
 
@@ -1064,6 +1088,8 @@ void build_grid_modules(ModuleManager& module_manager,
    * to its parent in module manager  
    */
   /* Build modules starting from the top-level pb_type/pb_graph_node, and traverse the graph in a recursive way */
+  VTR_LOG("Building logical tiles...");
+  VTR_LOGV(verbose, "\n");
   for (const t_logical_block_type& logical_tile : device_ctx.logical_block_types) {
     /* Bypass empty pb_graph */
     if (nullptr == logical_tile.pb_graph_head) {
@@ -1072,12 +1098,16 @@ void build_grid_modules(ModuleManager& module_manager,
     rec_build_logical_tile_modules(module_manager, device_annotation,
                                    circuit_lib, mux_lib, 
                                    sram_orgz_type, sram_model, 
-                                   logical_tile.pb_graph_head);
+                                   logical_tile.pb_graph_head,
+                                   verbose);
   }
+  VTR_LOG("Done\n");
 
   /* Enumerate the types of physical tiles
    * Use the logical tile module to build the physical tiles
    */
+  VTR_LOG("Building physical tiles...");
+  VTR_LOGV(verbose, "\n");
   for (const t_physical_tile_type& physical_tile : device_ctx.physical_tile_types) {
     /* Bypass empty type or nullptr */
     if (true == is_empty_type(&physical_tile)) {
@@ -1090,7 +1120,8 @@ void build_grid_modules(ModuleManager& module_manager,
                                    sram_orgz_type, sram_model,
                                    &physical_tile,
                                    side_manager.get_side(),
-                                   duplicate_grid_pin);
+                                   duplicate_grid_pin,
+                                   verbose);
       } 
       continue;
     } else {
@@ -1099,9 +1130,11 @@ void build_grid_modules(ModuleManager& module_manager,
                                  sram_orgz_type, sram_model,
                                  &physical_tile,
                                  NUM_SIDES,
-                                 duplicate_grid_pin);
+                                 duplicate_grid_pin,
+                                 verbose);
     }
   }
+  VTR_LOG("Done\n");
 }
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/fabric/build_grid_modules.h b/openfpga/src/fabric/build_grid_modules.h
index 4c02f3783..f2a8e967b 100644
--- a/openfpga/src/fabric/build_grid_modules.h
+++ b/openfpga/src/fabric/build_grid_modules.h
@@ -23,7 +23,8 @@ void build_grid_modules(ModuleManager& module_manager,
                         const MuxLibrary& mux_lib,
                         const e_config_protocol_type& sram_orgz_type,
                         const CircuitModelId& sram_model,
-                        const bool& duplicate_grid_pin);
+                        const bool& duplicate_grid_pin,
+                        const bool& verbose);
 
 } /* end namespace openfpga */
 

From cf440f92d3441fd52111c3c9997918ff9b9cbee0 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 13 Feb 2020 16:05:23 -0700
Subject: [PATCH 134/645] put routing module builder util function online

---
 .../src/fabric/build_essential_modules.cpp    |   4 +-
 .../src/fabric/build_grid_module_utils.cpp    |   2 +-
 openfpga/src/fabric/build_grid_modules.cpp    |   6 +-
 openfpga/src/fabric/build_lut_modules.cpp     |   9 +-
 openfpga/src/fabric/build_memory_modules.cpp  |   4 +-
 openfpga/src/fabric/build_mux_modules.cpp     |   6 +-
 .../src/fabric/build_routing_module_utils.cpp | 213 ++++++++++++++++++
 .../src/fabric/build_routing_module_utils.h   |  63 ++++++
 8 files changed, 292 insertions(+), 15 deletions(-)
 create mode 100644 openfpga/src/fabric/build_routing_module_utils.cpp
 create mode 100644 openfpga/src/fabric/build_routing_module_utils.h

diff --git a/openfpga/src/fabric/build_essential_modules.cpp b/openfpga/src/fabric/build_essential_modules.cpp
index a66a52979..e39282f2d 100644
--- a/openfpga/src/fabric/build_essential_modules.cpp
+++ b/openfpga/src/fabric/build_essential_modules.cpp
@@ -52,7 +52,7 @@ void build_invbuf_module(ModuleManager& module_manager,
     }
     /* Report errors if there are any */
     if (0 < num_err) {
-      VTR_LOG_ERROR("Inverter/buffer circuit model '%s' is power-gated. At least one config-enable global port is required!\n",
+      VTR_LOGF_ERROR(__FILE__, __LINE__, "Inverter/buffer circuit model '%s' is power-gated. At least one config-enable global port is required!\n",
                  circuit_lib.model_name(circuit_model).c_str()); 
       exit(1);
     }
@@ -98,7 +98,7 @@ void build_passgate_module(ModuleManager& module_manager,
     }
     break;
   default:
-    VTR_LOG_ERROR("Invalid topology for circuit model '%s'!\n",
+    VTR_LOGF_ERROR(__FILE__, __LINE__, "Invalid topology for circuit model '%s'!\n",
                   circuit_lib.model_name(circuit_model).c_str());
     exit(1);
   }
diff --git a/openfpga/src/fabric/build_grid_module_utils.cpp b/openfpga/src/fabric/build_grid_module_utils.cpp
index 1386e93fe..a61bc5f0a 100644
--- a/openfpga/src/fabric/build_grid_module_utils.cpp
+++ b/openfpga/src/fabric/build_grid_module_utils.cpp
@@ -102,7 +102,7 @@ void add_grid_module_net_connect_pb_graph_pin(ModuleManager& module_manager,
       module_manager.add_module_net_sink(grid_module, net, grid_module, 0, grid_module_port_id, grid_module_pin_id);
       break;
     default:
-      VTR_LOG_ERROR("Invalid pin-to-pin interconnection type!\n");
+      VTR_LOGF_ERROR(__FILE__, __LINE__, "Invalid pin-to-pin interconnection type!\n");
       exit(1);
     }
   }
diff --git a/openfpga/src/fabric/build_grid_modules.cpp b/openfpga/src/fabric/build_grid_modules.cpp
index bbddd4964..fcfbfa0aa 100644
--- a/openfpga/src/fabric/build_grid_modules.cpp
+++ b/openfpga/src/fabric/build_grid_modules.cpp
@@ -354,7 +354,7 @@ void add_module_pb_graph_pin2pin_net(ModuleManager& module_manager,
     module_manager.add_module_net_sink(pb_module, pin2pin_net, pin_pb_type_module, pin_pb_type_instance, pin_module_port_id, pin_module_pin_id);
     break;
   default:
-    VTR_LOG_ERROR("Invalid pin-to-pin interconnection type!\n");
+    VTR_LOGF_ERROR(__FILE__, __LINE__, "Invalid pin-to-pin interconnection type!\n");
     exit(1);
   }
 }
@@ -532,7 +532,7 @@ void add_module_pb_graph_pin_interc(ModuleManager& module_manager,
     break;
   }
   default:
-    VTR_LOG_ERROR("Invalid interconnection type for %s [at Architecture XML LINE%d]!\n",
+    VTR_LOGF_ERROR(__FILE__, __LINE__, "Invalid interconnection type for %s [at Architecture XML LINE%d]!\n",
                   cur_interc->name, cur_interc->line_num);
     exit(1);
   }
@@ -620,7 +620,7 @@ void add_module_pb_graph_port_interc(ModuleManager& module_manager,
     break;
   }
   default:
-    VTR_LOG_ERROR("Invalid pb port type!\n");
+    VTR_LOGF_ERROR(__FILE__, __LINE__, "Invalid pb port type!\n");
     exit(1);
   }
 }
diff --git a/openfpga/src/fabric/build_lut_modules.cpp b/openfpga/src/fabric/build_lut_modules.cpp
index c799fe75a..184de6698 100644
--- a/openfpga/src/fabric/build_lut_modules.cpp
+++ b/openfpga/src/fabric/build_lut_modules.cpp
@@ -265,10 +265,11 @@ void build_lut_module(ModuleManager& module_manager,
   /* Sanitity check */
   if ( true == circuit_lib.is_lut_fracturable(lut_model) ) {
     if (mode_select_port_lsb != circuit_lib.port_size(lut_mode_select_sram_ports[0])) {
-      VTR_LOG_ERROR("(ircuit model '%s' has a unmatched tri-state map '%s' implied by mode_port size='%d'!\n",
-                    circuit_lib.model_name(lut_model).c_str(), 
-                    tri_state_map.c_str(), 
-                    circuit_lib.port_size(lut_mode_select_sram_ports[0])); 
+      VTR_LOGF_ERROR(__FILE__, __LINE__,
+                     "Circuit model '%s' has a unmatched tri-state map '%s' implied by mode_port size='%d'!\n",
+                     circuit_lib.model_name(lut_model).c_str(), 
+                     tri_state_map.c_str(), 
+                     circuit_lib.port_size(lut_mode_select_sram_ports[0])); 
       exit(1);
     }
   }
diff --git a/openfpga/src/fabric/build_memory_modules.cpp b/openfpga/src/fabric/build_memory_modules.cpp
index 26b463377..299bf6d70 100644
--- a/openfpga/src/fabric/build_memory_modules.cpp
+++ b/openfpga/src/fabric/build_memory_modules.cpp
@@ -585,7 +585,7 @@ void build_memory_module(ModuleManager& module_manager,
                              module_name, sram_model, num_mems);
     break;
   default:
-    VTR_LOG_ERROR("Invalid SRAM organization!\n");
+    VTR_LOGF_ERROR(__FILE__, __LINE__, "Invalid SRAM organization!\n");
     exit(1);
   }
 }
@@ -636,7 +636,7 @@ void build_mux_memory_module(ModuleManager& module_manager,
      */ 
     break;
   default:
-    VTR_LOG_ERROR("Invalid design technology of multiplexer '%s'\n",
+    VTR_LOGF_ERROR(__FILE__, __LINE__, "Invalid design technology of multiplexer '%s'\n",
                   circuit_lib.model_name(mux_model).c_str()); 
     exit(1);
   }
diff --git a/openfpga/src/fabric/build_mux_modules.cpp b/openfpga/src/fabric/build_mux_modules.cpp
index 0f430c4d3..41cb68118 100644
--- a/openfpga/src/fabric/build_mux_modules.cpp
+++ b/openfpga/src/fabric/build_mux_modules.cpp
@@ -346,7 +346,7 @@ void build_mux_branch_module(ModuleManager& module_manager,
     build_rram_mux_branch_module(module_manager, circuit_lib, mux_model, module_name, mux_graph);
     break;
   default:
-    VTR_LOG_ERROR("Invalid design technology of multiplexer '%s'\n",
+    VTR_LOGF_ERROR(__FILE__, __LINE__, "Invalid design technology of multiplexer '%s'\n",
                   circuit_lib.model_name(mux_model).c_str()); 
     exit(1);
   }
@@ -1262,7 +1262,7 @@ void build_rram_mux_module(ModuleManager& module_manager,
   /* Error out for the conditions where we are not yet supported! */
   if (CIRCUIT_MODEL_LUT == circuit_lib.model_type(circuit_model)) {
     /* RRAM LUT is not supported now... */
-    VTR_LOG_ERROR("RRAM-based LUT is not supported for circuit model '%s')!\n",
+    VTR_LOGF_ERROR(__FILE__, __LINE__, "RRAM-based LUT is not supported for circuit model '%s')!\n",
                   circuit_lib.model_name(circuit_model).c_str());
     exit(1);
   }
@@ -1367,7 +1367,7 @@ void build_mux_module(ModuleManager& module_manager,
     build_rram_mux_module(module_manager, circuit_lib, circuit_model, module_name, mux_graph);
     break;
   default:
-    VTR_LOG_ERROR("Invalid design technology of multiplexer '%s'\n",
+    VTR_LOGF_ERROR(__FILE__, __LINE__, "Invalid design technology of multiplexer '%s'\n",
                  circuit_lib.model_name(circuit_model).c_str()); 
     exit(1);
   }
diff --git a/openfpga/src/fabric/build_routing_module_utils.cpp b/openfpga/src/fabric/build_routing_module_utils.cpp
new file mode 100644
index 000000000..c717604c5
--- /dev/null
+++ b/openfpga/src/fabric/build_routing_module_utils.cpp
@@ -0,0 +1,213 @@
+/********************************************************************
+ * This file includes most utilized functions that are used to build modules 
+ * for global routing architecture of a FPGA fabric
+ * Covering:
+ * 1. Connection blocks
+ * 2. Switch blocks
+ *******************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_log.h"
+#include "vtr_assert.h"
+#include "vtr_geometry.h"
+
+#include "openfpga_naming.h"
+
+#include "build_routing_module_utils.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/*********************************************************************
+ * Generate a port for a routing track of a swtich block
+ ********************************************************************/
+ModulePortId find_switch_block_module_chan_port(const ModuleManager& module_manager, 
+                                                const ModuleId& sb_module,
+                                                const RRGraph& rr_graph,
+                                                const RRGSB& rr_gsb, 
+                                                const e_side& chan_side,
+                                                const RRNodeId& cur_rr_node,
+                                                const PORTS& cur_rr_node_direction) {
+  /* Get the index in sb_info of cur_rr_node */
+  int index = rr_gsb.get_node_index(rr_graph, cur_rr_node, chan_side, cur_rr_node_direction);
+  /* Make sure this node is included in this sb_info */
+  VTR_ASSERT((-1 != index) && (NUM_SIDES != chan_side));
+
+  std::string chan_port_name = generate_sb_module_track_port_name(rr_graph.node_type(rr_gsb.get_chan_node(chan_side, index)),
+                                                                  chan_side, index,  
+                                                                  rr_gsb.get_chan_node_direction(chan_side, index));
+  
+  /* Must find a valid port id in the Switch Block module */
+  ModulePortId chan_port_id = module_manager.find_module_port(sb_module, chan_port_name); 
+  VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module, chan_port_id));
+  return chan_port_id; 
+}
+
+/*********************************************************************
+ * Generate an input port for routing multiplexer inside the switch block
+ * In addition to give the Routing Resource node of the input
+ * Users should provide the side of input, which is different case by case:
+ * 1. When the input is a pin of a CLB/Logic Block, the input_side should
+ *    be the side of the node on its grid!
+ *    For example, the input pin is on the top side of a switch block
+ *    but on the right side of a switch block
+ *                      +--------+
+ *                      |        |
+ *                      |  Grid  |---+
+ *                      |        |   |
+ *                      +--------+   v input_pin
+ *                      +----------------+
+ *                      |  Switch Block  |
+ *                      +----------------+
+ * 2. When the input is a routing track, the input_side should be
+ *    the side of the node locating on the switch block
+ ********************************************************************/
+ModulePortId find_switch_block_module_input_port(const ModuleManager& module_manager,
+                                                 const ModuleId& sb_module, 
+                                                 const RRGraph& rr_graph,
+                                                 const RRGSB& rr_gsb, 
+                                                 const e_side& input_side,
+                                                 const RRNodeId& input_rr_node) {
+  /* Deposit an invalid value */
+  ModulePortId input_port_id = ModulePortId::INVALID();
+  /* Generate the input port object */
+  switch (rr_graph.node_type(input_rr_node)) {
+  /* case SOURCE: */
+  case OPIN: {
+    /* Find the coordinator (grid_x and grid_y) for the input port */
+    vtr::Point<size_t> input_port_coord(rr_graph.node_xlow(input_rr_node),
+                                        rr_graph.node_ylow(input_rr_node));
+
+    /* Find the side where the grid pin locates in the grid */
+    enum e_side grid_pin_side = rr_graph.node_side(input_rr_node);
+    VTR_ASSERT(NUM_SIDES != grid_pin_side);
+
+    std::string input_port_name = generate_sb_module_grid_port_name(input_side,
+                                                                    grid_pin_side,
+                                                                    rr_graph.node_pin_num(input_rr_node)); 
+    /* Must find a valid port id in the Switch Block module */
+    input_port_id = module_manager.find_module_port(sb_module, input_port_name); 
+    VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module, input_port_id));
+    break;
+  }
+  case CHANX:
+  case CHANY: {
+    input_port_id = find_switch_block_module_chan_port(module_manager, sb_module, rr_graph, 
+                                                       rr_gsb, input_side, input_rr_node, IN_PORT);
+    break;
+  }
+  default: /* SOURCE, IPIN, SINK are invalid*/
+    VTR_LOGF_ERROR(__FILE__, __LINE__, "Invalid rr_node type! Should be [OPIN|CHANX|CHANY].\n");
+    exit(1);
+  }
+
+  return input_port_id; 
+}
+
+/*********************************************************************
+ * Generate a list of input ports for routing multiplexer inside the switch block
+ ********************************************************************/
+std::vector<ModulePortId> find_switch_block_module_input_ports(const ModuleManager& module_manager,
+                                                               const ModuleId& sb_module, 
+                                                               const RRGraph& rr_graph,
+                                                               const RRGSB& rr_gsb, 
+                                                               const std::vector<RRNodeId>& input_rr_nodes) {
+  std::vector<ModulePortId> input_ports;
+
+  for (const RRNodeId& input_rr_node : input_rr_nodes) {
+    /* Find the side where the input locates in the Switch Block */
+    enum e_side input_pin_side = NUM_SIDES;
+    /* The input could be at any side of the switch block, find it */
+    int index = -1;
+    rr_gsb.get_node_side_and_index(rr_graph, input_rr_node, IN_PORT, input_pin_side, index);
+    VTR_ASSERT(NUM_SIDES != input_pin_side);
+    VTR_ASSERT(-1 != index);
+
+    input_ports.push_back(find_switch_block_module_input_port(module_manager, sb_module, rr_graph, rr_gsb, input_pin_side, input_rr_node));
+  }
+
+  return input_ports;
+}
+
+/*********************************************************************
+ * Generate an input port for routing multiplexer inside the connection block
+ * which is the middle output of a routing track 
+ ********************************************************************/
+ModulePortId find_connection_block_module_chan_port(const ModuleManager& module_manager, 
+                                                    const ModuleId& cb_module,
+                                                    const RRGraph& rr_graph,
+                                                    const RRGSB& rr_gsb, 
+                                                    const t_rr_type& cb_type,
+                                                    const RRNodeId& chan_rr_node) {
+  ModulePortId input_port_id;
+  /* Generate the input port object */
+  switch (rr_graph.node_type(chan_rr_node)) {
+  case CHANX:
+  case CHANY: {
+    /* Create port description for the routing track middle output */
+    vtr::Point<size_t> port_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type));
+    int chan_node_track_id = rr_gsb.get_cb_chan_node_index(cb_type, chan_rr_node);
+    /* Create a port description for the middle output */
+    std::string input_port_name = generate_cb_module_track_port_name(cb_type,
+                                                                     chan_node_track_id,  
+                                                                     IN_PORT);
+    /* Must find a valid port id in the Switch Block module */
+    input_port_id = module_manager.find_module_port(cb_module, input_port_name); 
+    VTR_ASSERT(true == module_manager.valid_module_port_id(cb_module, input_port_id));
+    break;
+  }
+  default: /* OPIN, SOURCE, IPIN, SINK are invalid*/
+    VTR_LOGF_ERROR(__FILE__, __LINE__, "Invalid rr_node type! Should be [OPIN|CHANX|CHANY].\n");
+    exit(1);
+  }
+
+  return input_port_id;
+}
+
+/*********************************************************************
+ * Generate a port for a routing track of a swtich block
+ ********************************************************************/
+ModulePortId find_connection_block_module_ipin_port(const ModuleManager& module_manager,
+                                                    const ModuleId& cb_module, 
+                                                    const RRGraph& rr_graph,
+                                                    const RRGSB& rr_gsb, 
+                                                    const RRNodeId& src_rr_node) {
+
+  /* Ensure the src_rr_node is an input pin of a CLB */
+  VTR_ASSERT(IPIN == rr_graph.node_type(src_rr_node));
+  /* Create port description for input pin of a CLB */
+  vtr::Point<size_t> port_coord(rr_graph.node_xlow(src_rr_node), rr_graph.node_ylow(src_rr_node));
+  /* Search all the sides of a SB, see this drive_rr_node is an INPUT of this SB */
+  enum e_side cb_ipin_side = NUM_SIDES;
+  int cb_ipin_index = -1;
+  rr_gsb.get_node_side_and_index(rr_graph, src_rr_node, OUT_PORT, cb_ipin_side, cb_ipin_index);
+  /* We need to be sure that drive_rr_node is part of the CB */
+  VTR_ASSERT((-1 != cb_ipin_index)&&(NUM_SIDES != cb_ipin_side));
+  std::string port_name = generate_cb_module_grid_port_name(cb_ipin_side, 
+                                                            rr_graph.node_pin_num(rr_gsb.get_ipin_node(cb_ipin_side, cb_ipin_index))); 
+
+  /* Must find a valid port id in the Switch Block module */
+  ModulePortId ipin_port_id = module_manager.find_module_port(cb_module, port_name); 
+  VTR_ASSERT(true == module_manager.valid_module_port_id(cb_module, ipin_port_id));
+  return ipin_port_id;
+}
+
+/*********************************************************************
+ * Generate a list of routing track middle output ports 
+ * for routing multiplexer inside the connection block
+ ********************************************************************/
+std::vector<ModulePortId> find_connection_block_module_input_ports(const ModuleManager& module_manager,
+                                                                   const ModuleId& cb_module,
+                                                                   const RRGraph& rr_graph,
+                                                                   const RRGSB& rr_gsb, 
+                                                                   const t_rr_type& cb_type,
+                                                                   const std::vector<RRNodeId>& input_rr_nodes) {
+  std::vector<ModulePortId> input_ports;
+
+  for (auto input_rr_node : input_rr_nodes) {
+    input_ports.push_back(find_connection_block_module_chan_port(module_manager, cb_module, rr_graph, rr_gsb, cb_type, input_rr_node));
+  }
+
+  return input_ports;
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fabric/build_routing_module_utils.h b/openfpga/src/fabric/build_routing_module_utils.h
new file mode 100644
index 000000000..257a788cb
--- /dev/null
+++ b/openfpga/src/fabric/build_routing_module_utils.h
@@ -0,0 +1,63 @@
+#ifndef BUILD_ROUTING_MODULE_UTILS_H
+#define BUILD_ROUTING_MODULE_UTILS_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+
+#include <vector>
+#include "rr_gsb.h"
+#include "module_manager.h"
+#include "vpr_types.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+ModulePortId find_switch_block_module_chan_port(const ModuleManager& module_manager, 
+                                                const ModuleId& sb_module,
+                                                const RRGraph& rr_graph,
+                                                const RRGSB& rr_gsb, 
+                                                const e_side& chan_side,
+                                                const RRNodeId& cur_rr_node,
+                                                const PORTS& cur_rr_node_direction);
+
+ModulePortId find_switch_block_module_input_port(const ModuleManager& module_manager,
+                                                 const ModuleId& sb_module, 
+                                                 const RRGraph& rr_graph,
+                                                 const RRGSB& rr_gsb, 
+                                                 const e_side& input_side,
+                                                 const RRNodeId& input_rr_node);
+
+std::vector<ModulePortId> find_switch_block_module_input_ports(const ModuleManager& module_manager,
+                                                               const ModuleId& sb_module, 
+                                                               const RRGraph& rr_graph,
+                                                               const RRGSB& rr_gsb, 
+                                                               const std::vector<RRNodeId>& input_rr_nodes);
+
+ModulePortId find_connection_block_module_chan_port(const ModuleManager& module_manager, 
+                                                    const ModuleId& cb_module,
+                                                    const RRGraph& rr_graph,
+                                                    const RRGSB& rr_gsb, 
+                                                    const t_rr_type& cb_type,
+                                                    const RRNodeId& chan_rr_node);
+
+ModulePortId find_connection_block_module_ipin_port(const ModuleManager& module_manager,
+                                                    const ModuleId& cb_module, 
+                                                    const RRGraph& rr_graph,
+                                                    const RRGSB& rr_gsb, 
+                                                    const RRNodeId& src_rr_node);
+
+std::vector<ModulePortId> find_connection_block_module_input_ports(const ModuleManager& module_manager,
+                                                                   const ModuleId& cb_module,
+                                                                   const RRGraph& rr_graph,
+                                                                   const RRGSB& rr_gsb, 
+                                                                   const t_rr_type& cb_type,
+                                                                   const std::vector<RRNodeId>& input_rr_nodes);
+
+} /* end namespace openfpga */
+
+#endif

From afe8278670dab736c0e5bd2ce51cec354dcab2ec Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 13 Feb 2020 17:35:29 -0700
Subject: [PATCH 135/645] put routing module builder online

---
 openfpga/src/base/openfpga_build_fabric.cpp   |    1 +
 openfpga/src/fabric/build_device_module.cpp   |   32 +-
 openfpga/src/fabric/build_device_module.h     |    1 +
 openfpga/src/fabric/build_routing_modules.cpp | 1001 +++++++++++++++++
 openfpga/src/fabric/build_routing_modules.h   |   41 +
 .../src/utils/openfpga_rr_graph_utils.cpp     |   47 +
 openfpga/src/utils/openfpga_rr_graph_utils.h  |    9 +
 7 files changed, 1120 insertions(+), 12 deletions(-)
 create mode 100644 openfpga/src/fabric/build_routing_modules.cpp
 create mode 100644 openfpga/src/fabric/build_routing_modules.h

diff --git a/openfpga/src/base/openfpga_build_fabric.cpp b/openfpga/src/base/openfpga_build_fabric.cpp
index 879c127d6..5c3d8a69d 100644
--- a/openfpga/src/base/openfpga_build_fabric.cpp
+++ b/openfpga/src/base/openfpga_build_fabric.cpp
@@ -72,6 +72,7 @@ void build_fabric(OpenfpgaContext& openfpga_context,
 
   openfpga_context.mutable_module_graph() = build_device_module_graph(g_vpr_ctx.device(),
                                                                       const_cast<const OpenfpgaContext&>(openfpga_context),
+                                                                      cmd_context.option_enable(cmd, opt_compress_routing),
                                                                       cmd_context.option_enable(cmd, opt_duplicate_grid_pin),
                                                                       cmd_context.option_enable(cmd, opt_verbose));
 } 
diff --git a/openfpga/src/fabric/build_device_module.cpp b/openfpga/src/fabric/build_device_module.cpp
index fd7f1f31e..db3d3dfda 100644
--- a/openfpga/src/fabric/build_device_module.cpp
+++ b/openfpga/src/fabric/build_device_module.cpp
@@ -15,7 +15,7 @@
 #include "build_wire_modules.h"
 #include "build_memory_modules.h"
 #include "build_grid_modules.h"
-//#include "build_routing_modules.h"
+#include "build_routing_modules.h"
 //#include "build_top_module.h"
 #include "build_device_module.h"
 
@@ -28,6 +28,7 @@ namespace openfpga {
  *******************************************************************/
 ModuleManager build_device_module_graph(const DeviceContext& vpr_device_ctx,
                                         const OpenfpgaContext& openfpga_ctx,
+                                        const bool& compress_routing,
                                         const bool& duplicate_grid_pin,
                                         const bool& verbose) {
   vtr::ScopedStartFinishTimer timer("Build fabric module graph");
@@ -76,17 +77,24 @@ ModuleManager build_device_module_graph(const DeviceContext& vpr_device_ctx,
                      openfpga_ctx.arch().config_protocol.type(),
                      sram_model, duplicate_grid_pin, verbose);
 
-  //if (TRUE == vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy) {
-  //  build_unique_routing_modules(module_manager, L_device_rr_gsb, arch.spice->circuit_lib, 
-  //                               arch.sram_inf.verilog_sram_inf_orgz->type, sram_model, 
-  //                               vpr_setup.RoutingArch, rr_switches);
-  //} else {
-  //  VTR_ASSERT(FALSE == vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy);
-  //  build_flatten_routing_modules(module_manager, L_device_rr_gsb, arch.spice->circuit_lib, 
-  //                                arch.sram_inf.verilog_sram_inf_orgz->type, sram_model, 
-  //                                vpr_setup.RoutingArch, rr_switches);
-  //}
-
+  if (true == compress_routing) {
+    build_unique_routing_modules(module_manager,
+                                 vpr_device_ctx,
+                                 openfpga_ctx.vpr_device_annotation(),
+                                 openfpga_ctx.device_rr_gsb(),
+                                 openfpga_ctx.arch().circuit_lib,
+                                 openfpga_ctx.arch().config_protocol.type(),
+                                 sram_model, verbose);
+  } else {
+    VTR_ASSERT_SAFE(false == compress_routing);
+    build_flatten_routing_modules(module_manager,
+                                  vpr_device_ctx,
+                                  openfpga_ctx.vpr_device_annotation(),
+                                  openfpga_ctx.device_rr_gsb(),
+                                  openfpga_ctx.arch().circuit_lib,
+                                  openfpga_ctx.arch().config_protocol.type(),
+                                  sram_model, verbose);
+  }
 
   /* Build FPGA fabric top-level module */
   //build_top_module(module_manager, arch.spice->circuit_lib, 
diff --git a/openfpga/src/fabric/build_device_module.h b/openfpga/src/fabric/build_device_module.h
index 6830ca82b..fd585d986 100644
--- a/openfpga/src/fabric/build_device_module.h
+++ b/openfpga/src/fabric/build_device_module.h
@@ -16,6 +16,7 @@ namespace openfpga {
 
 ModuleManager build_device_module_graph(const DeviceContext& vpr_device_ctx,
                                         const OpenfpgaContext& openfpga_ctx,
+                                        const bool& compress_routing,
                                         const bool& duplicate_grid_pin,
                                         const bool& verbose);
 
diff --git a/openfpga/src/fabric/build_routing_modules.cpp b/openfpga/src/fabric/build_routing_modules.cpp
new file mode 100644
index 000000000..a08a0680f
--- /dev/null
+++ b/openfpga/src/fabric/build_routing_modules.cpp
@@ -0,0 +1,1001 @@
+/********************************************************************
+ * This file includes functions that are used to build modules 
+ * for global routing architecture of a FPGA fabric
+ * Covering:
+ * 1. Connection blocks
+ * 2. Switch blocks
+ *******************************************************************/
+#include <vector>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_geometry.h"
+#include "vtr_log.h"
+#include "vtr_time.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_side_manager.h"
+
+#include "openfpga_reserved_words.h"
+#include "openfpga_naming.h"
+
+#include "openfpga_rr_graph_utils.h"
+#include "module_manager_utils.h"
+#include "build_module_graph_utils.h"
+#include "build_routing_module_utils.h"
+
+#include "build_routing_modules.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/*********************************************************************
+ * Generate a short interconneciton in switch box
+ * There are two cases should be noticed.
+ * 1. The actual fan-in of cur_rr_node is 0. In this case,
+      the cur_rr_node need to be short connected to itself 
+      which is on the opposite side of this switch block
+ * 2. The actual fan-in of cur_rr_node is 0. In this case,
+ *    The cur_rr_node need to connected to the drive_rr_node
+ ********************************************************************/
+static 
+void build_switch_block_module_short_interc(ModuleManager& module_manager, 
+                                            const ModuleId& sb_module,
+                                            const RRGraph& rr_graph,
+                                            const RRGSB& rr_gsb,
+                                            const e_side& chan_side,
+                                            const RRNodeId& cur_rr_node,
+                                            const RRNodeId& drive_rr_node,
+                                            const std::map<ModulePortId, ModuleNetId>& input_port_to_module_nets) {
+  /* Find the name of output port */
+  ModulePortId output_port_id = find_switch_block_module_chan_port(module_manager, sb_module, 
+                                                                   rr_graph, rr_gsb, 
+                                                                   chan_side, cur_rr_node, OUT_PORT);
+  enum e_side input_pin_side = chan_side;
+  int index = -1;
+
+  /* Generate the input port object */
+  switch (rr_graph.node_type(drive_rr_node)) {
+  case OPIN: { 
+    rr_gsb.get_node_side_and_index(rr_graph, drive_rr_node, IN_PORT, input_pin_side, index);
+    break;
+  }
+  case CHANX:
+  case CHANY: {
+    /* This should be an input in the data structure of RRGSB */
+    if (cur_rr_node == drive_rr_node) {
+      /* To be strict, the input should locate on the opposite side. 
+       * Use the else part if this may change in some architecture.
+       */
+      SideManager side_manager(chan_side);
+      input_pin_side = side_manager.get_opposite(); 
+    } else {
+      /* The input could be at any side of the switch block, find it */
+      rr_gsb.get_node_side_and_index(rr_graph, drive_rr_node, IN_PORT, input_pin_side, index);
+    }
+    break;
+  }
+  default: /* SOURCE, IPIN, SINK are invalid*/
+    VTR_LOGF_ERROR(__FILE__, __LINE__, "Invalid rr_node type! Should be [OPIN|CHANX|CHANY].\n");
+    exit(1);
+  }
+  /* Find the name of input port */
+  ModulePortId input_port_id = find_switch_block_module_input_port(module_manager, sb_module, rr_graph, rr_gsb, input_pin_side, drive_rr_node);
+
+  /* The input port and output port must match in size */
+  BasicPort input_port = module_manager.module_port(sb_module, input_port_id);
+  BasicPort output_port = module_manager.module_port(sb_module, output_port_id);
+  VTR_ASSERT(input_port.get_width() == output_port.get_width());
+  
+  /* Create a module net for this short-wire connection */
+  for (size_t pin_id = 0; pin_id < input_port.pins().size(); ++pin_id) {
+    ModuleNetId net = input_port_to_module_nets.at(input_port_id);
+    /* Skip Configuring the net source, it is done before */
+    /* Configure the net sink */
+    module_manager.add_module_net_sink(sb_module, net, sb_module, 0, output_port_id, output_port.pins()[pin_id]);
+  }
+}
+
+/*********************************************************************
+ * Build a instance of a routing multiplexer as well as
+ * associated memory modules for a connection inside a switch block
+ ********************************************************************/
+static  
+void build_switch_block_mux_module(ModuleManager& module_manager, 
+                                   const ModuleId& sb_module, 
+                                   const VprDeviceAnnotation& device_annotation,
+                                   const RRGraph& rr_graph,
+                                   const RRGSB& rr_gsb, 
+                                   const CircuitLibrary& circuit_lib,
+                                   const e_side& chan_side,
+                                   const size_t& chan_node_id,
+                                   const RRNodeId& cur_rr_node,
+                                   const std::vector<RRNodeId>& driver_rr_nodes,
+                                   const RRSwitchId& switch_index,
+                                   const std::map<ModulePortId, ModuleNetId>& input_port_to_module_nets) {
+  /* Check current rr_node is CHANX or CHANY*/
+  VTR_ASSERT((CHANX == rr_graph.node_type(cur_rr_node)) || (CHANY == rr_graph.node_type(cur_rr_node)));
+
+  /* Get the circuit model id of the routing multiplexer */
+  CircuitModelId mux_model = device_annotation.rr_switch_circuit_model(switch_index);
+
+  /* Find the input size of the implementation of a routing multiplexer */
+  size_t datapath_mux_size = driver_rr_nodes.size();
+
+  /* Find the module name of the multiplexer and try to find it in the module manager */
+  std::string mux_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string(""));
+  ModuleId mux_module = module_manager.find_module(mux_module_name);
+  VTR_ASSERT (true == module_manager.valid_module_id(mux_module));
+
+  /* Get the MUX instance id from the module manager */
+  size_t mux_instance_id = module_manager.num_instance(sb_module, mux_module);
+  /* Instanciate the MUX Module */
+  module_manager.add_child_module(sb_module, mux_module);
+
+  /* Give an instance name: this name should be consistent with the block name given in SDC manager,
+   * If you want to bind the SDC generation to modules
+   */
+  std::string mux_instance_name = generate_sb_memory_instance_name(SWITCH_BLOCK_MUX_INSTANCE_PREFIX, chan_side, chan_node_id, std::string(""));
+  module_manager.set_child_instance_name(sb_module, mux_module, mux_instance_id, mux_instance_name);
+
+  /* Generate input ports that are wired to the input bus of the routing multiplexer */
+  std::vector<ModulePortId> sb_input_port_ids = find_switch_block_module_input_ports(module_manager, sb_module, rr_graph, rr_gsb, driver_rr_nodes);
+
+  /* Link input bus port to Switch Block inputs */
+  std::vector<CircuitPortId> mux_model_input_ports = circuit_lib.model_ports_by_type(mux_model, CIRCUIT_MODEL_PORT_INPUT, true);
+  VTR_ASSERT(1 == mux_model_input_ports.size());
+  /* Find the module port id of the input port */
+  ModulePortId mux_input_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_prefix(mux_model_input_ports[0])); 
+  VTR_ASSERT(true == module_manager.valid_module_port_id(mux_module, mux_input_port_id));
+  BasicPort mux_input_port = module_manager.module_port(mux_module, mux_input_port_id);
+
+  /* Check port size should match */
+  VTR_ASSERT(mux_input_port.get_width() == sb_input_port_ids.size());
+  for (size_t pin_id = 0; pin_id < sb_input_port_ids.size(); ++pin_id) {
+    /* Use the exising net */
+    ModuleNetId net = input_port_to_module_nets.at(sb_input_port_ids[pin_id]);
+    /* Configure the net source only if it is not yet in the source list */
+    if (false == module_manager.net_source_exist(sb_module, net, sb_module, 0, sb_input_port_ids[pin_id], 0)) {
+      module_manager.add_module_net_source(sb_module, net, sb_module, 0, sb_input_port_ids[pin_id], 0);
+    }
+    /* Configure the net sink */
+    module_manager.add_module_net_sink(sb_module, net, mux_module, mux_instance_id, mux_input_port_id, mux_input_port.pins()[pin_id]);
+  }
+
+  /* Link output port to Switch Block outputs */
+  std::vector<CircuitPortId> mux_model_output_ports = circuit_lib.model_ports_by_type(mux_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
+  VTR_ASSERT(1 == mux_model_output_ports.size());
+  /* Use the port name convention in the circuit library */
+  ModulePortId mux_output_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_prefix(mux_model_output_ports[0])); 
+  VTR_ASSERT(true == module_manager.valid_module_port_id(mux_module, mux_output_port_id));
+  BasicPort mux_output_port = module_manager.module_port(mux_module, mux_output_port_id);
+  ModulePortId sb_output_port_id = find_switch_block_module_chan_port(module_manager, sb_module, rr_graph, rr_gsb, chan_side, cur_rr_node, OUT_PORT); 
+  BasicPort sb_output_port = module_manager.module_port(sb_module, sb_output_port_id);
+
+  /* Check port size should match */
+  VTR_ASSERT(sb_output_port.get_width() == mux_output_port.get_width());
+  for (size_t pin_id = 0; pin_id < mux_output_port.pins().size(); ++pin_id) {
+    ModuleNetId net = module_manager.create_module_net(sb_module);
+    /* Configuring the net source */
+    module_manager.add_module_net_source(sb_module, net, mux_module, mux_instance_id, mux_output_port_id, mux_output_port.pins()[pin_id]);
+    /* Configure the net sink */
+    module_manager.add_module_net_sink(sb_module, net, sb_module, 0, sb_output_port_id, sb_output_port.pins()[pin_id]);
+  }
+
+  /* Instanciate memory modules */
+  /* Find the name and module id of the memory module */
+  std::string mem_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string(MEMORY_MODULE_POSTFIX)); 
+  ModuleId mem_module = module_manager.find_module(mem_module_name);
+  VTR_ASSERT (true == module_manager.valid_module_id(mem_module));
+
+  size_t mem_instance_id = module_manager.num_instance(sb_module, mem_module);
+  module_manager.add_child_module(sb_module, mem_module);
+  /* Give an instance name: this name should be consistent with the block name given in bitstream manager,
+   * If you want to bind the bitstream generation to modules
+   */
+  std::string mem_instance_name = generate_sb_memory_instance_name(SWITCH_BLOCK_MEM_INSTANCE_PREFIX, chan_side, chan_node_id, std::string(""));
+  module_manager.set_child_instance_name(sb_module, mem_module, mem_instance_id, mem_instance_name);
+
+  /* Add nets to connect regular and mode-select SRAM ports to the SRAM port of memory module */
+  add_module_nets_between_logic_and_memory_sram_bus(module_manager, sb_module, 
+                                                    mux_module, mux_instance_id,
+                                                    mem_module, mem_instance_id,
+                                                    circuit_lib, mux_model);
+  /* Update memory and instance list */
+  module_manager.add_configurable_child(sb_module, mem_module, mem_instance_id);
+}
+
+/*********************************************************************
+ * Generate child modules for a interconnection inside switch block
+ * The interconnection could be either a wire or a routing multiplexer,
+ * which depends on the fan-in of the rr_nodes in the switch block
+ ********************************************************************/
+static  
+void build_switch_block_interc_modules(ModuleManager& module_manager,
+                                       const ModuleId& sb_module, 
+                                       const VprDeviceAnnotation& device_annotation,
+                                       const RRGraph& rr_graph,
+                                       const RRGSB& rr_gsb,
+                                       const CircuitLibrary& circuit_lib,
+                                       const e_side& chan_side,
+                                       const size_t& chan_node_id,
+                                       const std::map<ModulePortId, ModuleNetId>& input_port_to_module_nets) {
+  std::vector<RRNodeId> driver_rr_nodes;
+
+  /* Get the node */
+  const RRNodeId& cur_rr_node = rr_gsb.get_chan_node(chan_side, chan_node_id);
+
+  /* Determine if the interc lies inside a channel wire, that is interc between segments */
+  if (false == rr_gsb.is_sb_node_passing_wire(rr_graph, chan_side, chan_node_id)) {
+    driver_rr_nodes = get_rr_graph_configurable_driver_nodes(rr_graph, cur_rr_node);
+    /* Special: if there are zero-driver nodes. We skip here */
+    if (0 == driver_rr_nodes.size()) {
+      return; 
+    }
+  }
+
+  if (0 == driver_rr_nodes.size()) {
+    /* Print a special direct connection*/
+    build_switch_block_module_short_interc(module_manager, sb_module,
+                                           rr_graph, rr_gsb, 
+                                           chan_side, cur_rr_node, 
+                                           cur_rr_node,
+                                           input_port_to_module_nets);
+  } else if (1 == driver_rr_nodes.size()) {
+    /* Print a direct connection*/
+    build_switch_block_module_short_interc(module_manager, sb_module,
+                                           rr_graph, rr_gsb, chan_side, cur_rr_node, 
+                                           driver_rr_nodes[0],
+                                           input_port_to_module_nets);
+  } else if (1 < driver_rr_nodes.size()) {
+    /* Print the multiplexer, fan_in >= 2 */
+    std::vector<RRSwitchId> driver_switches = get_rr_graph_driver_switches(rr_graph, cur_rr_node);
+    VTR_ASSERT(1 == driver_switches.size());
+    build_switch_block_mux_module(module_manager, 
+                                  sb_module, device_annotation, rr_graph, rr_gsb,
+                                  circuit_lib, 
+                                  chan_side, chan_node_id, cur_rr_node,  
+                                  driver_rr_nodes, 
+                                  driver_switches[0],
+                                  input_port_to_module_nets);
+  } /*Nothing should be done else*/ 
+}
+
+
+/********************************************************************
+ * Build a module for a switch block whose detailed description is
+ * available in a RRGSB object 
+ * A Switch Box module consists of following ports:
+ * 1. Channel Y [x][y] inputs 
+ * 2. Channel X [x+1][y] inputs
+ * 3. Channel Y [x][y-1] outputs
+ * 4. Channel X [x][y] outputs
+ * 5. Grid[x][y+1] Right side outputs pins
+ * 6. Grid[x+1][y+1] Left side output pins
+ * 7. Grid[x+1][y+1] Bottom side output pins
+ * 8. Grid[x+1][y] Top side output pins
+ * 9. Grid[x+1][y] Left side output pins
+ * 10. Grid[x][y] Right side output pins
+ * 11. Grid[x][y] Top side output pins
+ * 12. Grid[x][y+1] Bottom side output pins
+ *
+ * Location of a Switch Box in FPGA fabric:
+ *
+ *    --------------          --------------
+ *    |            |          |            |
+ *    |    Grid    |  ChanY   |    Grid    |
+ *    |  [x][y+1]  | [x][y+1] | [x+1][y+1] |
+ *    |            |          |            |
+ *    --------------          --------------
+ *                  ----------
+ *       ChanX      | Switch |     ChanX 
+ *       [x][y]     |   Box  |    [x+1][y]
+ *                  | [x][y] |
+ *                  ----------
+ *    --------------          --------------
+ *    |            |          |            |
+ *    |    Grid    |  ChanY   |    Grid    |
+ *    |   [x][y]   |  [x][y]  |  [x+1][y]  |
+ *    |            |          |            |
+ *    --------------          --------------
+ *
+ * Switch Block pin location map
+ *
+ *                       Grid[x][y+1]   ChanY[x][y+1]  Grid[x+1][y+1] 
+ *                        right_pins  inputs/outputs     left_pins
+ *                            |             ^                |
+ *                            |             |                |
+ *                            v             v                v
+ *                    +-----------------------------------------------+
+ *                    |                                               |
+ *    Grid[x][y+1]    |                                               |    Grid[x+1][y+1]
+ *    bottom_pins---->|                                               |<---- bottom_pins
+ *                    |                                               |
+ * ChanX[x][y]        |              Switch Box [x][y]                |     ChanX[x+1][y]
+ * inputs/outputs<--->|                                               |<---> inputs/outputs
+ *                    |                                               |
+ *    Grid[x][y+1]    |                                               |    Grid[x+1][y+1]
+ *       top_pins---->|                                               |<---- top_pins
+ *                    |                                               |
+ *                    +-----------------------------------------------+
+ *                            ^             ^                ^
+ *                            |             |                |
+ *                            |             v                |
+ *                       Grid[x][y]     ChanY[x][y]      Grid[x+1][y] 
+ *                       right_pins    inputs/outputs      left_pins
+ *
+ *
+ ********************************************************************/
+static 
+void build_switch_block_module(ModuleManager& module_manager, 
+                               const VprDeviceAnnotation& device_annotation,
+                               const RRGraph& rr_graph,
+                               const CircuitLibrary& circuit_lib,
+                               const e_config_protocol_type& sram_orgz_type,
+                               const CircuitModelId& sram_model,
+                               const RRGSB& rr_gsb,
+                               const bool& verbose) {
+  /* Create a Module of Switch Block and add to module manager */
+  vtr::Point<size_t> gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
+  ModuleId sb_module = module_manager.add_module(generate_switch_block_module_name(gsb_coordinate)); 
+
+  VTR_LOGV(verbose,
+           "Building module '%s'...",
+           generate_switch_block_module_name(gsb_coordinate).c_str());
+
+  /* Create a cache (fast look up) for module nets whose source are input ports */
+  std::map<ModulePortId, ModuleNetId> input_port_to_module_nets;
+
+  /* Add routing channel ports at each side of the GSB */
+  for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
+    SideManager side_manager(side);
+
+    for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) {
+      std::string port_name = generate_sb_module_track_port_name(rr_graph.node_type(rr_gsb.get_chan_node(side_manager.get_side(), itrack)),
+                                                                 side_manager.get_side(), itrack,  
+                                                                 rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack));
+      BasicPort module_port(port_name, 1); /* Every track has a port size of 1 */
+
+      switch (rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) {
+      case OUT_PORT: 
+        module_manager.add_port(sb_module, module_port, ModuleManager::MODULE_OUTPUT_PORT);
+        break;
+      case IN_PORT: {
+        ModulePortId input_port_id = module_manager.add_port(sb_module, module_port, ModuleManager::MODULE_INPUT_PORT);
+        /* Cache the input net */
+        ModuleNetId net = module_manager.create_module_net(sb_module);
+        module_manager.add_module_net_source(sb_module, net, sb_module, 0, input_port_id, 0);
+        input_port_to_module_nets[input_port_id] = net;
+        break;
+      }
+      default:
+        VTR_LOGF_ERROR(__FILE__, __LINE__,
+                       "Invalid direction of chan[%d][%d]_track[%d]!\n",
+                       rr_gsb.get_sb_x(), rr_gsb.get_sb_y(), itrack);
+        exit(1);
+      }
+    }
+    /* Dump OPINs of adjacent CLBs */
+    for (size_t inode = 0; inode < rr_gsb.get_num_opin_nodes(side_manager.get_side()); ++inode) {
+      vtr::Point<size_t> port_coord(rr_graph.node_xlow(rr_gsb.get_opin_node(side_manager.get_side(), inode)),
+                                    rr_graph.node_ylow(rr_gsb.get_opin_node(side_manager.get_side(), inode)));
+      std::string port_name = generate_sb_module_grid_port_name(side_manager.get_side(),
+                                                                rr_graph.node_side(rr_gsb.get_opin_node(side_manager.get_side(), inode)),
+                                                                rr_graph.node_pin_num(rr_gsb.get_opin_node(side_manager.get_side(), inode))); 
+      BasicPort module_port(port_name, 1); /* Every grid output has a port size of 1 */
+      /* Grid outputs are inputs of switch blocks */
+      ModulePortId input_port_id = module_manager.add_port(sb_module, module_port, ModuleManager::MODULE_INPUT_PORT);
+
+      /* Cache the input net */
+      ModuleNetId net = module_manager.create_module_net(sb_module);
+      module_manager.add_module_net_source(sb_module, net, sb_module, 0, input_port_id, 0);
+      input_port_to_module_nets[input_port_id] = net;
+    } 
+  }
+
+  /* Add routing multiplexers as child modules */
+  for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
+    SideManager side_manager(side);
+    for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) {
+      /* We care INC_DIRECTION tracks at this side*/
+      if (OUT_PORT == rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) {
+        build_switch_block_interc_modules(module_manager, 
+                                          sb_module, device_annotation, rr_graph, rr_gsb,
+                                          circuit_lib, 
+                                          side_manager.get_side(), 
+                                          itrack, 
+                                          input_port_to_module_nets);
+      } 
+    }
+  }
+
+  /* Add global ports to the pb_module:
+   * This is a much easier job after adding sub modules (instances), 
+   * we just need to find all the global ports from the child modules and build a list of it
+   */
+  add_module_global_ports_from_child_modules(module_manager, sb_module);
+
+  /* Count shared SRAM ports from the sub-modules under this Verilog module
+   * This is a much easier job after adding sub modules (instances), 
+   * we just need to find all the I/O ports from the child modules and build a list of it
+   */
+  size_t module_num_shared_config_bits = find_module_num_shared_config_bits_from_child_modules(module_manager, sb_module); 
+  if (0 < module_num_shared_config_bits) {
+    add_reserved_sram_ports_to_module_manager(module_manager, sb_module, module_num_shared_config_bits);
+  }
+
+  /* Count SRAM ports from the sub-modules under this Verilog module
+   * This is a much easier job after adding sub modules (instances), 
+   * we just need to find all the I/O ports from the child modules and build a list of it
+   */
+  size_t module_num_config_bits = find_module_num_config_bits_from_child_modules(module_manager, sb_module, circuit_lib, sram_model, sram_orgz_type); 
+  if (0 < module_num_config_bits) {
+    add_sram_ports_to_module_manager(module_manager, sb_module, circuit_lib, sram_model, sram_orgz_type, module_num_config_bits);
+  }
+
+  /* Add all the nets to connect configuration ports from memory module to primitive modules
+   * This is a one-shot addition that covers all the memory modules in this primitive module!
+   */
+  if (0 < module_manager.configurable_children(sb_module).size()) {
+    add_module_nets_memory_config_bus(module_manager, sb_module, 
+                                      sram_orgz_type, circuit_lib.design_tech_type(sram_model));
+  }
+
+  VTR_LOGV(verbose, "Done\n");
+}
+
+/*********************************************************************
+ * Print a short interconneciton in connection
+ ********************************************************************/
+static 
+void build_connection_block_module_short_interc(ModuleManager& module_manager, 
+                                                const ModuleId& cb_module,
+                                                const RRGraph& rr_graph,
+                                                const RRGSB& rr_gsb,
+                                                const t_rr_type& cb_type,
+                                                const RRNodeId& src_rr_node,
+                                                const std::map<ModulePortId, ModuleNetId>& input_port_to_module_nets) {
+  /* Ensure we have only one 1 driver node */
+  std::vector<RRNodeId> driver_rr_nodes = get_rr_graph_configurable_driver_nodes(rr_graph, src_rr_node);
+
+  /* We have OPINs since we may have direct connections:
+   * These connections should be handled by other functions in the compact_netlist.c 
+   * So we just return here for OPINs 
+   */
+  if (0 == driver_rr_nodes.size()) {
+    return;
+  }
+
+  /* Find the driver node */
+  VTR_ASSERT_SAFE(1 == driver_rr_nodes.size());
+  const RRNodeId& driver_rr_node = driver_rr_nodes[0]; 
+
+  VTR_ASSERT((CHANX == rr_graph.node_type(driver_rr_node)) || (CHANY == rr_graph.node_type(driver_rr_node)));
+
+  /* Create port description for the routing track middle output */
+  ModulePortId input_port_id = find_connection_block_module_chan_port(module_manager, cb_module, rr_graph, rr_gsb, cb_type, driver_rr_node);
+
+  /* Create port description for input pin of a CLB */
+  ModulePortId ipin_port_id = find_connection_block_module_ipin_port(module_manager, cb_module, rr_graph, rr_gsb, src_rr_node);
+
+  /* The input port and output port must match in size */
+  BasicPort input_port = module_manager.module_port(cb_module, input_port_id);
+  BasicPort ipin_port = module_manager.module_port(cb_module, ipin_port_id);
+  VTR_ASSERT(input_port.get_width() == ipin_port.get_width());
+  
+  /* Create a module net for this short-wire connection */
+  for (size_t pin_id = 0; pin_id < input_port.pins().size(); ++pin_id) {
+    ModuleNetId net = input_port_to_module_nets.at(input_port_id);
+    /* Skip Configuring the net source, it is done before */
+    /* Configure the net sink */
+    module_manager.add_module_net_sink(cb_module, net, cb_module, 0, ipin_port_id, ipin_port.pins()[pin_id]);
+  }
+}
+
+/*********************************************************************
+ * Build a instance of a routing multiplexer as well as
+ * associated memory modules for a connection inside a connection block
+ ********************************************************************/
+static  
+void build_connection_block_mux_module(ModuleManager& module_manager, 
+                                       const ModuleId& cb_module, 
+                                       const VprDeviceAnnotation& device_annotation,
+                                       const RRGraph& rr_graph,
+                                       const RRGSB& rr_gsb, 
+                                       const t_rr_type& cb_type, 
+                                       const CircuitLibrary& circuit_lib,
+                                       const e_side& cb_ipin_side,
+                                       const size_t& ipin_index,
+                                       const std::map<ModulePortId, ModuleNetId>& input_port_to_module_nets) {
+  const RRNodeId& cur_rr_node = rr_gsb.get_ipin_node(cb_ipin_side, ipin_index);
+  /* Check current rr_node is an input pin of a CLB */
+  VTR_ASSERT(IPIN == rr_graph.node_type(cur_rr_node));
+
+  /* Build a vector of driver rr_nodes */
+  std::vector<RRNodeId> driver_rr_nodes = get_rr_graph_configurable_driver_nodes(rr_graph, cur_rr_node);
+
+  std::vector<RRSwitchId> driver_switches = get_rr_graph_driver_switches(rr_graph, cur_rr_node);
+  VTR_ASSERT(1 == driver_switches.size());
+
+  /* Get the circuit model id of the routing multiplexer */
+  CircuitModelId mux_model = device_annotation.rr_switch_circuit_model(driver_switches[0]);
+
+  /* Find the input size of the implementation of a routing multiplexer */
+  size_t datapath_mux_size = driver_rr_nodes.size();
+
+  /* Find the module name of the multiplexer and try to find it in the module manager */
+  std::string mux_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string(""));
+  ModuleId mux_module = module_manager.find_module(mux_module_name);
+  VTR_ASSERT (true == module_manager.valid_module_id(mux_module));
+
+  /* Get the MUX instance id from the module manager */
+  size_t mux_instance_id = module_manager.num_instance(cb_module, mux_module);
+  module_manager.add_child_module(cb_module, mux_module);
+
+  /* Give an instance name: this name should be consistent with the block name given in SDC manager,
+   * If you want to bind the SDC generation to modules
+   */
+  std::string mux_instance_name = generate_cb_mux_instance_name(CONNECTION_BLOCK_MUX_INSTANCE_PREFIX, rr_graph.node_side(rr_gsb.get_ipin_node(cb_ipin_side, ipin_index)), ipin_index, std::string(""));
+  module_manager.set_child_instance_name(cb_module, mux_module, mux_instance_id, mux_instance_name);
+
+  /* TODO: Generate input ports that are wired to the input bus of the routing multiplexer */
+  std::vector<ModulePortId> cb_input_port_ids = find_connection_block_module_input_ports(module_manager, cb_module, rr_graph, rr_gsb, cb_type, driver_rr_nodes);
+
+  /* Link input bus port to Switch Block inputs */
+  std::vector<CircuitPortId> mux_model_input_ports = circuit_lib.model_ports_by_type(mux_model, CIRCUIT_MODEL_PORT_INPUT, true);
+  VTR_ASSERT(1 == mux_model_input_ports.size());
+  /* Find the module port id of the input port */
+  ModulePortId mux_input_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_prefix(mux_model_input_ports[0])); 
+  VTR_ASSERT(true == module_manager.valid_module_port_id(mux_module, mux_input_port_id));
+  BasicPort mux_input_port = module_manager.module_port(mux_module, mux_input_port_id);
+
+  /* Check port size should match */
+  VTR_ASSERT(mux_input_port.get_width() == cb_input_port_ids.size());
+  for (size_t pin_id = 0; pin_id < cb_input_port_ids.size(); ++pin_id) {
+    /* Use the exising net */
+    ModuleNetId net = input_port_to_module_nets.at(cb_input_port_ids[pin_id]);
+    /* No need to configure the net source since it is already done before */
+    /* Configure the net sink */
+    module_manager.add_module_net_sink(cb_module, net, mux_module, mux_instance_id, mux_input_port_id, mux_input_port.pins()[pin_id]);
+  }
+
+  /* Link output port to Switch Block outputs */
+  std::vector<CircuitPortId> mux_model_output_ports = circuit_lib.model_ports_by_type(mux_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
+  VTR_ASSERT(1 == mux_model_output_ports.size());
+  /* Use the port name convention in the circuit library */
+  ModulePortId mux_output_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_prefix(mux_model_output_ports[0])); 
+  VTR_ASSERT(true == module_manager.valid_module_port_id(mux_module, mux_output_port_id));
+  BasicPort mux_output_port = module_manager.module_port(mux_module, mux_output_port_id);
+  ModulePortId cb_output_port_id = find_connection_block_module_ipin_port(module_manager, cb_module, rr_graph, rr_gsb, cur_rr_node);
+  BasicPort cb_output_port = module_manager.module_port(cb_module, cb_output_port_id);
+
+  /* Check port size should match */
+  VTR_ASSERT(cb_output_port.get_width() == mux_output_port.get_width());
+  for (size_t pin_id = 0; pin_id < mux_output_port.pins().size(); ++pin_id) {
+    ModuleNetId net = module_manager.create_module_net(cb_module);
+    /* Configuring the net source */
+    module_manager.add_module_net_source(cb_module, net, mux_module, mux_instance_id, mux_output_port_id, mux_output_port.pins()[pin_id]);
+    /* Configure the net sink */
+    module_manager.add_module_net_sink(cb_module, net, cb_module, 0, cb_output_port_id, cb_output_port.pins()[pin_id]);
+  }
+
+  /* Instanciate memory modules */
+  /* Find the name and module id of the memory module */
+  std::string mem_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string(MEMORY_MODULE_POSTFIX)); 
+  ModuleId mem_module = module_manager.find_module(mem_module_name);
+  VTR_ASSERT (true == module_manager.valid_module_id(mem_module));
+
+  size_t mem_instance_id = module_manager.num_instance(cb_module, mem_module);
+  module_manager.add_child_module(cb_module, mem_module);
+
+  /* Give an instance name: this name should be consistent with the block name given in bitstream manager,
+   * If you want to bind the bitstream generation to modules
+   */
+  std::string mem_instance_name = generate_cb_memory_instance_name(CONNECTION_BLOCK_MEM_INSTANCE_PREFIX, rr_graph.node_side(rr_gsb.get_ipin_node(cb_ipin_side, ipin_index)), ipin_index, std::string(""));
+  module_manager.set_child_instance_name(cb_module, mem_module, mem_instance_id, mem_instance_name);
+
+  /* Add nets to connect regular and mode-select SRAM ports to the SRAM port of memory module */
+  add_module_nets_between_logic_and_memory_sram_bus(module_manager, cb_module, 
+                                                    mux_module, mux_instance_id,
+                                                    mem_module, mem_instance_id,
+                                                    circuit_lib, mux_model);
+  /* Update memory and instance list */
+  module_manager.add_configurable_child(cb_module, mem_module, mem_instance_id);
+}
+
+/********************************************************************
+ * Print internal connections of a connection block 
+ * For a IPIN node that is driven by only 1 fan-in,
+ * a short wire will be created
+ * For a IPIN node that is driven by more than two fan-ins,
+ * a routing multiplexer will be instanciated 
+ ********************************************************************/
+static 
+void build_connection_block_interc_modules(ModuleManager& module_manager,
+                                           const ModuleId& cb_module, 
+                                           const VprDeviceAnnotation& device_annotation,
+                                           const RRGraph& rr_graph,
+                                           const RRGSB& rr_gsb,
+                                           const t_rr_type& cb_type,
+                                           const CircuitLibrary& circuit_lib,
+                                           const e_side& cb_ipin_side,
+                                           const size_t& ipin_index,
+                                           const std::map<ModulePortId, ModuleNetId>& input_port_to_module_nets) {
+  const RRNodeId& src_rr_node = rr_gsb.get_ipin_node(cb_ipin_side, ipin_index);
+
+  if (1 > rr_graph.node_in_edges(src_rr_node).size()) {
+    return; /* This port has no driver, skip it */
+  } else if (1 == rr_graph.node_in_edges(src_rr_node).size()) {
+    /* Print a direct connection */
+    build_connection_block_module_short_interc(module_manager, cb_module, rr_graph, rr_gsb, cb_type, src_rr_node, input_port_to_module_nets);
+
+  } else if (1 < rr_graph.node_in_edges(src_rr_node).size()) {
+    /* Print the multiplexer, fan_in >= 2 */
+    build_connection_block_mux_module(module_manager, 
+                                      cb_module, device_annotation,
+                                      rr_graph, rr_gsb, cb_type, 
+                                      circuit_lib,
+                                      cb_ipin_side, ipin_index, 
+                                      input_port_to_module_nets); 
+  } /*Nothing should be done else*/ 
+}
+
+/******************************************************************** 
+ * Generate a module of a connection Box (Type: [CHANX|CHANY])
+ * Actually it is very similiar to switch box but
+ * the difference is connection boxes connect Grid INPUT Pins to channels
+ * NOTE: direct connection between CLBs should NOT be included inside this
+ *       module! They should be added in the top-level module as their connection
+ *       is not limited to adjacent CLBs!!!
+ *
+ * Location of a X- and Y-direction Connection Block in FPGA fabric
+ *               +------------+       +-------------+ 
+ *               |            |------>|             |
+ *               |     CLB    |<------| Y-direction |
+ *               |            | ...   |  Connection |
+ *               |            |------>|    Block    |
+ *               +------------+       +-------------+
+ *                 |  ^ ... |            | ^ ... |
+ *                 v  |     v            v |     v
+ *           +-------------------+    +-------------+
+ *       --->|                   |--->|             |
+ *       <---|     X-direction   |<---|    Switch   |                           
+ *        ...|  Connection block |... |    Block    |
+ *       --->|                   |--->|             |
+ *           +-------------------+    +-------------+
+ *
+ *  Internal structure:
+ *  This is an example of a X-direction connection block  
+ *  Note that middle output ports are shorted wire from inputs of routing tracks, 
+ *  which are also the inputs of routing multiplexer of the connection block 
+ *
+ *                      CLB Input Pins
+ *                         (IPINs)
+ *                       ^   ^     ^
+ *                       |   | ... |
+ *              +--------------------------+
+ *              |       ^    ^     ^       |
+ *              |       |    | ... |       |   
+ *              |  +--------------------+  | 
+ *              |  |       routing      |  |
+ *              |  |    multiplexers    |  |
+ *              |  +--------------------+  | 
+ *              |      middle outputs      |
+ *              |    of routing channel    |
+ *              |    ^ ^ ^ ^     ^ ^ ^ ^   |
+ *              |    | | | | ... | | | |   |
+ *     in[0] -->|------------------------->|---> out[0]
+ *    out[1] <--|<-------------------------|<--- in[1]
+ *              |           ...            |
+ *   in[W-2] -->|------------------------->|---> out[W-2]
+ *  out[W-1] <--|<-------------------------|<--- in[W-1]
+ *              +--------------------------+
+ *
+ *  W: routing channel width
+ *              
+ ********************************************************************/
+static 
+void build_connection_block_module(ModuleManager& module_manager, 
+                                   const VprDeviceAnnotation& device_annotation,
+                                   const RRGraph& rr_graph,
+                                   const CircuitLibrary& circuit_lib, 
+                                   const e_config_protocol_type& sram_orgz_type, 
+                                   const CircuitModelId& sram_model, 
+                                   const RRGSB& rr_gsb,
+                                   const t_rr_type& cb_type,
+                                   const bool& verbose) {
+  /* Create the netlist */
+  vtr::Point<size_t> gsb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type));
+
+  /* Create a Verilog Module based on the circuit model, and add to module manager */
+  ModuleId cb_module = module_manager.add_module(generate_connection_block_module_name(cb_type, gsb_coordinate)); 
+
+  VTR_LOGV(verbose,
+           "Building module '%s'...",
+           generate_connection_block_module_name(cb_type, gsb_coordinate).c_str());
+
+  /* Add the input and output ports of routing tracks in the channel 
+   * Routing tracks pass through the connection blocks  
+   */
+  for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) {
+    vtr::Point<size_t> port_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type));
+    std::string port_name = generate_cb_module_track_port_name(cb_type,
+                                                               itrack,  
+                                                               IN_PORT);
+    BasicPort module_port(port_name, 1); /* Every track has a port size of 1 */
+    module_manager.add_port(cb_module, module_port, ModuleManager::MODULE_INPUT_PORT);
+  }
+  for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) {
+    vtr::Point<size_t> port_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type));
+    std::string port_name = generate_cb_module_track_port_name(cb_type,
+                                                               itrack,  
+                                                               OUT_PORT);
+    BasicPort module_port(port_name, 1); /* Every track has a port size of 1 */
+    module_manager.add_port(cb_module, module_port, ModuleManager::MODULE_OUTPUT_PORT);
+  }
+
+  /* Add the input pins of grids, which are output ports of the connection block */
+  std::vector<enum e_side> cb_ipin_sides = rr_gsb.get_cb_ipin_sides(cb_type);
+  for (size_t iside = 0; iside < cb_ipin_sides.size(); ++iside) {
+    enum e_side cb_ipin_side = cb_ipin_sides[iside];
+    for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) {
+      const RRNodeId& ipin_node = rr_gsb.get_ipin_node(cb_ipin_side, inode);
+      vtr::Point<size_t> port_coord(rr_graph.node_xlow(ipin_node), rr_graph.node_ylow(ipin_node));
+      std::string port_name = generate_cb_module_grid_port_name(cb_ipin_side,
+                                                                rr_graph.node_pin_num(ipin_node)); 
+      BasicPort module_port(port_name, 1); /* Every grid output has a port size of 1 */
+      /* Grid outputs are inputs of switch blocks */
+      module_manager.add_port(cb_module, module_port, ModuleManager::MODULE_OUTPUT_PORT);
+    }
+  }
+
+  /* Create a cache (fast look up) for module nets whose source are input ports */
+  std::map<ModulePortId, ModuleNetId> input_port_to_module_nets;
+
+  /* Generate short-wire connection for each routing track : 
+   * Each input port is short-wired to its output port and middle output port
+   *    
+   *   in[i] ----------> out[i]
+   *             |
+   *             +-----> mid_out[i]
+   */
+  for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) {
+    vtr::Point<size_t> port_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type));
+    /* Create a port description for the input */
+    std::string input_port_name = generate_cb_module_track_port_name(cb_type,
+                                                                     itrack,  
+                                                                     IN_PORT);
+    ModulePortId input_port_id = module_manager.find_module_port(cb_module, input_port_name);
+    BasicPort input_port = module_manager.module_port(cb_module, input_port_id);
+
+    /* Create a port description for the output */
+    std::string output_port_name = generate_cb_module_track_port_name(cb_type,
+                                                                      itrack,  
+                                                                      OUT_PORT);
+    ModulePortId output_port_id = module_manager.find_module_port(cb_module, output_port_name);
+    BasicPort output_port = module_manager.module_port(cb_module, output_port_id);
+
+    /* Ensure port size matching */
+    VTR_ASSERT(1 == input_port.get_width());
+    VTR_ASSERT(input_port.get_width() == output_port.get_width());
+
+    /* Create short-wires: input port ---> output port
+     * Do short-wires: input port ---> middle output port 
+     */
+    for (size_t pin_id = 0; pin_id < input_port.pins().size(); ++pin_id) {
+      ModuleNetId net = module_manager.create_module_net(cb_module);
+      module_manager.add_module_net_source(cb_module, net, cb_module, 0, input_port_id, input_port.pins()[pin_id]); 
+      module_manager.add_module_net_sink(cb_module, net, cb_module, 0, output_port_id, output_port.pins()[pin_id]); 
+      /* Cache the module net */
+      input_port_to_module_nets[input_port_id] = net;
+    }
+  }
+
+  /* Add sub modules of routing multiplexers or direct interconnect*/
+  for (size_t iside = 0; iside < cb_ipin_sides.size(); ++iside) {
+    enum e_side cb_ipin_side = cb_ipin_sides[iside];
+    for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) {
+      build_connection_block_interc_modules(module_manager,  
+                                            cb_module, device_annotation,
+                                            rr_graph,
+                                            rr_gsb, cb_type, 
+                                            circuit_lib,
+                                            cb_ipin_side, inode,
+                                            input_port_to_module_nets);
+    }
+  }
+
+  /* Add global ports to the pb_module:
+   * This is a much easier job after adding sub modules (instances), 
+   * we just need to find all the global ports from the child modules and build a list of it
+   */
+  add_module_global_ports_from_child_modules(module_manager, cb_module);
+
+  /* Count shared SRAM ports from the sub-modules under this Verilog module
+   * This is a much easier job after adding sub modules (instances), 
+   * we just need to find all the I/O ports from the child modules and build a list of it
+   */
+  size_t module_num_shared_config_bits = find_module_num_shared_config_bits_from_child_modules(module_manager, cb_module); 
+  if (0 < module_num_shared_config_bits) {
+    add_reserved_sram_ports_to_module_manager(module_manager, cb_module, module_num_shared_config_bits);
+  }
+
+  /* Count SRAM ports from the sub-modules under this Verilog module
+   * This is a much easier job after adding sub modules (instances), 
+   * we just need to find all the I/O ports from the child modules and build a list of it
+   */
+  size_t module_num_config_bits = find_module_num_config_bits_from_child_modules(module_manager, cb_module, circuit_lib, sram_model, sram_orgz_type); 
+  if (0 < module_num_config_bits) {
+    add_sram_ports_to_module_manager(module_manager, cb_module, circuit_lib, sram_model, sram_orgz_type, module_num_config_bits);
+  }
+
+  /* Add all the nets to connect configuration ports from memory module to primitive modules
+   * This is a one-shot addition that covers all the memory modules in this primitive module!
+   */
+  if (0 < module_manager.configurable_children(cb_module).size()) {
+    add_module_nets_memory_config_bus(module_manager, cb_module, 
+                                      sram_orgz_type, circuit_lib.design_tech_type(sram_model));
+  }
+
+  VTR_LOGV(verbose, "Done\n");
+}
+
+
+/********************************************************************
+ * Iterate over all the connection blocks in a device
+ * and build a module for each of them 
+ *******************************************************************/
+static 
+void build_flatten_connection_block_modules(ModuleManager& module_manager, 
+                                            const DeviceContext& device_ctx,
+                                            const VprDeviceAnnotation& device_annotation,
+                                            const DeviceRRGSB& device_rr_gsb,
+                                            const CircuitLibrary& circuit_lib,
+                                            const e_config_protocol_type& sram_orgz_type,
+                                            const CircuitModelId& sram_model,
+                                            const t_rr_type& cb_type,
+                                            const bool& verbose) {
+  /* Build unique X-direction connection block modules */
+  vtr::Point<size_t> cb_range = device_rr_gsb.get_gsb_range();
+
+  for (size_t ix = 0; ix < cb_range.x(); ++ix) {
+    for (size_t iy = 0; iy < cb_range.y(); ++iy) {
+      /* Check if the connection block exists in the device!
+       * Some of them do NOT exist due to heterogeneous blocks (height > 1) 
+       * We will skip those modules
+       */
+      const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
+      if (false == rr_gsb.is_cb_exist(cb_type)) {
+        continue;
+      }
+      build_connection_block_module(module_manager, 
+                                    device_annotation,
+                                    device_ctx.rr_graph,
+                                    circuit_lib, 
+                                    sram_orgz_type, sram_model, 
+                                    rr_gsb, cb_type,
+                                    verbose);
+    }
+  }
+}
+
+/********************************************************************
+ * A top-level function of this file
+ * Build all the modules for global routing architecture of a FPGA fabric
+ * in a flatten way:
+ *   Each connection block and switch block will be generated as a unique module
+ * Covering:
+ * 1. Connection blocks
+ * 2. Switch blocks
+ *******************************************************************/
+void build_flatten_routing_modules(ModuleManager& module_manager,
+                                   const DeviceContext& device_ctx,
+                                   const VprDeviceAnnotation& device_annotation,
+                                   const DeviceRRGSB& device_rr_gsb,
+                                   const CircuitLibrary& circuit_lib,
+                                   const e_config_protocol_type& sram_orgz_type,
+                                   const CircuitModelId& sram_model,
+                                   const bool& verbose) {
+
+  vtr::ScopedStartFinishTimer timer("Build routing modules...");
+
+  vtr::Point<size_t> sb_range = device_rr_gsb.get_gsb_range();
+
+  /* Build unique switch block modules */
+  for (size_t ix = 0; ix < sb_range.x(); ++ix) {
+    for (size_t iy = 0; iy < sb_range.y(); ++iy) {
+      const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
+      if (false == rr_gsb.is_sb_exist()) {
+        continue;
+      }
+      build_switch_block_module(module_manager,
+                                device_annotation,
+                                device_ctx.rr_graph,
+                                circuit_lib, 
+                                sram_orgz_type, sram_model, 
+                                rr_gsb,
+                                verbose);
+    }
+  }
+
+  build_flatten_connection_block_modules(module_manager,
+                                         device_ctx, 
+                                         device_annotation, 
+                                         device_rr_gsb, 
+                                         circuit_lib, 
+                                         sram_orgz_type, sram_model, 
+                                         CHANX,
+                                         verbose);
+
+  build_flatten_connection_block_modules(module_manager,
+                                         device_ctx, 
+                                         device_annotation, 
+                                         device_rr_gsb, 
+                                         circuit_lib,
+                                         sram_orgz_type, sram_model, 
+                                         CHANY,
+                                         verbose);
+}
+
+/********************************************************************
+ * A top-level function of this file
+ * Build all the unique modules for global routing architecture of a FPGA fabric
+ * This function will use unique module list built in device_rr_gsb,
+ * to build only unique modules (in terms of graph connections) of
+ * 1. Connection blocks
+ * 2. Switch blocks
+ *
+ * Note: this function SHOULD be called only when 
+ * the option compact_routing_hierarchy is turned on!!!
+ *******************************************************************/
+void build_unique_routing_modules(ModuleManager& module_manager,
+                                  const DeviceContext& device_ctx,
+                                  const VprDeviceAnnotation& device_annotation,
+                                  const DeviceRRGSB& device_rr_gsb,
+                                  const CircuitLibrary& circuit_lib,
+                                  const e_config_protocol_type& sram_orgz_type,
+                                  const CircuitModelId& sram_model,
+                                  const bool& verbose) {
+
+  vtr::ScopedStartFinishTimer timer("Build unique routing modules...");
+
+  /* Build unique switch block modules */
+  for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_module(); ++isb) {
+    const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(isb);
+    build_switch_block_module(module_manager,
+                              device_annotation,
+                              device_ctx.rr_graph,
+                              circuit_lib, 
+                              sram_orgz_type, sram_model, 
+                              unique_mirror,
+                              verbose);
+  }
+
+  /* Build unique X-direction connection block modules */
+  for (size_t icb = 0; icb < device_rr_gsb.get_num_cb_unique_module(CHANX); ++icb) {
+    const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANX, icb);
+
+    build_connection_block_module(module_manager, 
+                                  device_annotation,
+                                  device_ctx.rr_graph,
+                                  circuit_lib,  
+                                  sram_orgz_type, sram_model, 
+                                  unique_mirror, CHANX,
+                                  verbose);
+  }
+
+  /* Build unique X-direction connection block modules */
+  for (size_t icb = 0; icb < device_rr_gsb.get_num_cb_unique_module(CHANY); ++icb) {
+    const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANY, icb);
+
+    build_connection_block_module(module_manager, 
+                                  device_annotation,
+                                  device_ctx.rr_graph,
+                                  circuit_lib, 
+                                  sram_orgz_type, sram_model, 
+                                  unique_mirror, CHANY,
+                                  verbose);
+  }
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fabric/build_routing_modules.h b/openfpga/src/fabric/build_routing_modules.h
new file mode 100644
index 000000000..d8eb09784
--- /dev/null
+++ b/openfpga/src/fabric/build_routing_modules.h
@@ -0,0 +1,41 @@
+#ifndef BUILD_ROUTING_MODULES_H
+#define BUILD_ROUTING_MODULES_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "vpr_context.h"
+#include "vpr_device_annotation.h"
+#include "device_rr_gsb.h"
+#include "mux_library.h"
+#include "circuit_library.h"
+#include "module_manager.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void build_flatten_routing_modules(ModuleManager& module_manager,
+                                   const DeviceContext& device_ctx,
+                                   const VprDeviceAnnotation& device_annotation,
+                                   const DeviceRRGSB& device_rr_gsb,
+                                   const CircuitLibrary& circuit_lib,
+                                   const e_config_protocol_type& sram_orgz_type,
+                                   const CircuitModelId& sram_model,
+                                   const bool& verbose);
+
+void build_unique_routing_modules(ModuleManager& module_manager,
+                                  const DeviceContext& device_ctx,
+                                  const VprDeviceAnnotation& device_annotation,
+                                  const DeviceRRGSB& device_rr_gsb,
+                                  const CircuitLibrary& circuit_lib,
+                                  const e_config_protocol_type& sram_orgz_type,
+                                  const CircuitModelId& sram_model,
+                                  const bool& verbose); 
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/utils/openfpga_rr_graph_utils.cpp b/openfpga/src/utils/openfpga_rr_graph_utils.cpp
index 21ec1b640..ba789b4da 100644
--- a/openfpga/src/utils/openfpga_rr_graph_utils.cpp
+++ b/openfpga/src/utils/openfpga_rr_graph_utils.cpp
@@ -81,4 +81,51 @@ std::vector<RRSwitchId> get_rr_graph_driver_switches(const RRGraph& rr_graph,
   return driver_switches;
 }
 
+/************************************************************************
+ * Find the driver nodes for a node in the rr_graph
+ ***********************************************************************/
+std::vector<RRNodeId> get_rr_graph_driver_nodes(const RRGraph& rr_graph,
+                                                const RRNodeId& node) {
+  std::vector<RRNodeId> driver_nodes;
+  for (const RREdgeId& edge : rr_graph.node_in_edges(node)) {
+    driver_nodes.push_back(rr_graph.edge_src_node(edge));
+  }
+
+  return driver_nodes;
+}
+
+/************************************************************************
+ * Find the configurable driver nodes for a node in the rr_graph
+ ***********************************************************************/
+std::vector<RRNodeId> get_rr_graph_configurable_driver_nodes(const RRGraph& rr_graph,
+                                                             const RRNodeId& node) {
+  std::vector<RRNodeId> driver_nodes;
+  for (const RREdgeId& edge : rr_graph.node_in_edges(node)) {
+    /* Bypass non-configurable edges */
+    if (false == rr_graph.edge_is_configurable(edge)) {
+      continue;
+    } 
+    driver_nodes.push_back(rr_graph.edge_src_node(edge));
+  }
+
+  return driver_nodes;
+}
+
+/************************************************************************
+ * Find the configurable driver nodes for a node in the rr_graph
+ ***********************************************************************/
+std::vector<RRNodeId> get_rr_graph_non_configurable_driver_nodes(const RRGraph& rr_graph,
+                                                                 const RRNodeId& node) {
+  std::vector<RRNodeId> driver_nodes;
+  for (const RREdgeId& edge : rr_graph.node_in_edges(node)) {
+    /* Bypass configurable edges */
+    if (true == rr_graph.edge_is_configurable(edge)) {
+      continue;
+    } 
+    driver_nodes.push_back(rr_graph.edge_src_node(edge));
+  }
+
+  return driver_nodes;
+}
+
 } /* end namespace openfpga */
diff --git a/openfpga/src/utils/openfpga_rr_graph_utils.h b/openfpga/src/utils/openfpga_rr_graph_utils.h
index 0c4d174c6..0466892f8 100644
--- a/openfpga/src/utils/openfpga_rr_graph_utils.h
+++ b/openfpga/src/utils/openfpga_rr_graph_utils.h
@@ -26,6 +26,15 @@ vtr::Point<size_t> get_track_rr_node_end_coordinate(const RRGraph& rr_graph,
 std::vector<RRSwitchId> get_rr_graph_driver_switches(const RRGraph& rr_graph,
                                                      const RRNodeId& node);
 
+std::vector<RRNodeId> get_rr_graph_driver_nodes(const RRGraph& rr_graph,
+                                                const RRNodeId& node);
+
+std::vector<RRNodeId> get_rr_graph_configurable_driver_nodes(const RRGraph& rr_graph,
+                                                             const RRNodeId& node);
+
+std::vector<RRNodeId> get_rr_graph_non_configurable_driver_nodes(const RRGraph& rr_graph,
+                                                                 const RRNodeId& node);
+
 } /* end namespace openfpga */
 
 #endif

From 36179b6cedc612c4b830a198d3c6ac975dff37cf Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 14 Feb 2020 10:00:24 -0700
Subject: [PATCH 136/645] start moving top-module builder. Now adapt the utils

---
 .../src/fabric/build_top_module_utils.cpp     | 90 +++++++++++++++++++
 openfpga/src/fabric/build_top_module_utils.h  | 31 +++++++
 2 files changed, 121 insertions(+)
 create mode 100644 openfpga/src/fabric/build_top_module_utils.cpp
 create mode 100644 openfpga/src/fabric/build_top_module_utils.h

diff --git a/openfpga/src/fabric/build_top_module_utils.cpp b/openfpga/src/fabric/build_top_module_utils.cpp
new file mode 100644
index 000000000..141d2dd54
--- /dev/null
+++ b/openfpga/src/fabric/build_top_module_utils.cpp
@@ -0,0 +1,90 @@
+/********************************************************************
+ * This file include most utilized functions for building the module 
+ * graph for FPGA fabric
+ *******************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+
+/* Headers from vpr library */
+#include "vpr_utils.h"
+
+#include "openfpga_naming.h"
+
+/* Module builder headers */
+#include "build_top_module_utils.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Generate the name for a grid block, by considering
+ * 1. if it locates on the border with given device size
+ * 2. its type
+ * 
+ * This function is mainly used in the top-level module generation
+ *******************************************************************/
+std::string generate_grid_block_module_name_in_top_module(const std::string& prefix,
+                                                          const DeviceGrid& grids,
+                                                          const vtr::Point<size_t>& grid_coord) {
+  /* Determine if the grid locates at the border */
+  vtr::Point<size_t> device_size(grids.width(), grids.height());
+  e_side border_side = find_grid_border_side(device_size, grid_coord);
+
+  return generate_grid_block_module_name(prefix, 
+                                         std::string(grids[grid_coord.x()][grid_coord.y()].type->name), 
+                                         is_io_type(grids[grid_coord.x()][grid_coord.y()].type),
+                                         border_side);
+}
+
+/********************************************************************
+ * Find the cb_type of a GSB in the top-level module 
+ * depending on the side of SB
+ * TOP/BOTTOM side: CHANY
+ * RIGHT/LEFT side: CHANX
+ *******************************************************************/
+t_rr_type find_top_module_cb_type_by_sb_side(const e_side& sb_side) {
+  VTR_ASSERT(NUM_SIDES != sb_side);
+
+  if ((TOP == sb_side) || (BOTTOM == sb_side)) {
+    return CHANY;
+  }
+
+  VTR_ASSERT((RIGHT == sb_side) || (LEFT == sb_side));
+  return CHANX;
+}
+
+/********************************************************************
+ * Find the GSB coordinate for a CB in the top-level module 
+ * depending on the side of a SB
+ * TODO: use vtr::Point<size_t> to replace DeviceCoordinator
+ *******************************************************************/
+vtr::Point<size_t> find_top_module_gsb_coordinate_by_sb_side(const RRGSB& rr_gsb,
+                                                             const e_side& sb_side) {
+  VTR_ASSERT(NUM_SIDES != sb_side);
+
+  vtr::Point<size_t> gsb_coordinate;
+
+  if ((TOP == sb_side) || (LEFT == sb_side)) {
+    gsb_coordinate.set_x(rr_gsb.get_x()); 
+    gsb_coordinate.set_y(rr_gsb.get_y()); 
+    return gsb_coordinate;
+  }
+ 
+  VTR_ASSERT((RIGHT == sb_side) || (BOTTOM == sb_side));
+
+  /* RIGHT side: x + 1 */
+  if (RIGHT == sb_side) {
+    gsb_coordinate.set_x(rr_gsb.get_x() + 1); 
+    gsb_coordinate.set_y(rr_gsb.get_y()); 
+  }
+
+  /* BOTTOM side: y - 1 */
+  if (BOTTOM == sb_side) {
+    gsb_coordinate.set_x(rr_gsb.get_x()); 
+    gsb_coordinate.set_y(rr_gsb.get_y() - 1); 
+  }
+
+  return gsb_coordinate;
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fabric/build_top_module_utils.h b/openfpga/src/fabric/build_top_module_utils.h
new file mode 100644
index 000000000..c0bcbcee5
--- /dev/null
+++ b/openfpga/src/fabric/build_top_module_utils.h
@@ -0,0 +1,31 @@
+#ifndef BUILD_TOP_MODULE_UTILS_H
+#define BUILD_TOP_MODULE_UTILS_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <vector>
+#include <string>
+#include "vtr_geometry.h"
+#include "device_grid.h"
+#include "rr_gsb.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+std::string generate_grid_block_module_name_in_top_module(const std::string& prefix,
+                                                          const DeviceGrid& grids,
+                                                          const vtr::Point<size_t>& grid_coord);
+
+t_rr_type find_top_module_cb_type_by_sb_side(const e_side& sb_side);
+
+vtr::Point<size_t> find_top_module_gsb_coordinate_by_sb_side(const RRGSB& rr_gsb,
+                                                             const e_side& sb_side);
+
+} /* end namespace openfpga */
+
+#endif

From 9dc9c2c9f793fe6835157f6b924d4d2d9d70a603 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 14 Feb 2020 10:45:24 -0700
Subject: [PATCH 137/645] add build top module connection functions

---
 .../fabric/build_top_module_connection.cpp    | 676 ++++++++++++++++++
 .../src/fabric/build_top_module_connection.h  |  35 +
 openfpga/src/utils/rr_gsb_utils.cpp           |  39 +
 openfpga/src/utils/rr_gsb_utils.h             |  23 +
 4 files changed, 773 insertions(+)
 create mode 100644 openfpga/src/fabric/build_top_module_connection.cpp
 create mode 100644 openfpga/src/fabric/build_top_module_connection.h
 create mode 100644 openfpga/src/utils/rr_gsb_utils.cpp
 create mode 100644 openfpga/src/utils/rr_gsb_utils.h

diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp
new file mode 100644
index 000000000..f1895305e
--- /dev/null
+++ b/openfpga/src/fabric/build_top_module_connection.cpp
@@ -0,0 +1,676 @@
+/********************************************************************
+ * This file include most utilized functions for building connections 
+ * inside the module graph for FPGA fabric
+ *******************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_side_manager.h"
+
+#include "openfpga_reserved_words.h"
+#include "openfpga_naming.h"
+#include "pb_type_utils.h"
+#include "rr_gsb_utils.h"
+
+#include "build_top_module_utils.h"
+#include "build_top_module_connection.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Add module nets to connect a GSB to adjacent grid ports/pins 
+ * as well as connection blocks
+ * This function will create nets for the following types of connections
+ * between grid output pins of Switch block and adjacent grids
+ * In this case, the net source is the grid pin, while the net sink
+ * is the switch block pin
+ *    
+ *    +------------+                +------------+
+ *    |            |                |            |
+ *    |    Grid    |                |    Grid    |
+ *    |  [x][y+1]  |                | [x+1][y+1] |
+ *    |            |----+      +----|            |
+ *    +------------+    |      |    +------------+
+ *           |          v      v         |
+ *           |       +------------+      |
+ *           +------>|            |<-----+
+ *                   |   Switch   |
+ *                   |   Block    |
+ *           +------>|   [x][y]   |<-----+
+ *           |       +------------+      |
+ *           |          ^     ^          |
+ *           |          |     |          |
+ *    +------------+    |     |     +------------+
+ *    |            |----+     +-----|            |
+ *    |    Grid    |                |    Grid    |
+ *    |   [x][y]   |                |  [x+1][y]  |
+ *    |            |                |            |
+ *    +------------+                +------------+
+
+ *
+ *******************************************************************/
+static 
+void add_top_module_nets_connect_grids_and_sb(ModuleManager& module_manager, 
+                                              const ModuleId& top_module, 
+                                              const DeviceGrid& grids,
+                                              const vtr::Matrix<size_t>& grid_instance_ids,
+                                              const RRGraph& rr_graph,
+                                              const DeviceRRGSB& device_rr_gsb,
+                                              const RRGSB& rr_gsb, 
+                                              const vtr::Matrix<size_t>& sb_instance_ids,
+                                              const bool& compact_routing_hierarchy) {
+
+  /* We could have two different coordinators, one is the instance, the other is the module */
+  vtr::Point<size_t> instance_sb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
+  vtr::Point<size_t> module_gsb_coordinate(rr_gsb.get_x(), rr_gsb.get_y());
+
+  /* If we use compact routing hierarchy, we should find the unique module of CB, which is added to the top module */
+  if (true == compact_routing_hierarchy) {
+    vtr::Point<size_t> gsb_coord(rr_gsb.get_x(), rr_gsb.get_y());
+    const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(gsb_coord);
+    module_gsb_coordinate.set_x(unique_mirror.get_x()); 
+    module_gsb_coordinate.set_y(unique_mirror.get_y()); 
+  } 
+
+  /* This is the source cb that is added to the top module */
+  const RRGSB& module_sb = device_rr_gsb.get_gsb(module_gsb_coordinate);
+  vtr::Point<size_t> module_sb_coordinate(module_sb.get_sb_x(), module_sb.get_sb_y());
+
+  /* Collect sink-related information */
+  std::string sink_sb_module_name = generate_switch_block_module_name(module_sb_coordinate);
+  ModuleId sink_sb_module = module_manager.find_module(sink_sb_module_name);
+  VTR_ASSERT(true == module_manager.valid_module_id(sink_sb_module));
+  size_t sink_sb_instance = sb_instance_ids[instance_sb_coordinate.x()][instance_sb_coordinate.y()];
+
+  /* Connect grid output pins (OPIN) to switch block grid pins */
+  for (size_t side = 0; side < module_sb.get_num_sides(); ++side) {
+    SideManager side_manager(side);
+    for (size_t inode = 0; inode < module_sb.get_num_opin_nodes(side_manager.get_side()); ++inode) {
+      /* Collect source-related information */
+      /* Generate the grid module name by considering if it locates on the border */
+      vtr::Point<size_t> grid_coordinate(rr_graph.node_xlow(rr_gsb.get_opin_node(side_manager.get_side(), inode)), 
+                                         rr_graph.node_ylow(rr_gsb.get_opin_node(side_manager.get_side(), inode)));
+      std::string src_grid_module_name = generate_grid_block_module_name_in_top_module(std::string(GRID_MODULE_NAME_PREFIX), grids, grid_coordinate); 
+      ModuleId src_grid_module = module_manager.find_module(src_grid_module_name);
+      VTR_ASSERT(true == module_manager.valid_module_id(src_grid_module));
+      size_t src_grid_instance = grid_instance_ids[grid_coordinate.x()][grid_coordinate.y()];
+      size_t src_grid_pin_index = rr_graph.node_pin_num(rr_gsb.get_opin_node(side_manager.get_side(), inode));
+      size_t src_grid_pin_width = grids[grid_coordinate.x()][grid_coordinate.y()].type->pin_width_offset[src_grid_pin_index];
+      size_t src_grid_pin_height = grids[grid_coordinate.x()][grid_coordinate.y()].type->pin_height_offset[src_grid_pin_index];
+      std::string src_grid_port_name = generate_grid_port_name(grid_coordinate, src_grid_pin_width, src_grid_pin_height,
+                                                               rr_graph.node_side(rr_gsb.get_opin_node(side_manager.get_side(), inode)),
+                                                               src_grid_pin_index, false);
+      ModulePortId src_grid_port_id = module_manager.find_module_port(src_grid_module, src_grid_port_name);
+      VTR_ASSERT(true == module_manager.valid_module_port_id(src_grid_module, src_grid_port_id));
+      BasicPort src_grid_port = module_manager.module_port(src_grid_module, src_grid_port_id); 
+
+      /* Collect sink-related information */
+      vtr::Point<size_t> sink_sb_port_coord(rr_graph.node_xlow(module_sb.get_opin_node(side_manager.get_side(), inode)),
+                                            rr_graph.node_ylow(module_sb.get_opin_node(side_manager.get_side(), inode)));
+      std::string sink_sb_port_name = generate_sb_module_grid_port_name(side_manager.get_side(),
+                                                                        rr_graph.node_side(module_sb.get_opin_node(side_manager.get_side(), inode)),
+                                                                        src_grid_pin_index); 
+      ModulePortId sink_sb_port_id = module_manager.find_module_port(sink_sb_module, sink_sb_port_name);
+      VTR_ASSERT(true == module_manager.valid_module_port_id(sink_sb_module, sink_sb_port_id));
+      BasicPort sink_sb_port =  module_manager.module_port(sink_sb_module, sink_sb_port_id); 
+
+      /* Source and sink port should match in size */
+      VTR_ASSERT(src_grid_port.get_width() == sink_sb_port.get_width());
+      
+      /* Create a net for each pin */
+      for (size_t pin_id = 0; pin_id < src_grid_port.pins().size(); ++pin_id) {
+        ModuleNetId net = module_manager.create_module_net(top_module);
+        /* Configure the net source */
+        module_manager.add_module_net_source(top_module, net, src_grid_module, src_grid_instance, src_grid_port_id, src_grid_port.pins()[pin_id]);
+        /* Configure the net sink */
+        module_manager.add_module_net_sink(top_module, net, sink_sb_module, sink_sb_instance, sink_sb_port_id, sink_sb_port.pins()[pin_id]);
+      }
+    } 
+  }
+}
+
+/********************************************************************
+ * Add module nets to connect a GSB to adjacent grid ports/pins 
+ * as well as connection blocks
+ * This function will create nets for the following types of connections
+ * between grid output pins of Switch block and adjacent grids
+ * In this case, the net source is the grid pin, while the net sink
+ * is the switch block pin
+ *
+ * In particular, this function considers the duplicated output pins of grids
+ * when creating the connecting nets.
+ * The follow figure shows the different pin postfix to be considered when
+ * connecting the grid pins to SB inputs
+ *    
+ *    +------------+                +------------+
+ *    |            |                |            |
+ *    |    Grid    |                |    Grid    |
+ *    |  [x][y+1]  |lower      lower| [x+1][y+1] |
+ *    |            |----+      +----|            |
+ *    +------------+    |      |    +------------+
+ *           |lower     v      v         |upper
+ *           |       +------------+      |
+ *           +------>|            |<-----+
+ *                   |   Switch   |
+ *                   |   Block    |
+ *           +------>|   [x][y]   |<-----+
+ *           |       +------------+      |
+ *           |          ^     ^          |
+ *           |lower     |     |          |upper
+ *    +------------+    |     |     +------------+
+ *    |            |----+     +-----|            |
+ *    |    Grid    |upper     upper |    Grid    |
+ *    |   [x][y]   |                |  [x+1][y]  |
+ *    |            |                |            |
+ *    +------------+                +------------+
+ *
+ *******************************************************************/
+static 
+void add_top_module_nets_connect_grids_and_sb_with_duplicated_pins(ModuleManager& module_manager, 
+                                                                   const ModuleId& top_module, 
+                                                                   const DeviceGrid& grids,
+                                                                   const vtr::Matrix<size_t>& grid_instance_ids,
+                                                                   const RRGraph& rr_graph,
+                                                                   const DeviceRRGSB& device_rr_gsb,
+                                                                   const RRGSB& rr_gsb, 
+                                                                   const vtr::Matrix<size_t>& sb_instance_ids,
+                                                                   const bool& compact_routing_hierarchy) {
+
+  /* We could have two different coordinators, one is the instance, the other is the module */
+  vtr::Point<size_t> instance_sb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
+  vtr::Point<size_t> module_gsb_coordinate(rr_gsb.get_x(), rr_gsb.get_y());
+
+  /* If we use compact routing hierarchy, we should find the unique module of CB, which is added to the top module */
+  if (true == compact_routing_hierarchy) {
+    vtr::Point<size_t> gsb_coord(rr_gsb.get_x(), rr_gsb.get_y());
+    const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(gsb_coord);
+    module_gsb_coordinate.set_x(unique_mirror.get_x()); 
+    module_gsb_coordinate.set_y(unique_mirror.get_y()); 
+  } 
+
+  /* This is the source cb that is added to the top module */
+  const RRGSB& module_sb = device_rr_gsb.get_gsb(module_gsb_coordinate);
+  vtr::Point<size_t> module_sb_coordinate(module_sb.get_sb_x(), module_sb.get_sb_y());
+
+  /* Collect sink-related information */
+  std::string sink_sb_module_name = generate_switch_block_module_name(module_sb_coordinate);
+  ModuleId sink_sb_module = module_manager.find_module(sink_sb_module_name);
+  VTR_ASSERT(true == module_manager.valid_module_id(sink_sb_module));
+  size_t sink_sb_instance = sb_instance_ids[instance_sb_coordinate.x()][instance_sb_coordinate.y()];
+
+  /* Create a truth table for the postfix to be used regarding to the different side of switch blocks */
+  std::map<e_side, bool> sb_side2postfix_map;
+  /* Boolean variable "true" indicates the upper postfix in naming functions 
+   * Boolean variable "false" indicates the lower postfix in naming functions 
+   */
+  sb_side2postfix_map[TOP] = false;
+  sb_side2postfix_map[RIGHT] = true;
+  sb_side2postfix_map[BOTTOM] = true;
+  sb_side2postfix_map[LEFT] = false;
+
+  /* Connect grid output pins (OPIN) to switch block grid pins */
+  for (size_t side = 0; side < module_sb.get_num_sides(); ++side) {
+    SideManager side_manager(side);
+    for (size_t inode = 0; inode < module_sb.get_num_opin_nodes(side_manager.get_side()); ++inode) {
+      /* Collect source-related information */
+      /* Generate the grid module name by considering if it locates on the border */
+      vtr::Point<size_t> grid_coordinate(rr_graph.node_xlow(rr_gsb.get_opin_node(side_manager.get_side(), inode)),
+                                         rr_graph.node_ylow(rr_gsb.get_opin_node(side_manager.get_side(), inode)));
+      std::string src_grid_module_name = generate_grid_block_module_name_in_top_module(std::string(GRID_MODULE_NAME_PREFIX), grids, grid_coordinate); 
+      ModuleId src_grid_module = module_manager.find_module(src_grid_module_name);
+      VTR_ASSERT(true == module_manager.valid_module_id(src_grid_module));
+      size_t src_grid_instance = grid_instance_ids[grid_coordinate.x()][grid_coordinate.y()];
+      size_t src_grid_pin_index = rr_graph.node_pin_num(rr_gsb.get_opin_node(side_manager.get_side(), inode));
+      size_t src_grid_pin_width = grids[grid_coordinate.x()][grid_coordinate.y()].type->pin_width_offset[src_grid_pin_index];
+      size_t src_grid_pin_height = grids[grid_coordinate.x()][grid_coordinate.y()].type->pin_height_offset[src_grid_pin_index];
+
+      /* Pins for direct connection are NOT duplicated.
+       * Follow the traditional recipe when adding nets!  
+       * Xifan: I assume that each direct connection pin must have Fc=0. 
+       * For other duplicated pins, we follow the new naming
+       */
+      std::string src_grid_port_name;
+      if (0. == grids[grid_coordinate.x()][grid_coordinate.y()].type->fc_specs[src_grid_pin_index].fc_value) {
+        src_grid_port_name = generate_grid_port_name(grid_coordinate, src_grid_pin_width, src_grid_pin_height, 
+                                                     rr_graph.node_side(rr_gsb.get_opin_node(side_manager.get_side(), inode)),
+                                                     src_grid_pin_index, false);
+      } else {
+       src_grid_port_name = generate_grid_duplicated_port_name(src_grid_pin_width, src_grid_pin_height, 
+                                                               rr_graph.node_side(rr_gsb.get_opin_node(side_manager.get_side(), inode)),
+                                                               src_grid_pin_index, sb_side2postfix_map[side_manager.get_side()]);
+      }
+      ModulePortId src_grid_port_id = module_manager.find_module_port(src_grid_module, src_grid_port_name);
+      VTR_ASSERT(true == module_manager.valid_module_port_id(src_grid_module, src_grid_port_id));
+      BasicPort src_grid_port = module_manager.module_port(src_grid_module, src_grid_port_id); 
+
+      /* Collect sink-related information */
+      vtr::Point<size_t> sink_sb_port_coord(rr_graph.node_xlow(module_sb.get_opin_node(side_manager.get_side(), inode)),
+                                            rr_graph.node_ylow(module_sb.get_opin_node(side_manager.get_side(), inode)));
+      std::string sink_sb_port_name = generate_sb_module_grid_port_name(side_manager.get_side(),
+                                                                        rr_graph.node_side(module_sb.get_opin_node(side_manager.get_side(), inode)),
+                                                                        src_grid_pin_index); 
+      ModulePortId sink_sb_port_id = module_manager.find_module_port(sink_sb_module, sink_sb_port_name);
+      VTR_ASSERT(true == module_manager.valid_module_port_id(sink_sb_module, sink_sb_port_id));
+      BasicPort sink_sb_port =  module_manager.module_port(sink_sb_module, sink_sb_port_id); 
+
+      /* Source and sink port should match in size */
+      VTR_ASSERT(src_grid_port.get_width() == sink_sb_port.get_width());
+      
+      /* Create a net for each pin */
+      for (size_t pin_id = 0; pin_id < src_grid_port.pins().size(); ++pin_id) {
+        ModuleNetId net = module_manager.create_module_net(top_module);
+        /* Configure the net source */
+        module_manager.add_module_net_source(top_module, net, src_grid_module, src_grid_instance, src_grid_port_id, src_grid_port.pins()[pin_id]);
+        /* Configure the net sink */
+        module_manager.add_module_net_sink(top_module, net, sink_sb_module, sink_sb_instance, sink_sb_port_id, sink_sb_port.pins()[pin_id]);
+      }
+    } 
+  }
+}
+
+/********************************************************************
+ * This function will create nets for the connections
+ * between grid input pins and connection blocks
+ * In this case, the net source is the connection block pin, 
+ * while the net sink is the grid input
+ *
+ *    +------------+      +------------------+      +------------+
+ *    |            |      |                  |      |            |
+ *    |    Grid    |<-----| Connection Block |----->|    Grid    |
+ *    |  [x][y+1]  |      |  Y-direction     |      | [x+1][y+1] | 
+ *    |            |      |    [x][y+1]      |      |            |
+ *    +------------+      +------------------+      +------------+
+ *          ^                                            
+ *          |                                              
+ *    +------------+      +------------------+      
+ *    | Connection |      |                  |    
+ *    |    Block   |      |  Switch Block    |  
+ *    | X-direction|      |      [x][y]      |    
+ *    |   [x][y]   |      |                  |     
+ *    +------------+      +------------------+ 
+ *          |                           
+ *          v                           
+ *    +------------+    
+ *    |            |    
+ *    |    Grid    |    
+ *    |   [x][y]   |   
+ *    |            |      
+ *    +------------+    
+ *
+ *
+ *    Relationship between source connection block and its unique module 
+ *    Take an example of a CBY
+ *
+ *    grid_pin name should follow unique module of Grid[x][y+1]
+ *    cb_pin name should follow unique module of CBY[x][y+1]
+ *    
+ *    However, instace id should follow the origin Grid and Connection block 
+ *                    
+ *                    
+ *    +------------+             +------------------+ 
+ *    |            |             |                  | 
+ *    |    Grid    |<------------| Connection Block |
+ *    |  [x][y+1]  |             |  Y-direction     | 
+ *    |            |             |    [x][y+1]      |
+ *    +------------+             +------------------+
+ *                                         ^
+ *                                        || unique mirror
+ *    +------------+             +------------------+ 
+ *    |            |             |                  | 
+ *    |    Grid    |<------------| Connection Block |
+ *    |  [i][j+1]  |             |  Y-direction     | 
+ *    |            |             |    [i][j+1]      |
+ *    +------------+             +------------------+
+ *
+ *******************************************************************/
+static 
+void add_top_module_nets_connect_grids_and_cb(ModuleManager& module_manager, 
+                                              const ModuleId& top_module, 
+                                              const DeviceGrid& grids,
+                                              const vtr::Matrix<size_t>& grid_instance_ids,
+                                              const RRGraph& rr_graph,
+                                              const DeviceRRGSB& device_rr_gsb,
+                                              const RRGSB& rr_gsb, 
+                                              const t_rr_type& cb_type,
+                                              const vtr::Matrix<size_t>& cb_instance_ids,
+                                              const bool& compact_routing_hierarchy) {
+  /* We could have two different coordinators, one is the instance, the other is the module */
+  vtr::Point<size_t> instance_cb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type));
+  vtr::Point<size_t> module_gsb_coordinate(rr_gsb.get_x(), rr_gsb.get_y());
+
+  /* Skip those Connection blocks that do not exist */
+  if (false == rr_gsb.is_cb_exist(cb_type)) {
+    return;
+  }
+
+  /* Skip if the cb does not contain any configuration bits! */
+  if (true == connection_block_contain_only_routing_tracks(rr_gsb, cb_type)) {
+    return;
+  }
+
+  /* If we use compact routing hierarchy, we should find the unique module of CB, which is added to the top module */
+  if (true == compact_routing_hierarchy) {
+    vtr::Point<size_t> gsb_coord(rr_gsb.get_x(), rr_gsb.get_y());
+    const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(cb_type, gsb_coord);
+    module_gsb_coordinate.set_x(unique_mirror.get_x()); 
+    module_gsb_coordinate.set_y(unique_mirror.get_y()); 
+  } 
+
+  /* This is the source cb that is added to the top module */
+  const RRGSB& module_cb = device_rr_gsb.get_gsb(module_gsb_coordinate);
+  vtr::Point<size_t> module_cb_coordinate(module_cb.get_cb_x(cb_type), module_cb.get_cb_y(cb_type));
+
+  /* Collect source-related information */
+  std::string src_cb_module_name = generate_connection_block_module_name(cb_type, module_cb_coordinate);
+  ModuleId src_cb_module = module_manager.find_module(src_cb_module_name);
+  VTR_ASSERT(true == module_manager.valid_module_id(src_cb_module));
+  /* Instance id should follow the instance cb coordinate */
+  size_t src_cb_instance = cb_instance_ids[instance_cb_coordinate.x()][instance_cb_coordinate.y()];
+
+  /* Iterate over the output pins of the Connection Block */
+  std::vector<enum e_side> cb_ipin_sides = module_cb.get_cb_ipin_sides(cb_type);
+  for (size_t iside = 0; iside < cb_ipin_sides.size(); ++iside) {
+    enum e_side cb_ipin_side = cb_ipin_sides[iside];
+    for (size_t inode = 0; inode < module_cb.get_num_ipin_nodes(cb_ipin_side); ++inode) {
+      /* Collect source-related information */
+      RRNodeId module_ipin_node = module_cb.get_ipin_node(cb_ipin_side, inode);
+      vtr::Point<size_t> cb_src_port_coord(rr_graph.node_xlow(module_ipin_node),
+                                           rr_graph.node_ylow(module_ipin_node));
+      std::string src_cb_port_name = generate_cb_module_grid_port_name(cb_ipin_side,
+                                                                       rr_graph.node_pin_num(module_ipin_node)); 
+      ModulePortId src_cb_port_id = module_manager.find_module_port(src_cb_module, src_cb_port_name);
+      VTR_ASSERT(true == module_manager.valid_module_port_id(src_cb_module, src_cb_port_id));
+      BasicPort src_cb_port = module_manager.module_port(src_cb_module, src_cb_port_id); 
+
+      /* Collect sink-related information */
+      /* Note that we use the instance cb pin here!!!
+       * because it has the correct coordinator for the grid!!! 
+       */
+      RRNodeId instance_ipin_node = rr_gsb.get_ipin_node(cb_ipin_side, inode);
+      vtr::Point<size_t> grid_coordinate(rr_graph.node_xlow(instance_ipin_node), 
+                                         rr_graph.node_ylow(instance_ipin_node));
+      std::string sink_grid_module_name = generate_grid_block_module_name_in_top_module(std::string(GRID_MODULE_NAME_PREFIX), grids, grid_coordinate); 
+      ModuleId sink_grid_module = module_manager.find_module(sink_grid_module_name);
+      VTR_ASSERT(true == module_manager.valid_module_id(sink_grid_module));
+      size_t sink_grid_instance = grid_instance_ids[grid_coordinate.x()][grid_coordinate.y()];
+      size_t sink_grid_pin_index = rr_graph.node_pin_num(instance_ipin_node);
+      size_t sink_grid_pin_width = grids[grid_coordinate.x()][grid_coordinate.y()].type->pin_width_offset[sink_grid_pin_index];
+      size_t sink_grid_pin_height = grids[grid_coordinate.x()][grid_coordinate.y()].type->pin_height_offset[sink_grid_pin_index];
+      std::string sink_grid_port_name = generate_grid_port_name(grid_coordinate, sink_grid_pin_width, sink_grid_pin_height,
+                                                                rr_graph.node_side(rr_gsb.get_ipin_node(cb_ipin_side, inode)),
+                                                                sink_grid_pin_index, false);
+      ModulePortId sink_grid_port_id = module_manager.find_module_port(sink_grid_module, sink_grid_port_name);
+      VTR_ASSERT(true == module_manager.valid_module_port_id(sink_grid_module, sink_grid_port_id));
+      BasicPort sink_grid_port = module_manager.module_port(sink_grid_module, sink_grid_port_id); 
+
+      /* Source and sink port should match in size */
+      VTR_ASSERT(src_cb_port.get_width() == sink_grid_port.get_width());
+      
+      /* Create a net for each pin */
+      for (size_t pin_id = 0; pin_id < src_cb_port.pins().size(); ++pin_id) {
+        ModuleNetId net = module_manager.create_module_net(top_module);
+        /* Configure the net source */
+        module_manager.add_module_net_source(top_module, net, src_cb_module, src_cb_instance, src_cb_port_id, src_cb_port.pins()[pin_id]);
+        /* Configure the net sink */
+        module_manager.add_module_net_sink(top_module, net, sink_grid_module, sink_grid_instance, sink_grid_port_id, sink_grid_port.pins()[pin_id]);
+      }
+    }
+  }
+}
+
+/********************************************************************
+ * This function will create nets for the connections
+ * between connection block and switch block pins
+ * Two cases should be considered:
+ * a. The switch block pin denotes an input of a routing track
+ * The net source is an output of a routing track of connection block
+ * while the net sink is an input of a routing track of switch block
+ * b. The switch block pin denotes an output of a routing track
+ * The net source is an output of routing track of switch block 
+ * while the net sink is an input of a routing track of connection block
+ *
+ *    +------------+      +------------------+      +------------+
+ *    |            |      |                  |      |            |
+ *    |    Grid    |      | Connection Block |      |    Grid    |
+ *    |  [x][y+1]  |      |  Y-direction     |      | [x+1][y+1] | 
+ *    |            |      |    [x][y+1]      |      |            |
+ *    +------------+      +------------------+      +------------+
+ *                             |       ^
+ *                             v       |
+ *    +------------+      +------------------+      +------------+
+ *    | Connection |----->|                  |----->| Connection |
+ *    |    Block   |      |  Switch Block    |      |  Block     |
+ *    | X-direction|<-----|      [x][y]      |<-----| X-direction|
+ *    |   [x][y]   |      |                  |      | [x+1][y]   |
+ *    +------------+      +------------------+      +------------+
+ *                            |        ^
+ *                            v        |
+ *    +------------+      +------------------+      +------------+
+ *    |            |      |                  |      |            |
+ *    |    Grid    |      | Connection Block |      |    Grid    |
+ *    |   [x][y]   |      |   Y-direction    |      |  [x][y+1]  |
+ *    |            |      |    [x][y]        |      |            |
+ *    +------------+      +------------------+      +------------+
+ *
+ * Here, to achieve the purpose, we can simply iterate over the 
+ * four sides of switch block and make connections to adjancent 
+ * connection blocks
+ *
+ *******************************************************************/
+static 
+void add_top_module_nets_connect_sb_and_cb(ModuleManager& module_manager, 
+                                           const ModuleId& top_module, 
+                                           const RRGraph& rr_graph,
+                                           const DeviceRRGSB& device_rr_gsb,
+                                           const RRGSB& rr_gsb, 
+                                           const vtr::Matrix<size_t>& sb_instance_ids,
+                                           const std::map<t_rr_type, vtr::Matrix<size_t>>& cb_instance_ids,
+                                           const bool& compact_routing_hierarchy) {
+  /* We could have two different coordinators, one is the instance, the other is the module */
+  vtr::Point<size_t> instance_sb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
+  vtr::Point<size_t> module_gsb_sb_coordinate(rr_gsb.get_x(), rr_gsb.get_y());
+
+  /* Skip those Switch blocks that do not exist */
+  if (false == rr_gsb.is_sb_exist()) {
+    return;
+  }
+
+  /* If we use compact routing hierarchy, we should find the unique module of CB, which is added to the top module */
+  if (true == compact_routing_hierarchy) {
+    vtr::Point<size_t> gsb_coord(rr_gsb.get_x(), rr_gsb.get_y());
+    const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(gsb_coord);
+    module_gsb_sb_coordinate.set_x(unique_mirror.get_x()); 
+    module_gsb_sb_coordinate.set_y(unique_mirror.get_y()); 
+  } 
+
+  /* This is the source cb that is added to the top module */
+  const RRGSB& module_sb = device_rr_gsb.get_gsb(module_gsb_sb_coordinate);
+  vtr::Point<size_t> module_sb_coordinate(module_sb.get_sb_x(), module_sb.get_sb_y());
+  std::string sb_module_name = generate_switch_block_module_name(module_sb_coordinate);
+  ModuleId sb_module_id = module_manager.find_module(sb_module_name);
+  VTR_ASSERT(true == module_manager.valid_module_id(sb_module_id));
+  size_t sb_instance = sb_instance_ids[instance_sb_coordinate.x()][instance_sb_coordinate.y()];
+
+  /* Connect grid output pins (OPIN) to switch block grid pins */
+  for (size_t side = 0; side < module_sb.get_num_sides(); ++side) {
+    SideManager side_manager(side);
+    /* Iterate over the routing tracks on this side */
+    /* Early skip: if there is no routing tracks at this side */
+    if (0 == module_sb.get_chan_width(side_manager.get_side())) {
+      continue;
+    }
+    /* Find the Connection Block module */
+    /* We find the original connection block and then spot its unique mirror! 
+     * Do NOT use module_sb here!!!
+     */
+    t_rr_type cb_type = find_top_module_cb_type_by_sb_side(side_manager.get_side());
+    vtr::Point<size_t> instance_gsb_cb_coordinate = find_top_module_gsb_coordinate_by_sb_side(rr_gsb, side_manager.get_side());
+    vtr::Point<size_t> module_gsb_cb_coordinate = find_top_module_gsb_coordinate_by_sb_side(rr_gsb, side_manager.get_side());
+
+    /* Skip those Connection blocks that do not exist:
+     * 1. The CB does not exist in the device level! We should skip! 
+     * 2. The CB does exist but we need to make sure if the GSB includes such CBs 
+     *    For TOP and LEFT side, check the existence using RRGSB method is_cb_exist()
+     *    FOr RIGHT and BOTTOM side, find the adjacent RRGSB and then use is_cb_exist()
+     */
+    if ( TOP == side_manager.get_side() || LEFT == side_manager.get_side() ) {
+      if ( false == rr_gsb.is_cb_exist(cb_type)) {
+        continue;
+      }
+    }
+
+    if ( RIGHT == side_manager.get_side() || BOTTOM == side_manager.get_side() ) {
+      const RRGSB& adjacent_gsb = device_rr_gsb.get_gsb(module_gsb_cb_coordinate);
+      if ( false == adjacent_gsb.is_cb_exist(cb_type)) {
+        continue;
+      }
+    }
+
+    /* If we use compact routing hierarchy, we should find the unique module of CB, which is added to the top module */
+    if (true == compact_routing_hierarchy) {
+      const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(cb_type, module_gsb_cb_coordinate);
+      module_gsb_cb_coordinate.set_x(unique_mirror.get_x()); 
+      module_gsb_cb_coordinate.set_y(unique_mirror.get_y()); 
+    } 
+  
+    const RRGSB& module_cb = device_rr_gsb.get_gsb(module_gsb_cb_coordinate);
+    vtr::Point<size_t> module_cb_coordinate(module_cb.get_cb_x(cb_type), module_cb.get_cb_y(cb_type));
+    std::string cb_module_name = generate_connection_block_module_name(cb_type, module_cb_coordinate);
+    ModuleId cb_module_id = module_manager.find_module(cb_module_name);
+    VTR_ASSERT(true == module_manager.valid_module_id(cb_module_id));
+    const RRGSB& instance_cb = device_rr_gsb.get_gsb(instance_gsb_cb_coordinate);
+    vtr::Point<size_t> instance_cb_coordinate(instance_cb.get_cb_x(cb_type), instance_cb.get_cb_y(cb_type));
+    size_t cb_instance = cb_instance_ids.at(cb_type)[instance_cb_coordinate.x()][instance_cb_coordinate.y()];
+ 
+    for (size_t itrack = 0; itrack < module_sb.get_chan_width(side_manager.get_side()); ++itrack) {
+      std::string sb_port_name = generate_sb_module_track_port_name(rr_graph.node_type(module_sb.get_chan_node(side_manager.get_side(), itrack)),
+                                                                    side_manager.get_side(), itrack,  
+                                                                    module_sb.get_chan_node_direction(side_manager.get_side(), itrack));
+      /* Prepare SB-related port information */
+      ModulePortId sb_port_id = module_manager.find_module_port(sb_module_id, sb_port_name); 
+      VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module_id, sb_port_id));
+      BasicPort sb_port = module_manager.module_port(sb_module_id, sb_port_id);
+     
+      /* Prepare CB-related port information */ 
+      PORTS cb_port_direction = OUT_PORT;
+      /* The cb port direction should be opposite to the sb port !!! */
+      if (OUT_PORT == module_sb.get_chan_node_direction(side_manager.get_side(), itrack)) {
+        cb_port_direction = IN_PORT;
+      } else {
+        VTR_ASSERT(IN_PORT == module_sb.get_chan_node_direction(side_manager.get_side(), itrack));
+      }  
+      std::string cb_port_name = generate_cb_module_track_port_name(cb_type,
+                                                                    itrack,  
+                                                                    cb_port_direction);
+      ModulePortId cb_port_id = module_manager.find_module_port(cb_module_id, cb_port_name); 
+      VTR_ASSERT(true == module_manager.valid_module_port_id(cb_module_id, cb_port_id));
+      BasicPort cb_port = module_manager.module_port(cb_module_id, cb_port_id);
+
+      /* Source and sink port should match in size */
+      VTR_ASSERT(cb_port.get_width() == sb_port.get_width());
+      
+      /* Create a net for each pin */
+      for (size_t pin_id = 0; pin_id < cb_port.pins().size(); ++pin_id) {
+        ModuleNetId net = module_manager.create_module_net(top_module);
+        /* Configure the net source and sink:
+         * If sb port is an output (source), cb port is an input (sink) 
+         * If sb port is an input (sink), cb port is an output (source) 
+         */
+        if (OUT_PORT == module_sb.get_chan_node_direction(side_manager.get_side(), itrack)) {
+          module_manager.add_module_net_sink(top_module, net, cb_module_id, cb_instance, cb_port_id, cb_port.pins()[pin_id]);
+          module_manager.add_module_net_source(top_module, net, sb_module_id, sb_instance, sb_port_id, sb_port.pins()[pin_id]);
+        } else {
+          VTR_ASSERT(IN_PORT == module_sb.get_chan_node_direction(side_manager.get_side(), itrack));
+          module_manager.add_module_net_source(top_module, net, cb_module_id, cb_instance, cb_port_id, cb_port.pins()[pin_id]);
+          module_manager.add_module_net_sink(top_module, net, sb_module_id, sb_instance, sb_port_id, sb_port.pins()[pin_id]);
+        }  
+      }
+    }
+  }
+}
+
+/********************************************************************
+ * Add module nets to connect the grid ports/pins to Connection Blocks
+ * and Switch Blocks
+ * To make it easy, this function will iterate over all the General
+ * Switch Blocks (GSBs), through which we can obtain the coordinates
+ * of all the grids, connection blocks and switch blocks that are 
+ * supposed to be connected tightly.
+ *
+ * As such, we have completed all the connection for each grid.
+ * There is no need to iterate over the grids
+ *
+ * +-------------------------+   +---------------------------------+
+ * |                         |   |          Y-direction CB         |
+ * |       Grid[x][y+1]      |   |              [x][y + 1]         |
+ * |                         |   +---------------------------------+
+ * +-------------------------+
+ *                                          TOP SIDE
+ *  +-------------+              +---------------------------------+
+ *  |             |              | OPIN_NODE CHAN_NODES OPIN_NODES |
+ *  |             |              |                                 |
+ *  |             |              | OPIN_NODES           OPIN_NODES |
+ *  | X-direction |              |                                 |
+ *  |      CB     |  LEFT SIDE   |        Switch Block             |  RIGHT SIDE
+ *  |   [x][y]    |              |              [x][y]             |
+ *  |             |              |                                 |
+ *  |             |              | CHAN_NODES           CHAN_NODES |
+ *  |             |              |                                 |
+ *  |             |              | OPIN_NODES           OPIN_NODES |
+ *  |             |              |                                 |
+ *  |             |              | OPIN_NODE CHAN_NODES OPIN_NODES |
+ *  +-------------+              +---------------------------------+
+ *                                             BOTTOM SIDE
+ *******************************************************************/
+void add_top_module_nets_connect_grids_and_gsbs(ModuleManager& module_manager, 
+                                                const ModuleId& top_module, 
+                                                const DeviceGrid& grids,
+                                                const vtr::Matrix<size_t>& grid_instance_ids,
+                                                const RRGraph& rr_graph,
+                                                const DeviceRRGSB& device_rr_gsb,
+                                                const vtr::Matrix<size_t>& sb_instance_ids,
+                                                const std::map<t_rr_type, vtr::Matrix<size_t>>& cb_instance_ids,
+                                                const bool& compact_routing_hierarchy,
+                                                const bool& duplicate_grid_pin) {
+
+  vtr::Point<size_t> gsb_range = device_rr_gsb.get_gsb_range();
+
+  for (size_t ix = 0; ix < gsb_range.x(); ++ix) {
+    for (size_t iy = 0; iy < gsb_range.y(); ++iy) {
+      vtr::Point<size_t> gsb_coordinate(ix, iy);
+      const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
+      /* Connect the grid pins of the GSB to adjacent grids */
+      if (false == duplicate_grid_pin) {
+        add_top_module_nets_connect_grids_and_sb(module_manager, top_module, 
+                                                 grids, grid_instance_ids,
+                                                 rr_graph, device_rr_gsb, rr_gsb, sb_instance_ids, 
+                                                 compact_routing_hierarchy);
+      } else {
+        VTR_ASSERT_SAFE(true == duplicate_grid_pin);
+        add_top_module_nets_connect_grids_and_sb_with_duplicated_pins(module_manager, top_module, 
+                                                                      grids, grid_instance_ids,
+                                                                      rr_graph, device_rr_gsb, rr_gsb, sb_instance_ids, 
+                                                                      compact_routing_hierarchy);
+      }
+
+      add_top_module_nets_connect_grids_and_cb(module_manager, top_module, 
+                                               grids, grid_instance_ids,
+                                               rr_graph, device_rr_gsb, rr_gsb, CHANX, cb_instance_ids.at(CHANX),
+                                               compact_routing_hierarchy);
+
+      add_top_module_nets_connect_grids_and_cb(module_manager, top_module, 
+                                               grids, grid_instance_ids,
+                                               rr_graph, device_rr_gsb, rr_gsb, CHANY, cb_instance_ids.at(CHANY),
+                                               compact_routing_hierarchy);
+
+      add_top_module_nets_connect_sb_and_cb(module_manager, top_module, 
+                                            rr_graph, device_rr_gsb, rr_gsb, sb_instance_ids, cb_instance_ids,
+                                            compact_routing_hierarchy);
+
+    }
+  }
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fabric/build_top_module_connection.h b/openfpga/src/fabric/build_top_module_connection.h
new file mode 100644
index 000000000..7f7d06905
--- /dev/null
+++ b/openfpga/src/fabric/build_top_module_connection.h
@@ -0,0 +1,35 @@
+#ifndef BUILD_TOP_MODULE_CONNECTION_H
+#define BUILD_TOP_MODULE_CONNECTION_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <vector>
+#include "vtr_geometry.h"
+#include "vtr_ndmatrix.h"
+#include "device_grid.h"
+#include "rr_graph_obj.h"
+#include "device_rr_gsb.h"
+#include "module_manager.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void add_top_module_nets_connect_grids_and_gsbs(ModuleManager& module_manager, 
+                                                const ModuleId& top_module, 
+                                                const DeviceGrid& grids,
+                                                const vtr::Matrix<size_t>& grid_instance_ids,
+                                                const RRGraph& rr_graph,
+                                                const DeviceRRGSB& device_rr_gsb,
+                                                const vtr::Matrix<size_t>& sb_instance_ids,
+                                                const std::map<t_rr_type, vtr::Matrix<size_t>>& cb_instance_ids,
+                                                const bool& compact_routing_hierarchy,
+                                                const bool& duplicate_grid_pin);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/utils/rr_gsb_utils.cpp b/openfpga/src/utils/rr_gsb_utils.cpp
new file mode 100644
index 000000000..3f332e6db
--- /dev/null
+++ b/openfpga/src/utils/rr_gsb_utils.cpp
@@ -0,0 +1,39 @@
+/********************************************************************
+ * This file includes most utilized functions for data structure
+ * DeviceRRGSB
+ *******************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_side_manager.h"
+
+#include "rr_gsb_utils.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Find if a X-direction or Y-direction Connection Block contains
+ * routing tracks only (zero configuration bits and routing multiplexers)
+ *******************************************************************/
+bool connection_block_contain_only_routing_tracks(const RRGSB& rr_gsb,
+                                                  const t_rr_type& cb_type) {
+  bool routing_track_only = true;
+
+  /* Find routing multiplexers on the sides of a Connection block where IPIN nodes locate */
+  std::vector<enum e_side> cb_sides = rr_gsb.get_cb_ipin_sides(cb_type);
+
+  for (size_t side = 0; side < cb_sides.size(); ++side) {
+    enum e_side cb_ipin_side = cb_sides[side];
+    SideManager side_manager(cb_ipin_side);
+    if (0 < rr_gsb.get_num_ipin_nodes(cb_ipin_side)) { 
+      routing_track_only = false;
+      break;
+    }
+  }
+  
+  return routing_track_only;
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/utils/rr_gsb_utils.h b/openfpga/src/utils/rr_gsb_utils.h
new file mode 100644
index 000000000..57e3e23fc
--- /dev/null
+++ b/openfpga/src/utils/rr_gsb_utils.h
@@ -0,0 +1,23 @@
+#ifndef RR_GSB_UTILS_H
+#define RR_GSB_UTILS_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <string>
+#include <vector>
+#include "rr_gsb.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+bool connection_block_contain_only_routing_tracks(const RRGSB& rr_gsb,
+                                                  const t_rr_type& cb_type);
+
+} /* end namespace openfpga */
+
+#endif

From c855ab24f5bc2206094384fc4a23d3f4c9179db7 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 14 Feb 2020 11:07:04 -0700
Subject: [PATCH 138/645] put build top module memory connections online

---
 .../src/fabric/build_top_module_memory.cpp    | 447 ++++++++++++++++++
 openfpga/src/fabric/build_top_module_memory.h |  43 ++
 openfpga/src/utils/module_manager_utils.cpp   |   3 +
 3 files changed, 493 insertions(+)
 create mode 100644 openfpga/src/fabric/build_top_module_memory.cpp
 create mode 100644 openfpga/src/fabric/build_top_module_memory.h

diff --git a/openfpga/src/fabric/build_top_module_memory.cpp b/openfpga/src/fabric/build_top_module_memory.cpp
new file mode 100644
index 000000000..37f67f0be
--- /dev/null
+++ b/openfpga/src/fabric/build_top_module_memory.cpp
@@ -0,0 +1,447 @@
+/********************************************************************
+ * This file includes functions that are used to organize memories 
+ * in the top module of FPGA fabric
+ *******************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+/* Headers from vpr library */
+#include "vpr_utils.h"
+
+#include "rr_gsb_utils.h"
+#include "openfpga_reserved_words.h"
+#include "openfpga_naming.h"
+
+#include "module_manager_utils.h"
+#include "build_top_module_memory.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * This function adds the CBX/CBY of a tile
+ * to the memory modules and memory instances 
+ * This function is designed for organizing memory modules in top-level
+ * module
+ *******************************************************************/
+static 
+void organize_top_module_tile_cb_modules(ModuleManager& module_manager, 
+                                         const ModuleId& top_module,
+                                         const CircuitLibrary& circuit_lib,
+                                         const e_config_protocol_type& sram_orgz_type,
+                                         const CircuitModelId& sram_model,
+                                         const vtr::Matrix<size_t>& cb_instance_ids,
+                                         const DeviceRRGSB& device_rr_gsb,
+                                         const RRGSB& rr_gsb,
+                                         const t_rr_type& cb_type,
+                                         const bool& compact_routing_hierarchy) {
+  /* If the CB does not exist, we can skip addition */
+  if ( false == rr_gsb.is_cb_exist(cb_type)) {
+    return;
+  }
+
+  /* Skip if the cb does not contain any configuration bits! */
+  if (true == connection_block_contain_only_routing_tracks(rr_gsb, cb_type)) {
+    return;
+  }
+
+  vtr::Point<size_t> cb_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type));
+  /* If we use compact routing hierarchy, we should instanciate the unique module of SB */
+  if (true == compact_routing_hierarchy) {
+    /* Note: use GSB coordinate when inquire for unique modules!!! */
+    const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(cb_type, vtr::Point<size_t>(rr_gsb.get_x(), rr_gsb.get_y()));
+    cb_coord.set_x(unique_mirror.get_cb_x(cb_type)); 
+    cb_coord.set_y(unique_mirror.get_cb_y(cb_type)); 
+  } 
+
+  std::string cb_module_name = generate_connection_block_module_name(cb_type, cb_coord);
+  ModuleId cb_module = module_manager.find_module(cb_module_name);
+  VTR_ASSERT(true == module_manager.valid_module_id(cb_module));
+
+  /* Identify if this sub module includes configuration bits, 
+   * we will update the memory module and instance list
+   */
+  if (0 < find_module_num_config_bits(module_manager, cb_module,
+                                      circuit_lib, sram_model, 
+                                      sram_orgz_type)) {
+    /* Note that use the original CB coodinate for instance id searching ! */
+    module_manager.add_configurable_child(top_module, cb_module, cb_instance_ids[rr_gsb.get_cb_x(cb_type)][rr_gsb.get_cb_y(cb_type)]);
+  }
+}
+
+/********************************************************************
+ * This function adds the SB, CBX, CBY and Grid of a tile
+ * to the memory modules and memory instances 
+ * This function is designed for organizing memory modules in top-level
+ * module
+ *******************************************************************/
+static 
+void organize_top_module_tile_memory_modules(ModuleManager& module_manager, 
+                                             const ModuleId& top_module,
+                                             const CircuitLibrary& circuit_lib,
+                                             const e_config_protocol_type& sram_orgz_type,
+                                             const CircuitModelId& sram_model,
+                                             const DeviceGrid& grids,
+                                             const vtr::Matrix<size_t>& grid_instance_ids,
+                                             const DeviceRRGSB& device_rr_gsb,
+                                             const vtr::Matrix<size_t>& sb_instance_ids,
+                                             const std::map<t_rr_type, vtr::Matrix<size_t>>& cb_instance_ids,
+                                             const bool& compact_routing_hierarchy,
+                                             const vtr::Point<size_t>& tile_coord,
+                                             const e_side& tile_border_side) {
+
+  vtr::Point<size_t> gsb_coord_range = device_rr_gsb.get_gsb_range();
+
+  vtr::Point<size_t> gsb_coord(tile_coord.x(), tile_coord.y() - 1);
+
+  /* We do NOT consider SB and CBs if the gsb is not in the range! */
+  if ( (gsb_coord.x() < gsb_coord_range.x())
+    && (gsb_coord.y() < gsb_coord_range.y()) ) { 
+    const RRGSB& rr_gsb = device_rr_gsb.get_gsb(gsb_coord.x(), gsb_coord.y());
+    /* Find Switch Block: unique module id and instance id!
+     * Note that switch block does always exist in a GSB
+     */
+    vtr::Point<size_t> sb_coord(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
+    /* If we use compact routing hierarchy, we should instanciate the unique module of SB */
+    if (true == compact_routing_hierarchy) {
+      const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(sb_coord);
+      sb_coord.set_x(unique_mirror.get_sb_x()); 
+      sb_coord.set_y(unique_mirror.get_sb_y()); 
+    } 
+    std::string sb_module_name = generate_switch_block_module_name(sb_coord);
+    ModuleId sb_module = module_manager.find_module(sb_module_name);
+    VTR_ASSERT(true == module_manager.valid_module_id(sb_module));
+
+    /* Identify if this sub module includes configuration bits, 
+     * we will update the memory module and instance list
+     */
+    /* If the CB does not exist, we can skip addition */
+    if ( true == rr_gsb.is_sb_exist()) {
+      if (0 < find_module_num_config_bits(module_manager, sb_module,
+                                          circuit_lib, sram_model, 
+                                          sram_orgz_type)) {
+        module_manager.add_configurable_child(top_module, sb_module, sb_instance_ids[rr_gsb.get_sb_x()][rr_gsb.get_sb_y()]);
+      }
+    }
+    
+    /* Try to find and add CBX and CBY */
+    organize_top_module_tile_cb_modules(module_manager, top_module, circuit_lib,
+                                        sram_orgz_type, sram_model,
+                                        cb_instance_ids.at(CHANX),
+                                        device_rr_gsb, rr_gsb, CHANX,
+                                        compact_routing_hierarchy);
+
+    organize_top_module_tile_cb_modules(module_manager, top_module, circuit_lib,
+                                        sram_orgz_type, sram_model,
+                                        cb_instance_ids.at(CHANY),
+                                        device_rr_gsb, rr_gsb, CHANY,
+                                        compact_routing_hierarchy);
+  }
+
+  /* Find the module name for this type of grid */
+  t_physical_tile_type_ptr grid_type = grids[tile_coord.x()][tile_coord.y()].type;
+
+  /* Skip EMPTY Grid */
+  if (true == is_empty_type(grid_type)) {
+    return;
+  }
+  /* Skip width > 1 or height > 1 Grid, which should already been processed when offset=0 */
+  if ( (0 < grids[tile_coord.x()][tile_coord.y()].width_offset) 
+    || (0 < grids[tile_coord.x()][tile_coord.y()].height_offset) ) {
+    return;
+  }
+
+  std::string grid_module_name_prefix(GRID_MODULE_NAME_PREFIX);
+  std::string grid_module_name = generate_grid_block_module_name(grid_module_name_prefix, std::string(grid_type->name), is_io_type(grid_type), tile_border_side);
+  ModuleId grid_module = module_manager.find_module(grid_module_name);
+  VTR_ASSERT(true == module_manager.valid_module_id(grid_module));
+
+  /* Identify if this sub module includes configuration bits, 
+   * we will update the memory module and instance list
+   */
+  if (0 < find_module_num_config_bits(module_manager, grid_module,
+                                      circuit_lib, sram_model, 
+                                      sram_orgz_type)) {
+    module_manager.add_configurable_child(top_module, grid_module, grid_instance_ids[tile_coord.x()][tile_coord.y()]);
+  }
+}
+
+/********************************************************************
+ * Organize the list of memory modules and instances
+ * This function will record all the sub modules of the top-level module
+ * (those have memory ports) to two lists:
+ * 1. memory_modules records the module ids
+ * 2. memory_instances records the instance ids
+ * To keep a clean memory connection between sub modules and top-level module,
+ * the sequence of memory_modules and memory_instances will follow
+ * a chain of tiles considering their physical location
+ *
+ * Inter tile connection:
+ *    +--------------------------------------------------------+
+ *    |              +------+------+-----+------+              |
+ *    |              | I/O  | I/O  | ... | I/O  |              |
+ *    |              | TOP  | TOP  |     | TOP  |              |
+ *    |              +------+------+-----+------+              |
+ *    |           +---------------------------------->tail     |
+ *    |  +------+ |  +------+------+-----+------+   +------+   |
+ *    |  |      | |  |      |      |     |      |   |      |   |
+ *    |  | I/O  | |  | Tile | Tile | ... | Tile |   | I/O  |   |
+ *    |  | LEFT | |  | [h+1]| [h+2]|     |  [n] |   |RIGHT |   |
+ *    |  +------+ |  +------+------+-----+------+   +------+   |
+ *    |           +-------------------------------+            |
+ *    |    ...         ...    ...    ...   ...    |   ...      |
+ *    |           +-------------------------------+            |
+ *    |  +------+ |  +------+------+-----+------+   +------+   |
+ *    |  |      | |  |      |      |     |      |   |      |   |
+ *    |  | I/O  | |  | Tile | Tile | ... | Tile |   | I/O  |   |
+ *    |  | LEFT | |  | [i+1]| [i+2]|     | [j]  |   |RIGHT |   |
+ *    |  +------+ |  +------+------+-----+------+   +------+   |
+ *    |           +-------------------------------+            |
+ *    |  +------+    +------+------+-----+------+ | +------+   |
+ *    |  |      |    |      |      |     |      | | |      |   |
+ *    |  | I/O  |    | Tile | Tile | ... | Tile | | | I/O  |   |
+ *    |  | LEFT |    | [0]  |  [1] |     |  [i] | | |RIGHT |   |
+ *    |  +------+    +------+------+-----+------+ | +------+   |
+ *    +-------------------------------------------+            |
+ *                   +------+------+-----+------+              |
+ *                   | I/O  | I/O  | ... | I/O  |              |
+ *                   |BOTTOM|BOTTOM|     |BOTTOM|              |
+ *                   +------+------+-----+------+              |
+ *        head >-----------------------------------------------+
+ *
+ * Inner tile connection
+ *
+ *       Tile
+ *     +---------------+----------+
+ *   <-+---------------+ +        |
+ *     |               | |        |
+ *     |     CLB       | | CBY    |
+ *     |             +-|-+        |  
+ *     |             | |          |
+ *     +---------------+----------+
+ *     |             +-+----+-----+---<---
+ *     |     CBX       |   SB     |
+ *     |               |          |
+ *     +---------------+----------+
+ *
+ *******************************************************************/
+void organize_top_module_memory_modules(ModuleManager& module_manager, 
+                                        const ModuleId& top_module,
+                                        const CircuitLibrary& circuit_lib,
+                                        const e_config_protocol_type& sram_orgz_type,
+                                        const CircuitModelId& sram_model,
+                                        const DeviceGrid& grids,
+                                        const vtr::Matrix<size_t>& grid_instance_ids,
+                                        const DeviceRRGSB& device_rr_gsb,
+                                        const vtr::Matrix<size_t>& sb_instance_ids,
+                                        const std::map<t_rr_type, vtr::Matrix<size_t>>& cb_instance_ids,
+                                        const bool& compact_routing_hierarchy) {
+
+  /* Ensure clean vectors to return */
+  VTR_ASSERT(true == module_manager.configurable_children(top_module).empty());
+
+  /* First, organize the I/O tiles on the border */
+  /* Special for the I/O tileas on RIGHT and BOTTOM,
+   * which are only I/O blocks, which do NOT contain CBs and SBs 
+   */
+  std::vector<e_side> io_sides{BOTTOM, RIGHT, TOP, LEFT};
+  std::map<e_side, std::vector<vtr::Point<size_t>>> io_coords;
+
+  /* BOTTOM side I/Os */
+  for (size_t ix = 1; ix < grids.width() - 1; ++ix) {
+    io_coords[BOTTOM].push_back(vtr::Point<size_t>(ix, 0));
+  }
+
+  /* RIGHT side I/Os */
+  for (size_t iy = 1; iy < grids.height() - 1; ++iy) {
+    io_coords[RIGHT].push_back(vtr::Point<size_t>(grids.width() - 1, iy));
+  }
+
+  /* TOP side I/Os 
+   * Special case for TOP side: We need tile at ix = 0, which has a SB!!! 
+   *
+   *  TOP-LEFT CORNER of FPGA fabric
+   *    
+   *    +--------+ +-------+
+   *    | EMPTY  | | EMPTY |
+   *    | Grid   | |  CBX  |
+   *    | [0][x] | |       |
+   *    +--------+ +-------+
+   *    +--------+ +--------+
+   *    | EMPTY  | |  SB    |
+   *    | CBX    | | [0][x] |
+   *    +--------+ +--------+
+   * 
+   */
+  for (size_t ix = grids.width() - 2; ix >= 1; --ix) {
+    io_coords[TOP].push_back(vtr::Point<size_t>(ix, grids.height() - 1));
+  }
+  io_coords[TOP].push_back(vtr::Point<size_t>(0, grids.height() - 1));
+
+  /* LEFT side I/Os */
+  for (size_t iy = grids.height() - 2; iy >= 1; --iy) {
+    io_coords[LEFT].push_back(vtr::Point<size_t>(0, iy));
+  }
+
+  for (const e_side& io_side : io_sides) {
+    for (const vtr::Point<size_t>& io_coord : io_coords[io_side]) {
+      /* Identify the GSB that surrounds the grid */
+      organize_top_module_tile_memory_modules(module_manager, top_module, 
+                                              circuit_lib, sram_orgz_type, sram_model,
+                                              grids, grid_instance_ids,
+                                              device_rr_gsb, sb_instance_ids, cb_instance_ids,
+                                              compact_routing_hierarchy,
+                                              io_coord, io_side);
+    }
+  }
+
+  /* For the core grids */
+  std::vector<vtr::Point<size_t>> core_coords;
+  bool positive_direction = true;
+  for (size_t iy = 1; iy < grids.height() - 1; ++iy) {
+    /* For positive direction: -----> */
+    if (true == positive_direction) {
+      for (size_t ix = 1; ix < grids.width() - 1; ++ix) {
+        core_coords.push_back(vtr::Point<size_t>(ix, iy)); 
+      }
+    } else {
+      VTR_ASSERT(false == positive_direction);
+      /* For negative direction: -----> */
+      for (size_t ix = grids.width() - 2; ix >= 1; --ix) {
+        core_coords.push_back(vtr::Point<size_t>(ix, iy)); 
+      }
+    }
+    /* Flip the positive direction to be negative */
+    positive_direction = !positive_direction;
+  }
+
+  for (const vtr::Point<size_t>& core_coord : core_coords) {
+    organize_top_module_tile_memory_modules(module_manager, top_module,  
+                                            circuit_lib, sram_orgz_type, sram_model, 
+                                            grids, grid_instance_ids,
+                                            device_rr_gsb, sb_instance_ids, cb_instance_ids,
+                                            compact_routing_hierarchy,
+                                            core_coord, NUM_SIDES);
+  }
+}
+
+
+/*********************************************************************
+ * Add the port-to-port connection between all the memory modules 
+ * and their parent module
+ *
+ * Create nets to wire the control signals of memory module to 
+ *    the configuration ports of primitive module
+ *
+ * Configuration Chain 
+ * -------------------
+ *
+ *        config_bus (head)   config_bus (tail) 
+ *            |                   ^
+ * primitive  |                   |
+ *   +---------------------------------------------+
+ *   |        |                   |                |
+ *   |        v                   |                |
+ *   |  +-------------------------------------+    |
+ *   |  |        CMOS-based Memory Modules    |    |
+ *   |  +-------------------------------------+    |
+ *   |        |                   |                |
+ *   |        v                   v                |
+ *   |     sram_out             sram_outb          |
+ *   |                                             |
+ *   +---------------------------------------------+
+ *
+ * Memory bank 
+ * -----------
+ *
+ *        config_bus (BL)   config_bus (WL) 
+ *            |                   |
+ * primitive  |                   |
+ *   +---------------------------------------------+
+ *   |        |                   |                |
+ *   |        v                   v                |
+ *   |  +-------------------------------------+    |
+ *   |  |        CMOS-based Memory Modules    |    |
+ *   |  +-------------------------------------+    |
+ *   |        |                   |                |
+ *   |        v                   v                |
+ *   |     sram_out             sram_outb          |
+ *   |                                             |
+ *   +---------------------------------------------+
+ *
+ **********************************************************************/
+static 
+void add_top_module_nets_cmos_memory_config_bus(ModuleManager& module_manager,
+                                                const ModuleId& parent_module,
+                                                const e_config_protocol_type& sram_orgz_type) {
+  switch (sram_orgz_type) {
+  case CONFIG_MEM_STANDALONE:
+    /* Nothing to do */
+    break;
+  case CONFIG_MEM_SCAN_CHAIN: {
+    add_module_nets_cmos_memory_chain_config_bus(module_manager, parent_module, CONFIG_MEM_SCAN_CHAIN);
+    break;
+  }
+  case CONFIG_MEM_MEMORY_BANK:
+    /* TODO: */
+    break;
+  default:
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid type of SRAM organization!\n");
+    exit(1);
+  }
+}
+
+
+/********************************************************************
+ * TODO:
+ * Add the port-to-port connection between a memory module 
+ * and the configuration bus of a primitive module
+ *
+ * Create nets to wire the control signals of memory module to 
+ *    the configuration ports of primitive module
+ *
+ *              Primitive module
+ *             +----------------------------+
+ *             |                +--------+  |
+ *  config     |                |        |  |
+ *   ports --->|--------------->| Memory |  |
+ *             |                | Module |  |
+ *             |                |        |  |
+ *             |                +--------+  |
+ *             +----------------------------+
+ *     The detailed config ports really depend on the type
+ *     of SRAM organization. 
+ *
+ * The config_bus in the argument is the reserved address of configuration
+ * bus in the parent_module for this memory module
+ *
+ * The configuration bus connection will depend not only 
+ * the design technology of the memory cells but also the 
+ * configuration styles of FPGA fabric.
+ * Here we will branch on the design technology
+ *
+ * Note: this function SHOULD be called after the pb_type_module is created
+ * and its child module (logic_module and memory_module) is created! 
+ *******************************************************************/
+void add_top_module_nets_memory_config_bus(ModuleManager& module_manager,
+                                           const ModuleId& parent_module,
+                                           const e_config_protocol_type& sram_orgz_type, 
+                                           const e_circuit_model_design_tech& mem_tech) {
+  switch (mem_tech) {
+  case CIRCUIT_MODEL_DESIGN_CMOS:
+    add_top_module_nets_cmos_memory_config_bus(module_manager, parent_module, 
+                                               sram_orgz_type);
+    break;
+  case CIRCUIT_MODEL_DESIGN_RRAM:
+    /* TODO: */
+    break;
+  default:
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                  "Invalid type of memory design technology!\n");
+    exit(1);
+  }
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fabric/build_top_module_memory.h b/openfpga/src/fabric/build_top_module_memory.h
new file mode 100644
index 000000000..dfa9a5c78
--- /dev/null
+++ b/openfpga/src/fabric/build_top_module_memory.h
@@ -0,0 +1,43 @@
+#ifndef BUILD_TOP_MODULE_MEMORY_H
+#define BUILD_TOP_MODULE_MEMORY_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+
+#include <vector>
+#include <map>
+#include "vtr_ndmatrix.h"
+#include "module_manager.h"
+#include "circuit_types.h"
+#include "circuit_library.h"
+#include "device_grid.h"
+#include "device_rr_gsb.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void organize_top_module_memory_modules(ModuleManager& module_manager, 
+                                        const ModuleId& top_module,
+                                        const CircuitLibrary& circuit_lib,
+                                        const e_config_protocol_type& sram_orgz_type,
+                                        const CircuitModelId& sram_model,
+                                        const DeviceGrid& grids,
+                                        const vtr::Matrix<size_t>& grid_instance_ids,
+                                        const DeviceRRGSB& device_rr_gsb,
+                                        const vtr::Matrix<size_t>& sb_instance_ids,
+                                        const std::map<t_rr_type, vtr::Matrix<size_t>>& cb_instance_ids,
+                                        const bool& compact_routing_hierarchy);
+
+void add_top_module_nets_memory_config_bus(ModuleManager& module_manager,
+                                           const ModuleId& parent_module,
+                                           const e_config_protocol_type& sram_orgz_type, 
+                                           const e_circuit_model_design_tech& mem_tech);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/utils/module_manager_utils.cpp b/openfpga/src/utils/module_manager_utils.cpp
index 25a77a752..9797763b0 100644
--- a/openfpga/src/utils/module_manager_utils.cpp
+++ b/openfpga/src/utils/module_manager_utils.cpp
@@ -10,6 +10,9 @@
 #include "vtr_log.h"
 #include "vtr_assert.h"
 
+/* Headers from openfpgautil library */
+#include "openfpga_port.h"
+
 #include "openfpga_naming.h"
 #include "memory_utils.h"
 #include "pb_type_utils.h"

From 59c13550e0e750482be53581eff556d0a49c251e Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 14 Feb 2020 17:40:59 -0700
Subject: [PATCH 139/645]  add direct annotation with inter-column/row syntax

---
 .../libarchopenfpga/arch/sample_arch.xml      |   2 +-
 .../libarchopenfpga/src/arch_direct.cpp       | 112 ++++++++++++++++++
 libopenfpga/libarchopenfpga/src/arch_direct.h | 103 ++++++++++++++++
 .../libarchopenfpga/src/arch_direct_fwd.h     |  22 ++++
 .../libarchopenfpga/src/direct_types.h        |  22 ----
 .../libarchopenfpga/src/openfpga_arch.h       |   3 +-
 .../src/read_xml_openfpga_arch.cpp            |   4 +-
 .../src/read_xml_routing_circuit.cpp          |  84 +++++++++++--
 .../src/read_xml_routing_circuit.h            |   8 +-
 .../src/write_xml_openfpga_arch.cpp           |   3 +-
 .../src/write_xml_routing_circuit.cpp         |  31 ++++-
 .../src/write_xml_routing_circuit.h           |   3 +-
 openfpga/src/annotation/annotate_rr_graph.cpp |  11 +-
 .../src/annotation/vpr_device_annotation.cpp  |  20 ++--
 .../src/annotation/vpr_device_annotation.h    |   9 +-
 15 files changed, 372 insertions(+), 65 deletions(-)
 create mode 100644 libopenfpga/libarchopenfpga/src/arch_direct.cpp
 create mode 100644 libopenfpga/libarchopenfpga/src/arch_direct.h
 create mode 100644 libopenfpga/libarchopenfpga/src/arch_direct_fwd.h
 delete mode 100644 libopenfpga/libarchopenfpga/src/direct_types.h

diff --git a/libopenfpga/libarchopenfpga/arch/sample_arch.xml b/libopenfpga/libarchopenfpga/arch/sample_arch.xml
index dafaa83dd..1d9f8f5a0 100644
--- a/libopenfpga/libarchopenfpga/arch/sample_arch.xml
+++ b/libopenfpga/libarchopenfpga/arch/sample_arch.xml
@@ -266,7 +266,7 @@
     <segment name="L4" circuit_model_name="chan_segment"/>
   </routing_segment>
   <direct_connection>
-    <direct name="adder" circuit_model_name="direct_interc"/>
+    <direct name="adder" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
   </direct_connection>
   <pb_type_annotations>
     <!-- physical pb_type binding in complex block IO -->
diff --git a/libopenfpga/libarchopenfpga/src/arch_direct.cpp b/libopenfpga/libarchopenfpga/src/arch_direct.cpp
new file mode 100644
index 000000000..a741dd878
--- /dev/null
+++ b/libopenfpga/libarchopenfpga/src/arch_direct.cpp
@@ -0,0 +1,112 @@
+#include "vtr_assert.h"
+
+#include "arch_direct.h"
+
+/************************************************************************
+ * Member functions for class ArchDirect
+ ***********************************************************************/
+
+/************************************************************************
+ * Constructors
+ ***********************************************************************/
+ArchDirect::ArchDirect() {
+  return;
+}
+
+/************************************************************************
+ * Public Accessors : aggregates
+ ***********************************************************************/
+ArchDirect::arch_direct_range ArchDirect::directs() const {
+  return vtr::make_range(direct_ids_.begin(), direct_ids_.end());
+}
+
+/************************************************************************
+ * Public Accessors 
+ ***********************************************************************/
+ArchDirectId ArchDirect::direct(const std::string& name) const {
+  if (0 < direct_name2ids_.count(name)) {
+    return direct_name2ids_.at(name);
+  }
+  return ArchDirectId::INVALID();
+}
+
+std::string ArchDirect::name(const ArchDirectId& direct_id) const {
+  /* validate the direct_id */
+  VTR_ASSERT(valid_direct_id(direct_id));
+  return names_[direct_id]; 
+}
+
+CircuitModelId ArchDirect::circuit_model(const ArchDirectId& direct_id) const {
+  /* validate the direct_id */
+  VTR_ASSERT(valid_direct_id(direct_id));
+  return circuit_models_[direct_id]; 
+}
+
+e_direct_type ArchDirect::type(const ArchDirectId& direct_id) const {
+  /* validate the direct_id */
+  VTR_ASSERT(valid_direct_id(direct_id));
+  return types_[direct_id]; 
+}
+
+e_direct_direction ArchDirect::x_dir(const ArchDirectId& direct_id) const {
+  /* validate the direct_id */
+  VTR_ASSERT(valid_direct_id(direct_id));
+  return directions_[direct_id].x(); 
+}
+
+e_direct_direction ArchDirect::y_dir(const ArchDirectId& direct_id) const {
+  /* validate the direct_id */
+  VTR_ASSERT(valid_direct_id(direct_id));
+  return directions_[direct_id].y(); 
+}
+
+/************************************************************************
+ * Public Mutators
+ ***********************************************************************/
+ArchDirectId ArchDirect::add_direct(const std::string& name) {
+  if (0 < direct_name2ids_.count(name)) {
+    return ArchDirectId::INVALID();
+  }
+
+  /* This is a legal name. we can create a new id */
+  ArchDirectId direct = ArchDirectId(direct_ids_.size());
+  direct_ids_.push_back(direct);
+  names_.push_back(name);
+  circuit_models_.push_back(CircuitModelId::INVALID());
+  types_.emplace_back(NUM_DIRECT_TYPES);
+  directions_.emplace_back(vtr::Point<e_direct_direction>(NUM_DIRECT_DIRECTIONS, NUM_DIRECT_DIRECTIONS));
+
+  /* Register in the name-to-id map */
+  direct_name2ids_[name] = direct;
+  
+  return direct;
+}
+
+void ArchDirect::set_circuit_model(const ArchDirectId& direct_id, const CircuitModelId& circuit_model) {
+  /* validate the direct_id */
+  VTR_ASSERT(valid_direct_id(direct_id));
+  circuit_models_[direct_id] = circuit_model; 
+}
+
+void ArchDirect::set_type(const ArchDirectId& direct_id, const e_direct_type& type) {
+  /* validate the direct_id */
+  VTR_ASSERT(valid_direct_id(direct_id));
+  types_[direct_id] = type; 
+}
+
+void ArchDirect::set_direction(const ArchDirectId& direct_id,
+                               const e_direct_direction& x_dir,
+                               const e_direct_direction& y_dir) {
+  /* validate the direct_id */
+  VTR_ASSERT(valid_direct_id(direct_id));
+  directions_[direct_id].set_x(x_dir); 
+  directions_[direct_id].set_y(y_dir); 
+}
+
+/************************************************************************
+ * Internal invalidators/validators 
+ ***********************************************************************/
+/* Validators */
+bool ArchDirect::valid_direct_id(const ArchDirectId& direct_id) const {
+  return ( size_t(direct_id) < direct_ids_.size() ) && ( direct_id == direct_ids_[direct_id] ); 
+}
diff --git a/libopenfpga/libarchopenfpga/src/arch_direct.h b/libopenfpga/libarchopenfpga/src/arch_direct.h
new file mode 100644
index 000000000..067b257d1
--- /dev/null
+++ b/libopenfpga/libarchopenfpga/src/arch_direct.h
@@ -0,0 +1,103 @@
+#ifndef ARCH_DIRECT_H
+#define ARCH_DIRECT_H
+
+#include <map>
+
+#include "vtr_vector.h"
+#include "vtr_geometry.h"
+
+#include "circuit_library_fwd.h"
+#include "arch_direct_fwd.h"
+
+/********************************************************************
+ * Define the types of point to point connection between CLBs 
+ * These types are supplementary to the original VPR direct connections
+ * Here we extend to the cross-row and cross-column connections
+ ********************************************************************/
+enum e_direct_type {
+  INNER_COLUMN,
+  INNER_ROW,
+  INTER_COLUMN,
+  INTER_ROW,
+  NUM_DIRECT_TYPES
+};
+constexpr std::array<const char*, NUM_DIRECT_TYPES> DIRECT_TYPE_STRING = {{"inner_column", "inner_row", "inter_column", "inter_row"}};
+
+enum e_direct_direction {
+  POSITIVE_DIR,
+  NEGATIVE_DIR,
+  NUM_DIRECT_DIRECTIONS
+};
+constexpr std::array<const char*, NUM_DIRECT_DIRECTIONS> DIRECT_DIRECTION_STRING = {{"positive", "negative"}};
+
+/********************************************************************
+ * A data base to describe the direct connection in OpenFPGA architecture
+ * For each direct connection, it will include
+ * - name: the identifier to annotate the original direct connection in VPR architecture 
+ * - circuit model: the circuit model to used to implement this connection
+ * - type: if this connection should be cross-column or cross-row
+ * - x-direction: how this connection is going to be applied to adjacent columns 
+ *                a positive x-direction means that column A will be connected
+ *                to the column B on the right side of column A
+ * - y-direction: how this connection is going to be applied to adjacent rows 
+ *                a positive y-direction means that row A will be connected
+ *                to the row B on the bottom side of row A
+ *
+ * Note that: this is the data structure to be used when parsing the XML 
+ *            this is NOT the data structure to be use in core engine
+ ********************************************************************/
+class ArchDirect {
+  public: /* Types */
+    typedef vtr::vector<ArchDirectId, ArchDirectId>::const_iterator arch_direct_iterator;
+    /* Create range */
+    typedef vtr::Range<arch_direct_iterator> arch_direct_range;
+
+  public:  /* Constructors */
+    ArchDirect();
+
+  public: /* Accessors: aggregates */
+    arch_direct_range directs() const;
+
+  public: /* Public Accessors: Basic data query on directs */
+    ArchDirectId direct(const std::string& name) const;
+    std::string name(const ArchDirectId& direct_id) const;
+    CircuitModelId circuit_model(const ArchDirectId& direct_id) const;
+    e_direct_type type(const ArchDirectId& direct_id) const;
+    e_direct_direction x_dir(const ArchDirectId& direct_id) const;
+    e_direct_direction y_dir(const ArchDirectId& direct_id) const;
+  public: /* Public Mutators */
+    ArchDirectId add_direct(const std::string& name);
+    void set_circuit_model(const ArchDirectId& direct_id, const CircuitModelId& circuit_model);
+    void set_type(const ArchDirectId& direct_id, const e_direct_type& type);
+    void set_direction(const ArchDirectId& direct_id,
+                       const e_direct_direction& x_dir,
+                       const e_direct_direction& y_dir);
+  public: /* Public invalidators/validators */
+    bool valid_direct_id(const ArchDirectId& direct_id) const;
+  private: /* Internal data */
+    vtr::vector<ArchDirectId, ArchDirectId> direct_ids_;
+    
+    /* Unique name: the identifier to annotate the original direct connection in VPR architecture */
+    vtr::vector<ArchDirectId, std::string> names_;
+
+    /* circuit model: the circuit model to used to implement this connection */
+    vtr::vector<ArchDirectId, CircuitModelId> circuit_models_;
+
+    /* type: if this connection should be cross-column or cross-row */
+    vtr::vector<ArchDirectId, e_direct_type> types_;
+
+    /*
+     * x-direction: how this connection is going to be applied to adjacent columns 
+     *              a positive x-direction means that column A will be connected
+     *              to the column B on the right side of column A
+     * y-direction: how this connection is going to be applied to adjacent rows 
+     *              a positive y-direction means that row A will be connected
+     *              to the row B on the bottom side of row A
+     */
+    vtr::vector<ArchDirectId, vtr::Point<e_direct_direction>> directions_;
+
+    /* Fast look-up */
+    std::map<std::string, ArchDirectId> direct_name2ids_;
+};
+
+#endif
diff --git a/libopenfpga/libarchopenfpga/src/arch_direct_fwd.h b/libopenfpga/libarchopenfpga/src/arch_direct_fwd.h
new file mode 100644
index 000000000..8a1f302f3
--- /dev/null
+++ b/libopenfpga/libarchopenfpga/src/arch_direct_fwd.h
@@ -0,0 +1,22 @@
+/************************************************************************
+ * A header file for ArchDirect class, including critical data declaration
+ * Please include this file only for using any TechnologyLibrary data structure
+ * Refer to arch_direct.h for more details 
+ ***********************************************************************/
+
+/************************************************************************
+ * Create strong id for ArchDirect to avoid illegal type casting 
+ ***********************************************************************/
+#ifndef ARCH_DIRECT_FWD_H
+#define ARCH_DIRECT_FWD_H
+
+#include "vtr_strong_id.h"
+
+struct arch_direct_id_tag;
+
+typedef vtr::StrongId<arch_direct_id_tag> ArchDirectId;
+
+/* Short declaration of class */
+class ArchDirect;
+
+#endif
diff --git a/libopenfpga/libarchopenfpga/src/direct_types.h b/libopenfpga/libarchopenfpga/src/direct_types.h
deleted file mode 100644
index 6b44f1fa5..000000000
--- a/libopenfpga/libarchopenfpga/src/direct_types.h
+++ /dev/null
@@ -1,22 +0,0 @@
-#ifndef DIRECT_TYPES_H
-#define DIRECT_TYPES_H
-
-/********************************************************************
- * Define the types of point to point connection between CLBs 
- * These types are supplementary to the original VPR direct connections
- * Here we extend to the cross-row and cross-column connections
- ********************************************************************/
-enum e_point2point_interconnection_type {
-  NO_P2P,
-  P2P_DIRECT_COLUMN,
-  P2P_DIRECT_ROW,
-  NUM_POINT2POINT_INTERCONNECT_TYPE
-};
-
-enum e_point2point_interconnection_dir {
-  POSITIVE_DIR,
-  NEGATIVE_DIR,
-  NUM_POINT2POINT_INTERCONNECT_DIR
-};
-
-#endif
diff --git a/libopenfpga/libarchopenfpga/src/openfpga_arch.h b/libopenfpga/libarchopenfpga/src/openfpga_arch.h
index 7f102dc85..a3dd71a12 100644
--- a/libopenfpga/libarchopenfpga/src/openfpga_arch.h
+++ b/libopenfpga/libarchopenfpga/src/openfpga_arch.h
@@ -8,6 +8,7 @@
 #include "technology_library.h"
 #include "simulation_setting.h"
 #include "config_protocol.h"
+#include "arch_direct.h"
 #include "pb_type_annotation.h"
 
 /* namespace openfpga begins */
@@ -48,7 +49,7 @@ struct Arch {
   /* Mapping from the names of direct connection
    * to circuit models in circuit library 
    */
-  std::map<std::string, CircuitModelId> direct2circuit;
+  ArchDirect arch_direct;
 
   /* Pb type annotations 
    * Bind from operating to physical
diff --git a/libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.cpp b/libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.cpp
index b35955f97..4c773f87f 100644
--- a/libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.cpp
+++ b/libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.cpp
@@ -94,8 +94,8 @@ openfpga::Arch read_xml_openfpga_arch(const char* arch_file_name) {
                                                                          openfpga_arch.circuit_lib);
 
     /* Parse the direct circuit definition */
-    openfpga_arch.direct2circuit = read_xml_direct_circuit(xml_openfpga_arch, loc_data,
-                                                           openfpga_arch.circuit_lib);
+    openfpga_arch.arch_direct = read_xml_direct_circuit(xml_openfpga_arch, loc_data,
+                                                        openfpga_arch.circuit_lib);
 
     /* Parse the pb_type annotation */
     openfpga_arch.pb_type_annotations = read_xml_pb_type_annotations(xml_openfpga_arch, loc_data);
diff --git a/libopenfpga/libarchopenfpga/src/read_xml_routing_circuit.cpp b/libopenfpga/libarchopenfpga/src/read_xml_routing_circuit.cpp
index 060e26f1b..3114276ae 100644
--- a/libopenfpga/libarchopenfpga/src/read_xml_routing_circuit.cpp
+++ b/libopenfpga/libarchopenfpga/src/read_xml_routing_circuit.cpp
@@ -185,20 +185,53 @@ std::map<std::string, CircuitModelId> read_xml_routing_segment_circuit(pugi::xml
   return seg2circuit;
 }
 
+/********************************************************************
+ * Convert string to the enumerate of direct type
+ *******************************************************************/
+static 
+e_direct_type string_to_direct_type(const std::string& type_string) {
+  if (std::string("column") == type_string) {
+    return INTER_COLUMN;
+  }
+
+  if (std::string("row") == type_string) {
+    return INTER_ROW;
+  }
+
+  return NUM_DIRECT_TYPES;
+} 
+
+/********************************************************************
+ * Convert string to the enumerate of direct direction type
+ *******************************************************************/
+static 
+e_direct_direction string_to_direct_direction(const std::string& type_string) {
+  if (std::string("positive") == type_string) {
+    return POSITIVE_DIR;
+  }
+
+  if (std::string("negative") == type_string) {
+    return NEGATIVE_DIR;
+  }
+
+  return NUM_DIRECT_DIRECTIONS;
+} 
+
+
 /********************************************************************
  * Parse XML codes about <direct_connection> to an object of name-to-circuit mapping
  * Note: this function should be called AFTER the parsing of circuit library!!!
  *******************************************************************/
-std::map<std::string, CircuitModelId> read_xml_direct_circuit(pugi::xml_node& Node,
-                                                              const pugiutil::loc_data& loc_data,
-                                                              const CircuitLibrary& circuit_lib) {
-  std::map<std::string, CircuitModelId> direct2circuit;
+ArchDirect read_xml_direct_circuit(pugi::xml_node& Node,
+                                   const pugiutil::loc_data& loc_data,
+                                   const CircuitLibrary& circuit_lib) {
+  ArchDirect arch_direct;
 
   /* Parse direct list, this is optional. May not be used */
   pugi::xml_node xml_directs= get_single_child(Node, "direct_connection", loc_data, pugiutil::ReqOpt::OPTIONAL);
   /* Not found, we can return */
   if (!xml_directs) {
-    return direct2circuit;
+    return arch_direct;
   }
 
   /* Iterate over the children under this node,
@@ -219,17 +252,46 @@ std::map<std::string, CircuitModelId> read_xml_direct_circuit(pugi::xml_node& No
                                                              circuit_lib, direct_model_name,
                                                              CIRCUIT_MODEL_WIRE);
   
-    /* Ensure that there is no duplicated seg names defined here */
-    std::map<std::string, CircuitModelId>::const_iterator it = direct2circuit.find(direct_name);
-    if (it != direct2circuit.end()) {
+    /* Add to the Arch direct database */
+    ArchDirectId direct = arch_direct.add_direct(direct_name);
+    if (false == arch_direct.valid_direct_id(direct)) {
       archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_direct),
                      "Direct name '%s' has been defined more than once!\n",
                      direct_name.c_str());
     }
+    arch_direct.set_circuit_model(direct, direct_model);
 
-    /* Pass all the check, we can add it to the map */
-    direct2circuit[direct_name] = direct_model; 
+    /* Add more information*/
+    std::string direct_type_name = get_attribute(xml_direct, "type", loc_data).as_string();
+    e_direct_type direct_type = string_to_direct_type(direct_type_name);
+
+    if (NUM_DIRECT_TYPES == direct_type) {
+      archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_direct),
+                     "Direct type '%s' is not support! Acceptable values are [column|row]\n",
+                     direct_type_name.c_str());
+    }
+
+    arch_direct.set_type(direct, direct_type);
+
+    std::string x_dir_name = get_attribute(xml_direct, "x_dir", loc_data).as_string();
+    std::string y_dir_name = get_attribute(xml_direct, "y_dir", loc_data).as_string();
+    e_direct_direction x_dir = string_to_direct_direction(x_dir_name);
+    e_direct_direction y_dir = string_to_direct_direction(y_dir_name);
+
+    if (NUM_DIRECT_DIRECTIONS == x_dir) {
+      archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_direct),
+                     "Direct x-direction '%s' is not support! Acceptable values are [positive|column]\n",
+                     x_dir_name.c_str());
+    }
+
+    if (NUM_DIRECT_DIRECTIONS == y_dir) {
+      archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_direct),
+                     "Direct y-direction '%s' is not support! Acceptable values are [positive|column]\n",
+                     y_dir_name.c_str());
+    }
+
+    arch_direct.set_direction(direct, x_dir, y_dir);
   } 
 
-  return direct2circuit;
+  return arch_direct;
 }
diff --git a/libopenfpga/libarchopenfpga/src/read_xml_routing_circuit.h b/libopenfpga/libarchopenfpga/src/read_xml_routing_circuit.h
index e00627022..28d14710d 100644
--- a/libopenfpga/libarchopenfpga/src/read_xml_routing_circuit.h
+++ b/libopenfpga/libarchopenfpga/src/read_xml_routing_circuit.h
@@ -10,6 +10,7 @@
 #include "pugixml_util.hpp"
 #include "pugixml.hpp"
 #include "circuit_library.h"
+#include "arch_direct.h"
 
 /********************************************************************
  * Function declaration
@@ -26,8 +27,9 @@ std::map<std::string, CircuitModelId> read_xml_routing_segment_circuit(pugi::xml
                                                                        const pugiutil::loc_data& loc_data,
                                                                        const CircuitLibrary& circuit_lib);
 
-std::map<std::string, CircuitModelId> read_xml_direct_circuit(pugi::xml_node& Node,
-                                                              const pugiutil::loc_data& loc_data,
-                                                              const CircuitLibrary& circuit_lib);
+ArchDirect read_xml_direct_circuit(pugi::xml_node& Node,
+                                   const pugiutil::loc_data& loc_data,
+                                   const CircuitLibrary& circuit_lib);
+
 
 #endif
diff --git a/libopenfpga/libarchopenfpga/src/write_xml_openfpga_arch.cpp b/libopenfpga/libarchopenfpga/src/write_xml_openfpga_arch.cpp
index eb999dcd1..6d0a8ff06 100644
--- a/libopenfpga/libarchopenfpga/src/write_xml_openfpga_arch.cpp
+++ b/libopenfpga/libarchopenfpga/src/write_xml_openfpga_arch.cpp
@@ -56,8 +56,7 @@ void write_xml_openfpga_arch(const char* fname,
   write_xml_routing_segment_circuit(fp, fname, openfpga_arch.circuit_lib, openfpga_arch.routing_seg2circuit);
 
   /* Write the direct connection circuit definition */
-  write_xml_direct_circuit(fp, fname, openfpga_arch.circuit_lib, openfpga_arch.direct2circuit);
-
+  write_xml_direct_circuit(fp, fname, openfpga_arch.circuit_lib, openfpga_arch.arch_direct);
 
   /* Write the pb_type annotations */
   openfpga::write_xml_pb_type_annotations(fp, fname, openfpga_arch. pb_type_annotations);
diff --git a/libopenfpga/libarchopenfpga/src/write_xml_routing_circuit.cpp b/libopenfpga/libarchopenfpga/src/write_xml_routing_circuit.cpp
index 70f95f37f..978d38516 100644
--- a/libopenfpga/libarchopenfpga/src/write_xml_routing_circuit.cpp
+++ b/libopenfpga/libarchopenfpga/src/write_xml_routing_circuit.cpp
@@ -38,6 +38,29 @@ void write_xml_routing_component_circuit(std::fstream& fp,
   }
 }
 
+/********************************************************************
+ * Write switch circuit model definition in XML format
+ *******************************************************************/
+static 
+void write_xml_direct_component_circuit(std::fstream& fp,
+                                         const char* fname,
+                                         const std::string& direct_tag_name, 
+                                         const CircuitLibrary& circuit_lib,
+                                         const ArchDirect& arch_direct,
+                                         const ArchDirectId& direct_id) {
+  /* Validate the file stream */
+  openfpga::check_file_stream(fname, fp);
+
+  /* Iterate over the mapping */
+  fp << "\t\t" << "<" << direct_tag_name;
+  write_xml_attribute(fp, "name", arch_direct.name(direct_id).c_str()); 
+  write_xml_attribute(fp, "circuit_model_name", circuit_lib.model_name(arch_direct.circuit_model(direct_id)).c_str()); 
+  write_xml_attribute(fp, "type", DIRECT_TYPE_STRING[arch_direct.type(direct_id)]); 
+  write_xml_attribute(fp, "x_dir", DIRECT_DIRECTION_STRING[arch_direct.x_dir(direct_id)]); 
+  write_xml_attribute(fp, "y_dir", DIRECT_DIRECTION_STRING[arch_direct.y_dir(direct_id)]); 
+  fp << "/>" << "\n";
+}
+
 /********************************************************************
  * Write Connection block circuit models in XML format
  *******************************************************************/
@@ -104,9 +127,9 @@ void write_xml_routing_segment_circuit(std::fstream& fp,
 void write_xml_direct_circuit(std::fstream& fp,
                               const char* fname,
                               const CircuitLibrary& circuit_lib,
-                              const std::map<std::string, CircuitModelId>& direct2circuit) {
+                              const ArchDirect& arch_direct) {
   /* If the direct2circuit is empty, we do not output XML */
-  if (direct2circuit.empty()) {
+  if (0 == arch_direct.directs().size()) {
     return;
   }
 
@@ -117,7 +140,9 @@ void write_xml_direct_circuit(std::fstream& fp,
   fp << "\t" << "<direct_connection>" << "\n";
 
   /* Write each direct connection circuit definition */ 
-  write_xml_routing_component_circuit(fp, fname, std::string("direct"), circuit_lib, direct2circuit);
+  for (const ArchDirectId& direct_id : arch_direct.directs()) {
+    write_xml_direct_component_circuit(fp, fname, std::string("direct"), circuit_lib, arch_direct, direct_id);
+  }
 
   /* Finish writing the root node */
   fp << "\t" << "</direct_connection>" << "\n";
diff --git a/libopenfpga/libarchopenfpga/src/write_xml_routing_circuit.h b/libopenfpga/libarchopenfpga/src/write_xml_routing_circuit.h
index 7cf2cd8ae..bddb7cc56 100644
--- a/libopenfpga/libarchopenfpga/src/write_xml_routing_circuit.h
+++ b/libopenfpga/libarchopenfpga/src/write_xml_routing_circuit.h
@@ -9,6 +9,7 @@
 #include <string>
 
 #include "circuit_library.h"
+#include "arch_direct.h"
 
 /********************************************************************
  * Function declaration
@@ -31,6 +32,6 @@ void write_xml_routing_segment_circuit(std::fstream& fp,
 void write_xml_direct_circuit(std::fstream& fp,
                               const char* fname,
                               const CircuitLibrary& circuit_lib,
-                              const std::map<std::string, CircuitModelId>& direct2circuit);
+                              const ArchDirect& arch_direct);
 
 #endif
diff --git a/openfpga/src/annotation/annotate_rr_graph.cpp b/openfpga/src/annotation/annotate_rr_graph.cpp
index 351c248bb..d0097ced6 100644
--- a/openfpga/src/annotation/annotate_rr_graph.cpp
+++ b/openfpga/src/annotation/annotate_rr_graph.cpp
@@ -524,13 +524,16 @@ void annotate_direct_circuit_models(const DeviceContext& vpr_device_ctx,
 
   for (int idirect = 0; idirect < vpr_device_ctx.arch->num_directs; ++idirect) {
     std::string direct_name = vpr_device_ctx.arch->Directs[idirect].name; 
-    CircuitModelId circuit_model = CircuitModelId::INVALID();
     /* The name-to-circuit mapping is stored in either cb_switch-to-circuit or sb_switch-to-circuit,
      * Try to find one and update the device annotation
      */ 
-    if (0 < openfpga_arch.direct2circuit.count(direct_name)) {
-      circuit_model = openfpga_arch.direct2circuit.at(direct_name); 
+    ArchDirectId direct_id = openfpga_arch.arch_direct.direct(direct_name);
+    /* Cannot find a direct, no annotation needed for this direct */
+    if (ArchDirectId::INVALID() == direct_id) {
+      continue;
     }
+
+    CircuitModelId circuit_model = openfpga_arch.arch_direct.circuit_model(direct_id); 
     /* Cannot find a circuit model, error out! */
     if (CircuitModelId::INVALID() == circuit_model) {
       VTR_LOG_ERROR("Fail to find a circuit model for a direct connection '%s'!\nPlease check your OpenFPGA architecture XML!\n",
@@ -547,7 +550,7 @@ void annotate_direct_circuit_models(const DeviceContext& vpr_device_ctx,
     }
   
     /* Now update the device annotation */
-    vpr_device_annotation.add_direct_circuit_model(idirect, circuit_model);
+    vpr_device_annotation.add_direct_annotation(idirect, direct_id);
     VTR_LOGV(verbose_output, 
              "Binded a direct connection '%s' to circuit model '%s'\n",
              direct_name.c_str(),
diff --git a/openfpga/src/annotation/vpr_device_annotation.cpp b/openfpga/src/annotation/vpr_device_annotation.cpp
index aa2e6fce9..5b36e3885 100644
--- a/openfpga/src/annotation/vpr_device_annotation.cpp
+++ b/openfpga/src/annotation/vpr_device_annotation.cpp
@@ -233,13 +233,12 @@ CircuitModelId VprDeviceAnnotation::rr_segment_circuit_model(const RRSegmentId&
   return rr_segment_circuit_models_.at(rr_segment);
 }
 
-CircuitModelId VprDeviceAnnotation::direct_circuit_model(const size_t& direct) const {
+ArchDirectId VprDeviceAnnotation::direct_annotation(const size_t& direct) const {
   /* Ensure that the rr_switch is in the list */
-  std::map<size_t, CircuitModelId>::const_iterator it = direct_circuit_models_.find(direct);
-  if (it == direct_circuit_models_.end()) {
-    return CircuitModelId::INVALID();
+  if (0 == direct_annotations_.count(direct)) {
+    return ArchDirectId::INVALID();
   }
-  return direct_circuit_models_.at(direct);
+  return direct_annotations_.at(direct);
 }
 
 /************************************************************************
@@ -461,15 +460,14 @@ void VprDeviceAnnotation::add_rr_segment_circuit_model(const RRSegmentId& rr_seg
   rr_segment_circuit_models_[rr_segment] = circuit_model;
 }
 
-void VprDeviceAnnotation::add_direct_circuit_model(const size_t& direct, const CircuitModelId& circuit_model) {
+void VprDeviceAnnotation::add_direct_annotation(const size_t& direct, const ArchDirectId& arch_direct_id) {
   /* Warn any override attempt */
-  std::map<size_t, CircuitModelId>::const_iterator it = direct_circuit_models_.find(direct);
-  if (it != direct_circuit_models_.end()) {
-    VTR_LOG_WARN("Override the annotation between direct '%ld' and its circuit_model '%ld'!\n",
-                 size_t(direct), size_t(circuit_model));
+  if (0 < direct_annotations_.count(direct)) {
+    VTR_LOG_WARN("Override the annotation between direct '%ld' and its annotation '%ld'!\n",
+                 size_t(direct), size_t(arch_direct_id));
   }
 
-  direct_circuit_models_[direct] = circuit_model;
+  direct_annotations_[direct] = arch_direct_id;
 }
 
 } /* End namespace openfpga*/
diff --git a/openfpga/src/annotation/vpr_device_annotation.h b/openfpga/src/annotation/vpr_device_annotation.h
index 74868ae61..5c083e367 100644
--- a/openfpga/src/annotation/vpr_device_annotation.h
+++ b/openfpga/src/annotation/vpr_device_annotation.h
@@ -18,6 +18,7 @@
 /* Header from openfpgautil library */
 #include "openfpga_port.h"
 #include "circuit_library.h"
+#include "arch_direct.h"
 
 /* Begin namespace openfpga */
 namespace openfpga {
@@ -71,7 +72,7 @@ class VprDeviceAnnotation {
     t_pb_graph_pin* physical_pb_graph_pin(t_pb_graph_pin* pb_graph_pin) const;
     CircuitModelId rr_switch_circuit_model(const RRSwitchId& rr_switch) const;
     CircuitModelId rr_segment_circuit_model(const RRSegmentId& rr_segment) const;
-    CircuitModelId direct_circuit_model(const size_t& direct) const;
+    ArchDirectId direct_annotation(const size_t& direct) const;
   public:  /* Public mutators */
     void add_pb_type_physical_mode(t_pb_type* pb_type, t_mode* physical_mode);
     void add_physical_pb_type(t_pb_type* operating_pb_type, t_pb_type* physical_pb_type);
@@ -91,7 +92,7 @@ class VprDeviceAnnotation {
     void add_physical_pb_graph_pin(t_pb_graph_pin* operating_pb_graph_pin, t_pb_graph_pin* physical_pb_graph_pin);
     void add_rr_switch_circuit_model(const RRSwitchId& rr_switch, const CircuitModelId& circuit_model);
     void add_rr_segment_circuit_model(const RRSegmentId& rr_segment, const CircuitModelId& circuit_model);
-    void add_direct_circuit_model(const size_t& direct, const CircuitModelId& circuit_model);
+    void add_direct_annotation(const size_t& direct, const ArchDirectId& arch_direct_id);
   private: /* Internal data */
     /* Pair a regular pb_type to its physical pb_type */
     std::map<t_pb_type*, t_pb_type*> physical_pb_types_;
@@ -173,8 +174,8 @@ class VprDeviceAnnotation {
     /* Pair a Routing Segment (rr_segment) to a circuit model */
     std::map<RRSegmentId, CircuitModelId> rr_segment_circuit_models_;
 
-    /* Pair a direct connection (direct) to a circuit model */
-    std::map<size_t, CircuitModelId> direct_circuit_models_;
+    /* Pair a direct connection (direct) to a annotation which contains circuit model id */
+    std::map<size_t, ArchDirectId> direct_annotations_;
 };
 
 } /* End namespace openfpga*/

From 7e86cf107915b00cc3095aba31808e9e6c8b4706 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 14 Feb 2020 19:11:49 -0700
Subject: [PATCH 140/645] add tile direct data structure

---
 openfpga/src/tile_direct/tile_direct.cpp   | 102 +++++++++++++++++++++
 openfpga/src/tile_direct/tile_direct.h     |  78 ++++++++++++++++
 openfpga/src/tile_direct/tile_direct_fwd.h |  23 +++++
 3 files changed, 203 insertions(+)
 create mode 100644 openfpga/src/tile_direct/tile_direct.cpp
 create mode 100644 openfpga/src/tile_direct/tile_direct.h
 create mode 100644 openfpga/src/tile_direct/tile_direct_fwd.h

diff --git a/openfpga/src/tile_direct/tile_direct.cpp b/openfpga/src/tile_direct/tile_direct.cpp
new file mode 100644
index 000000000..0face1b7e
--- /dev/null
+++ b/openfpga/src/tile_direct/tile_direct.cpp
@@ -0,0 +1,102 @@
+/******************************************************************************
+ * Memember functions for data structure TileDirect
+ ******************************************************************************/
+#include "vtr_assert.h"
+
+#include "tile_direct.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/**************************************************
+ * Public Accessors 
+ *************************************************/
+TileDirect::tile_direct_range TileDirect::directs() const {
+  return vtr::make_range(direct_ids_.begin(), direct_ids_.end());
+}
+
+t_physical_tile_type_ptr TileDirect::from_tile(const TileDirectId& direct_id) const {
+  /* Validate the direct_id */
+  VTR_ASSERT(valid_direct_id(direct_id));
+  return from_tiles_[direct_id];
+}
+
+vtr::Point<size_t> TileDirect::from_tile_coordinate(const TileDirectId& direct_id) const {
+  /* Validate the direct_id */
+  VTR_ASSERT(valid_direct_id(direct_id));
+  return from_tile_coords_[direct_id];
+}
+
+size_t TileDirect::from_tile_pin(const TileDirectId& direct_id) const {
+  /* Validate the direct_id */
+  VTR_ASSERT(valid_direct_id(direct_id));
+  return from_tile_pins_[direct_id];
+}
+
+e_side TileDirect::from_tile_side(const TileDirectId& direct_id) const {
+  /* Validate the direct_id */
+  VTR_ASSERT(valid_direct_id(direct_id));
+  return from_tile_sides_[direct_id];
+}
+
+t_physical_tile_type_ptr TileDirect::to_tile(const TileDirectId& direct_id) const {
+  /* Validate the direct_id */
+  VTR_ASSERT(valid_direct_id(direct_id));
+  return to_tiles_[direct_id];
+}
+
+vtr::Point<size_t> TileDirect::to_tile_coordinate(const TileDirectId& direct_id) const {
+  /* Validate the direct_id */
+  VTR_ASSERT(valid_direct_id(direct_id));
+  return to_tile_coords_[direct_id];
+}
+
+size_t TileDirect::to_tile_pin(const TileDirectId& direct_id) const {
+  /* Validate the direct_id */
+  VTR_ASSERT(valid_direct_id(direct_id));
+  return to_tile_pins_[direct_id];
+}
+
+e_side TileDirect::to_tile_side(const TileDirectId& direct_id) const {
+  /* Validate the direct_id */
+  VTR_ASSERT(valid_direct_id(direct_id));
+  return to_tile_sides_[direct_id];
+}
+
+/******************************************************************************
+ * Private Mutators
+ ******************************************************************************/
+TileDirectId TileDirect::add_direct(t_physical_tile_type_ptr from_tile,
+                                    const vtr::Point<size_t>& from_tile_coord,
+                                    const e_side& from_tile_side,
+                                    const size_t& from_tile_pin,
+                                    t_physical_tile_type_ptr to_tile,
+                                    const vtr::Point<size_t>& to_tile_coord,
+                                    const e_side& to_tile_side,
+                                    const size_t& to_tile_pin) {
+  /* Create an new id */
+  TileDirectId direct = TileDirectId(direct_ids_.size());
+  direct_ids_.push_back(direct);
+
+  /* Allocate other attributes */
+  from_tiles_.push_back(from_tile);
+  from_tile_coords_.push_back(from_tile_coord);
+  from_tile_sides_.push_back(from_tile_side);
+  from_tile_pins_.push_back(from_tile_pin);
+
+  to_tiles_.push_back(to_tile);
+  to_tile_coords_.push_back(to_tile_coord);
+  to_tile_sides_.push_back(to_tile_side);
+  to_tile_pins_.push_back(to_tile_pin);
+
+  return direct;
+}
+
+/******************************************************************************
+ * Private validators/invalidators
+ ******************************************************************************/
+bool TileDirect::valid_direct_id(const TileDirectId& direct_id) const {
+  return ( size_t(direct_id) < direct_ids_.size() ) && ( direct_id == direct_ids_[direct_id] ); 
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/tile_direct/tile_direct.h b/openfpga/src/tile_direct/tile_direct.h
new file mode 100644
index 000000000..562b559ca
--- /dev/null
+++ b/openfpga/src/tile_direct/tile_direct.h
@@ -0,0 +1,78 @@
+#ifndef TILE_DIRECT_H
+#define TILE_DIRECT_H
+
+/********************************************************************
+ * Include header files required by the data structure definition
+ *******************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_geometry.h"
+#include "vtr_vector.h"
+
+/* Headers from readarch library */
+#include "physical_types.h"
+
+#include "tile_direct_fwd.h"
+
+/* Begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * TileDirect object aims to be a database to store all the information 
+ * about direct connection between tiles
+ *  - starting tile and end tile for each point-to-point direct connection
+ *  - circuit model to implement each direct connection
+ *
+ * TileDirect is compiled from ArchDirect for a specific FPGA fabric. 
+ *******************************************************************/
+class TileDirect {
+  public: /* Types and ranges */
+    typedef vtr::vector<TileDirectId, TileDirectId>::const_iterator tile_direct_iterator;
+    typedef vtr::Range<tile_direct_iterator> tile_direct_range;
+  public: /* Public aggregators */
+    tile_direct_range directs() const;
+    t_physical_tile_type_ptr from_tile(const TileDirectId& direct_id) const;
+    vtr::Point<size_t> from_tile_coordinate(const TileDirectId& direct_id) const;
+    e_side from_tile_side(const TileDirectId& direct_id) const;
+    size_t from_tile_pin(const TileDirectId& direct_id) const;
+    t_physical_tile_type_ptr to_tile(const TileDirectId& direct_id) const;
+    vtr::Point<size_t> to_tile_coordinate(const TileDirectId& direct_id) const;
+    e_side to_tile_side(const TileDirectId& direct_id) const;
+    size_t to_tile_pin(const TileDirectId& direct_id) const;
+  public: /* Public mutators */
+    TileDirectId add_direct(t_physical_tile_type_ptr from_tile,
+                            const vtr::Point<size_t>& from_tile_coord,
+                            const e_side& from_tile_side,
+                            const size_t& from_tile_pin,
+                            t_physical_tile_type_ptr to_tile,
+                            const vtr::Point<size_t>& to_tile_coord,
+                            const e_side& to_tile_side,
+                            const size_t& to_tile_pin);
+  public: /* Public validators/invalidators */
+    bool valid_direct_id(const TileDirectId& direct_id) const;
+  private: /* Internal Data */
+    vtr::vector<TileDirectId, TileDirectId> direct_ids_;
+
+    /* Detailed information about the starting tile
+     * - tile type description
+     * - tile coordinate
+     * - tile pin id
+     */
+    vtr::vector<TileDirectId, t_physical_tile_type_ptr> from_tiles_;
+    vtr::vector<TileDirectId, vtr::Point<size_t>> from_tile_coords_;
+    vtr::vector<TileDirectId, e_side> from_tile_sides_;
+    vtr::vector<TileDirectId, size_t> from_tile_pins_;
+
+    /* Detailed information about the ending tile
+     * - tile type description
+     * - tile coordinate
+     * - tile pin id
+     */
+    vtr::vector<TileDirectId, t_physical_tile_type_ptr> to_tiles_;
+    vtr::vector<TileDirectId, vtr::Point<size_t>> to_tile_coords_;
+    vtr::vector<TileDirectId, e_side> to_tile_sides_;
+    vtr::vector<TileDirectId, size_t> to_tile_pins_;
+};
+
+} /* End namespace openfpga*/
+
+#endif
diff --git a/openfpga/src/tile_direct/tile_direct_fwd.h b/openfpga/src/tile_direct/tile_direct_fwd.h
new file mode 100644
index 000000000..c83a00ee9
--- /dev/null
+++ b/openfpga/src/tile_direct/tile_direct_fwd.h
@@ -0,0 +1,23 @@
+/**************************************************
+ * This file includes only declarations for 
+ * the data structures for TileDirect
+ * Please refer to tile_direct.h for more details
+ *************************************************/
+#ifndef TILE_DIRECT_FWD_H
+#define TILE_DIRECT_FWD_H
+
+#include "vtr_strong_id.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/* Strong Ids for ModuleManager */
+struct tile_direct_id_tag;
+
+typedef vtr::StrongId<tile_direct_id_tag> TileDirectId;
+
+class TileDirect;
+
+} /* end namespace openfpga */
+
+#endif 

From 213c611c0b323b9d2e4e03f8cef52b881a29134d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 14 Feb 2020 22:21:32 -0700
Subject: [PATCH 141/645] add tile direct builder

---
 openfpga/src/base/openfpga_context.h          |   8 +-
 openfpga/src/base/openfpga_link_arch.cpp      |   7 +
 .../src/tile_direct/build_tile_direct.cpp     | 367 ++++++++++++++++++
 openfpga/src/tile_direct/build_tile_direct.h  |  25 ++
 openfpga/src/tile_direct/tile_direct.cpp      |  15 +
 openfpga/src/tile_direct/tile_direct.h        |   8 +
 6 files changed, 429 insertions(+), 1 deletion(-)
 create mode 100644 openfpga/src/tile_direct/build_tile_direct.cpp
 create mode 100644 openfpga/src/tile_direct/build_tile_direct.h

diff --git a/openfpga/src/base/openfpga_context.h b/openfpga/src/base/openfpga_context.h
index 6f9ee0910..ac3cc99c8 100644
--- a/openfpga/src/base/openfpga_context.h
+++ b/openfpga/src/base/openfpga_context.h
@@ -8,6 +8,7 @@
 #include "vpr_clustering_annotation.h"
 #include "vpr_routing_annotation.h"
 #include "mux_library.h"
+#include "tile_direct.h"
 #include "module_manager.h"
 #include "device_rr_gsb.h"
 
@@ -47,6 +48,7 @@ class OpenfpgaContext : public Context  {
     const openfpga::VprRoutingAnnotation& vpr_routing_annotation() const { return vpr_routing_annotation_; }
     const openfpga::DeviceRRGSB& device_rr_gsb() const { return device_rr_gsb_; }
     const openfpga::MuxLibrary& mux_lib() const { return mux_lib_; }
+    const openfpga::TileDirect& tile_direct() const { return tile_direct_; }
     const openfpga::ModuleManager& module_graph() const { return module_graph_; }
   public:  /* Public mutators */
     openfpga::Arch& mutable_arch() { return arch_; }
@@ -56,6 +58,7 @@ class OpenfpgaContext : public Context  {
     openfpga::VprRoutingAnnotation& mutable_vpr_routing_annotation() { return vpr_routing_annotation_; }
     openfpga::DeviceRRGSB& mutable_device_rr_gsb() { return device_rr_gsb_; }
     openfpga::MuxLibrary& mutable_mux_lib() { return mux_lib_; }
+    openfpga::TileDirect& mutable_tile_direct() { return tile_direct_; }
     openfpga::ModuleManager& mutable_module_graph() { return module_graph_; }
   private: /* Internal data */
     /* Data structure to store information from read_openfpga_arch library */
@@ -67,7 +70,7 @@ class OpenfpgaContext : public Context  {
     /* Naming fix to netlist */
     openfpga::VprNetlistAnnotation vpr_netlist_annotation_;
 
-    /* TODO: Pin net fix to cluster results */
+    /* Pin net fix to cluster results */
     openfpga::VprClusteringAnnotation vpr_clustering_annotation_;
 
     /* Routing results annotation */ 
@@ -79,6 +82,9 @@ class OpenfpgaContext : public Context  {
     /* Library of physical implmentation of routing multiplexers */
     openfpga::MuxLibrary mux_lib_;
 
+    /* Inner/inter-column/row tile direct connections */
+    openfpga::TileDirect tile_direct_;
+
     /* Fabric module graph */
     openfpga::ModuleManager module_graph_;
 };
diff --git a/openfpga/src/base/openfpga_link_arch.cpp b/openfpga/src/base/openfpga_link_arch.cpp
index 78afc93a2..7ee522b6a 100644
--- a/openfpga/src/base/openfpga_link_arch.cpp
+++ b/openfpga/src/base/openfpga_link_arch.cpp
@@ -14,6 +14,7 @@
 #include "annotate_routing.h"
 #include "annotate_rr_graph.h"
 #include "mux_library_builder.h"
+#include "build_tile_direct.h"
 #include "openfpga_link_arch.h"
 
 /* Include global variables of VPR */
@@ -106,6 +107,12 @@ void link_arch(OpenfpgaContext& openfpga_context,
   /* Build multiplexer library */
   openfpga_context.mutable_mux_lib() = build_device_mux_library(g_vpr_ctx.device(),
                                                                 const_cast<const OpenfpgaContext&>(openfpga_context)); 
+
+  /* Build tile direct annotation */
+  openfpga_context.mutable_tile_direct() =  build_device_tile_direct(g_vpr_ctx.device(),
+                                                                     openfpga_context.arch().arch_direct,
+                                                                     openfpga_context.arch().circuit_lib);
+
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/tile_direct/build_tile_direct.cpp b/openfpga/src/tile_direct/build_tile_direct.cpp
new file mode 100644
index 000000000..5a40e2ca5
--- /dev/null
+++ b/openfpga/src/tile_direct/build_tile_direct.cpp
@@ -0,0 +1,367 @@
+/***************************************************************************************
+ * This file includes functions that build the point-to-point direct connections
+ * between tiles (programmable blocks) 
+ ***************************************************************************************/
+
+/* Headers from vtrutil library */
+#include "vtr_log.h"
+#include "vtr_assert.h"
+#include "vtr_time.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_tokenizer.h"
+#include "openfpga_port.h"
+#include "openfpga_port_parser.h"
+
+/* Headers from vpr library */
+#include "vpr_utils.h"
+
+#include "build_tile_direct.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/***************************************************************************************
+ * Parse the from tile name from the direct definition  
+ * The definition string should be in the following format:
+ *   <tile_type_name>.<pin_name>[<pin_lsb>:<pin_msb>]  
+ ***************************************************************************************/
+static 
+std::string parse_direct_tile_name(const std::string& direct_tile_inf) {
+  StringToken tokenizer(direct_tile_inf);
+  std::vector<std::string> tokens = tokenizer.split('.');
+  /* We should have only 2 elements and the first is tile name */
+  if (2 != tokens.size()) {
+    VTR_LOG_ERROR("Invalid definition on direct tile '%s'!\n\tExpect <tile_type_name>.<pin_name>[<pin_lsb>:<pin_msb>].\n",
+                  direct_tile_inf.c_str());
+  }
+
+  return tokens[0];
+}
+
+/***************************************************************************************
+ * Check if a pin is located on a given side of physical tile
+ * If the given side is NUM_SIDES, we will search all the sides 
+ ***************************************************************************************/
+static 
+bool is_pin_locate_at_physical_tile_side(t_physical_tile_type_ptr physical_tile,
+                                         const size_t& pin_width_offset,
+                                         const size_t& pin_height_offset,
+                                         const size_t& pin_id,
+                                         const e_side& pin_side) {
+  if (NUM_SIDES == pin_side) {
+    for (size_t side = 0; side < NUM_SIDES; ++side) {
+      if (true == physical_tile->pinloc[pin_width_offset][pin_height_offset][side][pin_id]) {
+        return true;
+      }
+    }
+  }
+  
+  return physical_tile->pinloc[pin_width_offset][pin_height_offset][size_t(pin_side)][pin_id];
+}
+
+/***************************************************************************************
+ * Find the pin ids of a physical tile based on the given port name, LSB and MSB 
+ ***************************************************************************************/
+static 
+std::vector<size_t> find_physical_tile_pin_id(t_physical_tile_type_ptr physical_tile, 
+                                              const size_t& pin_width_offset,
+                                              const size_t& pin_height_offset,
+                                              const BasicPort& tile_port,
+                                              const e_side& pin_side) {
+  std::vector<size_t> pin_ids;
+
+  /* Walk through the port of the tile */
+  for (const t_physical_tile_port& physical_tile_port : physical_tile->ports) {
+    if (std::string(physical_tile_port.name) != tile_port.get_name()) {
+      continue;
+    }
+    /* If the wanted port is invalid, it assumes that we want the full port */
+    if (false == tile_port.is_valid()) {
+      for (int ipin = 0; ipin < physical_tile_port.num_pins; ++ipin) {
+        int pin_id = physical_tile_port.absolute_first_pin_index + ipin;
+        VTR_ASSERT(pin_id < physical_tile->num_pins);
+        /* Check if the pin is located on the wanted side */
+        if (true == is_pin_locate_at_physical_tile_side(physical_tile,
+                                                        pin_width_offset,
+                                                        pin_height_offset,
+                                                        pin_id, pin_side)) {
+          pin_ids.push_back(pin_id);
+        }
+      }
+      continue;
+    }
+    /* Find the LSB and MSB of the pin */
+    VTR_ASSERT_SAFE(true == tile_port.is_valid());
+    BasicPort ref_port(physical_tile_port.name, physical_tile_port.num_pins); 
+    if (false == ref_port.contained(tile_port)) {
+      VTR_LOG_ERROR("Defined direct port '%s[%lu:%lu]' is out of range for physical port '%s[%lu:%lu]'!\n",
+                    tile_port.get_name().c_str(),
+                    tile_port.get_lsb(), tile_port.get_msb(),
+                    ref_port.get_name().c_str(),
+                    ref_port.get_lsb(), ref_port.get_msb());
+      exit(1);
+    }
+    for (const size_t& ipin : tile_port.pins()) {
+      int pin_id = physical_tile_port.absolute_first_pin_index + ipin;
+      VTR_ASSERT(pin_id < physical_tile->num_pins);
+      /* Check if the pin is located on the wanted side */
+      if (true == is_pin_locate_at_physical_tile_side(physical_tile,
+                                                      pin_width_offset,
+                                                      pin_height_offset,
+                                                      pin_id, pin_side)) {
+
+        pin_ids.push_back(pin_id);
+      }
+    }
+  }
+
+  return pin_ids;
+}
+
+/***************************************************************************************
+ * Build the point-to-point direct connections based on 
+ *   - original VPR arch definition 
+ *     This is limited to the inner-column and inner-row connections
+ *
+ * Build the inner-column and inner-row connections
+ *
+ *     +------+
+ *     | Tile |
+ *     +------+            +------+    +------+
+ *        |           or   | Tile |--->| Tile |
+ *        v                +------+    +------+
+ *     +------+
+ *     | Tile |
+ *     +------+
+ *
+ ***************************************************************************************/
+static 
+void build_inner_column_row_tile_direct(TileDirect& tile_direct,
+                                        t_direct_inf& vpr_direct,
+                                        const DeviceContext& device_ctx,
+                                        const ArchDirectId& arch_direct_id) {
+  /* Get the source tile and pin information */
+  std::string from_tile_name = parse_direct_tile_name(std::string(vpr_direct.from_pin));
+  PortParser from_tile_port_parser(std::string(vpr_direct.from_pin));
+  const BasicPort& from_tile_port = from_tile_port_parser.port();
+
+  /* Get the sink tile and pin information */
+  std::string to_tile_name = parse_direct_tile_name(std::string(vpr_direct.to_pin));
+  PortParser to_tile_port_parser(std::string(vpr_direct.to_pin));
+  const BasicPort& to_tile_port = to_tile_port_parser.port();
+
+  /* Walk through the device fabric and find the grid that fit the source */
+  for (size_t x = 0; x < device_ctx.grid.width(); ++x) {
+    for (size_t y = 0; y < device_ctx.grid.height(); ++y) {
+      /* Bypass empty grid */
+      if (true == is_empty_type(device_ctx.grid[x][y].type)) {
+        continue;
+      }
+
+      /* Bypass the grid that does not fit the from_tile name */
+      if (from_tile_name != std::string(device_ctx.grid[x][y].type->name)) {
+        continue;
+      }
+      
+      /* Try to find the pin in this tile */
+      std::vector<size_t> from_pins = find_physical_tile_pin_id(device_ctx.grid[x][y].type,
+                                                               device_ctx.grid[x][y].width_offset,
+                                                               device_ctx.grid[x][y].height_offset,
+                                                               from_tile_port,
+                                                               vpr_direct.from_side);
+      /* If nothing found, we can continue */
+      if (0 == from_pins.size()) {
+        continue;
+      }
+      
+      /* We should try to the sink grid for inner-column/row direct connections */
+      vtr::Point<size_t> from_grid_coord(x, y);
+      vtr::Point<size_t> to_grid_coord(x + vpr_direct.x_offset, y + vpr_direct.y_offset);
+      if ((to_grid_coord.x() >= device_ctx.grid.width())
+       || (to_grid_coord.y() >= device_ctx.grid.height())) {
+        continue;
+      }
+
+      /* Bypass the grid that does not fit the from_tile name */
+      if (to_tile_name != std::string(device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].type->name)) {
+        continue;
+      }
+      /* Try to find the pin in this tile */
+      std::vector<size_t> to_pins = find_physical_tile_pin_id(device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].type,
+                                                              device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].width_offset,
+                                                              device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].height_offset,
+                                                              to_tile_port,
+                                                              vpr_direct.to_side);
+      /* If nothing found, we can continue */
+      if (0 == to_pins.size()) {
+        continue;
+      }
+
+      /* If from port and to port do not match in sizes, error out */
+      if (from_pins.size() != to_pins.size()) {
+        VTR_LOG_ERROR("From_port '%s[%lu:%lu] of direct '%s' does not match to_port '%s[%lu:%lu]'!\n",
+                      from_tile_port.get_name().c_str(),
+                      from_tile_port.get_lsb(),
+                      from_tile_port.get_msb(),
+                      vpr_direct.name,
+                      to_tile_port.get_name().c_str(),
+                      to_tile_port.get_lsb(),
+                      to_tile_port.get_msb());
+        exit(1);
+      }
+
+      /* Now add the tile direct */
+      for (size_t ipin = 0; ipin < from_pins.size(); ++ipin) {
+        TileDirectId tile_direct_id = tile_direct.add_direct(device_ctx.grid[x][y].type,
+                                                             from_grid_coord, vpr_direct.from_side, from_pins[ipin],
+                                                             device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].type,
+                                                             to_grid_coord, vpr_direct.to_side, to_pins[ipin]);
+        tile_direct.set_arch_direct_id(tile_direct_id, arch_direct_id);
+      }
+
+    }
+  }
+}
+
+/***************************************************************************************
+ * Build the point-to-point direct connections based on 
+ *   - OpenFPGA arch definition  
+ *     This is limited to the inter-column and inter-row connections
+ *
+ * Build the inter-column and inter-row connections
+ *
+ *     +------+     +------+
+ *     | Tile |     | Tile |
+ *     +------+     +------+
+ *        |            ^
+ *        |            |
+ *        +-------------
+ *
+ *     +------+
+ *     | Tile |-------+ 
+ *     +------+       |
+ *                    |
+ *     +------+       |
+ *     | Tile |<------+ 
+ *     +------+
+ *        
+ *
+ ***************************************************************************************/
+static 
+void build_inter_column_row_tile_direct(TileDirect& tile_direct,
+                                        t_direct_inf& vpr_direct,
+                                        const DeviceContext& device_ctx,
+                                        const ArchDirect& arch_direct,
+                                        const ArchDirectId& arch_direct_id,
+                                        const CircuitLibrary& circuit_lib) {
+  /* Get the source tile and pin information */
+  std::string from_tile_name = parse_direct_tile_name(std::string(vpr_direct.from_pin));
+  PortParser from_tile_port_parser(std::string(vpr_direct.from_pin));
+  const BasicPort& from_tile_port = from_tile_port_parser.port();
+
+  /* Get the sink tile and pin information */
+  std::string to_tile_name = parse_direct_tile_name(std::string(vpr_direct.to_pin));
+  PortParser to_tile_port_parser(std::string(vpr_direct.to_pin));
+  const BasicPort& to_tile_port = to_tile_port_parser.port();
+
+  /* Walk through the device fabric and find the grid that fit the source */
+  for (size_t x = 0; x < device_ctx.grid.width(); ++x) {
+    for (size_t y = 0; y < device_ctx.grid.height(); ++y) {
+      /* Bypass empty grid */
+      if (true == is_empty_type(device_ctx.grid[x][y].type)) {
+        continue;
+      }
+
+      /* Bypass the grid that does not fit the from_tile name */
+      if (from_tile_name != std::string(device_ctx.grid[x][y].type->name)) {
+        continue;
+      }
+      
+      /* Try to find the pin in this tile */
+      std::vector<size_t> from_pins = find_physical_tile_pin_id(device_ctx.grid[x][y].type,
+                                                               device_ctx.grid[x][y].width_offset,
+                                                               device_ctx.grid[x][y].height_offset,
+                                                               from_tile_port,
+                                                               vpr_direct.from_side);
+      /* If nothing found, we can continue */
+      if (0 == from_pins.size()) {
+        continue;
+      }
+      
+      /* We should try to the sink grid for inner-column/row direct connections */
+      vtr::Point<size_t> from_grid_coord(x, y);
+      vtr::Point<size_t> to_grid_coord(x + vpr_direct.x_offset, y + vpr_direct.y_offset);
+      if ((to_grid_coord.x() >= device_ctx.grid.width())
+       || (to_grid_coord.y() >= device_ctx.grid.height())) {
+        continue;
+      }
+
+      /* Bypass the grid that does not fit the from_tile name */
+      if (to_tile_name != std::string(device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].type->name)) {
+        continue;
+      }
+      /* Try to find the pin in this tile */
+      std::vector<size_t> to_pins = find_physical_tile_pin_id(device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].type,
+                                                              device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].width_offset,
+                                                              device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].height_offset,
+                                                              to_tile_port,
+                                                              vpr_direct.to_side);
+      /* If nothing found, we can continue */
+      if (0 == to_pins.size()) {
+        continue;
+      }
+
+      /* If from port and to port do not match in sizes, error out */
+      if (from_pins.size() != to_pins.size()) {
+        VTR_LOG_ERROR("From_port '%s[%lu:%lu] of direct '%s' does not match to_port '%s[%lu:%lu]'!\n",
+                      from_tile_port.get_name().c_str(),
+                      from_tile_port.get_lsb(),
+                      from_tile_port.get_msb(),
+                      vpr_direct.name,
+                      to_tile_port.get_name().c_str(),
+                      to_tile_port.get_lsb(),
+                      to_tile_port.get_msb());
+        exit(1);
+      }
+
+      /* Now add the tile direct */
+      for (size_t ipin = 0; ipin < from_pins.size(); ++ipin) {
+        TileDirectId tile_direct_id = tile_direct.add_direct(device_ctx.grid[x][y].type,
+                                                             from_grid_coord, vpr_direct.from_side, from_pins[ipin],
+                                                             device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].type,
+                                                             to_grid_coord, vpr_direct.to_side, to_pins[ipin]);
+        tile_direct.set_arch_direct_id(tile_direct_id, arch_direct_id);
+      }
+
+    }
+  }
+}
+
+/***************************************************************************************
+ * Top-level functions that build the point-to-point direct connections
+ * between tiles (programmable blocks) 
+ ***************************************************************************************/
+TileDirect build_device_tile_direct(const DeviceContext& device_ctx,
+                                    const ArchDirect& arch_direct,
+                                    const CircuitLibrary& circuit_lib) {
+  vtr::ScopedStartFinishTimer timer("Build the annotation about direct connection between tiles");
+
+  TileDirect tile_direct;
+
+  /* Walk through each direct definition in the VPR arch */
+  for (int idirect = 0; idirect < device_ctx.arch->num_directs; ++idirect) {
+    ArchDirectId arch_direct_id = arch_direct.direct(std::string(device_ctx.arch->Directs[idirect].name));
+    VTR_ASSERT(ArchDirectId::INVALID() != arch_direct_id);
+    /* Build from original VPR arch definition */
+    build_inner_column_row_tile_direct(tile_direct,
+                                       device_ctx.arch->Directs[idirect],
+                                       device_ctx,
+                                       arch_direct_id);
+   /* TODO: Build from OpenFPGA arch definition */ 
+  } 
+
+  return tile_direct;
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/tile_direct/build_tile_direct.h b/openfpga/src/tile_direct/build_tile_direct.h
new file mode 100644
index 000000000..08d0397ce
--- /dev/null
+++ b/openfpga/src/tile_direct/build_tile_direct.h
@@ -0,0 +1,25 @@
+#ifndef BUILD_TILE_DIRECT_H
+#define BUILD_TILE_DIRECT_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "vpr_context.h"
+#include "arch_direct.h"
+#include "tile_direct.h"
+#include "circuit_library.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+TileDirect build_device_tile_direct(const DeviceContext& device_ctx,
+                                    const ArchDirect& arch_direct,
+                                    const CircuitLibrary& circuit_lib);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/tile_direct/tile_direct.cpp b/openfpga/src/tile_direct/tile_direct.cpp
index 0face1b7e..d0d1f6122 100644
--- a/openfpga/src/tile_direct/tile_direct.cpp
+++ b/openfpga/src/tile_direct/tile_direct.cpp
@@ -63,6 +63,12 @@ e_side TileDirect::to_tile_side(const TileDirectId& direct_id) const {
   return to_tile_sides_[direct_id];
 }
 
+ArchDirectId TileDirect::arch_direct(const TileDirectId& direct_id) const {
+  /* Validate the direct_id */
+  VTR_ASSERT(valid_direct_id(direct_id));
+  return arch_directs_[direct_id];
+}
+
 /******************************************************************************
  * Private Mutators
  ******************************************************************************/
@@ -89,9 +95,18 @@ TileDirectId TileDirect::add_direct(t_physical_tile_type_ptr from_tile,
   to_tile_sides_.push_back(to_tile_side);
   to_tile_pins_.push_back(to_tile_pin);
 
+  arch_directs_.emplace_back(ArchDirectId::INVALID());
+
   return direct;
 }
 
+void TileDirect::set_arch_direct_id(const TileDirectId& tile_direct_id, 
+                                    const ArchDirectId& arch_direct_id) {
+  /* Validate the direct_id */
+  VTR_ASSERT(valid_direct_id(tile_direct_id));
+  arch_directs_[tile_direct_id] = arch_direct_id;
+}
+
 /******************************************************************************
  * Private validators/invalidators
  ******************************************************************************/
diff --git a/openfpga/src/tile_direct/tile_direct.h b/openfpga/src/tile_direct/tile_direct.h
index 562b559ca..d8d0e180f 100644
--- a/openfpga/src/tile_direct/tile_direct.h
+++ b/openfpga/src/tile_direct/tile_direct.h
@@ -11,6 +11,9 @@
 /* Headers from readarch library */
 #include "physical_types.h"
 
+/* Headers from readarchopenfpga library */
+#include "arch_direct.h"
+
 #include "tile_direct_fwd.h"
 
 /* Begin namespace openfpga */
@@ -38,6 +41,7 @@ class TileDirect {
     vtr::Point<size_t> to_tile_coordinate(const TileDirectId& direct_id) const;
     e_side to_tile_side(const TileDirectId& direct_id) const;
     size_t to_tile_pin(const TileDirectId& direct_id) const;
+    ArchDirectId arch_direct(const TileDirectId& direct_id) const;
   public: /* Public mutators */
     TileDirectId add_direct(t_physical_tile_type_ptr from_tile,
                             const vtr::Point<size_t>& from_tile_coord,
@@ -47,6 +51,8 @@ class TileDirect {
                             const vtr::Point<size_t>& to_tile_coord,
                             const e_side& to_tile_side,
                             const size_t& to_tile_pin);
+    void set_arch_direct_id(const TileDirectId& tile_direct_id, 
+                            const ArchDirectId& arch_direct_id);
   public: /* Public validators/invalidators */
     bool valid_direct_id(const TileDirectId& direct_id) const;
   private: /* Internal Data */
@@ -71,6 +77,8 @@ class TileDirect {
     vtr::vector<TileDirectId, vtr::Point<size_t>> to_tile_coords_;
     vtr::vector<TileDirectId, e_side> to_tile_sides_;
     vtr::vector<TileDirectId, size_t> to_tile_pins_;
+
+    vtr::vector<TileDirectId, ArchDirectId> arch_directs_;
 };
 
 } /* End namespace openfpga*/

From 539f13720a1f0d1e6968d6983c72486b3f54866c Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 15 Feb 2020 13:42:53 -0700
Subject: [PATCH 142/645] tile direct supports inter-column/inter-row direct
 connections

---
 openfpga/src/base/openfpga_link_arch.cpp      |  27 +-
 .../src/fabric/build_top_module_directs.cpp   | 151 ++++++
 .../src/fabric/build_top_module_directs.h     |  33 ++
 .../src/tile_direct/build_tile_direct.cpp     | 471 +++++++++++++++---
 openfpga/src/tile_direct/build_tile_direct.h  |   3 +-
 openfpga/src/tile_direct/tile_direct.cpp      |  18 +-
 openfpga/src/tile_direct/tile_direct.h        |   8 +-
 7 files changed, 590 insertions(+), 121 deletions(-)
 create mode 100644 openfpga/src/fabric/build_top_module_directs.cpp
 create mode 100644 openfpga/src/fabric/build_top_module_directs.h

diff --git a/openfpga/src/base/openfpga_link_arch.cpp b/openfpga/src/base/openfpga_link_arch.cpp
index 7ee522b6a..567ad2e08 100644
--- a/openfpga/src/base/openfpga_link_arch.cpp
+++ b/openfpga/src/base/openfpga_link_arch.cpp
@@ -53,7 +53,7 @@ bool is_vpr_rr_graph_supported(const RRGraph& rr_graph) {
  * - physical pb_graph nodes and pb_graph pins
  * - circuit models for global routing architecture
  *******************************************************************/
-void link_arch(OpenfpgaContext& openfpga_context,
+void link_arch(OpenfpgaContext& openfpga_ctx,
                const Command& cmd, const CommandContext& cmd_context) { 
 
   vtr::ScopedStartFinishTimer timer("Link OpenFPGA architecture to VPR architecture");
@@ -65,8 +65,8 @@ void link_arch(OpenfpgaContext& openfpga_context,
    * - mode selection bits for pb_type and pb interconnect
    * - circuit models for pb_type and pb interconnect
    */
-  annotate_pb_types(g_vpr_ctx.device(), openfpga_context.arch(),
-                    openfpga_context.mutable_vpr_device_annotation(),
+  annotate_pb_types(g_vpr_ctx.device(), openfpga_ctx.arch(),
+                    openfpga_ctx.mutable_vpr_device_annotation(),
                     cmd_context.option_enable(cmd, opt_verbose));
 
   /* Annotate pb_graph_nodes
@@ -75,21 +75,21 @@ void link_arch(OpenfpgaContext& openfpga_context,
    * - Bind pins from operating pb_graph_node to their physical pb_graph_node pins
    */
   annotate_pb_graph(g_vpr_ctx.device(),
-                    openfpga_context.mutable_vpr_device_annotation(),
+                    openfpga_ctx.mutable_vpr_device_annotation(),
                     cmd_context.option_enable(cmd, opt_verbose));
 
   /* Annotate routing architecture to circuit library */
   annotate_rr_graph_circuit_models(g_vpr_ctx.device(),
-                                   openfpga_context.arch(),
-                                   openfpga_context.mutable_vpr_device_annotation(),
+                                   openfpga_ctx.arch(),
+                                   openfpga_ctx.mutable_vpr_device_annotation(),
                                    cmd_context.option_enable(cmd, opt_verbose));
 
   /* Annotate net mapping to each rr_node 
    */
-  openfpga_context.mutable_vpr_routing_annotation().init(g_vpr_ctx.device().rr_graph);
+  openfpga_ctx.mutable_vpr_routing_annotation().init(g_vpr_ctx.device().rr_graph);
 
   annotate_rr_node_nets(g_vpr_ctx.device(), g_vpr_ctx.clustering(), g_vpr_ctx.routing(), 
-                        openfpga_context.mutable_vpr_routing_annotation(),
+                        openfpga_ctx.mutable_vpr_routing_annotation(),
                         cmd_context.option_enable(cmd, opt_verbose));
 
   /* Build the routing graph annotation
@@ -101,17 +101,16 @@ void link_arch(OpenfpgaContext& openfpga_context,
   }
 
   annotate_device_rr_gsb(g_vpr_ctx.device(),
-                         openfpga_context.mutable_device_rr_gsb(),
+                         openfpga_ctx.mutable_device_rr_gsb(),
                          cmd_context.option_enable(cmd, opt_verbose));
 
   /* Build multiplexer library */
-  openfpga_context.mutable_mux_lib() = build_device_mux_library(g_vpr_ctx.device(),
-                                                                const_cast<const OpenfpgaContext&>(openfpga_context)); 
+  openfpga_ctx.mutable_mux_lib() = build_device_mux_library(g_vpr_ctx.device(),
+                                                            const_cast<const OpenfpgaContext&>(openfpga_ctx)); 
 
   /* Build tile direct annotation */
-  openfpga_context.mutable_tile_direct() =  build_device_tile_direct(g_vpr_ctx.device(),
-                                                                     openfpga_context.arch().arch_direct,
-                                                                     openfpga_context.arch().circuit_lib);
+  openfpga_ctx.mutable_tile_direct() =  build_device_tile_direct(g_vpr_ctx.device(),
+                                                                 openfpga_ctx.arch().arch_direct);
 
 } 
 
diff --git a/openfpga/src/fabric/build_top_module_directs.cpp b/openfpga/src/fabric/build_top_module_directs.cpp
new file mode 100644
index 000000000..63d4a1882
--- /dev/null
+++ b/openfpga/src/fabric/build_top_module_directs.cpp
@@ -0,0 +1,151 @@
+/********************************************************************
+ * This file includes functions that are used to add module nets
+ * for direct connections between CLBs/heterogeneous blocks
+ * in the top-level module of a FPGA fabric
+ *******************************************************************/
+#include <algorithm>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_port.h"
+
+/* Headers from vpr library */
+#include "vpr_utils.h"
+
+#include "openfpga_reserved_words.h"
+#include "openfpga_naming.h"
+#include "module_manager_utils.h"
+
+#include "build_top_module_directs.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Add module net for one direction connection between two CLBs or
+ * two grids
+ * This function will 
+ * 1. find the pin id and port id of the source clb port in module manager
+ * 2. find the pin id and port id of the destination clb port in module manager
+ * 3. add a direct connection module to the top module 
+ * 4. add a first module net and configure its source and sink, 
+ * in order to connect the source pin to the input of the top module
+ * 4. add a second module net and configure its source and sink, 
+ * in order to connect the sink pin to the output of the top module
+ *******************************************************************/
+static 
+void add_module_nets_tile_direct_connection(ModuleManager& module_manager, 
+                                            const ModuleId& top_module,  
+                                            const CircuitLibrary& circuit_lib, 
+                                            const DeviceGrid& grids,
+                                            const vtr::Matrix<size_t>& grid_instance_ids,
+                                            const TileDirect& tile_direct,
+                                            const TileDirectId& tile_direct_id,
+                                            const ArchDirect& arch_direct) {
+  vtr::Point<size_t> device_size(grids.width(), grids.height());
+
+  /* Find the module name of source clb */
+  vtr::Point<size_t> src_clb_coord = tile_direct.from_tile_coordinate(tile_direct_id);
+  t_physical_tile_type_ptr src_grid_type = grids[src_clb_coord.x()][src_clb_coord.y()].type;
+  e_side src_grid_border_side = find_grid_border_side(device_size, src_clb_coord);
+  std::string src_module_name_prefix(GRID_MODULE_NAME_PREFIX);
+  std::string src_module_name = generate_grid_block_module_name(src_module_name_prefix, std::string(src_grid_type->name), is_io_type(src_grid_type), src_grid_border_side);
+  ModuleId src_grid_module = module_manager.find_module(src_module_name);
+  VTR_ASSERT(true == module_manager.valid_module_id(src_grid_module));
+  /* Record the instance id */
+  size_t src_grid_instance = grid_instance_ids[src_clb_coord.x()][src_clb_coord.y()];
+
+  /* Find the module name of sink clb */
+  vtr::Point<size_t> des_clb_coord = tile_direct.to_tile_coordinate(tile_direct_id);
+  t_physical_tile_type_ptr sink_grid_type = grids[des_clb_coord.x()][des_clb_coord.y()].type;
+  e_side sink_grid_border_side = find_grid_border_side(device_size, des_clb_coord);
+  std::string sink_module_name_prefix(GRID_MODULE_NAME_PREFIX);
+  std::string sink_module_name = generate_grid_block_module_name(sink_module_name_prefix, std::string(sink_grid_type->name), is_io_type(sink_grid_type), sink_grid_border_side);
+  ModuleId sink_grid_module = module_manager.find_module(sink_module_name);
+  VTR_ASSERT(true == module_manager.valid_module_id(sink_grid_module));
+  /* Record the instance id */
+  size_t sink_grid_instance = grid_instance_ids[des_clb_coord.x()][des_clb_coord.y()];
+
+  /* Find the module id of a direct connection module */
+  CircuitModelId direct_circuit_model = arch_direct.circuit_model(tile_direct.arch_direct(tile_direct_id));
+  std::string direct_module_name = circuit_lib.model_name(direct_circuit_model);
+  ModuleId direct_module = module_manager.find_module(direct_module_name);
+  VTR_ASSERT(true == module_manager.valid_module_id(direct_module));
+
+  /* Find inputs and outputs of the direct circuit module */
+  std::vector<CircuitPortId> direct_input_ports = circuit_lib.model_ports_by_type(direct_circuit_model, CIRCUIT_MODEL_PORT_INPUT, true);
+  VTR_ASSERT(1 == direct_input_ports.size());
+  ModulePortId direct_input_port_id = module_manager.find_module_port(direct_module, circuit_lib.port_prefix(direct_input_ports[0]));
+  VTR_ASSERT(true == module_manager.valid_module_port_id(direct_module, direct_input_port_id));
+  VTR_ASSERT(1 == module_manager.module_port(direct_module, direct_input_port_id).get_width());
+
+  std::vector<CircuitPortId> direct_output_ports = circuit_lib.model_ports_by_type(direct_circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
+  VTR_ASSERT(1 == direct_output_ports.size());
+  ModulePortId direct_output_port_id = module_manager.find_module_port(direct_module, circuit_lib.port_prefix(direct_output_ports[0]));
+  VTR_ASSERT(true == module_manager.valid_module_port_id(direct_module, direct_output_port_id));
+  VTR_ASSERT(1 == module_manager.module_port(direct_module, direct_output_port_id).get_width());
+
+  /* Generate the pin name of source port/pin in the grid */
+  e_side src_pin_grid_side = tile_direct.from_tile_side(tile_direct_id);
+  size_t src_tile_pin = tile_direct.from_tile_pin(tile_direct_id);
+  size_t src_pin_width = grids[src_clb_coord.x()][src_clb_coord.y()].type->pin_width_offset[src_tile_pin]; 
+  size_t src_pin_height = grids[src_clb_coord.x()][src_clb_coord.y()].type->pin_height_offset[src_tile_pin]; 
+  std::string src_port_name = generate_grid_port_name(src_clb_coord, src_pin_width, src_pin_height, src_pin_grid_side, src_tile_pin, false);
+  ModulePortId src_port_id = module_manager.find_module_port(src_grid_module, src_port_name); 
+  VTR_ASSERT(true == module_manager.valid_module_port_id(src_grid_module, src_port_id));
+  VTR_ASSERT(1 == module_manager.module_port(src_grid_module, src_port_id).get_width());
+
+  /* Generate the pin name of sink port/pin in the grid */
+  e_side sink_pin_grid_side = tile_direct.to_tile_side(tile_direct_id);
+  size_t sink_tile_pin = tile_direct.to_tile_pin(tile_direct_id);
+  size_t sink_pin_width = grids[des_clb_coord.x()][des_clb_coord.y()].type->pin_width_offset[src_tile_pin]; 
+  size_t sink_pin_height = grids[des_clb_coord.x()][des_clb_coord.y()].type->pin_height_offset[src_tile_pin]; 
+
+  std::string sink_port_name = generate_grid_port_name(des_clb_coord, sink_pin_width, sink_pin_height, sink_pin_grid_side, sink_tile_pin, false);
+  ModulePortId sink_port_id = module_manager.find_module_port(sink_grid_module, sink_port_name); 
+  VTR_ASSERT(true == module_manager.valid_module_port_id(sink_grid_module, sink_port_id));
+  VTR_ASSERT(1 == module_manager.module_port(sink_grid_module, sink_port_id).get_width());
+
+  /* Add a submodule of direct connection module to the top-level module */
+  size_t direct_instance_id = module_manager.num_instance(top_module, direct_module);
+  module_manager.add_child_module(top_module, direct_module);
+
+  /* Create the 1st module net */
+  ModuleNetId net_direct_src = module_manager.create_module_net(top_module); 
+  /* Connect the wire between src_pin of clb and direct_instance input*/
+  module_manager.add_module_net_source(top_module, net_direct_src, src_grid_module, src_grid_instance, src_port_id, 0);
+  module_manager.add_module_net_sink(top_module, net_direct_src, direct_module, direct_instance_id, direct_input_port_id, 0);
+
+  /* Create the 2nd module net */
+  ModuleNetId net_direct_sink = module_manager.create_module_net(top_module); 
+  /* Connect the wire between direct_instance output and sink_pin of clb */
+  module_manager.add_module_net_source(top_module, net_direct_sink, direct_module, direct_instance_id, direct_output_port_id, 0);
+  module_manager.add_module_net_sink(top_module, net_direct_sink, sink_grid_module, sink_grid_instance, sink_port_id, 0);
+}
+
+/********************************************************************
+ * Add module net of clb-to-clb direct connections to module manager
+ * Note that the direct connections are not limited to CLBs only.
+ * It can be more generic and thus cover all the grid types,
+ * such as heterogeneous blocks
+ *******************************************************************/
+void add_top_module_nets_tile_direct_connections(ModuleManager& module_manager, 
+                                                 const ModuleId& top_module, 
+                                                 const CircuitLibrary& circuit_lib, 
+                                                 const DeviceGrid& grids,
+                                                 const vtr::Matrix<size_t>& grid_instance_ids,
+                                                 const TileDirect& tile_direct,
+                                                 const ArchDirect& arch_direct) {
+
+  for (const TileDirectId& tile_direct_id : tile_direct.directs()) {
+    add_module_nets_tile_direct_connection(module_manager, top_module, circuit_lib, 
+                                           grids, grid_instance_ids,
+                                           tile_direct, tile_direct_id,  
+                                           arch_direct);
+  }
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fabric/build_top_module_directs.h b/openfpga/src/fabric/build_top_module_directs.h
new file mode 100644
index 000000000..e9855db70
--- /dev/null
+++ b/openfpga/src/fabric/build_top_module_directs.h
@@ -0,0 +1,33 @@
+#ifndef BUILD_TOP_MODULE_DIRECTS_H
+#define BUILD_TOP_MODULE_DIRECTS_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <vector>
+#include "vtr_geometry.h"
+#include "vtr_ndmatrix.h"
+#include "arch_direct.h"
+#include "tile_direct.h"
+#include "device_grid.h"
+#include "module_manager.h"
+#include "circuit_library.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void add_top_module_nets_tile_direct_connections(ModuleManager& module_manager, 
+                                                 const ModuleId& top_module, 
+                                                 const CircuitLibrary& circuit_lib, 
+                                                 const DeviceGrid& grids,
+                                                 const vtr::Matrix<size_t>& grid_instance_ids,
+                                                 const TileDirect& tile_direct,
+                                                 const ArchDirect& arch_direct);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/tile_direct/build_tile_direct.cpp b/openfpga/src/tile_direct/build_tile_direct.cpp
index 5a40e2ca5..a99370a0b 100644
--- a/openfpga/src/tile_direct/build_tile_direct.cpp
+++ b/openfpga/src/tile_direct/build_tile_direct.cpp
@@ -119,26 +119,250 @@ std::vector<size_t> find_physical_tile_pin_id(t_physical_tile_type_ptr physical_
   return pin_ids;
 }
 
+/********************************************************************
+ * Check if the grid coorindate given is in the device grid range 
+ *******************************************************************/
+static 
+bool is_grid_coordinate_exist_in_device(const DeviceGrid& device_grid,
+                                        const vtr::Point<size_t>& grid_coordinate) {
+  return (grid_coordinate < vtr::Point<size_t>(device_grid.width(), device_grid.height()));
+}
+
+/********************************************************************
+ * Find the coordinate of a grid in a specific column 
+ * with a given type
+ * This function will return the coordinate of the grid that satifies
+ * the type requirement
+ *******************************************************************/
+static 
+vtr::Point<size_t> find_grid_coordinate_given_type(const DeviceGrid& grids,
+                                                   const std::vector<vtr::Point<size_t>>& candidate_coords, 
+                                                   const std::string& wanted_grid_type_name) {
+  for (vtr::Point<size_t> coord : candidate_coords) {
+    /* If the next column is not longer in device range, we can return */
+    if (false == is_grid_coordinate_exist_in_device(grids, coord)) {
+      continue;
+    }
+    if (wanted_grid_type_name == std::string(grids[coord.x()][coord.y()].type->name)) {
+      return coord;
+    }
+  }
+  /* Return an valid coordinate */
+  return vtr::Point<size_t>(grids.width(), grids.height()); 
+}
+
+/********************************************************************
+ * Find the coordinate of the destination clb/heterogeneous block
+ * considering intra column/row direct connections in core grids
+ *******************************************************************/
+static 
+vtr::Point<size_t> find_inter_direct_destination_coordinate(const DeviceGrid& grids,
+                                                            const vtr::Point<size_t>& src_coord,
+                                                            const std::string des_tile_type_name,
+                                                            const ArchDirect& arch_direct,
+                                                            const ArchDirectId& arch_direct_id) {
+  vtr::Point<size_t> des_coord(grids.width(), grids.height());
+
+  std::vector<size_t> first_search_space;
+  std::vector<size_t> second_search_space;
+
+  /* Cross column connection from Bottom to Top on Right 
+   * The next column may NOT have the grid type we want!
+   * Think about heterogeneous architecture!  
+   * Our search space will start from the next column 
+   * and ends at the RIGHT side of fabric 
+   */
+  if (INTER_COLUMN == arch_direct.type(arch_direct_id)) {
+    if (POSITIVE_DIR == arch_direct.x_dir(arch_direct_id)) {
+     /* Our first search space will be in x-direction:
+      *
+      *      x      ...      nx 
+      *   +-----+
+      *   |Grid |  ----->
+      *   +-----+
+      */
+      for (size_t ix = src_coord.x() + 1; ix < grids.width() - 1; ++ix) {
+        first_search_space.push_back(ix);
+      }
+    } else { 
+      VTR_ASSERT(NEGATIVE_DIR == arch_direct.x_dir(arch_direct_id));
+     /* Our first search space will be in x-direction:
+      *
+      *    1   ...      x    
+      *              +-----+
+      *     < -------|Grid | 
+      *              +-----+
+      */
+      for (size_t ix = src_coord.x() - 1; ix >= 1; --ix) {
+        first_search_space.push_back(ix);
+      }
+    }
+
+    /* Our second search space will be in y-direction:
+     *
+     *  +------+  
+     *  | Grid | ny
+     *  +------+
+     *     |     .
+     *     |     .
+     *     v     .
+     *  +------+
+     *  | Grid | 1
+     *  +------+
+     */
+    for (size_t iy = 1 ; iy < grids.height() - 1; ++iy) {
+      second_search_space.push_back(iy);
+    }
+
+    /* For negative direction, our second search space will be in y-direction:
+     *
+     *  +------+  
+     *  | Grid | ny
+     *  +------+
+     *     ^     .
+     *     |     .
+     *     |     .
+     *  +------+
+     *  | Grid | 1
+     *  +------+
+     */
+    if (NEGATIVE_DIR == arch_direct.y_dir(arch_direct_id)) {
+      std::reverse(second_search_space.begin(), second_search_space.end());
+    }
+  }
+
+
+  /* Cross row connection from Bottom to Top on Right 
+   * The next column may NOT have the grid type we want!
+   * Think about heterogeneous architecture!  
+   * Our search space will start from the next column 
+   * and ends at the RIGHT side of fabric 
+   */
+  if (INTER_ROW == arch_direct.type(arch_direct_id)) {
+    if (POSITIVE_DIR == arch_direct.y_dir(arch_direct_id)) {
+     /* Our first search space will be in y-direction:
+      *
+      *  +------+  
+      *  | Grid | ny
+      *  +------+
+      *     ^     .
+      *     |     .
+      *     |     .
+      *  +------+
+      *  | Grid | y
+      *  +------+
+      */
+      for (size_t iy = src_coord.y() + 1; iy < grids.height() - 1; ++iy) {
+        first_search_space.push_back(iy);
+      }
+    } else { 
+      VTR_ASSERT(NEGATIVE_DIR == arch_direct.y_dir(arch_direct_id));
+      /* For negative y-direction,
+       * Our first search space will be in y-direction:
+       *
+       *  +------+  
+       *  | Grid | ny
+       *  +------+
+       *     |     .
+       *     |     .
+       *     v     .
+       *  +------+
+       *  | Grid | y
+       *  +------+
+       */
+      for (size_t iy = src_coord.y() - 1; iy >= 1; --iy) {
+        first_search_space.push_back(iy);
+      }
+    }
+
+    /* Our second search space will be in x-direction:
+     *
+     *     1      ...     nx
+     *  +------+       +------+
+     *  | Grid |------>| Grid |
+     *  +------+       +------+
+     */
+    for (size_t ix = 1 ; ix < grids.width() - 1; ++ix) {
+      second_search_space.push_back(ix);
+    }
+
+    /* For negative direction,
+     * our second search space will be in x-direction:
+     *
+     *     1      ...     nx
+     *  +------+       +------+
+     *  | Grid |<------| Grid |
+     *  +------+       +------+
+     */
+    if (NEGATIVE_DIR == arch_direct.x_dir(arch_direct_id)) {
+      std::reverse(second_search_space.begin(), second_search_space.end());
+    }
+  }
+
+  for (size_t ix : first_search_space) {
+    std::vector<vtr::Point<size_t>> next_col_row_coords;
+    for (size_t iy : second_search_space) {
+      if (INTER_COLUMN == arch_direct.type(arch_direct_id)) {
+        next_col_row_coords.push_back(vtr::Point<size_t>(ix, iy));
+      } else {
+        VTR_ASSERT(INTER_ROW == arch_direct.type(arch_direct_id));
+        /* For cross-row connection, our search space is flipped */
+        next_col_row_coords.push_back(vtr::Point<size_t>(iy, ix));
+      }
+    }
+    vtr::Point<size_t> des_coord_cand = find_grid_coordinate_given_type(grids, next_col_row_coords, des_tile_type_name); 
+    /* For a valid coordinate, we can return */
+    if (true == is_grid_coordinate_exist_in_device(grids, des_coord_cand)) {
+      return des_coord_cand;
+    }
+  }
+  return des_coord;
+}
+
+/***************************************************************************************
+ * Report error for port matching failure
+ ***************************************************************************************/
+static 
+void report_direct_from_port_and_to_port_mismatch(const t_direct_inf& vpr_direct, 
+                                                  const BasicPort& from_tile_port,
+                                                  const BasicPort& to_tile_port) {
+  VTR_LOG_ERROR("From_port '%s[%lu:%lu] of direct '%s' does not match to_port '%s[%lu:%lu]'!\n",
+                from_tile_port.get_name().c_str(),
+                from_tile_port.get_lsb(),
+                from_tile_port.get_msb(),
+                vpr_direct.name,
+                to_tile_port.get_name().c_str(),
+                to_tile_port.get_lsb(),
+                to_tile_port.get_msb());
+}
+
 /***************************************************************************************
  * Build the point-to-point direct connections based on 
  *   - original VPR arch definition 
  *     This is limited to the inner-column and inner-row connections
+ * Note that the direct connections are not limited to CLBs only.
+ * It can be more generic and thus cover all the grid types,
+ * such as heterogeneous blocks
  *
- * Build the inner-column and inner-row connections
- *
- *     +------+
- *     | Tile |
- *     +------+            +------+    +------+
- *        |           or   | Tile |--->| Tile |
- *        v                +------+    +------+
+ * This function supports the following type of direct connection:
+ * 1. Direct connection between tiles in the same column or row
+ *     +------+      +------+
+ *     |      |      |      |
+ *     | Tile |----->| Tile |
+ *     |      |      |      |
+ *     +------+      +------+
+ *         | direction connection 
+ *         v
  *     +------+
+ *     |      |
  *     | Tile |
+ *     |      |
  *     +------+
  *
  ***************************************************************************************/
 static 
 void build_inner_column_row_tile_direct(TileDirect& tile_direct,
-                                        t_direct_inf& vpr_direct,
+                                        const t_direct_inf& vpr_direct,
                                         const DeviceContext& device_ctx,
                                         const ArchDirectId& arch_direct_id) {
   /* Get the source tile and pin information */
@@ -166,10 +390,10 @@ void build_inner_column_row_tile_direct(TileDirect& tile_direct,
       
       /* Try to find the pin in this tile */
       std::vector<size_t> from_pins = find_physical_tile_pin_id(device_ctx.grid[x][y].type,
-                                                               device_ctx.grid[x][y].width_offset,
-                                                               device_ctx.grid[x][y].height_offset,
-                                                               from_tile_port,
-                                                               vpr_direct.from_side);
+                                                                device_ctx.grid[x][y].width_offset,
+                                                                device_ctx.grid[x][y].height_offset,
+                                                                from_tile_port,
+                                                                vpr_direct.from_side);
       /* If nothing found, we can continue */
       if (0 == from_pins.size()) {
         continue;
@@ -178,8 +402,7 @@ void build_inner_column_row_tile_direct(TileDirect& tile_direct,
       /* We should try to the sink grid for inner-column/row direct connections */
       vtr::Point<size_t> from_grid_coord(x, y);
       vtr::Point<size_t> to_grid_coord(x + vpr_direct.x_offset, y + vpr_direct.y_offset);
-      if ((to_grid_coord.x() >= device_ctx.grid.width())
-       || (to_grid_coord.y() >= device_ctx.grid.height())) {
+      if (false == is_grid_coordinate_exist_in_device(device_ctx.grid, to_grid_coord)) {
         continue;
       }
 
@@ -200,61 +423,60 @@ void build_inner_column_row_tile_direct(TileDirect& tile_direct,
 
       /* If from port and to port do not match in sizes, error out */
       if (from_pins.size() != to_pins.size()) {
-        VTR_LOG_ERROR("From_port '%s[%lu:%lu] of direct '%s' does not match to_port '%s[%lu:%lu]'!\n",
-                      from_tile_port.get_name().c_str(),
-                      from_tile_port.get_lsb(),
-                      from_tile_port.get_msb(),
-                      vpr_direct.name,
-                      to_tile_port.get_name().c_str(),
-                      to_tile_port.get_lsb(),
-                      to_tile_port.get_msb());
+        report_direct_from_port_and_to_port_mismatch(vpr_direct, from_tile_port, to_tile_port);
         exit(1);
       }
 
       /* Now add the tile direct */
       for (size_t ipin = 0; ipin < from_pins.size(); ++ipin) {
-        TileDirectId tile_direct_id = tile_direct.add_direct(device_ctx.grid[x][y].type,
-                                                             from_grid_coord, vpr_direct.from_side, from_pins[ipin],
-                                                             device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].type,
+        TileDirectId tile_direct_id = tile_direct.add_direct(from_grid_coord, vpr_direct.from_side, from_pins[ipin],
                                                              to_grid_coord, vpr_direct.to_side, to_pins[ipin]);
         tile_direct.set_arch_direct_id(tile_direct_id, arch_direct_id);
       }
-
     }
   }
 }
 
-/***************************************************************************************
+/********************************************************************
  * Build the point-to-point direct connections based on 
  *   - OpenFPGA arch definition  
  *     This is limited to the inter-column and inter-row connections
  *
- * Build the inter-column and inter-row connections
+ * Note that the direct connections are not limited to CLBs only.
+ * It can be more generic and thus cover all the grid types,
+ * such as heterogeneous blocks
  *
- *     +------+     +------+
- *     | Tile |     | Tile |
- *     +------+     +------+
- *        |            ^
- *        |            |
- *        +-------------
+ * This function supports the following type of direct connection:
  *
- *     +------+
- *     | Tile |-------+ 
- *     +------+       |
- *                    |
- *     +------+       |
- *     | Tile |<------+ 
- *     +------+
- *        
+ * 1. Direct connections across columns and rows 
+ *               +------+
+ *               |      |
+ *               |      v 
+ *     +------+  |   +------+
+ *     |      |  |   |      |
+ *     | Grid |  |   | Grid |
+ *     |      |  |   |      |
+ *     +------+  |   +------+
+ *               |
+ *     +------+  |   +------+
+ *     |      |  |   |      |
+ *     | Grid |  |   | Grid |
+ *     |      |  |   |      |
+ *     +------+  |   +------+
+ *        |      |
+ *        +------+
  *
- ***************************************************************************************/
+ * Note that: this will only apply to the core grids!
+ *            I/Os or any blocks on the border of fabric are NOT supported!
+ *
+ *******************************************************************/
 static 
 void build_inter_column_row_tile_direct(TileDirect& tile_direct,
-                                        t_direct_inf& vpr_direct,
+                                        const t_direct_inf& vpr_direct,
                                         const DeviceContext& device_ctx,
                                         const ArchDirect& arch_direct,
-                                        const ArchDirectId& arch_direct_id,
-                                        const CircuitLibrary& circuit_lib) {
+                                        const ArchDirectId& arch_direct_id) {
+
   /* Get the source tile and pin information */
   std::string from_tile_name = parse_direct_tile_name(std::string(vpr_direct.from_pin));
   PortParser from_tile_port_parser(std::string(vpr_direct.from_pin));
@@ -265,42 +487,63 @@ void build_inter_column_row_tile_direct(TileDirect& tile_direct,
   PortParser to_tile_port_parser(std::string(vpr_direct.to_pin));
   const BasicPort& to_tile_port = to_tile_port_parser.port();
 
-  /* Walk through the device fabric and find the grid that fit the source */
-  for (size_t x = 0; x < device_ctx.grid.width(); ++x) {
-    for (size_t y = 0; y < device_ctx.grid.height(); ++y) {
-      /* Bypass empty grid */
-      if (true == is_empty_type(device_ctx.grid[x][y].type)) {
-        continue;
+  /* Go through the direct connection list, see if we need intra-column/row connection here */
+  if ( (INTER_COLUMN != arch_direct.type(arch_direct_id))
+    && (INTER_ROW != arch_direct.type(arch_direct_id))) {
+    return;
+  }
+  /* For cross-column connection, we will search the first valid grid in each column 
+   * from y = 1 to y = ny
+   *
+   *   +------+
+   *   | Grid |  y=ny
+   *   +------+
+   *      ^
+   *      |  search direction (when y_dir is negative)
+   *     ...
+   *      |
+   *   +------+
+   *   | Grid |  y=1
+   *   +------+
+   * 
+   */
+  if (INTER_COLUMN == arch_direct.type(arch_direct_id)) {
+    for (size_t ix = 1; ix < device_ctx.grid.width() - 1; ++ix) {
+      std::vector<vtr::Point<size_t>> next_col_src_grid_coords;
+      /* For negative y- direction, we should start from y = ny */
+      for (size_t iy = 1; iy < device_ctx.grid.height() - 1; ++iy) {
+        next_col_src_grid_coords.push_back(vtr::Point<size_t>(ix, iy));
+      }
+      /* For positive y- direction, we should start from y = 1 */
+      if (POSITIVE_DIR == arch_direct.y_dir(arch_direct_id)) {
+        std::reverse(next_col_src_grid_coords.begin(), next_col_src_grid_coords.end());
       }
 
       /* Bypass the grid that does not fit the from_tile name */
-      if (from_tile_name != std::string(device_ctx.grid[x][y].type->name)) {
+      vtr::Point<size_t> from_grid_coord = find_grid_coordinate_given_type(device_ctx.grid, next_col_src_grid_coords, from_tile_name); 
+      /* Skip if we do not have a valid coordinate for source CLB/heterogeneous block */
+      if (false == is_grid_coordinate_exist_in_device(device_ctx.grid, from_grid_coord)) {
         continue;
       }
       
       /* Try to find the pin in this tile */
-      std::vector<size_t> from_pins = find_physical_tile_pin_id(device_ctx.grid[x][y].type,
-                                                               device_ctx.grid[x][y].width_offset,
-                                                               device_ctx.grid[x][y].height_offset,
+      std::vector<size_t> from_pins = find_physical_tile_pin_id(device_ctx.grid[from_grid_coord.x()][from_grid_coord.y()].type,
+                                                               device_ctx.grid[from_grid_coord.x()][from_grid_coord.y()].width_offset,
+                                                               device_ctx.grid[from_grid_coord.x()][from_grid_coord.y()].height_offset,
                                                                from_tile_port,
                                                                vpr_direct.from_side);
       /* If nothing found, we can continue */
       if (0 == from_pins.size()) {
         continue;
       }
-      
-      /* We should try to the sink grid for inner-column/row direct connections */
-      vtr::Point<size_t> from_grid_coord(x, y);
-      vtr::Point<size_t> to_grid_coord(x + vpr_direct.x_offset, y + vpr_direct.y_offset);
-      if ((to_grid_coord.x() >= device_ctx.grid.width())
-       || (to_grid_coord.y() >= device_ctx.grid.height())) {
-        continue;
+
+      /* For a valid coordinate, we can find the coordinate of the destination clb */
+       vtr::Point<size_t> to_grid_coord = find_inter_direct_destination_coordinate(device_ctx.grid, from_grid_coord, to_tile_name, arch_direct, arch_direct_id);
+       /* If destination clb is valid, we should add something */
+      if (false == is_grid_coordinate_exist_in_device(device_ctx.grid, to_grid_coord)) {
+         continue;
       }
 
-      /* Bypass the grid that does not fit the from_tile name */
-      if (to_tile_name != std::string(device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].type->name)) {
-        continue;
-      }
       /* Try to find the pin in this tile */
       std::vector<size_t> to_pins = find_physical_tile_pin_id(device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].type,
                                                               device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].width_offset,
@@ -314,26 +557,88 @@ void build_inter_column_row_tile_direct(TileDirect& tile_direct,
 
       /* If from port and to port do not match in sizes, error out */
       if (from_pins.size() != to_pins.size()) {
-        VTR_LOG_ERROR("From_port '%s[%lu:%lu] of direct '%s' does not match to_port '%s[%lu:%lu]'!\n",
-                      from_tile_port.get_name().c_str(),
-                      from_tile_port.get_lsb(),
-                      from_tile_port.get_msb(),
-                      vpr_direct.name,
-                      to_tile_port.get_name().c_str(),
-                      to_tile_port.get_lsb(),
-                      to_tile_port.get_msb());
+        report_direct_from_port_and_to_port_mismatch(vpr_direct, from_tile_port, to_tile_port);
         exit(1);
       }
 
       /* Now add the tile direct */
       for (size_t ipin = 0; ipin < from_pins.size(); ++ipin) {
-        TileDirectId tile_direct_id = tile_direct.add_direct(device_ctx.grid[x][y].type,
-                                                             from_grid_coord, vpr_direct.from_side, from_pins[ipin],
-                                                             device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].type,
+        TileDirectId tile_direct_id = tile_direct.add_direct(from_grid_coord, vpr_direct.from_side, from_pins[ipin],
                                                              to_grid_coord, vpr_direct.to_side, to_pins[ipin]);
         tile_direct.set_arch_direct_id(tile_direct_id, arch_direct_id);
       }
+    }
+    return; /* Go to next direct type */
+  }
+  
+  /* Reach here, it must be a cross-row connection */
+  VTR_ASSERT(INTER_ROW == arch_direct.type(arch_direct_id));
+  /* For cross-row connection, we will search the first valid grid in each column 
+   * from x = 1 to x = nx
+   *
+   *     x=1                    x=nx
+   *   +------+               +------+
+   *   | Grid | <--- ... ---- | Grid |
+   *   +------+               +------+
+   * 
+   */
+  for (size_t iy = 1; iy < device_ctx.grid.height() - 1; ++iy) {
+    std::vector<vtr::Point<size_t>> next_col_src_grid_coords;
+    /* For negative x- direction, we should start from x = nx */
+    for (size_t ix = 1; ix < device_ctx.grid.width() - 1; ++ix) {
+      next_col_src_grid_coords.push_back(vtr::Point<size_t>(ix, iy));
+    }
+    /* For positive x- direction, we should start from x = 1 */
+    if (POSITIVE_DIR == arch_direct.x_dir(arch_direct_id)) {
+      std::reverse(next_col_src_grid_coords.begin(), next_col_src_grid_coords.end());
+    }
 
+    vtr::Point<size_t> from_grid_coord = find_grid_coordinate_given_type(device_ctx.grid, next_col_src_grid_coords, from_tile_name); 
+    /* Skip if we do not have a valid coordinate for source CLB/heterogeneous block */
+    if (false == is_grid_coordinate_exist_in_device(device_ctx.grid, from_grid_coord)) {
+      continue;
+    }
+
+    /* Try to find the pin in this tile */
+    std::vector<size_t> from_pins = find_physical_tile_pin_id(device_ctx.grid[from_grid_coord.x()][from_grid_coord.y()].type,
+                                                              device_ctx.grid[from_grid_coord.x()][from_grid_coord.y()].width_offset,
+                                                              device_ctx.grid[from_grid_coord.x()][from_grid_coord.y()].height_offset,
+                                                              from_tile_port,
+                                                              vpr_direct.from_side);
+    /* If nothing found, we can continue */
+    if (0 == from_pins.size()) {
+      continue;
+    }
+
+    /* For a valid coordinate, we can find the coordinate of the destination clb */
+    vtr::Point<size_t> to_grid_coord = find_inter_direct_destination_coordinate(device_ctx.grid, from_grid_coord, to_tile_name, arch_direct, arch_direct_id);
+    /* If destination clb is valid, we should add something */
+    if (false == is_grid_coordinate_exist_in_device(device_ctx.grid, to_grid_coord)) {
+      continue;
+    }
+
+    /* Try to find the pin in this tile */
+    std::vector<size_t> to_pins = find_physical_tile_pin_id(device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].type,
+                                                            device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].width_offset,
+                                                            device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].height_offset,
+                                                            to_tile_port,
+                                                            vpr_direct.to_side);
+    /* If nothing found, we can continue */
+    if (0 == to_pins.size()) {
+      continue;
+    }
+
+    /* If from port and to port do not match in sizes, error out */
+    if (from_pins.size() != to_pins.size()) {
+      report_direct_from_port_and_to_port_mismatch(vpr_direct, from_tile_port, to_tile_port);
+      exit(1);
+    }
+
+    /* Now add the tile direct */
+    for (size_t ipin = 0; ipin < from_pins.size(); ++ipin) {
+      TileDirectId tile_direct_id = tile_direct.add_direct(from_grid_coord, vpr_direct.from_side, from_pins[ipin],
+                                                           to_grid_coord, vpr_direct.to_side, to_pins[ipin]);
+      tile_direct.set_arch_direct_id(tile_direct_id, arch_direct_id);
     }
   }
 }
@@ -343,8 +648,7 @@ void build_inter_column_row_tile_direct(TileDirect& tile_direct,
  * between tiles (programmable blocks) 
  ***************************************************************************************/
 TileDirect build_device_tile_direct(const DeviceContext& device_ctx,
-                                    const ArchDirect& arch_direct,
-                                    const CircuitLibrary& circuit_lib) {
+                                    const ArchDirect& arch_direct) {
   vtr::ScopedStartFinishTimer timer("Build the annotation about direct connection between tiles");
 
   TileDirect tile_direct;
@@ -358,7 +662,12 @@ TileDirect build_device_tile_direct(const DeviceContext& device_ctx,
                                        device_ctx.arch->Directs[idirect],
                                        device_ctx,
                                        arch_direct_id);
-   /* TODO: Build from OpenFPGA arch definition */ 
+    /* Build from OpenFPGA arch definition */ 
+    build_inter_column_row_tile_direct(tile_direct,
+                                       device_ctx.arch->Directs[idirect],
+                                       device_ctx,
+                                       arch_direct,
+                                       arch_direct_id);
   } 
 
   return tile_direct;
diff --git a/openfpga/src/tile_direct/build_tile_direct.h b/openfpga/src/tile_direct/build_tile_direct.h
index 08d0397ce..78ca2f6b0 100644
--- a/openfpga/src/tile_direct/build_tile_direct.h
+++ b/openfpga/src/tile_direct/build_tile_direct.h
@@ -17,8 +17,7 @@
 namespace openfpga {
 
 TileDirect build_device_tile_direct(const DeviceContext& device_ctx,
-                                    const ArchDirect& arch_direct,
-                                    const CircuitLibrary& circuit_lib);
+                                    const ArchDirect& arch_direct);
 
 } /* end namespace openfpga */
 
diff --git a/openfpga/src/tile_direct/tile_direct.cpp b/openfpga/src/tile_direct/tile_direct.cpp
index d0d1f6122..228724c78 100644
--- a/openfpga/src/tile_direct/tile_direct.cpp
+++ b/openfpga/src/tile_direct/tile_direct.cpp
@@ -15,12 +15,6 @@ TileDirect::tile_direct_range TileDirect::directs() const {
   return vtr::make_range(direct_ids_.begin(), direct_ids_.end());
 }
 
-t_physical_tile_type_ptr TileDirect::from_tile(const TileDirectId& direct_id) const {
-  /* Validate the direct_id */
-  VTR_ASSERT(valid_direct_id(direct_id));
-  return from_tiles_[direct_id];
-}
-
 vtr::Point<size_t> TileDirect::from_tile_coordinate(const TileDirectId& direct_id) const {
   /* Validate the direct_id */
   VTR_ASSERT(valid_direct_id(direct_id));
@@ -39,12 +33,6 @@ e_side TileDirect::from_tile_side(const TileDirectId& direct_id) const {
   return from_tile_sides_[direct_id];
 }
 
-t_physical_tile_type_ptr TileDirect::to_tile(const TileDirectId& direct_id) const {
-  /* Validate the direct_id */
-  VTR_ASSERT(valid_direct_id(direct_id));
-  return to_tiles_[direct_id];
-}
-
 vtr::Point<size_t> TileDirect::to_tile_coordinate(const TileDirectId& direct_id) const {
   /* Validate the direct_id */
   VTR_ASSERT(valid_direct_id(direct_id));
@@ -72,11 +60,9 @@ ArchDirectId TileDirect::arch_direct(const TileDirectId& direct_id) const {
 /******************************************************************************
  * Private Mutators
  ******************************************************************************/
-TileDirectId TileDirect::add_direct(t_physical_tile_type_ptr from_tile,
-                                    const vtr::Point<size_t>& from_tile_coord,
+TileDirectId TileDirect::add_direct(const vtr::Point<size_t>& from_tile_coord,
                                     const e_side& from_tile_side,
                                     const size_t& from_tile_pin,
-                                    t_physical_tile_type_ptr to_tile,
                                     const vtr::Point<size_t>& to_tile_coord,
                                     const e_side& to_tile_side,
                                     const size_t& to_tile_pin) {
@@ -85,12 +71,10 @@ TileDirectId TileDirect::add_direct(t_physical_tile_type_ptr from_tile,
   direct_ids_.push_back(direct);
 
   /* Allocate other attributes */
-  from_tiles_.push_back(from_tile);
   from_tile_coords_.push_back(from_tile_coord);
   from_tile_sides_.push_back(from_tile_side);
   from_tile_pins_.push_back(from_tile_pin);
 
-  to_tiles_.push_back(to_tile);
   to_tile_coords_.push_back(to_tile_coord);
   to_tile_sides_.push_back(to_tile_side);
   to_tile_pins_.push_back(to_tile_pin);
diff --git a/openfpga/src/tile_direct/tile_direct.h b/openfpga/src/tile_direct/tile_direct.h
index d8d0e180f..84593e80c 100644
--- a/openfpga/src/tile_direct/tile_direct.h
+++ b/openfpga/src/tile_direct/tile_direct.h
@@ -33,21 +33,17 @@ class TileDirect {
     typedef vtr::Range<tile_direct_iterator> tile_direct_range;
   public: /* Public aggregators */
     tile_direct_range directs() const;
-    t_physical_tile_type_ptr from_tile(const TileDirectId& direct_id) const;
     vtr::Point<size_t> from_tile_coordinate(const TileDirectId& direct_id) const;
     e_side from_tile_side(const TileDirectId& direct_id) const;
     size_t from_tile_pin(const TileDirectId& direct_id) const;
-    t_physical_tile_type_ptr to_tile(const TileDirectId& direct_id) const;
     vtr::Point<size_t> to_tile_coordinate(const TileDirectId& direct_id) const;
     e_side to_tile_side(const TileDirectId& direct_id) const;
     size_t to_tile_pin(const TileDirectId& direct_id) const;
     ArchDirectId arch_direct(const TileDirectId& direct_id) const;
   public: /* Public mutators */
-    TileDirectId add_direct(t_physical_tile_type_ptr from_tile,
-                            const vtr::Point<size_t>& from_tile_coord,
+    TileDirectId add_direct(const vtr::Point<size_t>& from_tile_coord,
                             const e_side& from_tile_side,
                             const size_t& from_tile_pin,
-                            t_physical_tile_type_ptr to_tile,
                             const vtr::Point<size_t>& to_tile_coord,
                             const e_side& to_tile_side,
                             const size_t& to_tile_pin);
@@ -63,7 +59,6 @@ class TileDirect {
      * - tile coordinate
      * - tile pin id
      */
-    vtr::vector<TileDirectId, t_physical_tile_type_ptr> from_tiles_;
     vtr::vector<TileDirectId, vtr::Point<size_t>> from_tile_coords_;
     vtr::vector<TileDirectId, e_side> from_tile_sides_;
     vtr::vector<TileDirectId, size_t> from_tile_pins_;
@@ -73,7 +68,6 @@ class TileDirect {
      * - tile coordinate
      * - tile pin id
      */
-    vtr::vector<TileDirectId, t_physical_tile_type_ptr> to_tiles_;
     vtr::vector<TileDirectId, vtr::Point<size_t>> to_tile_coords_;
     vtr::vector<TileDirectId, e_side> to_tile_sides_;
     vtr::vector<TileDirectId, size_t> to_tile_pins_;

From 85627dc128e7888f73393f22d6d5806124e0547e Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 15 Feb 2020 14:13:32 -0700
Subject: [PATCH 143/645] put build top module online

---
 openfpga/src/fabric/build_device_module.cpp |  19 +-
 openfpga/src/fabric/build_top_module.cpp    | 367 ++++++++++++++++++++
 openfpga/src/fabric/build_top_module.h      |  39 +++
 3 files changed, 417 insertions(+), 8 deletions(-)
 create mode 100644 openfpga/src/fabric/build_top_module.cpp
 create mode 100644 openfpga/src/fabric/build_top_module.h

diff --git a/openfpga/src/fabric/build_device_module.cpp b/openfpga/src/fabric/build_device_module.cpp
index db3d3dfda..a137407ed 100644
--- a/openfpga/src/fabric/build_device_module.cpp
+++ b/openfpga/src/fabric/build_device_module.cpp
@@ -16,7 +16,7 @@
 #include "build_memory_modules.h"
 #include "build_grid_modules.h"
 #include "build_routing_modules.h"
-//#include "build_top_module.h"
+#include "build_top_module.h"
 #include "build_device_module.h"
 
 /* begin namespace openfpga */
@@ -97,12 +97,15 @@ ModuleManager build_device_module_graph(const DeviceContext& vpr_device_ctx,
   }
 
   /* Build FPGA fabric top-level module */
-  //build_top_module(module_manager, arch.spice->circuit_lib, 
-  //                 device_size, grids, L_device_rr_gsb, 
-  //                 clb2clb_directs, 
-  //                 arch.sram_inf.verilog_sram_inf_orgz->type, sram_model, 
-  //                 TRUE == vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy,
-  //                 TRUE == vpr_setup.FPGA_SPICE_Opts.duplicate_grid_pin);
+  build_top_module(module_manager, openfpga_ctx.arch().circuit_lib, 
+                   vpr_device_ctx.grid,
+                   vpr_device_ctx.rr_graph,
+                   openfpga_ctx.device_rr_gsb(), 
+                   openfpga_ctx.tile_direct(), 
+                   openfpga_ctx.arch().arch_direct, 
+                   openfpga_ctx.arch().config_protocol.type(),
+                   sram_model,
+                   compress_routing, duplicate_grid_pin);
 
   /* Now a critical correction has to be done!
    * In the module construction, we always use prefix of ports because they are binded
@@ -111,7 +114,7 @@ ModuleManager build_device_module_graph(const DeviceContext& vpr_device_ctx,
    * rename the ports of primitive modules using lib_name instead of prefix
    * (which have no children and are probably linked to a standard cell!)
    */
-  //rename_primitive_module_port_names(module_manager, arch.spice->circuit_lib);
+  rename_primitive_module_port_names(module_manager, openfpga_ctx.arch().circuit_lib);
 
   return module_manager;
 }
diff --git a/openfpga/src/fabric/build_top_module.cpp b/openfpga/src/fabric/build_top_module.cpp
new file mode 100644
index 000000000..3357b2b95
--- /dev/null
+++ b/openfpga/src/fabric/build_top_module.cpp
@@ -0,0 +1,367 @@
+/********************************************************************
+ * This file includes functions that are used to print the top-level
+ * module for the FPGA fabric in Verilog format
+ *******************************************************************/
+#include <map>
+#include <algorithm>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_time.h"
+#include "vtr_log.h"
+
+/* Headers from vpr library */
+#include "vpr_utils.h"
+
+#include "rr_gsb_utils.h"
+#include "openfpga_reserved_words.h"
+#include "openfpga_naming.h"
+#include "module_manager_utils.h"
+#include "build_top_module_utils.h"
+#include "build_top_module_connection.h"
+#include "build_top_module_memory.h"
+#include "build_top_module_directs.h"
+
+#include "build_module_graph_utils.h"
+#include "build_top_module.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Add a instance of a grid module to the top module
+ *******************************************************************/
+static 
+size_t add_top_module_grid_instance(ModuleManager& module_manager,
+                                    const ModuleId& top_module,
+                                    t_physical_tile_type_ptr grid_type,
+                                    const e_side& border_side,
+                                    const vtr::Point<size_t>& grid_coord) {
+  /* Find the module name for this type of grid */
+  std::string grid_module_name_prefix(GRID_MODULE_NAME_PREFIX);
+  std::string grid_module_name = generate_grid_block_module_name(grid_module_name_prefix, std::string(grid_type->name), is_io_type(grid_type), border_side);
+  ModuleId grid_module = module_manager.find_module(grid_module_name);
+  VTR_ASSERT(true == module_manager.valid_module_id(grid_module));
+  /* Record the instance id */
+  size_t grid_instance = module_manager.num_instance(top_module, grid_module);
+  /* Add the module to top_module */ 
+  module_manager.add_child_module(top_module, grid_module);
+  /* Set an unique name to the instance
+   * Note: it is your risk to gurantee the name is unique!
+   */
+  std::string instance_name = generate_grid_block_instance_name(grid_module_name_prefix, std::string(grid_type->name), is_io_type(grid_type), border_side, grid_coord);
+  module_manager.set_child_instance_name(top_module, grid_module, grid_instance, instance_name);
+
+  return grid_instance;
+}
+
+/********************************************************************
+ * Add all the grids as sub-modules across the fabric
+ * The grid modules are created for each unique type of grid (based 
+ * on the type in data structure data_structure
+ * Here, we will iterate over the full fabric (coordinates)
+ * and instanciate the grid modules 
+ *
+ * Return an 2-D array of instance ids of the grid modules that 
+ * have been added
+ *
+ * This function assumes an island-style floorplanning for FPGA fabric 
+ *
+ *
+ *                +-----------------------------------+
+ *                |              I/O grids            |
+ *                |              TOP side             |
+ *                +-----------------------------------+
+ *
+ * +-----------+  +-----------------------------------+ +------------+
+ * |           |  |                                   | |            |
+ * | I/O grids |  |          Core grids               | | I/O grids  |
+ * | LEFT side |  | (CLB, Heterogeneous blocks, etc.) | | RIGHT side |
+ * |           |  |                                   | |            |
+ * +-----------+  +-----------------------------------+ +------------+
+ *
+ *                +-----------------------------------+
+ *                |              I/O grids            |
+ *                |             BOTTOM side           |
+ *                +-----------------------------------+
+ *
+ *******************************************************************/
+static 
+vtr::Matrix<size_t> add_top_module_grid_instances(ModuleManager& module_manager,
+                                                  const ModuleId& top_module,
+                                                  const DeviceGrid& grids) {
+  /* Reserve an array for the instance ids */
+  vtr::Matrix<size_t> grid_instance_ids({grids.width(), grids.height()}); 
+  grid_instance_ids.fill(size_t(-1));
+
+  /* Instanciate core grids */
+  for (size_t ix = 1; ix < grids.width() - 1; ++ix) {
+    for (size_t iy = 1; iy < grids.height() - 1; ++iy) {
+      /* Bypass EMPTY grid */
+      if (true == is_empty_type(grids[ix][iy].type)) {
+        continue;
+      } 
+      /* Skip width or height > 1 tiles (mostly heterogeneous blocks) */
+      if ( (0 < grids[ix][iy].width_offset)
+        || (0 < grids[ix][iy].height_offset)) {
+        continue;
+      }
+      /* We should not meet any I/O grid */
+      VTR_ASSERT(false == is_io_type(grids[ix][iy].type));
+      /* Add a grid module to top_module*/
+      vtr::Point<size_t> grid_coord(ix, iy);
+      grid_instance_ids[ix][iy] = add_top_module_grid_instance(module_manager, top_module,
+                                                               grids[ix][iy].type,
+                                                               NUM_SIDES, grid_coord);
+    }
+  }
+
+  /* Instanciate I/O grids */
+  /* Create the coordinate range for each side of FPGA fabric */
+  std::vector<e_side> io_sides{TOP, RIGHT, BOTTOM, LEFT};
+  std::map<e_side, std::vector<vtr::Point<size_t>>> io_coordinates;
+
+  /* TOP side*/
+  for (size_t ix = 1; ix < grids.width() - 1; ++ix) { 
+    io_coordinates[TOP].push_back(vtr::Point<size_t>(ix, grids.height() - 1));
+  } 
+
+  /* RIGHT side */
+  for (size_t iy = 1; iy < grids.height() - 1; ++iy) { 
+    io_coordinates[RIGHT].push_back(vtr::Point<size_t>(grids.width() - 1, iy));
+  } 
+
+  /* BOTTOM side*/
+  for (size_t ix = 1; ix < grids.width() - 1; ++ix) { 
+    io_coordinates[BOTTOM].push_back(vtr::Point<size_t>(ix, 0));
+  } 
+
+  /* LEFT side */
+  for (size_t iy = 1; iy < grids.height() - 1; ++iy) { 
+    io_coordinates[LEFT].push_back(vtr::Point<size_t>(0, iy));
+  }
+
+  /* Add instances of I/O grids to top_module */
+  for (const e_side& io_side : io_sides) {
+    for (const vtr::Point<size_t>& io_coordinate : io_coordinates[io_side]) {
+      /* Bypass EMPTY grid */
+      if (true == is_empty_type(grids[io_coordinate.x()][io_coordinate.y()].type)) {
+        continue;
+      } 
+      /* Skip width, height > 1 tiles (mostly heterogeneous blocks) */
+      if ( (0 < grids[io_coordinate.x()][io_coordinate.y()].width_offset)
+        || (0 < grids[io_coordinate.x()][io_coordinate.y()].height_offset)) {
+        continue;
+      }
+      /* We should not meet any I/O grid */
+      VTR_ASSERT(true == is_io_type(grids[io_coordinate.x()][io_coordinate.y()].type));
+      /* Add a grid module to top_module*/
+      grid_instance_ids[io_coordinate.x()][io_coordinate.y()] = add_top_module_grid_instance(module_manager, top_module, grids[io_coordinate.x()][io_coordinate.y()].type, io_side, io_coordinate);
+    }
+  }
+
+  return grid_instance_ids;
+}
+
+/********************************************************************
+ * Add switch blocks across the FPGA fabric to the top-level module
+ * Return an 2-D array of instance ids of the switch blocks that 
+ * have been added
+ *******************************************************************/
+static 
+vtr::Matrix<size_t> add_top_module_switch_block_instances(ModuleManager& module_manager, 
+                                                          const ModuleId& top_module, 
+                                                          const DeviceRRGSB& device_rr_gsb,
+                                                          const bool& compact_routing_hierarchy) {
+  vtr::Point<size_t> sb_range = device_rr_gsb.get_gsb_range();
+
+  /* Reserve an array for the instance ids */
+  vtr::Matrix<size_t> sb_instance_ids({sb_range.x(), sb_range.y()}); 
+  sb_instance_ids.fill(size_t(-1));
+
+  for (size_t ix = 0; ix < sb_range.x(); ++ix) {
+    for (size_t iy = 0; iy < sb_range.y(); ++iy) {
+      /* If we use compact routing hierarchy, we should instanciate the unique module of SB */
+      const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
+
+      if ( false == rr_gsb.is_sb_exist() ) {
+        continue;
+      }
+
+      vtr::Point<size_t> sb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
+      if (true == compact_routing_hierarchy) {
+        vtr::Point<size_t> sb_coord(ix, iy);
+        const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(sb_coord);
+        sb_coordinate.set_x(unique_mirror.get_sb_x()); 
+        sb_coordinate.set_y(unique_mirror.get_sb_y()); 
+      } 
+      std::string sb_module_name = generate_switch_block_module_name(sb_coordinate);
+      ModuleId sb_module = module_manager.find_module(sb_module_name);
+      VTR_ASSERT(true == module_manager.valid_module_id(sb_module));
+      /* Record the instance id */
+      sb_instance_ids[rr_gsb.get_sb_x()][rr_gsb.get_sb_y()] = module_manager.num_instance(top_module, sb_module);
+      /* Add the module to top_module */ 
+      module_manager.add_child_module(top_module, sb_module);
+      /* Set an unique name to the instance
+       * Note: it is your risk to gurantee the name is unique!
+       */
+      module_manager.set_child_instance_name(top_module, sb_module, 
+                                             sb_instance_ids[rr_gsb.get_sb_x()][rr_gsb.get_sb_y()],
+                                             generate_switch_block_module_name(vtr::Point<size_t>(rr_gsb.get_sb_x(), rr_gsb.get_sb_y())));
+    }
+  }
+
+  return sb_instance_ids;
+}
+
+/********************************************************************
+ * Add switch blocks across the FPGA fabric to the top-level module
+ *******************************************************************/
+static 
+vtr::Matrix<size_t> add_top_module_connection_block_instances(ModuleManager& module_manager, 
+                                                              const ModuleId& top_module, 
+                                                              const DeviceRRGSB& device_rr_gsb,
+                                                              const t_rr_type& cb_type,
+                                                              const bool& compact_routing_hierarchy) {
+  vtr::Point<size_t> cb_range = device_rr_gsb.get_gsb_range();
+
+  /* Reserve an array for the instance ids */
+  vtr::Matrix<size_t> cb_instance_ids({cb_range.x(), cb_range.y()}); 
+  cb_instance_ids.fill(size_t(-1));
+
+  for (size_t ix = 0; ix < cb_range.x(); ++ix) {
+    for (size_t iy = 0; iy < cb_range.y(); ++iy) {
+      /* Check if the connection block exists in the device!
+       * Some of them do NOT exist due to heterogeneous blocks (height > 1) 
+       * We will skip those modules
+       */
+      const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
+      vtr::Point<size_t> cb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type));
+      if ( false == rr_gsb.is_cb_exist(cb_type) ) {
+        continue;
+      }
+      /* If we use compact routing hierarchy, we should instanciate the unique module of SB */
+      if (true == compact_routing_hierarchy) {
+        vtr::Point<size_t> cb_coord(ix, iy);
+        /* Note: use GSB coordinate when inquire for unique modules!!! */
+        const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(cb_type, cb_coord);
+        cb_coordinate.set_x(unique_mirror.get_cb_x(cb_type)); 
+        cb_coordinate.set_y(unique_mirror.get_cb_y(cb_type)); 
+      } 
+      std::string cb_module_name = generate_connection_block_module_name(cb_type, cb_coordinate);
+      ModuleId cb_module = module_manager.find_module(cb_module_name);
+      VTR_ASSERT(true == module_manager.valid_module_id(cb_module));
+      /* Record the instance id */
+      cb_instance_ids[rr_gsb.get_cb_x(cb_type)][rr_gsb.get_cb_y(cb_type)] = module_manager.num_instance(top_module, cb_module);
+      /* Add the module to top_module */ 
+      module_manager.add_child_module(top_module, cb_module);
+      /* Set an unique name to the instance
+       * Note: it is your risk to gurantee the name is unique!
+       */
+      std::string cb_instance_name = generate_connection_block_module_name(cb_type, vtr::Point<size_t>(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)));
+      module_manager.set_child_instance_name(top_module, cb_module, 
+                                             cb_instance_ids[rr_gsb.get_cb_x(cb_type)][rr_gsb.get_cb_y(cb_type)],
+                                             cb_instance_name); 
+    }
+  }
+
+  return cb_instance_ids;
+}
+
+/********************************************************************
+ * Print the top-level module for the FPGA fabric in Verilog format
+ * This function will 
+ * 1. name the top-level module
+ * 2. include dependent netlists 
+ *    - User defined netlists
+ *    - Auto-generated netlists
+ * 3. Add the submodules to the top-level graph
+ * 4. Add module nets to connect datapath ports
+ * 5. Add module nets/submodules to connect configuration ports
+ *******************************************************************/
+void build_top_module(ModuleManager& module_manager,
+                      const CircuitLibrary& circuit_lib,
+                      const DeviceGrid& grids,
+                      const RRGraph& rr_graph,
+                      const DeviceRRGSB& device_rr_gsb,
+                      const TileDirect& tile_direct,
+                      const ArchDirect& arch_direct,
+                      const e_config_protocol_type& sram_orgz_type,
+                      const CircuitModelId& sram_model,
+                      const bool& compact_routing_hierarchy,
+                      const bool& duplicate_grid_pin) {
+
+  vtr::ScopedStartFinishTimer timer("Build FPGA fabric module");
+
+  /* Create a module as the top-level fabric, and add it to the module manager */
+  std::string top_module_name = generate_fpga_top_module_name();
+  ModuleId top_module = module_manager.add_module(top_module_name);
+
+  std::map<t_rr_type, vtr::Matrix<size_t>> cb_instance_ids;
+ 
+  /* Add sub modules, which are grid, SB and CBX/CBY modules as instances */
+  /* Add all the grids across the fabric */
+  vtr::Matrix<size_t> grid_instance_ids = add_top_module_grid_instances(module_manager, top_module, grids);
+  /* Add all the SBs across the fabric */
+  vtr::Matrix<size_t> sb_instance_ids = add_top_module_switch_block_instances(module_manager, top_module, device_rr_gsb, compact_routing_hierarchy);
+  /* Add all the CBX and CBYs across the fabric */
+  cb_instance_ids[CHANX] = add_top_module_connection_block_instances(module_manager, top_module, device_rr_gsb, CHANX, compact_routing_hierarchy);
+  cb_instance_ids[CHANY] = add_top_module_connection_block_instances(module_manager, top_module, device_rr_gsb, CHANY, compact_routing_hierarchy);
+
+  /* Add module nets to connect the sub modules */
+  add_top_module_nets_connect_grids_and_gsbs(module_manager, top_module, 
+                                             grids, grid_instance_ids, 
+                                             rr_graph, device_rr_gsb, sb_instance_ids, cb_instance_ids,
+                                             compact_routing_hierarchy, duplicate_grid_pin);
+  /* Add inter-CLB direct connections */
+  add_top_module_nets_tile_direct_connections(module_manager, top_module, circuit_lib, 
+                                              grids, grid_instance_ids,
+                                              tile_direct, arch_direct);
+
+  /* Add global ports to the pb_module:
+   * This is a much easier job after adding sub modules (instances), 
+   * we just need to find all the global ports from the child modules and build a list of it
+   */
+  add_module_global_ports_from_child_modules(module_manager, top_module);
+
+  /* Add GPIO ports from the sub-modules under this Verilog module 
+   * This is a much easier job after adding sub modules (instances), 
+   * we just need to find all the I/O ports from the child modules and build a list of it
+   */
+  add_module_gpio_ports_from_child_modules(module_manager, top_module);
+
+  /* Add shared SRAM ports from the sub-modules under this Verilog module
+   * This is a much easier job after adding sub modules (instances), 
+   * we just need to find all the I/O ports from the child modules and build a list of it
+   */
+  size_t module_num_shared_config_bits = find_module_num_shared_config_bits_from_child_modules(module_manager, top_module); 
+  if (0 < module_num_shared_config_bits) {
+    add_reserved_sram_ports_to_module_manager(module_manager, top_module, module_num_shared_config_bits);
+  }
+
+  /* Add SRAM ports from the sub-modules under this Verilog module
+   * This is a much easier job after adding sub modules (instances), 
+   * we just need to find all the I/O ports from the child modules and build a list of it
+   */
+  size_t module_num_config_bits = find_module_num_config_bits_from_child_modules(module_manager, top_module, circuit_lib, sram_model, sram_orgz_type); 
+  if (0 < module_num_config_bits) {
+    add_sram_ports_to_module_manager(module_manager, top_module, circuit_lib, sram_model, sram_orgz_type, module_num_config_bits);
+  }
+
+  /* Organize the list of memory modules and instances */
+  organize_top_module_memory_modules(module_manager, top_module, 
+                                     circuit_lib, sram_orgz_type, sram_model,
+                                     grids, grid_instance_ids, 
+                                     device_rr_gsb, sb_instance_ids, cb_instance_ids,
+                                     compact_routing_hierarchy);
+
+  /* Add module nets to connect memory cells inside
+   * This is a one-shot addition that covers all the memory modules in this pb module!
+   */
+  if (0 < module_manager.configurable_children(top_module).size()) {
+    add_top_module_nets_memory_config_bus(module_manager, top_module, 
+                                          sram_orgz_type, circuit_lib.design_tech_type(sram_model));
+  }
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fabric/build_top_module.h b/openfpga/src/fabric/build_top_module.h
new file mode 100644
index 000000000..3b6badfb2
--- /dev/null
+++ b/openfpga/src/fabric/build_top_module.h
@@ -0,0 +1,39 @@
+#ifndef BUILD_TOP_MODULE_H
+#define BUILD_TOP_MODULE_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+
+#include <string>
+#include "vtr_geometry.h"
+#include "device_grid.h"
+#include "rr_graph_obj.h"
+#include "device_rr_gsb.h"
+#include "circuit_library.h"
+#include "tile_direct.h"
+#include "arch_direct.h"
+#include "module_manager.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void build_top_module(ModuleManager& module_manager,
+                      const CircuitLibrary& circuit_lib,
+                      const DeviceGrid& grids,
+                      const RRGraph& rr_graph,
+                      const DeviceRRGSB& device_rr_gsb,
+                      const TileDirect& tile_direct,
+                      const ArchDirect& arch_direct,
+                      const e_config_protocol_type& sram_orgz_type,
+                      const CircuitModelId& sram_model,
+                      const bool& compact_routing_hierarchy,
+                      const bool& duplicate_grid_pin);
+
+} /* end namespace openfpga */
+
+#endif

From 622c7826d1f48cf8a457aeda1dadd11ce05fda7f Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 15 Feb 2020 15:03:00 -0700
Subject: [PATCH 144/645] start transplanting fpga_verilog

---
 .../libopenfpgautil/src/openfpga_digest.cpp   | 113 +++++++++++++++++
 .../libopenfpgautil/src/openfpga_digest.h     |   8 ++
 openfpga/src/fpga_verilog/verilog_api.cpp     | 118 ++++++++++++++++++
 openfpga/src/fpga_verilog/verilog_api.h       |  36 ++++++
 openfpga/src/fpga_verilog/verilog_constants.h |  40 ++++++
 .../src/fpga_verilog/verilog_port_types.h     |  16 +++
 6 files changed, 331 insertions(+)
 create mode 100644 openfpga/src/fpga_verilog/verilog_api.cpp
 create mode 100644 openfpga/src/fpga_verilog/verilog_api.h
 create mode 100644 openfpga/src/fpga_verilog/verilog_constants.h
 create mode 100644 openfpga/src/fpga_verilog/verilog_port_types.h

diff --git a/libopenfpga/libopenfpgautil/src/openfpga_digest.cpp b/libopenfpga/libopenfpgautil/src/openfpga_digest.cpp
index f1b44d788..3340ea8b1 100644
--- a/libopenfpga/libopenfpgautil/src/openfpga_digest.cpp
+++ b/libopenfpga/libopenfpgautil/src/openfpga_digest.cpp
@@ -2,6 +2,9 @@
  * This file includes functions that handles the file outputting
  * in OpenFPGA framework
  *******************************************************************/
+#include <sys/stat.h>
+#include <algorithm>
+
 /* Headers from vtrutil library */
 #include "vtr_log.h"
 
@@ -37,4 +40,114 @@ void check_file_stream(const char* fname,
   }
 }
 
+/********************************************************************
+ * Format a directory path:
+ * 1. Replace "\" with "/" 
+ * 2. add a "/" if the string does not end with a "/"
+ *******************************************************************/
+std::string format_dir_path(const std::string& dir_path_to_format) {
+  std::string formatted_dir_path = dir_path_to_format;
+
+  char illegal_back_slash = '\\';
+  char legal_back_slash = '/';
+
+#ifdef _WIN32
+/* For windows OS, replace any '/' with '\' */
+  char illegal_back_slash = '/';
+  char legal_back_slash = '\\';
+#endif
+
+  /* Replace "\" with "/" */
+  std::replace(formatted_dir_path.begin(), formatted_dir_path.end(), illegal_back_slash, legal_back_slash); 
+
+  /* Add a back slash the string is not ended like this! */
+  if (legal_back_slash != formatted_dir_path.back()) {
+    formatted_dir_path.push_back(legal_back_slash);
+  }
+ 
+  return formatted_dir_path; 
+}
+
+/******************************************************************** 
+ * Extract full file name from a full path of file 
+ * For example: <dir_path>/<file_name>
+ * This function will return <file_name>
+ ********************************************************************/
+std::string find_path_file_name(const std::string& file_name) {
+
+  char back_slash = '/';
+
+#ifdef _WIN32
+/* For windows OS, replace any '/' with '\' */
+  char back_slash = '\\';
+#endif 
+
+  /* Find the last '/' in the string and return the left part */
+  size_t found = file_name.rfind(back_slash);
+  if (found != std::string::npos) {
+    return file_name.substr(found + 1);
+  }
+  /* Not found. The input is the file name! Return the original string */
+  return file_name;
+}
+
+/******************************************************************** 
+ * Extract full directory path from a full path of file
+ * For example: <dir_path>/<file_name>
+ * This function will return <dir_path>
+ ********************************************************************/
+std::string find_path_dir_name(const std::string& file_name) {
+
+  char back_slash = '/';
+
+#ifdef _WIN32
+/* For windows OS, replace any '/' with '\' */
+  char back_slash = '\\';
+#endif 
+
+  /* Find the last '/' in the string and return the left part */
+  size_t found = file_name.rfind(back_slash);
+  if (found != std::string::npos) {
+    return file_name.substr(0, found);
+  }
+  /* Not found, return an empty string */
+  return std::string();
+}
+
+/******************************************************************** 
+ * Create a directory with a given path
+ ********************************************************************/
+bool create_dir_path(const char* dir_path) {
+   /* Give up if the path is empty */
+   if (nullptr == dir_path) {
+     VTR_LOG_ERROR("dir_path is empty and nothing is created.\n");
+     return false;
+   }
+
+   /* Try to create a directory */
+   int ret = mkdir(dir_path, S_IRWXU|S_IRWXG|S_IROTH|S_IXOTH);
+
+   /* Analyze the return flag and output status */
+   switch (ret) {
+   case 0:
+     VTR_LOG("Succeed to create directory '%s'\n",
+             dir_path);
+     return true;
+   case -1:
+     if (EEXIST == errno) {
+       VTR_LOG_ERROR("Directory '%s' already exists. Will overwrite contents\n",
+                     dir_path);
+       return true;
+     }
+     break;
+   default:
+     VTR_LOG_ERROR("Create directory '%s'...Failed!\n",
+                 dir_path);
+     exit(1);
+     return false;
+  }
+
+  return false;
+}
+
 } /* namespace openfpga ends */
diff --git a/libopenfpga/libopenfpgautil/src/openfpga_digest.h b/libopenfpga/libopenfpgautil/src/openfpga_digest.h
index 332249d56..90af3dc4e 100644
--- a/libopenfpga/libopenfpgautil/src/openfpga_digest.h
+++ b/libopenfpga/libopenfpgautil/src/openfpga_digest.h
@@ -17,6 +17,14 @@ bool valid_file_stream(std::fstream& fp);
 void check_file_stream(const char* fname, 
                        std::fstream& fp);
 
+std::string format_dir_path(const std::string& dir_path_to_format);
+
+std::string find_path_file_name(const std::string& file_name);
+
+std::string find_path_dir_name(const std::string& file_name);
+
+bool create_dir_path(const char* dir_path);
+
 } /* namespace openfpga ends */
 
 #endif
diff --git a/openfpga/src/fpga_verilog/verilog_api.cpp b/openfpga/src/fpga_verilog/verilog_api.cpp
new file mode 100644
index 000000000..7de1b95e9
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_api.cpp
@@ -0,0 +1,118 @@
+/********************************************************************
+ * This file include top-level function of FPGA-Verilog
+ ********************************************************************/
+
+/* Headers from vtrutil library */
+#include "vtr_log.h"
+#include "vtr_assert.h"
+#include "vtr_time.h"
+
+#include "circuit_library_utils.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_digest.h"
+
+#include "device_rr_gsb.h"
+#include "verilog_constants.h"
+//#include "verilog_submodules.h"
+//#include "verilog_routing.h"
+//#include "verilog_submodules.h"
+//#include "verilog_grid.h"
+//#include "verilog_routing.h"
+//#include "verilog_top_module.h"
+
+/* Header file for this source file */
+#include "verilog_api.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Top-level function of FPGA-Verilog
+ * This function will generate
+ * 1. primitive modules required by the full fabric
+ *    which are LUTs, routing multiplexer, logic gates, transmission-gates etc.
+ * 2. Routing modules, which are Switch Blocks (SBs) and Connection Blocks (CBs)
+ * 3. Logic block modules, which are Configuration Logic Blocks (CLBs)
+ * 4. FPGA module, which are the full FPGA fabric with configuration protocol
+ * 5. A wrapper module, which encapsulate the FPGA module in a Verilog module which have the same port as the input benchmark 
+ * 6. Testbench, where a FPGA module is configured with a bitstream and then driven by input vectors
+ * 7. Pre-configured testbench, which can skip the configuration phase and pre-configure the FPGA module. This testbench is created for quick verification and formal verification purpose.
+ * 8. Verilog netlist including preprocessing flags and all the Verilog netlists that have been generated
+ ********************************************************************/
+void fabric_verilog(ModuleManager& module_manager,
+                    const CircuitLibrary& circuit_lib,
+                    const MuxLibrary& mux_lib,
+                    const DeviceGrid& grids, 
+                    const DeviceRRGSB& device_rr_gsb,
+                    const std::string& output_directory,
+                    const bool& compress_routing,
+                    const bool& dump_explict_verilog,
+                    const bool& verbose) {
+
+  vtr::ScopedStartFinishTimer timer("Generate Verilog netlists for FPGA fabric\n");
+
+  std::string src_dir_path = format_dir_path(output_directory);
+
+  /* Create directories */
+  create_dir_path(src_dir_path.c_str());
+
+  /* Sub directory under SRC directory to contain all the primitive block netlists */
+  std::string submodule_dir_path = src_dir_path + std::string(DEFAULT_SUBMODULE_DIR_NAME);
+  create_dir_path(submodule_dir_path.c_str());
+
+  /* Sub directory under SRC directory to contain all the logic block netlists */
+  std::string lb_dir_path = src_dir_path + std::string(DEFAULT_LB_DIR_NAME);
+  create_dir_path(lb_dir_path.c_str());
+
+  /* Sub directory under SRC directory to contain all the routing block netlists */
+  std::string rr_dir_path = src_dir_path + std::string(DEFAULT_RR_DIR_NAME);
+  create_dir_path(rr_dir_path.c_str());
+
+  /* Print Verilog files containing preprocessing flags */
+  //print_verilog_preprocessing_flags_netlist(std::string(src_dir_path),
+  //                                          vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts);
+
+  //print_verilog_simulation_preprocessing_flags(std::string(src_dir_path),
+  //                                             vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts);
+
+  /* Generate primitive Verilog modules, which are corner stones of FPGA fabric
+   * Note that this function MUST be called before Verilog generation of
+   * core logic (i.e., logic blocks and routing resources) !!!
+   * This is because that this function will add the primitive Verilog modules to 
+   * the module manager.
+   * Without the modules in the module manager, core logic generation is not possible!!!
+   */
+  //print_verilog_submodules(module_manager, mux_lib, sram_verilog_orgz_info, src_dir_path.c_str(), submodule_dir_path.c_str(), 
+  //                         Arch, vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts);
+
+  /* Generate routing blocks */
+  //if (true == compress_routing) {
+  //  print_verilog_unique_routing_modules(module_manager, device_rr_gsb,  
+  //                                       src_dir_path, rr_dir_path,
+  //                                       dump_explicit_verilog);
+  //} else {
+  //  VTR_ASSERT(false == compress_routing);
+  //  print_verilog_flatten_routing_modules(module_manager, device_rr_gsb, 
+  //                                        src_dir_path, rr_dir_path,
+  //                                        dump_explicit_verilog);
+  //}
+
+  /* Generate grids */
+  //print_verilog_grids(module_manager, 
+  //                    src_dir_path, lb_dir_path,
+  //                    dump_explicit_verilog);
+
+  /* Generate FPGA fabric */
+  //print_verilog_top_module(module_manager, 
+  //                         std::string(vpr_setup.FileNameOpts.ArchFile), 
+  //                         src_dir_path,
+  //                         dump_explicit_verilog);
+
+  /* Given a brief stats on how many Verilog modules have been written to files */
+  VTR_LOGV(verbose, 
+           "Outputted %lu Verilog modules in total\n", 
+           module_manager.num_modules());  
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_verilog/verilog_api.h b/openfpga/src/fpga_verilog/verilog_api.h
new file mode 100644
index 000000000..9d601ee46
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_api.h
@@ -0,0 +1,36 @@
+#ifndef VERILOG_API_H 
+#define VERILOG_API_H 
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+
+#include <string>
+#include <vector>
+#include "vpr_types.h"
+#include "mux_library.h"
+#include "circuit_library.h"
+#include "device_grid.h"
+#include "device_rr_gsb.h"
+#include "module_manager.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void fabric_verilog(ModuleManager& module_manager,
+                    const CircuitLibrary& circuit_lib,
+                    const MuxLibrary& mux_lib,
+                    const DeviceGrid& grids, 
+                    const DeviceRRGSB& device_rr_gsb,
+                    const std::string& output_directory,
+                    const bool& compress_routing,
+                    const bool& dump_explict_verilog,
+                    const bool& verbose);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/fpga_verilog/verilog_constants.h b/openfpga/src/fpga_verilog/verilog_constants.h
new file mode 100644
index 000000000..10a6c0669
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_constants.h
@@ -0,0 +1,40 @@
+#ifndef VERILOG_CONSTANTS_H
+#define VERILOG_CONSTANTS_H
+
+/* global parameters for dumping synthesizable verilog */
+
+constexpr char* VERILOG_NETLIST_FILE_POSTFIX = ".v";
+constexpr float VERILOG_SIM_TIMESCALE = 1e-9; // Verilog Simulation time scale (minimum time unit) : 1ns
+
+constexpr char* VERILOG_TIMING_PREPROC_FLAG = "ENABLE_TIMING"; // the flag to enable timing definition during compilation
+constexpr char* VERILOG_SIGNAL_INIT_PREPROC_FLAG = "ENABLE_SIGNAL_INITIALIZATION"; // the flag to enable signal initialization during compilation
+constexpr char* VERILOG_FORMAL_VERIFICATGION_PREPROC_FLAG = "ENABLE_FORMAL_VERIFICATION"; // the flag to enable formal verification during compilation
+constexpr char* INITIAL_SIMULATION_FLAG = "INITIAL_SIMULATION"; // the flag to enable initial functional verification
+constexpr char* AUTOCHECKED_SIMULATION_FLAG = "AUTOCHECKED_SIMULATION"; // the flag to enable autochecked functional verification
+constexpr char* FORMAL_SIMULATION_FLAG = "FORMAL_SIMULATION"; // the flag to enable formal functional verification
+
+constexpr char* DEFAULT_LB_DIR_NAME = "lb/";
+constexpr char* DEFAULT_RR_DIR_NAME = "routing/";
+constexpr char* DEFAULT_SUBMODULE_DIR_NAME = "sub_module/";
+constexpr char* MODELSIM_SIMULATION_TIME_UNIT = "ms";
+
+// Icarus variables and flag
+constexpr char* ICARUS_SIMULATION_FLAG = "ICARUS_SIMULATOR"; // the flag to enable specific Verilog code in testbenches
+// End of Icarus variables and flag
+
+constexpr char* VERILOG_TOP_POSTFIX = "_top.v";
+constexpr char* DEFINES_VERILOG_FILE_NAME = "fpga_defines.v";
+constexpr char* DEFINES_VERILOG_SIMULATION_FILE_NAME = "define_simulation.v";
+constexpr char* SUBMODULE_VERILOG_FILE_NAME = "sub_module.v";
+constexpr char* LOGIC_BLOCK_VERILOG_FILE_NAME = "logic_blocks.v";
+constexpr char* LUTS_VERILOG_FILE_NAME = "luts.v";
+constexpr char* ROUTING_VERILOG_FILE_NAME = "routing.v";
+constexpr char* MUXES_VERILOG_FILE_NAME = "muxes.v";
+constexpr char* LOCAL_ENCODER_VERILOG_FILE_NAME = "local_encoder.v";
+constexpr char* MEMORIES_VERILOG_FILE_NAME = "memories.v";
+constexpr char* WIRES_VERILOG_FILE_NAME = "wires.v";
+constexpr char* ESSENTIALS_VERILOG_FILE_NAME = "inv_buf_passgate.v";
+constexpr char* CONFIG_PERIPHERAL_VERILOG_FILE_NAME = "config_peripherals.v";
+constexpr char* USER_DEFINED_TEMPLATE_VERILOG_FILE_NAME = "user_defined_templates.v";
+
+#endif
diff --git a/openfpga/src/fpga_verilog/verilog_port_types.h b/openfpga/src/fpga_verilog/verilog_port_types.h
new file mode 100644
index 000000000..2100ba272
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_port_types.h
@@ -0,0 +1,16 @@
+#ifndef VERILOG_PORT_TYPES_H
+#define VERILOG_PORT_TYPES_H
+
+enum e_dump_verilog_port_type {
+  VERILOG_PORT_INPUT,
+  VERILOG_PORT_OUTPUT,
+  VERILOG_PORT_INOUT,
+  VERILOG_PORT_WIRE,
+  VERILOG_PORT_REG,
+  VERILOG_PORT_CONKT,
+  NUM_VERILOG_PORT_TYPES
+};
+constexpr std::array<const char*, NUM_VERILOG_PORT_TYPES> VERILOG_PORT_TYPE_STRING = {{"input", "output", "inout", "wire", "reg", ""}}; /* string version of enum e_verilog_port_type */
+
+#endif
+

From 8b0df8632c35332342401e2766a400e3a01962a4 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 15 Feb 2020 20:38:45 -0700
Subject: [PATCH 145/645] bring fpga verilog create directory online

---
 openfpga/src/base/openfpga_context.h          |  6 +++
 openfpga/src/base/openfpga_flow_manager.cpp   | 26 ++++++++++
 openfpga/src/base/openfpga_flow_manager.h     | 28 ++++++++++
 openfpga/src/base/openfpga_setup_command.cpp  |  2 +-
 .../src/base/openfpga_verilog_command.cpp     | 51 +++++++++++++++++++
 openfpga/src/base/openfpga_verilog_command.h  | 21 ++++++++
 openfpga/src/fpga_verilog/verilog_api.cpp     | 20 ++++----
 openfpga/src/fpga_verilog/verilog_api.h       | 18 +++----
 openfpga/src/main.cpp                         |  4 ++
 openfpga/test_script/s298_k6_frac.openfpga    |  4 ++
 10 files changed, 160 insertions(+), 20 deletions(-)
 create mode 100644 openfpga/src/base/openfpga_flow_manager.cpp
 create mode 100644 openfpga/src/base/openfpga_flow_manager.h
 create mode 100644 openfpga/src/base/openfpga_verilog_command.cpp
 create mode 100644 openfpga/src/base/openfpga_verilog_command.h

diff --git a/openfpga/src/base/openfpga_context.h b/openfpga/src/base/openfpga_context.h
index ac3cc99c8..5726cbba9 100644
--- a/openfpga/src/base/openfpga_context.h
+++ b/openfpga/src/base/openfpga_context.h
@@ -10,6 +10,7 @@
 #include "mux_library.h"
 #include "tile_direct.h"
 #include "module_manager.h"
+#include "openfpga_flow_manager.h"
 #include "device_rr_gsb.h"
 
 /********************************************************************
@@ -50,6 +51,7 @@ class OpenfpgaContext : public Context  {
     const openfpga::MuxLibrary& mux_lib() const { return mux_lib_; }
     const openfpga::TileDirect& tile_direct() const { return tile_direct_; }
     const openfpga::ModuleManager& module_graph() const { return module_graph_; }
+    const openfpga::FlowManager& flow_manager() const { return flow_manager_; }
   public:  /* Public mutators */
     openfpga::Arch& mutable_arch() { return arch_; }
     openfpga::VprDeviceAnnotation& mutable_vpr_device_annotation() { return vpr_device_annotation_; }
@@ -60,6 +62,7 @@ class OpenfpgaContext : public Context  {
     openfpga::MuxLibrary& mutable_mux_lib() { return mux_lib_; }
     openfpga::TileDirect& mutable_tile_direct() { return tile_direct_; }
     openfpga::ModuleManager& mutable_module_graph() { return module_graph_; }
+    openfpga::FlowManager& mutable_flow_manager() { return flow_manager_; }
   private: /* Internal data */
     /* Data structure to store information from read_openfpga_arch library */
     openfpga::Arch arch_;
@@ -87,6 +90,9 @@ class OpenfpgaContext : public Context  {
 
     /* Fabric module graph */
     openfpga::ModuleManager module_graph_;
+ 
+    /* Flow status */
+    openfpga::FlowManager flow_manager_;
 };
 
 #endif
diff --git a/openfpga/src/base/openfpga_flow_manager.cpp b/openfpga/src/base/openfpga_flow_manager.cpp
new file mode 100644
index 000000000..bc97f291d
--- /dev/null
+++ b/openfpga/src/base/openfpga_flow_manager.cpp
@@ -0,0 +1,26 @@
+/******************************************************************************
+ * Memember functions for data structure FlowManager
+ ******************************************************************************/
+#include "vtr_assert.h"
+
+#include "openfpga_flow_manager.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/**************************************************
+ * Public Accessors 
+ *************************************************/
+bool FlowManager::compress_routing() const {
+  return compress_routing_;
+}
+
+/******************************************************************************
+ * Private Mutators
+ ******************************************************************************/
+void FlowManager::set_compress_routing(const bool& enabled) {
+  compress_routing_ = enabled;
+}
+
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_flow_manager.h b/openfpga/src/base/openfpga_flow_manager.h
new file mode 100644
index 000000000..6a6ae7c75
--- /dev/null
+++ b/openfpga/src/base/openfpga_flow_manager.h
@@ -0,0 +1,28 @@
+#ifndef FLOW_MANAGER_H
+#define FLOW_MANAGER_H
+
+/********************************************************************
+ * Include header files required by the data structure definition
+ *******************************************************************/
+/* Begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * FlowManager aims to resolve the dependency between OpenFPGA functional
+ * code blocks
+ * It can provide flags for downstream modules about if the data structures
+ * they require have already been constructed
+ *
+ *******************************************************************/
+class FlowManager {
+  public: /* Public accessors */
+    bool compress_routing() const;
+  public: /* Public mutators */
+    void set_compress_routing(const bool& enabled);
+  private: /* Internal Data */
+    bool compress_routing_;
+};
+
+} /* End namespace openfpga*/
+
+#endif
diff --git a/openfpga/src/base/openfpga_setup_command.cpp b/openfpga/src/base/openfpga_setup_command.cpp
index 1b6971167..e84227187 100644
--- a/openfpga/src/base/openfpga_setup_command.cpp
+++ b/openfpga/src/base/openfpga_setup_command.cpp
@@ -135,7 +135,7 @@ void add_openfpga_setup_commands(openfpga::Shell<OpenfpgaContext>& shell) {
   shell.set_command_execute_function(shell_cmd_build_fabric_id, build_fabric);
   /* The 'build_fabric' command should NOT be executed before 'link_openfpga_arch' */
   std::vector<ShellCommandId> cmd_dependency_build_fabric;
-  cmd_dependency_lut_truth_table_fixup.push_back(shell_cmd_link_openfpga_arch_id);
+  cmd_dependency_build_fabric.push_back(shell_cmd_link_openfpga_arch_id);
   shell.set_command_dependency(shell_cmd_build_fabric_id, cmd_dependency_build_fabric);
 } 
 
diff --git a/openfpga/src/base/openfpga_verilog_command.cpp b/openfpga/src/base/openfpga_verilog_command.cpp
new file mode 100644
index 000000000..fa3ff9c4b
--- /dev/null
+++ b/openfpga/src/base/openfpga_verilog_command.cpp
@@ -0,0 +1,51 @@
+/********************************************************************
+ * Add commands to the OpenFPGA shell interface, 
+ * in purpose of generate Verilog netlists modeling the full FPGA fabric
+ * This is one of the core engine of openfpga, including:
+ * - generate_fabric_verilog : generate Verilog netlists about FPGA fabric 
+ * - generate_fabric_verilog_testbench : TODO: generate Verilog testbenches 
+ *******************************************************************/
+#include "openfpga_verilog.h"
+#include "openfpga_verilog_command.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void add_openfpga_verilog_commands(openfpga::Shell<OpenfpgaContext>& shell) {
+  /* Get the unique id of 'build_fabric' command which is to be used in creating the dependency graph */
+  const ShellCommandId& shell_cmd_build_fabric_id = shell.command(std::string("build_fabric"));
+
+  /* Add a new class of commands */
+  ShellCommandClassId openfpga_verilog_cmd_class = shell.add_command_class("FPGA-Verilog");
+
+  /******************************** 
+   * Command 'wirte_fabric_verilog' 
+   */
+  Command shell_cmd_write_fabric_verilog("write_fabric_verilog");
+  /* Add an option '--file' in short '-f'*/
+  CommandOptionId fabric_verilog_output_opt = shell_cmd_write_fabric_verilog.add_option("file", true, "Specify the output directory for Verilog netlists");
+  shell_cmd_write_fabric_verilog.set_option_short_name(fabric_verilog_output_opt, "f");
+  shell_cmd_write_fabric_verilog.set_option_require_value(fabric_verilog_output_opt, openfpga::OPT_STRING);
+  /* Add an option '--explicit_port_mapping' */
+  shell_cmd_write_fabric_verilog.add_option("explicit_port_mapping", false, "Use explicit port mapping in Verilog netlists");
+  /* Add an option '--include_timing' */
+  shell_cmd_write_fabric_verilog.add_option("include_timing", false, "Enable timing annotation in Verilog netlists");
+  /* Add an option '--include_signal_init' */
+  shell_cmd_write_fabric_verilog.add_option("include_signal_init", false, "Initialize all the signals in Verilog netlists");
+  /* Add an option '--support_icarus_simulator' */
+  shell_cmd_write_fabric_verilog.add_option("support_icarus_simulator", false, "Fine-tune Verilog netlists to support icarus simulator");
+  /* Add an option '--verbose' */
+  shell_cmd_write_fabric_verilog.add_option("verbose", false, "Enable verbose output");
+  
+  /* Add command 'write_fabric_verilog' to the Shell */
+  ShellCommandId shell_cmd_write_fabric_verilog_id = shell.add_command(shell_cmd_write_fabric_verilog, "generate Verilog netlists modeling full FPGA fabric");
+  shell.set_command_class(shell_cmd_write_fabric_verilog_id, openfpga_verilog_cmd_class);
+  shell.set_command_execute_function(shell_cmd_write_fabric_verilog_id, write_fabric_verilog);
+
+  /* The 'build_fabric' command should NOT be executed before 'link_openfpga_arch' */
+  std::vector<ShellCommandId> cmd_dependency_write_fabric_verilog;
+  cmd_dependency_write_fabric_verilog.push_back(shell_cmd_build_fabric_id);
+  shell.set_command_dependency(shell_cmd_write_fabric_verilog_id, cmd_dependency_write_fabric_verilog);
+} 
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_verilog_command.h b/openfpga/src/base/openfpga_verilog_command.h
new file mode 100644
index 000000000..a99b809dd
--- /dev/null
+++ b/openfpga/src/base/openfpga_verilog_command.h
@@ -0,0 +1,21 @@
+#ifndef OPENFPGA_VERILOG_COMMAND_H
+#define OPENFPGA_VERILOG_COMMAND_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "shell.h"
+#include "openfpga_context.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void add_openfpga_verilog_commands(openfpga::Shell<OpenfpgaContext>& shell); 
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/fpga_verilog/verilog_api.cpp b/openfpga/src/fpga_verilog/verilog_api.cpp
index 7de1b95e9..0ad2cecb6 100644
--- a/openfpga/src/fpga_verilog/verilog_api.cpp
+++ b/openfpga/src/fpga_verilog/verilog_api.cpp
@@ -40,17 +40,17 @@ namespace openfpga {
  * 7. Pre-configured testbench, which can skip the configuration phase and pre-configure the FPGA module. This testbench is created for quick verification and formal verification purpose.
  * 8. Verilog netlist including preprocessing flags and all the Verilog netlists that have been generated
  ********************************************************************/
-void fabric_verilog(ModuleManager& module_manager,
-                    const CircuitLibrary& circuit_lib,
-                    const MuxLibrary& mux_lib,
-                    const DeviceGrid& grids, 
-                    const DeviceRRGSB& device_rr_gsb,
-                    const std::string& output_directory,
-                    const bool& compress_routing,
-                    const bool& dump_explict_verilog,
-                    const bool& verbose) {
+void fpga_fabric_verilog(const ModuleManager& module_manager,
+                         const CircuitLibrary& circuit_lib,
+                         const MuxLibrary& mux_lib,
+                         const DeviceGrid& grids, 
+                         const DeviceRRGSB& device_rr_gsb,
+                         const std::string& output_directory,
+                         const bool& compress_routing,
+                         const bool& dump_explict_verilog,
+                         const bool& verbose) {
 
-  vtr::ScopedStartFinishTimer timer("Generate Verilog netlists for FPGA fabric\n");
+  vtr::ScopedStartFinishTimer timer("Write Verilog netlists for FPGA fabric\n");
 
   std::string src_dir_path = format_dir_path(output_directory);
 
diff --git a/openfpga/src/fpga_verilog/verilog_api.h b/openfpga/src/fpga_verilog/verilog_api.h
index 9d601ee46..91f78e918 100644
--- a/openfpga/src/fpga_verilog/verilog_api.h
+++ b/openfpga/src/fpga_verilog/verilog_api.h
@@ -21,15 +21,15 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-void fabric_verilog(ModuleManager& module_manager,
-                    const CircuitLibrary& circuit_lib,
-                    const MuxLibrary& mux_lib,
-                    const DeviceGrid& grids, 
-                    const DeviceRRGSB& device_rr_gsb,
-                    const std::string& output_directory,
-                    const bool& compress_routing,
-                    const bool& dump_explict_verilog,
-                    const bool& verbose);
+void fpga_fabric_verilog(const ModuleManager& module_manager,
+                         const CircuitLibrary& circuit_lib,
+                         const MuxLibrary& mux_lib,
+                         const DeviceGrid& grids, 
+                         const DeviceRRGSB& device_rr_gsb,
+                         const std::string& output_directory,
+                         const bool& compress_routing,
+                         const bool& dump_explict_verilog,
+                         const bool& verbose);
 
 } /* end namespace openfpga */
 
diff --git a/openfpga/src/main.cpp b/openfpga/src/main.cpp
index c7c31b00c..792223e3c 100644
--- a/openfpga/src/main.cpp
+++ b/openfpga/src/main.cpp
@@ -12,6 +12,7 @@
 /* Header file from openfpga */
 #include "vpr_command.h"
 #include "openfpga_setup_command.h"
+#include "openfpga_verilog_command.h"
 #include "basic_command.h"
 
 #include "openfpga_title.h"
@@ -52,6 +53,9 @@ int main(int argc, char** argv) {
   /* Add openfpga setup commands */
   openfpga::add_openfpga_setup_commands(shell);
 
+  /* Add openfpga verilog commands */
+  openfpga::add_openfpga_verilog_commands(shell);
+
   /* Add basic commands: exit, help, etc. 
    * Note:
    * This MUST be the last command group to be added! 
diff --git a/openfpga/test_script/s298_k6_frac.openfpga b/openfpga/test_script/s298_k6_frac.openfpga
index 9d4edcced..1dece6d57 100644
--- a/openfpga/test_script/s298_k6_frac.openfpga
+++ b/openfpga/test_script/s298_k6_frac.openfpga
@@ -21,5 +21,9 @@ lut_truth_table_fixup #--verbose
 #  - Enable pin duplication on grid modules 
 build_fabric --compress_routing --duplicate_grid_pin --verbose
 
+# Write the Verilog netlit for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --verbose
+
 # Finish and exit OpenFPGA
 exit

From da79ef687c53351b4a184f1e7ab02156f05dd9d3 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 15 Feb 2020 20:54:37 -0700
Subject: [PATCH 146/645] add missing files

---
 openfpga/src/base/openfpga_verilog.cpp | 38 ++++++++++++++++++++++++++
 openfpga/src/base/openfpga_verilog.h   | 23 ++++++++++++++++
 2 files changed, 61 insertions(+)
 create mode 100644 openfpga/src/base/openfpga_verilog.cpp
 create mode 100644 openfpga/src/base/openfpga_verilog.h

diff --git a/openfpga/src/base/openfpga_verilog.cpp b/openfpga/src/base/openfpga_verilog.cpp
new file mode 100644
index 000000000..076127f4a
--- /dev/null
+++ b/openfpga/src/base/openfpga_verilog.cpp
@@ -0,0 +1,38 @@
+/********************************************************************
+ * This file includes functions to compress the hierachy of routing architecture
+ *******************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_time.h"
+#include "vtr_log.h"
+
+#include "verilog_api.h"
+#include "openfpga_verilog.h"
+
+/* Include global variables of VPR */
+#include "globals.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * A wrapper function to call the fabric_verilog function of FPGA-Verilog 
+ *******************************************************************/
+void write_fabric_verilog(OpenfpgaContext& openfpga_ctx,
+                          const Command& cmd, const CommandContext& cmd_context) {
+
+  CommandOptionId opt_output_dir = cmd.option("file");
+  CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping");
+  CommandOptionId opt_verbose = cmd.option("verbose");
+  
+  fpga_fabric_verilog(openfpga_ctx.module_graph(),
+                      openfpga_ctx.arch().circuit_lib,
+                      openfpga_ctx.mux_lib(),
+                      g_vpr_ctx.device().grid,
+                      openfpga_ctx.device_rr_gsb(),
+                      cmd_context.option_value(cmd, opt_output_dir),
+                      openfpga_ctx.flow_manager().compress_routing(),
+                      cmd_context.option_enable(cmd, opt_explicit_port_mapping),
+                      cmd_context.option_enable(cmd, opt_verbose));
+} 
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_verilog.h b/openfpga/src/base/openfpga_verilog.h
new file mode 100644
index 000000000..a62d19411
--- /dev/null
+++ b/openfpga/src/base/openfpga_verilog.h
@@ -0,0 +1,23 @@
+#ifndef OPENFPGA_VERILOG_H
+#define OPENFPGA_VERILOG_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "command.h"
+#include "command_context.h"
+#include "openfpga_context.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void write_fabric_verilog(OpenfpgaContext& openfpga_ctx,
+                          const Command& cmd, const CommandContext& cmd_context); 
+
+} /* end namespace openfpga */
+
+#endif

From bf54be3d00ac77b0d98e575804b03ef83007db6c Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 15 Feb 2020 21:39:47 -0700
Subject: [PATCH 147/645] add option data structure for FPGA Verilog

---
 openfpga/src/base/openfpga_verilog.cpp        | 20 ++++-
 openfpga/src/fpga_verilog/verilog_api.cpp     |  9 +--
 openfpga/src/fpga_verilog/verilog_api.h       |  6 +-
 openfpga/src/fpga_verilog/verilog_options.cpp | 73 +++++++++++++++++++
 openfpga/src/fpga_verilog/verilog_options.h   | 48 ++++++++++++
 5 files changed, 142 insertions(+), 14 deletions(-)
 create mode 100644 openfpga/src/fpga_verilog/verilog_options.cpp
 create mode 100644 openfpga/src/fpga_verilog/verilog_options.h

diff --git a/openfpga/src/base/openfpga_verilog.cpp b/openfpga/src/base/openfpga_verilog.cpp
index 076127f4a..2612fe76a 100644
--- a/openfpga/src/base/openfpga_verilog.cpp
+++ b/openfpga/src/base/openfpga_verilog.cpp
@@ -22,17 +22,29 @@ void write_fabric_verilog(OpenfpgaContext& openfpga_ctx,
 
   CommandOptionId opt_output_dir = cmd.option("file");
   CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping");
+  CommandOptionId opt_include_timing = cmd.option("include_timing");
+  CommandOptionId opt_include_signal_init = cmd.option("include_signal_init");
+  CommandOptionId opt_support_icarus_simulator = cmd.option("support_icarus_simulator");
   CommandOptionId opt_verbose = cmd.option("verbose");
+
+  /* This is an intermediate data structure which is designed to modularize the FPGA-Verilog
+   * Keep it independent from any other outside data structures
+   */
+  FabricVerilogOption options;
+  options.set_output_directory(cmd_context.option_value(cmd, opt_output_dir));
+  options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping));
+  options.set_include_timing(cmd_context.option_enable(cmd, opt_include_timing));
+  options.set_include_signal_init(cmd_context.option_enable(cmd, opt_include_signal_init));
+  options.set_support_icarus_simulator(cmd_context.option_enable(cmd, opt_support_icarus_simulator));
+  options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
+  options.set_compress_routing(openfpga_ctx.flow_manager().compress_routing());
   
   fpga_fabric_verilog(openfpga_ctx.module_graph(),
                       openfpga_ctx.arch().circuit_lib,
                       openfpga_ctx.mux_lib(),
                       g_vpr_ctx.device().grid,
                       openfpga_ctx.device_rr_gsb(),
-                      cmd_context.option_value(cmd, opt_output_dir),
-                      openfpga_ctx.flow_manager().compress_routing(),
-                      cmd_context.option_enable(cmd, opt_explicit_port_mapping),
-                      cmd_context.option_enable(cmd, opt_verbose));
+                      options);
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/fpga_verilog/verilog_api.cpp b/openfpga/src/fpga_verilog/verilog_api.cpp
index 0ad2cecb6..d8dd8dab8 100644
--- a/openfpga/src/fpga_verilog/verilog_api.cpp
+++ b/openfpga/src/fpga_verilog/verilog_api.cpp
@@ -45,14 +45,11 @@ void fpga_fabric_verilog(const ModuleManager& module_manager,
                          const MuxLibrary& mux_lib,
                          const DeviceGrid& grids, 
                          const DeviceRRGSB& device_rr_gsb,
-                         const std::string& output_directory,
-                         const bool& compress_routing,
-                         const bool& dump_explict_verilog,
-                         const bool& verbose) {
+                         const FabricVerilogOption& options) {
 
   vtr::ScopedStartFinishTimer timer("Write Verilog netlists for FPGA fabric\n");
 
-  std::string src_dir_path = format_dir_path(output_directory);
+  std::string src_dir_path = format_dir_path(options.output_directory());
 
   /* Create directories */
   create_dir_path(src_dir_path.c_str());
@@ -110,7 +107,7 @@ void fpga_fabric_verilog(const ModuleManager& module_manager,
   //                         dump_explicit_verilog);
 
   /* Given a brief stats on how many Verilog modules have been written to files */
-  VTR_LOGV(verbose, 
+  VTR_LOGV(options.verbose_output(), 
            "Outputted %lu Verilog modules in total\n", 
            module_manager.num_modules());  
 }
diff --git a/openfpga/src/fpga_verilog/verilog_api.h b/openfpga/src/fpga_verilog/verilog_api.h
index 91f78e918..a24c0a1e8 100644
--- a/openfpga/src/fpga_verilog/verilog_api.h
+++ b/openfpga/src/fpga_verilog/verilog_api.h
@@ -13,6 +13,7 @@
 #include "device_grid.h"
 #include "device_rr_gsb.h"
 #include "module_manager.h"
+#include "verilog_options.h"
 
 /********************************************************************
  * Function declaration
@@ -26,10 +27,7 @@ void fpga_fabric_verilog(const ModuleManager& module_manager,
                          const MuxLibrary& mux_lib,
                          const DeviceGrid& grids, 
                          const DeviceRRGSB& device_rr_gsb,
-                         const std::string& output_directory,
-                         const bool& compress_routing,
-                         const bool& dump_explict_verilog,
-                         const bool& verbose);
+                         const FabricVerilogOption& options);
 
 } /* end namespace openfpga */
 
diff --git a/openfpga/src/fpga_verilog/verilog_options.cpp b/openfpga/src/fpga_verilog/verilog_options.cpp
new file mode 100644
index 000000000..a0dfd7e2a
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_options.cpp
@@ -0,0 +1,73 @@
+/******************************************************************************
+ * Memember functions for data structure FabricVerilogOption
+ ******************************************************************************/
+#include "vtr_assert.h"
+
+#include "verilog_options.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/**************************************************
+ * Public Accessors 
+ *************************************************/
+std::string FabricVerilogOption::output_directory() const {
+  return output_directory_;
+}
+
+bool FabricVerilogOption::support_icarus_simulator() const {
+  return support_icarus_simulator_;
+}
+
+bool FabricVerilogOption::include_timing() const {
+  return include_timing_;
+}
+
+bool FabricVerilogOption::include_signal_init() const {
+  return include_signal_init_;
+}
+
+bool FabricVerilogOption::explicit_port_mapping() const {
+  return explicit_port_mapping_;
+}
+
+bool FabricVerilogOption::compress_routing() const {
+  return compress_routing_;
+}
+
+bool FabricVerilogOption::verbose_output() const {
+  return verbose_output_;
+}
+
+/******************************************************************************
+ * Private Mutators
+ ******************************************************************************/
+void FabricVerilogOption::set_output_directory(const std::string& output_dir) {
+  output_directory_ = output_dir;
+}
+
+void FabricVerilogOption::set_support_icarus_simulator(const bool& enabled) {
+  support_icarus_simulator_ = enabled;
+}
+
+void FabricVerilogOption::set_include_timing(const bool& enabled) {
+  include_timing_ = enabled;
+}
+
+void FabricVerilogOption::set_include_signal_init(const bool& enabled) {
+  include_signal_init_ = enabled;
+}
+
+void FabricVerilogOption::set_explicit_port_mapping(const bool& enabled) {
+  explicit_port_mapping_ = enabled;
+}
+
+void FabricVerilogOption::set_compress_routing(const bool& enabled) {
+  compress_routing_ = enabled;
+}
+
+void FabricVerilogOption::set_verbose_output(const bool& enabled) {
+  verbose_output_ = enabled;
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_verilog/verilog_options.h b/openfpga/src/fpga_verilog/verilog_options.h
new file mode 100644
index 000000000..336ec542a
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_options.h
@@ -0,0 +1,48 @@
+#ifndef VERILOG_OPTIONS_H
+#define VERILOG_OPTIONS_H
+
+/********************************************************************
+ * Include header files required by the data structure definition
+ *******************************************************************/
+#include <string>
+
+/* Begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * FlowManager aims to resolve the dependency between OpenFPGA functional
+ * code blocks
+ * It can provide flags for downstream modules about if the data structures
+ * they require have already been constructed
+ *
+ *******************************************************************/
+class FabricVerilogOption {
+  public: /* Public accessors */
+    std::string output_directory() const;
+    bool support_icarus_simulator() const;
+    bool include_timing() const;
+    bool include_signal_init() const;
+    bool explicit_port_mapping() const;
+    bool compress_routing() const;
+    bool verbose_output() const;
+  public: /* Public mutators */
+    void set_output_directory(const std::string& output_dir);
+    void set_support_icarus_simulator(const bool& enabled);
+    void set_include_timing(const bool& enabled);
+    void set_include_signal_init(const bool& enabled);
+    void set_explicit_port_mapping(const bool& enabled);
+    void set_compress_routing(const bool& enabled);
+    void set_verbose_output(const bool& enabled);
+  private: /* Internal Data */
+    std::string output_directory_;
+    bool support_icarus_simulator_;
+    bool include_signal_init_;
+    bool include_timing_;
+    bool explicit_port_mapping_;
+    bool compress_routing_;
+    bool verbose_output_;
+};
+
+} /* End namespace openfpga*/
+
+#endif

From 0d5292ad0da38f66440805281288ce6823f1b9ed Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 15 Feb 2020 23:26:59 -0700
Subject: [PATCH 148/645] adapt verilog writer utils

---
 .../src/fpga_verilog/verilog_writer_utils.cpp | 1397 +++++++++++++++++
 .../src/fpga_verilog/verilog_writer_utils.h   |  187 +++
 2 files changed, 1584 insertions(+)
 create mode 100644 openfpga/src/fpga_verilog/verilog_writer_utils.cpp
 create mode 100644 openfpga/src/fpga_verilog/verilog_writer_utils.h

diff --git a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp
new file mode 100644
index 000000000..5798b05fc
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp
@@ -0,0 +1,1397 @@
+/************************************************
+ * Include functions for most frequently
+ * used Verilog writers 
+ ***********************************************/
+#include <chrono>
+#include <ctime>
+#include <string>
+#include <fstream>
+#include <iomanip>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+/* Headers from readarchopenfpga library */
+#include "circuit_types.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_digest.h"
+
+#include "openfpga_naming.h"
+#include "circuit_library_utils.h"
+#include "verilog_constants.h"
+#include "verilog_writer_utils.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/************************************************
+ * Generate header comments for a Verilog netlist
+ * include the description 
+ ***********************************************/
+void print_verilog_file_header(std::fstream& fp,
+                               const std::string& usage) {
+  valid_file_stream(fp);
+ 
+  auto end = std::chrono::system_clock::now(); 
+  std::time_t end_time = std::chrono::system_clock::to_time_t(end);
+
+  fp << "//-------------------------------------------" << std::endl;
+  fp << "//\tFPGA Synthesizable Verilog Netlist" << std::endl;
+  fp << "//\tDescription: " << usage << std::endl;
+  fp << "//\tAuthor: Xifan TANG" << std::endl;
+  fp << "//\tOrganization: University of Utah" << std::endl;
+  fp << "//\tDate: " << std::ctime(&end_time) ;
+  fp << "//-------------------------------------------" << std::endl;
+  fp << "//----- Time scale -----" << std::endl;
+  fp << "`timescale 1ns / 1ps" << std::endl;
+  fp << std::endl;
+}
+
+/********************************************************************
+ * Print Verilog codes to include a netlist  
+ *******************************************************************/
+void print_verilog_include_netlist(std::fstream& fp, 
+                                   const std::string& netlist_name) {
+  valid_file_stream(fp);
+
+  fp << "`include \"" << netlist_name << "\"" << std::endl; 
+}
+
+/********************************************************************
+ * Print Verilog codes to define a preprocessing flag
+ *******************************************************************/
+void print_verilog_define_flag(std::fstream& fp, 
+                               const std::string& flag_name,
+                               const int& flag_value) {
+  valid_file_stream(fp);
+
+  fp << "`define " << flag_name << " " << flag_value << std::endl; 
+}
+
+/************************************************
+ * Generate include files for a Verilog netlist
+ ***********************************************/
+void print_verilog_include_defines_preproc_file(std::fstream& fp, 
+                                                const std::string& verilog_dir) {
+  
+  /* Generate the file name */
+  std::string include_file_path = format_dir_path(verilog_dir);
+  include_file_path += std::string(DEFINES_VERILOG_FILE_NAME);
+
+  print_verilog_include_netlist(fp, include_file_path); 
+}
+
+/************************************************
+ * Print a Verilog comment line
+ ***********************************************/
+void print_verilog_comment(std::fstream& fp, 
+                           const std::string& comment) {
+  valid_file_stream(fp);
+
+  fp << "// " << comment << std::endl;
+}
+
+/************************************************
+ * Print the declaration of a Verilog preprocessing flag
+ ***********************************************/
+void print_verilog_preprocessing_flag(std::fstream& fp,
+                                      const std::string& preproc_flag) {
+  valid_file_stream(fp);
+
+  fp << "`ifdef " << preproc_flag << std::endl;
+}
+
+/************************************************
+ * Print the endif of a Verilog preprocessing flag
+ ***********************************************/
+void print_verilog_endif(std::fstream& fp) {
+  valid_file_stream(fp);
+
+  fp << "`endif" << std::endl;
+}
+
+/************************************************
+ * Print a Verilog module definition
+ * We use the following format:
+ * module <module_name> (<ports without directions>);
+ ***********************************************/
+void print_verilog_module_definition(std::fstream& fp, 
+                                     const ModuleManager& module_manager, const ModuleId& module_id) {
+  valid_file_stream(fp);
+
+  print_verilog_comment(fp, std::string("----- Verilog module for " + module_manager.module_name(module_id) + " -----"));
+
+  std::string module_head_line = "module " + module_manager.module_name(module_id) + "(";
+  fp << module_head_line;
+
+  /* port type2type mapping */
+  std::map<ModuleManager::e_module_port_type, enum e_dump_verilog_port_type> port_type2type_map;
+  port_type2type_map[ModuleManager::MODULE_GLOBAL_PORT] = VERILOG_PORT_CONKT;
+  port_type2type_map[ModuleManager::MODULE_GPIO_PORT] = VERILOG_PORT_CONKT;
+  port_type2type_map[ModuleManager::MODULE_INOUT_PORT] = VERILOG_PORT_CONKT;
+  port_type2type_map[ModuleManager::MODULE_INPUT_PORT] = VERILOG_PORT_CONKT;
+  port_type2type_map[ModuleManager::MODULE_OUTPUT_PORT] = VERILOG_PORT_CONKT;
+  port_type2type_map[ModuleManager::MODULE_CLOCK_PORT] = VERILOG_PORT_CONKT;
+
+  /* Port sequence: global, inout, input, output and clock ports, */
+  size_t port_cnt = 0;
+  bool printed_ifdef = false; /* A flag to tell if an ifdef has been printed for the last port */
+  for (const auto& kv : port_type2type_map) {
+    for (const auto& port : module_manager.module_ports_by_type(module_id, kv.first)) {
+      if (0 != port_cnt) {
+        /* Do not dump a comma for the first port */
+        fp << "," << std::endl; 
+      }
+
+      if (true == printed_ifdef) {
+        /* Print an endif to pair the ifdef */
+        print_verilog_endif(fp);
+        /* Reset the flag */
+        printed_ifdef = false;
+      }
+
+      ModulePortId port_id = module_manager.find_module_port(module_id, port.get_name());
+      VTR_ASSERT(ModulePortId::INVALID() != port_id);
+      /* Print pre-processing flag for a port, if defined */
+      std::string preproc_flag = module_manager.port_preproc_flag(module_id, port_id);
+      if (false == preproc_flag.empty()) {
+        /* Print an ifdef Verilog syntax */
+        print_verilog_preprocessing_flag(fp, preproc_flag);
+        /* Raise the flag */
+        printed_ifdef = true;
+      }
+
+      /* Create a space for "module <module_name>" except the first line! */
+      if (0 != port_cnt) {
+        std::string port_whitespace(module_head_line.length(), ' ');
+        fp << port_whitespace;
+      }
+      /* Print port: only the port name is enough */
+      fp << port.get_name();
+
+      /* Increase the counter */
+      port_cnt++;
+    }
+  }
+  fp << ");" << std::endl;
+}
+
+/************************************************
+ * Print a Verilog module ports based on the module id 
+ ***********************************************/
+void print_verilog_module_ports(std::fstream& fp, 
+                                const ModuleManager& module_manager, const ModuleId& module_id) {
+  valid_file_stream(fp);
+
+  /* port type2type mapping */
+  std::map<ModuleManager::e_module_port_type, enum e_dump_verilog_port_type> port_type2type_map;
+  port_type2type_map[ModuleManager::MODULE_GLOBAL_PORT] = VERILOG_PORT_INPUT;
+  port_type2type_map[ModuleManager::MODULE_GPIO_PORT] = VERILOG_PORT_INOUT;
+  port_type2type_map[ModuleManager::MODULE_INOUT_PORT] = VERILOG_PORT_INOUT;
+  port_type2type_map[ModuleManager::MODULE_INPUT_PORT] = VERILOG_PORT_INPUT;
+  port_type2type_map[ModuleManager::MODULE_OUTPUT_PORT] = VERILOG_PORT_OUTPUT;
+  port_type2type_map[ModuleManager::MODULE_CLOCK_PORT] = VERILOG_PORT_INPUT;
+
+  /* Port sequence: global, inout, input, output and clock ports, */
+  for (const auto& kv : port_type2type_map) {
+    for (const auto& port : module_manager.module_ports_by_type(module_id, kv.first)) {
+      ModulePortId port_id = module_manager.find_module_port(module_id, port.get_name());
+      VTR_ASSERT(ModulePortId::INVALID() != port_id);
+      /* Print pre-processing flag for a port, if defined */
+      std::string preproc_flag = module_manager.port_preproc_flag(module_id, port_id);
+      if (false == preproc_flag.empty()) {
+        /* Print an ifdef Verilog syntax */
+        print_verilog_preprocessing_flag(fp, preproc_flag);
+      }
+
+      /* Print port */
+      fp << "//----- " << module_manager.module_port_type_str(kv.first)  << " -----" << std::endl; 
+      fp << generate_verilog_port(kv.second, port);
+      fp << ";" << std::endl;
+
+      if (false == preproc_flag.empty()) {
+        /* Print an endif to pair the ifdef */
+        print_verilog_endif(fp);
+      }
+    }
+  }
+
+  /* Output any port that is also wire connection */
+  fp << std::endl;
+  fp << "//----- BEGIN wire-connection ports -----" << std::endl; 
+  for (const auto& kv : port_type2type_map) {
+    for (const auto& port : module_manager.module_ports_by_type(module_id, kv.first)) {
+      /* Skip the ports that are not registered */
+      ModulePortId port_id = module_manager.find_module_port(module_id, port.get_name());
+      VTR_ASSERT(ModulePortId::INVALID() != port_id);
+      if (false == module_manager.port_is_wire(module_id, port_id)) {
+        continue;
+      }
+
+      /* Print pre-processing flag for a port, if defined */
+      std::string preproc_flag = module_manager.port_preproc_flag(module_id, port_id);
+      if (false == preproc_flag.empty()) {
+        /* Print an ifdef Verilog syntax */
+        print_verilog_preprocessing_flag(fp, preproc_flag);
+      }
+
+      /* Print port */
+      fp << generate_verilog_port(VERILOG_PORT_WIRE, port);
+      fp << ";" << std::endl;
+
+      if (false == preproc_flag.empty()) {
+        /* Print an endif to pair the ifdef */
+        print_verilog_endif(fp);
+      }
+    }
+  }
+  fp << "//----- END wire-connection ports -----" << std::endl; 
+  fp << std::endl;
+
+ 
+  /* Output any port that is registered */
+  fp << std::endl;
+  fp << "//----- BEGIN Registered ports -----" << std::endl; 
+  for (const auto& kv : port_type2type_map) {
+    for (const auto& port : module_manager.module_ports_by_type(module_id, kv.first)) {
+      /* Skip the ports that are not registered */
+      ModulePortId port_id = module_manager.find_module_port(module_id, port.get_name());
+      VTR_ASSERT(ModulePortId::INVALID() != port_id);
+      if (false == module_manager.port_is_register(module_id, port_id)) {
+        continue;
+      }
+
+      /* Print pre-processing flag for a port, if defined */
+      std::string preproc_flag = module_manager.port_preproc_flag(module_id, port_id);
+      if (false == preproc_flag.empty()) {
+        /* Print an ifdef Verilog syntax */
+        print_verilog_preprocessing_flag(fp, preproc_flag);
+      }
+
+      /* Print port */
+      fp << generate_verilog_port(VERILOG_PORT_REG, port);
+      fp << ";" << std::endl;
+
+      if (false == preproc_flag.empty()) {
+        /* Print an endif to pair the ifdef */
+        print_verilog_endif(fp);
+      }
+    }
+  }
+  fp << "//----- END Registered ports -----" << std::endl; 
+  fp << std::endl;
+}
+
+/************************************************
+ * Print a Verilog module declaration (definition + port list
+ * We use the following format:
+ * module <module_name> (<ports without directions>);
+ * <tab><port definition with direction> 
+ ***********************************************/
+void print_verilog_module_declaration(std::fstream& fp, 
+                                      const ModuleManager& module_manager, const ModuleId& module_id) {
+  valid_file_stream(fp);
+
+  print_verilog_module_definition(fp, module_manager, module_id);
+
+  print_verilog_module_ports(fp, module_manager, module_id);
+}
+
+
+/********************************************************************
+ * Print an instance in Verilog format (a generic version)
+ * This function will require user to provide an instance name
+ *
+ * This function will output the port map by referring to a port-to-port 
+ * mapping:
+ *   <module_port_name> -> <instance_port_name>
+ * The key of the port-to-port mapping is the port name of the module: 
+ * The value of the port-to-port mapping is the port information of the instance
+ * With link between module and instance, the function can output a Verilog 
+ * instance easily, supporting both explicit port mapping:
+ *   .<module_port_name>(<instance_port_name>)
+ * and inexplicit port mapping
+ *   <instance_port_name>
+ *
+ * Note that, it is not necessary that the port-to-port mapping 
+ * covers all the module ports.
+ * Any instance/module port which are not specified in the port-to-port 
+ * mapping will be output by the module port name.
+ *******************************************************************/
+void print_verilog_module_instance(std::fstream& fp, 
+                                   const ModuleManager& module_manager, 
+                                   const ModuleId& module_id,
+                                   const std::string& instance_name,
+                                   const std::map<std::string, BasicPort>& port2port_name_map,
+                                   const bool& use_explicit_port_map) {
+
+  valid_file_stream(fp);
+
+  /* Check: all the key ports in the port2port_name_map does exist in the child module */
+  for (const auto& kv : port2port_name_map) {
+    ModulePortId module_port_id = module_manager.find_module_port(module_id, kv.first);
+    VTR_ASSERT(ModulePortId::INVALID() != module_port_id);
+  }
+
+  /* Print module name */
+  fp << "\t" << module_manager.module_name(module_id) << " ";
+  /* Print instance name */
+  fp << instance_name << " (" << std::endl;
+  
+  /* Print each port with/without explicit port map */
+  /* port type2type mapping */
+  std::map<ModuleManager::e_module_port_type, enum e_dump_verilog_port_type> port_type2type_map;
+  port_type2type_map[ModuleManager::MODULE_GLOBAL_PORT] = VERILOG_PORT_CONKT;
+  port_type2type_map[ModuleManager::MODULE_GPIO_PORT] = VERILOG_PORT_CONKT;
+  port_type2type_map[ModuleManager::MODULE_INOUT_PORT] = VERILOG_PORT_CONKT;
+  port_type2type_map[ModuleManager::MODULE_INPUT_PORT] = VERILOG_PORT_CONKT;
+  port_type2type_map[ModuleManager::MODULE_OUTPUT_PORT] = VERILOG_PORT_CONKT;
+  port_type2type_map[ModuleManager::MODULE_CLOCK_PORT] = VERILOG_PORT_CONKT;
+
+  /* Port sequence: global, inout, input, output and clock ports, */
+  size_t port_cnt = 0;
+  for (const auto& kv : port_type2type_map) {
+    for (const auto& port : module_manager.module_ports_by_type(module_id, kv.first)) {
+      if (0 != port_cnt) {
+        /* Do not dump a comma for the first port */
+        fp << "," << std::endl; 
+      }
+      /* Print port */
+      fp << "\t\t";
+      /* if explicit port map is required, output the port name */
+      if (true == use_explicit_port_map) {
+        fp << "." << port.get_name() << "(";
+      }
+      /* Try to find the instanced port name in the name map */
+      if (port2port_name_map.find(port.get_name()) != port2port_name_map.end()) {
+        /* Found it, we assign the port name */ 
+        /* TODO: make sure the port width matches! */
+        ModulePortId module_port_id = module_manager.find_module_port(module_id, port.get_name());
+        /* Get the port from module */
+        BasicPort module_port = module_manager.module_port(module_id, module_port_id);
+        VTR_ASSERT(module_port.get_width() == port2port_name_map.at(port.get_name()).get_width());
+        fp << generate_verilog_port(kv.second, port2port_name_map.at(port.get_name()));
+      } else {
+        /* Not found, we give the default port name */
+        fp << generate_verilog_port(kv.second, port);
+      }
+      /* if explicit port map is required, output the pair of branket */
+      if (true == use_explicit_port_map) {
+        fp << ")";
+      }
+      port_cnt++;
+    }
+  }
+  
+  /* Print an end to the instance */
+  fp << ");" << std::endl;
+}
+
+
+/************************************************
+ * Print an instance for a Verilog module
+ * This function is a wrapper for the generic version of
+ * print_verilog_module_instance() 
+ * This function create an instance name based on the index
+ * of the child module in its parent module
+ ***********************************************/
+void print_verilog_module_instance(std::fstream& fp, 
+                                   const ModuleManager& module_manager, 
+                                   const ModuleId& parent_module_id, const ModuleId& child_module_id,
+                                   const std::map<std::string, BasicPort>& port2port_name_map,
+                                   const bool& use_explicit_port_map) {
+
+  /* Create instance name, <name>_<num_instance_in_parent_module> */
+  std::string instance_name = module_manager.module_name(child_module_id) 
+                            + "_" 
+                            + std::to_string(module_manager.num_instance(parent_module_id, child_module_id)) 
+                            + "_";
+
+  print_verilog_module_instance(fp, module_manager, child_module_id, instance_name,
+                                port2port_name_map, use_explicit_port_map);
+}
+
+/************************************************
+ * Print an end line for a Verilog module
+ ***********************************************/
+void print_verilog_module_end(std::fstream& fp, 
+                              const std::string& module_name) {
+  valid_file_stream(fp);
+
+  fp << "endmodule" << std::endl;
+  print_verilog_comment(fp, std::string("----- END Verilog module for " + module_name + " -----"));
+  fp << std::endl;
+}
+
+/************************************************
+ * Generate a string of a Verilog port  
+ ***********************************************/
+std::string generate_verilog_port(const enum e_dump_verilog_port_type& verilog_port_type,
+                                  const BasicPort& port_info) {  
+  std::string verilog_line;
+
+  /* Ensure the port type is valid */
+  VTR_ASSERT(verilog_port_type < NUM_VERILOG_PORT_TYPES);
+
+  std::string size_str = "[" + std::to_string(port_info.get_lsb()) + ":" + std::to_string(port_info.get_msb()) + "]";
+
+  /* Only connection require a format of <port_name>[<lsb>:<msb>]
+   * others require a format of <port_type> [<lsb>:<msb>] <port_name> 
+   */
+  if (VERILOG_PORT_CONKT == verilog_port_type) {
+    /* When LSB == MSB, we can use a simplified format <port_type>[<lsb>]*/
+    if ( 1 == port_info.get_width()) {
+      size_str = "[" + std::to_string(port_info.get_lsb()) + "]";
+    }
+    verilog_line = port_info.get_name() + size_str;
+  } else { 
+    verilog_line = VERILOG_PORT_TYPE_STRING[verilog_port_type]; 
+    verilog_line += " " + size_str + " " + port_info.get_name();
+  }
+
+  return verilog_line;
+}
+
+/********************************************************************
+ * Evaluate if two Verilog ports can be merged:
+ * If the port name is same, it can merged 
+ *******************************************************************/
+bool two_verilog_ports_mergeable(const BasicPort& portA,
+                                 const BasicPort& portB) {
+  if (0 == portA.get_name().compare(portB.get_name())) {
+    return true;
+  }
+  return false;
+}
+
+/********************************************************************
+ * Merge two Verilog ports, return the merged port
+ * The ports should have the same name
+ * The new LSB will be minimum of the LSBs of the two ports
+ * The new MSB will the maximum of the MSBs of the two ports
+ *******************************************************************/
+BasicPort merge_two_verilog_ports(const BasicPort& portA,
+                                  const BasicPort& portB) {
+  BasicPort merged_port;
+  
+  VTR_ASSERT(true == two_verilog_ports_mergeable(portA, portB));
+
+  merged_port.set_name(portA.get_name());
+  merged_port.set_lsb((size_t)std::min((int)portA.get_lsb(), (int)portB.get_lsb()));
+  merged_port.set_msb((size_t)std::max((int)portA.get_msb(), (int)portB.get_msb()));
+
+  return merged_port;
+}
+
+/************************************************
+ * This function takes a list of ports and
+ * combine the port string by comparing the name 
+ * and width of ports.
+ * For example, two ports A and B share the same name is 
+ * mergable as long as A's MSB + 1 == B's LSB
+ * Note that the port sequence really matters!
+ * This function will NOT change the sequence
+ * of ports in the list port_info
+ ***********************************************/
+std::vector<BasicPort> combine_verilog_ports(const std::vector<BasicPort>& ports) { 
+  std::vector<BasicPort> merged_ports;
+
+  /* Directly return if there are no ports */
+  if (0 == ports.size()) {
+    return merged_ports;
+  }
+  /* Push the first port to the merged ports */
+  merged_ports.push_back(ports[0]);
+
+  /* Iterate over ports */
+  for (const auto& port : ports) {
+    /* Bypass the first port, it is already in the list */
+    if (&port == &ports[0]) {
+      continue;
+    } 
+    /* Identify if the port name can be potentially merged: if the port name is already in the merged port list, it may be merged */
+    bool merged = false;
+    for (auto& merged_port : merged_ports) {
+      if (false == port.mergeable(merged_port)) {
+        /* Unable to merge, Go to next */
+        continue;
+      }
+      /* May be merged, check LSB of port and MSB of merged_port */
+      if (merged_port.get_msb() + 1 != port.get_lsb()) {
+        /* Unable to merge, Go to next */
+        continue;
+      } 
+      /* Reach here, we should merge the ports,
+       * LSB of merged_port remains the same,
+       * MSB of merged_port will be updated 
+       * to the MSB of port 
+       */
+      merged_port.set_msb(port.get_msb());
+      merged = true;
+      break;
+    }
+    if (false == merged) {
+      /* Unable to merge, add the port to merged port list */
+      merged_ports.push_back(port);
+    }
+  }
+
+  return merged_ports;
+}
+
+/************************************************
+ * Generate the string of a list of verilog ports 
+ ***********************************************/
+std::string generate_verilog_ports(const std::vector<BasicPort>& merged_ports) {  
+
+  /* Output the string of ports:
+   * If there is only one port in the merged_port list
+   * we only output the port.
+   * If there are more than one port in the merged port list, we output an concatenated port:
+   *  {<port1>, <port2>, ... <last_port>}  
+   */
+  VTR_ASSERT(0 < merged_ports.size());
+  if ( 1 == merged_ports.size()) {
+    /* Use connection type of verilog port */
+    return generate_verilog_port(VERILOG_PORT_CONKT, merged_ports[0]);  
+  }
+
+  std::string verilog_line = "{";
+  for (const auto& port : merged_ports) {
+    /* The first port does not need a comma */
+    if (&port != &merged_ports[0]) {
+      verilog_line += ", ";
+    }
+    verilog_line += generate_verilog_port(VERILOG_PORT_CONKT, port);  
+  }
+  verilog_line += "}";
+
+  return verilog_line;
+}
+
+/********************************************************************
+ * Generate a bus port (could be used to create a local wire) 
+ * for a list of Verilog ports
+ * The bus port will be created by aggregating the ports in the list 
+ * A bus port name may be need only there are many ports with 
+ * different names. It is hard to name the bus port
+ *******************************************************************/
+BasicPort generate_verilog_bus_port(const std::vector<BasicPort>& input_ports, 
+                                    const std::string& bus_port_name) {
+  /* Try to combine the ports */
+  std::vector<BasicPort> combined_input_ports = combine_verilog_ports(input_ports);
+  
+  /* Create a port data structure that is to be returned */
+  BasicPort bus_port;
+
+  if (1 == combined_input_ports.size()) {
+    bus_port = combined_input_ports[0];
+  } else {
+    /* TODO: the naming could be more flexible? */
+    bus_port.set_name(bus_port_name);
+    /* Deposite a [0:0] port */
+    bus_port.set_width(1);
+    for (const auto& port : combined_input_ports) {
+      bus_port.combine(port);
+    }
+  }
+  
+  return bus_port;
+}
+
+/********************************************************************
+ * Generate a bus wire declaration for a list of Verilog ports
+ * Output ports: the local_wire name
+ * Input ports: the driving ports
+ * When there are more than two ports, a bus wiring will be created
+ *     {<port0>, <port1>, ... <last_port>}
+ *******************************************************************/
+std::string generate_verilog_local_wire(const BasicPort& output_port,
+                                        const std::vector<BasicPort>& input_ports) {
+  /* Try to combine the ports */
+  std::vector<BasicPort> combined_input_ports = combine_verilog_ports(input_ports);
+
+  /* If we have more than 1 port in the combined ports , 
+   * output a local wire */
+  VTR_ASSERT(0 < combined_input_ports.size());
+
+  /* Must check: the port width matches */
+  size_t input_ports_width = 0;
+  for (const auto& port : combined_input_ports) {
+    /* We must have valid ports! */
+    VTR_ASSERT( 0 < port.get_width() );
+    input_ports_width += port.get_width();
+  }
+  VTR_ASSERT( input_ports_width == output_port.get_width() );
+
+  std::string wire_str;
+  wire_str += generate_verilog_port(VERILOG_PORT_WIRE, output_port);
+  wire_str += " = ";
+  wire_str += generate_verilog_ports(combined_input_ports);
+  wire_str += ";";
+
+  return wire_str;
+}
+
+/********************************************************************
+ * Generate a string for a constant value in Verilog format:
+ *  <#.of bits>'b<binary numbers>
+ *******************************************************************/
+std::string generate_verilog_constant_values(const std::vector<size_t>& const_values) {
+  std::string str = std::to_string(const_values.size());
+  str += "'b";
+  for (const auto& val : const_values) {
+    str += std::to_string(val);
+  }
+  return str;
+}
+
+/********************************************************************
+ * Generate a verilog port with a deposite of constant values
+ ********************************************************************/
+std::string generate_verilog_port_constant_values(const BasicPort& output_port,
+                                                  const std::vector<size_t>& const_values) {
+  std::string port_str;
+
+  /* Must check: the port width matches */
+  VTR_ASSERT( const_values.size() == output_port.get_width() );
+
+  port_str = generate_verilog_port(VERILOG_PORT_CONKT, output_port);
+  port_str += " = ";
+  port_str += generate_verilog_constant_values(const_values);
+  return port_str;
+}
+
+/********************************************************************
+ * Generate a wire connection, that assigns constant values to a 
+ * Verilog port 
+ *******************************************************************/
+void print_verilog_wire_constant_values(std::fstream& fp,
+                                        const BasicPort& output_port,
+                                        const std::vector<size_t>& const_values) {
+  /* Make sure we have a valid file handler*/
+  valid_file_stream(fp);
+
+  fp << "\t";
+  fp << "assign ";
+  fp << generate_verilog_port_constant_values(output_port, const_values);
+  fp << ";" << std::endl;
+}
+
+/********************************************************************
+ * Deposit constant values to a Verilog port 
+ *******************************************************************/
+void print_verilog_deposit_wire_constant_values(std::fstream& fp,
+                                                const BasicPort& output_port,
+                                                const std::vector<size_t>& const_values) {
+  /* Make sure we have a valid file handler*/
+  valid_file_stream(fp);
+
+  fp << "\t";
+  fp << "$deposit(";
+  fp << generate_verilog_port(VERILOG_PORT_CONKT, output_port);
+  fp << ", ";
+  fp << generate_verilog_constant_values(const_values);
+  fp << ");" << std::endl;
+}
+
+/********************************************************************
+ * Generate a wire connection, that assigns constant values to a 
+ * Verilog port 
+ *******************************************************************/
+void print_verilog_force_wire_constant_values(std::fstream& fp,
+                                              const BasicPort& output_port,
+                                              const std::vector<size_t>& const_values) {
+  /* Make sure we have a valid file handler*/
+  valid_file_stream(fp);
+
+  fp << "\t";
+  fp << "force ";
+  fp << generate_verilog_port_constant_values(output_port, const_values);
+  fp << ";" << std::endl;
+}
+
+/********************************************************************
+ * Generate a wire connection for two Verilog ports 
+ * using "assign" syntax  
+ *******************************************************************/
+void print_verilog_wire_connection(std::fstream& fp,
+                                   const BasicPort& output_port,
+                                   const BasicPort& input_port, 
+                                   const bool& inverted) {
+  /* Make sure we have a valid file handler*/
+  valid_file_stream(fp);
+
+  /* Must check: the port width matches */
+  VTR_ASSERT( input_port.get_width() == output_port.get_width() );
+
+  fp << "\t";
+  fp << "assign ";
+  fp << generate_verilog_port(VERILOG_PORT_CONKT, output_port);
+  fp << " = ";
+  
+  if (true == inverted) {
+    fp << "~";
+  }
+
+  fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port);
+  fp << ";" << std::endl;
+}
+
+/********************************************************************
+ * Generate a wire connection for two Verilog ports 
+ * using "assign" syntax  
+ *******************************************************************/
+void print_verilog_register_connection(std::fstream& fp,
+                                       const BasicPort& output_port,
+                                       const BasicPort& input_port, 
+                                       const bool& inverted) {
+  /* Make sure we have a valid file handler*/
+  valid_file_stream(fp);
+
+  /* Must check: the port width matches */
+  VTR_ASSERT( input_port.get_width() == output_port.get_width() );
+
+  fp << "\t";
+  fp << generate_verilog_port(VERILOG_PORT_CONKT, output_port);
+  fp << " <= ";
+  
+  if (true == inverted) {
+    fp << "~";
+  }
+
+  fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port);
+  fp << ";" << std::endl;
+}
+
+
+/********************************************************************
+ * Generate an instance of a buffer module  
+ * with given information about the input and output ports of instance
+ *
+ *                                          Buffer instance
+ *                             +----------------------------------------+
+ *     instance_input_port --->| buffer_input_port    buffer_output_port|----> instance_output_port 
+ *                             +----------------------------------------+
+ *
+ * Restrictions:
+ *    Buffer must have only 1 input (non-global) port and 1 output (non-global) port
+ *******************************************************************/
+void print_verilog_buffer_instance(std::fstream& fp,
+                                   ModuleManager& module_manager, 
+                                   const CircuitLibrary& circuit_lib, 
+                                   const ModuleId& parent_module_id, 
+                                   const CircuitModelId& buffer_model, 
+                                   const BasicPort& instance_input_port,
+                                   const BasicPort& instance_output_port) {
+  /* Make sure we have a valid file handler*/
+  valid_file_stream(fp);
+
+  /* To match the context, Buffer should have only 2 non-global ports: 1 input port and 1 output port */
+  std::vector<CircuitPortId> buffer_model_input_ports = circuit_lib.model_ports_by_type(buffer_model, CIRCUIT_MODEL_PORT_INPUT, true);
+  std::vector<CircuitPortId> buffer_model_output_ports = circuit_lib.model_ports_by_type(buffer_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
+  VTR_ASSERT(1 == buffer_model_input_ports.size());
+  VTR_ASSERT(1 == buffer_model_output_ports.size());
+
+  /* Get the moduleId for the buffer module */
+  ModuleId buffer_module_id = module_manager.find_module(circuit_lib.model_name(buffer_model));
+  /* We must have one */
+  VTR_ASSERT(ModuleId::INVALID() != buffer_module_id);
+
+  /* Create a port-to-port map */
+  std::map<std::string, BasicPort> buffer_port2port_name_map;
+
+  /* Build the link between buffer_input_port[0] and output_node_pre_buffer 
+   * Build the link between buffer_output_port[0] and output_node_bufferred
+   */
+  { /* Create a code block to accommodate the local variables */
+    std::string module_input_port_name = circuit_lib.port_lib_name(buffer_model_input_ports[0]);
+    buffer_port2port_name_map[module_input_port_name] = instance_input_port; 
+    std::string module_output_port_name = circuit_lib.port_lib_name(buffer_model_output_ports[0]);
+    buffer_port2port_name_map[module_output_port_name] = instance_output_port; 
+  }
+
+  /* Output an instance of the module */
+  print_verilog_module_instance(fp, module_manager, parent_module_id, buffer_module_id, buffer_port2port_name_map, circuit_lib.dump_explicit_port_map(buffer_model));
+
+  /* IMPORTANT: this update MUST be called after the instance outputting!!!!
+   * update the module manager with the relationship between the parent and child modules 
+   */
+  module_manager.add_child_module(parent_module_id, buffer_module_id);
+}
+
+/********************************************************************
+ * Print local wires that are used for SRAM configuration 
+ * The local wires are strongly dependent on the organization of SRAMs.
+ * Standalone SRAMs: 
+ * -----------------
+ *    No need for local wires, their outputs are port of the module
+ *        
+ *              Module
+ *             +------------------------------+
+ *             |  Sub-module                  |
+ *             |  +---------------------+     |
+ *             |  |             sram_out|---->|---->sram_out
+ *             |  |                     |     |
+ *             |  |             sram_out|---->|---->sram_out
+ *             |  |                     |     |
+ *             |  +---------------------+     |
+ *             +------------------------------+      
+ *
+ * Configuration chain-style
+ * -------------------------
+ * wire [0:N] config_bus
+ *
+ *
+ *           Module
+ *          +--------------------------------------------------------------+
+ *          |  config_bus    config_bus    config_bus       config_bus     |
+ *          |     [0]           [1]           [2]              [N]         |
+ *          |      |             |             |                |          |
+ *          |      v             v             v                v          |
+ * ccff_head| ----------+  +---------+   +------------+   +----------------|-> ccff_tail
+ *          |           |  ^         |   ^            |   ^                |
+ *          |      head v  |tail     v   |            v   |                |
+ *          |       +----------+  +----------+     +----------+            |
+ *          |       |  Memory  |  |  Memory  |     |  Memory  |            |
+ *          |       |  Module  |  |  Module  | ... |  Module  |            |
+ *          |       |   [0]    |  |   [1]    |     |    [N]   |            |
+ *          |       +----------+  +----------+     +----------+            |
+ *          |            |             |                 |                 |
+ *          |            v             v                 v                 |
+ *          |       +----------+  +----------+     +----------+            |
+ *          |       |  MUX     |  |  MUX     |     |  MUX     |            |
+ *          |       |  Module  |  |  Module  | ... |  Module  |            |
+ *          |       |   [0]    |  |   [1]    |     |    [N]   |            |
+ *          |       +----------+  +----------+     +----------+            |
+ *          |                                                              |
+ *          +--------------------------------------------------------------+
+ *
+ * Memory bank-style
+ * -----------------
+ *    two ports will be added, which are regular output and inverted output 
+ *    Note that the outputs are the data outputs of SRAMs 
+ *    BL/WLs of memory decoders are ports of module but not local wires
+ *
+ *             Module
+ *            +-------------------------------------------------+
+ *            |                                                 |
+  BL/WL bus --+--------+------------+-----------------+         |
+ *            |         |            |                |         |
+ *            |   BL/WL v      BL/WL v          BL/WL v         |
+ *            |   +----------+  +----------+     +----------+   |
+ *            |   |  Memory  |  |  Memory  |     |  Memory  |   |
+ *            |   |  Module  |  |  Module  | ... |  Module  |   |
+ *            |   |   [0]    |  |   [1]    |     |    [N]   |   |
+ *            |   +----------+  +----------+     +----------+   |
+ *            |        |             |                 |        |
+ *            |        v             v                 v        |
+ *            |   +----------+  +----------+     +----------+   |
+ *            |   |  MUX     |  |  MUX     |     |  MUX     |   |
+ *            |   |  Module  |  |  Module  | ... |  Module  |   |
+ *            |   |   [0]    |  |   [1]    |     |    [N]   |   |
+ *            |   +----------+  +----------+     +----------+   |
+ *            |                                                 |
+ *            +-------------------------------------------------+
+ *
+ ********************************************************************/
+void print_verilog_local_sram_wires(std::fstream& fp,
+                                    const CircuitLibrary& circuit_lib,
+                                    const CircuitModelId& sram_model,
+                                    const e_config_protocol_type sram_orgz_type,
+                                    const size_t& port_size) {
+  /* Make sure we have a valid file handler*/
+  valid_file_stream(fp);
+
+  /* Port size must be at least one! */
+  if (0 == port_size) {
+    return;
+  }
+
+  /* Depend on the configuraion style */
+  switch(sram_orgz_type) {
+  case CONFIG_MEM_STANDALONE:
+    /* Nothing to do here */
+    break;
+  case CONFIG_MEM_SCAN_CHAIN: {
+    /* Generate the name of local wire for the CCFF inputs, CCFF output and inverted output */
+    /* [0] => CCFF input */
+    BasicPort ccff_config_bus_port(generate_local_config_bus_port_name(), port_size);
+    fp << generate_verilog_port(VERILOG_PORT_WIRE, ccff_config_bus_port) << ";" << std::endl; 
+    /* Connect first CCFF to the head */
+    /* Head is always a 1-bit port */
+    BasicPort ccff_head_port(generate_sram_port_name(sram_orgz_type, CIRCUIT_MODEL_PORT_INPUT), 1); 
+    BasicPort ccff_head_local_port(ccff_config_bus_port.get_name(), 1); 
+    print_verilog_wire_connection(fp, ccff_head_local_port, ccff_head_port, false); 
+    /* Connect last CCFF to the tail */
+    /* Tail is always a 1-bit port */
+    BasicPort ccff_tail_port(generate_sram_port_name(sram_orgz_type, CIRCUIT_MODEL_PORT_OUTPUT), 1); 
+    BasicPort ccff_tail_local_port(ccff_config_bus_port.get_name(), ccff_config_bus_port.get_msb(), ccff_config_bus_port.get_msb()); 
+    print_verilog_wire_connection(fp, ccff_tail_local_port, ccff_tail_port, false); 
+    break;
+  }
+  case CONFIG_MEM_MEMORY_BANK: {
+    /* Generate the name of local wire for the SRAM output and inverted output */
+    std::vector<BasicPort> sram_ports;
+    /* [0] => SRAM output */
+    sram_ports.push_back(BasicPort(generate_sram_local_port_name(circuit_lib, sram_model, sram_orgz_type, CIRCUIT_MODEL_PORT_INPUT), port_size));
+    /* [1] => SRAM inverted output */
+    sram_ports.push_back(BasicPort(generate_sram_local_port_name(circuit_lib, sram_model, sram_orgz_type, CIRCUIT_MODEL_PORT_OUTPUT), port_size));
+    /* Print local wire definition */
+    for (const auto& sram_port : sram_ports) {
+      fp << generate_verilog_port(VERILOG_PORT_WIRE, sram_port) << ";" << std::endl; 
+    }
+
+    break;
+  }
+  default:
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid SRAM organization!\n");
+    exit(1);
+  }
+}
+
+/*********************************************************************
+ * Print a number of bus ports which are wired to the configuration
+ * ports of a CMOS (SRAM-based) routing multiplexer
+ * This port is supposed to be used locally inside a Verilog/SPICE module 
+ *
+ * The following shows a few representative examples:
+ *
+ * For standalone configuration style:
+ * ------------------------------------
+ * No bus needed
+ *
+ * Configuration chain-style
+ * -------------------------
+ * wire [0:N] config_bus
+ *
+ *            config_bus    config_bus    config_bus       config_bus
+ *               [0]           [1]           [2]              [N]
+ *                |             |             |                |
+ *                v             v             v                v
+ * ccff_head ----------+  +---------+   +------------+   +----> ccff_tail
+ *                     |  ^         |   ^            |   ^
+ *                head v  |tail     v   |            v   |
+ *                 +----------+  +----------+     +----------+
+ *                 |  Memory  |  |  Memory  |     |  Memory  |
+ *                 |  Module  |  |  Module  | ... |  Module  |
+ *                 |   [0]    |  |   [1]    |     |    [N]   |
+ *                 +----------+  +----------+     +----------+
+ *                      |             |                 |
+ *                      v             v                 v
+ *                 +----------+  +----------+     +----------+
+ *                 |  MUX     |  |  MUX     |     |  MUX     |
+ *                 |  Module  |  |  Module  | ... |  Module  |
+ *                 |   [0]    |  |   [1]    |     |    [N]   |
+ *                 +----------+  +----------+     +----------+
+ *
+ * Memory bank-style
+ * -----------------
+ *         BL/WL bus --+------------+-------------------->
+ *                     |            |                |
+ *               BL/WL v      BL/WL v          BL/WL v
+ *               +----------+  +----------+     +----------+
+ *               |  Memory  |  |  Memory  |     |  Memory  |
+ *               |  Module  |  |  Module  | ... |  Module  |
+ *               |   [0]    |  |   [1]    |     |    [N]   |
+ *               +----------+  +----------+     +----------+
+ *                    |             |                 |
+ *                    v             v                 v
+ *               +----------+  +----------+     +----------+
+ *               |  MUX     |  |  MUX     |     |  MUX     |
+ *               |  Module  |  |  Module  | ... |  Module  |
+ *               |   [0]    |  |   [1]    |     |    [N]   |
+ *               +----------+  +----------+     +----------+
+ *     
+ *********************************************************************/
+void print_verilog_local_config_bus(std::fstream& fp, 
+                                    const std::string& prefix,
+                                    const e_config_protocol_type& sram_orgz_type,
+                                    const size_t& instance_id,
+                                    const size_t& num_conf_bits) { 
+  /* Make sure we have a valid file handler*/
+  valid_file_stream(fp);
+
+  switch(sram_orgz_type) {
+  case CONFIG_MEM_STANDALONE:
+    /* Not need for configuration bus
+     * The configuration ports of SRAM are directly wired to the ports of modules
+     */
+    break;
+  case CONFIG_MEM_SCAN_CHAIN: 
+  case CONFIG_MEM_MEMORY_BANK: {
+    /* Two configuration buses should be outputted
+     * One for the regular SRAM ports of a routing multiplexer
+     * The other for the inverted SRAM ports of a routing multiplexer
+     */
+    BasicPort config_port(generate_local_sram_port_name(prefix, instance_id, CIRCUIT_MODEL_PORT_INPUT), 
+                          num_conf_bits);
+    fp << generate_verilog_port(VERILOG_PORT_WIRE, config_port) << ";" << std::endl;
+    BasicPort inverted_config_port(generate_local_sram_port_name(prefix, instance_id, CIRCUIT_MODEL_PORT_OUTPUT), 
+                                   num_conf_bits); 
+    fp << generate_verilog_port(VERILOG_PORT_WIRE, inverted_config_port) << ";" << std::endl;
+    break;
+  }
+  default:
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid SRAM organization!\n");
+    exit(1);
+  }
+}
+
+/*********************************************************************
+ * Print a number of bus ports which are wired to the configuration
+ * ports of a ReRAM-based routing multiplexer
+ * This port is supposed to be used locally inside a Verilog/SPICE module 
+ *
+ * Currently support: 
+ * For memory-bank configuration style:
+ * ------------------------------------
+ * Different than CMOS routing multiplexers, ReRAM multiplexers require 
+ * reserved BL/WLs to be grouped in buses
+ *
+ *            Module Port
+ *                |
+ *                v
+ *  regular/reserved bus_port  --+----------------+---->     ...
+ *                               |                |
+ *          bl/wl/../sram_ports  v                v
+ *                        +-----------+     +-----------+
+ *                        |  Memory   |     |  Memory   |
+ *                        | Module[0] |     | Module[1] |    ...
+ *                        +-----------+     +-----------+
+ *                               |                |
+ *                               v                v
+ *                        +-----------+     +-----------+
+ *                        |  Routing  |     |  Routing  |
+ *                        |   MUX [0] |     |   MUX[1]  |    ...
+ *                        +-----------+     +-----------+
+ * 
+ *********************************************************************/
+static 
+void print_verilog_rram_mux_config_bus(std::fstream& fp, 
+                                       const CircuitLibrary& circuit_lib,
+                                       const CircuitModelId& mux_model,
+                                       const e_config_protocol_type& sram_orgz_type,
+                                       const size_t& mux_size,
+                                       const size_t& mux_instance_id,
+                                       const size_t& num_reserved_conf_bits, 
+                                       const size_t& num_conf_bits) { 
+  /* Make sure we have a valid file handler*/
+  valid_file_stream(fp);
+
+  switch(sram_orgz_type) {
+  case CONFIG_MEM_STANDALONE:
+    /* Not need for configuration bus
+     * The configuration ports of SRAM are directly wired to the ports of modules
+     */
+    break;
+  case CONFIG_MEM_SCAN_CHAIN: {
+    /* Not supported yet. 
+     * Configuration chain may be only applied to ReRAM-based multiplexers with local decoders
+     */
+    break;
+  }
+  case CONFIG_MEM_MEMORY_BANK: {
+    /* This is currently most used in ReRAM FPGAs */
+    /* Print configuration bus to group reserved BL/WLs */
+    BasicPort reserved_bl_bus(generate_reserved_sram_port_name(CIRCUIT_MODEL_PORT_BL), 
+                              num_reserved_conf_bits);
+    fp << generate_verilog_port(VERILOG_PORT_WIRE, reserved_bl_bus) << ";" << std::endl;
+    BasicPort reserved_wl_bus(generate_reserved_sram_port_name(CIRCUIT_MODEL_PORT_WL), 
+                              num_reserved_conf_bits);
+    fp << generate_verilog_port(VERILOG_PORT_WIRE, reserved_wl_bus) << ";" << std::endl;
+
+    /* Print configuration bus to group BL/WLs */
+    BasicPort bl_bus(generate_mux_config_bus_port_name(circuit_lib, mux_model, mux_size, 0, false), 
+                     num_conf_bits + num_reserved_conf_bits);
+    fp << generate_verilog_port(VERILOG_PORT_WIRE, bl_bus) << ";" << std::endl;
+    BasicPort wl_bus(generate_mux_config_bus_port_name(circuit_lib, mux_model, mux_size, 1, false), 
+                     num_conf_bits + num_reserved_conf_bits);
+    fp << generate_verilog_port(VERILOG_PORT_WIRE, wl_bus) << ";" << std::endl;
+
+    /* Print bus to group SRAM outputs, this is to interface memory cells to routing multiplexers */
+    BasicPort sram_output_bus(generate_mux_sram_port_name(circuit_lib, mux_model, mux_size, mux_instance_id, CIRCUIT_MODEL_PORT_INPUT), 
+                          num_conf_bits);
+    fp << generate_verilog_port(VERILOG_PORT_WIRE, sram_output_bus) << ";" << std::endl;
+    BasicPort inverted_sram_output_bus(generate_mux_sram_port_name(circuit_lib, mux_model, mux_size, mux_instance_id, CIRCUIT_MODEL_PORT_OUTPUT), 
+                                       num_conf_bits); 
+    fp << generate_verilog_port(VERILOG_PORT_WIRE, inverted_sram_output_bus) << ";" << std::endl;
+
+    /* Get the SRAM model of the mux_model */
+    std::vector<CircuitModelId> sram_models = find_circuit_sram_models(circuit_lib, mux_model);
+    /* TODO: maybe later multiplexers may have mode select ports... This should be relaxed */
+    VTR_ASSERT( 1 == sram_models.size() );
+
+    /* Wire the reserved configuration bits to part of bl/wl buses */
+    BasicPort bl_bus_reserved_bits(bl_bus.get_name(), num_reserved_conf_bits);
+    print_verilog_wire_connection(fp, bl_bus_reserved_bits, reserved_bl_bus, false);
+    BasicPort wl_bus_reserved_bits(wl_bus.get_name(), num_reserved_conf_bits);
+    print_verilog_wire_connection(fp, wl_bus_reserved_bits, reserved_wl_bus, false);
+
+    /* Connect SRAM BL/WLs to bus */
+    BasicPort mux_bl_wire(generate_sram_port_name(sram_orgz_type, CIRCUIT_MODEL_PORT_BL), 
+                          num_conf_bits); 
+    BasicPort bl_bus_regular_bits(bl_bus.get_name(), num_reserved_conf_bits, num_reserved_conf_bits + num_conf_bits - 1);
+    print_verilog_wire_connection(fp, bl_bus_regular_bits, mux_bl_wire, false);
+    BasicPort mux_wl_wire(generate_sram_port_name(sram_orgz_type, CIRCUIT_MODEL_PORT_WL), 
+                          num_conf_bits); 
+    BasicPort wl_bus_regular_bits(wl_bus.get_name(), num_reserved_conf_bits, num_reserved_conf_bits + num_conf_bits - 1);
+    print_verilog_wire_connection(fp, wl_bus_regular_bits, mux_wl_wire, false);
+
+    break;
+  }
+  default:
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid SRAM organization!\n");
+    exit(1);
+  }
+
+}
+
+/*********************************************************************
+ * Print a number of bus ports which are wired to the configuration
+ * ports of a memory module, which consists of a number of configuration
+ * memory cells, such as SRAMs.
+ * Note that the configuration bus will only interface the memory
+ * module, rather than the programming routing multiplexers, LUTs, IOs
+ * etc. This helps us to keep clean and simple Verilog generation
+ *********************************************************************/
+void print_verilog_mux_config_bus(std::fstream& fp, 
+                                  const CircuitLibrary& circuit_lib,
+                                  const CircuitModelId& mux_model,
+                                  const e_config_protocol_type& sram_orgz_type,
+                                  const size_t& mux_size,
+                                  const size_t& mux_instance_id,
+                                  const size_t& num_reserved_conf_bits, 
+                                  const size_t& num_conf_bits) { 
+  /* Depend on the design technology of this MUX:
+   * bus connections are different
+   * SRAM MUX: bus is connected to the output ports of SRAM
+   * RRAM MUX: bus is connected to the BL/WL of MUX
+   * TODO: Maybe things will become even more complicated, 
+   * the bus connections may depend on the type of configuration circuit...
+   * Currently, this is fine.
+   */
+  switch (circuit_lib.design_tech_type(mux_model)) {
+  case CIRCUIT_MODEL_DESIGN_CMOS: {
+    std::string prefix = generate_mux_subckt_name(circuit_lib, mux_model, mux_size, std::string());
+    print_verilog_local_config_bus(fp, prefix, sram_orgz_type, mux_instance_id, num_conf_bits);
+    break;
+  }
+  case CIRCUIT_MODEL_DESIGN_RRAM:
+    print_verilog_rram_mux_config_bus(fp, circuit_lib, mux_model, sram_orgz_type, mux_size, mux_instance_id, num_reserved_conf_bits, num_conf_bits);
+    break;
+  default:
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid design technology for routing multiplexer!\n");
+    exit(1);
+  }
+}
+
+/*********************************************************************
+ * Print a wire to connect MUX configuration ports 
+ * This function connects the sram ports to the ports of a Verilog module
+ * used for formal verification
+ *
+ * Note: MSB and LSB of formal verification configuration bus MUST be updated 
+ * before running this function !!!!
+ *********************************************************************/
+void print_verilog_formal_verification_mux_sram_ports_wiring(std::fstream& fp, 
+                                                             const CircuitLibrary& circuit_lib,
+                                                             const CircuitModelId& mux_model,
+                                                             const size_t& mux_size,
+                                                             const size_t& mux_instance_id,
+                                                             const size_t& num_conf_bits, 
+                                                             const BasicPort& fm_config_bus) { 
+  BasicPort mux_sram_output(generate_mux_sram_port_name(circuit_lib, mux_model, mux_size, mux_instance_id, CIRCUIT_MODEL_PORT_INPUT),
+                            num_conf_bits);
+  /* Get the SRAM model of the mux_model */
+  std::vector<CircuitModelId> sram_models = find_circuit_sram_models(circuit_lib, mux_model);
+  /* TODO: maybe later multiplexers may have mode select ports... This should be relaxed */
+  VTR_ASSERT( 1 == sram_models.size() );
+  BasicPort formal_verification_port;
+  formal_verification_port.set_name(generate_formal_verification_sram_port_name(circuit_lib, sram_models[0]));
+  VTR_ASSERT(num_conf_bits == fm_config_bus.get_width());
+  formal_verification_port.set_lsb(fm_config_bus.get_lsb());
+  formal_verification_port.set_msb(fm_config_bus.get_msb());
+  print_verilog_wire_connection(fp, mux_sram_output, formal_verification_port, false);
+}
+
+/********************************************************************
+ * Print stimuli for a pulse generation
+ *
+ *                |<--- pulse width --->|
+ *                                      +------ flip_value
+ *                                      |      
+ *  initial_value ----------------------+       
+ *
+ *******************************************************************/
+void print_verilog_pulse_stimuli(std::fstream& fp, 
+                                 const BasicPort& port,
+                                 const size_t& initial_value,
+                                 const float& pulse_width,
+                                 const size_t& flip_value) {
+  /* Validate the file stream */
+  valid_file_stream(fp);
+
+  /* Config_done signal: indicate when configuration is finished */
+  fp << "initial" << std::endl;
+  fp << "\tbegin" << std::endl;
+  fp << "\t";
+  std::vector<size_t> initial_values(port.get_width(), initial_value);
+  fp << "\t";
+  fp << generate_verilog_port_constant_values(port, initial_values);
+  fp << ";" << std::endl;
+  
+  /* if flip_value is the same as initial value, we do not need to flip the signal ! */
+  if (flip_value != initial_value) {
+    fp << "\t" << "#" << std::setprecision(10) << pulse_width;
+    std::vector<size_t> port_flip_values(port.get_width(), flip_value);
+    fp << "\t";
+    fp << generate_verilog_port_constant_values(port, port_flip_values);
+    fp << ";" << std::endl;
+  }
+
+  fp << "\tend" << std::endl;
+
+  /* Print an empty line as splitter */
+  fp << std::endl;
+}
+
+/********************************************************************
+ * Print stimuli for a pulse generation
+ * This function supports multiple signal switching under different pulse width
+ *
+ *                 |<-- wait condition -->|
+ *                                        |<--- pulse width --->|
+ *                                                              +------ flip_values
+ *                                                              |      
+ *  initial_value -------  ...  --------------------------------+       
+ *
+ *******************************************************************/
+void print_verilog_pulse_stimuli(std::fstream& fp, 
+                                 const BasicPort& port,
+                                 const size_t& initial_value,
+                                 const std::vector<float>& pulse_widths,
+                                 const std::vector<size_t>& flip_values,
+                                 const std::string& wait_condition) {
+  /* Validate the file stream */
+  valid_file_stream(fp);
+
+  /* Config_done signal: indicate when configuration is finished */
+  fp << "initial" << std::endl;
+  fp << "\tbegin" << std::endl;
+  fp << "\t";
+  std::vector<size_t> initial_values(port.get_width(), initial_value);
+  fp << "\t";
+  fp << generate_verilog_port_constant_values(port, initial_values);
+  fp << ";" << std::endl;
+
+  /* Set a wait condition if specified */
+  if (false == wait_condition.empty()) {
+    fp << "\twait(" << wait_condition << ")" << std::endl;
+  }
+  
+  /* Number of flip conditions and values should match */
+  VTR_ASSERT(flip_values.size() == pulse_widths.size());
+  for (size_t ipulse = 0; ipulse < pulse_widths.size(); ++ipulse) {
+    fp << "\t" << "#" << std::setprecision(10) << pulse_widths[ipulse];
+    std::vector<size_t> port_flip_value(port.get_width(), flip_values[ipulse]);
+    fp << "\t";
+    fp << generate_verilog_port_constant_values(port, port_flip_value);
+    fp << ";" << std::endl;
+  }
+
+  fp << "\tend" << std::endl;
+
+  /* Print an empty line as splitter */
+  fp << std::endl;
+}
+
+/********************************************************************
+ * Print stimuli for a clock signal
+ * This function can support if the clock signal should wait for a period
+ * of time and then start 
+ *                          pulse width
+ *                           |<----->|
+ *                           +-------+       +-------+
+ *                           |       |       |       |
+ *  initial_value --- ... ---+       +-------+       +------ ...
+ *           |<--wait_condition-->|
+ *
+ *******************************************************************/
+void print_verilog_clock_stimuli(std::fstream& fp, 
+                                 const BasicPort& port,
+                                 const size_t& initial_value,
+                                 const float& pulse_width,
+                                 const std::string& wait_condition) {
+  /* Validate the file stream */
+  valid_file_stream(fp);
+
+  /* Config_done signal: indicate when configuration is finished */
+  fp << "initial" << std::endl;
+  fp << "\tbegin" << std::endl;
+
+  std::vector<size_t> initial_values(port.get_width(), initial_value);
+  fp << "\t\t";
+  fp << generate_verilog_port_constant_values(port, initial_values);
+  fp << ";" << std::endl;
+
+  fp << "\tend" << std::endl;
+  fp << "always";
+
+  /* Set a wait condition if specified */
+  if (true == wait_condition.empty()) {
+    fp << std::endl;
+  } else {
+    fp << " wait(" << wait_condition << ")" << std::endl;
+  }
+
+  fp << "\tbegin" << std::endl;
+  fp << "\t\t" << "#" << std::setprecision(10) << pulse_width;
+
+  fp << "\t";
+  fp << generate_verilog_port(VERILOG_PORT_CONKT, port);
+  fp << " = ";
+  fp << "~";
+  fp << generate_verilog_port(VERILOG_PORT_CONKT, port);
+  fp << ";" << std::endl;
+
+  fp << "\tend" << std::endl;
+
+  /* Print an empty line as splitter */
+  fp << std::endl;
+}
+
+/********************************************************************
+ * Output a header file that includes a number of Verilog netlists
+ * so that it can be easily included in a top-level netlist
+ ********************************************************************/
+void print_verilog_netlist_include_header_file(const std::vector<std::string>& netlists_to_be_included,
+                                               const char* subckt_dir,
+                                               const char* header_file_name) {
+  std::string verilog_fname(std::string(subckt_dir) + std::string(header_file_name));
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
+
+  valid_file_stream(fp);
+
+  /* Generate the descriptions*/
+  print_verilog_file_header(fp, "Header file to include other Verilog netlists"); 
+
+  /* Output file names */
+  for (const std::string& netlist_name : netlists_to_be_included) {
+    fp << "`include \"" << netlist_name << "\"" << std::endl;
+  }
+
+  /* close file stream */
+  fp.close();
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_verilog/verilog_writer_utils.h b/openfpga/src/fpga_verilog/verilog_writer_utils.h
new file mode 100644
index 000000000..b145d8be6
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_writer_utils.h
@@ -0,0 +1,187 @@
+/************************************************
+ * Header file for verilog_writer_utils.cpp
+ * Include function declaration for most frequently
+ * used Verilog writers 
+ ***********************************************/
+#ifndef VERILOG_WRITER_UTILS_H 
+#define VERILOG_WRITER_UTILS_H 
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <fstream>
+#include <vector>
+#include <string>
+#include "openfpga_port.h"
+#include "verilog_port_types.h"
+#include "module_manager.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/* Tips: for naming your function in this header/source file
+ * If a function outputs to a file, its name should begin with "print_verilog"
+ * If a function creates a string without outputting to a file, its name should begin with "generate_verilog"
+ * Please show respect to this naming convention, in order to keep a clean header/source file
+ * as well maintain a easy way to identify the functions
+ */
+
+void print_verilog_file_header(std::fstream& fp,
+                               const std::string& usage);
+
+void print_verilog_include_netlist(std::fstream& fp, 
+                                   const std::string& netlist_name);
+
+void print_verilog_define_flag(std::fstream& fp, 
+                               const std::string& flag_name,
+                               const int& flag_value);
+
+void print_verilog_include_defines_preproc_file(std::fstream& fp, 
+                                                const std::string& verilog_dir);
+
+void print_verilog_comment(std::fstream& fp, 
+                           const std::string& comment);
+
+void print_verilog_preprocessing_flag(std::fstream& fp,
+                                      const std::string& preproc_flag);
+
+void print_verilog_endif(std::fstream& fp);
+
+void print_verilog_module_definition(std::fstream& fp, 
+                                     const ModuleManager& module_manager, const ModuleId& module_id);
+
+void print_verilog_module_ports(std::fstream& fp, 
+                                const ModuleManager& module_manager, const ModuleId& module_id);
+
+void print_verilog_module_declaration(std::fstream& fp, 
+                                      const ModuleManager& module_manager, const ModuleId& module_id);
+
+void print_verilog_module_instance(std::fstream& fp, 
+                                   const ModuleManager& module_manager, 
+                                   const ModuleId& module_id,
+                                   const std::string& instance_name,
+                                   const std::map<std::string, BasicPort>& port2port_name_map,
+                                   const bool& use_explicit_port_map);
+
+void print_verilog_module_instance(std::fstream& fp, 
+                                   const ModuleManager& module_manager,
+                                   const ModuleId& parent_module_id, const ModuleId& child_module_id,
+                                   const std::map<std::string, BasicPort>& port2port_name_map,
+                                   const bool& use_explicit_port_map);
+
+void print_verilog_module_end(std::fstream& fp, 
+                              const std::string& module_name);
+
+std::string generate_verilog_port(const enum e_dump_verilog_port_type& dump_port_type,
+                                  const BasicPort& port_info);
+
+bool two_verilog_ports_mergeable(const BasicPort& portA,
+                                 const BasicPort& portB);
+
+BasicPort merge_two_verilog_ports(const BasicPort& portA,
+                                  const BasicPort& portB);
+
+std::vector<BasicPort> combine_verilog_ports(const std::vector<BasicPort>& ports); 
+
+std::string generate_verilog_ports(const std::vector<BasicPort>& merged_ports); 
+
+BasicPort generate_verilog_bus_port(const std::vector<BasicPort>& input_ports, 
+                                    const std::string& bus_port_name);
+
+std::string generate_verilog_local_wire(const BasicPort& output_port,
+                                        const std::vector<BasicPort>& input_ports);
+
+std::string generate_verilog_constant_values(const std::vector<size_t>& const_values);
+
+std::string generate_verilog_port_constant_values(const BasicPort& output_port,
+                                                  const std::vector<size_t>& const_values);
+
+void print_verilog_wire_constant_values(std::fstream& fp,
+                                        const BasicPort& output_port,
+                                        const std::vector<size_t>& const_values);
+
+void print_verilog_deposit_wire_constant_values(std::fstream& fp,
+                                                const BasicPort& output_port,
+                                                const std::vector<size_t>& const_values);
+
+void print_verilog_force_wire_constant_values(std::fstream& fp,
+                                              const BasicPort& output_port,
+                                              const std::vector<size_t>& const_values);
+
+void print_verilog_wire_connection(std::fstream& fp,
+                                   const BasicPort& output_port,
+                                   const BasicPort& input_port,
+                                   const bool& inverted);
+
+void print_verilog_register_connection(std::fstream& fp,
+                                       const BasicPort& output_port,
+                                       const BasicPort& input_port, 
+                                       const bool& inverted);
+
+void print_verilog_buffer_instance(std::fstream& fp,
+                                   ModuleManager& module_manager, 
+                                   const CircuitLibrary& circuit_lib, 
+                                   const ModuleId& parent_module_id, 
+                                   const CircuitModelId& buffer_model, 
+                                   const BasicPort& instance_input_port,
+                                   const BasicPort& instance_output_port);
+
+void print_verilog_local_sram_wires(std::fstream& fp,
+                                    const CircuitLibrary& circuit_lib,
+                                    const CircuitModelId& sram_model,
+                                    const e_config_protocol_type sram_orgz_type,
+                                    const size_t& port_size);
+
+void print_verilog_local_config_bus(std::fstream& fp, 
+                                    const std::string& prefix,
+                                    const e_config_protocol_type& sram_orgz_type,
+                                    const size_t& instance_id,
+                                    const size_t& num_conf_bits); 
+
+void print_verilog_mux_config_bus(std::fstream& fp, 
+                                  const CircuitLibrary& circuit_lib,
+                                  const CircuitModelId& mux_model,
+                                  const e_config_protocol_type& sram_orgz_type,
+                                  const size_t& mux_size,
+                                  const size_t& mux_instance_id,
+                                  const size_t& num_reserved_conf_bits, 
+                                  const size_t& num_conf_bits); 
+
+void print_verilog_formal_verification_mux_sram_ports_wiring(std::fstream& fp, 
+                                                             const CircuitLibrary& circuit_lib,
+                                                             const CircuitModelId& mux_model,
+                                                             const size_t& mux_size,
+                                                             const size_t& mux_instance_id,
+                                                             const size_t& num_conf_bits, 
+                                                             const BasicPort& fm_config_bus); 
+
+void print_verilog_pulse_stimuli(std::fstream& fp, 
+                                 const BasicPort& port,
+                                 const size_t& initial_value,
+                                 const float& pulse_width,
+                                 const size_t& flip_value);
+
+void print_verilog_pulse_stimuli(std::fstream& fp, 
+                                 const BasicPort& port,
+                                 const size_t& initial_value,
+                                 const std::vector<float>& pulse_widths,
+                                 const std::vector<size_t>& flip_values,
+                                 const std::string& wait_condition);
+
+void print_verilog_clock_stimuli(std::fstream& fp, 
+                                 const BasicPort& port,
+                                 const size_t& initial_value,
+                                 const float& pulse_width,
+                                 const std::string& wait_condition);
+
+void print_verilog_netlist_include_header_file(const std::vector<std::string>& netlists_to_be_included,
+                                               const char* subckt_dir,
+                                               const char* header_file_name);
+
+} /* end namespace openfpga */
+
+#endif

From 4cb61e2138b74ac840f4f934c64e5d0d5393cc11 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 16 Feb 2020 00:03:24 -0700
Subject: [PATCH 149/645] bring preprocessing flag Verilog netlists online

---
 openfpga/src/fpga_verilog/verilog_api.cpp     |   9 +-
 .../verilog_auxiliary_netlists.cpp            | 200 ++++++++++++++++++
 .../fpga_verilog/verilog_auxiliary_netlists.h |  31 +++
 openfpga/src/fpga_verilog/verilog_constants.h |   8 +-
 openfpga/src/fpga_verilog/verilog_options.cpp |  28 +++
 openfpga/src/fpga_verilog/verilog_options.h   |  11 +
 6 files changed, 281 insertions(+), 6 deletions(-)
 create mode 100644 openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
 create mode 100644 openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h

diff --git a/openfpga/src/fpga_verilog/verilog_api.cpp b/openfpga/src/fpga_verilog/verilog_api.cpp
index d8dd8dab8..71ec0708d 100644
--- a/openfpga/src/fpga_verilog/verilog_api.cpp
+++ b/openfpga/src/fpga_verilog/verilog_api.cpp
@@ -14,6 +14,7 @@
 
 #include "device_rr_gsb.h"
 #include "verilog_constants.h"
+#include "verilog_auxiliary_netlists.h"
 //#include "verilog_submodules.h"
 //#include "verilog_routing.h"
 //#include "verilog_submodules.h"
@@ -67,11 +68,11 @@ void fpga_fabric_verilog(const ModuleManager& module_manager,
   create_dir_path(rr_dir_path.c_str());
 
   /* Print Verilog files containing preprocessing flags */
-  //print_verilog_preprocessing_flags_netlist(std::string(src_dir_path),
-  //                                          vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts);
+  print_verilog_preprocessing_flags_netlist(std::string(src_dir_path),
+                                            options);
 
-  //print_verilog_simulation_preprocessing_flags(std::string(src_dir_path),
-  //                                             vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts);
+  print_verilog_simulation_preprocessing_flags(std::string(src_dir_path),
+                                               options);
 
   /* Generate primitive Verilog modules, which are corner stones of FPGA fabric
    * Note that this function MUST be called before Verilog generation of
diff --git a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
new file mode 100644
index 000000000..f1a12798d
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
@@ -0,0 +1,200 @@
+/********************************************************************
+ * This file includes functions that are used to generate Verilog files
+ * or code blocks, with a focus on 
+ * `include user-defined or auto-generated netlists in Verilog format
+ *******************************************************************/
+#include <fstream>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_digest.h"
+
+#include "openfpga_naming.h"
+#include "circuit_library_utils.h"
+#include "verilog_constants.h"
+#include "verilog_writer_utils.h"
+#include "verilog_auxiliary_netlists.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Local constant variables
+ *******************************************************************/
+constexpr char* TOP_INCLUDE_NETLIST_FILE_NAME_POSTFIX = "_include_netlists.v";
+
+/********************************************************************
+ * Print a file that includes all the netlists that have been generated
+ * and user-defined.
+ * Some netlists are open to compile under specific preprocessing flags
+ *******************************************************************/
+void print_include_netlists(const std::string& src_dir,
+                            const std::string& circuit_name,
+                            const std::string& reference_benchmark_file,
+                            const CircuitLibrary& circuit_lib) {
+  std::string verilog_fname = src_dir + circuit_name + std::string(TOP_INCLUDE_NETLIST_FILE_NAME_POSTFIX);
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
+
+  /* Validate the file stream */
+  check_file_stream(verilog_fname.c_str(), fp);
+
+  /* Print the title */
+  print_verilog_file_header(fp, std::string("Netlist Summary")); 
+
+  /* Print preprocessing flags */
+  print_verilog_comment(fp, std::string("------ Include defines: preproc flags -----"));
+  print_verilog_include_netlist(fp, std::string(src_dir + std::string(DEFINES_VERILOG_FILE_NAME)));
+  fp << std::endl;
+
+  print_verilog_comment(fp, std::string("------ Include simulation defines -----"));
+  print_verilog_include_netlist(fp, src_dir + std::string(DEFINES_VERILOG_SIMULATION_FILE_NAME));
+  fp << std::endl;
+
+  /* Include all the user-defined netlists */
+  for (const std::string& user_defined_netlist : find_circuit_library_unique_verilog_netlists(circuit_lib)) {
+    print_verilog_include_netlist(fp, user_defined_netlist);
+  }
+
+  /* Include all the primitive modules */
+  print_verilog_include_netlist(fp, src_dir + std::string(DEFAULT_SUBMODULE_DIR_NAME) + std::string(SUBMODULE_VERILOG_FILE_NAME));
+  fp << std::endl;
+
+  /* Include all the CLB, heterogeneous block modules */
+  print_verilog_include_netlist(fp, src_dir  + std::string(DEFAULT_LB_DIR_NAME) + std::string(LOGIC_BLOCK_VERILOG_FILE_NAME));
+  fp << std::endl;
+
+  /* Include all the routing architecture modules */
+  print_verilog_include_netlist(fp, src_dir + std::string(DEFAULT_RR_DIR_NAME) + std::string(ROUTING_VERILOG_FILE_NAME));
+  fp << std::endl;
+
+  /* Include FPGA top module */
+  print_verilog_include_netlist(fp, src_dir + generate_fpga_top_netlist_name(std::string(VERILOG_NETLIST_FILE_POSTFIX)));
+  fp << std::endl;
+
+  /* Include reference benchmark netlist only when auto-check flag is enabled */
+  print_verilog_preprocessing_flag(fp, std::string(AUTOCHECKED_SIMULATION_FLAG));
+  fp << "\t";
+  print_verilog_include_netlist(fp, std::string(reference_benchmark_file));
+  print_verilog_endif(fp);
+  fp << std::endl;
+
+  /* Include formal verification netlists only when formal verification flag is enable */
+  print_verilog_preprocessing_flag(fp, std::string(VERILOG_FORMAL_VERIFICATION_PREPROC_FLAG));
+  fp << "\t";
+  print_verilog_include_netlist(fp, src_dir + circuit_name + std::string(FORMAL_VERIFICATION_VERILOG_FILE_POSTFIX));
+  
+  /* Include formal verification testbench only when formal simulation flag is enabled */
+  fp << "\t";
+  print_verilog_preprocessing_flag(fp, std::string(FORMAL_SIMULATION_FLAG));
+  fp << "\t\t";
+  print_verilog_include_netlist(fp, src_dir + circuit_name + std::string(RANDOM_TOP_TESTBENCH_VERILOG_FILE_POSTFIX));
+  fp << "\t";
+  print_verilog_endif(fp);
+  
+  print_verilog_endif(fp);
+  fp << std::endl;
+
+  /* Include top-level testbench only when auto-check flag is enabled */
+  print_verilog_preprocessing_flag(fp, std::string(AUTOCHECKED_SIMULATION_FLAG));
+  fp << "\t";
+  print_verilog_include_netlist(fp, src_dir + circuit_name + std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_FILE_POSTFIX));
+  print_verilog_endif(fp);
+  fp << std::endl;
+
+  /* Close the file stream */
+  fp.close();
+}
+
+/********************************************************************
+ * Print a Verilog file containing preprocessing flags
+ * which are used enable/disable some features in FPGA Verilog modules
+ *******************************************************************/
+void print_verilog_preprocessing_flags_netlist(const std::string& src_dir,
+                                               const FabricVerilogOption& fpga_verilog_opts) {
+
+  std::string verilog_fname = src_dir + std::string(DEFINES_VERILOG_FILE_NAME);
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
+
+  /* Validate the file stream */
+  check_file_stream(verilog_fname.c_str(), fp);
+
+  /* Print the title */
+  print_verilog_file_header(fp, std::string("Preprocessing flags to enable/disable features in FPGA Verilog modules")); 
+
+  /* To enable timing */
+  if (true == fpga_verilog_opts.include_timing()) {
+    print_verilog_define_flag(fp, std::string(VERILOG_TIMING_PREPROC_FLAG), 1);
+    fp << std::endl;
+  } 
+
+  /* To enable timing */
+  if (true == fpga_verilog_opts.include_signal_init()) {
+    print_verilog_define_flag(fp, std::string(VERILOG_SIGNAL_INIT_PREPROC_FLAG), 1);
+    fp << std::endl;
+  } 
+
+  /* To enable formal verfication flag */
+  if (true == fpga_verilog_opts.print_formal_verification_top_netlist()) {
+    print_verilog_define_flag(fp, std::string(VERILOG_FORMAL_VERIFICATION_PREPROC_FLAG), 1);
+    fp << std::endl;
+  } 
+
+  /* To enable functional verfication with Icarus */
+  if (true == fpga_verilog_opts.support_icarus_simulator()) {
+    print_verilog_define_flag(fp, std::string(ICARUS_SIMULATOR_FLAG), 1);
+    fp << std::endl;
+  } 
+
+  /* Close the file stream */
+  fp.close();
+}
+
+/********************************************************************
+ * Print a Verilog file containing simulation-related preprocessing flags
+ *******************************************************************/
+void print_verilog_simulation_preprocessing_flags(const std::string& src_dir,
+                                                  const FabricVerilogOption& fpga_verilog_opts) {
+
+  std::string verilog_fname = src_dir + std::string(DEFINES_VERILOG_SIMULATION_FILE_NAME);
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
+
+  /* Validate the file stream */
+  check_file_stream(verilog_fname.c_str(), fp);
+
+  /* Print the title */
+  print_verilog_file_header(fp, std::string("Preprocessing flags to enable/disable simulation features")); 
+
+  /* To enable manualy checked simulation */
+  if (true == fpga_verilog_opts.print_top_testbench()) {
+    print_verilog_define_flag(fp, std::string(INITIAL_SIMULATION_FLAG), 1);
+    fp << std::endl;
+  } 
+
+  /* To enable auto-checked simulation */
+  if (true == fpga_verilog_opts.print_autocheck_top_testbench()) {
+    print_verilog_define_flag(fp, std::string(AUTOCHECKED_SIMULATION_FLAG), 1);
+    fp << std::endl;
+  } 
+
+  /* To enable pre-configured FPGA simulation */
+  if (true == fpga_verilog_opts.print_formal_verification_top_netlist()) {
+    print_verilog_define_flag(fp, std::string(FORMAL_SIMULATION_FLAG), 1);
+    fp << std::endl;
+  } 
+
+  /* Close the file stream */
+  fp.close();
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h
new file mode 100644
index 000000000..42f3b0042
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h
@@ -0,0 +1,31 @@
+#ifndef VERILOG_AUXILIARY_NETLISTS_H
+#define VERILOG_AUXILIARY_NETLISTS_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <string>
+#include "circuit_library.h"
+#include "verilog_options.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void print_include_netlists(const std::string& src_dir,
+                            const std::string& circuit_name,
+                            const std::string& reference_benchmark_file,
+                            const CircuitLibrary& circuit_lib);
+
+void print_verilog_preprocessing_flags_netlist(const std::string& src_dir,
+                                               const FabricVerilogOption& fpga_verilog_opts);
+
+void print_verilog_simulation_preprocessing_flags(const std::string& src_dir,
+                                                  const FabricVerilogOption& fpga_verilog_opts);
+
+} /* end namespace openfpga */
+
+#endif 
diff --git a/openfpga/src/fpga_verilog/verilog_constants.h b/openfpga/src/fpga_verilog/verilog_constants.h
index 10a6c0669..9562bd730 100644
--- a/openfpga/src/fpga_verilog/verilog_constants.h
+++ b/openfpga/src/fpga_verilog/verilog_constants.h
@@ -8,7 +8,7 @@ constexpr float VERILOG_SIM_TIMESCALE = 1e-9; // Verilog Simulation time scale (
 
 constexpr char* VERILOG_TIMING_PREPROC_FLAG = "ENABLE_TIMING"; // the flag to enable timing definition during compilation
 constexpr char* VERILOG_SIGNAL_INIT_PREPROC_FLAG = "ENABLE_SIGNAL_INITIALIZATION"; // the flag to enable signal initialization during compilation
-constexpr char* VERILOG_FORMAL_VERIFICATGION_PREPROC_FLAG = "ENABLE_FORMAL_VERIFICATION"; // the flag to enable formal verification during compilation
+constexpr char* VERILOG_FORMAL_VERIFICATION_PREPROC_FLAG = "ENABLE_FORMAL_VERIFICATION"; // the flag to enable formal verification during compilation
 constexpr char* INITIAL_SIMULATION_FLAG = "INITIAL_SIMULATION"; // the flag to enable initial functional verification
 constexpr char* AUTOCHECKED_SIMULATION_FLAG = "AUTOCHECKED_SIMULATION"; // the flag to enable autochecked functional verification
 constexpr char* FORMAL_SIMULATION_FLAG = "FORMAL_SIMULATION"; // the flag to enable formal functional verification
@@ -19,10 +19,14 @@ constexpr char* DEFAULT_SUBMODULE_DIR_NAME = "sub_module/";
 constexpr char* MODELSIM_SIMULATION_TIME_UNIT = "ms";
 
 // Icarus variables and flag
-constexpr char* ICARUS_SIMULATION_FLAG = "ICARUS_SIMULATOR"; // the flag to enable specific Verilog code in testbenches
+constexpr char* ICARUS_SIMULATOR_FLAG = "ICARUS_SIMULATOR"; // the flag to enable specific Verilog code in testbenches
 // End of Icarus variables and flag
 
 constexpr char* VERILOG_TOP_POSTFIX = "_top.v";
+constexpr char* FORMAL_VERIFICATION_VERILOG_FILE_POSTFIX = "_top_formal_verification.v"; 
+constexpr char* TOP_TESTBENCH_VERILOG_FILE_POSTFIX = "_top_tb.v"; /* !!! must be consist with the modelsim_testbench_module_postfix */ 
+constexpr char* AUTOCHECK_TOP_TESTBENCH_VERILOG_FILE_POSTFIX = "_autocheck_top_tb.v"; /* !!! must be consist with the modelsim_autocheck_testbench_module_postfix */ 
+constexpr char* RANDOM_TOP_TESTBENCH_VERILOG_FILE_POSTFIX = "_formal_random_top_tb.v"; 
 constexpr char* DEFINES_VERILOG_FILE_NAME = "fpga_defines.v";
 constexpr char* DEFINES_VERILOG_SIMULATION_FILE_NAME = "define_simulation.v";
 constexpr char* SUBMODULE_VERILOG_FILE_NAME = "sub_module.v";
diff --git a/openfpga/src/fpga_verilog/verilog_options.cpp b/openfpga/src/fpga_verilog/verilog_options.cpp
index a0dfd7e2a..2539d5e51 100644
--- a/openfpga/src/fpga_verilog/verilog_options.cpp
+++ b/openfpga/src/fpga_verilog/verilog_options.cpp
@@ -35,6 +35,22 @@ bool FabricVerilogOption::compress_routing() const {
   return compress_routing_;
 }
 
+bool FabricVerilogOption::print_top_testbench() const {
+  return print_top_testbench_;
+}
+
+bool FabricVerilogOption::print_formal_verification_top_netlist() const {
+  return print_formal_verification_top_netlist_;
+}
+
+bool FabricVerilogOption::print_autocheck_top_testbench() const {
+  return false == reference_verilog_file_path_.empty();
+}
+
+std::string FabricVerilogOption::reference_verilog_file_path() const {
+  return reference_verilog_file_path_;
+}
+
 bool FabricVerilogOption::verbose_output() const {
   return verbose_output_;
 }
@@ -66,6 +82,18 @@ void FabricVerilogOption::set_compress_routing(const bool& enabled) {
   compress_routing_ = enabled;
 }
 
+void FabricVerilogOption::set_print_top_testbench(const bool& enabled) {
+  print_top_testbench_ = enabled;
+}
+
+void FabricVerilogOption::set_print_formal_verification_top_netlist(const bool& enabled) {
+  print_formal_verification_top_netlist_ = enabled;
+}
+
+void FabricVerilogOption::set_print_autocheck_top_testbench(const std::string& reference_verilog_file_path) {
+  reference_verilog_file_path_ = reference_verilog_file_path;
+}
+
 void FabricVerilogOption::set_verbose_output(const bool& enabled) {
   verbose_output_ = enabled;
 }
diff --git a/openfpga/src/fpga_verilog/verilog_options.h b/openfpga/src/fpga_verilog/verilog_options.h
index 336ec542a..182cabcf2 100644
--- a/openfpga/src/fpga_verilog/verilog_options.h
+++ b/openfpga/src/fpga_verilog/verilog_options.h
@@ -24,6 +24,10 @@ class FabricVerilogOption {
     bool include_signal_init() const;
     bool explicit_port_mapping() const;
     bool compress_routing() const;
+    bool print_top_testbench() const;
+    bool print_formal_verification_top_netlist() const;
+    bool print_autocheck_top_testbench() const;
+    std::string reference_verilog_file_path() const;
     bool verbose_output() const;
   public: /* Public mutators */
     void set_output_directory(const std::string& output_dir);
@@ -32,6 +36,9 @@ class FabricVerilogOption {
     void set_include_signal_init(const bool& enabled);
     void set_explicit_port_mapping(const bool& enabled);
     void set_compress_routing(const bool& enabled);
+    void set_print_top_testbench(const bool& enabled);
+    void set_print_formal_verification_top_netlist(const bool& enabled);
+    void set_print_autocheck_top_testbench(const std::string& reference_verilog_file_path);
     void set_verbose_output(const bool& enabled);
   private: /* Internal Data */
     std::string output_directory_;
@@ -40,6 +47,10 @@ class FabricVerilogOption {
     bool include_timing_;
     bool explicit_port_mapping_;
     bool compress_routing_;
+    bool print_top_testbench_;
+    bool print_formal_verification_top_netlist_;
+    /* print_autocheck_top_testbench will be enabled when reference file path is not empty */
+    std::string reference_verilog_file_path_;
     bool verbose_output_;
 };
 

From 2eba8823320ad8c74de0816f8dade1c39289d67c Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 16 Feb 2020 11:41:20 -0700
Subject: [PATCH 150/645] put verilog submodules online. ready to bring the how
 submodule writer online

---
 .../fpga_verilog/verilog_submodule_utils.cpp  | 243 ++++++++++++++++++
 .../fpga_verilog/verilog_submodule_utils.h    |  37 +++
 .../src/fpga_verilog/verilog_writer_utils.cpp |  48 ++--
 3 files changed, 304 insertions(+), 24 deletions(-)
 create mode 100644 openfpga/src/fpga_verilog/verilog_submodule_utils.cpp
 create mode 100644 openfpga/src/fpga_verilog/verilog_submodule_utils.h

diff --git a/openfpga/src/fpga_verilog/verilog_submodule_utils.cpp b/openfpga/src/fpga_verilog/verilog_submodule_utils.cpp
new file mode 100644
index 000000000..f4f02472d
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_submodule_utils.cpp
@@ -0,0 +1,243 @@
+/************************************************
+ * This file includes most utilized functions for 
+ * generating Verilog sub-modules
+ * such as timing matrix and signal initialization
+ ***********************************************/
+#include <fstream>
+#include <limits>
+#include <iomanip>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_port.h"
+#include "openfpga_digest.h"
+
+/* Headers from readarchopenfpga library */
+#include "circuit_types.h"
+
+#include "module_manager_utils.h"
+#include "verilog_constants.h"
+#include "verilog_writer_utils.h"
+#include "verilog_submodule_utils.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/* All values are printed with this precision value. The higher the
+ * value, the more accurate timing assignment is. Using a number of 6
+ * guarentees that a precision of femtosecond which is sufficent for 
+ * electrical simulation (simulation timescale is 10-9 
+ */
+/* constexpr int FLOAT_PRECISION = std::numeric_limits<float>::max_digits10; */
+constexpr int FLOAT_PRECISION = 6; 
+
+/************************************************
+ * Print a timing matrix defined in theecircuit model
+ * into a Verilog format. 
+ * This function print all the timing edges available
+ * in the circuit model (any pin-to-pin delay)
+ ***********************************************/
+void print_verilog_submodule_timing(std::fstream& fp, 
+                                    const CircuitLibrary& circuit_lib,
+                                    const CircuitModelId& circuit_model) {
+  /* return if there is no delay info */
+  if ( 0 == circuit_lib.num_delay_info(circuit_model)) {
+    return;
+  }
+
+  /* Return if there is no ports */
+  if (0 == circuit_lib.num_model_ports(circuit_model)) {
+    return;
+  }
+
+  /* Ensure a valid file handler*/
+  VTR_ASSERT(true == valid_file_stream(fp));
+
+  fp << std::endl;
+  fp << "`ifdef " << VERILOG_TIMING_PREPROC_FLAG << std::endl;
+  print_verilog_comment(fp, std::string("------ BEGIN Pin-to-pin Timing constraints -----"));
+  fp << "\tspecify" << std::endl;
+
+  /* Read out pin-to-pin delays by finding out all the edges belonging to a circuit model */
+  for (const auto& timing_edge : circuit_lib.timing_edges_by_model(circuit_model)) {
+     CircuitPortId src_port = circuit_lib.timing_edge_src_port(timing_edge);
+     size_t src_pin = circuit_lib.timing_edge_src_pin(timing_edge);
+     BasicPort src_port_info(circuit_lib.port_lib_name(src_port), src_pin, src_pin); 
+
+     CircuitPortId sink_port = circuit_lib.timing_edge_sink_port(timing_edge);
+     size_t sink_pin = circuit_lib.timing_edge_sink_pin(timing_edge);
+     BasicPort sink_port_info(circuit_lib.port_lib_name(sink_port), sink_pin, sink_pin); 
+   
+     fp << "\t\t";
+     fp << "(" << generate_verilog_port(VERILOG_PORT_CONKT, src_port_info);
+     fp << " => ";
+     fp << generate_verilog_port(VERILOG_PORT_CONKT, sink_port_info) << ")";
+     fp << " = ";
+     fp << "(" << std::setprecision(FLOAT_PRECISION) << circuit_lib.timing_edge_delay(timing_edge, CIRCUIT_MODEL_DELAY_RISE) / VERILOG_SIM_TIMESCALE;
+     fp << ", ";
+     fp << std::setprecision(FLOAT_PRECISION) << circuit_lib.timing_edge_delay(timing_edge, CIRCUIT_MODEL_DELAY_FALL) / VERILOG_SIM_TIMESCALE << ")";
+     fp << ";" << std::endl;
+  }
+
+  fp << "\tendspecify" << std::endl;
+  print_verilog_comment(fp, std::string("------ END Pin-to-pin Timing constraints -----"));
+  fp << "`endif" << std::endl;
+
+}
+
+void print_verilog_submodule_signal_init(std::fstream& fp, 
+                                         const CircuitLibrary& circuit_lib,
+                                         const CircuitModelId& circuit_model) {
+  /* Ensure a valid file handler*/
+  VTR_ASSERT(true == valid_file_stream(fp));
+
+  fp << std::endl;
+  fp << "`ifdef " << VERILOG_SIGNAL_INIT_PREPROC_FLAG << std::endl;
+  print_verilog_comment(fp, std::string("------ BEGIN driver initialization -----"));
+  fp << "\tinitial begin" << std::endl;
+  fp << "\t`ifdef " << VERILOG_FORMAL_VERIFICATION_PREPROC_FLAG << std::endl;
+
+  /* Only for formal verification: deposite a zero signal values */
+  /* Initialize each input port */
+  for (const auto& input_port : circuit_lib.model_input_ports(circuit_model)) {
+    BasicPort input_port_info(circuit_lib.port_lib_name(input_port), circuit_lib.port_size(input_port));
+    fp << "\t\t$deposit(";
+    fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port_info);
+    fp << ", " <<  circuit_lib.port_size(input_port) << "'b" << std::string(circuit_lib.port_size(input_port), '0');
+    fp << ");" << std::endl;
+  }
+  fp << "\t`else" << std::endl;
+
+  /* Regular case: deposite initial signal values: a random value */
+  for (const auto& input_port : circuit_lib.model_input_ports(circuit_model)) {
+    BasicPort input_port_info(circuit_lib.port_lib_name(input_port), circuit_lib.port_size(input_port));
+    fp << "\t\t$deposit(";
+    fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port_info);
+    fp << ", $random);" << std::endl;
+  }
+
+  fp << "\t`endif\n" << std::endl;
+  fp << "\tend" << std::endl;
+  print_verilog_comment(fp, std::string("------ END driver initialization -----"));
+  fp << "`endif" << std::endl;
+}
+
+/*********************************************************************
+ * Register all the user-defined modules in the module manager
+ * Walk through the circuit library and add user-defined circuit models
+ * to the module_manager
+ ********************************************************************/
+void add_user_defined_verilog_modules(ModuleManager& module_manager, 
+                                      const CircuitLibrary& circuit_lib) {
+  /* Iterate over Verilog modules */
+  for (const auto& model : circuit_lib.models()) {
+    /* We only care about user-defined models */
+    if (true == circuit_lib.model_verilog_netlist(model).empty()) {
+      continue;
+    }
+    /* Skip Routing channel wire models because they need a different name. Do it later */
+    if (CIRCUIT_MODEL_CHAN_WIRE == circuit_lib.model_type(model)) {
+      continue;
+    }
+    /* Reach here, the model requires a user-defined Verilog netlist, 
+     * Try to find it in the module manager 
+     * If not found, register it in the module_manager  
+     */
+    ModuleId module_id = module_manager.find_module(circuit_lib.model_name(model));
+    if (ModuleId::INVALID() == module_id) {
+      add_circuit_model_to_module_manager(module_manager, circuit_lib, model);
+    }
+  }
+}
+
+/*********************************************************************
+ * Print a template for a user-defined circuit model
+ * The template will include just the port declaration of the Verilog module
+ * The template aims to help user to write Verilog codes with a guaranteed
+ * module definition, which can be correctly instanciated (with correct
+ * port mapping) in the FPGA fabric
+ ********************************************************************/
+static 
+void print_one_verilog_template_module(const ModuleManager& module_manager,
+                                       std::fstream& fp,
+                                       const std::string& module_name) {
+  /* Ensure a valid file handler*/
+  VTR_ASSERT(true == valid_file_stream(fp));
+
+  print_verilog_comment(fp, std::string("----- Template Verilog module for " + module_name + " -----"));
+
+  /* Find the module in module manager, which should be already registered */
+  /* TODO: routing channel wire model may have a different name! */
+  ModuleId template_module = module_manager.find_module(module_name);
+  VTR_ASSERT(ModuleId::INVALID() != template_module);
+
+  /* dump module definition + ports */
+  print_verilog_module_declaration(fp, module_manager, template_module);
+  /* Finish dumping ports */
+
+  print_verilog_comment(fp, std::string("----- Internal logic should start here -----"));
+
+  /* Add some empty lines as placeholders for the internal logic*/
+  fp << std::endl << std::endl;
+ 
+  print_verilog_comment(fp, std::string("----- Internal logic should end here -----"));
+
+  /* Put an end to the Verilog module */
+  print_verilog_module_end(fp, module_name);
+
+  /* Add an empty line as a splitter */
+  fp << std::endl;
+}
+
+/*********************************************************************
+ * Print a template of all the submodules that are user-defined
+ * The template will include just the port declaration of the submodule
+ * The template aims to help user to write Verilog codes with a guaranteed
+ * module definition, which can be correctly instanciated (with correct
+ * port mapping) in the FPGA fabric
+ ********************************************************************/
+void print_verilog_submodule_templates(const ModuleManager& module_manager,
+                                       const CircuitLibrary& circuit_lib,
+                                       const std::string& verilog_dir,
+                                       const std::string& submodule_dir) {
+  std::string verilog_fname(submodule_dir + USER_DEFINED_TEMPLATE_VERILOG_FILE_NAME);
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
+
+  check_file_stream(verilog_fname.c_str(), fp);
+
+  /* Print out debugging information for if the file is not opened/created properly */
+  VTR_LOG("Creating template for user-defined Verilog modules '%s'...",
+          verilog_fname.c_str()); 
+
+  print_verilog_file_header(fp, "Template for user-defined Verilog modules"); 
+
+  print_verilog_include_defines_preproc_file(fp, verilog_dir);
+
+  /* Output essential models*/
+  for (const auto& model : circuit_lib.models()) {
+    /* Focus on user-defined modules, which must have a Verilog netlist defined */
+    if (circuit_lib.model_verilog_netlist(model).empty()) {
+      continue;
+    }
+    /* Skip Routing channel wire models because they need a different name. Do it later */
+    if (CIRCUIT_MODEL_CHAN_WIRE == circuit_lib.model_type(model)) {
+      continue;
+    }
+    /* Print a Verilog template for the circuit model */
+    print_one_verilog_template_module(module_manager, fp, circuit_lib.model_name(model)); 
+  }
+
+  /* close file stream */
+  fp.close();
+ 
+  /* No need to add the template to the subckt include files! */
+  VTR_LOG("Done\n");
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_verilog/verilog_submodule_utils.h b/openfpga/src/fpga_verilog/verilog_submodule_utils.h
new file mode 100644
index 000000000..fedcb63a8
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_submodule_utils.h
@@ -0,0 +1,37 @@
+#ifndef VERILOG_SUBMODULE_UTILS_H
+#define VERILOG_SUBMODULE_UTILS_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <fstream>
+#include <string>
+#include "module_manager.h"
+#include "circuit_library.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void print_verilog_submodule_timing(std::fstream& fp, 
+                                    const CircuitLibrary& circuit_lib,
+                                    const CircuitModelId& circuit_model);
+
+void print_verilog_submodule_signal_init(std::fstream& fp, 
+                                         const CircuitLibrary& circuit_lib,
+                                         const CircuitModelId& circuit_model);
+
+void add_user_defined_verilog_modules(ModuleManager& module_manager, 
+                                      const CircuitLibrary& circuit_lib);
+
+void print_verilog_submodule_templates(const ModuleManager& module_manager,
+                                       const CircuitLibrary& circuit_lib,
+                                       const std::string& verilog_dir,
+                                       const std::string& submodule_dir);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp
index 5798b05fc..28f2ed5db 100644
--- a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp
+++ b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp
@@ -32,7 +32,7 @@ namespace openfpga {
  ***********************************************/
 void print_verilog_file_header(std::fstream& fp,
                                const std::string& usage) {
-  valid_file_stream(fp);
+  VTR_ASSERT(true == valid_file_stream(fp));
  
   auto end = std::chrono::system_clock::now(); 
   std::time_t end_time = std::chrono::system_clock::to_time_t(end);
@@ -54,7 +54,7 @@ void print_verilog_file_header(std::fstream& fp,
  *******************************************************************/
 void print_verilog_include_netlist(std::fstream& fp, 
                                    const std::string& netlist_name) {
-  valid_file_stream(fp);
+  VTR_ASSERT(true == valid_file_stream(fp));
 
   fp << "`include \"" << netlist_name << "\"" << std::endl; 
 }
@@ -65,7 +65,7 @@ void print_verilog_include_netlist(std::fstream& fp,
 void print_verilog_define_flag(std::fstream& fp, 
                                const std::string& flag_name,
                                const int& flag_value) {
-  valid_file_stream(fp);
+  VTR_ASSERT(true == valid_file_stream(fp));
 
   fp << "`define " << flag_name << " " << flag_value << std::endl; 
 }
@@ -88,7 +88,7 @@ void print_verilog_include_defines_preproc_file(std::fstream& fp,
  ***********************************************/
 void print_verilog_comment(std::fstream& fp, 
                            const std::string& comment) {
-  valid_file_stream(fp);
+  VTR_ASSERT(true == valid_file_stream(fp));
 
   fp << "// " << comment << std::endl;
 }
@@ -98,7 +98,7 @@ void print_verilog_comment(std::fstream& fp,
  ***********************************************/
 void print_verilog_preprocessing_flag(std::fstream& fp,
                                       const std::string& preproc_flag) {
-  valid_file_stream(fp);
+  VTR_ASSERT(true == valid_file_stream(fp));
 
   fp << "`ifdef " << preproc_flag << std::endl;
 }
@@ -107,7 +107,7 @@ void print_verilog_preprocessing_flag(std::fstream& fp,
  * Print the endif of a Verilog preprocessing flag
  ***********************************************/
 void print_verilog_endif(std::fstream& fp) {
-  valid_file_stream(fp);
+  VTR_ASSERT(true == valid_file_stream(fp));
 
   fp << "`endif" << std::endl;
 }
@@ -119,7 +119,7 @@ void print_verilog_endif(std::fstream& fp) {
  ***********************************************/
 void print_verilog_module_definition(std::fstream& fp, 
                                      const ModuleManager& module_manager, const ModuleId& module_id) {
-  valid_file_stream(fp);
+  VTR_ASSERT(true == valid_file_stream(fp));
 
   print_verilog_comment(fp, std::string("----- Verilog module for " + module_manager.module_name(module_id) + " -----"));
 
@@ -183,7 +183,7 @@ void print_verilog_module_definition(std::fstream& fp,
  ***********************************************/
 void print_verilog_module_ports(std::fstream& fp, 
                                 const ModuleManager& module_manager, const ModuleId& module_id) {
-  valid_file_stream(fp);
+  VTR_ASSERT(true == valid_file_stream(fp));
 
   /* port type2type mapping */
   std::map<ModuleManager::e_module_port_type, enum e_dump_verilog_port_type> port_type2type_map;
@@ -292,7 +292,7 @@ void print_verilog_module_ports(std::fstream& fp,
  ***********************************************/
 void print_verilog_module_declaration(std::fstream& fp, 
                                       const ModuleManager& module_manager, const ModuleId& module_id) {
-  valid_file_stream(fp);
+  VTR_ASSERT(true == valid_file_stream(fp));
 
   print_verilog_module_definition(fp, module_manager, module_id);
 
@@ -327,7 +327,7 @@ void print_verilog_module_instance(std::fstream& fp,
                                    const std::map<std::string, BasicPort>& port2port_name_map,
                                    const bool& use_explicit_port_map) {
 
-  valid_file_stream(fp);
+  VTR_ASSERT(true == valid_file_stream(fp));
 
   /* Check: all the key ports in the port2port_name_map does exist in the child module */
   for (const auto& kv : port2port_name_map) {
@@ -418,7 +418,7 @@ void print_verilog_module_instance(std::fstream& fp,
  ***********************************************/
 void print_verilog_module_end(std::fstream& fp, 
                               const std::string& module_name) {
-  valid_file_stream(fp);
+  VTR_ASSERT(true == valid_file_stream(fp));
 
   fp << "endmodule" << std::endl;
   print_verilog_comment(fp, std::string("----- END Verilog module for " + module_name + " -----"));
@@ -672,7 +672,7 @@ void print_verilog_wire_constant_values(std::fstream& fp,
                                         const BasicPort& output_port,
                                         const std::vector<size_t>& const_values) {
   /* Make sure we have a valid file handler*/
-  valid_file_stream(fp);
+  VTR_ASSERT(true == valid_file_stream(fp));
 
   fp << "\t";
   fp << "assign ";
@@ -687,7 +687,7 @@ void print_verilog_deposit_wire_constant_values(std::fstream& fp,
                                                 const BasicPort& output_port,
                                                 const std::vector<size_t>& const_values) {
   /* Make sure we have a valid file handler*/
-  valid_file_stream(fp);
+  VTR_ASSERT(true == valid_file_stream(fp));
 
   fp << "\t";
   fp << "$deposit(";
@@ -705,7 +705,7 @@ void print_verilog_force_wire_constant_values(std::fstream& fp,
                                               const BasicPort& output_port,
                                               const std::vector<size_t>& const_values) {
   /* Make sure we have a valid file handler*/
-  valid_file_stream(fp);
+  VTR_ASSERT(true == valid_file_stream(fp));
 
   fp << "\t";
   fp << "force ";
@@ -722,7 +722,7 @@ void print_verilog_wire_connection(std::fstream& fp,
                                    const BasicPort& input_port, 
                                    const bool& inverted) {
   /* Make sure we have a valid file handler*/
-  valid_file_stream(fp);
+  VTR_ASSERT(true == valid_file_stream(fp));
 
   /* Must check: the port width matches */
   VTR_ASSERT( input_port.get_width() == output_port.get_width() );
@@ -749,7 +749,7 @@ void print_verilog_register_connection(std::fstream& fp,
                                        const BasicPort& input_port, 
                                        const bool& inverted) {
   /* Make sure we have a valid file handler*/
-  valid_file_stream(fp);
+  VTR_ASSERT(true == valid_file_stream(fp));
 
   /* Must check: the port width matches */
   VTR_ASSERT( input_port.get_width() == output_port.get_width() );
@@ -787,7 +787,7 @@ void print_verilog_buffer_instance(std::fstream& fp,
                                    const BasicPort& instance_input_port,
                                    const BasicPort& instance_output_port) {
   /* Make sure we have a valid file handler*/
-  valid_file_stream(fp);
+  VTR_ASSERT(true == valid_file_stream(fp));
 
   /* To match the context, Buffer should have only 2 non-global ports: 1 input port and 1 output port */
   std::vector<CircuitPortId> buffer_model_input_ports = circuit_lib.model_ports_by_type(buffer_model, CIRCUIT_MODEL_PORT_INPUT, true);
@@ -903,7 +903,7 @@ void print_verilog_local_sram_wires(std::fstream& fp,
                                     const e_config_protocol_type sram_orgz_type,
                                     const size_t& port_size) {
   /* Make sure we have a valid file handler*/
-  valid_file_stream(fp);
+  VTR_ASSERT(true == valid_file_stream(fp));
 
   /* Port size must be at least one! */
   if (0 == port_size) {
@@ -1013,7 +1013,7 @@ void print_verilog_local_config_bus(std::fstream& fp,
                                     const size_t& instance_id,
                                     const size_t& num_conf_bits) { 
   /* Make sure we have a valid file handler*/
-  valid_file_stream(fp);
+  VTR_ASSERT(true == valid_file_stream(fp));
 
   switch(sram_orgz_type) {
   case CONFIG_MEM_STANDALONE:
@@ -1081,7 +1081,7 @@ void print_verilog_rram_mux_config_bus(std::fstream& fp,
                                        const size_t& num_reserved_conf_bits, 
                                        const size_t& num_conf_bits) { 
   /* Make sure we have a valid file handler*/
-  valid_file_stream(fp);
+  VTR_ASSERT(true == valid_file_stream(fp));
 
   switch(sram_orgz_type) {
   case CONFIG_MEM_STANDALONE:
@@ -1236,7 +1236,7 @@ void print_verilog_pulse_stimuli(std::fstream& fp,
                                  const float& pulse_width,
                                  const size_t& flip_value) {
   /* Validate the file stream */
-  valid_file_stream(fp);
+  VTR_ASSERT(true == valid_file_stream(fp));
 
   /* Config_done signal: indicate when configuration is finished */
   fp << "initial" << std::endl;
@@ -1280,7 +1280,7 @@ void print_verilog_pulse_stimuli(std::fstream& fp,
                                  const std::vector<size_t>& flip_values,
                                  const std::string& wait_condition) {
   /* Validate the file stream */
-  valid_file_stream(fp);
+  VTR_ASSERT(true == valid_file_stream(fp));
 
   /* Config_done signal: indicate when configuration is finished */
   fp << "initial" << std::endl;
@@ -1330,7 +1330,7 @@ void print_verilog_clock_stimuli(std::fstream& fp,
                                  const float& pulse_width,
                                  const std::string& wait_condition) {
   /* Validate the file stream */
-  valid_file_stream(fp);
+  VTR_ASSERT(true == valid_file_stream(fp));
 
   /* Config_done signal: indicate when configuration is finished */
   fp << "initial" << std::endl;
@@ -1380,7 +1380,7 @@ void print_verilog_netlist_include_header_file(const std::vector<std::string>& n
   std::fstream fp;
   fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
 
-  valid_file_stream(fp);
+  VTR_ASSERT(true == valid_file_stream(fp));
 
   /* Generate the descriptions*/
   print_verilog_file_header(fp, "Header file to include other Verilog netlists"); 

From cf34339e96cfbd20c8f93c5e11c2966dfb9142d9 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 16 Feb 2020 11:57:19 -0700
Subject: [PATCH 151/645] adapt essential gates for submodule generation

---
 .../fpga_verilog/verilog_essential_gates.cpp  | 585 ++++++++++++++++++
 .../fpga_verilog/verilog_essential_gates.h    |  25 +
 2 files changed, 610 insertions(+)
 create mode 100644 openfpga/src/fpga_verilog/verilog_essential_gates.cpp
 create mode 100644 openfpga/src/fpga_verilog/verilog_essential_gates.h

diff --git a/openfpga/src/fpga_verilog/verilog_essential_gates.cpp b/openfpga/src/fpga_verilog/verilog_essential_gates.cpp
new file mode 100644
index 000000000..c18bece61
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_essential_gates.cpp
@@ -0,0 +1,585 @@
+/************************************************
+ * This file includes functions on 
+ * outputting Verilog netlists for essential gates
+ * which are inverters, buffers, transmission-gates
+ * logic gates etc. 
+ ***********************************************/
+#include <fstream>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_port.h"
+#include "openfpga_digest.h"
+
+#include "openfpga_naming.h"
+#include "module_manager.h"
+#include "module_manager_utils.h"
+
+#include "verilog_constants.h"
+#include "verilog_writer_utils.h"
+#include "verilog_submodule_utils.h"
+#include "verilog_essential_gates.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/************************************************
+ * Print Verilog body codes of a power-gated inverter 
+ * This function does NOT generate any port map !
+ ***********************************************/
+static 
+void print_verilog_power_gated_invbuf_body(std::fstream& fp,
+                                           const CircuitLibrary& circuit_lib,
+                                           const CircuitModelId& circuit_model,
+                                           const CircuitPortId& input_port,
+                                           const CircuitPortId& output_port,
+                                           const std::vector<CircuitPortId>& power_gate_ports) {
+  /* Ensure a valid file handler*/
+  VTR_ASSERT(true == valid_file_stream(fp));
+
+  print_verilog_comment(fp, std::string("----- Verilog codes of a power-gated inverter -----"));
+
+  /* Create a sensitive list */
+  fp << "\treg " << circuit_lib.port_prefix(output_port) << "_reg;" << std::endl;
+
+  fp << "\talways @(" << std::endl;
+  /* Power-gate port first*/
+  for (const auto& power_gate_port : power_gate_ports) {
+    /* Skip first comma to dump*/
+    if (0 < &power_gate_port - &power_gate_ports[0]) {
+      fp << ",";
+    }
+    fp << circuit_lib.port_prefix(power_gate_port);
+  }
+  fp << circuit_lib.port_prefix(input_port) << ") begin" << std::endl; 
+
+  /* Dump the case of power-gated */
+  fp << "\t\tif (";
+  /* For the first pin, we skip output comma */
+  size_t port_cnt = 0;
+  for (const auto& power_gate_port : power_gate_ports) {
+    for (const auto& power_gate_pin : circuit_lib.pins(power_gate_port)) {
+      if (0 < port_cnt) { 
+        fp << std::endl << "\t\t&&";
+      }
+      fp << "(";
+
+      /* Power-gated signal are disable during operating, enabled during configuration,
+       * Therefore, we need to reverse them here   
+       */
+      if (0 == circuit_lib.port_default_value(power_gate_port)) {
+        fp << "~";
+      }
+      
+      fp << circuit_lib.port_prefix(power_gate_port) << "[" << power_gate_pin << "])";
+
+      port_cnt++; /* Update port counter*/
+    }
+  }
+
+  fp << ") begin" << std::endl;
+  fp << "\t\t\tassign " << circuit_lib.port_prefix(output_port) << "_reg = "; 
+
+  /* Branch on the type of inverter/buffer: 
+   * 1. If this is an inverter or an tapered(multi-stage) buffer with odd number of stages, 
+   *    we invert the input to output
+   * 2. If this is a buffer or an tapere(multi-stage) buffer with even number of stages,
+   *    we wire the input to output
+   */
+  if ( (CIRCUIT_MODEL_BUF_INV == circuit_lib.buffer_type(circuit_model))
+    || ( (CIRCUIT_MODEL_BUF_BUF == circuit_lib.buffer_type(circuit_model))
+      && (size_t(-1) != circuit_lib.buffer_num_levels(circuit_model)) 
+      && (1 == circuit_lib.buffer_num_levels(circuit_model) % 2 ) ) ) {
+    fp << "~";
+  } 
+
+  fp << circuit_lib.port_prefix(input_port) << ";" << std::endl;
+  fp << "\t\tend else begin" << std::endl;
+  fp << "\t\t\tassign " << circuit_lib.port_prefix(output_port) << "_reg = 1'bz;" << std::endl;
+  fp << "\t\tend" << std::endl;
+  fp << "\tend" << std::endl;
+  fp << "\tassign " << circuit_lib.port_prefix(output_port) << " = " << circuit_lib.port_prefix(output_port) << "_reg;" << std::endl;
+}
+
+/************************************************
+ * Print Verilog body codes of a regular inverter 
+ * This function does NOT generate any port map !
+ ***********************************************/
+static 
+void print_verilog_invbuf_body(std::fstream& fp,
+                               const CircuitLibrary& circuit_lib,
+                               const CircuitModelId& circuit_model,
+                               const CircuitPortId& input_port,
+                               const CircuitPortId& output_port) {
+  /* Ensure a valid file handler*/
+  VTR_ASSERT(true == valid_file_stream(fp));
+
+  print_verilog_comment(fp, std::string("----- Verilog codes of a regular inverter -----"));
+  
+  fp << "\tassign " << circuit_lib.port_prefix(output_port) << " = (" << circuit_lib.port_prefix(input_port) << " === 1'bz)? $random : ";
+
+  /* Branch on the type of inverter/buffer: 
+   * 1. If this is an inverter or an tapered(multi-stage) buffer with odd number of stages, 
+   *    we invert the input to output
+   * 2. If this is a buffer or an tapere(multi-stage) buffer with even number of stages,
+   *    we wire the input to output
+   */
+  if ( (CIRCUIT_MODEL_BUF_INV == circuit_lib.buffer_type(circuit_model))
+    || ( (CIRCUIT_MODEL_BUF_BUF == circuit_lib.buffer_type(circuit_model))
+      && (size_t(-1) != circuit_lib.buffer_num_levels(circuit_model)) 
+      && (1 == circuit_lib.buffer_num_levels(circuit_model) % 2 ) ) ) {
+    fp << "~";
+  } 
+
+  fp << circuit_lib.port_prefix(input_port) << ";" << std::endl;
+}
+
+/************************************************
+ * Print a Verilog module of inverter or buffer 
+ * or tapered buffer to a file 
+ ***********************************************/
+static 
+void print_verilog_invbuf_module(ModuleManager& module_manager, 
+                                 std::fstream& fp,
+                                 const CircuitLibrary& circuit_lib,
+                                 const CircuitModelId& circuit_model) {
+  /* Ensure a valid file handler*/
+  VTR_ASSERT(true == valid_file_stream(fp));
+
+  /* Find the input port, output port and global inputs*/
+  std::vector<CircuitPortId> input_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true);
+  std::vector<CircuitPortId> output_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
+  std::vector<CircuitPortId> global_ports = circuit_lib.model_global_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true, true);
+
+  /* Make sure:
+   * There is only 1 input port and 1 output port, 
+   * each size of which is 1
+   */
+  VTR_ASSERT( (1 == input_ports.size()) && (1 == circuit_lib.port_size(input_ports[0])) );
+  VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) );
+
+  /* TODO: move the check codes to check_circuit_library.h */
+  /* If the circuit model is power-gated, we need to find at least one global config_enable signals */
+  if (true == circuit_lib.is_power_gated(circuit_model)) { 
+    /* Check all the ports we have are good for a power-gated circuit model */
+    size_t num_err = 0;
+    /* We need at least one global port */
+    if (0 == global_ports.size())  {
+      num_err++;
+    }
+    /* All the global ports should be config_enable */
+    for (const auto& port : global_ports) {
+      if (false == circuit_lib.port_is_config_enable(port)) {
+        num_err++;
+      }
+    }
+    /* Report errors if there are any */
+    if (0 < num_err) {
+      VTR_LOGF_ERROR(__FILE__, __LINE__,
+                     "Inverter/buffer circuit model '%s' is power-gated. At least one config-enable global port is required!\n",
+                     circuit_lib.model_name(circuit_model).c_str()); 
+      exit(1);
+    }
+  }
+
+  /* Create a Verilog Module based on the circuit model, and add to module manager */
+  ModuleId module_id = module_manager.find_module(circuit_lib.model_name(circuit_model)); 
+  VTR_ASSERT(true == module_manager.valid_module_id(module_id));
+
+  /* dump module definition + ports */
+  print_verilog_module_declaration(fp, module_manager, module_id);
+  /* Finish dumping ports */
+
+  /* Assign logics : depending on topology */
+  /* Error out for unsupported technology */
+  if ( ( CIRCUIT_MODEL_BUF_INV != circuit_lib.buffer_type(circuit_model))
+    && ( CIRCUIT_MODEL_BUF_BUF != circuit_lib.buffer_type(circuit_model)) ) {
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid topology for circuit model '%s'!\n",
+                   circuit_lib.model_name(circuit_model).c_str());
+    exit(1);
+  }
+
+  if (true == circuit_lib.is_power_gated(circuit_model)) {
+    /* Output Verilog codes for a power-gated inverter */
+    print_verilog_power_gated_invbuf_body(fp, circuit_lib, circuit_model, input_ports[0], output_ports[0], global_ports);
+  } else {
+    /* Output Verilog codes for a regular inverter */
+    print_verilog_invbuf_body(fp, circuit_lib, circuit_model, input_ports[0], output_ports[0]);
+  }
+
+  /* Print timing info */
+  print_verilog_submodule_timing(fp, circuit_lib, circuit_model);
+
+  /* Print signal initialization */
+  print_verilog_submodule_signal_init(fp, circuit_lib, circuit_model);
+
+  /* Put an end to the Verilog module */
+  print_verilog_module_end(fp, circuit_lib.model_name(circuit_model));
+}
+
+/************************************************
+ * Print a Verilog module of a pass-gate,
+ * either transmission-gate or pass-transistor
+ ***********************************************/
+static 
+void print_verilog_passgate_module(ModuleManager& module_manager, 
+                                   std::fstream& fp,
+                                   const CircuitLibrary& circuit_lib,
+                                   const CircuitModelId& circuit_model) {
+  /* Ensure a valid file handler*/
+  VTR_ASSERT(true == valid_file_stream(fp));
+
+  /* Find the input port, output port*/
+  std::vector<CircuitPortId> input_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true);
+  std::vector<CircuitPortId> output_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
+  std::vector<CircuitPortId> global_ports = circuit_lib.model_global_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true, true);
+
+  switch (circuit_lib.pass_gate_logic_type(circuit_model)) {
+  case CIRCUIT_MODEL_PASS_GATE_TRANSMISSION:
+    /* Make sure:
+     * There is only 3 input port (in, sel, selb), 
+     * each size of which is 1
+     */
+    VTR_ASSERT( 3 == input_ports.size() );
+    for (const auto& input_port : input_ports) {
+      VTR_ASSERT(1 == circuit_lib.port_size(input_port));
+    }
+    break;
+  case CIRCUIT_MODEL_PASS_GATE_TRANSISTOR:
+    /* Make sure:
+     * There is only 2 input port (in, sel), 
+     * each size of which is 1
+     */
+    VTR_ASSERT( 2 == input_ports.size() );
+    for (const auto& input_port : input_ports) {
+      VTR_ASSERT(1 == circuit_lib.port_size(input_port));
+    }
+    break;
+  default:
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid topology for circuit model '%s'!\n",
+                   circuit_lib.model_name(circuit_model).c_str());
+    exit(1);
+  }
+
+  /* Make sure:
+   * There is only 1 output port, 
+   * each size of which is 1
+   */
+  VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) );
+
+  /* Create a Verilog Module based on the circuit model, and add to module manager */
+  ModuleId module_id = module_manager.find_module(circuit_lib.model_name(circuit_model)); 
+  VTR_ASSERT(true == module_manager.valid_module_id(module_id));
+
+  /* dump module definition + ports */
+  print_verilog_module_declaration(fp, module_manager, module_id);
+  /* Finish dumping ports */
+
+  /* Dump logics: we propagate input to the output when the gate is '1' 
+   * the input is blocked from output when the gate is '0'
+   */
+  fp << "\tassign " << circuit_lib.port_prefix(output_ports[0]) << " = ";
+  fp << circuit_lib.port_prefix(input_ports[1]) << " ? " << circuit_lib.port_prefix(input_ports[0]);
+  fp << " : 1'bz;" << std::endl;
+
+  /* Print timing info */
+  print_verilog_submodule_timing(fp, circuit_lib, circuit_model);
+
+  /* Print signal initialization */
+  print_verilog_submodule_signal_init(fp, circuit_lib, circuit_model);
+   
+  /* Put an end to the Verilog module */
+  print_verilog_module_end(fp, circuit_lib.model_name(circuit_model));
+}
+
+/************************************************
+ * Print Verilog body codes of an N-input AND gate
+ ***********************************************/
+static 
+void print_verilog_and_or_gate_body(std::fstream& fp,
+                                    const CircuitLibrary& circuit_lib,
+                                    const CircuitModelId& circuit_model,
+                                    const std::vector<CircuitPortId>& input_ports,
+                                    const std::vector<CircuitPortId>& output_ports) {
+  /* Ensure a valid file handler*/
+  VTR_ASSERT(true == valid_file_stream(fp));
+
+  /* Find the logic operator for the gate */
+  std::string gate_verilog_operator;
+  switch (circuit_lib.gate_type(circuit_model)) {
+  case CIRCUIT_MODEL_GATE_AND:
+    gate_verilog_operator = "&";
+    break;
+  case CIRCUIT_MODEL_GATE_OR:
+    gate_verilog_operator = "|";
+    break;
+  default:
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid topology for circuit model '%s'!\n",
+                   circuit_lib.model_name(circuit_model).c_str());
+    exit(1);
+  }
+
+  /* Output verilog codes */
+  print_verilog_comment(fp, std::string("----- Verilog codes of a " + std::to_string(input_ports.size()) + "-input " + std::to_string(output_ports.size()) + "-output AND gate -----"));
+
+  for (const auto& output_port : output_ports) {
+    for (const auto& output_pin : circuit_lib.pins(output_port)) {
+      BasicPort output_port_info(circuit_lib.port_prefix(output_port), output_pin, output_pin);
+      fp << "\tassign " << generate_verilog_port(VERILOG_PORT_CONKT, output_port_info);
+      fp << " = ";
+
+      size_t port_cnt = 0;
+      for (const auto& input_port : input_ports) {
+        for (const auto& input_pin : circuit_lib.pins(input_port)) {
+          /* Do not output AND/OR operator for the first element in the loop */
+          if (0 < port_cnt) {
+            fp << " " << gate_verilog_operator << " ";
+          }
+
+          BasicPort input_port_info(circuit_lib.port_prefix(input_port), input_pin, input_pin);
+          fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port_info);
+            
+          /* Increment the counter for port */ 
+          port_cnt++;
+        }
+      }
+      fp << ";" << std::endl;
+    }
+  }
+}
+
+/************************************************
+ * Print Verilog body codes of an 2-input MUX gate
+ ***********************************************/
+static 
+void print_verilog_mux2_gate_body(std::fstream& fp,
+                                  const CircuitLibrary& circuit_lib,
+                                  const CircuitModelId& circuit_model,
+                                  const std::vector<CircuitPortId>& input_ports,
+                                  const std::vector<CircuitPortId>& output_ports) {
+  /* Ensure a valid file handler*/
+  VTR_ASSERT(true == valid_file_stream(fp));
+
+  /* TODO: Move the check codes to check_circuit_library.cpp */
+  size_t num_err = 0;
+  /* Check on the port sequence and map */
+  /* MUX2 should only have 1 output port with size 1 */
+  if (1 != output_ports.size()) {
+    VTR_LOGF_ERROR(__FILE__, __LINE__, 
+                   "MUX2 circuit model '%s' must have only 1 output!\n",
+                   circuit_lib.model_name(circuit_model).c_str());
+    num_err++;
+  } 
+  for (const auto& output_port : output_ports) {  
+    /* Bypass port size of 1 */
+    if (1 == circuit_lib.port_size(output_port)) {
+      continue;
+    }
+    VTR_LOGF_ERROR(__FILE__, __LINE__, 
+                   "Output port size of a MUX2 circuit model '%s' must be 1!\n",
+                   circuit_lib.model_name(circuit_model).c_str());
+    num_err++;
+  }
+  /* MUX2 should only have 3 output port, each of which has a port size of 1 */
+  if (3 != input_ports.size()) {
+    VTR_LOGF_ERROR(__FILE__, __LINE__, 
+                   "MUX2 circuit model '%s' must have only 3 input!\n",
+                   circuit_lib.model_name(circuit_model).c_str());
+    num_err++;
+  }
+
+  for (const auto& input_port : input_ports) {  
+    /* Bypass port size of 1 */
+    if (1 == circuit_lib.port_size(input_port)) {
+      continue;
+    }
+    VTR_LOGF_ERROR(__FILE__, __LINE__, 
+                   "Input size MUX2 circuit model '%s' must be 1!\n",
+                   circuit_lib.model_name(circuit_model).c_str());
+    num_err++;
+  }
+  if (0 < num_err) {
+    exit(1);
+  }
+
+  /* Now, we output the logic of MUX2
+   * IMPORTANT Restriction:
+   * We always assum the first two inputs are data inputs
+   * the third input is the select port  
+   */
+  fp << "\tassign ";
+  BasicPort out_port_info(circuit_lib.port_prefix(output_ports[0]), 0, 0);
+  BasicPort sel_port_info(circuit_lib.port_prefix(input_ports[2]), 0, 0);
+  BasicPort in0_port_info(circuit_lib.port_prefix(input_ports[0]), 0, 0);
+  BasicPort in1_port_info(circuit_lib.port_prefix(input_ports[1]), 0, 0);
+
+  fp << generate_verilog_port(VERILOG_PORT_CONKT, out_port_info);
+  fp << " = ";
+  fp << generate_verilog_port(VERILOG_PORT_CONKT, sel_port_info);
+  fp << " ? ";
+  fp << generate_verilog_port(VERILOG_PORT_CONKT, in0_port_info);
+  fp << " : ";
+  fp << generate_verilog_port(VERILOG_PORT_CONKT, in1_port_info);
+  fp << ";" << std::endl;
+}
+
+/************************************************
+ * Print a Verilog module of a logic gate
+ * which are standard cells
+ * Supported gate types: 
+ * 1. N-input AND 
+ * 2. N-input OR
+ * 3. 2-input MUX
+ ***********************************************/
+static 
+void print_verilog_gate_module(ModuleManager& module_manager, 
+                               std::fstream& fp,
+                               const CircuitLibrary& circuit_lib,
+                               const CircuitModelId& circuit_model) {
+  /* Ensure a valid file handler*/
+  VTR_ASSERT(true == valid_file_stream(fp));
+
+  /* Find the input port, output port*/
+  std::vector<CircuitPortId> input_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true);
+  std::vector<CircuitPortId> output_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
+  std::vector<CircuitPortId> global_ports = circuit_lib.model_global_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true, true);
+
+  /* Make sure:
+   * There is only 1 output port, 
+   * each size of which is 1
+   */
+  VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) );
+
+  /* Create a Verilog Module based on the circuit model, and add to module manager */
+  ModuleId module_id = module_manager.find_module(circuit_lib.model_name(circuit_model)); 
+  VTR_ASSERT(true == module_manager.valid_module_id(module_id));
+
+  /* dump module definition + ports */
+  print_verilog_module_declaration(fp, module_manager, module_id);
+  /* Finish dumping ports */
+
+  /* Dump logics */
+  switch (circuit_lib.gate_type(circuit_model)) {
+  case CIRCUIT_MODEL_GATE_AND:
+  case CIRCUIT_MODEL_GATE_OR:
+    print_verilog_and_or_gate_body(fp, circuit_lib, circuit_model, input_ports, output_ports);
+    break;
+  case CIRCUIT_MODEL_GATE_MUX2:
+    print_verilog_mux2_gate_body(fp, circuit_lib, circuit_model, input_ports, output_ports);
+    break;
+  default:
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid topology for circuit model '%s'!\n",
+                   circuit_lib.model_name(circuit_model).c_str());
+    exit(1);
+  }
+
+  /* Print timing info */
+  print_verilog_submodule_timing(fp, circuit_lib, circuit_model);
+
+  /* Print signal initialization */
+  print_verilog_submodule_signal_init(fp, circuit_lib, circuit_model);
+   
+  /* Put an end to the Verilog module */
+  print_verilog_module_end(fp, circuit_lib.model_name(circuit_model));
+}
+
+/************************************************
+ * Generate the Verilog netlist for a constant generator,
+ * i.e., either VDD or GND
+ ***********************************************/
+static 
+void print_verilog_constant_generator_module(const ModuleManager& module_manager, 
+                                             std::fstream& fp, 
+                                             const size_t& const_value) {
+  /* Find the module in module manager */
+  std::string module_name = generate_const_value_module_name(const_value);
+  ModuleId const_val_module = module_manager.find_module(module_name);
+  VTR_ASSERT(true == module_manager.valid_module_id(const_val_module));
+
+  /* Ensure a valid file handler*/
+  VTR_ASSERT(true == valid_file_stream(fp));
+
+  /* dump module definition + ports */
+  print_verilog_module_declaration(fp, module_manager, const_val_module);
+  /* Finish dumping ports */
+
+  /* Find the only output*/
+  for (const ModulePortId& module_port_id : module_manager.module_ports(const_val_module)) {
+    BasicPort module_port = module_manager.module_port(const_val_module, module_port_id);
+    print_verilog_wire_constant_values(fp, module_port, std::vector<size_t>(1, const_value));
+  }
+  
+  /* Put an end to the Verilog module */
+  print_verilog_module_end(fp, module_name);
+}
+
+/************************************************
+ * Generate the Verilog netlist for essential gates
+ * include inverters, buffers, transmission-gates,
+ * etc.
+ ***********************************************/
+void print_verilog_submodule_essentials(ModuleManager& module_manager, 
+                                        std::vector<std::string>& netlist_names,
+                                        const std::string& verilog_dir, 
+                                        const std::string& submodule_dir,
+                                        const CircuitLibrary& circuit_lib) {
+  /* TODO: remove .bak when this part is completed and tested */
+  std::string verilog_fname = submodule_dir + std::string(ESSENTIALS_VERILOG_FILE_NAME);
+
+  std::fstream fp;
+
+  /* Create the file stream */
+  fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
+  /* Check if the file stream if valid or not */
+  check_file_stream(verilog_fname.c_str(), fp); 
+
+  /* Create file */
+  VTR_LOG("Generating Verilog netlist '%s' for essential gates...",
+          verilog_fname.c_str()); 
+
+  print_verilog_file_header(fp, "Essential gates"); 
+
+  print_verilog_include_defines_preproc_file(fp, verilog_dir);
+
+  /* Print constant generators */
+  /* VDD */
+  print_verilog_constant_generator_module(module_manager, fp, 0);
+  /* GND */
+  print_verilog_constant_generator_module(module_manager, fp, 1);
+
+  for (const auto& circuit_model : circuit_lib.models()) {
+    /* By pass user-defined modules */
+    if (!circuit_lib.model_verilog_netlist(circuit_model).empty()) {
+      continue;
+    }
+    if (CIRCUIT_MODEL_INVBUF == circuit_lib.model_type(circuit_model)) {
+      print_verilog_invbuf_module(module_manager, fp, circuit_lib, circuit_model);
+      continue;
+    }
+    if (CIRCUIT_MODEL_PASSGATE == circuit_lib.model_type(circuit_model)) {
+      print_verilog_passgate_module(module_manager, fp, circuit_lib, circuit_model);
+      continue;
+    }
+    if (CIRCUIT_MODEL_GATE == circuit_lib.model_type(circuit_model)) {
+      print_verilog_gate_module(module_manager, fp, circuit_lib, circuit_model);
+      continue;
+    }
+  }
+  
+  /* Close file handler*/
+  fp.close();
+
+  /* Add fname to the netlist name list */
+  netlist_names.push_back(verilog_fname);
+
+  VTR_LOG("Done\n");
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_verilog/verilog_essential_gates.h b/openfpga/src/fpga_verilog/verilog_essential_gates.h
new file mode 100644
index 000000000..33ce49c6c
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_essential_gates.h
@@ -0,0 +1,25 @@
+#ifndef VERILOG_ESSENTIAL_GATES_H
+#define VERILOG_ESSENTIAL_GATES_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <string>
+#include "circuit_library.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void print_verilog_submodule_essentials(ModuleManager& module_manager, 
+                                        std::vector<std::string>& netlist_names,
+                                        const std::string& verilog_dir, 
+                                        const std::string& submodule_dir,
+                                        const CircuitLibrary& circuit_lib);
+
+} /* end namespace openfpga */
+
+#endif

From 3efd1a2a6d59711e1aadcded3bc3c0bb3e20a742 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 16 Feb 2020 12:04:03 -0700
Subject: [PATCH 152/645] print verilog module writer online

---
 .../fpga_verilog/verilog_module_writer.cpp    | 502 ++++++++++++++++++
 .../src/fpga_verilog/verilog_module_writer.h  |  24 +
 2 files changed, 526 insertions(+)
 create mode 100644 openfpga/src/fpga_verilog/verilog_module_writer.cpp
 create mode 100644 openfpga/src/fpga_verilog/verilog_module_writer.h

diff --git a/openfpga/src/fpga_verilog/verilog_module_writer.cpp b/openfpga/src/fpga_verilog/verilog_module_writer.cpp
new file mode 100644
index 000000000..15a5bc28d
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_module_writer.cpp
@@ -0,0 +1,502 @@
+/********************************************************************
+ * This file includes functions to write a Verilog module
+ * based on its definition in Module Manager
+ *
+ * Note that Verilog writer functions are just an outputter for the
+ * module definition. 
+ * You should NOT modify any content of the module manager
+ * Please use const keyword to restrict this!
+ *******************************************************************/
+#include <algorithm>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_port.h"
+#include "openfpga_digest.h"
+
+#include "module_manager_utils.h"
+#include "verilog_port_types.h"
+#include "verilog_writer_utils.h"
+#include "verilog_module_writer.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Generate the name of a local wire for a undriven port inside Verilog 
+ * module 
+ *******************************************************************/
+static 
+std::string generate_verilog_undriven_local_wire_name(const ModuleManager& module_manager, 
+                                                      const ModuleId& module, 
+                                                      const ModulePortId& module_port_id) {
+  return module_manager.module_port(module, module_port_id).get_name();
+}
+
+/********************************************************************
+ * Name a net for a local wire for a verilog module 
+ * 1. If this is a local wire, name it after the <src_module_name>_<instance_id>_<src_port_name>
+ * 2. If this is not a local wire, name it after the port name of parent module 
+ *
+ * In addition, it will assign the pin index as well  
+ *
+ * Restriction: this function requires each net has single driver
+ * which is definitely always true in circuits.
+ *******************************************************************/
+static 
+BasicPort generate_verilog_port_for_module_net(const ModuleManager& module_manager,
+                                               const ModuleId& module_id,
+                                               const ModuleNetId& module_net) {
+  /* Check all the sink modules of the net, 
+   * if we have a source module is the current module, this is not local wire 
+   */
+  for (ModuleNetSrcId src_id : module_manager.module_net_sources(module_id, module_net)) {
+    if (module_id == module_manager.net_source_modules(module_id, module_net)[src_id]) {
+      /* Here, this is not a local wire, return the port name of the src_port */
+      ModulePortId net_src_port = module_manager.net_source_ports(module_id, module_net)[src_id];
+      size_t src_pin_index = module_manager.net_source_pins(module_id, module_net)[src_id];
+      return BasicPort(module_manager.module_port(module_id, net_src_port).get_name(), src_pin_index, src_pin_index);
+    }
+  }
+
+  /* Check all the sink modules of the net */
+  for (ModuleNetSinkId sink_id : module_manager.module_net_sinks(module_id, module_net)) {
+    if (module_id == module_manager.net_sink_modules(module_id, module_net)[sink_id]) {
+      /* Here, this is not a local wire, return the port name of the sink_port */
+      ModulePortId net_sink_port = module_manager.net_sink_ports(module_id, module_net)[sink_id];
+      size_t sink_pin_index = module_manager.net_sink_pins(module_id, module_net)[sink_id];
+      return BasicPort(module_manager.module_port(module_id, net_sink_port).get_name(), sink_pin_index, sink_pin_index);
+    }
+  }
+
+  /* Reach here, this is a local wire */
+  std::string net_name;
+
+  /* Each net must only one 1 source */ 
+  VTR_ASSERT(1 == module_manager.net_source_modules(module_id, module_net).size());
+
+  /* Get the source module */
+  ModuleId net_src_module = module_manager.net_source_modules(module_id, module_net)[ModuleNetSrcId(0)];
+  /* Get the instance id */
+  size_t net_src_instance = module_manager.net_source_instances(module_id, module_net)[ModuleNetSrcId(0)]; 
+  /* Get the port id */
+  ModulePortId net_src_port = module_manager.net_source_ports(module_id, module_net)[ModuleNetSrcId(0)]; 
+  /* Get the pin id */
+  size_t net_src_pin = module_manager.net_source_pins(module_id, module_net)[ModuleNetSrcId(0)]; 
+
+  /* Load user-defined name if we have it */
+  if (false == module_manager.net_name(module_id, module_net).empty()) {
+    net_name = module_manager.net_name(module_id, module_net);
+  } else {
+    net_name  = module_manager.module_name(net_src_module); 
+    net_name += std::string("_") + std::to_string(net_src_instance) + std::string("_");
+    net_name += module_manager.module_port(net_src_module, net_src_port).get_name();
+  }
+  
+  return BasicPort(net_name, net_src_pin, net_src_pin);
+}
+
+/********************************************************************
+ * Find all the nets that are going to be local wires
+ * And organize it in a vector of ports
+ * Verilog wire writter function will use the output of this function
+ * to write up local wire declaration in Verilog format
+ *******************************************************************/
+static 
+std::map<std::string, std::vector<BasicPort>> find_verilog_module_local_wires(const ModuleManager& module_manager,
+                                                                              const ModuleId& module_id) {
+  std::map<std::string, std::vector<BasicPort>> local_wires;
+
+  /* Local wires come from the child modules */
+  for (ModuleNetId module_net : module_manager.module_nets(module_id)) {
+    /* Bypass dangling nets:
+     * Xifan Tang: I comment this part because it will shadow our problems in creating module graph
+     * Indeed this make a robust and a smooth Verilog module writing
+     * But I do want the module graph create is nice and clean !!! 
+     */
+    /*
+    if ( (0 == module_manager.net_source_modules(module_id, module_net).size()) 
+      && (0 == module_manager.net_source_modules(module_id, module_net).size()) ) {
+      continue;
+    }
+    */
+
+    /* We only care local wires */ 
+    if (false == module_net_is_local_wire(module_manager, module_id, module_net)) {
+      continue;
+    }
+    /* Find the name for this local wire */
+    BasicPort local_wire_candidate = generate_verilog_port_for_module_net(module_manager, module_id, module_net);
+    /* Cache the net name, try to find it in the cache.
+     * If you can find one, it means this port may be mergeable, try to do merging. If merge fail, add to the local wire list
+     * If you cannot find one, it means that this port is not mergeable, add to the local wire list immediately.
+     */
+    std::map<std::string, std::vector<BasicPort>>::iterator it = local_wires.find(local_wire_candidate.get_name());
+    bool merged = false;
+    if (it != local_wires.end()) {
+      /* Try to merge to one the port in the list that can absorb the current local wire */
+      for (BasicPort& local_wire : local_wires[local_wire_candidate.get_name()]) {
+        /* check if the candidate can be combined to an existing local wire */
+        if (true == two_verilog_ports_mergeable(local_wire, local_wire_candidate)) {
+          /* Merge the ports */
+          local_wire = merge_two_verilog_ports(local_wire, local_wire_candidate);
+          merged = true;
+          break;
+        } 
+      }
+    }
+
+    /* If not merged/not found in the cache, push the port to the list */
+    if (false == merged) {
+      local_wires[local_wire_candidate.get_name()].push_back(local_wire_candidate);
+    }
+  }
+
+  /* Local wires could also happen for undriven ports of child module */
+  for (const ModuleId& child : module_manager.child_modules(module_id)) {
+    for (size_t instance : module_manager.child_module_instances(module_id, child)) {
+      for (const ModulePortId& child_port_id : module_manager.module_ports(child)) {
+        BasicPort child_port = module_manager.module_port(child, child_port_id);
+        std::vector<size_t> undriven_pins;
+        for (size_t child_pin : child_port.pins()) {
+          /* Find the net linked to the pin */
+          ModuleNetId net = module_manager.module_instance_port_net(module_id, child, instance, 
+                                                                    child_port_id, child_pin);
+          /* We only care undriven ports */
+          if (ModuleNetId::INVALID() == net) {
+            undriven_pins.push_back(child_pin);
+          }
+        }
+        if (true == undriven_pins.empty()) {
+          continue;
+        }
+        /* Reach here, we need a local wire, we will create a port only for the undriven pins of the port! */
+        BasicPort instance_port;
+        instance_port.set_name(generate_verilog_undriven_local_wire_name(module_manager, child, child_port_id));
+        /* We give the same port name as child module, this case happens to global ports */
+        instance_port.set_width(*std::min_element(undriven_pins.begin(), undriven_pins.end()),
+                                *std::max_element(undriven_pins.begin(), undriven_pins.end())); 
+
+        local_wires[instance_port.get_name()].push_back(instance_port);
+      }
+    }
+  }
+
+  return local_wires;
+}
+
+/********************************************************************
+ * Print a Verilog wire connection 
+ * We search all the sinks of the net, 
+ * if we find a module output, we try to find the next module output 
+ * among the sinks of the net
+ * For each module output (except the first one), we print a wire connection 
+ *******************************************************************/
+static 
+void print_verilog_module_output_short_connection(std::fstream& fp, 
+                                                  const ModuleManager& module_manager,
+                                                  const ModuleId& module_id,
+                                                  const ModuleNetId& module_net) {
+  /* Ensure a valid file stream */
+  VTR_ASSERT(true == valid_file_stream(fp));
+
+  bool first_port = true;
+  BasicPort src_port;
+
+  /* We have found a module input, now check all the sink modules of the net */
+  for (ModuleNetSinkId net_sink : module_manager.module_net_sinks(module_id, module_net)) {
+    ModuleId sink_module = module_manager.net_sink_modules(module_id, module_net)[net_sink];
+    if (module_id != sink_module) {
+      continue;
+    }
+
+    /* Find the sink port and pin information */
+    ModulePortId sink_port_id = module_manager.net_sink_ports(module_id, module_net)[net_sink];
+    size_t sink_pin = module_manager.net_sink_pins(module_id, module_net)[net_sink];
+    BasicPort sink_port(module_manager.module_port(module_id, sink_port_id).get_name(), sink_pin, sink_pin);
+
+    /* For the first module output, this is the source port, we do nothing and go to the next */
+    if (true == first_port) {
+      src_port = sink_port;
+      /* Flip the flag */
+      first_port = false;
+      continue;
+    }
+
+    /* We need to print a wire connection here */
+    print_verilog_wire_connection(fp, sink_port, src_port, false);
+  }
+}
+
+
+/********************************************************************
+ * Print a Verilog wire connection 
+ * We search all the sources of the net, 
+ * if we find a module input, we try to find a module output 
+ * among the sinks of the net
+ * If we find such a pair, we print a wire connection 
+ *******************************************************************/
+static 
+void print_verilog_module_local_short_connection(std::fstream& fp, 
+                                                 const ModuleManager& module_manager,
+                                                 const ModuleId& module_id,
+                                                 const ModuleNetId& module_net) {
+  /* Ensure a valid file stream */
+  VTR_ASSERT(true == valid_file_stream(fp));
+
+  for (ModuleNetSrcId net_src : module_manager.module_net_sources(module_id, module_net)) {
+    ModuleId src_module = module_manager.net_source_modules(module_id, module_net)[net_src];
+    if (module_id != src_module) {
+      continue;
+    }
+    /* Find the source port and pin information */
+    print_verilog_comment(fp, std::string("----- Net source id " + std::to_string(size_t(net_src)) + " -----"));
+    ModulePortId src_port_id = module_manager.net_source_ports(module_id, module_net)[net_src];
+    size_t src_pin = module_manager.net_source_pins(module_id, module_net)[net_src];
+    BasicPort src_port(module_manager.module_port(module_id, src_port_id).get_name(), src_pin, src_pin);
+
+    /* We have found a module input, now check all the sink modules of the net */
+    for (ModuleNetSinkId net_sink : module_manager.module_net_sinks(module_id, module_net)) {
+      ModuleId sink_module = module_manager.net_sink_modules(module_id, module_net)[net_sink];
+      if (module_id != sink_module) {
+        continue;
+      }
+
+      /* Find the sink port and pin information */
+      print_verilog_comment(fp, std::string("----- Net sink id " + std::to_string(size_t(net_sink)) + " -----"));
+      ModulePortId sink_port_id = module_manager.net_sink_ports(module_id, module_net)[net_sink];
+      size_t sink_pin = module_manager.net_sink_pins(module_id, module_net)[net_sink];
+      BasicPort sink_port(module_manager.module_port(module_id, sink_port_id).get_name(), sink_pin, sink_pin);
+
+      /* We need to print a wire connection here */
+      print_verilog_wire_connection(fp, sink_port, src_port, false);
+    }
+  }
+}
+
+/********************************************************************
+ * Print short connections inside a Verilog module
+ * The short connection is defined as the direct connection
+ * between an input port of the module and an output port of the module
+ * This type of connection is not covered when printing Verilog instances
+ * Therefore, they are covered in this function 
+ *
+ *            module
+ *            +-----------------------------+
+ *            |                             |
+ *  inputA--->|---------------------------->|--->outputB
+ *            |                             |
+ *            |                             |
+ *            |                             |
+ *            +-----------------------------+
+ *******************************************************************/
+static 
+void print_verilog_module_local_short_connections(std::fstream& fp, 
+                                                  const ModuleManager& module_manager,
+                                                  const ModuleId& module_id) {
+  /* Local wires come from the child modules */
+  for (ModuleNetId module_net : module_manager.module_nets(module_id)) {
+    /* We only care the nets that indicate short connections */ 
+    if (false == module_net_include_local_short_connection(module_manager, module_id, module_net)) {
+      continue;
+    }
+    print_verilog_comment(fp, std::string("----- Local connection due to Wire " + std::to_string(size_t(module_net)) + " -----"));
+    print_verilog_module_local_short_connection(fp, module_manager, module_id, module_net); 
+  }
+}
+
+/********************************************************************
+ * Print output short connections inside a Verilog module
+ * The output short connection is defined as the direct connection
+ * between two output ports of the module
+ * This type of connection is not covered when printing Verilog instances
+ * Therefore, they are covered in this function 
+ *
+ *            module
+ *            +-----------------------------+
+ *                                          |
+ *               src------>+--------------->|--->outputA
+ *                         |                |
+ *                         |                |
+ *                         +--------------->|--->outputB
+ *            +-----------------------------+
+ *******************************************************************/
+static 
+void print_verilog_module_output_short_connections(std::fstream& fp, 
+                                                   const ModuleManager& module_manager,
+                                                   const ModuleId& module_id) {
+  /* Local wires come from the child modules */
+  for (ModuleNetId module_net : module_manager.module_nets(module_id)) {
+    /* We only care the nets that indicate short connections */ 
+    if (false == module_net_include_output_short_connection(module_manager, module_id, module_net)) {
+      continue;
+    }
+    print_verilog_module_output_short_connection(fp, module_manager, module_id, module_net); 
+  }
+}
+
+/********************************************************************
+ * Write a Verilog instance to a file
+ * This function will name the input and output connections to
+ * the inputs/output or local wires available in the parent module
+ *      
+ *    Parent_module
+ *    +-----------------------------+
+ *    |                             |
+ *    |       +--------------+      |
+ *    |       |              |      |
+ *    |       | child_module |      |
+ *    |       |  [instance]  |      |
+ *    |       +--------------+      |
+ *    |                             |
+ *    +-----------------------------+
+ *
+ *******************************************************************/
+static 
+void write_verilog_instance_to_file(std::fstream& fp,
+                                    const ModuleManager& module_manager,
+                                    const ModuleId& parent_module,
+                                    const ModuleId& child_module,
+                                    const size_t& instance_id,
+                                    const bool& use_explicit_port_map) {
+  /* Ensure a valid file stream */
+  VTR_ASSERT(true == valid_file_stream(fp));
+
+  /* Print module name */
+  fp << "\t" << module_manager.module_name(child_module) << " ";
+  /* Print instance name: 
+   * if we have an instance name, use it;
+   * if not, we use a default name <name>_<num_instance_in_parent_module> 
+   */
+  if (true == module_manager.instance_name(parent_module, child_module, instance_id).empty()) {
+    fp << module_manager.module_name(child_module) << "_" << instance_id << "_" << " (" << std::endl;
+  } else {
+    fp << module_manager.instance_name(parent_module, child_module, instance_id) << " (" << std::endl;
+  }
+
+  /* Print each port with/without explicit port map */
+  /* port type2type mapping */
+  std::map<ModuleManager::e_module_port_type, enum e_dump_verilog_port_type> port_type2type_map;
+  port_type2type_map[ModuleManager::MODULE_GLOBAL_PORT] = VERILOG_PORT_CONKT;
+  port_type2type_map[ModuleManager::MODULE_GPIO_PORT] = VERILOG_PORT_CONKT;
+  port_type2type_map[ModuleManager::MODULE_INOUT_PORT] = VERILOG_PORT_CONKT;
+  port_type2type_map[ModuleManager::MODULE_INPUT_PORT] = VERILOG_PORT_CONKT;
+  port_type2type_map[ModuleManager::MODULE_OUTPUT_PORT] = VERILOG_PORT_CONKT;
+  port_type2type_map[ModuleManager::MODULE_CLOCK_PORT] = VERILOG_PORT_CONKT;
+
+  /* Port sequence: global, inout, input, output and clock ports, */
+  size_t port_cnt = 0;
+  for (const auto& kv : port_type2type_map) {
+    for (const ModulePortId& child_port_id : module_manager.module_port_ids_by_type(child_module, kv.first)) {
+      BasicPort child_port = module_manager.module_port(child_module, child_port_id);
+      if (0 != port_cnt) {
+        /* Do not dump a comma for the first port */
+        fp << "," << std::endl; 
+      }
+      /* Print port */
+      fp << "\t\t";
+      /* if explicit port map is required, output the port name */
+      if (true == use_explicit_port_map) {
+        fp << "." << child_port.get_name() << "(";
+      }
+
+      /* Create the port name and width to be used by the instance */
+      std::vector<BasicPort> instance_ports; 
+      for (size_t child_pin : child_port.pins()) {
+        /* Find the net linked to the pin */
+        ModuleNetId net = module_manager.module_instance_port_net(parent_module, child_module, instance_id, 
+                                                                  child_port_id, child_pin);
+        BasicPort instance_port;
+        if (ModuleNetId::INVALID() == net) {
+          /* We give the same port name as child module, this case happens to global ports */
+          instance_port.set_name(generate_verilog_undriven_local_wire_name(module_manager, child_module, child_port_id));
+          instance_port.set_width(child_pin, child_pin); 
+        } else {
+          /* Find the name for this child port */
+          instance_port = generate_verilog_port_for_module_net(module_manager, parent_module, net);
+        }
+        /* Create the port information for the net */
+        instance_ports.push_back(instance_port);
+      } 
+      /* Try to merge the ports */
+      std::vector<BasicPort> merged_ports = combine_verilog_ports(instance_ports); 
+
+      /* Print a verilog port by combining the instance ports */
+      fp << generate_verilog_ports(merged_ports);
+
+      /* if explicit port map is required, output the pair of branket */
+      if (true == use_explicit_port_map) {
+        fp << ")";
+      }
+      port_cnt++;
+    }
+  }
+  
+  /* Print an end to the instance */
+  fp << ");" << std::endl;
+}
+
+/********************************************************************
+ * Write a Verilog module to a file
+ * This is a key function, maybe most frequently called in our Verilog writer
+ * Note that file stream must be valid 
+ *******************************************************************/
+void write_verilog_module_to_file(std::fstream& fp,
+                                  const ModuleManager& module_manager,
+                                  const ModuleId& module_id,
+                                  const bool& use_explicit_port_map) {
+
+  VTR_ASSERT(true == valid_file_stream(fp));
+
+  /* Ensure we have a valid module_id */
+  VTR_ASSERT(module_manager.valid_module_id(module_id)); 
+
+  /* Print module declaration */
+  print_verilog_module_declaration(fp, module_manager, module_id);
+
+  /* Print an empty line as splitter */
+  fp << std::endl;
+   
+  /* Print internal wires */
+  std::map<std::string, std::vector<BasicPort>> local_wires = find_verilog_module_local_wires(module_manager, module_id);
+  for (std::pair<std::string, std::vector<BasicPort>> port_group : local_wires) {
+    for (const BasicPort& local_wire : port_group.second) {
+      fp << generate_verilog_port(VERILOG_PORT_WIRE, local_wire) << ";" << std::endl;
+    }
+  }
+
+  /* Print an empty line as splitter */
+  fp << std::endl;
+
+  /* Print local connection (from module inputs to output! */
+  print_verilog_comment(fp, std::string("----- BEGIN Local short connections -----"));
+  print_verilog_module_local_short_connections(fp, module_manager, module_id);
+  print_verilog_comment(fp, std::string("----- END Local short connections -----"));
+
+  print_verilog_comment(fp, std::string("----- BEGIN Local output short connections -----"));
+  print_verilog_module_output_short_connections(fp, module_manager, module_id);
+ 
+  print_verilog_comment(fp, std::string("----- END Local output short connections -----"));
+  /* Print an empty line as splitter */
+  fp << std::endl;
+
+  /* Print instances */
+  for (ModuleId child_module : module_manager.child_modules(module_id)) {
+    for (size_t instance : module_manager.child_module_instances(module_id, child_module)) {
+      /* Print an instance */
+      write_verilog_instance_to_file(fp, module_manager, module_id, child_module, instance, use_explicit_port_map); 
+      /* Print an empty line as splitter */
+      fp << std::endl;
+    }
+  }
+
+  /* Print an end for the module */
+  print_verilog_module_end(fp, module_manager.module_name(module_id)); 
+
+  /* Print an empty line as splitter */
+  fp << std::endl;
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_verilog/verilog_module_writer.h b/openfpga/src/fpga_verilog/verilog_module_writer.h
new file mode 100644
index 000000000..1c0391492
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_module_writer.h
@@ -0,0 +1,24 @@
+#ifndef VERILOG_MODULE_WRITER_H
+#define VERILOG_MODULE_WRITER_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <fstream>
+#include "module_manager.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void write_verilog_module_to_file(std::fstream& fp,
+                                  const ModuleManager& module_manager,
+                                  const ModuleId& module_id,
+                                  const bool& use_explicit_port_map);
+
+} /* end namespace openfpga */
+
+#endif

From a88c4bc954f38edef0fb29ee7e753b357cab47dd Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 16 Feb 2020 12:21:59 -0700
Subject: [PATCH 153/645] add decode utils to libopenfpga and adapt local
 decoder writer in Verilog

---
 .../libopenfpgautil/src/openfpga_decode.cpp   |  55 +++++
 .../libopenfpgautil/src/openfpga_decode.h     |  23 ++
 .../src/fpga_verilog/verilog_decoders.cpp     | 231 ++++++++++++++++++
 openfpga/src/fpga_verilog/verilog_decoders.h  |  32 +++
 4 files changed, 341 insertions(+)
 create mode 100644 libopenfpga/libopenfpgautil/src/openfpga_decode.cpp
 create mode 100644 libopenfpga/libopenfpgautil/src/openfpga_decode.h
 create mode 100644 openfpga/src/fpga_verilog/verilog_decoders.cpp
 create mode 100644 openfpga/src/fpga_verilog/verilog_decoders.h

diff --git a/libopenfpga/libopenfpgautil/src/openfpga_decode.cpp b/libopenfpga/libopenfpgautil/src/openfpga_decode.cpp
new file mode 100644
index 000000000..9839f13b9
--- /dev/null
+++ b/libopenfpga/libopenfpgautil/src/openfpga_decode.cpp
@@ -0,0 +1,55 @@
+/***************************************************************************************
+ * This file includes functions that are used to decode integer to binary vectors
+ * or the reverse operation
+ ***************************************************************************************/
+#include <cmath>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+
+#include "openfpga_decode.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/******************************************************************** 
+ * Convert an integer to an one-hot encoding integer array
+ ********************************************************************/
+std::vector<size_t> ito1hot_vec(const size_t& in_int,
+                                const size_t& bin_len) {
+  /* Make sure we do not have any overflow! */
+  VTR_ASSERT ( (in_int <= bin_len) );
+
+  /* Initialize */
+  std::vector<size_t> ret(bin_len, 0);
+
+  if (bin_len == in_int) {
+    return ret; /* all zero case */
+  }
+  ret[in_int] = 1; /* Keep a good sequence of bits */
+ 
+  return ret;
+}
+
+/******************************************************************** 
+ * Converter an integer to a binary vector 
+ ********************************************************************/
+std::vector<size_t> itobin_vec(const size_t& in_int,
+                               const size_t& bin_len) {
+  std::vector<size_t> ret(bin_len, 0);
+
+  /* Make sure we do not have any overflow! */
+  VTR_ASSERT ( (in_int < pow(2., bin_len)) );
+  
+  size_t temp = in_int;
+  for (size_t i = 0; i < bin_len; i++) {
+    if (1 == temp % 2) { 
+      ret[i] = 1; /* Keep a good sequence of bits */
+    }
+    temp = temp / 2;
+  }
+ 
+  return ret;
+}
+
+} /* end namespace openfpga */
diff --git a/libopenfpga/libopenfpgautil/src/openfpga_decode.h b/libopenfpga/libopenfpgautil/src/openfpga_decode.h
new file mode 100644
index 000000000..c79254f63
--- /dev/null
+++ b/libopenfpga/libopenfpgautil/src/openfpga_decode.h
@@ -0,0 +1,23 @@
+#ifndef OPENFPGA_DECODE_H
+#define OPENFPGA_DECODE_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <vector>
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+/* namespace openfpga begins */
+namespace openfpga {
+
+std::vector<size_t> ito1hot_vec(const size_t& in_int,
+                                const size_t& bin_len);
+
+std::vector<size_t> itobin_vec(const size_t& in_int,
+                               const size_t& bin_len);
+
+} /* namespace openfpga ends */
+
+#endif
diff --git a/openfpga/src/fpga_verilog/verilog_decoders.cpp b/openfpga/src/fpga_verilog/verilog_decoders.cpp
new file mode 100644
index 000000000..7689d3ed6
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_decoders.cpp
@@ -0,0 +1,231 @@
+/***************************************************************************************
+ * This file includes functions to generate Verilog modules of decoders
+ ***************************************************************************************/
+/* TODO: merge verilog_decoder.c to this source file and rename to verilog_decoder.cpp */
+#include <string>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_digest.h"
+#include "openfpga_decode.h"
+
+#include "decoder_library_utils.h"
+#include "module_manager.h"
+
+#include "openfpga_naming.h"
+
+#include "verilog_constants.h"
+#include "verilog_writer_utils.h"
+#include "verilog_decoders.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/***************************************************************************************
+ * Create a Verilog module for a decoder with a given output size
+ *
+ *                     Inputs 
+ *                   | | ... | 
+ *                   v v     v
+ *                 +-----------+
+ *                /             \
+ *               /    Decoder    \
+ *              +-----------------+
+ *                | | | ... | | |
+ *                v v v     v v v
+ *                    Outputs
+ *               
+ *  The outputs are assumes to be one-hot codes (at most only one '1' exist)
+ *  Considering this fact, there are only num_of_outputs conditions to be encoded.
+ *  Therefore, the number of inputs is ceil(log(num_of_outputs)/log(2))
+ ***************************************************************************************/
+static 
+void print_verilog_mux_local_decoder_module(std::fstream& fp, 
+                                            ModuleManager& module_manager,
+                                            const DecoderLibrary& decoder_lib,
+                                            const DecoderId& decoder) {
+  /* Get the number of inputs */
+  size_t addr_size = decoder_lib.addr_size(decoder);
+  size_t data_size = decoder_lib.data_size(decoder);
+
+  /* Validate the FILE handler */
+  VTR_ASSERT(true == valid_file_stream(fp));
+
+  /* TODO: create a name for the local encoder */
+  std::string module_name = generate_mux_local_decoder_subckt_name(addr_size, data_size);
+
+  /* Create a Verilog Module based on the circuit model, and add to module manager */
+  ModuleId module_id = module_manager.find_module(module_name); 
+  VTR_ASSERT(true == module_manager.valid_module_id(module_id));
+  /* Add module ports */
+  /* Add each input port */
+  BasicPort addr_port(generate_mux_local_decoder_addr_port_name(), addr_size);
+  /* Add each output port */
+  BasicPort data_port(generate_mux_local_decoder_data_port_name(), data_size);
+  /* Data port is registered. It should be outputted as 
+   *   output reg [lsb:msb] data 
+   */
+  /* Add data_in port */
+  BasicPort data_inv_port(generate_mux_local_decoder_data_inv_port_name(), data_size);
+  VTR_ASSERT(true == decoder_lib.use_data_inv_port(decoder));
+
+  /* dump module definition + ports */
+  print_verilog_module_declaration(fp, module_manager, module_id);
+  /* Finish dumping ports */
+
+  print_verilog_comment(fp, std::string("----- BEGIN Verilog codes for Decoder convert " + std::to_string(addr_size) + "-bit addr to " + std::to_string(data_size) + "-bit data -----"));
+
+  /* Print the truth table of this decoder */
+  /* Internal logics */
+  /* Early exit: Corner case for data size = 1 the logic is very simple:
+   * data = addr;  
+   * data_inv = ~data_inv
+   */
+  if (1 == data_size) {
+    print_verilog_wire_connection(fp, data_port, addr_port, false);
+    print_verilog_wire_connection(fp, data_inv_port, addr_port, true);
+    print_verilog_comment(fp, std::string("----- END Verilog codes for Decoder convert " + std::to_string(addr_size) + "-bit addr to " + std::to_string(data_size) + "-bit data -----"));
+
+    /* Put an end to the Verilog module */
+    print_verilog_module_end(fp, module_name);
+    return;
+  }
+
+  /* We use a magic number -1 as the addr=1 should be mapped to ...1
+   * Otherwise addr will map addr=1 to ..10 
+   * Note that there should be a range for the shift operators
+   * We should narrow the encoding to be applied to a given set of data
+   * This will lead to that any addr which falls out of the op code of data
+   * will give a all-zero code
+   * For example: 
+   * data is 5-bit while addr is 3-bit 
+   * data=8'b0_0000 will be encoded to addr=3'b001;
+   * data=8'b0_0001 will be encoded to addr=3'b010;
+   * data=8'b0_0010 will be encoded to addr=3'b011;
+   * data=8'b0_0100 will be encoded to addr=3'b100;
+   * data=8'b0_1000 will be encoded to addr=3'b101;
+   * data=8'b1_0000 will be encoded to addr=3'b110;
+   * The rest of addr codes 3'b110, 3'b111 will be decoded to data=8'b0_0000;
+   */
+
+  fp << "\t" << "always@(" << generate_verilog_port(VERILOG_PORT_CONKT, addr_port) << ")" << std::endl;
+  fp << "\t" << "case (" << generate_verilog_port(VERILOG_PORT_CONKT, addr_port) << ")" << std::endl;
+  /* Create a string for addr and data */
+  for (size_t i = 0; i < data_size; ++i) {
+    fp << "\t\t" << generate_verilog_constant_values(itobin_vec(i, addr_size)); 
+    fp << " : ";
+    fp << generate_verilog_port_constant_values(data_port, ito1hot_vec(i, data_size)); 
+    fp << ";" << std::endl;
+  }
+  fp << "\t\t" << "default : ";
+  fp << generate_verilog_port_constant_values(data_port, ito1hot_vec(data_size - 1, data_size)); 
+  fp << ";" << std::endl;
+  fp << "\t" << "endcase" << std::endl;
+
+  print_verilog_wire_connection(fp, data_inv_port, data_port, true);
+  
+  print_verilog_comment(fp, std::string("----- END Verilog codes for Decoder convert " + std::to_string(addr_size) + "-bit addr to " + std::to_string(data_size) + "-bit data -----"));
+
+  /* Put an end to the Verilog module */
+  print_verilog_module_end(fp, module_name);
+}
+
+
+/***************************************************************************************
+ * This function will generate all the unique Verilog modules of local decoders for 
+ * the multiplexers used in a FPGA fabric
+ * It will reach the goal in two steps:
+ * 1. Find the unique local decoders w.r.t. the number of inputs/outputs 
+ *    We will generate the subgraphs from the multiplexing graph of each multiplexers
+ *    The number of memory bits is the number of outputs.
+ *    From that we can infer the number of inputs of each local decoders.
+ *    Here is an illustrative example of how local decoders are interfaced with multi-level MUXes
+ *
+ *        +---------+         +---------+
+ *        |  Local  |         |  Local  |
+ *        | Decoder |         | Decoder |
+ *        |    A    |         |    B    |
+ *        +---------+         +---------+
+ *          | ... |             | ... |
+ *          v     v             v     v
+ *      +--------------+    +--------------+
+ *      |  MUX Level 0 |--->|  MUX Level 1 |
+ *      +--------------+    +--------------+
+ * 2. Generate local decoder Verilog modules using behavioral description.
+ *    Note that the implementation of local decoders can be dependent on the technology
+ *    and standard cell libraries.
+ *    Therefore, behavioral Verilog is used and the local decoders should be synthesized 
+ *    before running the back-end flow for FPGA fabric 
+ *    See more details in the function print_verilog_mux_local_decoder() for more details
+ ***************************************************************************************/
+void print_verilog_submodule_mux_local_decoders(ModuleManager& module_manager,
+                                                std::vector<std::string>& netlist_names,
+                                                const MuxLibrary& mux_lib,
+                                                const CircuitLibrary& circuit_lib,
+                                                const std::string& verilog_dir,
+                                                const std::string& submodule_dir) {
+  std::string verilog_fname(submodule_dir + std::string(LOCAL_ENCODER_VERILOG_FILE_NAME));
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
+
+  check_file_stream(verilog_fname.c_str(), fp);
+
+  /* Print out debugging information for if the file is not opened/created properly */
+  VTR_LOG("Writing Verilog netlist for local decoders for multiplexers '%s'...",
+          verilog_fname.c_str()); 
+
+  print_verilog_file_header(fp, "Local Decoders for Multiplexers"); 
+
+  print_verilog_include_defines_preproc_file(fp, verilog_dir);
+
+  /* Create a library for local encoders with different sizes */
+  DecoderLibrary decoder_lib;
+  
+  /* Find unique local decoders for unique branches shared by the multiplexers */
+  for (auto mux : mux_lib.muxes()) {
+    /* Local decoders are need only when users specify them */
+    CircuitModelId mux_circuit_model = mux_lib.mux_circuit_model(mux); 
+    /* If this MUX does not need local decoder, we skip it */
+    if (false == circuit_lib.mux_use_local_encoder(mux_circuit_model)) {
+      continue;
+    }
+
+    const MuxGraph& mux_graph = mux_lib.mux_graph(mux);
+    /* Create a mux graph for the branch circuit */
+    std::vector<MuxGraph> branch_mux_graphs = mux_graph.build_mux_branch_graphs();
+    /* Add the decoder to the decoder library */
+    for (auto branch_mux_graph : branch_mux_graphs) {
+      /* The decoder size depends on the number of memories of a branch MUX.
+       * Note that only when there are >=2 memories, a decoder is needed
+       */
+      size_t decoder_data_size = branch_mux_graph.num_memory_bits();
+      if (0 == decoder_data_size) {
+        continue;
+      }
+      /* Try to find if the decoder already exists in the library, 
+       * If there is no such decoder, add it to the library 
+       */
+      add_mux_local_decoder_to_library(decoder_lib, decoder_data_size);
+    }
+  }
+
+  /* Generate Verilog modules for the found unique local encoders */
+  for (const auto& decoder : decoder_lib.decoders()) {
+    print_verilog_mux_local_decoder_module(fp, module_manager, decoder_lib, decoder);
+  }
+
+  /* Close the file stream */
+  fp.close();
+
+  /* Add fname to the netlist name list */
+  netlist_names.push_back(verilog_fname);
+
+  VTR_LOG("Done\n");
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_verilog/verilog_decoders.h b/openfpga/src/fpga_verilog/verilog_decoders.h
new file mode 100644
index 000000000..41f932932
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_decoders.h
@@ -0,0 +1,32 @@
+#ifndef VERILOG_DECODERS_H
+#define VERILOG_DECODERS_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <fstream>
+#include <string>
+#include <vector>
+
+#include "circuit_library.h"
+#include "mux_graph.h"
+#include "mux_library.h"
+#include "module_manager.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void print_verilog_submodule_mux_local_decoders(ModuleManager& module_manager,
+                                                std::vector<std::string>& netlist_names,
+                                                const MuxLibrary& mux_lib,
+                                                const CircuitLibrary& circuit_lib,
+                                                const std::string& verilog_dir,
+                                                const std::string& submodule_dir);
+
+} /* end namespace openfpga */
+
+#endif

From c9d8120ae09b3c7ffda1d294931562ef4f4c6963 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 16 Feb 2020 12:35:41 -0700
Subject: [PATCH 154/645] adapt Verilog mux writer

---
 openfpga/src/fpga_verilog/verilog_constants.h |    2 +
 openfpga/src/fpga_verilog/verilog_mux.cpp     | 1281 +++++++++++++++++
 openfpga/src/fpga_verilog/verilog_mux.h       |   32 +
 3 files changed, 1315 insertions(+)
 create mode 100644 openfpga/src/fpga_verilog/verilog_mux.cpp
 create mode 100644 openfpga/src/fpga_verilog/verilog_mux.h

diff --git a/openfpga/src/fpga_verilog/verilog_constants.h b/openfpga/src/fpga_verilog/verilog_constants.h
index 9562bd730..49a73bf6d 100644
--- a/openfpga/src/fpga_verilog/verilog_constants.h
+++ b/openfpga/src/fpga_verilog/verilog_constants.h
@@ -41,4 +41,6 @@ constexpr char* ESSENTIALS_VERILOG_FILE_NAME = "inv_buf_passgate.v";
 constexpr char* CONFIG_PERIPHERAL_VERILOG_FILE_NAME = "config_peripherals.v";
 constexpr char* USER_DEFINED_TEMPLATE_VERILOG_FILE_NAME = "user_defined_templates.v";
 
+constexpr char* VERILOG_MUX_BASIS_POSTFIX = "_basis";
+
 #endif
diff --git a/openfpga/src/fpga_verilog/verilog_mux.cpp b/openfpga/src/fpga_verilog/verilog_mux.cpp
new file mode 100644
index 000000000..b78a9362a
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_mux.cpp
@@ -0,0 +1,1281 @@
+/***********************************************
+ * This file includes functions to generate
+ * Verilog submodules for multiplexers.
+ * including both fundamental submodules
+ * such as a branch in a multiplexer 
+ * and the full multiplexer
+ **********************************************/
+#include <string>
+#include <algorithm>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+/* Headers from readarch library */
+#include "physical_types.h"
+
+/* Headers from readarcopenfpga library */
+#include "circuit_types.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_digest.h"
+
+#include "mux_graph.h"
+#include "module_manager.h"
+#include "mux_utils.h"
+#include "circuit_library_utils.h"
+#include "decoder_library_utils.h"
+
+#include "openfpga_naming.h"
+
+#include "verilog_constants.h"
+#include "verilog_writer_utils.h"
+#include "verilog_module_writer.h"
+#include "verilog_mux.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/*********************************************************************
+ * Generate behavior-level Verilog codes modeling an branch circuit 
+ * for a multiplexer with the given size 
+ *********************************************************************/
+static 
+void generate_verilog_cmos_mux_branch_body_behavioral(std::fstream& fp,
+                                                      const BasicPort& input_port,
+                                                      const BasicPort& output_port,
+                                                      const BasicPort& mem_port,
+                                                      const MuxGraph& mux_graph,
+                                                      const size_t& default_mem_val) {
+  /* Make sure we have a valid file handler*/
+  VTR_ASSERT(true == valid_file_stream(fp));
+
+  /* Verilog Behavior description for a MUX */
+  print_verilog_comment(fp, std::string("---- Behavioral-level description -----"));
+
+  /* Add an internal register for the output */
+  BasicPort outreg_port("out_reg", mux_graph.num_outputs());
+  /* Print the port */
+  fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, outreg_port) << ";" << std::endl; 
+
+  /* Generate the case-switch table */
+  fp << "\talways @(" << generate_verilog_port(VERILOG_PORT_CONKT, input_port) << ", " << generate_verilog_port(VERILOG_PORT_CONKT, mem_port) << ")" << std::endl; 
+  fp << "\tcase (" << generate_verilog_port(VERILOG_PORT_CONKT, mem_port) << ")" << std::endl;
+
+  /* Output the netlist following the connections in mux_graph */
+  /* Iterate over the inputs */
+  for (const auto& mux_input : mux_graph.inputs()) {
+    BasicPort cur_input_port(input_port.get_name(), size_t(mux_graph.input_id(mux_input)), size_t(mux_graph.input_id(mux_input)));
+    /* Iterate over the outputs */
+    for (const auto& mux_output : mux_graph.outputs()) {
+      BasicPort cur_output_port(output_port.get_name(), size_t(mux_graph.output_id(mux_output)), size_t(mux_graph.output_id(mux_output)));
+      /* if there is a connection between the input and output, a tgate will be outputted */
+      std::vector<MuxEdgeId> edges = mux_graph.find_edges(mux_input, mux_output);
+      /* There should be only one edge or no edge*/
+      VTR_ASSERT((1 == edges.size()) || (0 == edges.size()));
+      /* No need to output tgates if there are no edges between two nodes */
+      if (0 == edges.size()) {
+        continue;
+      }
+      /* For each case, generate the logic levels for all the inputs */
+      /* In each case, only one mem is enabled */
+      fp << "\t\t" << mem_port.get_width() << "'b";
+      std::string case_code(mem_port.get_width(), default_mem_val);
+
+      /* Find the mem_id controlling the edge */
+      MuxMemId mux_mem = mux_graph.find_edge_mem(edges[0]);
+      /* Flip a bit by the mem_id */
+      if (false == mux_graph.is_edge_use_inv_mem(edges[0])) {
+        case_code[size_t(mux_mem)] = '1';
+      } else {
+        case_code[size_t(mux_mem)] = '0';
+      }
+      fp << case_code << ": " << generate_verilog_port(VERILOG_PORT_CONKT, outreg_port) << " <= ";
+      fp << generate_verilog_port(VERILOG_PORT_CONKT, cur_input_port) << ";" << std::endl;
+    }
+  }
+
+  /* Default case: outputs are at high-impedance state 'z' */
+  std::string default_case(mux_graph.num_outputs(), 'z');
+  fp << "\t\tdefault: " << generate_verilog_port(VERILOG_PORT_CONKT, outreg_port) << " <= ";
+  fp << mux_graph.num_outputs() << "'b" << default_case << ";" << std::endl;
+
+  /* End the case */
+  fp << "\tendcase" << std::endl;
+
+  /* Wire registers to output ports */
+  fp << "\tassign " << generate_verilog_port(VERILOG_PORT_CONKT, output_port) << " = ";
+  fp << generate_verilog_port(VERILOG_PORT_CONKT, outreg_port) << ";" << std::endl;
+}
+
+/*********************************************************************
+ * Generate  Verilog codes modeling an branch circuit 
+ * for a CMOS multiplexer with the given size 
+ * Support structural and behavioral Verilog codes
+ *********************************************************************/
+static 
+void print_verilog_cmos_mux_branch_module_behavioral(ModuleManager& module_manager,
+                                                     const CircuitLibrary& circuit_lib, 
+                                                     std::fstream& fp,
+                                                     const CircuitModelId& mux_model, 
+                                                     const std::string& module_name, 
+                                                     const MuxGraph& mux_graph) {
+  /* Get the tgate model */
+  CircuitModelId tgate_model = circuit_lib.pass_gate_logic_model(mux_model);
+
+  /* Skip output if the tgate model is a MUX2, it is handled by essential-gate generator */
+  if (CIRCUIT_MODEL_GATE == circuit_lib.model_type(tgate_model)) {
+    VTR_ASSERT(CIRCUIT_MODEL_GATE_MUX2 == circuit_lib.gate_type(tgate_model));
+    return;
+  }
+
+  /* Make sure we have a valid file handler*/
+  VTR_ASSERT(true == valid_file_stream(fp));
+
+  /* Generate the Verilog netlist according to the mux_graph */
+  /* Find out the number of inputs */ 
+  size_t num_inputs = mux_graph.num_inputs();
+  /* Find out the number of outputs */ 
+  size_t num_outputs = mux_graph.num_outputs();
+  /* Find out the number of memory bits */ 
+  size_t num_mems = mux_graph.num_memory_bits();
+
+  /* Check codes to ensure the port of Verilog netlists will match */
+  /* MUX graph must have only 1 output */
+  VTR_ASSERT(1 == num_outputs);
+  /* MUX graph must have only 1 level*/
+  VTR_ASSERT(1 == mux_graph.num_levels());
+
+  /* Create a Verilog Module based on the circuit model, and add to module manager */
+  ModuleId mux_module = module_manager.find_module(module_name); 
+  VTR_ASSERT(true == module_manager.valid_module_id(mux_module));
+  /* Find module ports */
+  /* Find each input port */
+  BasicPort input_port("in", num_inputs);
+  /* Find each output port */
+  BasicPort output_port("out", num_outputs);
+  /* Find each memory port */
+  BasicPort mem_port("mem", num_mems);
+
+  /* dump module definition + ports */
+  print_verilog_module_declaration(fp, module_manager, mux_module);
+
+  /* Print the internal logic in behavioral Verilog codes */
+  /* Get the default value of SRAM ports */
+  std::vector<CircuitPortId> regular_sram_ports = find_circuit_regular_sram_ports(circuit_lib, mux_model); 
+  VTR_ASSERT(1 == regular_sram_ports.size());
+  std::string mem_default_val = std::to_string(circuit_lib.port_default_value(regular_sram_ports[0]));
+  /* Mem string must be only 1-bit! */
+  VTR_ASSERT(1 == mem_default_val.length());
+  generate_verilog_cmos_mux_branch_body_behavioral(fp, input_port, output_port, mem_port, mux_graph, mem_default_val[0]);
+
+  /* Put an end to the Verilog module */
+  print_verilog_module_end(fp, module_name);
+}
+
+/*********************************************************************
+ * Dump a structural verilog for RRAM MUX basis module 
+ * This is only called when structural verilog dumping option is enabled for this spice model
+ * IMPORTANT: the structural verilog can NOT be used for functionality verification!!!
+ * TODO: This part is quite restricted to the way we implemented our RRAM FPGA
+ *       Should be reworked to be more generic !!!
+ *
+ * By structural the schematic is splitted into two parts: left part and right part
+ * The left part includes BLB[0..N-1] and WL[0..N-1] signals as well as RRAMs
+ * The right part includes BLB[N] and WL[N] 
+ * Corresponding Schematic is as follows:
+ *
+ *      LEFT PART   |    RIGHT PART
+ *
+ *         BLB[0]         BLB[N]
+ *            |             |
+ *           \|/           \|/
+ *   in[0] ---->RRAM[0]-----+
+ *                          |
+ *         BLB[1]           |
+ *           |              |
+ *          \|/             |
+ *   in[1] ---->RRAM[1]-----+ 
+ *                          |-----> out[0]
+ *              ...         
+ *                          |
+ * in[N-1] ---->RRAM[N-1]---+ 
+ *           /|\           /|\
+ *            |             |
+ *          BLB[N-1]       WL[N]
+ *
+ * Working principle:
+ * 1. Set a RRAM[i]: enable BLB[i] and WL[N]
+ * 2. Reset a RRAM[i]: enable BLB[N] and WL[i]
+ * 3. Operation: disable all BLBs and WLs
+ *
+ * The structure is done in the way we implement the physical layout of RRAM MUX
+ * It is NOT the only road to the goal!!!
+ *********************************************************************/
+static 
+void generate_verilog_rram_mux_branch_body_structural(ModuleManager& module_manager,
+                                                      const CircuitLibrary& circuit_lib, 
+                                                      std::fstream& fp,
+                                                      const ModuleId& module_id, 
+                                                      const CircuitModelId& circuit_model, 
+                                                      const BasicPort& input_port,
+                                                      const BasicPort& output_port,
+                                                      const BasicPort& blb_port,
+                                                      const BasicPort& wl_port,
+                                                      const MuxGraph& mux_graph) {
+  std::string progTE_module_name("PROG_TE");
+  std::string progBE_module_name("PROG_BE");  
+
+  /* Make sure we have a valid file handler*/
+  VTR_ASSERT(true == valid_file_stream(fp));
+
+  /* Verilog Behavior description for a MUX */
+  print_verilog_comment(fp, std::string("---- Structure-level description of RRAM MUX -----"));
+
+  /* Print internal structure of 4T1R programming structures
+   * Written in structural Verilog
+   * The whole structure-level description is divided into two parts:
+   * 1. Left part consists of N PROG_TE modules, each of which
+   * includes a PMOS, a NMOS and a RRAM, which is actually the left
+   * part of a 4T1R programming structure 
+   * 2. Right part includes only a PROG_BE module, which consists
+   * of a PMOS and a NMOS, which is actually the right part of a
+   * 4T1R programming sturcture
+   */
+  /* Create a module for the progTE and register it in the module manager 
+   * Structure of progTE
+   *
+   *        +----------+
+   *  in--->|          |
+   *  BLB-->|  progTE  |--> out
+   *  WL--->|          |
+   *        +----------+
+   */
+  ModuleId progTE_module_id = module_manager.add_module(progTE_module_name);
+  /* If there is already such as module inside, we just ned to find the module id */
+  if (ModuleId::INVALID() == progTE_module_id) {
+    progTE_module_id = module_manager.find_module(progTE_module_name);
+    /* We should have a valid id! */
+    VTR_ASSERT(ModuleId::INVALID() != progTE_module_id);
+  }
+  /* Add ports to the module */
+  /* input port */
+  BasicPort progTE_in_port("A", 1);
+  module_manager.add_port(progTE_module_id, progTE_in_port, ModuleManager::MODULE_INPUT_PORT);
+  /* WL port */
+  BasicPort progTE_wl_port("WL", 1);
+  module_manager.add_port(progTE_module_id, progTE_wl_port, ModuleManager::MODULE_INPUT_PORT);
+  /* BLB port */
+  BasicPort progTE_blb_port("BLB", 1);
+  module_manager.add_port(progTE_module_id, progTE_blb_port, ModuleManager::MODULE_INPUT_PORT);
+  /* output port */
+  BasicPort progTE_out_port("Z", 1);
+  module_manager.add_port(progTE_module_id, progTE_out_port, ModuleManager::MODULE_INPUT_PORT);
+
+  /* LEFT part: Verilog code generation */
+  /* Iterate over the inputs */
+  for (const auto& mux_input : mux_graph.inputs()) {
+    BasicPort cur_input_port(input_port.get_name(), size_t(mux_graph.input_id(mux_input)), size_t(mux_graph.input_id(mux_input)));
+    /* Iterate over the outputs */
+    for (const auto& mux_output : mux_graph.outputs()) {
+      BasicPort cur_output_port(output_port.get_name(), size_t(mux_graph.output_id(mux_output)), size_t(mux_graph.output_id(mux_output)));
+      /* if there is a connection between the input and output, a tgate will be outputted */
+      std::vector<MuxEdgeId> edges = mux_graph.find_edges(mux_input, mux_output);
+      /* There should be only one edge or no edge*/
+      VTR_ASSERT((1 == edges.size()) || (0 == edges.size()));
+      /* No need to output tgates if there are no edges between two nodes */
+      if (0 == edges.size()) {
+        continue;
+      }
+      /* Create a port-to-port name map */
+      std::map<std::string, BasicPort> port2port_name_map;
+      /* input port */
+      port2port_name_map[progTE_in_port.get_name()] = cur_input_port;
+      /* output port */
+      port2port_name_map[progTE_out_port.get_name()] = cur_output_port;
+      /* Find the mem_id controlling the edge */
+      MuxMemId mux_mem = mux_graph.find_edge_mem(edges[0]);
+      BasicPort cur_blb_port(blb_port.get_name(), size_t(mux_mem), size_t(mux_mem));
+      BasicPort cur_wl_port(wl_port.get_name(), size_t(mux_mem), size_t(mux_mem));
+      /* RRAM configuration port: there should not be any inverted edge in RRAM MUX! */
+      VTR_ASSERT( false == mux_graph.is_edge_use_inv_mem(edges[0]) );
+      /* wire mem to mem of module, and wire mem_inv to mem_inv of module */
+      port2port_name_map[progTE_blb_port.get_name()] = cur_blb_port;
+      port2port_name_map[progTE_wl_port.get_name()] = cur_wl_port;
+      /* Output an instance of the module */
+      print_verilog_module_instance(fp, module_manager, module_id, progTE_module_id, port2port_name_map, circuit_lib.dump_explicit_port_map(circuit_model));
+      /* IMPORTANT: this update MUST be called after the instance outputting!!!!
+       * update the module manager with the relationship between the parent and child modules 
+       */
+      module_manager.add_child_module(module_id, progTE_module_id);
+    }
+  }
+
+  /* Create a module for the progBE and register it in the module manager 
+   * Structure of progBE
+   *
+   *        +----------+
+   *        |          |
+   *  BLB-->|  progBE  |<-> out
+   *  WL--->|          |
+   *        +----------+
+   */
+  ModuleId progBE_module_id = module_manager.add_module(progBE_module_name);
+  /* If there is already such as module inside, we just ned to find the module id */
+  if (ModuleId::INVALID() == progBE_module_id) {
+    progBE_module_id = module_manager.find_module(progBE_module_name);
+    /* We should have a valid id! */
+    VTR_ASSERT(ModuleId::INVALID() != progBE_module_id);
+  }
+  /* Add ports to the module */
+  /* inout port */
+  BasicPort progBE_inout_port("INOUT", 1);
+  module_manager.add_port(progBE_module_id, progBE_inout_port, ModuleManager::MODULE_INOUT_PORT);
+  /* WL port */
+  BasicPort progBE_wl_port("WL", 1);
+  module_manager.add_port(progBE_module_id, progBE_wl_port, ModuleManager::MODULE_INPUT_PORT);
+  /* BLB port */
+  BasicPort progBE_blb_port("BLB", 1);
+  module_manager.add_port(progBE_module_id, progBE_blb_port, ModuleManager::MODULE_INPUT_PORT);
+
+  /* RIGHT part: Verilog code generation */
+  /* Iterate over the outputs */
+  for (const auto& mux_output : mux_graph.outputs()) {
+    BasicPort cur_output_port(output_port.get_name(), size_t(mux_graph.output_id(mux_output)), size_t(mux_graph.output_id(mux_output)));
+    /* Create a port-to-port name map */
+    std::map<std::string, BasicPort> port2port_name_map;
+    /* Wire the output port to the INOUT port */
+    port2port_name_map[progBE_inout_port.get_name()] = cur_output_port;
+    /* Find the mem_id controlling the edge */
+    BasicPort cur_blb_port(blb_port.get_name(), mux_graph.num_memory_bits(), mux_graph.num_memory_bits());
+    BasicPort cur_wl_port(wl_port.get_name(), mux_graph.num_memory_bits(), mux_graph.num_memory_bits());
+    port2port_name_map[progBE_blb_port.get_name()] = cur_blb_port;
+    port2port_name_map[progBE_wl_port.get_name()] = cur_wl_port;
+    /* Output an instance of the module */
+    print_verilog_module_instance(fp, module_manager, module_id, progBE_module_id, port2port_name_map, circuit_lib.dump_explicit_port_map(circuit_model));
+    /* IMPORTANT: this update MUST be called after the instance outputting!!!!
+     * update the module manager with the relationship between the parent and child modules 
+     */
+    module_manager.add_child_module(module_id, progBE_module_id);
+  }
+}
+
+/*********************************************************************
+ * Generate behavior-level Verilog codes modeling an branch circuit 
+ * for a RRAM-based multiplexer with the given size 
+ * Corresponding Schematic is as follows:
+ *
+ *         BLB[0]         BLB[N]
+ *            |             |
+ *           \|/           \|/
+ *   in[0] ---->RRAM[0]-----+
+ *                          |
+ *         BLB[1]           |
+ *           |              |
+ *          \|/             |
+ *   in[1] ---->RRAM[1]-----+ 
+ *                          |-----> out[0]
+ *              ...         
+ *                          |
+ * in[N-1] ---->RRAM[N-1]---+ 
+ *           /|\           /|\
+ *            |             |
+ *          BLB[N-1]       WL[N]
+ *
+ * Working principle:
+ * 1. Set a RRAM[i]: enable BLB[i] and WL[N]
+ * 2. Reset a RRAM[i]: enable BLB[N] and WL[i]
+ * 3. Operation: disable all BLBs and WLs
+ *
+ * TODO: Elaborate the codes to output the circuit logic
+ * following the mux_graph! 
+ *********************************************************************/
+static 
+void generate_verilog_rram_mux_branch_body_behavioral(std::fstream& fp,
+                                                      const CircuitLibrary& circuit_lib, 
+                                                      const CircuitModelId& circuit_model, 
+                                                      const BasicPort& input_port,
+                                                      const BasicPort& output_port,
+                                                      const BasicPort& blb_port,
+                                                      const BasicPort& wl_port,
+                                                      const MuxGraph& mux_graph) {
+  /* Make sure we have a valid file handler*/
+  VTR_ASSERT(true == valid_file_stream(fp));
+
+  /* Verilog Behavior description for a MUX */
+  print_verilog_comment(fp, std::string("---- Behavioral-level description of RRAM MUX -----"));
+
+  /* Add an internal register for the output */
+  BasicPort outreg_port("out_reg", mux_graph.num_inputs());
+  /* Print the port */
+  fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, outreg_port) << ";" << std::endl; 
+
+  /* Print the internal logics */
+  fp << "\t" << "always @(";
+  fp << generate_verilog_port(VERILOG_PORT_CONKT, blb_port); 
+  fp << ", ";
+  fp << generate_verilog_port(VERILOG_PORT_CONKT, wl_port); 
+  fp << ")";
+  fp << " begin" << std::endl;
+
+  /* Only when the last bit of wl is enabled, 
+   * the propagating path can be changed 
+   * (RRAM value can be changed) */
+  fp << "\t\t" << "if (";
+  BasicPort set_enable_port(wl_port.get_name(), wl_port.get_width() - 1, wl_port.get_width() - 1); 
+  fp << generate_verilog_port(VERILOG_PORT_CONKT, set_enable_port); 
+  /* We need two config-enable ports: prog_EN and prog_ENb */
+  bool find_prog_EN = false;
+  bool find_prog_ENb = false;
+  for (const auto& port : circuit_lib.model_global_ports(circuit_model, true)) {
+    /* Bypass non-config-enable ports */
+    if (false == circuit_lib.port_is_config_enable(port)) {
+      continue;
+    }
+    /* Reach here, the port should be is_config_enable */   
+    /* Create a port object */
+    fp << " && "; 
+    BasicPort prog_en_port(circuit_lib.port_prefix(port), circuit_lib.port_size(port));
+    if ( 0 == circuit_lib.port_default_value(port)) {
+      /* Default value = 0 means that this is a prog_EN port */
+      fp << generate_verilog_port(VERILOG_PORT_CONKT, prog_en_port); 
+      find_prog_EN = true;
+    } else {
+      VTR_ASSERT ( 1 == circuit_lib.port_default_value(port));
+      /* Default value = 1 means that this is a prog_ENb port, add inversion in the if condition */
+      fp << "(~" << generate_verilog_port(VERILOG_PORT_CONKT, prog_en_port) << ")"; 
+      find_prog_ENb = true;
+    }
+  }
+  /* Check if we find any config_enable signals */
+  if (false == find_prog_EN) {
+    VTR_LOGF_ERROR(__FILE__, __LINE__, 
+                   "Unable to find a config_enable signal with default value 0 for a RRAM MUX '%s'!\n",
+                   circuit_lib.model_name(circuit_model).c_str()); 
+    exit(1);
+  }
+  if (false == find_prog_ENb) {
+    VTR_LOGF_ERROR(__FILE__, __LINE__, 
+                   "Unable to find a config_enable signal with default value 1 for a RRAM MUX '%s'!\n",
+                   circuit_lib.model_name(circuit_model).c_str()); 
+    exit(1);
+  }
+
+  /* Finish the if clause */
+  fp << ") begin" << std::endl;
+
+  for (const auto& mux_input : mux_graph.inputs()) {
+    /* First if clause need tabs */
+    if ( 0 == size_t(mux_graph.input_id(mux_input)) ) {
+      fp << "\t\t\t";
+    }
+    fp << "if (1 == ";
+    /* Create a temp port of a BLB bit */
+    BasicPort cur_blb_port(blb_port.get_name(), size_t(mux_graph.input_id(mux_input)), size_t(mux_graph.input_id(mux_input)));
+    fp << generate_verilog_port(VERILOG_PORT_CONKT, cur_blb_port); 
+    fp << ") begin" << std::endl;
+    fp << "\t\t\t\t" << "assign ";
+  fp << outreg_port.get_name(); 
+    fp << " = " << size_t(mux_graph.input_id(mux_input)) << ";" << std::endl;
+    fp << "\t\t\t" << "end else ";
+  }
+  fp << "begin" << std::endl;
+  fp << "\t\t\t\t" << "assign ";
+  fp << outreg_port.get_name(); 
+  fp << " = 0;" << std::endl;
+  fp << "\t\t\t" << "end" << std::endl;
+  fp << "\t\t" << "end" << std::endl;
+  fp << "\t" << "end" << std::endl;
+ 
+  fp << "\t" << "assign ";
+  fp << generate_verilog_port(VERILOG_PORT_CONKT, output_port);
+  fp << " = "; 
+  fp << input_port.get_name() << "[";
+  fp << outreg_port.get_name(); 
+  fp << "];" << std::endl;
+}
+
+/*********************************************************************
+ * Generate  Verilog codes modeling an branch circuit 
+ * for a RRAM-based multiplexer with the given size 
+ * Support structural and behavioral Verilog codes
+ *********************************************************************/
+static 
+void generate_verilog_rram_mux_branch_module(ModuleManager& module_manager,
+                                             const CircuitLibrary& circuit_lib, 
+                                             std::fstream& fp,
+                                             const CircuitModelId& circuit_model, 
+                                             const std::string& module_name, 
+                                             const MuxGraph& mux_graph,
+                                             const bool& use_structural_verilog) {
+  /* Make sure we have a valid file handler*/
+  VTR_ASSERT(true == valid_file_stream(fp));
+
+  /* Get the input ports from the mux */
+  std::vector<CircuitPortId> mux_input_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true);
+  /* Get the output ports from the mux */
+  std::vector<CircuitPortId> mux_output_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
+  /* Get the BL and WL ports from the mux */
+  std::vector<CircuitPortId> mux_blb_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_BLB, true);
+  std::vector<CircuitPortId> mux_wl_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_WL, true);
+
+  /* Generate the Verilog netlist according to the mux_graph */
+  /* Find out the number of inputs */ 
+  size_t num_inputs = mux_graph.num_inputs();
+  /* Find out the number of outputs */ 
+  size_t num_outputs = mux_graph.num_outputs();
+  /* Find out the number of memory bits */ 
+  size_t num_mems = mux_graph.num_memory_bits();
+
+  /* Check codes to ensure the port of Verilog netlists will match */
+  /* MUX graph must have only 1 output */
+  VTR_ASSERT(1 == num_outputs);
+  /* MUX graph must have only 1 level*/
+  VTR_ASSERT(1 == mux_graph.num_levels());
+  /* MUX graph must have only 1 input and 1 BLB and 1 WL port */
+  VTR_ASSERT(1 == mux_input_ports.size());
+  VTR_ASSERT(1 == mux_output_ports.size());
+  VTR_ASSERT(1 == mux_blb_ports.size());
+  VTR_ASSERT(1 == mux_wl_ports.size());
+
+  /* Create a Verilog Module based on the circuit model, and add to module manager */
+  ModuleId module_id = module_manager.find_module(module_name); 
+  VTR_ASSERT(true == module_manager.valid_module_id(module_id));
+
+  /* Find each input port */
+  BasicPort input_port(circuit_lib.port_prefix(mux_input_ports[0]), num_inputs);
+
+  /* Find each output port */
+  BasicPort output_port(circuit_lib.port_prefix(mux_output_ports[0]), num_outputs);
+
+  /* Find RRAM programming ports, 
+   * RRAM MUXes require one more pair of BLB and WL 
+   * to configure the memories. See schematic for details
+   */
+  BasicPort blb_port(circuit_lib.port_prefix(mux_blb_ports[0]), num_mems + 1);
+
+  BasicPort wl_port(circuit_lib.port_prefix(mux_wl_ports[0]), num_mems + 1);
+
+  /* dump module definition + ports */
+  print_verilog_module_declaration(fp, module_manager, module_id);
+
+  /* Print the internal logic in either structural or behavioral Verilog codes */
+  if (true == use_structural_verilog) {
+    generate_verilog_rram_mux_branch_body_structural(module_manager, circuit_lib, fp, module_id, circuit_model, input_port, output_port, blb_port, wl_port, mux_graph);
+  } else {
+    generate_verilog_rram_mux_branch_body_behavioral(fp, circuit_lib, circuit_model, input_port, output_port, blb_port, wl_port, mux_graph);
+  }
+
+  /* Put an end to the Verilog module */
+  print_verilog_module_end(fp, module_name);
+}
+
+/***********************************************
+ * Generate Verilog codes modeling an branch circuit 
+ * for a multiplexer with the given size 
+ **********************************************/
+static 
+void generate_verilog_mux_branch_module(ModuleManager& module_manager,
+                                        const CircuitLibrary& circuit_lib, 
+                                        std::fstream& fp, 
+                                        const CircuitModelId& mux_model, 
+                                        const size_t& mux_size, 
+                                        const MuxGraph& mux_graph,
+                                        const bool& use_explicit_port_map) {
+  std::string module_name = generate_mux_branch_subckt_name(circuit_lib, mux_model, mux_size, mux_graph.num_inputs(), VERILOG_MUX_BASIS_POSTFIX);
+
+  /* Multiplexers built with different technology is in different organization */
+  switch (circuit_lib.design_tech_type(mux_model)) {
+  case CIRCUIT_MODEL_DESIGN_CMOS:
+    /* Skip module writing if the branch subckt is a standard cell! */
+    if (true == circuit_lib.valid_model_id(circuit_lib.model(module_name))) {
+      /* This model must be a MUX2 gate */
+      VTR_ASSERT(CIRCUIT_MODEL_GATE == circuit_lib.model_type(circuit_lib.model(module_name)));
+      VTR_ASSERT(CIRCUIT_MODEL_GATE_MUX2 == circuit_lib.gate_type(circuit_lib.model(module_name)));
+      break;
+    }
+    if (true == circuit_lib.dump_structural_verilog(mux_model)) {
+      /* Structural verilog can be easily generated by module writer */
+      ModuleId mux_module = module_manager.find_module(module_name);
+      VTR_ASSERT(true == module_manager.valid_module_id(mux_module));
+      write_verilog_module_to_file(fp, module_manager, mux_module, 
+                                   use_explicit_port_map || circuit_lib.dump_explicit_port_map(mux_model));
+      /* Add an empty line as a splitter */
+      fp << std::endl;
+    } else {
+      /* Behavioral verilog requires customized generation */
+      print_verilog_cmos_mux_branch_module_behavioral(module_manager, circuit_lib, fp, mux_model, module_name, mux_graph);
+    }
+    break;
+  case CIRCUIT_MODEL_DESIGN_RRAM:
+    generate_verilog_rram_mux_branch_module(module_manager, circuit_lib, fp, mux_model, module_name, mux_graph, 
+                                            circuit_lib.dump_structural_verilog(mux_model));
+    break;
+  default:
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid design technology of multiplexer '%s'\n",
+                   circuit_lib.model_name(mux_model).c_str()); 
+    exit(1);
+  }
+}
+
+/********************************************************************
+ * Generate the input bufferes for a multiplexer or LUT in Verilog codes 
+ * 1. If input are required to be buffered (specified by users),
+ *    buffers will be added to all the datapath inputs.
+ * 2. If input are required to NOT be buffered (specified by users),
+ *    all the datapath inputs will be short wired to MUX inputs. 
+ *
+ * For those Multiplexers or LUTs require a constant input:
+ *    the last input of multiplexer will be wired to a constant voltage level
+ *******************************************************************/
+static 
+void generate_verilog_cmos_mux_module_input_buffers(ModuleManager& module_manager,
+                                                    const CircuitLibrary& circuit_lib, 
+                                                    std::fstream& fp, 
+                                                    const ModuleId& module_id, 
+                                                    const CircuitModelId& circuit_model, 
+                                                    const MuxGraph& mux_graph) {
+  /* Make sure we have a valid file handler*/
+  VTR_ASSERT(true == valid_file_stream(fp));
+
+  /* Get the input ports from the mux */
+  std::vector<CircuitPortId> mux_input_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true);
+  /* We should have only 1 input port! */
+  VTR_ASSERT(1 == mux_input_ports.size());
+
+  /* Get the input port from MUX module */
+  ModulePortId module_input_port_id = module_manager.find_module_port(module_id, circuit_lib.port_prefix(mux_input_ports[0]));
+  VTR_ASSERT(ModulePortId::INVALID() != module_input_port_id);
+  /* Get the port from module */
+  BasicPort module_input_port = module_manager.module_port(module_id, module_input_port_id);
+
+  /* Iterate over all the inputs in the MUX graph */
+  for (const auto& input_node : mux_graph.inputs()) {
+    /* Fetch fundamental information from MUX graph w.r.t. the input node */
+    MuxInputId input_index = mux_graph.input_id(input_node);
+    VTR_ASSERT(MuxInputId::INVALID() != input_index);   
+ 
+    size_t input_node_level = mux_graph.node_level(input_node);
+    size_t input_node_index_at_level = mux_graph.node_index_at_level(input_node);
+
+    /* Create the port information of the MUX input, which is the input of buffer instance */
+    BasicPort instance_input_port(module_input_port.get_name(), size_t(input_index), size_t(input_index));
+
+    /* Create the port information of the MUX graph input, which is the output of buffer instance */
+    BasicPort instance_output_port(generate_mux_node_name(input_node_level, false), input_node_index_at_level, input_node_index_at_level);
+
+    /* For last input:
+     * Add a constant value to the last input, if this MUX needs a constant input
+     */
+    if (  (MuxInputId(mux_graph.num_inputs() - 1) == mux_graph.input_id(input_node)) 
+       && (true == circuit_lib.mux_add_const_input(circuit_model)) ) {
+      /* Get the constant input value */
+      size_t const_value = circuit_lib.mux_const_input_value(circuit_model);
+      VTR_ASSERT( (0 == const_value) || (1 == const_value) ); 
+      /* For the output of the buffer instance:
+       * Get the last inputs from the MUX graph and generate the node name in MUX module.
+       */
+      print_verilog_comment(fp, std::string("---- BEGIN short-wire a multiplexing structure input to a constant value -----"));
+      print_verilog_wire_constant_values(fp, instance_output_port, std::vector<size_t>(1, const_value));
+      print_verilog_comment(fp, std::string("---- END short-wire a multiplexing structure input to a constant value -----"));
+      fp << std::endl;
+      continue; /* Finish here */
+    }
+
+    /* If the inputs are not supposed to be buffered */
+    if (false == circuit_lib.is_input_buffered(circuit_model)) {
+      print_verilog_comment(fp, std::string("---- BEGIN short-wire a multiplexing structure input to MUX module input -----"));
+
+      /* Short wire all the datapath inputs to the MUX inputs */
+      print_verilog_wire_connection(fp, instance_output_port, instance_input_port, false);      
+
+      print_verilog_comment(fp, std::string("---- END short-wire a multiplexing structure input to MUX module input -----"));
+      fp << std::endl;
+      continue; /* Finish here */
+    }
+
+    /* Reach here, we need a buffer, create a port-to-port map and output the buffer instance */
+    print_verilog_comment(fp, std::string("---- BEGIN Instanciation of an input buffer module -----"));
+
+    /* Now we need to add intermediate buffers by instanciating the modules */
+    CircuitModelId buffer_model = circuit_lib.input_buffer_model(circuit_model);
+    /* We must have a valid model id */
+    VTR_ASSERT(CircuitModelId::INVALID() != buffer_model);
+
+    print_verilog_buffer_instance(fp, module_manager, circuit_lib, module_id, buffer_model, instance_input_port, instance_output_port);
+
+    print_verilog_comment(fp, std::string("---- END Instanciation of an input buffer module -----"));
+    fp << std::endl;
+  } 
+}
+
+/********************************************************************
+ * Generate the output bufferes for a multiplexer or LUT in Verilog codes 
+ * 1. If output are required to be buffered (specified by users),
+ *    buffers will be added to all the outputs.
+ * 2. If output are required to NOT be buffered (specified by users),
+ *    all the outputs will be short wired to MUX outputs. 
+ *******************************************************************/
+static 
+void generate_verilog_cmos_mux_module_output_buffers(ModuleManager& module_manager,
+                                                     const CircuitLibrary& circuit_lib, 
+                                                     std::fstream& fp, 
+                                                     const ModuleId& module_id, 
+                                                     const CircuitModelId& circuit_model, 
+                                                     const MuxGraph& mux_graph) {
+  /* Make sure we have a valid file handler*/
+  VTR_ASSERT(true == valid_file_stream(fp));
+
+  /* Get the output ports from the mux */
+  std::vector<CircuitPortId> mux_output_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
+
+  /* Iterate over all the outputs in the MUX module */
+  for (const auto& output_port : mux_output_ports) {
+    /* Get the output port from MUX module */
+    ModulePortId module_output_port_id = module_manager.find_module_port(module_id, circuit_lib.port_prefix(output_port));
+    VTR_ASSERT(ModulePortId::INVALID() != module_output_port_id);
+    /* Get the port from module */
+    BasicPort module_output_port = module_manager.module_port(module_id, module_output_port_id);
+
+    /* Iterate over each pin of the output port */
+    for (const auto& pin : circuit_lib.pins(output_port)) {
+      /* Fetch fundamental information from MUX graph w.r.t. the input node */
+      /* Deposite the last level of the graph, which is a default value */
+      size_t output_node_level = mux_graph.num_node_levels() - 1; 
+      /* If there is a fracturable level specified for the output, we find the exact level */
+      if (size_t(-1) != circuit_lib.port_lut_frac_level(output_port)) {
+        output_node_level = circuit_lib.port_lut_frac_level(output_port);
+      }
+      /* Deposite a zero, which is a default value */
+      size_t output_node_index_at_level = 0; 
+      /* If there are output masks, we find the node_index */
+      if (!circuit_lib.port_lut_output_mask(output_port).empty()) {
+        output_node_index_at_level = circuit_lib.port_lut_output_mask(output_port).at(pin);
+      } 
+      /* Double check the node exists in the Mux Graph */
+      VTR_ASSERT(MuxNodeId::INVALID() != mux_graph.node_id(output_node_level, output_node_index_at_level));
+
+      /* Create the port information of the MUX input, which is the input of buffer instance */
+      BasicPort instance_input_port(generate_mux_node_name(output_node_level, false), output_node_index_at_level, output_node_index_at_level);
+
+      /* Create the port information of the module output at the given pin range, which is the output of buffer instance */
+      BasicPort instance_output_port(module_output_port.get_name(), pin, pin);
+
+      /* If the output is not supposed to be buffered */
+      if (false == circuit_lib.is_output_buffered(circuit_model)) {
+        print_verilog_comment(fp, std::string("---- BEGIN short-wire a multiplexing structure output to MUX module output -----"));
+
+        /* Short wire all the datapath inputs to the MUX inputs */
+        print_verilog_wire_connection(fp, instance_output_port, instance_input_port, false);      
+
+        print_verilog_comment(fp, std::string("---- END short-wire a multiplexing structure output to MUX module output -----"));
+        fp << std::endl;
+        continue; /* Finish here */
+      }
+
+      /* Reach here, we need a buffer, create a port-to-port map and output the buffer instance */
+      print_verilog_comment(fp, std::string("---- BEGIN Instanciation of an output buffer module -----"));
+
+      /* Now we need to add intermediate buffers by instanciating the modules */
+      CircuitModelId buffer_model = circuit_lib.output_buffer_model(circuit_model);
+      /* We must have a valid model id */
+      VTR_ASSERT(CircuitModelId::INVALID() != buffer_model);
+
+      print_verilog_buffer_instance(fp, module_manager, circuit_lib, module_id, buffer_model, instance_input_port, instance_output_port);
+
+      print_verilog_comment(fp, std::string("---- END Instanciation of an output buffer module -----"));
+      fp << std::endl;
+    }
+  }
+}
+
+/********************************************************************
+ * Generate the 4T1R-based internal logic 
+ * (multiplexing structure) for a multiplexer in Verilog codes 
+ * This function will : 
+ * 1. build a multiplexing structure by instanciating the branch circuits
+ *    generated before
+ * 2. add intermediate buffers between multiplexing stages if specified.
+ *******************************************************************/
+static 
+void generate_verilog_rram_mux_module_multiplexing_structure(ModuleManager& module_manager,
+                                                             const CircuitLibrary& circuit_lib, 
+                                                             std::fstream& fp, 
+                                                             const ModuleId& module_id, 
+                                                             const CircuitModelId& circuit_model, 
+                                                             const MuxGraph& mux_graph) {
+  /* Make sure we have a valid file handler*/
+  VTR_ASSERT(true == valid_file_stream(fp));
+
+  /* Find the actual mux size */
+  size_t mux_size = find_mux_num_datapath_inputs(circuit_lib, circuit_model, mux_graph.num_inputs());
+
+  /* Get the BL and WL ports from the mux */
+  std::vector<CircuitPortId> mux_blb_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_BLB, true);
+  std::vector<CircuitPortId> mux_wl_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_WL, true);
+  /* MUX graph must have only 1 BLB and 1 WL port */
+  VTR_ASSERT(1 == mux_blb_ports.size());
+  VTR_ASSERT(1 == mux_wl_ports.size());
+
+  /* Build the location map of intermediate buffers */
+  std::vector<bool> inter_buffer_location_map = build_mux_intermediate_buffer_location_map(circuit_lib, circuit_model, mux_graph.num_node_levels());
+
+  print_verilog_comment(fp, std::string("---- BEGIN Internal Logic of a RRAM-based MUX module -----"));
+
+  print_verilog_comment(fp, std::string("---- BEGIN Internal wires of a RRAM-based MUX module -----"));
+  /* Print local wires which are the nodes in the mux graph */
+  for (size_t level = 0; level < mux_graph.num_levels(); ++level) {
+    /* Print the internal wires located at this level */
+    BasicPort internal_wire_port(generate_mux_node_name(level, false), mux_graph.num_nodes_at_level(level));
+    fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, internal_wire_port) << ";" << std::endl;
+    /* Identify if an intermediate buffer is needed */
+    if (false == inter_buffer_location_map[level]) { 
+      continue;
+    }
+    BasicPort internal_wire_buffered_port(generate_mux_node_name(level, true), mux_graph.num_nodes_at_level(level));
+    fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, internal_wire_buffered_port) << std::endl;
+  }
+  print_verilog_comment(fp, std::string("---- END Internal wires of a RRAM-based MUX module -----"));
+  fp << std::endl;
+
+  /* Iterate over all the internal nodes and output nodes in the mux graph */
+  for (const auto& node : mux_graph.non_input_nodes()) {
+    print_verilog_comment(fp, std::string("---- BEGIN Instanciation of a branch RRAM-based MUX module -----"));
+    /* Get the size of branch circuit 
+     * Instanciate an branch circuit by the size (fan-in) of the node 
+     */
+    size_t branch_size = mux_graph.node_in_edges(node).size();
+
+    /* Get the node level and index in the current level */
+    size_t output_node_level = mux_graph.node_level(node);
+    size_t output_node_index_at_level = mux_graph.node_index_at_level(node);
+
+    /* Get the nodes which drive the root_node */
+    std::vector<MuxNodeId> input_nodes; 
+    for (const auto& edge : mux_graph.node_in_edges(node)) {
+      /* Get the nodes drive the edge */
+      for (const auto& src_node : mux_graph.edge_src_nodes(edge)) {
+        input_nodes.push_back(src_node);
+      }
+    }
+    /* Number of inputs should match the branch_input_size!!! */
+    VTR_ASSERT(input_nodes.size() == branch_size);
+
+    /* Get the mems in the branch circuits */
+    std::vector<MuxMemId> mems; 
+    for (const auto& edge : mux_graph.node_in_edges(node)) {
+      /* Get the mem control the edge */
+      MuxMemId mem = mux_graph.find_edge_mem(edge);
+      /* Add the mem if it is not in the list */
+      if (mems.end() == std::find(mems.begin(), mems.end(), mem)) {
+        mems.push_back(mem);
+      }
+    }
+
+    /* Instanciate the branch module which is a tgate-based module  
+     */
+    std::string branch_module_name= generate_mux_branch_subckt_name(circuit_lib, circuit_model, mux_size, branch_size, VERILOG_MUX_BASIS_POSTFIX);
+    /* Get the moduleId for the submodule */
+    ModuleId branch_module_id = module_manager.find_module(branch_module_name);
+    /* We must have one */
+    VTR_ASSERT(ModuleId::INVALID() != branch_module_id);
+
+    /* Create a port-to-port map */
+    std::map<std::string, BasicPort> port2port_name_map;
+    /* TODO: the branch module name should NOT be hard-coded. Use the port lib_name given by users! */
+
+    /* All the input node names organized in bus */
+    std::vector<BasicPort> branch_node_input_ports;
+    for (const auto& input_node : input_nodes) {
+      /* Generate the port info of each input node */
+      size_t input_node_level = mux_graph.node_level(input_node);
+      size_t input_node_index_at_level = mux_graph.node_index_at_level(input_node);
+      BasicPort branch_node_input_port(generate_mux_node_name(input_node_level, inter_buffer_location_map[input_node_level]), input_node_index_at_level, input_node_index_at_level);
+      branch_node_input_ports.push_back(branch_node_input_port);  
+    } 
+
+    /* Create the port info for the input */
+    /* TODO: the naming could be more flexible? */
+    BasicPort instance_input_port = generate_verilog_bus_port(branch_node_input_ports, std::string(generate_mux_node_name(output_node_level, false) + "_in"));
+    /* If we have more than 1 port in the combined instance ports , 
+     * output a local wire */
+    if (1 < combine_verilog_ports(branch_node_input_ports).size()) {
+      /* Print a local wire for the merged ports */
+      fp << "\t" << generate_verilog_local_wire(instance_input_port, branch_node_input_ports) << std::endl;
+    } else {
+      /* Safety check */
+      VTR_ASSERT(1 == combine_verilog_ports(branch_node_input_ports).size());
+    }
+
+    /* Link nodes to input ports for the branch module */
+    ModulePortId module_input_port_id = module_manager.find_module_port(branch_module_id, "in");
+    VTR_ASSERT(ModulePortId::INVALID() != module_input_port_id);
+    /* Get the port from module */
+    BasicPort module_input_port = module_manager.module_port(branch_module_id, module_input_port_id);
+    port2port_name_map[module_input_port.get_name()] = instance_input_port; 
+
+    /* Link nodes to output ports for the branch module */
+    BasicPort instance_output_port(generate_mux_node_name(output_node_level, false), output_node_index_at_level, output_node_index_at_level);
+    ModulePortId module_output_port_id = module_manager.find_module_port(branch_module_id, "out");
+    VTR_ASSERT(ModulePortId::INVALID() != module_output_port_id);
+    /* Get the port from module */
+    BasicPort module_output_port = module_manager.module_port(branch_module_id, module_output_port_id);
+    port2port_name_map[module_output_port.get_name()] = instance_output_port; 
+
+    /* All the mem node names organized in bus 
+     * RRAM-based MUX uses BLB and WL to control memories  
+     */
+    std::vector<BasicPort> branch_node_blb_ports;
+    for (const auto& mem : mems) {
+      /* Generate the port info of each mem node:
+       */
+      BasicPort branch_node_blb_port(circuit_lib.port_prefix(mux_blb_ports[0]), size_t(mem), size_t(mem));
+      branch_node_blb_ports.push_back(branch_node_blb_port);  
+    } 
+    /* Every stage, we have an additonal BLB and WL in controlling purpose 
+     * The additional BLB is arranged at the tail of BLB port  
+     * For example: 
+     *    The total port width is BLB[0 ... <num_mem> + <num_levels> - 1]
+     *    The regular BLB used by branches are  BLB[0 .. <num_mem> - 1]
+     *    The additional BLB used by branches are BLB[<num_mem> .. <num_mem> + <num_levels> - 1]
+     *
+     * output_node_level is always larger than the mem_level by 1
+     */
+    branch_node_blb_ports.push_back(BasicPort(circuit_lib.port_prefix(mux_blb_ports[0]), 
+                                              mux_graph.num_memory_bits() + output_node_level - 1, 
+                                              mux_graph.num_memory_bits() + output_node_level - 1) 
+                                    );
+
+    /* Create the port info for the input */
+    /* TODO: the naming could be more flexible? */
+    BasicPort instance_blb_port = generate_verilog_bus_port(branch_node_blb_ports, std::string(generate_mux_node_name(output_node_level, false) + "_blb"));
+    /* If we have more than 1 port in the combined instance ports , 
+     * output a local wire */
+    if (1 < combine_verilog_ports(branch_node_blb_ports).size()) {
+      /* Print a local wire for the merged ports */
+      fp << "\t" << generate_verilog_local_wire(instance_blb_port, branch_node_blb_ports) << std::endl;
+    } else {
+      /* Safety check */
+      VTR_ASSERT(1 == combine_verilog_ports(branch_node_blb_ports).size());
+    }
+
+    /* Link nodes to BLB ports for the branch module */
+    ModulePortId module_blb_port_id = module_manager.find_module_port(branch_module_id, circuit_lib.port_prefix(mux_blb_ports[0]));
+    VTR_ASSERT(ModulePortId::INVALID() != module_blb_port_id);
+    /* Get the port from module */
+    BasicPort module_blb_port = module_manager.module_port(branch_module_id, module_blb_port_id);
+    port2port_name_map[module_blb_port.get_name()] = instance_blb_port; 
+
+    std::vector<BasicPort> branch_node_wl_ports;
+    for (const auto& mem : mems) {
+      /* Generate the port info of each mem node:
+       */
+      BasicPort branch_node_blb_port(circuit_lib.port_prefix(mux_wl_ports[0]), size_t(mem), size_t(mem));
+      branch_node_wl_ports.push_back(branch_node_blb_port);  
+    } 
+    /* Every stage, we have an additonal BLB and WL in controlling purpose 
+     * The additional BLB is arranged at the tail of BLB port  
+     * For example: 
+     *    The total port width is WL[0 ... <num_mem> + <num_levels> - 1]
+     *    The regular BLB used by branches are  WL[0 .. <num_mem> - 1]
+     *    The additional BLB used by branches are WL[<num_mem> .. <num_mem> + <num_levels> - 1]
+     *
+     * output_node_level is always larger than the mem_level by 1
+     */
+    branch_node_wl_ports.push_back(BasicPort(circuit_lib.port_prefix(mux_wl_ports[0]), 
+                                             mux_graph.num_memory_bits() + output_node_level - 1, 
+                                             mux_graph.num_memory_bits() + output_node_level - 1) 
+                                   );
+
+    /* Create the port info for the WL */
+    /* TODO: the naming could be more flexible? */
+    BasicPort instance_wl_port = generate_verilog_bus_port(branch_node_wl_ports, std::string(generate_mux_node_name(output_node_level, false) + "_wl"));
+    /* If we have more than 1 port in the combined instance ports , 
+     * output a local wire */
+    if (1 < combine_verilog_ports(branch_node_wl_ports).size()) {
+      /* Print a local wire for the merged ports */
+      fp << "\t" << generate_verilog_local_wire(instance_wl_port, branch_node_wl_ports) << std::endl;
+    } else {
+      /* Safety check */
+      VTR_ASSERT(1 == combine_verilog_ports(branch_node_wl_ports).size());
+    }
+
+    /* Link nodes to BLB ports for the branch module */
+    ModulePortId module_wl_port_id = module_manager.find_module_port(branch_module_id, circuit_lib.port_prefix(mux_wl_ports[0]));
+    VTR_ASSERT(ModulePortId::INVALID() != module_wl_port_id);
+    /* Get the port from module */
+    BasicPort module_wl_port = module_manager.module_port(branch_module_id, module_wl_port_id);
+    port2port_name_map[module_wl_port.get_name()] = instance_wl_port; 
+
+    /* Output an instance of the module */
+    print_verilog_module_instance(fp, module_manager, module_id, branch_module_id, port2port_name_map, circuit_lib.dump_explicit_port_map(circuit_model));
+    /* IMPORTANT: this update MUST be called after the instance outputting!!!!
+     * update the module manager with the relationship between the parent and child modules 
+     */
+    module_manager.add_child_module(module_id, branch_module_id);
+
+    print_verilog_comment(fp, std::string("---- END Instanciation of a branch RRAM-based MUX module -----"));
+    fp << std::endl;
+
+    if (false == inter_buffer_location_map[output_node_level]) {
+      continue; /* No need for intermediate buffers */
+    }
+
+    print_verilog_comment(fp, std::string("---- BEGIN Instanciation of an intermediate buffer modules -----"));
+
+    /* Now we need to add intermediate buffers by instanciating the modules */
+    CircuitModelId buffer_model = circuit_lib.lut_intermediate_buffer_model(circuit_model);
+    /* We must have a valid model id */
+    VTR_ASSERT(CircuitModelId::INVALID() != buffer_model);
+   
+    BasicPort buffer_instance_input_port(generate_mux_node_name(output_node_level, false), output_node_index_at_level, output_node_index_at_level);
+    BasicPort buffer_instance_output_port(generate_mux_node_name(output_node_level, true), output_node_index_at_level, output_node_index_at_level);
+
+    print_verilog_buffer_instance(fp, module_manager, circuit_lib, module_id, buffer_model, buffer_instance_input_port, buffer_instance_output_port);
+
+    print_verilog_comment(fp, std::string("---- END Instanciation of an intermediate buffer module -----"));
+    fp << std::endl;
+  }
+
+  print_verilog_comment(fp, std::string("---- END Internal Logic of a RRAM-based MUX module -----"));
+  fp << std::endl;
+}
+
+/*********************************************************************
+ * Generate Verilog codes modeling a RRAM-based multiplexer with the given size 
+ * The Verilog module will consist of three parts:
+ * 1. instances of the branch circuits of multiplexers which are generated before  
+ *    This builds up the 4T1R-based multiplexing structure
+ *
+ *                    BLB   WL
+ *                     |    |       ...
+ *                     v    v
+ *                   +--------+            
+ *           in[0]-->|        |            BLB   WL 
+ *                ...| Branch |-----+       |    |
+ *             in -->|   0    |     |       v    v
+ *            [N-1]  +--------+     |     +--------+
+ *                      ...            -->|        |
+ *                    BLBs WLs         ...| Branch |
+ *                     |    |    ...   -->|   X    |
+ *                     v    v             +--------+
+ *                   +--------+    |
+ *                -->|        |    |
+ *                ...| Branch |----+
+ *                -->|   i    |
+ *                   +--------+
+ *
+ * 2. Input buffers/inverters
+ * 3. Output buffers/inverters
+ *********************************************************************/
+static 
+void generate_verilog_rram_mux_module(ModuleManager& module_manager,
+                                      const CircuitLibrary& circuit_lib, 
+                                      std::fstream& fp,
+                                      const CircuitModelId& circuit_model, 
+                                      const std::string& module_name, 
+                                      const MuxGraph& mux_graph) {
+  /* Error out for the conditions where we are not yet supported! */
+  if (CIRCUIT_MODEL_LUT == circuit_lib.model_type(circuit_model)) {
+    /* RRAM LUT is not supported now... */
+    VTR_LOGF_ERROR(__FILE__, __LINE__, 
+                   "RRAM-based LUT is not supported for circuit model '%s'!\n",
+                   circuit_lib.model_name(circuit_model).c_str());
+    exit(1);
+  }
+
+  /* Get the global ports required by MUX (and any submodules) */
+  std::vector<CircuitPortId> mux_global_ports = circuit_lib.model_global_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true, true);
+  /* Get the input ports from the mux */
+  std::vector<CircuitPortId> mux_input_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true);
+  /* Get the output ports from the mux */
+  std::vector<CircuitPortId> mux_output_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
+  /* Get the BL and WL ports from the mux */
+  std::vector<CircuitPortId> mux_blb_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_BLB, true);
+  std::vector<CircuitPortId> mux_wl_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_WL, true);
+
+  /* Make sure we have a valid file handler*/
+  VTR_ASSERT(true == valid_file_stream(fp));
+
+  /* Generate the Verilog netlist according to the mux_graph */
+  /* Find out the number of data-path inputs */ 
+  size_t num_inputs = find_mux_num_datapath_inputs(circuit_lib, circuit_model, mux_graph.num_inputs());
+  /* Find out the number of outputs */ 
+  size_t num_outputs = mux_graph.num_outputs();
+  /* Find out the number of memory bits */ 
+  size_t num_mems = mux_graph.num_memory_bits();
+
+  /* Check codes to ensure the port of Verilog netlists will match */
+  /* MUX graph must have only 1 input and 1 BLB and 1 WL port */
+  VTR_ASSERT(1 == mux_input_ports.size());
+  VTR_ASSERT(1 == mux_blb_ports.size());
+  VTR_ASSERT(1 == mux_wl_ports.size());
+
+  /* Create a Verilog Module based on the circuit model, and add to module manager */
+  ModuleId module_id = module_manager.add_module(module_name); 
+  VTR_ASSERT(ModuleId::INVALID() != module_id);
+  /* Add module ports */
+  /* Add each global port */
+  for (const auto& port : mux_global_ports) {
+    /* Configure each global port */
+    BasicPort global_port(circuit_lib.port_prefix(port), circuit_lib.port_size(port));
+    module_manager.add_port(module_id, global_port, ModuleManager::MODULE_GLOBAL_PORT);
+  }
+  /* Add each input port */
+  size_t input_port_cnt = 0;
+  for (const auto& port : mux_input_ports) {
+    BasicPort input_port(circuit_lib.port_prefix(port), num_inputs);
+    module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT);
+    /* Update counter */
+    input_port_cnt++;
+  }
+  /* Double check: We should have only 1 input port generated here! */
+  VTR_ASSERT(1 == input_port_cnt);
+
+  for (const auto& port : mux_output_ports) {
+    BasicPort output_port(circuit_lib.port_prefix(port), num_outputs);
+    if (CIRCUIT_MODEL_LUT == circuit_lib.model_type(circuit_model)) {
+      output_port.set_width(circuit_lib.port_size(port));
+    }
+    module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT);
+  }
+
+  /* BLB port */
+  for (const auto& port : mux_blb_ports) {
+    /* IMPORTANT: RRAM-based MUX has an additional BLB pin per level 
+     * So, the actual port width of BLB should be added by the number of levels of the MUX graph 
+     */
+    BasicPort blb_port(circuit_lib.port_prefix(port), num_mems + mux_graph.num_levels());
+    module_manager.add_port(module_id, blb_port, ModuleManager::MODULE_INPUT_PORT);
+  }
+
+  /* WL port */
+  for (const auto& port : mux_wl_ports) {
+    /* IMPORTANT: RRAM-based MUX has an additional WL pin per level 
+     * So, the actual port width of WL should be added by the number of levels of the MUX graph 
+     */
+    BasicPort wl_port(circuit_lib.port_prefix(port), num_mems + mux_graph.num_levels());
+    module_manager.add_port(module_id, wl_port, ModuleManager::MODULE_INPUT_PORT);
+  }
+ 
+  /* dump module definition + ports */
+  print_verilog_module_declaration(fp, module_manager, module_id);
+
+  /* TODO: Print the internal logic in Verilog codes */
+  generate_verilog_rram_mux_module_multiplexing_structure(module_manager, circuit_lib, fp, module_id, circuit_model, mux_graph);
+
+  /* Print the input and output buffers in Verilog codes */
+  /* TODO, we should rename the follow functions to a generic name? Since they are applicable to both MUXes */
+  generate_verilog_cmos_mux_module_input_buffers(module_manager, circuit_lib, fp, module_id, circuit_model, mux_graph);
+  generate_verilog_cmos_mux_module_output_buffers(module_manager, circuit_lib, fp, module_id, circuit_model, mux_graph);
+
+  /* Put an end to the Verilog module */
+  print_verilog_module_end(fp, module_name);
+}
+
+
+/***********************************************
+ * Generate Verilog codes modeling a multiplexer 
+ * with the given graph-level description
+ **********************************************/
+static 
+void generate_verilog_mux_module(ModuleManager& module_manager,
+                                 const CircuitLibrary& circuit_lib, 
+                                 std::fstream& fp, 
+                                 const CircuitModelId& mux_model, 
+                                 const MuxGraph& mux_graph,
+                                 const bool& use_explicit_port_map) {
+  std::string module_name = generate_mux_subckt_name(circuit_lib, mux_model, 
+                                                     find_mux_num_datapath_inputs(circuit_lib, mux_model, mux_graph.num_inputs()), 
+                                                     std::string(""));
+ 
+  /* Multiplexers built with different technology is in different organization */
+  switch (circuit_lib.design_tech_type(mux_model)) {
+  case CIRCUIT_MODEL_DESIGN_CMOS: {
+    /* Use Verilog writer to print the module to file */
+    ModuleId mux_module = module_manager.find_module(module_name);
+    VTR_ASSERT(true == module_manager.valid_module_id(mux_module));
+    write_verilog_module_to_file(fp, module_manager, mux_module, 
+                                  ( use_explicit_port_map 
+                                 || circuit_lib.dump_explicit_port_map(mux_model) 
+                                 || circuit_lib.dump_explicit_port_map(circuit_lib.pass_gate_logic_model(mux_model)) ) 
+                                 );
+    /* Add an empty line as a splitter */
+    fp << std::endl;
+    break;
+  }
+  case CIRCUIT_MODEL_DESIGN_RRAM:
+    /* TODO: RRAM-based Multiplexer Verilog module generation */
+    generate_verilog_rram_mux_module(module_manager, circuit_lib, fp, mux_model, module_name, mux_graph);
+    break;
+  default:
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid design technology of multiplexer '%s'\n",
+                   circuit_lib.model_name(mux_model).c_str()); 
+    exit(1);
+  }
+}
+
+
+/***********************************************
+ * Generate Verilog modules for all the unique
+ * multiplexers in the FPGA device
+ **********************************************/
+void print_verilog_submodule_muxes(ModuleManager& module_manager,
+                                   std::vector<std::string>& netlist_names,
+                                   const MuxLibrary& mux_lib,
+                                   const CircuitLibrary& circuit_lib,
+                                   const std::string& verilog_dir,
+                                   const std::string& submodule_dir,
+                                   const bool& use_explicit_port_map) {
+
+  std::string verilog_fname(submodule_dir + std::string(MUXES_VERILOG_FILE_NAME));
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
+
+  check_file_stream(verilog_fname.c_str(), fp);
+
+  /* Print out debugging information for if the file is not opened/created properly */
+  VTR_LOG("Writing Verilog netlist for Multiplexers '%s' ...\n",
+          verilog_fname.c_str()); 
+
+  print_verilog_file_header(fp, "Multiplexers"); 
+
+  print_verilog_include_defines_preproc_file(fp, verilog_dir);
+  
+  /* Generate basis sub-circuit for unique branches shared by the multiplexers */
+  for (auto mux : mux_lib.muxes()) {
+    const MuxGraph& mux_graph = mux_lib.mux_graph(mux);
+    CircuitModelId mux_circuit_model = mux_lib.mux_circuit_model(mux); 
+    /* Create a mux graph for the branch circuit */
+    std::vector<MuxGraph> branch_mux_graphs = mux_graph.build_mux_branch_graphs();
+    /* Create branch circuits, which are N:1 one-level or 2:1 tree-like MUXes */
+    for (auto branch_mux_graph : branch_mux_graphs) {
+      generate_verilog_mux_branch_module(module_manager, circuit_lib, fp, mux_circuit_model, 
+                                         find_mux_num_datapath_inputs(circuit_lib, mux_circuit_model, mux_graph.num_inputs()), 
+                                         branch_mux_graph, use_explicit_port_map);
+    }
+  }
+
+  /* Generate unique Verilog modules for the multiplexers */
+  for (auto mux : mux_lib.muxes()) {
+    const MuxGraph& mux_graph = mux_lib.mux_graph(mux);
+    CircuitModelId mux_circuit_model = mux_lib.mux_circuit_model(mux); 
+    /* Create MUX circuits */
+    generate_verilog_mux_module(module_manager, circuit_lib, fp, mux_circuit_model, mux_graph, use_explicit_port_map);
+  }
+
+  /* Close the file stream */
+  fp.close();
+
+  /* Add fname to the netlist name list */
+  netlist_names.push_back(verilog_fname);
+
+  VTR_LOG("Done\n");
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_verilog/verilog_mux.h b/openfpga/src/fpga_verilog/verilog_mux.h
new file mode 100644
index 000000000..16e6c2f2a
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_mux.h
@@ -0,0 +1,32 @@
+#ifndef VERILOG_MUX_H
+#define VERILOG_MUX_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <fstream>
+#include <vector>
+
+#include "circuit_library.h"
+#include "mux_graph.h"
+#include "mux_library.h"
+#include "module_manager.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void print_verilog_submodule_muxes(ModuleManager& module_manager,
+                                   std::vector<std::string>& netlist_names,
+                                   const MuxLibrary& mux_lib,
+                                   const CircuitLibrary& circuit_lib,
+                                   const std::string& verilog_dir,
+                                   const std::string& submodule_dir,
+                                   const bool& use_explicit_port_map);
+
+} /* end namespace openfpga */
+
+#endif

From 105ccabecc4ae7ae0d1b5a9391653afcae6593e2 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 16 Feb 2020 12:41:43 -0700
Subject: [PATCH 155/645] adapt memroy writer for verilog

---
 openfpga/src/fpga_verilog/verilog_constants.h |   1 +
 openfpga/src/fpga_verilog/verilog_memory.cpp  | 195 ++++++++++++++++++
 openfpga/src/fpga_verilog/verilog_memory.h    |  31 +++
 3 files changed, 227 insertions(+)
 create mode 100644 openfpga/src/fpga_verilog/verilog_memory.cpp
 create mode 100644 openfpga/src/fpga_verilog/verilog_memory.h

diff --git a/openfpga/src/fpga_verilog/verilog_constants.h b/openfpga/src/fpga_verilog/verilog_constants.h
index 49a73bf6d..91f87c475 100644
--- a/openfpga/src/fpga_verilog/verilog_constants.h
+++ b/openfpga/src/fpga_verilog/verilog_constants.h
@@ -42,5 +42,6 @@ constexpr char* CONFIG_PERIPHERAL_VERILOG_FILE_NAME = "config_peripherals.v";
 constexpr char* USER_DEFINED_TEMPLATE_VERILOG_FILE_NAME = "user_defined_templates.v";
 
 constexpr char* VERILOG_MUX_BASIS_POSTFIX = "_basis";
+constexpr char* VERILOG_MEM_POSTFIX = "_mem";
 
 #endif
diff --git a/openfpga/src/fpga_verilog/verilog_memory.cpp b/openfpga/src/fpga_verilog/verilog_memory.cpp
new file mode 100644
index 000000000..743647d44
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_memory.cpp
@@ -0,0 +1,195 @@
+/*********************************************************************
+ * This file includes functions to generate Verilog submodules for 
+ * the memories that are affiliated to multiplexers and other programmable
+ * circuit models, such as IOPADs, LUTs, etc.
+ ********************************************************************/
+#include <string>
+#include <algorithm>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_digest.h"
+
+#include "mux_graph.h"
+#include "module_manager.h"
+#include "circuit_library_utils.h"
+#include "mux_utils.h"
+
+#include "openfpga_naming.h"
+
+#include "verilog_constants.h"
+#include "verilog_writer_utils.h"
+#include "verilog_module_writer.h"
+#include "verilog_memory.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/*********************************************************************
+ * Generate Verilog modules for the memories that are used
+ * by multiplexers  
+ *
+ *            +----------------+
+ * mem_in --->|  Memory Module |---> mem_out
+ *            +----------------+
+ *              |  |  ... |  | 
+ *              v  v      v  v SRAM ports of multiplexer
+ *          +---------------------+
+ *    in--->|  Multiplexer Module |---> out
+ *          +---------------------+
+ ********************************************************************/
+static 
+void print_verilog_mux_memory_module(ModuleManager& module_manager,
+                                     const CircuitLibrary& circuit_lib,
+                                     std::fstream& fp,
+                                     const CircuitModelId& mux_model,
+                                     const MuxGraph& mux_graph,
+                                     const bool& use_explicit_port_map) {
+  /* Multiplexers built with different technology is in different organization */
+  switch (circuit_lib.design_tech_type(mux_model)) {
+  case CIRCUIT_MODEL_DESIGN_CMOS: {
+    /* Generate module name */
+    std::string module_name = generate_mux_subckt_name(circuit_lib, mux_model, 
+                                                       find_mux_num_datapath_inputs(circuit_lib, mux_model, mux_graph.num_inputs()), 
+                                                       std::string(VERILOG_MEM_POSTFIX));
+    ModuleId mem_module = module_manager.find_module(module_name);
+    VTR_ASSERT(true == module_manager.valid_module_id(mem_module));
+    /* Write the module content in Verilog format */
+    write_verilog_module_to_file(fp, module_manager, mem_module, 
+                                 use_explicit_port_map || circuit_lib.dump_explicit_port_map(mux_model));
+
+    /* Add an empty line as a splitter */
+    fp << std::endl;
+    break;
+  }
+  case CIRCUIT_MODEL_DESIGN_RRAM:
+    /* We do not need a memory submodule for RRAM MUX,
+     * RRAM are embedded in the datapath  
+     * TODO: generate local encoders for RRAM-based multiplexers here!!!
+     */ 
+    break;
+  default:
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid design technology of multiplexer '%s'\n",
+                   circuit_lib.model_name(mux_model).c_str()); 
+    exit(1);
+  }
+}
+
+
+/*********************************************************************
+ * Generate Verilog modules for 
+ * the memories that are affiliated to multiplexers and other programmable
+ * circuit models, such as IOPADs, LUTs, etc.
+ *
+ * We keep the memory modules separated from the multiplexers and other 
+ * programmable circuit models, for the sake of supporting
+ * various configuration schemes.
+ * By following such organiztion, the Verilog modules of the circuit models
+ * implements the functionality (circuit logic) only, while the memory Verilog
+ * modules implements the memory circuits as well as configuration protocols.
+ * For example, the local decoders of multiplexers are implemented in the
+ * memory modules. 
+ * Take another example, the memory circuit can implement the scan-chain or 
+ * memory-bank organization for the memories.
+ ********************************************************************/
+void print_verilog_submodule_memories(ModuleManager& module_manager,
+                                      std::vector<std::string>& netlist_names,
+                                      const MuxLibrary& mux_lib,
+                                      const CircuitLibrary& circuit_lib,
+                                      const std::string& verilog_dir,
+                                      const std::string& submodule_dir,
+                                      const bool& use_explicit_port_map) {
+  /* Plug in with the mux subckt */
+  std::string verilog_fname(submodule_dir + std::string(MEMORIES_VERILOG_FILE_NAME));
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
+
+  check_file_stream(verilog_fname.c_str(), fp);
+
+  /* Print out debugging information for if the file is not opened/created properly */
+  VTR_LOG("Writing Verilog netlist for memories '%s' ...",
+          verilog_fname.c_str()); 
+
+  print_verilog_file_header(fp, "Memories used in FPGA"); 
+
+  print_verilog_include_defines_preproc_file(fp, verilog_dir);
+  
+  /* Create the memory circuits for the multiplexer */
+  for (auto mux : mux_lib.muxes()) {
+    const MuxGraph& mux_graph = mux_lib.mux_graph(mux);
+    CircuitModelId mux_model = mux_lib.mux_circuit_model(mux); 
+    /* Bypass the non-MUX circuit models (i.e., LUTs). 
+     * They should be handled in a different way 
+     * Memory circuits of LUT includes both regular and mode-select ports
+     */
+    if (CIRCUIT_MODEL_MUX != circuit_lib.model_type(mux_model)) {
+      continue;
+    }
+    /* Create a Verilog module for the memories used by the multiplexer */
+    print_verilog_mux_memory_module(module_manager, circuit_lib, fp, mux_model, mux_graph, use_explicit_port_map);
+  }
+
+  /* Create the memory circuits for non-MUX circuit models.
+   * In this case, the memory modules are designed to interface
+   * the mode-select ports 
+   */
+  for (const auto& model : circuit_lib.models()) {
+    /* Bypass MUXes, they have already been considered */
+    if (CIRCUIT_MODEL_MUX == circuit_lib.model_type(model)) {
+      continue;
+    }
+    /* Bypass those modules without any SRAM ports */
+    std::vector<CircuitPortId> sram_ports = circuit_lib.model_ports_by_type(model, CIRCUIT_MODEL_PORT_SRAM, true);
+    if (0 == sram_ports.size()) {
+      continue;
+    }
+    /* Find the name of memory module */
+    /* Get the total number of SRAMs */
+    size_t num_mems = 0; 
+    for (const auto& port : sram_ports) {
+      num_mems += circuit_lib.port_size(port);
+    }
+    /* Get the circuit model for the memory circuit used by the multiplexer */
+    std::vector<CircuitModelId> sram_models;
+    for (const auto& port : sram_ports) {
+      CircuitModelId sram_model = circuit_lib.port_tri_state_model(port);
+      VTR_ASSERT(CircuitModelId::INVALID() != sram_model);
+      /* Found in the vector of sram_models, do not update and go to the next */
+      if (sram_models.end() != std::find(sram_models.begin(), sram_models.end(), sram_model)) {
+        continue;
+      }
+      /* sram_model not found in the vector, update the sram_models */
+      sram_models.push_back(sram_model);
+    }
+    /* Should have only 1 SRAM model */
+    VTR_ASSERT( 1 == sram_models.size() );
+  
+    /* Create the module name for the memory block */
+    std::string module_name = generate_memory_module_name(circuit_lib, model, sram_models[0], std::string(VERILOG_MEM_POSTFIX));
+
+    ModuleId mem_module = module_manager.find_module(module_name);
+    VTR_ASSERT(true == module_manager.valid_module_id(mem_module));
+    /* Write the module content in Verilog format */
+    write_verilog_module_to_file(fp, module_manager, mem_module, 
+                                 use_explicit_port_map || circuit_lib.dump_explicit_port_map(model));
+
+    /* Add an empty line as a splitter */
+    fp << std::endl;
+  }
+
+  /* Close the file stream */
+  fp.close();
+
+  /* Add fname to the netlist name list */
+  netlist_names.push_back(verilog_fname);
+
+  VTR_LOG("Done\n");
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_verilog/verilog_memory.h b/openfpga/src/fpga_verilog/verilog_memory.h
new file mode 100644
index 000000000..774e6feb9
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_memory.h
@@ -0,0 +1,31 @@
+#ifndef VERILOG_MEMORY_H
+#define VERILOG_MEMORY_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <fstream>
+
+#include "circuit_library.h"
+#include "mux_graph.h"
+#include "mux_library.h"
+#include "module_manager.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void print_verilog_submodule_memories(ModuleManager& module_manager,
+                                      std::vector<std::string>& netlist_names,
+                                      const MuxLibrary& mux_lib,
+                                      const CircuitLibrary& circuit_lib,
+                                      const std::string& verilog_dir,
+                                      const std::string& submodule_dir,
+                                      const bool& use_explicit_port_map);
+
+} /* end namespace openfpga */
+
+#endif

From 5cc68b07301860d559c7a090afdb4cf43ed9a7b2 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 16 Feb 2020 12:45:58 -0700
Subject: [PATCH 156/645] adapt LUT Verilog writer

---
 openfpga/src/fpga_verilog/verilog_lut.cpp | 78 +++++++++++++++++++++++
 openfpga/src/fpga_verilog/verilog_lut.h   | 29 +++++++++
 2 files changed, 107 insertions(+)
 create mode 100644 openfpga/src/fpga_verilog/verilog_lut.cpp
 create mode 100644 openfpga/src/fpga_verilog/verilog_lut.h

diff --git a/openfpga/src/fpga_verilog/verilog_lut.cpp b/openfpga/src/fpga_verilog/verilog_lut.cpp
new file mode 100644
index 000000000..900ef3073
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_lut.cpp
@@ -0,0 +1,78 @@
+/********************************************************************
+ * This file includes functions to generate Verilog submodules for LUTs
+ ********************************************************************/
+#include <string>
+#include <algorithm>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_digest.h"
+
+#include "mux_graph.h"
+#include "module_manager.h"
+#include "mux_utils.h"
+
+#include "openfpga_naming.h"
+
+#include "verilog_constants.h"
+#include "verilog_writer_utils.h"
+#include "verilog_module_writer.h"
+#include "verilog_lut.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/******************************************************************** 
+ * Print Verilog modules for the Look-Up Tables (LUTs) 
+ * in the circuit library
+ ********************************************************************/
+void print_verilog_submodule_luts(ModuleManager& module_manager,
+                                  std::vector<std::string>& netlist_names,
+                                  const CircuitLibrary& circuit_lib,
+                                  const std::string& verilog_dir,
+                                  const std::string& submodule_dir,
+                                  const bool& use_explicit_port_map) {
+  std::string verilog_fname = submodule_dir + std::string(LUTS_VERILOG_FILE_NAME);
+
+  std::fstream fp;
+
+  /* Create the file stream */
+  fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
+  /* Check if the file stream if valid or not */
+  check_file_stream(verilog_fname.c_str(), fp); 
+
+  /* Create file */
+  VTR_LOG("Writing Verilog netlist for LUTs '%s'...",
+          verilog_fname.c_str()); 
+
+  print_verilog_file_header(fp, "Look-Up Tables"); 
+
+  print_verilog_include_defines_preproc_file(fp, verilog_dir);
+
+  /* Search for each LUT circuit model */
+  for (const auto& lut_model : circuit_lib.models()) {
+    /* Bypass user-defined and non-LUT modules */
+    if ( (!circuit_lib.model_verilog_netlist(lut_model).empty()) 
+      || (CIRCUIT_MODEL_LUT != circuit_lib.model_type(lut_model)) ) {
+      continue;
+    }
+    /* Find the module id */
+    ModuleId lut_module = module_manager.find_module(circuit_lib.model_name(lut_model));
+    VTR_ASSERT(true == module_manager.valid_module_id(lut_module));
+    write_verilog_module_to_file(fp, module_manager, lut_module, 
+                                 use_explicit_port_map || circuit_lib.dump_explicit_port_map(lut_model));
+  }
+
+  /* Close the file handler */
+  fp.close();
+
+  /* Add fname to the netlist name list */
+  netlist_names.push_back(verilog_fname);
+
+  VTR_LOG("Done\n");
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_verilog/verilog_lut.h b/openfpga/src/fpga_verilog/verilog_lut.h
new file mode 100644
index 000000000..f5d1345dc
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_lut.h
@@ -0,0 +1,29 @@
+#ifndef VERILOG_LUT_H
+#define VERILOG_LUT_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <fstream>
+#include <string>
+
+#include "circuit_library.h"
+#include "module_manager.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void print_verilog_submodule_luts(ModuleManager& module_manager,
+                                  std::vector<std::string>& netlist_names,
+                                  const CircuitLibrary& circuit_lib,
+                                  const std::string& verilog_dir,
+                                  const std::string& submodule_dir,
+                                  const bool& use_explicit_port_map);
+
+} /* end namespace openfpga */
+
+#endif

From 99c3712b6f649da9fea727b7df3ca01765aec98a Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 16 Feb 2020 12:59:37 -0700
Subject: [PATCH 157/645] adapt Verilog wire module writer

---
 openfpga/src/fpga_verilog/verilog_wire.cpp | 136 +++++++++++++++++++++
 openfpga/src/fpga_verilog/verilog_wire.h   |  28 +++++
 2 files changed, 164 insertions(+)
 create mode 100644 openfpga/src/fpga_verilog/verilog_wire.cpp
 create mode 100644 openfpga/src/fpga_verilog/verilog_wire.h

diff --git a/openfpga/src/fpga_verilog/verilog_wire.cpp b/openfpga/src/fpga_verilog/verilog_wire.cpp
new file mode 100644
index 000000000..2ac9e7ffa
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_wire.cpp
@@ -0,0 +1,136 @@
+/***********************************************
+ * This file includes functions to generate
+ * Verilog submodules for wires.
+ **********************************************/
+#include <string>
+#include <algorithm>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_digest.h"
+
+#include "module_manager.h"
+#include "module_manager_utils.h"
+
+#include "openfpga_naming.h"
+
+#include "verilog_constants.h"
+#include "verilog_submodule_utils.h"
+#include "verilog_writer_utils.h"
+#include "verilog_wire.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Print a Verilog module of a regular wire segment
+ * Regular wire, which is 1-input and 1-output
+ * This type of wires are used in the local routing architecture
+ *              +------+
+ *    input --->| wire |---> output
+ *              +------+
+ *
+ *******************************************************************/
+static 
+void print_verilog_wire_module(ModuleManager& module_manager, 
+                               const CircuitLibrary& circuit_lib,
+                               std::fstream& fp,
+                               const CircuitModelId& wire_model) {
+  /* Ensure a valid file handler*/
+  VTR_ASSERT(true == valid_file_stream(fp));
+
+  /* Find the input port, output port*/
+  std::vector<CircuitPortId> input_ports = circuit_lib.model_ports_by_type(wire_model, CIRCUIT_MODEL_PORT_INPUT, true);
+  std::vector<CircuitPortId> output_ports = circuit_lib.model_ports_by_type(wire_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
+  std::vector<CircuitPortId> global_ports = circuit_lib.model_global_ports_by_type(wire_model, CIRCUIT_MODEL_PORT_INPUT, true, true);
+
+  /* Makre sure the port size is what we want */
+  VTR_ASSERT (1 == input_ports.size());
+  VTR_ASSERT (1 == output_ports.size());
+  VTR_ASSERT (1 == circuit_lib.port_size(input_ports[0]));
+  VTR_ASSERT (1 == circuit_lib.port_size(output_ports[0]));
+
+  /* Create a Verilog Module based on the circuit model, and add to module manager */
+  ModuleId wire_module = module_manager.find_module(circuit_lib.model_name(wire_model)); 
+  VTR_ASSERT(true == module_manager.valid_module_id(wire_module));
+
+  /* dump module definition + ports */
+  print_verilog_module_declaration(fp, module_manager, wire_module);
+  /* Finish dumping ports */
+
+  /* Print the internal logic of Verilog module */
+  /* Find the input port of the module */
+  ModulePortId module_input_port_id = module_manager.find_module_port(wire_module, circuit_lib.port_lib_name(input_ports[0]));
+  VTR_ASSERT(ModulePortId::INVALID() != module_input_port_id);
+  BasicPort module_input_port = module_manager.module_port(wire_module, module_input_port_id);
+
+  /* Find the output port of the module */
+  ModulePortId module_output_port_id = module_manager.find_module_port(wire_module, circuit_lib.port_lib_name(output_ports[0]));
+  VTR_ASSERT(ModulePortId::INVALID() != module_output_port_id);
+  BasicPort module_output_port = module_manager.module_port(wire_module, module_output_port_id);
+
+  /* Print wire declaration for the inputs and outputs */
+  fp << generate_verilog_port(VERILOG_PORT_WIRE, module_input_port) << ";" << std::endl;
+  fp << generate_verilog_port(VERILOG_PORT_WIRE, module_output_port) << ";" << std::endl;
+
+  /* Direct shortcut */
+  print_verilog_wire_connection(fp, module_output_port, module_input_port, false);
+  
+  /* Print timing info */
+  print_verilog_submodule_timing(fp, circuit_lib, wire_model);
+   
+  /* Put an end to the Verilog module */
+  print_verilog_module_end(fp, circuit_lib.model_name(wire_model));
+
+  /* Add an empty line as a splitter */
+  fp << std::endl;
+}
+
+/********************************************************************
+ * Top-level function to print wire modules
+ *******************************************************************/
+void print_verilog_submodule_wires(ModuleManager& module_manager,
+                                   std::vector<std::string>& netlist_names,
+                                   const CircuitLibrary& circuit_lib,
+                                   const std::string& verilog_dir,
+                                   const std::string& submodule_dir) {
+  std::string verilog_fname(submodule_dir + std::string(WIRES_VERILOG_FILE_NAME));
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
+
+  check_file_stream(verilog_fname.c_str(), fp);
+
+  /* Print out debugging information for if the file is not opened/created properly */
+  VTR_LOG("Writing Verilog netlist for wires '%s'...",
+          verilog_fname.c_str()); 
+
+  print_verilog_file_header(fp, "Wires"); 
+
+  print_verilog_include_defines_preproc_file(fp, verilog_dir);
+
+  /* Print Verilog models for regular wires*/
+  print_verilog_comment(fp, std::string("----- BEGIN Verilog modules for regular wires -----"));
+  for (const auto& model : circuit_lib.models_by_type(CIRCUIT_MODEL_WIRE)) { 
+    /* Bypass user-defined circuit models */
+    if (!circuit_lib.model_verilog_netlist(model).empty()) {
+      continue;
+    }
+    print_verilog_wire_module(module_manager, circuit_lib, fp, model);
+  }
+  print_verilog_comment(fp, std::string("----- END Verilog modules for regular wires -----"));
+
+  /* Close the file stream */
+  fp.close();
+
+  /* Add fname to the netlist name list */
+  netlist_names.push_back(verilog_fname);
+
+  VTR_LOG("Done\n");
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_verilog/verilog_wire.h b/openfpga/src/fpga_verilog/verilog_wire.h
new file mode 100644
index 000000000..7d22ae4c8
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_wire.h
@@ -0,0 +1,28 @@
+#ifndef VERILOG_WIRE_H
+#define VERILOG_WIRE_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <fstream>
+#include <vector>
+
+#include "circuit_library.h"
+#include "module_manager.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void print_verilog_submodule_wires(ModuleManager& module_manager,
+                                   std::vector<std::string>& netlist_names,
+                                   const CircuitLibrary& circuit_lib,
+                                   const std::string& verilog_dir,
+                                   const std::string& submodule_dir);
+
+} /* end namespace openfpga */
+
+#endif

From c6c3ef71f39654af33522288873dc4bcb440a92f Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 16 Feb 2020 13:35:18 -0700
Subject: [PATCH 158/645] adapt all the Verilog submodule writers and bring it
 onlien

---
 .../libopenfpgautil/src/openfpga_digest.cpp   |  2 +-
 openfpga/src/base/openfpga_verilog.cpp        | 10 +-
 .../src/base/openfpga_verilog_command.cpp     |  9 ++
 openfpga/src/fpga_verilog/verilog_api.cpp     | 16 ++--
 openfpga/src/fpga_verilog/verilog_api.h       |  2 +-
 openfpga/src/fpga_verilog/verilog_mux.cpp     |  2 +-
 openfpga/src/fpga_verilog/verilog_options.cpp | 25 +++++
 openfpga/src/fpga_verilog/verilog_options.h   |  6 ++
 .../src/fpga_verilog/verilog_submodule.cpp    | 96 +++++++++++++++++++
 openfpga/src/fpga_verilog/verilog_submodule.h | 27 ++++++
 .../fpga_verilog/verilog_submodule_utils.cpp  |  6 ++
 .../src/fpga_verilog/verilog_writer_utils.cpp |  6 ++
 openfpga/test_script/s298_k6_frac.openfpga    |  2 +-
 13 files changed, 198 insertions(+), 11 deletions(-)
 create mode 100644 openfpga/src/fpga_verilog/verilog_submodule.cpp
 create mode 100644 openfpga/src/fpga_verilog/verilog_submodule.h

diff --git a/libopenfpga/libopenfpgautil/src/openfpga_digest.cpp b/libopenfpga/libopenfpgautil/src/openfpga_digest.cpp
index 3340ea8b1..4714700e4 100644
--- a/libopenfpga/libopenfpgautil/src/openfpga_digest.cpp
+++ b/libopenfpga/libopenfpgautil/src/openfpga_digest.cpp
@@ -135,7 +135,7 @@ bool create_dir_path(const char* dir_path) {
      return true;
    case -1:
      if (EEXIST == errno) {
-       VTR_LOG_ERROR("Directory '%s' already exists. Will overwrite contents\n",
+       VTR_LOG_WARN("Directory '%s' already exists. Will overwrite contents\n",
                      dir_path);
        return true;
      }
diff --git a/openfpga/src/base/openfpga_verilog.cpp b/openfpga/src/base/openfpga_verilog.cpp
index 2612fe76a..018fe1249 100644
--- a/openfpga/src/base/openfpga_verilog.cpp
+++ b/openfpga/src/base/openfpga_verilog.cpp
@@ -25,6 +25,10 @@ void write_fabric_verilog(OpenfpgaContext& openfpga_ctx,
   CommandOptionId opt_include_timing = cmd.option("include_timing");
   CommandOptionId opt_include_signal_init = cmd.option("include_signal_init");
   CommandOptionId opt_support_icarus_simulator = cmd.option("support_icarus_simulator");
+  CommandOptionId opt_print_user_defined_template = cmd.option("print_user_defined_template");
+  CommandOptionId opt_print_top_testbench = cmd.option("print_top_testbench");
+  CommandOptionId opt_print_formal_verification_top_netlist = cmd.option("print_formal_verification_top_netlist");
+  CommandOptionId opt_print_autocheck_top_testbench = cmd.option("print_autocheck_top_testbench");
   CommandOptionId opt_verbose = cmd.option("verbose");
 
   /* This is an intermediate data structure which is designed to modularize the FPGA-Verilog
@@ -36,10 +40,14 @@ void write_fabric_verilog(OpenfpgaContext& openfpga_ctx,
   options.set_include_timing(cmd_context.option_enable(cmd, opt_include_timing));
   options.set_include_signal_init(cmd_context.option_enable(cmd, opt_include_signal_init));
   options.set_support_icarus_simulator(cmd_context.option_enable(cmd, opt_support_icarus_simulator));
+  options.set_print_user_defined_template(cmd_context.option_enable(cmd, opt_print_user_defined_template));
+  options.set_print_top_testbench(cmd_context.option_enable(cmd, opt_print_top_testbench));
+  options.set_print_formal_verification_top_netlist(cmd_context.option_enable(cmd, opt_print_formal_verification_top_netlist));
+  options.set_print_autocheck_top_testbench(cmd_context.option_value(cmd, opt_print_autocheck_top_testbench));
   options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
   options.set_compress_routing(openfpga_ctx.flow_manager().compress_routing());
   
-  fpga_fabric_verilog(openfpga_ctx.module_graph(),
+  fpga_fabric_verilog(openfpga_ctx.mutable_module_graph(),
                       openfpga_ctx.arch().circuit_lib,
                       openfpga_ctx.mux_lib(),
                       g_vpr_ctx.device().grid,
diff --git a/openfpga/src/base/openfpga_verilog_command.cpp b/openfpga/src/base/openfpga_verilog_command.cpp
index fa3ff9c4b..7eb7674b9 100644
--- a/openfpga/src/base/openfpga_verilog_command.cpp
+++ b/openfpga/src/base/openfpga_verilog_command.cpp
@@ -34,6 +34,15 @@ void add_openfpga_verilog_commands(openfpga::Shell<OpenfpgaContext>& shell) {
   shell_cmd_write_fabric_verilog.add_option("include_signal_init", false, "Initialize all the signals in Verilog netlists");
   /* Add an option '--support_icarus_simulator' */
   shell_cmd_write_fabric_verilog.add_option("support_icarus_simulator", false, "Fine-tune Verilog netlists to support icarus simulator");
+  /* Add an option '--print_user_defined_template' */
+  shell_cmd_write_fabric_verilog.add_option("print_user_defined_template", false, "Generate a template Verilog files for user-defined circuit models");
+  /* Add an option '--print_top_testbench' */
+  shell_cmd_write_fabric_verilog.add_option("print_top_testbench", false, "Generate a testbench for top-level fabric module");
+  /* Add an option '--print_formal_verification_top_netlist' */
+  shell_cmd_write_fabric_verilog.add_option("print_formal_verification_top_netlist", false, "Generate a top-level module which can be used in formal verification");
+  /* Add an option '--print_autocheck_top_testbench' */
+  CommandOptionId fabric_verilog_autocheck_tb_opt = shell_cmd_write_fabric_verilog.add_option("print_autocheck_top_testbench", false, "Generate a testbench for top-level fabric module with autocheck capability");
+  shell_cmd_write_fabric_verilog.set_option_require_value(fabric_verilog_autocheck_tb_opt, openfpga::OPT_STRING);
   /* Add an option '--verbose' */
   shell_cmd_write_fabric_verilog.add_option("verbose", false, "Enable verbose output");
   
diff --git a/openfpga/src/fpga_verilog/verilog_api.cpp b/openfpga/src/fpga_verilog/verilog_api.cpp
index 71ec0708d..baa18abb4 100644
--- a/openfpga/src/fpga_verilog/verilog_api.cpp
+++ b/openfpga/src/fpga_verilog/verilog_api.cpp
@@ -15,11 +15,9 @@
 #include "device_rr_gsb.h"
 #include "verilog_constants.h"
 #include "verilog_auxiliary_netlists.h"
-//#include "verilog_submodules.h"
+#include "verilog_submodule.h"
 //#include "verilog_routing.h"
-//#include "verilog_submodules.h"
 //#include "verilog_grid.h"
-//#include "verilog_routing.h"
 //#include "verilog_top_module.h"
 
 /* Header file for this source file */
@@ -40,8 +38,13 @@ namespace openfpga {
  * 6. Testbench, where a FPGA module is configured with a bitstream and then driven by input vectors
  * 7. Pre-configured testbench, which can skip the configuration phase and pre-configure the FPGA module. This testbench is created for quick verification and formal verification purpose.
  * 8. Verilog netlist including preprocessing flags and all the Verilog netlists that have been generated
+ *
+ * TODO: We should use module manager as a constant here. 
+ * All the modification should be done before this writer!
+ * The only exception now is the user-defined modules.
+ * We should think clearly about how to handle them for both Verilog and SPICE generators!
  ********************************************************************/
-void fpga_fabric_verilog(const ModuleManager& module_manager,
+void fpga_fabric_verilog(ModuleManager& module_manager,
                          const CircuitLibrary& circuit_lib,
                          const MuxLibrary& mux_lib,
                          const DeviceGrid& grids, 
@@ -81,8 +84,9 @@ void fpga_fabric_verilog(const ModuleManager& module_manager,
    * the module manager.
    * Without the modules in the module manager, core logic generation is not possible!!!
    */
-  //print_verilog_submodules(module_manager, mux_lib, sram_verilog_orgz_info, src_dir_path.c_str(), submodule_dir_path.c_str(), 
-  //                         Arch, vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts);
+  print_verilog_submodule(module_manager, mux_lib, circuit_lib,
+                          src_dir_path, submodule_dir_path, 
+                          options);
 
   /* Generate routing blocks */
   //if (true == compress_routing) {
diff --git a/openfpga/src/fpga_verilog/verilog_api.h b/openfpga/src/fpga_verilog/verilog_api.h
index a24c0a1e8..569650f2a 100644
--- a/openfpga/src/fpga_verilog/verilog_api.h
+++ b/openfpga/src/fpga_verilog/verilog_api.h
@@ -22,7 +22,7 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-void fpga_fabric_verilog(const ModuleManager& module_manager,
+void fpga_fabric_verilog(ModuleManager& module_manager,
                          const CircuitLibrary& circuit_lib,
                          const MuxLibrary& mux_lib,
                          const DeviceGrid& grids, 
diff --git a/openfpga/src/fpga_verilog/verilog_mux.cpp b/openfpga/src/fpga_verilog/verilog_mux.cpp
index b78a9362a..1e58e3fc8 100644
--- a/openfpga/src/fpga_verilog/verilog_mux.cpp
+++ b/openfpga/src/fpga_verilog/verilog_mux.cpp
@@ -1240,7 +1240,7 @@ void print_verilog_submodule_muxes(ModuleManager& module_manager,
   check_file_stream(verilog_fname.c_str(), fp);
 
   /* Print out debugging information for if the file is not opened/created properly */
-  VTR_LOG("Writing Verilog netlist for Multiplexers '%s' ...\n",
+  VTR_LOG("Writing Verilog netlist for Multiplexers '%s' ...",
           verilog_fname.c_str()); 
 
   print_verilog_file_header(fp, "Multiplexers"); 
diff --git a/openfpga/src/fpga_verilog/verilog_options.cpp b/openfpga/src/fpga_verilog/verilog_options.cpp
index 2539d5e51..b3b398dd7 100644
--- a/openfpga/src/fpga_verilog/verilog_options.cpp
+++ b/openfpga/src/fpga_verilog/verilog_options.cpp
@@ -8,6 +8,23 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
+/**************************************************
+ * Public Constructors
+ *************************************************/
+FabricVerilogOption::FabricVerilogOption() {
+  output_directory_.clear();
+  support_icarus_simulator_ = false;
+  include_signal_init_ = false;
+  include_timing_ = false;
+  explicit_port_mapping_ = false;
+  compress_routing_ = false;
+  print_top_testbench_ = false;
+  print_formal_verification_top_netlist_ = false;
+  reference_verilog_file_path_.clear();
+  print_user_defined_template_ = false;
+  verbose_output_ = false;
+}
+
 /**************************************************
  * Public Accessors 
  *************************************************/
@@ -51,6 +68,10 @@ std::string FabricVerilogOption::reference_verilog_file_path() const {
   return reference_verilog_file_path_;
 }
 
+bool FabricVerilogOption::print_user_defined_template() const {
+  return print_user_defined_template_;
+}
+
 bool FabricVerilogOption::verbose_output() const {
   return verbose_output_;
 }
@@ -94,6 +115,10 @@ void FabricVerilogOption::set_print_autocheck_top_testbench(const std::string& r
   reference_verilog_file_path_ = reference_verilog_file_path;
 }
 
+void FabricVerilogOption::set_print_user_defined_template(const bool& enabled) {
+  print_user_defined_template_ = enabled;
+}
+
 void FabricVerilogOption::set_verbose_output(const bool& enabled) {
   verbose_output_ = enabled;
 }
diff --git a/openfpga/src/fpga_verilog/verilog_options.h b/openfpga/src/fpga_verilog/verilog_options.h
index 182cabcf2..48e32086b 100644
--- a/openfpga/src/fpga_verilog/verilog_options.h
+++ b/openfpga/src/fpga_verilog/verilog_options.h
@@ -17,6 +17,9 @@ namespace openfpga {
  *
  *******************************************************************/
 class FabricVerilogOption {
+  public: /* Public constructor */
+    /* Set default options */
+    FabricVerilogOption();
   public: /* Public accessors */
     std::string output_directory() const;
     bool support_icarus_simulator() const;
@@ -28,6 +31,7 @@ class FabricVerilogOption {
     bool print_formal_verification_top_netlist() const;
     bool print_autocheck_top_testbench() const;
     std::string reference_verilog_file_path() const;
+    bool print_user_defined_template() const;
     bool verbose_output() const;
   public: /* Public mutators */
     void set_output_directory(const std::string& output_dir);
@@ -39,6 +43,7 @@ class FabricVerilogOption {
     void set_print_top_testbench(const bool& enabled);
     void set_print_formal_verification_top_netlist(const bool& enabled);
     void set_print_autocheck_top_testbench(const std::string& reference_verilog_file_path);
+    void set_print_user_defined_template(const bool& enabled);
     void set_verbose_output(const bool& enabled);
   private: /* Internal Data */
     std::string output_directory_;
@@ -51,6 +56,7 @@ class FabricVerilogOption {
     bool print_formal_verification_top_netlist_;
     /* print_autocheck_top_testbench will be enabled when reference file path is not empty */
     std::string reference_verilog_file_path_;
+    bool print_user_defined_template_;
     bool verbose_output_;
 };
 
diff --git a/openfpga/src/fpga_verilog/verilog_submodule.cpp b/openfpga/src/fpga_verilog/verilog_submodule.cpp
new file mode 100644
index 000000000..c52fc2262
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_submodule.cpp
@@ -0,0 +1,96 @@
+/*********************************************************************
+ * This file includes top-level function to generate Verilog primitive modules
+ * and print them to files
+ ********************************************************************/
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+#include "verilog_submodule_utils.h"
+#include "verilog_essential_gates.h"
+#include "verilog_decoders.h"
+#include "verilog_mux.h"
+#include "verilog_lut.h"
+#include "verilog_wire.h"
+#include "verilog_memory.h"
+#include "verilog_writer_utils.h"
+
+#include "verilog_constants.h"
+#include "verilog_submodule.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/*********************************************************************
+ * Top-level function to generate primitive modules:
+ * 1. Logic gates: AND/OR, inverter, buffer and transmission-gate/pass-transistor
+ * 2. Routing multiplexers
+ * 3. Local encoders for routing multiplexers
+ * 4. Wires
+ * 5. Configuration memory blocks
+ * 6. Verilog template
+ ********************************************************************/
+void print_verilog_submodule(ModuleManager& module_manager, 
+                             const MuxLibrary& mux_lib,
+                             const CircuitLibrary& circuit_lib, 
+                             const std::string& verilog_dir, 
+                             const std::string& submodule_dir, 
+                             const FabricVerilogOption& fpga_verilog_opts) {
+
+  /* Register all the user-defined modules in the module manager
+   * This should be done prior to other steps in this function, 
+   * because they will be instanciated by other primitive modules 
+   */
+  add_user_defined_verilog_modules(module_manager, circuit_lib);
+
+  /* Create a vector to contain all the Verilog netlist names that have been generated in this function */
+  std::vector<std::string> netlist_names;
+
+
+  print_verilog_submodule_essentials(module_manager, 
+                                     netlist_names,
+                                     verilog_dir, 
+                                     submodule_dir,
+                                     circuit_lib);
+
+  /* Routing multiplexers */
+  /* NOTE: local decoders generation must go before the MUX generation!!! 
+   *       because local decoders modules will be instanciated in the MUX modules 
+   */
+  print_verilog_submodule_mux_local_decoders(module_manager, netlist_names, 
+                                             mux_lib, circuit_lib, 
+                                             verilog_dir, submodule_dir);
+  print_verilog_submodule_muxes(module_manager, netlist_names, mux_lib, circuit_lib,
+                                verilog_dir, submodule_dir,
+                                fpga_verilog_opts.explicit_port_mapping());
+
+ 
+  /* LUTes */
+  print_verilog_submodule_luts(module_manager, netlist_names, circuit_lib,
+                               verilog_dir, submodule_dir,
+                               fpga_verilog_opts.explicit_port_mapping());
+
+  /* Hard wires */
+  print_verilog_submodule_wires(module_manager, netlist_names, circuit_lib,
+                                verilog_dir, submodule_dir);
+
+  /* 4. Memories */
+  print_verilog_submodule_memories(module_manager, netlist_names,
+                                   mux_lib, circuit_lib, 
+                                   verilog_dir, submodule_dir,
+                                   fpga_verilog_opts.explicit_port_mapping());
+
+  /* 5. Dump template for all the modules */
+  if (true == fpga_verilog_opts.print_user_defined_template()) { 
+    print_verilog_submodule_templates(module_manager, circuit_lib,
+                                      verilog_dir, submodule_dir);
+  }
+
+  /* Create a header file to include all the subckts */
+  print_verilog_netlist_include_header_file(netlist_names,
+                                            submodule_dir.c_str(),
+                                            SUBMODULE_VERILOG_FILE_NAME);
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_verilog/verilog_submodule.h b/openfpga/src/fpga_verilog/verilog_submodule.h
new file mode 100644
index 000000000..4f7cb511c
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_submodule.h
@@ -0,0 +1,27 @@
+#ifndef VERILOG_SUBMODULE_H
+#define VERILOG_SUBMODULE_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "module_manager.h"
+#include "mux_library.h"
+#include "verilog_options.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void print_verilog_submodule(ModuleManager& module_manager, 
+                             const MuxLibrary& mux_lib,
+                             const CircuitLibrary& circuit_lib, 
+                             const std::string& verilog_dir, 
+                             const std::string& submodule_dir, 
+                             const FabricVerilogOption& fpga_verilog_opts);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/fpga_verilog/verilog_submodule_utils.cpp b/openfpga/src/fpga_verilog/verilog_submodule_utils.cpp
index f4f02472d..b4255b3e9 100644
--- a/openfpga/src/fpga_verilog/verilog_submodule_utils.cpp
+++ b/openfpga/src/fpga_verilog/verilog_submodule_utils.cpp
@@ -132,6 +132,8 @@ void print_verilog_submodule_signal_init(std::fstream& fp,
  ********************************************************************/
 void add_user_defined_verilog_modules(ModuleManager& module_manager, 
                                       const CircuitLibrary& circuit_lib) {
+  VTR_LOG("Registering user-defined modules...");
+
   /* Iterate over Verilog modules */
   for (const auto& model : circuit_lib.models()) {
     /* We only care about user-defined models */
@@ -149,8 +151,12 @@ void add_user_defined_verilog_modules(ModuleManager& module_manager,
     ModuleId module_id = module_manager.find_module(circuit_lib.model_name(model));
     if (ModuleId::INVALID() == module_id) {
       add_circuit_model_to_module_manager(module_manager, circuit_lib, model);
+      VTR_LOG("Registered user-defined circuit model '%s'\n",
+              circuit_lib.model_name(model).c_str());
     }
   }
+
+  VTR_LOG("Done\n");
 }
 
 /*********************************************************************
diff --git a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp
index 28f2ed5db..600357c36 100644
--- a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp
+++ b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp
@@ -1374,8 +1374,12 @@ void print_verilog_clock_stimuli(std::fstream& fp,
 void print_verilog_netlist_include_header_file(const std::vector<std::string>& netlists_to_be_included,
                                                const char* subckt_dir,
                                                const char* header_file_name) {
+
   std::string verilog_fname(std::string(subckt_dir) + std::string(header_file_name));
 
+  VTR_LOG("Writing header file for primitive modules '%s' ...",
+          verilog_fname.c_str());
+
   /* Create the file stream */
   std::fstream fp;
   fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
@@ -1392,6 +1396,8 @@ void print_verilog_netlist_include_header_file(const std::vector<std::string>& n
 
   /* close file stream */
   fp.close();
+
+  VTR_LOG("Done\n");
 }
 
 } /* end namespace openfpga */
diff --git a/openfpga/test_script/s298_k6_frac.openfpga b/openfpga/test_script/s298_k6_frac.openfpga
index 1dece6d57..c01774bd3 100644
--- a/openfpga/test_script/s298_k6_frac.openfpga
+++ b/openfpga/test_script/s298_k6_frac.openfpga
@@ -23,7 +23,7 @@ build_fabric --compress_routing --duplicate_grid_pin --verbose
 
 # Write the Verilog netlit for FPGA fabric
 #  - Enable the use of explicit port mapping in Verilog netlist
-write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --verbose
+write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
 
 # Finish and exit OpenFPGA
 exit

From c20caa1fa385e415b7831039c01f9be98cb9c961 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 16 Feb 2020 14:47:54 -0700
Subject: [PATCH 159/645] routing module Verilog writer is online

---
 openfpga/src/fpga_verilog/verilog_api.cpp     |  24 +-
 openfpga/src/fpga_verilog/verilog_constants.h |   2 +
 openfpga/src/fpga_verilog/verilog_routing.cpp | 355 ++++++++++++++++++
 openfpga/src/fpga_verilog/verilog_routing.h   |  33 ++
 4 files changed, 403 insertions(+), 11 deletions(-)
 create mode 100644 openfpga/src/fpga_verilog/verilog_routing.cpp
 create mode 100644 openfpga/src/fpga_verilog/verilog_routing.h

diff --git a/openfpga/src/fpga_verilog/verilog_api.cpp b/openfpga/src/fpga_verilog/verilog_api.cpp
index baa18abb4..aa68e0024 100644
--- a/openfpga/src/fpga_verilog/verilog_api.cpp
+++ b/openfpga/src/fpga_verilog/verilog_api.cpp
@@ -16,7 +16,7 @@
 #include "verilog_constants.h"
 #include "verilog_auxiliary_netlists.h"
 #include "verilog_submodule.h"
-//#include "verilog_routing.h"
+#include "verilog_routing.h"
 //#include "verilog_grid.h"
 //#include "verilog_top_module.h"
 
@@ -89,16 +89,18 @@ void fpga_fabric_verilog(ModuleManager& module_manager,
                           options);
 
   /* Generate routing blocks */
-  //if (true == compress_routing) {
-  //  print_verilog_unique_routing_modules(module_manager, device_rr_gsb,  
-  //                                       src_dir_path, rr_dir_path,
-  //                                       dump_explicit_verilog);
-  //} else {
-  //  VTR_ASSERT(false == compress_routing);
-  //  print_verilog_flatten_routing_modules(module_manager, device_rr_gsb, 
-  //                                        src_dir_path, rr_dir_path,
-  //                                        dump_explicit_verilog);
-  //}
+  if (true == options.compress_routing()) {
+    print_verilog_unique_routing_modules(const_cast<const ModuleManager&>(module_manager),
+                                         device_rr_gsb,  
+                                         src_dir_path, rr_dir_path,
+                                         options.explicit_port_mapping());
+  } else {
+    VTR_ASSERT(false == options.compress_routing());
+    print_verilog_flatten_routing_modules(const_cast<const ModuleManager&>(module_manager),
+                                          device_rr_gsb, 
+                                          src_dir_path, rr_dir_path,
+                                          options.explicit_port_mapping());
+  }
 
   /* Generate grids */
   //print_verilog_grids(module_manager, 
diff --git a/openfpga/src/fpga_verilog/verilog_constants.h b/openfpga/src/fpga_verilog/verilog_constants.h
index 91f87c475..d5e1f4edb 100644
--- a/openfpga/src/fpga_verilog/verilog_constants.h
+++ b/openfpga/src/fpga_verilog/verilog_constants.h
@@ -44,4 +44,6 @@ constexpr char* USER_DEFINED_TEMPLATE_VERILOG_FILE_NAME = "user_defined_template
 constexpr char* VERILOG_MUX_BASIS_POSTFIX = "_basis";
 constexpr char* VERILOG_MEM_POSTFIX = "_mem";
 
+constexpr char* SB_VERILOG_FILE_NAME_PREFIX = "sb_";
+
 #endif
diff --git a/openfpga/src/fpga_verilog/verilog_routing.cpp b/openfpga/src/fpga_verilog/verilog_routing.cpp
new file mode 100644
index 000000000..0d9582556
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_routing.cpp
@@ -0,0 +1,355 @@
+/*********************************************************************
+ * This file includes functions that are used for 
+ * Verilog generation of FPGA routing architecture (global routing) 
+ *********************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_time.h"
+#include "vtr_log.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_digest.h"
+
+/* Include FPGA-Verilog header files*/
+#include "openfpga_naming.h"
+#include "verilog_constants.h"
+#include "verilog_writer_utils.h"
+#include "verilog_module_writer.h"
+#include "verilog_routing.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/******************************************************************** 
+ * Print the sub-circuit of a connection Box (Type: [CHANX|CHANY])
+ * Actually it is very similiar to switch box but
+ * the difference is connection boxes connect Grid INPUT Pins to channels
+ * NOTE: direct connection between CLBs should NOT be included inside this
+ *       module! They should be added in the top-level module as their connection
+ *       is not limited to adjacent CLBs!!!
+ *
+ * Location of a X- and Y-direction Connection Block in FPGA fabric
+ *               +------------+       +-------------+ 
+ *               |            |------>|             |
+ *               |     CLB    |<------| Y-direction |
+ *               |            | ...   |  Connection |
+ *               |            |------>|    Block    |
+ *               +------------+       +-------------+
+ *                 |  ^ ... |            | ^ ... |
+ *                 v  |     v            v |     v
+ *           +-------------------+    +-------------+
+ *       --->|                   |--->|             |
+ *       <---|     X-direction   |<---|    Switch   |                           
+ *        ...|  Connection block |... |    Block    |
+ *       --->|                   |--->|             |
+ *           +-------------------+    +-------------+
+ *
+ *  Internal structure:
+ *  This is an example of a X-direction connection block  
+ *  Note that middle output ports are shorted wire from inputs of routing tracks, 
+ *  which are also the inputs of routing multiplexer of the connection block 
+ *
+ *                      CLB Input Pins
+ *                         (IPINs)
+ *                       ^   ^     ^
+ *                       |   | ... |
+ *              +--------------------------+
+ *              |       ^    ^     ^       |
+ *              |       |    | ... |       |   
+ *              |  +--------------------+  | 
+ *              |  |       routing      |  |
+ *              |  |    multiplexers    |  |
+ *              |  +--------------------+  | 
+ *              |      middle outputs      |
+ *              |    of routing channel    |
+ *              |    ^ ^ ^ ^     ^ ^ ^ ^   |
+ *              |    | | | | ... | | | |   |
+ *     in[0] -->|------------------------->|---> out[0]
+ *    out[1] <--|<-------------------------|<--- in[1]
+ *              |           ...            |
+ *   in[W-2] -->|------------------------->|---> out[W-2]
+ *  out[W-1] <--|<-------------------------|<--- in[W-1]
+ *              +--------------------------+
+ *
+ *  W: routing channel width
+ *              
+ ********************************************************************/
+static 
+void print_verilog_routing_connection_box_unique_module(const ModuleManager& module_manager, 
+                                                        std::vector<std::string>& netlist_names,
+                                                        const std::string& verilog_dir, 
+                                                        const std::string& subckt_dir, 
+                                                        const RRGSB& rr_gsb,
+                                                        const t_rr_type& cb_type,
+                                                        const bool& use_explicit_port_map) {
+  /* Create the netlist */
+  vtr::Point<size_t> gsb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type));
+  std::string verilog_fname(subckt_dir + generate_connection_block_netlist_name(cb_type, gsb_coordinate, std::string(VERILOG_NETLIST_FILE_POSTFIX)));
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
+
+  check_file_stream(verilog_fname.c_str(), fp);
+
+  print_verilog_file_header(fp, std::string("Verilog modules for Unique Connection Blocks[" + std::to_string(rr_gsb.get_cb_x(cb_type)) + "]["+ std::to_string(rr_gsb.get_cb_y(cb_type)) + "]")); 
+
+  /* Print preprocessing flags */
+  print_verilog_include_defines_preproc_file(fp, verilog_dir);
+
+  /* Create a Verilog Module based on the circuit model, and add to module manager */
+  ModuleId cb_module = module_manager.find_module(generate_connection_block_module_name(cb_type, gsb_coordinate)); 
+  VTR_ASSERT(true == module_manager.valid_module_id(cb_module));
+
+  /* Write the verilog module */
+  write_verilog_module_to_file(fp, module_manager, cb_module, use_explicit_port_map);
+ 
+  /* Add an empty line as a splitter */
+  fp << std::endl;
+
+  /* Close file handler */
+  fp.close();
+
+  /* Add fname to the netlist name list */
+  netlist_names.push_back(verilog_fname);
+}
+
+/*********************************************************************
+ * Generate the Verilog module for a Switch Box.
+ * A Switch Box module consists of following ports:
+ * 1. Channel Y [x][y] inputs 
+ * 2. Channel X [x+1][y] inputs
+ * 3. Channel Y [x][y-1] outputs
+ * 4. Channel X [x][y] outputs
+ * 5. Grid[x][y+1] Right side outputs pins
+ * 6. Grid[x+1][y+1] Left side output pins
+ * 7. Grid[x+1][y+1] Bottom side output pins
+ * 8. Grid[x+1][y] Top side output pins
+ * 9. Grid[x+1][y] Left side output pins
+ * 10. Grid[x][y] Right side output pins
+ * 11. Grid[x][y] Top side output pins
+ * 12. Grid[x][y+1] Bottom side output pins
+ *
+ * Location of a Switch Box in FPGA fabric:
+ *
+ *    --------------          --------------
+ *    |            |          |            |
+ *    |    Grid    |  ChanY   |    Grid    |
+ *    |  [x][y+1]  | [x][y+1] | [x+1][y+1] |
+ *    |            |          |            |
+ *    --------------          --------------
+ *                  ----------
+ *       ChanX      | Switch |     ChanX 
+ *       [x][y]     |   Box  |    [x+1][y]
+ *                  | [x][y] |
+ *                  ----------
+ *    --------------          --------------
+ *    |            |          |            |
+ *    |    Grid    |  ChanY   |    Grid    |
+ *    |   [x][y]   |  [x][y]  |  [x+1][y]  |
+ *    |            |          |            |
+ *    --------------          --------------
+ *
+ * Switch Block pin location map
+ *
+ *                       Grid[x][y+1]   ChanY[x][y+1]  Grid[x+1][y+1] 
+ *                        right_pins  inputs/outputs     left_pins
+ *                            |             ^                |
+ *                            |             |                |
+ *                            v             v                v
+ *                    +-----------------------------------------------+
+ *                    |                                               |
+ *    Grid[x][y+1]    |                                               |    Grid[x+1][y+1]
+ *    bottom_pins---->|                                               |<---- bottom_pins
+ *                    |                                               |
+ * ChanX[x][y]        |              Switch Box [x][y]                |     ChanX[x+1][y]
+ * inputs/outputs<--->|                                               |<---> inputs/outputs
+ *                    |                                               |
+ *    Grid[x][y+1]    |                                               |    Grid[x+1][y+1]
+ *       top_pins---->|                                               |<---- top_pins
+ *                    |                                               |
+ *                    +-----------------------------------------------+
+ *                            ^             ^                ^
+ *                            |             |                |
+ *                            |             v                |
+ *                       Grid[x][y]     ChanY[x][y]      Grid[x+1][y] 
+ *                       right_pins    inputs/outputs      left_pins
+ *
+ *
+ ********************************************************************/
+static 
+void print_verilog_routing_switch_box_unique_module(const ModuleManager& module_manager, 
+                                                    std::vector<std::string>& netlist_names,
+                                                    const std::string& verilog_dir, 
+                                                    const std::string& subckt_dir, 
+                                                    const RRGSB& rr_gsb,
+                                                    const bool& use_explicit_port_map) {
+  /* Create the netlist */
+  vtr::Point<size_t> gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
+  std::string verilog_fname(subckt_dir + generate_routing_block_netlist_name(SB_VERILOG_FILE_NAME_PREFIX, gsb_coordinate, std::string(VERILOG_NETLIST_FILE_POSTFIX)));
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
+
+  check_file_stream(verilog_fname.c_str(), fp);
+
+  print_verilog_file_header(fp, std::string("Verilog modules for Unique Switch Blocks[" + std::to_string(rr_gsb.get_sb_x()) + "]["+ std::to_string(rr_gsb.get_sb_y()) + "]")); 
+
+  /* Print preprocessing flags */
+  print_verilog_include_defines_preproc_file(fp, verilog_dir);
+
+  /* Create a Verilog Module based on the circuit model, and add to module manager */
+  ModuleId sb_module = module_manager.find_module(generate_switch_block_module_name(gsb_coordinate)); 
+  VTR_ASSERT(true == module_manager.valid_module_id(sb_module));
+
+  /* Write the verilog module */
+  write_verilog_module_to_file(fp, module_manager, sb_module, use_explicit_port_map);
+ 
+  /* Close file handler */
+  fp.close();
+
+  /* Add fname to the netlist name list */
+  netlist_names.push_back(verilog_fname);
+}
+
+/********************************************************************
+ * Iterate over all the connection blocks in a device
+ * and build a module for each of them 
+ *******************************************************************/
+static 
+void print_verilog_flatten_connection_block_modules(const ModuleManager& module_manager, 
+                                                    std::vector<std::string>& netlist_names,
+                                                    const DeviceRRGSB& device_rr_gsb,
+                                                    const std::string& verilog_dir,
+                                                    const std::string& subckt_dir,
+                                                    const t_rr_type& cb_type,
+                                                    const bool& use_explicit_port_map) {
+  /* Build unique X-direction connection block modules */
+  vtr::Point<size_t> cb_range = device_rr_gsb.get_gsb_range();
+
+  for (size_t ix = 0; ix < cb_range.x(); ++ix) {
+    for (size_t iy = 0; iy < cb_range.y(); ++iy) {
+      /* Check if the connection block exists in the device!
+       * Some of them do NOT exist due to heterogeneous blocks (height > 1) 
+       * We will skip those modules
+       */
+      const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
+      if (true != rr_gsb.is_cb_exist(cb_type)) {
+        continue;
+      }
+      print_verilog_routing_connection_box_unique_module(module_manager, netlist_names, 
+                                                         verilog_dir,
+                                                         subckt_dir, 
+                                                         rr_gsb, cb_type,  
+                                                         use_explicit_port_map);
+    }
+  }
+}
+
+/********************************************************************
+ * A top-level function of this file
+ * Print all the modules for global routing architecture of a FPGA fabric
+ * in Verilog format  in a flatten way:
+ *   Each connection block and switch block will be generated as a unique module
+ * Covering:
+ * 1. Connection blocks
+ * 2. Switch blocks
+ *******************************************************************/
+void print_verilog_flatten_routing_modules(const ModuleManager& module_manager,
+                                           const DeviceRRGSB& device_rr_gsb,
+                                           const std::string& verilog_dir,
+                                           const std::string& subckt_dir,
+                                           const bool& use_explicit_port_map) {
+  /* Create a vector to contain all the Verilog netlist names that have been generated in this function */
+  std::vector<std::string> netlist_names;
+
+  vtr::Point<size_t> sb_range = device_rr_gsb.get_gsb_range();
+
+  /* Build unique switch block modules */
+  for (size_t ix = 0; ix < sb_range.x(); ++ix) {
+    for (size_t iy = 0; iy < sb_range.y(); ++iy) {
+      const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
+      if (true != rr_gsb.is_sb_exist()) {
+        continue;
+      }
+      print_verilog_routing_switch_box_unique_module(module_manager, netlist_names, 
+                                                     verilog_dir,
+                                                     subckt_dir, 
+                                                     rr_gsb, 
+                                                     use_explicit_port_map);
+    }
+  }
+
+  print_verilog_flatten_connection_block_modules(module_manager, netlist_names, device_rr_gsb, verilog_dir, subckt_dir, CHANX, use_explicit_port_map);
+
+  print_verilog_flatten_connection_block_modules(module_manager, netlist_names, device_rr_gsb, verilog_dir, subckt_dir, CHANY, use_explicit_port_map);
+
+  VTR_LOG("Writing header file for routing submodules '%s'...",
+          ROUTING_VERILOG_FILE_NAME);
+  print_verilog_netlist_include_header_file(netlist_names,
+                                            subckt_dir.c_str(),
+                                            ROUTING_VERILOG_FILE_NAME);
+  VTR_LOG("Done\n");
+}
+
+
+/********************************************************************
+ * A top-level function of this file
+ * Print all the unique modules for global routing architecture of a FPGA fabric
+ * in Verilog format, including: 
+ * 1. Connection blocks
+ * 2. Switch blocks
+ *
+ * Note: this function SHOULD be called only when 
+ * the option compact_routing_hierarchy is turned on!!!
+ *******************************************************************/
+void print_verilog_unique_routing_modules(const ModuleManager& module_manager,
+                                          const DeviceRRGSB& device_rr_gsb,
+                                          const std::string& verilog_dir,
+                                          const std::string& subckt_dir,
+                                          const bool& use_explicit_port_map) {
+  /* Create a vector to contain all the Verilog netlist names that have been generated in this function */
+  std::vector<std::string> netlist_names;
+
+  /* Build unique switch block modules */
+  for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_module(); ++isb) {
+    const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(isb);
+    print_verilog_routing_switch_box_unique_module(module_manager, netlist_names,
+                                                   verilog_dir,
+                                                   subckt_dir, 
+                                                   unique_mirror, 
+                                                   use_explicit_port_map);
+  }
+
+  /* Build unique X-direction connection block modules */
+  for (size_t icb = 0; icb < device_rr_gsb.get_num_cb_unique_module(CHANX); ++icb) {
+    const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANX, icb);
+
+    print_verilog_routing_connection_box_unique_module(module_manager, netlist_names,
+                                                       verilog_dir,
+                                                       subckt_dir, 
+                                                       unique_mirror, CHANX,  
+                                                       use_explicit_port_map);
+  }
+
+  /* Build unique X-direction connection block modules */
+  for (size_t icb = 0; icb < device_rr_gsb.get_num_cb_unique_module(CHANY); ++icb) {
+    const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANY, icb);
+
+    print_verilog_routing_connection_box_unique_module(module_manager, netlist_names, 
+                                                       verilog_dir,
+                                                       subckt_dir, 
+                                                       unique_mirror, CHANY,  
+                                                       use_explicit_port_map);
+  }
+
+  VTR_LOG("Writing header file for routing submodules '%s'...",
+          ROUTING_VERILOG_FILE_NAME);
+  print_verilog_netlist_include_header_file(netlist_names,
+                                            subckt_dir.c_str(),
+                                            ROUTING_VERILOG_FILE_NAME);
+  VTR_LOG("Done\n");
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_verilog/verilog_routing.h b/openfpga/src/fpga_verilog/verilog_routing.h
new file mode 100644
index 000000000..2a1a58a66
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_routing.h
@@ -0,0 +1,33 @@
+#ifndef VERILOG_ROUTING_H
+#define VERILOG_ROUTING_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+
+#include "mux_library.h"
+#include "module_manager.h"
+#include "device_rr_gsb.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void print_verilog_flatten_routing_modules(const ModuleManager& module_manager,
+                                           const DeviceRRGSB& device_rr_gsb,
+                                           const std::string& verilog_dir,
+                                           const std::string& subckt_dir,
+                                           const bool& use_explicit_port_map);
+
+void print_verilog_unique_routing_modules(const ModuleManager& module_manager,
+                                          const DeviceRRGSB& device_rr_gsb,
+                                          const std::string& verilog_dir,
+                                          const std::string& subckt_dir,
+                                          const bool& use_explicit_port_map);
+
+} /* end namespace openfpga */
+
+#endif

From e37ac8a09800ca75cad7a3c03f89cb77eea4a5f5 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 16 Feb 2020 16:04:41 -0700
Subject: [PATCH 160/645] add grid module Verilog writer

---
 openfpga/src/base/openfpga_naming.cpp         |  16 +
 openfpga/src/base/openfpga_naming.h           |   4 +
 openfpga/src/base/openfpga_verilog.cpp        |   3 +-
 openfpga/src/fpga_verilog/verilog_api.cpp     |  13 +-
 openfpga/src/fpga_verilog/verilog_api.h       |   6 +-
 openfpga/src/fpga_verilog/verilog_constants.h |   2 +
 openfpga/src/fpga_verilog/verilog_grid.cpp    | 411 ++++++++++++++++++
 openfpga/src/fpga_verilog/verilog_grid.h      |  30 ++
 openfpga/src/fpga_verilog/verilog_routing.cpp |   2 +
 9 files changed, 479 insertions(+), 8 deletions(-)
 create mode 100644 openfpga/src/fpga_verilog/verilog_grid.cpp
 create mode 100644 openfpga/src/fpga_verilog/verilog_grid.h

diff --git a/openfpga/src/base/openfpga_naming.cpp b/openfpga/src/base/openfpga_naming.cpp
index 7aaafff5d..fab27a12b 100644
--- a/openfpga/src/base/openfpga_naming.cpp
+++ b/openfpga/src/base/openfpga_naming.cpp
@@ -905,6 +905,22 @@ std::string generate_mux_sram_port_name(const CircuitLibrary& circuit_lib,
   return generate_local_sram_port_name(prefix, mux_instance_id, port_type);
 }
 
+/*********************************************************************
+ * Generate the netlist name of a logical tile
+ **********************************************************************/
+std::string generate_logical_tile_netlist_name(const std::string& prefix,
+                                               const t_pb_graph_node* pb_graph_head,
+                                               const std::string& postfix) {
+  /* This must be the root node */
+  VTR_ASSERT(true == pb_graph_head->is_root());
+  /* Add the name of physical block */
+  std::string module_name = prefix + std::string(pb_graph_head->pb_type->name);
+
+  module_name += postfix;
+
+  return module_name;
+}
+
 /*********************************************************************
  * Generate the prefix for naming a grid block netlist or a grid module
  * This function will consider the io side and add it to the prefix 
diff --git a/openfpga/src/base/openfpga_naming.h b/openfpga/src/base/openfpga_naming.h
index 4bc22f3c9..13d4c56c0 100644
--- a/openfpga/src/base/openfpga_naming.h
+++ b/openfpga/src/base/openfpga_naming.h
@@ -200,6 +200,10 @@ std::string generate_mux_sram_port_name(const CircuitLibrary& circuit_lib,
                                         const size_t& mux_instance_id,
                                         const e_circuit_model_port_type& port_type);
 
+std::string generate_logical_tile_netlist_name(const std::string& prefix,
+                                               const t_pb_graph_node* pb_graph_head,
+                                               const std::string& postfix);
+
 std::string generate_grid_block_prefix(const std::string& prefix,
                                        const e_side& io_side);
 
diff --git a/openfpga/src/base/openfpga_verilog.cpp b/openfpga/src/base/openfpga_verilog.cpp
index 018fe1249..72b8fb100 100644
--- a/openfpga/src/base/openfpga_verilog.cpp
+++ b/openfpga/src/base/openfpga_verilog.cpp
@@ -50,7 +50,8 @@ void write_fabric_verilog(OpenfpgaContext& openfpga_ctx,
   fpga_fabric_verilog(openfpga_ctx.mutable_module_graph(),
                       openfpga_ctx.arch().circuit_lib,
                       openfpga_ctx.mux_lib(),
-                      g_vpr_ctx.device().grid,
+                      g_vpr_ctx.device(),
+                      openfpga_ctx.vpr_device_annotation(),
                       openfpga_ctx.device_rr_gsb(),
                       options);
 } 
diff --git a/openfpga/src/fpga_verilog/verilog_api.cpp b/openfpga/src/fpga_verilog/verilog_api.cpp
index aa68e0024..ce339e813 100644
--- a/openfpga/src/fpga_verilog/verilog_api.cpp
+++ b/openfpga/src/fpga_verilog/verilog_api.cpp
@@ -17,7 +17,7 @@
 #include "verilog_auxiliary_netlists.h"
 #include "verilog_submodule.h"
 #include "verilog_routing.h"
-//#include "verilog_grid.h"
+#include "verilog_grid.h"
 //#include "verilog_top_module.h"
 
 /* Header file for this source file */
@@ -47,7 +47,8 @@ namespace openfpga {
 void fpga_fabric_verilog(ModuleManager& module_manager,
                          const CircuitLibrary& circuit_lib,
                          const MuxLibrary& mux_lib,
-                         const DeviceGrid& grids, 
+                         const DeviceContext& device_ctx, 
+                         const VprDeviceAnnotation& device_annotation, 
                          const DeviceRRGSB& device_rr_gsb,
                          const FabricVerilogOption& options) {
 
@@ -103,9 +104,11 @@ void fpga_fabric_verilog(ModuleManager& module_manager,
   }
 
   /* Generate grids */
-  //print_verilog_grids(module_manager, 
-  //                    src_dir_path, lb_dir_path,
-  //                    dump_explicit_verilog);
+  print_verilog_grids(const_cast<const ModuleManager&>(module_manager),
+                      device_ctx, device_annotation, 
+                      src_dir_path, lb_dir_path,
+                      options.explicit_port_mapping(),
+                      options.verbose_output());
 
   /* Generate FPGA fabric */
   //print_verilog_top_module(module_manager, 
diff --git a/openfpga/src/fpga_verilog/verilog_api.h b/openfpga/src/fpga_verilog/verilog_api.h
index 569650f2a..7494a5a8f 100644
--- a/openfpga/src/fpga_verilog/verilog_api.h
+++ b/openfpga/src/fpga_verilog/verilog_api.h
@@ -10,7 +10,8 @@
 #include "vpr_types.h"
 #include "mux_library.h"
 #include "circuit_library.h"
-#include "device_grid.h"
+#include "vpr_context.h"
+#include "vpr_device_annotation.h"
 #include "device_rr_gsb.h"
 #include "module_manager.h"
 #include "verilog_options.h"
@@ -25,7 +26,8 @@ namespace openfpga {
 void fpga_fabric_verilog(ModuleManager& module_manager,
                          const CircuitLibrary& circuit_lib,
                          const MuxLibrary& mux_lib,
-                         const DeviceGrid& grids, 
+                         const DeviceContext& device_ctx, 
+                         const VprDeviceAnnotation& device_annotation, 
                          const DeviceRRGSB& device_rr_gsb,
                          const FabricVerilogOption& options);
 
diff --git a/openfpga/src/fpga_verilog/verilog_constants.h b/openfpga/src/fpga_verilog/verilog_constants.h
index d5e1f4edb..e355b7a5f 100644
--- a/openfpga/src/fpga_verilog/verilog_constants.h
+++ b/openfpga/src/fpga_verilog/verilog_constants.h
@@ -45,5 +45,7 @@ constexpr char* VERILOG_MUX_BASIS_POSTFIX = "_basis";
 constexpr char* VERILOG_MEM_POSTFIX = "_mem";
 
 constexpr char* SB_VERILOG_FILE_NAME_PREFIX = "sb_";
+constexpr char* LOGICAL_MODULE_VERILOG_FILE_NAME_PREFIX = "logical_tile_";
+constexpr char* GRID_VERILOG_FILE_NAME_PREFIX = "grid_";
 
 #endif
diff --git a/openfpga/src/fpga_verilog/verilog_grid.cpp b/openfpga/src/fpga_verilog/verilog_grid.cpp
new file mode 100644
index 000000000..73e69ca29
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_grid.cpp
@@ -0,0 +1,411 @@
+/********************************************************************
+ * This file includes functions to print Verilog modules for a Grid
+ * (CLBs, I/Os, heterogeneous blocks etc.) 
+ *******************************************************************/
+/* System header files */
+#include <vector>
+#include <fstream>
+
+/* Headers from vtrutil library */
+#include "vtr_geometry.h"
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+/* Headers from readarch library */
+#include "physical_types.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_digest.h"
+#include "openfpga_side_manager.h"
+
+/* Headers from vpr library */
+#include "vpr_utils.h"
+
+#include "openfpga_reserved_words.h"
+#include "openfpga_naming.h"
+#include "pb_type_utils.h"
+#include "circuit_library_utils.h"
+#include "module_manager_utils.h"
+
+#include "verilog_constants.h"
+#include "verilog_writer_utils.h"
+#include "verilog_module_writer.h"
+#include "verilog_grid.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Print Verilog modules of a primitive node in the pb_graph_node graph
+ * This generic function can support all the different types of primitive nodes
+ * i.e., Look-Up Tables (LUTs), Flip-flops (FFs) and hard logic blocks such as adders.
+ *
+ * The Verilog module will consist of two parts:
+ * 1. Logic module of the primitive node
+ *    This module performs the logic function of the block
+ * 2. Memory module of the primitive node
+ *    This module stores the configuration bits for the logic module
+ *    if the logic module is a programmable resource, such as LUT
+ *
+ * Verilog module structure:
+ *
+ *       Primitive block
+ *     +---------------------------------------+
+ *     |                                       | 
+ *     |      +---------+    +---------+       |
+ *  in |----->|         |--->|         |<------|configuration lines
+ *     |      |  Logic  |... |  Memory |       |
+ *  out|<-----|         |--->|         |       |
+ *     |      +---------+    +---------+       |
+ *     |                                       | 
+ *     +---------------------------------------+
+ *
+ *******************************************************************/
+static 
+void print_verilog_primitive_block(std::fstream& fp,
+                                   const ModuleManager& module_manager,
+                                   t_pb_graph_node* primitive_pb_graph_node,
+                                   const bool& use_explicit_mapping,
+                                   const bool& verbose) {
+  /* Ensure a valid file handler */ 
+  VTR_ASSERT(true == valid_file_stream(fp));
+
+  /* Ensure a valid pb_graph_node */ 
+  if (nullptr == primitive_pb_graph_node) {
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid primitive_pb_graph_node!\n");
+    exit(1);
+  }
+
+  /* Generate the module name for this primitive pb_graph_node*/
+  std::string primitive_module_name = generate_physical_block_module_name(primitive_pb_graph_node->pb_type);
+
+  /* Create a module of the primitive LUT and register it to module manager */
+  ModuleId primitive_module = module_manager.find_module(primitive_module_name);
+  /* Ensure that the module has been created and thus unique! */
+  VTR_ASSERT(true == module_manager.valid_module_id(primitive_module));
+
+  VTR_LOGV(verbose,
+          "Writing Verilog codes of logical tile primitive block '%s'...",
+           module_manager.module_name(primitive_module).c_str());
+  
+  /* Write the verilog module */
+  write_verilog_module_to_file(fp, module_manager, primitive_module, use_explicit_mapping);
+
+  /* Add an empty line as a splitter */
+  fp << std::endl;
+
+  VTR_LOGV(verbose, "Done\n");
+}
+
+/********************************************************************
+ * Print Verilog modules of physical blocks inside a grid (CLB, I/O. etc.)
+ * This function will traverse the graph of complex logic block (t_pb_graph_node)
+ * in a recursive way, using a Depth First Search (DFS) algorithm.
+ * As such, primitive physical blocks (LUTs, FFs, etc.), leaf node of the pb_graph
+ * will be printed out first, while the top-level will be printed out in the last
+ *
+ * Note: this function will print a unique Verilog module for each type of 
+ * t_pb_graph_node, i.e., t_pb_type, in the graph, in order to enable highly 
+ * hierarchical Verilog organization as well as simplify the Verilog file sizes.
+ *
+ * Note: DFS is the right way. Do NOT use BFS.
+ * DFS can guarantee that all the sub-modules can be registered properly
+ * to its parent in module manager  
+ *******************************************************************/
+static 
+void rec_print_verilog_logical_tile(std::fstream& fp,
+                                    const ModuleManager& module_manager,
+                                    const VprDeviceAnnotation& device_annotation,
+                                    t_pb_graph_node* physical_pb_graph_node,
+                                    const bool& use_explicit_mapping,
+                                    const bool& verbose) {
+  /* Check the file handler*/ 
+  VTR_ASSERT(true == valid_file_stream(fp));
+
+  /* Check cur_pb_graph_node*/
+  if (nullptr == physical_pb_graph_node) {
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid physical_pb_graph_node\n"); 
+    exit(1);
+  }
+
+  /* Get the pb_type definition related to the node */
+  t_pb_type* physical_pb_type = physical_pb_graph_node->pb_type; 
+
+  /* Find the mode that physical implementation of a pb_type */
+  t_mode* physical_mode = device_annotation.physical_mode(physical_pb_type);
+
+  /* For non-leaf node in the pb_type graph: 
+   * Recursively Depth-First Generate all the child pb_type at the level 
+   */
+  if (false == is_primitive_pb_type(physical_pb_type)) { 
+    for (int ipb = 0; ipb < physical_mode->num_pb_type_children; ++ipb) {
+      /* Go recursive to visit the children */
+      rec_print_verilog_logical_tile(fp,
+                                     module_manager, device_annotation, 
+                                     &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb][0]),
+                                     use_explicit_mapping,
+                                     verbose);
+    }
+  }
+
+  /* For leaf node, a primitive Verilog module will be generated.
+   * Note that the primitive may be mapped to a standard cell, we force to use 
+   * explict port mapping. This aims to avoid any port sequence issues!!!
+   */
+  if (true == is_primitive_pb_type(physical_pb_type)) { 
+    print_verilog_primitive_block(fp, module_manager,
+                                  physical_pb_graph_node, 
+                                  true, 
+                                  verbose);
+    /* Finish for primitive node, return */
+    return;
+  }
+
+  /* Generate the name of the Verilog module for this pb_type */
+  std::string pb_module_name = generate_physical_block_module_name(physical_pb_type);
+
+  /* Register the Verilog module in module manager */
+  ModuleId pb_module = module_manager.find_module(pb_module_name);
+  VTR_ASSERT(true == module_manager.valid_module_id(pb_module));
+
+  VTR_LOGV(verbose,
+          "Writing Verilog codes of logical tile block '%s'...",
+           module_manager.module_name(pb_module).c_str());
+
+  /* Comment lines */
+  print_verilog_comment(fp, std::string("----- BEGIN Physical programmable logic block Verilog module: " + std::string(physical_pb_type->name) + " -----"));
+
+  /* Write the verilog module */
+  write_verilog_module_to_file(fp, module_manager, pb_module, use_explicit_mapping);
+
+  print_verilog_comment(fp, std::string("----- END Physical programmable logic block Verilog module: " + std::string(physical_pb_type->name) + " -----"));
+
+  /* Add an empty line as a splitter */
+  fp << std::endl;
+
+  VTR_LOGV(verbose, "Done\n");
+}
+
+/*****************************************************************************
+ * This function will create a Verilog file and print out a Verilog netlist 
+ * for the logical tile (pb_graph/pb_type) 
+ *****************************************************************************/
+static 
+void print_verilog_logical_tile_netlist(const ModuleManager& module_manager,
+                                        std::vector<std::string>& netlist_names,
+                                        const VprDeviceAnnotation& device_annotation,
+                                        const std::string& verilog_dir,
+                                        const std::string& subckt_dir,
+                                        t_pb_graph_node* pb_graph_head,
+                                        const bool& use_explicit_mapping,
+                                        const bool& verbose) {
+  /* Give a name to the Verilog netlist */
+  /* Create the file name for Verilog */
+  std::string verilog_fname(subckt_dir 
+                          + generate_logical_tile_netlist_name(std::string(LOGICAL_MODULE_VERILOG_FILE_NAME_PREFIX), pb_graph_head, std::string(VERILOG_NETLIST_FILE_POSTFIX))
+                           );
+
+  VTR_LOG("Writing Verilog netlist '%s' for logic tile '%s' ...",
+          verilog_fname.c_str(), pb_graph_head->pb_type->name);
+  VTR_LOGV(verbose, "\n");
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
+
+  check_file_stream(verilog_fname.c_str(), fp);
+
+  print_verilog_file_header(fp, std::string("Verilog modules for logical tile: " + std::string(pb_graph_head->pb_type->name) + "]")); 
+
+  /* Print preprocessing flags */
+  print_verilog_include_defines_preproc_file(fp, verilog_dir);
+
+  /* Print Verilog modules for all the pb_types/pb_graph_nodes
+   * use a Depth-First Search Algorithm to print the sub-modules 
+   * Note: DFS is the right way. Do NOT use BFS.
+   * DFS can guarantee that all the sub-modules can be registered properly
+   * to its parent in module manager  
+   */
+  /* Print Verilog modules starting from the top-level pb_type/pb_graph_node, and traverse the graph in a recursive way */
+  rec_print_verilog_logical_tile(fp, module_manager,
+                                 device_annotation, 
+                                 pb_graph_head,
+                                 use_explicit_mapping,
+                                 verbose);
+
+  /* Add an empty line as a splitter */
+  fp << std::endl;
+
+  /* Close file handler */
+  fp.close();
+
+  /* Add fname to the netlist name list */
+  netlist_names.push_back(verilog_fname);
+
+  VTR_LOG("Done\n");
+  VTR_LOG("\n");
+}
+
+/*****************************************************************************
+ * This function will create a Verilog file and print out a Verilog netlist 
+ * for a type of physical block 
+ *
+ * For IO blocks: 
+ * The param 'border_side' is required, which is specify which side of fabric
+ * the I/O block locates at.
+ *****************************************************************************/
+static 
+void print_verilog_physical_tile_netlist(const ModuleManager& module_manager,
+                                         std::vector<std::string>& netlist_names,
+                                         const std::string& verilog_dir,
+                                         const std::string& subckt_dir,
+                                         t_physical_tile_type_ptr phy_block_type,
+                                         const e_side& border_side,
+                                         const bool& use_explicit_mapping) {
+  /* Check code: if this is an IO block, the border side MUST be valid */
+  if (true == is_io_type(phy_block_type)) {
+    VTR_ASSERT(NUM_SIDES != border_side);
+  }
+  
+  /* Give a name to the Verilog netlist */
+  /* Create the file name for Verilog */
+  std::string verilog_fname(subckt_dir 
+                          + generate_grid_block_netlist_name(std::string(phy_block_type->name), 
+                                                             is_io_type(phy_block_type), 
+                                                             border_side, 
+                                                             std::string(VERILOG_NETLIST_FILE_POSTFIX))
+                           );
+
+  /* Echo status */
+  if (true == is_io_type(phy_block_type)) {
+    SideManager side_manager(border_side);
+    VTR_LOG("Writing Verilog Netlist '%s' for physical tile '%s' at %s side ...",
+            verilog_fname.c_str(), phy_block_type->name, 
+            side_manager.c_str());
+  } else { 
+    VTR_LOG("Writing Verilog Netlist '%s' for physical_tile '%s'...",
+            verilog_fname.c_str(), phy_block_type->name);
+  }
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
+
+  check_file_stream(verilog_fname.c_str(), fp);
+
+  print_verilog_file_header(fp, std::string("Verilog modules for physical tile: " + std::string(phy_block_type->name) + "]")); 
+
+  /* Print preprocessing flags */
+  print_verilog_include_defines_preproc_file(fp, verilog_dir);
+
+  /* Create a Verilog Module for the top-level physical block, and add to module manager */
+  std::string grid_module_name = generate_grid_block_module_name(std::string(GRID_VERILOG_FILE_NAME_PREFIX), std::string(phy_block_type->name), is_io_type(phy_block_type), border_side);
+  ModuleId grid_module = module_manager.find_module(grid_module_name); 
+  VTR_ASSERT(true == module_manager.valid_module_id(grid_module));
+
+  /* Write the verilog module */
+  print_verilog_comment(fp, std::string("----- BEGIN Grid Verilog module: " + module_manager.module_name(grid_module) + " -----"));
+  write_verilog_module_to_file(fp, module_manager, grid_module, use_explicit_mapping);
+
+  print_verilog_comment(fp, std::string("----- END Grid Verilog module: " + module_manager.module_name(grid_module) + " -----"));
+
+  /* Add an empty line as a splitter */
+  fp << std::endl;
+
+  /* Close file handler */
+  fp.close();
+
+  /* Add fname to the netlist name list */
+  netlist_names.push_back(verilog_fname);
+
+  VTR_LOG("Done\n");
+}
+
+/*****************************************************************************
+ * Create logic block modules in a compact way:
+ * 1. Only one module for each I/O on each border side (IO_TYPE)
+ * 2. Only one module for each CLB (FILL_TYPE)
+ * 3. Only one module for each heterogeneous block
+ ****************************************************************************/
+void print_verilog_grids(const ModuleManager& module_manager,
+                         const DeviceContext& device_ctx,
+                         const VprDeviceAnnotation& device_annotation,
+                         const std::string& verilog_dir,
+                         const std::string& subckt_dir,
+                         const bool& use_explicit_mapping,
+                         const bool& verbose) {
+  /* Create a vector to contain all the Verilog netlist names that have been generated in this function */
+  std::vector<std::string> netlist_names;
+
+  /* Enumerate the types of logical tiles, and build a module for each 
+   * Write modules for all the pb_types/pb_graph_nodes
+   * use a Depth-First Search Algorithm to print the sub-modules 
+   * Note: DFS is the right way. Do NOT use BFS.
+   * DFS can guarantee that all the sub-modules can be registered properly
+   * to its parent in module manager  
+   */
+  VTR_LOG("Writing logical tiles...");
+  VTR_LOGV(verbose, "\n");
+  for (const t_logical_block_type& logical_tile : device_ctx.logical_block_types) {
+    /* Bypass empty pb_graph */
+    if (nullptr == logical_tile.pb_graph_head) {
+      continue;
+    }
+    print_verilog_logical_tile_netlist(module_manager, netlist_names,
+                                       device_annotation,
+                                       verilog_dir, subckt_dir,
+                                       logical_tile.pb_graph_head,
+                                       use_explicit_mapping,
+                                       verbose);
+  }
+  VTR_LOG("Writing logical tiles...");
+  VTR_LOG("Done\n");
+
+  VTR_LOG("\n");
+
+  /* Enumerate the types of physical tiles
+   * Use the logical tile module to build the physical tiles
+   */
+  VTR_LOG("Building physical tiles...");
+  VTR_LOGV(verbose, "\n");
+  for (const t_physical_tile_type& physical_tile : device_ctx.physical_tile_types) {
+    /* Bypass empty type or nullptr */
+    if (true == is_empty_type(&physical_tile)) {
+      continue;
+    } else if (true == is_io_type(&physical_tile)) {
+      /* Special for I/O block, generate one module for each border side */
+      for (int iside = 0; iside < NUM_SIDES; iside++) {
+        SideManager side_manager(iside);
+        print_verilog_physical_tile_netlist(module_manager, netlist_names,
+                                            verilog_dir, subckt_dir, 
+                                            &physical_tile,
+                                            side_manager.get_side(),
+                                            use_explicit_mapping);
+      } 
+      continue;
+    } else {
+      /* For CLB and heterogenenous blocks */
+      print_verilog_physical_tile_netlist(module_manager, netlist_names,
+                                          verilog_dir, subckt_dir, 
+                                          &physical_tile,
+                                          NUM_SIDES,
+                                          use_explicit_mapping);
+    }
+  }
+  VTR_LOG("Building physical tiles...");
+  VTR_LOG("Done\n");
+  VTR_LOG("\n");
+
+  /* Output a header file for all the logic blocks */
+  std::string grid_verilog_fname(LOGIC_BLOCK_VERILOG_FILE_NAME);
+  VTR_LOG("Writing header file for grid Verilog modules '%s' ...",
+          grid_verilog_fname.c_str());
+  print_verilog_netlist_include_header_file(netlist_names,
+                                            subckt_dir.c_str(),
+                                            grid_verilog_fname.c_str());
+  VTR_LOG("Done\n");
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_verilog/verilog_grid.h b/openfpga/src/fpga_verilog/verilog_grid.h
new file mode 100644
index 000000000..da8ea09fa
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_grid.h
@@ -0,0 +1,30 @@
+#ifndef VERILOG_GRID_H
+#define VERILOG_GRID_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <string>
+#include "vpr_context.h"
+#include "module_manager.h"
+#include "vpr_device_annotation.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void print_verilog_grids(const ModuleManager& module_manager,
+                         const DeviceContext& device_ctx,
+                         const VprDeviceAnnotation& device_annotation,
+                         const std::string& verilog_dir,
+                         const std::string& subckt_dir,
+                         const bool& use_explicit_mapping,
+                         const bool& verbose);
+
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/fpga_verilog/verilog_routing.cpp b/openfpga/src/fpga_verilog/verilog_routing.cpp
index 0d9582556..a3361fd06 100644
--- a/openfpga/src/fpga_verilog/verilog_routing.cpp
+++ b/openfpga/src/fpga_verilog/verilog_routing.cpp
@@ -291,6 +291,7 @@ void print_verilog_flatten_routing_modules(const ModuleManager& module_manager,
                                             subckt_dir.c_str(),
                                             ROUTING_VERILOG_FILE_NAME);
   VTR_LOG("Done\n");
+  VTR_LOG("\n");
 }
 
 
@@ -350,6 +351,7 @@ void print_verilog_unique_routing_modules(const ModuleManager& module_manager,
                                             subckt_dir.c_str(),
                                             ROUTING_VERILOG_FILE_NAME);
   VTR_LOG("Done\n");
+  VTR_LOG("\n");
 }
 
 } /* end namespace openfpga */

From 11775c370b986f695d18da12cde3ae9e6f9e4b96 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 16 Feb 2020 16:18:14 -0700
Subject: [PATCH 161/645] bring FPGA top module verilog writer online. Fabric
 Verilog generator done

---
 openfpga/src/fpga_verilog/verilog_api.cpp     | 11 ++-
 .../src/fpga_verilog/verilog_top_module.cpp   | 75 +++++++++++++++++++
 .../src/fpga_verilog/verilog_top_module.h     | 23 ++++++
 .../src/fpga_verilog/verilog_writer_utils.cpp |  5 --
 4 files changed, 103 insertions(+), 11 deletions(-)
 create mode 100644 openfpga/src/fpga_verilog/verilog_top_module.cpp
 create mode 100644 openfpga/src/fpga_verilog/verilog_top_module.h

diff --git a/openfpga/src/fpga_verilog/verilog_api.cpp b/openfpga/src/fpga_verilog/verilog_api.cpp
index ce339e813..645033d65 100644
--- a/openfpga/src/fpga_verilog/verilog_api.cpp
+++ b/openfpga/src/fpga_verilog/verilog_api.cpp
@@ -18,7 +18,7 @@
 #include "verilog_submodule.h"
 #include "verilog_routing.h"
 #include "verilog_grid.h"
-//#include "verilog_top_module.h"
+#include "verilog_top_module.h"
 
 /* Header file for this source file */
 #include "verilog_api.h"
@@ -111,14 +111,13 @@ void fpga_fabric_verilog(ModuleManager& module_manager,
                       options.verbose_output());
 
   /* Generate FPGA fabric */
-  //print_verilog_top_module(module_manager, 
-  //                         std::string(vpr_setup.FileNameOpts.ArchFile), 
-  //                         src_dir_path,
-  //                         dump_explicit_verilog);
+  print_verilog_top_module(const_cast<const ModuleManager&>(module_manager), 
+                           src_dir_path,
+                           options.explicit_port_mapping());
 
   /* Given a brief stats on how many Verilog modules have been written to files */
   VTR_LOGV(options.verbose_output(), 
-           "Outputted %lu Verilog modules in total\n", 
+           "Written %lu Verilog modules in total\n", 
            module_manager.num_modules());  
 }
 
diff --git a/openfpga/src/fpga_verilog/verilog_top_module.cpp b/openfpga/src/fpga_verilog/verilog_top_module.cpp
new file mode 100644
index 000000000..9bcfadc68
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_top_module.cpp
@@ -0,0 +1,75 @@
+/********************************************************************
+ * This file includes functions that are used to print the top-level
+ * module for the FPGA fabric in Verilog format
+ *******************************************************************/
+#include <fstream>
+#include <map>
+#include <algorithm>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_digest.h"
+
+#include "openfpga_naming.h"
+
+#include "verilog_constants.h"
+#include "verilog_writer_utils.h"
+#include "verilog_module_writer.h"
+#include "verilog_top_module.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Print the top-level module for the FPGA fabric in Verilog format
+ * This function will 
+ * 1. name the top-level module
+ * 2. include dependent netlists 
+ *    - User defined netlists
+ *    - Auto-generated netlists
+ * 3. Add the submodules to the top-level graph
+ * 4. Add module nets to connect datapath ports
+ * 5. Add module nets/submodules to connect configuration ports
+ *******************************************************************/
+void print_verilog_top_module(const ModuleManager& module_manager,
+                              const std::string& verilog_dir,
+                              const bool& use_explicit_mapping) {
+  /* Create a module as the top-level fabric, and add it to the module manager */
+  std::string top_module_name = generate_fpga_top_module_name();
+  ModuleId top_module = module_manager.find_module(top_module_name);
+  VTR_ASSERT(true == module_manager.valid_module_id(top_module));
+
+  /* Start printing out Verilog netlists */
+  /* Create the file name for Verilog netlist */
+  std::string verilog_fname(verilog_dir + generate_fpga_top_netlist_name(std::string(VERILOG_NETLIST_FILE_POSTFIX)));
+
+  VTR_LOG("Writing Verilog netlist for top-level module of FPGA fabric '%s'...",
+          verilog_fname.c_str());
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
+
+  check_file_stream(verilog_fname.c_str(), fp);
+
+  print_verilog_file_header(fp, std::string("Top-level Verilog module for FPGA")); 
+
+  /* Print preprocessing flags */
+  print_verilog_include_defines_preproc_file(fp, verilog_dir);
+
+  /* Write the module content in Verilog format */
+  write_verilog_module_to_file(fp, module_manager, top_module, use_explicit_mapping);
+
+  /* Add an empty line as a splitter */
+  fp << std::endl;
+
+  /* Close file handler */
+  fp.close();
+
+  VTR_LOG("Done\n");
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_verilog/verilog_top_module.h b/openfpga/src/fpga_verilog/verilog_top_module.h
new file mode 100644
index 000000000..2fb451e16
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_top_module.h
@@ -0,0 +1,23 @@
+#ifndef VERILOG_TOP_MODULE_H
+#define VERILOG_TOP_MODULE_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <string>
+#include "module_manager.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void print_verilog_top_module(const ModuleManager& module_manager,
+                              const std::string& verilog_dir,
+                              const bool& use_explicit_mapping);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp
index 600357c36..95f34ab1f 100644
--- a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp
+++ b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp
@@ -1377,9 +1377,6 @@ void print_verilog_netlist_include_header_file(const std::vector<std::string>& n
 
   std::string verilog_fname(std::string(subckt_dir) + std::string(header_file_name));
 
-  VTR_LOG("Writing header file for primitive modules '%s' ...",
-          verilog_fname.c_str());
-
   /* Create the file stream */
   std::fstream fp;
   fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
@@ -1396,8 +1393,6 @@ void print_verilog_netlist_include_header_file(const std::vector<std::string>& n
 
   /* close file stream */
   fp.close();
-
-  VTR_LOG("Done\n");
 }
 
 } /* end namespace openfpga */

From 60f40a965783f2846fd1bb168c8a46522688f788 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 16 Feb 2020 16:35:26 -0700
Subject: [PATCH 162/645] use constant module manager as much as possible in
 Verilog writer

---
 .../src/fpga_verilog/verilog_decoders.cpp     |  4 ++--
 openfpga/src/fpga_verilog/verilog_decoders.h  |  2 +-
 .../fpga_verilog/verilog_essential_gates.cpp  |  8 ++++----
 .../fpga_verilog/verilog_essential_gates.h    |  2 +-
 openfpga/src/fpga_verilog/verilog_lut.cpp     |  2 +-
 openfpga/src/fpga_verilog/verilog_lut.h       |  2 +-
 openfpga/src/fpga_verilog/verilog_memory.cpp  |  4 ++--
 openfpga/src/fpga_verilog/verilog_memory.h    |  2 +-
 .../src/fpga_verilog/verilog_submodule.cpp    | 19 ++++++++++++-------
 openfpga/src/fpga_verilog/verilog_wire.cpp    |  4 ++--
 openfpga/src/fpga_verilog/verilog_wire.h      |  2 +-
 11 files changed, 28 insertions(+), 23 deletions(-)

diff --git a/openfpga/src/fpga_verilog/verilog_decoders.cpp b/openfpga/src/fpga_verilog/verilog_decoders.cpp
index 7689d3ed6..e9b9f6d02 100644
--- a/openfpga/src/fpga_verilog/verilog_decoders.cpp
+++ b/openfpga/src/fpga_verilog/verilog_decoders.cpp
@@ -44,7 +44,7 @@ namespace openfpga {
  ***************************************************************************************/
 static 
 void print_verilog_mux_local_decoder_module(std::fstream& fp, 
-                                            ModuleManager& module_manager,
+                                            const ModuleManager& module_manager,
                                             const DecoderLibrary& decoder_lib,
                                             const DecoderId& decoder) {
   /* Get the number of inputs */
@@ -161,7 +161,7 @@ void print_verilog_mux_local_decoder_module(std::fstream& fp,
  *    before running the back-end flow for FPGA fabric 
  *    See more details in the function print_verilog_mux_local_decoder() for more details
  ***************************************************************************************/
-void print_verilog_submodule_mux_local_decoders(ModuleManager& module_manager,
+void print_verilog_submodule_mux_local_decoders(const ModuleManager& module_manager,
                                                 std::vector<std::string>& netlist_names,
                                                 const MuxLibrary& mux_lib,
                                                 const CircuitLibrary& circuit_lib,
diff --git a/openfpga/src/fpga_verilog/verilog_decoders.h b/openfpga/src/fpga_verilog/verilog_decoders.h
index 41f932932..271e7aa5c 100644
--- a/openfpga/src/fpga_verilog/verilog_decoders.h
+++ b/openfpga/src/fpga_verilog/verilog_decoders.h
@@ -20,7 +20,7 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-void print_verilog_submodule_mux_local_decoders(ModuleManager& module_manager,
+void print_verilog_submodule_mux_local_decoders(const ModuleManager& module_manager,
                                                 std::vector<std::string>& netlist_names,
                                                 const MuxLibrary& mux_lib,
                                                 const CircuitLibrary& circuit_lib,
diff --git a/openfpga/src/fpga_verilog/verilog_essential_gates.cpp b/openfpga/src/fpga_verilog/verilog_essential_gates.cpp
index c18bece61..a84d02bdf 100644
--- a/openfpga/src/fpga_verilog/verilog_essential_gates.cpp
+++ b/openfpga/src/fpga_verilog/verilog_essential_gates.cpp
@@ -142,7 +142,7 @@ void print_verilog_invbuf_body(std::fstream& fp,
  * or tapered buffer to a file 
  ***********************************************/
 static 
-void print_verilog_invbuf_module(ModuleManager& module_manager, 
+void print_verilog_invbuf_module(const ModuleManager& module_manager, 
                                  std::fstream& fp,
                                  const CircuitLibrary& circuit_lib,
                                  const CircuitModelId& circuit_model) {
@@ -226,7 +226,7 @@ void print_verilog_invbuf_module(ModuleManager& module_manager,
  * either transmission-gate or pass-transistor
  ***********************************************/
 static 
-void print_verilog_passgate_module(ModuleManager& module_manager, 
+void print_verilog_passgate_module(const ModuleManager& module_manager, 
                                    std::fstream& fp,
                                    const CircuitLibrary& circuit_lib,
                                    const CircuitModelId& circuit_model) {
@@ -438,7 +438,7 @@ void print_verilog_mux2_gate_body(std::fstream& fp,
  * 3. 2-input MUX
  ***********************************************/
 static 
-void print_verilog_gate_module(ModuleManager& module_manager, 
+void print_verilog_gate_module(const ModuleManager& module_manager, 
                                std::fstream& fp,
                                const CircuitLibrary& circuit_lib,
                                const CircuitModelId& circuit_model) {
@@ -525,7 +525,7 @@ void print_verilog_constant_generator_module(const ModuleManager& module_manager
  * include inverters, buffers, transmission-gates,
  * etc.
  ***********************************************/
-void print_verilog_submodule_essentials(ModuleManager& module_manager, 
+void print_verilog_submodule_essentials(const ModuleManager& module_manager, 
                                         std::vector<std::string>& netlist_names,
                                         const std::string& verilog_dir, 
                                         const std::string& submodule_dir,
diff --git a/openfpga/src/fpga_verilog/verilog_essential_gates.h b/openfpga/src/fpga_verilog/verilog_essential_gates.h
index 33ce49c6c..b7f9b519a 100644
--- a/openfpga/src/fpga_verilog/verilog_essential_gates.h
+++ b/openfpga/src/fpga_verilog/verilog_essential_gates.h
@@ -14,7 +14,7 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-void print_verilog_submodule_essentials(ModuleManager& module_manager, 
+void print_verilog_submodule_essentials(const ModuleManager& module_manager, 
                                         std::vector<std::string>& netlist_names,
                                         const std::string& verilog_dir, 
                                         const std::string& submodule_dir,
diff --git a/openfpga/src/fpga_verilog/verilog_lut.cpp b/openfpga/src/fpga_verilog/verilog_lut.cpp
index 900ef3073..a849c5827 100644
--- a/openfpga/src/fpga_verilog/verilog_lut.cpp
+++ b/openfpga/src/fpga_verilog/verilog_lut.cpp
@@ -29,7 +29,7 @@ namespace openfpga {
  * Print Verilog modules for the Look-Up Tables (LUTs) 
  * in the circuit library
  ********************************************************************/
-void print_verilog_submodule_luts(ModuleManager& module_manager,
+void print_verilog_submodule_luts(const ModuleManager& module_manager,
                                   std::vector<std::string>& netlist_names,
                                   const CircuitLibrary& circuit_lib,
                                   const std::string& verilog_dir,
diff --git a/openfpga/src/fpga_verilog/verilog_lut.h b/openfpga/src/fpga_verilog/verilog_lut.h
index f5d1345dc..7c8b85b79 100644
--- a/openfpga/src/fpga_verilog/verilog_lut.h
+++ b/openfpga/src/fpga_verilog/verilog_lut.h
@@ -17,7 +17,7 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-void print_verilog_submodule_luts(ModuleManager& module_manager,
+void print_verilog_submodule_luts(const ModuleManager& module_manager,
                                   std::vector<std::string>& netlist_names,
                                   const CircuitLibrary& circuit_lib,
                                   const std::string& verilog_dir,
diff --git a/openfpga/src/fpga_verilog/verilog_memory.cpp b/openfpga/src/fpga_verilog/verilog_memory.cpp
index 743647d44..de0418481 100644
--- a/openfpga/src/fpga_verilog/verilog_memory.cpp
+++ b/openfpga/src/fpga_verilog/verilog_memory.cpp
@@ -42,7 +42,7 @@ namespace openfpga {
  *          +---------------------+
  ********************************************************************/
 static 
-void print_verilog_mux_memory_module(ModuleManager& module_manager,
+void print_verilog_mux_memory_module(const ModuleManager& module_manager,
                                      const CircuitLibrary& circuit_lib,
                                      std::fstream& fp,
                                      const CircuitModelId& mux_model,
@@ -96,7 +96,7 @@ void print_verilog_mux_memory_module(ModuleManager& module_manager,
  * Take another example, the memory circuit can implement the scan-chain or 
  * memory-bank organization for the memories.
  ********************************************************************/
-void print_verilog_submodule_memories(ModuleManager& module_manager,
+void print_verilog_submodule_memories(const ModuleManager& module_manager,
                                       std::vector<std::string>& netlist_names,
                                       const MuxLibrary& mux_lib,
                                       const CircuitLibrary& circuit_lib,
diff --git a/openfpga/src/fpga_verilog/verilog_memory.h b/openfpga/src/fpga_verilog/verilog_memory.h
index 774e6feb9..9d29eb15f 100644
--- a/openfpga/src/fpga_verilog/verilog_memory.h
+++ b/openfpga/src/fpga_verilog/verilog_memory.h
@@ -18,7 +18,7 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-void print_verilog_submodule_memories(ModuleManager& module_manager,
+void print_verilog_submodule_memories(const ModuleManager& module_manager,
                                       std::vector<std::string>& netlist_names,
                                       const MuxLibrary& mux_lib,
                                       const CircuitLibrary& circuit_lib,
diff --git a/openfpga/src/fpga_verilog/verilog_submodule.cpp b/openfpga/src/fpga_verilog/verilog_submodule.cpp
index c52fc2262..099118e5f 100644
--- a/openfpga/src/fpga_verilog/verilog_submodule.cpp
+++ b/openfpga/src/fpga_verilog/verilog_submodule.cpp
@@ -42,13 +42,13 @@ void print_verilog_submodule(ModuleManager& module_manager,
    * This should be done prior to other steps in this function, 
    * because they will be instanciated by other primitive modules 
    */
-  add_user_defined_verilog_modules(module_manager, circuit_lib);
+  //add_user_defined_verilog_modules(module_manager, circuit_lib);
 
   /* Create a vector to contain all the Verilog netlist names that have been generated in this function */
   std::vector<std::string> netlist_names;
 
 
-  print_verilog_submodule_essentials(module_manager, 
+  print_verilog_submodule_essentials(const_cast<const ModuleManager&>(module_manager), 
                                      netlist_names,
                                      verilog_dir, 
                                      submodule_dir,
@@ -58,7 +58,8 @@ void print_verilog_submodule(ModuleManager& module_manager,
   /* NOTE: local decoders generation must go before the MUX generation!!! 
    *       because local decoders modules will be instanciated in the MUX modules 
    */
-  print_verilog_submodule_mux_local_decoders(module_manager, netlist_names, 
+  print_verilog_submodule_mux_local_decoders(const_cast<const ModuleManager&>(module_manager),
+                                             netlist_names, 
                                              mux_lib, circuit_lib, 
                                              verilog_dir, submodule_dir);
   print_verilog_submodule_muxes(module_manager, netlist_names, mux_lib, circuit_lib,
@@ -67,23 +68,27 @@ void print_verilog_submodule(ModuleManager& module_manager,
 
  
   /* LUTes */
-  print_verilog_submodule_luts(module_manager, netlist_names, circuit_lib,
+  print_verilog_submodule_luts(const_cast<const ModuleManager&>(module_manager),
+                               netlist_names, circuit_lib,
                                verilog_dir, submodule_dir,
                                fpga_verilog_opts.explicit_port_mapping());
 
   /* Hard wires */
-  print_verilog_submodule_wires(module_manager, netlist_names, circuit_lib,
+  print_verilog_submodule_wires(const_cast<const ModuleManager&>(module_manager),
+                                netlist_names, circuit_lib,
                                 verilog_dir, submodule_dir);
 
   /* 4. Memories */
-  print_verilog_submodule_memories(module_manager, netlist_names,
+  print_verilog_submodule_memories(const_cast<const ModuleManager&>(module_manager),
+                                   netlist_names,
                                    mux_lib, circuit_lib, 
                                    verilog_dir, submodule_dir,
                                    fpga_verilog_opts.explicit_port_mapping());
 
   /* 5. Dump template for all the modules */
   if (true == fpga_verilog_opts.print_user_defined_template()) { 
-    print_verilog_submodule_templates(module_manager, circuit_lib,
+    print_verilog_submodule_templates(const_cast<const ModuleManager&>(module_manager),
+                                      circuit_lib,
                                       verilog_dir, submodule_dir);
   }
 
diff --git a/openfpga/src/fpga_verilog/verilog_wire.cpp b/openfpga/src/fpga_verilog/verilog_wire.cpp
index 2ac9e7ffa..4f084fad9 100644
--- a/openfpga/src/fpga_verilog/verilog_wire.cpp
+++ b/openfpga/src/fpga_verilog/verilog_wire.cpp
@@ -35,7 +35,7 @@ namespace openfpga {
  *
  *******************************************************************/
 static 
-void print_verilog_wire_module(ModuleManager& module_manager, 
+void print_verilog_wire_module(const ModuleManager& module_manager, 
                                const CircuitLibrary& circuit_lib,
                                std::fstream& fp,
                                const CircuitModelId& wire_model) {
@@ -92,7 +92,7 @@ void print_verilog_wire_module(ModuleManager& module_manager,
 /********************************************************************
  * Top-level function to print wire modules
  *******************************************************************/
-void print_verilog_submodule_wires(ModuleManager& module_manager,
+void print_verilog_submodule_wires(const ModuleManager& module_manager,
                                    std::vector<std::string>& netlist_names,
                                    const CircuitLibrary& circuit_lib,
                                    const std::string& verilog_dir,
diff --git a/openfpga/src/fpga_verilog/verilog_wire.h b/openfpga/src/fpga_verilog/verilog_wire.h
index 7d22ae4c8..55c39fb30 100644
--- a/openfpga/src/fpga_verilog/verilog_wire.h
+++ b/openfpga/src/fpga_verilog/verilog_wire.h
@@ -17,7 +17,7 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-void print_verilog_submodule_wires(ModuleManager& module_manager,
+void print_verilog_submodule_wires(const ModuleManager& module_manager,
                                    std::vector<std::string>& netlist_names,
                                    const CircuitLibrary& circuit_lib,
                                    const std::string& verilog_dir,

From 92076c1460bd96442f5013f3ae7f665e4921df2b Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 17 Feb 2020 16:59:24 -0700
Subject: [PATCH 163/645] refactored lb_rr_graph in the same principle of
 RRGraph object

---
 openfpga/src/repack/lb_rr_graph.cpp   | 215 +++++++++++++++++++
 openfpga/src/repack/lb_rr_graph.h     | 296 ++++++++++++++++++++++++++
 openfpga/src/repack/lb_rr_graph_fwd.h |  19 ++
 vpr/src/pack/pack_types.h             |  12 +-
 4 files changed, 532 insertions(+), 10 deletions(-)
 create mode 100644 openfpga/src/repack/lb_rr_graph.cpp
 create mode 100644 openfpga/src/repack/lb_rr_graph.h
 create mode 100644 openfpga/src/repack/lb_rr_graph_fwd.h

diff --git a/openfpga/src/repack/lb_rr_graph.cpp b/openfpga/src/repack/lb_rr_graph.cpp
new file mode 100644
index 000000000..99b0ecd1b
--- /dev/null
+++ b/openfpga/src/repack/lb_rr_graph.cpp
@@ -0,0 +1,215 @@
+/************************************************************************
+ * Member Functions of LbRRGraph
+ * include mutators, accessors and utility functions 
+ ***********************************************************************/
+#include "vtr_assert.h"
+#include "vtr_log.h"
+#include "lb_rr_graph.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/**************************************************
+ * Public Accessors: Aggregates 
+ *************************************************/
+LbRRGraph::node_range LbRRGraph::nodes() const {
+  return vtr::make_range(node_ids_.begin(), node_ids_.end());
+}
+
+LbRRGraph::edge_range LbRRGraph::edges() const {
+  return vtr::make_range(edge_ids_.begin(), edge_ids_.end());
+}
+
+/**************************************************
+ * Public Accessors node-level attributes 
+ *************************************************/
+e_lb_rr_type LbRRGraph::node_type(const LbRRNodeId& node) const {
+  VTR_ASSERT(true == valid_node_id(node));
+  return node_types_[node];
+}
+
+short LbRRGraph::node_capacity(const LbRRNodeId& node) const {
+  VTR_ASSERT(true == valid_node_id(node));
+  return node_capacities_[node];
+}
+
+t_pb_graph_pin* LbRRGraph::node_pb_graph_pin(const LbRRNodeId& node) const {
+  VTR_ASSERT(true == valid_node_id(node));
+  return node_pb_graph_pins_[node];
+}
+
+float LbRRGraph::node_intrinsic_cost(const LbRRNodeId& node) const {
+  VTR_ASSERT(true == valid_node_id(node));
+  return node_intrinsic_costs_[node];
+}
+
+std::vector<LbRREdgeId> LbRRGraph::node_in_edges(const LbRRNodeId& node, t_mode* mode) const {
+  std::vector<LbRREdgeId> in_edges;
+
+  VTR_ASSERT(true == valid_node_id(node));
+  for (const LbRREdgeId& edge : node_in_edges_[node]) {
+    if (mode == edge_mode(edge)) {
+      in_edges.push_back(edge);
+    }
+  }
+
+  return in_edges;
+}
+
+std::vector<LbRREdgeId> LbRRGraph::node_out_edges(const LbRRNodeId& node, t_mode* mode) const {
+  std::vector<LbRREdgeId> out_edges;
+
+  VTR_ASSERT(true == valid_node_id(node));
+  for (const LbRREdgeId& edge : node_out_edges_[node]) {
+    if (mode == edge_mode(edge)) {
+      out_edges.push_back(edge);
+    }
+  }
+
+  return out_edges;
+}
+
+LbRRNodeId LbRRGraph::find_node(const e_lb_rr_type& type, t_pb_graph_pin* pb_graph_pin) const {
+  if (size_t(type) >= node_lookup_.size()) {
+    return LbRRNodeId::INVALID();
+  }
+
+  if (0 == node_lookup_[size_t(type)].count(pb_graph_pin)) {
+    return LbRRNodeId::INVALID();
+  }
+  
+  return node_lookup_[size_t(type)].at(pb_graph_pin);
+}
+
+LbRRNodeId LbRRGraph::edge_src_node(const LbRREdgeId& edge) const {
+  VTR_ASSERT(true == valid_edge_id(edge));
+  return edge_src_nodes_[edge];
+}
+
+LbRRNodeId LbRRGraph::edge_sink_node(const LbRREdgeId& edge) const {
+  VTR_ASSERT(true == valid_edge_id(edge));
+  return edge_sink_nodes_[edge];
+}
+
+float LbRRGraph::edge_intrinsic_cost(const LbRREdgeId& edge) const {
+  VTR_ASSERT(true == valid_edge_id(edge));
+  return edge_intrinsic_costs_[edge];
+}
+
+t_mode* LbRRGraph::edge_mode(const LbRREdgeId& edge) const {
+  VTR_ASSERT(true == valid_edge_id(edge));
+  return edge_modes_[edge];
+}
+
+/******************************************************************************
+ * Public Mutators
+ ******************************************************************************/
+void LbRRGraph::reserve_nodes(const unsigned long& num_nodes) {
+  node_ids_.reserve(num_nodes);
+  node_types_.reserve(num_nodes);
+  node_capacities_.reserve(num_nodes);
+  node_pb_graph_pins_.reserve(num_nodes);
+  node_intrinsic_costs_.reserve(num_nodes);
+
+  node_in_edges_.reserve(num_nodes);
+  node_out_edges_.reserve(num_nodes);
+}
+
+void LbRRGraph::reserve_edges(const unsigned long& num_edges) {
+  edge_ids_.reserve(num_edges);
+  edge_intrinsic_costs_.reserve(num_edges);
+  edge_modes_.reserve(num_edges);
+
+  edge_src_nodes_.reserve(num_edges);
+  edge_sink_nodes_.reserve(num_edges);
+}
+
+LbRRNodeId LbRRGraph::create_node(const e_lb_rr_type& type) {
+  /* Create an new id */
+  LbRRNodeId node = LbRRNodeId(node_ids_.size());
+  node_ids_.push_back(node);
+
+  /* Allocate other attributes */
+  node_types_.push_back(type);
+  node_capacities_.push_back(-1);
+  node_pb_graph_pins_.push_back(nullptr);
+  node_intrinsic_costs_.push_back(0.);
+
+  node_in_edges_.emplace_back();
+  node_out_edges_.emplace_back();
+
+  return node;
+}
+
+void LbRRGraph::set_node_type(const LbRRNodeId& node, const e_lb_rr_type& type) {
+  VTR_ASSERT(true == valid_node_id(node));
+  node_types_[node] = type;
+}
+
+void LbRRGraph::set_node_capacity(const LbRRNodeId& node, const short& capacity) {
+  VTR_ASSERT(true == valid_node_id(node));
+  node_capacities_[node] = capacity;
+}
+
+void LbRRGraph::set_node_pb_graph_pin(const LbRRNodeId& node, t_pb_graph_pin* pb_graph_pin) {
+  VTR_ASSERT(true == valid_node_id(node));
+  node_pb_graph_pins_[node] = pb_graph_pin;
+
+  /* Register in fast node look-up */
+  if (node_type(node) >= node_lookup_.size()) {
+    node_lookup_.resize(node_type(node) + 1);
+  }
+
+  if (0 < node_lookup_[node_type(node)].count(pb_graph_pin)) {
+    VTR_LOG_WARN("Detect pb_graph_pin '%s[%lu]' is mapped to LbRRGraph nodes (exist: %lu) and (to be mapped: %lu). Overwrite is done\n",
+                 pb_graph_pin->port->name, pb_graph_pin->pin_number,
+                 size_t(node_lookup_[node_type(node)].at(pb_graph_pin)),
+                 size_t(node));
+  }
+  node_lookup_[node_type(node)][pb_graph_pin] = node;
+}
+
+void LbRRGraph::set_node_intrinsic_cost(const LbRRNodeId& node, const float& cost) {
+  VTR_ASSERT(true == valid_node_id(node));
+  node_intrinsic_costs_[node] = cost;
+}
+
+LbRREdgeId LbRRGraph::create_edge(const LbRRNodeId& source,
+                                  const LbRRNodeId& sink,
+                                  t_mode* mode) {
+  VTR_ASSERT(true == valid_node_id(source));
+  VTR_ASSERT(true == valid_node_id(sink));
+
+  /* Create an new id */
+  LbRREdgeId edge = LbRREdgeId(edge_ids_.size());
+  edge_ids_.push_back(edge);
+
+  /* Allocate other attributes */
+  edge_src_nodes_.push_back(source);
+  edge_sink_nodes_.push_back(sink);
+  edge_intrinsic_costs_.push_back(0.);
+  edge_modes_.push_back(mode);
+
+  node_out_edges_[source].push_back(edge);
+  node_in_edges_[sink].push_back(edge);
+
+  return edge;
+}
+
+void LbRRGraph::set_edge_intrinsic_cost(const LbRREdgeId& edge, const float& cost) {
+  VTR_ASSERT(true == valid_edge_id(edge));
+  edge_intrinsic_costs_[edge] = cost;
+}
+
+/******************************************************************************
+ * Public validators/invalidators
+ ******************************************************************************/
+bool LbRRGraph::valid_node_id(const LbRRNodeId& node_id) const {
+  return ( size_t(node_id) < node_ids_.size() ) && ( node_id == node_ids_[node_id] ); 
+}
+
+bool LbRRGraph::valid_edge_id(const LbRREdgeId& edge_id) const {
+  return ( size_t(edge_id) < edge_ids_.size() ) && ( edge_id == edge_ids_[edge_id] ); 
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/repack/lb_rr_graph.h b/openfpga/src/repack/lb_rr_graph.h
new file mode 100644
index 000000000..c6cfbd552
--- /dev/null
+++ b/openfpga/src/repack/lb_rr_graph.h
@@ -0,0 +1,296 @@
+/************************************************************************
+ * This file introduces a class to model a Routing Resource Graph (RRGraph or RRG) 
+ * which is used by packer.
+ *
+ * Overview
+ * ========
+ * RRGraph aims to describe in a general way how routing resources are connected
+ * inside a pb_graph 
+ * 
+ * A Routing Resource Graph (RRGraph or RRG) is a directed graph (has many cycles),
+ * which consists of a number of nodes and edges.
+ *
+ * Node
+ * ----
+ * Each node represents a routing resource, which could be 
+ * 1. an intermediate node(INTERMEDIATE_NODE), which are input/output pins of non-primitive and non-root pb_graph_nodes. It represents a pb_graph_pin that exists in a pb_graph 
+ * 2. a virtual source (SOURCE), which are inputs of root pb_graph_nodes or outputs of primitive pb_graph_node 
+ * 3. a sink node (SINK), which are outputs of root pb_graph_nodes or inputs or primitive pb_graph_node
+ *
+ * Edge
+ * ----
+ * Each edge represents a connection between two pb_graph_pins 
+ * It represents a pb_graph_edge in a pb_graph 
+ *
+ * Guidlines on using the LbRRGraph data structure 
+ * =============================================
+ *
+ * For those want to access data from RRGraph
+ * ------------------------------------------
+ * Some examples for most frequent data query:
+ * 
+ *     // Strongly suggest to use a read-only lb_rr_graph object
+ *     const LbRRGraph& lb_rr_graph;
+ *
+ *     // Access type of a node with a given node id
+ *     // Get the unique node id that you may get 
+ *     // from other data structures or functions 
+ *     LbRRNodeId node_id;                                    
+ *     e_lb_rr_type node_type = lb_rr_graph.node_type(node_id);
+ *
+ *     // Access all the fan-out edges from a given node  
+ *     for (const RREdgeId& out_edge_id : rr_graph.node_out_edges(node_id)) {
+ *       // Do something with out_edge
+ *     }
+ *     // If you only want to learn the number of fan-out edges
+ *     size_t num_out_edges = rr_graph.node_fan_out(node_id);
+ *
+ * Please refer to the detailed comments on each public accessors
+ *
+ * For those want to build/modify a LbRRGraph
+ * -----------------------------------------
+ * Do NOT add a builder to this data structure!
+ * Builders should be kept as free functions that use the public mutators
+ * We suggest developers to create builders in separated C/C++ source files
+ * outside the rr_graph header and source files
+ *
+ * After build/modify a RRGraph, please do run a fundamental check, a public accessor.
+ * to ensure that your RRGraph does not include invalid nodes/edges/switches/segements 
+ * as well as connections.
+ * The validate() function gurantees the consistency between internal data structures, 
+ * such as the id cross-reference between nodes and edges etc.,
+ * so failing it indicates a fatal bug!
+ * This is a must-do check! 
+ *
+ * Example: 
+ *    RRGraph lb_rr_graph;
+ *    ... // Building RRGraph
+ *    lb_rr_graph.validate(); 
+ *
+ * Optionally, we strongly recommend developers to run an advance check in check_rr_graph()  
+ * This guarantees legal and routable RRGraph for VPR routers.
+ *
+ * This checks for connectivity or other information in the RRGraph that is unexpected 
+ * or unusual in an FPGA, and likely indicates a problem in your graph generation. 
+ * However, if you are intentionally creating an RRGraph with this unusual, 
+ * buts still technically legal, behaviour, you can write your own check_rr_graph() with weaker assumptions. 
+ *
+ * Note: Do NOT modify the coordinate system for nodes, they are designed for downstream drawers and routers
+ *
+ * For those want to extend RRGraph data structure
+ * --------------------------------------------------------------------------
+ * Please avoid modifying any existing public/private accessors/mutators
+ * in order to keep a stable RRGraph object in the framework
+ * Developers may add more internal data to RRGraph as well as associate accessors/mutators
+ * Please update and comment on the added features properly to keep this data structure friendly to be extended.
+ *
+ * Try to keep your extension within only graph-related internal data to RRGraph.
+ * In other words, extension is necessary when the new node/edge attributes are needed.
+ * RRGraph should NOT include other data which are shared by other data structures outside.
+ * The rr-graph is the single largest data structure in VPR,
+ * so avoid adding unnecessary information per node or per edge to it, as it will impact memory footprint.
+ * Instead, using indices to point to the outside data source instead of embedding to RRGraph
+ * For example: 
+ *   For any placement/routing cost related information, try to extend t_rr_indexed_data, but not RRGraph
+ *   For any placement/routing results, try to extend PlaceContext and RoutingContext, but not RRGraph
+ * 
+ * For those want to develop placers or routers
+ * --------------------------------------------------------------------------
+ * The RRGraph is designed to be a read-only database/graph, once created.
+ * Placement and routing should NOT change any attributes of RRGraph.
+ * Any placement and routing results should be stored in other data structures, such as PlaceContext and RoutingContext. 
+ *
+ * Tracing Cross-Reference 
+ * =======================
+ * RRGraph is designed to a self-contained data structure as much as possible.
+ * It includes the switch information (rr_switch) and segment_information (rr_segment)
+ * which are necessary to build-up any external data structures.
+ *
+ * Internal cross-reference
+ * ------------------------
+ *
+ *  +--------+                  +--------+
+ *  |        |  node_in_edges   |        |
+ *  |        |  node_out_edges  |        |
+ *  |  Node  |----------------->|  Edge  |
+ *  |        |<-----------------|        | 
+ *  |        |  edge_src_node   |        | 
+ *  +--------+  edge_sink_node  +--------+ 
+ *
+ *
+ * External cross-reference
+ * ------------------------
+ * The only cross-reference to outside data structures is the cost_index
+ * corresponding to the data structure t_rr_index_data
+ * Details can be found in the definition of t_rr_index_data
+ * This allows rapid look up by the router of additional information it needs for this node, using a flyweight pattern.
+ *
+ * +---------+  pb_graph_pin   +----------------+
+ * | RRGraph |---------------->| Pb_graph_node  | 
+ * +---------+  pb_graph_edge  +----------------+
+ *
+ ***********************************************************************/
+#ifndef LB_RR_GRAPH_OBJ_H
+#define LB_RR_GRAPH_OBJ_H
+
+/*
+ * Notes in include header files in a head file 
+ * Only include the neccessary header files 
+ * that is required by the data types in the function/class declarations!
+ */
+/* Header files should be included in a sequence */
+/* Standard header files required go first */
+#include <limits>
+#include <vector>
+
+/* Header from vtrutil library */
+#include "vtr_range.h"
+#include "vtr_vector.h"
+
+/* Header from readarch library */
+#include "physical_types.h"
+
+/* Header from vpr library */
+#include "lb_rr_graph_types.h"
+
+#include "lb_rr_graph_fwd.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+class LbRRGraph {
+  public: /* Types */
+    /* Iterators used to create iterator-based loop for nodes/edges/switches/segments */
+    typedef vtr::vector<LbRRNodeId, LbRRNodeId>::const_iterator node_iterator;
+    typedef vtr::vector<LbRREdgeId, LbRREdgeId>::const_iterator edge_iterator;
+
+    /* Ranges used to create range-based loop for nodes/edges/switches/segments */
+    typedef vtr::Range<node_iterator> node_range;
+    typedef vtr::Range<edge_iterator> edge_range;
+
+  public: /* Accessors */
+    /* Aggregates: create range-based loops for nodes/edges/switches/segments
+     * To iterate over the nodes/edges/switches/segments in a RRGraph, 
+     *    using a range-based loop is suggested.
+     *  -----------------------------------------------------------------
+     *    Example: iterate over all the nodes
+     *      // Strongly suggest to use a read-only rr_graph object
+     *      const LbRRGraph& lb_rr_graph;
+     *      for (const LbRRNodeId& node : lb_rr_graph.nodes()) {
+     *        // Do something with each node
+     *      }
+     *
+     *      for (const LbRREdgeId& edge : lb_rr_graph.edges()) {
+     *        // Do something with each edge
+     *      }
+     *
+     */
+    node_range nodes() const;
+    edge_range edges() const;
+
+    /* Node-level attributes */
+    e_lb_rr_type node_type(const LbRRNodeId& node) const;
+    short node_capacity(const LbRRNodeId& node) const;
+    t_pb_graph_pin* node_pb_graph_pin(const LbRRNodeId& node) const;
+    float node_intrinsic_cost(const LbRRNodeId& node) const;
+
+    /* Get a list of edge ids, which are incoming edges to a node */
+    std::vector<LbRREdgeId> node_in_edges(const LbRRNodeId& node, t_mode* mode) const;
+
+    /* Get a list of edge ids, which are outgoing edges from a node */
+    std::vector<LbRREdgeId> node_out_edges(const LbRRNodeId& node, t_mode* mode) const;
+
+    LbRRNodeId find_node(const e_lb_rr_type& type, t_pb_graph_pin* pb_graph_pin) const;
+
+    /* Get the source node which drives a edge */
+    LbRRNodeId edge_src_node(const LbRREdgeId& edge) const;
+    /* Get the sink node which a edge ends to */
+    LbRRNodeId edge_sink_node(const LbRREdgeId& edge) const;
+
+    float edge_intrinsic_cost(const LbRREdgeId& edge) const;
+    t_mode* edge_mode(const LbRREdgeId& edge) const;
+
+  public: /* Mutators */
+    /* Reserve the lists of nodes, edges, switches etc. to be memory efficient. 
+     * This function is mainly used to reserve memory space inside RRGraph,
+     * when adding a large number of nodes/edge/switches/segments,
+     * in order to avoid memory fragements
+     * For example: 
+     *    LbRRGraph lb_rr_graph;
+     *    // Add 1000 CHANX nodes to the LbRRGraph object
+     *    rr_graph.reserve_nodes(1000);
+     *    for (size_t i = 0; i < 1000; ++i) {
+     *      rr_graph.create_node(CHANX);
+     *    }
+     */
+    void reserve_nodes(const unsigned long& num_nodes);
+    void reserve_edges(const unsigned long& num_edges);
+
+    /* Add new elements (node, edge, switch, etc.) to RRGraph */
+    /* Add a node to the RRGraph with a deposited type 
+     * Detailed node-level information should be added using the set_node_* functions
+     * For example: 
+     *   RRNodeId node = create_node();
+     *   set_node_xlow(node, 0);
+     */
+    LbRRNodeId create_node(const e_lb_rr_type& type);
+
+    /* Set node-level information */
+    void set_node_type(const LbRRNodeId& node, const e_lb_rr_type& type);
+
+    void set_node_capacity(const LbRRNodeId& node, const short& capacity);
+
+    void set_node_pb_graph_pin(const LbRRNodeId& node, t_pb_graph_pin* pb_graph_pin);
+
+    void set_node_intrinsic_cost(const LbRRNodeId& node, const float& cost);
+
+    /* Add a edge to the RRGraph, by providing the source and sink node 
+     * This function will automatically create a node and
+     * configure the nodes and edges in connection   
+     */
+    LbRREdgeId create_edge(const LbRRNodeId& source, const LbRRNodeId& sink, t_mode* mode);
+    void set_edge_intrinsic_cost(const LbRREdgeId& edge, const float& cost);
+
+  public: /* Validators */
+    /* Validate is the node id does exist in the RRGraph */
+    bool valid_node_id(const LbRRNodeId& node) const;
+
+    /* Validate is the edge id does exist in the RRGraph */
+    bool valid_edge_id(const LbRREdgeId& edge) const;
+
+  private: /* Internal Data */
+    /* Node related data */
+    vtr::vector<LbRRNodeId, LbRRNodeId> node_ids_;
+
+    vtr::vector<LbRRNodeId, e_lb_rr_type> node_types_;
+
+    vtr::vector<LbRRNodeId, short> node_capacities_;
+
+    vtr::vector<LbRRNodeId, t_pb_graph_pin*> node_pb_graph_pins_;
+
+    vtr::vector<LbRRNodeId, float> node_intrinsic_costs_;
+
+    /* Edges per node is sorted by modes: [<mode_id>][<in_edges...><out_edges>] */
+    vtr::vector<LbRRNodeId, std::vector<LbRREdgeId>> node_in_edges_;
+    vtr::vector<LbRRNodeId, std::vector<LbRREdgeId>> node_out_edges_;
+
+    /* Edge related data */
+    /* Range of edge ids, use the unsigned long as 
+     * the number of edges could be >10 times larger than the number of nodes! 
+     */
+    vtr::vector<LbRREdgeId, LbRREdgeId> edge_ids_;
+    vtr::vector<LbRREdgeId, LbRRNodeId> edge_src_nodes_;
+    vtr::vector<LbRREdgeId, LbRRNodeId> edge_sink_nodes_;
+    vtr::vector<LbRREdgeId, float> edge_intrinsic_costs_;
+    vtr::vector<LbRREdgeId, t_mode*> edge_modes_;
+
+    /* Fast look-up to search a node by its type, coordinator and ptc_num 
+     * Indexing of fast look-up: [0..NUM_TYPES-1][t_pb_graph_pin*] 
+     */
+    typedef std::vector<std::map<t_pb_graph_pin*, LbRRNodeId>> NodeLookup;
+    mutable NodeLookup node_lookup_;
+};
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/repack/lb_rr_graph_fwd.h b/openfpga/src/repack/lb_rr_graph_fwd.h
new file mode 100644
index 000000000..22363628b
--- /dev/null
+++ b/openfpga/src/repack/lb_rr_graph_fwd.h
@@ -0,0 +1,19 @@
+#ifndef LB_RR_GRAPH_OBJ_FWD_H
+#define LB_RR_GRAPH_OBJ_FWD_H
+#include "vtr_strong_id.h"
+
+/***************************************************************
+ * This file includes a light declaration for the class LbRRGraph
+ * For a detailed description and how to use the class LbRRGraph,
+ * please refer to lb_rr_graph_obj.h
+ ***************************************************************/
+
+class LbRRGraph;
+
+struct lb_rr_node_id_tag;
+struct lb_rr_edge_id_tag;
+
+typedef vtr::StrongId<lb_rr_node_id_tag> LbRRNodeId;
+typedef vtr::StrongId<lb_rr_edge_id_tag> LbRREdgeId;
+
+#endif
diff --git a/vpr/src/pack/pack_types.h b/vpr/src/pack/pack_types.h
index c8d266b57..794173217 100644
--- a/vpr/src/pack/pack_types.h
+++ b/vpr/src/pack/pack_types.h
@@ -13,20 +13,12 @@
 #include "arch_types.h"
 #include "atom_netlist_fwd.h"
 
+#include "lb_rr_graph_types.h"
+
 /**************************************************************************
  * Packing Algorithm Enumerations
  ***************************************************************************/
 
-/* Describes different types of intra-logic cluster_ctx.blocks routing resource nodes */
-enum e_lb_rr_type {
-    LB_SOURCE = 0,
-    LB_SINK,
-    LB_INTERMEDIATE,
-    NUM_LB_RR_TYPES
-};
-const std::vector<const char*> lb_rr_type_str{
-    "LB_SOURCE", "LB_SINK", "LB_INTERMEDIATE", "INVALID"};
-
 /**************************************************************************
  * Packing Algorithm Data Structures
  ***************************************************************************/

From 6c69b52ded70c75e8ad929e31b12fab0b97df025 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 17 Feb 2020 17:11:29 -0700
Subject: [PATCH 164/645] Add missing file

---
 openfpga/src/base/openfpga_context.h |  1 +
 vpr/src/pack/lb_rr_graph_types.h     | 14 ++++++++++++++
 2 files changed, 15 insertions(+)
 create mode 100644 vpr/src/pack/lb_rr_graph_types.h

diff --git a/openfpga/src/base/openfpga_context.h b/openfpga/src/base/openfpga_context.h
index 5726cbba9..a8b37dcf7 100644
--- a/openfpga/src/base/openfpga_context.h
+++ b/openfpga/src/base/openfpga_context.h
@@ -11,6 +11,7 @@
 #include "tile_direct.h"
 #include "module_manager.h"
 #include "openfpga_flow_manager.h"
+#include "lb_rr_graph.h"
 #include "device_rr_gsb.h"
 
 /********************************************************************
diff --git a/vpr/src/pack/lb_rr_graph_types.h b/vpr/src/pack/lb_rr_graph_types.h
new file mode 100644
index 000000000..7abe7a5cf
--- /dev/null
+++ b/vpr/src/pack/lb_rr_graph_types.h
@@ -0,0 +1,14 @@
+#ifndef LB_RR_GRPAH_TYPES_H
+#define LB_RR_GRPAH_TYPES_H
+
+/* Describes different types of intra-logic cluster_ctx.blocks routing resource nodes */
+enum e_lb_rr_type {
+    LB_SOURCE = 0,
+    LB_SINK,
+    LB_INTERMEDIATE,
+    NUM_LB_RR_TYPES
+};
+const std::vector<const char*> lb_rr_type_str{
+    "LB_SOURCE", "LB_SINK", "LB_INTERMEDIATE", "INVALID"};
+
+#endif

From 62e4f14e3099bb4c262ba398ecec22980957f7b2 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 17 Feb 2020 17:26:27 -0700
Subject: [PATCH 165/645] add lb_rr_graph to device annotation

---
 .../src/annotation/vpr_device_annotation.cpp   | 18 ++++++++++++++++++
 .../src/annotation/vpr_device_annotation.h     |  6 ++++++
 openfpga/src/base/openfpga_context.h           |  1 -
 3 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/openfpga/src/annotation/vpr_device_annotation.cpp b/openfpga/src/annotation/vpr_device_annotation.cpp
index 5b36e3885..9be30591d 100644
--- a/openfpga/src/annotation/vpr_device_annotation.cpp
+++ b/openfpga/src/annotation/vpr_device_annotation.cpp
@@ -241,6 +241,14 @@ ArchDirectId VprDeviceAnnotation::direct_annotation(const size_t& direct) const
   return direct_annotations_.at(direct);
 }
 
+LbRRGraph VprDeviceAnnotation::physical_lb_rr_graph(t_pb_graph_node* pb_graph_head) const {
+  /* Ensure that the rr_switch is in the list */
+  if (0 == physical_lb_rr_graphs_.count(pb_graph_head)) {
+    return LbRRGraph();
+  }
+  return physical_lb_rr_graphs_.at(pb_graph_head);
+}
+
 /************************************************************************
  * Public mutators
  ***********************************************************************/
@@ -470,4 +478,14 @@ void VprDeviceAnnotation::add_direct_annotation(const size_t& direct, const Arch
   direct_annotations_[direct] = arch_direct_id;
 }
 
+void VprDeviceAnnotation::add_physical_lb_rr_graph(t_pb_graph_node* pb_graph_head, const LbRRGraph& lb_rr_graph) {
+  /* Warn any override attempt */
+  if (0 < physical_lb_rr_graphs_.count(pb_graph_head)) {
+    VTR_LOG_WARN("Override the physical lb_rr_graph for pb_graph_head '%s'!\n",
+                 pb_graph_head->pb_type->name);
+  }
+
+  physical_lb_rr_graphs_[pb_graph_head] = lb_rr_graph;
+}
+
 } /* End namespace openfpga*/
diff --git a/openfpga/src/annotation/vpr_device_annotation.h b/openfpga/src/annotation/vpr_device_annotation.h
index 5c083e367..0ecff4371 100644
--- a/openfpga/src/annotation/vpr_device_annotation.h
+++ b/openfpga/src/annotation/vpr_device_annotation.h
@@ -19,6 +19,7 @@
 #include "openfpga_port.h"
 #include "circuit_library.h"
 #include "arch_direct.h"
+#include "lb_rr_graph.h"
 
 /* Begin namespace openfpga */
 namespace openfpga {
@@ -73,6 +74,7 @@ class VprDeviceAnnotation {
     CircuitModelId rr_switch_circuit_model(const RRSwitchId& rr_switch) const;
     CircuitModelId rr_segment_circuit_model(const RRSegmentId& rr_segment) const;
     ArchDirectId direct_annotation(const size_t& direct) const;
+    LbRRGraph physical_lb_rr_graph(t_pb_graph_node* pb_graph_head) const;
   public:  /* Public mutators */
     void add_pb_type_physical_mode(t_pb_type* pb_type, t_mode* physical_mode);
     void add_physical_pb_type(t_pb_type* operating_pb_type, t_pb_type* physical_pb_type);
@@ -93,6 +95,7 @@ class VprDeviceAnnotation {
     void add_rr_switch_circuit_model(const RRSwitchId& rr_switch, const CircuitModelId& circuit_model);
     void add_rr_segment_circuit_model(const RRSegmentId& rr_segment, const CircuitModelId& circuit_model);
     void add_direct_annotation(const size_t& direct, const ArchDirectId& arch_direct_id);
+    void add_physical_lb_rr_graph(t_pb_graph_node* pb_graph_head, const LbRRGraph& lb_rr_graph);
   private: /* Internal data */
     /* Pair a regular pb_type to its physical pb_type */
     std::map<t_pb_type*, t_pb_type*> physical_pb_types_;
@@ -176,6 +179,9 @@ class VprDeviceAnnotation {
 
     /* Pair a direct connection (direct) to a annotation which contains circuit model id */
     std::map<size_t, ArchDirectId> direct_annotations_;
+
+    /* Logical type routing resource graphs built from physical modes */
+    std::map<t_pb_graph_node*, LbRRGraph> physical_lb_rr_graphs_;
 };
 
 } /* End namespace openfpga*/
diff --git a/openfpga/src/base/openfpga_context.h b/openfpga/src/base/openfpga_context.h
index a8b37dcf7..5726cbba9 100644
--- a/openfpga/src/base/openfpga_context.h
+++ b/openfpga/src/base/openfpga_context.h
@@ -11,7 +11,6 @@
 #include "tile_direct.h"
 #include "module_manager.h"
 #include "openfpga_flow_manager.h"
-#include "lb_rr_graph.h"
 #include "device_rr_gsb.h"
 
 /********************************************************************

From 8e97443410382fb47f006922ba8b533b7b165453 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 17 Feb 2020 17:57:43 -0700
Subject: [PATCH 166/645] start working on repack

---
 .../src/base/openfpga_bitstream_command.cpp   | 38 +++++++++++++++++++
 .../src/base/openfpga_bitstream_command.h     | 21 ++++++++++
 openfpga/src/base/openfpga_repack.cpp         | 33 ++++++++++++++++
 openfpga/src/base/openfpga_repack.h           | 23 +++++++++++
 openfpga/src/main.cpp                         |  4 ++
 openfpga/src/repack/repack.cpp                | 32 ++++++++++++++++
 openfpga/src/repack/repack.h                  | 27 +++++++++++++
 7 files changed, 178 insertions(+)
 create mode 100644 openfpga/src/base/openfpga_bitstream_command.cpp
 create mode 100644 openfpga/src/base/openfpga_bitstream_command.h
 create mode 100644 openfpga/src/base/openfpga_repack.cpp
 create mode 100644 openfpga/src/base/openfpga_repack.h
 create mode 100644 openfpga/src/repack/repack.cpp
 create mode 100644 openfpga/src/repack/repack.h

diff --git a/openfpga/src/base/openfpga_bitstream_command.cpp b/openfpga/src/base/openfpga_bitstream_command.cpp
new file mode 100644
index 000000000..827dd1eca
--- /dev/null
+++ b/openfpga/src/base/openfpga_bitstream_command.cpp
@@ -0,0 +1,38 @@
+/********************************************************************
+ * Add commands to the OpenFPGA shell interface, 
+ * in purpose of generate Verilog netlists modeling the full FPGA fabric
+ * This is one of the core engine of openfpga, including:
+ * - repack : create physical pbs and redo packing 
+ *******************************************************************/
+#include "openfpga_repack.h"
+#include "openfpga_bitstream_command.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void add_openfpga_bitstream_commands(openfpga::Shell<OpenfpgaContext>& shell) {
+  /* Get the unique id of 'build_fabric' command which is to be used in creating the dependency graph */
+  const ShellCommandId& shell_cmd_build_fabric_id = shell.command(std::string("build_fabric"));
+
+  /* Add a new class of commands */
+  ShellCommandClassId openfpga_bitstream_cmd_class = shell.add_command_class("FPGA-Bitstream");
+
+  /******************************** 
+   * Command 'repack' 
+   */
+  Command shell_cmd_repack("repack");
+  /* Add an option '--verbose' */
+  shell_cmd_repack.add_option("verbose", false, "Enable verbose output");
+  
+  /* Add command 'repack' to the Shell */
+  ShellCommandId shell_cmd_repack_id = shell.add_command(shell_cmd_repack, "Pack physical programmable logic blocks");
+  shell.set_command_class(shell_cmd_repack_id, openfpga_bitstream_cmd_class);
+  shell.set_command_execute_function(shell_cmd_repack_id, repack);
+
+  /* The 'repack' command should NOT be executed before 'build_fabric' */
+  std::vector<ShellCommandId> cmd_dependency_repack;
+  cmd_dependency_repack.push_back(shell_cmd_build_fabric_id);
+  shell.set_command_dependency(shell_cmd_repack_id, cmd_dependency_repack);
+} 
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_bitstream_command.h b/openfpga/src/base/openfpga_bitstream_command.h
new file mode 100644
index 000000000..d58555dd8
--- /dev/null
+++ b/openfpga/src/base/openfpga_bitstream_command.h
@@ -0,0 +1,21 @@
+#ifndef OPENFPGA_BITSTREAM_COMMAND_H
+#define OPENFPGA_BITSTREAM_COMMAND_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "shell.h"
+#include "openfpga_context.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void add_openfpga_bitstream_commands(openfpga::Shell<OpenfpgaContext>& shell); 
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/base/openfpga_repack.cpp b/openfpga/src/base/openfpga_repack.cpp
new file mode 100644
index 000000000..f605233da
--- /dev/null
+++ b/openfpga/src/base/openfpga_repack.cpp
@@ -0,0 +1,33 @@
+/********************************************************************
+ * This file includes functions to compress the hierachy of routing architecture
+ *******************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_time.h"
+#include "vtr_log.h"
+
+#include "verilog_api.h"
+#include "repack.h"
+#include "openfpga_repack.h"
+
+/* Include global variables of VPR */
+#include "globals.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * A wrapper function to call the fabric_verilog function of FPGA-Verilog 
+ *******************************************************************/
+void repack(OpenfpgaContext& openfpga_ctx,
+            const Command& cmd, const CommandContext& cmd_context) {
+
+  CommandOptionId opt_verbose = cmd.option("verbose");
+
+  pack_physical_pbs(g_vpr_ctx.device(),
+                    openfpga_ctx.mutable_vpr_device_annotation(),
+                    openfpga_ctx.mutable_vpr_clustering_annotation(),
+                    openfpga_ctx.vpr_routing_annotation(),
+                    cmd_context.option_enable(cmd, opt_verbose));
+} 
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_repack.h b/openfpga/src/base/openfpga_repack.h
new file mode 100644
index 000000000..0fce62f78
--- /dev/null
+++ b/openfpga/src/base/openfpga_repack.h
@@ -0,0 +1,23 @@
+#ifndef OPENFPGA_REPACK_H
+#define OPENFPGA_REPACK_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "command.h"
+#include "command_context.h"
+#include "openfpga_context.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void repack(OpenfpgaContext& openfpga_ctx,
+            const Command& cmd, const CommandContext& cmd_context); 
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/main.cpp b/openfpga/src/main.cpp
index 792223e3c..c018db4bf 100644
--- a/openfpga/src/main.cpp
+++ b/openfpga/src/main.cpp
@@ -13,6 +13,7 @@
 #include "vpr_command.h"
 #include "openfpga_setup_command.h"
 #include "openfpga_verilog_command.h"
+#include "openfpga_bitstream_command.h"
 #include "basic_command.h"
 
 #include "openfpga_title.h"
@@ -56,6 +57,9 @@ int main(int argc, char** argv) {
   /* Add openfpga verilog commands */
   openfpga::add_openfpga_verilog_commands(shell);
 
+  /* Add openfpga bitstream commands */
+  openfpga::add_openfpga_bitstream_commands(shell);
+
   /* Add basic commands: exit, help, etc. 
    * Note:
    * This MUST be the last command group to be added! 
diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp
new file mode 100644
index 000000000..2a7dada40
--- /dev/null
+++ b/openfpga/src/repack/repack.cpp
@@ -0,0 +1,32 @@
+/***************************************************************************************
+ * This file includes functions that are used to redo packing for physical pbs
+ ***************************************************************************************/
+
+/* Headers from vtrutil library */
+#include "vtr_log.h"
+#include "vtr_assert.h"
+#include "vtr_time.h"
+
+#include "repack.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/***************************************************************************************
+ * Top-level function to pack physical pb_graph 
+ * This function will do :
+ *  - create physical lb_rr_graph for each pb_graph considering physical modes only
+ *    the lb_rr_graph willbe added to device annotation
+ *  - annotate nets to be routed for each clustered block from operating modes of pb_graph 
+ *    to physical modes of pb_graph
+ *  - rerun the routing for each clustered block
+ *  - store the packing results to clustering annotation
+ ***************************************************************************************/
+void pack_physical_pbs(const DeviceContext& device_ctx,
+                       VprDeviceAnnotation& device_annotation,
+                       VprClusteringAnnotation& clustering_annotation,
+                       const VprRoutingAnnotation& routing_annotation,
+                       const bool& verbose) {
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/repack/repack.h b/openfpga/src/repack/repack.h
new file mode 100644
index 000000000..733a7d1ac
--- /dev/null
+++ b/openfpga/src/repack/repack.h
@@ -0,0 +1,27 @@
+#ifndef REPACK_H
+#define REPACK_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "vpr_context.h"
+#include "vpr_device_annotation.h"
+#include "vpr_clustering_annotation.h"
+#include "vpr_routing_annotation.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void pack_physical_pbs(const DeviceContext& device_ctx,
+                       VprDeviceAnnotation& device_annotation,
+                       VprClusteringAnnotation& clustering_annotation,
+                       const VprRoutingAnnotation& routing_annotation,
+                       const bool& verbose);
+
+} /* end namespace openfpga */
+
+#endif

From 409b3f68960168bce7728733200fb80ee571d5c8 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 17 Feb 2020 21:11:56 -0700
Subject: [PATCH 167/645] add lb_rr_graph builder for the refactored version

---
 openfpga/src/base/openfpga_link_arch.cpp      |   5 +
 openfpga/src/base/openfpga_repack.cpp         |   2 +-
 .../src/repack/build_physical_lb_rr_graph.cpp | 404 ++++++++++++++++++
 .../src/repack/build_physical_lb_rr_graph.h   |  23 +
 openfpga/src/repack/repack.cpp                |   2 +-
 openfpga/src/repack/repack.h                  |   2 +-
 openfpga/test_script/s298_k6_frac.openfpga    |   2 +-
 7 files changed, 436 insertions(+), 4 deletions(-)
 create mode 100644 openfpga/src/repack/build_physical_lb_rr_graph.cpp
 create mode 100644 openfpga/src/repack/build_physical_lb_rr_graph.h

diff --git a/openfpga/src/base/openfpga_link_arch.cpp b/openfpga/src/base/openfpga_link_arch.cpp
index 567ad2e08..ac403592c 100644
--- a/openfpga/src/base/openfpga_link_arch.cpp
+++ b/openfpga/src/base/openfpga_link_arch.cpp
@@ -15,6 +15,7 @@
 #include "annotate_rr_graph.h"
 #include "mux_library_builder.h"
 #include "build_tile_direct.h"
+#include "build_physical_lb_rr_graph.h"
 #include "openfpga_link_arch.h"
 
 /* Include global variables of VPR */
@@ -112,6 +113,10 @@ void link_arch(OpenfpgaContext& openfpga_ctx,
   openfpga_ctx.mutable_tile_direct() =  build_device_tile_direct(g_vpr_ctx.device(),
                                                                  openfpga_ctx.arch().arch_direct);
 
+
+  build_physical_lb_rr_graphs(g_vpr_ctx.device(),
+                              openfpga_ctx.mutable_vpr_device_annotation(),
+                              cmd_context.option_enable(cmd, opt_verbose));
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_repack.cpp b/openfpga/src/base/openfpga_repack.cpp
index f605233da..c58e2b4ff 100644
--- a/openfpga/src/base/openfpga_repack.cpp
+++ b/openfpga/src/base/openfpga_repack.cpp
@@ -24,7 +24,7 @@ void repack(OpenfpgaContext& openfpga_ctx,
   CommandOptionId opt_verbose = cmd.option("verbose");
 
   pack_physical_pbs(g_vpr_ctx.device(),
-                    openfpga_ctx.mutable_vpr_device_annotation(),
+                    openfpga_ctx.vpr_device_annotation(),
                     openfpga_ctx.mutable_vpr_clustering_annotation(),
                     openfpga_ctx.vpr_routing_annotation(),
                     cmd_context.option_enable(cmd, opt_verbose));
diff --git a/openfpga/src/repack/build_physical_lb_rr_graph.cpp b/openfpga/src/repack/build_physical_lb_rr_graph.cpp
new file mode 100644
index 000000000..4b7107fbb
--- /dev/null
+++ b/openfpga/src/repack/build_physical_lb_rr_graph.cpp
@@ -0,0 +1,404 @@
+/***************************************************************************************
+ * This file includes functions that are used to redo packing for physical pbs
+ ***************************************************************************************/
+
+/* Headers from vtrutil library */
+#include "vtr_log.h"
+#include "vtr_assert.h"
+#include "vtr_time.h"
+
+#include "pb_type_utils.h"
+
+#include "build_physical_lb_rr_graph.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/***************************************************************************************
+ * Create all the intermediate nodes for lb_rr_graph for each pb_graph_node.
+ * Different from the lb_rr_graph builder in VPR packer, this function only consider 
+ * the pb_graph_node under physical modes
+ ***************************************************************************************/
+static 
+void rec_build_physical_lb_rr_node_for_pb_graph_node(t_pb_graph_node* pb_graph_node,
+                                                     LbRRGraph& lb_rr_graph,
+                                                     const VprDeviceAnnotation& device_annotation) {
+  t_pb_type* pb_type = pb_graph_node->pb_type;
+
+  /* TODO: think if we need to consider wire mode of LUT when creating the lb_rr_graph here! 
+   * Should we create edges through the LUT input and output nodes?
+   */
+
+  /* The only difference between primitive node and intermediate nodes is
+   * the output pins of primitive node will be SINK node
+   * Otherwise it is always INTERMEDIATE node
+   */
+  e_lb_rr_type output_pin_rr_type = LB_INTERMEDIATE;
+  if (true == is_primitive_pb_type(pb_type)) {
+    output_pin_rr_type = LB_SOURCE; 
+  }
+
+  /* alloc and load input pins that connect to sinks */
+  for (int iport = 0; iport < pb_graph_node->num_input_ports; iport++) {
+    for (int ipin = 0; ipin < pb_graph_node->num_input_pins[iport]; ipin++) {
+      /* load intermediate indices */
+      t_pb_graph_pin* pb_pin = &pb_graph_node->input_pins[iport][ipin];
+
+      /* alloc and load rr node info */
+      LbRRNodeId node = lb_rr_graph.create_node(LB_INTERMEDIATE);
+      lb_rr_graph.set_node_capacity(node, 1);
+      lb_rr_graph.set_node_pb_graph_pin(node, pb_pin);
+
+      /* TODO: Double check if this is the case */
+      lb_rr_graph.set_node_intrinsic_cost(node, 1);
+    }
+  }
+
+  /* alloc and load input pins that connect to sinks */
+  for (int iport = 0; iport < pb_graph_node->num_clock_ports; iport++) {
+    for (int ipin = 0; ipin < pb_graph_node->num_clock_pins[iport]; ipin++) {
+      /* load intermediate indices */
+      t_pb_graph_pin* pb_pin = &pb_graph_node->clock_pins[iport][ipin];
+
+      /* alloc and load rr node info */
+      LbRRNodeId node = lb_rr_graph.create_node(LB_INTERMEDIATE);
+      lb_rr_graph.set_node_capacity(node, 1);
+      lb_rr_graph.set_node_pb_graph_pin(node, pb_pin);
+
+      /* TODO: Double check if this is the case */
+      lb_rr_graph.set_node_intrinsic_cost(node, 1);
+    }
+  }
+
+  /* alloc and load output pins that are represented as rr sources */
+  for (int iport = 0; iport < pb_graph_node->num_output_ports; iport++) {
+    for (int ipin = 0; ipin < pb_graph_node->num_output_pins[iport]; ipin++) {
+      /* load intermediate indices */
+      t_pb_graph_pin* pb_pin = &pb_graph_node->output_pins[iport][ipin];
+
+      /* alloc and load rr node info */
+      LbRRNodeId node = lb_rr_graph.create_node(output_pin_rr_type);
+      lb_rr_graph.set_node_capacity(node, 1);
+      lb_rr_graph.set_node_pb_graph_pin(node, pb_pin);
+
+      /* TODO: Double check if this is the case */
+      lb_rr_graph.set_node_intrinsic_cost(node, 1);
+    }
+  }
+
+  if (true == is_primitive_pb_type(pb_type)) {
+    return; 
+  }
+
+  /* For non-primitive node: 
+   * This pb_graph_node is a logic block or subcluster 
+   * Go recusrively 
+   */
+  t_mode* physical_mode = device_annotation.physical_mode(pb_type);
+  for (int ipb_type = 0; ipb_type < physical_mode->num_pb_type_children; ipb_type++) {
+    for (int ipb = 0; ipb < physical_mode->pb_type_children[ipb_type].num_pb; ipb++) {
+      rec_build_physical_lb_rr_node_for_pb_graph_node(&(pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb_type][ipb]), lb_rr_graph, device_annotation);
+    }
+  }
+}
+
+/***************************************************************************************
+ * Build the edge for an input/clock pb_graph_pin for a primitive pb_graph node
+ * This function will identify if the port equivalence should be considered 
+ ***************************************************************************************/
+static 
+void build_lb_rr_edge_primitive_pb_graph_input_pin(LbRRGraph& lb_rr_graph,
+                                                   t_pb_graph_pin* pb_pin,
+                                                   LbRRNodeId& sink_node) {
+  /* Find the node that we have already created */
+  LbRRNodeId node = lb_rr_graph.find_node(LB_INTERMEDIATE, pb_pin);
+  VTR_ASSERT(true == lb_rr_graph.valid_node_id(node));
+
+  PortEquivalence port_equivalent = pb_pin->port->equivalent;
+
+  if (port_equivalent == PortEquivalence::NONE || sink_node == LbRRNodeId::INVALID()) {
+    /* Create new sink for input to primitive */
+    LbRRNodeId new_sink = lb_rr_graph.create_node(LB_SINK);
+    if (port_equivalent != PortEquivalence::NONE) {
+      lb_rr_graph.set_node_capacity(new_sink, pb_pin->port->num_pins);
+    } else {
+      lb_rr_graph.set_node_capacity(new_sink, 1);
+    }
+    sink_node = new_sink;
+  }
+  
+  /* Connect the nodes denoting the input pins to sink, since this is a primtive node, we do not have any mode */ 
+  LbRREdgeId edge = lb_rr_graph.create_edge(node, sink_node, nullptr);
+
+  /* TODO: Double check if this is the case */
+  lb_rr_graph.set_edge_intrinsic_cost(edge, 1.); 
+}
+
+/***************************************************************************************
+ * Build the edge for a pb_graph_pin for a non-primitive pb_graph node
+ * Note: 
+ *   - this function is NOT applicable to 
+ *     - any input pin of primitive pb_graph_node 
+ *     - any output pin of root pb_graph_node!
+ ***************************************************************************************/
+static 
+void build_lb_rr_edge_pb_graph_pin(LbRRGraph& lb_rr_graph,
+                                   t_pb_graph_pin* pb_pin,
+                                   const e_lb_rr_type& pin_rr_type,
+                                   t_mode* physical_mode) {
+  /* Find the node that we have already created */
+  LbRRNodeId from_node = lb_rr_graph.find_node(pin_rr_type, pb_pin);
+  VTR_ASSERT(true == lb_rr_graph.valid_node_id(from_node));
+
+  /* Load edges only for physical mode! */
+  for (int iedge = 0; iedge < pb_pin->num_output_edges; iedge++) {
+    VTR_ASSERT(1 == pb_pin->output_edges[iedge]->num_output_pins);
+    if (physical_mode != pb_pin->output_edges[iedge]->interconnect->parent_mode) {
+      continue;
+    }
+    /* Find the node that we have already created */
+    LbRRNodeId to_node = lb_rr_graph.find_node(LB_INTERMEDIATE, pb_pin->output_edges[iedge]->output_pins[0]);
+    VTR_ASSERT(true == lb_rr_graph.valid_node_id(to_node));
+    LbRREdgeId edge = lb_rr_graph.create_edge(from_node, to_node, physical_mode);
+
+    /* TODO: Double check if this is the case */
+    lb_rr_graph.set_edge_intrinsic_cost(edge, 1.); 
+  }
+}
+
+/***************************************************************************************
+ * Build the edge for an output pb_graph_pin for a root pb_graph node
+ * These node should be connected to a command external lb_rr_node
+ ***************************************************************************************/
+static 
+void build_lb_rr_edge_root_pb_graph_pin(LbRRGraph& lb_rr_graph,
+                                        t_pb_graph_pin* pb_pin,
+                                        const e_lb_rr_type& pin_rr_type,
+                                        const LbRRNodeId& ext_rr_index) {
+  /* Find the node that we have already created */
+  LbRRNodeId from_node = lb_rr_graph.find_node(pin_rr_type, pb_pin);
+  VTR_ASSERT(true == lb_rr_graph.valid_node_id(from_node));
+
+  LbRREdgeId edge = lb_rr_graph.create_edge(from_node, ext_rr_index, nullptr);
+
+  /* TODO: Double check if this is the case */
+  lb_rr_graph.set_edge_intrinsic_cost(edge, 1.); 
+}
+
+/***************************************************************************************
+ * Create all the edges and special nodes (SOURCE/SINK) for lb_rr_graph for each pb_graph_node.
+ * Different from the lb_rr_graph builder in VPR packer, this function only consider 
+ * the pb_graph_node under physical modes
+ ***************************************************************************************/
+static 
+void rec_build_physical_lb_rr_edge_for_pb_graph_node(t_pb_graph_node* pb_graph_node,
+                                                     LbRRGraph& lb_rr_graph,
+                                                     const LbRRNodeId& ext_rr_index,
+                                                     const VprDeviceAnnotation& device_annotation) {
+  t_pb_type* pb_type = pb_graph_node->pb_type;
+  t_pb_graph_node* parent_node = pb_graph_node->parent_pb_graph_node;
+
+  /* TODO: think if we need to consider wire mode of LUT when creating the lb_rr_graph here! 
+   * Should we create edges through the LUT input and output nodes?
+   */
+
+  /* The only difference between primitive node and intermediate nodes is
+   * the output pins of primitive node will be SINK node
+   * Otherwise it is always INTERMEDIATE node
+   */
+  /* The input pins should connect to sinks */
+  for (int iport = 0; iport < pb_graph_node->num_input_ports; iport++) {
+    LbRRNodeId sink_node = LbRRNodeId::INVALID();
+    for (int ipin = 0; ipin < pb_graph_node->num_input_pins[iport]; ipin++) {
+      /* load intermediate indices */
+      t_pb_graph_pin* pb_pin = &pb_graph_node->input_pins[iport][ipin];
+      t_mode* physical_mode = device_annotation.physical_mode(pb_type);
+
+      if (true == is_primitive_pb_type(pb_type)) {
+        build_lb_rr_edge_primitive_pb_graph_input_pin(lb_rr_graph, pb_pin, sink_node);
+      } else {
+        VTR_ASSERT(false == is_primitive_pb_type(pb_type));
+        build_lb_rr_edge_pb_graph_pin(lb_rr_graph, pb_pin, LB_INTERMEDIATE, physical_mode);
+      }
+    }
+  }
+  /* The input pins should connect to sinks */
+  for (int iport = 0; iport < pb_graph_node->num_clock_ports; iport++) {
+    LbRRNodeId sink_node = LbRRNodeId::INVALID();
+    for (int ipin = 0; ipin < pb_graph_node->num_clock_pins[iport]; ipin++) {
+      /* load intermediate indices */
+      t_pb_graph_pin* pb_pin = &pb_graph_node->clock_pins[iport][ipin];
+      t_mode* physical_mode = device_annotation.physical_mode(pb_type);
+
+      if (true == is_primitive_pb_type(pb_type)) {
+        build_lb_rr_edge_primitive_pb_graph_input_pin(lb_rr_graph, pb_pin, sink_node);
+      } else {
+        VTR_ASSERT(false == is_primitive_pb_type(pb_type));
+        build_lb_rr_edge_pb_graph_pin(lb_rr_graph, pb_pin, LB_INTERMEDIATE, physical_mode);
+      }
+    }
+  }
+
+  e_lb_rr_type output_pin_rr_type = LB_INTERMEDIATE;
+  if (true == is_primitive_pb_type(pb_type)) {
+    output_pin_rr_type = LB_SOURCE;
+  }
+
+  /* The output pins should connect to its fan-outs */
+  for (int iport = 0; iport < pb_graph_node->num_output_ports; iport++) {
+    for (int ipin = 0; ipin < pb_graph_node->num_output_pins[iport]; ipin++) {
+      /* load intermediate indices */
+      t_pb_graph_pin* pb_pin = &pb_graph_node->output_pins[iport][ipin];
+
+      if (true == pb_graph_node->is_root()) {
+        build_lb_rr_edge_root_pb_graph_pin(lb_rr_graph, pb_pin, output_pin_rr_type, ext_rr_index);
+      } else {
+        VTR_ASSERT(false == pb_graph_node->is_root());
+        t_mode* physical_mode = device_annotation.physical_mode(parent_node->pb_type);
+        build_lb_rr_edge_pb_graph_pin(lb_rr_graph, pb_pin, output_pin_rr_type, physical_mode);
+      }
+    }
+  }
+
+  if (true == is_primitive_pb_type(pb_type)) {
+    return; 
+  }
+
+  /* For non-primitive node: 
+   * This pb_graph_node is a logic block or subcluster 
+   * Go recusrively 
+   */
+  t_mode* physical_mode = device_annotation.physical_mode(pb_graph_node->pb_type);
+  for (int ipb_type = 0; ipb_type < physical_mode->num_pb_type_children; ipb_type++) {
+    for (int ipb = 0; ipb < physical_mode->pb_type_children[ipb_type].num_pb; ipb++) {
+      rec_build_physical_lb_rr_edge_for_pb_graph_node(&(pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb_type][ipb]), lb_rr_graph, ext_rr_index, device_annotation);
+    }
+  }
+}
+
+/***************************************************************************************
+ * This functio will create a physical lb_rr_graph for a pb_graph considering physical modes only
+ ***************************************************************************************/
+static 
+LbRRGraph build_lb_type_physical_lb_rr_graph(t_pb_graph_node* pb_graph_head,
+                                             const VprDeviceAnnotation& device_annotation,
+                                             const bool& verbose) {
+  LbRRGraph lb_rr_graph;
+
+  /* TODO: ensure we have an empty lb_rr_graph */
+
+  /* Define the external source, sink, and external interconnect for the routing resource graph of the logic block type */
+  LbRRNodeId ext_source_index = lb_rr_graph.create_node(LB_SOURCE); 
+  LbRRNodeId ext_sink_index = lb_rr_graph.create_node(LB_SINK); 
+  LbRRNodeId ext_rr_index = lb_rr_graph.create_node(LB_INTERMEDIATE); 
+
+  /* Build the main body of lb rr_graph by walking through the pb_graph recursively */
+  /* Build all the regular nodes first */
+  rec_build_physical_lb_rr_node_for_pb_graph_node(pb_graph_head, lb_rr_graph, device_annotation);
+  /* Build all the edges and special node (SOURCE/SINK) */
+  rec_build_physical_lb_rr_edge_for_pb_graph_node(pb_graph_head, lb_rr_graph, ext_rr_index, device_annotation);
+
+  /*******************************************************************************
+   * Build logic block source node
+   *******************************************************************************/
+  t_pb_type* pb_type = pb_graph_head->pb_type;
+
+  /* External source node drives all inputs going into logic block type */
+  lb_rr_graph.set_node_capacity(ext_source_index, pb_type->num_input_pins + pb_type->num_clock_pins);
+
+  for (int iport = 0; iport < pb_graph_head->num_input_ports; iport++) {
+    for (int ipin = 0; ipin < pb_graph_head->num_input_pins[iport]; ipin++) {
+      LbRRNodeId to_node = lb_rr_graph.find_node(LB_INTERMEDIATE, &(pb_graph_head->input_pins[iport][ipin]));
+      VTR_ASSERT(true == lb_rr_graph.valid_node_id(to_node));
+      LbRREdgeId edge = lb_rr_graph.create_edge(ext_source_index, to_node, nullptr);
+      lb_rr_graph.set_edge_intrinsic_cost(edge, 1.);
+    }
+  }
+
+  for (int iport = 0; iport < pb_graph_head->num_clock_ports; iport++) {
+    for (int ipin = 0; ipin < pb_graph_head->num_clock_pins[iport]; ipin++) {
+      LbRRNodeId to_node = lb_rr_graph.find_node(LB_INTERMEDIATE, &(pb_graph_head->clock_pins[iport][ipin]));
+      VTR_ASSERT(true == lb_rr_graph.valid_node_id(to_node));
+      LbRREdgeId edge = lb_rr_graph.create_edge(ext_source_index, to_node, nullptr);
+      lb_rr_graph.set_edge_intrinsic_cost(edge, 1.);
+    }
+  }
+
+  /*******************************************************************************
+   * Build logic block sink node
+   *******************************************************************************/
+
+  /* External sink node driven by all outputs exiting logic block type */
+  lb_rr_graph.set_node_capacity(ext_sink_index, pb_type->num_output_pins);
+
+  /*******************************************************************************
+   * Build node that approximates external interconnect
+   *******************************************************************************/
+
+  /* External rr node that drives all existing logic block input pins and is driven by all outputs exiting logic block type */
+  lb_rr_graph.set_node_capacity(ext_rr_index, pb_type->num_output_pins);
+
+  /* Connect opin of logic block to sink */
+  {
+    LbRREdgeId edge = lb_rr_graph.create_edge(ext_rr_index, ext_sink_index, nullptr);
+    lb_rr_graph.set_edge_intrinsic_cost(edge, 1.);
+  }
+
+  /* Connect opin of logic block to all input and clock pins of logic block type */
+  for (int iport = 0; iport < pb_graph_head->num_input_ports; iport++) {
+    for (int ipin = 0; ipin < pb_graph_head->num_input_pins[iport]; ipin++) {
+      LbRRNodeId to_node = lb_rr_graph.find_node(LB_INTERMEDIATE, &(pb_graph_head->input_pins[iport][ipin]));
+      VTR_ASSERT(true == lb_rr_graph.valid_node_id(to_node));
+      LbRREdgeId edge = lb_rr_graph.create_edge(ext_rr_index, to_node, nullptr);
+      /* set cost high to avoid using external interconnect unless necessary */
+      lb_rr_graph.set_edge_intrinsic_cost(edge, 1000.);
+    }
+  }
+  for (int iport = 0; iport < pb_graph_head->num_clock_ports; iport++) {
+    for (int ipin = 0; ipin < pb_graph_head->num_clock_pins[iport]; ipin++) {
+      LbRRNodeId to_node = lb_rr_graph.find_node(LB_INTERMEDIATE, &(pb_graph_head->clock_pins[iport][ipin]));
+      VTR_ASSERT(true == lb_rr_graph.valid_node_id(to_node));
+      LbRREdgeId edge = lb_rr_graph.create_edge(ext_rr_index, to_node, nullptr);
+      /* set cost high to avoid using external interconnect unless necessary */
+      lb_rr_graph.set_edge_intrinsic_cost(edge, 1000.);
+    }
+  }
+
+  VTR_LOGV(verbose,
+           "\n\tNumber of nodes: %lu\n",
+           lb_rr_graph.nodes().size());
+
+  VTR_LOGV(verbose,
+           "\n\tNumber of edges: %lu\n",
+           lb_rr_graph.edges().size());
+
+  return lb_rr_graph;
+}
+
+/***************************************************************************************
+ * This functio will create physical lb_rr_graph for each pb_graph considering physical modes only
+ * the lb_rr_graph willbe added to device annotation
+ ***************************************************************************************/
+void build_physical_lb_rr_graphs(const DeviceContext& device_ctx,
+                                 VprDeviceAnnotation& device_annotation,
+                                 const bool& verbose) {
+  vtr::ScopedStartFinishTimer timer("Build routing resource graph for the physical implementation of logical tile");
+
+  for (const t_logical_block_type& lb_type : device_ctx.logical_block_types) {
+    /* By pass nullptr for pb_graph head */
+    if (nullptr == lb_type.pb_graph_head) {
+      continue;
+    }
+
+    VTR_LOGV(verbose,
+             "Building routing resource graph for logical tile '%s'...",
+             lb_type.pb_graph_head->pb_type->name);
+
+    const LbRRGraph& lb_rr_graph = build_lb_type_physical_lb_rr_graph(lb_type.pb_graph_head, const_cast<const VprDeviceAnnotation&>(device_annotation), verbose); 
+    device_annotation.add_physical_lb_rr_graph(lb_type.pb_graph_head, lb_rr_graph);
+  }
+
+  VTR_LOGV(verbose, "Done\n");
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/repack/build_physical_lb_rr_graph.h b/openfpga/src/repack/build_physical_lb_rr_graph.h
new file mode 100644
index 000000000..9499a9c1d
--- /dev/null
+++ b/openfpga/src/repack/build_physical_lb_rr_graph.h
@@ -0,0 +1,23 @@
+#ifndef BUILD_PHYSICAL_LB_RR_GRAPH_H
+#define BUILD_PHYSICAL_LB_RR_GRAPH_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "vpr_context.h"
+#include "vpr_device_annotation.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void build_physical_lb_rr_graphs(const DeviceContext& device_ctx,
+                                 VprDeviceAnnotation& device_annotation,
+                                 const bool& verbose);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp
index 2a7dada40..690dbaa23 100644
--- a/openfpga/src/repack/repack.cpp
+++ b/openfpga/src/repack/repack.cpp
@@ -23,7 +23,7 @@ namespace openfpga {
  *  - store the packing results to clustering annotation
  ***************************************************************************************/
 void pack_physical_pbs(const DeviceContext& device_ctx,
-                       VprDeviceAnnotation& device_annotation,
+                       const VprDeviceAnnotation& device_annotation,
                        VprClusteringAnnotation& clustering_annotation,
                        const VprRoutingAnnotation& routing_annotation,
                        const bool& verbose) {
diff --git a/openfpga/src/repack/repack.h b/openfpga/src/repack/repack.h
index 733a7d1ac..2f8acd241 100644
--- a/openfpga/src/repack/repack.h
+++ b/openfpga/src/repack/repack.h
@@ -17,7 +17,7 @@
 namespace openfpga {
 
 void pack_physical_pbs(const DeviceContext& device_ctx,
-                       VprDeviceAnnotation& device_annotation,
+                       const VprDeviceAnnotation& device_annotation,
                        VprClusteringAnnotation& clustering_annotation,
                        const VprRoutingAnnotation& routing_annotation,
                        const bool& verbose);
diff --git a/openfpga/test_script/s298_k6_frac.openfpga b/openfpga/test_script/s298_k6_frac.openfpga
index c01774bd3..3c44fddae 100644
--- a/openfpga/test_script/s298_k6_frac.openfpga
+++ b/openfpga/test_script/s298_k6_frac.openfpga
@@ -5,7 +5,7 @@ vpr ./test_vpr_arch/k6_frac_N10_40nm.xml ./test_blif/s298.blif --write_rr_graph
 read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
 
 # Annotate the OpenFPGA architecture to VPR data base
-link_openfpga_arch
+link_openfpga_arch --verbose
 
 # Check and correct any naming conflicts in the BLIF netlist
 check_netlist_naming_conflict --fix --report ./netlist_renaming.xml

From 6060440b97d40d32392ad62a061e5f3745656ef9 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 17 Feb 2020 21:14:15 -0700
Subject: [PATCH 168/645] fine tuning for the verbose output

---
 openfpga/src/repack/build_physical_lb_rr_graph.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/openfpga/src/repack/build_physical_lb_rr_graph.cpp b/openfpga/src/repack/build_physical_lb_rr_graph.cpp
index 4b7107fbb..aca8cb0d1 100644
--- a/openfpga/src/repack/build_physical_lb_rr_graph.cpp
+++ b/openfpga/src/repack/build_physical_lb_rr_graph.cpp
@@ -369,7 +369,7 @@ LbRRGraph build_lb_type_physical_lb_rr_graph(t_pb_graph_node* pb_graph_head,
            lb_rr_graph.nodes().size());
 
   VTR_LOGV(verbose,
-           "\n\tNumber of edges: %lu\n",
+           "\tNumber of edges: %lu\n",
            lb_rr_graph.edges().size());
 
   return lb_rr_graph;

From ef11482a95f1c951f11cc9323984099453e8ecb4 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 18 Feb 2020 11:36:16 -0700
Subject: [PATCH 169/645] fix dependency error in pack_types header file

---
 vpr/src/pack/pack_types.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/vpr/src/pack/pack_types.h b/vpr/src/pack/pack_types.h
index 794173217..e9b40462f 100644
--- a/vpr/src/pack/pack_types.h
+++ b/vpr/src/pack/pack_types.h
@@ -11,6 +11,7 @@
 #include <vector>
 
 #include "arch_types.h"
+#include "vpr_types.h"
 #include "atom_netlist_fwd.h"
 
 #include "lb_rr_graph_types.h"

From ed25ccc70f21fafac3b5f9cabf2602aa3c426ba2 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 18 Feb 2020 12:00:27 -0700
Subject: [PATCH 170/645] start refactoring lb router in openfpga namespace

---
 openfpga/src/repack/lb_router.cpp | 1498 +++++++++++++++++++++++++++++
 openfpga/src/repack/lb_router.h   |   40 +
 2 files changed, 1538 insertions(+)
 create mode 100644 openfpga/src/repack/lb_router.cpp
 create mode 100644 openfpga/src/repack/lb_router.h

diff --git a/openfpga/src/repack/lb_router.cpp b/openfpga/src/repack/lb_router.cpp
new file mode 100644
index 000000000..dd694fa49
--- /dev/null
+++ b/openfpga/src/repack/lb_router.cpp
@@ -0,0 +1,1498 @@
+/********************************************************************
+ * Intra-logic block router determines if a candidate packing solution (or intermediate solution) can route.
+ * Adapted from original VPR cluster router to the use of LbRRGraph object 
+ *
+ * Global Inputs: Architecture and netlist
+ * Input arguments: clustering info for one cluster (t_pb info)
+ * Working data set: t_routing_data contains intermediate work
+ * Output: Routable? true/false.  If true, store/return the routed solution.
+ *
+ * Routing algorithm used is Pathfinder.
+ *******************************************************************/
+#include <cstdio>
+#include <cstring>
+#include <vector>
+#include <map>
+#include <queue>
+#include <cmath>
+
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+#include "vpr_error.h"
+#include "vpr_types.h"
+#include "echo_files.h"
+
+#include "physical_types.h"
+#include "globals.h"
+#include "atom_netlist.h"
+#include "vpr_utils.h"
+#include "pack_types.h"
+#include "pb_type_graph.h"
+#include "lb_type_rr_graph.h"
+#include "lb_router.h"
+
+/* #define PRINT_INTRA_LB_ROUTE */
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/*****************************************************************************************
+ * Internal data structures
+ ******************************************************************************************/
+
+enum e_commit_remove { RT_COMMIT,
+                       RT_REMOVE };
+
+// TODO: check if this hacky class memory reserve thing is still necessary, if not, then delete
+/* Packing uses a priority queue that requires a large number of elements.  This backdoor
+ * allows me to use a priority queue where I can pre-allocate the # of elements in the underlying container
+ * for efficiency reasons.  Note: Must use vector with this */
+template<class T, class U, class V>
+class reservable_pq : public std::priority_queue<T, U, V> {
+  public:
+    typedef typename std::priority_queue<T>::size_type size_type;
+    reservable_pq(size_type capacity = 0) {
+        reserve(capacity);
+        cur_cap = capacity;
+    }
+    void reserve(size_type capacity) {
+        this->c.reserve(capacity);
+        cur_cap = capacity;
+    }
+    void clear() {
+        this->c.clear();
+        this->c.reserve(cur_cap);
+    }
+
+  private:
+    size_type cur_cap;
+};
+
+/*****************************************************************************************
+ * Internal functions declarations
+ ******************************************************************************************/
+static void free_lb_net_rt(t_lb_trace* lb_trace);
+static void free_lb_trace(t_lb_trace* lb_trace);
+static void add_pin_to_rt_terminals(t_lb_router_data* router_data, const AtomPinId pin_id);
+static void remove_pin_from_rt_terminals(t_lb_router_data* router_data, const AtomPinId pin_id);
+
+static void fix_duplicate_equivalent_pins(t_lb_router_data* router_data);
+
+static void commit_remove_rt(t_lb_trace* rt, t_lb_router_data* router_data, e_commit_remove op, std::unordered_map<const t_pb_graph_node*, const t_mode*>* mode_map, t_mode_selection_status* mode_status);
+static bool is_skip_route_net(t_lb_trace* rt, t_lb_router_data* router_data);
+static void add_source_to_rt(t_lb_router_data* router_data, int inet);
+static void expand_rt(t_lb_router_data* router_data, int inet, reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq, int irt_net);
+static void expand_rt_rec(t_lb_trace* rt, int prev_index, t_explored_node_tb* explored_node_tb, reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq, int irt_net, int explore_id_index);
+static bool try_expand_nodes(t_lb_router_data* router_data,
+                             t_intra_lb_net* lb_net,
+                             t_expansion_node* exp_node,
+                             reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq,
+                             int itarget,
+                             bool try_other_modes,
+                             int verbosity);
+
+static void expand_edges(t_lb_router_data* router_data,
+                         int mode,
+                         int cur_inode,
+                         float cur_cost,
+                         int net_fanout,
+                         reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq);
+
+static void expand_node(t_lb_router_data* router_data, t_expansion_node exp_node, reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq, int net_fanout);
+static void expand_node_all_modes(t_lb_router_data* router_data, t_expansion_node exp_node, reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq, int net_fanout);
+
+static bool add_to_rt(t_lb_trace* rt, int node_index, t_lb_router_data* router_data, int irt_net);
+static bool is_route_success(t_lb_router_data* router_data);
+static t_lb_trace* find_node_in_rt(t_lb_trace* rt, int rt_index);
+static void reset_explored_node_tb(t_lb_router_data* router_data);
+static void save_and_reset_lb_route(t_lb_router_data* router_data);
+static void load_trace_to_pb_route(t_pb_routes& pb_route, const int total_pins, const AtomNetId net_id, const int prev_pin_id, const t_lb_trace* trace);
+
+static std::string describe_lb_type_rr_node(int inode,
+                                            const t_lb_router_data* router_data);
+
+static std::vector<int> find_congested_rr_nodes(const std::vector<t_lb_type_rr_node>& lb_type_graph,
+                                                const t_lb_rr_node_stats* lb_rr_node_stats);
+static std::vector<int> find_incoming_rr_nodes(int dst_node, const t_lb_router_data* router_data);
+static std::string describe_congested_rr_nodes(const std::vector<int>& congested_rr_nodes,
+                                               const t_lb_router_data* router_data);
+/*****************************************************************************************
+ * Debug functions declarations
+ ******************************************************************************************/
+#ifdef PRINT_INTRA_LB_ROUTE
+static void print_route(const char* filename, t_lb_router_data* router_data);
+static void print_route(FILE* fp, t_lb_router_data* router_data);
+#endif
+static void print_trace(FILE* fp, t_lb_trace* trace, t_lb_router_data* router_data);
+
+/*****************************************************************************************
+ * Constructor/Destructor functions
+ ******************************************************************************************/
+
+/**
+ * Build data structures used by intra-logic block router
+ */
+t_lb_router_data* alloc_and_load_router_data(std::vector<t_lb_type_rr_node>* lb_type_graph, t_logical_block_type_ptr type) {
+    t_lb_router_data* router_data = new t_lb_router_data;
+    int size;
+
+    router_data->lb_type_graph = lb_type_graph;
+    size = router_data->lb_type_graph->size();
+    router_data->lb_rr_node_stats = new t_lb_rr_node_stats[size];
+    router_data->explored_node_tb = new t_explored_node_tb[size];
+    router_data->intra_lb_nets = new std::vector<t_intra_lb_net>;
+    router_data->atoms_added = new std::map<AtomBlockId, bool>;
+    router_data->lb_type = type;
+
+    return router_data;
+}
+
+/* free data used by router */
+void free_router_data(t_lb_router_data* router_data) {
+    if (router_data != nullptr && router_data->lb_type_graph != nullptr) {
+        delete[] router_data->lb_rr_node_stats;
+        router_data->lb_rr_node_stats = nullptr;
+        delete[] router_data->explored_node_tb;
+        router_data->explored_node_tb = nullptr;
+        router_data->lb_type_graph = nullptr;
+        delete router_data->atoms_added;
+        router_data->atoms_added = nullptr;
+        free_intra_lb_nets(router_data->intra_lb_nets);
+        free_intra_lb_nets(router_data->saved_lb_nets);
+        router_data->intra_lb_nets = nullptr;
+        delete router_data;
+    }
+}
+
+static bool route_has_conflict(t_lb_trace* rt, t_lb_router_data* router_data) {
+    std::vector<t_lb_type_rr_node>& lb_type_graph = *router_data->lb_type_graph;
+
+    int cur_mode = -1;
+    for (unsigned int i = 0; i < rt->next_nodes.size(); i++) {
+        int new_mode = get_lb_type_rr_graph_edge_mode(lb_type_graph,
+                                                      rt->current_node, rt->next_nodes[i].current_node);
+        if (cur_mode != -1 && cur_mode != new_mode) {
+            return true;
+        }
+        if (route_has_conflict(&rt->next_nodes[i], router_data) == true) {
+            return true;
+        }
+        cur_mode = new_mode;
+    }
+
+    return false;
+}
+
+// Check one edge for mode conflict.
+static bool check_edge_for_route_conflicts(std::unordered_map<const t_pb_graph_node*, const t_mode*>* mode_map,
+                                           const t_pb_graph_pin* driver_pin,
+                                           const t_pb_graph_pin* pin) {
+    if (driver_pin == nullptr) {
+        return false;
+    }
+
+    // Only check pins that are OUT_PORTs.
+    if (pin == nullptr || pin->port == nullptr || pin->port->type != OUT_PORT) {
+        return false;
+    }
+    VTR_ASSERT(!pin->port->is_clock);
+
+    auto* pb_graph_node = pin->parent_node;
+    VTR_ASSERT(pb_graph_node->pb_type == pin->port->parent_pb_type);
+
+    const t_pb_graph_edge* edge = get_edge_between_pins(driver_pin, pin);
+    VTR_ASSERT(edge != nullptr);
+
+    auto mode_of_edge = edge->interconnect->parent_mode_index;
+    auto* mode = &pb_graph_node->pb_type->modes[mode_of_edge];
+
+    auto result = mode_map->insert(std::make_pair(pb_graph_node, mode));
+    if (!result.second) {
+        if (result.first->second != mode) {
+            std::cout << vtr::string_fmt("Differing modes for block.  Got %s mode, while previously was %s for interconnect %s.",
+                                         mode->name, result.first->second->name,
+                                         edge->interconnect->name)
+                      << std::endl;
+
+            // The illegal mode is added to the pb_graph_node as it resulted in a conflict during atom-to-atom routing. This mode cannot be used in the consequent cluster
+            // generation try.
+            if (std::find(pb_graph_node->illegal_modes.begin(), pb_graph_node->illegal_modes.end(), result.first->second->index) == pb_graph_node->illegal_modes.end()) {
+                pb_graph_node->illegal_modes.push_back(result.first->second->index);
+            }
+
+            // If the number of illegal modes equals the number of available mode for a specific pb_graph_node it means that no cluster can be generated. This resuts
+            // in a fatal error.
+            if ((int)pb_graph_node->illegal_modes.size() >= pb_graph_node->pb_type->num_modes) {
+                VPR_FATAL_ERROR(VPR_ERROR_PACK, "There are no more available modes to be used. Routing Failed!");
+            }
+
+            return true;
+        }
+    }
+
+    return false;
+}
+
+/*****************************************************************************************
+ * Routing Functions
+ ******************************************************************************************/
+
+/* Add pins of netlist atom to to current routing drivers/targets */
+void add_atom_as_target(t_lb_router_data* router_data, const AtomBlockId blk_id) {
+    const t_pb* pb;
+    auto& atom_ctx = g_vpr_ctx.atom();
+
+    std::map<AtomBlockId, bool>& atoms_added = *router_data->atoms_added;
+
+    if (atoms_added.count(blk_id) > 0) {
+        VPR_FATAL_ERROR(VPR_ERROR_PACK, "Atom %s added twice to router\n", atom_ctx.nlist.block_name(blk_id).c_str());
+    }
+
+    pb = atom_ctx.lookup.atom_pb(blk_id);
+
+    VTR_ASSERT(pb);
+
+    atoms_added[blk_id] = true;
+
+    set_reset_pb_modes(router_data, pb, true);
+
+    for (auto pin_id : atom_ctx.nlist.block_pins(blk_id)) {
+        add_pin_to_rt_terminals(router_data, pin_id);
+    }
+
+    fix_duplicate_equivalent_pins(router_data);
+}
+
+/* Remove pins of netlist atom from current routing drivers/targets */
+void remove_atom_from_target(t_lb_router_data* router_data, const AtomBlockId blk_id) {
+    auto& atom_ctx = g_vpr_ctx.atom();
+
+    std::map<AtomBlockId, bool>& atoms_added = *router_data->atoms_added;
+
+    const t_pb* pb = atom_ctx.lookup.atom_pb(blk_id);
+
+    if (atoms_added.count(blk_id) == 0) {
+        return;
+    }
+
+    set_reset_pb_modes(router_data, pb, false);
+
+    for (auto pin_id : atom_ctx.nlist.block_pins(blk_id)) {
+        remove_pin_from_rt_terminals(router_data, pin_id);
+    }
+
+    atoms_added.erase(blk_id);
+}
+
+/* Set/Reset mode of rr nodes to the pb used.  If set == true, then set all modes of the rr nodes affected by pb to the mode of the pb.
+ * Set all modes related to pb to 0 otherwise */
+void set_reset_pb_modes(t_lb_router_data* router_data, const t_pb* pb, const bool set) {
+    t_pb_type* pb_type;
+    t_pb_graph_node* pb_graph_node;
+    int mode = pb->mode;
+    int inode;
+
+    VTR_ASSERT(mode >= 0);
+
+    pb_graph_node = pb->pb_graph_node;
+    pb_type = pb_graph_node->pb_type;
+
+    /* Input and clock pin modes are based on current pb mode */
+    for (int iport = 0; iport < pb_graph_node->num_input_ports; iport++) {
+        for (int ipin = 0; ipin < pb_graph_node->num_input_pins[iport]; ipin++) {
+            inode = pb_graph_node->input_pins[iport][ipin].pin_count_in_cluster;
+            router_data->lb_rr_node_stats[inode].mode = (set == true) ? mode : -1;
+        }
+    }
+    for (int iport = 0; iport < pb_graph_node->num_clock_ports; iport++) {
+        for (int ipin = 0; ipin < pb_graph_node->num_clock_pins[iport]; ipin++) {
+            inode = pb_graph_node->clock_pins[iport][ipin].pin_count_in_cluster;
+            router_data->lb_rr_node_stats[inode].mode = (set == true) ? mode : -1;
+        }
+    }
+
+    /* Output pin modes are based on parent pb, so set children to use new mode
+     * Output pin of top-level logic block is also set to mode 0
+     */
+    if (pb_type->num_modes != 0) {
+        for (int ichild_type = 0; ichild_type < pb_type->modes[mode].num_pb_type_children; ichild_type++) {
+            for (int ichild = 0; ichild < pb_type->modes[mode].pb_type_children[ichild_type].num_pb; ichild++) {
+                t_pb_graph_node* child_pb_graph_node = &pb_graph_node->child_pb_graph_nodes[mode][ichild_type][ichild];
+                for (int iport = 0; iport < child_pb_graph_node->num_output_ports; iport++) {
+                    for (int ipin = 0; ipin < child_pb_graph_node->num_output_pins[iport]; ipin++) {
+                        inode = child_pb_graph_node->output_pins[iport][ipin].pin_count_in_cluster;
+                        router_data->lb_rr_node_stats[inode].mode = (set == true) ? mode : -1;
+                    }
+                }
+            }
+        }
+    }
+}
+
+/* Expand all the nodes for a given lb_net */
+static bool try_expand_nodes(t_lb_router_data* router_data,
+                             t_intra_lb_net* lb_net,
+                             t_expansion_node* exp_node,
+                             reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq,
+                             int itarget,
+                             bool try_other_modes,
+                             int verbosity) {
+    bool is_impossible = false;
+
+    do {
+        if (pq.empty()) {
+            /* No connection possible */
+            is_impossible = true;
+
+            if (verbosity > 3) {
+                //Print detailed debug info
+                auto& atom_nlist = g_vpr_ctx.atom().nlist;
+                AtomNetId net_id = lb_net->atom_net_id;
+                AtomPinId driver_pin = lb_net->atom_pins[0];
+                AtomPinId sink_pin = lb_net->atom_pins[itarget];
+                int driver_rr_node = lb_net->terminals[0];
+                int sink_rr_node = lb_net->terminals[itarget];
+
+                VTR_LOG("\t\t\tNo possible routing path from %s to %s: needed for net '%s' from net pin '%s'",
+                        describe_lb_type_rr_node(driver_rr_node, router_data).c_str(),
+                        describe_lb_type_rr_node(sink_rr_node, router_data).c_str(),
+                        atom_nlist.net_name(net_id).c_str(),
+                        atom_nlist.pin_name(driver_pin).c_str());
+                VTR_LOGV(sink_pin, " to net pin '%s'", atom_nlist.pin_name(sink_pin).c_str());
+                VTR_LOG("\n");
+            }
+        } else {
+            *exp_node = pq.top();
+            pq.pop();
+            int exp_inode = exp_node->node_index;
+
+            if (router_data->explored_node_tb[exp_inode].explored_id != router_data->explore_id_index) {
+                /* First time node is popped implies path to this node is the lowest cost.
+                 * If the node is popped a second time, then the path to that node is higher than this path so
+                 * ignore.
+                 */
+                router_data->explored_node_tb[exp_inode].explored_id = router_data->explore_id_index;
+                router_data->explored_node_tb[exp_inode].prev_index = exp_node->prev_index;
+                if (exp_inode != lb_net->terminals[itarget]) {
+                    if (!try_other_modes) {
+                        expand_node(router_data, *exp_node, pq, lb_net->terminals.size() - 1);
+                    } else {
+                        expand_node_all_modes(router_data, *exp_node, pq, lb_net->terminals.size() - 1);
+                    }
+                }
+            }
+        }
+    } while (exp_node->node_index != lb_net->terminals[itarget] && !is_impossible);
+
+    return is_impossible;
+}
+
+/* Attempt to route routing driver/targets on the current architecture
+ * Follows pathfinder negotiated congestion algorithm
+ */
+bool try_intra_lb_route(t_lb_router_data* router_data,
+                        int verbosity,
+                        t_mode_selection_status* mode_status) {
+    std::vector<t_intra_lb_net>& lb_nets = *router_data->intra_lb_nets;
+    std::vector<t_lb_type_rr_node>& lb_type_graph = *router_data->lb_type_graph;
+    bool is_routed = false;
+    bool is_impossible = false;
+
+    mode_status->is_mode_conflict = false;
+    mode_status->try_expand_all_modes = false;
+
+    t_expansion_node exp_node;
+
+    /* Stores state info during route */
+    reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node> pq;
+
+    reset_explored_node_tb(router_data);
+
+    /* Reset current routing */
+    for (unsigned int inet = 0; inet < lb_nets.size(); inet++) {
+        free_lb_net_rt(lb_nets[inet].rt_tree);
+        lb_nets[inet].rt_tree = nullptr;
+    }
+    for (unsigned int inode = 0; inode < lb_type_graph.size(); inode++) {
+        router_data->lb_rr_node_stats[inode].historical_usage = 0;
+        router_data->lb_rr_node_stats[inode].occ = 0;
+    }
+
+    std::unordered_map<const t_pb_graph_node*, const t_mode*> mode_map;
+
+    /*	Iteratively remove congestion until a successful route is found.
+     * Cap the total number of iterations tried so that if a solution does not exist, then the router won't run indefinitely */
+    router_data->pres_con_fac = router_data->params.pres_fac;
+    for (int iter = 0; iter < router_data->params.max_iterations && !is_routed && !is_impossible; iter++) {
+        unsigned int inet;
+        /* Iterate across all nets internal to logic block */
+        for (inet = 0; inet < lb_nets.size() && !is_impossible; inet++) {
+            int idx = inet;
+            if (is_skip_route_net(lb_nets[idx].rt_tree, router_data)) {
+                continue;
+            }
+            commit_remove_rt(lb_nets[idx].rt_tree, router_data, RT_REMOVE, &mode_map, mode_status);
+            free_lb_net_rt(lb_nets[idx].rt_tree);
+            lb_nets[idx].rt_tree = nullptr;
+            add_source_to_rt(router_data, idx);
+
+            /* Route each sink of net */
+            for (unsigned int itarget = 1; itarget < lb_nets[idx].terminals.size() && !is_impossible; itarget++) {
+                pq.clear();
+                /* Get lowest cost next node, repeat until a path is found or if it is impossible to route */
+
+                expand_rt(router_data, idx, pq, idx);
+
+                is_impossible = try_expand_nodes(router_data, &lb_nets[idx], &exp_node, pq, itarget, mode_status->expand_all_modes, verbosity);
+
+                if (is_impossible && !mode_status->expand_all_modes) {
+                    mode_status->try_expand_all_modes = true;
+                    mode_status->expand_all_modes = true;
+                    break;
+                }
+
+                if (exp_node.node_index == lb_nets[idx].terminals[itarget]) {
+                    /* Net terminal is routed, add this to the route tree, clear data structures, and keep going */
+                    is_impossible = add_to_rt(lb_nets[idx].rt_tree, exp_node.node_index, router_data, idx);
+                }
+
+                if (verbosity > 5) {
+                    VTR_LOG("Routing finished\n");
+                    VTR_LOG("\tS");
+                    print_trace(stdout, lb_nets[idx].rt_tree, router_data);
+                    VTR_LOG("\n");
+                }
+
+                if (is_impossible) {
+                    VTR_LOG("Routing was impossible!\n");
+                } else if (mode_status->expand_all_modes) {
+                    is_impossible = route_has_conflict(lb_nets[idx].rt_tree, router_data);
+                    if (is_impossible) {
+                        VTR_LOG("Routing was impossible due to modes!\n");
+                    }
+                }
+
+                router_data->explore_id_index++;
+                if (router_data->explore_id_index > 2000000000) {
+                    /* overflow protection */
+                    for (unsigned int id = 0; id < lb_type_graph.size(); id++) {
+                        router_data->explored_node_tb[id].explored_id = OPEN;
+                        router_data->explored_node_tb[id].enqueue_id = OPEN;
+                        router_data->explore_id_index = 1;
+                    }
+                }
+            }
+
+            if (!is_impossible) {
+                commit_remove_rt(lb_nets[idx].rt_tree, router_data, RT_COMMIT, &mode_map, mode_status);
+                if (mode_status->is_mode_conflict) {
+                    is_impossible = true;
+                }
+            }
+        }
+
+        if (!is_impossible) {
+            is_routed = is_route_success(router_data);
+        } else {
+            --inet;
+            auto& atom_ctx = g_vpr_ctx.atom();
+            VTR_LOGV(verbosity < 3, "Net '%s' is impossible to route within proposed %s cluster\n",
+                     atom_ctx.nlist.net_name(lb_nets[inet].atom_net_id).c_str(), router_data->lb_type->name);
+            is_routed = false;
+        }
+        router_data->pres_con_fac *= router_data->params.pres_fac_mult;
+    }
+
+    if (is_routed) {
+        save_and_reset_lb_route(router_data);
+    } else {
+        //Unroutable
+#ifdef PRINT_INTRA_LB_ROUTE
+        print_route(getEchoFileName(E_ECHO_INTRA_LB_FAILED_ROUTE), router_data);
+#endif
+
+        if (verbosity > 3 && !is_impossible) {
+            //Report the congested nodes and associated nets
+            auto congested_rr_nodes = find_congested_rr_nodes(lb_type_graph, router_data->lb_rr_node_stats);
+            if (!congested_rr_nodes.empty()) {
+                VTR_LOG("%s\n", describe_congested_rr_nodes(congested_rr_nodes, router_data).c_str());
+            }
+        }
+
+        //Clean-up
+        for (unsigned int inet = 0; inet < lb_nets.size(); inet++) {
+            free_lb_net_rt(lb_nets[inet].rt_tree);
+            lb_nets[inet].rt_tree = nullptr;
+        }
+    }
+    return is_routed;
+}
+
+/*****************************************************************************************
+ * Accessor Functions
+ ******************************************************************************************/
+
+/* Creates an array [0..num_pb_graph_pins-1] lookup for intra-logic block routing.  Given pb_graph_pin id for clb, lookup atom net that uses that pin.
+ * If pin is not used, stores OPEN at that pin location */
+t_pb_routes alloc_and_load_pb_route(const std::vector<t_intra_lb_net>* intra_lb_nets, t_pb_graph_node* pb_graph_head) {
+    const std::vector<t_intra_lb_net>& lb_nets = *intra_lb_nets;
+    int total_pins = pb_graph_head->total_pb_pins;
+    t_pb_routes pb_route;
+
+    for (int inet = 0; inet < (int)lb_nets.size(); inet++) {
+        load_trace_to_pb_route(pb_route, total_pins, lb_nets[inet].atom_net_id, OPEN, lb_nets[inet].rt_tree);
+    }
+
+    return pb_route;
+}
+
+/* Free pin-to-atomic_net array lookup */
+void free_pb_route(t_pb_route* pb_route) {
+    if (pb_route != nullptr) {
+        delete[] pb_route;
+    }
+}
+
+void free_intra_lb_nets(std::vector<t_intra_lb_net>* intra_lb_nets) {
+    if (intra_lb_nets == nullptr) {
+        return;
+    }
+    std::vector<t_intra_lb_net>& lb_nets = *intra_lb_nets;
+    for (unsigned int i = 0; i < lb_nets.size(); i++) {
+        lb_nets[i].terminals.clear();
+        free_lb_net_rt(lb_nets[i].rt_tree);
+        lb_nets[i].rt_tree = nullptr;
+    }
+    delete intra_lb_nets;
+}
+
+/***************************************************************************
+ * Internal Functions
+ ****************************************************************************/
+
+/* Recurse through route tree trace to populate pb pin to atom net lookup array */
+static void load_trace_to_pb_route(t_pb_routes& pb_route, const int total_pins, const AtomNetId net_id, const int prev_pin_id, const t_lb_trace* trace) {
+    int ipin = trace->current_node;
+    int driver_pb_pin_id = prev_pin_id;
+    int cur_pin_id = OPEN;
+    if (ipin < total_pins) {
+        /* This routing node corresponds with a pin.  This node is virtual (ie. sink or source node) */
+        cur_pin_id = ipin;
+        if (!pb_route.count(ipin)) {
+            pb_route.insert(std::make_pair(cur_pin_id, t_pb_route()));
+            pb_route[cur_pin_id].atom_net_id = net_id;
+            pb_route[cur_pin_id].driver_pb_pin_id = driver_pb_pin_id;
+        } else {
+            VTR_ASSERT(pb_route[cur_pin_id].atom_net_id == net_id);
+        }
+    }
+    for (int itrace = 0; itrace < (int)trace->next_nodes.size(); itrace++) {
+        load_trace_to_pb_route(pb_route, total_pins, net_id, cur_pin_id, &trace->next_nodes[itrace]);
+    }
+}
+
+/* Free route tree for intra-logic block routing */
+static void free_lb_net_rt(t_lb_trace* lb_trace) {
+    if (lb_trace != nullptr) {
+        for (unsigned int i = 0; i < lb_trace->next_nodes.size(); i++) {
+            free_lb_trace(&lb_trace->next_nodes[i]);
+        }
+        lb_trace->next_nodes.clear();
+        delete lb_trace;
+    }
+}
+
+/* Free trace for intra-logic block routing */
+static void free_lb_trace(t_lb_trace* lb_trace) {
+    if (lb_trace != nullptr) {
+        for (unsigned int i = 0; i < lb_trace->next_nodes.size(); i++) {
+            free_lb_trace(&lb_trace->next_nodes[i]);
+        }
+        lb_trace->next_nodes.clear();
+    }
+}
+
+/* Given a pin of a net, assign route tree terminals for it
+ * Assumes that pin is not already assigned
+ */
+static void add_pin_to_rt_terminals(t_lb_router_data* router_data, const AtomPinId pin_id) {
+    std::vector<t_intra_lb_net>& lb_nets = *router_data->intra_lb_nets;
+    std::vector<t_lb_type_rr_node>& lb_type_graph = *router_data->lb_type_graph;
+    t_logical_block_type_ptr lb_type = router_data->lb_type;
+    bool found = false;
+    unsigned int ipos;
+    auto& atom_ctx = g_vpr_ctx.atom();
+
+    const t_pb_graph_pin* pb_graph_pin = find_pb_graph_pin(atom_ctx.nlist, atom_ctx.lookup, pin_id);
+    VTR_ASSERT(pb_graph_pin);
+
+    AtomPortId port_id = atom_ctx.nlist.pin_port(pin_id);
+    AtomNetId net_id = atom_ctx.nlist.pin_net(pin_id);
+
+    if (!net_id) {
+        //No net connected to this pin, so nothing to route
+        return;
+    }
+
+    /* Find if current net is in route tree, if not, then add to rt.
+     * Code assumes that # of nets in cluster is small so a linear search through
+     * vector is faster than using more complex data structures
+     */
+    for (ipos = 0; ipos < lb_nets.size(); ipos++) {
+        if (lb_nets[ipos].atom_net_id == net_id) {
+            found = true;
+            break;
+        }
+    }
+    if (found == false) {
+        struct t_intra_lb_net new_net;
+
+        new_net.atom_net_id = net_id;
+
+        ipos = lb_nets.size();
+        lb_nets.push_back(new_net);
+    }
+    VTR_ASSERT(lb_nets[ipos].atom_net_id == net_id);
+    VTR_ASSERT(lb_nets[ipos].atom_pins.size() == lb_nets[ipos].terminals.size());
+
+    /*
+     * Determine whether or not this is a new intra lb net, if yes, then add to list of intra lb nets
+     */
+    if (lb_nets[ipos].terminals.empty()) {
+        /* Add terminals */
+
+        //Default assumption is that the source is outside the current cluster (will be overriden later if required)
+        int source_terminal = get_lb_type_rr_graph_ext_source_index(lb_type);
+        lb_nets[ipos].terminals.push_back(source_terminal);
+
+        AtomPinId net_driver_pin_id = atom_ctx.nlist.net_driver(net_id);
+        lb_nets[ipos].atom_pins.push_back(net_driver_pin_id);
+
+        VTR_ASSERT_MSG(lb_type_graph[lb_nets[ipos].terminals[0]].type == LB_SOURCE, "Driver must be a source");
+    }
+
+    VTR_ASSERT(lb_nets[ipos].atom_pins.size() == lb_nets[ipos].terminals.size());
+
+    if (atom_ctx.nlist.port_type(port_id) == PortType::OUTPUT) {
+        //The current pin is the net driver, overwrite the default driver at index 0
+        VTR_ASSERT_MSG(lb_nets[ipos].terminals[0] == get_lb_type_rr_graph_ext_source_index(lb_type), "Default driver must be external source");
+
+        VTR_ASSERT(atom_ctx.nlist.pin_type(pin_id) == PinType::DRIVER);
+
+        //Override the default since this is the driver, and it is within the cluster
+        lb_nets[ipos].terminals[0] = pb_graph_pin->pin_count_in_cluster;
+        lb_nets[ipos].atom_pins[0] = pin_id;
+
+        VTR_ASSERT_MSG(lb_type_graph[lb_nets[ipos].terminals[0]].type == LB_SOURCE, "Driver must be a source");
+
+        int sink_terminal = OPEN;
+        if (lb_nets[ipos].terminals.size() < atom_ctx.nlist.net_pins(net_id).size()) {
+            //Not all of the pins are within the cluster
+            if (lb_nets[ipos].terminals.size() == 1) {
+                //Only the source has been specified so far, must add cluster-external sink
+                sink_terminal = get_lb_type_rr_graph_ext_sink_index(lb_type);
+                lb_nets[ipos].terminals.push_back(sink_terminal);
+                lb_nets[ipos].atom_pins.push_back(AtomPinId::INVALID());
+            } else {
+                VTR_ASSERT(lb_nets[ipos].terminals.size() > 1);
+
+                //TODO: Figure out why we swap terminal 1 here (although it appears to work correctly,
+                //      it's not clear why this is needed...)
+
+                //Move current terminal 1 to end
+                sink_terminal = lb_nets[ipos].terminals[1];
+                AtomPinId sink_atom_pin = lb_nets[ipos].atom_pins[1];
+                lb_nets[ipos].terminals.push_back(sink_terminal);
+                lb_nets[ipos].atom_pins.push_back(sink_atom_pin);
+
+                //Create external sink at terminal 1
+                sink_terminal = get_lb_type_rr_graph_ext_sink_index(lb_type);
+                lb_nets[ipos].terminals[1] = sink_terminal;
+                lb_nets[ipos].atom_pins[1] = AtomPinId::INVALID();
+            }
+            VTR_ASSERT(lb_type_graph[lb_nets[ipos].terminals[1]].type == LB_SINK);
+        }
+    } else {
+        //This is an input to a primitive
+        VTR_ASSERT(atom_ctx.nlist.port_type(port_id) == PortType::INPUT
+                   || atom_ctx.nlist.port_type(port_id) == PortType::CLOCK);
+        VTR_ASSERT(atom_ctx.nlist.pin_type(pin_id) == PinType::SINK);
+
+        //Get the rr node index associated with the pin
+        int pin_index = pb_graph_pin->pin_count_in_cluster;
+        VTR_ASSERT(lb_type_graph[pin_index].num_modes == 1);
+        VTR_ASSERT(lb_type_graph[pin_index].num_fanout[0] == 1);
+
+        /* We actually route to the sink (to handle logically equivalent pins).
+         * The sink is one past the primitive input pin */
+        int sink_index = lb_type_graph[pin_index].outedges[0][0].node_index;
+        VTR_ASSERT(lb_type_graph[sink_index].type == LB_SINK);
+
+        if (lb_nets[ipos].terminals.size() == atom_ctx.nlist.net_pins(net_id).size() && lb_nets[ipos].terminals[1] == get_lb_type_rr_graph_ext_sink_index(lb_type)) {
+            /* If all sinks of net are all contained in the logic block, then the net does
+             * not need to route out of the logic block, so can replace the external sink
+             * with this last sink terminal */
+            lb_nets[ipos].terminals[1] = sink_index;
+            lb_nets[ipos].atom_pins[1] = pin_id;
+        } else {
+            //Add as a regular sink
+            lb_nets[ipos].terminals.push_back(sink_index);
+            lb_nets[ipos].atom_pins.push_back(pin_id);
+        }
+    }
+    VTR_ASSERT(lb_nets[ipos].atom_pins.size() == lb_nets[ipos].terminals.size());
+
+    int num_lb_terminals = lb_nets[ipos].terminals.size();
+    VTR_ASSERT(num_lb_terminals <= (int)atom_ctx.nlist.net_pins(net_id).size());
+    VTR_ASSERT(num_lb_terminals >= 0);
+
+#ifdef VTR_ASSERT_SAFE_ENABLED
+    //Sanity checks
+    int num_extern_sources = 0;
+    int num_extern_sinks = 0;
+    for (size_t iterm = 0; iterm < lb_nets[ipos].terminals.size(); ++iterm) {
+        int inode = lb_nets[ipos].terminals[iterm];
+        AtomPinId atom_pin = lb_nets[ipos].atom_pins[iterm];
+        if (iterm == 0) {
+            //Net driver
+            VTR_ASSERT_SAFE_MSG(lb_type_graph[inode].type == LB_SOURCE, "Driver must be a source RR node");
+            VTR_ASSERT_SAFE_MSG(atom_pin, "Driver have an associated atom pin");
+            VTR_ASSERT_SAFE_MSG(atom_ctx.nlist.pin_type(atom_pin) == PinType::DRIVER, "Source RR must be associated with a driver pin in atom netlist");
+            if (inode == get_lb_type_rr_graph_ext_source_index(lb_type)) {
+                ++num_extern_sources;
+            }
+        } else {
+            //Net sink
+            VTR_ASSERT_SAFE_MSG(lb_type_graph[inode].type == LB_SINK, "Non-driver must be a sink");
+
+            if (inode == get_lb_type_rr_graph_ext_sink_index(lb_type)) {
+                //External sink may have multiple potentially matching atom pins, so it's atom pin is left invalid
+                VTR_ASSERT_SAFE_MSG(!atom_pin, "Cluster external sink should have no valid atom pin");
+                ++num_extern_sinks;
+            } else {
+                VTR_ASSERT_SAFE_MSG(atom_pin, "Intra-cluster sink must have an associated atom pin");
+                VTR_ASSERT_SAFE_MSG(atom_ctx.nlist.pin_type(atom_pin) == PinType::SINK, "Intra-cluster Sink RR must be associated with a sink pin in atom netlist");
+            }
+        }
+    }
+    VTR_ASSERT_SAFE_MSG(num_extern_sinks >= 0 && num_extern_sinks <= 1, "Net must have at most one external sink");
+    VTR_ASSERT_SAFE_MSG(num_extern_sources >= 0 && num_extern_sources <= 1, "Net must have at most one external source");
+#endif
+}
+
+/* Given a pin of a net, remove route tree terminals from it
+ */
+static void remove_pin_from_rt_terminals(t_lb_router_data* router_data, const AtomPinId pin_id) {
+    std::vector<t_intra_lb_net>& lb_nets = *router_data->intra_lb_nets;
+    std::vector<t_lb_type_rr_node>& lb_type_graph = *router_data->lb_type_graph;
+    t_logical_block_type_ptr lb_type = router_data->lb_type;
+    bool found = false;
+    unsigned int ipos;
+    auto& atom_ctx = g_vpr_ctx.atom();
+
+    const t_pb_graph_pin* pb_graph_pin = find_pb_graph_pin(atom_ctx.nlist, atom_ctx.lookup, pin_id);
+
+    AtomPortId port_id = atom_ctx.nlist.pin_port(pin_id);
+    AtomNetId net_id = atom_ctx.nlist.pin_net(pin_id);
+
+    if (!net_id) {
+        /* This is not a valid net */
+        return;
+    }
+
+    /* Find current net in route tree
+     * Code assumes that # of nets in cluster is small so a linear search through vector is faster than using more complex data structures
+     */
+    for (ipos = 0; ipos < lb_nets.size(); ipos++) {
+        if (lb_nets[ipos].atom_net_id == net_id) {
+            found = true;
+            break;
+        }
+    }
+    VTR_ASSERT(found == true);
+    VTR_ASSERT(lb_nets[ipos].atom_net_id == net_id);
+
+    VTR_ASSERT(lb_nets[ipos].atom_pins.size() == lb_nets[ipos].terminals.size());
+
+    auto port_type = atom_ctx.nlist.port_type(port_id);
+    if (port_type == PortType::OUTPUT) {
+        /* Net driver pin takes 0th position in terminals */
+        int sink_terminal;
+        VTR_ASSERT(lb_nets[ipos].terminals[0] == pb_graph_pin->pin_count_in_cluster);
+        lb_nets[ipos].terminals[0] = get_lb_type_rr_graph_ext_source_index(lb_type);
+
+        /* source terminal is now coming from outside logic block, do not need to route signal out of logic block */
+        sink_terminal = get_lb_type_rr_graph_ext_sink_index(lb_type);
+        if (lb_nets[ipos].terminals[1] == sink_terminal) {
+            lb_nets[ipos].terminals[1] = lb_nets[ipos].terminals.back();
+            lb_nets[ipos].terminals.pop_back();
+
+            lb_nets[ipos].atom_pins[1] = lb_nets[ipos].atom_pins.back();
+            lb_nets[ipos].atom_pins.pop_back();
+        }
+    } else {
+        VTR_ASSERT(port_type == PortType::INPUT || port_type == PortType::CLOCK);
+
+        /* Remove sink from list of terminals */
+        int pin_index = pb_graph_pin->pin_count_in_cluster;
+        unsigned int iterm;
+
+        VTR_ASSERT(lb_type_graph[pin_index].num_modes == 1);
+        VTR_ASSERT(lb_type_graph[pin_index].num_fanout[0] == 1);
+        int sink_index = lb_type_graph[pin_index].outedges[0][0].node_index;
+        VTR_ASSERT(lb_type_graph[sink_index].type == LB_SINK);
+
+        int target_index = -1;
+        //Search for the sink
+        found = false;
+        for (iterm = 0; iterm < lb_nets[ipos].terminals.size(); iterm++) {
+            if (lb_nets[ipos].terminals[iterm] == sink_index) {
+                target_index = sink_index;
+                found = true;
+                break;
+            }
+        }
+        if (!found) {
+            //Search for the pin
+            found = false;
+            for (iterm = 0; iterm < lb_nets[ipos].terminals.size(); iterm++) {
+                if (lb_nets[ipos].terminals[iterm] == pin_index) {
+                    target_index = pin_index;
+                    found = true;
+                    break;
+                }
+            }
+        }
+        VTR_ASSERT(found == true);
+        VTR_ASSERT(lb_nets[ipos].terminals[iterm] == target_index);
+        VTR_ASSERT(iterm > 0);
+
+        /* Drop terminal from list */
+        lb_nets[ipos].terminals[iterm] = lb_nets[ipos].terminals.back();
+        lb_nets[ipos].terminals.pop_back();
+
+        lb_nets[ipos].atom_pins[iterm] = lb_nets[ipos].atom_pins.back();
+        lb_nets[ipos].atom_pins.pop_back();
+
+        if (lb_nets[ipos].terminals.size() == 1 && lb_nets[ipos].terminals[0] != get_lb_type_rr_graph_ext_source_index(lb_type)) {
+            /* The removed sink must be driven by an atom found in the cluster, add in special sink outside of cluster to represent this */
+            lb_nets[ipos].terminals.push_back(get_lb_type_rr_graph_ext_sink_index(lb_type));
+            lb_nets[ipos].atom_pins.push_back(AtomPinId::INVALID());
+        }
+
+        if (lb_nets[ipos].terminals.size() > 1 && lb_nets[ipos].terminals[1] != get_lb_type_rr_graph_ext_sink_index(lb_type) && lb_nets[ipos].terminals[0] != get_lb_type_rr_graph_ext_source_index(lb_type)) {
+            /* The removed sink must be driven by an atom found in the cluster, add in special sink outside of cluster to represent this */
+            int terminal = lb_nets[ipos].terminals[1];
+            lb_nets[ipos].terminals.push_back(terminal);
+            lb_nets[ipos].terminals[1] = get_lb_type_rr_graph_ext_sink_index(lb_type);
+
+            AtomPinId pin = lb_nets[ipos].atom_pins[1];
+            lb_nets[ipos].atom_pins.push_back(pin);
+            lb_nets[ipos].atom_pins[1] = AtomPinId::INVALID();
+        }
+    }
+    VTR_ASSERT(lb_nets[ipos].atom_pins.size() == lb_nets[ipos].terminals.size());
+
+    if (lb_nets[ipos].terminals.size() == 1 && lb_nets[ipos].terminals[0] == get_lb_type_rr_graph_ext_source_index(lb_type)) {
+        /* This net is not routed, remove from list of nets in lb */
+        lb_nets[ipos] = lb_nets.back();
+        lb_nets.pop_back();
+    }
+}
+
+//It is possible that a net may connect multiple times to a logically equivalent set of primitive pins.
+//The cluster router will only route one connection for a particular net to the common sink of the
+//equivalent pins.
+//
+//To work around this, we fix all but one of these duplicate connections to route to specific pins,
+//(instead of the common sink). This ensures a legal routing is produced and that the duplicate pins
+//are not 'missing' in the clustered netlist.
+static void fix_duplicate_equivalent_pins(t_lb_router_data* router_data) {
+    auto& atom_ctx = g_vpr_ctx.atom();
+
+    std::vector<t_lb_type_rr_node>& lb_type_graph = *router_data->lb_type_graph;
+    std::vector<t_intra_lb_net>& lb_nets = *router_data->intra_lb_nets;
+
+    for (size_t ilb_net = 0; ilb_net < lb_nets.size(); ++ilb_net) {
+        //Collect all the sink terminals indicies which target a particular node
+        std::map<int, std::vector<int>> duplicate_terminals;
+        for (size_t iterm = 1; iterm < lb_nets[ilb_net].terminals.size(); ++iterm) {
+            int node = lb_nets[ilb_net].terminals[iterm];
+
+            duplicate_terminals[node].push_back(iterm);
+        }
+
+        for (auto kv : duplicate_terminals) {
+            if (kv.second.size() < 2) continue; //Only process duplicates
+
+            //Remap all the duplicate terminals so they target the pin instead of the sink
+            for (size_t idup_term = 0; idup_term < kv.second.size(); ++idup_term) {
+                int iterm = kv.second[idup_term]; //The index in terminals which is duplicated
+
+                VTR_ASSERT(lb_nets[ilb_net].atom_pins.size() == lb_nets[ilb_net].terminals.size());
+                AtomPinId atom_pin = lb_nets[ilb_net].atom_pins[iterm];
+                VTR_ASSERT(atom_pin);
+
+                const t_pb_graph_pin* pb_graph_pin = find_pb_graph_pin(atom_ctx.nlist, atom_ctx.lookup, atom_pin);
+                VTR_ASSERT(pb_graph_pin);
+
+                if (pb_graph_pin->port->equivalent == PortEquivalence::NONE) continue; //Only need to remap equivalent ports
+
+                //Remap this terminal to an explicit pin instead of the common sink
+                int pin_index = pb_graph_pin->pin_count_in_cluster;
+
+                VTR_LOG_WARN(
+                    "Found duplicate nets connected to logically equivalent pins. "
+                    "Remapping intra lb net %d (atom net %zu '%s') from common sink "
+                    "pb_route %d to fixed pin pb_route %d\n",
+                    ilb_net, size_t(lb_nets[ilb_net].atom_net_id), atom_ctx.nlist.net_name(lb_nets[ilb_net].atom_net_id).c_str(),
+                    kv.first, pin_index);
+
+                VTR_ASSERT(lb_type_graph[pin_index].type == LB_INTERMEDIATE);
+                VTR_ASSERT(lb_type_graph[pin_index].num_fanout[0] == 1);
+                int sink_index = lb_type_graph[pin_index].outedges[0][0].node_index;
+                VTR_ASSERT(lb_type_graph[sink_index].type == LB_SINK);
+                VTR_ASSERT_MSG(sink_index == lb_nets[ilb_net].terminals[iterm], "Remapped pin must be connected to original sink");
+
+                //Change the target
+                lb_nets[ilb_net].terminals[iterm] = pin_index;
+            }
+        }
+    }
+}
+
+/* Commit or remove route tree from currently routed solution */
+static void commit_remove_rt(t_lb_trace* rt, t_lb_router_data* router_data, e_commit_remove op, std::unordered_map<const t_pb_graph_node*, const t_mode*>* mode_map, t_mode_selection_status* mode_status) {
+    t_lb_rr_node_stats* lb_rr_node_stats;
+    t_explored_node_tb* explored_node_tb;
+    std::vector<t_lb_type_rr_node>& lb_type_graph = *router_data->lb_type_graph;
+    int inode;
+    int incr;
+
+    lb_rr_node_stats = router_data->lb_rr_node_stats;
+    explored_node_tb = router_data->explored_node_tb;
+
+    if (rt == nullptr) {
+        return;
+    }
+
+    inode = rt->current_node;
+
+    /* Determine if node is being used or removed */
+    if (op == RT_COMMIT) {
+        incr = 1;
+        if (lb_rr_node_stats[inode].occ >= lb_type_graph[inode].capacity) {
+            lb_rr_node_stats[inode].historical_usage += (lb_rr_node_stats[inode].occ - lb_type_graph[inode].capacity + 1); /* store historical overuse */
+        }
+    } else {
+        incr = -1;
+        explored_node_tb[inode].inet = OPEN;
+    }
+
+    lb_rr_node_stats[inode].occ += incr;
+    VTR_ASSERT(lb_rr_node_stats[inode].occ >= 0);
+
+    auto& driver_node = lb_type_graph[inode];
+    auto* driver_pin = driver_node.pb_graph_pin;
+
+    /* Recursively update route tree */
+    for (unsigned int i = 0; i < rt->next_nodes.size(); i++) {
+        // Check to see if there is no mode conflict between previous nets.
+        // A conflict is present if there are differing modes between a pb_graph_node
+        // and its children.
+        if (op == RT_COMMIT && mode_status->try_expand_all_modes) {
+            auto& node = lb_type_graph[rt->next_nodes[i].current_node];
+            auto* pin = node.pb_graph_pin;
+
+            if (check_edge_for_route_conflicts(mode_map, driver_pin, pin)) {
+                mode_status->is_mode_conflict = true;
+            }
+        }
+
+        commit_remove_rt(&rt->next_nodes[i], router_data, op, mode_map, mode_status);
+    }
+}
+
+/* Should net be skipped?  If the net does not conflict with another net, then skip routing this net */
+static bool is_skip_route_net(t_lb_trace* rt, t_lb_router_data* router_data) {
+    t_lb_rr_node_stats* lb_rr_node_stats;
+    std::vector<t_lb_type_rr_node>& lb_type_graph = *router_data->lb_type_graph;
+    int inode;
+
+    lb_rr_node_stats = router_data->lb_rr_node_stats;
+
+    if (rt == nullptr) {
+        return false; /* Net is not routed, therefore must route net */
+    }
+
+    inode = rt->current_node;
+
+    /* Determine if node is overused */
+    if (lb_rr_node_stats[inode].occ > lb_type_graph[inode].capacity) {
+        /* Conflict between this net and another net at this node, reroute net */
+        return false;
+    }
+
+    /* Recursively check that rest of route tree does not have a conflict */
+    for (unsigned int i = 0; i < rt->next_nodes.size(); i++) {
+        if (!is_skip_route_net(&rt->next_nodes[i], router_data)) {
+            return false;
+        }
+    }
+
+    /* No conflict, this net's current route is legal, skip routing this net */
+    return true;
+}
+
+/* At source mode as starting point to existing route tree */
+static void add_source_to_rt(t_lb_router_data* router_data, int inet) {
+    VTR_ASSERT((*router_data->intra_lb_nets)[inet].rt_tree == nullptr);
+    (*router_data->intra_lb_nets)[inet].rt_tree = new t_lb_trace;
+    (*router_data->intra_lb_nets)[inet].rt_tree->current_node = (*router_data->intra_lb_nets)[inet].terminals[0];
+}
+
+/* Expand all nodes found in route tree into priority queue */
+static void expand_rt(t_lb_router_data* router_data, int inet, reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq, int irt_net) {
+    std::vector<t_intra_lb_net>& lb_nets = *router_data->intra_lb_nets;
+
+    VTR_ASSERT(pq.empty());
+
+    expand_rt_rec(lb_nets[inet].rt_tree, OPEN, router_data->explored_node_tb, pq, irt_net, router_data->explore_id_index);
+}
+
+/* Expand all nodes found in route tree into priority queue recursively */
+static void expand_rt_rec(t_lb_trace* rt, int prev_index, t_explored_node_tb* explored_node_tb, reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq, int irt_net, int explore_id_index) {
+    t_expansion_node enode;
+
+    /* Perhaps should use a cost other than zero */
+    enode.cost = 0;
+    enode.node_index = rt->current_node;
+    enode.prev_index = prev_index;
+    pq.push(enode);
+    explored_node_tb[enode.node_index].inet = irt_net;
+    explored_node_tb[enode.node_index].explored_id = OPEN;
+    explored_node_tb[enode.node_index].enqueue_id = explore_id_index;
+    explored_node_tb[enode.node_index].enqueue_cost = 0;
+    explored_node_tb[enode.node_index].prev_index = prev_index;
+
+    for (unsigned int i = 0; i < rt->next_nodes.size(); i++) {
+        expand_rt_rec(&rt->next_nodes[i], rt->current_node, explored_node_tb, pq, irt_net, explore_id_index);
+    }
+}
+
+/* Expand all edges of an expantion node */
+static void expand_edges(t_lb_router_data* router_data,
+                         int mode,
+                         int cur_inode,
+                         float cur_cost,
+                         int net_fanout,
+                         reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq) {
+    std::vector<t_lb_type_rr_node>& lb_type_graph = *router_data->lb_type_graph;
+    t_lb_rr_node_stats* lb_rr_node_stats = router_data->lb_rr_node_stats;
+    t_lb_router_params params = router_data->params;
+    t_expansion_node enode;
+    int usage;
+    float incr_cost;
+
+    for (int iedge = 0; iedge < lb_type_graph[cur_inode].num_fanout[mode]; iedge++) {
+        /* Init new expansion node */
+        enode.prev_index = cur_inode;
+        enode.node_index = lb_type_graph[cur_inode].outedges[mode][iedge].node_index;
+        enode.cost = cur_cost;
+
+        /* Determine incremental cost of using expansion node */
+        usage = lb_rr_node_stats[enode.node_index].occ + 1 - lb_type_graph[enode.node_index].capacity;
+        incr_cost = lb_type_graph[enode.node_index].intrinsic_cost;
+        incr_cost += lb_type_graph[cur_inode].outedges[mode][iedge].intrinsic_cost;
+        incr_cost += params.hist_fac * lb_rr_node_stats[enode.node_index].historical_usage;
+        if (usage > 0) {
+            incr_cost *= (usage * router_data->pres_con_fac);
+        }
+
+        /* Adjust cost so that higher fanout nets prefer higher fanout routing nodes while lower fanout nets prefer lower fanout routing nodes */
+        float fanout_factor = 1.0;
+        int next_mode = lb_rr_node_stats[enode.node_index].mode;
+        /* Assume first mode if a mode hasn't been forced. */
+        if (next_mode == -1) {
+            next_mode = 0;
+        }
+        if (lb_type_graph[enode.node_index].num_fanout[next_mode] > 1) {
+            fanout_factor = 0.85 + (0.25 / net_fanout);
+        } else {
+            fanout_factor = 1.15 - (0.25 / net_fanout);
+        }
+
+        incr_cost *= fanout_factor;
+        enode.cost = cur_cost + incr_cost;
+
+        /* Add to queue if cost is lower than lowest cost path to this enode */
+        if (router_data->explored_node_tb[enode.node_index].enqueue_id == router_data->explore_id_index) {
+            if (enode.cost < router_data->explored_node_tb[enode.node_index].enqueue_cost) {
+                pq.push(enode);
+            }
+        } else {
+            router_data->explored_node_tb[enode.node_index].enqueue_id = router_data->explore_id_index;
+            router_data->explored_node_tb[enode.node_index].enqueue_cost = enode.cost;
+            pq.push(enode);
+        }
+    }
+}
+
+/* Expand all nodes found in route tree into priority queue */
+static void expand_node(t_lb_router_data* router_data, t_expansion_node exp_node, reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq, int net_fanout) {
+    int cur_node;
+    float cur_cost;
+    int mode;
+    t_expansion_node enode;
+    t_lb_rr_node_stats* lb_rr_node_stats = router_data->lb_rr_node_stats;
+
+    cur_node = exp_node.node_index;
+    cur_cost = exp_node.cost;
+    mode = lb_rr_node_stats[cur_node].mode;
+    if (mode == -1) {
+        mode = 0;
+    }
+
+    expand_edges(router_data, mode, cur_node, cur_cost, net_fanout, pq);
+}
+
+/* Expand all nodes using all possible modes found in route tree into priority queue */
+static void expand_node_all_modes(t_lb_router_data* router_data, t_expansion_node exp_node, reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq, int net_fanout) {
+    std::vector<t_lb_type_rr_node>& lb_type_graph = *router_data->lb_type_graph;
+    t_lb_rr_node_stats* lb_rr_node_stats = router_data->lb_rr_node_stats;
+
+    int cur_inode = exp_node.node_index;
+    float cur_cost = exp_node.cost;
+    int cur_mode = lb_rr_node_stats[cur_inode].mode;
+    auto& node = lb_type_graph[cur_inode];
+    auto* pin = node.pb_graph_pin;
+
+    for (int mode = 0; mode < lb_type_graph[cur_inode].num_modes; mode++) {
+        /* If a mode has been forced, only add edges from that mode, otherwise add edges from all modes. */
+        if (cur_mode != -1 && mode != cur_mode) {
+            continue;
+        }
+
+        /* Check whether a mode is illegal. If it is then the node will not be expanded */
+        bool is_illegal = false;
+        if (pin != nullptr) {
+            auto* pb_graph_node = pin->parent_node;
+            for (auto illegal_mode : pb_graph_node->illegal_modes) {
+                if (mode == illegal_mode) {
+                    is_illegal = true;
+                    break;
+                }
+            }
+        }
+
+        if (is_illegal == true) {
+            continue;
+        }
+
+        expand_edges(router_data, mode, cur_inode, cur_cost, net_fanout, pq);
+    }
+}
+
+/* Add new path from existing route tree to target sink */
+static bool add_to_rt(t_lb_trace* rt, int node_index, t_lb_router_data* router_data, int irt_net) {
+    t_explored_node_tb* explored_node_tb = router_data->explored_node_tb;
+    std::vector<int> trace_forward;
+    int rt_index, trace_index;
+    t_lb_trace* link_node;
+    t_lb_trace curr_node;
+
+    /* Store path all the way back to route tree */
+    rt_index = node_index;
+    while (explored_node_tb[rt_index].inet != irt_net) {
+        trace_forward.push_back(rt_index);
+        rt_index = explored_node_tb[rt_index].prev_index;
+        VTR_ASSERT(rt_index != OPEN);
+    }
+
+    /* Find rt_index on the route tree */
+    link_node = find_node_in_rt(rt, rt_index);
+    if (link_node == nullptr) {
+        VTR_LOG("Link node is nullptr. Routing impossible");
+        return true;
+    }
+
+    /* Add path to root tree */
+    while (!trace_forward.empty()) {
+        trace_index = trace_forward.back();
+        curr_node.current_node = trace_index;
+        link_node->next_nodes.push_back(curr_node);
+        link_node = &link_node->next_nodes.back();
+        trace_forward.pop_back();
+    }
+
+    return false;
+}
+
+/* Determine if a completed route is valid.  A successful route has no congestion (ie. no routing resource is used by two nets). */
+static bool is_route_success(t_lb_router_data* router_data) {
+    std::vector<t_lb_type_rr_node>& lb_type_graph = *router_data->lb_type_graph;
+
+    for (unsigned int inode = 0; inode < lb_type_graph.size(); inode++) {
+        if (router_data->lb_rr_node_stats[inode].occ > lb_type_graph[inode].capacity) {
+            return false;
+        }
+    }
+
+    return true;
+}
+
+/* Given a route tree and an index of a node on the route tree, return a pointer to the trace corresponding to that index */
+static t_lb_trace* find_node_in_rt(t_lb_trace* rt, int rt_index) {
+    t_lb_trace* cur;
+    if (rt->current_node == rt_index) {
+        return rt;
+    } else {
+        for (unsigned int i = 0; i < rt->next_nodes.size(); i++) {
+            cur = find_node_in_rt(&rt->next_nodes[i], rt_index);
+            if (cur != nullptr) {
+                return cur;
+            }
+        }
+    }
+    return nullptr;
+}
+
+#ifdef PRINT_INTRA_LB_ROUTE
+/* Debug routine, print out current intra logic block route */
+static void print_route(const char* filename, t_lb_router_data* router_data) {
+    FILE* fp;
+    std::vector<t_lb_type_rr_node>& lb_type_graph = *router_data->lb_type_graph;
+
+    fp = fopen(filename, "w");
+    for (unsigned int inode = 0; inode < lb_type_graph.size(); inode++) {
+        fprintf(fp, "node %d occ %d cap %d\n", inode, router_data->lb_rr_node_stats[inode].occ, lb_type_graph[inode].capacity);
+    }
+
+    print_route(fp, router_data);
+    fclose(fp);
+}
+
+static void print_route(FILE* fp, t_lb_router_data* router_data) {
+    std::vector<t_intra_lb_net>& lb_nets = *router_data->intra_lb_nets;
+    fprintf(fp, "\n\n----------------------------------------------------\n\n");
+
+    auto& atom_ctx = g_vpr_ctx.atom();
+
+    for (unsigned int inet = 0; inet < lb_nets.size(); inet++) {
+        AtomNetId net_id = lb_nets[inet].atom_net_id;
+        fprintf(fp, "net %s num targets %d \n", atom_ctx.nlist.net_name(net_id).c_str(), (int)lb_nets[inet].terminals.size());
+        fprintf(fp, "\tS");
+        print_trace(fp, lb_nets[inet].rt_tree, router_data);
+        fprintf(fp, "\n\n");
+    }
+}
+#endif
+
+/* Debug routine, print out trace of net */
+static void print_trace(FILE* fp, t_lb_trace* trace, t_lb_router_data* router_data) {
+    if (trace == NULL) {
+        fprintf(fp, "NULL");
+        return;
+    }
+    for (unsigned int ibranch = 0; ibranch < trace->next_nodes.size(); ibranch++) {
+        auto current_node = trace->current_node;
+        auto current_str = describe_lb_type_rr_node(current_node, router_data);
+        auto next_node = trace->next_nodes[ibranch].current_node;
+        auto next_str = describe_lb_type_rr_node(next_node, router_data);
+        if (trace->next_nodes.size() > 1) {
+            fprintf(fp, "\n\tB");
+        }
+        fprintf(fp, "(%d:%s-->%d:%s) ", current_node, current_str.c_str(), next_node, next_str.c_str());
+        print_trace(fp, &trace->next_nodes[ibranch], router_data);
+    }
+}
+
+static void reset_explored_node_tb(t_lb_router_data* router_data) {
+    std::vector<t_lb_type_rr_node>& lb_type_graph = *router_data->lb_type_graph;
+    for (unsigned int inode = 0; inode < lb_type_graph.size(); inode++) {
+        router_data->explored_node_tb[inode].prev_index = OPEN;
+        router_data->explored_node_tb[inode].explored_id = OPEN;
+        router_data->explored_node_tb[inode].inet = OPEN;
+        router_data->explored_node_tb[inode].enqueue_id = OPEN;
+        router_data->explored_node_tb[inode].enqueue_cost = 0;
+    }
+}
+
+/* Save last successful intra-logic block route and reset current traceback */
+static void save_and_reset_lb_route(t_lb_router_data* router_data) {
+    std::vector<t_intra_lb_net>& lb_nets = *router_data->intra_lb_nets;
+
+    /* Free old saved lb nets if exist */
+    if (router_data->saved_lb_nets != nullptr) {
+        free_intra_lb_nets(router_data->saved_lb_nets);
+        router_data->saved_lb_nets = nullptr;
+    }
+
+    /* Save current routed solution */
+    router_data->saved_lb_nets = new std::vector<t_intra_lb_net>(lb_nets.size());
+    std::vector<t_intra_lb_net>& saved_lb_nets = *router_data->saved_lb_nets;
+
+    for (int inet = 0; inet < (int)saved_lb_nets.size(); inet++) {
+        /*
+         * Save and reset route tree data
+         */
+        saved_lb_nets[inet].atom_net_id = lb_nets[inet].atom_net_id;
+        saved_lb_nets[inet].terminals.resize(lb_nets[inet].terminals.size());
+        for (int iterm = 0; iterm < (int)lb_nets[inet].terminals.size(); iterm++) {
+            saved_lb_nets[inet].terminals[iterm] = lb_nets[inet].terminals[iterm];
+        }
+        saved_lb_nets[inet].rt_tree = lb_nets[inet].rt_tree;
+        lb_nets[inet].rt_tree = nullptr;
+    }
+}
+
+static std::vector<int> find_congested_rr_nodes(const std::vector<t_lb_type_rr_node>& lb_type_graph,
+                                                const t_lb_rr_node_stats* lb_rr_node_stats) {
+    std::vector<int> congested_rr_nodes;
+    for (size_t inode = 0; inode < lb_type_graph.size(); ++inode) {
+        const t_lb_type_rr_node& rr_node = lb_type_graph[inode];
+        const t_lb_rr_node_stats& rr_node_stats = lb_rr_node_stats[inode];
+
+        if (rr_node_stats.occ > rr_node.capacity) {
+            congested_rr_nodes.push_back(inode);
+        }
+    }
+
+    return congested_rr_nodes;
+}
+
+static std::string describe_lb_type_rr_node(int inode,
+                                            const t_lb_router_data* router_data) {
+    std::string description;
+
+    const t_lb_type_rr_node& rr_node = (*router_data->lb_type_graph)[inode];
+    t_logical_block_type_ptr lb_type = router_data->lb_type;
+
+    const t_pb_graph_pin* pb_graph_pin = rr_node.pb_graph_pin;
+
+    if (pb_graph_pin) {
+        description += "'" + pb_graph_pin->to_string(false) + "'";
+    } else if (inode == get_lb_type_rr_graph_ext_source_index(lb_type)) {
+        VTR_ASSERT(rr_node.type == LB_SOURCE);
+        description = "cluster-external source (LB_SOURCE)";
+    } else if (inode == get_lb_type_rr_graph_ext_sink_index(lb_type)) {
+        VTR_ASSERT(rr_node.type == LB_SINK);
+        description = "cluster-external sink (LB_SINK)";
+    } else if (rr_node.type == LB_SINK) {
+        description = "cluster-internal sink (LB_SINK accessible via architecture pins: ";
+
+        //To account for equivalent pins multiple pins may route to a single sink.
+        //As a result we need to fin all the nodes which connect to this sink in order
+        //to give user-friendly pin names
+        std::vector<std::string> pin_descriptions;
+        std::vector<int> pin_rrs = find_incoming_rr_nodes(inode, router_data);
+        for (int pin_rr_idx : pin_rrs) {
+            const t_pb_graph_pin* pin_pb_gpin = (*router_data->lb_type_graph)[pin_rr_idx].pb_graph_pin;
+            pin_descriptions.push_back(pin_pb_gpin->to_string());
+        }
+
+        description += vtr::join(pin_descriptions, ", ");
+        description += ")";
+
+    } else if (rr_node.type == LB_SOURCE) {
+        description = "cluster-internal source (LB_SOURCE)";
+    } else if (rr_node.type == LB_INTERMEDIATE) {
+        description = "cluster-internal intermediate?";
+    } else {
+        description = "<unknown lb_type_rr_node>";
+    }
+
+    return description;
+}
+
+static std::vector<int> find_incoming_rr_nodes(int dst_node, const t_lb_router_data* router_data) {
+    std::vector<int> incoming_rr_nodes;
+    const auto& lb_rr_graph = *router_data->lb_type_graph;
+    for (size_t inode = 0; inode < lb_rr_graph.size(); ++inode) {
+        const t_lb_type_rr_node& rr_node = lb_rr_graph[inode];
+        for (int mode = 0; mode < rr_node.num_modes; mode++) {
+            for (int iedge = 0; iedge < rr_node.num_fanout[mode]; ++iedge) {
+                const t_lb_type_rr_node_edge& rr_edge = rr_node.outedges[mode][iedge];
+
+                if (rr_edge.node_index == dst_node) {
+                    //The current node connects to the destination node
+                    incoming_rr_nodes.push_back(inode);
+                }
+            }
+        }
+    }
+    return incoming_rr_nodes;
+}
+
+static std::string describe_congested_rr_nodes(const std::vector<int>& congested_rr_nodes,
+                                               const t_lb_router_data* router_data) {
+    std::string description;
+
+    const auto& lb_nets = *router_data->intra_lb_nets;
+    const auto& lb_type_graph = *router_data->lb_type_graph;
+    const auto& lb_rr_node_stats = router_data->lb_rr_node_stats;
+
+    std::multimap<size_t, AtomNetId> congested_rr_node_to_nets; //From rr_node to net
+    for (unsigned int inet = 0; inet < lb_nets.size(); inet++) {
+        AtomNetId atom_net = lb_nets[inet].atom_net_id;
+
+        //Walk the traceback to find congested RR nodes for each net
+        std::queue<t_lb_trace> q;
+
+        if (lb_nets[inet].rt_tree) {
+            q.push(*lb_nets[inet].rt_tree);
+        }
+        while (!q.empty()) {
+            t_lb_trace curr = q.front();
+            q.pop();
+
+            for (const t_lb_trace& next_trace : curr.next_nodes) {
+                q.push(next_trace);
+            }
+
+            int inode = curr.current_node;
+            const t_lb_type_rr_node& rr_node = lb_type_graph[inode];
+            const t_lb_rr_node_stats& rr_node_stats = lb_rr_node_stats[inode];
+
+            if (rr_node_stats.occ > rr_node.capacity) {
+                //Congested
+                congested_rr_node_to_nets.insert({inode, atom_net});
+            }
+        }
+    }
+
+    VTR_ASSERT(!congested_rr_node_to_nets.empty());
+    VTR_ASSERT(!congested_rr_nodes.empty());
+    auto& atom_ctx = g_vpr_ctx.atom();
+    for (int inode : congested_rr_nodes) {
+        const t_lb_type_rr_node& rr_node = lb_type_graph[inode];
+        const t_lb_rr_node_stats& rr_node_stats = lb_rr_node_stats[inode];
+        description += vtr::string_fmt("RR Node %d (%s) is congested (occ: %d > capacity: %d) with the following nets:\n",
+                                       inode,
+                                       describe_lb_type_rr_node(inode, router_data).c_str(),
+                                       rr_node_stats.occ,
+                                       rr_node.capacity);
+        auto range = congested_rr_node_to_nets.equal_range(inode);
+        for (auto itr = range.first; itr != range.second; ++itr) {
+            AtomNetId net = itr->second;
+            description += vtr::string_fmt("\tNet: %s\n",
+                                           atom_ctx.nlist.net_name(net).c_str());
+        }
+    }
+
+    return description;
+}
+
+void reset_intra_lb_route(t_lb_router_data* router_data) {
+    for (auto& node : *router_data->lb_type_graph) {
+        auto* pin = node.pb_graph_pin;
+        if (pin == nullptr) {
+            continue;
+        }
+        VTR_ASSERT(pin->parent_node != nullptr);
+        pin->parent_node->illegal_modes.clear();
+    }
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/repack/lb_router.h b/openfpga/src/repack/lb_router.h
new file mode 100644
index 000000000..a27011df0
--- /dev/null
+++ b/openfpga/src/repack/lb_router.h
@@ -0,0 +1,40 @@
+/********************************************************************
+ * Intra-logic block router determines if a candidate packing solution (or intermediate solution) can route.
+ * Adapted from original VPR cluster router to the use of LbRRGraph object 
+ *******************************************************************/
+#ifndef LB_ROUTER_H
+#define LB_ROUTER_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <vector>
+#include "atom_netlist_fwd.h"
+#include "pack_types.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/* Constructors/Destructors */
+t_lb_router_data* alloc_and_load_router_data(std::vector<t_lb_type_rr_node>* lb_type_graph, t_logical_block_type_ptr type);
+void free_router_data(t_lb_router_data* router_data);
+void free_intra_lb_nets(std::vector<t_intra_lb_net>* intra_lb_nets);
+
+/* Routing Functions */
+void add_atom_as_target(t_lb_router_data* router_data, const AtomBlockId blk_id);
+void remove_atom_from_target(t_lb_router_data* router_data, const AtomBlockId blk_id);
+void set_reset_pb_modes(t_lb_router_data* router_data, const t_pb* pb, const bool set);
+bool try_intra_lb_route(t_lb_router_data* router_data, int verbosity, t_mode_selection_status* mode_status);
+void reset_intra_lb_route(t_lb_router_data* router_data);
+
+/* Accessor Functions */
+t_pb_routes alloc_and_load_pb_route(const std::vector<t_intra_lb_net>* intra_lb_nets, t_pb_graph_node* pb_graph_head);
+void free_pb_route(t_pb_route* free_pb_route);
+
+} /* end namespace openfpga */
+
+#endif

From d58d14df8ec9431ae1283db61883d033ece771a8 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 18 Feb 2020 16:50:56 -0700
Subject: [PATCH 171/645] start encapsulate the whole lb router in an object

---
 openfpga/src/repack/lb_router.cpp         | 1498 ---------------------
 openfpga/src/repack/lb_router.h           |  179 ++-
 openfpga/src/repack/lb_rr_graph.cpp       |   41 +
 openfpga/src/repack/lb_rr_graph.h         |   18 +
 openfpga/src/repack/lb_rr_graph_utils.cpp |   59 +
 openfpga/src/repack/lb_rr_graph_utils.h   |   22 +
 6 files changed, 301 insertions(+), 1516 deletions(-)
 delete mode 100644 openfpga/src/repack/lb_router.cpp
 create mode 100644 openfpga/src/repack/lb_rr_graph_utils.cpp
 create mode 100644 openfpga/src/repack/lb_rr_graph_utils.h

diff --git a/openfpga/src/repack/lb_router.cpp b/openfpga/src/repack/lb_router.cpp
deleted file mode 100644
index dd694fa49..000000000
--- a/openfpga/src/repack/lb_router.cpp
+++ /dev/null
@@ -1,1498 +0,0 @@
-/********************************************************************
- * Intra-logic block router determines if a candidate packing solution (or intermediate solution) can route.
- * Adapted from original VPR cluster router to the use of LbRRGraph object 
- *
- * Global Inputs: Architecture and netlist
- * Input arguments: clustering info for one cluster (t_pb info)
- * Working data set: t_routing_data contains intermediate work
- * Output: Routable? true/false.  If true, store/return the routed solution.
- *
- * Routing algorithm used is Pathfinder.
- *******************************************************************/
-#include <cstdio>
-#include <cstring>
-#include <vector>
-#include <map>
-#include <queue>
-#include <cmath>
-
-#include "vtr_assert.h"
-#include "vtr_log.h"
-
-#include "vpr_error.h"
-#include "vpr_types.h"
-#include "echo_files.h"
-
-#include "physical_types.h"
-#include "globals.h"
-#include "atom_netlist.h"
-#include "vpr_utils.h"
-#include "pack_types.h"
-#include "pb_type_graph.h"
-#include "lb_type_rr_graph.h"
-#include "lb_router.h"
-
-/* #define PRINT_INTRA_LB_ROUTE */
-
-/* begin namespace openfpga */
-namespace openfpga {
-
-/*****************************************************************************************
- * Internal data structures
- ******************************************************************************************/
-
-enum e_commit_remove { RT_COMMIT,
-                       RT_REMOVE };
-
-// TODO: check if this hacky class memory reserve thing is still necessary, if not, then delete
-/* Packing uses a priority queue that requires a large number of elements.  This backdoor
- * allows me to use a priority queue where I can pre-allocate the # of elements in the underlying container
- * for efficiency reasons.  Note: Must use vector with this */
-template<class T, class U, class V>
-class reservable_pq : public std::priority_queue<T, U, V> {
-  public:
-    typedef typename std::priority_queue<T>::size_type size_type;
-    reservable_pq(size_type capacity = 0) {
-        reserve(capacity);
-        cur_cap = capacity;
-    }
-    void reserve(size_type capacity) {
-        this->c.reserve(capacity);
-        cur_cap = capacity;
-    }
-    void clear() {
-        this->c.clear();
-        this->c.reserve(cur_cap);
-    }
-
-  private:
-    size_type cur_cap;
-};
-
-/*****************************************************************************************
- * Internal functions declarations
- ******************************************************************************************/
-static void free_lb_net_rt(t_lb_trace* lb_trace);
-static void free_lb_trace(t_lb_trace* lb_trace);
-static void add_pin_to_rt_terminals(t_lb_router_data* router_data, const AtomPinId pin_id);
-static void remove_pin_from_rt_terminals(t_lb_router_data* router_data, const AtomPinId pin_id);
-
-static void fix_duplicate_equivalent_pins(t_lb_router_data* router_data);
-
-static void commit_remove_rt(t_lb_trace* rt, t_lb_router_data* router_data, e_commit_remove op, std::unordered_map<const t_pb_graph_node*, const t_mode*>* mode_map, t_mode_selection_status* mode_status);
-static bool is_skip_route_net(t_lb_trace* rt, t_lb_router_data* router_data);
-static void add_source_to_rt(t_lb_router_data* router_data, int inet);
-static void expand_rt(t_lb_router_data* router_data, int inet, reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq, int irt_net);
-static void expand_rt_rec(t_lb_trace* rt, int prev_index, t_explored_node_tb* explored_node_tb, reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq, int irt_net, int explore_id_index);
-static bool try_expand_nodes(t_lb_router_data* router_data,
-                             t_intra_lb_net* lb_net,
-                             t_expansion_node* exp_node,
-                             reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq,
-                             int itarget,
-                             bool try_other_modes,
-                             int verbosity);
-
-static void expand_edges(t_lb_router_data* router_data,
-                         int mode,
-                         int cur_inode,
-                         float cur_cost,
-                         int net_fanout,
-                         reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq);
-
-static void expand_node(t_lb_router_data* router_data, t_expansion_node exp_node, reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq, int net_fanout);
-static void expand_node_all_modes(t_lb_router_data* router_data, t_expansion_node exp_node, reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq, int net_fanout);
-
-static bool add_to_rt(t_lb_trace* rt, int node_index, t_lb_router_data* router_data, int irt_net);
-static bool is_route_success(t_lb_router_data* router_data);
-static t_lb_trace* find_node_in_rt(t_lb_trace* rt, int rt_index);
-static void reset_explored_node_tb(t_lb_router_data* router_data);
-static void save_and_reset_lb_route(t_lb_router_data* router_data);
-static void load_trace_to_pb_route(t_pb_routes& pb_route, const int total_pins, const AtomNetId net_id, const int prev_pin_id, const t_lb_trace* trace);
-
-static std::string describe_lb_type_rr_node(int inode,
-                                            const t_lb_router_data* router_data);
-
-static std::vector<int> find_congested_rr_nodes(const std::vector<t_lb_type_rr_node>& lb_type_graph,
-                                                const t_lb_rr_node_stats* lb_rr_node_stats);
-static std::vector<int> find_incoming_rr_nodes(int dst_node, const t_lb_router_data* router_data);
-static std::string describe_congested_rr_nodes(const std::vector<int>& congested_rr_nodes,
-                                               const t_lb_router_data* router_data);
-/*****************************************************************************************
- * Debug functions declarations
- ******************************************************************************************/
-#ifdef PRINT_INTRA_LB_ROUTE
-static void print_route(const char* filename, t_lb_router_data* router_data);
-static void print_route(FILE* fp, t_lb_router_data* router_data);
-#endif
-static void print_trace(FILE* fp, t_lb_trace* trace, t_lb_router_data* router_data);
-
-/*****************************************************************************************
- * Constructor/Destructor functions
- ******************************************************************************************/
-
-/**
- * Build data structures used by intra-logic block router
- */
-t_lb_router_data* alloc_and_load_router_data(std::vector<t_lb_type_rr_node>* lb_type_graph, t_logical_block_type_ptr type) {
-    t_lb_router_data* router_data = new t_lb_router_data;
-    int size;
-
-    router_data->lb_type_graph = lb_type_graph;
-    size = router_data->lb_type_graph->size();
-    router_data->lb_rr_node_stats = new t_lb_rr_node_stats[size];
-    router_data->explored_node_tb = new t_explored_node_tb[size];
-    router_data->intra_lb_nets = new std::vector<t_intra_lb_net>;
-    router_data->atoms_added = new std::map<AtomBlockId, bool>;
-    router_data->lb_type = type;
-
-    return router_data;
-}
-
-/* free data used by router */
-void free_router_data(t_lb_router_data* router_data) {
-    if (router_data != nullptr && router_data->lb_type_graph != nullptr) {
-        delete[] router_data->lb_rr_node_stats;
-        router_data->lb_rr_node_stats = nullptr;
-        delete[] router_data->explored_node_tb;
-        router_data->explored_node_tb = nullptr;
-        router_data->lb_type_graph = nullptr;
-        delete router_data->atoms_added;
-        router_data->atoms_added = nullptr;
-        free_intra_lb_nets(router_data->intra_lb_nets);
-        free_intra_lb_nets(router_data->saved_lb_nets);
-        router_data->intra_lb_nets = nullptr;
-        delete router_data;
-    }
-}
-
-static bool route_has_conflict(t_lb_trace* rt, t_lb_router_data* router_data) {
-    std::vector<t_lb_type_rr_node>& lb_type_graph = *router_data->lb_type_graph;
-
-    int cur_mode = -1;
-    for (unsigned int i = 0; i < rt->next_nodes.size(); i++) {
-        int new_mode = get_lb_type_rr_graph_edge_mode(lb_type_graph,
-                                                      rt->current_node, rt->next_nodes[i].current_node);
-        if (cur_mode != -1 && cur_mode != new_mode) {
-            return true;
-        }
-        if (route_has_conflict(&rt->next_nodes[i], router_data) == true) {
-            return true;
-        }
-        cur_mode = new_mode;
-    }
-
-    return false;
-}
-
-// Check one edge for mode conflict.
-static bool check_edge_for_route_conflicts(std::unordered_map<const t_pb_graph_node*, const t_mode*>* mode_map,
-                                           const t_pb_graph_pin* driver_pin,
-                                           const t_pb_graph_pin* pin) {
-    if (driver_pin == nullptr) {
-        return false;
-    }
-
-    // Only check pins that are OUT_PORTs.
-    if (pin == nullptr || pin->port == nullptr || pin->port->type != OUT_PORT) {
-        return false;
-    }
-    VTR_ASSERT(!pin->port->is_clock);
-
-    auto* pb_graph_node = pin->parent_node;
-    VTR_ASSERT(pb_graph_node->pb_type == pin->port->parent_pb_type);
-
-    const t_pb_graph_edge* edge = get_edge_between_pins(driver_pin, pin);
-    VTR_ASSERT(edge != nullptr);
-
-    auto mode_of_edge = edge->interconnect->parent_mode_index;
-    auto* mode = &pb_graph_node->pb_type->modes[mode_of_edge];
-
-    auto result = mode_map->insert(std::make_pair(pb_graph_node, mode));
-    if (!result.second) {
-        if (result.first->second != mode) {
-            std::cout << vtr::string_fmt("Differing modes for block.  Got %s mode, while previously was %s for interconnect %s.",
-                                         mode->name, result.first->second->name,
-                                         edge->interconnect->name)
-                      << std::endl;
-
-            // The illegal mode is added to the pb_graph_node as it resulted in a conflict during atom-to-atom routing. This mode cannot be used in the consequent cluster
-            // generation try.
-            if (std::find(pb_graph_node->illegal_modes.begin(), pb_graph_node->illegal_modes.end(), result.first->second->index) == pb_graph_node->illegal_modes.end()) {
-                pb_graph_node->illegal_modes.push_back(result.first->second->index);
-            }
-
-            // If the number of illegal modes equals the number of available mode for a specific pb_graph_node it means that no cluster can be generated. This resuts
-            // in a fatal error.
-            if ((int)pb_graph_node->illegal_modes.size() >= pb_graph_node->pb_type->num_modes) {
-                VPR_FATAL_ERROR(VPR_ERROR_PACK, "There are no more available modes to be used. Routing Failed!");
-            }
-
-            return true;
-        }
-    }
-
-    return false;
-}
-
-/*****************************************************************************************
- * Routing Functions
- ******************************************************************************************/
-
-/* Add pins of netlist atom to to current routing drivers/targets */
-void add_atom_as_target(t_lb_router_data* router_data, const AtomBlockId blk_id) {
-    const t_pb* pb;
-    auto& atom_ctx = g_vpr_ctx.atom();
-
-    std::map<AtomBlockId, bool>& atoms_added = *router_data->atoms_added;
-
-    if (atoms_added.count(blk_id) > 0) {
-        VPR_FATAL_ERROR(VPR_ERROR_PACK, "Atom %s added twice to router\n", atom_ctx.nlist.block_name(blk_id).c_str());
-    }
-
-    pb = atom_ctx.lookup.atom_pb(blk_id);
-
-    VTR_ASSERT(pb);
-
-    atoms_added[blk_id] = true;
-
-    set_reset_pb_modes(router_data, pb, true);
-
-    for (auto pin_id : atom_ctx.nlist.block_pins(blk_id)) {
-        add_pin_to_rt_terminals(router_data, pin_id);
-    }
-
-    fix_duplicate_equivalent_pins(router_data);
-}
-
-/* Remove pins of netlist atom from current routing drivers/targets */
-void remove_atom_from_target(t_lb_router_data* router_data, const AtomBlockId blk_id) {
-    auto& atom_ctx = g_vpr_ctx.atom();
-
-    std::map<AtomBlockId, bool>& atoms_added = *router_data->atoms_added;
-
-    const t_pb* pb = atom_ctx.lookup.atom_pb(blk_id);
-
-    if (atoms_added.count(blk_id) == 0) {
-        return;
-    }
-
-    set_reset_pb_modes(router_data, pb, false);
-
-    for (auto pin_id : atom_ctx.nlist.block_pins(blk_id)) {
-        remove_pin_from_rt_terminals(router_data, pin_id);
-    }
-
-    atoms_added.erase(blk_id);
-}
-
-/* Set/Reset mode of rr nodes to the pb used.  If set == true, then set all modes of the rr nodes affected by pb to the mode of the pb.
- * Set all modes related to pb to 0 otherwise */
-void set_reset_pb_modes(t_lb_router_data* router_data, const t_pb* pb, const bool set) {
-    t_pb_type* pb_type;
-    t_pb_graph_node* pb_graph_node;
-    int mode = pb->mode;
-    int inode;
-
-    VTR_ASSERT(mode >= 0);
-
-    pb_graph_node = pb->pb_graph_node;
-    pb_type = pb_graph_node->pb_type;
-
-    /* Input and clock pin modes are based on current pb mode */
-    for (int iport = 0; iport < pb_graph_node->num_input_ports; iport++) {
-        for (int ipin = 0; ipin < pb_graph_node->num_input_pins[iport]; ipin++) {
-            inode = pb_graph_node->input_pins[iport][ipin].pin_count_in_cluster;
-            router_data->lb_rr_node_stats[inode].mode = (set == true) ? mode : -1;
-        }
-    }
-    for (int iport = 0; iport < pb_graph_node->num_clock_ports; iport++) {
-        for (int ipin = 0; ipin < pb_graph_node->num_clock_pins[iport]; ipin++) {
-            inode = pb_graph_node->clock_pins[iport][ipin].pin_count_in_cluster;
-            router_data->lb_rr_node_stats[inode].mode = (set == true) ? mode : -1;
-        }
-    }
-
-    /* Output pin modes are based on parent pb, so set children to use new mode
-     * Output pin of top-level logic block is also set to mode 0
-     */
-    if (pb_type->num_modes != 0) {
-        for (int ichild_type = 0; ichild_type < pb_type->modes[mode].num_pb_type_children; ichild_type++) {
-            for (int ichild = 0; ichild < pb_type->modes[mode].pb_type_children[ichild_type].num_pb; ichild++) {
-                t_pb_graph_node* child_pb_graph_node = &pb_graph_node->child_pb_graph_nodes[mode][ichild_type][ichild];
-                for (int iport = 0; iport < child_pb_graph_node->num_output_ports; iport++) {
-                    for (int ipin = 0; ipin < child_pb_graph_node->num_output_pins[iport]; ipin++) {
-                        inode = child_pb_graph_node->output_pins[iport][ipin].pin_count_in_cluster;
-                        router_data->lb_rr_node_stats[inode].mode = (set == true) ? mode : -1;
-                    }
-                }
-            }
-        }
-    }
-}
-
-/* Expand all the nodes for a given lb_net */
-static bool try_expand_nodes(t_lb_router_data* router_data,
-                             t_intra_lb_net* lb_net,
-                             t_expansion_node* exp_node,
-                             reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq,
-                             int itarget,
-                             bool try_other_modes,
-                             int verbosity) {
-    bool is_impossible = false;
-
-    do {
-        if (pq.empty()) {
-            /* No connection possible */
-            is_impossible = true;
-
-            if (verbosity > 3) {
-                //Print detailed debug info
-                auto& atom_nlist = g_vpr_ctx.atom().nlist;
-                AtomNetId net_id = lb_net->atom_net_id;
-                AtomPinId driver_pin = lb_net->atom_pins[0];
-                AtomPinId sink_pin = lb_net->atom_pins[itarget];
-                int driver_rr_node = lb_net->terminals[0];
-                int sink_rr_node = lb_net->terminals[itarget];
-
-                VTR_LOG("\t\t\tNo possible routing path from %s to %s: needed for net '%s' from net pin '%s'",
-                        describe_lb_type_rr_node(driver_rr_node, router_data).c_str(),
-                        describe_lb_type_rr_node(sink_rr_node, router_data).c_str(),
-                        atom_nlist.net_name(net_id).c_str(),
-                        atom_nlist.pin_name(driver_pin).c_str());
-                VTR_LOGV(sink_pin, " to net pin '%s'", atom_nlist.pin_name(sink_pin).c_str());
-                VTR_LOG("\n");
-            }
-        } else {
-            *exp_node = pq.top();
-            pq.pop();
-            int exp_inode = exp_node->node_index;
-
-            if (router_data->explored_node_tb[exp_inode].explored_id != router_data->explore_id_index) {
-                /* First time node is popped implies path to this node is the lowest cost.
-                 * If the node is popped a second time, then the path to that node is higher than this path so
-                 * ignore.
-                 */
-                router_data->explored_node_tb[exp_inode].explored_id = router_data->explore_id_index;
-                router_data->explored_node_tb[exp_inode].prev_index = exp_node->prev_index;
-                if (exp_inode != lb_net->terminals[itarget]) {
-                    if (!try_other_modes) {
-                        expand_node(router_data, *exp_node, pq, lb_net->terminals.size() - 1);
-                    } else {
-                        expand_node_all_modes(router_data, *exp_node, pq, lb_net->terminals.size() - 1);
-                    }
-                }
-            }
-        }
-    } while (exp_node->node_index != lb_net->terminals[itarget] && !is_impossible);
-
-    return is_impossible;
-}
-
-/* Attempt to route routing driver/targets on the current architecture
- * Follows pathfinder negotiated congestion algorithm
- */
-bool try_intra_lb_route(t_lb_router_data* router_data,
-                        int verbosity,
-                        t_mode_selection_status* mode_status) {
-    std::vector<t_intra_lb_net>& lb_nets = *router_data->intra_lb_nets;
-    std::vector<t_lb_type_rr_node>& lb_type_graph = *router_data->lb_type_graph;
-    bool is_routed = false;
-    bool is_impossible = false;
-
-    mode_status->is_mode_conflict = false;
-    mode_status->try_expand_all_modes = false;
-
-    t_expansion_node exp_node;
-
-    /* Stores state info during route */
-    reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node> pq;
-
-    reset_explored_node_tb(router_data);
-
-    /* Reset current routing */
-    for (unsigned int inet = 0; inet < lb_nets.size(); inet++) {
-        free_lb_net_rt(lb_nets[inet].rt_tree);
-        lb_nets[inet].rt_tree = nullptr;
-    }
-    for (unsigned int inode = 0; inode < lb_type_graph.size(); inode++) {
-        router_data->lb_rr_node_stats[inode].historical_usage = 0;
-        router_data->lb_rr_node_stats[inode].occ = 0;
-    }
-
-    std::unordered_map<const t_pb_graph_node*, const t_mode*> mode_map;
-
-    /*	Iteratively remove congestion until a successful route is found.
-     * Cap the total number of iterations tried so that if a solution does not exist, then the router won't run indefinitely */
-    router_data->pres_con_fac = router_data->params.pres_fac;
-    for (int iter = 0; iter < router_data->params.max_iterations && !is_routed && !is_impossible; iter++) {
-        unsigned int inet;
-        /* Iterate across all nets internal to logic block */
-        for (inet = 0; inet < lb_nets.size() && !is_impossible; inet++) {
-            int idx = inet;
-            if (is_skip_route_net(lb_nets[idx].rt_tree, router_data)) {
-                continue;
-            }
-            commit_remove_rt(lb_nets[idx].rt_tree, router_data, RT_REMOVE, &mode_map, mode_status);
-            free_lb_net_rt(lb_nets[idx].rt_tree);
-            lb_nets[idx].rt_tree = nullptr;
-            add_source_to_rt(router_data, idx);
-
-            /* Route each sink of net */
-            for (unsigned int itarget = 1; itarget < lb_nets[idx].terminals.size() && !is_impossible; itarget++) {
-                pq.clear();
-                /* Get lowest cost next node, repeat until a path is found or if it is impossible to route */
-
-                expand_rt(router_data, idx, pq, idx);
-
-                is_impossible = try_expand_nodes(router_data, &lb_nets[idx], &exp_node, pq, itarget, mode_status->expand_all_modes, verbosity);
-
-                if (is_impossible && !mode_status->expand_all_modes) {
-                    mode_status->try_expand_all_modes = true;
-                    mode_status->expand_all_modes = true;
-                    break;
-                }
-
-                if (exp_node.node_index == lb_nets[idx].terminals[itarget]) {
-                    /* Net terminal is routed, add this to the route tree, clear data structures, and keep going */
-                    is_impossible = add_to_rt(lb_nets[idx].rt_tree, exp_node.node_index, router_data, idx);
-                }
-
-                if (verbosity > 5) {
-                    VTR_LOG("Routing finished\n");
-                    VTR_LOG("\tS");
-                    print_trace(stdout, lb_nets[idx].rt_tree, router_data);
-                    VTR_LOG("\n");
-                }
-
-                if (is_impossible) {
-                    VTR_LOG("Routing was impossible!\n");
-                } else if (mode_status->expand_all_modes) {
-                    is_impossible = route_has_conflict(lb_nets[idx].rt_tree, router_data);
-                    if (is_impossible) {
-                        VTR_LOG("Routing was impossible due to modes!\n");
-                    }
-                }
-
-                router_data->explore_id_index++;
-                if (router_data->explore_id_index > 2000000000) {
-                    /* overflow protection */
-                    for (unsigned int id = 0; id < lb_type_graph.size(); id++) {
-                        router_data->explored_node_tb[id].explored_id = OPEN;
-                        router_data->explored_node_tb[id].enqueue_id = OPEN;
-                        router_data->explore_id_index = 1;
-                    }
-                }
-            }
-
-            if (!is_impossible) {
-                commit_remove_rt(lb_nets[idx].rt_tree, router_data, RT_COMMIT, &mode_map, mode_status);
-                if (mode_status->is_mode_conflict) {
-                    is_impossible = true;
-                }
-            }
-        }
-
-        if (!is_impossible) {
-            is_routed = is_route_success(router_data);
-        } else {
-            --inet;
-            auto& atom_ctx = g_vpr_ctx.atom();
-            VTR_LOGV(verbosity < 3, "Net '%s' is impossible to route within proposed %s cluster\n",
-                     atom_ctx.nlist.net_name(lb_nets[inet].atom_net_id).c_str(), router_data->lb_type->name);
-            is_routed = false;
-        }
-        router_data->pres_con_fac *= router_data->params.pres_fac_mult;
-    }
-
-    if (is_routed) {
-        save_and_reset_lb_route(router_data);
-    } else {
-        //Unroutable
-#ifdef PRINT_INTRA_LB_ROUTE
-        print_route(getEchoFileName(E_ECHO_INTRA_LB_FAILED_ROUTE), router_data);
-#endif
-
-        if (verbosity > 3 && !is_impossible) {
-            //Report the congested nodes and associated nets
-            auto congested_rr_nodes = find_congested_rr_nodes(lb_type_graph, router_data->lb_rr_node_stats);
-            if (!congested_rr_nodes.empty()) {
-                VTR_LOG("%s\n", describe_congested_rr_nodes(congested_rr_nodes, router_data).c_str());
-            }
-        }
-
-        //Clean-up
-        for (unsigned int inet = 0; inet < lb_nets.size(); inet++) {
-            free_lb_net_rt(lb_nets[inet].rt_tree);
-            lb_nets[inet].rt_tree = nullptr;
-        }
-    }
-    return is_routed;
-}
-
-/*****************************************************************************************
- * Accessor Functions
- ******************************************************************************************/
-
-/* Creates an array [0..num_pb_graph_pins-1] lookup for intra-logic block routing.  Given pb_graph_pin id for clb, lookup atom net that uses that pin.
- * If pin is not used, stores OPEN at that pin location */
-t_pb_routes alloc_and_load_pb_route(const std::vector<t_intra_lb_net>* intra_lb_nets, t_pb_graph_node* pb_graph_head) {
-    const std::vector<t_intra_lb_net>& lb_nets = *intra_lb_nets;
-    int total_pins = pb_graph_head->total_pb_pins;
-    t_pb_routes pb_route;
-
-    for (int inet = 0; inet < (int)lb_nets.size(); inet++) {
-        load_trace_to_pb_route(pb_route, total_pins, lb_nets[inet].atom_net_id, OPEN, lb_nets[inet].rt_tree);
-    }
-
-    return pb_route;
-}
-
-/* Free pin-to-atomic_net array lookup */
-void free_pb_route(t_pb_route* pb_route) {
-    if (pb_route != nullptr) {
-        delete[] pb_route;
-    }
-}
-
-void free_intra_lb_nets(std::vector<t_intra_lb_net>* intra_lb_nets) {
-    if (intra_lb_nets == nullptr) {
-        return;
-    }
-    std::vector<t_intra_lb_net>& lb_nets = *intra_lb_nets;
-    for (unsigned int i = 0; i < lb_nets.size(); i++) {
-        lb_nets[i].terminals.clear();
-        free_lb_net_rt(lb_nets[i].rt_tree);
-        lb_nets[i].rt_tree = nullptr;
-    }
-    delete intra_lb_nets;
-}
-
-/***************************************************************************
- * Internal Functions
- ****************************************************************************/
-
-/* Recurse through route tree trace to populate pb pin to atom net lookup array */
-static void load_trace_to_pb_route(t_pb_routes& pb_route, const int total_pins, const AtomNetId net_id, const int prev_pin_id, const t_lb_trace* trace) {
-    int ipin = trace->current_node;
-    int driver_pb_pin_id = prev_pin_id;
-    int cur_pin_id = OPEN;
-    if (ipin < total_pins) {
-        /* This routing node corresponds with a pin.  This node is virtual (ie. sink or source node) */
-        cur_pin_id = ipin;
-        if (!pb_route.count(ipin)) {
-            pb_route.insert(std::make_pair(cur_pin_id, t_pb_route()));
-            pb_route[cur_pin_id].atom_net_id = net_id;
-            pb_route[cur_pin_id].driver_pb_pin_id = driver_pb_pin_id;
-        } else {
-            VTR_ASSERT(pb_route[cur_pin_id].atom_net_id == net_id);
-        }
-    }
-    for (int itrace = 0; itrace < (int)trace->next_nodes.size(); itrace++) {
-        load_trace_to_pb_route(pb_route, total_pins, net_id, cur_pin_id, &trace->next_nodes[itrace]);
-    }
-}
-
-/* Free route tree for intra-logic block routing */
-static void free_lb_net_rt(t_lb_trace* lb_trace) {
-    if (lb_trace != nullptr) {
-        for (unsigned int i = 0; i < lb_trace->next_nodes.size(); i++) {
-            free_lb_trace(&lb_trace->next_nodes[i]);
-        }
-        lb_trace->next_nodes.clear();
-        delete lb_trace;
-    }
-}
-
-/* Free trace for intra-logic block routing */
-static void free_lb_trace(t_lb_trace* lb_trace) {
-    if (lb_trace != nullptr) {
-        for (unsigned int i = 0; i < lb_trace->next_nodes.size(); i++) {
-            free_lb_trace(&lb_trace->next_nodes[i]);
-        }
-        lb_trace->next_nodes.clear();
-    }
-}
-
-/* Given a pin of a net, assign route tree terminals for it
- * Assumes that pin is not already assigned
- */
-static void add_pin_to_rt_terminals(t_lb_router_data* router_data, const AtomPinId pin_id) {
-    std::vector<t_intra_lb_net>& lb_nets = *router_data->intra_lb_nets;
-    std::vector<t_lb_type_rr_node>& lb_type_graph = *router_data->lb_type_graph;
-    t_logical_block_type_ptr lb_type = router_data->lb_type;
-    bool found = false;
-    unsigned int ipos;
-    auto& atom_ctx = g_vpr_ctx.atom();
-
-    const t_pb_graph_pin* pb_graph_pin = find_pb_graph_pin(atom_ctx.nlist, atom_ctx.lookup, pin_id);
-    VTR_ASSERT(pb_graph_pin);
-
-    AtomPortId port_id = atom_ctx.nlist.pin_port(pin_id);
-    AtomNetId net_id = atom_ctx.nlist.pin_net(pin_id);
-
-    if (!net_id) {
-        //No net connected to this pin, so nothing to route
-        return;
-    }
-
-    /* Find if current net is in route tree, if not, then add to rt.
-     * Code assumes that # of nets in cluster is small so a linear search through
-     * vector is faster than using more complex data structures
-     */
-    for (ipos = 0; ipos < lb_nets.size(); ipos++) {
-        if (lb_nets[ipos].atom_net_id == net_id) {
-            found = true;
-            break;
-        }
-    }
-    if (found == false) {
-        struct t_intra_lb_net new_net;
-
-        new_net.atom_net_id = net_id;
-
-        ipos = lb_nets.size();
-        lb_nets.push_back(new_net);
-    }
-    VTR_ASSERT(lb_nets[ipos].atom_net_id == net_id);
-    VTR_ASSERT(lb_nets[ipos].atom_pins.size() == lb_nets[ipos].terminals.size());
-
-    /*
-     * Determine whether or not this is a new intra lb net, if yes, then add to list of intra lb nets
-     */
-    if (lb_nets[ipos].terminals.empty()) {
-        /* Add terminals */
-
-        //Default assumption is that the source is outside the current cluster (will be overriden later if required)
-        int source_terminal = get_lb_type_rr_graph_ext_source_index(lb_type);
-        lb_nets[ipos].terminals.push_back(source_terminal);
-
-        AtomPinId net_driver_pin_id = atom_ctx.nlist.net_driver(net_id);
-        lb_nets[ipos].atom_pins.push_back(net_driver_pin_id);
-
-        VTR_ASSERT_MSG(lb_type_graph[lb_nets[ipos].terminals[0]].type == LB_SOURCE, "Driver must be a source");
-    }
-
-    VTR_ASSERT(lb_nets[ipos].atom_pins.size() == lb_nets[ipos].terminals.size());
-
-    if (atom_ctx.nlist.port_type(port_id) == PortType::OUTPUT) {
-        //The current pin is the net driver, overwrite the default driver at index 0
-        VTR_ASSERT_MSG(lb_nets[ipos].terminals[0] == get_lb_type_rr_graph_ext_source_index(lb_type), "Default driver must be external source");
-
-        VTR_ASSERT(atom_ctx.nlist.pin_type(pin_id) == PinType::DRIVER);
-
-        //Override the default since this is the driver, and it is within the cluster
-        lb_nets[ipos].terminals[0] = pb_graph_pin->pin_count_in_cluster;
-        lb_nets[ipos].atom_pins[0] = pin_id;
-
-        VTR_ASSERT_MSG(lb_type_graph[lb_nets[ipos].terminals[0]].type == LB_SOURCE, "Driver must be a source");
-
-        int sink_terminal = OPEN;
-        if (lb_nets[ipos].terminals.size() < atom_ctx.nlist.net_pins(net_id).size()) {
-            //Not all of the pins are within the cluster
-            if (lb_nets[ipos].terminals.size() == 1) {
-                //Only the source has been specified so far, must add cluster-external sink
-                sink_terminal = get_lb_type_rr_graph_ext_sink_index(lb_type);
-                lb_nets[ipos].terminals.push_back(sink_terminal);
-                lb_nets[ipos].atom_pins.push_back(AtomPinId::INVALID());
-            } else {
-                VTR_ASSERT(lb_nets[ipos].terminals.size() > 1);
-
-                //TODO: Figure out why we swap terminal 1 here (although it appears to work correctly,
-                //      it's not clear why this is needed...)
-
-                //Move current terminal 1 to end
-                sink_terminal = lb_nets[ipos].terminals[1];
-                AtomPinId sink_atom_pin = lb_nets[ipos].atom_pins[1];
-                lb_nets[ipos].terminals.push_back(sink_terminal);
-                lb_nets[ipos].atom_pins.push_back(sink_atom_pin);
-
-                //Create external sink at terminal 1
-                sink_terminal = get_lb_type_rr_graph_ext_sink_index(lb_type);
-                lb_nets[ipos].terminals[1] = sink_terminal;
-                lb_nets[ipos].atom_pins[1] = AtomPinId::INVALID();
-            }
-            VTR_ASSERT(lb_type_graph[lb_nets[ipos].terminals[1]].type == LB_SINK);
-        }
-    } else {
-        //This is an input to a primitive
-        VTR_ASSERT(atom_ctx.nlist.port_type(port_id) == PortType::INPUT
-                   || atom_ctx.nlist.port_type(port_id) == PortType::CLOCK);
-        VTR_ASSERT(atom_ctx.nlist.pin_type(pin_id) == PinType::SINK);
-
-        //Get the rr node index associated with the pin
-        int pin_index = pb_graph_pin->pin_count_in_cluster;
-        VTR_ASSERT(lb_type_graph[pin_index].num_modes == 1);
-        VTR_ASSERT(lb_type_graph[pin_index].num_fanout[0] == 1);
-
-        /* We actually route to the sink (to handle logically equivalent pins).
-         * The sink is one past the primitive input pin */
-        int sink_index = lb_type_graph[pin_index].outedges[0][0].node_index;
-        VTR_ASSERT(lb_type_graph[sink_index].type == LB_SINK);
-
-        if (lb_nets[ipos].terminals.size() == atom_ctx.nlist.net_pins(net_id).size() && lb_nets[ipos].terminals[1] == get_lb_type_rr_graph_ext_sink_index(lb_type)) {
-            /* If all sinks of net are all contained in the logic block, then the net does
-             * not need to route out of the logic block, so can replace the external sink
-             * with this last sink terminal */
-            lb_nets[ipos].terminals[1] = sink_index;
-            lb_nets[ipos].atom_pins[1] = pin_id;
-        } else {
-            //Add as a regular sink
-            lb_nets[ipos].terminals.push_back(sink_index);
-            lb_nets[ipos].atom_pins.push_back(pin_id);
-        }
-    }
-    VTR_ASSERT(lb_nets[ipos].atom_pins.size() == lb_nets[ipos].terminals.size());
-
-    int num_lb_terminals = lb_nets[ipos].terminals.size();
-    VTR_ASSERT(num_lb_terminals <= (int)atom_ctx.nlist.net_pins(net_id).size());
-    VTR_ASSERT(num_lb_terminals >= 0);
-
-#ifdef VTR_ASSERT_SAFE_ENABLED
-    //Sanity checks
-    int num_extern_sources = 0;
-    int num_extern_sinks = 0;
-    for (size_t iterm = 0; iterm < lb_nets[ipos].terminals.size(); ++iterm) {
-        int inode = lb_nets[ipos].terminals[iterm];
-        AtomPinId atom_pin = lb_nets[ipos].atom_pins[iterm];
-        if (iterm == 0) {
-            //Net driver
-            VTR_ASSERT_SAFE_MSG(lb_type_graph[inode].type == LB_SOURCE, "Driver must be a source RR node");
-            VTR_ASSERT_SAFE_MSG(atom_pin, "Driver have an associated atom pin");
-            VTR_ASSERT_SAFE_MSG(atom_ctx.nlist.pin_type(atom_pin) == PinType::DRIVER, "Source RR must be associated with a driver pin in atom netlist");
-            if (inode == get_lb_type_rr_graph_ext_source_index(lb_type)) {
-                ++num_extern_sources;
-            }
-        } else {
-            //Net sink
-            VTR_ASSERT_SAFE_MSG(lb_type_graph[inode].type == LB_SINK, "Non-driver must be a sink");
-
-            if (inode == get_lb_type_rr_graph_ext_sink_index(lb_type)) {
-                //External sink may have multiple potentially matching atom pins, so it's atom pin is left invalid
-                VTR_ASSERT_SAFE_MSG(!atom_pin, "Cluster external sink should have no valid atom pin");
-                ++num_extern_sinks;
-            } else {
-                VTR_ASSERT_SAFE_MSG(atom_pin, "Intra-cluster sink must have an associated atom pin");
-                VTR_ASSERT_SAFE_MSG(atom_ctx.nlist.pin_type(atom_pin) == PinType::SINK, "Intra-cluster Sink RR must be associated with a sink pin in atom netlist");
-            }
-        }
-    }
-    VTR_ASSERT_SAFE_MSG(num_extern_sinks >= 0 && num_extern_sinks <= 1, "Net must have at most one external sink");
-    VTR_ASSERT_SAFE_MSG(num_extern_sources >= 0 && num_extern_sources <= 1, "Net must have at most one external source");
-#endif
-}
-
-/* Given a pin of a net, remove route tree terminals from it
- */
-static void remove_pin_from_rt_terminals(t_lb_router_data* router_data, const AtomPinId pin_id) {
-    std::vector<t_intra_lb_net>& lb_nets = *router_data->intra_lb_nets;
-    std::vector<t_lb_type_rr_node>& lb_type_graph = *router_data->lb_type_graph;
-    t_logical_block_type_ptr lb_type = router_data->lb_type;
-    bool found = false;
-    unsigned int ipos;
-    auto& atom_ctx = g_vpr_ctx.atom();
-
-    const t_pb_graph_pin* pb_graph_pin = find_pb_graph_pin(atom_ctx.nlist, atom_ctx.lookup, pin_id);
-
-    AtomPortId port_id = atom_ctx.nlist.pin_port(pin_id);
-    AtomNetId net_id = atom_ctx.nlist.pin_net(pin_id);
-
-    if (!net_id) {
-        /* This is not a valid net */
-        return;
-    }
-
-    /* Find current net in route tree
-     * Code assumes that # of nets in cluster is small so a linear search through vector is faster than using more complex data structures
-     */
-    for (ipos = 0; ipos < lb_nets.size(); ipos++) {
-        if (lb_nets[ipos].atom_net_id == net_id) {
-            found = true;
-            break;
-        }
-    }
-    VTR_ASSERT(found == true);
-    VTR_ASSERT(lb_nets[ipos].atom_net_id == net_id);
-
-    VTR_ASSERT(lb_nets[ipos].atom_pins.size() == lb_nets[ipos].terminals.size());
-
-    auto port_type = atom_ctx.nlist.port_type(port_id);
-    if (port_type == PortType::OUTPUT) {
-        /* Net driver pin takes 0th position in terminals */
-        int sink_terminal;
-        VTR_ASSERT(lb_nets[ipos].terminals[0] == pb_graph_pin->pin_count_in_cluster);
-        lb_nets[ipos].terminals[0] = get_lb_type_rr_graph_ext_source_index(lb_type);
-
-        /* source terminal is now coming from outside logic block, do not need to route signal out of logic block */
-        sink_terminal = get_lb_type_rr_graph_ext_sink_index(lb_type);
-        if (lb_nets[ipos].terminals[1] == sink_terminal) {
-            lb_nets[ipos].terminals[1] = lb_nets[ipos].terminals.back();
-            lb_nets[ipos].terminals.pop_back();
-
-            lb_nets[ipos].atom_pins[1] = lb_nets[ipos].atom_pins.back();
-            lb_nets[ipos].atom_pins.pop_back();
-        }
-    } else {
-        VTR_ASSERT(port_type == PortType::INPUT || port_type == PortType::CLOCK);
-
-        /* Remove sink from list of terminals */
-        int pin_index = pb_graph_pin->pin_count_in_cluster;
-        unsigned int iterm;
-
-        VTR_ASSERT(lb_type_graph[pin_index].num_modes == 1);
-        VTR_ASSERT(lb_type_graph[pin_index].num_fanout[0] == 1);
-        int sink_index = lb_type_graph[pin_index].outedges[0][0].node_index;
-        VTR_ASSERT(lb_type_graph[sink_index].type == LB_SINK);
-
-        int target_index = -1;
-        //Search for the sink
-        found = false;
-        for (iterm = 0; iterm < lb_nets[ipos].terminals.size(); iterm++) {
-            if (lb_nets[ipos].terminals[iterm] == sink_index) {
-                target_index = sink_index;
-                found = true;
-                break;
-            }
-        }
-        if (!found) {
-            //Search for the pin
-            found = false;
-            for (iterm = 0; iterm < lb_nets[ipos].terminals.size(); iterm++) {
-                if (lb_nets[ipos].terminals[iterm] == pin_index) {
-                    target_index = pin_index;
-                    found = true;
-                    break;
-                }
-            }
-        }
-        VTR_ASSERT(found == true);
-        VTR_ASSERT(lb_nets[ipos].terminals[iterm] == target_index);
-        VTR_ASSERT(iterm > 0);
-
-        /* Drop terminal from list */
-        lb_nets[ipos].terminals[iterm] = lb_nets[ipos].terminals.back();
-        lb_nets[ipos].terminals.pop_back();
-
-        lb_nets[ipos].atom_pins[iterm] = lb_nets[ipos].atom_pins.back();
-        lb_nets[ipos].atom_pins.pop_back();
-
-        if (lb_nets[ipos].terminals.size() == 1 && lb_nets[ipos].terminals[0] != get_lb_type_rr_graph_ext_source_index(lb_type)) {
-            /* The removed sink must be driven by an atom found in the cluster, add in special sink outside of cluster to represent this */
-            lb_nets[ipos].terminals.push_back(get_lb_type_rr_graph_ext_sink_index(lb_type));
-            lb_nets[ipos].atom_pins.push_back(AtomPinId::INVALID());
-        }
-
-        if (lb_nets[ipos].terminals.size() > 1 && lb_nets[ipos].terminals[1] != get_lb_type_rr_graph_ext_sink_index(lb_type) && lb_nets[ipos].terminals[0] != get_lb_type_rr_graph_ext_source_index(lb_type)) {
-            /* The removed sink must be driven by an atom found in the cluster, add in special sink outside of cluster to represent this */
-            int terminal = lb_nets[ipos].terminals[1];
-            lb_nets[ipos].terminals.push_back(terminal);
-            lb_nets[ipos].terminals[1] = get_lb_type_rr_graph_ext_sink_index(lb_type);
-
-            AtomPinId pin = lb_nets[ipos].atom_pins[1];
-            lb_nets[ipos].atom_pins.push_back(pin);
-            lb_nets[ipos].atom_pins[1] = AtomPinId::INVALID();
-        }
-    }
-    VTR_ASSERT(lb_nets[ipos].atom_pins.size() == lb_nets[ipos].terminals.size());
-
-    if (lb_nets[ipos].terminals.size() == 1 && lb_nets[ipos].terminals[0] == get_lb_type_rr_graph_ext_source_index(lb_type)) {
-        /* This net is not routed, remove from list of nets in lb */
-        lb_nets[ipos] = lb_nets.back();
-        lb_nets.pop_back();
-    }
-}
-
-//It is possible that a net may connect multiple times to a logically equivalent set of primitive pins.
-//The cluster router will only route one connection for a particular net to the common sink of the
-//equivalent pins.
-//
-//To work around this, we fix all but one of these duplicate connections to route to specific pins,
-//(instead of the common sink). This ensures a legal routing is produced and that the duplicate pins
-//are not 'missing' in the clustered netlist.
-static void fix_duplicate_equivalent_pins(t_lb_router_data* router_data) {
-    auto& atom_ctx = g_vpr_ctx.atom();
-
-    std::vector<t_lb_type_rr_node>& lb_type_graph = *router_data->lb_type_graph;
-    std::vector<t_intra_lb_net>& lb_nets = *router_data->intra_lb_nets;
-
-    for (size_t ilb_net = 0; ilb_net < lb_nets.size(); ++ilb_net) {
-        //Collect all the sink terminals indicies which target a particular node
-        std::map<int, std::vector<int>> duplicate_terminals;
-        for (size_t iterm = 1; iterm < lb_nets[ilb_net].terminals.size(); ++iterm) {
-            int node = lb_nets[ilb_net].terminals[iterm];
-
-            duplicate_terminals[node].push_back(iterm);
-        }
-
-        for (auto kv : duplicate_terminals) {
-            if (kv.second.size() < 2) continue; //Only process duplicates
-
-            //Remap all the duplicate terminals so they target the pin instead of the sink
-            for (size_t idup_term = 0; idup_term < kv.second.size(); ++idup_term) {
-                int iterm = kv.second[idup_term]; //The index in terminals which is duplicated
-
-                VTR_ASSERT(lb_nets[ilb_net].atom_pins.size() == lb_nets[ilb_net].terminals.size());
-                AtomPinId atom_pin = lb_nets[ilb_net].atom_pins[iterm];
-                VTR_ASSERT(atom_pin);
-
-                const t_pb_graph_pin* pb_graph_pin = find_pb_graph_pin(atom_ctx.nlist, atom_ctx.lookup, atom_pin);
-                VTR_ASSERT(pb_graph_pin);
-
-                if (pb_graph_pin->port->equivalent == PortEquivalence::NONE) continue; //Only need to remap equivalent ports
-
-                //Remap this terminal to an explicit pin instead of the common sink
-                int pin_index = pb_graph_pin->pin_count_in_cluster;
-
-                VTR_LOG_WARN(
-                    "Found duplicate nets connected to logically equivalent pins. "
-                    "Remapping intra lb net %d (atom net %zu '%s') from common sink "
-                    "pb_route %d to fixed pin pb_route %d\n",
-                    ilb_net, size_t(lb_nets[ilb_net].atom_net_id), atom_ctx.nlist.net_name(lb_nets[ilb_net].atom_net_id).c_str(),
-                    kv.first, pin_index);
-
-                VTR_ASSERT(lb_type_graph[pin_index].type == LB_INTERMEDIATE);
-                VTR_ASSERT(lb_type_graph[pin_index].num_fanout[0] == 1);
-                int sink_index = lb_type_graph[pin_index].outedges[0][0].node_index;
-                VTR_ASSERT(lb_type_graph[sink_index].type == LB_SINK);
-                VTR_ASSERT_MSG(sink_index == lb_nets[ilb_net].terminals[iterm], "Remapped pin must be connected to original sink");
-
-                //Change the target
-                lb_nets[ilb_net].terminals[iterm] = pin_index;
-            }
-        }
-    }
-}
-
-/* Commit or remove route tree from currently routed solution */
-static void commit_remove_rt(t_lb_trace* rt, t_lb_router_data* router_data, e_commit_remove op, std::unordered_map<const t_pb_graph_node*, const t_mode*>* mode_map, t_mode_selection_status* mode_status) {
-    t_lb_rr_node_stats* lb_rr_node_stats;
-    t_explored_node_tb* explored_node_tb;
-    std::vector<t_lb_type_rr_node>& lb_type_graph = *router_data->lb_type_graph;
-    int inode;
-    int incr;
-
-    lb_rr_node_stats = router_data->lb_rr_node_stats;
-    explored_node_tb = router_data->explored_node_tb;
-
-    if (rt == nullptr) {
-        return;
-    }
-
-    inode = rt->current_node;
-
-    /* Determine if node is being used or removed */
-    if (op == RT_COMMIT) {
-        incr = 1;
-        if (lb_rr_node_stats[inode].occ >= lb_type_graph[inode].capacity) {
-            lb_rr_node_stats[inode].historical_usage += (lb_rr_node_stats[inode].occ - lb_type_graph[inode].capacity + 1); /* store historical overuse */
-        }
-    } else {
-        incr = -1;
-        explored_node_tb[inode].inet = OPEN;
-    }
-
-    lb_rr_node_stats[inode].occ += incr;
-    VTR_ASSERT(lb_rr_node_stats[inode].occ >= 0);
-
-    auto& driver_node = lb_type_graph[inode];
-    auto* driver_pin = driver_node.pb_graph_pin;
-
-    /* Recursively update route tree */
-    for (unsigned int i = 0; i < rt->next_nodes.size(); i++) {
-        // Check to see if there is no mode conflict between previous nets.
-        // A conflict is present if there are differing modes between a pb_graph_node
-        // and its children.
-        if (op == RT_COMMIT && mode_status->try_expand_all_modes) {
-            auto& node = lb_type_graph[rt->next_nodes[i].current_node];
-            auto* pin = node.pb_graph_pin;
-
-            if (check_edge_for_route_conflicts(mode_map, driver_pin, pin)) {
-                mode_status->is_mode_conflict = true;
-            }
-        }
-
-        commit_remove_rt(&rt->next_nodes[i], router_data, op, mode_map, mode_status);
-    }
-}
-
-/* Should net be skipped?  If the net does not conflict with another net, then skip routing this net */
-static bool is_skip_route_net(t_lb_trace* rt, t_lb_router_data* router_data) {
-    t_lb_rr_node_stats* lb_rr_node_stats;
-    std::vector<t_lb_type_rr_node>& lb_type_graph = *router_data->lb_type_graph;
-    int inode;
-
-    lb_rr_node_stats = router_data->lb_rr_node_stats;
-
-    if (rt == nullptr) {
-        return false; /* Net is not routed, therefore must route net */
-    }
-
-    inode = rt->current_node;
-
-    /* Determine if node is overused */
-    if (lb_rr_node_stats[inode].occ > lb_type_graph[inode].capacity) {
-        /* Conflict between this net and another net at this node, reroute net */
-        return false;
-    }
-
-    /* Recursively check that rest of route tree does not have a conflict */
-    for (unsigned int i = 0; i < rt->next_nodes.size(); i++) {
-        if (!is_skip_route_net(&rt->next_nodes[i], router_data)) {
-            return false;
-        }
-    }
-
-    /* No conflict, this net's current route is legal, skip routing this net */
-    return true;
-}
-
-/* At source mode as starting point to existing route tree */
-static void add_source_to_rt(t_lb_router_data* router_data, int inet) {
-    VTR_ASSERT((*router_data->intra_lb_nets)[inet].rt_tree == nullptr);
-    (*router_data->intra_lb_nets)[inet].rt_tree = new t_lb_trace;
-    (*router_data->intra_lb_nets)[inet].rt_tree->current_node = (*router_data->intra_lb_nets)[inet].terminals[0];
-}
-
-/* Expand all nodes found in route tree into priority queue */
-static void expand_rt(t_lb_router_data* router_data, int inet, reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq, int irt_net) {
-    std::vector<t_intra_lb_net>& lb_nets = *router_data->intra_lb_nets;
-
-    VTR_ASSERT(pq.empty());
-
-    expand_rt_rec(lb_nets[inet].rt_tree, OPEN, router_data->explored_node_tb, pq, irt_net, router_data->explore_id_index);
-}
-
-/* Expand all nodes found in route tree into priority queue recursively */
-static void expand_rt_rec(t_lb_trace* rt, int prev_index, t_explored_node_tb* explored_node_tb, reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq, int irt_net, int explore_id_index) {
-    t_expansion_node enode;
-
-    /* Perhaps should use a cost other than zero */
-    enode.cost = 0;
-    enode.node_index = rt->current_node;
-    enode.prev_index = prev_index;
-    pq.push(enode);
-    explored_node_tb[enode.node_index].inet = irt_net;
-    explored_node_tb[enode.node_index].explored_id = OPEN;
-    explored_node_tb[enode.node_index].enqueue_id = explore_id_index;
-    explored_node_tb[enode.node_index].enqueue_cost = 0;
-    explored_node_tb[enode.node_index].prev_index = prev_index;
-
-    for (unsigned int i = 0; i < rt->next_nodes.size(); i++) {
-        expand_rt_rec(&rt->next_nodes[i], rt->current_node, explored_node_tb, pq, irt_net, explore_id_index);
-    }
-}
-
-/* Expand all edges of an expantion node */
-static void expand_edges(t_lb_router_data* router_data,
-                         int mode,
-                         int cur_inode,
-                         float cur_cost,
-                         int net_fanout,
-                         reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq) {
-    std::vector<t_lb_type_rr_node>& lb_type_graph = *router_data->lb_type_graph;
-    t_lb_rr_node_stats* lb_rr_node_stats = router_data->lb_rr_node_stats;
-    t_lb_router_params params = router_data->params;
-    t_expansion_node enode;
-    int usage;
-    float incr_cost;
-
-    for (int iedge = 0; iedge < lb_type_graph[cur_inode].num_fanout[mode]; iedge++) {
-        /* Init new expansion node */
-        enode.prev_index = cur_inode;
-        enode.node_index = lb_type_graph[cur_inode].outedges[mode][iedge].node_index;
-        enode.cost = cur_cost;
-
-        /* Determine incremental cost of using expansion node */
-        usage = lb_rr_node_stats[enode.node_index].occ + 1 - lb_type_graph[enode.node_index].capacity;
-        incr_cost = lb_type_graph[enode.node_index].intrinsic_cost;
-        incr_cost += lb_type_graph[cur_inode].outedges[mode][iedge].intrinsic_cost;
-        incr_cost += params.hist_fac * lb_rr_node_stats[enode.node_index].historical_usage;
-        if (usage > 0) {
-            incr_cost *= (usage * router_data->pres_con_fac);
-        }
-
-        /* Adjust cost so that higher fanout nets prefer higher fanout routing nodes while lower fanout nets prefer lower fanout routing nodes */
-        float fanout_factor = 1.0;
-        int next_mode = lb_rr_node_stats[enode.node_index].mode;
-        /* Assume first mode if a mode hasn't been forced. */
-        if (next_mode == -1) {
-            next_mode = 0;
-        }
-        if (lb_type_graph[enode.node_index].num_fanout[next_mode] > 1) {
-            fanout_factor = 0.85 + (0.25 / net_fanout);
-        } else {
-            fanout_factor = 1.15 - (0.25 / net_fanout);
-        }
-
-        incr_cost *= fanout_factor;
-        enode.cost = cur_cost + incr_cost;
-
-        /* Add to queue if cost is lower than lowest cost path to this enode */
-        if (router_data->explored_node_tb[enode.node_index].enqueue_id == router_data->explore_id_index) {
-            if (enode.cost < router_data->explored_node_tb[enode.node_index].enqueue_cost) {
-                pq.push(enode);
-            }
-        } else {
-            router_data->explored_node_tb[enode.node_index].enqueue_id = router_data->explore_id_index;
-            router_data->explored_node_tb[enode.node_index].enqueue_cost = enode.cost;
-            pq.push(enode);
-        }
-    }
-}
-
-/* Expand all nodes found in route tree into priority queue */
-static void expand_node(t_lb_router_data* router_data, t_expansion_node exp_node, reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq, int net_fanout) {
-    int cur_node;
-    float cur_cost;
-    int mode;
-    t_expansion_node enode;
-    t_lb_rr_node_stats* lb_rr_node_stats = router_data->lb_rr_node_stats;
-
-    cur_node = exp_node.node_index;
-    cur_cost = exp_node.cost;
-    mode = lb_rr_node_stats[cur_node].mode;
-    if (mode == -1) {
-        mode = 0;
-    }
-
-    expand_edges(router_data, mode, cur_node, cur_cost, net_fanout, pq);
-}
-
-/* Expand all nodes using all possible modes found in route tree into priority queue */
-static void expand_node_all_modes(t_lb_router_data* router_data, t_expansion_node exp_node, reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq, int net_fanout) {
-    std::vector<t_lb_type_rr_node>& lb_type_graph = *router_data->lb_type_graph;
-    t_lb_rr_node_stats* lb_rr_node_stats = router_data->lb_rr_node_stats;
-
-    int cur_inode = exp_node.node_index;
-    float cur_cost = exp_node.cost;
-    int cur_mode = lb_rr_node_stats[cur_inode].mode;
-    auto& node = lb_type_graph[cur_inode];
-    auto* pin = node.pb_graph_pin;
-
-    for (int mode = 0; mode < lb_type_graph[cur_inode].num_modes; mode++) {
-        /* If a mode has been forced, only add edges from that mode, otherwise add edges from all modes. */
-        if (cur_mode != -1 && mode != cur_mode) {
-            continue;
-        }
-
-        /* Check whether a mode is illegal. If it is then the node will not be expanded */
-        bool is_illegal = false;
-        if (pin != nullptr) {
-            auto* pb_graph_node = pin->parent_node;
-            for (auto illegal_mode : pb_graph_node->illegal_modes) {
-                if (mode == illegal_mode) {
-                    is_illegal = true;
-                    break;
-                }
-            }
-        }
-
-        if (is_illegal == true) {
-            continue;
-        }
-
-        expand_edges(router_data, mode, cur_inode, cur_cost, net_fanout, pq);
-    }
-}
-
-/* Add new path from existing route tree to target sink */
-static bool add_to_rt(t_lb_trace* rt, int node_index, t_lb_router_data* router_data, int irt_net) {
-    t_explored_node_tb* explored_node_tb = router_data->explored_node_tb;
-    std::vector<int> trace_forward;
-    int rt_index, trace_index;
-    t_lb_trace* link_node;
-    t_lb_trace curr_node;
-
-    /* Store path all the way back to route tree */
-    rt_index = node_index;
-    while (explored_node_tb[rt_index].inet != irt_net) {
-        trace_forward.push_back(rt_index);
-        rt_index = explored_node_tb[rt_index].prev_index;
-        VTR_ASSERT(rt_index != OPEN);
-    }
-
-    /* Find rt_index on the route tree */
-    link_node = find_node_in_rt(rt, rt_index);
-    if (link_node == nullptr) {
-        VTR_LOG("Link node is nullptr. Routing impossible");
-        return true;
-    }
-
-    /* Add path to root tree */
-    while (!trace_forward.empty()) {
-        trace_index = trace_forward.back();
-        curr_node.current_node = trace_index;
-        link_node->next_nodes.push_back(curr_node);
-        link_node = &link_node->next_nodes.back();
-        trace_forward.pop_back();
-    }
-
-    return false;
-}
-
-/* Determine if a completed route is valid.  A successful route has no congestion (ie. no routing resource is used by two nets). */
-static bool is_route_success(t_lb_router_data* router_data) {
-    std::vector<t_lb_type_rr_node>& lb_type_graph = *router_data->lb_type_graph;
-
-    for (unsigned int inode = 0; inode < lb_type_graph.size(); inode++) {
-        if (router_data->lb_rr_node_stats[inode].occ > lb_type_graph[inode].capacity) {
-            return false;
-        }
-    }
-
-    return true;
-}
-
-/* Given a route tree and an index of a node on the route tree, return a pointer to the trace corresponding to that index */
-static t_lb_trace* find_node_in_rt(t_lb_trace* rt, int rt_index) {
-    t_lb_trace* cur;
-    if (rt->current_node == rt_index) {
-        return rt;
-    } else {
-        for (unsigned int i = 0; i < rt->next_nodes.size(); i++) {
-            cur = find_node_in_rt(&rt->next_nodes[i], rt_index);
-            if (cur != nullptr) {
-                return cur;
-            }
-        }
-    }
-    return nullptr;
-}
-
-#ifdef PRINT_INTRA_LB_ROUTE
-/* Debug routine, print out current intra logic block route */
-static void print_route(const char* filename, t_lb_router_data* router_data) {
-    FILE* fp;
-    std::vector<t_lb_type_rr_node>& lb_type_graph = *router_data->lb_type_graph;
-
-    fp = fopen(filename, "w");
-    for (unsigned int inode = 0; inode < lb_type_graph.size(); inode++) {
-        fprintf(fp, "node %d occ %d cap %d\n", inode, router_data->lb_rr_node_stats[inode].occ, lb_type_graph[inode].capacity);
-    }
-
-    print_route(fp, router_data);
-    fclose(fp);
-}
-
-static void print_route(FILE* fp, t_lb_router_data* router_data) {
-    std::vector<t_intra_lb_net>& lb_nets = *router_data->intra_lb_nets;
-    fprintf(fp, "\n\n----------------------------------------------------\n\n");
-
-    auto& atom_ctx = g_vpr_ctx.atom();
-
-    for (unsigned int inet = 0; inet < lb_nets.size(); inet++) {
-        AtomNetId net_id = lb_nets[inet].atom_net_id;
-        fprintf(fp, "net %s num targets %d \n", atom_ctx.nlist.net_name(net_id).c_str(), (int)lb_nets[inet].terminals.size());
-        fprintf(fp, "\tS");
-        print_trace(fp, lb_nets[inet].rt_tree, router_data);
-        fprintf(fp, "\n\n");
-    }
-}
-#endif
-
-/* Debug routine, print out trace of net */
-static void print_trace(FILE* fp, t_lb_trace* trace, t_lb_router_data* router_data) {
-    if (trace == NULL) {
-        fprintf(fp, "NULL");
-        return;
-    }
-    for (unsigned int ibranch = 0; ibranch < trace->next_nodes.size(); ibranch++) {
-        auto current_node = trace->current_node;
-        auto current_str = describe_lb_type_rr_node(current_node, router_data);
-        auto next_node = trace->next_nodes[ibranch].current_node;
-        auto next_str = describe_lb_type_rr_node(next_node, router_data);
-        if (trace->next_nodes.size() > 1) {
-            fprintf(fp, "\n\tB");
-        }
-        fprintf(fp, "(%d:%s-->%d:%s) ", current_node, current_str.c_str(), next_node, next_str.c_str());
-        print_trace(fp, &trace->next_nodes[ibranch], router_data);
-    }
-}
-
-static void reset_explored_node_tb(t_lb_router_data* router_data) {
-    std::vector<t_lb_type_rr_node>& lb_type_graph = *router_data->lb_type_graph;
-    for (unsigned int inode = 0; inode < lb_type_graph.size(); inode++) {
-        router_data->explored_node_tb[inode].prev_index = OPEN;
-        router_data->explored_node_tb[inode].explored_id = OPEN;
-        router_data->explored_node_tb[inode].inet = OPEN;
-        router_data->explored_node_tb[inode].enqueue_id = OPEN;
-        router_data->explored_node_tb[inode].enqueue_cost = 0;
-    }
-}
-
-/* Save last successful intra-logic block route and reset current traceback */
-static void save_and_reset_lb_route(t_lb_router_data* router_data) {
-    std::vector<t_intra_lb_net>& lb_nets = *router_data->intra_lb_nets;
-
-    /* Free old saved lb nets if exist */
-    if (router_data->saved_lb_nets != nullptr) {
-        free_intra_lb_nets(router_data->saved_lb_nets);
-        router_data->saved_lb_nets = nullptr;
-    }
-
-    /* Save current routed solution */
-    router_data->saved_lb_nets = new std::vector<t_intra_lb_net>(lb_nets.size());
-    std::vector<t_intra_lb_net>& saved_lb_nets = *router_data->saved_lb_nets;
-
-    for (int inet = 0; inet < (int)saved_lb_nets.size(); inet++) {
-        /*
-         * Save and reset route tree data
-         */
-        saved_lb_nets[inet].atom_net_id = lb_nets[inet].atom_net_id;
-        saved_lb_nets[inet].terminals.resize(lb_nets[inet].terminals.size());
-        for (int iterm = 0; iterm < (int)lb_nets[inet].terminals.size(); iterm++) {
-            saved_lb_nets[inet].terminals[iterm] = lb_nets[inet].terminals[iterm];
-        }
-        saved_lb_nets[inet].rt_tree = lb_nets[inet].rt_tree;
-        lb_nets[inet].rt_tree = nullptr;
-    }
-}
-
-static std::vector<int> find_congested_rr_nodes(const std::vector<t_lb_type_rr_node>& lb_type_graph,
-                                                const t_lb_rr_node_stats* lb_rr_node_stats) {
-    std::vector<int> congested_rr_nodes;
-    for (size_t inode = 0; inode < lb_type_graph.size(); ++inode) {
-        const t_lb_type_rr_node& rr_node = lb_type_graph[inode];
-        const t_lb_rr_node_stats& rr_node_stats = lb_rr_node_stats[inode];
-
-        if (rr_node_stats.occ > rr_node.capacity) {
-            congested_rr_nodes.push_back(inode);
-        }
-    }
-
-    return congested_rr_nodes;
-}
-
-static std::string describe_lb_type_rr_node(int inode,
-                                            const t_lb_router_data* router_data) {
-    std::string description;
-
-    const t_lb_type_rr_node& rr_node = (*router_data->lb_type_graph)[inode];
-    t_logical_block_type_ptr lb_type = router_data->lb_type;
-
-    const t_pb_graph_pin* pb_graph_pin = rr_node.pb_graph_pin;
-
-    if (pb_graph_pin) {
-        description += "'" + pb_graph_pin->to_string(false) + "'";
-    } else if (inode == get_lb_type_rr_graph_ext_source_index(lb_type)) {
-        VTR_ASSERT(rr_node.type == LB_SOURCE);
-        description = "cluster-external source (LB_SOURCE)";
-    } else if (inode == get_lb_type_rr_graph_ext_sink_index(lb_type)) {
-        VTR_ASSERT(rr_node.type == LB_SINK);
-        description = "cluster-external sink (LB_SINK)";
-    } else if (rr_node.type == LB_SINK) {
-        description = "cluster-internal sink (LB_SINK accessible via architecture pins: ";
-
-        //To account for equivalent pins multiple pins may route to a single sink.
-        //As a result we need to fin all the nodes which connect to this sink in order
-        //to give user-friendly pin names
-        std::vector<std::string> pin_descriptions;
-        std::vector<int> pin_rrs = find_incoming_rr_nodes(inode, router_data);
-        for (int pin_rr_idx : pin_rrs) {
-            const t_pb_graph_pin* pin_pb_gpin = (*router_data->lb_type_graph)[pin_rr_idx].pb_graph_pin;
-            pin_descriptions.push_back(pin_pb_gpin->to_string());
-        }
-
-        description += vtr::join(pin_descriptions, ", ");
-        description += ")";
-
-    } else if (rr_node.type == LB_SOURCE) {
-        description = "cluster-internal source (LB_SOURCE)";
-    } else if (rr_node.type == LB_INTERMEDIATE) {
-        description = "cluster-internal intermediate?";
-    } else {
-        description = "<unknown lb_type_rr_node>";
-    }
-
-    return description;
-}
-
-static std::vector<int> find_incoming_rr_nodes(int dst_node, const t_lb_router_data* router_data) {
-    std::vector<int> incoming_rr_nodes;
-    const auto& lb_rr_graph = *router_data->lb_type_graph;
-    for (size_t inode = 0; inode < lb_rr_graph.size(); ++inode) {
-        const t_lb_type_rr_node& rr_node = lb_rr_graph[inode];
-        for (int mode = 0; mode < rr_node.num_modes; mode++) {
-            for (int iedge = 0; iedge < rr_node.num_fanout[mode]; ++iedge) {
-                const t_lb_type_rr_node_edge& rr_edge = rr_node.outedges[mode][iedge];
-
-                if (rr_edge.node_index == dst_node) {
-                    //The current node connects to the destination node
-                    incoming_rr_nodes.push_back(inode);
-                }
-            }
-        }
-    }
-    return incoming_rr_nodes;
-}
-
-static std::string describe_congested_rr_nodes(const std::vector<int>& congested_rr_nodes,
-                                               const t_lb_router_data* router_data) {
-    std::string description;
-
-    const auto& lb_nets = *router_data->intra_lb_nets;
-    const auto& lb_type_graph = *router_data->lb_type_graph;
-    const auto& lb_rr_node_stats = router_data->lb_rr_node_stats;
-
-    std::multimap<size_t, AtomNetId> congested_rr_node_to_nets; //From rr_node to net
-    for (unsigned int inet = 0; inet < lb_nets.size(); inet++) {
-        AtomNetId atom_net = lb_nets[inet].atom_net_id;
-
-        //Walk the traceback to find congested RR nodes for each net
-        std::queue<t_lb_trace> q;
-
-        if (lb_nets[inet].rt_tree) {
-            q.push(*lb_nets[inet].rt_tree);
-        }
-        while (!q.empty()) {
-            t_lb_trace curr = q.front();
-            q.pop();
-
-            for (const t_lb_trace& next_trace : curr.next_nodes) {
-                q.push(next_trace);
-            }
-
-            int inode = curr.current_node;
-            const t_lb_type_rr_node& rr_node = lb_type_graph[inode];
-            const t_lb_rr_node_stats& rr_node_stats = lb_rr_node_stats[inode];
-
-            if (rr_node_stats.occ > rr_node.capacity) {
-                //Congested
-                congested_rr_node_to_nets.insert({inode, atom_net});
-            }
-        }
-    }
-
-    VTR_ASSERT(!congested_rr_node_to_nets.empty());
-    VTR_ASSERT(!congested_rr_nodes.empty());
-    auto& atom_ctx = g_vpr_ctx.atom();
-    for (int inode : congested_rr_nodes) {
-        const t_lb_type_rr_node& rr_node = lb_type_graph[inode];
-        const t_lb_rr_node_stats& rr_node_stats = lb_rr_node_stats[inode];
-        description += vtr::string_fmt("RR Node %d (%s) is congested (occ: %d > capacity: %d) with the following nets:\n",
-                                       inode,
-                                       describe_lb_type_rr_node(inode, router_data).c_str(),
-                                       rr_node_stats.occ,
-                                       rr_node.capacity);
-        auto range = congested_rr_node_to_nets.equal_range(inode);
-        for (auto itr = range.first; itr != range.second; ++itr) {
-            AtomNetId net = itr->second;
-            description += vtr::string_fmt("\tNet: %s\n",
-                                           atom_ctx.nlist.net_name(net).c_str());
-        }
-    }
-
-    return description;
-}
-
-void reset_intra_lb_route(t_lb_router_data* router_data) {
-    for (auto& node : *router_data->lb_type_graph) {
-        auto* pin = node.pb_graph_pin;
-        if (pin == nullptr) {
-            continue;
-        }
-        VTR_ASSERT(pin->parent_node != nullptr);
-        pin->parent_node->illegal_modes.clear();
-    }
-}
-
-} /* end namespace openfpga */
diff --git a/openfpga/src/repack/lb_router.h b/openfpga/src/repack/lb_router.h
index a27011df0..fe4c7d110 100644
--- a/openfpga/src/repack/lb_router.h
+++ b/openfpga/src/repack/lb_router.h
@@ -1,16 +1,20 @@
-/********************************************************************
- * Intra-logic block router determines if a candidate packing solution (or intermediate solution) can route.
- * Adapted from original VPR cluster router to the use of LbRRGraph object 
- *******************************************************************/
 #ifndef LB_ROUTER_H
 #define LB_ROUTER_H
 
 /********************************************************************
  * Include header files that are required by function declaration
  *******************************************************************/
+#include <map>
+#include <unordered_map>
 #include <vector>
+
+#include "vtr_vector.h"
+
+#include "arch_types.h"
+#include "vpr_types.h"
 #include "atom_netlist_fwd.h"
-#include "pack_types.h"
+
+#include "lb_rr_graph.h"
 
 /********************************************************************
  * Function declaration
@@ -19,21 +23,160 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-/* Constructors/Destructors */
-t_lb_router_data* alloc_and_load_router_data(std::vector<t_lb_type_rr_node>* lb_type_graph, t_logical_block_type_ptr type);
-void free_router_data(t_lb_router_data* router_data);
-void free_intra_lb_nets(std::vector<t_intra_lb_net>* intra_lb_nets);
+class LbRouter {
+  public: /* Intra-Logic Block Routing Data Structures (by instance) */
+    /**************************************************************************
+     * A routing traceback data structure, provides a logic cluster_ctx.blocks 
+     * instance specific trace lookup directly from the t_lb_type_rr_node array index
+     * After packing, routing info for each CLB will have an array of t_lb_traceback 
+     * to store routing info within the CLB
+     ***************************************************************************/
+    struct t_traceback {
+      int net;             /* net of flat, technology-mapped, netlist using this node */
+      LbRRNodeId prev_lb_rr_node; /* index of previous node that drives current node */
+      LbRREdgeId prev_edge;       /* index of previous edge that drives current node */
+    };
 
-/* Routing Functions */
-void add_atom_as_target(t_lb_router_data* router_data, const AtomBlockId blk_id);
-void remove_atom_from_target(t_lb_router_data* router_data, const AtomBlockId blk_id);
-void set_reset_pb_modes(t_lb_router_data* router_data, const t_pb* pb, const bool set);
-bool try_intra_lb_route(t_lb_router_data* router_data, int verbosity, t_mode_selection_status* mode_status);
-void reset_intra_lb_route(t_lb_router_data* router_data);
+    /**************************************************************************
+     * Describes the status of a logic cluster_ctx.blocks routing resource node 
+     * for a given logic cluster_ctx.blocks instance
+     ***************************************************************************/
+    struct t_routing_stats {
+      int occ;  /* Number of nets currently using this lb_rr_node */
+      t_mode* mode; /* Mode that this rr_node is set to */
+    
+      int historical_usage; /* Historical usage of using this node */
+    
+      t_lb_rr_graph_stats() {
+        occ = 0;
+        mode = nullptr;
+        historical_usage = 0;
+      }
+    };
 
-/* Accessor Functions */
-t_pb_routes alloc_and_load_pb_route(const std::vector<t_intra_lb_net>* intra_lb_nets, t_pb_graph_node* pb_graph_head);
-void free_pb_route(t_pb_route* free_pb_route);
+    /**************************************************************************
+     * Data structure forming the route tree of a net within one logic cluster_ctx.blocks.
+     * A net is implemented using routing resource nodes. 
+     * The t_lb_trace data structure records one of the nodes used by the net and the connections
+     * to other nodes
+     ***************************************************************************/
+    struct t_trace {
+      LbRRNodeId current_node;            /* current t_lb_type_rr_node used by net */
+      std::vector<t_lb_trace> next_nodes; /* index of previous edge that drives current node */
+    };
+
+    /**************************************************************************
+     * Represents a net used inside a logic cluster_ctx.blocks and the 
+     * physical nodes used by the net
+     ***************************************************************************/
+    struct t_net {
+      AtomNetId atom_net_id;             /* index of atom net this intra_lb_net represents */
+      std::vector<LbRRNodeId> terminals; /* endpoints of the intra_lb_net, 0th position is the source, all others are sinks */
+      std::vector<AtomPinId> atom_pins;  /* AtomPin's associated with each terminal */
+      std::vector<bool> fixed_terminals; /* Marks a terminal as having a fixed target (i.e. a pin not a sink) */
+      t_lb_trace* rt_tree;               /* Route tree head */
+    
+      t_lb_rr_net() {
+          atom_net_id = AtomNetId::INVALID();
+          rt_tree = nullptr;
+      }
+    };
+
+    /**************************************************************************
+     * Stores tuning parameters used by intra-logic cluster_ctx.blocks router 
+     ***************************************************************************/
+    struct t_option {
+      int max_iterations;
+      float pres_fac;
+      float pres_fac_mult;
+      float hist_fac;
+    };
+
+    /**************************************************************************
+     * Node expanded by router 
+     ***************************************************************************/
+    struct t_expansion_node {
+      LbRRNodeId node_index; /* Index of logic cluster_ctx.blocks rr node this expansion node represents */
+      LbRRNodeId prev_index; /* Index of logic cluster_ctx.blocks rr node that drives this expansion node */
+      float cost;
+    
+      t_expansion_node() {
+        node_index = LbRRNodeId::INVALID();
+        prev_index = LbRRNodeId::INVALID();
+        cost = 0;
+      }
+    };
+
+    class compare_expansion_node {
+      public:
+        /* Returns true if t1 is earlier than t2 */
+        bool operator()(t_expansion_node& e1, t_expansion_node& e2) {
+          if (e1.cost > e2.cost) {
+            return true;
+          }
+          return false;
+        }
+    };
+
+    /**************************************************************************
+     * Stores explored nodes by router 
+     ***************************************************************************/
+    struct t_explored_node_stats {
+      LbRRNodeId prev_index;     /* Prevous node that drives this one */
+      int explored_id;    /* ID used to determine if this node has been explored */
+      int inet;           /* net index of route tree */
+      int enqueue_id;     /* ID used ot determine if this node has been pushed on exploration priority queue */
+      float enqueue_cost; /* cost of node pused on exploration priority queue */
+    
+      t_explored_node_stats() {
+        prev_index = LbRRNodeId::INVALID();
+        explored_id = OPEN;
+        enqueue_id = OPEN;
+        inet = OPEN;
+        enqueue_cost = 0;
+      }
+    };
+
+    /**************************************************************************
+     * Stores status of mode selection during clustering 
+     ***************************************************************************/
+    struct t_mode_selection_status {
+      bool is_mode_conflict = false;
+      bool try_expand_all_modes = false;
+      bool expand_all_modes = false;
+    
+      bool is_mode_issue() {
+        return is_mode_conflict || try_expand_all_modes;
+      }
+    };
+
+  private : /* Stores all data needed by intra-logic cluster_ctx.blocks router */
+    /* Logical Netlist Info */
+    std::vector<t_net> intra_lb_nets_; /* Pointer to vector of intra logic cluster_ctx.blocks nets and their connections */
+
+    /* Saved nets */
+    std::vector<t_net> saved_lb_nets_; /* Save vector of intra logic cluster_ctx.blocks nets and their connections */
+
+    std::map<AtomBlockId, bool> atoms_added_; /* map that records which atoms are added to cluster router */
+
+    /* Logical-to-physical mapping info */
+    vtr::vector<LbRRNodeId, t_routing_stats> lb_rr_node_stats_; /* [0..lb_type_graph->size()-1] Stats for each logic cluster_ctx.blocks rr node instance */
+
+    /* Stores state info during Pathfinder iterative routing */
+    vtr::vector<LbRRNodeId, t_explored_node_stats> explored_node_tb_; /* [0..lb_type_graph->size()-1] Stores mode exploration and traceback info for nodes */
+    int explore_id_index_;                 /* used in conjunction with node_traceback to determine whether or not a location has been explored.  By using a unique identifier every route, I don't have to clear the previous route exploration */
+
+    /* Current type */
+    t_logical_block_type_ptr lb_type_;
+
+    /* Parameters used by router */
+    t_option options_;
+
+    bool is_routed_;                       /* Stores whether or not the current logical-to-physical mapping has a routed solution */
+
+    /* current congestion factor */
+    float pres_con_fac_;
+};
 
 } /* end namespace openfpga */
 
diff --git a/openfpga/src/repack/lb_rr_graph.cpp b/openfpga/src/repack/lb_rr_graph.cpp
index 99b0ecd1b..712acd50b 100644
--- a/openfpga/src/repack/lb_rr_graph.cpp
+++ b/openfpga/src/repack/lb_rr_graph.cpp
@@ -9,6 +9,14 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
+/**************************************************
+ * Public Constructors
+ *************************************************/
+LbRRGraph::LbRRGraph() {
+  ext_source_node_ = LbRRNodeId::INVALID();
+  ext_sink_node_ = LbRRNodeId::INVALID();
+}
+
 /**************************************************
  * Public Accessors: Aggregates 
  *************************************************/
@@ -43,6 +51,11 @@ float LbRRGraph::node_intrinsic_cost(const LbRRNodeId& node) const {
   return node_intrinsic_costs_[node];
 }
 
+std::vector<LbRREdgeId> LbRRGraph::node_in_edges(const LbRRNodeId& node) const {
+  VTR_ASSERT(true == valid_node_id(node));
+  return node_in_edges_[node];
+}
+
 std::vector<LbRREdgeId> LbRRGraph::node_in_edges(const LbRRNodeId& node, t_mode* mode) const {
   std::vector<LbRREdgeId> in_edges;
 
@@ -81,6 +94,24 @@ LbRRNodeId LbRRGraph::find_node(const e_lb_rr_type& type, t_pb_graph_pin* pb_gra
   return node_lookup_[size_t(type)].at(pb_graph_pin);
 }
 
+LbRRNodeId ext_source_node() const {
+  return ext_source_node_;
+}
+
+LbRRNodeId ext_sink_node() const {
+  return ext_sink_node_;
+}
+
+std::vector<LbRREdgeId> find_edge(const LbRRNodeId& src_node, const LbRRNodeId& sink_node) const {
+  std::vector<LbRREdgeId> edges;
+  for (const LbRREdgeId& edge : node_out_edges_[src_node]) {
+    if (sink_node == edge_sink_node(edge)) {
+      edges.push_back(edge);
+    }
+  }
+  return edges;
+}
+
 LbRRNodeId LbRRGraph::edge_src_node(const LbRREdgeId& edge) const {
   VTR_ASSERT(true == valid_edge_id(edge));
   return edge_src_nodes_[edge];
@@ -141,6 +172,16 @@ LbRRNodeId LbRRGraph::create_node(const e_lb_rr_type& type) {
   return node;
 }
 
+LbRRNodeId LbRRGraph::create_ext_source_node(const e_lb_rr_type& type) {
+  LbRRNodeId ext_source_node = create_node(type); 
+  ext_source_node_ = ext_source_node;
+}
+
+LbRRNodeId LbRRGraph::create_ext_sink_node(const e_lb_rr_type& type) {
+  LbRRNodeId ext_sink_node = create_node(type); 
+  ext_sink_node_ = ext_sink_node;
+}
+
 void LbRRGraph::set_node_type(const LbRRNodeId& node, const e_lb_rr_type& type) {
   VTR_ASSERT(true == valid_node_id(node));
   node_types_[node] = type;
diff --git a/openfpga/src/repack/lb_rr_graph.h b/openfpga/src/repack/lb_rr_graph.h
index c6cfbd552..a85bcd4c5 100644
--- a/openfpga/src/repack/lb_rr_graph.h
+++ b/openfpga/src/repack/lb_rr_graph.h
@@ -168,6 +168,9 @@ class LbRRGraph {
     typedef vtr::Range<node_iterator> node_range;
     typedef vtr::Range<edge_iterator> edge_range;
 
+  public: /* Constructors */
+    LbRRGraph();
+
   public: /* Accessors */
     /* Aggregates: create range-based loops for nodes/edges/switches/segments
      * To iterate over the nodes/edges/switches/segments in a RRGraph, 
@@ -195,13 +198,20 @@ class LbRRGraph {
     float node_intrinsic_cost(const LbRRNodeId& node) const;
 
     /* Get a list of edge ids, which are incoming edges to a node */
+    std::vector<LbRREdgeId> node_in_edges(const LbRRNodeId& node) const;
     std::vector<LbRREdgeId> node_in_edges(const LbRRNodeId& node, t_mode* mode) const;
 
     /* Get a list of edge ids, which are outgoing edges from a node */
     std::vector<LbRREdgeId> node_out_edges(const LbRRNodeId& node, t_mode* mode) const;
 
+    /* General method to look up a node with type and only pb_graph_pin information */
     LbRRNodeId find_node(const e_lb_rr_type& type, t_pb_graph_pin* pb_graph_pin) const;
+    /* Method to find special node */
+    LbRRNodeId ext_source_node() const;
+    LbRRNodeId ext_sink_node() const;
 
+    /* General method to look up a edge with source and sink nodes */
+    std::vector<LbRREdgeId> find_edge(const LbRRNodeId& src_node, const LbRRNodeId& sink_node) const;
     /* Get the source node which drives a edge */
     LbRRNodeId edge_src_node(const LbRREdgeId& edge) const;
     /* Get the sink node which a edge ends to */
@@ -234,6 +244,10 @@ class LbRRGraph {
      *   set_node_xlow(node, 0);
      */
     LbRRNodeId create_node(const e_lb_rr_type& type);
+  
+    /* Create special nodes */
+    LbRRNodeId create_ext_source_node(const e_lb_rr_type& type);
+    LbRRNodeId create_ext_sink_node(const e_lb_rr_type& type);
 
     /* Set node-level information */
     void set_node_type(const LbRRNodeId& node, const e_lb_rr_type& type);
@@ -289,6 +303,10 @@ class LbRRGraph {
      */
     typedef std::vector<std::map<t_pb_graph_pin*, LbRRNodeId>> NodeLookup;
     mutable NodeLookup node_lookup_;
+
+    /* Special node look-up */
+    LbRRNodeId ext_source_node_;
+    LbRRNodeId ext_sink_node_;
 };
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/repack/lb_rr_graph_utils.cpp b/openfpga/src/repack/lb_rr_graph_utils.cpp
new file mode 100644
index 000000000..665dace21
--- /dev/null
+++ b/openfpga/src/repack/lb_rr_graph_utils.cpp
@@ -0,0 +1,59 @@
+/***************************************************************************************
+ * This file includes most utilized functions for LbRRGraph object
+ ***************************************************************************************/
+
+/* Headers from vtrutil library */
+#include "vtr_log.h"
+#include "vtr_assert.h"
+
+#include "lb_rr_graph_utils.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/***************************************************************************************
+ * Generate a string to describe a node in a logical tile rr_graph
+ * in the context of logical tile
+ ***************************************************************************************/
+std::string describe_lb_rr_node(const LbRRGraph& lb_rr_graph,
+                                const LbRRNodeId& inode) {
+  std::string description;
+
+  const t_pb_graph_pin* pb_graph_pin = lb_rr_graph.node_pb_graph_pin(inode);
+
+  if (pb_graph_pin) {
+    description += "'" + pb_graph_pin->to_string(false) + "'";
+  } else if (inode == lb_rr_graph.ext_source_node()) {
+    VTR_ASSERT(LB_SOURCE == lb_rr_graph.node_type(inode));
+    description = "cluster-external source (LB_SOURCE)";
+  } else if (inode == lb_rr_graph.ext_sink_index()) {
+    VTR_ASSERT(LB_SINK == lb_rr_graph.node_type(inode));
+    description = "cluster-external sink (LB_SINK)";
+  } else if (LB_SINK == lb_rr_graph.node_type(inode)) {
+    description = "cluster-internal sink (LB_SINK accessible via architecture pins: ";
+
+    //To account for equivalent pins multiple pins may route to a single sink.
+    //As a result we need to fin all the nodes which connect to this sink in order
+    //to give user-friendly pin names
+    std::vector<std::string> pin_descriptions;
+    for (const LbRREdgeId edge : lb_rr_graph.node_in_edges(inode)) {
+      const LbRRNodeId pin_rr_idx = lb_rr_graph.edge_src_node(edge);
+      const t_pb_graph_pin* pin_pb_gpin = lb_rr_graph.node_pb_graph_pin(pin_rr_idx);
+      pin_descriptions.push_back(pin_pb_gpin->to_string());
+    }
+
+    description += vtr::join(pin_descriptions, ", ");
+    description += ")";
+
+  } else if (LB_SOURCE == lb_rr_graph.node_type(inode)) {
+    description = "cluster-internal source (LB_SOURCE)";
+  } else if (LB_INTERMEDIATE == lb_rr_graph.node_type(inode)) {
+    description = "cluster-internal intermediate?";
+  } else {
+    description = "<unknown lb_type_rr_node>";
+  }
+
+  return description;
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/repack/lb_rr_graph_utils.h b/openfpga/src/repack/lb_rr_graph_utils.h
new file mode 100644
index 000000000..392617f6a
--- /dev/null
+++ b/openfpga/src/repack/lb_rr_graph_utils.h
@@ -0,0 +1,22 @@
+#ifndef LB_RR_GRAPH_UTILS_H
+#define LB_RR_GRAPH_UTILS_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <string>
+#include "lb_rr_graph.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+std::string describe_lb_rr_node(const LbRRGraph& lb_rr_graph,
+                                const LbRRNodeId& inode);
+
+} /* end namespace openfpga */
+
+#endif

From 1799db810da4d9d6e8fa9991e881b98e4a6006f0 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 18 Feb 2020 17:04:36 -0700
Subject: [PATCH 172/645] compilation error fix

---
 openfpga/src/repack/lb_router.h           | 8 ++++----
 openfpga/src/repack/lb_rr_graph.cpp       | 6 +++---
 openfpga/src/repack/lb_rr_graph_utils.cpp | 3 ++-
 3 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/openfpga/src/repack/lb_router.h b/openfpga/src/repack/lb_router.h
index fe4c7d110..c0e575324 100644
--- a/openfpga/src/repack/lb_router.h
+++ b/openfpga/src/repack/lb_router.h
@@ -10,8 +10,7 @@
 
 #include "vtr_vector.h"
 
-#include "arch_types.h"
-#include "vpr_types.h"
+#include "physical_types.h"
 #include "atom_netlist_fwd.h"
 
 #include "lb_rr_graph.h"
@@ -41,7 +40,7 @@ class LbRouter {
      * Describes the status of a logic cluster_ctx.blocks routing resource node 
      * for a given logic cluster_ctx.blocks instance
      ***************************************************************************/
-    struct t_routing_stats {
+    struct t_routing_status {
       int occ;  /* Number of nets currently using this lb_rr_node */
       t_mode* mode; /* Mode that this rr_node is set to */
     
@@ -160,10 +159,11 @@ class LbRouter {
     std::map<AtomBlockId, bool> atoms_added_; /* map that records which atoms are added to cluster router */
 
     /* Logical-to-physical mapping info */
-    vtr::vector<LbRRNodeId, t_routing_stats> lb_rr_node_stats_; /* [0..lb_type_graph->size()-1] Stats for each logic cluster_ctx.blocks rr node instance */
+    vtr::vector<LbRRNodeId, t_routing_status> routing_status_; /* [0..lb_type_graph->size()-1] Stats for each logic cluster_ctx.blocks rr node instance */
 
     /* Stores state info during Pathfinder iterative routing */
     vtr::vector<LbRRNodeId, t_explored_node_stats> explored_node_tb_; /* [0..lb_type_graph->size()-1] Stores mode exploration and traceback info for nodes */
+
     int explore_id_index_;                 /* used in conjunction with node_traceback to determine whether or not a location has been explored.  By using a unique identifier every route, I don't have to clear the previous route exploration */
 
     /* Current type */
diff --git a/openfpga/src/repack/lb_rr_graph.cpp b/openfpga/src/repack/lb_rr_graph.cpp
index 712acd50b..581edd905 100644
--- a/openfpga/src/repack/lb_rr_graph.cpp
+++ b/openfpga/src/repack/lb_rr_graph.cpp
@@ -94,15 +94,15 @@ LbRRNodeId LbRRGraph::find_node(const e_lb_rr_type& type, t_pb_graph_pin* pb_gra
   return node_lookup_[size_t(type)].at(pb_graph_pin);
 }
 
-LbRRNodeId ext_source_node() const {
+LbRRNodeId LbRRGraph::ext_source_node() const {
   return ext_source_node_;
 }
 
-LbRRNodeId ext_sink_node() const {
+LbRRNodeId LbRRGraph::ext_sink_node() const {
   return ext_sink_node_;
 }
 
-std::vector<LbRREdgeId> find_edge(const LbRRNodeId& src_node, const LbRRNodeId& sink_node) const {
+std::vector<LbRREdgeId> LbRRGraph::find_edge(const LbRRNodeId& src_node, const LbRRNodeId& sink_node) const {
   std::vector<LbRREdgeId> edges;
   for (const LbRREdgeId& edge : node_out_edges_[src_node]) {
     if (sink_node == edge_sink_node(edge)) {
diff --git a/openfpga/src/repack/lb_rr_graph_utils.cpp b/openfpga/src/repack/lb_rr_graph_utils.cpp
index 665dace21..351103647 100644
--- a/openfpga/src/repack/lb_rr_graph_utils.cpp
+++ b/openfpga/src/repack/lb_rr_graph_utils.cpp
@@ -5,6 +5,7 @@
 /* Headers from vtrutil library */
 #include "vtr_log.h"
 #include "vtr_assert.h"
+#include "vtr_util.h"
 
 #include "lb_rr_graph_utils.h"
 
@@ -26,7 +27,7 @@ std::string describe_lb_rr_node(const LbRRGraph& lb_rr_graph,
   } else if (inode == lb_rr_graph.ext_source_node()) {
     VTR_ASSERT(LB_SOURCE == lb_rr_graph.node_type(inode));
     description = "cluster-external source (LB_SOURCE)";
-  } else if (inode == lb_rr_graph.ext_sink_index()) {
+  } else if (inode == lb_rr_graph.ext_sink_node()) {
     VTR_ASSERT(LB_SINK == lb_rr_graph.node_type(inode));
     description = "cluster-external sink (LB_SINK)";
   } else if (LB_SINK == lb_rr_graph.node_type(inode)) {

From 0310dafe423edf0bb363da6a8b96a9a17bd0ca2a Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 18 Feb 2020 18:35:00 -0700
Subject: [PATCH 173/645] add accessors to LBRouter

---
 openfpga/src/repack/lb_router.cpp | 26 ++++++++++++++++++++++++++
 openfpga/src/repack/lb_router.h   | 15 +++++++++++----
 2 files changed, 37 insertions(+), 4 deletions(-)
 create mode 100644 openfpga/src/repack/lb_router.cpp

diff --git a/openfpga/src/repack/lb_router.cpp b/openfpga/src/repack/lb_router.cpp
new file mode 100644
index 000000000..be2cbe37f
--- /dev/null
+++ b/openfpga/src/repack/lb_router.cpp
@@ -0,0 +1,26 @@
+/******************************************************************************
+ * Memember functions for data structure LbRouter
+ ******************************************************************************/
+#include "vtr_assert.h"
+
+#include "lb_router.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/**************************************************
+ * Public Accessors 
+ *************************************************/
+std::vector<LbRRNodeId> LbRouter::find_congested_rr_nodes(const LbRRGraph& lb_rr_graph) const {
+  std::vector<LbRRNodeId> congested_rr_nodes;
+
+  for (const LbRRNodeId& inode : lb_rr_graph.nodes()) {
+    if (routing_status_[inode].occ > lb_rr_graph.node_capacity(inode)) {
+      congested_rr_nodes.push_back(inode);
+    }
+  }
+
+  return congested_rr_nodes;
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/repack/lb_router.h b/openfpga/src/repack/lb_router.h
index c0e575324..ae45afba5 100644
--- a/openfpga/src/repack/lb_router.h
+++ b/openfpga/src/repack/lb_router.h
@@ -46,7 +46,7 @@ class LbRouter {
     
       int historical_usage; /* Historical usage of using this node */
     
-      t_lb_rr_graph_stats() {
+      t_routing_status() {
         occ = 0;
         mode = nullptr;
         historical_usage = 0;
@@ -61,7 +61,7 @@ class LbRouter {
      ***************************************************************************/
     struct t_trace {
       LbRRNodeId current_node;            /* current t_lb_type_rr_node used by net */
-      std::vector<t_lb_trace> next_nodes; /* index of previous edge that drives current node */
+      std::vector<t_trace> next_nodes; /* index of previous edge that drives current node */
     };
 
     /**************************************************************************
@@ -73,9 +73,9 @@ class LbRouter {
       std::vector<LbRRNodeId> terminals; /* endpoints of the intra_lb_net, 0th position is the source, all others are sinks */
       std::vector<AtomPinId> atom_pins;  /* AtomPin's associated with each terminal */
       std::vector<bool> fixed_terminals; /* Marks a terminal as having a fixed target (i.e. a pin not a sink) */
-      t_lb_trace* rt_tree;               /* Route tree head */
+      t_trace* rt_tree;               /* Route tree head */
     
-      t_lb_rr_net() {
+      t_net() {
           atom_net_id = AtomNetId::INVALID();
           rt_tree = nullptr;
       }
@@ -148,6 +148,13 @@ class LbRouter {
         return is_mode_conflict || try_expand_all_modes;
       }
     };
+  
+  public :  /* Public accessors */
+    /**
+     * Find all the routing resource nodes that is congested, which they are used more than their capacity
+     * This function is call to collect the nodes and router can reroute these net
+     */   
+    std::vector<LbRRNodeId> find_congested_rr_nodes(const LbRRGraph& lb_rr_graph) const;
 
   private : /* Stores all data needed by intra-logic cluster_ctx.blocks router */
     /* Logical Netlist Info */

From 11879d43b404db02c46a8903003b0ef529819a84 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 18 Feb 2020 19:22:36 -0700
Subject: [PATCH 174/645] add methods one by one to LbRouter from
 cluster_router.cpp

---
 openfpga/src/repack/lb_router.cpp | 106 ++++++++++++++++++++++++++++++
 openfpga/src/repack/lb_router.h   |  31 ++++++++-
 2 files changed, 134 insertions(+), 3 deletions(-)

diff --git a/openfpga/src/repack/lb_router.cpp b/openfpga/src/repack/lb_router.cpp
index be2cbe37f..f362ce34a 100644
--- a/openfpga/src/repack/lb_router.cpp
+++ b/openfpga/src/repack/lb_router.cpp
@@ -2,16 +2,37 @@
  * Memember functions for data structure LbRouter
  ******************************************************************************/
 #include "vtr_assert.h"
+#include "vtr_log.h"
 
 #include "lb_router.h"
 
 /* begin namespace openfpga */
 namespace openfpga {
 
+/**************************************************
+ * Public Constructors
+ *************************************************/
+LbRouter::LbRouter(const LbRRGraph& lb_rr_graph) {
+  routing_status_.resize(lb_rr_graph.nodes().size());
+  explored_node_tb_.resize(lb_rr_graph.nodes().size());
+  explore_id_index_ = 1;
+
+  /* Default routing parameters */
+  params_.max_iterations = 50;
+  params_.pres_fac = 1;
+  params_.pres_fac_mult = 2;
+  params_.hist_fac = 0.3;
+ 
+  pres_con_fac_ = 1;
+}
+
 /**************************************************
  * Public Accessors 
  *************************************************/
 std::vector<LbRRNodeId> LbRouter::find_congested_rr_nodes(const LbRRGraph& lb_rr_graph) const {
+  /* Validate if the rr_graph is the one we used to initialize the router */
+  VTR_ASSERT(true == matched_lb_rr_graph(lb_rr_graph));
+
   std::vector<LbRRNodeId> congested_rr_nodes;
 
   for (const LbRRNodeId& inode : lb_rr_graph.nodes()) {
@@ -23,4 +44,89 @@ std::vector<LbRRNodeId> LbRouter::find_congested_rr_nodes(const LbRRGraph& lb_rr
   return congested_rr_nodes;
 }
 
+bool LbRouter::is_route_success(const LbRRGraph& lb_rr_graph) const {
+  /* Validate if the rr_graph is the one we used to initialize the router */
+  VTR_ASSERT(true == matched_lb_rr_graph(lb_rr_graph));
+
+  for (const LbRRNodeId& inode : lb_rr_graph.nodes()) {
+    if (routing_status_[inode].occ > lb_rr_graph.node_capacity(inode)) {
+      return false;
+    }
+  }
+
+  return true;
+}
+
+/**************************************************
+ * Private accessors
+ *************************************************/
+LbRouter::t_trace* LbRouter::find_node_in_rt(t_trace* rt, const LbRRNodeId& rt_index) {
+  t_trace* cur;
+  if (rt->current_node == rt_index) {
+    return rt;
+  } else {
+    for (unsigned int i = 0; i < rt->next_nodes.size(); i++) {
+      cur = find_node_in_rt(&rt->next_nodes[i], rt_index);
+      if (cur != nullptr) {
+        return cur;
+      }
+    }
+  }
+  return nullptr;
+}
+
+/**************************************************
+ * Private mutators
+ *************************************************/
+void LbRouter::reset_explored_node_tb() {
+  for (t_explored_node_stats& explored_node : explored_node_tb_) {
+    explored_node.prev_index = LbRRNodeId::INVALID();
+    explored_node.explored_id = OPEN;
+    explored_node.inet = OPEN;
+    explored_node.enqueue_id = OPEN;
+    explored_node.enqueue_cost = 0;
+  }
+}
+
+bool LbRouter::add_to_rt(t_trace* rt, const LbRRNodeId& node_index, const int& irt_net) {
+  std::vector<LbRRNodeId> trace_forward;
+  t_trace* link_node;
+  t_trace curr_node;
+
+  /* Store path all the way back to route tree */
+  LbRRNodeId rt_index = node_index;
+  while (explored_node_tb_[rt_index].inet != irt_net) {
+    trace_forward.push_back(rt_index);
+    rt_index = explored_node_tb_[rt_index].prev_index;
+    VTR_ASSERT(rt_index != LbRRNodeId::INVALID());
+  }
+
+  /* Find rt_index on the route tree */
+  link_node = find_node_in_rt(rt, rt_index);
+  if (link_node == nullptr) {
+    VTR_LOG("Link node is nullptr. Routing impossible");
+    return true;
+  }
+
+  /* Add path to root tree */
+  LbRRNodeId trace_index;
+  while (!trace_forward.empty()) {
+    trace_index = trace_forward.back();
+    curr_node.current_node = trace_index;
+    link_node->next_nodes.push_back(curr_node);
+    link_node = &link_node->next_nodes.back();
+    trace_forward.pop_back();
+  }
+
+  return false;
+}
+
+/**************************************************
+ * Private validators
+ *************************************************/
+bool LbRouter::matched_lb_rr_graph(const LbRRGraph& lb_rr_graph) const {
+  return ( (routing_status_.size() == lb_rr_graph.nodes().size())
+        && (explored_node_tb_.size() == lb_rr_graph.nodes().size()) );
+}
+
 } /* end namespace openfpga */
diff --git a/openfpga/src/repack/lb_router.h b/openfpga/src/repack/lb_router.h
index ae45afba5..e5f1ba432 100644
--- a/openfpga/src/repack/lb_router.h
+++ b/openfpga/src/repack/lb_router.h
@@ -148,17 +148,42 @@ class LbRouter {
         return is_mode_conflict || try_expand_all_modes;
       }
     };
+
+  public :  /* Public constructors */
+    LbRouter(const LbRRGraph& lb_rr_graph);
   
   public :  /* Public accessors */
     /**
-     * Find all the routing resource nodes that is congested, which they are used more than their capacity
+     * Find all the routing resource nodes that are over-used, which they are used more than their capacity
      * This function is call to collect the nodes and router can reroute these net
      */   
     std::vector<LbRRNodeId> find_congested_rr_nodes(const LbRRGraph& lb_rr_graph) const;
 
+    /**
+     * Report if the routing is successfully done on a logical block routing resource graph
+     */  
+    bool is_route_success(const LbRRGraph& lb_rr_graph) const;
+
+  private :  /* Private accessors */
+    /**
+     * Try to find a node in the routing traces recursively
+     * If not found, will return an empty pointer
+     */
+    t_trace* find_node_in_rt(t_trace* rt, const LbRRNodeId& rt_index);
+
+  private : /* Private mutators */
+    void reset_explored_node_tb();
+    bool add_to_rt(t_trace* rt, const LbRRNodeId& node_index, const int& irt_net);
+
+  private :  /* Private validators */
+    /** 
+     * Validate if the rr_graph is the one we used to initialize the router 
+     */
+    bool matched_lb_rr_graph(const LbRRGraph& lb_rr_graph) const;
+
   private : /* Stores all data needed by intra-logic cluster_ctx.blocks router */
     /* Logical Netlist Info */
-    std::vector<t_net> intra_lb_nets_; /* Pointer to vector of intra logic cluster_ctx.blocks nets and their connections */
+    std::vector<t_net> lb_nets_; /* Pointer to vector of intra logic cluster_ctx.blocks nets and their connections */
 
     /* Saved nets */
     std::vector<t_net> saved_lb_nets_; /* Save vector of intra logic cluster_ctx.blocks nets and their connections */
@@ -177,7 +202,7 @@ class LbRouter {
     t_logical_block_type_ptr lb_type_;
 
     /* Parameters used by router */
-    t_option options_;
+    t_option params_;
 
     bool is_routed_;                       /* Stores whether or not the current logical-to-physical mapping has a routed solution */
 

From c7ef14fc23517859a7b15cae30f518edb767bad7 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 18 Feb 2020 21:51:03 -0700
Subject: [PATCH 175/645] refactoring node expansion in LbRouter

---
 openfpga/src/repack/lb_router.cpp   | 116 ++++++++++++++++++++++++++++
 openfpga/src/repack/lb_router.h     |  42 ++++++++++
 openfpga/src/repack/lb_rr_graph.cpp |   9 +++
 openfpga/src/repack/lb_rr_graph.h   |   1 +
 4 files changed, 168 insertions(+)

diff --git a/openfpga/src/repack/lb_router.cpp b/openfpga/src/repack/lb_router.cpp
index f362ce34a..63fc0105b 100644
--- a/openfpga/src/repack/lb_router.cpp
+++ b/openfpga/src/repack/lb_router.cpp
@@ -1,6 +1,8 @@
 /******************************************************************************
  * Memember functions for data structure LbRouter
  ******************************************************************************/
+#include <queue>
+
 #include "vtr_assert.h"
 #include "vtr_log.h"
 
@@ -121,6 +123,120 @@ bool LbRouter::add_to_rt(t_trace* rt, const LbRRNodeId& node_index, const int& i
   return false;
 }
 
+void LbRouter::expand_edges(const LbRRGraph& lb_rr_graph,
+                            t_mode* mode,
+                            const LbRRNodeId& cur_inode,
+                            float cur_cost,
+                            int net_fanout,
+                            reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq) {
+  /* Validate if the rr_graph is the one we used to initialize the router */
+  VTR_ASSERT(true == matched_lb_rr_graph(lb_rr_graph));
+
+  t_expansion_node enode;
+  int usage;
+  float incr_cost;
+
+  for (const LbRREdgeId& iedge : lb_rr_graph.node_out_edges(cur_inode, mode)) {
+    /* Init new expansion node */
+    enode.prev_index = cur_inode;
+    enode.node_index = lb_rr_graph.edge_sink_node(iedge);
+    enode.cost = cur_cost;
+
+    /* Determine incremental cost of using expansion node */
+    usage = routing_status_[enode.node_index].occ + 1 - lb_rr_graph.node_capacity(enode.node_index);
+    incr_cost = lb_rr_graph.node_intrinsic_cost(enode.node_index);
+    incr_cost += lb_rr_graph.edge_intrinsic_cost(iedge);
+    incr_cost += params_.hist_fac * routing_status_[enode.node_index].historical_usage;
+    if (usage > 0) {
+      incr_cost *= (usage * pres_con_fac_);
+    }
+
+    /* Adjust cost so that higher fanout nets prefer higher fanout routing nodes while lower fanout nets prefer lower fanout routing nodes */
+    float fanout_factor = 1.0;
+    t_mode* next_mode = routing_status_[enode.node_index].mode;
+    /* Assume first mode if a mode hasn't been forced. */
+    if (nullptr == next_mode) {
+      next_mode = &(lb_rr_graph.node_pb_graph_pin(enode.node_index)->parent_node->pb_type->modes[0]);
+    }
+    if (lb_rr_graph.node_out_edges(enode.node_index, next_mode).size() > 1) {
+      fanout_factor = 0.85 + (0.25 / net_fanout);
+    } else {
+      fanout_factor = 1.15 - (0.25 / net_fanout);
+    }
+
+    incr_cost *= fanout_factor;
+    enode.cost = cur_cost + incr_cost;
+
+    /* Add to queue if cost is lower than lowest cost path to this enode */
+    if (explored_node_tb_[enode.node_index].enqueue_id == explore_id_index_) {
+      if (enode.cost < explored_node_tb_[enode.node_index].enqueue_cost) {
+        pq.push(enode);
+      }
+    } else {
+      explored_node_tb_[enode.node_index].enqueue_id = explore_id_index_;
+      explored_node_tb_[enode.node_index].enqueue_cost = enode.cost;
+      pq.push(enode);
+    }
+  }
+}
+
+void LbRouter::expand_node(const LbRRGraph& lb_rr_graph,
+                           const t_expansion_node& exp_node,
+                           reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq,
+                           const int& net_fanout) {
+  /* Validate if the rr_graph is the one we used to initialize the router */
+  VTR_ASSERT(true == matched_lb_rr_graph(lb_rr_graph));
+
+  t_expansion_node enode;
+
+  LbRRNodeId cur_node = exp_node.node_index;
+  float cur_cost = exp_node.cost;
+  t_mode* mode = routing_status_[cur_node].mode;
+  if (nullptr == mode) {
+    mode = &(lb_rr_graph.node_pb_graph_pin(cur_node)->parent_node->pb_type->modes[0]);
+  }
+
+  expand_edges(lb_rr_graph, mode, cur_node, cur_cost, net_fanout, pq);
+}
+
+void LbRouter::expand_node_all_modes(const LbRRGraph& lb_rr_graph,
+                                     const t_expansion_node& exp_node,
+                                     reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq, 
+                                     const int& net_fanout) {
+  /* Validate if the rr_graph is the one we used to initialize the router */
+  VTR_ASSERT(true == matched_lb_rr_graph(lb_rr_graph));
+
+  LbRRNodeId cur_inode = exp_node.node_index;
+  float cur_cost = exp_node.cost;
+  t_mode* cur_mode = routing_status_[cur_inode].mode;
+  auto* pin = lb_rr_graph.node_pb_graph_pin(cur_inode);
+
+  for (const LbRREdgeId& edge : lb_rr_graph.node_out_edges(cur_inode)) {
+    t_mode* mode = lb_rr_graph.edge_mode(edge);
+    /* If a mode has been forced, only add edges from that mode, otherwise add edges from all modes. */
+    if (cur_mode != nullptr && mode != cur_mode) {
+      continue;
+    }
+
+    /* Check whether a mode is illegal. If it is then the node will not be expanded */
+    bool is_illegal = false;
+    if (pin != nullptr) {
+      auto* pb_graph_node = pin->parent_node;
+      for (auto illegal_mode : pb_graph_node->illegal_modes) {
+        if (mode->index == illegal_mode) {
+          is_illegal = true;
+          break;
+        }
+      }
+    }
+
+    if (is_illegal == true) {
+      continue;
+    }
+    expand_edges(lb_rr_graph, mode, cur_inode, cur_cost, net_fanout, pq);
+  }
+}
+
 /**************************************************
  * Private validators
  *************************************************/
diff --git a/openfpga/src/repack/lb_router.h b/openfpga/src/repack/lb_router.h
index e5f1ba432..51778df91 100644
--- a/openfpga/src/repack/lb_router.h
+++ b/openfpga/src/repack/lb_router.h
@@ -149,6 +149,34 @@ class LbRouter {
       }
     };
 
+    // TODO: check if this hacky class memory reserve thing is still necessary, if not, then delete
+    /* Packing uses a priority queue that requires a large number of elements.  
+     * This backdoor
+     * allows me to use a priority queue where I can pre-allocate the # of elements 
+     * in the underlying container
+     * for efficiency reasons.  Note: Must use vector with this
+     */
+    template<class T, class U, class V>
+    class reservable_pq : public std::priority_queue<T, U, V> {
+      public:
+        typedef typename std::priority_queue<T>::size_type size_type;
+        reservable_pq(size_type capacity = 0) {
+            reserve(capacity);
+            cur_cap = capacity;
+        }
+        void reserve(size_type capacity) {
+            this->c.reserve(capacity);
+            cur_cap = capacity;
+        }
+        void clear() {
+            this->c.clear();
+            this->c.reserve(cur_cap);
+        }
+
+      private:
+        size_type cur_cap;
+    };
+
   public :  /* Public constructors */
     LbRouter(const LbRRGraph& lb_rr_graph);
   
@@ -174,6 +202,20 @@ class LbRouter {
   private : /* Private mutators */
     void reset_explored_node_tb();
     bool add_to_rt(t_trace* rt, const LbRRNodeId& node_index, const int& irt_net);
+    void expand_edges(const LbRRGraph& lb_rr_graph,
+                      t_mode* mode,
+                      const LbRRNodeId& cur_inode,
+                      float cur_cost,
+                      int net_fanout,
+                      reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq);
+    void expand_node(const LbRRGraph& lb_rr_graph,
+                     const t_expansion_node& exp_node,
+                     reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq,
+                     const int& net_fanout);
+    void expand_node_all_modes(const LbRRGraph& lb_rr_graph,
+                               const t_expansion_node& exp_node,
+                               reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq, 
+                               const int& net_fanout);
 
   private :  /* Private validators */
     /** 
diff --git a/openfpga/src/repack/lb_rr_graph.cpp b/openfpga/src/repack/lb_rr_graph.cpp
index 581edd905..3645e60e6 100644
--- a/openfpga/src/repack/lb_rr_graph.cpp
+++ b/openfpga/src/repack/lb_rr_graph.cpp
@@ -69,6 +69,11 @@ std::vector<LbRREdgeId> LbRRGraph::node_in_edges(const LbRRNodeId& node, t_mode*
   return in_edges;
 }
 
+std::vector<LbRREdgeId> LbRRGraph::node_out_edges(const LbRRNodeId& node) const {
+  VTR_ASSERT(true == valid_node_id(node));
+  return node_out_edges_[node];
+}
+
 std::vector<LbRREdgeId> LbRRGraph::node_out_edges(const LbRRNodeId& node, t_mode* mode) const {
   std::vector<LbRREdgeId> out_edges;
 
@@ -175,11 +180,15 @@ LbRRNodeId LbRRGraph::create_node(const e_lb_rr_type& type) {
 LbRRNodeId LbRRGraph::create_ext_source_node(const e_lb_rr_type& type) {
   LbRRNodeId ext_source_node = create_node(type); 
   ext_source_node_ = ext_source_node;
+
+  return ext_source_node;
 }
 
 LbRRNodeId LbRRGraph::create_ext_sink_node(const e_lb_rr_type& type) {
   LbRRNodeId ext_sink_node = create_node(type); 
   ext_sink_node_ = ext_sink_node;
+
+  return ext_sink_node;
 }
 
 void LbRRGraph::set_node_type(const LbRRNodeId& node, const e_lb_rr_type& type) {
diff --git a/openfpga/src/repack/lb_rr_graph.h b/openfpga/src/repack/lb_rr_graph.h
index a85bcd4c5..e75d866b3 100644
--- a/openfpga/src/repack/lb_rr_graph.h
+++ b/openfpga/src/repack/lb_rr_graph.h
@@ -202,6 +202,7 @@ class LbRRGraph {
     std::vector<LbRREdgeId> node_in_edges(const LbRRNodeId& node, t_mode* mode) const;
 
     /* Get a list of edge ids, which are outgoing edges from a node */
+    std::vector<LbRREdgeId> node_out_edges(const LbRRNodeId& node) const;
     std::vector<LbRREdgeId> node_out_edges(const LbRRNodeId& node, t_mode* mode) const;
 
     /* General method to look up a node with type and only pb_graph_pin information */

From 289c869caff4b7e97661e35a0ad38ac837153cb2 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 18 Feb 2020 22:01:22 -0700
Subject: [PATCH 176/645] refactored expand rt_node in LbRouter

---
 openfpga/src/repack/lb_router.cpp | 31 +++++++++++++++++++++++++++++++
 openfpga/src/repack/lb_router.h   |  8 ++++++++
 2 files changed, 39 insertions(+)

diff --git a/openfpga/src/repack/lb_router.cpp b/openfpga/src/repack/lb_router.cpp
index 63fc0105b..16c7f8f35 100644
--- a/openfpga/src/repack/lb_router.cpp
+++ b/openfpga/src/repack/lb_router.cpp
@@ -123,6 +123,37 @@ bool LbRouter::add_to_rt(t_trace* rt, const LbRRNodeId& node_index, const int& i
   return false;
 }
 
+void LbRouter::expand_rt_rec(t_trace* rt,
+                             const LbRRNodeId& prev_index, 
+                             reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq,
+                             const int& irt_net,
+                             const int& explore_id_index) {
+  t_expansion_node enode;
+
+  /* Perhaps should use a cost other than zero */
+  enode.cost = 0;
+  enode.node_index = rt->current_node;
+  enode.prev_index = prev_index;
+  pq.push(enode);
+  explored_node_tb_[enode.node_index].inet = irt_net;
+  explored_node_tb_[enode.node_index].explored_id = OPEN;
+  explored_node_tb_[enode.node_index].enqueue_id = explore_id_index;
+  explored_node_tb_[enode.node_index].enqueue_cost = 0;
+  explored_node_tb_[enode.node_index].prev_index = prev_index;
+
+  for (unsigned int i = 0; i < rt->next_nodes.size(); i++) {
+    expand_rt_rec(&rt->next_nodes[i], rt->current_node, pq, irt_net, explore_id_index);
+  }
+}
+
+void LbRouter::expand_rt(const int& inet,
+                         reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq,
+                         const int& irt_net) {
+  VTR_ASSERT(pq.empty());
+
+  expand_rt_rec(lb_nets_[inet].rt_tree, LbRRNodeId::INVALID(), pq, irt_net, explore_id_index_);
+}
+
 void LbRouter::expand_edges(const LbRRGraph& lb_rr_graph,
                             t_mode* mode,
                             const LbRRNodeId& cur_inode,
diff --git a/openfpga/src/repack/lb_router.h b/openfpga/src/repack/lb_router.h
index 51778df91..1d07954df 100644
--- a/openfpga/src/repack/lb_router.h
+++ b/openfpga/src/repack/lb_router.h
@@ -202,6 +202,14 @@ class LbRouter {
   private : /* Private mutators */
     void reset_explored_node_tb();
     bool add_to_rt(t_trace* rt, const LbRRNodeId& node_index, const int& irt_net);
+    void expand_rt_rec(t_trace* rt,
+                       const LbRRNodeId& prev_index, 
+                       reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq,
+                       const int& irt_net,
+                       const int& explore_id_index);
+    void expand_rt(const int& inet,
+                   reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq,
+                   const int& irt_net);
     void expand_edges(const LbRRGraph& lb_rr_graph,
                       t_mode* mode,
                       const LbRRNodeId& cur_inode,

From 80fa6f8a0a2994bec31a791679146f2a59620543 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 18 Feb 2020 22:08:51 -0700
Subject: [PATCH 177/645] refactored skip nets in LbRouter

---
 openfpga/src/repack/lb_router.cpp | 53 +++++++++++++++++++++++++++----
 openfpga/src/repack/lb_router.h   |  6 +++-
 2 files changed, 51 insertions(+), 8 deletions(-)

diff --git a/openfpga/src/repack/lb_router.cpp b/openfpga/src/repack/lb_router.cpp
index 16c7f8f35..267d8d3f9 100644
--- a/openfpga/src/repack/lb_router.cpp
+++ b/openfpga/src/repack/lb_router.cpp
@@ -80,14 +80,32 @@ LbRouter::t_trace* LbRouter::find_node_in_rt(t_trace* rt, const LbRRNodeId& rt_i
 /**************************************************
  * Private mutators
  *************************************************/
-void LbRouter::reset_explored_node_tb() {
-  for (t_explored_node_stats& explored_node : explored_node_tb_) {
-    explored_node.prev_index = LbRRNodeId::INVALID();
-    explored_node.explored_id = OPEN;
-    explored_node.inet = OPEN;
-    explored_node.enqueue_id = OPEN;
-    explored_node.enqueue_cost = 0;
+bool LbRouter::is_skip_route_net(const LbRRGraph& lb_rr_graph,
+                                 t_trace* rt) {
+  /* Validate if the rr_graph is the one we used to initialize the router */
+  VTR_ASSERT(true == matched_lb_rr_graph(lb_rr_graph));
+
+  if (rt == nullptr) {
+    return false; /* Net is not routed, therefore must route net */
   }
+
+  LbRRNodeId inode = rt->current_node;
+
+  /* Determine if node is overused */
+  if (routing_status_[inode].occ > lb_rr_graph.node_capacity(inode)) {
+    /* Conflict between this net and another net at this node, reroute net */
+    return false;
+  }
+
+  /* Recursively check that rest of route tree does not have a conflict */
+  for (unsigned int i = 0; i < rt->next_nodes.size(); i++) {
+    if (!is_skip_route_net(lb_rr_graph, &rt->next_nodes[i])) {
+      return false;
+    }
+  }
+
+  /* No conflict, this net's current route is legal, skip routing this net */
+  return true;
 }
 
 bool LbRouter::add_to_rt(t_trace* rt, const LbRRNodeId& node_index, const int& irt_net) {
@@ -123,6 +141,13 @@ bool LbRouter::add_to_rt(t_trace* rt, const LbRRNodeId& node_index, const int& i
   return false;
 }
 
+void LbRouter::add_source_to_rt(const int& inet) {
+  /* TODO: Validate net id */
+  VTR_ASSERT(nullptr == lb_nets_[inet].rt_tree);
+  lb_nets_[inet].rt_tree = new t_trace;
+  lb_nets_[inet].rt_tree->current_node = lb_nets_[inet].terminals[0];
+}
+
 void LbRouter::expand_rt_rec(t_trace* rt,
                              const LbRRNodeId& prev_index, 
                              reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq,
@@ -276,4 +301,18 @@ bool LbRouter::matched_lb_rr_graph(const LbRRGraph& lb_rr_graph) const {
         && (explored_node_tb_.size() == lb_rr_graph.nodes().size()) );
 }
 
+/**************************************************
+ * Private Initializer and cleaner
+ *************************************************/
+void LbRouter::reset_explored_node_tb() {
+  for (t_explored_node_stats& explored_node : explored_node_tb_) {
+    explored_node.prev_index = LbRRNodeId::INVALID();
+    explored_node.explored_id = OPEN;
+    explored_node.inet = OPEN;
+    explored_node.enqueue_id = OPEN;
+    explored_node.enqueue_cost = 0;
+  }
+}
+
+
 } /* end namespace openfpga */
diff --git a/openfpga/src/repack/lb_router.h b/openfpga/src/repack/lb_router.h
index 1d07954df..92aca94c1 100644
--- a/openfpga/src/repack/lb_router.h
+++ b/openfpga/src/repack/lb_router.h
@@ -200,8 +200,9 @@ class LbRouter {
     t_trace* find_node_in_rt(t_trace* rt, const LbRRNodeId& rt_index);
 
   private : /* Private mutators */
-    void reset_explored_node_tb();
+    bool is_skip_route_net(const LbRRGraph& lb_rr_graph, t_trace* rt);
     bool add_to_rt(t_trace* rt, const LbRRNodeId& node_index, const int& irt_net);
+    void add_source_to_rt(const int& inet);
     void expand_rt_rec(t_trace* rt,
                        const LbRRNodeId& prev_index, 
                        reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq,
@@ -231,6 +232,9 @@ class LbRouter {
      */
     bool matched_lb_rr_graph(const LbRRGraph& lb_rr_graph) const;
 
+  private :  /* Private initializer and cleaner */
+    void reset_explored_node_tb();
+
   private : /* Stores all data needed by intra-logic cluster_ctx.blocks router */
     /* Logical Netlist Info */
     std::vector<t_net> lb_nets_; /* Pointer to vector of intra logic cluster_ctx.blocks nets and their connections */

From 3d5a15d41e0087a413722c7bd2752e726640d037 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 19 Feb 2020 00:07:36 -0700
Subject: [PATCH 178/645] refactored most functions except echo and try_route()
 in LbRouter

---
 openfpga/src/repack/lb_router.cpp   | 226 +++++++++++++++++++++++++++-
 openfpga/src/repack/lb_router.h     |  36 ++++-
 openfpga/src/repack/lb_rr_graph.cpp |   2 +-
 openfpga/src/repack/lb_rr_graph.h   |   4 +-
 4 files changed, 263 insertions(+), 5 deletions(-)

diff --git a/openfpga/src/repack/lb_router.cpp b/openfpga/src/repack/lb_router.cpp
index 267d8d3f9..fece00596 100644
--- a/openfpga/src/repack/lb_router.cpp
+++ b/openfpga/src/repack/lb_router.cpp
@@ -6,6 +6,11 @@
 #include "vtr_assert.h"
 #include "vtr_log.h"
 
+#include "physical_types.h"
+#include "pb_type_graph.h"
+#include "vpr_error.h"
+
+#include "lb_rr_graph_utils.h"
 #include "lb_router.h"
 
 /* begin namespace openfpga */
@@ -77,9 +82,172 @@ LbRouter::t_trace* LbRouter::find_node_in_rt(t_trace* rt, const LbRRNodeId& rt_i
   return nullptr;
 }
 
+bool LbRouter::route_has_conflict(const LbRRGraph& lb_rr_graph, t_trace* rt) const {
+  t_mode* cur_mode = nullptr;
+  for (unsigned int i = 0; i < rt->next_nodes.size(); i++) {
+    std::vector<LbRREdgeId> edges = lb_rr_graph.find_edge(rt->current_node, rt->next_nodes[i].current_node);
+    VTR_ASSERT(0 == edges.size());
+    t_mode* new_mode = lb_rr_graph.edge_mode(edges[0]);
+    if (cur_mode != nullptr && cur_mode != new_mode) {
+      return true;
+    }
+    if (route_has_conflict(lb_rr_graph, &rt->next_nodes[i]) == true) {
+      return true;
+    }
+    cur_mode = new_mode;
+  }
+
+  return false;
+}
+
 /**************************************************
  * Private mutators
  *************************************************/
+void LbRouter::fix_duplicate_equivalent_pins(const AtomContext& atom_ctx,
+                                             const LbRRGraph& lb_rr_graph) {
+  for (size_t ilb_net = 0; ilb_net < lb_nets_.size(); ++ilb_net) {
+    //Collect all the sink terminals indicies which target a particular node
+    std::map<LbRRNodeId, std::vector<int>> duplicate_terminals;
+    for (size_t iterm = 1; iterm < lb_nets_[ilb_net].terminals.size(); ++iterm) {
+      LbRRNodeId node = lb_nets_[ilb_net].terminals[iterm];
+
+      duplicate_terminals[node].push_back(iterm);
+    }
+
+    for (auto kv : duplicate_terminals) {
+      if (kv.second.size() < 2) continue; //Only process duplicates
+
+      //Remap all the duplicate terminals so they target the pin instead of the sink
+      for (size_t idup_term = 0; idup_term < kv.second.size(); ++idup_term) {
+        int iterm = kv.second[idup_term]; //The index in terminals which is duplicated
+
+        VTR_ASSERT(lb_nets_[ilb_net].atom_pins.size() == lb_nets_[ilb_net].terminals.size());
+        AtomPinId atom_pin = lb_nets_[ilb_net].atom_pins[iterm];
+        VTR_ASSERT(atom_pin);
+
+        const t_pb_graph_pin* pb_graph_pin = find_pb_graph_pin(atom_ctx.nlist, atom_ctx.lookup, atom_pin);
+        VTR_ASSERT(pb_graph_pin);
+
+        if (pb_graph_pin->port->equivalent == PortEquivalence::NONE) continue; //Only need to remap equivalent ports
+
+        //Remap this terminal to an explicit pin instead of the common sink
+        LbRRNodeId pin_index = lb_rr_graph.find_node(LB_INTERMEDIATE, pb_graph_pin);
+        VTR_ASSERT(true == lb_rr_graph.valid_node_id(pin_index));
+
+        VTR_LOG_WARN(
+            "Found duplicate nets connected to logically equivalent pins. "
+            "Remapping intra lb net %d (atom net %zu '%s') from common sink "
+            "pb_route %d to fixed pin pb_route %d\n",
+            ilb_net, size_t(lb_nets_[ilb_net].atom_net_id), atom_ctx.nlist.net_name(lb_nets_[ilb_net].atom_net_id).c_str(),
+            kv.first, size_t(pin_index));
+
+        VTR_ASSERT(1 == lb_rr_graph.node_out_edges(pin_index, &(pb_graph_pin->parent_node->pb_type->modes[0])).size());
+        LbRRNodeId sink_index = lb_rr_graph.edge_sink_node(lb_rr_graph.node_out_edges(pin_index, &(pb_graph_pin->parent_node->pb_type->modes[0]))[0]);
+        VTR_ASSERT(LB_SINK == lb_rr_graph.node_type(sink_index));
+        VTR_ASSERT_MSG(sink_index == lb_nets_[ilb_net].terminals[iterm], "Remapped pin must be connected to original sink");
+
+        //Change the target
+        lb_nets_[ilb_net].terminals[iterm] = pin_index;
+      }
+    }
+  }
+}
+
+// Check one edge for mode conflict.
+bool LbRouter::check_edge_for_route_conflicts(std::unordered_map<const t_pb_graph_node*, const t_mode*>& mode_map,
+                                              const t_pb_graph_pin* driver_pin,
+                                              const t_pb_graph_pin* pin) {
+  if (driver_pin == nullptr) {
+    return false;
+  }
+
+  // Only check pins that are OUT_PORTs.
+  if (pin == nullptr || pin->port == nullptr || pin->port->type != OUT_PORT) {
+    return false;
+  }
+  VTR_ASSERT(!pin->port->is_clock);
+
+  auto* pb_graph_node = pin->parent_node;
+  VTR_ASSERT(pb_graph_node->pb_type == pin->port->parent_pb_type);
+
+  const t_pb_graph_edge* edge = get_edge_between_pins(driver_pin, pin);
+  VTR_ASSERT(edge != nullptr);
+
+  auto mode_of_edge = edge->interconnect->parent_mode_index;
+  auto* mode = &pb_graph_node->pb_type->modes[mode_of_edge];
+
+  auto result = mode_map.insert(std::make_pair(pb_graph_node, mode));
+  if (!result.second) {
+    if (result.first->second != mode) {
+      VTR_LOG("Differing modes for block. Got %s mode, while previously was %s for interconnect %s.\n",
+              mode->name, result.first->second->name,
+              edge->interconnect->name);
+      // The illegal mode is added to the pb_graph_node as it resulted in a conflict during atom-to-atom routing. This mode cannot be used in the consequent cluster
+      // generation try.
+      if (std::find(pb_graph_node->illegal_modes.begin(), pb_graph_node->illegal_modes.end(), result.first->second->index) == pb_graph_node->illegal_modes.end()) {
+        pb_graph_node->illegal_modes.push_back(result.first->second->index);
+      }
+
+      // If the number of illegal modes equals the number of available mode for a specific pb_graph_node it means that no cluster can be generated. This resuts
+      // in a fatal error.
+      if ((int)pb_graph_node->illegal_modes.size() >= pb_graph_node->pb_type->num_modes) {
+        VPR_FATAL_ERROR(VPR_ERROR_PACK, "There are no more available modes to be used. Routing Failed!");
+      }
+
+      return true;
+    }
+  }
+
+  return false;
+}
+
+void LbRouter::commit_remove_rt(const LbRRGraph& lb_rr_graph,
+                                t_trace* rt,
+                                const e_commit_remove& op,
+                                std::unordered_map<const t_pb_graph_node*, const t_mode*>& mode_map,
+                                t_mode_selection_status& mode_status) {
+  int incr;
+
+  if (nullptr == rt) {
+    return;
+  }
+
+  LbRRNodeId inode = rt->current_node;
+
+  /* Determine if node is being used or removed */
+  if (op == RT_COMMIT) {
+    incr = 1;
+    if (routing_status_[inode].occ >= lb_rr_graph.node_capacity(inode)) {
+      routing_status_[inode].historical_usage += (routing_status_[inode].occ - lb_rr_graph.node_capacity(inode) + 1); /* store historical overuse */
+    }
+  } else {
+    incr = -1;
+    explored_node_tb_[inode].inet = OPEN;
+  }
+
+  routing_status_[inode].occ += incr;
+  VTR_ASSERT(routing_status_[inode].occ >= 0);
+
+  t_pb_graph_pin* driver_pin = lb_rr_graph.node_pb_graph_pin(inode);
+
+  /* Recursively update route tree */
+  for (unsigned int i = 0; i < rt->next_nodes.size(); i++) {
+    // Check to see if there is no mode conflict between previous nets.
+    // A conflict is present if there are differing modes between a pb_graph_node
+    // and its children.
+    if (op == RT_COMMIT && mode_status.try_expand_all_modes) {
+      const LbRRNodeId& node = rt->next_nodes[i].current_node;
+      t_pb_graph_pin* pin = lb_rr_graph.node_pb_graph_pin(node);
+
+      if (check_edge_for_route_conflicts(mode_map, driver_pin, pin)) {
+        mode_status.is_mode_conflict = true;
+      }
+    }
+
+    commit_remove_rt(lb_rr_graph, &rt->next_nodes[i], op, mode_map, mode_status);
+  }
+}
+
 bool LbRouter::is_skip_route_net(const LbRRGraph& lb_rr_graph,
                                  t_trace* rt) {
   /* Validate if the rr_graph is the one we used to initialize the router */
@@ -293,6 +461,63 @@ void LbRouter::expand_node_all_modes(const LbRRGraph& lb_rr_graph,
   }
 }
 
+bool LbRouter::try_expand_nodes(const AtomNetlist& atom_nlist,
+                                const LbRRGraph& lb_rr_graph,
+                                const t_net& lb_net,
+                                t_expansion_node& exp_node,
+                                reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq,
+                                const int& itarget,
+                                const bool& try_other_modes,
+                                const int& verbosity) {
+  bool is_impossible = false;
+
+  do {
+    if (pq.empty()) {
+      /* No connection possible */
+      is_impossible = true;
+
+      if (verbosity > 3) {
+        //Print detailed debug info
+        AtomNetId net_id = lb_net.atom_net_id;
+        AtomPinId driver_pin = lb_net.atom_pins[0];
+        AtomPinId sink_pin = lb_net.atom_pins[itarget];
+        LbRRNodeId driver_rr_node = lb_net.terminals[0];
+        LbRRNodeId sink_rr_node = lb_net.terminals[itarget];
+
+        VTR_LOG("\t\t\tNo possible routing path from %s to %s: needed for net '%s' from net pin '%s'",
+                describe_lb_rr_node(lb_rr_graph, driver_rr_node).c_str(),
+                describe_lb_rr_node(lb_rr_graph, sink_rr_node).c_str(),
+                atom_nlist.net_name(net_id).c_str(),
+                atom_nlist.pin_name(driver_pin).c_str());
+        VTR_LOGV(sink_pin, " to net pin '%s'", atom_nlist.pin_name(sink_pin).c_str());
+        VTR_LOG("\n");
+      }
+    } else {
+      exp_node = pq.top();
+      pq.pop();
+      LbRRNodeId exp_inode = exp_node.node_index;
+
+      if (explored_node_tb_[exp_inode].explored_id != explore_id_index_) {
+        /* First time node is popped implies path to this node is the lowest cost.
+         * If the node is popped a second time, then the path to that node is higher 
+         * than this path so ignore.
+         */
+        explored_node_tb_[exp_inode].explored_id = explore_id_index_;
+        explored_node_tb_[exp_inode].prev_index = exp_node.prev_index;
+        if (exp_inode != lb_net.terminals[itarget]) {
+          if (!try_other_modes) {
+            expand_node(lb_rr_graph, exp_node, pq, lb_net.terminals.size() - 1);
+          } else {
+            expand_node_all_modes(lb_rr_graph, exp_node, pq, lb_net.terminals.size() - 1);
+          }
+        }
+      }
+    }
+  } while (exp_node.node_index != lb_net.terminals[itarget] && !is_impossible);
+
+  return is_impossible;
+}
+
 /**************************************************
  * Private validators
  *************************************************/
@@ -314,5 +539,4 @@ void LbRouter::reset_explored_node_tb() {
   }
 }
 
-
 } /* end namespace openfpga */
diff --git a/openfpga/src/repack/lb_router.h b/openfpga/src/repack/lb_router.h
index 92aca94c1..8a4feac9c 100644
--- a/openfpga/src/repack/lb_router.h
+++ b/openfpga/src/repack/lb_router.h
@@ -11,7 +11,7 @@
 #include "vtr_vector.h"
 
 #include "physical_types.h"
-#include "atom_netlist_fwd.h"
+#include "vpr_context.h"
 
 #include "lb_rr_graph.h"
 
@@ -176,6 +176,11 @@ class LbRouter {
       private:
         size_type cur_cap;
     };
+ 
+    enum e_commit_remove {
+      RT_COMMIT,
+      RT_REMOVE
+    };
 
   public :  /* Public constructors */
     LbRouter(const LbRRGraph& lb_rr_graph);
@@ -199,7 +204,27 @@ class LbRouter {
      */
     t_trace* find_node_in_rt(t_trace* rt, const LbRRNodeId& rt_index);
 
+    bool route_has_conflict(const LbRRGraph& lb_rr_graph, t_trace* rt) const;
+
   private : /* Private mutators */
+    /*It is possible that a net may connect multiple times to a logically equivalent set of primitive pins.
+     *The cluster router will only route one connection for a particular net to the common sink of the
+     *equivalent pins.
+     *
+     *To work around this, we fix all but one of these duplicate connections to route to specific pins,
+     *(instead of the common sink). This ensures a legal routing is produced and that the duplicate pins
+     *are not 'missing' in the clustered netlist.
+     */
+    void fix_duplicate_equivalent_pins(const AtomContext& atom_ctx,
+                                       const LbRRGraph& lb_rr_graph);
+    bool check_edge_for_route_conflicts(std::unordered_map<const t_pb_graph_node*, const t_mode*>& mode_map,
+                                        const t_pb_graph_pin* driver_pin,
+                                        const t_pb_graph_pin* pin);
+    void commit_remove_rt(const LbRRGraph& lb_rr_graph,
+                          t_trace* rt,
+                          const e_commit_remove& op,
+                          std::unordered_map<const t_pb_graph_node*, const t_mode*>& mode_map,
+                          t_mode_selection_status& mode_status);
     bool is_skip_route_net(const LbRRGraph& lb_rr_graph, t_trace* rt);
     bool add_to_rt(t_trace* rt, const LbRRNodeId& node_index, const int& irt_net);
     void add_source_to_rt(const int& inet);
@@ -225,6 +250,15 @@ class LbRouter {
                                const t_expansion_node& exp_node,
                                reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq, 
                                const int& net_fanout);
+    bool try_expand_nodes(const AtomNetlist& atom_nlist,
+                          const LbRRGraph& lb_rr_graph,
+                          const t_net& lb_net,
+                          t_expansion_node& exp_node,
+                          reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq,
+                          const int& itarget,
+                          const bool& try_other_modes,
+                          const int& verbosity);
+
 
   private :  /* Private validators */
     /** 
diff --git a/openfpga/src/repack/lb_rr_graph.cpp b/openfpga/src/repack/lb_rr_graph.cpp
index 3645e60e6..434ac0b3e 100644
--- a/openfpga/src/repack/lb_rr_graph.cpp
+++ b/openfpga/src/repack/lb_rr_graph.cpp
@@ -87,7 +87,7 @@ std::vector<LbRREdgeId> LbRRGraph::node_out_edges(const LbRRNodeId& node, t_mode
   return out_edges;
 }
 
-LbRRNodeId LbRRGraph::find_node(const e_lb_rr_type& type, t_pb_graph_pin* pb_graph_pin) const {
+LbRRNodeId LbRRGraph::find_node(const e_lb_rr_type& type, const t_pb_graph_pin* pb_graph_pin) const {
   if (size_t(type) >= node_lookup_.size()) {
     return LbRRNodeId::INVALID();
   }
diff --git a/openfpga/src/repack/lb_rr_graph.h b/openfpga/src/repack/lb_rr_graph.h
index e75d866b3..4500a504b 100644
--- a/openfpga/src/repack/lb_rr_graph.h
+++ b/openfpga/src/repack/lb_rr_graph.h
@@ -206,7 +206,7 @@ class LbRRGraph {
     std::vector<LbRREdgeId> node_out_edges(const LbRRNodeId& node, t_mode* mode) const;
 
     /* General method to look up a node with type and only pb_graph_pin information */
-    LbRRNodeId find_node(const e_lb_rr_type& type, t_pb_graph_pin* pb_graph_pin) const;
+    LbRRNodeId find_node(const e_lb_rr_type& type, const t_pb_graph_pin* pb_graph_pin) const;
     /* Method to find special node */
     LbRRNodeId ext_source_node() const;
     LbRRNodeId ext_sink_node() const;
@@ -302,7 +302,7 @@ class LbRRGraph {
     /* Fast look-up to search a node by its type, coordinator and ptc_num 
      * Indexing of fast look-up: [0..NUM_TYPES-1][t_pb_graph_pin*] 
      */
-    typedef std::vector<std::map<t_pb_graph_pin*, LbRRNodeId>> NodeLookup;
+    typedef std::vector<std::map<const t_pb_graph_pin*, LbRRNodeId>> NodeLookup;
     mutable NodeLookup node_lookup_;
 
     /* Special node look-up */

From 5ccb4adb0856f417d9bc87ea37a27702013bbf3e Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 19 Feb 2020 11:09:24 -0700
Subject: [PATCH 179/645] refactored LB router main function

---
 openfpga/src/repack/lb_router.cpp | 197 ++++++++++++++++++++++++++----
 openfpga/src/repack/lb_router.h   |  38 ++++--
 2 files changed, 197 insertions(+), 38 deletions(-)

diff --git a/openfpga/src/repack/lb_router.cpp b/openfpga/src/repack/lb_router.cpp
index fece00596..a22d1d25e 100644
--- a/openfpga/src/repack/lb_router.cpp
+++ b/openfpga/src/repack/lb_router.cpp
@@ -19,11 +19,13 @@ namespace openfpga {
 /**************************************************
  * Public Constructors
  *************************************************/
-LbRouter::LbRouter(const LbRRGraph& lb_rr_graph) {
+LbRouter::LbRouter(const LbRRGraph& lb_rr_graph, t_logical_block_type_ptr lb_type) {
   routing_status_.resize(lb_rr_graph.nodes().size());
   explored_node_tb_.resize(lb_rr_graph.nodes().size());
   explore_id_index_ = 1;
 
+  lb_type_ = lb_type;
+
   /* Default routing parameters */
   params_.max_iterations = 50;
   params_.pres_fac = 1;
@@ -100,6 +102,115 @@ bool LbRouter::route_has_conflict(const LbRRGraph& lb_rr_graph, t_trace* rt) con
   return false;
 }
 
+/**************************************************
+ * Public mutators
+ *************************************************/
+bool LbRouter::try_route(const LbRRGraph& lb_rr_graph,
+                         const AtomNetlist& atom_nlist,
+                         const int& verbosity) {
+  /* Validate if the rr_graph is the one we used to initialize the router */
+  VTR_ASSERT(true == matched_lb_rr_graph(lb_rr_graph));
+
+  bool is_routed = false;
+  bool is_impossible = false;
+
+  mode_status_.is_mode_conflict = false;
+  mode_status_.try_expand_all_modes = false;
+
+  t_expansion_node exp_node;
+
+  reset_explored_node_tb();
+
+  /* Reset current routing */
+  reset_net_rt();
+  reset_routing_status();
+
+  std::unordered_map<const t_pb_graph_node*, const t_mode*> mode_map;
+
+  /* Iteratively remove congestion until a successful route is found.
+   * Cap the total number of iterations tried so that if a solution does not exist, then the router won't run indefinitely */
+  pres_con_fac_ = params_.pres_fac;
+  for (int iter = 0; iter < params_.max_iterations && !is_routed && !is_impossible; iter++) {
+    unsigned int inet;
+    /* Iterate across all nets internal to logic block */
+    for (inet = 0; inet < lb_nets_.size() && !is_impossible; inet++) {
+      int idx = inet;
+      if (is_skip_route_net(lb_rr_graph, lb_nets_[idx].rt_tree)) {
+        continue;
+      }
+      commit_remove_rt(lb_rr_graph, lb_nets_[idx].rt_tree, RT_REMOVE, mode_map);
+      free_net_rt(lb_nets_[idx].rt_tree);
+      lb_nets_[idx].rt_tree = nullptr;
+      add_source_to_rt(idx);
+
+      /* Route each sink of net */
+      for (unsigned int itarget = 1; itarget < lb_nets_[idx].terminals.size() && !is_impossible; itarget++) {
+        pq_.clear();
+        /* Get lowest cost next node, repeat until a path is found or if it is impossible to route */
+
+        expand_rt(idx, idx);
+
+        is_impossible = try_expand_nodes(atom_nlist, lb_rr_graph, lb_nets_[idx], exp_node, itarget, mode_status_.expand_all_modes, verbosity);
+
+        if (is_impossible && !mode_status_.expand_all_modes) {
+          mode_status_.try_expand_all_modes = true;
+          mode_status_.expand_all_modes = true;
+          break;
+        }
+
+        if (exp_node.node_index == lb_nets_[idx].terminals[itarget]) {
+          /* Net terminal is routed, add this to the route tree, clear data structures, and keep going */
+          is_impossible = add_to_rt(lb_nets_[idx].rt_tree, exp_node.node_index, idx);
+        }
+
+        if (is_impossible) {
+          VTR_LOG("Routing was impossible!\n");
+        } else if (mode_status_.expand_all_modes) {
+          is_impossible = route_has_conflict(lb_rr_graph, lb_nets_[idx].rt_tree);
+          if (is_impossible) {
+            VTR_LOG("Routing was impossible due to modes!\n");
+          }
+        }
+
+        explore_id_index_++;
+        if (explore_id_index_ > 2000000000) {
+          /* overflow protection */
+          for (const LbRRNodeId& id : lb_rr_graph.nodes()) {
+            explored_node_tb_[id].explored_id = OPEN;
+            explored_node_tb_[id].enqueue_id = OPEN;
+            explore_id_index_ = 1;
+          }
+        }
+      }
+
+      if (!is_impossible) {
+        commit_remove_rt(lb_rr_graph, lb_nets_[idx].rt_tree, RT_COMMIT, mode_map);
+        if (mode_status_.is_mode_conflict) {
+          is_impossible = true;
+        }
+      }
+    }
+
+    if (!is_impossible) {
+      is_routed_ = is_route_success(lb_rr_graph);
+    } else {
+      --inet;
+      VTR_LOGV(verbosity < 3, "Net '%s' is impossible to route within proposed %s cluster\n",
+               atom_nlist.net_name(lb_nets_[inet].atom_net_id).c_str(), lb_type_->name);
+      is_routed_ = false;
+    }
+    pres_con_fac_ *= params_.pres_fac_mult;
+  }
+
+  /* TODO: 
+   * Let user to decide to how proceed upon the routing results: 
+   * - route success: save the results through public accessors to lb_nets_
+   *                  print the route results to files
+   * - route fail: report all the congestion nodes 
+   */
+  return is_routed_;
+}
+
 /**************************************************
  * Private mutators
  *************************************************/
@@ -204,8 +315,7 @@ bool LbRouter::check_edge_for_route_conflicts(std::unordered_map<const t_pb_grap
 void LbRouter::commit_remove_rt(const LbRRGraph& lb_rr_graph,
                                 t_trace* rt,
                                 const e_commit_remove& op,
-                                std::unordered_map<const t_pb_graph_node*, const t_mode*>& mode_map,
-                                t_mode_selection_status& mode_status) {
+                                std::unordered_map<const t_pb_graph_node*, const t_mode*>& mode_map) {
   int incr;
 
   if (nullptr == rt) {
@@ -235,16 +345,16 @@ void LbRouter::commit_remove_rt(const LbRRGraph& lb_rr_graph,
     // Check to see if there is no mode conflict between previous nets.
     // A conflict is present if there are differing modes between a pb_graph_node
     // and its children.
-    if (op == RT_COMMIT && mode_status.try_expand_all_modes) {
+    if (op == RT_COMMIT && mode_status_.try_expand_all_modes) {
       const LbRRNodeId& node = rt->next_nodes[i].current_node;
       t_pb_graph_pin* pin = lb_rr_graph.node_pb_graph_pin(node);
 
       if (check_edge_for_route_conflicts(mode_map, driver_pin, pin)) {
-        mode_status.is_mode_conflict = true;
+        mode_status_.is_mode_conflict = true;
       }
     }
 
-    commit_remove_rt(lb_rr_graph, &rt->next_nodes[i], op, mode_map, mode_status);
+    commit_remove_rt(lb_rr_graph, &rt->next_nodes[i], op, mode_map);
   }
 }
 
@@ -318,7 +428,6 @@ void LbRouter::add_source_to_rt(const int& inet) {
 
 void LbRouter::expand_rt_rec(t_trace* rt,
                              const LbRRNodeId& prev_index, 
-                             reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq,
                              const int& irt_net,
                              const int& explore_id_index) {
   t_expansion_node enode;
@@ -327,7 +436,7 @@ void LbRouter::expand_rt_rec(t_trace* rt,
   enode.cost = 0;
   enode.node_index = rt->current_node;
   enode.prev_index = prev_index;
-  pq.push(enode);
+  pq_.push(enode);
   explored_node_tb_[enode.node_index].inet = irt_net;
   explored_node_tb_[enode.node_index].explored_id = OPEN;
   explored_node_tb_[enode.node_index].enqueue_id = explore_id_index;
@@ -335,24 +444,22 @@ void LbRouter::expand_rt_rec(t_trace* rt,
   explored_node_tb_[enode.node_index].prev_index = prev_index;
 
   for (unsigned int i = 0; i < rt->next_nodes.size(); i++) {
-    expand_rt_rec(&rt->next_nodes[i], rt->current_node, pq, irt_net, explore_id_index);
+    expand_rt_rec(&rt->next_nodes[i], rt->current_node, irt_net, explore_id_index);
   }
 }
 
 void LbRouter::expand_rt(const int& inet,
-                         reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq,
                          const int& irt_net) {
-  VTR_ASSERT(pq.empty());
+  VTR_ASSERT(pq_.empty());
 
-  expand_rt_rec(lb_nets_[inet].rt_tree, LbRRNodeId::INVALID(), pq, irt_net, explore_id_index_);
+  expand_rt_rec(lb_nets_[inet].rt_tree, LbRRNodeId::INVALID(), irt_net, explore_id_index_);
 }
 
 void LbRouter::expand_edges(const LbRRGraph& lb_rr_graph,
                             t_mode* mode,
                             const LbRRNodeId& cur_inode,
                             float cur_cost,
-                            int net_fanout,
-                            reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq) {
+                            int net_fanout) {
   /* Validate if the rr_graph is the one we used to initialize the router */
   VTR_ASSERT(true == matched_lb_rr_graph(lb_rr_graph));
 
@@ -394,19 +501,18 @@ void LbRouter::expand_edges(const LbRRGraph& lb_rr_graph,
     /* Add to queue if cost is lower than lowest cost path to this enode */
     if (explored_node_tb_[enode.node_index].enqueue_id == explore_id_index_) {
       if (enode.cost < explored_node_tb_[enode.node_index].enqueue_cost) {
-        pq.push(enode);
+        pq_.push(enode);
       }
     } else {
       explored_node_tb_[enode.node_index].enqueue_id = explore_id_index_;
       explored_node_tb_[enode.node_index].enqueue_cost = enode.cost;
-      pq.push(enode);
+      pq_.push(enode);
     }
   }
 }
 
 void LbRouter::expand_node(const LbRRGraph& lb_rr_graph,
                            const t_expansion_node& exp_node,
-                           reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq,
                            const int& net_fanout) {
   /* Validate if the rr_graph is the one we used to initialize the router */
   VTR_ASSERT(true == matched_lb_rr_graph(lb_rr_graph));
@@ -420,12 +526,11 @@ void LbRouter::expand_node(const LbRRGraph& lb_rr_graph,
     mode = &(lb_rr_graph.node_pb_graph_pin(cur_node)->parent_node->pb_type->modes[0]);
   }
 
-  expand_edges(lb_rr_graph, mode, cur_node, cur_cost, net_fanout, pq);
+  expand_edges(lb_rr_graph, mode, cur_node, cur_cost, net_fanout);
 }
 
 void LbRouter::expand_node_all_modes(const LbRRGraph& lb_rr_graph,
                                      const t_expansion_node& exp_node,
-                                     reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq, 
                                      const int& net_fanout) {
   /* Validate if the rr_graph is the one we used to initialize the router */
   VTR_ASSERT(true == matched_lb_rr_graph(lb_rr_graph));
@@ -457,7 +562,7 @@ void LbRouter::expand_node_all_modes(const LbRRGraph& lb_rr_graph,
     if (is_illegal == true) {
       continue;
     }
-    expand_edges(lb_rr_graph, mode, cur_inode, cur_cost, net_fanout, pq);
+    expand_edges(lb_rr_graph, mode, cur_inode, cur_cost, net_fanout);
   }
 }
 
@@ -465,14 +570,13 @@ bool LbRouter::try_expand_nodes(const AtomNetlist& atom_nlist,
                                 const LbRRGraph& lb_rr_graph,
                                 const t_net& lb_net,
                                 t_expansion_node& exp_node,
-                                reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq,
                                 const int& itarget,
                                 const bool& try_other_modes,
                                 const int& verbosity) {
   bool is_impossible = false;
 
   do {
-    if (pq.empty()) {
+    if (pq_.empty()) {
       /* No connection possible */
       is_impossible = true;
 
@@ -493,8 +597,8 @@ bool LbRouter::try_expand_nodes(const AtomNetlist& atom_nlist,
         VTR_LOG("\n");
       }
     } else {
-      exp_node = pq.top();
-      pq.pop();
+      exp_node = pq_.top();
+      pq_.pop();
       LbRRNodeId exp_inode = exp_node.node_index;
 
       if (explored_node_tb_[exp_inode].explored_id != explore_id_index_) {
@@ -506,9 +610,9 @@ bool LbRouter::try_expand_nodes(const AtomNetlist& atom_nlist,
         explored_node_tb_[exp_inode].prev_index = exp_node.prev_index;
         if (exp_inode != lb_net.terminals[itarget]) {
           if (!try_other_modes) {
-            expand_node(lb_rr_graph, exp_node, pq, lb_net.terminals.size() - 1);
+            expand_node(lb_rr_graph, exp_node, lb_net.terminals.size() - 1);
           } else {
-            expand_node_all_modes(lb_rr_graph, exp_node, pq, lb_net.terminals.size() - 1);
+            expand_node_all_modes(lb_rr_graph, exp_node, lb_net.terminals.size() - 1);
           }
         }
       }
@@ -539,4 +643,45 @@ void LbRouter::reset_explored_node_tb() {
   }
 }
 
+void LbRouter::reset_net_rt() {
+  for (unsigned int inet = 0; inet < lb_nets_.size(); inet++) {
+    free_net_rt(lb_nets_[inet].rt_tree);
+    lb_nets_[inet].rt_tree = nullptr;
+  }
+}
+
+void LbRouter::reset_routing_status() {
+  for (t_routing_status& status : routing_status_) {
+    status.historical_usage = 0;
+    status.occ = 0;
+  }
+}
+
+void LbRouter::clear_nets() {
+  reset_net_rt();
+  for (unsigned int i = 0; i < lb_nets_.size(); i++) {
+    lb_nets_[i].terminals.clear();
+  }
+  lb_nets_.clear();
+}
+
+void LbRouter::free_net_rt(t_trace* lb_trace) {
+  if (lb_trace != nullptr) {
+    for (unsigned int i = 0; i < lb_trace->next_nodes.size(); i++) {
+      free_lb_trace(&lb_trace->next_nodes[i]);
+    }
+    lb_trace->next_nodes.clear();
+    delete lb_trace;
+  }
+}
+
+void LbRouter::free_lb_trace(t_trace* lb_trace) {
+  if (lb_trace != nullptr) {
+    for (unsigned int i = 0; i < lb_trace->next_nodes.size(); i++) {
+      free_lb_trace(&lb_trace->next_nodes[i]);
+    }
+    lb_trace->next_nodes.clear();
+  }
+}
+
 } /* end namespace openfpga */
diff --git a/openfpga/src/repack/lb_router.h b/openfpga/src/repack/lb_router.h
index 8a4feac9c..40d8d5d93 100644
--- a/openfpga/src/repack/lb_router.h
+++ b/openfpga/src/repack/lb_router.h
@@ -183,7 +183,7 @@ class LbRouter {
     };
 
   public :  /* Public constructors */
-    LbRouter(const LbRRGraph& lb_rr_graph);
+    LbRouter(const LbRRGraph& lb_rr_graph, t_logical_block_type_ptr lb_type);
   
   public :  /* Public accessors */
     /**
@@ -206,6 +206,15 @@ class LbRouter {
 
     bool route_has_conflict(const LbRRGraph& lb_rr_graph, t_trace* rt) const;
 
+  public : /* Public mutators */
+    /**
+     * Perform routing algorithm on a given logical tile routing resource graph
+     * Note: the lb_rr_graph must be the same as you initilized the router!!!
+     */
+    bool try_route(const LbRRGraph& lb_rr_graph,
+                   const AtomNetlist& atom_nlist,
+                   const int& verbosity);
+
   private : /* Private mutators */
     /*It is possible that a net may connect multiple times to a logically equivalent set of primitive pins.
      *The cluster router will only route one connection for a particular net to the common sink of the
@@ -223,43 +232,35 @@ class LbRouter {
     void commit_remove_rt(const LbRRGraph& lb_rr_graph,
                           t_trace* rt,
                           const e_commit_remove& op,
-                          std::unordered_map<const t_pb_graph_node*, const t_mode*>& mode_map,
-                          t_mode_selection_status& mode_status);
+                          std::unordered_map<const t_pb_graph_node*, const t_mode*>& mode_map);
     bool is_skip_route_net(const LbRRGraph& lb_rr_graph, t_trace* rt);
     bool add_to_rt(t_trace* rt, const LbRRNodeId& node_index, const int& irt_net);
     void add_source_to_rt(const int& inet);
     void expand_rt_rec(t_trace* rt,
                        const LbRRNodeId& prev_index, 
-                       reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq,
                        const int& irt_net,
                        const int& explore_id_index);
     void expand_rt(const int& inet,
-                   reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq,
                    const int& irt_net);
     void expand_edges(const LbRRGraph& lb_rr_graph,
                       t_mode* mode,
                       const LbRRNodeId& cur_inode,
                       float cur_cost,
-                      int net_fanout,
-                      reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq);
+                      int net_fanout);
     void expand_node(const LbRRGraph& lb_rr_graph,
                      const t_expansion_node& exp_node,
-                     reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq,
                      const int& net_fanout);
     void expand_node_all_modes(const LbRRGraph& lb_rr_graph,
                                const t_expansion_node& exp_node,
-                               reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq, 
                                const int& net_fanout);
     bool try_expand_nodes(const AtomNetlist& atom_nlist,
                           const LbRRGraph& lb_rr_graph,
                           const t_net& lb_net,
                           t_expansion_node& exp_node,
-                          reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node>& pq,
                           const int& itarget,
                           const bool& try_other_modes,
                           const int& verbosity);
 
-
   private :  /* Private validators */
     /** 
      * Validate if the rr_graph is the one we used to initialize the router 
@@ -268,6 +269,12 @@ class LbRouter {
 
   private :  /* Private initializer and cleaner */
     void reset_explored_node_tb();
+    void reset_net_rt();
+    void reset_routing_status();
+
+    void clear_nets();
+    void free_net_rt(t_trace* lb_trace);
+    void free_lb_trace(t_trace* lb_trace);
 
   private : /* Stores all data needed by intra-logic cluster_ctx.blocks router */
     /* Logical Netlist Info */
@@ -292,7 +299,14 @@ class LbRouter {
     /* Parameters used by router */
     t_option params_;
 
-    bool is_routed_;                       /* Stores whether or not the current logical-to-physical mapping has a routed solution */
+    /* Stores whether or not the current logical-to-physical mapping has a routed solution */
+    bool is_routed_;
+
+    /* Stores the mode selection status when expanding the edges */
+    t_mode_selection_status mode_status_;
+
+    /* Stores state info of the priority queue in expanding edges during route */
+    reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node> pq_;
 
     /* current congestion factor */
     float pres_con_fac_;

From 2f1bcdd27d1f7e1e67ff75233abd6f24e2fff4e4 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 19 Feb 2020 14:53:35 -0700
Subject: [PATCH 180/645] use local data to store illegal modes for
 pb_graph_node inside LbRouter

---
 openfpga/src/repack/lb_router.cpp | 39 +++++++++++++++++++++++--------
 openfpga/src/repack/lb_router.h   | 11 +++++++--
 2 files changed, 38 insertions(+), 12 deletions(-)

diff --git a/openfpga/src/repack/lb_router.cpp b/openfpga/src/repack/lb_router.cpp
index a22d1d25e..753ba2e32 100644
--- a/openfpga/src/repack/lb_router.cpp
+++ b/openfpga/src/repack/lb_router.cpp
@@ -31,6 +31,8 @@ LbRouter::LbRouter(const LbRRGraph& lb_rr_graph, t_logical_block_type_ptr lb_typ
   params_.pres_fac = 1;
   params_.pres_fac_mult = 2;
   params_.hist_fac = 0.3;
+
+  is_routed_ = false;
  
   pres_con_fac_ = 1;
 }
@@ -53,6 +55,13 @@ std::vector<LbRRNodeId> LbRouter::find_congested_rr_nodes(const LbRRGraph& lb_rr
   return congested_rr_nodes;
 }
 
+bool LbRouter::is_routed() const {
+  return is_routed_;
+}
+
+/**************************************************
+ * Private accessors
+ *************************************************/
 bool LbRouter::is_route_success(const LbRRGraph& lb_rr_graph) const {
   /* Validate if the rr_graph is the one we used to initialize the router */
   VTR_ASSERT(true == matched_lb_rr_graph(lb_rr_graph));
@@ -66,9 +75,6 @@ bool LbRouter::is_route_success(const LbRRGraph& lb_rr_graph) const {
   return true;
 }
 
-/**************************************************
- * Private accessors
- *************************************************/
 LbRouter::t_trace* LbRouter::find_node_in_rt(t_trace* rt, const LbRRNodeId& rt_index) {
   t_trace* cur;
   if (rt->current_node == rt_index) {
@@ -111,7 +117,7 @@ bool LbRouter::try_route(const LbRRGraph& lb_rr_graph,
   /* Validate if the rr_graph is the one we used to initialize the router */
   VTR_ASSERT(true == matched_lb_rr_graph(lb_rr_graph));
 
-  bool is_routed = false;
+  is_routed_ = false;
   bool is_impossible = false;
 
   mode_status_.is_mode_conflict = false;
@@ -130,7 +136,7 @@ bool LbRouter::try_route(const LbRRGraph& lb_rr_graph,
   /* Iteratively remove congestion until a successful route is found.
    * Cap the total number of iterations tried so that if a solution does not exist, then the router won't run indefinitely */
   pres_con_fac_ = params_.pres_fac;
-  for (int iter = 0; iter < params_.max_iterations && !is_routed && !is_impossible; iter++) {
+  for (int iter = 0; iter < params_.max_iterations && !is_routed_ && !is_impossible; iter++) {
     unsigned int inet;
     /* Iterate across all nets internal to logic block */
     for (inet = 0; inet < lb_nets_.size() && !is_impossible; inet++) {
@@ -295,13 +301,18 @@ bool LbRouter::check_edge_for_route_conflicts(std::unordered_map<const t_pb_grap
               edge->interconnect->name);
       // The illegal mode is added to the pb_graph_node as it resulted in a conflict during atom-to-atom routing. This mode cannot be used in the consequent cluster
       // generation try.
-      if (std::find(pb_graph_node->illegal_modes.begin(), pb_graph_node->illegal_modes.end(), result.first->second->index) == pb_graph_node->illegal_modes.end()) {
-        pb_graph_node->illegal_modes.push_back(result.first->second->index);
+      auto it = illegal_modes_.find(pb_graph_node);
+      if (it == illegal_modes_.end()) {
+        illegal_modes_[pb_graph_node].push_back(result.first->second);
+      } else {
+        if (std::find(illegal_modes_.at(pb_graph_node).begin(), illegal_modes_.at(pb_graph_node).end(), result.first->second) == illegal_modes_.at(pb_graph_node).end()) {
+          it->second.push_back(result.first->second);
+        }
       }
 
       // If the number of illegal modes equals the number of available mode for a specific pb_graph_node it means that no cluster can be generated. This resuts
       // in a fatal error.
-      if ((int)pb_graph_node->illegal_modes.size() >= pb_graph_node->pb_type->num_modes) {
+      if ((int)illegal_modes_.at(pb_graph_node).size() >= pb_graph_node->pb_type->num_modes) {
         VPR_FATAL_ERROR(VPR_ERROR_PACK, "There are no more available modes to be used. Routing Failed!");
       }
 
@@ -551,8 +562,11 @@ void LbRouter::expand_node_all_modes(const LbRRGraph& lb_rr_graph,
     bool is_illegal = false;
     if (pin != nullptr) {
       auto* pb_graph_node = pin->parent_node;
-      for (auto illegal_mode : pb_graph_node->illegal_modes) {
-        if (mode->index == illegal_mode) {
+      if (0 == illegal_modes_.count(pb_graph_node)) {
+        continue;
+      }
+      for (auto illegal_mode : illegal_modes_.at(pb_graph_node)) {
+        if (mode == illegal_mode) {
           is_illegal = true;
           break;
         }
@@ -684,4 +698,9 @@ void LbRouter::free_lb_trace(t_trace* lb_trace) {
   }
 }
 
+void LbRouter::reset_illegal_modes() {
+  illegal_modes_.clear();
+}
+
+
 } /* end namespace openfpga */
diff --git a/openfpga/src/repack/lb_router.h b/openfpga/src/repack/lb_router.h
index 40d8d5d93..9d7e76c02 100644
--- a/openfpga/src/repack/lb_router.h
+++ b/openfpga/src/repack/lb_router.h
@@ -192,12 +192,15 @@ class LbRouter {
      */   
     std::vector<LbRRNodeId> find_congested_rr_nodes(const LbRRGraph& lb_rr_graph) const;
 
+    /* Show if a valid routing solution has been founded or not */
+    bool is_routed() const;
+
+  private :  /* Private accessors */
     /**
      * Report if the routing is successfully done on a logical block routing resource graph
      */  
     bool is_route_success(const LbRRGraph& lb_rr_graph) const;
 
-  private :  /* Private accessors */
     /**
      * Try to find a node in the routing traces recursively
      * If not found, will return an empty pointer
@@ -271,6 +274,7 @@ class LbRouter {
     void reset_explored_node_tb();
     void reset_net_rt();
     void reset_routing_status();
+    void reset_illegal_modes();
 
     void clear_nets();
     void free_net_rt(t_trace* lb_trace);
@@ -300,7 +304,7 @@ class LbRouter {
     t_option params_;
 
     /* Stores whether or not the current logical-to-physical mapping has a routed solution */
-    bool is_routed_;
+    bool is_routed_; 
 
     /* Stores the mode selection status when expanding the edges */
     t_mode_selection_status mode_status_;
@@ -308,6 +312,9 @@ class LbRouter {
     /* Stores state info of the priority queue in expanding edges during route */
     reservable_pq<t_expansion_node, std::vector<t_expansion_node>, compare_expansion_node> pq_;
 
+    /* Store the illegal modes for each pb_graph_node that is involved in the routing resource graph */
+    std::map<const t_pb_graph_node*, std::vector<const t_mode*>> illegal_modes_;
+
     /* current congestion factor */
     float pres_con_fac_;
 };

From 2b37fcb296bb5ed057ec44550bc0609106c6159e Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 19 Feb 2020 15:09:25 -0700
Subject: [PATCH 181/645] use strong id for nets to be routed in LbRouter

---
 openfpga/src/repack/lb_router.cpp | 38 +++++++++++++++----------------
 openfpga/src/repack/lb_router.h   | 25 ++++++++++----------
 2 files changed, 31 insertions(+), 32 deletions(-)

diff --git a/openfpga/src/repack/lb_router.cpp b/openfpga/src/repack/lb_router.cpp
index 753ba2e32..0a13b9fa6 100644
--- a/openfpga/src/repack/lb_router.cpp
+++ b/openfpga/src/repack/lb_router.cpp
@@ -140,7 +140,7 @@ bool LbRouter::try_route(const LbRRGraph& lb_rr_graph,
     unsigned int inet;
     /* Iterate across all nets internal to logic block */
     for (inet = 0; inet < lb_nets_.size() && !is_impossible; inet++) {
-      int idx = inet;
+      NetId idx = NetId(inet);
       if (is_skip_route_net(lb_rr_graph, lb_nets_[idx].rt_tree)) {
         continue;
       }
@@ -202,7 +202,7 @@ bool LbRouter::try_route(const LbRRGraph& lb_rr_graph,
     } else {
       --inet;
       VTR_LOGV(verbosity < 3, "Net '%s' is impossible to route within proposed %s cluster\n",
-               atom_nlist.net_name(lb_nets_[inet].atom_net_id).c_str(), lb_type_->name);
+               atom_nlist.net_name(lb_nets_[NetId(inet)].atom_net_id).c_str(), lb_type_->name);
       is_routed_ = false;
     }
     pres_con_fac_ *= params_.pres_fac_mult;
@@ -225,8 +225,8 @@ void LbRouter::fix_duplicate_equivalent_pins(const AtomContext& atom_ctx,
   for (size_t ilb_net = 0; ilb_net < lb_nets_.size(); ++ilb_net) {
     //Collect all the sink terminals indicies which target a particular node
     std::map<LbRRNodeId, std::vector<int>> duplicate_terminals;
-    for (size_t iterm = 1; iterm < lb_nets_[ilb_net].terminals.size(); ++iterm) {
-      LbRRNodeId node = lb_nets_[ilb_net].terminals[iterm];
+    for (size_t iterm = 1; iterm < lb_nets_[NetId(ilb_net)].terminals.size(); ++iterm) {
+      LbRRNodeId node = lb_nets_[NetId(ilb_net)].terminals[iterm];
 
       duplicate_terminals[node].push_back(iterm);
     }
@@ -238,8 +238,8 @@ void LbRouter::fix_duplicate_equivalent_pins(const AtomContext& atom_ctx,
       for (size_t idup_term = 0; idup_term < kv.second.size(); ++idup_term) {
         int iterm = kv.second[idup_term]; //The index in terminals which is duplicated
 
-        VTR_ASSERT(lb_nets_[ilb_net].atom_pins.size() == lb_nets_[ilb_net].terminals.size());
-        AtomPinId atom_pin = lb_nets_[ilb_net].atom_pins[iterm];
+        VTR_ASSERT(lb_nets_[NetId(ilb_net)].atom_pins.size() == lb_nets_[NetId(ilb_net)].terminals.size());
+        AtomPinId atom_pin = lb_nets_[NetId(ilb_net)].atom_pins[iterm];
         VTR_ASSERT(atom_pin);
 
         const t_pb_graph_pin* pb_graph_pin = find_pb_graph_pin(atom_ctx.nlist, atom_ctx.lookup, atom_pin);
@@ -255,16 +255,16 @@ void LbRouter::fix_duplicate_equivalent_pins(const AtomContext& atom_ctx,
             "Found duplicate nets connected to logically equivalent pins. "
             "Remapping intra lb net %d (atom net %zu '%s') from common sink "
             "pb_route %d to fixed pin pb_route %d\n",
-            ilb_net, size_t(lb_nets_[ilb_net].atom_net_id), atom_ctx.nlist.net_name(lb_nets_[ilb_net].atom_net_id).c_str(),
+            ilb_net, size_t(lb_nets_[NetId(ilb_net)].atom_net_id), atom_ctx.nlist.net_name(lb_nets_[NetId(ilb_net)].atom_net_id).c_str(),
             kv.first, size_t(pin_index));
 
         VTR_ASSERT(1 == lb_rr_graph.node_out_edges(pin_index, &(pb_graph_pin->parent_node->pb_type->modes[0])).size());
         LbRRNodeId sink_index = lb_rr_graph.edge_sink_node(lb_rr_graph.node_out_edges(pin_index, &(pb_graph_pin->parent_node->pb_type->modes[0]))[0]);
         VTR_ASSERT(LB_SINK == lb_rr_graph.node_type(sink_index));
-        VTR_ASSERT_MSG(sink_index == lb_nets_[ilb_net].terminals[iterm], "Remapped pin must be connected to original sink");
+        VTR_ASSERT_MSG(sink_index == lb_nets_[NetId(ilb_net)].terminals[iterm], "Remapped pin must be connected to original sink");
 
         //Change the target
-        lb_nets_[ilb_net].terminals[iterm] = pin_index;
+        lb_nets_[NetId(ilb_net)].terminals[iterm] = pin_index;
       }
     }
   }
@@ -343,7 +343,7 @@ void LbRouter::commit_remove_rt(const LbRRGraph& lb_rr_graph,
     }
   } else {
     incr = -1;
-    explored_node_tb_[inode].inet = OPEN;
+    explored_node_tb_[inode].inet = NetId::INVALID();
   }
 
   routing_status_[inode].occ += incr;
@@ -397,7 +397,7 @@ bool LbRouter::is_skip_route_net(const LbRRGraph& lb_rr_graph,
   return true;
 }
 
-bool LbRouter::add_to_rt(t_trace* rt, const LbRRNodeId& node_index, const int& irt_net) {
+bool LbRouter::add_to_rt(t_trace* rt, const LbRRNodeId& node_index, const NetId& irt_net) {
   std::vector<LbRRNodeId> trace_forward;
   t_trace* link_node;
   t_trace curr_node;
@@ -430,7 +430,7 @@ bool LbRouter::add_to_rt(t_trace* rt, const LbRRNodeId& node_index, const int& i
   return false;
 }
 
-void LbRouter::add_source_to_rt(const int& inet) {
+void LbRouter::add_source_to_rt(const NetId& inet) {
   /* TODO: Validate net id */
   VTR_ASSERT(nullptr == lb_nets_[inet].rt_tree);
   lb_nets_[inet].rt_tree = new t_trace;
@@ -439,7 +439,7 @@ void LbRouter::add_source_to_rt(const int& inet) {
 
 void LbRouter::expand_rt_rec(t_trace* rt,
                              const LbRRNodeId& prev_index, 
-                             const int& irt_net,
+                             const NetId& irt_net,
                              const int& explore_id_index) {
   t_expansion_node enode;
 
@@ -459,8 +459,8 @@ void LbRouter::expand_rt_rec(t_trace* rt,
   }
 }
 
-void LbRouter::expand_rt(const int& inet,
-                         const int& irt_net) {
+void LbRouter::expand_rt(const NetId& inet,
+                         const NetId& irt_net) {
   VTR_ASSERT(pq_.empty());
 
   expand_rt_rec(lb_nets_[inet].rt_tree, LbRRNodeId::INVALID(), irt_net, explore_id_index_);
@@ -651,7 +651,7 @@ void LbRouter::reset_explored_node_tb() {
   for (t_explored_node_stats& explored_node : explored_node_tb_) {
     explored_node.prev_index = LbRRNodeId::INVALID();
     explored_node.explored_id = OPEN;
-    explored_node.inet = OPEN;
+    explored_node.inet = NetId::INVALID();
     explored_node.enqueue_id = OPEN;
     explored_node.enqueue_cost = 0;
   }
@@ -659,8 +659,8 @@ void LbRouter::reset_explored_node_tb() {
 
 void LbRouter::reset_net_rt() {
   for (unsigned int inet = 0; inet < lb_nets_.size(); inet++) {
-    free_net_rt(lb_nets_[inet].rt_tree);
-    lb_nets_[inet].rt_tree = nullptr;
+    free_net_rt(lb_nets_[NetId(inet)].rt_tree);
+    lb_nets_[NetId(inet)].rt_tree = nullptr;
   }
 }
 
@@ -674,7 +674,7 @@ void LbRouter::reset_routing_status() {
 void LbRouter::clear_nets() {
   reset_net_rt();
   for (unsigned int i = 0; i < lb_nets_.size(); i++) {
-    lb_nets_[i].terminals.clear();
+    lb_nets_[NetId(i)].terminals.clear();
   }
   lb_nets_.clear();
 }
diff --git a/openfpga/src/repack/lb_router.h b/openfpga/src/repack/lb_router.h
index 9d7e76c02..44bd7b1b8 100644
--- a/openfpga/src/repack/lb_router.h
+++ b/openfpga/src/repack/lb_router.h
@@ -9,6 +9,7 @@
 #include <vector>
 
 #include "vtr_vector.h"
+#include "vtr_strong_id.h"
 
 #include "physical_types.h"
 #include "vpr_context.h"
@@ -23,6 +24,9 @@
 namespace openfpga {
 
 class LbRouter {
+  public: /* Strong ids */
+    struct net_id_tag;
+    typedef vtr::StrongId<net_id_tag> NetId;
   public: /* Intra-Logic Block Routing Data Structures (by instance) */
     /**************************************************************************
      * A routing traceback data structure, provides a logic cluster_ctx.blocks 
@@ -123,7 +127,7 @@ class LbRouter {
     struct t_explored_node_stats {
       LbRRNodeId prev_index;     /* Prevous node that drives this one */
       int explored_id;    /* ID used to determine if this node has been explored */
-      int inet;           /* net index of route tree */
+      NetId inet;           /* net index of route tree */
       int enqueue_id;     /* ID used ot determine if this node has been pushed on exploration priority queue */
       float enqueue_cost; /* cost of node pused on exploration priority queue */
     
@@ -131,7 +135,7 @@ class LbRouter {
         prev_index = LbRRNodeId::INVALID();
         explored_id = OPEN;
         enqueue_id = OPEN;
-        inet = OPEN;
+        inet = NetId::INVALID();
         enqueue_cost = 0;
       }
     };
@@ -237,14 +241,14 @@ class LbRouter {
                           const e_commit_remove& op,
                           std::unordered_map<const t_pb_graph_node*, const t_mode*>& mode_map);
     bool is_skip_route_net(const LbRRGraph& lb_rr_graph, t_trace* rt);
-    bool add_to_rt(t_trace* rt, const LbRRNodeId& node_index, const int& irt_net);
-    void add_source_to_rt(const int& inet);
+    bool add_to_rt(t_trace* rt, const LbRRNodeId& node_index, const NetId& irt_net);
+    void add_source_to_rt(const NetId& inet);
     void expand_rt_rec(t_trace* rt,
                        const LbRRNodeId& prev_index, 
-                       const int& irt_net,
+                       const NetId& irt_net,
                        const int& explore_id_index);
-    void expand_rt(const int& inet,
-                   const int& irt_net);
+    void expand_rt(const NetId& inet,
+                   const NetId& irt_net);
     void expand_edges(const LbRRGraph& lb_rr_graph,
                       t_mode* mode,
                       const LbRRNodeId& cur_inode,
@@ -282,12 +286,7 @@ class LbRouter {
 
   private : /* Stores all data needed by intra-logic cluster_ctx.blocks router */
     /* Logical Netlist Info */
-    std::vector<t_net> lb_nets_; /* Pointer to vector of intra logic cluster_ctx.blocks nets and their connections */
-
-    /* Saved nets */
-    std::vector<t_net> saved_lb_nets_; /* Save vector of intra logic cluster_ctx.blocks nets and their connections */
-
-    std::map<AtomBlockId, bool> atoms_added_; /* map that records which atoms are added to cluster router */
+    vtr::vector<NetId, t_net> lb_nets_; /* Pointer to vector of intra logic cluster_ctx.blocks nets and their connections */
 
     /* Logical-to-physical mapping info */
     vtr::vector<LbRRNodeId, t_routing_status> routing_status_; /* [0..lb_type_graph->size()-1] Stats for each logic cluster_ctx.blocks rr node instance */

From 444b994285fbeb8b2d6f4a0616b6e2c13a63d5f1 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 19 Feb 2020 15:37:22 -0700
Subject: [PATCH 182/645] flatten the t_net inside LbRouter into internal data

---
 openfpga/src/repack/lb_router.cpp | 86 ++++++++++++++++---------------
 openfpga/src/repack/lb_router.h   | 60 +++++++--------------
 2 files changed, 65 insertions(+), 81 deletions(-)

diff --git a/openfpga/src/repack/lb_router.cpp b/openfpga/src/repack/lb_router.cpp
index 0a13b9fa6..610501dde 100644
--- a/openfpga/src/repack/lb_router.cpp
+++ b/openfpga/src/repack/lb_router.cpp
@@ -139,24 +139,24 @@ bool LbRouter::try_route(const LbRRGraph& lb_rr_graph,
   for (int iter = 0; iter < params_.max_iterations && !is_routed_ && !is_impossible; iter++) {
     unsigned int inet;
     /* Iterate across all nets internal to logic block */
-    for (inet = 0; inet < lb_nets_.size() && !is_impossible; inet++) {
+    for (inet = 0; inet < lb_net_ids_.size() && !is_impossible; inet++) {
       NetId idx = NetId(inet);
-      if (is_skip_route_net(lb_rr_graph, lb_nets_[idx].rt_tree)) {
+      if (is_skip_route_net(lb_rr_graph, lb_net_rt_trees_[idx])) {
         continue;
       }
-      commit_remove_rt(lb_rr_graph, lb_nets_[idx].rt_tree, RT_REMOVE, mode_map);
-      free_net_rt(lb_nets_[idx].rt_tree);
-      lb_nets_[idx].rt_tree = nullptr;
+      commit_remove_rt(lb_rr_graph, lb_net_rt_trees_[idx], RT_REMOVE, mode_map);
+      free_net_rt(lb_net_rt_trees_[idx]);
+      lb_net_rt_trees_[idx] = nullptr;
       add_source_to_rt(idx);
 
       /* Route each sink of net */
-      for (unsigned int itarget = 1; itarget < lb_nets_[idx].terminals.size() && !is_impossible; itarget++) {
+      for (unsigned int itarget = 1; itarget < lb_net_terminals_[idx].size() && !is_impossible; itarget++) {
         pq_.clear();
         /* Get lowest cost next node, repeat until a path is found or if it is impossible to route */
 
         expand_rt(idx, idx);
 
-        is_impossible = try_expand_nodes(atom_nlist, lb_rr_graph, lb_nets_[idx], exp_node, itarget, mode_status_.expand_all_modes, verbosity);
+        is_impossible = try_expand_nodes(atom_nlist, lb_rr_graph, idx, exp_node, itarget, mode_status_.expand_all_modes, verbosity);
 
         if (is_impossible && !mode_status_.expand_all_modes) {
           mode_status_.try_expand_all_modes = true;
@@ -164,15 +164,15 @@ bool LbRouter::try_route(const LbRRGraph& lb_rr_graph,
           break;
         }
 
-        if (exp_node.node_index == lb_nets_[idx].terminals[itarget]) {
+        if (exp_node.node_index == lb_net_terminals_[idx][itarget]) {
           /* Net terminal is routed, add this to the route tree, clear data structures, and keep going */
-          is_impossible = add_to_rt(lb_nets_[idx].rt_tree, exp_node.node_index, idx);
+          is_impossible = add_to_rt(lb_net_rt_trees_[idx], exp_node.node_index, idx);
         }
 
         if (is_impossible) {
           VTR_LOG("Routing was impossible!\n");
         } else if (mode_status_.expand_all_modes) {
-          is_impossible = route_has_conflict(lb_rr_graph, lb_nets_[idx].rt_tree);
+          is_impossible = route_has_conflict(lb_rr_graph, lb_net_rt_trees_[idx]);
           if (is_impossible) {
             VTR_LOG("Routing was impossible due to modes!\n");
           }
@@ -190,7 +190,7 @@ bool LbRouter::try_route(const LbRRGraph& lb_rr_graph,
       }
 
       if (!is_impossible) {
-        commit_remove_rt(lb_rr_graph, lb_nets_[idx].rt_tree, RT_COMMIT, mode_map);
+        commit_remove_rt(lb_rr_graph, lb_net_rt_trees_[idx], RT_COMMIT, mode_map);
         if (mode_status_.is_mode_conflict) {
           is_impossible = true;
         }
@@ -202,7 +202,7 @@ bool LbRouter::try_route(const LbRRGraph& lb_rr_graph,
     } else {
       --inet;
       VTR_LOGV(verbosity < 3, "Net '%s' is impossible to route within proposed %s cluster\n",
-               atom_nlist.net_name(lb_nets_[NetId(inet)].atom_net_id).c_str(), lb_type_->name);
+               atom_nlist.net_name(lb_net_atom_net_ids_[NetId(inet)]).c_str(), lb_type_->name);
       is_routed_ = false;
     }
     pres_con_fac_ *= params_.pres_fac_mult;
@@ -222,11 +222,11 @@ bool LbRouter::try_route(const LbRRGraph& lb_rr_graph,
  *************************************************/
 void LbRouter::fix_duplicate_equivalent_pins(const AtomContext& atom_ctx,
                                              const LbRRGraph& lb_rr_graph) {
-  for (size_t ilb_net = 0; ilb_net < lb_nets_.size(); ++ilb_net) {
+  for (const NetId& ilb_net : lb_net_ids_) {
     //Collect all the sink terminals indicies which target a particular node
     std::map<LbRRNodeId, std::vector<int>> duplicate_terminals;
-    for (size_t iterm = 1; iterm < lb_nets_[NetId(ilb_net)].terminals.size(); ++iterm) {
-      LbRRNodeId node = lb_nets_[NetId(ilb_net)].terminals[iterm];
+    for (size_t iterm = 1; iterm < lb_net_terminals_[ilb_net].size(); ++iterm) {
+      LbRRNodeId node = lb_net_terminals_[ilb_net][iterm];
 
       duplicate_terminals[node].push_back(iterm);
     }
@@ -238,8 +238,8 @@ void LbRouter::fix_duplicate_equivalent_pins(const AtomContext& atom_ctx,
       for (size_t idup_term = 0; idup_term < kv.second.size(); ++idup_term) {
         int iterm = kv.second[idup_term]; //The index in terminals which is duplicated
 
-        VTR_ASSERT(lb_nets_[NetId(ilb_net)].atom_pins.size() == lb_nets_[NetId(ilb_net)].terminals.size());
-        AtomPinId atom_pin = lb_nets_[NetId(ilb_net)].atom_pins[iterm];
+        VTR_ASSERT(lb_net_atom_pins_[ilb_net].size() == lb_net_terminals_[ilb_net].size());
+        AtomPinId atom_pin = lb_net_atom_pins_[ilb_net][iterm];
         VTR_ASSERT(atom_pin);
 
         const t_pb_graph_pin* pb_graph_pin = find_pb_graph_pin(atom_ctx.nlist, atom_ctx.lookup, atom_pin);
@@ -255,16 +255,16 @@ void LbRouter::fix_duplicate_equivalent_pins(const AtomContext& atom_ctx,
             "Found duplicate nets connected to logically equivalent pins. "
             "Remapping intra lb net %d (atom net %zu '%s') from common sink "
             "pb_route %d to fixed pin pb_route %d\n",
-            ilb_net, size_t(lb_nets_[NetId(ilb_net)].atom_net_id), atom_ctx.nlist.net_name(lb_nets_[NetId(ilb_net)].atom_net_id).c_str(),
+            size_t(ilb_net), size_t(lb_net_atom_net_ids_[ilb_net]), atom_ctx.nlist.net_name(lb_net_atom_net_ids_[ilb_net]).c_str(),
             kv.first, size_t(pin_index));
 
         VTR_ASSERT(1 == lb_rr_graph.node_out_edges(pin_index, &(pb_graph_pin->parent_node->pb_type->modes[0])).size());
         LbRRNodeId sink_index = lb_rr_graph.edge_sink_node(lb_rr_graph.node_out_edges(pin_index, &(pb_graph_pin->parent_node->pb_type->modes[0]))[0]);
         VTR_ASSERT(LB_SINK == lb_rr_graph.node_type(sink_index));
-        VTR_ASSERT_MSG(sink_index == lb_nets_[NetId(ilb_net)].terminals[iterm], "Remapped pin must be connected to original sink");
+        VTR_ASSERT_MSG(sink_index == lb_net_terminals_[ilb_net][iterm], "Remapped pin must be connected to original sink");
 
         //Change the target
-        lb_nets_[NetId(ilb_net)].terminals[iterm] = pin_index;
+        lb_net_terminals_[ilb_net][iterm] = pin_index;
       }
     }
   }
@@ -432,9 +432,9 @@ bool LbRouter::add_to_rt(t_trace* rt, const LbRRNodeId& node_index, const NetId&
 
 void LbRouter::add_source_to_rt(const NetId& inet) {
   /* TODO: Validate net id */
-  VTR_ASSERT(nullptr == lb_nets_[inet].rt_tree);
-  lb_nets_[inet].rt_tree = new t_trace;
-  lb_nets_[inet].rt_tree->current_node = lb_nets_[inet].terminals[0];
+  VTR_ASSERT(nullptr == lb_net_rt_trees_[inet]);
+  lb_net_rt_trees_[inet] = new t_trace;
+  lb_net_rt_trees_[inet]->current_node = lb_net_terminals_[inet][0];
 }
 
 void LbRouter::expand_rt_rec(t_trace* rt,
@@ -463,7 +463,7 @@ void LbRouter::expand_rt(const NetId& inet,
                          const NetId& irt_net) {
   VTR_ASSERT(pq_.empty());
 
-  expand_rt_rec(lb_nets_[inet].rt_tree, LbRRNodeId::INVALID(), irt_net, explore_id_index_);
+  expand_rt_rec(lb_net_rt_trees_[inet], LbRRNodeId::INVALID(), irt_net, explore_id_index_);
 }
 
 void LbRouter::expand_edges(const LbRRGraph& lb_rr_graph,
@@ -582,7 +582,7 @@ void LbRouter::expand_node_all_modes(const LbRRGraph& lb_rr_graph,
 
 bool LbRouter::try_expand_nodes(const AtomNetlist& atom_nlist,
                                 const LbRRGraph& lb_rr_graph,
-                                const t_net& lb_net,
+                                const NetId& lb_net,
                                 t_expansion_node& exp_node,
                                 const int& itarget,
                                 const bool& try_other_modes,
@@ -596,11 +596,11 @@ bool LbRouter::try_expand_nodes(const AtomNetlist& atom_nlist,
 
       if (verbosity > 3) {
         //Print detailed debug info
-        AtomNetId net_id = lb_net.atom_net_id;
-        AtomPinId driver_pin = lb_net.atom_pins[0];
-        AtomPinId sink_pin = lb_net.atom_pins[itarget];
-        LbRRNodeId driver_rr_node = lb_net.terminals[0];
-        LbRRNodeId sink_rr_node = lb_net.terminals[itarget];
+        AtomNetId net_id = lb_net_atom_net_ids_[lb_net];
+        AtomPinId driver_pin = lb_net_atom_pins_[lb_net][0];
+        AtomPinId sink_pin = lb_net_atom_pins_[lb_net][itarget];
+        LbRRNodeId driver_rr_node = lb_net_terminals_[lb_net][0];
+        LbRRNodeId sink_rr_node = lb_net_terminals_[lb_net][itarget];
 
         VTR_LOG("\t\t\tNo possible routing path from %s to %s: needed for net '%s' from net pin '%s'",
                 describe_lb_rr_node(lb_rr_graph, driver_rr_node).c_str(),
@@ -622,16 +622,16 @@ bool LbRouter::try_expand_nodes(const AtomNetlist& atom_nlist,
          */
         explored_node_tb_[exp_inode].explored_id = explore_id_index_;
         explored_node_tb_[exp_inode].prev_index = exp_node.prev_index;
-        if (exp_inode != lb_net.terminals[itarget]) {
+        if (exp_inode != lb_net_terminals_[lb_net][itarget]) {
           if (!try_other_modes) {
-            expand_node(lb_rr_graph, exp_node, lb_net.terminals.size() - 1);
+            expand_node(lb_rr_graph, exp_node, lb_net_terminals_[lb_net].size() - 1);
           } else {
-            expand_node_all_modes(lb_rr_graph, exp_node, lb_net.terminals.size() - 1);
+            expand_node_all_modes(lb_rr_graph, exp_node, lb_net_terminals_[lb_net].size() - 1);
           }
         }
       }
     }
-  } while (exp_node.node_index != lb_net.terminals[itarget] && !is_impossible);
+  } while (exp_node.node_index != lb_net_terminals_[lb_net][itarget] && !is_impossible);
 
   return is_impossible;
 }
@@ -658,9 +658,9 @@ void LbRouter::reset_explored_node_tb() {
 }
 
 void LbRouter::reset_net_rt() {
-  for (unsigned int inet = 0; inet < lb_nets_.size(); inet++) {
-    free_net_rt(lb_nets_[NetId(inet)].rt_tree);
-    lb_nets_[NetId(inet)].rt_tree = nullptr;
+  for (const NetId& inet : lb_net_ids_) {
+    free_net_rt(lb_net_rt_trees_[inet]);
+    lb_net_rt_trees_[inet] = nullptr;
   }
 }
 
@@ -672,11 +672,15 @@ void LbRouter::reset_routing_status() {
 }
 
 void LbRouter::clear_nets() {
+  /* TODO: Trace should no longer use pointers */
   reset_net_rt();
-  for (unsigned int i = 0; i < lb_nets_.size(); i++) {
-    lb_nets_[NetId(i)].terminals.clear();
-  }
-  lb_nets_.clear();
+
+  lb_net_ids_.clear();
+  lb_net_atom_net_ids_.clear();
+  lb_net_atom_pins_.clear();
+  lb_net_terminals_.clear();
+  lb_net_fixed_terminals_.clear();
+  lb_net_rt_trees_.clear();
 }
 
 void LbRouter::free_net_rt(t_trace* lb_trace) {
diff --git a/openfpga/src/repack/lb_router.h b/openfpga/src/repack/lb_router.h
index 44bd7b1b8..a922d1fb4 100644
--- a/openfpga/src/repack/lb_router.h
+++ b/openfpga/src/repack/lb_router.h
@@ -28,18 +28,6 @@ class LbRouter {
     struct net_id_tag;
     typedef vtr::StrongId<net_id_tag> NetId;
   public: /* Intra-Logic Block Routing Data Structures (by instance) */
-    /**************************************************************************
-     * A routing traceback data structure, provides a logic cluster_ctx.blocks 
-     * instance specific trace lookup directly from the t_lb_type_rr_node array index
-     * After packing, routing info for each CLB will have an array of t_lb_traceback 
-     * to store routing info within the CLB
-     ***************************************************************************/
-    struct t_traceback {
-      int net;             /* net of flat, technology-mapped, netlist using this node */
-      LbRRNodeId prev_lb_rr_node; /* index of previous node that drives current node */
-      LbRREdgeId prev_edge;       /* index of previous edge that drives current node */
-    };
-
     /**************************************************************************
      * Describes the status of a logic cluster_ctx.blocks routing resource node 
      * for a given logic cluster_ctx.blocks instance
@@ -68,23 +56,6 @@ class LbRouter {
       std::vector<t_trace> next_nodes; /* index of previous edge that drives current node */
     };
 
-    /**************************************************************************
-     * Represents a net used inside a logic cluster_ctx.blocks and the 
-     * physical nodes used by the net
-     ***************************************************************************/
-    struct t_net {
-      AtomNetId atom_net_id;             /* index of atom net this intra_lb_net represents */
-      std::vector<LbRRNodeId> terminals; /* endpoints of the intra_lb_net, 0th position is the source, all others are sinks */
-      std::vector<AtomPinId> atom_pins;  /* AtomPin's associated with each terminal */
-      std::vector<bool> fixed_terminals; /* Marks a terminal as having a fixed target (i.e. a pin not a sink) */
-      t_trace* rt_tree;               /* Route tree head */
-    
-      t_net() {
-          atom_net_id = AtomNetId::INVALID();
-          rt_tree = nullptr;
-      }
-    };
-
     /**************************************************************************
      * Stores tuning parameters used by intra-logic cluster_ctx.blocks router 
      ***************************************************************************/
@@ -199,6 +170,19 @@ class LbRouter {
     /* Show if a valid routing solution has been founded or not */
     bool is_routed() const;
 
+  public : /* Public mutators */
+    /**
+     * Add net to be routed
+     */ 
+
+    /**
+     * Perform routing algorithm on a given logical tile routing resource graph
+     * Note: the lb_rr_graph must be the same as you initilized the router!!!
+     */
+    bool try_route(const LbRRGraph& lb_rr_graph,
+                   const AtomNetlist& atom_nlist,
+                   const int& verbosity);
+
   private :  /* Private accessors */
     /**
      * Report if the routing is successfully done on a logical block routing resource graph
@@ -213,15 +197,6 @@ class LbRouter {
 
     bool route_has_conflict(const LbRRGraph& lb_rr_graph, t_trace* rt) const;
 
-  public : /* Public mutators */
-    /**
-     * Perform routing algorithm on a given logical tile routing resource graph
-     * Note: the lb_rr_graph must be the same as you initilized the router!!!
-     */
-    bool try_route(const LbRRGraph& lb_rr_graph,
-                   const AtomNetlist& atom_nlist,
-                   const int& verbosity);
-
   private : /* Private mutators */
     /*It is possible that a net may connect multiple times to a logically equivalent set of primitive pins.
      *The cluster router will only route one connection for a particular net to the common sink of the
@@ -262,7 +237,7 @@ class LbRouter {
                                const int& net_fanout);
     bool try_expand_nodes(const AtomNetlist& atom_nlist,
                           const LbRRGraph& lb_rr_graph,
-                          const t_net& lb_net,
+                          const NetId& lb_net,
                           t_expansion_node& exp_node,
                           const int& itarget,
                           const bool& try_other_modes,
@@ -286,7 +261,12 @@ class LbRouter {
 
   private : /* Stores all data needed by intra-logic cluster_ctx.blocks router */
     /* Logical Netlist Info */
-    vtr::vector<NetId, t_net> lb_nets_; /* Pointer to vector of intra logic cluster_ctx.blocks nets and their connections */
+    vtr::vector<NetId, NetId> lb_net_ids_; /* Pointer to vector of intra logic cluster_ctx.blocks nets and their connections */
+    vtr::vector<NetId, AtomNetId> lb_net_atom_net_ids_;             /* index of atom net this intra_lb_net represents */
+    vtr::vector<NetId, std::vector<AtomPinId>> lb_net_atom_pins_;  /* AtomPin's associated with each terminal */
+    vtr::vector<NetId, std::vector<LbRRNodeId>> lb_net_terminals_; /* endpoints of the intra_lb_net, 0th position is the source, all others are sinks */
+    vtr::vector<NetId, std::vector<bool>> lb_net_fixed_terminals_; /* Marks a terminal as having a fixed target (i.e. a pin not a sink) */
+    vtr::vector<NetId, t_trace*> lb_net_rt_trees_;               /* Route tree head */
 
     /* Logical-to-physical mapping info */
     vtr::vector<LbRRNodeId, t_routing_status> routing_status_; /* [0..lb_type_graph->size()-1] Stats for each logic cluster_ctx.blocks rr node instance */

From 43f15e4d6f4beb92a1922194e1b3cc8ad4584a08 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 19 Feb 2020 16:40:53 -0700
Subject: [PATCH 183/645] add methods to LbRouter for nets to be routed and
 access to routing traceback

---
 openfpga/src/repack/lb_router.cpp | 59 ++++++++++++++++++++++++++++++-
 openfpga/src/repack/lb_router.h   | 15 +++++++-
 2 files changed, 72 insertions(+), 2 deletions(-)

diff --git a/openfpga/src/repack/lb_router.cpp b/openfpga/src/repack/lb_router.cpp
index 610501dde..3ce17deaa 100644
--- a/openfpga/src/repack/lb_router.cpp
+++ b/openfpga/src/repack/lb_router.cpp
@@ -59,6 +59,22 @@ bool LbRouter::is_routed() const {
   return is_routed_;
 }
 
+std::vector<LbRRNodeId> LbRouter::net_routed_nodes(const NetId& net) const {
+  VTR_ASSERT(true == is_routed());
+  VTR_ASSERT(true == valid_net_id(net));
+
+  std::vector<LbRRNodeId> routed_nodes;
+
+  t_trace* rt_tree = lb_net_rt_trees_[net];
+  if (nullptr == rt_tree) {
+    return routed_nodes;
+  }
+  /* Walk through the routing tree of the net */
+  rec_collect_trace_nodes(rt_tree, routed_nodes);  
+
+  return routed_nodes;  
+}
+
 /**************************************************
  * Private accessors
  *************************************************/
@@ -108,9 +124,47 @@ bool LbRouter::route_has_conflict(const LbRRGraph& lb_rr_graph, t_trace* rt) con
   return false;
 }
 
+void LbRouter::rec_collect_trace_nodes(const t_trace* trace, std::vector<LbRRNodeId>& routed_nodes) const {
+  if (routed_nodes.end() == std::find(routed_nodes.begin(), routed_nodes.end(), trace->current_node)) {
+    routed_nodes.push_back(trace->current_node);
+  }
+
+  for (const t_trace& next : trace->next_nodes) {
+    rec_collect_trace_nodes(&next, routed_nodes);
+  }
+}
+
 /**************************************************
  * Public mutators
  *************************************************/
+LbRouter::NetId LbRouter::create_net_to_route(const LbRRNodeId& source, const std::vector<LbRRNodeId>& terminals) {
+  /* Create an new id */
+  NetId net = NetId(lb_net_ids_.size());
+  lb_net_ids_.push_back(net);
+
+  /* Allocate other attributes */
+  lb_net_atom_net_ids_.push_back(AtomNetId::INVALID());
+  lb_net_atom_pins_.emplace_back();
+  
+  std::vector<LbRRNodeId> net_terminals = terminals;
+  net_terminals.insert(net_terminals.begin(), source);
+
+  lb_net_terminals_.push_back(net_terminals);
+
+  return net;
+}
+
+void LbRouter::add_net_atom_net_id(const NetId& net, const AtomNetId& atom_net) {
+  VTR_ASSERT(true == valid_net_id(net));
+  lb_net_atom_net_ids_[net] = atom_net;
+}
+
+void LbRouter::add_net_atom_pins(const NetId& net, const AtomPinId& src_pin, const std::vector<AtomPinId>& terminal_pins) {
+  VTR_ASSERT(true == valid_net_id(net));
+  lb_net_atom_pins_[net] = terminal_pins;
+  lb_net_atom_pins_[net].insert(lb_net_atom_pins_[net].begin(), src_pin);
+}
+
 bool LbRouter::try_route(const LbRRGraph& lb_rr_graph,
                          const AtomNetlist& atom_nlist,
                          const int& verbosity) {
@@ -644,6 +698,10 @@ bool LbRouter::matched_lb_rr_graph(const LbRRGraph& lb_rr_graph) const {
         && (explored_node_tb_.size() == lb_rr_graph.nodes().size()) );
 }
 
+bool LbRouter::valid_net_id(const NetId& net_id) const {
+  return ( size_t(net_id) < lb_net_ids_.size() ) && ( net_id == lb_net_ids_[net_id] ); 
+}
+
 /**************************************************
  * Private Initializer and cleaner
  *************************************************/
@@ -679,7 +737,6 @@ void LbRouter::clear_nets() {
   lb_net_atom_net_ids_.clear();
   lb_net_atom_pins_.clear();
   lb_net_terminals_.clear();
-  lb_net_fixed_terminals_.clear();
   lb_net_rt_trees_.clear();
 }
 
diff --git a/openfpga/src/repack/lb_router.h b/openfpga/src/repack/lb_router.h
index a922d1fb4..117ede40c 100644
--- a/openfpga/src/repack/lb_router.h
+++ b/openfpga/src/repack/lb_router.h
@@ -170,10 +170,19 @@ class LbRouter {
     /* Show if a valid routing solution has been founded or not */
     bool is_routed() const;
 
+    /**
+     * Get the routing results for a Net 
+     */
+    std::vector<LbRRNodeId> net_routed_nodes(const NetId& net) const;
+
   public : /* Public mutators */
     /**
      * Add net to be routed
      */ 
+    NetId create_net_to_route(const LbRRNodeId& source, const std::vector<LbRRNodeId>& terminals);
+    void add_net_atom_net_id(const NetId& net, const AtomNetId& atom_net);
+    void add_net_atom_pins(const NetId& net, const AtomPinId& src_pin, const std::vector<AtomPinId>& terminal_pins);
+    void set_net_fix_terminal(const NetId& net, const LbRRNodeId& terminal, const bool& fix);
 
     /**
      * Perform routing algorithm on a given logical tile routing resource graph
@@ -197,6 +206,9 @@ class LbRouter {
 
     bool route_has_conflict(const LbRRGraph& lb_rr_graph, t_trace* rt) const;
 
+    /* Recursively find all the nodes in the trace */
+    void rec_collect_trace_nodes(const t_trace* trace, std::vector<LbRRNodeId>& routed_nodes) const;
+
   private : /* Private mutators */
     /*It is possible that a net may connect multiple times to a logically equivalent set of primitive pins.
      *The cluster router will only route one connection for a particular net to the common sink of the
@@ -249,6 +261,8 @@ class LbRouter {
      */
     bool matched_lb_rr_graph(const LbRRGraph& lb_rr_graph) const;
 
+    bool valid_net_id(const NetId& net_id) const;
+
   private :  /* Private initializer and cleaner */
     void reset_explored_node_tb();
     void reset_net_rt();
@@ -265,7 +279,6 @@ class LbRouter {
     vtr::vector<NetId, AtomNetId> lb_net_atom_net_ids_;             /* index of atom net this intra_lb_net represents */
     vtr::vector<NetId, std::vector<AtomPinId>> lb_net_atom_pins_;  /* AtomPin's associated with each terminal */
     vtr::vector<NetId, std::vector<LbRRNodeId>> lb_net_terminals_; /* endpoints of the intra_lb_net, 0th position is the source, all others are sinks */
-    vtr::vector<NetId, std::vector<bool>> lb_net_fixed_terminals_; /* Marks a terminal as having a fixed target (i.e. a pin not a sink) */
     vtr::vector<NetId, t_trace*> lb_net_rt_trees_;               /* Route tree head */
 
     /* Logical-to-physical mapping info */

From bc27f9dd0c788376c770782ad21bef36c9025e5f Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 19 Feb 2020 20:34:30 -0700
Subject: [PATCH 184/645] add check codes for nets inside LbRouter

---
 openfpga/src/repack/lb_router.cpp | 36 +++++++++++++++++++++++++++++++
 openfpga/src/repack/lb_router.h   |  8 +++++++
 2 files changed, 44 insertions(+)

diff --git a/openfpga/src/repack/lb_router.cpp b/openfpga/src/repack/lb_router.cpp
index 3ce17deaa..1244143a0 100644
--- a/openfpga/src/repack/lb_router.cpp
+++ b/openfpga/src/repack/lb_router.cpp
@@ -171,7 +171,13 @@ bool LbRouter::try_route(const LbRRGraph& lb_rr_graph,
   /* Validate if the rr_graph is the one we used to initialize the router */
   VTR_ASSERT(true == matched_lb_rr_graph(lb_rr_graph));
 
+  /* Ensure each net to be routed is valid */
+  for (const NetId& net : lb_net_ids_) {
+    VTR_ASSERT(true == check_net(lb_rr_graph, atom_nlist, net));
+  }
+
   is_routed_ = false;
+
   bool is_impossible = false;
 
   mode_status_.is_mode_conflict = false;
@@ -198,6 +204,7 @@ bool LbRouter::try_route(const LbRRGraph& lb_rr_graph,
       if (is_skip_route_net(lb_rr_graph, lb_net_rt_trees_[idx])) {
         continue;
       }
+
       commit_remove_rt(lb_rr_graph, lb_net_rt_trees_[idx], RT_REMOVE, mode_map);
       free_net_rt(lb_net_rt_trees_[idx]);
       lb_net_rt_trees_[idx] = nullptr;
@@ -702,6 +709,35 @@ bool LbRouter::valid_net_id(const NetId& net_id) const {
   return ( size_t(net_id) < lb_net_ids_.size() ) && ( net_id == lb_net_ids_[net_id] ); 
 }
 
+bool LbRouter::check_net(const LbRRGraph& lb_rr_graph,
+                         const AtomNetlist& atom_nlist,
+                         const NetId& net) const {
+  if (false == atom_nlist.valid_net_id(lb_net_atom_net_ids_[net])) {
+    return false;
+  }
+  if (lb_net_atom_pins_[net].size() != lb_net_terminals_[net].size()) {
+    return false;
+  }
+  /* We must have 1 source and >1 terminal */
+  if (2 > lb_net_terminals_[net].size()) {
+    return false;
+  } 
+  /* Each node must be valid */
+  for (const LbRRNodeId& node : lb_net_terminals_[net]) {
+    if (false == lb_rr_graph.valid_node_id(node)) {
+      return false;
+    }
+  }
+  /* Each atom pin must be valid */
+  for (const AtomPinId& pin : lb_net_atom_pins_[net]) {
+    if (false == atom_nlist.valid_pin_id(pin)) {
+      return false;
+    }
+  }
+
+  return true;
+}
+
 /**************************************************
  * Private Initializer and cleaner
  *************************************************/
diff --git a/openfpga/src/repack/lb_router.h b/openfpga/src/repack/lb_router.h
index 117ede40c..3a1f299af 100644
--- a/openfpga/src/repack/lb_router.h
+++ b/openfpga/src/repack/lb_router.h
@@ -263,6 +263,14 @@ class LbRouter {
 
     bool valid_net_id(const NetId& net_id) const;
 
+    /* Validate that all the nets have 
+     * - valid source, terminal nodes in lb routing resource graph
+     * - valid atom net and pin ids in atom netlist
+     */
+    bool check_net(const LbRRGraph& lb_rr_graph,
+                   const AtomNetlist& atom_nlist,
+                   const NetId& net) const;
+
   private :  /* Private initializer and cleaner */
     void reset_explored_node_tb();
     void reset_net_rt();

From ed5d83178f0a4b582a224d28afd0d73c72ec8f3d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 19 Feb 2020 21:07:31 -0700
Subject: [PATCH 185/645] add fundamental check codes for LbRRGraph

---
 .../src/repack/build_physical_lb_rr_graph.cpp |   7 +
 openfpga/src/repack/lb_rr_graph.cpp           | 191 ++++++++++++++++++
 openfpga/src/repack/lb_rr_graph.h             |  16 +-
 3 files changed, 213 insertions(+), 1 deletion(-)

diff --git a/openfpga/src/repack/build_physical_lb_rr_graph.cpp b/openfpga/src/repack/build_physical_lb_rr_graph.cpp
index aca8cb0d1..e79985082 100644
--- a/openfpga/src/repack/build_physical_lb_rr_graph.cpp
+++ b/openfpga/src/repack/build_physical_lb_rr_graph.cpp
@@ -395,6 +395,13 @@ void build_physical_lb_rr_graphs(const DeviceContext& device_ctx,
              lb_type.pb_graph_head->pb_type->name);
 
     const LbRRGraph& lb_rr_graph = build_lb_type_physical_lb_rr_graph(lb_type.pb_graph_head, const_cast<const VprDeviceAnnotation&>(device_annotation), verbose); 
+    /* Check the rr_graph */
+    if (false == lb_rr_graph.validate()) {
+      exit(1);
+    }
+    VTR_LOGV(verbose, 
+             "Check routing resource graph for logical tile passed\n");
+
     device_annotation.add_physical_lb_rr_graph(lb_type.pb_graph_head, lb_rr_graph);
   }
 
diff --git a/openfpga/src/repack/lb_rr_graph.cpp b/openfpga/src/repack/lb_rr_graph.cpp
index 434ac0b3e..db43543da 100644
--- a/openfpga/src/repack/lb_rr_graph.cpp
+++ b/openfpga/src/repack/lb_rr_graph.cpp
@@ -262,4 +262,195 @@ bool LbRRGraph::valid_edge_id(const LbRREdgeId& edge_id) const {
   return ( size_t(edge_id) < edge_ids_.size() ) && ( edge_id == edge_ids_[edge_id] ); 
 }
 
+/* This function run fundamental checks on internal data 
+ * Errors are thrown if fundamental checking fails
+ */
+bool LbRRGraph::validate() const {
+  size_t num_err = 0;
+
+  /* Validate the sizes of nodes and node-related vectors 
+   * Validate the sizes of edges and edge-related vectors 
+   */
+  if (false == validate_sizes()) {
+    VTR_LOG_WARN("Fail in validating node and edges sizes!\n");
+    num_err++;
+  }
+
+  /* Fundamental check */
+  if (false == validate_nodes_edges()) {
+    VTR_LOG_WARN("Fail in validating edges connected to each node!\n");
+    num_err++;
+  }
+
+  /* Error out if there is any fatal errors found */
+  if (0 < num_err) {
+    VTR_LOG_ERROR("Logical tile Routing Resource graph is not valid due to %d fatal errors !\n",
+                  num_err);
+  }
+
+  return (0 == num_err);
+}
+
+/******************************************************************************
+ * Private validators/invalidators
+ ******************************************************************************/
+bool LbRRGraph::validate_node_sizes() const {
+  size_t num_nodes = node_ids_.size();
+  return node_ids_.size() == num_nodes
+         && node_types_.size() == num_nodes
+         && node_capacities_.size() == num_nodes
+         && node_pb_graph_pins_.size() == num_nodes
+         && node_intrinsic_costs_.size() == num_nodes
+         && node_in_edges_.size() == num_nodes
+         && node_out_edges_.size() == num_nodes;
+}
+
+bool LbRRGraph::validate_edge_sizes() const {
+  size_t num_edges = edge_ids_.size();
+  return edge_src_nodes_.size() == num_edges
+         && edge_sink_nodes_.size() == num_edges
+         && edge_intrinsic_costs_.size() == num_edges
+         && edge_modes_.size() == num_edges;
+}
+
+bool LbRRGraph::validate_sizes() const {
+  return validate_node_sizes() && validate_edge_sizes(); 
+}
+
+/* Check if a node is in the list of source_nodes of a edge */
+bool LbRRGraph::validate_node_is_edge_src(const LbRRNodeId& node, const LbRREdgeId& edge) const {
+  /* Assure a valid node id */
+  VTR_ASSERT_SAFE(valid_node_id(node));
+  /* assure a valid edge id */
+  VTR_ASSERT_SAFE(valid_edge_id(edge));
+  /* find if the node is the src */
+  if (node == edge_src_node(edge)) {
+    return true; /* confirmed source node*/
+  } else {
+    return false; /* not a source */
+  }
+}
+
+/* Check if a node is in the list of sink_nodes of a edge */
+bool LbRRGraph::validate_node_is_edge_sink(const LbRRNodeId& node, const LbRREdgeId& edge) const {
+  /* Assure a valid node id */
+  VTR_ASSERT_SAFE(valid_node_id(node));
+  /* assure a valid edge id */
+  VTR_ASSERT_SAFE(valid_edge_id(edge));
+  /* find if the node is the sink */
+  if (node == edge_sink_node(edge)) {
+    return true; /* confirmed source node*/
+  } else {
+    return false; /* not a source */
+  }
+}
+/* This function will check if a node has valid input edges
+ * 1. Check the edge ids are valid
+ * 2. Check the node is in the list of edge_sink_node
+ */
+bool LbRRGraph::validate_node_in_edges(const LbRRNodeId& node) const {
+  bool all_valid = true;
+  /* Assure a valid node id */
+  VTR_ASSERT_SAFE(valid_node_id(node));
+  /* Check each edge */
+  for (auto edge : node_in_edges(node)) {
+      /* assure a valid edge id */
+      VTR_ASSERT_SAFE(valid_edge_id(edge));
+      /* check the node is in the list of edge_sink_node */
+      if (true == validate_node_is_edge_sink(node, edge)) {
+        continue;
+    }
+    /* Reach here, it means there is something wrong! 
+     * Print a warning  
+     */
+    VTR_LOG_WARN("Edge %d is in the input edge list of node %d while the node is not in edge's sink node list!\n",
+                  size_t(edge), size_t(node));
+    all_valid = false;
+  }
+
+  return all_valid;
+}
+
+/* This function will check if a node has valid output edges
+ * 1. Check the edge ids are valid
+ * 2. Check the node is in the list of edge_source_node
+ */
+bool LbRRGraph::validate_node_out_edges(const LbRRNodeId& node) const {
+  bool all_valid = true;
+  /* Assure a valid node id */
+  VTR_ASSERT_SAFE(valid_node_id(node));
+  /* Check each edge */
+  for (auto edge : node_out_edges(node)) {
+    /* assure a valid edge id */
+    VTR_ASSERT_SAFE(valid_edge_id(edge));
+    /* check the node is in the list of edge_sink_node */
+    if (true == validate_node_is_edge_src(node, edge)) {
+      continue;
+    }
+    /* Reach here, it means there is something wrong! 
+     * Print a warning  
+     */
+    VTR_LOG_WARN("Edge %d is in the output edge list of node %d while the node is not in edge's source node list!\n",
+                 size_t(edge), size_t(node));
+    all_valid = false;
+  }
+
+  return all_valid;
+}
+
+
+/* check if all the nodes' input edges are valid */
+bool LbRRGraph::validate_nodes_in_edges() const {
+  bool all_valid = true;
+  for (const LbRRNodeId& id : nodes()) {
+    /* Try to find if this is an invalid id or not */
+    if (!valid_node_id(id)) {
+      /* Skip this id */
+      continue;
+    }
+    if (true == validate_node_in_edges(id)) {
+      continue;
+    }
+    /* Reach here, it means there is something wrong! 
+     * Print a warning  
+     */
+    all_valid = false;
+  }
+  return all_valid;
+}
+
+/* check if all the nodes' output edges are valid */
+bool LbRRGraph::validate_nodes_out_edges() const {
+  bool all_valid = true;
+  for (const LbRRNodeId& id : nodes()) {
+    /* Try to find if this is an invalid id or not */
+    if (!valid_node_id(id)) {
+      /* Skip this id */
+      continue;
+    }
+    if (true == validate_node_out_edges(id)) {
+      continue;
+    }
+    /* Reach here, it means there is something wrong! 
+     * Print a warning  
+     */
+    all_valid = false;
+  }
+  return all_valid;
+}
+
+/* check all the edges of every node */
+bool LbRRGraph::validate_nodes_edges() const {
+  bool all_valid = true;
+
+  if (false == validate_nodes_in_edges()) {
+    all_valid = false;
+  }
+  if (false == validate_nodes_out_edges()) {
+    all_valid = false;
+  }
+
+  return all_valid;
+}
+
 } /* end namespace openfpga */
diff --git a/openfpga/src/repack/lb_rr_graph.h b/openfpga/src/repack/lb_rr_graph.h
index 4500a504b..3aca85934 100644
--- a/openfpga/src/repack/lb_rr_graph.h
+++ b/openfpga/src/repack/lb_rr_graph.h
@@ -266,13 +266,27 @@ class LbRRGraph {
     LbRREdgeId create_edge(const LbRRNodeId& source, const LbRRNodeId& sink, t_mode* mode);
     void set_edge_intrinsic_cost(const LbRREdgeId& edge, const float& cost);
 
-  public: /* Validators */
+  public: /* Public validators */
     /* Validate is the node id does exist in the RRGraph */
     bool valid_node_id(const LbRRNodeId& node) const;
 
     /* Validate is the edge id does exist in the RRGraph */
     bool valid_edge_id(const LbRREdgeId& edge) const;
 
+    bool validate() const;
+
+  private: /* Private Validators */
+    bool validate_node_sizes() const;
+    bool validate_edge_sizes() const;
+    bool validate_sizes() const;
+    bool validate_node_is_edge_src(const LbRRNodeId& node, const LbRREdgeId& edge) const;
+    bool validate_node_is_edge_sink(const LbRRNodeId& node, const LbRREdgeId& edge) const;
+    bool validate_node_in_edges(const LbRRNodeId& node) const;
+    bool validate_node_out_edges(const LbRRNodeId& node) const;
+    bool validate_nodes_in_edges() const;
+    bool validate_nodes_out_edges() const;
+    bool validate_nodes_edges() const;
+
   private: /* Internal Data */
     /* Node related data */
     vtr::vector<LbRRNodeId, LbRRNodeId> node_ids_;

From d8ab5536e110324343e02f6cf2d4718f0fee2f15 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 19 Feb 2020 21:41:05 -0700
Subject: [PATCH 186/645] add advanced check codes for lb_rr_graph

---
 .../src/repack/build_physical_lb_rr_graph.cpp |   4 +
 openfpga/src/repack/check_lb_rr_graph.cpp     | 206 ++++++++++++++++++
 openfpga/src/repack/check_lb_rr_graph.h       |  21 ++
 openfpga/src/repack/lb_rr_graph_utils.cpp     |  13 ++
 openfpga/src/repack/lb_rr_graph_utils.h       |   3 +
 5 files changed, 247 insertions(+)
 create mode 100644 openfpga/src/repack/check_lb_rr_graph.cpp
 create mode 100644 openfpga/src/repack/check_lb_rr_graph.h

diff --git a/openfpga/src/repack/build_physical_lb_rr_graph.cpp b/openfpga/src/repack/build_physical_lb_rr_graph.cpp
index e79985082..ae9fc4c65 100644
--- a/openfpga/src/repack/build_physical_lb_rr_graph.cpp
+++ b/openfpga/src/repack/build_physical_lb_rr_graph.cpp
@@ -10,6 +10,7 @@
 #include "pb_type_utils.h"
 
 #include "build_physical_lb_rr_graph.h"
+#include "check_lb_rr_graph.h"
 
 /* begin namespace openfpga */
 namespace openfpga {
@@ -399,6 +400,9 @@ void build_physical_lb_rr_graphs(const DeviceContext& device_ctx,
     if (false == lb_rr_graph.validate()) {
       exit(1);
     }
+    if (false == check_lb_rr_graph(lb_rr_graph)) {
+      exit(1);
+    }
     VTR_LOGV(verbose, 
              "Check routing resource graph for logical tile passed\n");
 
diff --git a/openfpga/src/repack/check_lb_rr_graph.cpp b/openfpga/src/repack/check_lb_rr_graph.cpp
new file mode 100644
index 000000000..9b3adbf8f
--- /dev/null
+++ b/openfpga/src/repack/check_lb_rr_graph.cpp
@@ -0,0 +1,206 @@
+#include <map>
+
+#include "vtr_log.h"
+
+#include "lb_rr_graph_utils.h"
+#include "check_lb_rr_graph.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/*********************************************************************** 
+ * This function aims at checking any duplicated edges (with same EdgeId) 
+ * of a given node. 
+ * We will walkthrough the input edges of a node and see if there is any duplication
+ **********************************************************************/
+static bool check_lb_rr_graph_node_duplicated_edges(const LbRRGraph& lb_rr_graph,
+                         const LbRRNodeId& node) {
+  bool no_duplication = true;
+
+  /* Create a map for each input edge */
+  std::map<const t_mode*, std::map<LbRREdgeId, size_t>> edge_counter;
+
+  /* Check each input edges */
+  for (const auto edge : lb_rr_graph.node_in_edges(node)) {
+    if (nullptr == lb_rr_graph.edge_mode(edge)) {
+      continue;
+    }
+    auto result = edge_counter[lb_rr_graph.edge_mode(edge)].insert(std::pair<LbRREdgeId, size_t>(edge, 1));
+    if (false == result.second) {
+      result.first->second++;
+    }
+  }
+
+  for (auto& edge_mode : edge_counter) {
+    for (auto& elem : edge_mode.second) {
+      if (elem.second > 1) {
+        /* Reach here it means we find some duplicated edges and report errors */
+        /* Print a warning! */
+        VTR_LOG_WARN("Node %d has duplicated input edges (id = %d)!\n",
+               size_t(node), size_t(elem.first));
+        print_lb_rr_node(lb_rr_graph, node);
+        no_duplication = false;
+      }
+    }
+  }
+
+  return no_duplication;
+}
+
+/*********************************************************************** 
+ * Check the whole Routing Resource Graph  
+ * identify and report any duplicated edges between two nodes 
+ **********************************************************************/
+static bool check_lb_rr_graph_duplicated_edges(const LbRRGraph& lb_rr_graph) {
+  bool no_duplication = true;
+  /* For each node:
+   * Search input edges, see there are two edges with same id or address 
+   */
+  for (const auto& node : lb_rr_graph.nodes()) {
+    if (false == check_lb_rr_graph_node_duplicated_edges(lb_rr_graph, node)) {
+      no_duplication = false;
+    }
+  }
+
+  return no_duplication;
+}
+
+/*********************************************************************** 
+ * Identify and report any dangling node (nodes without any fan-in or fan-out)
+ * in the LbRRGraph
+ **********************************************************************/
+static bool check_lb_rr_graph_dangling_nodes(const LbRRGraph& lb_rr_graph) {
+  bool no_dangling = true;
+  /* For each node: 
+   * check if the number of input edges and output edges are both 0
+   * If so, this is a dangling nodes and report 
+   */
+  for (auto node : lb_rr_graph.nodes()) {
+    if ((0 == lb_rr_graph.node_in_edges(node).size())
+      && (0 == lb_rr_graph.node_out_edges(node).size())) {
+      /* Print a warning! */
+      VTR_LOG_WARN("Node %s is dangling (zero fan-in and zero fan-out)!\n",
+             node);
+      VTR_LOG_WARN("Node details for debugging:\n");
+      print_lb_rr_node(lb_rr_graph, node);
+      no_dangling = false;
+    }
+  }
+
+  return no_dangling;
+}
+
+/*********************************************************************** 
+ * check if all the source nodes are in the right condition:
+ * 1. zero fan-in and non-zero fanout
+ **********************************************************************/
+static bool check_lb_rr_graph_source_nodes(const LbRRGraph& lb_rr_graph) {
+  bool invalid_sources = false;
+  /* For each node: 
+   * check if the number of input edges and output edges are both 0
+   * If so, this is a dangling nodes and report 
+   */
+  for (auto node : lb_rr_graph.nodes()) {
+    /* Pass nodes whose types are not LB_SOURCE */
+    if (LB_SOURCE != lb_rr_graph.node_type(node)) {
+      continue;
+    }
+    if ((0 != lb_rr_graph.node_in_edges(node).size())
+      || (0 == lb_rr_graph.node_out_edges(node).size())) {
+      /* Print a warning! */
+      VTR_LOG_WARN("Source node %d is invalid (should have zero fan-in and non-zero fan-out)!\n",
+             size_t(node));
+      VTR_LOG_WARN("Node details for debugging:\n");
+      print_lb_rr_node(lb_rr_graph, node);
+      invalid_sources = true;
+    }
+  }
+
+  return !invalid_sources;
+}
+
+/*********************************************************************** 
+ * check if all the sink nodes are in the right condition:
+ * 1. non-zero fan-in and zero fanout
+ **********************************************************************/
+static bool check_lb_rr_graph_sink_nodes(const LbRRGraph& lb_rr_graph) {
+  bool invalid_sinks = false;
+  /* For each node: 
+   * check if the number of input edges and output edges are both 0
+   * If so, this is a dangling nodes and report 
+   */
+  for (auto node : lb_rr_graph.nodes()) {
+    /* Pass nodes whose types are not LB_SINK */
+    if (LB_SINK != lb_rr_graph.node_type(node)) {
+      continue;
+    }
+    if ((0 == lb_rr_graph.node_in_edges(node).size())
+      || (0 != lb_rr_graph.node_out_edges(node).size())) {
+      /* Print a warning! */
+      VTR_LOG_WARN("Sink node %s is invalid (should have non-zero fan-in and zero fan-out)!\n",
+             node);
+      VTR_LOG_WARN("Node details for debugging:\n");
+      print_lb_rr_node(lb_rr_graph, node);
+      invalid_sinks = true;
+    }
+  }
+
+  return !invalid_sinks;
+}
+
+/*********************************************************************** 
+ * This is an advanced checker for LbRRGraph object
+ * Note that the checker try to report as many problems as it can. 
+ * The problems may cause routing efficiency or even failures, depending
+ * on routing algorithms.
+ * It is strongly suggested to run this sanitizer before conducting
+ * routing algorithms
+ * 
+ * For those who will develop customized lb_rr_graphs and routers:
+ * On the other hand, it is suggested that developers to create their 
+ * own checking function for the lb_rr_graph, to guarantee their routers
+ * will work properly.
+ **********************************************************************/
+bool check_lb_rr_graph(const LbRRGraph& lb_rr_graph) {
+  size_t num_err = 0;
+
+  if (false == check_lb_rr_graph_duplicated_edges(lb_rr_graph)) {
+    VTR_LOG_WARN("Fail in checking duplicated edges !\n");
+    num_err++;
+  }
+
+  if (false == check_lb_rr_graph_dangling_nodes(lb_rr_graph)) {
+    VTR_LOG_WARN("Fail in checking dangling nodes !\n");
+    num_err++;
+  }
+
+  if (false == check_lb_rr_graph_source_nodes(lb_rr_graph)) {
+    VTR_LOG_WARN("Fail in checking source nodes!\n");
+    num_err++;
+  }
+
+  if (false == check_lb_rr_graph_sink_nodes(lb_rr_graph)) {
+    VTR_LOG_WARN("Fail in checking sink nodes!\n");
+    num_err++;
+  }
+
+  if (false == check_lb_rr_graph_source_nodes(lb_rr_graph)) {
+    VTR_LOG_WARN("Fail in checking source nodes!\n");
+    num_err++;
+  }
+
+  if (false == check_lb_rr_graph_sink_nodes(lb_rr_graph)) {
+    VTR_LOG_WARN("Fail in checking sink nodes!\n");
+    num_err++;
+  }
+
+  /* Error out if there is any fatal errors found */
+  if (0 < num_err) {
+    VTR_LOG_WARN("Checked Logical tile Routing Resource graph with %d errors !\n",
+           num_err);
+  }
+
+  return (0 == num_err);
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/repack/check_lb_rr_graph.h b/openfpga/src/repack/check_lb_rr_graph.h
new file mode 100644
index 000000000..232fa597c
--- /dev/null
+++ b/openfpga/src/repack/check_lb_rr_graph.h
@@ -0,0 +1,21 @@
+#ifndef CHECK_LB_RR_GRAPH_H
+#define CHECK_LB_RR_GRAPH_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "lb_rr_graph.h"
+
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+bool check_lb_rr_graph(const LbRRGraph& rr_graph);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/repack/lb_rr_graph_utils.cpp b/openfpga/src/repack/lb_rr_graph_utils.cpp
index 351103647..a2e1df63a 100644
--- a/openfpga/src/repack/lb_rr_graph_utils.cpp
+++ b/openfpga/src/repack/lb_rr_graph_utils.cpp
@@ -57,4 +57,17 @@ std::string describe_lb_rr_node(const LbRRGraph& lb_rr_graph,
   return description;
 }
 
+/* This function aims to print basic information about a node */
+void print_lb_rr_node(const LbRRGraph& lb_rr_graph,
+                      const LbRRNodeId& node) {
+    VTR_LOG("Node id: %d\n", size_t(node));
+    VTR_LOG("Node type: %s\n", lb_rr_type_str[lb_rr_graph.node_type(node)]);
+    VTR_LOG("Node capacity: %d\n", lb_rr_graph.node_capacity(node));
+    VTR_LOG("Node pb_graph_pin: %s\n", lb_rr_graph.node_pb_graph_pin(node)->to_string().c_str());
+    VTR_LOG("Node intrinsic_cost: %f\n", lb_rr_graph.node_intrinsic_cost(node));
+    VTR_LOG("Node num in_edges: %ld\n", lb_rr_graph.node_in_edges(node).size());
+    VTR_LOG("Node num out_edges: %ld\n", lb_rr_graph.node_out_edges(node).size());
+}
+
+
 } /* end namespace openfpga */
diff --git a/openfpga/src/repack/lb_rr_graph_utils.h b/openfpga/src/repack/lb_rr_graph_utils.h
index 392617f6a..f493caa4f 100644
--- a/openfpga/src/repack/lb_rr_graph_utils.h
+++ b/openfpga/src/repack/lb_rr_graph_utils.h
@@ -17,6 +17,9 @@ namespace openfpga {
 std::string describe_lb_rr_node(const LbRRGraph& lb_rr_graph,
                                 const LbRRNodeId& inode);
 
+void print_lb_rr_node(const LbRRGraph& lb_rr_graph,
+                      const LbRRNodeId& node);
+
 } /* end namespace openfpga */
 
 #endif

From fdb27c5a6b4822e8cea7cf64460ad34279ca977d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 20 Feb 2020 13:24:34 -0700
Subject: [PATCH 187/645] move lb_rr_graph construction to repack command

---
 openfpga/src/base/openfpga_link_arch.cpp   |  6 ------
 openfpga/src/base/openfpga_repack.cpp      |  2 +-
 openfpga/src/repack/repack.cpp             | 10 ++++++++--
 openfpga/src/repack/repack.h               |  2 +-
 openfpga/test_script/s298_k6_frac.openfpga |  5 +++++
 5 files changed, 15 insertions(+), 10 deletions(-)

diff --git a/openfpga/src/base/openfpga_link_arch.cpp b/openfpga/src/base/openfpga_link_arch.cpp
index ac403592c..fcaa1f128 100644
--- a/openfpga/src/base/openfpga_link_arch.cpp
+++ b/openfpga/src/base/openfpga_link_arch.cpp
@@ -15,7 +15,6 @@
 #include "annotate_rr_graph.h"
 #include "mux_library_builder.h"
 #include "build_tile_direct.h"
-#include "build_physical_lb_rr_graph.h"
 #include "openfpga_link_arch.h"
 
 /* Include global variables of VPR */
@@ -112,11 +111,6 @@ void link_arch(OpenfpgaContext& openfpga_ctx,
   /* Build tile direct annotation */
   openfpga_ctx.mutable_tile_direct() =  build_device_tile_direct(g_vpr_ctx.device(),
                                                                  openfpga_ctx.arch().arch_direct);
-
-
-  build_physical_lb_rr_graphs(g_vpr_ctx.device(),
-                              openfpga_ctx.mutable_vpr_device_annotation(),
-                              cmd_context.option_enable(cmd, opt_verbose));
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_repack.cpp b/openfpga/src/base/openfpga_repack.cpp
index c58e2b4ff..f605233da 100644
--- a/openfpga/src/base/openfpga_repack.cpp
+++ b/openfpga/src/base/openfpga_repack.cpp
@@ -24,7 +24,7 @@ void repack(OpenfpgaContext& openfpga_ctx,
   CommandOptionId opt_verbose = cmd.option("verbose");
 
   pack_physical_pbs(g_vpr_ctx.device(),
-                    openfpga_ctx.vpr_device_annotation(),
+                    openfpga_ctx.mutable_vpr_device_annotation(),
                     openfpga_ctx.mutable_vpr_clustering_annotation(),
                     openfpga_ctx.vpr_routing_annotation(),
                     cmd_context.option_enable(cmd, opt_verbose));
diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp
index 690dbaa23..ffb1ac631 100644
--- a/openfpga/src/repack/repack.cpp
+++ b/openfpga/src/repack/repack.cpp
@@ -7,6 +7,7 @@
 #include "vtr_assert.h"
 #include "vtr_time.h"
 
+#include "build_physical_lb_rr_graph.h"
 #include "repack.h"
 
 /* begin namespace openfpga */
@@ -16,17 +17,22 @@ namespace openfpga {
  * Top-level function to pack physical pb_graph 
  * This function will do :
  *  - create physical lb_rr_graph for each pb_graph considering physical modes only
- *    the lb_rr_graph willbe added to device annotation
+ *    the lb_rr_graph will be added to device annotation
  *  - annotate nets to be routed for each clustered block from operating modes of pb_graph 
  *    to physical modes of pb_graph
  *  - rerun the routing for each clustered block
  *  - store the packing results to clustering annotation
  ***************************************************************************************/
 void pack_physical_pbs(const DeviceContext& device_ctx,
-                       const VprDeviceAnnotation& device_annotation,
+                       VprDeviceAnnotation& device_annotation,
                        VprClusteringAnnotation& clustering_annotation,
                        const VprRoutingAnnotation& routing_annotation,
                        const bool& verbose) {
+
+  build_physical_lb_rr_graphs(device_ctx,
+                              device_annotation,
+                              verbose);
+
 }
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/repack/repack.h b/openfpga/src/repack/repack.h
index 2f8acd241..733a7d1ac 100644
--- a/openfpga/src/repack/repack.h
+++ b/openfpga/src/repack/repack.h
@@ -17,7 +17,7 @@
 namespace openfpga {
 
 void pack_physical_pbs(const DeviceContext& device_ctx,
-                       const VprDeviceAnnotation& device_annotation,
+                       VprDeviceAnnotation& device_annotation,
                        VprClusteringAnnotation& clustering_annotation,
                        const VprRoutingAnnotation& routing_annotation,
                        const bool& verbose);
diff --git a/openfpga/test_script/s298_k6_frac.openfpga b/openfpga/test_script/s298_k6_frac.openfpga
index 3c44fddae..f597475b9 100644
--- a/openfpga/test_script/s298_k6_frac.openfpga
+++ b/openfpga/test_script/s298_k6_frac.openfpga
@@ -21,6 +21,11 @@ lut_truth_table_fixup #--verbose
 #  - Enable pin duplication on grid modules 
 build_fabric --compress_routing --duplicate_grid_pin --verbose
 
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack --verbose
+
 # Write the Verilog netlit for FPGA fabric
 #  - Enable the use of explicit port mapping in Verilog netlist
 write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose

From 3e07d7d5e0b49f12740804fd1e73195a76653b5d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 20 Feb 2020 20:26:20 -0700
Subject: [PATCH 188/645] finish net addition to LbRouter. Found a bug in pb
 pin fix-up. Need to consider clustered I/O block z offset

---
 openfpga/src/base/openfpga_pb_pin_fixup.cpp |   2 +-
 openfpga/src/base/openfpga_repack.cpp       |   3 +-
 openfpga/src/fabric/build_grid_modules.cpp  |   2 +-
 openfpga/src/repack/lb_router.cpp           |   2 -
 openfpga/src/repack/lb_router.h             |   2 +-
 openfpga/src/repack/lb_router_utils.cpp     |  40 +++
 openfpga/src/repack/lb_router_utils.h       |  26 ++
 openfpga/src/repack/lb_rr_graph.cpp         |   4 +
 openfpga/src/repack/lb_rr_graph.h           |   2 +
 openfpga/src/repack/repack.cpp              | 286 +++++++++++++++++++-
 openfpga/src/repack/repack.h                |   3 +-
 openfpga/src/utils/pb_type_utils.cpp        |  14 +-
 openfpga/test_script/s298_k6_frac.openfpga  |   6 +-
 13 files changed, 378 insertions(+), 14 deletions(-)
 create mode 100644 openfpga/src/repack/lb_router_utils.cpp
 create mode 100644 openfpga/src/repack/lb_router_utils.h

diff --git a/openfpga/src/base/openfpga_pb_pin_fixup.cpp b/openfpga/src/base/openfpga_pb_pin_fixup.cpp
index 1c0beee27..54850c7c8 100644
--- a/openfpga/src/base/openfpga_pb_pin_fixup.cpp
+++ b/openfpga/src/base/openfpga_pb_pin_fixup.cpp
@@ -122,7 +122,7 @@ void update_cluster_pin_with_post_routing_results(const DeviceContext& device_ct
 
     /* If matched, we finish here */
     if (routing_net_id == cluster_net_id) {
-       continue;
+      continue;
     }
     /* Add to net modification */
     vpr_clustering_annotation.rename_net(blk_id, j, routing_net_id);
diff --git a/openfpga/src/base/openfpga_repack.cpp b/openfpga/src/base/openfpga_repack.cpp
index f605233da..f49321252 100644
--- a/openfpga/src/base/openfpga_repack.cpp
+++ b/openfpga/src/base/openfpga_repack.cpp
@@ -24,9 +24,10 @@ void repack(OpenfpgaContext& openfpga_ctx,
   CommandOptionId opt_verbose = cmd.option("verbose");
 
   pack_physical_pbs(g_vpr_ctx.device(),
+                    g_vpr_ctx.atom(),
+                    g_vpr_ctx.clustering(),
                     openfpga_ctx.mutable_vpr_device_annotation(),
                     openfpga_ctx.mutable_vpr_clustering_annotation(),
-                    openfpga_ctx.vpr_routing_annotation(),
                     cmd_context.option_enable(cmd, opt_verbose));
 } 
 
diff --git a/openfpga/src/fabric/build_grid_modules.cpp b/openfpga/src/fabric/build_grid_modules.cpp
index fcfbfa0aa..39ca8e266 100644
--- a/openfpga/src/fabric/build_grid_modules.cpp
+++ b/openfpga/src/fabric/build_grid_modules.cpp
@@ -1053,7 +1053,7 @@ void build_physical_tile_module(ModuleManager& module_manager,
                                       sram_orgz_type, circuit_lib.design_tech_type(sram_model));
   }
 
-  VTR_LOG("Done\n");
+  VTR_LOGV(verbose, "Done\n");
 }
 
 /*****************************************************************************
diff --git a/openfpga/src/repack/lb_router.cpp b/openfpga/src/repack/lb_router.cpp
index 1244143a0..9c83be476 100644
--- a/openfpga/src/repack/lb_router.cpp
+++ b/openfpga/src/repack/lb_router.cpp
@@ -1,8 +1,6 @@
 /******************************************************************************
  * Memember functions for data structure LbRouter
  ******************************************************************************/
-#include <queue>
-
 #include "vtr_assert.h"
 #include "vtr_log.h"
 
diff --git a/openfpga/src/repack/lb_router.h b/openfpga/src/repack/lb_router.h
index 3a1f299af..0a8bb95fd 100644
--- a/openfpga/src/repack/lb_router.h
+++ b/openfpga/src/repack/lb_router.h
@@ -7,6 +7,7 @@
 #include <map>
 #include <unordered_map>
 #include <vector>
+#include <queue>
 
 #include "vtr_vector.h"
 #include "vtr_strong_id.h"
@@ -182,7 +183,6 @@ class LbRouter {
     NetId create_net_to_route(const LbRRNodeId& source, const std::vector<LbRRNodeId>& terminals);
     void add_net_atom_net_id(const NetId& net, const AtomNetId& atom_net);
     void add_net_atom_pins(const NetId& net, const AtomPinId& src_pin, const std::vector<AtomPinId>& terminal_pins);
-    void set_net_fix_terminal(const NetId& net, const LbRRNodeId& terminal, const bool& fix);
 
     /**
      * Perform routing algorithm on a given logical tile routing resource graph
diff --git a/openfpga/src/repack/lb_router_utils.cpp b/openfpga/src/repack/lb_router_utils.cpp
new file mode 100644
index 000000000..961b61ff7
--- /dev/null
+++ b/openfpga/src/repack/lb_router_utils.cpp
@@ -0,0 +1,40 @@
+/***************************************************************************************
+ * This file includes functions that are used to redo packing for physical pbs
+ ***************************************************************************************/
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+
+#include "lb_router_utils.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/***************************************************************************************
+ * Add a net to route to a logical block router
+ * This function will automatically find the source and sink atom pins
+ * based on the given atom net
+ ***************************************************************************************/
+LbRouter::NetId add_lb_router_net_to_route(LbRouter& lb_router,
+                                           const LbRRNodeId& source_node,
+                                           const std::vector<LbRRNodeId>& sink_nodes,
+                                           const AtomNetlist& atom_nlist,
+                                           const AtomNetId& atom_net_id) {
+  VTR_ASSERT(0 < sink_nodes.size());
+
+  LbRouter::NetId lb_net = lb_router.create_net_to_route(source_node, sink_nodes);
+
+  VTR_ASSERT(AtomNetId::INVALID() != atom_net_id);
+  lb_router.add_net_atom_net_id(lb_net, atom_net_id);
+  std::vector<AtomPinId> terminal_pins;
+  for (const AtomPinId& atom_pin : atom_nlist.net_sinks(atom_net_id)) {
+    VTR_ASSERT(AtomPinId::INVALID() != atom_pin);
+    terminal_pins.push_back(atom_pin);
+  }
+  VTR_ASSERT(AtomPinId::INVALID() != atom_nlist.net_driver(atom_net_id));
+  lb_router.add_net_atom_pins(lb_net, atom_nlist.net_driver(atom_net_id), terminal_pins);
+
+  return lb_net;
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/repack/lb_router_utils.h b/openfpga/src/repack/lb_router_utils.h
new file mode 100644
index 000000000..bcfc6004b
--- /dev/null
+++ b/openfpga/src/repack/lb_router_utils.h
@@ -0,0 +1,26 @@
+#ifndef LB_ROUTER_UTILS_H
+#define LB_ROUTER_UTILS_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "atom_netlist.h"
+#include "lb_rr_graph.h"
+#include "lb_router.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+LbRouter::NetId add_lb_router_net_to_route(LbRouter& lb_router,
+                                           const LbRRNodeId& source_node,
+                                           const std::vector<LbRRNodeId>& sink_nodes,
+                                           const AtomNetlist& atom_nlist,
+                                           const AtomNetId& atom_net_id);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/repack/lb_rr_graph.cpp b/openfpga/src/repack/lb_rr_graph.cpp
index db43543da..137b4a105 100644
--- a/openfpga/src/repack/lb_rr_graph.cpp
+++ b/openfpga/src/repack/lb_rr_graph.cpp
@@ -291,6 +291,10 @@ bool LbRRGraph::validate() const {
   return (0 == num_err);
 }
 
+bool LbRRGraph::empty() const {
+  return (0 == nodes().size()) && (0 == edges().size());
+}
+
 /******************************************************************************
  * Private validators/invalidators
  ******************************************************************************/
diff --git a/openfpga/src/repack/lb_rr_graph.h b/openfpga/src/repack/lb_rr_graph.h
index 3aca85934..b4d4a093a 100644
--- a/openfpga/src/repack/lb_rr_graph.h
+++ b/openfpga/src/repack/lb_rr_graph.h
@@ -275,6 +275,8 @@ class LbRRGraph {
 
     bool validate() const;
 
+    bool empty() const;
+
   private: /* Private Validators */
     bool validate_node_sizes() const;
     bool validate_edge_sizes() const;
diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp
index ffb1ac631..f69d23e32 100644
--- a/openfpga/src/repack/repack.cpp
+++ b/openfpga/src/repack/repack.cpp
@@ -7,12 +7,290 @@
 #include "vtr_assert.h"
 #include "vtr_time.h"
 
+/* Headers from vpr library */
+#include "vpr_utils.h"
+
+#include "pb_type_utils.h"
 #include "build_physical_lb_rr_graph.h"
+#include "lb_router.h"
+#include "lb_router_utils.h"
 #include "repack.h"
 
 /* begin namespace openfpga */
 namespace openfpga {
 
+/***************************************************************************************
+ * Try find the pin id which is mapped to a given atom net id in the context of pb route
+ ***************************************************************************************/
+static 
+std::vector<t_pb_graph_pin*> find_routed_pb_graph_pins_atom_net(const t_pb* pb,
+                                                                const AtomNetId& atom_net_id,
+                                                                t_pb_graph_pin** pb_graph_pin_lookup_from_index) {
+  std::vector<t_pb_graph_pin*> sink_pb_pins;  
+
+  /* Find the sink nodes from top-level node */
+  for (int pin = 0; pin < pb->pb_graph_node->total_pb_pins; ++pin) {
+    /* Bypass unused pins */
+    if ((0 == pb->pb_route.count(pin)) || (AtomNetId::INVALID() == pb->pb_route[pin].atom_net_id)) {
+      continue;
+    }
+    /* Get the driver pb pin id, it must be valid */
+    if (atom_net_id != pb->pb_route[pin].atom_net_id) {
+      continue;
+    }
+    /* Check each sink nodes, if pin belongs to an input of a primitive pb_graph_node, it is what we want */
+    for (const int& sink_pb_pin_id : pb->pb_route[pin].sink_pb_pin_ids) {
+      t_pb_graph_pin* sink_pb_pin = pb_graph_pin_lookup_from_index[sink_pb_pin_id];
+      VTR_ASSERT(nullptr != sink_pb_pin);
+      /* We care only
+       * - input pins of primitive nodes
+       * - output pins of top node 
+       */ 
+      if ( (true == is_primitive_pb_type(sink_pb_pin->parent_node->pb_type))
+        && (IN_PORT == sink_pb_pin->port->type)) {
+        sink_pb_pins.push_back(sink_pb_pin);
+      }
+
+      if ( (true == sink_pb_pin->parent_node->is_root())
+        && (OUT_PORT == sink_pb_pin->port->type)) {
+        sink_pb_pins.push_back(sink_pb_pin);
+      }
+    }
+  }
+
+  return sink_pb_pins;
+}
+
+/***************************************************************************************
+ * Find the corresponding nodes in a logical block routing resource graph
+ * with a given list of sink pb_graph pins
+ * Note that these sink pins belong to operating pb_graph_node,
+ * we will find the associated physical pb_graph_node as well as physical pins
+ * and then spot the nodes in lb_rr_graph
+ ***************************************************************************************/
+static 
+std::vector<LbRRNodeId> find_lb_net_physical_sink_lb_rr_nodes(const LbRRGraph& lb_rr_graph,
+                                                              const std::vector<t_pb_graph_pin*>& sink_pins,
+                                                              const VprDeviceAnnotation& device_annotation) {
+  std::vector<LbRRNodeId> sink_nodes;
+
+  for (t_pb_graph_pin* sink_pin : sink_pins) {
+    /* Find the physical pin */
+    t_pb_graph_pin* physical_sink_pin = nullptr;
+    if (true == sink_pin->parent_node->is_root()) {
+      physical_sink_pin = sink_pin;
+    } else {
+      physical_sink_pin = device_annotation.physical_pb_graph_pin(sink_pin);
+    } 
+
+    /* if this is the root node, the physical pin is its self */
+    if (nullptr == physical_sink_pin) {
+      VTR_LOG("Fail to find a physical pin for operating pin '%s'!\n",
+              sink_pin->to_string().c_str());
+    }
+    VTR_ASSERT(nullptr != physical_sink_pin);
+    LbRRNodeId sink_lb_rr_node = lb_rr_graph.find_node(LB_INTERMEDIATE, physical_sink_pin);
+    if (true != lb_rr_graph.valid_node_id(sink_lb_rr_node)) {
+      VTR_LOG("Try to find the lb_rr_node for pb_graph_pin '%s'\n",
+              physical_sink_pin->to_string().c_str());
+    }
+    VTR_ASSERT(true == lb_rr_graph.valid_node_id(sink_lb_rr_node));
+    sink_nodes.push_back(sink_lb_rr_node);
+  }
+
+  return sink_nodes;
+}
+
+/***************************************************************************************
+ * Create nets to be routed, including the source nodes and terminals
+ * And add them to the logical block router
+ ***************************************************************************************/
+static 
+void add_lb_router_nets(LbRouter& lb_router,
+                        t_logical_block_type_ptr lb_type,
+                        const LbRRGraph& lb_rr_graph,
+                        const AtomContext& atom_ctx,
+                        const VprDeviceAnnotation& device_annotation,
+                        const ClusteringContext& clustering_ctx,
+                        const VprClusteringAnnotation& clustering_annotation,
+                        const ClusterBlockId& block_id,
+                        const bool& verbose) {
+  size_t net_counter = 0;
+
+  /* Two spots to find source nodes for each nets
+   *  - nets that appear in the inputs of a clustered block
+   *    Note that these nets may be moved to another input of the same cluster block
+   *    we will locate the final pin and consider its corresponding routing resource node as source
+   *  - nets that appear in the outputs of a primitive pb_graph_node
+   *    Note that these primitive pb_graph node are operating pb_graph_node
+   *    while we are considering physical pb_graph node
+   *    Therefore, we will find the outputs of physical pb_graph_node corresponding to the operating one
+   *    and then consider the assoicated routing resource node as source
+   */
+  t_pb* pb = clustering_ctx.clb_nlist.block_pb(block_id);
+  VTR_ASSERT(true == pb->pb_graph_node->is_root());
+
+  /* Build the fast look-up between pb_pin_id and pb_graph_pin pointer */
+  t_pb_graph_pin** pb_graph_pin_lookup_from_index = alloc_and_load_pb_graph_pin_lookup_from_index(lb_type);
+
+  /* Find the source nodes for the nets mapped to inputs of a clustered block */
+  for (int j = 0; j < lb_type->pb_type->num_pins; j++) {
+    /* Find the net mapped to this pin in clustering results*/
+    ClusterNetId cluster_net_id = clustering_ctx.clb_nlist.block_net(block_id, j);
+    /* Get the actual net id because it may be renamed during routing */
+    if (true == clustering_annotation.is_net_renamed(block_id, j)) {
+      cluster_net_id = clustering_annotation.net(block_id, j);
+    }
+    /* Bypass unmapped pins */
+    if (ClusterNetId::INVALID() == cluster_net_id) {
+      continue;
+    }
+
+    /* Get the source pb_graph pin and find the rr_node in logical block routing resource graph */
+    const t_pb_graph_pin* source_pb_pin = get_pb_graph_node_pin_from_block_pin(block_id, j);
+    VTR_ASSERT(source_pb_pin->parent_node == pb->pb_graph_node);
+    /* Bypass output pins */
+    if (OUT_PORT == source_pb_pin->port->type) {
+      continue;
+    }
+
+    /* The outputs of pb_graph_node is INTERMEDIATE node in the routing resource graph,
+     * they are all connected to a common source node
+     */
+    LbRRNodeId source_lb_rr_node = lb_rr_graph.find_node(LB_INTERMEDIATE, source_pb_pin);
+    VTR_ASSERT(true == lb_rr_graph.valid_node_id(source_lb_rr_node));
+
+    AtomNetId atom_net_id = atom_ctx.lookup.atom_net(cluster_net_id);
+    VTR_ASSERT(AtomNetId::INVALID() != atom_net_id);
+
+    /* Find all the sink pins in the pb_route, we walk through the input pins and find the pin  */
+    std::vector<t_pb_graph_pin*> sink_pb_graph_pins = find_routed_pb_graph_pins_atom_net(pb, atom_net_id, pb_graph_pin_lookup_from_index);
+    std::vector<LbRRNodeId> sink_lb_rr_nodes = find_lb_net_physical_sink_lb_rr_nodes(lb_rr_graph, sink_pb_graph_pins, device_annotation);
+    VTR_ASSERT(sink_lb_rr_nodes.size() == sink_pb_graph_pins.size());
+
+    /* Add the net */
+    add_lb_router_net_to_route(lb_router,
+                               source_lb_rr_node, sink_lb_rr_nodes,
+                               atom_ctx.nlist, atom_net_id);
+    net_counter++;
+  }
+
+  /* Find the source nodes for the nets mapped to outputs of primitive pb_graph_node */
+  for (int pin = 0; pin < pb->pb_graph_node->total_pb_pins; ++pin) {
+    /* Bypass unused pins */
+    if ((0 == pb->pb_route.count(pin)) || (AtomNetId::INVALID() == pb->pb_route[pin].atom_net_id)) {
+      continue;
+    }
+    /* Get the driver pb pin id, it must be valid */
+    int source_pb_pin_id = pb->pb_route[pin].driver_pb_pin_id;
+    if (OPEN == source_pb_pin_id) {
+      continue;
+    }
+    VTR_ASSERT(OPEN != source_pb_pin_id && source_pb_pin_id < pb->pb_graph_node->total_pb_pins);
+    /* Find the corresponding pb_graph_pin and its physical pb_graph_pin */
+    t_pb_graph_pin* source_pb_pin = pb_graph_pin_lookup_from_index[source_pb_pin_id];
+    /* Skip the pin from top-level pb_graph_node, they have been handled already */ 
+    if (source_pb_pin->parent_node == pb->pb_graph_node) {
+      continue;
+    }
+
+    /* The pin must be an output of a primitive pb_graph_node */
+    if (OUT_PORT != source_pb_pin->port->type) {
+      continue;
+    }
+    if (true != is_primitive_pb_type(source_pb_pin->parent_node->pb_type)) {
+      continue;
+    }
+
+    /* The outputs of pb_graph_node is SOURCE node in the routing resource graph */
+    t_pb_graph_pin* physical_source_pb_pin = device_annotation.physical_pb_graph_pin(source_pb_pin);
+    LbRRNodeId source_lb_rr_node = lb_rr_graph.find_node(LB_SOURCE, physical_source_pb_pin);
+    VTR_ASSERT(true == lb_rr_graph.valid_node_id(source_lb_rr_node));
+
+    AtomNetId atom_net_id = pb->pb_route[pin].atom_net_id;
+    VTR_ASSERT(AtomNetId::INVALID() != atom_net_id);
+
+    /* Find all the sink pins in the pb_route */
+    std::vector<t_pb_graph_pin*> sink_pb_graph_pins = find_routed_pb_graph_pins_atom_net(pb, atom_net_id, pb_graph_pin_lookup_from_index);
+    std::vector<LbRRNodeId> sink_lb_rr_nodes = find_lb_net_physical_sink_lb_rr_nodes(lb_rr_graph, sink_pb_graph_pins, device_annotation);
+    VTR_ASSERT(sink_lb_rr_nodes.size() == sink_pb_graph_pins.size());
+
+    /* Add the net */
+    add_lb_router_net_to_route(lb_router,
+                               source_lb_rr_node, sink_lb_rr_nodes,
+                               atom_ctx.nlist, atom_net_id);
+    net_counter++;
+  } 
+
+  /* Free */
+  free_pb_graph_pin_lookup_from_index(pb_graph_pin_lookup_from_index);
+
+  VTR_LOGV(verbose,
+           "Added %lu nets to be routed.\n",
+           net_counter);
+}
+
+/***************************************************************************************
+ * Repack a clustered block in the physical mode
+ * This function will do 
+ * - Find the lb_rr_graph that is affiliated to the clustered block 
+ *   and initilize the logcial tile router 
+ * - Create nets to be routed, including the source nodes and terminals
+ *   This should consider the net remapping in the clustering_annotation 
+ * - Run the router to finish the repacking
+ * - Output routing results to data structure PhysicalPb and store it in clustering annotation
+ ***************************************************************************************/
+static 
+void repack_cluster(const DeviceContext& device_ctx,
+                    const AtomContext& atom_ctx,
+                    const ClusteringContext& clustering_ctx,
+                    const VprDeviceAnnotation& device_annotation,
+                    VprClusteringAnnotation& clustering_annotation,
+                    const ClusterBlockId& block_id,
+                    const bool& verbose) {
+  /* Get the pb graph that current clustered block is mapped to */
+  t_logical_block_type_ptr lb_type = clustering_ctx.clb_nlist.block_type(block_id);
+  t_pb_graph_node* pb_graph_head = lb_type->pb_graph_head;
+  VTR_ASSERT(nullptr != pb_graph_head);
+
+  /* We should get a non-empty graph */
+  const LbRRGraph& lb_rr_graph = device_annotation.physical_lb_rr_graph(pb_graph_head);
+  VTR_ASSERT(!lb_rr_graph.empty());
+
+  VTR_LOG("Repack clustered block '%s'...",
+          clustering_ctx.clb_nlist.block_name(block_id).c_str());
+  VTR_LOGV(verbose, "\n");
+
+  /* Initialize the router */
+  LbRouter lb_router(lb_rr_graph, lb_type);
+
+  /* Add nets to be routed with source and terminals */
+  add_lb_router_nets(lb_router, lb_type, lb_rr_graph, atom_ctx, device_annotation,
+                     clustering_ctx, const_cast<const VprClusteringAnnotation&>(clustering_annotation),
+                     block_id, verbose);
+
+  VTR_LOG("Done\n");
+}
+
+/***************************************************************************************
+ * Repack each clustered blocks in the clustering context
+ ***************************************************************************************/
+static 
+void repack_clusters(const DeviceContext& device_ctx,
+                     const AtomContext& atom_ctx,
+                     const ClusteringContext& clustering_ctx,
+                     const VprDeviceAnnotation& device_annotation,
+                     VprClusteringAnnotation& clustering_annotation,
+                     const bool& verbose) {
+  vtr::ScopedStartFinishTimer timer("Repack clustered blocks to physical implementation of logical tile");
+
+  for (auto blk_id : clustering_ctx.clb_nlist.blocks()) {
+    repack_cluster(device_ctx, atom_ctx, clustering_ctx, 
+                   device_annotation, clustering_annotation, 
+                   blk_id, verbose);
+  }
+}
+
 /***************************************************************************************
  * Top-level function to pack physical pb_graph 
  * This function will do :
@@ -24,15 +302,21 @@ namespace openfpga {
  *  - store the packing results to clustering annotation
  ***************************************************************************************/
 void pack_physical_pbs(const DeviceContext& device_ctx,
+                       const AtomContext& atom_ctx,
+                       const ClusteringContext& clustering_ctx,
                        VprDeviceAnnotation& device_annotation,
                        VprClusteringAnnotation& clustering_annotation,
-                       const VprRoutingAnnotation& routing_annotation,
                        const bool& verbose) {
 
+  /* build the routing resource graph for each logical tile */
   build_physical_lb_rr_graphs(device_ctx,
                               device_annotation,
                               verbose);
 
+  /* Call the LbRouter to re-pack each clustered block to physical implementation */ 
+  repack_clusters(device_ctx, atom_ctx, clustering_ctx, 
+                  const_cast<const VprDeviceAnnotation&>(device_annotation), clustering_annotation, 
+                  verbose);
 }
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/repack/repack.h b/openfpga/src/repack/repack.h
index 733a7d1ac..8121a58bd 100644
--- a/openfpga/src/repack/repack.h
+++ b/openfpga/src/repack/repack.h
@@ -17,9 +17,10 @@
 namespace openfpga {
 
 void pack_physical_pbs(const DeviceContext& device_ctx,
+                       const AtomContext& atom_ctx,
+                       const ClusteringContext& clustering_ctx,
                        VprDeviceAnnotation& device_annotation,
                        VprClusteringAnnotation& clustering_annotation,
-                       const VprRoutingAnnotation& routing_annotation,
                        const bool& verbose);
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/utils/pb_type_utils.cpp b/openfpga/src/utils/pb_type_utils.cpp
index 9f52c01da..13d7ccadb 100644
--- a/openfpga/src/utils/pb_type_utils.cpp
+++ b/openfpga/src/utils/pb_type_utils.cpp
@@ -25,9 +25,17 @@ namespace openfpga {
  ************************************************************************/
 bool is_primitive_pb_type(t_pb_type* pb_type) {
   if (LUT_CLASS == pb_type->class_type) {
-    /* The first mode of LUT is wire, the second is the regular LUT */
-    VTR_ASSERT(std::string("wire") == std::string(pb_type->modes[0].name)); 
-    VTR_ASSERT(std::string(pb_type->name) == std::string(pb_type->modes[1].name)); 
+    /* The only primitive LUT we recognize is the one which have 
+     * a first mode of LUT is wire, the second is the regular LUT
+     * VPR contructed two modes under a regular LUT, and these children
+     * are labelled as LUT_CLASS as well. OpenFPGA does not consider
+     * them as primitive as they are for CAD usage only
+     */
+    if (0 == pb_type->num_modes) {
+      return false;
+    }
+    VTR_ASSERT( (std::string("wire") == std::string(pb_type->modes[0].name))
+             && (std::string(pb_type->name) == std::string(pb_type->modes[1].name)));
     return true;
   }
   return 0 == pb_type->num_modes;
diff --git a/openfpga/test_script/s298_k6_frac.openfpga b/openfpga/test_script/s298_k6_frac.openfpga
index f597475b9..91c5fa551 100644
--- a/openfpga/test_script/s298_k6_frac.openfpga
+++ b/openfpga/test_script/s298_k6_frac.openfpga
@@ -5,13 +5,13 @@ vpr ./test_vpr_arch/k6_frac_N10_40nm.xml ./test_blif/s298.blif --write_rr_graph
 read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
 
 # Annotate the OpenFPGA architecture to VPR data base
-link_openfpga_arch --verbose
+link_openfpga_arch #--verbose
 
 # Check and correct any naming conflicts in the BLIF netlist
 check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
 
 # Apply fix-up to clustering nets based on routing results
-pb_pin_fixup #--verbose
+pb_pin_fixup --verbose
 
 # Apply fix-up to Look-Up Table truth tables based on packing results
 lut_truth_table_fixup #--verbose
@@ -19,7 +19,7 @@ lut_truth_table_fixup #--verbose
 # Build the module graph 
 #  - Enabled compression on routing architecture modules
 #  - Enable pin duplication on grid modules 
-build_fabric --compress_routing --duplicate_grid_pin --verbose
+build_fabric --compress_routing --duplicate_grid_pin #--verbose
 
 # Repack the netlist to physical pbs
 # This must be done before bitstream generator and testbench generation

From 4abaef14b5abdae9959f0febdce217178d044527 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 20 Feb 2020 20:50:59 -0700
Subject: [PATCH 189/645] bug fixed in pb_pin fix-up. This is due to A CRITICAL
 BUG IN PHYSICAL_TILE PIN MAPPING!!!

---
 openfpga/src/base/openfpga_pb_pin_fixup.cpp | 17 +++++++++++++----
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/openfpga/src/base/openfpga_pb_pin_fixup.cpp b/openfpga/src/base/openfpga_pb_pin_fixup.cpp
index 54850c7c8..901dbaa5f 100644
--- a/openfpga/src/base/openfpga_pb_pin_fixup.cpp
+++ b/openfpga/src/base/openfpga_pb_pin_fixup.cpp
@@ -60,14 +60,19 @@ void update_cluster_pin_with_post_routing_results(const DeviceContext& device_ct
                                                   const vtr::Point<size_t>& grid_coord,
                                                   const ClusterBlockId& blk_id,
                                                   const e_side& border_side,
+                                                  const size_t& z,
                                                   const bool& verbose) {
   /* Handle each pin */
   auto logical_block = clustering_ctx.clb_nlist.block_type(blk_id);
   auto physical_tile = pick_best_physical_type(logical_block);
 
   for (int j = 0; j < logical_block->pb_type->num_pins; j++) {
-    /* Get the ptc num for the pin in rr_graph */
-    int physical_pin = get_physical_pin(physical_tile, logical_block, j);
+    /* Get the ptc num for the pin in rr_graph, we need t consider the z offset here
+     * z offset is the location in the multiple-logic-tile tile
+     * Get physical pin does not consider THIS!!!!
+     */
+    int physical_pin = z * logical_block->pb_type->num_pins 
+                     + get_physical_pin(physical_tile, logical_block, j);
     auto pin_class = physical_tile->pin_class[physical_pin];
     auto class_inf = physical_tile->class_inf[pin_class];
 
@@ -179,8 +184,10 @@ void update_pb_pin_with_post_routing_results(const DeviceContext& device_ctx,
         /* We know the entrance to grid info and mapping results, do the fix-up for this block */
         vtr::Point<size_t> grid_coord(x, y);
         update_cluster_pin_with_post_routing_results(device_ctx, clustering_ctx, 
-                                                     vpr_routing_annotation, vpr_clustering_annotation,
+                                                     vpr_routing_annotation,
+                                                     vpr_clustering_annotation,
                                                      grid_coord, cluster_blk_id, NUM_SIDES,
+                                                     placement_ctx.block_locs[cluster_blk_id].loc.z,
                                                      verbose);
       } 
     }
@@ -227,8 +234,10 @@ void update_pb_pin_with_post_routing_results(const DeviceContext& device_ctx,
         }
         /* Update on I/O grid */
         update_cluster_pin_with_post_routing_results(device_ctx, clustering_ctx, 
-                                                     vpr_routing_annotation, vpr_clustering_annotation,
+                                                     vpr_routing_annotation,
+                                                     vpr_clustering_annotation,
                                                      io_coord, cluster_blk_id, io_side,
+                                                     placement_ctx.block_locs[cluster_blk_id].loc.z,
                                                      verbose);
       }
     }

From 0b0e00b5f426f2ce23bb28b8523b4a8531ee7ee4 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 20 Feb 2020 21:56:15 -0700
Subject: [PATCH 190/645] debugging the LbRouter

---
 openfpga/src/repack/lb_router.cpp           | 37 ++++++++++++++++++-
 openfpga/src/repack/lb_router_utils.cpp     | 41 ++++++++++++++++++---
 openfpga/src/repack/lb_router_utils.h       |  3 +-
 openfpga/src/repack/repack.cpp              | 18 +++++++--
 openfpga/test_vpr_arch/k6_frac_N10_40nm.xml |  3 +-
 5 files changed, 88 insertions(+), 14 deletions(-)

diff --git a/openfpga/src/repack/lb_router.cpp b/openfpga/src/repack/lb_router.cpp
index 9c83be476..9ab0058ab 100644
--- a/openfpga/src/repack/lb_router.cpp
+++ b/openfpga/src/repack/lb_router.cpp
@@ -8,6 +8,7 @@
 #include "pb_type_graph.h"
 #include "vpr_error.h"
 
+#include "pb_type_utils.h"
 #include "lb_rr_graph_utils.h"
 #include "lb_router.h"
 
@@ -148,6 +149,7 @@ LbRouter::NetId LbRouter::create_net_to_route(const LbRRNodeId& source, const st
   net_terminals.insert(net_terminals.begin(), source);
 
   lb_net_terminals_.push_back(net_terminals);
+  lb_net_rt_trees_.push_back(nullptr);
 
   return net;
 }
@@ -260,8 +262,22 @@ bool LbRouter::try_route(const LbRRGraph& lb_rr_graph,
       is_routed_ = is_route_success(lb_rr_graph);
     } else {
       --inet;
-      VTR_LOGV(verbosity < 3, "Net '%s' is impossible to route within proposed %s cluster\n",
+      VTR_LOGV(verbosity < 3,
+               "Net '%s' is impossible to route within proposed %s cluster\n",
                atom_nlist.net_name(lb_net_atom_net_ids_[NetId(inet)]).c_str(), lb_type_->name);
+      VTR_LOGV(verbosity < 3,
+               "\tNet source pin '%s'\n",
+               lb_rr_graph.node_pb_graph_pin(lb_net_terminals_[NetId(inet)][0])->to_string().c_str()); 
+      VTR_LOGV(verbosity < 3,
+               "\tNet sink pins:\n");
+      for (size_t isink = 1; isink < lb_net_terminals_[NetId(inet)].size(); ++isink) {
+        VTR_LOGV(verbosity < 3,
+                 "\t\t%s\n",
+                 lb_rr_graph.node_pb_graph_pin(lb_net_terminals_[NetId(inet)][isink])->to_string().c_str()); 
+      }
+      VTR_LOGV(verbosity < 3,
+               "Please check your architecture XML to see if it is routable\n");
+      
       is_routed_ = false;
     }
     pres_con_fac_ *= params_.pres_fac_mult;
@@ -557,7 +573,12 @@ void LbRouter::expand_edges(const LbRRGraph& lb_rr_graph,
     t_mode* next_mode = routing_status_[enode.node_index].mode;
     /* Assume first mode if a mode hasn't been forced. */
     if (nullptr == next_mode) {
-      next_mode = &(lb_rr_graph.node_pb_graph_pin(enode.node_index)->parent_node->pb_type->modes[0]);
+      /* For primitive node, we give nullptr as default */
+      if (true == is_primitive_pb_type(lb_rr_graph.node_pb_graph_pin(enode.node_index)->parent_node->pb_type)) {
+        next_mode = nullptr;
+      } else {
+        next_mode = &(lb_rr_graph.node_pb_graph_pin(enode.node_index)->parent_node->pb_type->modes[0]);
+      }
     }
     if (lb_rr_graph.node_out_edges(enode.node_index, next_mode).size() > 1) {
       fanout_factor = 0.85 + (0.25 / net_fanout);
@@ -714,21 +735,33 @@ bool LbRouter::check_net(const LbRRGraph& lb_rr_graph,
     return false;
   }
   if (lb_net_atom_pins_[net].size() != lb_net_terminals_[net].size()) {
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Net '%lu' has unmatched atom pins and terminals.\n",
+                   size_t(net));
     return false;
   }
   /* We must have 1 source and >1 terminal */
   if (2 > lb_net_terminals_[net].size()) {
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Net '%lu' has only %lu terminal.\n",
+                   size_t(net), lb_net_terminals_[net].size());
     return false;
   } 
   /* Each node must be valid */
   for (const LbRRNodeId& node : lb_net_terminals_[net]) {
     if (false == lb_rr_graph.valid_node_id(node)) {
+      VTR_LOGF_ERROR(__FILE__, __LINE__,
+                     "Net '%lu' has invalid terminal node in lb_rr_graph.\n",
+                     size_t(net));
       return false;
     }
   }
   /* Each atom pin must be valid */
   for (const AtomPinId& pin : lb_net_atom_pins_[net]) {
     if (false == atom_nlist.valid_pin_id(pin)) {
+      VTR_LOGF_ERROR(__FILE__, __LINE__,
+                     "Net '%lu' has invalid atom pin.\n",
+                     size_t(net));
       return false;
     }
   }
diff --git a/openfpga/src/repack/lb_router_utils.cpp b/openfpga/src/repack/lb_router_utils.cpp
index 961b61ff7..221f5a640 100644
--- a/openfpga/src/repack/lb_router_utils.cpp
+++ b/openfpga/src/repack/lb_router_utils.cpp
@@ -16,9 +16,10 @@ namespace openfpga {
  * based on the given atom net
  ***************************************************************************************/
 LbRouter::NetId add_lb_router_net_to_route(LbRouter& lb_router,
+                                           const LbRRGraph& lb_rr_graph,
                                            const LbRRNodeId& source_node,
                                            const std::vector<LbRRNodeId>& sink_nodes,
-                                           const AtomNetlist& atom_nlist,
+                                           const AtomContext& atom_ctx,
                                            const AtomNetId& atom_net_id) {
   VTR_ASSERT(0 < sink_nodes.size());
 
@@ -26,13 +27,41 @@ LbRouter::NetId add_lb_router_net_to_route(LbRouter& lb_router,
 
   VTR_ASSERT(AtomNetId::INVALID() != atom_net_id);
   lb_router.add_net_atom_net_id(lb_net, atom_net_id);
+
   std::vector<AtomPinId> terminal_pins;
-  for (const AtomPinId& atom_pin : atom_nlist.net_sinks(atom_net_id)) {
-    VTR_ASSERT(AtomPinId::INVALID() != atom_pin);
-    terminal_pins.push_back(atom_pin);
+  AtomPinId atom_pin_outside_pb = AtomPinId::INVALID();
+
+  for (const LbRRNodeId& sink_node : sink_nodes) {
+    t_pb_graph_pin* sink_pb_pin = lb_rr_graph.node_pb_graph_pin(sink_node); 
+    bool atom_pin_inside_pb = false;
+    for (const AtomPinId& atom_pin : atom_ctx.nlist.net_sinks(atom_net_id)) {
+      VTR_ASSERT(AtomPinId::INVALID() != atom_pin);
+      if (sink_pb_pin == find_pb_graph_pin(atom_ctx.nlist, atom_ctx.lookup, atom_pin)) {
+        terminal_pins.push_back(atom_pin);
+        atom_pin_inside_pb = true;
+        break;
+      }
+      if (AtomPinId::INVALID() == atom_pin_outside_pb) {
+        atom_pin_outside_pb = atom_pin;
+      }
+    }
+    /* Add a atom pin which is not inside the pb */
+    if (false == atom_pin_inside_pb) {
+      VTR_ASSERT(AtomPinId::INVALID() != atom_pin_outside_pb);
+      terminal_pins.push_back(atom_pin_outside_pb);
+    }
   }
-  VTR_ASSERT(AtomPinId::INVALID() != atom_nlist.net_driver(atom_net_id));
-  lb_router.add_net_atom_pins(lb_net, atom_nlist.net_driver(atom_net_id), terminal_pins);
+  VTR_ASSERT(AtomPinId::INVALID() != atom_ctx.nlist.net_driver(atom_net_id));
+  if (sink_nodes.size() != terminal_pins.size()) {
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Net '%s' has %lu sink nodes while has %lu associated atom pins!\n",
+                   atom_ctx.nlist.net_name(atom_net_id).c_str(),
+                   sink_nodes.size(),
+                   terminal_pins.size());
+  }
+  VTR_ASSERT(sink_nodes.size() == terminal_pins.size());
+
+  lb_router.add_net_atom_pins(lb_net, atom_ctx.nlist.net_driver(atom_net_id), terminal_pins);
 
   return lb_net;
 }
diff --git a/openfpga/src/repack/lb_router_utils.h b/openfpga/src/repack/lb_router_utils.h
index bcfc6004b..6a92201eb 100644
--- a/openfpga/src/repack/lb_router_utils.h
+++ b/openfpga/src/repack/lb_router_utils.h
@@ -16,9 +16,10 @@
 namespace openfpga {
 
 LbRouter::NetId add_lb_router_net_to_route(LbRouter& lb_router,
+                                           const LbRRGraph& lb_rr_graph,
                                            const LbRRNodeId& source_node,
                                            const std::vector<LbRRNodeId>& sink_nodes,
-                                           const AtomNetlist& atom_nlist,
+                                           const AtomContext& atom_ctx,
                                            const AtomNetId& atom_net_id);
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp
index f69d23e32..eee2c9075 100644
--- a/openfpga/src/repack/repack.cpp
+++ b/openfpga/src/repack/repack.cpp
@@ -169,9 +169,9 @@ void add_lb_router_nets(LbRouter& lb_router,
     VTR_ASSERT(sink_lb_rr_nodes.size() == sink_pb_graph_pins.size());
 
     /* Add the net */
-    add_lb_router_net_to_route(lb_router,
+    add_lb_router_net_to_route(lb_router, lb_rr_graph,
                                source_lb_rr_node, sink_lb_rr_nodes,
-                               atom_ctx.nlist, atom_net_id);
+                               atom_ctx, atom_net_id);
     net_counter++;
   }
 
@@ -216,9 +216,9 @@ void add_lb_router_nets(LbRouter& lb_router,
     VTR_ASSERT(sink_lb_rr_nodes.size() == sink_pb_graph_pins.size());
 
     /* Add the net */
-    add_lb_router_net_to_route(lb_router,
+    add_lb_router_net_to_route(lb_router, lb_rr_graph,
                                source_lb_rr_node, sink_lb_rr_nodes,
-                               atom_ctx.nlist, atom_net_id);
+                               atom_ctx, atom_net_id);
     net_counter++;
   } 
 
@@ -269,6 +269,16 @@ void repack_cluster(const DeviceContext& device_ctx,
                      clustering_ctx, const_cast<const VprClusteringAnnotation&>(clustering_annotation),
                      block_id, verbose);
 
+  /* Run the router */
+  bool route_success = lb_router.try_route(lb_rr_graph, atom_ctx.nlist, verbose);
+
+  if (true == route_success) {
+    VTR_LOGV(verbose, "Reroute failed\n");
+    exit(1);
+  }
+  VTR_ASSERT(true == route_success);
+  VTR_LOGV(verbose, "Reroute succeed\n");
+
   VTR_LOG("Done\n");
 }
 
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml
index a090fd45b..018cf491f 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml
@@ -236,7 +236,8 @@
                 <output name="lut6_out" num_pins="1"/>
               </pb_type>
               <interconnect>
-                <direct name="direct1" input="frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
+                <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
+                <direct name="direct2" input="frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
                 <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
               </interconnect>
             </pb_type>

From 1b66e837bafe4cbd62866093e5cac6530b49e342 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 21 Feb 2020 11:29:00 -0700
Subject: [PATCH 191/645] bug fixing for lb router. Add physical mode to
 default node expanding settings

---
 openfpga/src/repack/lb_router.cpp             | 49 +++++++++++++++++--
 openfpga/src/repack/lb_router.h               | 12 +++++
 openfpga/src/repack/repack.cpp                |  5 ++
 .../k6_frac_N10_40nm_openfpga.xml             |  2 +-
 openfpga/test_vpr_arch/k6_frac_N10_40nm.xml   |  6 ++-
 5 files changed, 66 insertions(+), 8 deletions(-)

diff --git a/openfpga/src/repack/lb_router.cpp b/openfpga/src/repack/lb_router.cpp
index 9ab0058ab..277548e18 100644
--- a/openfpga/src/repack/lb_router.cpp
+++ b/openfpga/src/repack/lb_router.cpp
@@ -109,7 +109,7 @@ bool LbRouter::route_has_conflict(const LbRRGraph& lb_rr_graph, t_trace* rt) con
   t_mode* cur_mode = nullptr;
   for (unsigned int i = 0; i < rt->next_nodes.size(); i++) {
     std::vector<LbRREdgeId> edges = lb_rr_graph.find_edge(rt->current_node, rt->next_nodes[i].current_node);
-    VTR_ASSERT(0 == edges.size());
+    VTR_ASSERT(1 == edges.size());
     t_mode* new_mode = lb_rr_graph.edge_mode(edges[0]);
     if (cur_mode != nullptr && cur_mode != new_mode) {
       return true;
@@ -165,6 +165,34 @@ void LbRouter::add_net_atom_pins(const NetId& net, const AtomPinId& src_pin, con
   lb_net_atom_pins_[net].insert(lb_net_atom_pins_[net].begin(), src_pin);
 }
 
+void LbRouter::set_physical_pb_modes(const LbRRGraph& lb_rr_graph,
+                                     const VprDeviceAnnotation& device_annotation) {
+  /* Go through each node in the routing resource graph
+   * Find the physical mode of each pb_graph_pin that is binded to the node
+   * For input pins, the physical mode is a mode of its parent pb_type
+   * For output pins, the physical mode is a mode of the parent pb_type of its parent
+   */
+  for (const LbRRNodeId& node : lb_rr_graph.nodes()) {
+    t_pb_graph_pin* pb_pin = lb_rr_graph.node_pb_graph_pin(node);
+    if (nullptr == pb_pin) {
+      routing_status_[node].mode = nullptr;
+    } else {
+      if (IN_PORT == pb_pin->port->type) {
+        routing_status_[node].mode = device_annotation.physical_mode(pb_pin->parent_node->pb_type);
+      } else {
+        VTR_ASSERT(OUT_PORT == pb_pin->port->type);
+        /* For top-level pb_graph node, the physical mode is nullptr */
+        if (true == pb_pin->parent_node->is_root()) {
+          routing_status_[node].mode = nullptr;
+        } else { 
+          routing_status_[node].mode = device_annotation.physical_mode(pb_pin->parent_node->parent_pb_graph_node->pb_type);
+          /* TODO: need to think about how to handle INOUT ports !!! */
+        }
+      }
+    }
+  }
+}
+
 bool LbRouter::try_route(const LbRRGraph& lb_rr_graph,
                          const AtomNetlist& atom_nlist,
                          const int& verbosity) {
@@ -263,8 +291,10 @@ bool LbRouter::try_route(const LbRRGraph& lb_rr_graph,
     } else {
       --inet;
       VTR_LOGV(verbosity < 3,
-               "Net '%s' is impossible to route within proposed %s cluster\n",
-               atom_nlist.net_name(lb_net_atom_net_ids_[NetId(inet)]).c_str(), lb_type_->name);
+               "Net %lu '%s' is impossible to route within proposed %s cluster\n",
+               inet,
+               atom_nlist.net_name(lb_net_atom_net_ids_[NetId(inet)]).c_str(),
+               lb_type_->name);
       VTR_LOGV(verbosity < 3,
                "\tNet source pin '%s'\n",
                lb_rr_graph.node_pb_graph_pin(lb_net_terminals_[NetId(inet)][0])->to_string().c_str()); 
@@ -573,8 +603,11 @@ void LbRouter::expand_edges(const LbRRGraph& lb_rr_graph,
     t_mode* next_mode = routing_status_[enode.node_index].mode;
     /* Assume first mode if a mode hasn't been forced. */
     if (nullptr == next_mode) {
+      /* If the node is mapped to a nullptr pb_graph_pin, this is a special SINK. Use nullptr mode */
+      if (nullptr == lb_rr_graph.node_pb_graph_pin(enode.node_index)) {
+        next_mode = nullptr;
+      } else if (true == is_primitive_pb_type(lb_rr_graph.node_pb_graph_pin(enode.node_index)->parent_node->pb_type)) {
       /* For primitive node, we give nullptr as default */
-      if (true == is_primitive_pb_type(lb_rr_graph.node_pb_graph_pin(enode.node_index)->parent_node->pb_type)) {
         next_mode = nullptr;
       } else {
         next_mode = &(lb_rr_graph.node_pb_graph_pin(enode.node_index)->parent_node->pb_type->modes[0]);
@@ -614,7 +647,13 @@ void LbRouter::expand_node(const LbRRGraph& lb_rr_graph,
   float cur_cost = exp_node.cost;
   t_mode* mode = routing_status_[cur_node].mode;
   if (nullptr == mode) {
-    mode = &(lb_rr_graph.node_pb_graph_pin(cur_node)->parent_node->pb_type->modes[0]);
+    if (nullptr == lb_rr_graph.node_pb_graph_pin(cur_node)) {
+      mode = nullptr;
+    } else if (true == is_primitive_pb_type(lb_rr_graph.node_pb_graph_pin(cur_node)->parent_node->pb_type)) {
+      mode = nullptr;
+    } else {
+      mode = &(lb_rr_graph.node_pb_graph_pin(cur_node)->parent_node->pb_type->modes[0]);
+    }
   }
 
   expand_edges(lb_rr_graph, mode, cur_node, cur_cost, net_fanout);
diff --git a/openfpga/src/repack/lb_router.h b/openfpga/src/repack/lb_router.h
index 0a8bb95fd..bf96a5958 100644
--- a/openfpga/src/repack/lb_router.h
+++ b/openfpga/src/repack/lb_router.h
@@ -15,6 +15,7 @@
 #include "physical_types.h"
 #include "vpr_context.h"
 
+#include "vpr_device_annotation.h"
 #include "lb_rr_graph.h"
 
 /********************************************************************
@@ -184,6 +185,17 @@ class LbRouter {
     void add_net_atom_net_id(const NetId& net, const AtomNetId& atom_net);
     void add_net_atom_pins(const NetId& net, const AtomPinId& src_pin, const std::vector<AtomPinId>& terminal_pins);
 
+    /* TODO: Initialize all the modes in routing status with the mode set in pb
+     * This is function used for general purpose packing
+     */
+
+    /* Set all the modes in routing status with the physical mode defined in device annotation
+     * This method is used only in repacking for physical logical blocks
+     * Do NOT use it during the general purpose packing
+     */ 
+    void set_physical_pb_modes(const LbRRGraph& lb_rr_graph,
+                               const VprDeviceAnnotation& device_annotation);
+
     /**
      * Perform routing algorithm on a given logical tile routing resource graph
      * Note: the lb_rr_graph must be the same as you initilized the router!!!
diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp
index eee2c9075..02f943b1c 100644
--- a/openfpga/src/repack/repack.cpp
+++ b/openfpga/src/repack/repack.cpp
@@ -269,6 +269,11 @@ void repack_cluster(const DeviceContext& device_ctx,
                      clustering_ctx, const_cast<const VprClusteringAnnotation&>(clustering_annotation),
                      block_id, verbose);
 
+  /* Initialize the modes to expand routing trees with the physical modes in device annotation
+   * This is a must-do before running the routeri in the purpose of repacking!!!
+   */
+  lb_router.set_physical_pb_modes(lb_rr_graph, device_annotation); 
+
   /* Run the router */
   bool route_success = lb_router.try_route(lb_rr_graph, atom_ctx.nlist, verbose);
 
diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
index 829deb1a9..2f318cbaa 100644
--- a/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
@@ -226,7 +226,7 @@
       <port name="in" physical_mode_port="in[0:5]"/>
       <port name="out" physical_mode_port="lut6_out"/>
     </pb_type>
-    <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="1"/>
+    <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
     <!-- End physical pb_type binding in complex block IO -->
   </pb_type_annotations>
 </openfpga_architecture>
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml
index 018cf491f..97001c497 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml
@@ -237,8 +237,9 @@
               </pb_type>
               <interconnect>
                 <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
-                <direct name="direct2" input="frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
-                <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
+                <direct name="direct2" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
+                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
+                <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
               </interconnect>
             </pb_type>
             <!-- Define flip-flop -->
@@ -251,6 +252,7 @@
             </pb_type>
             <interconnect>
               <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
+              <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
               <complete name="direct3" input="fabric.clk" output="ff[1:0].clk"/>
               <mux name="mux1" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
                 <!-- LUT to output is faster than FF to output on a Stratix IV -->

From b035b4c87f3317d5be332a86c0f9b148c9c02c13 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 21 Feb 2020 12:16:50 -0700
Subject: [PATCH 192/645] debugged with Lbrouter. Next step is to output
 routing traces to physical pb data structure

---
 .../libarchopenfpga/src/pb_type_annotation.cpp       |  4 ++--
 libopenfpga/libarchopenfpga/src/pb_type_annotation.h |  6 +++---
 .../src/read_xml_pb_type_annotation.cpp              |  2 +-
 openfpga/src/annotation/annotate_pb_graph.cpp        |  1 +
 openfpga/src/annotation/vpr_device_annotation.cpp    | 12 ++++++------
 openfpga/src/annotation/vpr_device_annotation.h      |  6 +++---
 openfpga/src/repack/repack.cpp                       |  2 +-
 openfpga/test_script/s298_k6_frac.openfpga           |  5 ++++-
 8 files changed, 21 insertions(+), 17 deletions(-)

diff --git a/libopenfpga/libarchopenfpga/src/pb_type_annotation.cpp b/libopenfpga/libarchopenfpga/src/pb_type_annotation.cpp
index d04e39b72..b38796c9c 100644
--- a/libopenfpga/libarchopenfpga/src/pb_type_annotation.cpp
+++ b/libopenfpga/libarchopenfpga/src/pb_type_annotation.cpp
@@ -69,7 +69,7 @@ std::string PbTypeAnnotation::circuit_model_name() const {
   return circuit_model_name_;
 }
 
-int PbTypeAnnotation::physical_pb_type_index_factor() const {
+float PbTypeAnnotation::physical_pb_type_index_factor() const {
   return physical_pb_type_index_factor_;
 }
 
@@ -164,7 +164,7 @@ void PbTypeAnnotation::set_circuit_model_name(const std::string& name) {
   circuit_model_name_ = name;
 }
 
-void PbTypeAnnotation::set_physical_pb_type_index_factor(const int& value) {
+void PbTypeAnnotation::set_physical_pb_type_index_factor(const float& value) {
   VTR_ASSERT(true == is_operating_pb_type());
   physical_pb_type_index_factor_ = value;
 }
diff --git a/libopenfpga/libarchopenfpga/src/pb_type_annotation.h b/libopenfpga/libarchopenfpga/src/pb_type_annotation.h
index a969ee93d..e80acc3dc 100644
--- a/libopenfpga/libarchopenfpga/src/pb_type_annotation.h
+++ b/libopenfpga/libarchopenfpga/src/pb_type_annotation.h
@@ -45,7 +45,7 @@ class PbTypeAnnotation {
     std::string idle_mode_name() const;
     std::vector<size_t> mode_bits() const;
     std::string circuit_model_name() const;
-    int physical_pb_type_index_factor() const;
+    float physical_pb_type_index_factor() const;
     int physical_pb_type_index_offset() const;
     std::vector<std::string> port_names() const;
     BasicPort physical_pb_type_port(const std::string& port_name) const;
@@ -63,7 +63,7 @@ class PbTypeAnnotation {
     void set_idle_mode_name(const std::string& name);
     void set_mode_bits(const std::vector<size_t>& mode_bits);
     void set_circuit_model_name(const std::string& name);
-    void set_physical_pb_type_index_factor(const int& value);
+    void set_physical_pb_type_index_factor(const float& value);
     void set_physical_pb_type_index_offset(const int& value);
     void add_pb_type_port_pair(const std::string& operating_pb_port_name,
                                const BasicPort& physical_pb_port);
@@ -119,7 +119,7 @@ class PbTypeAnnotation {
      * operating pb_type adder[5] with a full path clb.fle[arith].adder[5]
      * to physical pb_type adder[10] with a full path clb.fle[physical].adder[10]
      */
-    int physical_pb_type_index_factor_;
+    float physical_pb_type_index_factor_;
 
     /* The offset aims to align the indices for pb_type between operating and physical modes, 
      * especially when an operating mode contains multiple pb_type (num_pb>1) 
diff --git a/libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.cpp b/libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.cpp
index a17e970b7..743e23741 100644
--- a/libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.cpp
+++ b/libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.cpp
@@ -156,7 +156,7 @@ void read_xml_pb_type_annotation(pugi::xml_node& xml_pb_type,
 
   /* If this is an operating pb_type, index factor and offset may be optional needed */
   if (true == pb_type_annotation.is_operating_pb_type()) {
-    pb_type_annotation.set_physical_pb_type_index_factor(get_attribute(xml_pb_type, "physical_pb_type_index_factor", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(1));
+    pb_type_annotation.set_physical_pb_type_index_factor(get_attribute(xml_pb_type, "physical_pb_type_index_factor", loc_data, pugiutil::ReqOpt::OPTIONAL).as_float(1.));
     pb_type_annotation.set_physical_pb_type_index_offset(get_attribute(xml_pb_type, "physical_pb_type_index_offset", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(0));
   }
 
diff --git a/openfpga/src/annotation/annotate_pb_graph.cpp b/openfpga/src/annotation/annotate_pb_graph.cpp
index bf93cf28e..2b78f2f0e 100644
--- a/openfpga/src/annotation/annotate_pb_graph.cpp
+++ b/openfpga/src/annotation/annotate_pb_graph.cpp
@@ -405,6 +405,7 @@ void rec_build_vpr_physical_pb_graph_node_annotation(t_pb_graph_node* pb_graph_n
                                           * (size_t)vpr_device_annotation.pb_graph_node_unique_index(pb_graph_node)
                                           + vpr_device_annotation.physical_pb_type_index_offset(pb_graph_node->pb_type)
                                             );
+
   t_pb_graph_node* physical_pb_graph_node = vpr_device_annotation.pb_graph_node(physical_pb_type, physical_pb_graph_node_id);
   VTR_ASSERT(nullptr != physical_pb_graph_node);
   vpr_device_annotation.add_physical_pb_graph_node(pb_graph_node, physical_pb_graph_node);
diff --git a/openfpga/src/annotation/vpr_device_annotation.cpp b/openfpga/src/annotation/vpr_device_annotation.cpp
index 9be30591d..dfbcde112 100644
--- a/openfpga/src/annotation/vpr_device_annotation.cpp
+++ b/openfpga/src/annotation/vpr_device_annotation.cpp
@@ -165,12 +165,12 @@ t_pb_graph_node* VprDeviceAnnotation::physical_pb_graph_node(t_pb_graph_node* pb
   return physical_pb_graph_nodes_.at(pb_graph_node);
 }
 
-int VprDeviceAnnotation::physical_pb_type_index_factor(t_pb_type* pb_type) const {
+float VprDeviceAnnotation::physical_pb_type_index_factor(t_pb_type* pb_type) const {
   /* Ensure that the pb_type is in the list */
-  std::map<t_pb_type*, int>::const_iterator it = physical_pb_type_index_factors_.find(pb_type);
+  std::map<t_pb_type*, float>::const_iterator it = physical_pb_type_index_factors_.find(pb_type);
   if (it == physical_pb_type_index_factors_.end()) {
     /* Default value is 1 */
-    return 1;
+    return 1.;
   }
   return physical_pb_type_index_factors_.at(pb_type);
 }
@@ -374,11 +374,11 @@ void VprDeviceAnnotation::add_physical_pb_graph_node(t_pb_graph_node* operating_
   physical_pb_graph_nodes_[operating_pb_graph_node] = physical_pb_graph_node;
 }
 
-void VprDeviceAnnotation::add_physical_pb_type_index_factor(t_pb_type* pb_type, const int& factor) {
+void VprDeviceAnnotation::add_physical_pb_type_index_factor(t_pb_type* pb_type, const float& factor) {
   /* Warn any override attempt */
-  std::map<t_pb_type*, int>::const_iterator it = physical_pb_type_index_factors_.find(pb_type);
+  std::map<t_pb_type*, float>::const_iterator it = physical_pb_type_index_factors_.find(pb_type);
   if (it != physical_pb_type_index_factors_.end()) {
-    VTR_LOG_WARN("Override the annotation between operating pb_type '%s' and it physical pb_type index factor '%d'!\n",
+    VTR_LOG_WARN("Override the annotation between operating pb_type '%s' and it physical pb_type index factor '%f'!\n",
                  pb_type->name, factor);
   }
 
diff --git a/openfpga/src/annotation/vpr_device_annotation.h b/openfpga/src/annotation/vpr_device_annotation.h
index 0ecff4371..1cfdcd412 100644
--- a/openfpga/src/annotation/vpr_device_annotation.h
+++ b/openfpga/src/annotation/vpr_device_annotation.h
@@ -57,7 +57,7 @@ class VprDeviceAnnotation {
     /* Get the pointer to a pb_graph node using an unique index */
     t_pb_graph_node* pb_graph_node(t_pb_type* pb_type, const PbGraphNodeId& unique_index) const;
     t_pb_graph_node* physical_pb_graph_node(t_pb_graph_node* pb_graph_node) const;
-    int physical_pb_type_index_factor(t_pb_type* pb_type) const;
+    float physical_pb_type_index_factor(t_pb_type* pb_type) const;
     int physical_pb_type_index_offset(t_pb_type* pb_type) const;
 
     int physical_pb_pin_rotate_offset(t_port* pb_port) const;
@@ -88,7 +88,7 @@ class VprDeviceAnnotation {
     void add_pb_graph_node_unique_index(t_pb_graph_node* pb_graph_node);
     void add_physical_pb_graph_node(t_pb_graph_node* operating_pb_graph_node, 
                                     t_pb_graph_node* physical_pb_graph_node);
-    void add_physical_pb_type_index_factor(t_pb_type* pb_type, const int& factor);
+    void add_physical_pb_type_index_factor(t_pb_type* pb_type, const float& factor);
     void add_physical_pb_type_index_offset(t_pb_type* pb_type, const int& offset);
     void add_physical_pb_pin_rotate_offset(t_port* pb_port, const int& offset);
     void add_physical_pb_graph_pin(t_pb_graph_pin* operating_pb_graph_pin, t_pb_graph_pin* physical_pb_graph_pin);
@@ -99,7 +99,7 @@ class VprDeviceAnnotation {
   private: /* Internal data */
     /* Pair a regular pb_type to its physical pb_type */
     std::map<t_pb_type*, t_pb_type*> physical_pb_types_;
-    std::map<t_pb_type*, int> physical_pb_type_index_factors_;
+    std::map<t_pb_type*, float> physical_pb_type_index_factors_;
     std::map<t_pb_type*, int> physical_pb_type_index_offsets_;
 
     /* Pair a physical mode for a pb_type
diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp
index 02f943b1c..e554a63ed 100644
--- a/openfpga/src/repack/repack.cpp
+++ b/openfpga/src/repack/repack.cpp
@@ -277,7 +277,7 @@ void repack_cluster(const DeviceContext& device_ctx,
   /* Run the router */
   bool route_success = lb_router.try_route(lb_rr_graph, atom_ctx.nlist, verbose);
 
-  if (true == route_success) {
+  if (false == route_success) {
     VTR_LOGV(verbose, "Reroute failed\n");
     exit(1);
   }
diff --git a/openfpga/test_script/s298_k6_frac.openfpga b/openfpga/test_script/s298_k6_frac.openfpga
index 91c5fa551..a985511c4 100644
--- a/openfpga/test_script/s298_k6_frac.openfpga
+++ b/openfpga/test_script/s298_k6_frac.openfpga
@@ -4,8 +4,11 @@ vpr ./test_vpr_arch/k6_frac_N10_40nm.xml ./test_blif/s298.blif --write_rr_graph
 # Read OpenFPGA architecture definition
 read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
 
+# Write out the architecture XML as a proof
+#write_openfpga_arch -f ./arch_echo.xml
+
 # Annotate the OpenFPGA architecture to VPR data base
-link_openfpga_arch #--verbose
+link_openfpga_arch --verbose
 
 # Check and correct any naming conflicts in the BLIF netlist
 check_netlist_naming_conflict --fix --report ./netlist_renaming.xml

From 12f2888c7c063038ee06d34dee12cda0e219c187 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 21 Feb 2020 17:47:27 -0700
Subject: [PATCH 193/645] add physical pb data structure and basic allocator

---
 .../annotation/vpr_clustering_annotation.cpp  |  20 +++
 .../annotation/vpr_clustering_annotation.h    |   7 ++
 openfpga/src/repack/physical_pb.cpp           |  96 ++++++++++++++
 openfpga/src/repack/physical_pb.h             |  71 +++++++++++
 openfpga/src/repack/physical_pb_fwd.h         |  23 ++++
 openfpga/src/repack/repack.cpp                |   9 ++
 openfpga/src/utils/physical_pb_utils.cpp      | 119 ++++++++++++++++++
 openfpga/src/utils/physical_pb_utils.h        |  31 +++++
 8 files changed, 376 insertions(+)
 create mode 100644 openfpga/src/repack/physical_pb.cpp
 create mode 100644 openfpga/src/repack/physical_pb.h
 create mode 100644 openfpga/src/repack/physical_pb_fwd.h
 create mode 100644 openfpga/src/utils/physical_pb_utils.cpp
 create mode 100644 openfpga/src/utils/physical_pb_utils.h

diff --git a/openfpga/src/annotation/vpr_clustering_annotation.cpp b/openfpga/src/annotation/vpr_clustering_annotation.cpp
index cd32fdeac..e0c7ab575 100644
--- a/openfpga/src/annotation/vpr_clustering_annotation.cpp
+++ b/openfpga/src/annotation/vpr_clustering_annotation.cpp
@@ -41,6 +41,14 @@ AtomNetlist::TruthTable VprClusteringAnnotation::truth_table(t_pb* pb) const {
   return block_truth_tables_.at(pb);
 }
 
+PhysicalPb VprClusteringAnnotation::physical_pb(const ClusterBlockId& block_id) const {
+  if (physical_pbs_.end() == physical_pbs_.find(block_id)) {
+    return PhysicalPb();
+  }
+
+  return physical_pbs_.at(block_id);
+}
+
 /************************************************************************
  * Public mutators
  ***********************************************************************/
@@ -67,4 +75,16 @@ void VprClusteringAnnotation::adapt_truth_table(t_pb* pb,
   block_truth_tables_[pb] = tt;
 }
 
+void VprClusteringAnnotation::add_physical_pb(const ClusterBlockId& block_id,
+                                              const PhysicalPb& physical_pb) {
+  /* Warn any override attempt */
+  if (physical_pbs_.end() != physical_pbs_.find(block_id)) {
+    VTR_LOG_WARN("Override the physical pb for clustered block %lu in clustering context annotation!\n",
+                 size_t(block_id));
+  }
+
+  physical_pbs_[block_id] = physical_pb;
+}
+
+
 } /* End namespace openfpga*/
diff --git a/openfpga/src/annotation/vpr_clustering_annotation.h b/openfpga/src/annotation/vpr_clustering_annotation.h
index 2951ef226..b72173e1d 100644
--- a/openfpga/src/annotation/vpr_clustering_annotation.h
+++ b/openfpga/src/annotation/vpr_clustering_annotation.h
@@ -9,6 +9,8 @@
 /* Header from vpr library */
 #include "clustered_netlist.h"
 
+#include "physical_pb.h"
+
 /* Begin namespace openfpga */
 namespace openfpga {
 
@@ -33,14 +35,19 @@ class VprClusteringAnnotation {
     ClusterNetId net(const ClusterBlockId& block_id, const int& pin_index) const;
     bool is_truth_table_adapted(t_pb* pb) const;
     AtomNetlist::TruthTable truth_table(t_pb* pb) const;
+    PhysicalPb physical_pb(const ClusterBlockId& block_id) const;
   public:  /* Public mutators */
     void rename_net(const ClusterBlockId& block_id, const int& pin_index,
                     const ClusterNetId& net_id);
     void adapt_truth_table(t_pb* pb, const AtomNetlist::TruthTable& tt);
+    void add_physical_pb(const ClusterBlockId& block_id, const PhysicalPb& physical_pb);
   private: /* Internal data */
     /* Pair a regular pb_type to its physical pb_type */
     std::map<ClusterBlockId, std::map<int, ClusterNetId>> net_names_;
     std::map<t_pb*, AtomNetlist::TruthTable> block_truth_tables_;
+
+    /* Link clustered blocks to physical pb (mapping results) */
+    std::map<ClusterBlockId, PhysicalPb> physical_pbs_;
 };
 
 } /* End namespace openfpga*/
diff --git a/openfpga/src/repack/physical_pb.cpp b/openfpga/src/repack/physical_pb.cpp
new file mode 100644
index 000000000..1b3760dcc
--- /dev/null
+++ b/openfpga/src/repack/physical_pb.cpp
@@ -0,0 +1,96 @@
+/******************************************************************************
+ * Memember functions for data structure PhysicalPb
+ ******************************************************************************/
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+#include "physical_pb.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/**************************************************
+ * Public Accessors 
+ *************************************************/
+PhysicalPb::physical_pb_range PhysicalPb::pbs() const {
+  return vtr::make_range(pb_ids_.begin(), pb_ids_.end());
+}
+
+std::string PhysicalPb::name(const PhysicalPbId& pb) const {
+  VTR_ASSERT(true == valid_pb_id(pb));
+  return names_[pb];
+}
+
+/* Find the module id by a given name, return invalid if not found */
+PhysicalPbId PhysicalPb::find_pb(const t_pb_graph_node* pb_graph_node) const {
+  if (type2id_map_.find(pb_graph_node) != type2id_map_.end()) {
+    /* Find it, return the id */
+    return type2id_map_.at(pb_graph_node); 
+  }
+  /* Not found, return an invalid id */
+  return PhysicalPbId::INVALID();
+}
+
+PhysicalPbId PhysicalPb::parent(const PhysicalPbId& pb) const {
+  VTR_ASSERT(true == valid_pb_id(pb));
+  return parent_pbs_[pb];
+}
+
+/******************************************************************************
+ * Private Mutators
+ ******************************************************************************/
+PhysicalPbId PhysicalPb::create_pb(const t_pb_graph_node* pb_graph_node) {
+  /* Find if the name has been used. If used, return an invalid Id and report error! */
+  std::map<const t_pb_graph_node*, PhysicalPbId>::iterator it = type2id_map_.find(pb_graph_node);
+  if (it != type2id_map_.end()) {
+    return PhysicalPbId::INVALID();
+  }
+
+  /* Create an new id */
+  PhysicalPbId pb = PhysicalPbId(pb_ids_.size());
+  pb_ids_.push_back(pb);
+
+  /* Allocate other attributes */
+  names_.emplace_back();
+  pb_graph_nodes_.push_back(pb_graph_node);
+  mapped_atoms_.emplace_back();
+  child_pbs_.emplace_back();
+  parent_pbs_.emplace_back();
+  mode_bits_.emplace_back();
+
+  /* Register in the name2id map */
+  type2id_map_[pb_graph_node] = pb;
+
+  return pb;
+}
+
+void PhysicalPb::add_child(const PhysicalPbId& parent,
+                           const PhysicalPbId& child,
+                           const t_pb_type* child_type) {
+  VTR_ASSERT(true == valid_pb_id(parent)); 
+  VTR_ASSERT(true == valid_pb_id(child)); 
+
+  child_pbs_[parent][child_type].push_back(child);
+
+  if (PhysicalPbId::INVALID() != parent_pbs_[child]) {
+    VTR_LOGF_WARN(__FILE__, __LINE__,
+                  "Overwrite parent '%s' for physical pb '%s' with a new one '%s'!\n",
+                  pb_graph_nodes_[parent_pbs_[child]]->hierarchical_type_name().c_str(),
+                  pb_graph_nodes_[child]->hierarchical_type_name().c_str(),
+                  pb_graph_nodes_[parent]->hierarchical_type_name().c_str());
+  }
+  parent_pbs_[child] = parent;
+}
+
+/******************************************************************************
+ * Private validators/invalidators
+ ******************************************************************************/
+bool PhysicalPb::valid_pb_id(const PhysicalPbId& pb_id) const {
+  return ( size_t(pb_id) < pb_ids_.size() ) && ( pb_id == pb_ids_[pb_id] ); 
+}
+
+bool PhysicalPb::empty() const {
+  return 0 == pb_ids_.size();
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/repack/physical_pb.h b/openfpga/src/repack/physical_pb.h
new file mode 100644
index 000000000..8a9d3b20d
--- /dev/null
+++ b/openfpga/src/repack/physical_pb.h
@@ -0,0 +1,71 @@
+#ifndef PHYSICAL_PB_H
+#define PHYSICAL_PB_H
+
+/********************************************************************
+ * Include header files required by the data structure definition
+ *******************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_geometry.h"
+#include "vtr_vector.h"
+
+/* Headers from readarch library */
+#include "physical_types.h"
+
+/* Headers from vpr library */
+#include "atom_netlist_fwd.h"
+
+#include "physical_pb_fwd.h"
+
+/* Begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * PhysicalPb object aims to store the mapped result for a programmable 
+ * logical block like the VPR data structure t_pb does.
+ * Differently, it is tailored for the physical implementation of a
+ * programmable block. 
+ *  - It does not contain multi-mode for each child physical_pb while
+ *    VPR t_pb does have multi-mode. This is because that the hardware 
+ *    implementation is unique
+ *  - It contains mode-selection bits for each primitive physical_pb
+ *    This is used to help bitstream generator to configure a primitive
+ *    circuit in the correct mode
+ *  - A primitive LUT can be mapped to various truth tables. 
+ *    This is true for any fracturable LUTs.
+ *******************************************************************/
+class PhysicalPb {
+  public: /* Types and ranges */
+    typedef vtr::vector<PhysicalPbId, PhysicalPbId>::const_iterator physical_pb_iterator;
+    typedef vtr::Range<physical_pb_iterator> physical_pb_range;
+  public: /* Public aggregators */
+    physical_pb_range pbs() const;
+    std::string name(const PhysicalPbId& pb) const;
+    PhysicalPbId find_pb(const t_pb_graph_node* name) const;
+    PhysicalPbId parent(const PhysicalPbId& pb) const;
+  public: /* Public mutators */
+    PhysicalPbId create_pb(const t_pb_graph_node* pb_graph_node);
+    void add_child(const PhysicalPbId& parent,
+                   const PhysicalPbId& child,
+                   const t_pb_type* child_type);
+  public: /* Public validators/invalidators */
+    bool valid_pb_id(const PhysicalPbId& pb_id) const;
+    bool empty() const;
+  private: /* Internal Data */
+    vtr::vector<PhysicalPbId, PhysicalPbId> pb_ids_;
+    vtr::vector<PhysicalPbId, const t_pb_graph_node*> pb_graph_nodes_;
+    vtr::vector<PhysicalPbId, std::string> names_;
+    vtr::vector<PhysicalPbId, std::vector<AtomBlockId>> mapped_atoms_;
+
+    /* Child pbs are organized as [0..num_child_pb_types-1][0..child_pb_type->num_pb-1] */
+    vtr::vector<PhysicalPbId, std::map<const t_pb_type*, std::vector<PhysicalPbId>>> child_pbs_;
+    vtr::vector<PhysicalPbId, PhysicalPbId> parent_pbs_;
+
+    vtr::vector<PhysicalPbId, std::vector<size_t>> mode_bits_;
+
+    /* Fast lookup */
+    std::map<const t_pb_graph_node*, PhysicalPbId> type2id_map_;
+};
+
+} /* End namespace openfpga*/
+
+#endif
diff --git a/openfpga/src/repack/physical_pb_fwd.h b/openfpga/src/repack/physical_pb_fwd.h
new file mode 100644
index 000000000..d601ab060
--- /dev/null
+++ b/openfpga/src/repack/physical_pb_fwd.h
@@ -0,0 +1,23 @@
+/**************************************************
+ * This file includes only declarations for 
+ * the data structures for PhysicalPb
+ * Please refer to physical_pb.h for more details
+ *************************************************/
+#ifndef PHYSICAL_PB_FWD_H
+#define PHYSICAL_PB_FWD_H
+
+#include "vtr_strong_id.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/* Strong Ids for ModuleManager */
+struct physical_pb_id_tag;
+
+typedef vtr::StrongId<physical_pb_id_tag> PhysicalPbId;
+
+class PhysicalPb;
+
+} /* end namespace openfpga */
+
+#endif 
diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp
index e554a63ed..578efd91f 100644
--- a/openfpga/src/repack/repack.cpp
+++ b/openfpga/src/repack/repack.cpp
@@ -14,6 +14,7 @@
 #include "build_physical_lb_rr_graph.h"
 #include "lb_router.h"
 #include "lb_router_utils.h"
+#include "physical_pb_utils.h"
 #include "repack.h"
 
 /* begin namespace openfpga */
@@ -284,6 +285,14 @@ void repack_cluster(const DeviceContext& device_ctx,
   VTR_ASSERT(true == route_success);
   VTR_LOGV(verbose, "Reroute succeed\n");
 
+  /* Annotate routing results to physical pb */
+  PhysicalPb phy_pb;
+  alloc_physical_pb_from_pb_graph(phy_pb, pb_graph_head, device_annotation);
+  rec_update_physical_pb_from_operating_pb(phy_pb, clustering_ctx.clb_nlist.block_pb(block_id));
+
+  /* Add the pb to clustering context */
+  clustering_annotation.add_physical_pb(block_id, phy_pb);
+
   VTR_LOG("Done\n");
 }
 
diff --git a/openfpga/src/utils/physical_pb_utils.cpp b/openfpga/src/utils/physical_pb_utils.cpp
new file mode 100644
index 000000000..9502df674
--- /dev/null
+++ b/openfpga/src/utils/physical_pb_utils.cpp
@@ -0,0 +1,119 @@
+/************************************************************************
+ * Function to perform fundamental operation for the physical pb using
+ * data structures
+ ***********************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+#include "openfpga_naming.h"
+#include "pb_type_utils.h"
+#include "physical_pb_utils.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/************************************************************************
+ * Allocate an empty physical pb graph based on pb_graph 
+ * This function should start with an empty physical pb object!!!
+ * Suggest to check this before executing this function
+ *   VTR_ASSERT(true == phy_pb.empty());
+ ***********************************************************************/
+static 
+void rec_alloc_physical_pb_from_pb_graph(PhysicalPb& phy_pb,
+                                         t_pb_graph_node* pb_graph_node,
+                                         const VprDeviceAnnotation& device_annotation) {
+  t_pb_type* pb_type = pb_graph_node->pb_type;
+
+  t_mode* physical_mode = device_annotation.physical_mode(pb_type);
+
+  PhysicalPbId cur_phy_pb_id = phy_pb.create_pb(pb_graph_node);
+  VTR_ASSERT(true == phy_pb.valid_pb_id(cur_phy_pb_id));
+
+  /* Finish for primitive node */
+  if (true == is_primitive_pb_type(pb_type)) {
+    return;
+  } 
+
+  /* Find the physical mode */
+  VTR_ASSERT(nullptr != physical_mode);
+
+  /* Go to the leaf nodes first. This aims to build all the primitive nodes first 
+   * and then we build the parents and create links
+   */
+  for (int ipb = 0; ipb < physical_mode->num_pb_type_children; ++ipb) {
+    for (int jpb = 0; jpb < physical_mode->pb_type_children[ipb].num_pb; ++jpb) {
+      rec_alloc_physical_pb_from_pb_graph(phy_pb,
+                                          &(pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb][jpb]),
+                                          device_annotation);
+    }
+  }
+}
+
+/************************************************************************
+ * Build all the relationships between parent and children 
+ * inside a physical pb graph 
+ * This function must be executed after rec_alloc_physical_pb_from_pb_graph()!!!
+ ***********************************************************************/
+static 
+void rec_build_physical_pb_children_from_pb_graph(PhysicalPb& phy_pb,
+                                                  t_pb_graph_node* pb_graph_node,
+                                                  const VprDeviceAnnotation& device_annotation) {
+  t_pb_type* pb_type = pb_graph_node->pb_type;
+
+  /* Finish for primitive node */
+  if (true == is_primitive_pb_type(pb_type)) {
+    return;
+  } 
+
+  t_mode* physical_mode = device_annotation.physical_mode(pb_type);
+  VTR_ASSERT(nullptr != physical_mode);
+
+  /* Please use the openfpga naming function so that you can build the link to module manager */
+  PhysicalPbId parent_pb_id = phy_pb.find_pb(pb_graph_node);
+  VTR_ASSERT(true == phy_pb.valid_pb_id(parent_pb_id));
+
+  /* Add all the children */
+  for (int ipb = 0; ipb < physical_mode->num_pb_type_children; ++ipb) {
+    for (int jpb = 0; jpb < physical_mode->pb_type_children[ipb].num_pb; ++jpb) {
+      PhysicalPbId child_pb_id = phy_pb.find_pb(&(pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb][jpb]));
+      VTR_ASSERT(true == phy_pb.valid_pb_id(child_pb_id));
+      phy_pb.add_child(parent_pb_id, child_pb_id, &(physical_mode->pb_type_children[ipb]));
+    }
+  }
+
+  /* Go to the leaf nodes first. This aims to build all the primitive nodes first 
+   * and then we build the parents and create links
+   */
+  for (int ipb = 0; ipb < physical_mode->num_pb_type_children; ++ipb) {
+    for (int jpb = 0; jpb < physical_mode->pb_type_children[ipb].num_pb; ++jpb) {
+      rec_build_physical_pb_children_from_pb_graph(phy_pb,
+                                                   &(pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb][jpb]),
+                                                   device_annotation);
+    }
+  }
+}
+
+/************************************************************************
+ * Allocate an empty physical pb graph based on pb_graph 
+ * This function should start with an empty physical pb object!!!
+ * Suggest to check this before executing this function
+ *   VTR_ASSERT(true == phy_pb.empty());
+ ***********************************************************************/
+void alloc_physical_pb_from_pb_graph(PhysicalPb& phy_pb,
+                                     t_pb_graph_node* pb_graph_head,
+                                     const VprDeviceAnnotation& device_annotation) {
+  VTR_ASSERT(true == phy_pb.empty());
+
+  rec_alloc_physical_pb_from_pb_graph(phy_pb, pb_graph_head, device_annotation);
+  rec_build_physical_pb_children_from_pb_graph(phy_pb, pb_graph_head, device_annotation);
+}
+
+/************************************************************************
+ * Synchronize mapping results from an operating pb to a physical pb
+ ***********************************************************************/
+void rec_update_physical_pb_from_operating_pb(PhysicalPb& phy_pb, 
+                                              t_pb* op_pb) {
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/utils/physical_pb_utils.h b/openfpga/src/utils/physical_pb_utils.h
new file mode 100644
index 000000000..bdd37dc81
--- /dev/null
+++ b/openfpga/src/utils/physical_pb_utils.h
@@ -0,0 +1,31 @@
+/********************************************************************
+ * Header file for circuit_library_utils.cpp
+ *******************************************************************/
+#ifndef PHYSICAL_PB_UTILS_H
+#define PHYSICAL_PB_UTILS_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <vector>
+#include "physical_types.h"
+#include "vpr_device_annotation.h"
+#include "physical_pb.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void alloc_physical_pb_from_pb_graph(PhysicalPb& phy_pb,
+                                     t_pb_graph_node* pb_graph_head,
+                                     const VprDeviceAnnotation& device_annotation);
+
+void rec_update_physical_pb_from_operating_pb(PhysicalPb& phy_pb, 
+                                              t_pb* op_pb);
+
+} /* end namespace openfpga */
+
+#endif

From 926e429374632096b76c7e04265c951ccfeab007 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 21 Feb 2020 20:39:49 -0700
Subject: [PATCH 194/645] add save repacking results in physical pb

---
 openfpga/src/repack/physical_pb.cpp      |  44 ++++++-
 openfpga/src/repack/physical_pb.h        |  12 +-
 openfpga/src/repack/repack.cpp           |  18 ++-
 openfpga/src/utils/physical_pb_utils.cpp | 161 ++++++++++++++++++++++-
 openfpga/src/utils/physical_pb_utils.h   |   8 +-
 5 files changed, 228 insertions(+), 15 deletions(-)

diff --git a/openfpga/src/repack/physical_pb.cpp b/openfpga/src/repack/physical_pb.cpp
index 1b3760dcc..647c527af 100644
--- a/openfpga/src/repack/physical_pb.cpp
+++ b/openfpga/src/repack/physical_pb.cpp
@@ -36,6 +36,17 @@ PhysicalPbId PhysicalPb::parent(const PhysicalPbId& pb) const {
   return parent_pbs_[pb];
 }
 
+AtomNetId PhysicalPb::pb_graph_pin_atom_net(const PhysicalPbId& pb,
+                                            const t_pb_graph_pin* pb_graph_pin) const {
+  VTR_ASSERT(true == valid_pb_id(pb));
+  if (pin_atom_nets_[pb].find(pb_graph_pin) != pin_atom_nets_[pb].end()) {
+    /* Find it, return the id */
+    return pin_atom_nets_[pb].at(pb_graph_pin); 
+  }
+  /* Not found, return an invalid id */
+  return AtomNetId::INVALID();
+}
+
 /******************************************************************************
  * Private Mutators
  ******************************************************************************/
@@ -53,9 +64,12 @@ PhysicalPbId PhysicalPb::create_pb(const t_pb_graph_node* pb_graph_node) {
   /* Allocate other attributes */
   names_.emplace_back();
   pb_graph_nodes_.push_back(pb_graph_node);
-  mapped_atoms_.emplace_back();
+  atom_blocks_.emplace_back();
+  pin_atom_nets_.emplace_back();
+
   child_pbs_.emplace_back();
   parent_pbs_.emplace_back();
+
   mode_bits_.emplace_back();
 
   /* Register in the name2id map */
@@ -82,6 +96,34 @@ void PhysicalPb::add_child(const PhysicalPbId& parent,
   parent_pbs_[child] = parent;
 }
 
+void PhysicalPb::set_mode_bits(const PhysicalPbId& pb,
+                               const std::vector<size_t>& mode_bits) {
+  VTR_ASSERT(true == valid_pb_id(pb)); 
+   
+  mode_bits_[pb] = mode_bits;
+}
+
+void PhysicalPb::add_atom_block(const PhysicalPbId& pb,
+                                const AtomBlockId& atom_block) {
+  VTR_ASSERT(true == valid_pb_id(pb)); 
+   
+  atom_blocks_[pb].push_back(atom_block);
+}
+
+void PhysicalPb::set_pb_graph_pin_atom_net(const PhysicalPbId& pb,
+                                           const t_pb_graph_pin* pb_graph_pin,
+                                           const AtomNetId& atom_net) {
+  VTR_ASSERT(true == valid_pb_id(pb)); 
+  if (pin_atom_nets_[pb].end() != pin_atom_nets_[pb].find(pb_graph_pin)) {
+    VTR_LOG_WARN("Overwrite pb_graph_pin '%s[%d]' atom net '%lu' with '%lu'\n",
+                 pb_graph_pin->port->name, pb_graph_pin->pin_number,
+                 size_t(pin_atom_nets_[pb][pb_graph_pin]),
+                 size_t(atom_net));
+  }
+
+  pin_atom_nets_[pb][pb_graph_pin] = atom_net;
+}
+
 /******************************************************************************
  * Private validators/invalidators
  ******************************************************************************/
diff --git a/openfpga/src/repack/physical_pb.h b/openfpga/src/repack/physical_pb.h
index 8a9d3b20d..9e4dff206 100644
--- a/openfpga/src/repack/physical_pb.h
+++ b/openfpga/src/repack/physical_pb.h
@@ -42,11 +42,20 @@ class PhysicalPb {
     std::string name(const PhysicalPbId& pb) const;
     PhysicalPbId find_pb(const t_pb_graph_node* name) const;
     PhysicalPbId parent(const PhysicalPbId& pb) const;
+    AtomNetId pb_graph_pin_atom_net(const PhysicalPbId& pb,
+                                    const t_pb_graph_pin* pb_graph_pin) const;
   public: /* Public mutators */
     PhysicalPbId create_pb(const t_pb_graph_node* pb_graph_node);
     void add_child(const PhysicalPbId& parent,
                    const PhysicalPbId& child,
                    const t_pb_type* child_type);
+    void add_atom_block(const PhysicalPbId& pb,
+                        const AtomBlockId& atom_block);
+    void set_mode_bits(const PhysicalPbId& pb,
+                       const std::vector<size_t>& mode_bits);
+    void set_pb_graph_pin_atom_net(const PhysicalPbId& pb,
+                                   const t_pb_graph_pin* pb_graph_pin,
+                                   const AtomNetId& atom_net);
   public: /* Public validators/invalidators */
     bool valid_pb_id(const PhysicalPbId& pb_id) const;
     bool empty() const;
@@ -54,7 +63,8 @@ class PhysicalPb {
     vtr::vector<PhysicalPbId, PhysicalPbId> pb_ids_;
     vtr::vector<PhysicalPbId, const t_pb_graph_node*> pb_graph_nodes_;
     vtr::vector<PhysicalPbId, std::string> names_;
-    vtr::vector<PhysicalPbId, std::vector<AtomBlockId>> mapped_atoms_;
+    vtr::vector<PhysicalPbId, std::vector<AtomBlockId>> atom_blocks_;
+    vtr::vector<PhysicalPbId, std::map<const t_pb_graph_pin*, AtomNetId>> pin_atom_nets_;
 
     /* Child pbs are organized as [0..num_child_pb_types-1][0..child_pb_type->num_pb-1] */
     vtr::vector<PhysicalPbId, std::map<const t_pb_type*, std::vector<PhysicalPbId>>> child_pbs_;
diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp
index 578efd91f..e4df2986d 100644
--- a/openfpga/src/repack/repack.cpp
+++ b/openfpga/src/repack/repack.cpp
@@ -242,8 +242,7 @@ void add_lb_router_nets(LbRouter& lb_router,
  * - Output routing results to data structure PhysicalPb and store it in clustering annotation
  ***************************************************************************************/
 static 
-void repack_cluster(const DeviceContext& device_ctx,
-                    const AtomContext& atom_ctx,
+void repack_cluster(const AtomContext& atom_ctx,
                     const ClusteringContext& clustering_ctx,
                     const VprDeviceAnnotation& device_annotation,
                     VprClusteringAnnotation& clustering_annotation,
@@ -288,7 +287,13 @@ void repack_cluster(const DeviceContext& device_ctx,
   /* Annotate routing results to physical pb */
   PhysicalPb phy_pb;
   alloc_physical_pb_from_pb_graph(phy_pb, pb_graph_head, device_annotation);
-  rec_update_physical_pb_from_operating_pb(phy_pb, clustering_ctx.clb_nlist.block_pb(block_id));
+  rec_update_physical_pb_from_operating_pb(phy_pb,
+                                           clustering_ctx.clb_nlist.block_pb(block_id),
+                                           clustering_ctx.clb_nlist.block_pb(block_id)->pb_route,
+                                           atom_ctx,
+                                           device_annotation);
+  /* TODO: save routing results */
+  VTR_LOGV(verbose, "Saved results in physical pb\n");
 
   /* Add the pb to clustering context */
   clustering_annotation.add_physical_pb(block_id, phy_pb);
@@ -300,8 +305,7 @@ void repack_cluster(const DeviceContext& device_ctx,
  * Repack each clustered blocks in the clustering context
  ***************************************************************************************/
 static 
-void repack_clusters(const DeviceContext& device_ctx,
-                     const AtomContext& atom_ctx,
+void repack_clusters(const AtomContext& atom_ctx,
                      const ClusteringContext& clustering_ctx,
                      const VprDeviceAnnotation& device_annotation,
                      VprClusteringAnnotation& clustering_annotation,
@@ -309,7 +313,7 @@ void repack_clusters(const DeviceContext& device_ctx,
   vtr::ScopedStartFinishTimer timer("Repack clustered blocks to physical implementation of logical tile");
 
   for (auto blk_id : clustering_ctx.clb_nlist.blocks()) {
-    repack_cluster(device_ctx, atom_ctx, clustering_ctx, 
+    repack_cluster(atom_ctx, clustering_ctx, 
                    device_annotation, clustering_annotation, 
                    blk_id, verbose);
   }
@@ -338,7 +342,7 @@ void pack_physical_pbs(const DeviceContext& device_ctx,
                               verbose);
 
   /* Call the LbRouter to re-pack each clustered block to physical implementation */ 
-  repack_clusters(device_ctx, atom_ctx, clustering_ctx, 
+  repack_clusters(atom_ctx, clustering_ctx, 
                   const_cast<const VprDeviceAnnotation&>(device_annotation), clustering_annotation, 
                   verbose);
 }
diff --git a/openfpga/src/utils/physical_pb_utils.cpp b/openfpga/src/utils/physical_pb_utils.cpp
index 9502df674..ec668a7d3 100644
--- a/openfpga/src/utils/physical_pb_utils.cpp
+++ b/openfpga/src/utils/physical_pb_utils.cpp
@@ -21,7 +21,7 @@ namespace openfpga {
  ***********************************************************************/
 static 
 void rec_alloc_physical_pb_from_pb_graph(PhysicalPb& phy_pb,
-                                         t_pb_graph_node* pb_graph_node,
+                                         const t_pb_graph_node* pb_graph_node,
                                          const VprDeviceAnnotation& device_annotation) {
   t_pb_type* pb_type = pb_graph_node->pb_type;
 
@@ -57,7 +57,7 @@ void rec_alloc_physical_pb_from_pb_graph(PhysicalPb& phy_pb,
  ***********************************************************************/
 static 
 void rec_build_physical_pb_children_from_pb_graph(PhysicalPb& phy_pb,
-                                                  t_pb_graph_node* pb_graph_node,
+                                                  const t_pb_graph_node* pb_graph_node,
                                                   const VprDeviceAnnotation& device_annotation) {
   t_pb_type* pb_type = pb_graph_node->pb_type;
 
@@ -101,7 +101,7 @@ void rec_build_physical_pb_children_from_pb_graph(PhysicalPb& phy_pb,
  *   VTR_ASSERT(true == phy_pb.empty());
  ***********************************************************************/
 void alloc_physical_pb_from_pb_graph(PhysicalPb& phy_pb,
-                                     t_pb_graph_node* pb_graph_head,
+                                     const t_pb_graph_node* pb_graph_head,
                                      const VprDeviceAnnotation& device_annotation) {
   VTR_ASSERT(true == phy_pb.empty());
 
@@ -109,11 +109,164 @@ void alloc_physical_pb_from_pb_graph(PhysicalPb& phy_pb,
   rec_build_physical_pb_children_from_pb_graph(phy_pb, pb_graph_head, device_annotation);
 }
 
+/************************************************************************
+ * Update a mapping net from a pin of an operating primitive pb to a 
+ * physical pb data base
+ ***********************************************************************/
+static 
+void update_primitive_physical_pb_pin_atom_net(PhysicalPb& phy_pb, 
+                                               const PhysicalPbId& primitive_pb,
+                                               const t_pb_graph_pin* pb_graph_pin,
+                                               const t_pb_routes& pb_route,
+                                               const VprDeviceAnnotation& device_annotation) {
+  int node_index = pb_graph_pin->pin_count_in_cluster;
+  if (pb_route.count(node_index)) {
+    /* The pin is mapped to a net, find the original pin in the atom netlist */
+    AtomNetId atom_net = pb_route[node_index].atom_net_id;
+
+    VTR_ASSERT(atom_net);
+   
+    /* Find the physical pb_graph_pin */
+    t_pb_graph_pin* physical_pb_graph_pin = device_annotation.physical_pb_graph_pin((t_pb_graph_pin*)pb_graph_pin);
+    VTR_ASSERT(nullptr != physical_pb_graph_pin);
+
+    /* Check if the pin has been mapped to a net.
+     * If yes, the atom net must be the same 
+     */
+    if (AtomNetId::INVALID() == phy_pb.pb_graph_pin_atom_net(primitive_pb, physical_pb_graph_pin)) {
+      phy_pb.set_pb_graph_pin_atom_net(primitive_pb, physical_pb_graph_pin, atom_net);
+    } else {
+      VTR_ASSERT(atom_net == phy_pb.pb_graph_pin_atom_net(primitive_pb, physical_pb_graph_pin));
+    }
+  }
+}
+
+/************************************************************************
+ * Synchronize mapping nets from an operating primitive pb to a physical pb
+ ***********************************************************************/
+static 
+void synchronize_primitive_physical_pb_atom_nets(PhysicalPb& phy_pb, 
+                                                 const PhysicalPbId& primitive_pb,
+                                                 const t_pb_graph_node* pb_graph_node,
+                                                 const t_pb_routes& pb_route,
+                                                 const AtomContext& atom_ctx,
+                                                 const AtomBlockId& atom_blk,
+                                                 const VprDeviceAnnotation& device_annotation) {
+  /* Iterate over all the ports: input, output and clock */
+  for (int iport = 0; iport < pb_graph_node->num_input_ports; ++iport) {
+    for (int ipin = 0; ipin < pb_graph_node->num_input_pins[iport]; ++ipin) {
+      /* Port exists (some LUTs may have no input and hence no port in the atom netlist) */
+      t_model_ports* model_port = pb_graph_node->input_pins[iport][ipin].port->model_port;
+      if (nullptr == model_port) {
+        continue;
+      } 
+
+      AtomPortId atom_port = atom_ctx.nlist.find_atom_port(atom_blk, model_port);
+      if (!atom_port) { 
+        continue;
+      }
+      /* Find the atom nets mapped to the pin
+       * Note that some inputs may not be used, we set them to be open by default
+       */
+      update_primitive_physical_pb_pin_atom_net(phy_pb, primitive_pb,
+                                                &(pb_graph_node->input_pins[iport][ipin]),
+                                                pb_route, device_annotation);
+    }
+  }
+
+  for (int iport = 0; iport < pb_graph_node->num_output_ports; ++iport) {
+    for (int ipin = 0; ipin < pb_graph_node->num_output_pins[iport]; ++ipin) {
+      /* Port exists (some LUTs may have no input and hence no port in the atom netlist) */
+      t_model_ports* model_port = pb_graph_node->output_pins[iport][ipin].port->model_port;
+      if (nullptr == model_port) {
+        continue;
+      } 
+
+      AtomPortId atom_port = atom_ctx.nlist.find_atom_port(atom_blk, model_port);
+      if (!atom_port) { 
+        continue;
+      }
+      /* Find the atom nets mapped to the pin
+       * Note that some inputs may not be used, we set them to be open by default
+       */
+      update_primitive_physical_pb_pin_atom_net(phy_pb, primitive_pb,
+                                                &(pb_graph_node->output_pins[iport][ipin]),
+                                                pb_route, device_annotation);
+    }
+  }
+
+  for (int iport = 0; iport < pb_graph_node->num_clock_ports; ++iport) {
+    for (int ipin = 0; ipin < pb_graph_node->num_clock_pins[iport]; ++ipin) {
+      /* Port exists (some LUTs may have no input and hence no port in the atom netlist) */
+      t_model_ports* model_port = pb_graph_node->clock_pins[iport][ipin].port->model_port;
+      if (nullptr == model_port) {
+        continue;
+      } 
+
+      AtomPortId atom_port = atom_ctx.nlist.find_atom_port(atom_blk, model_port);
+      if (!atom_port) { 
+        continue;
+      }
+      /* Find the atom nets mapped to the pin
+       * Note that some inputs may not be used, we set them to be open by default
+       */
+      update_primitive_physical_pb_pin_atom_net(phy_pb, primitive_pb,
+                                                &(pb_graph_node->clock_pins[iport][ipin]),
+                                                pb_route, device_annotation);
+    }
+  }
+}
+
 /************************************************************************
  * Synchronize mapping results from an operating pb to a physical pb
  ***********************************************************************/
 void rec_update_physical_pb_from_operating_pb(PhysicalPb& phy_pb, 
-                                              t_pb* op_pb) {
+                                              const t_pb* op_pb,
+                                              const t_pb_routes& pb_route,
+                                              const AtomContext& atom_ctx,
+                                              const VprDeviceAnnotation& device_annotation) {
+  t_pb_graph_node* pb_graph_node = op_pb->pb_graph_node;
+  t_pb_type* pb_type = pb_graph_node->pb_type;
+
+  if (true == is_primitive_pb_type(pb_type)) {
+    t_pb_graph_node* physical_pb_graph_node = device_annotation.physical_pb_graph_node(pb_graph_node);
+    VTR_ASSERT(nullptr != physical_pb_graph_node);
+    /* Find the physical pb */
+    const PhysicalPbId& physical_pb = phy_pb.find_pb(physical_pb_graph_node);
+    VTR_ASSERT(true == phy_pb.valid_pb_id(physical_pb));
+
+    /* Set the mode bits */
+    phy_pb.set_mode_bits(physical_pb, device_annotation.pb_type_mode_bits(physical_pb_graph_node->pb_type));
+
+    /* Find mapped atom block and add to this physical pb */
+    AtomBlockId atom_blk = atom_ctx.nlist.find_block(op_pb->name);
+    VTR_ASSERT(atom_blk);
+
+    phy_pb.add_atom_block(physical_pb, atom_blk);
+
+    /* TODO: Iterate over ports and annotate the atom pins */
+    synchronize_primitive_physical_pb_atom_nets(phy_pb, physical_pb,
+                                                pb_graph_node, 
+                                                pb_route,
+                                                atom_ctx, atom_blk,
+                                                device_annotation);
+    return;
+  }
+
+  /* Walk through the pb recursively but only visit the mapped modes and child pbs */
+  t_mode* mapped_mode = &(pb_graph_node->pb_type->modes[op_pb->mode]);
+  for (int ipb = 0; ipb < mapped_mode->num_pb_type_children; ++ipb) {
+    /* Each child may exist multiple times in the hierarchy*/
+    for (int jpb = 0; jpb < mapped_mode->pb_type_children[ipb].num_pb; ++jpb) {
+      if ((nullptr != op_pb->child_pbs[ipb]) && (nullptr != op_pb->child_pbs[ipb][jpb].name)) {
+        rec_update_physical_pb_from_operating_pb(phy_pb, 
+                                                 &(op_pb->child_pbs[ipb][jpb]),
+                                                 pb_route,
+                                                 atom_ctx,
+                                                 device_annotation);
+      }
+    }
+  }
 }
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/utils/physical_pb_utils.h b/openfpga/src/utils/physical_pb_utils.h
index bdd37dc81..0e8bb71df 100644
--- a/openfpga/src/utils/physical_pb_utils.h
+++ b/openfpga/src/utils/physical_pb_utils.h
@@ -10,6 +10,7 @@
 #include <vector>
 #include "physical_types.h"
 #include "vpr_device_annotation.h"
+#include "vpr_context.h"
 #include "physical_pb.h"
 
 /********************************************************************
@@ -20,11 +21,14 @@
 namespace openfpga {
 
 void alloc_physical_pb_from_pb_graph(PhysicalPb& phy_pb,
-                                     t_pb_graph_node* pb_graph_head,
+                                     const t_pb_graph_node* pb_graph_head,
                                      const VprDeviceAnnotation& device_annotation);
 
 void rec_update_physical_pb_from_operating_pb(PhysicalPb& phy_pb, 
-                                              t_pb* op_pb);
+                                              const t_pb* op_pb,
+                                              const t_pb_routes& pb_route,
+                                              const AtomContext& atom_ctx,
+                                              const VprDeviceAnnotation& device_annotation);
 
 } /* end namespace openfpga */
 

From 921bf7dd7bac1f4303936cc41562e4d8a063b530 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 21 Feb 2020 20:45:22 -0700
Subject: [PATCH 195/645] use constant in device annotation

---
 openfpga/src/annotation/vpr_device_annotation.cpp | 8 ++++----
 openfpga/src/annotation/vpr_device_annotation.h   | 6 +++---
 openfpga/src/utils/physical_pb_utils.cpp          | 2 +-
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/openfpga/src/annotation/vpr_device_annotation.cpp b/openfpga/src/annotation/vpr_device_annotation.cpp
index dfbcde112..0787e0225 100644
--- a/openfpga/src/annotation/vpr_device_annotation.cpp
+++ b/openfpga/src/annotation/vpr_device_annotation.cpp
@@ -206,9 +206,9 @@ int VprDeviceAnnotation::physical_pb_pin_offset(t_port* pb_port) const {
 }
 
 
-t_pb_graph_pin* VprDeviceAnnotation::physical_pb_graph_pin(t_pb_graph_pin* pb_graph_pin) const {
+t_pb_graph_pin* VprDeviceAnnotation::physical_pb_graph_pin(const t_pb_graph_pin* pb_graph_pin) const {
   /* Ensure that the pb_type is in the list */
-  std::map<t_pb_graph_pin*, t_pb_graph_pin*>::const_iterator it = physical_pb_graph_pins_.find(pb_graph_pin);
+  std::map<const t_pb_graph_pin*, t_pb_graph_pin*>::const_iterator it = physical_pb_graph_pins_.find(pb_graph_pin);
   if (it == physical_pb_graph_pins_.end()) {
     return nullptr;
   }
@@ -409,10 +409,10 @@ void VprDeviceAnnotation::add_physical_pb_pin_rotate_offset(t_port* pb_port, con
   physical_pb_pin_offsets_[pb_port] = 0;
 }
 
-void VprDeviceAnnotation::add_physical_pb_graph_pin(t_pb_graph_pin* operating_pb_graph_pin, 
+void VprDeviceAnnotation::add_physical_pb_graph_pin(const t_pb_graph_pin* operating_pb_graph_pin, 
                                                     t_pb_graph_pin* physical_pb_graph_pin) {
   /* Warn any override attempt */
-  std::map<t_pb_graph_pin*, t_pb_graph_pin*>::const_iterator it = physical_pb_graph_pins_.find(operating_pb_graph_pin);
+  std::map<const t_pb_graph_pin*, t_pb_graph_pin*>::const_iterator it = physical_pb_graph_pins_.find(operating_pb_graph_pin);
   if (it != physical_pb_graph_pins_.end()) {
     VTR_LOG_WARN("Override the annotation between operating pb_graph_pin '%s' and it physical pb_graph_pin '%s'!\n",
                  operating_pb_graph_pin->port->name, physical_pb_graph_pin->port->name);
diff --git a/openfpga/src/annotation/vpr_device_annotation.h b/openfpga/src/annotation/vpr_device_annotation.h
index 1cfdcd412..00209df5c 100644
--- a/openfpga/src/annotation/vpr_device_annotation.h
+++ b/openfpga/src/annotation/vpr_device_annotation.h
@@ -70,7 +70,7 @@ class VprDeviceAnnotation {
      * The accumulated offset will be reset to 0 when it exceeds the msb() of the physical port
      */
     int physical_pb_pin_offset(t_port* pb_port) const;
-    t_pb_graph_pin* physical_pb_graph_pin(t_pb_graph_pin* pb_graph_pin) const;
+    t_pb_graph_pin* physical_pb_graph_pin(const t_pb_graph_pin* pb_graph_pin) const;
     CircuitModelId rr_switch_circuit_model(const RRSwitchId& rr_switch) const;
     CircuitModelId rr_segment_circuit_model(const RRSegmentId& rr_segment) const;
     ArchDirectId direct_annotation(const size_t& direct) const;
@@ -91,7 +91,7 @@ class VprDeviceAnnotation {
     void add_physical_pb_type_index_factor(t_pb_type* pb_type, const float& factor);
     void add_physical_pb_type_index_offset(t_pb_type* pb_type, const int& offset);
     void add_physical_pb_pin_rotate_offset(t_port* pb_port, const int& offset);
-    void add_physical_pb_graph_pin(t_pb_graph_pin* operating_pb_graph_pin, t_pb_graph_pin* physical_pb_graph_pin);
+    void add_physical_pb_graph_pin(const t_pb_graph_pin* operating_pb_graph_pin, t_pb_graph_pin* physical_pb_graph_pin);
     void add_rr_switch_circuit_model(const RRSwitchId& rr_switch, const CircuitModelId& circuit_model);
     void add_rr_segment_circuit_model(const RRSegmentId& rr_segment, const CircuitModelId& circuit_model);
     void add_direct_annotation(const size_t& direct, const ArchDirectId& arch_direct_id);
@@ -169,7 +169,7 @@ class VprDeviceAnnotation {
     std::map<t_pb_graph_node*, t_pb_graph_node*> physical_pb_graph_nodes_;
 
     /* Pair a pb_graph_pin to a physical pb_graph_pin */
-    std::map<t_pb_graph_pin*, t_pb_graph_pin*> physical_pb_graph_pins_;
+    std::map<const t_pb_graph_pin*, t_pb_graph_pin*> physical_pb_graph_pins_;
 
     /* Pair a Routing Resource Switch (rr_switch) to a circuit model */
     std::map<RRSwitchId, CircuitModelId> rr_switch_circuit_models_;
diff --git a/openfpga/src/utils/physical_pb_utils.cpp b/openfpga/src/utils/physical_pb_utils.cpp
index ec668a7d3..777f2ad0c 100644
--- a/openfpga/src/utils/physical_pb_utils.cpp
+++ b/openfpga/src/utils/physical_pb_utils.cpp
@@ -127,7 +127,7 @@ void update_primitive_physical_pb_pin_atom_net(PhysicalPb& phy_pb,
     VTR_ASSERT(atom_net);
    
     /* Find the physical pb_graph_pin */
-    t_pb_graph_pin* physical_pb_graph_pin = device_annotation.physical_pb_graph_pin((t_pb_graph_pin*)pb_graph_pin);
+    t_pb_graph_pin* physical_pb_graph_pin = device_annotation.physical_pb_graph_pin(pb_graph_pin);
     VTR_ASSERT(nullptr != physical_pb_graph_pin);
 
     /* Check if the pin has been mapped to a net.

From 9583731531c1d038f2f18c084936923e6a7f3c83 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 22 Feb 2020 22:10:32 -0700
Subject: [PATCH 196/645] add results saver for lb router

---
 openfpga/src/repack/lb_router.cpp       |  9 ++++++++
 openfpga/src/repack/lb_router.h         |  9 ++++++++
 openfpga/src/repack/lb_router_utils.cpp | 30 +++++++++++++++++++++++++
 openfpga/src/repack/lb_router_utils.h   |  5 +++++
 openfpga/src/repack/repack.cpp          |  1 +
 5 files changed, 54 insertions(+)

diff --git a/openfpga/src/repack/lb_router.cpp b/openfpga/src/repack/lb_router.cpp
index 277548e18..c1b67b804 100644
--- a/openfpga/src/repack/lb_router.cpp
+++ b/openfpga/src/repack/lb_router.cpp
@@ -39,6 +39,15 @@ LbRouter::LbRouter(const LbRRGraph& lb_rr_graph, t_logical_block_type_ptr lb_typ
 /**************************************************
  * Public Accessors 
  *************************************************/
+LbRouter::net_range LbRouter::nets() const {
+  return vtr::make_range(lb_net_ids_.begin(), lb_net_ids_.end());
+}
+
+AtomNetId LbRouter::net_atom_net_id(const NetId& net) const {
+  VTR_ASSERT(true == valid_net_id(net));
+  return lb_net_atom_net_ids_[net]; 
+}
+
 std::vector<LbRRNodeId> LbRouter::find_congested_rr_nodes(const LbRRGraph& lb_rr_graph) const {
   /* Validate if the rr_graph is the one we used to initialize the router */
   VTR_ASSERT(true == matched_lb_rr_graph(lb_rr_graph));
diff --git a/openfpga/src/repack/lb_router.h b/openfpga/src/repack/lb_router.h
index bf96a5958..c1d82ca1c 100644
--- a/openfpga/src/repack/lb_router.h
+++ b/openfpga/src/repack/lb_router.h
@@ -29,6 +29,9 @@ class LbRouter {
   public: /* Strong ids */
     struct net_id_tag;
     typedef vtr::StrongId<net_id_tag> NetId;
+  public: /* Types and ranges */
+    typedef vtr::vector<NetId, NetId>::const_iterator net_iterator;
+    typedef vtr::Range<net_iterator> net_range;
   public: /* Intra-Logic Block Routing Data Structures (by instance) */
     /**************************************************************************
      * Describes the status of a logic cluster_ctx.blocks routing resource node 
@@ -163,6 +166,12 @@ class LbRouter {
     LbRouter(const LbRRGraph& lb_rr_graph, t_logical_block_type_ptr lb_type);
   
   public :  /* Public accessors */
+    /* Return the ids for all the nets to be routed */ 
+    net_range nets() const;
+
+    /* Return the atom net id for a net to be routed */
+    AtomNetId net_atom_net_id(const NetId& net) const;    
+
     /**
      * Find all the routing resource nodes that are over-used, which they are used more than their capacity
      * This function is call to collect the nodes and router can reroute these net
diff --git a/openfpga/src/repack/lb_router_utils.cpp b/openfpga/src/repack/lb_router_utils.cpp
index 221f5a640..c106cd9f7 100644
--- a/openfpga/src/repack/lb_router_utils.cpp
+++ b/openfpga/src/repack/lb_router_utils.cpp
@@ -66,4 +66,34 @@ LbRouter::NetId add_lb_router_net_to_route(LbRouter& lb_router,
   return lb_net;
 }
 
+/***************************************************************************************
+ * Load the routing results (routing tree) from lb router to 
+ * a physical pb data structure
+ ***************************************************************************************/
+void save_lb_router_results_to_physical_pb(PhysicalPb& phy_pb,
+                                           const LbRouter& lb_router,
+                                           const LbRRGraph& lb_rr_graph) {
+  /* Get mapping routing nodes per net */
+  for (const LbRouter::NetId& net : lb_router.nets()) {
+    std::vector<LbRRNodeId> routed_nodes = lb_router.net_routed_nodes(net);
+    for (const LbRRNodeId& node : routed_nodes) {
+      t_pb_graph_pin* pb_graph_pin = lb_rr_graph.node_pb_graph_pin(node);
+      if (nullptr == pb_graph_pin) {
+        continue;
+      }
+      /* Find the pb id */
+      const PhysicalPbId& pb_id = phy_pb.find_pb(pb_graph_pin->parent_node);
+      VTR_ASSERT(true == phy_pb.valid_pb_id(pb_id));
+
+      const AtomNetId& atom_net = lb_router.net_atom_net_id(net);
+      
+      if (AtomNetId::INVALID() == phy_pb.pb_graph_pin_atom_net(pb_id, pb_graph_pin)) {
+        phy_pb.set_pb_graph_pin_atom_net(pb_id, pb_graph_pin, atom_net);
+      } else {
+        VTR_ASSERT(atom_net == phy_pb.pb_graph_pin_atom_net(pb_id, pb_graph_pin));
+      }
+    }
+  }
+}
+
 } /* end namespace openfpga */
diff --git a/openfpga/src/repack/lb_router_utils.h b/openfpga/src/repack/lb_router_utils.h
index 6a92201eb..129796e7d 100644
--- a/openfpga/src/repack/lb_router_utils.h
+++ b/openfpga/src/repack/lb_router_utils.h
@@ -7,6 +7,7 @@
 #include "atom_netlist.h"
 #include "lb_rr_graph.h"
 #include "lb_router.h"
+#include "physical_pb.h"
 
 /********************************************************************
  * Function declaration
@@ -22,6 +23,10 @@ LbRouter::NetId add_lb_router_net_to_route(LbRouter& lb_router,
                                            const AtomContext& atom_ctx,
                                            const AtomNetId& atom_net_id);
 
+void save_lb_router_results_to_physical_pb(PhysicalPb& phy_pb,
+                                           const LbRouter& lb_router,
+                                           const LbRRGraph& lb_rr_graph);
+
 } /* end namespace openfpga */
 
 #endif
diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp
index e4df2986d..371d4ab46 100644
--- a/openfpga/src/repack/repack.cpp
+++ b/openfpga/src/repack/repack.cpp
@@ -293,6 +293,7 @@ void repack_cluster(const AtomContext& atom_ctx,
                                            atom_ctx,
                                            device_annotation);
   /* TODO: save routing results */
+  save_lb_router_results_to_physical_pb(phy_pb, lb_router, lb_rr_graph);
   VTR_LOGV(verbose, "Saved results in physical pb\n");
 
   /* Add the pb to clustering context */

From 2d17395e13f5bb87717c1d898a705009d697b360 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 22 Feb 2020 23:04:42 -0700
Subject: [PATCH 197/645] start integrating fpga_bitstream. Bring data
 structures online

---
 openfpga/src/base/openfpga_bitstream.cpp      |  28 +++
 openfpga/src/base/openfpga_bitstream.h        |  23 +++
 .../src/base/openfpga_bitstream_command.cpp   |  20 ++
 openfpga/src/base/openfpga_context.h          |   6 +
 .../src/fpga_bitstream/bitstream_manager.cpp  | 187 ++++++++++++++++++
 .../src/fpga_bitstream/bitstream_manager.h    | 133 +++++++++++++
 .../fpga_bitstream/bitstream_manager_fwd.h    |  25 +++
 .../bitstream_manager_utils.cpp               |  58 ++++++
 .../fpga_bitstream/bitstream_manager_utils.h  |  24 +++
 .../fpga_bitstream/build_device_bitstream.cpp |  69 +++++++
 .../fpga_bitstream/build_device_bitstream.h   |  24 +++
 11 files changed, 597 insertions(+)
 create mode 100644 openfpga/src/base/openfpga_bitstream.cpp
 create mode 100644 openfpga/src/base/openfpga_bitstream.h
 create mode 100644 openfpga/src/fpga_bitstream/bitstream_manager.cpp
 create mode 100644 openfpga/src/fpga_bitstream/bitstream_manager.h
 create mode 100644 openfpga/src/fpga_bitstream/bitstream_manager_fwd.h
 create mode 100644 openfpga/src/fpga_bitstream/bitstream_manager_utils.cpp
 create mode 100644 openfpga/src/fpga_bitstream/bitstream_manager_utils.h
 create mode 100644 openfpga/src/fpga_bitstream/build_device_bitstream.cpp
 create mode 100644 openfpga/src/fpga_bitstream/build_device_bitstream.h

diff --git a/openfpga/src/base/openfpga_bitstream.cpp b/openfpga/src/base/openfpga_bitstream.cpp
new file mode 100644
index 000000000..8a51899e0
--- /dev/null
+++ b/openfpga/src/base/openfpga_bitstream.cpp
@@ -0,0 +1,28 @@
+/********************************************************************
+ * This file includes functions to build bitstream database
+ *******************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_time.h"
+#include "vtr_log.h"
+
+#include "build_device_bitstream.h"
+#include "openfpga_bitstream.h"
+
+/* Include global variables of VPR */
+#include "globals.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * A wrapper function to call the fabric_verilog function of FPGA-Verilog 
+ *******************************************************************/
+void fpga_bitstream(OpenfpgaContext& openfpga_ctx,
+                    const Command& cmd, const CommandContext& cmd_context) {
+
+  CommandOptionId opt_verbose = cmd.option("verbose");
+
+  openfpga_ctx.mutable_bitstream_manager() = build_device_bitstream(g_vpr_ctx, openfpga_ctx, cmd_context.option_enable(cmd, opt_verbose));
+} 
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_bitstream.h b/openfpga/src/base/openfpga_bitstream.h
new file mode 100644
index 000000000..1411dc090
--- /dev/null
+++ b/openfpga/src/base/openfpga_bitstream.h
@@ -0,0 +1,23 @@
+#ifndef OPENFPGA_BITSTREAM_H
+#define OPENFPGA_BITSTREAM_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "command.h"
+#include "command_context.h"
+#include "openfpga_context.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void fpga_bitstream(OpenfpgaContext& openfpga_ctx,
+                    const Command& cmd, const CommandContext& cmd_context); 
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/base/openfpga_bitstream_command.cpp b/openfpga/src/base/openfpga_bitstream_command.cpp
index 827dd1eca..af06cd60b 100644
--- a/openfpga/src/base/openfpga_bitstream_command.cpp
+++ b/openfpga/src/base/openfpga_bitstream_command.cpp
@@ -5,6 +5,7 @@
  * - repack : create physical pbs and redo packing 
  *******************************************************************/
 #include "openfpga_repack.h"
+#include "openfpga_bitstream.h"
 #include "openfpga_bitstream_command.h"
 
 /* begin namespace openfpga */
@@ -33,6 +34,25 @@ void add_openfpga_bitstream_commands(openfpga::Shell<OpenfpgaContext>& shell) {
   std::vector<ShellCommandId> cmd_dependency_repack;
   cmd_dependency_repack.push_back(shell_cmd_build_fabric_id);
   shell.set_command_dependency(shell_cmd_repack_id, cmd_dependency_repack);
+
+  /******************************** 
+   * Command 'fpga_bitstream' 
+   */
+  Command shell_cmd_fpga_bitstream("fpga_bitstream");
+  /* Add an option '--verbose' */
+  shell_cmd_fpga_bitstream.add_option("fabric_dependent", false, "Enable the bitstream construction for the FPGA fabric");
+  shell_cmd_fpga_bitstream.add_option("verbose", false, "Enable verbose output");
+  
+  /* Add command 'fpga_bitstream' to the Shell */
+  ShellCommandId shell_cmd_fpga_bitstream_id = shell.add_command(shell_cmd_fpga_bitstream, "Build bitstream database");
+  shell.set_command_class(shell_cmd_fpga_bitstream_id, openfpga_bitstream_cmd_class);
+  shell.set_command_execute_function(shell_cmd_fpga_bitstream_id, fpga_bitstream);
+
+  /* The 'fpga_bitstream' command should NOT be executed before 'repack' */
+  std::vector<ShellCommandId> cmd_dependency_fpga_bitstream;
+  cmd_dependency_fpga_bitstream.push_back(shell_cmd_repack_id);
+  shell.set_command_dependency(shell_cmd_fpga_bitstream_id, cmd_dependency_fpga_bitstream);
+
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_context.h b/openfpga/src/base/openfpga_context.h
index 5726cbba9..06c70cd24 100644
--- a/openfpga/src/base/openfpga_context.h
+++ b/openfpga/src/base/openfpga_context.h
@@ -11,6 +11,7 @@
 #include "tile_direct.h"
 #include "module_manager.h"
 #include "openfpga_flow_manager.h"
+#include "bitstream_manager.h"
 #include "device_rr_gsb.h"
 
 /********************************************************************
@@ -52,6 +53,7 @@ class OpenfpgaContext : public Context  {
     const openfpga::TileDirect& tile_direct() const { return tile_direct_; }
     const openfpga::ModuleManager& module_graph() const { return module_graph_; }
     const openfpga::FlowManager& flow_manager() const { return flow_manager_; }
+    const openfpga::BitstreamManager& bitstream_manager() const { return bitstream_manager_; }
   public:  /* Public mutators */
     openfpga::Arch& mutable_arch() { return arch_; }
     openfpga::VprDeviceAnnotation& mutable_vpr_device_annotation() { return vpr_device_annotation_; }
@@ -63,6 +65,7 @@ class OpenfpgaContext : public Context  {
     openfpga::TileDirect& mutable_tile_direct() { return tile_direct_; }
     openfpga::ModuleManager& mutable_module_graph() { return module_graph_; }
     openfpga::FlowManager& mutable_flow_manager() { return flow_manager_; }
+    openfpga::BitstreamManager& mutable_bitstream_manager() { return bitstream_manager_; }
   private: /* Internal data */
     /* Data structure to store information from read_openfpga_arch library */
     openfpga::Arch arch_;
@@ -90,6 +93,9 @@ class OpenfpgaContext : public Context  {
 
     /* Fabric module graph */
     openfpga::ModuleManager module_graph_;
+
+    /* Bitstream database */
+    openfpga::BitstreamManager bitstream_manager_;
  
     /* Flow status */
     openfpga::FlowManager flow_manager_;
diff --git a/openfpga/src/fpga_bitstream/bitstream_manager.cpp b/openfpga/src/fpga_bitstream/bitstream_manager.cpp
new file mode 100644
index 000000000..2a96b1113
--- /dev/null
+++ b/openfpga/src/fpga_bitstream/bitstream_manager.cpp
@@ -0,0 +1,187 @@
+/******************************************************************************
+ * This file includes member functions for data structure BitstreamManager 
+ ******************************************************************************/
+#include <algorithm>
+
+#include "vtr_assert.h"
+#include "bitstream_manager.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/**************************************************
+ * Public Accessors : Aggregates
+ *************************************************/
+/* Find all the configuration bits */
+BitstreamManager::config_bit_range BitstreamManager::bits() const {
+  return vtr::make_range(bit_ids_.begin(), bit_ids_.end());
+}
+
+/* Find all the configuration blocks */
+BitstreamManager::config_block_range BitstreamManager::blocks() const {
+  return vtr::make_range(block_ids_.begin(), block_ids_.end());
+}
+
+/******************************************************************************
+ * Public Accessors
+ ******************************************************************************/
+bool BitstreamManager::bit_value(const ConfigBitId& bit_id) const {
+  /* Ensure a valid id */
+  VTR_ASSERT(true == valid_bit_id(bit_id));
+
+  return bit_values_[bit_id];
+}
+
+std::string BitstreamManager::block_name(const ConfigBlockId& block_id) const {
+  /* Ensure the input ids are valid */
+  VTR_ASSERT(true == valid_block_id(block_id));
+
+  return block_names_[block_id];
+}
+
+ConfigBlockId BitstreamManager::block_parent(const ConfigBlockId& block_id) const {
+  /* Ensure the input ids are valid */
+  VTR_ASSERT(true == valid_block_id(block_id));
+
+  return parent_block_ids_[block_id];
+}
+
+std::vector<ConfigBlockId> BitstreamManager::block_children(const ConfigBlockId& block_id) const {
+  /* Ensure the input ids are valid */
+  VTR_ASSERT(true == valid_block_id(block_id));
+
+  return child_block_ids_[block_id];
+}
+
+std::vector<ConfigBitId> BitstreamManager::block_bits(const ConfigBlockId& block_id) const {
+  /* Ensure the input ids are valid */
+  VTR_ASSERT(true == valid_block_id(block_id));
+
+  return block_bit_ids_[block_id];
+}
+
+ConfigBlockId BitstreamManager::bit_parent_block(const ConfigBitId& bit_id) const {
+  /* Ensure the input ids are valid */
+  VTR_ASSERT(true == valid_bit_id(bit_id));
+
+  return bit_parent_block_ids_[bit_id];
+}
+
+size_t BitstreamManager::bit_index_in_parent_block(const ConfigBitId& bit_id) const {
+  /* Ensure the input ids are valid */
+  VTR_ASSERT(true == valid_bit_id(bit_id));
+
+  ConfigBlockId bit_parent_block = bit_parent_block_ids_[bit_id];
+
+  VTR_ASSERT(true == valid_block_id(bit_parent_block));
+
+  for (size_t index = 0; index < block_bits(bit_parent_block).size(); ++index) {
+    if (bit_id == block_bits(bit_parent_block)[index]) {
+      return index;
+    }
+  }
+
+  /* Not found, return in valid value */
+  return size_t(-1); 
+}
+
+/* Find the child block in a bitstream manager with a given name */
+ConfigBlockId BitstreamManager::find_child_block(const ConfigBlockId& block_id, 
+                                                 const std::string& child_block_name) const {
+  /* Ensure the input ids are valid */
+  VTR_ASSERT(true == valid_block_id(block_id));
+
+  std::vector<ConfigBlockId> candidates;
+
+  for (const ConfigBlockId& child : block_children(block_id)) {
+    if (0 == child_block_name.compare(block_name(child))) {
+      candidates.push_back(child);
+    }
+  }
+
+  /* We should have 0 or 1 candidate! */
+  VTR_ASSERT(0 == candidates.size() || 1 == candidates.size());
+  if (0 == candidates.size()) {
+    /* Not found, return an invalid value */
+    return ConfigBlockId::INVALID();
+  }
+  return candidates[0];
+}
+
+/******************************************************************************
+ * Public Mutators
+ ******************************************************************************/
+ConfigBitId BitstreamManager::add_bit(const bool& bit_value) {
+  ConfigBitId bit = ConfigBitId(bit_ids_.size());
+  /* Add a new bit, and allocate associated data structures */
+  bit_ids_.push_back(bit);
+  bit_values_.push_back(bit_value);
+  shared_config_bit_values_.emplace_back();
+  bit_parent_block_ids_.push_back(ConfigBlockId::INVALID());
+
+  return bit; 
+}
+
+ConfigBlockId BitstreamManager::add_block(const std::string& block_name) {
+  ConfigBlockId block = ConfigBlockId(block_ids_.size());
+  /* Add a new bit, and allocate associated data structures */
+  block_ids_.push_back(block);
+  block_names_.push_back(block_name);
+  block_bit_ids_.emplace_back();
+  parent_block_ids_.push_back(ConfigBlockId::INVALID());
+  child_block_ids_.emplace_back();
+
+  return block; 
+}
+
+void BitstreamManager::add_child_block(const ConfigBlockId& parent_block, const ConfigBlockId& child_block) {
+  /* Ensure the input ids are valid */
+  VTR_ASSERT(true == valid_block_id(parent_block));
+  VTR_ASSERT(true == valid_block_id(child_block));
+
+  /* We should have only a parent block for each block! */
+  VTR_ASSERT(ConfigBlockId::INVALID() == parent_block_ids_[child_block]);
+
+  /* Ensure the child block is not in the list of children of the parent block */
+  std::vector<ConfigBlockId>::iterator it = std::find(child_block_ids_[parent_block].begin(), child_block_ids_[parent_block].end(), child_block);
+  VTR_ASSERT(it == child_block_ids_[parent_block].end());
+
+  /* Add the child_block to the parent_block */
+  child_block_ids_[parent_block].push_back(child_block);
+  /* Register the block in the parent of the block */
+  parent_block_ids_[child_block] = parent_block;
+}
+
+void BitstreamManager::add_bit_to_block(const ConfigBlockId& block, const ConfigBitId& bit) {
+  /* Ensure the input ids are valid */
+  VTR_ASSERT(true == valid_block_id(block));
+  VTR_ASSERT(true == valid_bit_id(bit));
+
+  /* We should have only a parent block for each bit! */
+  VTR_ASSERT(ConfigBlockId::INVALID() == bit_parent_block_ids_[bit]);
+
+  /* Add the bit to the block */
+  block_bit_ids_[block].push_back(bit);
+  /* Register the block in the parent of the bit */
+  bit_parent_block_ids_[bit] = block;
+}
+
+void BitstreamManager::add_shared_config_bit_values(const ConfigBitId& bit, const std::vector<bool>& shared_config_bits) {
+  /* Ensure the input ids are valid */
+  VTR_ASSERT(true == valid_bit_id(bit));
+ 
+  shared_config_bit_values_[bit] = shared_config_bits;
+}
+
+/******************************************************************************
+ * Public Validators
+ ******************************************************************************/
+bool BitstreamManager::valid_bit_id(const ConfigBitId& bit_id) const {
+  return (size_t(bit_id) < bit_ids_.size()) && (bit_id == bit_ids_[bit_id]);
+}
+
+bool BitstreamManager::valid_block_id(const ConfigBlockId& block_id) const {
+  return (size_t(block_id) < block_ids_.size()) && (block_id == block_ids_[block_id]);
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_bitstream/bitstream_manager.h b/openfpga/src/fpga_bitstream/bitstream_manager.h
new file mode 100644
index 000000000..640b5a325
--- /dev/null
+++ b/openfpga/src/fpga_bitstream/bitstream_manager.h
@@ -0,0 +1,133 @@
+/******************************************************************************
+ * This file introduces a data structure to store bitstream-related information 
+ *
+ * General concept
+ * ---------------
+ * The idea is to create a unified data structure that stores all the configuration bits 
+ * with proper annotation to which modules in FPGA fabric it belongs to.
+ *   1. It can be easily organized in fabric-dependent representation 
+ *      (generate a sequence of bitstream which exactly fit the configuration protocol of FPGA fabric)
+ *   2. Or it can be easily organized in fabric-independent representation (think about XML file)
+ *
+ * Cross-reference 
+ * ---------------
+ * May be used only when you want to bind the bitstream to a specific FPGA fabric!
+ * If you do so, please make sure the block name is exactly same as the instance name
+ * of a child module in ModuleManager!!!
+ * The configurable modules/instances in module manager are arranged
+ * in the sequence to fit different configuration protocol. 
+ * By using the link between ModuleManager and BitstreamManager, 
+ * we can build a sequence of configuration bits to fit different configuration protocols.
+ *
+ *     +------------------+                                 +-----------------+
+ *     |                  |   block_name == instance_name   |                 |
+ *     | BitstreamManager |-------------------------------->|  ModuleManager  |
+ *     |                  |                                 |                 |
+ *     +------------------+                                 +-----------------+ 
+ *
+ * Restrictions:
+ * 1. Each block inside BitstreamManager should have only 1 parent block 
+ *    and multiple child block
+ * 2. Each bit inside BitstreamManager should have only 1 parent block 
+ * 
+ ******************************************************************************/
+#ifndef BITSTREAM_MANAGER_H
+#define BITSTREAM_MANAGER_H
+
+#include <vector>
+#include <map>
+#include "vtr_vector.h"
+
+#include "bitstream_manager_fwd.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+class BitstreamManager {
+  public: /* Types and ranges */
+    typedef vtr::vector<ConfigBitId, ConfigBitId>::const_iterator config_bit_iterator;
+    typedef vtr::vector<ConfigBlockId, ConfigBlockId>::const_iterator config_block_iterator;
+
+    typedef vtr::Range<config_bit_iterator> config_bit_range;
+    typedef vtr::Range<config_block_iterator> config_block_range;
+
+  public: /* Public aggregators */
+    /* Find all the configuration bits */
+    config_bit_range bits() const;
+
+    config_block_range blocks() const;
+
+  public:  /* Public Accessors */
+    /* Find the value of bitstream */
+    bool bit_value(const ConfigBitId& bit_id) const;
+
+    /* Find a name of a block */
+    std::string block_name(const ConfigBlockId& block_id) const;
+
+    /* Find the parent of a block */
+    ConfigBlockId block_parent(const ConfigBlockId& block_id) const;
+
+    /* Find the children of a block */
+    std::vector<ConfigBlockId> block_children(const ConfigBlockId& block_id) const;
+
+    /* Find all the bits that belong to a block */
+    std::vector<ConfigBitId> block_bits(const ConfigBlockId& block_id) const;
+
+    /* Find the parent block of a bit */
+    ConfigBlockId bit_parent_block(const ConfigBitId& bit_id) const;
+
+    /* Find the index of a configuration bit in its parent block */
+    size_t bit_index_in_parent_block(const ConfigBitId& bit_id) const; 
+
+    /* Find the child block in a bitstream manager with a given name */
+    ConfigBlockId find_child_block(const ConfigBlockId& block_id, const std::string& child_block_name) const;
+
+  public:  /* Public Mutators */
+    /* Add a new configuration bit to the bitstream manager */
+    ConfigBitId add_bit(const bool& bit_value);
+
+    /* Add a new block of configuration bits to the bitstream manager */
+    ConfigBlockId add_block(const std::string& block_name);
+
+    /* Set a block as a child block of another */
+    void add_child_block(const ConfigBlockId& parent_block, const ConfigBlockId& child_block);
+
+    /* Add a configuration bit to a block */
+    void add_bit_to_block(const ConfigBlockId& block, const ConfigBitId& bit);
+
+    /* Add share configuration bits to a configuration bit */
+    void add_shared_config_bit_values(const ConfigBitId& bit, const std::vector<bool>& shared_config_bits);
+
+  public:  /* Public Validators */
+    bool valid_bit_id(const ConfigBitId& bit_id) const;
+
+    bool valid_block_id(const ConfigBlockId& block_id) const;
+
+  private: /* Internal data */
+    /* Unique id of a block of bits in the Bitstream */
+    vtr::vector<ConfigBlockId, ConfigBlockId> block_ids_; 
+    vtr::vector<ConfigBlockId, std::vector<ConfigBitId>> block_bit_ids_; 
+
+    /* Back-annotation for the bits */
+    /* Parent block of a bit in the Bitstream 
+     * For each bit, the block name can be designed to be same as the instance name in a module
+     * to reflect its position in the module tree (ModuleManager)
+     * Note that the blocks here all unique, unlike ModuleManager where modules can be instanciated 
+     * Therefore, this block graph can be considered as a flattened graph of ModuleGraph
+     */
+    vtr::vector<ConfigBlockId, std::string> block_names_; 
+    vtr::vector<ConfigBlockId, ConfigBlockId> parent_block_ids_; 
+    vtr::vector<ConfigBlockId, std::vector<ConfigBlockId>> child_block_ids_; 
+
+    /* Unique id of a bit in the Bitstream */
+    vtr::vector<ConfigBitId, ConfigBitId> bit_ids_; 
+    vtr::vector<ConfigBitId, ConfigBlockId> bit_parent_block_ids_;
+    /* value of a bit in the Bitstream */
+    vtr::vector<ConfigBitId, bool> bit_values_;
+    /* value of a shared configuration bits in the Bitstream */
+    vtr::vector<ConfigBitId, std::vector<bool>> shared_config_bit_values_;
+};
+
+#endif
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_bitstream/bitstream_manager_fwd.h b/openfpga/src/fpga_bitstream/bitstream_manager_fwd.h
new file mode 100644
index 000000000..55a596633
--- /dev/null
+++ b/openfpga/src/fpga_bitstream/bitstream_manager_fwd.h
@@ -0,0 +1,25 @@
+/**************************************************
+ * This file includes only declarations for 
+ * the data structures for bitstream database
+ * Please refer to bitstream_manager.h for more details
+ *************************************************/
+#ifndef BITSTREAM_MANAGER_FWD_H
+#define BITSTREAM_MANAGER_FWD_H
+
+#include "vtr_strong_id.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/* Strong Ids for BitstreamContext */
+struct config_block_id_tag;
+struct config_bit_id_tag;
+
+typedef vtr::StrongId<config_block_id_tag> ConfigBlockId;
+typedef vtr::StrongId<config_bit_id_tag> ConfigBitId;
+
+class BitstreamManager;
+
+} /* end namespace openfpga */
+
+#endif 
diff --git a/openfpga/src/fpga_bitstream/bitstream_manager_utils.cpp b/openfpga/src/fpga_bitstream/bitstream_manager_utils.cpp
new file mode 100644
index 000000000..1225602ef
--- /dev/null
+++ b/openfpga/src/fpga_bitstream/bitstream_manager_utils.cpp
@@ -0,0 +1,58 @@
+/********************************************************************
+ * This file includes most utilized functions for data structure
+ * BitstreamManager
+ *
+ * Note: These functions are not generic enough so that they
+ *       should NOT be a member function! 
+ *******************************************************************/
+#include <algorithm>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+
+#include "bitstream_manager_utils.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Recursively find the hierarchy of a block of bitstream manager 
+ * Return a vector of the block ids, where the top-level block 
+ * locates in the head, while the leaf block locates in the tail 
+ *   top, next, ... , block
+ *******************************************************************/
+std::vector<ConfigBlockId> find_bitstream_manager_block_hierarchy(const BitstreamManager& bitstream_manager, 
+                                                                  const ConfigBlockId& block) {
+  std::vector<ConfigBlockId> block_hierarchy;
+  ConfigBlockId temp_block = block;
+
+  /* Generate a tree of parent block */
+  while (true == bitstream_manager.valid_block_id(temp_block)) {
+    block_hierarchy.push_back(temp_block);
+    /* Go to upper level */ 
+    temp_block = bitstream_manager.block_parent(temp_block);
+  }
+
+  /* Reverse the vector, so that top block stay in the first */
+  std::reverse(block_hierarchy.begin(), block_hierarchy.end());
+
+  return block_hierarchy;
+}
+
+/********************************************************************
+ * Find all the top-level blocks in a bitstream manager, 
+ * which have no parents
+ *******************************************************************/
+std::vector<ConfigBlockId> find_bitstream_manager_top_blocks(const BitstreamManager& bitstream_manager) {
+  std::vector<ConfigBlockId> top_blocks;
+  for (const ConfigBlockId& blk : bitstream_manager.blocks()) {
+    if (ConfigBlockId::INVALID() != bitstream_manager.block_parent(blk)) {
+      continue;
+    }
+    top_blocks.push_back(blk);
+  }
+
+  return top_blocks;
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_bitstream/bitstream_manager_utils.h b/openfpga/src/fpga_bitstream/bitstream_manager_utils.h
new file mode 100644
index 000000000..4c8b26ad2
--- /dev/null
+++ b/openfpga/src/fpga_bitstream/bitstream_manager_utils.h
@@ -0,0 +1,24 @@
+#ifndef BITSTREAM_MANAGER_UTILS_H
+#define BITSTREAM_MANAGER_UTILS_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <vector>
+#include "bitstream_manager.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+std::vector<ConfigBlockId> find_bitstream_manager_block_hierarchy(const BitstreamManager& bitstream_manager, 
+                                                                  const ConfigBlockId& block);
+
+std::vector<ConfigBlockId> find_bitstream_manager_top_blocks(const BitstreamManager& bitstream_manager);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/fpga_bitstream/build_device_bitstream.cpp b/openfpga/src/fpga_bitstream/build_device_bitstream.cpp
new file mode 100644
index 000000000..997c83fb6
--- /dev/null
+++ b/openfpga/src/fpga_bitstream/build_device_bitstream.cpp
@@ -0,0 +1,69 @@
+/********************************************************************
+ * This file includes functions to build bitstream from a mapped
+ * FPGA fabric.
+ * We decode the bitstream from configuration of routing multiplexers 
+ * and Look-Up Tables (LUTs) which locate in CLBs and global routing architecture
+ *******************************************************************/
+#include <vector>
+
+/* Headers from vtrutil library */
+#include "vtr_log.h"
+#include "vtr_assert.h"
+#include "vtr_time.h"
+
+#include "openfpga_naming.h"
+
+//#include "build_grid_bitstream.h"
+//#include "build_routing_bitstream.h"
+#include "build_device_bitstream.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * A top-level function to build a bistream from the FPGA device
+ * 1. It will organize the bitstream w.r.t. the hierarchy of module graphs 
+ *    describing the FPGA fabric
+ * 2. It will decode configuration bits from routing multiplexers used in 
+ *    global routing architecture
+ * 3. It will decode configuration bits from routing multiplexers and LUTs
+ *    used in CLBs
+ *
+ * Note: this function create a bitstream which is binding to the module graphs
+ * of the FPGA fabric that FPGA-X2P generates!
+ * But it can be used to output a generic bitstream for VPR mapping FPGA
+ *******************************************************************/
+BitstreamManager build_device_bitstream(const VprContext& vpr_ctx,
+                                        const OpenfpgaContext& openfpga_ctx,
+                                        const bool& verbose) {
+
+  std::string timer_message = std::string("\nBuild fabric-independent bitstream for implementation '") + vpr_ctx.atom().nlist.netlist_name() + std::string("'\n");
+  vtr::ScopedStartFinishTimer timer(timer_message);
+
+  /* Bitstream manager to be built */
+  BitstreamManager bitstream_manager;
+
+  /* Assign the SRAM model applied to the FPGA fabric */
+  CircuitModelId sram_model = openfpga_ctx.arch().config_protocol.memory_model();  
+  VTR_ASSERT(true == openfpga_ctx.arch().circuit_lib.valid_model_id(sram_model));
+
+  /* Create the top-level block for bitstream 
+   * This is related to the top-level module of fpga  
+   */
+  std::string top_block_name = generate_fpga_top_module_name();
+  ConfigBlockId top_block = bitstream_manager.add_block(top_block_name);
+
+  /* Create bitstream from grids */
+  VTR_LOGV(verbose, "Building grid bitstream...\n");
+  //build_grid_bitstream(bitstream_manager, top_block, module_manager, circuit_lib, mux_lib, device_size, grids);
+  VTR_LOGV(verbose, "Done\n");
+
+  /* Create bitstream from routing architectures */
+  VTR_LOGV(verbose, "Building routing bitstream...\n");
+  //build_routing_bitstream(bitstream_manager, top_block, module_manager, circuit_lib, mux_lib, rr_switches, L_rr_node, L_device_rr_gsb);
+  VTR_LOGV(verbose, "Done\n");
+
+  return bitstream_manager;
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_bitstream/build_device_bitstream.h b/openfpga/src/fpga_bitstream/build_device_bitstream.h
new file mode 100644
index 000000000..3926f2733
--- /dev/null
+++ b/openfpga/src/fpga_bitstream/build_device_bitstream.h
@@ -0,0 +1,24 @@
+#ifndef BUILD_DEVICE_BITSTREAM_H
+#define BUILD_DEVICE_BITSTREAM_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <vector>
+#include "vpr_context.h"
+#include "openfpga_context.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+BitstreamManager build_device_bitstream(const VprContext& vpr_ctx,
+                                        const OpenfpgaContext& openfpga_ctx,
+                                        const bool& verbose);
+
+} /* end namespace openfpga */
+
+#endif

From 51439ba3b4af63a19772d1a61c356c612f1339f1 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 23 Feb 2020 20:40:18 -0700
Subject: [PATCH 198/645] add bitstream writer to be integrated

---
 .../src/fpga_bitstream/bitstream_manager.h    |   4 +-
 .../src/fpga_bitstream/bitstream_writer.cpp   | 140 ++++++++++++++++++
 .../src/fpga_bitstream/bitstream_writer.h     |  22 +++
 openfpga/test_script/s298_k6_frac.openfpga    |   5 +-
 4 files changed, 168 insertions(+), 3 deletions(-)
 create mode 100644 openfpga/src/fpga_bitstream/bitstream_writer.cpp
 create mode 100644 openfpga/src/fpga_bitstream/bitstream_writer.h

diff --git a/openfpga/src/fpga_bitstream/bitstream_manager.h b/openfpga/src/fpga_bitstream/bitstream_manager.h
index 640b5a325..58a2af8ee 100644
--- a/openfpga/src/fpga_bitstream/bitstream_manager.h
+++ b/openfpga/src/fpga_bitstream/bitstream_manager.h
@@ -128,6 +128,6 @@ class BitstreamManager {
     vtr::vector<ConfigBitId, std::vector<bool>> shared_config_bit_values_;
 };
 
-#endif
-
 } /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/fpga_bitstream/bitstream_writer.cpp b/openfpga/src/fpga_bitstream/bitstream_writer.cpp
new file mode 100644
index 000000000..f19e3819f
--- /dev/null
+++ b/openfpga/src/fpga_bitstream/bitstream_writer.cpp
@@ -0,0 +1,140 @@
+/********************************************************************
+ * This file includes functions that output bitstream database
+ * to files in different formats
+ *******************************************************************/
+#include <chrono>
+#include <ctime>
+#include <fstream>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+#include "vtr_time.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_digest.h"
+
+#include "openfpga_naming.h"
+
+#include "bitstream_manager_utils.h"
+#include "bitstream_writer.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * This function write header information to a bitstream file
+ *******************************************************************/
+static 
+void write_bitstream_xml_file_head(std::fstream& fp) {
+  valid_file_stream(fp);
+ 
+  auto end = std::chrono::system_clock::now(); 
+  std::time_t end_time = std::chrono::system_clock::to_time_t(end);
+
+  fp << "<!--" << std::endl;
+  fp << "\t- Architecture independent bitstream" << std::endl;
+  fp << "\t- Author: Xifan TANG" << std::endl;
+  fp << "\t- Organization: University of Utah" << std::endl;
+  fp << "\t- Date: " << std::ctime(&end_time) ;
+  fp << "-->" << std::endl;
+  fp << std::endl;
+}
+
+/********************************************************************
+ * Recursively write the bitstream of a block to a xml file
+ * This function will use a Depth-First Search in outputting bitstream
+ * for each block 
+ * 1. For block with bits as children, we will output the XML lines
+ * 2. For block without bits/child blocks, we can return 
+ * 3. For block with child blocks, we visit each child recursively
+ *******************************************************************/
+static 
+void rec_write_block_bitstream_to_xml_file(std::fstream& fp,
+                                           const BitstreamManager& bitstream_manager, 
+                                           const ConfigBlockId& block) {
+  valid_file_stream(fp);
+
+  /* Dive to child blocks if this block has any */
+  for (const ConfigBlockId& child_block : bitstream_manager.block_children(block)) {
+    rec_write_block_bitstream_to_xml_file(fp, bitstream_manager, child_block);
+  }
+  
+  if (0 == bitstream_manager.block_bits(block).size()) {
+    return;
+  }
+
+  /* Write the bits of this block */
+  fp << "<bitstream_block index=\"" << size_t(block) << "\">" << std::endl;
+
+  std::vector<ConfigBlockId> block_hierarchy = find_bitstream_manager_block_hierarchy(bitstream_manager, block); 
+  
+  /* Output hierarchy of this parent*/
+  fp << "\t<hierarchy>" << std::endl;
+  size_t hierarchy_counter = 0;
+  for (const ConfigBlockId& temp_block : block_hierarchy) {
+    fp << "\t\t<instance level=\"" << hierarchy_counter << "\"";
+    fp << " name=\"" << bitstream_manager.block_name(temp_block) << "\"";
+    fp << "/>" << std::endl;
+    hierarchy_counter++;
+  }
+  fp << "\t</hierarchy>" << std::endl;
+
+  /* Output child bits under this block */
+  size_t bit_counter = 0;
+  fp << "\t<bitstream>" << std::endl;
+  for (const ConfigBitId& child_bit : bitstream_manager.block_bits(block)) {
+    fp << "\t\t<bit";
+    fp << " memory_port=\"" << generate_configuration_chain_data_out_name() << "[" << bit_counter << "]" << "\"";
+    fp << " value=\"" << bitstream_manager.bit_value(child_bit) << "\"";
+    fp << "/>" << std::endl;
+    bit_counter++;
+  }
+  fp << "\t</bitstream>" << std::endl;
+
+  fp << "</bitstream_block>" <<std::endl;
+}
+
+/********************************************************************
+ * Write the bitstream to a file without binding to the configuration 
+ * procotols of a given FPGA fabric in XML format
+ *
+ * Notes: 
+ * This is a very generic representation for bitstream that are implemented
+ * by VPR engine. It shows the bitstream for each blocks in the FPGA 
+ * architecture that users are modeling.
+ * This function can be used to: 
+ * 1. Debug the bitstream decoding to see if there is any bug
+ * 2. Create an intermediate file to reorganize a bitstream for 
+ *    specific FPGAs
+ * 3. TODO: support FASM format 
+ *******************************************************************/
+void write_arch_independent_bitstream_to_xml_file(const BitstreamManager& bitstream_manager,
+                                                  const std::string& fname) {
+  std::string timer_message = std::string("Writing ") + std::to_string(bitstream_manager.bits().size()) + std::string(" architecture independent bitstream into XML file '") + fname + std::string("'\n");
+  vtr::ScopedStartFinishTimer timer(timer_message);
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(fname, std::fstream::out | std::fstream::trunc);
+
+  check_file_stream(fname.c_str(), fp);
+
+  /* Put down a brief introduction */
+  write_bitstream_xml_file_head(fp);
+
+  std::string top_block_name = generate_fpga_top_module_name();
+  /* Find the top block, which has not parents */
+  std::vector<ConfigBlockId> top_block = find_bitstream_manager_top_blocks(bitstream_manager);
+  /* Make sure we have only 1 top block and its name matches the top module */
+  VTR_ASSERT(1 == top_block.size());
+  VTR_ASSERT(0 == top_block_name.compare(bitstream_manager.block_name(top_block[0])));
+
+  /* Write bitstream, block by block, in a recursive way */
+  rec_write_block_bitstream_to_xml_file(fp, bitstream_manager, top_block[0]);
+
+  /* Close file handler */
+  fp.close();
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_bitstream/bitstream_writer.h b/openfpga/src/fpga_bitstream/bitstream_writer.h
new file mode 100644
index 000000000..338bfde35
--- /dev/null
+++ b/openfpga/src/fpga_bitstream/bitstream_writer.h
@@ -0,0 +1,22 @@
+#ifndef BITSTREAM_WRITER_H
+#define BITSTREAM_WRITER_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <string>
+#include "bitstream_manager.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void write_arch_independent_bitstream_to_xml_file(const BitstreamManager& bitstream_manager,
+                                                  const std::string& fname);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/test_script/s298_k6_frac.openfpga b/openfpga/test_script/s298_k6_frac.openfpga
index a985511c4..490284fe4 100644
--- a/openfpga/test_script/s298_k6_frac.openfpga
+++ b/openfpga/test_script/s298_k6_frac.openfpga
@@ -8,7 +8,7 @@ read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
 #write_openfpga_arch -f ./arch_echo.xml
 
 # Annotate the OpenFPGA architecture to VPR data base
-link_openfpga_arch --verbose
+link_openfpga_arch #--verbose
 
 # Check and correct any naming conflicts in the BLIF netlist
 check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
@@ -29,6 +29,9 @@ build_fabric --compress_routing --duplicate_grid_pin #--verbose
 # Strongly recommend it is done after all the fix-up have been applied
 repack --verbose
 
+# Build the bitstream 
+fpga_bitstream --verbose
+
 # Write the Verilog netlit for FPGA fabric
 #  - Enable the use of explicit port mapping in Verilog netlist
 write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose

From 8723007f6855163060bc519ea62f8fe70f131eb8 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 23 Feb 2020 20:53:24 -0700
Subject: [PATCH 199/645] Bring mux bitstream generation online

---
 .../fpga_bitstream/build_mux_bitstream.cpp    | 178 ++++++++++++++++++
 .../src/fpga_bitstream/build_mux_bitstream.h  |  30 +++
 2 files changed, 208 insertions(+)
 create mode 100644 openfpga/src/fpga_bitstream/build_mux_bitstream.cpp
 create mode 100644 openfpga/src/fpga_bitstream/build_mux_bitstream.h

diff --git a/openfpga/src/fpga_bitstream/build_mux_bitstream.cpp b/openfpga/src/fpga_bitstream/build_mux_bitstream.cpp
new file mode 100644
index 000000000..3b7e06354
--- /dev/null
+++ b/openfpga/src/fpga_bitstream/build_mux_bitstream.cpp
@@ -0,0 +1,178 @@
+/********************************************************************
+ * This file includes functions to build bitstream from routing multiplexers
+ * which are based on different technology
+ *******************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_log.h"
+#include "vtr_assert.h"
+#include "vtr_vector.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_decode.h"
+
+#include "mux_utils.h"
+#include "decoder_library_utils.h"
+
+#include "build_mux_bitstream.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/* Default path ID of a unused multiplexer */
+#define DEFAULT_PATH_ID -1
+
+/* Default path ID of a unused multiplexer when there are no constant inputs*/
+#define DEFAULT_MUX_PATH_ID 0
+
+/********************************************************************
+ * Find the default path id of a MUX
+ * This is applied when the path id specified is DEFAULT_PATH_ID,
+ * which is not correlated to the MUX implementation 
+ * This function is binding the default path id to the implemented structure
+ * 1. If the MUX has a constant input, the default path id will be 
+ *    directed to the last input of the MUX, which is the constant input
+ * 2. If the MUX does not have a constant input, the default path id 
+ *    will the first input of the MUX.
+ *
+ * Restriction:
+ *   we assume the default path is the first input of the MUX
+ *   Change if this is not what you want
+ *******************************************************************/
+size_t find_mux_default_path_id(const CircuitLibrary& circuit_lib,
+                                const CircuitModelId& mux_model,
+                                const size_t& mux_size) {
+  size_t default_path_id;
+
+  if (true == circuit_lib.mux_add_const_input(mux_model)) {
+    default_path_id = mux_size - 1; /* When there is a constant input, use the last path */
+  } else {
+    default_path_id = DEFAULT_MUX_PATH_ID; /* When there is no constant input, use the default one */
+  }
+
+  return default_path_id; 
+}
+
+/********************************************************************
+ * This function generates bitstream for a CMOS routing multiplexer
+ * Thanks to MuxGraph object has already describe the internal multiplexing 
+ * structure, bitstream generation is simply done by routing the signal
+ * to from a given input to the output
+ * All the memory bits can be generated by an API of MuxGraph
+ *
+ * To be generic, this function only returns a vector bit values
+ * without touching an bitstream-relate data structure
+ *******************************************************************/
+static 
+std::vector<bool> build_cmos_mux_bitstream(const CircuitLibrary& circuit_lib,
+                                           const CircuitModelId& mux_model,
+                                           const MuxLibrary& mux_lib,
+                                           const size_t& mux_size,
+                                           const int& path_id) {
+  /* Note that the size of implemented mux could be different than the mux size we see here,
+   * due to the constant inputs 
+   * We will find the input size of implemented MUX and fetch the graph-based representation in MUX library 
+   */
+  size_t implemented_mux_size = find_mux_implementation_num_inputs(circuit_lib, mux_model, mux_size);
+  /* Note that the mux graph is indexed using datapath MUX size!!!! */
+  MuxId mux_graph_id = mux_lib.mux_graph(mux_model, mux_size);
+  const MuxGraph mux_graph = mux_lib.mux_graph(mux_graph_id);
+
+  size_t datapath_id = path_id;
+
+  /* Find the path_id related to the implementation */
+  if (DEFAULT_PATH_ID == path_id) {
+    datapath_id = find_mux_default_path_id(circuit_lib, mux_model, implemented_mux_size);
+  } else { 
+    VTR_ASSERT( datapath_id < mux_size);
+  }
+  /* Path id should makes sense */
+  VTR_ASSERT(datapath_id < mux_graph.inputs().size());
+  /* We should have only one output for this MUX! */
+  VTR_ASSERT(1 == mux_graph.outputs().size());
+
+  /* Generate the memory bits */
+  vtr::vector<MuxMemId, bool> raw_bitstream = mux_graph.decode_memory_bits(MuxInputId(datapath_id), mux_graph.output_id(mux_graph.outputs()[0]));
+
+  std::vector<bool> mux_bitstream;
+  for (const bool& bit : raw_bitstream) {
+    mux_bitstream.push_back(bit);
+  }
+
+  /* Consider local encoder support, we need further encode the bitstream */
+  if (false == circuit_lib.mux_use_local_encoder(mux_model)) {
+    return mux_bitstream;
+  }
+
+  /* Clear the mux_bitstream, we need to apply encoding */
+  mux_bitstream.clear();
+
+  /* Encode the memory bits level by level,
+   * One local encoder is used for each level of multiplexers 
+   */
+  for (const size_t& level : mux_graph.levels()) {
+    /* The encoder will convert the path_id to a binary number 
+     * For example: when path_id=3 (use the 4th input), using a 2-input encoder 
+     * the sram_bits will be the 2-digit binary number of 3: 10
+     */
+    std::vector<size_t> encoder_data;
+
+    /* Exception: there is only 1 memory at this level, bitstream will not be changed!!! */
+    if (1 == mux_graph.memories_at_level(level).size()) {
+      mux_bitstream.push_back(raw_bitstream[mux_graph.memories_at_level(level)[0]]);
+      continue;
+    }
+
+    /* Otherwise: we follow a regular recipe */
+    for (size_t mem_index = 0; mem_index < mux_graph.memories_at_level(level).size(); ++mem_index) {
+      /* Conversion rule: true = 1, false = 0 */
+      if (true == raw_bitstream[mux_graph.memories_at_level(level)[mem_index]]) {
+        encoder_data.push_back(mem_index);
+      } 
+    }
+    /* There should be at most one '1' */
+    VTR_ASSERT( (0 == encoder_data.size()) || (1 == encoder_data.size()));
+    /* Convert to encoded bits */
+    std::vector<size_t> encoder_addr;
+    if (0 == encoder_data.size()) { 
+      encoder_addr = itobin_vec(0, find_mux_local_decoder_addr_size(mux_graph.memories_at_level(level).size()));
+    } else {
+      VTR_ASSERT(1 == encoder_data.size());
+      encoder_addr = itobin_vec(encoder_data[0], find_mux_local_decoder_addr_size(mux_graph.memories_at_level(level).size()));
+    }
+    /* Build final mux bitstream */
+    for (const size_t& bit : encoder_addr) {
+      mux_bitstream.push_back(1 == bit);
+    }
+  } 
+
+  return mux_bitstream;
+}
+
+/********************************************************************
+ * This function generates bitstream for a routing multiplexer
+ * supporting both CMOS and ReRAM multiplexer designs 
+ *******************************************************************/
+std::vector<bool> build_mux_bitstream(const CircuitLibrary& circuit_lib,
+                                      const CircuitModelId& mux_model,
+                                      const MuxLibrary& mux_lib,
+                                      const size_t& mux_size,
+                                      const int& path_id) {
+  std::vector<bool> mux_bitstream;
+
+  switch (circuit_lib.design_tech_type(mux_model)) {
+  case CIRCUIT_MODEL_DESIGN_CMOS:
+    mux_bitstream = build_cmos_mux_bitstream(circuit_lib, mux_model, mux_lib, mux_size, path_id);
+    break;
+  case CIRCUIT_MODEL_DESIGN_RRAM:
+    /* TODO: ReRAM MUX needs a different bitstream generation strategy */
+    break;
+  default:
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid design technology for circuit model '%s'!\n",
+                   circuit_lib.model_name(mux_model).c_str());
+    exit(1);
+  }
+  return mux_bitstream;
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_bitstream/build_mux_bitstream.h b/openfpga/src/fpga_bitstream/build_mux_bitstream.h
new file mode 100644
index 000000000..639e086bc
--- /dev/null
+++ b/openfpga/src/fpga_bitstream/build_mux_bitstream.h
@@ -0,0 +1,30 @@
+#ifndef BUILD_MUX_BITSTREAM_H
+#define BUILD_MUX_BITSTREAM_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <vector>
+#include "circuit_library.h"
+#include "mux_library.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+size_t find_mux_default_path_id(const CircuitLibrary& circuit_lib,
+                                const CircuitModelId& mux_model,
+                                const size_t& mux_size);
+
+std::vector<bool> build_mux_bitstream(const CircuitLibrary& circuit_lib,
+                                      const CircuitModelId& mux_model,
+                                      const MuxLibrary& mux_lib,
+                                      const size_t& mux_size,
+                                      const int& path_id);
+
+} /* end namespace openfpga */
+
+#endif

From 86c7c24701816ac888d754e0d050bd0b40412b23 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 23 Feb 2020 20:58:17 -0700
Subject: [PATCH 200/645] add fabric bitstream generation online

---
 .../fpga_bitstream/build_fabric_bitstream.cpp | 131 ++++++++++++++++++
 .../fpga_bitstream/build_fabric_bitstream.h   |  23 +++
 2 files changed, 154 insertions(+)
 create mode 100644 openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp
 create mode 100644 openfpga/src/fpga_bitstream/build_fabric_bitstream.h

diff --git a/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp b/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp
new file mode 100644
index 000000000..241aee04d
--- /dev/null
+++ b/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp
@@ -0,0 +1,131 @@
+/********************************************************************
+ * This file includes functions to build fabric dependent bitstream
+ *******************************************************************/
+#include <string>
+#include <algorithm>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+#include "vtr_time.h"
+
+#include "openfpga_naming.h"
+
+#include "bitstream_manager_utils.h"
+#include "build_fabric_bitstream.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * This function will walk through all the configurable children under a module
+ * in a recursive way, following a Depth-First Search (DFS) strategy
+ * For each configuration child, we use its instance name as a key to spot the 
+ * configuration bits in bitstream manager.
+ * Note that it is guarentee that the instance name in module manager is 
+ * consistent with the block names in bitstream manager
+ * We use this link to reorganize the bitstream in the sequence of memories as we stored
+ * in the configurable_children) and configurable_child_instances() of each module of module manager 
+ *******************************************************************/
+static 
+void rec_build_module_fabric_dependent_bitstream(const BitstreamManager& bitstream_manager,
+                                                 const ConfigBlockId& parent_block,
+                                                 const ModuleManager& module_manager,
+                                                 const ModuleId& parent_module,
+                                                 std::vector<ConfigBitId>& fabric_bitstream) {
+
+  /* Depth-first search: if we have any children in the parent_block, 
+   * we dive to the next level first! 
+   */
+  if (0 < bitstream_manager.block_children(parent_block).size()) {
+    for (size_t child_id = 0; child_id < module_manager.configurable_children(parent_module).size(); ++child_id) {
+      ModuleId child_module = module_manager.configurable_children(parent_module)[child_id]; 
+      size_t child_instance = module_manager.configurable_child_instances(parent_module)[child_id]; 
+      /* Get the instance name and ensure it is not empty */
+      std::string instance_name = module_manager.instance_name(parent_module, child_module, child_instance);
+       
+      /* Find the child block that matches the instance name! */ 
+      ConfigBlockId child_block = bitstream_manager.find_child_block(parent_block, instance_name); 
+      /* We must have one valid block id! */
+      if (true != bitstream_manager.valid_block_id(child_block))
+      VTR_ASSERT(true == bitstream_manager.valid_block_id(child_block));
+
+      /* Go recursively */
+      rec_build_module_fabric_dependent_bitstream(bitstream_manager, child_block,
+                                                  module_manager, child_module,
+                                                  fabric_bitstream);
+    }
+    /* Ensure that there should be no configuration bits in the parent block */
+    VTR_ASSERT(0 == bitstream_manager.block_bits(parent_block).size());
+  }
+
+  /* Note that, reach here, it means that this is a leaf node. 
+   * We add the configuration bits to the fabric_bitstream,
+   * And then, we can return
+   */
+  for (const ConfigBitId& config_bit : bitstream_manager.block_bits(parent_block)) {
+    fabric_bitstream.push_back(config_bit);
+  }
+}
+
+/********************************************************************
+ * A top-level function re-organizes the bitstream for a specific 
+ * FPGA fabric, where configuration bits are organized in the sequence
+ * that can be directly loaded to the FPGA configuration protocol.
+ * Support:
+ * 1. Configuration chain
+ * 2. Memory decoders
+ * This function does NOT modify the bitstream database
+ * Instead, it builds a vector of ids for configuration bits in bitstream manager
+ *
+ * This function can be called ONLY after the function build_device_bitstream() 
+ * Note that this function does NOT decode bitstreams from circuit implementation
+ * It was done in the function build_device_bitstream() 
+ *******************************************************************/
+std::vector<ConfigBitId> build_fabric_dependent_bitstream(const BitstreamManager& bitstream_manager,
+                                                          const ModuleManager& module_manager) {
+  std::vector<ConfigBitId> fabric_bitstream; 
+
+  vtr::ScopedStartFinishTimer timer("\nBuild fabric dependent bitstream\n");
+
+  /* Get the top module name in module manager, which is our starting point */
+  std::string top_module_name = generate_fpga_top_module_name();
+  ModuleId top_module = module_manager.find_module(top_module_name);
+  VTR_ASSERT(true == module_manager.valid_module_id(top_module));
+
+  /* Find the top block in bitstream manager, which has not parents */
+  std::vector<ConfigBlockId> top_block = find_bitstream_manager_top_blocks(bitstream_manager);
+  /* Make sure we have only 1 top block and its name matches the top module */
+  VTR_ASSERT(1 == top_block.size());
+  VTR_ASSERT(0 == top_module_name.compare(bitstream_manager.block_name(top_block[0])));
+
+  rec_build_module_fabric_dependent_bitstream(bitstream_manager, top_block[0],
+                                              module_manager, top_module, 
+                                              fabric_bitstream);
+
+  /* Time-consuming sanity check: Uncomment these codes only for debugging!!!
+   * Check which configuration bits are not touched 
+   */
+  /*
+  for (const ConfigBitId& config_bit : bitstream_manager.bits()) {
+    std::vector<ConfigBitId>::iterator it = std::find(fabric_bitstream.begin(), fabric_bitstream.end(), config_bit);
+    if (it == fabric_bitstream.end()) {
+      std::vector<ConfigBlockId> block_hierarchy = find_bitstream_manager_block_hierarchy(bitstream_manager, bitstream_manager.bit_parent_block(config_bit)); 
+      std::string block_hierarchy_name;
+      for (const ConfigBlockId& temp_block : block_hierarchy) {
+        block_hierarchy_name += std::string("/") + bitstream_manager.block_name(temp_block);
+      }
+      vpr_printf(TIO_MESSAGE_INFO, 
+                 "bit (parent_block = %s) is not touched!\n", 
+                 block_hierarchy_name.c_str());
+    }
+  }
+   */
+
+  /* Ensure our fabric bitstream is in the same size as device bistream */
+  VTR_ASSERT(bitstream_manager.bits().size() == fabric_bitstream.size());
+
+  return fabric_bitstream;
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_bitstream/build_fabric_bitstream.h b/openfpga/src/fpga_bitstream/build_fabric_bitstream.h
new file mode 100644
index 000000000..47d46084c
--- /dev/null
+++ b/openfpga/src/fpga_bitstream/build_fabric_bitstream.h
@@ -0,0 +1,23 @@
+#ifndef BUILD_FABRIC_BITSTREAM_H
+#define BUILD_FABRIC_BITSTREAM_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <vector>
+#include "bitstream_manager.h"
+#include "module_manager.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+std::vector<ConfigBitId> build_fabric_dependent_bitstream(const BitstreamManager& bitstream_manager,
+                                                          const ModuleManager& module_manager);
+
+} /* end namespace openfpga */
+
+#endif

From 712eeb13402bdf163ad0952e9ed898aff0bdb732 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 23 Feb 2020 22:09:46 -0700
Subject: [PATCH 201/645] bring bitstream generator for routing modules online

---
 .../fpga_bitstream/build_device_bitstream.cpp |  13 +-
 .../fpga_bitstream/build_mux_bitstream.cpp    |   7 +-
 .../build_routing_bitstream.cpp               | 442 ++++++++++++++++++
 .../fpga_bitstream/build_routing_bitstream.h  |  39 ++
 .../fpga_bitstream/mux_bitstream_constants.h  |  15 +
 5 files changed, 508 insertions(+), 8 deletions(-)
 create mode 100644 openfpga/src/fpga_bitstream/build_routing_bitstream.cpp
 create mode 100644 openfpga/src/fpga_bitstream/build_routing_bitstream.h
 create mode 100644 openfpga/src/fpga_bitstream/mux_bitstream_constants.h

diff --git a/openfpga/src/fpga_bitstream/build_device_bitstream.cpp b/openfpga/src/fpga_bitstream/build_device_bitstream.cpp
index 997c83fb6..0b6d01d39 100644
--- a/openfpga/src/fpga_bitstream/build_device_bitstream.cpp
+++ b/openfpga/src/fpga_bitstream/build_device_bitstream.cpp
@@ -14,7 +14,7 @@
 #include "openfpga_naming.h"
 
 //#include "build_grid_bitstream.h"
-//#include "build_routing_bitstream.h"
+#include "build_routing_bitstream.h"
 #include "build_device_bitstream.h"
 
 /* begin namespace openfpga */
@@ -60,9 +60,18 @@ BitstreamManager build_device_bitstream(const VprContext& vpr_ctx,
 
   /* Create bitstream from routing architectures */
   VTR_LOGV(verbose, "Building routing bitstream...\n");
-  //build_routing_bitstream(bitstream_manager, top_block, module_manager, circuit_lib, mux_lib, rr_switches, L_rr_node, L_device_rr_gsb);
+  build_routing_bitstream(bitstream_manager, top_block, 
+                          openfpga_ctx.module_graph(),
+                          openfpga_ctx.arch().circuit_lib,
+                          openfpga_ctx.mux_lib(),
+                          openfpga_ctx.vpr_device_annotation(),
+                          openfpga_ctx.vpr_routing_annotation(),
+                          vpr_ctx.device().rr_graph,
+                          openfpga_ctx.device_rr_gsb());
   VTR_LOGV(verbose, "Done\n");
 
+  VTR_LOGV(verbose, "Decoded %lu configuration bits\n", bitstream_manager.bits().size());
+
   return bitstream_manager;
 }
 
diff --git a/openfpga/src/fpga_bitstream/build_mux_bitstream.cpp b/openfpga/src/fpga_bitstream/build_mux_bitstream.cpp
index 3b7e06354..5de0e3d0e 100644
--- a/openfpga/src/fpga_bitstream/build_mux_bitstream.cpp
+++ b/openfpga/src/fpga_bitstream/build_mux_bitstream.cpp
@@ -13,17 +13,12 @@
 #include "mux_utils.h"
 #include "decoder_library_utils.h"
 
+#include "mux_bitstream_constants.h"
 #include "build_mux_bitstream.h"
 
 /* begin namespace openfpga */
 namespace openfpga {
 
-/* Default path ID of a unused multiplexer */
-#define DEFAULT_PATH_ID -1
-
-/* Default path ID of a unused multiplexer when there are no constant inputs*/
-#define DEFAULT_MUX_PATH_ID 0
-
 /********************************************************************
  * Find the default path id of a MUX
  * This is applied when the path id specified is DEFAULT_PATH_ID,
diff --git a/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp b/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp
new file mode 100644
index 000000000..e0dd75c2a
--- /dev/null
+++ b/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp
@@ -0,0 +1,442 @@
+/********************************************************************
+ * This file includes functions to build bitstream from global routing
+ * architecture of a mapped FPGA fabric
+ * We decode the bitstream from configuration of routing multiplexers 
+ * which locate in global routing architecture
+ *******************************************************************/
+#include <vector>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_side_manager.h"
+
+#include "mux_utils.h"
+#include "rr_gsb_utils.h"
+#include "openfpga_reserved_words.h"
+#include "openfpga_naming.h"
+#include "openfpga_rr_graph_utils.h"
+
+#include "mux_bitstream_constants.h"
+#include "build_mux_bitstream.h"
+#include "build_routing_bitstream.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * This function generates bitstream for a routing multiplexer
+ * This function will identify if a node indicates a routing multiplexer
+ * If not a routing multiplexer, no bitstream is needed here
+ * If yes, we will generate the bitstream for the routing multiplexer
+ *******************************************************************/
+static 
+void build_switch_block_mux_bitstream(BitstreamManager& bitstream_manager,
+                                      const ConfigBlockId& mux_mem_block,
+                                      const ModuleManager& module_manager,
+                                      const CircuitLibrary& circuit_lib,
+                                      const MuxLibrary& mux_lib,
+                                      const RRGraph& rr_graph,
+                                      const RRNodeId& cur_rr_node,
+                                      const std::vector<RRNodeId>& drive_rr_nodes,
+                                      const VprDeviceAnnotation& device_annotation,
+                                      const VprRoutingAnnotation& routing_annotation) {
+  /* Check current rr_node is CHANX or CHANY*/
+  VTR_ASSERT( (CHANX == rr_graph.node_type(cur_rr_node))
+           || (CHANY == rr_graph.node_type(cur_rr_node)));
+  
+  /* Find the input size of the implementation of a routing multiplexer */
+  size_t datapath_mux_size = drive_rr_nodes.size();
+
+  /* Find out which routing path is used in this MUX */
+  int path_id = DEFAULT_PATH_ID;
+  for (size_t inode = 0; inode < drive_rr_nodes.size(); ++inode) {
+    if (routing_annotation.rr_node_net(drive_rr_nodes[inode]) == routing_annotation.rr_node_net(cur_rr_node)) {
+      path_id = (int)inode;
+      break;
+    }
+  }
+
+  /* Ensure that our path id makes sense! */
+  VTR_ASSERT( (DEFAULT_PATH_ID == path_id)
+           || ( (DEFAULT_PATH_ID < path_id) && (path_id < (int)datapath_mux_size) ) 
+            );
+
+  /* Find the circuit model id of the mux, we need its design technology which matters the bitstream generation */
+  std::vector<RRSwitchId> driver_switches = get_rr_graph_driver_switches(rr_graph, cur_rr_node);
+  VTR_ASSERT(1 == driver_switches.size());
+  CircuitModelId mux_model = device_annotation.rr_switch_circuit_model(driver_switches[0]);
+
+  /* Generate bitstream depend on both technology and structure of this MUX */
+  std::vector<bool> mux_bitstream = build_mux_bitstream(circuit_lib, mux_model, mux_lib, datapath_mux_size, path_id); 
+
+  /* Find the module in module manager and ensure the bitstream size matches! */
+  std::string mem_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string(MEMORY_MODULE_POSTFIX)); 
+  ModuleId mux_mem_module = module_manager.find_module(mem_module_name); 
+  VTR_ASSERT (true == module_manager.valid_module_id(mux_mem_module));
+  ModulePortId mux_mem_out_port_id = module_manager.find_module_port(mux_mem_module, generate_configuration_chain_data_out_name());
+  VTR_ASSERT(mux_bitstream.size() == module_manager.module_port(mux_mem_module, mux_mem_out_port_id).get_width());
+
+  /* Add the bistream to the bitstream manager */
+  for (const bool& bit : mux_bitstream) {
+    ConfigBitId config_bit = bitstream_manager.add_bit(bit);
+    /* Link the memory bits to the mux mem block */
+    bitstream_manager.add_bit_to_block(mux_mem_block, config_bit);
+  }
+}
+
+/********************************************************************
+ * This function generates bitstream for an interconnection, 
+ * i.e., a routing multiplexer, in a Switch Block
+ * This function will identify if a node indicates a routing multiplexer
+ * If not a routing multiplexer, no bitstream is needed here
+ * If yes, we will generate the bitstream for the routing multiplexer
+ *******************************************************************/
+static 
+void build_switch_block_interc_bitstream(BitstreamManager& bitstream_manager,
+                                         const ConfigBlockId& sb_configurable_block,
+                                         const ModuleManager& module_manager,
+                                         const CircuitLibrary& circuit_lib,
+                                         const MuxLibrary& mux_lib,
+                                         const RRGraph& rr_graph,
+                                         const VprDeviceAnnotation& device_annotation,
+                                         const VprRoutingAnnotation& routing_annotation,
+                                         const RRGSB& rr_gsb,
+                                         const e_side& chan_side,
+                                         const size_t& chan_node_id) {
+
+  std::vector<RRNodeId> driver_rr_nodes;
+
+  /* Get the node */
+  const RRNodeId& cur_rr_node = rr_gsb.get_chan_node(chan_side, chan_node_id);
+
+  /* Determine if the interc lies inside a channel wire, that is interc between segments */
+  if (false == rr_gsb.is_sb_node_passing_wire(rr_graph, chan_side, chan_node_id)) {
+    driver_rr_nodes = get_rr_graph_configurable_driver_nodes(rr_graph, cur_rr_node);
+    /* Special: if there are zero-driver nodes. We skip here */
+    if (0 == driver_rr_nodes.size()) {
+      return; 
+    }
+  }
+
+  if ( (0 == driver_rr_nodes.size())
+    || (0 == driver_rr_nodes.size()) ) {
+    /* No bitstream generation required by a special direct connection*/
+    return;
+  } else if (1 < driver_rr_nodes.size()) {
+    /* Create the block denoting the memory instances that drives this node in Switch Block */
+    std::string mem_block_name = generate_sb_memory_instance_name(SWITCH_BLOCK_MEM_INSTANCE_PREFIX, chan_side, chan_node_id, std::string(""));
+    ConfigBlockId mux_mem_block = bitstream_manager.add_block(mem_block_name);
+    bitstream_manager.add_child_block(sb_configurable_block, mux_mem_block);
+    /* This is a routing multiplexer! Generate bitstream */
+    build_switch_block_mux_bitstream(bitstream_manager, mux_mem_block, module_manager,
+                                     circuit_lib, mux_lib, rr_graph, 
+                                     cur_rr_node, driver_rr_nodes, 
+                                     device_annotation, routing_annotation);
+  } /*Nothing should be done else*/ 
+}
+
+/********************************************************************
+ * This function generates bitstream for a Switch Block
+ * and add it to the bitstream manager
+ * This function will spot all the routing multiplexers in a Switch Block
+ * using a simple but effective rule:
+ * The fan-in of each output node. 
+ * If there are more than 2 fan-in, there is a routing multiplexer 
+ *
+ * Note that the output nodes typically spread over all the sides of a Switch Block
+ * So, we will iterate over that.
+ *******************************************************************/
+static 
+void build_switch_block_bitstream(BitstreamManager& bitstream_manager,
+                                  const ConfigBlockId& sb_config_block,
+                                  const ModuleManager& module_manager,
+                                  const CircuitLibrary& circuit_lib,
+                                  const MuxLibrary& mux_lib,
+                                  const VprDeviceAnnotation& device_annotation,
+                                  const VprRoutingAnnotation& routing_annotation,
+                                  const RRGraph& rr_graph,
+                                  const RRGSB& rr_gsb) {
+
+  /* Iterate over all the multiplexers */
+  for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
+    SideManager side_manager(side);
+    for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) {
+      VTR_ASSERT( (CHANX == rr_graph.node_type(rr_gsb.get_chan_node(side_manager.get_side(), itrack)))
+               || (CHANY == rr_graph.node_type(rr_gsb.get_chan_node(side_manager.get_side(), itrack))) );
+      /* Only output port indicates a routing multiplexer */
+      if (OUT_PORT != rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) {
+        continue;
+      }
+      build_switch_block_interc_bitstream(bitstream_manager, sb_config_block, 
+                                          module_manager, 
+                                          circuit_lib, mux_lib, rr_graph,
+                                          device_annotation, routing_annotation,
+                                          rr_gsb, side_manager.get_side(), itrack);
+    }
+  }
+}
+
+/********************************************************************
+ * This function generates bitstream for a routing multiplexer
+ * in a Connection block
+ * This function will identify if a node indicates a routing multiplexer
+ * If not a routing multiplexer, no bitstream is needed here
+ * If yes, we will generate the bitstream for the routing multiplexer
+ *******************************************************************/
+static 
+void build_connection_block_mux_bitstream(BitstreamManager& bitstream_manager,
+                                          const ConfigBlockId& mux_mem_block,
+                                          const ModuleManager& module_manager,
+                                          const CircuitLibrary& circuit_lib,
+                                          const MuxLibrary& mux_lib,
+                                          const VprDeviceAnnotation& device_annotation,
+                                          const VprRoutingAnnotation& routing_annotation,
+                                          const RRGraph& rr_graph,
+                                          const RRNodeId& src_rr_node) {
+
+  /* Find drive_rr_nodes*/
+  size_t datapath_mux_size = rr_graph.node_fan_in(src_rr_node);
+
+  /* Configuration bits for MUX*/
+  int path_id = DEFAULT_PATH_ID;
+  int edge_index = 0;
+  for (const RREdgeId& edge : rr_graph.node_in_edges(src_rr_node)) {
+    RRNodeId driver_node = rr_graph.edge_src_node(edge);
+    if (routing_annotation.rr_node_net(driver_node) == routing_annotation.rr_node_net(src_rr_node)) {
+      path_id = edge_index;
+      break;
+    }
+    edge_index++;
+  }
+
+  /* Ensure that our path id makes sense! */
+  VTR_ASSERT( (DEFAULT_PATH_ID == path_id)
+           || ( (DEFAULT_PATH_ID < path_id) && (path_id < (int)datapath_mux_size) ) 
+            );
+
+
+  /* Find the circuit model id of the mux, we need its design technology which matters the bitstream generation */
+  std::vector<RRSwitchId> driver_switches = get_rr_graph_driver_switches(rr_graph, src_rr_node);
+  VTR_ASSERT(1 == driver_switches.size());
+  CircuitModelId mux_model = device_annotation.rr_switch_circuit_model(driver_switches[0]);
+
+  /* Generate bitstream depend on both technology and structure of this MUX */
+  std::vector<bool> mux_bitstream = build_mux_bitstream(circuit_lib, mux_model, mux_lib, datapath_mux_size, path_id); 
+
+  /* Find the module in module manager and ensure the bitstream size matches! */
+  std::string mem_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string(MEMORY_MODULE_POSTFIX)); 
+  ModuleId mux_mem_module = module_manager.find_module(mem_module_name); 
+  VTR_ASSERT (true == module_manager.valid_module_id(mux_mem_module));
+  ModulePortId mux_mem_out_port_id = module_manager.find_module_port(mux_mem_module, generate_configuration_chain_data_out_name());
+  VTR_ASSERT(mux_bitstream.size() == module_manager.module_port(mux_mem_module, mux_mem_out_port_id).get_width());
+
+  /* Add the bistream to the bitstream manager */
+  for (const bool& bit : mux_bitstream) {
+    ConfigBitId config_bit = bitstream_manager.add_bit(bit);
+    /* Link the memory bits to the mux mem block */
+    bitstream_manager.add_bit_to_block(mux_mem_block, config_bit);
+  }
+}
+
+
+/********************************************************************
+ * This function generates bitstream for an interconnection, 
+ * i.e., a routing multiplexer, in a Connection Block
+ * This function will identify if a node indicates a routing multiplexer
+ * If not a routing multiplexer, no bitstream is needed here
+ * If yes, we will generate the bitstream for the routing multiplexer
+ *******************************************************************/
+static 
+void build_connection_block_interc_bitstream(BitstreamManager& bitstream_manager,
+                                         const ConfigBlockId& cb_configurable_block,
+                                         const ModuleManager& module_manager,
+                                         const CircuitLibrary& circuit_lib,
+                                         const MuxLibrary& mux_lib,
+                                         const VprDeviceAnnotation& device_annotation,
+                                         const VprRoutingAnnotation& routing_annotation,
+                                         const RRGraph& rr_graph,
+                                         const RRGSB& rr_gsb,
+                                         const e_side& cb_ipin_side, 
+                                         const size_t& ipin_index) {
+
+  RRNodeId src_rr_node = rr_gsb.get_ipin_node(cb_ipin_side, ipin_index);
+
+  /* Consider configurable edges only */
+  std::vector<RRNodeId> driver_rr_nodes = get_rr_graph_configurable_driver_nodes(rr_graph, src_rr_node);
+
+  if (1 == driver_rr_nodes.size()) {
+    /* No bitstream generation required by a special direct connection*/
+  } else if (1 < driver_rr_nodes.size()) {
+    /* Create the block denoting the memory instances that drives this node in Switch Block */
+    std::string mem_block_name = generate_cb_memory_instance_name(CONNECTION_BLOCK_MEM_INSTANCE_PREFIX, rr_graph.node_side(src_rr_node), ipin_index, std::string(""));
+    ConfigBlockId mux_mem_block = bitstream_manager.add_block(mem_block_name);
+    bitstream_manager.add_child_block(cb_configurable_block, mux_mem_block);
+    /* This is a routing multiplexer! Generate bitstream */
+    build_connection_block_mux_bitstream(bitstream_manager, mux_mem_block, 
+                                         module_manager, circuit_lib, mux_lib, 
+                                         device_annotation, routing_annotation,
+                                         rr_graph, src_rr_node);
+  } /*Nothing should be done else*/ 
+}
+
+/********************************************************************
+ * This function generates bitstream for a Connection Block
+ * and add it to the bitstream manager
+ * This function will spot all the routing multiplexers in a Connection Block
+ * using a simple but effective rule:
+ * The fan-in of each output node. 
+ * If there are more than 2 fan-in, there is a routing multiplexer 
+ *
+ * Note that the output nodes are the IPIN rr node in a Connection Block
+ * So, we will iterate over that.
+ *******************************************************************/
+static 
+void build_connection_block_bitstream(BitstreamManager& bitstream_manager,
+                                      const ConfigBlockId& cb_configurable_block,
+                                      const ModuleManager& module_manager,
+                                      const CircuitLibrary& circuit_lib,
+                                      const MuxLibrary& mux_lib,
+                                      const VprDeviceAnnotation& device_annotation,
+                                      const VprRoutingAnnotation& routing_annotation,
+                                      const RRGraph& rr_graph,
+                                      const RRGSB& rr_gsb,
+                                      const t_rr_type& cb_type) {
+   
+  /* Find routing multiplexers on the sides of a Connection block where IPIN nodes locate */
+  std::vector<enum e_side> cb_sides = rr_gsb.get_cb_ipin_sides(cb_type);
+
+  for (size_t side = 0; side < cb_sides.size(); ++side) {
+    enum e_side cb_ipin_side = cb_sides[side];
+    SideManager side_manager(cb_ipin_side);
+    for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { 
+      build_connection_block_interc_bitstream(bitstream_manager, cb_configurable_block,
+                                              module_manager, circuit_lib, mux_lib, 
+                                              device_annotation, routing_annotation,
+                                              rr_graph, rr_gsb,
+                                              cb_ipin_side, inode);
+    }
+  }
+}
+
+/********************************************************************
+ * Create bitstream for a X-direction or Y-direction Connection Blocks
+ *******************************************************************/
+static 
+void build_connection_block_bitstreams(BitstreamManager& bitstream_manager,
+                                       const ConfigBlockId& top_configurable_block,
+                                       const ModuleManager& module_manager,
+                                       const CircuitLibrary& circuit_lib,
+                                       const MuxLibrary& mux_lib,
+                                       const VprDeviceAnnotation& device_annotation,
+                                       const VprRoutingAnnotation& routing_annotation,
+                                       const RRGraph& rr_graph,
+                                       const DeviceRRGSB& device_rr_gsb,
+                                       const t_rr_type& cb_type) {
+
+  vtr::Point<size_t> cb_range = device_rr_gsb.get_gsb_range();
+
+  for (size_t ix = 0; ix < cb_range.x(); ++ix) {
+    for (size_t iy = 0; iy < cb_range.y(); ++iy) {
+      const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
+      /* Check if the connection block exists in the device!
+       * Some of them do NOT exist due to heterogeneous blocks (height > 1) 
+       * We will skip those modules
+       */
+      if (false == rr_gsb.is_cb_exist(cb_type)) {
+        continue;
+      }
+      /* Skip if the cb does not contain any configuration bits! */
+      if (true == connection_block_contain_only_routing_tracks(rr_gsb, cb_type)) {
+        continue;
+      }
+      /* Create a block for the bitstream which corresponds to the Switch block */
+      vtr::Point<size_t> cb_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type));
+      ConfigBlockId cb_configurable_block = bitstream_manager.add_block(generate_connection_block_module_name(cb_type, cb_coord));
+      /* Set switch block as a child of top block */
+      bitstream_manager.add_child_block(top_configurable_block, cb_configurable_block);
+  
+      build_connection_block_bitstream(bitstream_manager, cb_configurable_block, module_manager,  
+                                       circuit_lib, mux_lib,
+                                       device_annotation, routing_annotation,
+                                       rr_graph,
+                                       rr_gsb, cb_type);
+    }
+  }
+}
+
+/********************************************************************
+ * Top-level function to create bitstream for global routing architecture
+ * Two major tasks: 
+ * 1. Generate bitstreams for Switch Blocks
+ * 2. Generate bitstreams for both X-direction and Y-direction Connection Blocks
+ *******************************************************************/
+void build_routing_bitstream(BitstreamManager& bitstream_manager,
+                             const ConfigBlockId& top_configurable_block,
+                             const ModuleManager& module_manager,
+                             const CircuitLibrary& circuit_lib,
+                             const MuxLibrary& mux_lib,
+                             const VprDeviceAnnotation& device_annotation,
+                             const VprRoutingAnnotation& routing_annotation,
+                             const RRGraph& rr_graph,
+                             const DeviceRRGSB& device_rr_gsb) {
+
+  /* Generate bitstream for each switch blocks
+   * To organize the bitstream in blocks, we create a block for each switch block 
+   * and give names which are same as they are in top-level module managers
+   */
+  VTR_LOG("Generating bitstream for Switch blocks...");
+  vtr::Point<size_t> sb_range = device_rr_gsb.get_gsb_range();
+  for (size_t ix = 0; ix < sb_range.x(); ++ix) {
+    for (size_t iy = 0; iy < sb_range.y(); ++iy) {
+      const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
+      /* Check if the switch block exists in the device!
+       * Some of them do NOT exist due to heterogeneous blocks (width > 1) 
+       * We will skip those modules
+       */
+      if (false == rr_gsb.is_sb_exist()) {
+        continue;
+      }
+
+      /* Create a block for the bitstream which corresponds to the Switch block */
+      vtr::Point<size_t> sb_coord(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
+      ConfigBlockId sb_configurable_block = bitstream_manager.add_block(generate_switch_block_module_name(sb_coord));
+      /* Set switch block as a child of top block */
+      bitstream_manager.add_child_block(top_configurable_block, sb_configurable_block);
+
+      build_switch_block_bitstream(bitstream_manager, sb_configurable_block, module_manager,  
+                                   circuit_lib, mux_lib,
+                                   device_annotation, routing_annotation,
+                                   rr_graph,
+                                   rr_gsb);
+    }
+  }
+  VTR_LOG("Done\n");
+
+  /* Generate bitstream for each connection blocks
+   * To organize the bitstream in blocks, we create a block for each connection block 
+   * and give names which are same as they are in top-level module managers
+   */
+  VTR_LOG("Generating bitstream for X-direction Connection blocks ...");
+
+  build_connection_block_bitstreams(bitstream_manager, top_configurable_block, module_manager,  
+                                    circuit_lib, mux_lib,
+                                    device_annotation, routing_annotation,
+                                    rr_graph,
+                                    device_rr_gsb, CHANX);
+  VTR_LOG("Done\n");
+
+  VTR_LOG("Generating bitstream for Y-direction Connection blocks ...");
+
+  build_connection_block_bitstreams(bitstream_manager, top_configurable_block, module_manager,  
+                                    circuit_lib, mux_lib,
+                                    device_annotation, routing_annotation,
+                                    rr_graph,
+                                    device_rr_gsb, CHANY);
+  VTR_LOG("Done");
+
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_bitstream/build_routing_bitstream.h b/openfpga/src/fpga_bitstream/build_routing_bitstream.h
new file mode 100644
index 000000000..2337601fe
--- /dev/null
+++ b/openfpga/src/fpga_bitstream/build_routing_bitstream.h
@@ -0,0 +1,39 @@
+/********************************************************************
+ * Header file for build_routing_bitstream.cpp
+ *******************************************************************/
+#ifndef BUILD_ROUTING_BITSTREAM_H
+#define BUILD_ROUTING_BITSTREAM_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <vector>
+#include "bitstream_manager.h"
+#include "vpr_context.h"
+#include "module_manager.h"
+#include "circuit_library.h"
+#include "mux_library.h"
+#include "device_rr_gsb.h"
+#include "vpr_device_annotation.h"
+#include "vpr_routing_annotation.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void build_routing_bitstream(BitstreamManager& bitstream_manager,
+                             const ConfigBlockId& top_configurable_block,
+                             const ModuleManager& module_manager,
+                             const CircuitLibrary& circuit_lib,
+                             const MuxLibrary& mux_lib,
+                             const VprDeviceAnnotation& device_annotation,
+                             const VprRoutingAnnotation& routing_annotation,
+                             const RRGraph& rr_graph,
+                             const DeviceRRGSB& device_rr_gsb);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/fpga_bitstream/mux_bitstream_constants.h b/openfpga/src/fpga_bitstream/mux_bitstream_constants.h
new file mode 100644
index 000000000..73d707ad5
--- /dev/null
+++ b/openfpga/src/fpga_bitstream/mux_bitstream_constants.h
@@ -0,0 +1,15 @@
+#ifndef MUX_BITSTREAM_CONSTANTS_H
+#define MUX_BITSTREAM_CONSTANTS_H
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/* Default path ID of a unused multiplexer */
+#define DEFAULT_PATH_ID -1
+
+/* Default path ID of a unused multiplexer when there are no constant inputs*/
+#define DEFAULT_MUX_PATH_ID 0
+
+} /* end namespace openfpga */
+
+#endif

From 8e9660b816238c76f6269aafe819be3e573ece7c Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 24 Feb 2020 16:09:29 -0700
Subject: [PATCH 202/645] add mapped block fast look-up as placement annotation

---
 .../src/annotation/annotate_placement.cpp     | 34 +++++++++++++
 openfpga/src/annotation/annotate_placement.h  | 24 +++++++++
 .../annotation/vpr_placement_annotation.cpp   | 49 +++++++++++++++++++
 .../src/annotation/vpr_placement_annotation.h | 48 ++++++++++++++++++
 openfpga/src/base/openfpga_context.h          |  6 +++
 openfpga/src/base/openfpga_link_arch.cpp      | 11 ++++-
 openfpga/src/fabric/build_grid_modules.cpp    | 34 +++----------
 7 files changed, 177 insertions(+), 29 deletions(-)
 create mode 100644 openfpga/src/annotation/annotate_placement.cpp
 create mode 100644 openfpga/src/annotation/annotate_placement.h
 create mode 100644 openfpga/src/annotation/vpr_placement_annotation.cpp
 create mode 100644 openfpga/src/annotation/vpr_placement_annotation.h

diff --git a/openfpga/src/annotation/annotate_placement.cpp b/openfpga/src/annotation/annotate_placement.cpp
new file mode 100644
index 000000000..adc83d5ff
--- /dev/null
+++ b/openfpga/src/annotation/annotate_placement.cpp
@@ -0,0 +1,34 @@
+/********************************************************************
+ * This file includes functions that are used to annotate pb_graph_node
+ * and pb_graph_pins from VPR to OpenFPGA
+ *******************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+#include "vtr_geometry.h"
+
+#include "annotate_placement.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Assign mapped blocks to grid locations 
+ * This is used by bitstream generator mainly as a fast look-up to 
+ * get mapped blocks with a given coordinate
+ *******************************************************************/
+void annotate_mapped_blocks(const DeviceContext& device_ctx, 
+                            const ClusteringContext& cluster_ctx, 
+                            const PlacementContext& place_ctx, 
+                            VprPlacementAnnotation& place_annotation) {
+  VTR_LOG("Building annotation for mapped blocks on grid locations...");
+
+  place_annotation.init_mapped_blocks(device_ctx.grid);
+  for (const ClusterBlockId& blk_id : cluster_ctx.clb_nlist.blocks()) {
+    vtr::Point<size_t> grid_coord(place_ctx.block_locs[blk_id].loc.x, place_ctx.block_locs[blk_id].loc.y);
+    place_annotation.add_mapped_block(grid_coord, place_ctx.block_locs[blk_id].loc.z, blk_id);
+  } 
+  VTR_LOG("Done\n");
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/annotation/annotate_placement.h b/openfpga/src/annotation/annotate_placement.h
new file mode 100644
index 000000000..fd47bb56d
--- /dev/null
+++ b/openfpga/src/annotation/annotate_placement.h
@@ -0,0 +1,24 @@
+#ifndef ANNOTATE_PLACEMENT_H
+#define ANNOTATE_PLACEMENT_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "vpr_context.h"
+#include "vpr_placement_annotation.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void annotate_mapped_blocks(const DeviceContext& device_ctx, 
+                            const ClusteringContext& cluster_ctx, 
+                            const PlacementContext& place_ctx, 
+                            VprPlacementAnnotation& place_annotation);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/annotation/vpr_placement_annotation.cpp b/openfpga/src/annotation/vpr_placement_annotation.cpp
new file mode 100644
index 000000000..779707250
--- /dev/null
+++ b/openfpga/src/annotation/vpr_placement_annotation.cpp
@@ -0,0 +1,49 @@
+/************************************************************************
+ * Member functions for class VprPlacementAnnotation
+ ***********************************************************************/
+#include "vtr_log.h"
+#include "vtr_assert.h"
+#include "vpr_placement_annotation.h"
+
+/* namespace openfpga begins */
+namespace openfpga {
+
+/************************************************************************
+ * Constructors
+ ***********************************************************************/
+
+/************************************************************************
+ * Public accessors
+ ***********************************************************************/
+std::vector<ClusterBlockId> VprPlacementAnnotation::grid_blocks(const vtr::Point<size_t>& grid_coord) const {
+  return blocks_[grid_coord.x()][grid_coord.y()];
+}
+
+/************************************************************************
+ * Public mutators
+ ***********************************************************************/
+void VprPlacementAnnotation::init_mapped_blocks(const DeviceGrid& grids) {
+  /* Size the block array with grid sizes */
+  blocks_.resize({grids.width(), grids.height()});
+
+  /* Resize the number of blocks allowed per grid by the capacity of the type */
+  for (size_t x = 0; x < grids.width(); ++x) {
+    for (size_t y = 0; y < grids.height(); ++y) {
+      /* Deposit invalid ids and we will fill later */
+      blocks_[x][y].resize(grids[x][y].type->capacity, ClusterBlockId::INVALID());
+    }
+  }
+}
+
+void VprPlacementAnnotation::add_mapped_block(const vtr::Point<size_t>& grid_coord,
+                                              const size_t& z,
+                                              const ClusterBlockId& mapped_block) {
+  VTR_ASSERT(z < grid_blocks(grid_coord).size());
+  if (ClusterBlockId::INVALID() != blocks_[grid_coord.x()][grid_coord.y()][z]) {
+    VTR_LOG("Override mapped blocks at grid[%lu][%lu][%lu]!\n",
+            grid_coord.x(), grid_coord.y(), z);
+  }
+  blocks_[grid_coord.x()][grid_coord.y()][z] = mapped_block;
+}
+
+} /* End namespace openfpga*/
diff --git a/openfpga/src/annotation/vpr_placement_annotation.h b/openfpga/src/annotation/vpr_placement_annotation.h
new file mode 100644
index 000000000..6a5e9c134
--- /dev/null
+++ b/openfpga/src/annotation/vpr_placement_annotation.h
@@ -0,0 +1,48 @@
+#ifndef VPR_PLACEMENT_ANNOTATION_H
+#define VPR_PLACEMENT_ANNOTATION_H
+
+/********************************************************************
+ * Include header files required by the data structure definition
+ *******************************************************************/
+#include <map> 
+
+/* Header from vtrutil library */
+#include "vtr_geometry.h"
+
+/* Header from vpr library */
+#include "device_grid.h"
+#include "clustered_netlist.h"
+
+/* Begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * This is the critical data structure to annotate placement results
+ * in VPR context
+ *******************************************************************/
+class VprPlacementAnnotation {
+  public:  /* Public accessors */
+    std::vector<ClusterBlockId> grid_blocks(const vtr::Point<size_t>& grid_coord) const;
+  public:  /* Public mutators */
+    void init_mapped_blocks(const DeviceGrid& grids);
+    void add_mapped_block(const vtr::Point<size_t>& grid_coord,
+                          const size_t& z, const ClusterBlockId& mapped_block);
+  private: /* Internal data */
+    /* A direct mapping show each mapped/unmapped blocks in grids
+     * The blocks_ array represents each grid on the FPGA fabric
+     * For example, block_[x][y] showed the mapped/unmapped blocks 
+     * at grid[x][y]. The third coordinate 'z' is the index of the same
+     * type of blocks in the grids. This is mainly applied to I/O
+     * blocks where you may have >1 I/O in a grid
+     *
+     * Note that this is different from the grid blocks in PlacementContext
+     * VPR considers only mapped blocks while this annotation 
+     * considers both unmapped and mapped blocks
+     * Unmapped blocks will be labelled as an invalid id in the vector
+     */
+    vtr::Matrix<std::vector<ClusterBlockId>> blocks_;
+};
+
+} /* End namespace openfpga*/
+
+#endif
diff --git a/openfpga/src/base/openfpga_context.h b/openfpga/src/base/openfpga_context.h
index 06c70cd24..9c685b247 100644
--- a/openfpga/src/base/openfpga_context.h
+++ b/openfpga/src/base/openfpga_context.h
@@ -6,6 +6,7 @@
 #include "vpr_netlist_annotation.h"
 #include "vpr_device_annotation.h"
 #include "vpr_clustering_annotation.h"
+#include "vpr_placement_annotation.h"
 #include "vpr_routing_annotation.h"
 #include "mux_library.h"
 #include "tile_direct.h"
@@ -47,6 +48,7 @@ class OpenfpgaContext : public Context  {
     const openfpga::VprDeviceAnnotation& vpr_device_annotation() const { return vpr_device_annotation_; }
     const openfpga::VprNetlistAnnotation& vpr_netlist_annotation() const { return vpr_netlist_annotation_; }
     const openfpga::VprClusteringAnnotation& vpr_clustering_annotation() const { return vpr_clustering_annotation_; }
+    const openfpga::VprPlacementAnnotation& vpr_placement_annotation() const { return vpr_placement_annotation_; }
     const openfpga::VprRoutingAnnotation& vpr_routing_annotation() const { return vpr_routing_annotation_; }
     const openfpga::DeviceRRGSB& device_rr_gsb() const { return device_rr_gsb_; }
     const openfpga::MuxLibrary& mux_lib() const { return mux_lib_; }
@@ -59,6 +61,7 @@ class OpenfpgaContext : public Context  {
     openfpga::VprDeviceAnnotation& mutable_vpr_device_annotation() { return vpr_device_annotation_; }
     openfpga::VprNetlistAnnotation& mutable_vpr_netlist_annotation() { return vpr_netlist_annotation_; }
     openfpga::VprClusteringAnnotation& mutable_vpr_clustering_annotation() { return vpr_clustering_annotation_; }
+    openfpga::VprPlacementAnnotation& mutable_vpr_placement_annotation() { return vpr_placement_annotation_; }
     openfpga::VprRoutingAnnotation& mutable_vpr_routing_annotation() { return vpr_routing_annotation_; }
     openfpga::DeviceRRGSB& mutable_device_rr_gsb() { return device_rr_gsb_; }
     openfpga::MuxLibrary& mutable_mux_lib() { return mux_lib_; }
@@ -79,6 +82,9 @@ class OpenfpgaContext : public Context  {
     /* Pin net fix to cluster results */
     openfpga::VprClusteringAnnotation vpr_clustering_annotation_;
 
+    /* Placement results */
+    openfpga::VprPlacementAnnotation vpr_placement_annotation_;
+
     /* Routing results annotation */ 
     openfpga::VprRoutingAnnotation vpr_routing_annotation_;
 
diff --git a/openfpga/src/base/openfpga_link_arch.cpp b/openfpga/src/base/openfpga_link_arch.cpp
index fcaa1f128..9dc1e38c7 100644
--- a/openfpga/src/base/openfpga_link_arch.cpp
+++ b/openfpga/src/base/openfpga_link_arch.cpp
@@ -15,6 +15,7 @@
 #include "annotate_rr_graph.h"
 #include "mux_library_builder.h"
 #include "build_tile_direct.h"
+#include "annotate_placement.h"
 #include "openfpga_link_arch.h"
 
 /* Include global variables of VPR */
@@ -109,8 +110,14 @@ void link_arch(OpenfpgaContext& openfpga_ctx,
                                                             const_cast<const OpenfpgaContext&>(openfpga_ctx)); 
 
   /* Build tile direct annotation */
-  openfpga_ctx.mutable_tile_direct() =  build_device_tile_direct(g_vpr_ctx.device(),
-                                                                 openfpga_ctx.arch().arch_direct);
+  openfpga_ctx.mutable_tile_direct() = build_device_tile_direct(g_vpr_ctx.device(),
+                                                                openfpga_ctx.arch().arch_direct);
+
+  /* Annotate placement results */
+  annotate_mapped_blocks(g_vpr_ctx.device(), 
+                         g_vpr_ctx.clustering(),
+                         g_vpr_ctx.placement(),
+                         openfpga_ctx.mutable_vpr_placement_annotation());
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/fabric/build_grid_modules.cpp b/openfpga/src/fabric/build_grid_modules.cpp
index 39ca8e266..17ecc67e2 100644
--- a/openfpga/src/fabric/build_grid_modules.cpp
+++ b/openfpga/src/fabric/build_grid_modules.cpp
@@ -914,35 +914,15 @@ void build_physical_tile_module(ModuleManager& module_manager,
   ModuleId grid_module = module_manager.add_module(grid_module_name); 
   VTR_ASSERT(true == module_manager.valid_module_id(grid_module));
 
-  /* Now each physical tile may have a number of diffrent logical blocks
-   * We assume the following organization:
-   *     
-   *    Physical tile
-   *    +----------------------- 
-   *    |
-   *    |   pb_typeA[0] - from equivalent site[A]
-   *    |   +--------------------
-   *    |   |
-   *    |   +--------------------
-   *    |
-   *    |   pb_typeB[0] - from equivalent site[B] 
-   *    |   +--------------------
-   *    |   |
-   *    |   +--------------------
-   *   ...           ...
-   *    |   pb_typeA[capacity - 1] - from equivalent site[A]
-   *    |   +--------------------
-   *    |   |
-   *    |   +--------------------
-   *    |
-   *    |   pb_typeB[capacity - 1] - from equivalent site[B] 
-   *    |   +--------------------
-   *    |   |
-   *    |   +--------------------
-   *    | 
-   *    +----------------------- 
+  /* Now each physical tile may have a number of logical blocks
+   * OpenFPGA only considers the physical implementation of the tiles.
+   * So, we do not allow multiple equivalent sites to be defined 
+   * under a physical tile type. 
+   * If you need different equivalent sites, you can always define 
+   * it as a mode under a <pb_type>
    */
   for (int iz = 0; iz < phy_block_type->capacity; ++iz) {
+    VTR_ASSERT(1 == phy_block_type->equivalent_sites.size());
     for (t_logical_block_type_ptr lb_type : phy_block_type->equivalent_sites) {
       /* Bypass empty pb_graph */
       if (nullptr == lb_type->pb_graph_head) {

From 04c69d30c287f702df15eaae9e69cbbc39ffc697 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 24 Feb 2020 19:38:02 -0700
Subject: [PATCH 203/645] start adding grid bitstream builder. TODO: lut and
 interconnect bitstream decoding

---
 .../fpga_bitstream/build_grid_bitstream.cpp   | 367 ++++++++++++++++++
 .../src/fpga_bitstream/build_grid_bitstream.h |  37 ++
 openfpga/src/repack/physical_pb.cpp           |  22 ++
 openfpga/src/repack/physical_pb.h             |   5 +
 4 files changed, 431 insertions(+)
 create mode 100644 openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
 create mode 100644 openfpga/src/fpga_bitstream/build_grid_bitstream.h

diff --git a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
new file mode 100644
index 000000000..0ed29be12
--- /dev/null
+++ b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
@@ -0,0 +1,367 @@
+/********************************************************************
+ * This file includes functions that are used for building bitstreams
+ * for grids (CLBs, heterogenerous blocks, I/Os, etc.)
+ *******************************************************************/
+#include <string>
+
+/* Headers from vtrutil library */
+#include "vtr_log.h"
+#include "vtr_assert.h"
+#include "vtr_time.h"
+
+/* Headers from vpr library */
+#include "vpr_utils.h"
+
+#include "mux_utils.h"
+
+#include "circuit_library_utils.h"
+
+#include "openfpga_reserved_words.h"
+#include "openfpga_naming.h"
+#include "mux_bitstream_constants.h"
+#include "pb_type_utils.h"
+
+#include "build_mux_bitstream.h"
+//#include "build_lut_bitstream.h"
+#include "build_grid_bitstream.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Decode mode bits "01..." to a bitstream vector
+ *******************************************************************/
+static 
+std::vector<bool> generate_mode_select_bitstream(const std::vector<size_t>& mode_bits) {
+  std::vector<bool> mode_select_bitstream;
+ 
+  for (const size_t& mode_bit : mode_bits) {
+    /* Error out for unexpected bits */
+    VTR_ASSERT((0 == mode_bit) || (1 == mode_bit));
+    mode_select_bitstream.push_back(1 == mode_bit);
+  }
+
+  return mode_select_bitstream;
+}
+
+/********************************************************************
+ * Generate bitstream for a primitive node and add it to bitstream manager
+ *******************************************************************/
+static 
+void build_primitive_bitstream(BitstreamManager& bitstream_manager,
+                               const ConfigBlockId& parent_configurable_block,
+                               const ModuleManager& module_manager,
+                               const CircuitLibrary& circuit_lib,
+                               const VprDeviceAnnotation& device_annotation,
+                               const PhysicalPb& physical_pb,
+                               const PhysicalPbId& primitive_pb_id,
+                               t_pb_type* primitive_pb_type) {
+
+  /* Ensure a valid physical pritimive pb */ 
+  if (nullptr == primitive_pb_type) {
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid primitive_pb_type!\n");
+    exit(1);
+  }
+
+  CircuitModelId primitive_model = device_annotation.pb_type_circuit_model(primitive_pb_type);
+  VTR_ASSERT(CircuitModelId::INVALID() != primitive_model);
+  VTR_ASSERT( (CIRCUIT_MODEL_IOPAD == circuit_lib.model_type(primitive_model))
+           || (CIRCUIT_MODEL_HARDLOGIC == circuit_lib.model_type(primitive_model))
+           || (CIRCUIT_MODEL_FF == circuit_lib.model_type(primitive_model)) );
+
+  /* Find SRAM ports for mode-selection */
+  std::vector<CircuitPortId> primitive_mode_select_ports = find_circuit_mode_select_sram_ports(circuit_lib, primitive_model);
+
+  /* We may have a port for mode select or not. */
+  VTR_ASSERT( (0 == primitive_mode_select_ports.size())
+           || (1 == primitive_mode_select_ports.size()) );
+
+  /* Generate bitstream for mode-select ports */
+  if (0 == primitive_mode_select_ports.size()) {
+    return; /* Nothing to do, return directly */
+  }
+
+  std::vector<bool> mode_select_bitstream;
+  if (true == physical_pb.valid_pb_id(primitive_pb_id)) {
+    mode_select_bitstream = generate_mode_select_bitstream(physical_pb.mode_bits(primitive_pb_id));
+  } else { /* get default mode_bits */
+    mode_select_bitstream = generate_mode_select_bitstream(device_annotation.pb_type_mode_bits(primitive_pb_type));
+  }
+
+  /* Ensure the length of bitstream matches the side of memory circuits */
+  std::vector<CircuitModelId> sram_models = find_circuit_sram_models(circuit_lib, primitive_model);
+  VTR_ASSERT(1 == sram_models.size());
+  std::string mem_block_name = generate_memory_module_name(circuit_lib, primitive_model, sram_models[0], std::string(MEMORY_MODULE_POSTFIX));
+  ModuleId mem_module = module_manager.find_module(mem_block_name);
+  VTR_ASSERT (true == module_manager.valid_module_id(mem_module));
+  ModulePortId mem_out_port_id = module_manager.find_module_port(mem_module, generate_configuration_chain_data_out_name());
+  VTR_ASSERT(mode_select_bitstream.size() == module_manager.module_port(mem_module, mem_out_port_id).get_width());
+
+  /* Create a block for the bitstream which corresponds to the memory module associated to the LUT */
+  ConfigBlockId mem_block = bitstream_manager.add_block(mem_block_name);
+  bitstream_manager.add_child_block(parent_configurable_block, mem_block);
+
+  /* Add the bitstream to the bitstream manager */
+  for (const bool& bit : mode_select_bitstream) {
+    ConfigBitId config_bit = bitstream_manager.add_bit(bit);
+    /* Link the memory bits to the mux mem block */
+    bitstream_manager.add_bit_to_block(mem_block, config_bit);
+  }
+}
+
+/********************************************************************
+ * This function generates bitstream for a physical block, which is 
+ * a child block of a grid 
+ * This function will follow a recursive way in generating bitstreams
+ * It will follow the same sequence in visiting all the sub blocks
+ * in a physical as we did during module generation
+ *
+ * Note: if you want to bind your bitstream with a FPGA fabric generated by FPGA-X2P
+ * Please follow the same sequence in visiting pb_graph nodes!!!
+ * For more details, you may refer to function rec_build_physical_block_modules()
+ *******************************************************************/
+static 
+void rec_build_physical_block_bitstream(BitstreamManager& bitstream_manager,
+                                        const ConfigBlockId& parent_configurable_block,
+                                        const ModuleManager& module_manager,
+                                        const CircuitLibrary& circuit_lib,
+                                        const MuxLibrary& mux_lib,
+                                        const VprDeviceAnnotation& device_annotation,
+                                        const e_side& border_side,
+                                        const PhysicalPb& physical_pb, 
+                                        const PhysicalPbId& pb_id, 
+                                        t_pb_graph_node* physical_pb_graph_node,
+                                        const size_t& pb_graph_node_index) {
+  /* Get the physical pb_type that is linked to the pb_graph node */
+  t_pb_type* physical_pb_type = physical_pb_graph_node->pb_type;
+
+  /* Find the mode that define_idle_mode*/
+  t_mode* physical_mode = device_annotation.physical_mode(physical_pb_type);
+
+  /* Create a block for the physical block under the grid block in bitstream manager */
+  std::string pb_block_name = generate_physical_block_instance_name(physical_pb_type, pb_graph_node_index);
+  ConfigBlockId pb_configurable_block = bitstream_manager.add_block(pb_block_name);
+  bitstream_manager.add_child_block(parent_configurable_block, pb_configurable_block);
+
+  /* Recursively finish all the child pb_types*/
+  if (false == is_primitive_pb_type(physical_pb_type)) { 
+    for (int ipb = 0; ipb < physical_mode->num_pb_type_children; ++ipb) {
+      for (int jpb = 0; jpb < physical_mode->pb_type_children[ipb].num_pb; ++jpb) {
+        PhysicalPbId child_pb = PhysicalPbId::INVALID();
+        /* Find the child pb that is mapped, and the mapping info is not stored in the physical mode ! */
+        if (true == physical_pb.valid_pb_id(pb_id)) {
+          child_pb = physical_pb.child(pb_id, &(physical_mode->pb_type_children[ipb]), jpb);
+          VTR_ASSERT(true == physical_pb.valid_pb_id(child_pb));
+        }
+        /* Go recursively */
+        rec_build_physical_block_bitstream(bitstream_manager, pb_configurable_block,
+                                           module_manager, circuit_lib, mux_lib, 
+                                           device_annotation, 
+                                           border_side, 
+                                           physical_pb, child_pb,
+                                           &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb][jpb]),
+                                           jpb);
+      }
+    }
+  }
+
+  /* Check if this has defined a circuit_model*/
+  if (true == is_primitive_pb_type(physical_pb_type)) { 
+    switch (physical_pb_type->class_type) {
+    case LUT_CLASS: 
+      /* Special case for LUT !!!
+       * Mapped logical block information is stored in child_pbs of this pb!!!
+       */
+      //build_lut_bitstream(bitstream_manager, pb_configurable_block,
+      //                    module_manager, circuit_lib, mux_lib, 
+      //                    physical_pb, pb_id, physical_pb_type);
+      break;
+    case LATCH_CLASS:
+    case UNKNOWN_CLASS:
+    case MEMORY_CLASS:
+      /* For other types of blocks, we can apply a generic therapy */
+      build_primitive_bitstream(bitstream_manager, pb_configurable_block,
+                                module_manager, circuit_lib, device_annotation, 
+                                physical_pb, pb_id, physical_pb_type);
+      break;  
+    default:
+      VTR_LOGF_ERROR(__FILE__, __LINE__, 
+                     "Unknown class type of pb_type '%s'!\n",
+                     physical_pb_type->name);
+      exit(1);
+    }
+    /* Finish for primitive node, return */
+    return;
+  }
+
+  /* Generate the bitstream for the interconnection in this physical block */
+  //build_physical_block_interc_bitstream(bitstream_manager, pb_configurable_block,
+  //                                      module_manager, circuit_lib, mux_lib,
+  //                                      physical_pb_graph_node, physical_pb,
+  //                                      pb_id, physical_mode_index);
+}
+
+/********************************************************************
+ * This function generates bitstream for a grid, which could be a
+ * CLB, a heterogenerous block, an I/O, etc.
+ * Note that each grid may contain a number of physical blocks,
+ * this function will iterate over them
+ *******************************************************************/
+static 
+void build_physical_block_bitstream(BitstreamManager& bitstream_manager,
+                                    const ConfigBlockId& top_block,
+                                    const ModuleManager& module_manager,
+                                    const CircuitLibrary& circuit_lib,
+                                    const MuxLibrary& mux_lib,
+                                    const VprDeviceAnnotation& device_annotation,
+                                    const VprClusteringAnnotation& cluster_annotation,
+                                    const VprPlacementAnnotation& place_annotation,
+                                    const DeviceGrid& grids,
+                                    const vtr::Point<size_t>& grid_coord,
+                                    const e_side& border_side) {
+  /* Create a block for the grid in bitstream manager */
+  t_physical_tile_type_ptr grid_type = grids[grid_coord.x()][grid_coord.y()].type;
+  std::string grid_module_name_prefix(GRID_MODULE_NAME_PREFIX);
+  std::string grid_block_name = generate_grid_block_instance_name(grid_module_name_prefix, std::string(grid_type->name), 
+                                                                  is_io_type(grid_type), border_side, grid_coord);
+  ConfigBlockId grid_configurable_block = bitstream_manager.add_block(grid_block_name);
+  bitstream_manager.add_child_block(top_block, grid_configurable_block);
+
+  /* Iterate over the capacity of the grid
+   * Now each physical tile may have a number of logical blocks
+   * OpenFPGA only considers the physical implementation of the tiles.
+   * So, we do not allow multiple equivalent sites to be defined 
+   * under a physical tile type. 
+   * If you need different equivalent sites, you can always define 
+   * it as a mode under a <pb_type>
+   */
+  for (size_t z = 0; z < place_annotation.grid_blocks(grid_coord).size(); ++z) {
+    VTR_ASSERT(1 == grid_type->equivalent_sites.size());
+    for (t_logical_block_type_ptr lb_type : grid_type->equivalent_sites) {
+      /* Bypass empty pb_graph */
+      if (nullptr == lb_type->pb_graph_head) {
+        continue;
+      }
+
+      if (ClusterBlockId::INVALID() == place_annotation.grid_blocks(grid_coord)[z]) {
+        /* Recursively traverse the pb_graph and generate bitstream */
+        rec_build_physical_block_bitstream(bitstream_manager, grid_configurable_block, 
+                                           module_manager, circuit_lib, mux_lib, 
+                                           device_annotation, border_side, 
+                                           PhysicalPb(), PhysicalPbId::INVALID(),
+                                           lb_type->pb_graph_head, z);
+      } else {
+        const PhysicalPb& phy_pb = cluster_annotation.physical_pb(place_annotation.grid_blocks(grid_coord)[z]);
+
+        /* Get the top-level node of the pb_graph */
+        t_pb_graph_node* pb_graph_head = lb_type->pb_graph_head;
+        VTR_ASSERT(nullptr != pb_graph_head);
+        const PhysicalPbId& top_pb_id = phy_pb.find_pb(pb_graph_head);
+
+        /* Recursively traverse the pb_graph and generate bitstream */
+        rec_build_physical_block_bitstream(bitstream_manager, grid_configurable_block, 
+                                           module_manager, circuit_lib, mux_lib, 
+                                           device_annotation, border_side, 
+                                           phy_pb, top_pb_id, pb_graph_head, z);
+      }
+    }
+  } 
+}
+
+
+/********************************************************************
+ * Top-level function of this file: 
+ * Generate bitstreams for all the grids, including 
+ * 1. core grids that sit in the center of the fabric
+ * 2. side grids (I/O grids) that sit in the borders for the fabric
+ *******************************************************************/
+void build_grid_bitstream(BitstreamManager& bitstream_manager,
+                          const ConfigBlockId& top_block,
+                          const ModuleManager& module_manager,
+                          const CircuitLibrary& circuit_lib,
+                          const MuxLibrary& mux_lib,
+                          const DeviceGrid& grids,
+                          const VprDeviceAnnotation& device_annotation,
+                          const VprClusteringAnnotation& cluster_annotation,
+                          const VprPlacementAnnotation& place_annotation,
+                          const bool& verbose) {
+
+  VTR_LOGV(verbose, "Generating bitstream for core grids...");
+
+  /* Generate bitstream for the core logic block one by one */
+  for (size_t ix = 1; ix < grids.width() - 1; ++ix) {
+    for (size_t iy = 1; iy < grids.height() - 1; ++iy) {
+      /* Bypass EMPTY grid */
+      if (true == is_empty_type(grids[ix][iy].type)) {
+        continue;
+      } 
+      /* Skip width > 1 or height > 1 tiles (mostly heterogeneous blocks) */
+      if ( (0 < grids[ix][iy].width_offset)
+        || (0 < grids[ix][iy].height_offset) ) {
+        continue;
+      }
+      /* We should not meet any I/O grid */
+      VTR_ASSERT(true != is_io_type(grids[ix][iy].type));
+      /* Add a grid module to top_module*/
+      vtr::Point<size_t> grid_coord(ix, iy);
+      build_physical_block_bitstream(bitstream_manager, top_block, module_manager,
+                                     circuit_lib, mux_lib,
+                                     device_annotation, cluster_annotation,
+                                     place_annotation,
+                                     grids, grid_coord, NUM_SIDES);
+    }
+  }
+  VTR_LOGV(verbose, "Done\n");
+
+  VTR_LOGV(verbose, "Generating bitstream for I/O grids...");
+
+  /* Create the coordinate range for each side of FPGA fabric */
+  std::vector<e_side> io_sides{TOP, RIGHT, BOTTOM, LEFT};
+  std::map<e_side, std::vector<vtr::Point<size_t>>> io_coordinates;
+
+  /* TOP side*/
+  for (size_t ix = 1; ix < grids.width() - 1; ++ix) { 
+    io_coordinates[TOP].push_back(vtr::Point<size_t>(ix, grids.height() - 1));
+  } 
+
+  /* RIGHT side */
+  for (size_t iy = 1; iy < grids.height() - 1; ++iy) { 
+    io_coordinates[RIGHT].push_back(vtr::Point<size_t>(grids.width() - 1, iy));
+  } 
+
+  /* BOTTOM side*/
+  for (size_t ix = 1; ix < grids.width() - 1; ++ix) { 
+    io_coordinates[BOTTOM].push_back(vtr::Point<size_t>(ix, 0));
+  } 
+
+  /* LEFT side */
+  for (size_t iy = 1; iy < grids.height() - 1; ++iy) { 
+    io_coordinates[LEFT].push_back(vtr::Point<size_t>(0, iy));
+  }
+
+  /* Add instances of I/O grids to top_module */
+  for (const e_side& io_side : io_sides) {
+    for (const vtr::Point<size_t>& io_coordinate : io_coordinates[io_side]) {
+      /* Bypass EMPTY grid */
+      if (true == is_empty_type(grids[io_coordinate.x()][io_coordinate.y()].type)) {
+        continue;
+      } 
+      /* Skip height > 1 tiles (mostly heterogeneous blocks) */
+      if ( (0 < grids[io_coordinate.x()][io_coordinate.y()].width_offset)
+        || (0 < grids[io_coordinate.x()][io_coordinate.y()].height_offset) ) {
+        continue;
+      }
+      /* We should not meet any I/O grid */
+      VTR_ASSERT(true == is_io_type(grids[io_coordinate.x()][io_coordinate.y()].type));
+      build_physical_block_bitstream(bitstream_manager, top_block, module_manager,
+                                     circuit_lib, mux_lib,
+                                     device_annotation, cluster_annotation, 
+                                     place_annotation,
+                                     grids, io_coordinate, io_side);
+    }
+  }
+  VTR_LOGV(verbose, "Done\n");
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_bitstream/build_grid_bitstream.h b/openfpga/src/fpga_bitstream/build_grid_bitstream.h
new file mode 100644
index 000000000..6f192a9b7
--- /dev/null
+++ b/openfpga/src/fpga_bitstream/build_grid_bitstream.h
@@ -0,0 +1,37 @@
+#ifndef BUILD_GRID_BITSTREAM_H
+#define BUILD_GRID_BITSTREAM_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <vector>
+#include "device_grid.h"
+#include "bitstream_manager.h"
+#include "module_manager.h"
+#include "circuit_library.h"
+#include "mux_library.h"
+#include "vpr_device_annotation.h"
+#include "vpr_clustering_annotation.h"
+#include "vpr_placement_annotation.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void build_grid_bitstream(BitstreamManager& bitstream_manager,
+                          const ConfigBlockId& top_block,
+                          const ModuleManager& module_manager,
+                          const CircuitLibrary& circuit_lib,
+                          const MuxLibrary& mux_lib,
+                          const DeviceGrid& grids,
+                          const VprDeviceAnnotation& device_annotation,
+                          const VprClusteringAnnotation& cluster_annotation,
+                          const VprPlacementAnnotation& place_annotation,
+                          const bool& verbose);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/repack/physical_pb.cpp b/openfpga/src/repack/physical_pb.cpp
index 647c527af..f64a3d29a 100644
--- a/openfpga/src/repack/physical_pb.cpp
+++ b/openfpga/src/repack/physical_pb.cpp
@@ -36,6 +36,23 @@ PhysicalPbId PhysicalPb::parent(const PhysicalPbId& pb) const {
   return parent_pbs_[pb];
 }
 
+PhysicalPbId PhysicalPb::child(const PhysicalPbId& pb,
+                               const t_pb_type* pb_type, 
+                               const size_t& index) const {
+  VTR_ASSERT(true == valid_pb_id(pb));
+  if (0 < child_pbs_[pb].count(pb_type)) {
+    if (index < child_pbs_[pb].at(pb_type).size()) {
+      return child_pbs_[pb].at(pb_type)[index]; 
+    }
+  }
+  return PhysicalPbId::INVALID();
+}
+
+std::vector<AtomBlockId> PhysicalPb::atom_blocks(const PhysicalPbId& pb) const {
+  VTR_ASSERT(true == valid_pb_id(pb));
+  return atom_blocks_[pb];
+}
+
 AtomNetId PhysicalPb::pb_graph_pin_atom_net(const PhysicalPbId& pb,
                                             const t_pb_graph_pin* pb_graph_pin) const {
   VTR_ASSERT(true == valid_pb_id(pb));
@@ -47,6 +64,11 @@ AtomNetId PhysicalPb::pb_graph_pin_atom_net(const PhysicalPbId& pb,
   return AtomNetId::INVALID();
 }
 
+std::vector<size_t> PhysicalPb::mode_bits(const PhysicalPbId& pb) const {
+  VTR_ASSERT(true == valid_pb_id(pb));
+  return mode_bits_[pb];
+}
+
 /******************************************************************************
  * Private Mutators
  ******************************************************************************/
diff --git a/openfpga/src/repack/physical_pb.h b/openfpga/src/repack/physical_pb.h
index 9e4dff206..2ad29c2cd 100644
--- a/openfpga/src/repack/physical_pb.h
+++ b/openfpga/src/repack/physical_pb.h
@@ -42,8 +42,13 @@ class PhysicalPb {
     std::string name(const PhysicalPbId& pb) const;
     PhysicalPbId find_pb(const t_pb_graph_node* name) const;
     PhysicalPbId parent(const PhysicalPbId& pb) const;
+    PhysicalPbId child(const PhysicalPbId& pb,
+                       const t_pb_type* pb_type, 
+                       const size_t& index) const;
+    std::vector<AtomBlockId> atom_blocks(const PhysicalPbId& pb) const;
     AtomNetId pb_graph_pin_atom_net(const PhysicalPbId& pb,
                                     const t_pb_graph_pin* pb_graph_pin) const;
+    std::vector<size_t> mode_bits(const PhysicalPbId& pb) const;
   public: /* Public mutators */
     PhysicalPbId create_pb(const t_pb_graph_node* pb_graph_node);
     void add_child(const PhysicalPbId& parent,

From 2c44c70557cb17ff9509b7e5eb4ba3e6795c387d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 25 Feb 2020 00:28:06 -0700
Subject: [PATCH 204/645] bring pb interconnection bitstream generation online

---
 .../fpga_bitstream/build_device_bitstream.cpp |  12 +-
 .../fpga_bitstream/build_grid_bitstream.cpp   | 248 +++++++++++++++++-
 .../build_routing_bitstream.cpp               |   2 +-
 3 files changed, 249 insertions(+), 13 deletions(-)

diff --git a/openfpga/src/fpga_bitstream/build_device_bitstream.cpp b/openfpga/src/fpga_bitstream/build_device_bitstream.cpp
index 0b6d01d39..a5cde4853 100644
--- a/openfpga/src/fpga_bitstream/build_device_bitstream.cpp
+++ b/openfpga/src/fpga_bitstream/build_device_bitstream.cpp
@@ -13,7 +13,7 @@
 
 #include "openfpga_naming.h"
 
-//#include "build_grid_bitstream.h"
+#include "build_grid_bitstream.h"
 #include "build_routing_bitstream.h"
 #include "build_device_bitstream.h"
 
@@ -55,7 +55,15 @@ BitstreamManager build_device_bitstream(const VprContext& vpr_ctx,
 
   /* Create bitstream from grids */
   VTR_LOGV(verbose, "Building grid bitstream...\n");
-  //build_grid_bitstream(bitstream_manager, top_block, module_manager, circuit_lib, mux_lib, device_size, grids);
+  build_grid_bitstream(bitstream_manager, top_block,
+                       openfpga_ctx.module_graph(),
+                       openfpga_ctx.arch().circuit_lib,
+                       openfpga_ctx.mux_lib(),
+                       vpr_ctx.device().grid,
+                       openfpga_ctx.vpr_device_annotation(),
+                       openfpga_ctx.vpr_clustering_annotation(),
+                       openfpga_ctx.vpr_placement_annotation(),
+                       verbose);
   VTR_LOGV(verbose, "Done\n");
 
   /* Create bitstream from routing architectures */
diff --git a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
index 0ed29be12..d344d8880 100644
--- a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
+++ b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
@@ -12,10 +12,12 @@
 /* Headers from vpr library */
 #include "vpr_utils.h"
 
+#include "pb_graph_utils.h"
 #include "mux_utils.h"
 
 #include "circuit_library_utils.h"
 
+#include "openfpga_interconnect_types.h"
 #include "openfpga_reserved_words.h"
 #include "openfpga_naming.h"
 #include "mux_bitstream_constants.h"
@@ -110,6 +112,229 @@ void build_primitive_bitstream(BitstreamManager& bitstream_manager,
   }
 }
 
+/********************************************************************
+ * This function generates bitstream for a programmable routing
+ * multiplexer which drives an output pin of physical_pb_graph_node and its the input_edges
+ *
+ *   src_pb_graph_node.[in|out]_pins -----------------> des_pb_graph_node.[in|out]pins
+ *                                        /|\
+ *                                         |
+ *                         input_pins,   edges,       output_pins
+ *******************************************************************/
+static 
+void build_physical_block_pin_interc_bitstream(BitstreamManager& bitstream_manager,
+                                               const ConfigBlockId& parent_configurable_block,
+                                               const ModuleManager& module_manager,
+                                               const CircuitLibrary& circuit_lib,
+                                               const MuxLibrary& mux_lib,
+                                               const VprDeviceAnnotation& device_annotation,
+                                               const PhysicalPb& physical_pb,
+                                               t_pb_graph_pin* des_pb_graph_pin,
+                                               t_mode* physical_mode) {
+  /* Identify the number of fan-in (Consider interconnection edges of only selected mode) */
+  t_interconnect* cur_interc = pb_graph_pin_interc(des_pb_graph_pin, physical_mode);
+  size_t fan_in = pb_graph_pin_inputs(des_pb_graph_pin, cur_interc).size();
+
+  if ((nullptr == cur_interc) || (0 == fan_in)) { 
+    /* No interconnection matched */
+    return;
+  }
+
+  /* Identify pin interconnection type */
+  enum e_interconnect interc_type = device_annotation.interconnect_physical_type(cur_interc);
+  switch (interc_type) {
+  case DIRECT_INTERC:
+    /* Nothing to do, return */
+    break;
+  case COMPLETE_INTERC:
+  case MUX_INTERC: {
+    /* Find the circuit model id of the mux, we need its design technology which matters the bitstream generation */
+    CircuitModelId mux_model = device_annotation.interconnect_circuit_model(cur_interc);
+    VTR_ASSERT(CIRCUIT_MODEL_MUX == circuit_lib.model_type(mux_model));
+
+    /* Find the input size of the implementation of a routing multiplexer */
+    size_t datapath_mux_size = fan_in;
+    VTR_ASSERT(true == valid_mux_implementation_num_inputs(datapath_mux_size));
+
+    /* Find the path id:
+     * - if des pb is not valid, this is an unmapped pb, we can set a default path_id
+     */
+    const PhysicalPbId& des_pb_id = physical_pb.find_pb(des_pb_graph_pin->parent_node);
+    size_t mux_input_pin_id = 0;
+    if (true != physical_pb.valid_pb_id(des_pb_id)) {
+      mux_input_pin_id = DEFAULT_PATH_ID;
+    } else { 
+      for (t_pb_graph_pin* src_pb_graph_pin : pb_graph_pin_inputs(des_pb_graph_pin, cur_interc)) {
+        const PhysicalPbId& src_pb_id = physical_pb.find_pb(src_pb_graph_pin->parent_node);
+        /* If the src pb id is not valid, we bypass it */
+        if ( (true != physical_pb.valid_pb_id(src_pb_id))
+          && (physical_pb.pb_graph_pin_atom_net(src_pb_id, src_pb_graph_pin) == physical_pb.pb_graph_pin_atom_net(des_pb_id, des_pb_graph_pin))) {
+          break;
+        }
+        mux_input_pin_id++;
+      }
+      VTR_ASSERT (mux_input_pin_id <= fan_in);
+      /* Unmapped pin, use default path id */
+      if (fan_in == mux_input_pin_id) {
+        mux_input_pin_id = DEFAULT_PATH_ID;
+      }
+    }
+
+    /* Generate bitstream depend on both technology and structure of this MUX */
+    std::vector<bool> mux_bitstream = build_mux_bitstream(circuit_lib, mux_model, mux_lib, datapath_mux_size, mux_input_pin_id); 
+
+    /* Create the block denoting the memory instances that drives this node in physical_block */
+    std::string mem_block_name = generate_pb_memory_instance_name(GRID_MEM_INSTANCE_PREFIX, des_pb_graph_pin, std::string(""));
+    ConfigBlockId mux_mem_block = bitstream_manager.add_block(mem_block_name);
+    bitstream_manager.add_child_block(parent_configurable_block, mux_mem_block);
+  
+    /* Find the module in module manager and ensure the bitstream size matches! */
+    std::string mem_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string(MEMORY_MODULE_POSTFIX)); 
+    ModuleId mux_mem_module = module_manager.find_module(mem_module_name); 
+    VTR_ASSERT (true == module_manager.valid_module_id(mux_mem_module));
+    ModulePortId mux_mem_out_port_id = module_manager.find_module_port(mux_mem_module, generate_configuration_chain_data_out_name());
+    VTR_ASSERT(mux_bitstream.size() == module_manager.module_port(mux_mem_module, mux_mem_out_port_id).get_width());
+  
+    /* Add the bistream to the bitstream manager */
+    for (const bool& bit : mux_bitstream) {
+      ConfigBitId config_bit = bitstream_manager.add_bit(bit);
+      /* Link the memory bits to the mux mem block */
+      bitstream_manager.add_bit_to_block(mux_mem_block, config_bit);
+    }
+    break;
+  }
+  default:
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid interconnection type for %s (Arch[LINE%d])!\n",
+                   cur_interc->name, cur_interc->line_num);
+    exit(1);
+  }
+}
+
+/********************************************************************
+ * This function generates bitstream for the programmable routing
+ * multiplexers in a pb_graph node 
+ *******************************************************************/
+static 
+void build_physical_block_interc_port_bitstream(BitstreamManager& bitstream_manager,
+                                                const ConfigBlockId& parent_configurable_block,
+                                                const ModuleManager& module_manager,
+                                                const CircuitLibrary& circuit_lib,
+                                                const MuxLibrary& mux_lib,
+                                                const VprDeviceAnnotation& device_annotation,
+                                                t_pb_graph_node* physical_pb_graph_node,
+                                                const PhysicalPb& physical_pb,
+                                                const e_circuit_pb_port_type& pb_port_type,
+                                                t_mode* physical_mode) {
+  switch (pb_port_type) {
+  case CIRCUIT_PB_PORT_INPUT:
+    for (int iport = 0; iport < physical_pb_graph_node->num_input_ports; ++iport) {
+      for (int ipin = 0; ipin < physical_pb_graph_node->num_input_pins[iport]; ++ipin) {
+        build_physical_block_pin_interc_bitstream(bitstream_manager, parent_configurable_block,
+                                                  module_manager, circuit_lib, mux_lib,
+                                                  device_annotation,
+                                                  physical_pb,
+                                                  &(physical_pb_graph_node->input_pins[iport][ipin]),
+                                                  physical_mode);
+      }
+    }
+    break;
+  case CIRCUIT_PB_PORT_OUTPUT:
+    for (int iport = 0; iport < physical_pb_graph_node->num_output_ports; ++iport) {
+      for (int ipin = 0; ipin < physical_pb_graph_node->num_output_pins[iport]; ++ipin) {
+        build_physical_block_pin_interc_bitstream(bitstream_manager, parent_configurable_block,
+                                                  module_manager, circuit_lib, mux_lib,
+                                                  device_annotation,
+                                                  physical_pb,
+                                                  &(physical_pb_graph_node->output_pins[iport][ipin]),
+                                                  physical_mode);
+      }
+    }
+    break;
+  case CIRCUIT_PB_PORT_CLOCK:
+    for (int iport = 0; iport < physical_pb_graph_node->num_clock_ports; ++iport) {
+      for (int ipin = 0; ipin < physical_pb_graph_node->num_clock_pins[iport]; ++ipin) {
+        build_physical_block_pin_interc_bitstream(bitstream_manager, parent_configurable_block,
+                                                  module_manager, circuit_lib, mux_lib,
+                                                  device_annotation,
+                                                  physical_pb,
+                                                  &(physical_pb_graph_node->clock_pins[iport][ipin]),
+                                                  physical_mode);
+
+      }
+    }
+    break;
+  default:
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid pb port type!\n");
+    exit(1);
+  }
+}
+
+/********************************************************************
+ * This function generates bitstream for the programmable routing
+ * multiplexers in a pb_graph node 
+ *******************************************************************/
+static 
+void build_physical_block_interc_bitstream(BitstreamManager& bitstream_manager,
+                                           const ConfigBlockId& parent_configurable_block,
+                                           const ModuleManager& module_manager,
+                                           const CircuitLibrary& circuit_lib,
+                                           const MuxLibrary& mux_lib,
+                                           const VprDeviceAnnotation& device_annotation,
+                                           t_pb_graph_node* physical_pb_graph_node,
+                                           const PhysicalPb& physical_pb,
+                                           t_mode* physical_mode) {
+  /* Check if the pb_graph node is valid or not */
+  if (nullptr == physical_pb_graph_node) {
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid physical_pb_graph_node.\n"); 
+    exit(1);
+  }
+
+  /* We check output_pins of physical_pb_graph_node and its the input_edges
+   * Iterate over the interconnections between outputs of physical_pb_graph_node 
+   * and outputs of child_pb_graph_node
+   *   child_pb_graph_node.output_pins -----------------> physical_pb_graph_node.outpins
+   *                                        /|\
+   *                                         |
+   *                         input_pins,   edges,       output_pins
+   * Note: it is not applied to primitive pb_type!
+   */ 
+  build_physical_block_interc_port_bitstream(bitstream_manager, parent_configurable_block,
+                                             module_manager, circuit_lib, mux_lib, 
+                                             device_annotation, 
+                                             physical_pb_graph_node, physical_pb,  
+                                             CIRCUIT_PB_PORT_OUTPUT, physical_mode);
+ 
+  /* We check input_pins of child_pb_graph_node and its the input_edges
+   * Iterate over the interconnections between inputs of physical_pb_graph_node 
+   * and inputs of child_pb_graph_node
+   *   physical_pb_graph_node.input_pins -----------------> child_pb_graph_node.input_pins
+   *                                        /|\
+   *                                         |
+   *                         input_pins,   edges,       output_pins
+   */ 
+  for (int ipb = 0; ipb < physical_mode->num_pb_type_children; ipb++) {
+    for (int jpb = 0; jpb < physical_mode->pb_type_children[ipb].num_pb; jpb++) {
+      t_pb_graph_node* child_pb_graph_node = &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb][jpb]);
+
+      /* For each child_pb_graph_node input pins*/
+      build_physical_block_interc_port_bitstream(bitstream_manager, parent_configurable_block,
+                                                 module_manager, circuit_lib, mux_lib, 
+                                                 device_annotation, 
+                                                 child_pb_graph_node, physical_pb,  
+                                                 CIRCUIT_PB_PORT_INPUT, physical_mode);
+      /* For clock pins, we should do the same work */
+      build_physical_block_interc_port_bitstream(bitstream_manager, parent_configurable_block,
+                                                 module_manager, circuit_lib, mux_lib, 
+                                                 device_annotation, 
+                                                 child_pb_graph_node, physical_pb,  
+                                                 CIRCUIT_PB_PORT_CLOCK, physical_mode);
+    }
+  }
+}
+
 /********************************************************************
  * This function generates bitstream for a physical block, which is 
  * a child block of a grid 
@@ -168,8 +393,10 @@ void rec_build_physical_block_bitstream(BitstreamManager& bitstream_manager,
 
   /* Check if this has defined a circuit_model*/
   if (true == is_primitive_pb_type(physical_pb_type)) { 
-    switch (physical_pb_type->class_type) {
-    case LUT_CLASS: 
+    CircuitModelId primitive_circuit_model = device_annotation.pb_type_circuit_model(physical_pb_type);
+    VTR_ASSERT(CircuitModelId::INVALID() != primitive_circuit_model);
+    switch (circuit_lib.model_type(primitive_circuit_model)) {
+    case CIRCUIT_MODEL_LUT: 
       /* Special case for LUT !!!
        * Mapped logical block information is stored in child_pbs of this pb!!!
        */
@@ -177,9 +404,9 @@ void rec_build_physical_block_bitstream(BitstreamManager& bitstream_manager,
       //                    module_manager, circuit_lib, mux_lib, 
       //                    physical_pb, pb_id, physical_pb_type);
       break;
-    case LATCH_CLASS:
-    case UNKNOWN_CLASS:
-    case MEMORY_CLASS:
+    case CIRCUIT_MODEL_FF:
+    case CIRCUIT_MODEL_HARDLOGIC:
+    case CIRCUIT_MODEL_IOPAD:
       /* For other types of blocks, we can apply a generic therapy */
       build_primitive_bitstream(bitstream_manager, pb_configurable_block,
                                 module_manager, circuit_lib, device_annotation, 
@@ -187,7 +414,7 @@ void rec_build_physical_block_bitstream(BitstreamManager& bitstream_manager,
       break;  
     default:
       VTR_LOGF_ERROR(__FILE__, __LINE__, 
-                     "Unknown class type of pb_type '%s'!\n",
+                     "Unknown circuit model type of pb_type '%s'!\n",
                      physical_pb_type->name);
       exit(1);
     }
@@ -196,10 +423,11 @@ void rec_build_physical_block_bitstream(BitstreamManager& bitstream_manager,
   }
 
   /* Generate the bitstream for the interconnection in this physical block */
-  //build_physical_block_interc_bitstream(bitstream_manager, pb_configurable_block,
-  //                                      module_manager, circuit_lib, mux_lib,
-  //                                      physical_pb_graph_node, physical_pb,
-  //                                      pb_id, physical_mode_index);
+  build_physical_block_interc_bitstream(bitstream_manager, pb_configurable_block,
+                                        module_manager, circuit_lib, mux_lib,
+                                        device_annotation,
+                                        physical_pb_graph_node, physical_pb,
+                                        physical_mode);
 }
 
 /********************************************************************
diff --git a/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp b/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp
index e0dd75c2a..5b4fadb09 100644
--- a/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp
+++ b/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp
@@ -435,7 +435,7 @@ void build_routing_bitstream(BitstreamManager& bitstream_manager,
                                     device_annotation, routing_annotation,
                                     rr_graph,
                                     device_rr_gsb, CHANY);
-  VTR_LOG("Done");
+  VTR_LOG("Done\n");
 
 }
 

From 2d86a02358278e85c6d2cc4cd550ffd7927dfe95 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 25 Feb 2020 12:45:13 -0700
Subject: [PATCH 205/645] refactored LUT bitstream generation to use vtr logic

---
 libs/libvtrutil/src/vtr_logic.h  |   7 +-
 openfpga/src/utils/lut_utils.cpp | 395 ++++++++++++++++++++++++++++++-
 openfpga/src/utils/lut_utils.h   |  19 ++
 3 files changed, 419 insertions(+), 2 deletions(-)

diff --git a/libs/libvtrutil/src/vtr_logic.h b/libs/libvtrutil/src/vtr_logic.h
index 2287f3383..c1ab29462 100644
--- a/libs/libvtrutil/src/vtr_logic.h
+++ b/libs/libvtrutil/src/vtr_logic.h
@@ -1,15 +1,20 @@
 #ifndef VTR_LOGIC_H
 #define VTR_LOGIC_H
 
+#include <array>
+
 namespace vtr {
 
 enum class LogicValue {
     FALSE = 0,
     TRUE = 1,
     DONT_CARE = 2,
-    UNKOWN = 3
+    UNKOWN = 3,
+    NUM_LOGIC_VALUE_TYPES
 };
 
+constexpr std::array<const char*, size_t(LogicValue::NUM_LOGIC_VALUE_TYPES)> LOGIC_VALUE_STRING = {{"false", "true", "don't care", "unknown"}};
+
 } // namespace vtr
 
 #endif
diff --git a/openfpga/src/utils/lut_utils.cpp b/openfpga/src/utils/lut_utils.cpp
index e2b01edb5..b8b96f74b 100644
--- a/openfpga/src/utils/lut_utils.cpp
+++ b/openfpga/src/utils/lut_utils.cpp
@@ -2,10 +2,15 @@
  * This file includes most utilized functions to manipulate LUTs, 
  * especially their truth tables, in the OpenFPGA context
  *******************************************************************/
+#include <cmath>
+
 /* Headers from vtrutil library */
 #include "vtr_assert.h"
 #include "vtr_log.h"
 
+/* Headers from openfpgautil library */
+#include "openfpga_decode.h"
+
 #include "lut_utils.h"
 
 /* begin namespace openfpga */
@@ -29,6 +34,21 @@ namespace openfpga {
  *   Truth table line:       00111
  *   rotated_pin_map:        2310
  *   Adapt truth table line: 11001     
+ *
+ * An illustrative example: 
+ *          
+ *          Original Truth Table       Post VPR Truth Table
+ *
+ *               +-------+                  +-------+
+ *      net0 --->|       |          net1--->|       |
+ *      net1 --->|  LUT  |          net0--->|  LUT  |
+ *           ... |       |              ... |       |
+ *               +-------+                  +-------+
+ *
+ *         Truth table line             Truth table line
+ *     .names net0 net1 out          .names net1 net0 out
+ *     01 1                          10 1
+ *
  *******************************************************************/
 AtomNetlist::TruthTable lut_truth_table_adaption(const AtomNetlist::TruthTable& orig_tt, 
                                                  const std::vector<int>& rotated_pin_map) {
@@ -89,5 +109,378 @@ std::vector<std::string> truth_table_to_string(const AtomNetlist::TruthTable& tt
   return tt_str;
 }
 
-} /* end namespace openfpga */
+/********************************************************************
+ * Adapt the truth table from the short-wire connection 
+ * from the input nets of a LUT to an output of a LUT
+ * 
+ *                  LUT
+ *                +-------------+
+ *   lut_input--->|----+        |
+ *                |    |        |
+ *                |    +------->|---> lut_output
+ *                |             |
+ *                +-------------+
+ *
+ * In this case, LUT is configured as a wiring module
+ * This function will generate a truth for the wiring LUT
+ *
+ * For example: 
+ * The truth table of the case where the 3rd input of 
+ * a 4-input LUT is wired to output 
+ *    
+ *    --1- 1
+ * 
+ ********************************************************************/
+AtomNetlist::TruthTable build_post_routing_wired_lut_truth_table(const size_t& lut_size, 
+                                                                 const size_t& wire_input_id) {
+  AtomNetlist::TruthTable tt;
+  
+  /* There is always only one line in this truth table */
+  tt.resize(1);
 
+  /* Pre-allocate the truth table: 
+   * Each truth table line is organized in BLIF format:
+   *     |<---LUT size--->|
+   *   < a string of 0 or 1> <0 or 1>
+   * The first <lut_size> of characters represent the input values of each LUT input
+   * Here, we add 2 characters, which denote the space and a digit (0|1)
+   * By default, we set all the inputs as don't care value '-'
+   *
+   * For more details, please refer to the BLIF format documentation
+   */
+  tt[0].resize(lut_size, vtr::LogicValue::DONT_CARE);
+  /* Fill the truth table !!! */
+  VTR_ASSERT(wire_input_id < lut_size);
+  tt[0][wire_input_id] = vtr::LogicValue::TRUE; 
+  tt[0].push_back(vtr::LogicValue::TRUE);
+
+  return tt;
+}
+
+/********************************************************************
+ * Adapt truth table for a fracturable LUT
+ * Determine fixed input bits for this truth table:
+ * 1. input bits within frac_level (all '-' if not specified) 
+ * 2. input bits outside frac_level, decoded to its output mask (0 -> first part -> all '1') 
+ *
+ * For example: 
+ *   A 4-input function is mapped to input[0..3] of a 6-input fracturable LUT 
+ *   Plus, it uses the 2nd output of the fracturable LUT
+ *   The truth table of the 4-input function is
+ *     1001 1
+ *   while truth table of a 6-input LUT requires 6 characters
+ *   Therefore, it must be adapted by adding mask bits, which are
+ *   a number of fixed digits to configure the fracturable LUT to
+ *   operate in a 4-input LUT mode
+ *   The mask bits can be decoded from the index of output used in the fracturable LUT
+ *   For the 2nd output, it will be '01', the binary representation of index '1'
+ *   Now the truth table will be adapt to
+ *     100101 1
+ *   where the first 4 digits come from the original truth table
+ *   the 2 following digits are mask bits
+ *   
+ ********************************************************************/
+AtomNetlist::TruthTable adapt_truth_table_for_frac_lut(const size_t& lut_frac_level,
+                                                       const size_t& lut_output_mask,
+                                                       const AtomNetlist::TruthTable& truth_table) {
+  /* No adaption required for when the lut_frac_level is not set */
+  if (size_t(OPEN) == lut_frac_level) {
+    return truth_table;
+  }
+
+  AtomNetlist::TruthTable adapt_truth_table;
+
+  /* Apply modification to the truth table */
+  for (const std::vector<vtr::LogicValue>& tt_line : truth_table) {
+    /* Last element is the output */
+    size_t lut_size = tt_line.size() - 1;
+    /* Get the number of bits to be masked (modified) */
+    int num_mask_bits = lut_size - lut_frac_level;
+    /* Check if we need to modify any bits */
+    VTR_ASSERT(0 <= num_mask_bits);
+    if ( 0 == num_mask_bits ) {
+      /* No modification needed, push to adapted truth table */
+      adapt_truth_table.push_back(tt_line);
+      continue;
+    }
+    /* Modify bits starting from lut_frac_level */
+    /* Decode the lut_output_mask to LUT input codes */ 
+    int temp = pow(2., num_mask_bits) - 1 - lut_output_mask;
+    VTR_ASSERT(0 <= temp);
+    std::vector<size_t> mask_bits_vec = itobin_vec(temp, num_mask_bits);
+    /* Copy the bits to the truth table line */
+    std::vector<vtr::LogicValue> adapt_tt_line = tt_line;
+    for (size_t itt = lut_frac_level; itt < lut_frac_level + mask_bits_vec.size(); ++itt) { 
+      
+      vtr::LogicValue logic_val = vtr::LogicValue::FALSE;
+      VTR_ASSERT( (1 == mask_bits_vec[itt - lut_frac_level])
+               || (0 == mask_bits_vec[itt - lut_frac_level]) );
+      if (1 == mask_bits_vec[itt - lut_frac_level]) {
+        logic_val = vtr::LogicValue::TRUE;
+      }
+      adapt_tt_line[itt] = logic_val;
+    }
+
+    /* Push to adapted truth table */
+    adapt_truth_table.push_back(adapt_tt_line);
+  }
+
+  return adapt_truth_table;
+}
+
+/********************************************************************
+ * Determine if the truth table of a LUT is a on-set or a off-set
+ *  - An on-set is defined as the truth table lines are ended with logic '1'
+ *  - An off-set is defined as the truth table lines are ended with logic '0'
+ *******************************************************************/
+bool lut_truth_table_use_on_set(const AtomNetlist::TruthTable& truth_table) {
+  bool on_set = false;
+  bool off_set = false;
+
+  for (const std::vector<vtr::LogicValue>& tt_line : truth_table) {
+    switch (tt_line.back()) {
+    case vtr::LogicValue::TRUE :
+      on_set = true;
+      break;
+    case vtr::LogicValue::FALSE :
+      off_set = true;
+      break;
+    default:
+      VTR_LOGF_ERROR(__FILE__, __LINE__, 
+                     "Invalid truth_table_line ending '%s'!\n",
+                     vtr::LOGIC_VALUE_STRING[size_t(tt_line.back())]);
+      exit(1);
+    }
+  }
+
+  /* Prefer on_set if both are true */
+  if (true == on_set && true == off_set) {
+    on_set = true; 
+    off_set = false;
+  }
+  VTR_ASSERT(on_set == !off_set);
+
+  return on_set;
+}
+
+/********************************************************************
+ * Complete a line in truth table with a given lut size
+ * Due to the size of truth table may be less than the lut size.
+ * i.e. in LUT-6 architecture, there exists LUT1-6 in technology-mapped netlists
+ * So, in truth table line, there may be 10- 1
+ * In this case, we should complete it by --10- 1
+ *******************************************************************/
+static 
+std::vector<vtr::LogicValue> complete_truth_table_line(const size_t& lut_size,
+                                                       const std::vector<vtr::LogicValue>& tt_line) {
+  std::vector<vtr::LogicValue> ret;
+
+  VTR_ASSERT(0 < tt_line.size());
+
+  /* Complete the truth table line*/
+  size_t cover_len = tt_line.size() - 1; 
+  VTR_ASSERT(cover_len <= lut_size);
+
+  /* Copy the original truth table line */ 
+  ret = tt_line;
+  /* Kick out the last value for now as it is the output value */
+  ret.pop_back();
+
+  /* Add the number of '-' we should add in the back !!! */
+  for (size_t j = cover_len; j < lut_size; ++j) {
+    ret.push_back(vtr::LogicValue::DONT_CARE);
+  }
+
+  /* Copy the original truth table line */ 
+  ret.push_back(tt_line.back());
+
+  /* Check if the size of ret matches our expectation */
+  VTR_ASSERT(lut_size + 1 == ret.size());
+  
+  return ret;
+}
+
+/********************************************************************
+ * For each lut_bit_lines, we should recover the truth table,
+ * and then set the sram bits to "1" if the truth table defines so.
+ * Start_point: the position we start converting don't care sign '-'
+ *              to explicit '0' or '1'
+ *******************************************************************/
+static 
+void rec_build_lut_bitstream_per_line(std::vector<bool>& lut_bitstream, 
+                                      const size_t& lut_size,
+                                      const std::vector<vtr::LogicValue>& tt_line,
+                                      const size_t& start_point) {
+  std::vector<vtr::LogicValue> temp_line = tt_line;
+
+  /* Check the length of sram bits and truth table line */
+  VTR_ASSERT(lut_size + 1 == tt_line.size()); /* lut_size + '1|0' */
+
+  /* End of truth_table_line should be "space" and "1" */ 
+  VTR_ASSERT( (vtr::LogicValue::TRUE == tt_line.back())
+           || (vtr::LogicValue::FALSE == tt_line.back()) );
+
+  /* Make sure before start point there is no '-' */
+  VTR_ASSERT(start_point < tt_line.size());
+  for (size_t i = 0; i < start_point; ++i) {
+    VTR_ASSERT(vtr::LogicValue::DONT_CARE != tt_line[i]);
+  }
+
+  /* Configure sram bits recursively */
+  for (size_t i = start_point; i < lut_size; ++i) {
+    if (vtr::LogicValue::DONT_CARE == tt_line[i]) {
+      /* if we find a dont_care, we don't do configure now but recursively*/
+      /* '0' branch */
+      temp_line[i] = vtr::LogicValue::FALSE; 
+      rec_build_lut_bitstream_per_line(lut_bitstream, lut_size, temp_line, start_point + 1);
+      /* '1' branch */
+      temp_line[i] = vtr::LogicValue::TRUE; 
+      rec_build_lut_bitstream_per_line(lut_bitstream, lut_size, temp_line, start_point + 1);
+      return; 
+    }
+  }
+
+  /* TODO: Use MuxGraph to decode this!!! */
+  /* Decode bitstream only when there are only 0 or 1 in the truth table */
+  size_t sram_id = 0;
+  for (size_t i = 0; i < lut_size; ++i) {
+    /* Should be either '0' or '1' */
+    switch (tt_line[i]) {
+    case vtr::LogicValue::FALSE :
+      /* We assume the 1-lut pass sram1 when input = 0 */
+      sram_id += (size_t)pow(2., (double)(i));
+      break;
+    case vtr::LogicValue::TRUE :
+      /* We assume the 1-lut pass sram0 when input = 1 */
+      break;
+    case vtr::LogicValue::DONT_CARE :
+    default :
+      VTR_LOGF_ERROR(__FILE__, __LINE__, 
+                     "Invalid truth_table bit '%s', should be [0|1|]!\n",
+                     vtr::LOGIC_VALUE_STRING[size_t(tt_line[i])]); 
+      exit(1);
+    }
+  }
+  /* Set the sram bit to '1'*/
+  VTR_ASSERT(sram_id < lut_bitstream.size());
+  if (vtr::LogicValue::TRUE == tt_line.back()) {
+    lut_bitstream[sram_id] = true; /* on set*/
+  } else if (vtr::LogicValue::FALSE == tt_line.back()) {
+    lut_bitstream[sram_id] = false; /* off set */
+  } else {
+    VTR_LOGF_ERROR(__FILE__, __LINE__, 
+                   "Invalid truth_table_line ending '%s'!\n",
+                   vtr::LOGIC_VALUE_STRING[size_t(tt_line.back())]);
+    exit(1);
+  }
+}
+
+/********************************************************************
+ * Generate the bitstream for a single-output LUT with a given truth table
+ * As truth tables may come from different logic blocks, truth tables could be in on and off sets
+ * We first build a base SRAM bits, where different parts are set to tbe on/off sets 
+ * Then, we can decode SRAM bits as regular process 
+ *******************************************************************/
+static 
+std::vector<bool> build_single_output_lut_bitstream(const AtomNetlist::TruthTable& truth_table,
+                                                    const MuxGraph& lut_mux_graph,
+                                                    const size_t& default_sram_bit_value) {
+  size_t lut_size = lut_mux_graph.num_memory_bits();
+  size_t bitstream_size = lut_mux_graph.num_inputs();
+  std::vector<bool> lut_bitstream(bitstream_size, false);
+  AtomNetlist::TruthTable completed_truth_table;
+  bool on_set = false;
+  bool off_set = false;
+
+  /* if No truth_table, do default*/
+  if (0 == truth_table.size()) {
+    switch (default_sram_bit_value) {
+    case 0:
+      on_set = true;
+      off_set = false;
+      break;
+    case 1:
+      on_set = false;
+      off_set = true;
+      break;
+    default:
+      VTR_LOGF_ERROR(__FILE__, __LINE__,
+                     "Invalid default_signal_init_value '%lu'!\n",
+                     default_sram_bit_value);
+      exit(1);
+    }
+  } else {
+    on_set = lut_truth_table_use_on_set(truth_table);
+    off_set = !on_set;
+  }
+
+  /* Read in truth table lines, decode one by one */
+  for (const std::vector<vtr::LogicValue>& tt_line : truth_table) {
+    /* Complete the truth table line by line*/
+    completed_truth_table.push_back(complete_truth_table_line(lut_size, tt_line));
+  }
+
+  /* Initial all the bits in the bitstream */
+  if (true == off_set) {
+    /* By default, the lut_bitstream is initialize for on_set
+     * For off set, it should be flipped
+     */
+    lut_bitstream.clear(); 
+    lut_bitstream.resize(bitstream_size, true);
+  }
+
+  for (const std::vector<vtr::LogicValue>& tt_line : completed_truth_table) {
+    /* Update the truth table, sram_bits */
+    rec_build_lut_bitstream_per_line(lut_bitstream, lut_size, tt_line, 0);
+  }
+
+  return lut_bitstream;
+}
+
+/********************************************************************
+ * Generate bitstream for a fracturable LUT (also applicable to single-output LUT)
+ * Check type of truth table of each mapped logical block
+ * if it is on-set, we give a all 0 base bitstream
+ * if it is off-set, we give a all 1 base bitstream
+ *******************************************************************/
+std::vector<bool> build_frac_lut_bitstream(const CircuitLibrary& circuit_lib,
+                                           const MuxGraph& lut_mux_graph, 
+                                           const VprDeviceAnnotation& device_annotation, 
+                                           const std::map<t_pb_graph_pin*, AtomNetlist::TruthTable>& truth_tables,
+                                           const size_t& default_sram_bit_value) {
+  /* Initialization */
+  std::vector<bool> lut_bitstream(lut_mux_graph.num_inputs(), default_sram_bit_value);
+
+  for (const std::pair<t_pb_graph_pin*, AtomNetlist::TruthTable>& element : truth_tables) {
+    /* Find the corresponding circuit model output port and assoicated lut_output_mask */
+    CircuitPortId lut_model_output_port = device_annotation.pb_circuit_port(element.first->port);
+    size_t lut_frac_level = circuit_lib.port_lut_frac_level(lut_model_output_port);
+    /* By default, lut_frac_level will be the lut_size, i.e., number of levels of the mux graph */
+    if (size_t(-1) == lut_frac_level) {
+      lut_frac_level = lut_mux_graph.num_levels();
+    }
+
+    /* Find the corresponding circuit model output port and assoicated lut_output_mask */
+    size_t lut_output_mask = circuit_lib.port_lut_output_mask(lut_model_output_port)[element.first->pin_number];
+
+    /* Decode lut sram bits */
+    std::vector<bool> temp_bitstream = build_single_output_lut_bitstream(element.second, lut_mux_graph, default_sram_bit_value); 
+
+    /* Depending on the frac-level, we get the location(starting/end points) of sram bits */
+    size_t length_of_temp_bitstream_to_copy = (size_t)pow(2., (double)(lut_frac_level)); 
+    size_t bitstream_offset = length_of_temp_bitstream_to_copy * lut_output_mask; 
+    /* Ensure the offset is in range */        
+    VTR_ASSERT(bitstream_offset < lut_bitstream.size());
+    VTR_ASSERT(bitstream_offset + length_of_temp_bitstream_to_copy <= lut_bitstream.size());
+
+    /* Copy to the segment of bitstream */
+    for (size_t bit = bitstream_offset; bit < bitstream_offset + length_of_temp_bitstream_to_copy; ++bit) {
+      lut_bitstream[bit] = temp_bitstream[bit];
+    }
+  }
+
+  return lut_bitstream; 
+}
+
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/utils/lut_utils.h b/openfpga/src/utils/lut_utils.h
index 800c1fc59..a1d713f25 100644
--- a/openfpga/src/utils/lut_utils.h
+++ b/openfpga/src/utils/lut_utils.h
@@ -6,7 +6,11 @@
  *******************************************************************/
 #include <string>
 #include <vector>
+#include <map>
 #include "atom_netlist.h"
+#include "mux_graph.h"
+#include "physical_types.h"
+#include "vpr_device_annotation.h"
 
 /********************************************************************
  * Function declaration
@@ -20,6 +24,21 @@ AtomNetlist::TruthTable lut_truth_table_adaption(const AtomNetlist::TruthTable&
 
 std::vector<std::string> truth_table_to_string(const AtomNetlist::TruthTable& tt);
 
+AtomNetlist::TruthTable build_post_routing_wired_lut_truth_table(const size_t& lut_size, 
+                                                                 const size_t& wire_input_id);
+
+AtomNetlist::TruthTable adapt_truth_table_for_frac_lut(const size_t& lut_frac_level,
+                                                       const size_t& lut_output_mask,
+                                                       const AtomNetlist::TruthTable& truth_table);
+
+bool lut_truth_table_use_on_set(const AtomNetlist::TruthTable& truth_table);
+
+std::vector<bool> build_frac_lut_bitstream(const CircuitLibrary& circuit_lib,
+                                           const MuxGraph& lut_mux_graph, 
+                                           const VprDeviceAnnotation& device_annotation, 
+                                           const std::map<t_pb_graph_pin*, AtomNetlist::TruthTable>& truth_tables,
+                                           const size_t& default_sram_bit_value);
+
 } /* end namespace openfpga */
 
 #endif

From ca038857d3b5988e439150d4b43be83dc4c6ce59 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 25 Feb 2020 13:34:13 -0700
Subject: [PATCH 206/645] add lut physical truth table to physical pb

---
 openfpga/src/repack/physical_pb.cpp      | 15 ++++++++++++++-
 openfpga/src/repack/physical_pb.h        | 10 +++++++++-
 openfpga/src/utils/lut_utils.cpp         |  4 ++--
 openfpga/src/utils/lut_utils.h           |  2 +-
 openfpga/src/utils/physical_pb_utils.cpp |  2 +-
 5 files changed, 27 insertions(+), 6 deletions(-)

diff --git a/openfpga/src/repack/physical_pb.cpp b/openfpga/src/repack/physical_pb.cpp
index f64a3d29a..a29b6d401 100644
--- a/openfpga/src/repack/physical_pb.cpp
+++ b/openfpga/src/repack/physical_pb.cpp
@@ -50,6 +50,7 @@ PhysicalPbId PhysicalPb::child(const PhysicalPbId& pb,
 
 std::vector<AtomBlockId> PhysicalPb::atom_blocks(const PhysicalPbId& pb) const {
   VTR_ASSERT(true == valid_pb_id(pb));
+  
   return atom_blocks_[pb];
 }
 
@@ -64,6 +65,11 @@ AtomNetId PhysicalPb::pb_graph_pin_atom_net(const PhysicalPbId& pb,
   return AtomNetId::INVALID();
 }
 
+AtomNetlist::TruthTable PhysicalPb::truth_table(const PhysicalPbId& pb) const {
+  VTR_ASSERT(true == valid_pb_id(pb));
+  return truth_tables_[pb];
+}
+
 std::vector<size_t> PhysicalPb::mode_bits(const PhysicalPbId& pb) const {
   VTR_ASSERT(true == valid_pb_id(pb));
   return mode_bits_[pb];
@@ -118,6 +124,13 @@ void PhysicalPb::add_child(const PhysicalPbId& parent,
   parent_pbs_[child] = parent;
 }
 
+void PhysicalPb::set_truth_table(const PhysicalPbId& pb,
+                                 const AtomNetlist::TruthTable& truth_table) {
+  VTR_ASSERT(true == valid_pb_id(pb)); 
+   
+  truth_tables_[pb] = truth_table;
+}
+
 void PhysicalPb::set_mode_bits(const PhysicalPbId& pb,
                                const std::vector<size_t>& mode_bits) {
   VTR_ASSERT(true == valid_pb_id(pb)); 
@@ -128,7 +141,7 @@ void PhysicalPb::set_mode_bits(const PhysicalPbId& pb,
 void PhysicalPb::add_atom_block(const PhysicalPbId& pb,
                                 const AtomBlockId& atom_block) {
   VTR_ASSERT(true == valid_pb_id(pb)); 
-   
+  
   atom_blocks_[pb].push_back(atom_block);
 }
 
diff --git a/openfpga/src/repack/physical_pb.h b/openfpga/src/repack/physical_pb.h
index 2ad29c2cd..d5f5b00a3 100644
--- a/openfpga/src/repack/physical_pb.h
+++ b/openfpga/src/repack/physical_pb.h
@@ -12,7 +12,7 @@
 #include "physical_types.h"
 
 /* Headers from vpr library */
-#include "atom_netlist_fwd.h"
+#include "atom_netlist.h"
 
 #include "physical_pb_fwd.h"
 
@@ -48,6 +48,7 @@ class PhysicalPb {
     std::vector<AtomBlockId> atom_blocks(const PhysicalPbId& pb) const;
     AtomNetId pb_graph_pin_atom_net(const PhysicalPbId& pb,
                                     const t_pb_graph_pin* pb_graph_pin) const;
+    AtomNetlist::TruthTable truth_table(const PhysicalPbId& pb) const;
     std::vector<size_t> mode_bits(const PhysicalPbId& pb) const;
   public: /* Public mutators */
     PhysicalPbId create_pb(const t_pb_graph_node* pb_graph_node);
@@ -56,6 +57,8 @@ class PhysicalPb {
                    const t_pb_type* child_type);
     void add_atom_block(const PhysicalPbId& pb,
                         const AtomBlockId& atom_block);
+    void set_truth_table(const PhysicalPbId& pb,
+                         const AtomNetlist::TruthTable& truth_table);
     void set_mode_bits(const PhysicalPbId& pb,
                        const std::vector<size_t>& mode_bits);
     void set_pb_graph_pin_atom_net(const PhysicalPbId& pb,
@@ -75,6 +78,11 @@ class PhysicalPb {
     vtr::vector<PhysicalPbId, std::map<const t_pb_type*, std::vector<PhysicalPbId>>> child_pbs_;
     vtr::vector<PhysicalPbId, PhysicalPbId> parent_pbs_;
 
+    /* configuration bits 
+     * Truth tables and mode selection
+     */
+    vtr::vector<PhysicalPbId, AtomNetlist::TruthTable> truth_tables_;
+
     vtr::vector<PhysicalPbId, std::vector<size_t>> mode_bits_;
 
     /* Fast lookup */
diff --git a/openfpga/src/utils/lut_utils.cpp b/openfpga/src/utils/lut_utils.cpp
index b8b96f74b..16bb8c3f2 100644
--- a/openfpga/src/utils/lut_utils.cpp
+++ b/openfpga/src/utils/lut_utils.cpp
@@ -446,12 +446,12 @@ std::vector<bool> build_single_output_lut_bitstream(const AtomNetlist::TruthTabl
 std::vector<bool> build_frac_lut_bitstream(const CircuitLibrary& circuit_lib,
                                            const MuxGraph& lut_mux_graph, 
                                            const VprDeviceAnnotation& device_annotation, 
-                                           const std::map<t_pb_graph_pin*, AtomNetlist::TruthTable>& truth_tables,
+                                           const std::map<const t_pb_graph_pin*, AtomNetlist::TruthTable>& truth_tables,
                                            const size_t& default_sram_bit_value) {
   /* Initialization */
   std::vector<bool> lut_bitstream(lut_mux_graph.num_inputs(), default_sram_bit_value);
 
-  for (const std::pair<t_pb_graph_pin*, AtomNetlist::TruthTable>& element : truth_tables) {
+  for (const std::pair<const t_pb_graph_pin*, AtomNetlist::TruthTable>& element : truth_tables) {
     /* Find the corresponding circuit model output port and assoicated lut_output_mask */
     CircuitPortId lut_model_output_port = device_annotation.pb_circuit_port(element.first->port);
     size_t lut_frac_level = circuit_lib.port_lut_frac_level(lut_model_output_port);
diff --git a/openfpga/src/utils/lut_utils.h b/openfpga/src/utils/lut_utils.h
index a1d713f25..21f638175 100644
--- a/openfpga/src/utils/lut_utils.h
+++ b/openfpga/src/utils/lut_utils.h
@@ -36,7 +36,7 @@ bool lut_truth_table_use_on_set(const AtomNetlist::TruthTable& truth_table);
 std::vector<bool> build_frac_lut_bitstream(const CircuitLibrary& circuit_lib,
                                            const MuxGraph& lut_mux_graph, 
                                            const VprDeviceAnnotation& device_annotation, 
-                                           const std::map<t_pb_graph_pin*, AtomNetlist::TruthTable>& truth_tables,
+                                           const std::map<const t_pb_graph_pin*, AtomNetlist::TruthTable>& truth_tables,
                                            const size_t& default_sram_bit_value);
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/utils/physical_pb_utils.cpp b/openfpga/src/utils/physical_pb_utils.cpp
index 777f2ad0c..71cf98677 100644
--- a/openfpga/src/utils/physical_pb_utils.cpp
+++ b/openfpga/src/utils/physical_pb_utils.cpp
@@ -244,7 +244,7 @@ void rec_update_physical_pb_from_operating_pb(PhysicalPb& phy_pb,
 
     phy_pb.add_atom_block(physical_pb, atom_blk);
 
-    /* TODO: Iterate over ports and annotate the atom pins */
+    /* Iterate over ports and annotate the atom pins */
     synchronize_primitive_physical_pb_atom_nets(phy_pb, physical_pb,
                                                 pb_graph_node, 
                                                 pb_route,

From 2dd80e4830dcb2fdcae458574b3788c3789b33b6 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 25 Feb 2020 21:21:44 -0700
Subject: [PATCH 207/645] add more methods to acquire physical truth table from
 physical pb

---
 openfpga/src/annotation/vpr_clustering_annotation.cpp |  5 +++++
 openfpga/src/annotation/vpr_clustering_annotation.h   |  1 +
 openfpga/src/repack/physical_pb.cpp                   | 11 +++++++++++
 openfpga/src/repack/physical_pb.h                     |  1 +
 4 files changed, 18 insertions(+)

diff --git a/openfpga/src/annotation/vpr_clustering_annotation.cpp b/openfpga/src/annotation/vpr_clustering_annotation.cpp
index e0c7ab575..8dbc2d6f4 100644
--- a/openfpga/src/annotation/vpr_clustering_annotation.cpp
+++ b/openfpga/src/annotation/vpr_clustering_annotation.cpp
@@ -86,5 +86,10 @@ void VprClusteringAnnotation::add_physical_pb(const ClusterBlockId& block_id,
   physical_pbs_[block_id] = physical_pb;
 }
 
+PhysicalPb& VprClusteringAnnotation::mutable_physical_pb(const ClusterBlockId& block_id) {
+  VTR_ASSERT(physical_pbs_.end() != physical_pbs_.find(block_id));
+
+  return physical_pbs_.at(block_id);
+}
 
 } /* End namespace openfpga*/
diff --git a/openfpga/src/annotation/vpr_clustering_annotation.h b/openfpga/src/annotation/vpr_clustering_annotation.h
index b72173e1d..f8e84bb02 100644
--- a/openfpga/src/annotation/vpr_clustering_annotation.h
+++ b/openfpga/src/annotation/vpr_clustering_annotation.h
@@ -41,6 +41,7 @@ class VprClusteringAnnotation {
                     const ClusterNetId& net_id);
     void adapt_truth_table(t_pb* pb, const AtomNetlist::TruthTable& tt);
     void add_physical_pb(const ClusterBlockId& block_id, const PhysicalPb& physical_pb);
+    PhysicalPb& mutable_physical_pb(const ClusterBlockId& block_id);
   private: /* Internal data */
     /* Pair a regular pb_type to its physical pb_type */
     std::map<ClusterBlockId, std::map<int, ClusterNetId>> net_names_;
diff --git a/openfpga/src/repack/physical_pb.cpp b/openfpga/src/repack/physical_pb.cpp
index a29b6d401..59417080e 100644
--- a/openfpga/src/repack/physical_pb.cpp
+++ b/openfpga/src/repack/physical_pb.cpp
@@ -16,6 +16,17 @@ PhysicalPb::physical_pb_range PhysicalPb::pbs() const {
   return vtr::make_range(pb_ids_.begin(), pb_ids_.end());
 }
 
+std::vector<PhysicalPbId> PhysicalPb::primitive_pbs() const {
+  std::vector<PhysicalPbId> results; 
+  /* The primitive pbs are those without any children */
+  for (auto pb : pbs()) {
+    if (true == child_pbs_[pb].empty()) {
+      results.push_back(pb);
+    } 
+  }
+  return results;
+}
+
 std::string PhysicalPb::name(const PhysicalPbId& pb) const {
   VTR_ASSERT(true == valid_pb_id(pb));
   return names_[pb];
diff --git a/openfpga/src/repack/physical_pb.h b/openfpga/src/repack/physical_pb.h
index d5f5b00a3..caea0a0b9 100644
--- a/openfpga/src/repack/physical_pb.h
+++ b/openfpga/src/repack/physical_pb.h
@@ -39,6 +39,7 @@ class PhysicalPb {
     typedef vtr::Range<physical_pb_iterator> physical_pb_range;
   public: /* Public aggregators */
     physical_pb_range pbs() const;
+    std::vector<PhysicalPbId> primitive_pbs() const;
     std::string name(const PhysicalPbId& pb) const;
     PhysicalPbId find_pb(const t_pb_graph_node* name) const;
     PhysicalPbId parent(const PhysicalPbId& pb) const;

From 4024ed63cb4c87f3ba0b2786aff8df8937d72857 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 25 Feb 2020 22:39:42 -0700
Subject: [PATCH 208/645] add truth table build up for physical LUTs

---
 openfpga/src/base/openfpga_repack.cpp         |   8 +-
 .../src/repack/build_physical_truth_table.cpp | 170 ++++++++++++++++++
 .../src/repack/build_physical_truth_table.h   |  27 +++
 openfpga/src/repack/physical_pb.cpp           |  16 +-
 openfpga/src/repack/physical_pb.h             |   6 +-
 openfpga/src/utils/lut_utils.cpp              |   4 +-
 openfpga/src/utils/lut_utils.h                |   4 +-
 7 files changed, 226 insertions(+), 9 deletions(-)
 create mode 100644 openfpga/src/repack/build_physical_truth_table.cpp
 create mode 100644 openfpga/src/repack/build_physical_truth_table.h

diff --git a/openfpga/src/base/openfpga_repack.cpp b/openfpga/src/base/openfpga_repack.cpp
index f49321252..91c6b4798 100644
--- a/openfpga/src/base/openfpga_repack.cpp
+++ b/openfpga/src/base/openfpga_repack.cpp
@@ -5,7 +5,7 @@
 #include "vtr_time.h"
 #include "vtr_log.h"
 
-#include "verilog_api.h"
+#include "build_physical_truth_table.h"
 #include "repack.h"
 #include "openfpga_repack.h"
 
@@ -29,6 +29,12 @@ void repack(OpenfpgaContext& openfpga_ctx,
                     openfpga_ctx.mutable_vpr_device_annotation(),
                     openfpga_ctx.mutable_vpr_clustering_annotation(),
                     cmd_context.option_enable(cmd, opt_verbose));
+
+  build_physical_lut_truth_tables(openfpga_ctx.mutable_vpr_clustering_annotation(),
+                                  g_vpr_ctx.atom(),
+                                  g_vpr_ctx.clustering(),
+                                  openfpga_ctx.vpr_device_annotation(),
+                                  openfpga_ctx.arch().circuit_lib); 
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/repack/build_physical_truth_table.cpp b/openfpga/src/repack/build_physical_truth_table.cpp
new file mode 100644
index 000000000..c749ae206
--- /dev/null
+++ b/openfpga/src/repack/build_physical_truth_table.cpp
@@ -0,0 +1,170 @@
+/***************************************************************************************
+ * This file includes functions that are used to build truth tables of
+ * the physical implementation of LUTs
+ ***************************************************************************************/
+
+/* Headers from vtrutil library */
+#include "vtr_log.h"
+#include "vtr_assert.h"
+#include "vtr_time.h"
+
+#include "openfpga_naming.h"
+
+#include "lut_utils.h"
+#include "physical_pb.h"
+#include "build_physical_truth_table.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/***************************************************************************************
+ * Identify if LUT is used as wiring 
+ * In this case, LUT functions as a buffer
+ *         +------+
+ *  in0 -->|---   |
+ *         |   \  |
+ *  in1 -->|    --|--->out
+ *  ...
+ *
+ *  Note that this function judge the LUT operating mode from the input nets and output
+ *  nets that are mapped to inputs and outputs. 
+ *  If the output net appear in the list of input nets, this LUT is used as a wire 
+ ***************************************************************************************/
+static 
+bool is_wired_lut(const std::vector<AtomNetId>& input_nets,
+                  const AtomNetId& output_net) {
+  for (const AtomNetId& input_net : input_nets) {
+    if (input_net == output_net) {
+      return true;
+    }
+  }
+  
+  return false;
+}
+
+/***************************************************************************************
+ * Create pin rotation map for a LUT
+ ***************************************************************************************/
+static 
+std::vector<int> generate_lut_rotated_input_pin_map(const std::vector<AtomNetId>& input_nets,
+                                                    const AtomContext& atom_ctx,
+                                                    const AtomBlockId& atom_blk,
+                                                    const t_pb_graph_node* pb_graph_node) { 
+  /* Find the pin rotation status and record it ,
+   * Note that some LUT inputs may not be used, we set them to be open by default
+   */
+  std::vector<int> rotated_pin_map(input_nets.size(), -1);
+
+  VTR_ASSERT(1 == pb_graph_node->num_input_ports);
+  for (int ipin = 0; ipin < pb_graph_node->num_input_pins[0]; ++ipin) {
+    /* Port exists (some LUTs may have no input and hence no port in the atom netlist) */
+    AtomPortId atom_port = atom_ctx.nlist.find_atom_port(atom_blk, pb_graph_node->input_pins[0][ipin].port->model_port);
+    if (!atom_port) { 
+      continue;
+    }
+
+    for (AtomPinId atom_pin : atom_ctx.nlist.port_pins(atom_port)) {
+      AtomNetId atom_pin_net = atom_ctx.nlist.pin_net(atom_pin);
+      if (atom_pin_net == input_nets[ipin]) {
+        rotated_pin_map[ipin] = atom_ctx.nlist.pin_port_bit(atom_pin);
+        break;
+      }
+    }
+  }
+  return rotated_pin_map;
+}
+
+/***************************************************************************************
+ * This function will iterate over all the inputs and outputs of the LUT pb 
+ * and find truth tables that are mapped to each output pins
+ * Note that a physical LUT may have multiple truth tables to be considered
+ * as they may be fracturable
+ ***************************************************************************************/
+static 
+void build_physical_pb_lut_truth_tables(PhysicalPb& physical_pb,
+                                        const PhysicalPbId& lut_pb_id,
+                                        const AtomContext& atom_ctx,
+                                        const VprDeviceAnnotation& device_annotation,
+                                        const CircuitLibrary& circuit_lib) {
+  const t_pb_graph_node* pb_graph_node = physical_pb.pb_graph_node(lut_pb_id);
+
+  CircuitModelId lut_model = device_annotation.pb_type_circuit_model(physical_pb.pb_graph_node(lut_pb_id)->pb_type);
+  VTR_ASSERT(CIRCUIT_MODEL_LUT == circuit_lib.model_type(lut_model));
+
+  /* Find all the nets mapped to each inputs */
+  std::vector<AtomNetId> input_nets;
+  VTR_ASSERT(1 == pb_graph_node->num_input_ports);
+  for (int ipin = 0; ipin < pb_graph_node->num_input_pins[0]; ++ipin) {
+    input_nets.push_back(physical_pb.pb_graph_pin_atom_net(lut_pb_id, &(pb_graph_node->input_pins[0][ipin]))); 
+  }
+
+
+  /* Find all the nets mapped to each outputs */
+  for (int iport = 0; iport < pb_graph_node->num_input_ports; ++iport) {
+    for (int ipin = 0; ipin < pb_graph_node->num_input_pins[iport]; ++ipin) {
+      const t_pb_graph_pin* output_pin = &(pb_graph_node->output_pins[iport][ipin]);
+      AtomNetId output_net = physical_pb.pb_graph_pin_atom_net(lut_pb_id, output_pin); 
+      /* Bypass unmapped pins */
+      if (AtomNetId::INVALID() == output_net) {
+        continue;
+      }
+      /* Check if this is a LUT used as wiring */
+      if (true == is_wired_lut(input_nets, output_net)) {
+        AtomNetlist::TruthTable wire_tt = build_wired_lut_truth_table(input_nets.size(), std::find(input_nets.begin(), input_nets.end(), output_net) - input_nets.begin()); 
+        physical_pb.set_truth_table(lut_pb_id, output_pin, wire_tt);
+        continue;
+      }
+
+      /* Find the truth table from atom block which drives the atom net */
+      const AtomBlockId& atom_blk = atom_ctx.nlist.net_driver_block(output_net); 
+      VTR_ASSERT(true == atom_ctx.nlist.valid_block_id(atom_blk));
+      const AtomNetlist::TruthTable& orig_tt = atom_ctx.nlist.block_truth_table(atom_blk);
+
+      std::vector<int> rotated_pin_map = generate_lut_rotated_input_pin_map(input_nets, atom_ctx, atom_blk, pb_graph_node);
+      const AtomNetlist::TruthTable& adapt_tt = lut_truth_table_adaption(orig_tt, rotated_pin_map);
+
+      /* Adapt the truth table for fracturable lut implementation and add to physical pb */
+      CircuitPortId lut_model_output_port = device_annotation.pb_circuit_port(output_pin->port);
+      size_t lut_frac_level = circuit_lib.port_lut_frac_level(lut_model_output_port);
+      if (size_t(-1) == lut_frac_level) {
+        lut_frac_level = input_nets.size();
+      }
+      size_t lut_output_mask = circuit_lib.port_lut_output_mask(lut_model_output_port)[output_pin->pin_number];
+      const AtomNetlist::TruthTable& frac_lut_tt = adapt_truth_table_for_frac_lut(lut_frac_level, lut_output_mask, adapt_tt);
+      physical_pb.set_truth_table(lut_pb_id, output_pin, frac_lut_tt);
+    }
+  }
+}
+
+/***************************************************************************************
+ * This function will iterate over all the physical pb that are
+ * binded to clustered blocks and build the truth tables for the
+ * physical Look-Up Table (LUT) implementations.
+ * Note that the truth table built here is different from the atom
+ * netlists in VPR context. We consider fracturable LUT features
+ * and LUTs operating as wires
+ ***************************************************************************************/
+void build_physical_lut_truth_tables(VprClusteringAnnotation& cluster_annotation,
+                                     const AtomContext& atom_ctx,
+                                     const ClusteringContext& cluster_ctx,
+                                     const VprDeviceAnnotation& device_annotation,
+                                     const CircuitLibrary& circuit_lib) {
+  vtr::ScopedStartFinishTimer timer("Build truth tables for physical LUTs");
+
+  for (auto blk_id : cluster_ctx.clb_nlist.blocks()) {
+    PhysicalPb& physical_pb = cluster_annotation.mutable_physical_pb(blk_id);
+    /* Find the LUT physical pb id */
+    for (const PhysicalPbId& primitive_pb : physical_pb.primitive_pbs()) {
+      CircuitModelId circuit_model = device_annotation.pb_type_circuit_model(physical_pb.pb_graph_node(primitive_pb)->pb_type);
+      VTR_ASSERT(true == circuit_lib.valid_model_id(circuit_model));
+      if (CIRCUIT_MODEL_LUT != circuit_lib.model_type(circuit_model)) {
+        continue;
+      }
+    
+      /* Reach here, we have a LUT to deal with. Find the truth tables that mapped to the LUT */
+      build_physical_pb_lut_truth_tables(physical_pb, primitive_pb, atom_ctx, device_annotation, circuit_lib);
+    }
+  }
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/repack/build_physical_truth_table.h b/openfpga/src/repack/build_physical_truth_table.h
new file mode 100644
index 000000000..c5d14059f
--- /dev/null
+++ b/openfpga/src/repack/build_physical_truth_table.h
@@ -0,0 +1,27 @@
+#ifndef BUILD_PHYSICAL_TRUTH_TABLE_H
+#define BUILD_PHYSICAL_TRUTH_TABLE_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "vpr_context.h"
+#include "vpr_device_annotation.h"
+#include "vpr_clustering_annotation.h"
+#include "circuit_library.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void build_physical_lut_truth_tables(VprClusteringAnnotation& cluster_annotation,
+                                     const AtomContext& atom_ctx,
+                                     const ClusteringContext& cluster_ctx,
+                                     const VprDeviceAnnotation& device_annotation,
+                                     const CircuitLibrary& circuit_lib);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/repack/physical_pb.cpp b/openfpga/src/repack/physical_pb.cpp
index 59417080e..74894293a 100644
--- a/openfpga/src/repack/physical_pb.cpp
+++ b/openfpga/src/repack/physical_pb.cpp
@@ -32,6 +32,11 @@ std::string PhysicalPb::name(const PhysicalPbId& pb) const {
   return names_[pb];
 }
 
+const t_pb_graph_node* PhysicalPb::pb_graph_node(const PhysicalPbId& pb) const {
+  VTR_ASSERT(true == valid_pb_id(pb));
+  return pb_graph_nodes_[pb];
+}
+
 /* Find the module id by a given name, return invalid if not found */
 PhysicalPbId PhysicalPb::find_pb(const t_pb_graph_node* pb_graph_node) const {
   if (type2id_map_.find(pb_graph_node) != type2id_map_.end()) {
@@ -76,7 +81,7 @@ AtomNetId PhysicalPb::pb_graph_pin_atom_net(const PhysicalPbId& pb,
   return AtomNetId::INVALID();
 }
 
-AtomNetlist::TruthTable PhysicalPb::truth_table(const PhysicalPbId& pb) const {
+std::map<const t_pb_graph_pin*, AtomNetlist::TruthTable> PhysicalPb::truth_tables(const PhysicalPbId& pb) const {
   VTR_ASSERT(true == valid_pb_id(pb));
   return truth_tables_[pb];
 }
@@ -109,6 +114,7 @@ PhysicalPbId PhysicalPb::create_pb(const t_pb_graph_node* pb_graph_node) {
   child_pbs_.emplace_back();
   parent_pbs_.emplace_back();
 
+  truth_tables_.emplace_back();
   mode_bits_.emplace_back();
 
   /* Register in the name2id map */
@@ -136,10 +142,16 @@ void PhysicalPb::add_child(const PhysicalPbId& parent,
 }
 
 void PhysicalPb::set_truth_table(const PhysicalPbId& pb,
+                                 const t_pb_graph_pin* pb_graph_pin,
                                  const AtomNetlist::TruthTable& truth_table) {
   VTR_ASSERT(true == valid_pb_id(pb)); 
+
+  if (0 < truth_tables_[pb].count(pb_graph_pin)) {
+    VTR_LOG_WARN("Overwrite truth tables mapped to pb_graph_pin '%s[%ld]!\n",
+                  pb_graph_pin->port->name, pb_graph_pin->pin_number);
+  }
    
-  truth_tables_[pb] = truth_table;
+  truth_tables_[pb][pb_graph_pin] = truth_table;
 }
 
 void PhysicalPb::set_mode_bits(const PhysicalPbId& pb,
diff --git a/openfpga/src/repack/physical_pb.h b/openfpga/src/repack/physical_pb.h
index caea0a0b9..11559da6b 100644
--- a/openfpga/src/repack/physical_pb.h
+++ b/openfpga/src/repack/physical_pb.h
@@ -41,6 +41,7 @@ class PhysicalPb {
     physical_pb_range pbs() const;
     std::vector<PhysicalPbId> primitive_pbs() const;
     std::string name(const PhysicalPbId& pb) const;
+    const t_pb_graph_node* pb_graph_node(const PhysicalPbId& pb) const;
     PhysicalPbId find_pb(const t_pb_graph_node* name) const;
     PhysicalPbId parent(const PhysicalPbId& pb) const;
     PhysicalPbId child(const PhysicalPbId& pb,
@@ -49,7 +50,7 @@ class PhysicalPb {
     std::vector<AtomBlockId> atom_blocks(const PhysicalPbId& pb) const;
     AtomNetId pb_graph_pin_atom_net(const PhysicalPbId& pb,
                                     const t_pb_graph_pin* pb_graph_pin) const;
-    AtomNetlist::TruthTable truth_table(const PhysicalPbId& pb) const;
+    std::map<const t_pb_graph_pin*, AtomNetlist::TruthTable> truth_tables(const PhysicalPbId& pb) const;
     std::vector<size_t> mode_bits(const PhysicalPbId& pb) const;
   public: /* Public mutators */
     PhysicalPbId create_pb(const t_pb_graph_node* pb_graph_node);
@@ -59,6 +60,7 @@ class PhysicalPb {
     void add_atom_block(const PhysicalPbId& pb,
                         const AtomBlockId& atom_block);
     void set_truth_table(const PhysicalPbId& pb,
+                         const t_pb_graph_pin* pb_graph_pin,
                          const AtomNetlist::TruthTable& truth_table);
     void set_mode_bits(const PhysicalPbId& pb,
                        const std::vector<size_t>& mode_bits);
@@ -82,7 +84,7 @@ class PhysicalPb {
     /* configuration bits 
      * Truth tables and mode selection
      */
-    vtr::vector<PhysicalPbId, AtomNetlist::TruthTable> truth_tables_;
+    vtr::vector<PhysicalPbId, std::map<const t_pb_graph_pin*, AtomNetlist::TruthTable>> truth_tables_;
 
     vtr::vector<PhysicalPbId, std::vector<size_t>> mode_bits_;
 
diff --git a/openfpga/src/utils/lut_utils.cpp b/openfpga/src/utils/lut_utils.cpp
index 16bb8c3f2..ca3ac343e 100644
--- a/openfpga/src/utils/lut_utils.cpp
+++ b/openfpga/src/utils/lut_utils.cpp
@@ -131,8 +131,8 @@ std::vector<std::string> truth_table_to_string(const AtomNetlist::TruthTable& tt
  *    --1- 1
  * 
  ********************************************************************/
-AtomNetlist::TruthTable build_post_routing_wired_lut_truth_table(const size_t& lut_size, 
-                                                                 const size_t& wire_input_id) {
+AtomNetlist::TruthTable build_wired_lut_truth_table(const size_t& lut_size, 
+                                                    const size_t& wire_input_id) {
   AtomNetlist::TruthTable tt;
   
   /* There is always only one line in this truth table */
diff --git a/openfpga/src/utils/lut_utils.h b/openfpga/src/utils/lut_utils.h
index 21f638175..4b2f8bd58 100644
--- a/openfpga/src/utils/lut_utils.h
+++ b/openfpga/src/utils/lut_utils.h
@@ -24,8 +24,8 @@ AtomNetlist::TruthTable lut_truth_table_adaption(const AtomNetlist::TruthTable&
 
 std::vector<std::string> truth_table_to_string(const AtomNetlist::TruthTable& tt);
 
-AtomNetlist::TruthTable build_post_routing_wired_lut_truth_table(const size_t& lut_size, 
-                                                                 const size_t& wire_input_id);
+AtomNetlist::TruthTable build_wired_lut_truth_table(const size_t& lut_size, 
+                                                    const size_t& wire_input_id);
 
 AtomNetlist::TruthTable adapt_truth_table_for_frac_lut(const size_t& lut_frac_level,
                                                        const size_t& lut_output_mask,

From 075264e3e38b4310fa7eb8942a0b761c2e36bde9 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 25 Feb 2020 23:29:16 -0700
Subject: [PATCH 209/645] debugging LUT bitstream generation

---
 .../fpga_bitstream/build_grid_bitstream.cpp   | 116 +++++++++++++++++-
 openfpga/src/utils/physical_pb_utils.cpp      |   2 +-
 2 files changed, 113 insertions(+), 5 deletions(-)

diff --git a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
index d344d8880..bce9f8271 100644
--- a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
+++ b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
@@ -2,6 +2,7 @@
  * This file includes functions that are used for building bitstreams
  * for grids (CLBs, heterogenerous blocks, I/Os, etc.)
  *******************************************************************/
+#include <cmath>
 #include <string>
 
 /* Headers from vtrutil library */
@@ -22,9 +23,9 @@
 #include "openfpga_naming.h"
 #include "mux_bitstream_constants.h"
 #include "pb_type_utils.h"
+#include "lut_utils.h"
 
 #include "build_mux_bitstream.h"
-//#include "build_lut_bitstream.h"
 #include "build_grid_bitstream.h"
 
 /* begin namespace openfpga */
@@ -335,6 +336,112 @@ void build_physical_block_interc_bitstream(BitstreamManager& bitstream_manager,
   }
 }
 
+/********************************************************************
+ * Generate bitstream for a LUT and add it to bitstream manager
+ * This function supports both single-output and fracturable LUTs
+ *******************************************************************/
+static 
+void build_lut_bitstream(BitstreamManager& bitstream_manager,
+                         const ConfigBlockId& parent_configurable_block,
+                         const VprDeviceAnnotation& device_annotation,
+                         const ModuleManager& module_manager,
+                         const CircuitLibrary& circuit_lib,
+                         const MuxLibrary& mux_lib,
+                         const PhysicalPb& physical_pb,
+                         const PhysicalPbId& lut_pb_id,
+                         t_pb_type* lut_pb_type) {
+
+  /* Ensure a valid physical pritimive pb */ 
+  if (nullptr == lut_pb_type) {
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid lut_pb_type!\n");
+    exit(1);
+  }
+
+  CircuitModelId lut_model = device_annotation.pb_type_circuit_model(lut_pb_type);
+  VTR_ASSERT(CircuitModelId::INVALID() != lut_model);
+  VTR_ASSERT(CIRCUIT_MODEL_LUT == circuit_lib.model_type(lut_model));
+
+  /* Find the input ports for LUT size, this is used to decode the LUT memory bits! */
+  std::vector<CircuitPortId> model_input_ports = circuit_lib.model_ports_by_type(lut_model, CIRCUIT_MODEL_PORT_INPUT, true);
+  VTR_ASSERT(1 == model_input_ports.size());
+  size_t lut_size = circuit_lib.port_size(model_input_ports[0]);
+
+  /* Find SRAM ports for truth tables and mode-selection */
+  std::vector<CircuitPortId> lut_regular_sram_ports = find_circuit_regular_sram_ports(circuit_lib, lut_model);
+  std::vector<CircuitPortId> lut_mode_select_ports = find_circuit_mode_select_sram_ports(circuit_lib, lut_model);
+  /* We should always 1 regular sram port, where truth table is loaded to */
+  VTR_ASSERT(1 == lut_regular_sram_ports.size());
+  /* We may have a port for mode select or not. This depends on if the LUT is fracturable or not */
+  VTR_ASSERT( (0 == lut_mode_select_ports.size())
+           || (1 == lut_mode_select_ports.size()) );
+
+  std::vector<bool> lut_bitstream;
+  /* Generate bitstream for the LUT */ 
+  if (false == physical_pb.valid_pb_id(lut_pb_id)) {
+    /* An empty pb means that this is an unused LUT, 
+     * we give an empty truth table, which are full of default values (defined by users) 
+     */
+    for (size_t i = 0; i < circuit_lib.port_size(lut_regular_sram_ports[0]); ++i) {
+      VTR_ASSERT( (0 == circuit_lib.port_default_value(lut_regular_sram_ports[0]))
+               || (1 == circuit_lib.port_default_value(lut_regular_sram_ports[0])) );
+      lut_bitstream.push_back(1 == circuit_lib.port_default_value(lut_regular_sram_ports[0]));
+    }
+  } else { 
+    VTR_ASSERT(true == physical_pb.valid_pb_id(lut_pb_id));
+
+    /* Find MUX graph correlated to the LUT */
+    MuxId lut_mux_id = mux_lib.mux_graph(lut_model, (size_t)pow(2., lut_size)); 
+    const MuxGraph& mux_graph = mux_lib.mux_graph(lut_mux_id);
+    /* Ensure the LUT MUX has the expected input and SRAM port sizes */
+    VTR_ASSERT(mux_graph.num_memory_bits() == lut_size);
+    VTR_ASSERT(mux_graph.num_inputs() == (size_t)pow(2., lut_size));
+    /* Generate LUT bitstream */
+    lut_bitstream = build_frac_lut_bitstream(circuit_lib, mux_graph,
+                                             device_annotation,
+                                             physical_pb.truth_tables(lut_pb_id),
+                                             circuit_lib.port_default_value(lut_regular_sram_ports[0]));
+  }
+  
+  /* Generate bitstream for mode-select ports */
+  if (0 != lut_mode_select_ports.size()) {
+    std::vector<bool> mode_select_bitstream;
+    /* TODO: Xifan Tang: find out why some lut_pb has no mode bits!!!
+     * I suspect that wire LUTs are not mapped to any pb
+     */
+    if ( (true == physical_pb.valid_pb_id(lut_pb_id))
+      && (0 != physical_pb.mode_bits(lut_pb_id).size()) ) {
+      mode_select_bitstream = generate_mode_select_bitstream(physical_pb.mode_bits(lut_pb_id));
+    } else { /* get default mode_bits */
+      mode_select_bitstream = generate_mode_select_bitstream(device_annotation.pb_type_mode_bits(lut_pb_type));
+    }
+    /* Conjunct the mode-select bitstream to the lut bitstream */
+    for (const bool& bit : mode_select_bitstream) {
+      lut_bitstream.push_back(bit);
+    }
+  }
+
+  /* Ensure the length of bitstream matches the side of memory circuits */
+  std::vector<CircuitModelId> sram_models = find_circuit_sram_models(circuit_lib, lut_model);
+  VTR_ASSERT(1 == sram_models.size());
+  std::string mem_block_name = generate_memory_module_name(circuit_lib, lut_model, sram_models[0], std::string(MEMORY_MODULE_POSTFIX));
+  ModuleId mem_module = module_manager.find_module(mem_block_name);
+  VTR_ASSERT (true == module_manager.valid_module_id(mem_module));
+  ModulePortId mem_out_port_id = module_manager.find_module_port(mem_module, generate_configuration_chain_data_out_name());
+  VTR_ASSERT(lut_bitstream.size() == module_manager.module_port(mem_module, mem_out_port_id).get_width());
+
+  /* Create a block for the bitstream which corresponds to the memory module associated to the LUT */
+  ConfigBlockId mem_block = bitstream_manager.add_block(mem_block_name);
+  bitstream_manager.add_child_block(parent_configurable_block, mem_block);
+
+  /* Add the bitstream to the bitstream manager */
+  for (const bool& bit : lut_bitstream) {
+    ConfigBitId config_bit = bitstream_manager.add_bit(bit);
+    /* Link the memory bits to the mux mem block */
+    bitstream_manager.add_bit_to_block(mem_block, config_bit);
+  }
+}
+
 /********************************************************************
  * This function generates bitstream for a physical block, which is 
  * a child block of a grid 
@@ -400,9 +507,10 @@ void rec_build_physical_block_bitstream(BitstreamManager& bitstream_manager,
       /* Special case for LUT !!!
        * Mapped logical block information is stored in child_pbs of this pb!!!
        */
-      //build_lut_bitstream(bitstream_manager, pb_configurable_block,
-      //                    module_manager, circuit_lib, mux_lib, 
-      //                    physical_pb, pb_id, physical_pb_type);
+      build_lut_bitstream(bitstream_manager, pb_configurable_block,
+                          device_annotation, 
+                          module_manager, circuit_lib, mux_lib, 
+                          physical_pb, pb_id, physical_pb_type);
       break;
     case CIRCUIT_MODEL_FF:
     case CIRCUIT_MODEL_HARDLOGIC:
diff --git a/openfpga/src/utils/physical_pb_utils.cpp b/openfpga/src/utils/physical_pb_utils.cpp
index 71cf98677..9fe61ef89 100644
--- a/openfpga/src/utils/physical_pb_utils.cpp
+++ b/openfpga/src/utils/physical_pb_utils.cpp
@@ -236,7 +236,7 @@ void rec_update_physical_pb_from_operating_pb(PhysicalPb& phy_pb,
     VTR_ASSERT(true == phy_pb.valid_pb_id(physical_pb));
 
     /* Set the mode bits */
-    phy_pb.set_mode_bits(physical_pb, device_annotation.pb_type_mode_bits(physical_pb_graph_node->pb_type));
+    phy_pb.set_mode_bits(physical_pb, device_annotation.pb_type_mode_bits(pb_type));
 
     /* Find mapped atom block and add to this physical pb */
     AtomBlockId atom_blk = atom_ctx.nlist.find_block(op_pb->name);

From 759758421d92babfe17dd65669581abc520e82a2 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 25 Feb 2020 23:45:49 -0700
Subject: [PATCH 210/645] found the bug in physical pb mode bits and fixed

---
 openfpga/src/fpga_bitstream/build_grid_bitstream.cpp | 3 +--
 openfpga/src/utils/physical_pb_utils.cpp             | 2 ++
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
index bce9f8271..b50d05f85 100644
--- a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
+++ b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
@@ -409,8 +409,7 @@ void build_lut_bitstream(BitstreamManager& bitstream_manager,
     /* TODO: Xifan Tang: find out why some lut_pb has no mode bits!!!
      * I suspect that wire LUTs are not mapped to any pb
      */
-    if ( (true == physical_pb.valid_pb_id(lut_pb_id))
-      && (0 != physical_pb.mode_bits(lut_pb_id).size()) ) {
+    if (true == physical_pb.valid_pb_id(lut_pb_id)) {
       mode_select_bitstream = generate_mode_select_bitstream(physical_pb.mode_bits(lut_pb_id));
     } else { /* get default mode_bits */
       mode_select_bitstream = generate_mode_select_bitstream(device_annotation.pb_type_mode_bits(lut_pb_type));
diff --git a/openfpga/src/utils/physical_pb_utils.cpp b/openfpga/src/utils/physical_pb_utils.cpp
index 9fe61ef89..93fbba992 100644
--- a/openfpga/src/utils/physical_pb_utils.cpp
+++ b/openfpga/src/utils/physical_pb_utils.cpp
@@ -32,6 +32,8 @@ void rec_alloc_physical_pb_from_pb_graph(PhysicalPb& phy_pb,
 
   /* Finish for primitive node */
   if (true == is_primitive_pb_type(pb_type)) {
+    /* Deposite mode bits here */
+    phy_pb.set_mode_bits(cur_phy_pb_id, device_annotation.pb_type_mode_bits(pb_type));
     return;
   } 
 

From a26d31b87f411c82e59e96fbe5c79c2dcace4177 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 26 Feb 2020 11:09:23 -0700
Subject: [PATCH 211/645] make write bitstream online

---
 openfpga/src/base/openfpga_bitstream.cpp      | 27 +++++++++++++++++--
 openfpga/src/base/openfpga_bitstream.h        |  3 +++
 .../src/base/openfpga_bitstream_command.cpp   | 22 ++++++++++++++-
 openfpga/src/base/openfpga_context.h          |  4 +++
 .../src/fpga_bitstream/bitstream_writer.cpp   |  7 ++++-
 .../fpga_bitstream/build_fabric_bitstream.cpp |  7 ++++-
 .../fpga_bitstream/build_fabric_bitstream.h   |  3 ++-
 openfpga/test_script/s298_k6_frac.openfpga    |  3 ++-
 8 files changed, 69 insertions(+), 7 deletions(-)

diff --git a/openfpga/src/base/openfpga_bitstream.cpp b/openfpga/src/base/openfpga_bitstream.cpp
index 8a51899e0..08fa7bf16 100644
--- a/openfpga/src/base/openfpga_bitstream.cpp
+++ b/openfpga/src/base/openfpga_bitstream.cpp
@@ -6,6 +6,8 @@
 #include "vtr_log.h"
 
 #include "build_device_bitstream.h"
+#include "bitstream_writer.h"
+#include "build_fabric_bitstream.h"
 #include "openfpga_bitstream.h"
 
 /* Include global variables of VPR */
@@ -15,14 +17,35 @@
 namespace openfpga {
 
 /********************************************************************
- * A wrapper function to call the fabric_verilog function of FPGA-Verilog 
+ * A wrapper function to call the build_device_bitstream() in FPGA bitstream
  *******************************************************************/
 void fpga_bitstream(OpenfpgaContext& openfpga_ctx,
                     const Command& cmd, const CommandContext& cmd_context) {
 
   CommandOptionId opt_verbose = cmd.option("verbose");
+  CommandOptionId opt_file = cmd.option("file");
 
-  openfpga_ctx.mutable_bitstream_manager() = build_device_bitstream(g_vpr_ctx, openfpga_ctx, cmd_context.option_enable(cmd, opt_verbose));
+  openfpga_ctx.mutable_bitstream_manager() = build_device_bitstream(g_vpr_ctx,
+                                                                    openfpga_ctx,
+                                                                    cmd_context.option_enable(cmd, opt_verbose));
+
+  if (true == cmd_context.option_enable(cmd, opt_file)) {
+    write_arch_independent_bitstream_to_xml_file(openfpga_ctx.bitstream_manager(),
+                                                 cmd_context.option_value(cmd, opt_file));
+  }
+}
+
+/********************************************************************
+ * A wrapper function to call the build_fabric_bitstream() in FPGA bitstream
+ *******************************************************************/
+void build_fabric_bitstream(OpenfpgaContext& openfpga_ctx,
+                            const Command& cmd, const CommandContext& cmd_context) {
+
+  CommandOptionId opt_verbose = cmd.option("verbose");
+
+  openfpga_ctx.mutable_fabric_bitstream() = build_fabric_dependent_bitstream(openfpga_ctx.bitstream_manager(),
+                                                                             openfpga_ctx.module_graph(),
+                                                                             cmd_context.option_enable(cmd, opt_verbose));
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_bitstream.h b/openfpga/src/base/openfpga_bitstream.h
index 1411dc090..9dc2ad471 100644
--- a/openfpga/src/base/openfpga_bitstream.h
+++ b/openfpga/src/base/openfpga_bitstream.h
@@ -18,6 +18,9 @@ namespace openfpga {
 void fpga_bitstream(OpenfpgaContext& openfpga_ctx,
                     const Command& cmd, const CommandContext& cmd_context); 
 
+void build_fabric_bitstream(OpenfpgaContext& openfpga_ctx,
+                            const Command& cmd, const CommandContext& cmd_context);
+
 } /* end namespace openfpga */
 
 #endif
diff --git a/openfpga/src/base/openfpga_bitstream_command.cpp b/openfpga/src/base/openfpga_bitstream_command.cpp
index af06cd60b..96201b6c7 100644
--- a/openfpga/src/base/openfpga_bitstream_command.cpp
+++ b/openfpga/src/base/openfpga_bitstream_command.cpp
@@ -39,8 +39,12 @@ void add_openfpga_bitstream_commands(openfpga::Shell<OpenfpgaContext>& shell) {
    * Command 'fpga_bitstream' 
    */
   Command shell_cmd_fpga_bitstream("fpga_bitstream");
+
+  /* Add an option '--file' in short '-f'*/
+  CommandOptionId fpga_bitstream_opt_file = shell_cmd_fpga_bitstream.add_option("file", true, "file path to output the bitstream database");
+  shell_cmd_fpga_bitstream.set_option_short_name(fpga_bitstream_opt_file, "f");
+  shell_cmd_fpga_bitstream.set_option_require_value(fpga_bitstream_opt_file, openfpga::OPT_STRING);
   /* Add an option '--verbose' */
-  shell_cmd_fpga_bitstream.add_option("fabric_dependent", false, "Enable the bitstream construction for the FPGA fabric");
   shell_cmd_fpga_bitstream.add_option("verbose", false, "Enable verbose output");
   
   /* Add command 'fpga_bitstream' to the Shell */
@@ -53,6 +57,22 @@ void add_openfpga_bitstream_commands(openfpga::Shell<OpenfpgaContext>& shell) {
   cmd_dependency_fpga_bitstream.push_back(shell_cmd_repack_id);
   shell.set_command_dependency(shell_cmd_fpga_bitstream_id, cmd_dependency_fpga_bitstream);
 
+  /******************************** 
+   * Command 'build_fabric_bitstream' 
+   */
+  Command shell_cmd_fabric_bitstream("build_fabric_bitstream");
+  /* Add an option '--verbose' */
+  shell_cmd_fabric_bitstream.add_option("verbose", false, "Enable verbose output");
+
+  /* Add command 'fabric_bitstream' to the Shell */
+  ShellCommandId shell_cmd_fabric_bitstream_id = shell.add_command(shell_cmd_fabric_bitstream, "Reorganize the fabric-independent bitstream for the FPGA fabric created by FPGA-Verilog");
+  shell.set_command_class(shell_cmd_fabric_bitstream_id, openfpga_bitstream_cmd_class);
+  shell.set_command_execute_function(shell_cmd_fabric_bitstream_id, build_fabric_bitstream);
+
+  /* The 'fabric_bitstream' command should NOT be executed before 'fpga_bitstream' */
+  std::vector<ShellCommandId> cmd_dependency_fabric_bitstream;
+  cmd_dependency_fabric_bitstream.push_back(shell_cmd_fpga_bitstream_id);
+  shell.set_command_dependency(shell_cmd_fabric_bitstream_id, cmd_dependency_fabric_bitstream);
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_context.h b/openfpga/src/base/openfpga_context.h
index 9c685b247..521a2cf6a 100644
--- a/openfpga/src/base/openfpga_context.h
+++ b/openfpga/src/base/openfpga_context.h
@@ -1,6 +1,7 @@
 #ifndef OPENFPGA_CONTEXT_H
 #define OPENFPGA_CONTEXT_H
 
+#include <vector>
 #include "vpr_context.h"
 #include "openfpga_arch.h"
 #include "vpr_netlist_annotation.h"
@@ -56,6 +57,7 @@ class OpenfpgaContext : public Context  {
     const openfpga::ModuleManager& module_graph() const { return module_graph_; }
     const openfpga::FlowManager& flow_manager() const { return flow_manager_; }
     const openfpga::BitstreamManager& bitstream_manager() const { return bitstream_manager_; }
+    const std::vector<openfpga::ConfigBitId>& fabric_bitstream() const { return fabric_bitstream_; }
   public:  /* Public mutators */
     openfpga::Arch& mutable_arch() { return arch_; }
     openfpga::VprDeviceAnnotation& mutable_vpr_device_annotation() { return vpr_device_annotation_; }
@@ -69,6 +71,7 @@ class OpenfpgaContext : public Context  {
     openfpga::ModuleManager& mutable_module_graph() { return module_graph_; }
     openfpga::FlowManager& mutable_flow_manager() { return flow_manager_; }
     openfpga::BitstreamManager& mutable_bitstream_manager() { return bitstream_manager_; }
+    std::vector<openfpga::ConfigBitId>& mutable_fabric_bitstream() { return fabric_bitstream_; }
   private: /* Internal data */
     /* Data structure to store information from read_openfpga_arch library */
     openfpga::Arch arch_;
@@ -102,6 +105,7 @@ class OpenfpgaContext : public Context  {
 
     /* Bitstream database */
     openfpga::BitstreamManager bitstream_manager_;
+    std::vector<openfpga::ConfigBitId> fabric_bitstream_;
  
     /* Flow status */
     openfpga::FlowManager flow_manager_;
diff --git a/openfpga/src/fpga_bitstream/bitstream_writer.cpp b/openfpga/src/fpga_bitstream/bitstream_writer.cpp
index f19e3819f..6f8539d3f 100644
--- a/openfpga/src/fpga_bitstream/bitstream_writer.cpp
+++ b/openfpga/src/fpga_bitstream/bitstream_writer.cpp
@@ -111,7 +111,12 @@ void rec_write_block_bitstream_to_xml_file(std::fstream& fp,
  *******************************************************************/
 void write_arch_independent_bitstream_to_xml_file(const BitstreamManager& bitstream_manager,
                                                   const std::string& fname) {
-  std::string timer_message = std::string("Writing ") + std::to_string(bitstream_manager.bits().size()) + std::string(" architecture independent bitstream into XML file '") + fname + std::string("'\n");
+  /* Ensure that we have a valid file name */
+  if (true == fname.empty()) {
+    VTR_LOG_ERROR("Received empty file name to output bitstream!\n\tPlease specify a valid file name.\n");
+  }
+
+  std::string timer_message = std::string("Write ") + std::to_string(bitstream_manager.bits().size()) + std::string(" architecture independent bitstream into XML file '") + fname + std::string("'");
   vtr::ScopedStartFinishTimer timer(timer_message);
 
   /* Create the file stream */
diff --git a/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp b/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp
index 241aee04d..0a15f6930 100644
--- a/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp
+++ b/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp
@@ -83,7 +83,8 @@ void rec_build_module_fabric_dependent_bitstream(const BitstreamManager& bitstre
  * It was done in the function build_device_bitstream() 
  *******************************************************************/
 std::vector<ConfigBitId> build_fabric_dependent_bitstream(const BitstreamManager& bitstream_manager,
-                                                          const ModuleManager& module_manager) {
+                                                          const ModuleManager& module_manager,
+                                                          const bool& verbose) {
   std::vector<ConfigBitId> fabric_bitstream; 
 
   vtr::ScopedStartFinishTimer timer("\nBuild fabric dependent bitstream\n");
@@ -125,6 +126,10 @@ std::vector<ConfigBitId> build_fabric_dependent_bitstream(const BitstreamManager
   /* Ensure our fabric bitstream is in the same size as device bistream */
   VTR_ASSERT(bitstream_manager.bits().size() == fabric_bitstream.size());
 
+  VTR_LOGV(verbose,
+           "Built %lu configuration bits for fabric\n",
+           fabric_bitstream.size());
+
   return fabric_bitstream;
 }
 
diff --git a/openfpga/src/fpga_bitstream/build_fabric_bitstream.h b/openfpga/src/fpga_bitstream/build_fabric_bitstream.h
index 47d46084c..507454059 100644
--- a/openfpga/src/fpga_bitstream/build_fabric_bitstream.h
+++ b/openfpga/src/fpga_bitstream/build_fabric_bitstream.h
@@ -16,7 +16,8 @@
 namespace openfpga {
 
 std::vector<ConfigBitId> build_fabric_dependent_bitstream(const BitstreamManager& bitstream_manager,
-                                                          const ModuleManager& module_manager);
+                                                          const ModuleManager& module_manager,
+                                                          const bool& verbose);
 
 } /* end namespace openfpga */
 
diff --git a/openfpga/test_script/s298_k6_frac.openfpga b/openfpga/test_script/s298_k6_frac.openfpga
index 490284fe4..5caf1d24c 100644
--- a/openfpga/test_script/s298_k6_frac.openfpga
+++ b/openfpga/test_script/s298_k6_frac.openfpga
@@ -30,7 +30,8 @@ build_fabric --compress_routing --duplicate_grid_pin #--verbose
 repack --verbose
 
 # Build the bitstream 
-fpga_bitstream --verbose
+#  - Output the fabric-independent bitstream to a file
+fpga_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
 
 # Write the Verilog netlit for FPGA fabric
 #  - Enable the use of explicit port mapping in Verilog netlist

From 410dcf6ab6d194aebc0f16e2f8f6b759b8e66c3d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 26 Feb 2020 11:42:18 -0700
Subject: [PATCH 212/645] debugged LUT bitstream

---
 openfpga/src/fpga_bitstream/build_grid_bitstream.cpp | 3 ---
 openfpga/src/repack/build_physical_truth_table.cpp   | 5 ++---
 openfpga/src/repack/repack.cpp                       | 2 +-
 3 files changed, 3 insertions(+), 7 deletions(-)

diff --git a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
index b50d05f85..253798c86 100644
--- a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
+++ b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
@@ -406,9 +406,6 @@ void build_lut_bitstream(BitstreamManager& bitstream_manager,
   /* Generate bitstream for mode-select ports */
   if (0 != lut_mode_select_ports.size()) {
     std::vector<bool> mode_select_bitstream;
-    /* TODO: Xifan Tang: find out why some lut_pb has no mode bits!!!
-     * I suspect that wire LUTs are not mapped to any pb
-     */
     if (true == physical_pb.valid_pb_id(lut_pb_id)) {
       mode_select_bitstream = generate_mode_select_bitstream(physical_pb.mode_bits(lut_pb_id));
     } else { /* get default mode_bits */
diff --git a/openfpga/src/repack/build_physical_truth_table.cpp b/openfpga/src/repack/build_physical_truth_table.cpp
index c749ae206..5e291d88b 100644
--- a/openfpga/src/repack/build_physical_truth_table.cpp
+++ b/openfpga/src/repack/build_physical_truth_table.cpp
@@ -98,10 +98,9 @@ void build_physical_pb_lut_truth_tables(PhysicalPb& physical_pb,
     input_nets.push_back(physical_pb.pb_graph_pin_atom_net(lut_pb_id, &(pb_graph_node->input_pins[0][ipin]))); 
   }
 
-
   /* Find all the nets mapped to each outputs */
-  for (int iport = 0; iport < pb_graph_node->num_input_ports; ++iport) {
-    for (int ipin = 0; ipin < pb_graph_node->num_input_pins[iport]; ++ipin) {
+  for (int iport = 0; iport < pb_graph_node->num_output_ports; ++iport) {
+    for (int ipin = 0; ipin < pb_graph_node->num_output_pins[iport]; ++ipin) {
       const t_pb_graph_pin* output_pin = &(pb_graph_node->output_pins[iport][ipin]);
       AtomNetId output_net = physical_pb.pb_graph_pin_atom_net(lut_pb_id, output_pin); 
       /* Bypass unmapped pins */
diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp
index 371d4ab46..6f312c0b7 100644
--- a/openfpga/src/repack/repack.cpp
+++ b/openfpga/src/repack/repack.cpp
@@ -292,7 +292,7 @@ void repack_cluster(const AtomContext& atom_ctx,
                                            clustering_ctx.clb_nlist.block_pb(block_id)->pb_route,
                                            atom_ctx,
                                            device_annotation);
-  /* TODO: save routing results */
+  /* Save routing results */
   save_lb_router_results_to_physical_pb(phy_pb, lb_router, lb_rr_graph);
   VTR_LOGV(verbose, "Saved results in physical pb\n");
 

From 25e0583636b4893fbdab8f13bba41d50a06af805 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 26 Feb 2020 17:10:57 -0700
Subject: [PATCH 213/645] add io location map data structure and start porting
 verilog testbench generator

---
 openfpga/src/base/io_location_map.cpp         |  46 ++
 openfpga/src/base/io_location_map.h           |  39 ++
 openfpga/src/base/openfpga_context.h          |   4 +
 .../fpga_verilog/verilog_testbench_utils.cpp  | 576 ++++++++++++++++++
 .../fpga_verilog/verilog_testbench_utils.h    |  86 +++
 .../src/fpga_verilog/verilog_writer_utils.h   |   1 +
 openfpga/test_script/s298_k6_frac.openfpga    |   2 +-
 7 files changed, 753 insertions(+), 1 deletion(-)
 create mode 100644 openfpga/src/base/io_location_map.cpp
 create mode 100644 openfpga/src/base/io_location_map.h
 create mode 100644 openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
 create mode 100644 openfpga/src/fpga_verilog/verilog_testbench_utils.h

diff --git a/openfpga/src/base/io_location_map.cpp b/openfpga/src/base/io_location_map.cpp
new file mode 100644
index 000000000..7e0c07dfa
--- /dev/null
+++ b/openfpga/src/base/io_location_map.cpp
@@ -0,0 +1,46 @@
+/******************************************************************************
+ * Memember functions for data structure IoLocationMap
+ ******************************************************************************/
+#include "vtr_assert.h"
+
+#include "io_location_map.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/**************************************************
+ * Public Accessors 
+ *************************************************/
+size_t IoLocationMap::io_index(const size_t& x, const size_t& y, const size_t& z) const {
+  if (x >= io_indices_.size()) {
+    return size_t(-1);
+  }
+
+  if (y >= io_indices_[x].size()) {
+    return size_t(-1);
+  }
+
+  if (z >= io_indices_[x][y].size()) {
+    return size_t(-1);
+  }
+
+  return io_indices_[x][y][z];
+}
+
+void IoLocationMap::set_io_index(const size_t& x, const size_t& y, const size_t& z, const size_t& io_index) {
+  if (x >= io_indices_.size()) {
+    io_indices_.resize(x);
+  }
+
+  if (y >= io_indices_[x].size()) {
+    io_indices_[x].resize(y);
+  }
+
+  if (z >= io_indices_[x][y].size()) {
+    io_indices_[x][y].resize(z);
+  }
+
+  io_indices_[x][y][z] = io_index;
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/base/io_location_map.h b/openfpga/src/base/io_location_map.h
new file mode 100644
index 000000000..de6422d23
--- /dev/null
+++ b/openfpga/src/base/io_location_map.h
@@ -0,0 +1,39 @@
+#ifndef IO_LOCATION_MAP_H
+#define IO_LOCATION_MAP_H
+
+/********************************************************************
+ * Include header files required by the data structure definition
+ *******************************************************************/
+#include <vector>
+
+/* Begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * I/O location map is a data structure to bridge the index of I/Os
+ * in the FPGA fabric, i.e., the module graph, and logical location
+ * of the I/O in VPR coordinate system
+ *
+ * For example 
+ *              io[0]   io[1]          io[2]
+ *           +-----------------+    +--------+
+ *           |        |        |    |        |
+ *           |  I/O   |  I/O   |    |  I/O   |
+ *           | [0][y] | [0][y] |    | [1][y] |
+ *           |  [0]   |  [1]   |    |  [0]   |
+ *           +-----------------+    +--------+
+ *
+ *******************************************************************/
+class IoLocationMap {
+  public: /* Public aggregators */
+    size_t io_index(const size_t& x, const size_t& y, const size_t& z) const;
+  public: /* Public mutators */
+    void set_io_index(const size_t& x, const size_t& y, const size_t& z, const size_t& io_index);
+  private: /* Internal Data */
+    /* I/O index fast lookup by [x][y][z] location */
+    std::vector<std::vector<std::vector<size_t>>> io_indices_;
+};
+
+} /* End namespace openfpga*/
+
+#endif
diff --git a/openfpga/src/base/openfpga_context.h b/openfpga/src/base/openfpga_context.h
index 521a2cf6a..4b6cdf2d2 100644
--- a/openfpga/src/base/openfpga_context.h
+++ b/openfpga/src/base/openfpga_context.h
@@ -15,6 +15,7 @@
 #include "openfpga_flow_manager.h"
 #include "bitstream_manager.h"
 #include "device_rr_gsb.h"
+#include "io_location_map.h"
 
 /********************************************************************
  * This file includes the declaration of the date structure 
@@ -58,6 +59,7 @@ class OpenfpgaContext : public Context  {
     const openfpga::FlowManager& flow_manager() const { return flow_manager_; }
     const openfpga::BitstreamManager& bitstream_manager() const { return bitstream_manager_; }
     const std::vector<openfpga::ConfigBitId>& fabric_bitstream() const { return fabric_bitstream_; }
+    const openfpga::IoLocationMap& io_location_map() { return io_location_map_; }
   public:  /* Public mutators */
     openfpga::Arch& mutable_arch() { return arch_; }
     openfpga::VprDeviceAnnotation& mutable_vpr_device_annotation() { return vpr_device_annotation_; }
@@ -72,6 +74,7 @@ class OpenfpgaContext : public Context  {
     openfpga::FlowManager& mutable_flow_manager() { return flow_manager_; }
     openfpga::BitstreamManager& mutable_bitstream_manager() { return bitstream_manager_; }
     std::vector<openfpga::ConfigBitId>& mutable_fabric_bitstream() { return fabric_bitstream_; }
+    openfpga::IoLocationMap& mutable_io_location_map() { return io_location_map_; }
   private: /* Internal data */
     /* Data structure to store information from read_openfpga_arch library */
     openfpga::Arch arch_;
@@ -102,6 +105,7 @@ class OpenfpgaContext : public Context  {
 
     /* Fabric module graph */
     openfpga::ModuleManager module_graph_;
+    openfpga::IoLocationMap io_location_map_;
 
     /* Bitstream database */
     openfpga::BitstreamManager bitstream_manager_;
diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
new file mode 100644
index 000000000..e73fe5ee4
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
@@ -0,0 +1,576 @@
+/********************************************************************
+ * This file includes most utilized functions that are used to create
+ * Verilog testbenches
+ *
+ * Note: please try to avoid using global variables in this file
+ * so that we can make it free to use anywhere
+ *******************************************************************/
+#include <iomanip>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_port.h"
+#include "openfpga_digest.h"
+
+#include "verilog_port_types.h"
+
+#include "verilog_constants.h"
+#include "verilog_writer_utils.h"
+#include "verilog_testbench_utils.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Print an instance of the FPGA top-level module
+ *******************************************************************/
+void print_verilog_testbench_fpga_instance(std::fstream& fp,
+                                           const ModuleManager& module_manager,
+                                           const ModuleId& top_module,
+                                           const std::string& top_instance_name) {
+  /* Validate the file stream */
+  valid_file_stream(fp);
+
+  /* Include defined top-level module */
+  print_verilog_comment(fp, std::string("----- FPGA top-level module to be capsulated -----"));
+
+  /* Create an empty port-to-port name mapping, because we use default names */
+  std::map<std::string, BasicPort> port2port_name_map;
+
+  /* Use explicit port mapping for a clean instanciation */
+  print_verilog_module_instance(fp, module_manager, top_module, 
+                                top_instance_name, 
+                                port2port_name_map, true); 
+
+  /* Add an empty line as a splitter */
+  fp << std::endl;
+}
+
+/********************************************************************
+ * Instanciate the input benchmark module
+ *******************************************************************/
+void print_verilog_testbench_benchmark_instance(std::fstream& fp,
+                                                const std::string& module_name,
+                                                const std::string& instance_name,
+                                                const std::string& module_input_port_postfix,
+                                                const std::string& module_output_port_postfix,
+                                                const std::string& output_port_postfix,
+                                                const AtomContext& atom_ctx,
+                                                const bool& use_explicit_port_map) {
+  /* Validate the file stream */
+  valid_file_stream(fp);
+
+  fp << "\t" << module_name << " " << instance_name << "(" << std::endl;
+
+  size_t port_counter = 0;
+  for (const AtomBlockId& atom_blk : atom_ctx.nlist.blocks()) {
+    /* Bypass non-I/O atom blocks ! */
+    if ( (AtomBlockType::INPAD != atom_ctx.nlist.block_type(atom_blk))
+      && (AtomBlockType::OUTPAD != atom_ctx.nlist.block_type(atom_blk)) ) {
+      continue;
+    }
+    /* The first port does not need a comma */
+    if(0 < port_counter){
+      fp << "," << std::endl;
+    }
+    /* Input port follows the logical block name while output port requires a special postfix */
+    if (AtomBlockType::INPAD == atom_ctx.nlist.block_type(atom_blk)) {
+      fp << "\t\t";
+      if (true == use_explicit_port_map) {
+        fp << "." << atom_ctx.nlist.block_name(atom_blk) << module_input_port_postfix << "(";
+      }
+      fp << atom_ctx.nlist.block_name(atom_blk);
+      if (true == use_explicit_port_map) {
+        fp << ")";
+      }
+    } else {
+      VTR_ASSERT_SAFE(AtomBlockType::OUTPAD == atom_ctx.nlist.block_type(atom_blk));
+      fp << "\t\t";
+      if (true == use_explicit_port_map) {
+        fp << "." << atom_ctx.nlist.block_name(atom_blk) << module_output_port_postfix << "(";
+      }
+      fp << atom_ctx.nlist.block_name(atom_blk) << output_port_postfix;
+      if (true == use_explicit_port_map) {
+        fp << ")";
+      }
+    }
+    /* Update the counter */
+    port_counter++;
+  }
+  fp << "\t);" << std::endl;
+}
+
+/********************************************************************
+ * This function adds stimuli to I/Os of FPGA fabric
+ * 1. For mapped I/Os, this function will wire them to the input ports
+ *    of the pre-configured FPGA top module
+ * 2. For unmapped I/Os, this function will assign a constant value
+ *    by default 
+ *******************************************************************/
+void print_verilog_testbench_connect_fpga_ios(std::fstream& fp,
+                                              const ModuleManager& module_manager,
+                                              const ModuleId& top_module,
+                                              const AtomContext& atom_ctx,
+                                              const PlacementContext& place_ctx,
+                                              const IoLocationMap& io_location_map,
+                                              const std::string& io_input_port_name_postfix,
+                                              const std::string& io_output_port_name_postfix,
+                                              const size_t& unused_io_value) {
+  /* Validate the file stream */
+  valid_file_stream(fp);
+
+  /* In this function, we support only 1 type of I/Os */
+  VTR_ASSERT(1 == module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPIO_PORT).size());
+  BasicPort module_io_port = module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPIO_PORT)[0];
+
+  /* Keep tracking which I/Os have been used */
+  std::vector<bool> io_used(module_io_port.get_width(), false);
+
+  /* See if this I/O should be wired to a benchmark input/output */
+  /* Add signals from blif benchmark and short-wire them to FPGA I/O PADs
+   * This brings convenience to checking functionality  
+   */
+  print_verilog_comment(fp, std::string("----- Link BLIF Benchmark I/Os to FPGA I/Os -----"));
+
+  for (const AtomBlockId& atom_blk : atom_ctx.nlist.blocks()) {
+    /* Bypass non-I/O atom blocks ! */
+    if ( (AtomBlockType::INPAD != atom_ctx.nlist.block_type(atom_blk))
+      && (AtomBlockType::OUTPAD != atom_ctx.nlist.block_type(atom_blk)) ) {
+      continue;
+    }
+
+    /* Find the index of the mapped GPIO in top-level FPGA fabric */
+    size_t io_index = io_location_map.io_index(place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.x,
+                                               place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.y,
+                                               place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.z);
+
+    /* Ensure that IO index is in range */
+    BasicPort module_mapped_io_port = module_io_port; 
+    /* Set the port pin index */ 
+    VTR_ASSERT(io_index < module_mapped_io_port.get_width());
+    module_mapped_io_port.set_width(io_index, io_index);
+
+    /* Create the port for benchmark I/O, due to BLIF benchmark, each I/O always has a size of 1 
+     * In addition, the input and output ports may have different postfix in naming
+     * due to verification context! Here, we give full customization on naming 
+     */
+    BasicPort benchmark_io_port;
+    if (AtomBlockType::INPAD == atom_ctx.nlist.block_type(atom_blk)) {
+      benchmark_io_port.set_name(std::string(atom_ctx.nlist.block_name(atom_blk) + io_input_port_name_postfix)); 
+      benchmark_io_port.set_width(1);
+      print_verilog_comment(fp, std::string("----- Blif Benchmark input " + atom_ctx.nlist.block_name(atom_blk) + " is mapped to FPGA IOPAD " + module_mapped_io_port.get_name() + "[" + std::to_string(io_index) + "] -----"));
+      print_verilog_wire_connection(fp, module_mapped_io_port, benchmark_io_port, false);
+    } else {
+      VTR_ASSERT(AtomBlockType::OUTPAD == atom_ctx.nlist.block_type(atom_blk));
+      benchmark_io_port.set_name(std::string(atom_ctx.nlist.block_name(atom_blk) + io_output_port_name_postfix)); 
+      benchmark_io_port.set_width(1);
+      print_verilog_comment(fp, std::string("----- Blif Benchmark output " + atom_ctx.nlist.block_name(atom_blk) + " is mapped to FPGA IOPAD " + module_mapped_io_port.get_name() + "[" + std::to_string(io_index) + "] -----"));
+      print_verilog_wire_connection(fp, benchmark_io_port, module_mapped_io_port, false);
+    }
+
+    /* Mark this I/O has been used/wired */
+    io_used[io_index] = true;
+  }
+
+  /* Add an empty line as a splitter */
+  fp << std::endl;
+
+  /* Wire the unused iopads to a constant */
+  print_verilog_comment(fp, std::string("----- Wire unused FPGA I/Os to constants -----"));
+  for (size_t io_index = 0; io_index < io_used.size(); ++io_index) {
+    /* Bypass used iopads */
+    if (true == io_used[io_index]) {
+      continue;
+    }
+
+    /* Wire to a contant */
+    BasicPort module_unused_io_port = module_io_port; 
+    /* Set the port pin index */ 
+    module_unused_io_port.set_width(io_index, io_index);
+
+    std::vector<size_t> default_values(module_unused_io_port.get_width(), unused_io_value);
+    print_verilog_wire_constant_values(fp, module_unused_io_port, default_values);
+  }
+
+  /* Add an empty line as a splitter */
+  fp << std::endl;
+}
+
+/********************************************************************
+ * Print Verilog codes to set up a timeout for the simulation 
+ * and dump the waveform to VCD files
+ *
+ * Note that: these codes are tuned for Icarus simulator!!!
+ *******************************************************************/
+void print_verilog_timeout_and_vcd(std::fstream& fp,
+                                   const std::string& icarus_preprocessing_flag,
+                                   const std::string& module_name,
+                                   const std::string& vcd_fname,
+                                   const std::string& simulation_start_counter_name,
+                                   const std::string& error_counter_name,
+                                   const int& simulation_time) {
+  /* Validate the file stream */
+  valid_file_stream(fp);
+
+  /* The following verilog codes are tuned for Icarus */
+  print_verilog_preprocessing_flag(fp, icarus_preprocessing_flag); 
+
+  print_verilog_comment(fp, std::string("----- Begin Icarus requirement -------"));
+
+  fp << "\tinitial begin" << std::endl;
+  fp << "\t\t$dumpfile(\"" << vcd_fname << "\");" << std::endl;
+  fp << "\t\t$dumpvars(1, " << module_name << ");" << std::endl;
+  fp << "\tend" << std::endl;
+
+  /* Condition ends for the Icarus requirement */
+  print_verilog_endif(fp);
+
+  print_verilog_comment(fp, std::string("----- END Icarus requirement -------"));
+
+  /* Add an empty line as splitter */
+  fp << std::endl;
+
+  BasicPort sim_start_port(simulation_start_counter_name, 1);
+
+  fp << "initial begin" << std::endl;
+  fp << "\t" << generate_verilog_port(VERILOG_PORT_CONKT, sim_start_port) << " <= 1'b1;" << std::endl;
+  fp << "\t$timeformat(-9, 2, \"ns\", 20);" << std::endl;
+  fp << "\t$display(\"Simulation start\");" << std::endl;
+  print_verilog_comment(fp, std::string("----- Can be changed by the user for his/her need -------"));
+  fp << "\t#" << simulation_time << std::endl;
+  fp << "\tif(" << error_counter_name << " == 0) begin" << std::endl;
+  fp << "\t\t$display(\"Simulation Succeed\");" << std::endl;
+  fp << "\tend else begin" << std::endl;
+  fp << "\t\t$display(\"Simulation Failed with " << std::string("%d") << " error(s)\", " << error_counter_name << ");" << std::endl;
+  fp << "\tend" << std::endl;
+  fp << "\t$finish;" << std::endl;
+  fp << "end" << std::endl;
+
+  /* Add an empty line as splitter */
+  fp << std::endl;
+}
+
+/********************************************************************
+ * Generate the clock port name to be used in this testbench
+ *
+ * Restrictions:
+ * Assume this is a single clock benchmark
+ *******************************************************************/
+BasicPort generate_verilog_testbench_clock_port(const std::vector<std::string>& clock_port_names,
+                                                const std::string& default_clock_name) {
+  if (0 == clock_port_names.size()) {
+    return BasicPort(default_clock_name, 1); 
+  }
+
+  VTR_ASSERT(1 == clock_port_names.size());
+  return BasicPort(clock_port_names[0], 1); 
+}
+
+/********************************************************************
+ * Print Verilog codes to check the equivalence of output vectors 
+ *
+ * Restriction: this function only supports single clock benchmarks!
+ *******************************************************************/
+void print_verilog_testbench_check(std::fstream& fp,
+                                   const std::string& autochecked_preprocessing_flag,
+                                   const std::string& simulation_start_counter_name,
+                                   const std::string& benchmark_port_postfix,
+                                   const std::string& fpga_port_postfix,
+                                   const std::string& check_flag_port_postfix,
+                                   const std::string& error_counter_name,
+                                   const AtomContext& atom_ctx,
+                                   const std::vector<std::string>& clock_port_names,
+                                   const std::string& default_clock_name) {
+
+  /* Validate the file stream */
+  valid_file_stream(fp);
+
+  /* Add output autocheck conditionally: only when a preprocessing flag is enable */
+  print_verilog_preprocessing_flag(fp, autochecked_preprocessing_flag); 
+
+  print_verilog_comment(fp, std::string("----- Begin checking output vectors -------"));
+
+  BasicPort clock_port = generate_verilog_testbench_clock_port(clock_port_names, default_clock_name);
+
+  print_verilog_comment(fp, std::string("----- Skip the first falling edge of clock, it is for initialization -------"));
+
+  BasicPort sim_start_port(simulation_start_counter_name, 1);
+
+  fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, sim_start_port) << ";" << std::endl;
+  fp << std::endl;
+
+  fp << "\talways@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << ") begin" << std::endl;
+  fp << "\t\tif (1'b1 == " << generate_verilog_port(VERILOG_PORT_CONKT, sim_start_port) << ") begin" << std::endl;
+  fp << "\t\t";
+  print_verilog_register_connection(fp, sim_start_port, sim_start_port, true);
+  fp << "\t\tend else begin" << std::endl;
+
+  for (const AtomBlockId& atom_blk : atom_ctx.nlist.blocks()) {
+    /* Bypass non-I/O atom blocks ! */
+    if ( (AtomBlockType::INPAD != atom_ctx.nlist.block_type(atom_blk))
+      && (AtomBlockType::OUTPAD != atom_ctx.nlist.block_type(atom_blk)) ) {
+      continue;
+    }
+
+    if (AtomBlockType::OUTPAD == atom_ctx.nlist.block_type(atom_blk)) {
+     fp << "\t\t\tif(!(" << atom_ctx.nlist.block_name(atom_blk) << fpga_port_postfix;
+     fp << " === " << atom_ctx.nlist.block_name(atom_blk) << benchmark_port_postfix;
+     fp << ") && !(" << atom_ctx.nlist.block_name(atom_blk) << benchmark_port_postfix;
+     fp << " === 1'bx)) begin" << std::endl;
+     fp << "\t\t\t\t" << atom_ctx.nlist.block_name(atom_blk) << check_flag_port_postfix << " <= 1'b1;" << std::endl;
+     fp << "\t\t\tend else begin" << std::endl;
+     fp << "\t\t\t\t" << atom_ctx.nlist.block_name(atom_blk) << check_flag_port_postfix << "<= 1'b0;" << std::endl;
+     fp << "\t\t\tend" << std::endl; 
+    }
+  } 
+  fp << "\t\tend" << std::endl;
+  fp << "\tend" << std::endl;
+
+  /* Add an empty line as splitter */
+  fp << std::endl;
+
+  for (const AtomBlockId& atom_blk : atom_ctx.nlist.blocks()) {
+    /* Only care about output atom blocks ! */
+    if (AtomBlockType::OUTPAD != atom_ctx.nlist.block_type(atom_blk)) {
+      continue;
+    }
+
+    fp << "\talways@(posedge " << atom_ctx.nlist.block_name(atom_blk) << check_flag_port_postfix << ") begin" << std::endl;
+    fp << "\t\tif(" << atom_ctx.nlist.block_name(atom_blk) << check_flag_port_postfix << ") begin" << std::endl;
+    fp << "\t\t\t" << error_counter_name << " = " << error_counter_name << " + 1;" << std::endl;
+    fp << "\t\t\t$display(\"Mismatch on " << atom_ctx.nlist.block_name(atom_blk) << fpga_port_postfix << " at time = " << std::string("%t") << "\", $realtime);" << std::endl;
+    fp << "\t\tend" << std::endl;
+    fp << "\tend" << std::endl;
+
+    /* Add an empty line as splitter */
+    fp << std::endl;
+  }
+
+  /* Condition ends */
+  print_verilog_endif(fp);
+
+  /* Add an empty line as splitter */
+  fp << std::endl;
+}
+
+/********************************************************************
+ * Generate random stimulus for the clock port
+ * This function is designed to drive the clock port of a benchmark module
+ * If there is no clock port found, we will give a default clock name
+ * In such case, this clock will not be wired to the benchmark module
+ * but be only used as a synchronizer in verification
+ *******************************************************************/
+void print_verilog_testbench_clock_stimuli(std::fstream& fp,
+                                           const SimulationSetting& simulation_parameters,
+                                           const BasicPort& clock_port) {
+  /* Validate the file stream */
+  valid_file_stream(fp);
+
+  print_verilog_comment(fp, std::string("----- Clock Initialization -------"));
+
+  fp << "\tinitial begin" << std::endl;
+  /* Create clock stimuli */
+  fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << " <= 1'b0;" << std::endl;
+  fp << "\t\twhile(1) begin" << std::endl;
+  fp << "\t\t\t#" << std::setprecision(10) << ((0.5/simulation_parameters.operating_clock_frequency())/VERILOG_SIM_TIMESCALE) << std::endl;
+  fp << "\t\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, clock_port);
+  fp << " <= !";
+  fp << generate_verilog_port(VERILOG_PORT_CONKT, clock_port);
+  fp << ";" << std::endl;
+  fp << "\t\tend" << std::endl;
+
+  fp << "\tend" << std::endl;
+
+  /* Add an empty line as splitter */
+  fp << std::endl;
+}
+
+/********************************************************************
+ * Generate random stimulus for the input ports (non-clock signals)
+ * For clock signals, please use print_verilog_testbench_clock_stimuli
+ *******************************************************************/
+void print_verilog_testbench_random_stimuli(std::fstream& fp,
+                                            const AtomContext& atom_ctx,
+                                            const std::string& check_flag_port_postfix,
+                                            const BasicPort& clock_port) {
+  /* Validate the file stream */
+  valid_file_stream(fp);
+
+  print_verilog_comment(fp, std::string("----- Input Initialization -------"));
+
+  fp << "\tinitial begin" << std::endl;
+
+  for (const AtomBlockId& atom_blk : atom_ctx.nlist.blocks()) {
+    /* Bypass non-I/O atom blocks ! */
+    if ( (AtomBlockType::INPAD != atom_ctx.nlist.block_type(atom_blk))
+      && (AtomBlockType::OUTPAD != atom_ctx.nlist.block_type(atom_blk)) ) {
+      continue;
+    }
+
+    /* TODO: find the clock inputs will be initialized later */
+    if (AtomBlockType::INPAD == atom_ctx.nlist.block_type(atom_blk)) {
+      fp << "\t\t" << atom_ctx.nlist.block_name(atom_blk) << " <= 1'b0;" << std::endl;
+    }
+  }
+
+  /* Add an empty line as splitter */
+  fp << std::endl;
+  
+  /* Set 0 to registers for checking flags */
+  for (const AtomBlockId& atom_blk : atom_ctx.nlist.blocks()) {
+    /* Bypass non-I/O atom blocks ! */
+    if (AtomBlockType::OUTPAD != atom_ctx.nlist.block_type(atom_blk)) {
+      continue;
+    }
+
+    /* Each logical block assumes a single-width port */
+    BasicPort output_port(std::string(atom_ctx.nlist.block_name(atom_blk) + check_flag_port_postfix), 1); 
+    fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, output_port) << " <= 1'b0;" << std::endl;
+  }
+
+  fp << "\tend" << std::endl;
+  /* Finish initialization */
+
+  /* Add an empty line as splitter */
+  fp << std::endl;
+
+  // Not ready yet to determine if input is reset
+/*
+  fprintf(fp, "//----- Reset Stimulis\n");      
+  fprintf(fp, "  initial begin\n");
+  fprintf(fp, "    #%.3f\n",(rand() % 10) + 0.001);
+  fprintf(fp, "    %s <= !%s;\n", reset_input_name, reset_input_name);
+  fprintf(fp, "    #%.3f\n",(rand() % 10) + 0.001);
+  fprintf(fp, "    %s <= !%s;\n", reset_input_name, reset_input_name);
+  fprintf(fp, "    while(1) begin\n");
+  fprintf(fp, "      #%.3f\n", (rand() % 15) + 0.5);
+  fprintf(fp, "      %s <= !%s;\n", reset_input_name, reset_input_name);
+  fprintf(fp, "      #%.3f\n", (rand() % 10000) + 200);
+  fprintf(fp, "      %s <= !%s;\n", reset_input_name, reset_input_name);
+  fprintf(fp, "    end\n");
+  fprintf(fp, "  end\n\n");  
+*/
+
+  print_verilog_comment(fp, std::string("----- Input Stimulus -------"));
+  fp << "\talways@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << ") begin" << std::endl;
+
+  for (const AtomBlockId& atom_blk : atom_ctx.nlist.blocks()) {
+    /* Bypass non-I/O atom blocks ! */
+    if ( (AtomBlockType::INPAD != atom_ctx.nlist.block_type(atom_blk))
+      && (AtomBlockType::OUTPAD != atom_ctx.nlist.block_type(atom_blk)) ) {
+      continue;
+    }
+
+    /* TODO: find the clock inputs will be initialized later */
+    if (AtomBlockType::INPAD != atom_ctx.nlist.block_type(atom_blk)) {
+      fp << "\t\t" << atom_ctx.nlist.block_name(atom_blk) << " <= $random;" << std::endl;
+    }
+  }
+
+  fp << "\tend" << std::endl;
+
+  /* Add an empty line as splitter */
+  fp << std::endl;
+}
+
+/********************************************************************
+ * Print Verilog declaration of shared ports appear in testbenches
+ * which are 
+ * 1. the shared input ports (registers) to drive both 
+ *    FPGA fabric and benchmark instance
+ * 2. the output ports (wires) for both FPGA fabric and benchmark instance
+ * 3. the checking flag ports to evaluate if outputs matches under the
+ *    same input vectors
+ *******************************************************************/
+void print_verilog_testbench_shared_ports(std::fstream& fp,
+                                          const AtomContext& atom_ctx,
+                                          const std::string& benchmark_output_port_postfix,
+                                          const std::string& fpga_output_port_postfix,
+                                          const std::string& check_flag_port_postfix,
+                                          const std::string& autocheck_preprocessing_flag) {
+  /* Validate the file stream */
+  valid_file_stream(fp);
+
+  /* Instantiate register for inputs stimulis */
+  print_verilog_comment(fp, std::string("----- Shared inputs -------"));
+  for (const AtomBlockId& atom_blk : atom_ctx.nlist.blocks()) {
+    /* We care only those logic blocks which are input I/Os */
+    if (AtomBlockType::INPAD != atom_ctx.nlist.block_type(atom_blk)) {
+      continue;
+    }
+
+    /* TODO: Skip clocks because they are handled in another function */
+   
+    /* Each logical block assumes a single-width port */
+    BasicPort input_port(atom_ctx.nlist.block_name(atom_blk), 1); 
+    fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, input_port) << ";" << std::endl;
+  }
+
+  /* Add an empty line as splitter */
+  fp << std::endl;
+
+  /* Instantiate wires for FPGA fabric outputs */
+  print_verilog_comment(fp, std::string("----- FPGA fabric outputs -------"));
+
+  for (const AtomBlockId& atom_blk : atom_ctx.nlist.blocks()) {
+    /* We care only those logic blocks which are output I/Os */
+    if (AtomBlockType::OUTPAD != atom_ctx.nlist.block_type(atom_blk)) {
+      continue;
+    }
+
+    /* Each logical block assumes a single-width port */
+    BasicPort output_port(std::string(atom_ctx.nlist.block_name(atom_blk) + fpga_output_port_postfix), 1); 
+    fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, output_port) << ";" << std::endl;
+  }
+
+  /* Add an empty line as splitter */
+  fp << std::endl;
+
+  /* Benchmark is instanciated conditionally: only when a preprocessing flag is enable */
+  print_verilog_preprocessing_flag(fp, std::string(autocheck_preprocessing_flag)); 
+
+  /* Add an empty line as splitter */
+  fp << std::endl;
+
+  /* Instantiate wire for benchmark output */
+  print_verilog_comment(fp, std::string("----- Benchmark outputs -------"));
+  for (const AtomBlockId& atom_blk : atom_ctx.nlist.blocks()) {
+    /* We care only those logic blocks which are output I/Os */
+    if (AtomBlockType::OUTPAD != atom_ctx.nlist.block_type(atom_blk)) {
+      continue;
+    }
+
+    /* Each logical block assumes a single-width port */
+    BasicPort output_port(std::string(atom_ctx.nlist.block_name(atom_blk) + benchmark_output_port_postfix), 1); 
+    fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, output_port) << ";" << std::endl;
+  }
+
+  /* Add an empty line as splitter */
+  fp << std::endl;
+
+  /* Instantiate register for output comparison */
+  print_verilog_comment(fp, std::string("----- Output vectors checking flags -------"));
+  for (const AtomBlockId& atom_blk : atom_ctx.nlist.blocks()) {
+    /* We care only those logic blocks which are output I/Os */
+    if (AtomBlockType::OUTPAD != atom_ctx.nlist.block_type(atom_blk)) {
+      continue;
+    }
+
+    /* Each logical block assumes a single-width port */
+    BasicPort output_port(std::string(atom_ctx.nlist.block_name(atom_blk) + check_flag_port_postfix), 1); 
+    fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, output_port) << ";" << std::endl;
+  }
+
+  /* Add an empty line as splitter */
+  fp << std::endl;
+
+  /* Condition ends for the benchmark instanciation */
+  print_verilog_endif(fp);
+
+  /* Add an empty line as splitter */
+  fp << std::endl;
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.h b/openfpga/src/fpga_verilog/verilog_testbench_utils.h
new file mode 100644
index 000000000..7de04deeb
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.h
@@ -0,0 +1,86 @@
+#ifndef VERILOG_TESTBENCH_UTILS_H
+#define VERILOG_TESTBENCH_UTILS_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <fstream>
+#include <string>
+#include <vector>
+#include "module_manager.h"
+#include "vpr_context.h"
+#include "io_location_map.h"
+#include "simulation_setting.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void print_verilog_testbench_fpga_instance(std::fstream& fp,
+                                           const ModuleManager& module_manager,
+                                           const ModuleId& top_module,
+                                           const std::string& top_instance_name);
+
+void print_verilog_testbench_benchmark_instance(std::fstream& fp,
+                                                const std::string& module_name,
+                                                const std::string& instance_name,
+                                                const std::string& module_input_port_postfix,
+                                                const std::string& module_output_port_postfix,
+                                                const std::string& output_port_postfix,
+                                                const AtomContext& atom_ctx,
+                                                const bool& use_explicit_port_map);
+
+void print_verilog_testbench_connect_fpga_ios(std::fstream& fp,
+                                              const ModuleManager& module_manager,
+                                              const ModuleId& top_module,
+                                              const AtomContext& atom_ctx,
+                                              const PlacementContext& place_ctx,
+                                              const IoLocationMap& io_location_map,
+                                              const std::string& io_input_port_name_postfix,
+                                              const std::string& io_output_port_name_postfix,
+                                              const size_t& unused_io_value);
+
+void print_verilog_timeout_and_vcd(std::fstream& fp,
+                                   const std::string& icarus_preprocessing_flag,
+                                   const std::string& module_name,
+                                   const std::string& vcd_fname,
+                                   const std::string& simulation_start_counter_name,
+                                   const std::string& error_counter_name,
+                                   const int& simulation_time);
+
+BasicPort generate_verilog_testbench_clock_port(const std::vector<std::string>& clock_port_names,
+                                                const std::string& default_clock_name);
+
+void print_verilog_testbench_check(std::fstream& fp,
+                                   const std::string& autochecked_preprocessing_flag,
+                                   const std::string& simulation_start_counter_name,
+                                   const std::string& benchmark_port_postfix,
+                                   const std::string& fpga_port_postfix,
+                                   const std::string& check_flag_port_postfix,
+                                   const std::string& error_counter_name,
+                                   const AtomContext& atom_ctx,
+                                   const std::vector<std::string>& clock_port_names,
+                                   const std::string& default_clock_name);
+
+void print_verilog_testbench_clock_stimuli(std::fstream& fp,
+                                           const SimulationSetting& simulation_parameters,
+                                           const BasicPort& clock_port);
+
+void print_verilog_testbench_random_stimuli(std::fstream& fp,
+                                            const AtomContext& atom_ctx,
+                                            const std::string& check_flag_port_postfix,
+                                            const BasicPort& clock_port);
+
+void print_verilog_testbench_shared_ports(std::fstream& fp,
+                                          const AtomContext& atom_ctx,
+                                          const std::string& benchmark_output_port_postfix,
+                                          const std::string& fpga_output_port_postfix,
+                                          const std::string& check_flag_port_postfix,
+                                          const std::string& autocheck_preprocessing_flag);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/fpga_verilog/verilog_writer_utils.h b/openfpga/src/fpga_verilog/verilog_writer_utils.h
index b145d8be6..8e6cddaaa 100644
--- a/openfpga/src/fpga_verilog/verilog_writer_utils.h
+++ b/openfpga/src/fpga_verilog/verilog_writer_utils.h
@@ -14,6 +14,7 @@
 #include <string>
 #include "openfpga_port.h"
 #include "verilog_port_types.h"
+#include "circuit_library.h"
 #include "module_manager.h"
 
 /********************************************************************
diff --git a/openfpga/test_script/s298_k6_frac.openfpga b/openfpga/test_script/s298_k6_frac.openfpga
index 5caf1d24c..0b2e3cc13 100644
--- a/openfpga/test_script/s298_k6_frac.openfpga
+++ b/openfpga/test_script/s298_k6_frac.openfpga
@@ -27,7 +27,7 @@ build_fabric --compress_routing --duplicate_grid_pin #--verbose
 # Repack the netlist to physical pbs
 # This must be done before bitstream generator and testbench generation
 # Strongly recommend it is done after all the fix-up have been applied
-repack --verbose
+repack #--verbose
 
 # Build the bitstream 
 #  - Output the fabric-independent bitstream to a file

From b3796b08181a74eb5dcb35c34d0c65d761aba7cc Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 26 Feb 2020 19:58:18 -0700
Subject: [PATCH 214/645] build io location map

---
 openfpga/src/base/io_location_map.cpp       |  6 +--
 openfpga/src/base/openfpga_build_fabric.cpp | 43 +++++++++++----------
 openfpga/src/base/openfpga_build_fabric.h   |  2 +-
 openfpga/src/fabric/build_device_module.cpp |  6 ++-
 openfpga/src/fabric/build_device_module.h   |  3 +-
 openfpga/src/fabric/build_top_module.cpp    | 20 +++++++++-
 openfpga/src/fabric/build_top_module.h      |  2 +
 7 files changed, 53 insertions(+), 29 deletions(-)

diff --git a/openfpga/src/base/io_location_map.cpp b/openfpga/src/base/io_location_map.cpp
index 7e0c07dfa..460ba080d 100644
--- a/openfpga/src/base/io_location_map.cpp
+++ b/openfpga/src/base/io_location_map.cpp
@@ -29,15 +29,15 @@ size_t IoLocationMap::io_index(const size_t& x, const size_t& y, const size_t& z
 
 void IoLocationMap::set_io_index(const size_t& x, const size_t& y, const size_t& z, const size_t& io_index) {
   if (x >= io_indices_.size()) {
-    io_indices_.resize(x);
+    io_indices_.resize(x + 1);
   }
 
   if (y >= io_indices_[x].size()) {
-    io_indices_[x].resize(y);
+    io_indices_[x].resize(y + 1);
   }
 
   if (z >= io_indices_[x][y].size()) {
-    io_indices_[x][y].resize(z);
+    io_indices_[x][y].resize(z + 1);
   }
 
   io_indices_[x][y][z] = io_index;
diff --git a/openfpga/src/base/openfpga_build_fabric.cpp b/openfpga/src/base/openfpga_build_fabric.cpp
index 5c3d8a69d..a1e90055b 100644
--- a/openfpga/src/base/openfpga_build_fabric.cpp
+++ b/openfpga/src/base/openfpga_build_fabric.cpp
@@ -21,43 +21,43 @@ namespace openfpga {
  * This function should only be called after the GSB builder is done
  *******************************************************************/
 static 
-void compress_routing_hierarchy(OpenfpgaContext& openfpga_context,
+void compress_routing_hierarchy(OpenfpgaContext& openfpga_ctx,
                                 const bool& verbose_output) {
   vtr::ScopedStartFinishTimer timer("Identify unique General Switch Blocks (GSBs)");
 
   /* Build unique module lists */
-  openfpga_context.mutable_device_rr_gsb().build_unique_module(g_vpr_ctx.device().rr_graph);
+  openfpga_ctx.mutable_device_rr_gsb().build_unique_module(g_vpr_ctx.device().rr_graph);
 
   /* Report the stats */
   VTR_LOGV(verbose_output, 
            "Detected %lu unique X-direction connection blocks from a total of %d (compression rate=%d%)\n",
-           openfpga_context.device_rr_gsb().get_num_cb_unique_module(CHANX),
-           find_device_rr_gsb_num_cb_modules(openfpga_context.device_rr_gsb(), CHANX),
-           100 * (openfpga_context.device_rr_gsb().get_num_cb_unique_module(CHANX) / find_device_rr_gsb_num_cb_modules(openfpga_context.device_rr_gsb(), CHANX) - 1));
+           openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANX),
+           find_device_rr_gsb_num_cb_modules(openfpga_ctx.device_rr_gsb(), CHANX),
+           100 * (openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANX) / find_device_rr_gsb_num_cb_modules(openfpga_ctx.device_rr_gsb(), CHANX) - 1));
 
   VTR_LOGV(verbose_output,
            "Detected %lu unique Y-direction connection blocks from a total of %d (compression rate=%d%)\n",
-           openfpga_context.device_rr_gsb().get_num_cb_unique_module(CHANY),
-           find_device_rr_gsb_num_cb_modules(openfpga_context.device_rr_gsb(), CHANY),
-           100 * (openfpga_context.device_rr_gsb().get_num_cb_unique_module(CHANY) / find_device_rr_gsb_num_cb_modules(openfpga_context.device_rr_gsb(), CHANY) - 1));
+           openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANY),
+           find_device_rr_gsb_num_cb_modules(openfpga_ctx.device_rr_gsb(), CHANY),
+           100 * (openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANY) / find_device_rr_gsb_num_cb_modules(openfpga_ctx.device_rr_gsb(), CHANY) - 1));
 
   VTR_LOGV(verbose_output,
            "Detected %lu unique switch blocks from a total of %d (compression rate=%d%)\n",
-           openfpga_context.device_rr_gsb().get_num_sb_unique_module(),
-           find_device_rr_gsb_num_sb_modules(openfpga_context.device_rr_gsb()),
-           100 * (openfpga_context.device_rr_gsb().get_num_sb_unique_module() / find_device_rr_gsb_num_sb_modules(openfpga_context.device_rr_gsb()) - 1));
+           openfpga_ctx.device_rr_gsb().get_num_sb_unique_module(),
+           find_device_rr_gsb_num_sb_modules(openfpga_ctx.device_rr_gsb()),
+           100 * (openfpga_ctx.device_rr_gsb().get_num_sb_unique_module() / find_device_rr_gsb_num_sb_modules(openfpga_ctx.device_rr_gsb()) - 1));
 
   VTR_LOGV(verbose_output,
            "Detected %lu unique general switch blocks from a total of %d (compression rate=%d%)\n",
-           openfpga_context.device_rr_gsb().get_num_gsb_unique_module(),
-           find_device_rr_gsb_num_gsb_modules(openfpga_context.device_rr_gsb()),
-           100 * (openfpga_context.device_rr_gsb().get_num_gsb_unique_module() / find_device_rr_gsb_num_gsb_modules(openfpga_context.device_rr_gsb()) - 1));
+           openfpga_ctx.device_rr_gsb().get_num_gsb_unique_module(),
+           find_device_rr_gsb_num_gsb_modules(openfpga_ctx.device_rr_gsb()),
+           100 * (openfpga_ctx.device_rr_gsb().get_num_gsb_unique_module() / find_device_rr_gsb_num_gsb_modules(openfpga_ctx.device_rr_gsb()) - 1));
 }
 
 /********************************************************************
  * Build the module graph for FPGA device
  *******************************************************************/
-void build_fabric(OpenfpgaContext& openfpga_context,
+void build_fabric(OpenfpgaContext& openfpga_ctx,
                   const Command& cmd, const CommandContext& cmd_context) { 
 
   CommandOptionId opt_compress_routing = cmd.option("compress_routing");
@@ -65,16 +65,17 @@ void build_fabric(OpenfpgaContext& openfpga_context,
   CommandOptionId opt_verbose = cmd.option("verbose");
   
   if (true == cmd_context.option_enable(cmd, opt_compress_routing)) {
-    compress_routing_hierarchy(openfpga_context, cmd_context.option_enable(cmd, opt_verbose));
+    compress_routing_hierarchy(openfpga_ctx, cmd_context.option_enable(cmd, opt_verbose));
   }
 
   VTR_LOG("\n");
 
-  openfpga_context.mutable_module_graph() = build_device_module_graph(g_vpr_ctx.device(),
-                                                                      const_cast<const OpenfpgaContext&>(openfpga_context),
-                                                                      cmd_context.option_enable(cmd, opt_compress_routing),
-                                                                      cmd_context.option_enable(cmd, opt_duplicate_grid_pin),
-                                                                      cmd_context.option_enable(cmd, opt_verbose));
+  openfpga_ctx.mutable_module_graph() = build_device_module_graph(openfpga_ctx.mutable_io_location_map(),
+                                                                  g_vpr_ctx.device(),
+                                                                  const_cast<const OpenfpgaContext&>(openfpga_ctx),
+                                                                  cmd_context.option_enable(cmd, opt_compress_routing),
+                                                                  cmd_context.option_enable(cmd, opt_duplicate_grid_pin),
+                                                                  cmd_context.option_enable(cmd, opt_verbose));
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_build_fabric.h b/openfpga/src/base/openfpga_build_fabric.h
index 44aa3632c..824ed63a1 100644
--- a/openfpga/src/base/openfpga_build_fabric.h
+++ b/openfpga/src/base/openfpga_build_fabric.h
@@ -15,7 +15,7 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-void build_fabric(OpenfpgaContext& openfpga_context,
+void build_fabric(OpenfpgaContext& openfpga_ctx,
                   const Command& cmd, const CommandContext& cmd_context); 
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/fabric/build_device_module.cpp b/openfpga/src/fabric/build_device_module.cpp
index a137407ed..9680285fa 100644
--- a/openfpga/src/fabric/build_device_module.cpp
+++ b/openfpga/src/fabric/build_device_module.cpp
@@ -26,7 +26,8 @@ namespace openfpga {
  * The main function to be called for building module graphs 
  * for a FPGA fabric
  *******************************************************************/
-ModuleManager build_device_module_graph(const DeviceContext& vpr_device_ctx,
+ModuleManager build_device_module_graph(IoLocationMap& io_location_map,
+                                        const DeviceContext& vpr_device_ctx,
                                         const OpenfpgaContext& openfpga_ctx,
                                         const bool& compress_routing,
                                         const bool& duplicate_grid_pin,
@@ -97,7 +98,8 @@ ModuleManager build_device_module_graph(const DeviceContext& vpr_device_ctx,
   }
 
   /* Build FPGA fabric top-level module */
-  build_top_module(module_manager, openfpga_ctx.arch().circuit_lib, 
+  build_top_module(module_manager, io_location_map,
+                   openfpga_ctx.arch().circuit_lib, 
                    vpr_device_ctx.grid,
                    vpr_device_ctx.rr_graph,
                    openfpga_ctx.device_rr_gsb(), 
diff --git a/openfpga/src/fabric/build_device_module.h b/openfpga/src/fabric/build_device_module.h
index fd585d986..b8f8c0ac8 100644
--- a/openfpga/src/fabric/build_device_module.h
+++ b/openfpga/src/fabric/build_device_module.h
@@ -14,7 +14,8 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-ModuleManager build_device_module_graph(const DeviceContext& vpr_device_ctx,
+ModuleManager build_device_module_graph(IoLocationMap& io_location_map,
+                                        const DeviceContext& vpr_device_ctx,
                                         const OpenfpgaContext& openfpga_ctx,
                                         const bool& compress_routing,
                                         const bool& duplicate_grid_pin,
diff --git a/openfpga/src/fabric/build_top_module.cpp b/openfpga/src/fabric/build_top_module.cpp
index 3357b2b95..7af79d46c 100644
--- a/openfpga/src/fabric/build_top_module.cpp
+++ b/openfpga/src/fabric/build_top_module.cpp
@@ -89,6 +89,7 @@ size_t add_top_module_grid_instance(ModuleManager& module_manager,
 static 
 vtr::Matrix<size_t> add_top_module_grid_instances(ModuleManager& module_manager,
                                                   const ModuleId& top_module,
+                                                  IoLocationMap& io_location_map,
                                                   const DeviceGrid& grids) {
   /* Reserve an array for the instance ids */
   vtr::Matrix<size_t> grid_instance_ids({grids.width(), grids.height()}); 
@@ -142,6 +143,7 @@ vtr::Matrix<size_t> add_top_module_grid_instances(ModuleManager& module_manager,
   }
 
   /* Add instances of I/O grids to top_module */
+  size_t io_counter = 0;
   for (const e_side& io_side : io_sides) {
     for (const vtr::Point<size_t>& io_coordinate : io_coordinates[io_side]) {
       /* Bypass EMPTY grid */
@@ -157,6 +159,21 @@ vtr::Matrix<size_t> add_top_module_grid_instances(ModuleManager& module_manager,
       VTR_ASSERT(true == is_io_type(grids[io_coordinate.x()][io_coordinate.y()].type));
       /* Add a grid module to top_module*/
       grid_instance_ids[io_coordinate.x()][io_coordinate.y()] = add_top_module_grid_instance(module_manager, top_module, grids[io_coordinate.x()][io_coordinate.y()].type, io_side, io_coordinate);
+
+      /* MUST DO: register in io location mapping!
+       * I/O location mapping is a critical look-up for testbench generators
+       * As we add the I/O grid instances to top module by following order:
+       * TOP -> RIGHT -> BOTTOM -> LEFT
+       * The I/O index will increase in this way as well.
+       * This organization I/O indices is also consistent to the way 
+       * that GPIOs are wired in function connect_gpio_module()
+       *
+       * Note: if you change the GPIO function, you should update here as well!
+       */
+      for (int z = 0; z < grids[io_coordinate.x()][io_coordinate.y()].type->capacity; ++z) {
+        io_location_map.set_io_index(io_coordinate.x(), io_coordinate.y(), z, io_counter);
+      }
+      io_counter++;
     }
   }
 
@@ -280,6 +297,7 @@ vtr::Matrix<size_t> add_top_module_connection_block_instances(ModuleManager& mod
  * 5. Add module nets/submodules to connect configuration ports
  *******************************************************************/
 void build_top_module(ModuleManager& module_manager,
+                      IoLocationMap& io_location_map,
                       const CircuitLibrary& circuit_lib,
                       const DeviceGrid& grids,
                       const RRGraph& rr_graph,
@@ -301,7 +319,7 @@ void build_top_module(ModuleManager& module_manager,
  
   /* Add sub modules, which are grid, SB and CBX/CBY modules as instances */
   /* Add all the grids across the fabric */
-  vtr::Matrix<size_t> grid_instance_ids = add_top_module_grid_instances(module_manager, top_module, grids);
+  vtr::Matrix<size_t> grid_instance_ids = add_top_module_grid_instances(module_manager, top_module, io_location_map, grids);
   /* Add all the SBs across the fabric */
   vtr::Matrix<size_t> sb_instance_ids = add_top_module_switch_block_instances(module_manager, top_module, device_rr_gsb, compact_routing_hierarchy);
   /* Add all the CBX and CBYs across the fabric */
diff --git a/openfpga/src/fabric/build_top_module.h b/openfpga/src/fabric/build_top_module.h
index 3b6badfb2..4ced0735b 100644
--- a/openfpga/src/fabric/build_top_module.h
+++ b/openfpga/src/fabric/build_top_module.h
@@ -14,6 +14,7 @@
 #include "tile_direct.h"
 #include "arch_direct.h"
 #include "module_manager.h"
+#include "io_location_map.h"
 
 /********************************************************************
  * Function declaration
@@ -23,6 +24,7 @@
 namespace openfpga {
 
 void build_top_module(ModuleManager& module_manager,
+                      IoLocationMap& io_location_map,
                       const CircuitLibrary& circuit_lib,
                       const DeviceGrid& grids,
                       const RRGraph& rr_graph,

From e9adb4fdbc243d89a1fb85cbcf1768a5ce4ef2f7 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 26 Feb 2020 20:38:01 -0700
Subject: [PATCH 215/645] add preconfig top module Verilog generation

---
 openfpga/src/fpga_verilog/verilog_constants.h |   6 +
 .../verilog_preconfig_top_module.cpp          | 442 ++++++++++++++++++
 .../verilog_preconfig_top_module.h            |  34 ++
 .../src/utils/openfpga_atom_netlist_utils.cpp |  34 ++
 .../src/utils/openfpga_atom_netlist_utils.h   |  22 +
 5 files changed, 538 insertions(+)
 create mode 100644 openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
 create mode 100644 openfpga/src/fpga_verilog/verilog_preconfig_top_module.h
 create mode 100644 openfpga/src/utils/openfpga_atom_netlist_utils.cpp
 create mode 100644 openfpga/src/utils/openfpga_atom_netlist_utils.h

diff --git a/openfpga/src/fpga_verilog/verilog_constants.h b/openfpga/src/fpga_verilog/verilog_constants.h
index e355b7a5f..c8a01d375 100644
--- a/openfpga/src/fpga_verilog/verilog_constants.h
+++ b/openfpga/src/fpga_verilog/verilog_constants.h
@@ -48,4 +48,10 @@ constexpr char* SB_VERILOG_FILE_NAME_PREFIX = "sb_";
 constexpr char* LOGICAL_MODULE_VERILOG_FILE_NAME_PREFIX = "logical_tile_";
 constexpr char* GRID_VERILOG_FILE_NAME_PREFIX = "grid_";
 
+constexpr char* FORMAL_VERIFICATION_TOP_MODULE_POSTFIX = "_top_formal_verification";
+constexpr char* FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX = "_fm";
+constexpr char* FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME = "U0_formal_verification";
+
+#define VERILOG_DEFAULT_SIGNAL_INIT_VALUE 0
+
 #endif
diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
new file mode 100644
index 000000000..e2bceb75d
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
@@ -0,0 +1,442 @@
+/********************************************************************
+ * This file includes functions that are used to generate 
+ * a Verilog module of a pre-configured FPGA fabric 
+ *******************************************************************/
+#include <fstream>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+#include "vtr_time.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_port.h"
+#include "openfpga_digest.h"
+
+#include "bitstream_manager_utils.h"
+#include "openfpga_atom_netlist_utils.h"
+
+#include "openfpga_naming.h"
+
+#include "verilog_constants.h"
+#include "verilog_writer_utils.h"
+#include "verilog_testbench_utils.h"
+#include "verilog_preconfig_top_module.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Print module declaration and ports for the pre-configured
+ * FPGA top module
+ * The module ports do exactly match the input benchmark 
+ *******************************************************************/
+static 
+void print_verilog_preconfig_top_module_ports(std::fstream& fp, 
+                                              const std::string& circuit_name,
+                                              const AtomContext& atom_ctx) {
+
+  /* Validate the file stream */
+  valid_file_stream(fp);
+
+  /* Module declaration */ 
+  fp << "module " << circuit_name << std::string(FORMAL_VERIFICATION_TOP_MODULE_POSTFIX);
+  fp << " (" << std::endl;
+ 
+  /* Add module ports */
+  size_t port_counter = 0;
+
+  /* Port type-to-type mapping */
+  std::map<AtomBlockType, enum e_dump_verilog_port_type> port_type2type_map;
+  port_type2type_map[AtomBlockType::INPAD] = VERILOG_PORT_INPUT;
+  port_type2type_map[AtomBlockType::OUTPAD] = VERILOG_PORT_OUTPUT;
+  
+  /* Print all the I/Os of the circuit implementation to be tested*/
+  for (const AtomBlockId& atom_blk : atom_ctx.nlist.blocks()) {
+    /* We only care I/O logical blocks !*/
+    if ( (AtomBlockType::INPAD != atom_ctx.nlist.block_type(atom_blk))
+      && (AtomBlockType::OUTPAD != atom_ctx.nlist.block_type(atom_blk)) ) {
+      continue;
+    }
+    if (0 < port_counter) { 
+      fp << "," << std::endl;
+    }
+    /* Both input and output ports have only size of 1 */
+    BasicPort module_port(std::string(atom_ctx.nlist.block_name(atom_blk) + std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX)), 1); 
+    fp << generate_verilog_port(port_type2type_map[atom_ctx.nlist.block_type(atom_blk)], module_port);  
+
+    /* Update port counter */
+    port_counter++;
+  }
+
+  fp << ");" << std::endl;
+
+  /* Add an empty line as a splitter */
+  fp << std::endl;
+}
+
+/********************************************************************
+ * Print internal wires for the pre-configured FPGA top module
+ * The internal wires are tailored for the ports of FPGA top module
+ * which will be different in various configuration protocols
+ *******************************************************************/
+static 
+void print_verilog_preconfig_top_module_internal_wires(std::fstream& fp,
+                                                       const ModuleManager& module_manager,
+                                                       const ModuleId& top_module) {
+  /* Validate the file stream */
+  valid_file_stream(fp);
+
+  /* Global ports of top-level module  */
+  print_verilog_comment(fp, std::string("----- Local wires for FPGA fabric -----"));
+  for (const ModulePortId& module_port_id : module_manager.module_ports(top_module)) {
+    BasicPort module_port = module_manager.module_port(top_module, module_port_id);
+    fp << generate_verilog_port(VERILOG_PORT_WIRE, module_port) << ";" << std::endl;
+  }
+  /* Add an empty line as a splitter */
+  fp << std::endl;
+}
+
+/********************************************************************
+ * Connect global ports of FPGA top module to constants except:
+ * 1. operating clock, which should be wired to the clock port of 
+ * this pre-configured FPGA top module
+ *******************************************************************/
+static 
+void print_verilog_preconfig_top_module_connect_global_ports(std::fstream& fp,
+                                                             const ModuleManager& module_manager,
+                                                             const ModuleId& top_module,
+                                                             const CircuitLibrary& circuit_lib,
+                                                             const std::vector<CircuitPortId>& global_ports,
+                                                             const std::vector<std::string>& benchmark_clock_port_names) {
+  /* Validate the file stream */
+  valid_file_stream(fp);
+
+  print_verilog_comment(fp, std::string("----- Begin Connect Global ports of FPGA top module -----"));
+
+  /* Global ports of the top module in module manager do not carry any attributes, 
+   * such as is_clock, is_set, etc. 
+   * Therefore, for each global port in the top module, we find the circuit port in the circuit library
+   * which share the same name. We can access to the attributes.
+   * To gurantee the correct link between global ports in module manager and those in circuit library
+   * We have performed some critical check in check_circuit_library() for global ports,
+   * where we guarantee all the global ports share the same name must have the same attributes.
+   * So that each global port with the same name is unique!
+   */
+  for (const BasicPort& module_global_port : module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GLOBAL_PORT)) {
+    CircuitPortId linked_circuit_port_id = CircuitPortId::INVALID();
+    /* Find the circuit port with the same name */
+    for (const CircuitPortId& circuit_port_id : global_ports) {
+      if (0 != module_global_port.get_name().compare(circuit_lib.port_prefix(circuit_port_id))) {
+        continue;
+      }
+      linked_circuit_port_id = circuit_port_id;
+      break;
+    }
+    /* Must find one valid circuit port */
+    VTR_ASSERT(CircuitPortId::INVALID() != linked_circuit_port_id);
+    /* Port size should match! */
+    VTR_ASSERT(module_global_port.get_width() == circuit_lib.port_size(linked_circuit_port_id));
+    /* Now, for operating clock port, we should wire it to the clock of benchmark! */
+    if  ( (CIRCUIT_MODEL_PORT_CLOCK == circuit_lib.port_type(linked_circuit_port_id)) 
+       && (false == circuit_lib.port_is_prog(linked_circuit_port_id)) ) {
+      /* Wiring to each pin of the global port: benchmark clock is always 1-bit */
+      for (const size_t& pin : module_global_port.pins()) {  
+        for (const std::string& clock_port_name : benchmark_clock_port_names) {  
+          BasicPort module_clock_pin(module_global_port.get_name(), pin, pin);
+          BasicPort benchmark_clock_pin(clock_port_name + std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX), 1);
+          print_verilog_wire_connection(fp, module_clock_pin, benchmark_clock_pin, false);
+        }
+      } 
+      /* Finish, go to the next */
+      continue;
+    } 
+
+    /* For other ports, give an default value */
+    std::vector<size_t> default_values(module_global_port.get_width(), circuit_lib.port_default_value(linked_circuit_port_id)); 
+    print_verilog_wire_constant_values(fp, module_global_port, default_values);
+  }
+
+  print_verilog_comment(fp, std::string("----- End Connect Global ports of FPGA top module -----"));
+
+  /* Add an empty line as a splitter */
+  fp << std::endl;
+}
+
+/********************************************************************
+ * Impose the bitstream on the configuration memories
+ * This function uses 'assign' syntax to impost the bitstream at mem port
+ * while uses 'force' syntax to impost the bitstream at mem_inv port
+ *******************************************************************/
+static 
+void print_verilog_preconfig_top_module_assign_bitstream(std::fstream& fp,
+                                                         const ModuleManager& module_manager,
+                                                         const ModuleId& top_module,
+                                                         const BitstreamManager& bitstream_manager) {
+  /* Validate the file stream */
+  valid_file_stream(fp);
+
+  print_verilog_comment(fp, std::string("----- Begin assign bitstream to configuration memories -----"));
+
+  for (const ConfigBlockId& config_block_id : bitstream_manager.blocks()) {
+    /* We only cares blocks with configuration bits */
+    if (0 == bitstream_manager.block_bits(config_block_id).size()) {
+      continue;
+    }
+    /* Build the hierarchical path of the configuration bit in modules */   
+    std::vector<ConfigBlockId> block_hierarchy = find_bitstream_manager_block_hierarchy(bitstream_manager, config_block_id);
+    /* Drop the first block, which is the top module, it should be replaced by the instance name here */
+    /* Ensure that this is the module we want to drop! */
+    VTR_ASSERT(0 == module_manager.module_name(top_module).compare(bitstream_manager.block_name(block_hierarchy[0])));
+    block_hierarchy.erase(block_hierarchy.begin());
+    /* Build the full hierarchy path */
+    std::string bit_hierarchy_path(FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME);
+    for (const ConfigBlockId& temp_block : block_hierarchy) {
+      bit_hierarchy_path += std::string(".");
+      bit_hierarchy_path += bitstream_manager.block_name(temp_block);
+    }
+    bit_hierarchy_path += std::string(".");
+
+    /* Find the bit index in the parent block */
+    BasicPort config_data_port(bit_hierarchy_path + generate_configuration_chain_data_out_name(),
+                               bitstream_manager.block_bits(config_block_id).size());
+
+    /* Wire it to the configuration bit: access both data out and data outb ports */
+    std::vector<size_t> config_data_values;
+    for (const ConfigBitId config_bit : bitstream_manager.block_bits(config_block_id)) {
+      config_data_values.push_back(bitstream_manager.bit_value(config_bit));
+    }
+    print_verilog_wire_constant_values(fp, config_data_port, config_data_values);
+  }
+
+  fp << "initial begin" << std::endl;
+
+  for (const ConfigBlockId& config_block_id : bitstream_manager.blocks()) {
+    /* We only cares blocks with configuration bits */
+    if (0 == bitstream_manager.block_bits(config_block_id).size()) {
+      continue;
+    }
+    /* Build the hierarchical path of the configuration bit in modules */   
+    std::vector<ConfigBlockId> block_hierarchy = find_bitstream_manager_block_hierarchy(bitstream_manager, config_block_id);
+    /* Drop the first block, which is the top module, it should be replaced by the instance name here */
+    /* Ensure that this is the module we want to drop! */
+    VTR_ASSERT(0 == module_manager.module_name(top_module).compare(bitstream_manager.block_name(block_hierarchy[0])));
+    block_hierarchy.erase(block_hierarchy.begin());
+    /* Build the full hierarchy path */
+    std::string bit_hierarchy_path(FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME);
+    for (const ConfigBlockId& temp_block : block_hierarchy) {
+      bit_hierarchy_path += std::string(".");
+      bit_hierarchy_path += bitstream_manager.block_name(temp_block);
+    }
+    bit_hierarchy_path += std::string(".");
+
+    /* Find the bit index in the parent block */
+    BasicPort config_datab_port(bit_hierarchy_path + generate_configuration_chain_inverted_data_out_name(),
+                                bitstream_manager.block_bits(config_block_id).size());
+
+    std::vector<size_t> config_datab_values;
+    for (const ConfigBitId config_bit : bitstream_manager.block_bits(config_block_id)) {
+      config_datab_values.push_back(!bitstream_manager.bit_value(config_bit));
+    }
+    print_verilog_force_wire_constant_values(fp, config_datab_port, config_datab_values);
+  }
+
+  fp << "end" << std::endl;
+
+  print_verilog_comment(fp, std::string("----- End assign bitstream to configuration memories -----"));
+}
+
+/********************************************************************
+ * Impose the bitstream on the configuration memories
+ * This function uses '$deposit' syntax to do so
+ *******************************************************************/
+static 
+void print_verilog_preconfig_top_module_deposit_bitstream(std::fstream& fp,
+                                                          const ModuleManager& module_manager,
+                                                          const ModuleId& top_module,
+                                                          const BitstreamManager& bitstream_manager) {
+  /* Validate the file stream */
+  valid_file_stream(fp);
+
+  print_verilog_comment(fp, std::string("----- Begin deposit bitstream to configuration memories -----"));
+  
+  fp << "initial begin" << std::endl;
+
+  for (const ConfigBlockId& config_block_id : bitstream_manager.blocks()) {
+    /* We only cares blocks with configuration bits */
+    if (0 == bitstream_manager.block_bits(config_block_id).size()) {
+      continue;
+    }
+    /* Build the hierarchical path of the configuration bit in modules */   
+    std::vector<ConfigBlockId> block_hierarchy = find_bitstream_manager_block_hierarchy(bitstream_manager, config_block_id);
+    /* Drop the first block, which is the top module, it should be replaced by the instance name here */
+    /* Ensure that this is the module we want to drop! */
+    VTR_ASSERT(0 == module_manager.module_name(top_module).compare(bitstream_manager.block_name(block_hierarchy[0])));
+    block_hierarchy.erase(block_hierarchy.begin());
+    /* Build the full hierarchy path */
+    std::string bit_hierarchy_path(FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME);
+    for (const ConfigBlockId& temp_block : block_hierarchy) {
+      bit_hierarchy_path += std::string(".");
+      bit_hierarchy_path += bitstream_manager.block_name(temp_block);
+    }
+    bit_hierarchy_path += std::string(".");
+
+    /* Find the bit index in the parent block */
+    BasicPort config_data_port(bit_hierarchy_path + generate_configuration_chain_data_out_name(),
+                               bitstream_manager.block_bits(config_block_id).size());
+
+    BasicPort config_datab_port(bit_hierarchy_path + generate_configuration_chain_inverted_data_out_name(),
+                               bitstream_manager.block_bits(config_block_id).size());
+
+    /* Wire it to the configuration bit: access both data out and data outb ports */
+    std::vector<size_t> config_data_values;
+    for (const ConfigBitId config_bit : bitstream_manager.block_bits(config_block_id)) {
+      config_data_values.push_back(bitstream_manager.bit_value(config_bit));
+    }
+    print_verilog_deposit_wire_constant_values(fp, config_data_port, config_data_values);
+
+    std::vector<size_t> config_datab_values;
+    for (const ConfigBitId config_bit : bitstream_manager.block_bits(config_block_id)) {
+      config_datab_values.push_back(!bitstream_manager.bit_value(config_bit));
+    }
+    print_verilog_deposit_wire_constant_values(fp, config_datab_port, config_datab_values);
+  }
+
+  fp << "end" << std::endl;
+
+  print_verilog_comment(fp, std::string("----- End deposit bitstream to configuration memories -----"));
+}
+
+/********************************************************************
+ * Impose the bitstream on the configuration memories
+ * We branch here for different simulators:
+ * 1. iVerilog Icarus prefers using 'assign' syntax to force the values
+ * 2. Mentor Modelsim prefers using '$deposit' syntax to do so
+ *******************************************************************/
+static 
+void print_verilog_preconfig_top_module_load_bitstream(std::fstream& fp,
+                                                       const ModuleManager& module_manager,
+                                                       const ModuleId& top_module,
+                                                       const BitstreamManager& bitstream_manager) {
+  print_verilog_comment(fp, std::string("----- Begin load bitstream to configuration memories -----"));
+  
+  print_verilog_preprocessing_flag(fp, std::string(ICARUS_SIMULATOR_FLAG)); 
+
+  /* Use assign syntax for Icarus simulator */
+  print_verilog_preconfig_top_module_assign_bitstream(fp, module_manager, top_module, bitstream_manager);
+
+  fp << "`else" << std::endl;
+
+  /* Use assign syntax for Icarus simulator */
+  print_verilog_preconfig_top_module_deposit_bitstream(fp, module_manager, top_module, bitstream_manager);
+
+  print_verilog_endif(fp);
+
+  print_verilog_comment(fp, std::string("----- End load bitstream to configuration memories -----"));
+}
+
+
+/********************************************************************
+ * Top-level function to generate a Verilog module of 
+ * a pre-configured FPGA fabric.
+ *
+ *   Pre-configured FPGA fabric
+ *                        +--------------------------------------------
+ *                        |
+ *                        |          FPGA fabric
+ *                        |          +-------------------------------+
+ *                        |          |                               |
+ *                        |  0/1---->|FPGA global ports              |
+ *                        |          |                               |
+ *   benchmark_clock----->|--------->|FPGA_clock                     |
+ *                        |          |                               |
+ *   benchmark_inputs---->|--------->|FPGA mapped I/Os               |
+ *                        |          |                               |
+ *   benchmark_outputs<---|<---------|FPGA mapped I/Os               |
+ *                        |          |                               |
+ *                        |  0/1---->|FPGA unmapped I/Os             |
+ *                        |          |                               |
+ *   fabric_bitstream---->|--------->|Internal_configuration_ports   |
+ *                        |          +-------------------------------+
+ *                        |
+ *                        +-------------------------------------------
+ *
+ * Note: we do NOT put this module in the module manager.
+ * Because, it is not a standard module, where we force configuration signals 
+ * This module is a wrapper for the FPGA fabric to be compatible in 
+ * the port map of input benchmark.
+ * It includes wires to force constant values to part of FPGA datapath I/Os
+ * All these are hard to implement as a module in module manager
+ *******************************************************************/
+void print_verilog_preconfig_top_module(const ModuleManager& module_manager,
+                                        const BitstreamManager& bitstream_manager,
+                                        const CircuitLibrary& circuit_lib,
+                                        const std::vector<CircuitPortId>& global_ports,
+                                        const AtomContext& atom_ctx,
+                                        const PlacementContext& place_ctx,
+                                        const IoLocationMap& io_location_map,
+                                        const std::string& circuit_name,
+                                        const std::string& verilog_fname,
+                                        const std::string& verilog_dir) {
+  std::string timer_message = std::string("Write pre-configured FPGA top-level Verilog netlist for design '") + circuit_name + std::string("'");
+
+  /* Start time count */
+  vtr::ScopedStartFinishTimer timer(timer_message);
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
+
+  /* Validate the file stream */
+  check_file_stream(verilog_fname.c_str(), fp);
+
+  /* Generate a brief description on the Verilog file*/
+  std::string title = std::string("Verilog netlist for pre-configured FPGA fabric by design: ") + circuit_name;
+  print_verilog_file_header(fp, title); 
+
+  /* Print preprocessing flags and external netlists */
+  print_verilog_include_defines_preproc_file(fp, verilog_dir);
+
+  print_verilog_include_netlist(fp, std::string(verilog_dir + std::string(DEFINES_VERILOG_SIMULATION_FILE_NAME)));  
+
+  /* Print module declaration and ports */
+  print_verilog_preconfig_top_module_ports(fp, circuit_name, atom_ctx);
+
+  /* Find the top_module */
+  ModuleId top_module = module_manager.find_module(generate_fpga_top_module_name());
+  VTR_ASSERT(true == module_manager.valid_module_id(top_module));
+
+  /* Print internal wires */
+  print_verilog_preconfig_top_module_internal_wires(fp, module_manager, top_module);
+
+  /* Instanciate FPGA top-level module */
+  print_verilog_testbench_fpga_instance(fp, module_manager, top_module, 
+                                        std::string(FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME)); 
+
+  /* Find clock ports in benchmark */
+  std::vector<std::string> benchmark_clock_port_names = find_atom_netlist_clock_port_names(atom_ctx.nlist);
+
+  /* Connect FPGA top module global ports to constant or benchmark global signals! */
+  print_verilog_preconfig_top_module_connect_global_ports(fp, module_manager, top_module,
+                                                          circuit_lib, global_ports,
+                                                          benchmark_clock_port_names);
+
+  /* Connect I/Os to benchmark I/Os or constant driver */
+  print_verilog_testbench_connect_fpga_ios(fp, module_manager, top_module,
+                                           atom_ctx, place_ctx, io_location_map, 
+                                           std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX), 
+                                           std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX), 
+                                           (size_t)VERILOG_DEFAULT_SIGNAL_INIT_VALUE);
+
+  /* Assign FPGA internal SRAM/Memory ports to bitstream values */
+  print_verilog_preconfig_top_module_load_bitstream(fp, module_manager, top_module,
+                                                    bitstream_manager);
+
+  /* Testbench ends*/
+  print_verilog_module_end(fp, std::string(circuit_name) + std::string(FORMAL_VERIFICATION_TOP_MODULE_POSTFIX));
+
+  /* Close the file stream */
+  fp.close();
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.h b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.h
new file mode 100644
index 000000000..0c8e54708
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.h
@@ -0,0 +1,34 @@
+#ifndef VERILOG_PRECONFIG_TOP_MODULE_H
+#define VERILOG_PRECONFIG_TOP_MODULE_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <vector>
+#include <string>
+#include "circuit_types.h" 
+#include "vpr_types.h" 
+#include "module_manager.h" 
+#include "bitstream_manager.h" 
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void print_verilog_preconfig_top_module(const ModuleManager& module_manager,
+                                        const BitstreamManager& bitstream_manager,
+                                        const CircuitLibrary& circuit_lib,
+                                        const std::vector<CircuitPortId>& global_ports,
+                                        const AtomContext& atom_ctx,
+                                        const PlacementContext& place_ctx,
+                                        const IoLocationMap& io_location_map,
+                                        const std::string& circuit_name,
+                                        const std::string& verilog_fname,
+                                        const std::string& verilog_dir);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/utils/openfpga_atom_netlist_utils.cpp b/openfpga/src/utils/openfpga_atom_netlist_utils.cpp
new file mode 100644
index 000000000..d2786e88d
--- /dev/null
+++ b/openfpga/src/utils/openfpga_atom_netlist_utils.cpp
@@ -0,0 +1,34 @@
+/***************************************************************************************
+ * This file includes most utilized functions that are used to acquire data from 
+ * VPR atom netlist (users' netlist to implement)
+ ***************************************************************************************/
+
+/* Headers from vtrutil library */
+#include "vtr_log.h"
+#include "vtr_assert.h"
+#include "vtr_time.h"
+
+/* Headers from vtrutil library */
+#include "atom_netlist_utils.h"
+
+#include "openfpga_atom_netlist_utils.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/***************************************************************************************
+ * Find the names of all the atom blocks that drive clock nets 
+ ***************************************************************************************/
+std::vector<std::string> find_atom_netlist_clock_port_names(const AtomNetlist& atom_nlist) {
+  std::vector<std::string> clock_names;
+
+  std::set<AtomPinId> clock_pins = find_netlist_logical_clock_drivers(atom_nlist);
+  for (const AtomPinId& clock_pin : clock_pins) {
+    const AtomBlockId& atom_blk = atom_nlist.port_block(atom_nlist.pin_port(clock_pin));
+    clock_names.push_back(atom_nlist.block_name(atom_blk));
+  }
+
+  return clock_names;
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/utils/openfpga_atom_netlist_utils.h b/openfpga/src/utils/openfpga_atom_netlist_utils.h
new file mode 100644
index 000000000..180181687
--- /dev/null
+++ b/openfpga/src/utils/openfpga_atom_netlist_utils.h
@@ -0,0 +1,22 @@
+#ifndef OPENFPGA_ATOM_NETLIST_UTILS_H
+#define OPENFPGA_ATOM_NETLIST_UTILS_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <vector>
+#include <string>
+#include "atom_netlist.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+std::vector<std::string> find_atom_netlist_clock_port_names(const AtomNetlist& atom_nlist);
+
+} /* end namespace openfpga */
+
+#endif

From bb671acac3bf1d8aaad193a2aa9c50a1e1845d24 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 26 Feb 2020 20:58:16 -0700
Subject: [PATCH 216/645] add formal random Verilog testbench generation

---
 .../verilog_formal_random_top_testbench.cpp   | 259 ++++++++++++++++++
 .../verilog_formal_random_top_testbench.h     |  26 ++
 openfpga/src/utils/simulation_utils.cpp       |  47 ++++
 openfpga/src/utils/simulation_utils.h         |  28 ++
 4 files changed, 360 insertions(+)
 create mode 100644 openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
 create mode 100644 openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.h
 create mode 100644 openfpga/src/utils/simulation_utils.cpp
 create mode 100644 openfpga/src/utils/simulation_utils.h

diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
new file mode 100644
index 000000000..71f7df873
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
@@ -0,0 +1,259 @@
+/********************************************************************
+ * This file includes functions that are used to generate a Verilog 
+ * testbench for the top-level module (FPGA fabric), in purpose of
+ * running formal verification with random input vectors 
+ *******************************************************************/
+#include <fstream>
+#include <cstring>
+#include <cmath>
+#include <iomanip>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+#include "vtr_time.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_port.h"
+#include "openfpga_digest.h"
+
+#include "openfpga_atom_netlist_utils.h"
+#include "simulation_utils.h"
+
+#include "verilog_constants.h"
+#include "verilog_writer_utils.h"
+#include "verilog_testbench_utils.h"
+#include "verilog_formal_random_top_testbench.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Local variables used only in this file
+ *******************************************************************/
+constexpr char* FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX = "_top_formal_verification_random_tb";
+constexpr char* FPGA_PORT_POSTFIX = "_gfpga";
+constexpr char* BENCHMARK_PORT_POSTFIX = "_bench";
+constexpr char* CHECKFLAG_PORT_POSTFIX = "_flag";
+constexpr char* DEFAULT_CLOCK_NAME = "clk";
+constexpr char* BENCHMARK_INSTANCE_NAME = "REF_DUT";
+constexpr char* FPGA_INSTANCE_NAME = "FPGA_DUT";
+constexpr char* ERROR_COUNTER = "nb_error";
+constexpr char* FORMAL_TB_SIM_START_PORT_NAME = "sim_start";
+constexpr int MAGIC_NUMBER_FOR_SIMULATION_TIME = 200;
+
+/********************************************************************
+ * Print the module ports for the Verilog testbench 
+ * using random vectors 
+ * This function generates 
+ * 1. the input ports to drive both input benchmark module and FPGA fabric module
+ * 2. the output ports for input benchmark module
+ * 3. the output ports for FPGA fabric module
+ * 4. the error checking ports 
+ *******************************************************************/
+static 
+void print_verilog_top_random_testbench_ports(std::fstream& fp,
+                                              const std::string& circuit_name,
+                                              const std::vector<std::string>& clock_port_names,
+                                              const AtomContext& atom_ctx) {
+  /* Validate the file stream */
+  valid_file_stream(fp);
+ 
+  /* Print the declaration for the module */
+  fp << "module " << circuit_name << FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX << ";" << std::endl;
+
+  /* Create a clock port if the benchmark does not have one! 
+   * The clock is used for counting and synchronizing input stimulus 
+   */
+  BasicPort clock_port = generate_verilog_testbench_clock_port(clock_port_names, std::string(DEFAULT_CLOCK_NAME));
+  print_verilog_comment(fp, std::string("----- Default clock port is added here since benchmark does not contain one -------"));
+  fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, clock_port) << ";" << std::endl;
+
+  /* Add an empty line as splitter */
+  fp << std::endl;
+
+  print_verilog_testbench_shared_ports(fp, atom_ctx,
+                                       std::string(BENCHMARK_PORT_POSTFIX),
+                                       std::string(FPGA_PORT_POSTFIX),
+                                       std::string(CHECKFLAG_PORT_POSTFIX),
+                                       std::string(AUTOCHECKED_SIMULATION_FLAG));
+
+  /* Instantiate an integer to count the number of error 
+   * and determine if the simulation succeed or failed 
+   */
+  print_verilog_comment(fp, std::string("----- Error counter -------"));
+  fp << "\tinteger " << ERROR_COUNTER << "= 0;" << std::endl;
+
+  /* Add an empty line as splitter */
+  fp << std::endl;
+}
+
+/********************************************************************
+ * Instanciate the input benchmark module
+ *******************************************************************/
+static
+void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp, 
+                                                           const std::string& reference_verilog_top_name,
+                                                           const AtomContext& atom_ctx) {
+  /* Validate the file stream */
+  valid_file_stream(fp);
+
+  /* Benchmark is instanciated conditionally: only when a preprocessing flag is enable */
+  print_verilog_preprocessing_flag(fp, std::string(AUTOCHECKED_SIMULATION_FLAG)); 
+
+  print_verilog_comment(fp, std::string("----- Reference Benchmark Instanication -------"));
+
+  /* Do NOT use explicit port mapping here: 
+   * VPR added a prefix of "out_" to the output ports of input benchmark
+   */
+  print_verilog_testbench_benchmark_instance(fp, reference_verilog_top_name,
+                                             std::string(BENCHMARK_INSTANCE_NAME),
+                                             std::string(),
+                                             std::string(),
+                                             std::string(BENCHMARK_PORT_POSTFIX),
+                                             atom_ctx,
+                                             false);
+
+  print_verilog_comment(fp, std::string("----- End reference Benchmark Instanication -------"));
+
+  /* Add an empty line as splitter */
+  fp << std::endl;
+
+  /* Condition ends for the benchmark instanciation */
+  print_verilog_endif(fp);
+
+  /* Add an empty line as splitter */
+  fp << std::endl;
+}
+
+/********************************************************************
+ * Instanciate the FPGA fabric module
+ *******************************************************************/
+static
+void print_verilog_random_testbench_fpga_instance(std::fstream& fp,
+                                                  const std::string& circuit_name,
+                                                  const AtomContext& atom_ctx) {
+  /* Validate the file stream */
+  valid_file_stream(fp);
+
+  print_verilog_comment(fp, std::string("----- FPGA fabric instanciation -------"));
+
+  /* Always use explicit port mapping */
+  print_verilog_testbench_benchmark_instance(fp, std::string(circuit_name + std::string(FORMAL_VERIFICATION_TOP_MODULE_POSTFIX)),
+                                             std::string(FPGA_INSTANCE_NAME),
+                                             std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX),
+                                             std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX),
+                                             std::string(FPGA_PORT_POSTFIX),
+                                             atom_ctx,
+                                             true);
+
+  print_verilog_comment(fp, std::string("----- End FPGA Fabric Instanication -------"));
+
+  /* Add an empty line as splitter */
+  fp << std::endl;
+}
+
+/*********************************************************************
+ * Top-level function in this file:
+ * Create a Verilog testbench using random input vectors 
+ * The testbench consists of two modules, i.e., Design Under Test (DUT)
+ * 1. top-level module of FPGA fabric
+ * 2. top-level module of users' benchmark, 
+ *    i.e., the input benchmark of VPR flow
+ *                                    +----------+
+ *                                    |   FPGA   |       +------------+
+ *                             +----->|  Fabric  |------>|            |
+ *                             |      |          |       |            |
+ *                             |      +----------+       |            |
+ *                             |                         | Output     | 
+ *   random_input_vectors -----+                         | Vector     |---->Functional correct?
+ *                             |                         | Comparator |    
+ *                             |      +-----------+      |            |
+ *                             |      |  Input    |      |            |
+ *                             +----->| Benchmark |----->|            |
+ *                                    +-----------+      +------------+
+ *
+ * Same input vectors are given to drive both DUTs.
+ * The output vectors of the DUTs are compared to verify if they
+ * have the same functionality.
+ * A flag will be raised to indicate the result 
+ ********************************************************************/
+void print_verilog_random_top_testbench(const std::string& circuit_name,
+                                        const std::string& verilog_fname,
+                                        const std::string& verilog_dir,
+                                        const AtomContext& atom_ctx,
+                                        const SimulationSetting& simulation_parameters) {
+  std::string timer_message = std::string("Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by '") + circuit_name.c_str() + std::string("'");
+
+  /* Start time count */
+  vtr::ScopedStartFinishTimer timer(timer_message);
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
+
+  /* Validate the file stream */
+  check_file_stream(verilog_fname.c_str(), fp);
+
+  /* Generate a brief description on the Verilog file*/
+  std::string title = std::string("FPGA Verilog Testbench for Formal Top-level netlist of Design: ") + circuit_name;
+  print_verilog_file_header(fp, title); 
+
+  /* Print preprocessing flags and external netlists */
+  print_verilog_include_defines_preproc_file(fp, verilog_dir);
+
+  print_verilog_include_netlist(fp, std::string(verilog_dir + std::string(DEFINES_VERILOG_SIMULATION_FILE_NAME)));  
+
+  /* Preparation: find all the clock ports */
+  std::vector<std::string> clock_port_names = find_atom_netlist_clock_port_names(atom_ctx.nlist);
+
+  /* Start of testbench */
+  print_verilog_top_random_testbench_ports(fp, circuit_name, clock_port_names, atom_ctx);
+
+  /* Call defined top-level module */
+  print_verilog_random_testbench_fpga_instance(fp, circuit_name, atom_ctx);
+
+  /* Call defined benchmark */
+  print_verilog_top_random_testbench_benchmark_instance(fp, circuit_name, atom_ctx);
+
+  /* Find clock port to be used */
+  BasicPort clock_port = generate_verilog_testbench_clock_port(clock_port_names, std::string(DEFAULT_CLOCK_NAME));
+
+  /* Add stimuli for reset, set, clock and iopad signals */
+  print_verilog_testbench_clock_stimuli(fp, simulation_parameters, 
+                                        clock_port);
+  print_verilog_testbench_random_stimuli(fp, atom_ctx, 
+                                         std::string(CHECKFLAG_PORT_POSTFIX), clock_port);
+
+  print_verilog_testbench_check(fp, 
+                                std::string(AUTOCHECKED_SIMULATION_FLAG),
+                                std::string(FORMAL_TB_SIM_START_PORT_NAME),
+                                std::string(BENCHMARK_PORT_POSTFIX),
+                                std::string(FPGA_PORT_POSTFIX),
+                                std::string(CHECKFLAG_PORT_POSTFIX),
+                                std::string(ERROR_COUNTER),
+                                atom_ctx,
+                                clock_port_names, std::string(DEFAULT_CLOCK_NAME));
+
+  int simulation_time = find_operating_phase_simulation_time(MAGIC_NUMBER_FOR_SIMULATION_TIME,
+                                                             simulation_parameters.num_clock_cycles(),
+                                                             1./simulation_parameters.operating_clock_frequency(),
+                                                             VERILOG_SIM_TIMESCALE);
+
+  /* Add Icarus requirement */
+  print_verilog_timeout_and_vcd(fp, 
+                                std::string(ICARUS_SIMULATOR_FLAG),
+                                std::string(circuit_name + std::string(FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX)),
+                                std::string(circuit_name + std::string("_formal.vcd")), 
+                                std::string(FORMAL_TB_SIM_START_PORT_NAME),
+                                std::string(ERROR_COUNTER),
+                                simulation_time);
+
+  /* Testbench ends*/
+  print_verilog_module_end(fp, std::string(circuit_name) + std::string(FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX));
+
+  /* Close the file stream */
+  fp.close();
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.h b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.h
new file mode 100644
index 000000000..f73b49fc1
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.h
@@ -0,0 +1,26 @@
+#ifndef VERILOG_FORMAL_RANDOM_TOP_TESTBENCH
+#define VERILOG_FORMAL_RANDOM_TOP_TESTBENCH
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <string>
+#include "vpr_context.h"
+#include "simulation_setting.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void print_verilog_random_top_testbench(const std::string& circuit_name,
+                                        const std::string& verilog_fname,
+                                        const std::string& verilog_dir,
+                                        const AtomContext& atom_ctx,
+                                        const SimulationSetting& simulation_parameters);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/utils/simulation_utils.cpp b/openfpga/src/utils/simulation_utils.cpp
new file mode 100644
index 000000000..e7d8d33bf
--- /dev/null
+++ b/openfpga/src/utils/simulation_utils.cpp
@@ -0,0 +1,47 @@
+/********************************************************************
+ * This file include most utilized functions in generating simulations
+ * Note: function placed here MUST be generic enough for both SPICE
+ * and Verilog simulations!
+ *******************************************************************/
+#include <cmath>
+
+#include "simulation_utils.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+
+/********************************************************************
+ * Compute the time period for the simulation
+ *******************************************************************/
+int find_operating_phase_simulation_time(const int& factor,
+                                         const int& num_op_clock_cycles,
+                                         const float& op_clock_period,
+                                         const float& timescale) {
+  /* Take into account the prog_reset and reset cycles 
+   * 1e9 is to change the unit to ns rather than second 
+   */
+  return (factor * num_op_clock_cycles * op_clock_period) / timescale; 
+}
+
+/********************************************************************
+ * Find the the full time period of a simulation, including
+ * both the programming time and operating time
+ * This is a generic function that can be used to generate simulation
+ * time period for SPICE/Verilog simulators
+ *******************************************************************/
+float find_simulation_time_period(const float &time_unit,
+                                  const int &num_prog_clock_cycles,
+                                  const float &prog_clock_period,
+                                  const int &num_op_clock_cycles,
+                                  const float &op_clock_period) {
+  float total_time_period = 0.;
+
+  /* Take into account the prog_reset and reset cycles */
+  total_time_period = (num_prog_clock_cycles + 2) * prog_clock_period + num_op_clock_cycles * op_clock_period;
+  total_time_period = total_time_period / time_unit;
+
+  return total_time_period;
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/utils/simulation_utils.h b/openfpga/src/utils/simulation_utils.h
new file mode 100644
index 000000000..d99a6226f
--- /dev/null
+++ b/openfpga/src/utils/simulation_utils.h
@@ -0,0 +1,28 @@
+#ifndef SIMULATION_UTILS_H
+#define SIMULATION_UTILS_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+int find_operating_phase_simulation_time(const int& factor,
+                                         const int& num_op_clock_cycles,
+                                         const float& op_clock_period,
+                                         const float& timescale);
+
+float find_simulation_time_period(const float& time_unit,
+                                  const int& num_prog_clock_cycles,
+                                  const float& prog_clock_period,
+                                  const int& num_op_clock_cycles,
+                                  const float& op_clock_period);
+
+} /* end namespace openfpga */
+
+#endif

From 77529f49574f4d4b085ed02c9599ed44fcf2a2c9 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 26 Feb 2020 21:30:21 -0700
Subject: [PATCH 217/645] adapt top Verilog testbench generation

---
 .../fpga_verilog/verilog_top_testbench.cpp    | 889 ++++++++++++++++++
 .../src/fpga_verilog/verilog_top_testbench.h  |  39 +
 2 files changed, 928 insertions(+)
 create mode 100644 openfpga/src/fpga_verilog/verilog_top_testbench.cpp
 create mode 100644 openfpga/src/fpga_verilog/verilog_top_testbench.h

diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
new file mode 100644
index 000000000..6159d1751
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
@@ -0,0 +1,889 @@
+/********************************************************************
+ * This file includes functions that are used to create
+ * an auto-check top-level testbench for a FPGA fabric
+ *******************************************************************/
+#include <fstream>
+#include <iomanip>
+#include <algorithm>
+
+
+/* Headers from vtrutil library */
+#include "vtr_log.h"
+#include "vtr_assert.h"
+#include "vtr_time.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_port.h"
+#include "openfpga_digest.h"
+
+#include "bitstream_manager_utils.h"
+
+#include "openfpga_naming.h"
+#include "simulation_utils.h"
+#include "openfpga_atom_netlist_utils.h"
+
+#include "verilog_constants.h"
+#include "verilog_writer_utils.h"
+#include "verilog_testbench_utils.h"
+#include "verilog_top_testbench.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Local variables used only in this file
+ *******************************************************************/
+constexpr char* TOP_TESTBENCH_REFERENCE_INSTANCE_NAME = "REF_DUT";
+constexpr char* TOP_TESTBENCH_FPGA_INSTANCE_NAME = "FPGA_DUT";
+constexpr char* TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX = "_benchmark";
+constexpr char* TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX = "_fpga";
+
+constexpr char* TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX = "_flag";
+
+constexpr char* TOP_TESTBENCH_CC_PROG_TASK_NAME = "prog_cycle_task";
+
+constexpr char* TOP_TESTBENCH_SIM_START_PORT_NAME = "sim_start";
+
+constexpr int TOP_TESTBENCH_MAGIC_NUMBER_FOR_SIMULATION_TIME = 200;
+constexpr char* TOP_TESTBENCH_ERROR_COUNTER = "nb_error";
+
+constexpr char* TOP_TB_RESET_PORT_NAME = "greset";
+constexpr char* TOP_TB_SET_PORT_NAME = "gset";
+constexpr char* TOP_TB_PROG_RESET_PORT_NAME = "prog_reset";
+constexpr char* TOP_TB_PROG_SET_PORT_NAME = "prog_set";
+constexpr char* TOP_TB_CONFIG_DONE_PORT_NAME = "config_done";
+constexpr char* TOP_TB_OP_CLOCK_PORT_NAME = "op_clock";
+constexpr char* TOP_TB_PROG_CLOCK_PORT_NAME = "prog_clock";
+constexpr char* TOP_TB_INOUT_REG_POSTFIX = "_reg";
+constexpr char* TOP_TB_CLOCK_REG_POSTFIX = "_reg";
+
+constexpr char* AUTOCHECK_TOP_TESTBENCH_VERILOG_MODULE_POSTFIX = "_autocheck_top_tb";
+
+/********************************************************************
+ * Print local wires for configuration chain protocols
+ *******************************************************************/
+static 
+void print_verilog_top_testbench_config_chain_port(std::fstream& fp) {
+  /* Validate the file stream */
+  valid_file_stream(fp);
+
+  /* Print the head of configuraion-chains here */
+  print_verilog_comment(fp, std::string("---- Configuration-chain head -----"));
+  BasicPort config_chain_head_port(generate_configuration_chain_head_name(), 1);
+  fp << generate_verilog_port(VERILOG_PORT_REG, config_chain_head_port) << ";" << std::endl;
+
+  /* Print the tail of configuration-chains here */
+  print_verilog_comment(fp, std::string("---- Configuration-chain tail -----"));
+  BasicPort config_chain_tail_port(generate_configuration_chain_tail_name(), 1);
+  fp << generate_verilog_port(VERILOG_PORT_WIRE, config_chain_tail_port) << ";" << std::endl;
+}
+
+/********************************************************************
+ * Print local wires for different types of configuration protocols
+ *******************************************************************/
+static 
+void print_verilog_top_testbench_config_protocol_port(std::fstream& fp,
+                                                      const e_config_protocol_type& sram_orgz_type) {
+  switch(sram_orgz_type) {
+  case CONFIG_MEM_STANDALONE:
+    /* TODO */
+    break;
+  case CONFIG_MEM_SCAN_CHAIN:
+    print_verilog_top_testbench_config_chain_port(fp);
+    break;
+  case CONFIG_MEM_MEMORY_BANK:
+    /* TODO */
+    break;
+  default:
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid type of SRAM organization!\n");
+    exit(1);
+  }
+}
+
+/********************************************************************
+ * Wire the global ports of FPGA fabric to local wires
+ *******************************************************************/
+static 
+void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp,
+                                                      const ModuleManager& module_manager,
+                                                      const ModuleId& top_module,
+                                                      const CircuitLibrary& circuit_lib,
+                                                      const std::vector<CircuitPortId>& global_ports) {
+  /* Validate the file stream */
+  valid_file_stream(fp);
+
+  print_verilog_comment(fp, std::string("----- Begin connecting global ports of FPGA fabric to stimuli -----"));
+
+  /* Connect global clock ports to operating or programming clock signal */
+  for (const CircuitPortId& model_global_port : global_ports) {
+    if (CIRCUIT_MODEL_PORT_CLOCK != circuit_lib.port_type(model_global_port)) {
+      continue;
+    }
+    /* Reach here, it means we have a global clock to deal with:
+     * 1. if the port is identified as a programming clock, 
+     *    connect it to the local wire of programming clock
+     * 2. if the port is identified as an operating clock 
+     *    connect it to the local wire of operating clock
+     */
+    /* Find the module port */
+    ModulePortId module_global_port = module_manager.find_module_port(top_module, circuit_lib.port_prefix(model_global_port));
+    VTR_ASSERT(true == module_manager.valid_module_port_id(top_module, module_global_port));
+
+    BasicPort stimuli_clock_port;
+    if (true == circuit_lib.port_is_prog(model_global_port)) {
+      stimuli_clock_port.set_name(std::string(TOP_TB_PROG_CLOCK_PORT_NAME));
+      stimuli_clock_port.set_width(1);
+    } else {
+      VTR_ASSERT_SAFE(false == circuit_lib.port_is_prog(model_global_port));
+      stimuli_clock_port.set_name(std::string(TOP_TB_OP_CLOCK_PORT_NAME));
+      stimuli_clock_port.set_width(1);
+    }
+    /* Wire the port to the input stimuli:
+     * The wiring will be inverted if the default value of the global port is 1
+     * Otherwise, the wiring will not be inverted!
+     */
+    print_verilog_wire_connection(fp, module_manager.module_port(top_module, module_global_port), 
+                                  stimuli_clock_port, 
+                                  1 == circuit_lib.port_default_value(model_global_port)); 
+  }
+
+  /* Connect global configuration done ports to configuration done signal */
+  for (const CircuitPortId& model_global_port : global_ports) {
+    /* Bypass clock signals, they have been processed */
+    if (CIRCUIT_MODEL_PORT_CLOCK == circuit_lib.port_type(model_global_port)) {
+      continue;
+    }
+    if (false == circuit_lib.port_is_config_enable(model_global_port)) {
+      continue;
+    }
+    /* Reach here, it means we have a configuration done port to deal with */
+    /* Find the module port */
+    ModulePortId module_global_port = module_manager.find_module_port(top_module, circuit_lib.port_prefix(model_global_port));
+    VTR_ASSERT(true == module_manager.valid_module_port_id(top_module, module_global_port));
+
+    BasicPort stimuli_config_done_port(std::string(TOP_TB_CONFIG_DONE_PORT_NAME), 1);
+    /* Wire the port to the input stimuli:
+     * The wiring will be inverted if the default value of the global port is 1
+     * Otherwise, the wiring will not be inverted!
+     */
+    print_verilog_wire_connection(fp, module_manager.module_port(top_module, module_global_port), 
+                                  stimuli_config_done_port, 
+                                  1 == circuit_lib.port_default_value(model_global_port)); 
+  }
+
+  /* Connect global reset ports to operating or programming reset signal */
+  for (const CircuitPortId& model_global_port : global_ports) {
+    /* Bypass clock signals, they have been processed */
+    if (CIRCUIT_MODEL_PORT_CLOCK == circuit_lib.port_type(model_global_port)) {
+      continue;
+    }
+    /* Bypass config_done signals, they have been processed */
+    if (true == circuit_lib.port_is_config_enable(model_global_port)) {
+      continue;
+    }
+
+    if (false == circuit_lib.port_is_reset(model_global_port)) {
+      continue;
+    }
+    /* Reach here, it means we have a reset port to deal with */
+    /* Find the module port */
+    ModulePortId module_global_port = module_manager.find_module_port(top_module, circuit_lib.port_prefix(model_global_port));
+    VTR_ASSERT(true == module_manager.valid_module_port_id(top_module, module_global_port));
+
+    BasicPort stimuli_reset_port;
+    if (true == circuit_lib.port_is_prog(model_global_port)) {
+      stimuli_reset_port.set_name(std::string(TOP_TB_PROG_RESET_PORT_NAME));
+      stimuli_reset_port.set_width(1);
+    } else {
+      VTR_ASSERT_SAFE(false == circuit_lib.port_is_prog(model_global_port));
+      stimuli_reset_port.set_name(std::string(TOP_TB_RESET_PORT_NAME));
+      stimuli_reset_port.set_width(1);
+    }
+    /* Wire the port to the input stimuli:
+     * The wiring will be inverted if the default value of the global port is 1
+     * Otherwise, the wiring will not be inverted!
+     */
+    print_verilog_wire_connection(fp, module_manager.module_port(top_module, module_global_port), 
+                                  stimuli_reset_port, 
+                                  1 == circuit_lib.port_default_value(model_global_port)); 
+  }
+
+  /* Connect global set ports to operating or programming set signal */
+  for (const CircuitPortId& model_global_port : global_ports) {
+    /* Bypass clock signals, they have been processed */
+    if (CIRCUIT_MODEL_PORT_CLOCK == circuit_lib.port_type(model_global_port)) {
+      continue;
+    }
+    /* Bypass config_done signals, they have been processed */
+    if (true == circuit_lib.port_is_config_enable(model_global_port)) {
+      continue;
+    }
+
+    /* Bypass reset signals, they have been processed */
+    if (true == circuit_lib.port_is_reset(model_global_port)) {
+      continue;
+    }
+
+    if (false == circuit_lib.port_is_set(model_global_port)) {
+      continue;
+    }
+    /* Reach here, it means we have a set port to deal with */
+    /* Find the module port */
+    ModulePortId module_global_port = module_manager.find_module_port(top_module, circuit_lib.port_prefix(model_global_port));
+    VTR_ASSERT(true == module_manager.valid_module_port_id(top_module, module_global_port));
+
+    BasicPort stimuli_set_port;
+    if (true == circuit_lib.port_is_prog(model_global_port)) {
+      stimuli_set_port.set_name(std::string(TOP_TB_PROG_SET_PORT_NAME));
+      stimuli_set_port.set_width(1);
+    } else {
+      VTR_ASSERT_SAFE(false == circuit_lib.port_is_prog(model_global_port));
+      stimuli_set_port.set_name(std::string(TOP_TB_SET_PORT_NAME));
+      stimuli_set_port.set_width(1);
+    }
+    /* Wire the port to the input stimuli:
+     * The wiring will be inverted if the default value of the global port is 1
+     * Otherwise, the wiring will not be inverted!
+     */
+    print_verilog_wire_connection(fp, module_manager.module_port(top_module, module_global_port), 
+                                  stimuli_set_port, 
+                                  1 == circuit_lib.port_default_value(model_global_port)); 
+  }
+
+  /* For the rest of global ports, wire them to constant signals */
+  for (const CircuitPortId& model_global_port : global_ports) {
+    /* Bypass clock signals, they have been processed */
+    if (CIRCUIT_MODEL_PORT_CLOCK == circuit_lib.port_type(model_global_port)) {
+      continue;
+    }
+    /* Bypass config_done signals, they have been processed */
+    if (true == circuit_lib.port_is_config_enable(model_global_port)) {
+      continue;
+    }
+
+    /* Bypass reset signals, they have been processed */
+    if (true == circuit_lib.port_is_reset(model_global_port)) {
+      continue;
+    }
+
+    /* Bypass set signals, they have been processed */
+    if (true == circuit_lib.port_is_set(model_global_port)) {
+      continue;
+    }
+
+    /* Reach here, it means we have a port to deal with */
+    /* Find the module port and wire it to constant values */
+    ModulePortId module_global_port = module_manager.find_module_port(top_module, circuit_lib.port_prefix(model_global_port));
+    VTR_ASSERT(true == module_manager.valid_module_port_id(top_module, module_global_port));
+
+    BasicPort module_port = module_manager.module_port(top_module, module_global_port);
+    std::vector<size_t> default_values(module_port.get_width(), circuit_lib.port_default_value(model_global_port));
+    print_verilog_wire_constant_values(fp, module_port, default_values);
+  }
+
+  print_verilog_comment(fp, std::string("----- End connecting global ports of FPGA fabric to stimuli -----"));
+}
+
+/********************************************************************
+ * This function prints the top testbench module declaration 
+ * and internal wires/port declaration
+ * Ports can be classified in two categories:
+ * 1. General-purpose ports, which are datapath I/Os, clock signals
+ *    for the FPGA fabric and input benchmark
+ * 2. Fabric-featured ports, which are required by configuration
+ *    protocols.
+ *    Due the difference in configuration protocols, the internal
+ *    wires and ports will be different:
+ *    (a) configuration-chain: we will have two ports,
+ *        a head and a tail for the configuration chain,
+ *        in addition to the regular ports.
+ *    (b) memory-decoders: we will have a few ports to drive 
+ *        address lines for decoders and a bit input port to feed
+ *        configuration bits
+ *******************************************************************/
+static 
+void print_verilog_top_testbench_ports(std::fstream& fp,
+                                       const ModuleManager& module_manager,
+                                       const ModuleId& top_module,
+                                       const AtomContext& atom_ctx,
+                                       const std::vector<std::string>& clock_port_names,
+                                       const e_config_protocol_type& sram_orgz_type,
+                                       const std::string& circuit_name){
+  /* Validate the file stream */
+  valid_file_stream(fp);
+
+  /* Print module definition */
+  fp << "module " << circuit_name << std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_MODULE_POSTFIX);
+  fp << ";" << std::endl;
+
+  /* Print regular local wires:
+   * 1. global ports, i.e., reset, set and clock signals
+   * 2. datapath I/O signals
+   */
+  /* Global ports of top-level module  */
+  print_verilog_comment(fp, std::string("----- Local wires for global ports of FPGA fabric -----"));
+  for (const BasicPort& module_port : module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GLOBAL_PORT)) {
+    fp << generate_verilog_port(VERILOG_PORT_WIRE, module_port) << ";" << std::endl;
+  }
+  /* Add an empty line as a splitter */
+  fp << std::endl;
+
+  /* Datapath I/Os of top-level module  */
+  print_verilog_comment(fp, std::string("----- Local wires for I/Os of FPGA fabric -----"));
+  for (const BasicPort& module_port : module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPIO_PORT)) {
+    fp << generate_verilog_port(VERILOG_PORT_WIRE, module_port) << ";" << std::endl;
+  }
+  /* Add an empty line as a splitter */
+  fp << std::endl;
+
+  /* Add local wires/registers that drive stimulus
+   * We create these general purpose ports here,
+   * and then wire them to the ports of FPGA fabric depending on their usage 
+   */
+  /* Configuration done port */
+  BasicPort config_done_port(std::string(TOP_TB_CONFIG_DONE_PORT_NAME), 1);
+  fp << generate_verilog_port(VERILOG_PORT_REG, config_done_port) << ";" << std::endl;
+
+  /* Programming clock */
+  BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME), 1);
+  fp << generate_verilog_port(VERILOG_PORT_WIRE, prog_clock_port) << ";" << std::endl;
+  BasicPort prog_clock_register_port(std::string(std::string(TOP_TB_PROG_CLOCK_PORT_NAME) + std::string(TOP_TB_CLOCK_REG_POSTFIX)), 1);
+  fp << generate_verilog_port(VERILOG_PORT_REG, prog_clock_register_port) << ";" << std::endl;
+
+  /* Operating clock */
+  BasicPort op_clock_port(std::string(TOP_TB_OP_CLOCK_PORT_NAME), 1);
+  fp << generate_verilog_port(VERILOG_PORT_WIRE, op_clock_port) << ";" << std::endl;
+  BasicPort op_clock_register_port(std::string(std::string(TOP_TB_OP_CLOCK_PORT_NAME) + std::string(TOP_TB_CLOCK_REG_POSTFIX)), 1);
+  fp << generate_verilog_port(VERILOG_PORT_REG, op_clock_register_port) << ";" << std::endl;
+
+  /* Programming set and reset */
+  BasicPort prog_reset_port(std::string(TOP_TB_PROG_RESET_PORT_NAME), 1);
+  fp << generate_verilog_port(VERILOG_PORT_REG, prog_reset_port) << ";" << std::endl;
+  BasicPort prog_set_port(std::string(TOP_TB_PROG_SET_PORT_NAME), 1);
+  fp << generate_verilog_port(VERILOG_PORT_REG, prog_set_port) << ";" << std::endl;
+
+  /* Global set and reset */
+  BasicPort reset_port(std::string(TOP_TB_RESET_PORT_NAME), 1);
+  fp << generate_verilog_port(VERILOG_PORT_REG, reset_port) << ";" << std::endl;
+  BasicPort set_port(std::string(TOP_TB_SET_PORT_NAME), 1);
+  fp << generate_verilog_port(VERILOG_PORT_REG, set_port) << ";" << std::endl;
+
+  /* Configuration ports depend on the organization of SRAMs */
+  print_verilog_top_testbench_config_protocol_port(fp, sram_orgz_type);
+
+  /* Create a clock port if the benchmark have one but not in the default name! 
+   * We will wire the clock directly to the operating clock directly
+   */
+  for (const std::string clock_port_name : clock_port_names) {
+    if (0 == clock_port_name.compare(op_clock_port.get_name())) {
+      continue;
+    }
+    /* Ensure the clock port name is not a duplication of global ports of the FPGA module */
+    bool print_clock_port = true;
+    for (const BasicPort& module_port : module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GLOBAL_PORT)) {
+      if (0 == clock_port_name.compare(module_port.get_name())) {
+        print_clock_port = false;
+      }
+    }
+    if (false == print_clock_port) {
+      continue;
+    }
+
+    /* Print the clock and wire it to op_clock */
+    print_verilog_comment(fp, std::string("----- Create a clock for benchmark and wire it to op_clock -------"));
+    BasicPort clock_port(clock_port_name, 1);
+    fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, clock_port) << ";" << std::endl;
+    print_verilog_wire_connection(fp, clock_port, op_clock_port, false);
+  }
+
+  print_verilog_testbench_shared_ports(fp, atom_ctx,
+                                       std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX),
+                                       std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX),
+                                       std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX),
+                                       std::string(AUTOCHECKED_SIMULATION_FLAG));
+
+  /* Instantiate an integer to count the number of error and 
+   * determine if the simulation succeed or failed
+   */
+  print_verilog_comment(fp, std::string("----- Error counter -----"));
+  fp << "\tinteger " << TOP_TESTBENCH_ERROR_COUNTER << "= 0;" << std::endl;
+}
+
+/********************************************************************
+ * Instanciate the input benchmark module
+ *******************************************************************/
+static
+void print_verilog_top_testbench_benchmark_instance(std::fstream& fp, 
+                                                    const std::string& reference_verilog_top_name,
+                                                    const AtomContext& atom_ctx) {
+  /* Validate the file stream */
+  valid_file_stream(fp);
+
+  /* Benchmark is instanciated conditionally: only when a preprocessing flag is enable */
+  print_verilog_preprocessing_flag(fp, std::string(AUTOCHECKED_SIMULATION_FLAG)); 
+
+  print_verilog_comment(fp, std::string("----- Reference Benchmark Instanication -------"));
+
+  /* Do NOT use explicit port mapping here: 
+   * VPR added a prefix of "out_" to the output ports of input benchmark
+   */
+  print_verilog_testbench_benchmark_instance(fp, reference_verilog_top_name,
+                                             std::string(TOP_TESTBENCH_REFERENCE_INSTANCE_NAME),
+                                             std::string(),
+                                             std::string(),
+                                             std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX),
+                                             atom_ctx,
+                                             false);
+
+  print_verilog_comment(fp, std::string("----- End reference Benchmark Instanication -------"));
+
+  /* Add an empty line as splitter */
+  fp << std::endl;
+
+  /* Condition ends for the benchmark instanciation */
+  print_verilog_endif(fp);
+
+  /* Add an empty line as splitter */
+  fp << std::endl;
+}
+
+/********************************************************************
+ * Print tasks (processes) in Verilog format, 
+ * which is very useful in generating stimuli for each clock cycle 
+ * This function is tuned for configuration-chain manipulation: 
+ * During each programming cycle, we feed the input of scan chain with a memory bit
+ *******************************************************************/
+static 
+void print_verilog_top_testbench_load_bitstream_task_configuration_chain(std::fstream& fp) {
+
+  /* Validate the file stream */
+  valid_file_stream(fp);
+
+  BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME), 1);
+  BasicPort cc_head_port(generate_configuration_chain_head_name(), 1);
+  BasicPort cc_head_value(generate_configuration_chain_head_name() + std::string("_val"), 1);
+
+  /* Add an empty line as splitter */
+  fp << std::endl;
+
+  /* Feed the scan-chain input at each falling edge of programming clock 
+   * It aims at avoid racing the programming clock (scan-chain data changes at the rising edge). 
+   */
+  print_verilog_comment(fp, std::string("----- Task: input values during a programming clock cycle -----"));
+  fp << "task " << std::string(TOP_TESTBENCH_CC_PROG_TASK_NAME) << ";" << std::endl;
+  fp << generate_verilog_port(VERILOG_PORT_INPUT, cc_head_value) << ";" << std::endl;
+  fp << "\tbegin" << std::endl;
+  fp << "\t\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ");" << std::endl;
+  fp << "\t\t\t"; 
+  fp << generate_verilog_port(VERILOG_PORT_CONKT, cc_head_port);
+  fp << " = ";
+  fp << generate_verilog_port(VERILOG_PORT_CONKT, cc_head_value);
+  fp << ";" << std::endl;
+
+  fp << "\tend" << std::endl;
+  fp << "endtask" << std::endl;
+
+  /* Add an empty line as splitter */
+  fp << std::endl;
+}
+
+/********************************************************************
+ * Print tasks, which is very useful in generating stimuli for each clock cycle 
+ *******************************************************************/
+static 
+void print_verilog_top_testbench_load_bitstream_task(std::fstream& fp,
+                                                     const e_config_protocol_type& sram_orgz_type) {
+  switch (sram_orgz_type) {
+  case CONFIG_MEM_STANDALONE:
+    break;
+  case CONFIG_MEM_SCAN_CHAIN:
+    print_verilog_top_testbench_load_bitstream_task_configuration_chain(fp);
+    break;
+  case CONFIG_MEM_MEMORY_BANK:
+    /* TODO: 
+    dump_verilog_top_testbench_stimuli_serial_version_tasks_memory_bank(cur_sram_orgz_info, fp);
+     */
+    break;
+  default:
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid type of SRAM organization!\n");
+    exit(1);
+  }
+}
+
+/********************************************************************
+ * Print generatic input stimuli for the top testbench
+ * include:
+ * 1. configuration done signal
+ * 2. programming clock
+ * 3. operating clock
+ * 4. programming reset signal
+ * 5. programming set signal
+ * 6. reset signal
+ * 7. set signal
+ *******************************************************************/
+static 
+void print_verilog_top_testbench_generic_stimulus(std::fstream& fp,
+                                                  const size_t& num_config_clock_cycles,
+                                                  const float& prog_clock_period,
+                                                  const float& op_clock_period,
+                                                  const float& timescale) {
+  /* Validate the file stream */
+  valid_file_stream(fp);
+
+  print_verilog_comment(fp, std::string("----- Number of clock cycles in configuration phase: " + std::to_string(num_config_clock_cycles) + " -----")); 
+
+  BasicPort config_done_port(std::string(TOP_TB_CONFIG_DONE_PORT_NAME), 1);
+
+  BasicPort op_clock_port(std::string(TOP_TB_OP_CLOCK_PORT_NAME), 1);
+  BasicPort op_clock_register_port(std::string(std::string(TOP_TB_OP_CLOCK_PORT_NAME) + std::string(TOP_TB_CLOCK_REG_POSTFIX)), 1);
+
+  BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME), 1);
+  BasicPort prog_clock_register_port(std::string(std::string(TOP_TB_PROG_CLOCK_PORT_NAME) + std::string(TOP_TB_CLOCK_REG_POSTFIX)), 1);
+
+  BasicPort prog_reset_port(std::string(TOP_TB_PROG_RESET_PORT_NAME), 1);
+  BasicPort prog_set_port(std::string(TOP_TB_PROG_SET_PORT_NAME), 1);
+
+  BasicPort reset_port(std::string(TOP_TB_RESET_PORT_NAME), 1);
+  BasicPort set_port(std::string(TOP_TB_SET_PORT_NAME), 1);
+
+  /* Generate stimuli waveform for configuration done signals */
+  print_verilog_comment(fp, "----- Begin configuration done signal generation -----"); 
+  print_verilog_pulse_stimuli(fp, config_done_port, 
+                              0, /* Initial value */
+                              num_config_clock_cycles * prog_clock_period / timescale, 0); 
+  print_verilog_comment(fp, "----- End configuration done signal generation -----"); 
+  fp << std::endl;
+
+  /* Generate stimuli waveform for programming clock signals */
+  print_verilog_comment(fp, "----- Begin raw programming clock signal generation -----"); 
+  print_verilog_clock_stimuli(fp, prog_clock_register_port, 
+                              0, /* Initial value */
+                              0.5 * prog_clock_period / timescale,
+                              std::string()); 
+  print_verilog_comment(fp, "----- End raw programming clock signal generation -----"); 
+  fp << std::endl;
+
+  /* Programming clock should be only enabled during programming phase.
+   * When configuration is done (config_done is enabled), programming clock should be always zero.
+   */
+  print_verilog_comment(fp, std::string("----- Actual programming clock is triggered only when " + config_done_port.get_name() + " and " + prog_reset_port.get_name() + " are disabled -----")); 
+  fp << "\tassign " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port);
+  fp << " = " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_register_port);
+  fp << " & (~" << generate_verilog_port(VERILOG_PORT_CONKT, config_done_port) << ")";
+  fp << " & (~" << generate_verilog_port(VERILOG_PORT_CONKT, prog_reset_port) << ")";
+  fp << ";" << std::endl;
+
+  fp << std::endl;
+
+  /* Generate stimuli waveform for operating clock signals */
+  print_verilog_comment(fp, "----- Begin raw operating clock signal generation -----"); 
+  print_verilog_clock_stimuli(fp, op_clock_register_port, 
+                              0, /* Initial value */
+                              0.5 * op_clock_period / timescale,
+                              std::string("~" + reset_port.get_name())); 
+  print_verilog_comment(fp, "----- End raw operating clock signal generation -----"); 
+
+  /* Operation clock should be enabled after programming phase finishes.
+   * Before configuration is done (config_done is enabled), operation clock should be always zero.
+   */
+  print_verilog_comment(fp, std::string("----- Actual operating clock is triggered only when " + config_done_port.get_name() + " is enabled -----")); 
+  fp << "\tassign " << generate_verilog_port(VERILOG_PORT_CONKT, op_clock_port);
+  fp << " = " << generate_verilog_port(VERILOG_PORT_CONKT, op_clock_register_port);
+  fp << " & " << generate_verilog_port(VERILOG_PORT_CONKT, config_done_port);
+  fp << ";" << std::endl;
+
+  fp << std::endl;
+
+  /* Reset signal for configuration circuit: 
+   * only enable during the first clock cycle in programming phase 
+   */
+  print_verilog_comment(fp, "----- Begin programming reset signal generation -----"); 
+  print_verilog_pulse_stimuli(fp, prog_reset_port, 
+                              1, /* Initial value */
+                              prog_clock_period / timescale, 0); 
+  print_verilog_comment(fp, "----- End programming reset signal generation -----"); 
+
+  fp << std::endl;
+
+  /* Programming set signal for configuration circuit : always disabled */
+  print_verilog_comment(fp, "----- Begin programming set signal generation: always disabled -----"); 
+  print_verilog_pulse_stimuli(fp, prog_set_port, 
+                              0, /* Initial value */
+                              prog_clock_period / timescale, 0); 
+  print_verilog_comment(fp, "----- End programming set signal generation: always disabled -----"); 
+
+  fp << std::endl;
+
+  /* Operating reset signals: only enabled during the first clock cycle in operation phase */
+  std::vector<float> reset_pulse_widths;
+  reset_pulse_widths.push_back(op_clock_period / timescale);
+  reset_pulse_widths.push_back(2 * op_clock_period / timescale);
+
+  std::vector<size_t> reset_flip_values;
+  reset_flip_values.push_back(1);
+  reset_flip_values.push_back(0);
+
+  print_verilog_comment(fp, "----- Begin operating reset signal generation -----"); 
+  print_verilog_comment(fp, "----- Reset signal is enabled until the first clock cycle in operation phase -----");
+  print_verilog_pulse_stimuli(fp, reset_port,
+                              1,
+                              reset_pulse_widths,
+                              reset_flip_values,
+                              config_done_port.get_name());
+  print_verilog_comment(fp, "----- End operating reset signal generation -----"); 
+
+  /* Operating set signal for configuration circuit : always disabled */
+  print_verilog_comment(fp, "----- Begin operating set signal generation: always disabled -----"); 
+  print_verilog_pulse_stimuli(fp, set_port, 
+                              0, /* Initial value */
+                              op_clock_period / timescale, 0); 
+  print_verilog_comment(fp, "----- End operating set signal generation: always disabled -----"); 
+
+  fp << std::endl;
+}
+
+/********************************************************************
+ * Print stimulus for a FPGA fabric with a configuration chain protocol 
+ * where configuration bits are programming in serial (one by one)
+ * Task list:
+ * 1. For clock signal, we should create voltage waveforms for two types of clock signals:
+ *    a. operation clock
+ *    b. programming clock 
+ * 2. For Set/Reset, we reset the chip after programming phase ends 
+ *    and before operation phase starts
+ * 3. For input/output clb nets (mapped to I/O grids), 
+ *    we should create voltage waveforms only after programming phase 
+ *******************************************************************/
+static 
+void print_verilog_top_testbench_configuration_chain_bitstream(std::fstream& fp,
+                                                               const BitstreamManager& bitstream_manager,
+                                                               const std::vector<ConfigBitId>& fabric_bitstream) {
+  /* Validate the file stream */
+  valid_file_stream(fp);
+
+  /* Initial value should be the first configuration bits
+   * In the rest of programming cycles, 
+   * configuration bits are fed at the falling edge of programming clock.
+   * We do not care the value of scan_chain head during the first programming cycle 
+   * It is reset anyway
+   */
+  BasicPort config_chain_head_port(generate_configuration_chain_head_name(), 1);
+  std::vector<size_t> initial_values(config_chain_head_port.get_width(), 0);
+
+  print_verilog_comment(fp, "----- Begin bitstream loading during configuration phase -----");
+  fp << "initial" << std::endl;
+  fp << "\tbegin" << std::endl;
+  print_verilog_comment(fp, "----- Configuration chain default input -----");
+  fp << "\t\t";
+  fp << generate_verilog_port_constant_values(config_chain_head_port, initial_values);
+  fp << ";";
+
+  fp << std::endl;
+
+  /* Attention: the configuration chain protcol requires the last configuration bit is fed first
+   * We will visit the fabric bitstream in a reverse way  
+   */
+  std::vector<ConfigBitId> cc_bitstream = fabric_bitstream;
+  std::reverse(cc_bitstream.begin(), cc_bitstream.end());
+  for (const ConfigBitId& bit_id : cc_bitstream) {
+    fp << "\t\t" << std::string(TOP_TESTBENCH_CC_PROG_TASK_NAME);
+    fp << "(1'b" << (size_t)bitstream_manager.bit_value(bit_id) << ");" << std::endl;
+  }
+
+  /* Raise the flag of configuration done when bitstream loading is complete */
+  BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME), 1);
+  fp << "\t\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ");" << std::endl;
+  
+  BasicPort config_done_port(std::string(TOP_TB_CONFIG_DONE_PORT_NAME), 1);
+  fp << "\t\t\t";
+  fp << generate_verilog_port(VERILOG_PORT_CONKT, config_done_port);
+  fp << " <= ";
+  std::vector<size_t> config_done_enable_values(config_done_port.get_width(), 1);
+  fp << generate_verilog_constant_values(config_done_enable_values);
+  fp << ";" << std::endl;
+
+  fp << "\tend" << std::endl;
+  print_verilog_comment(fp, "----- End bitstream loading during configuration phase -----");
+}
+
+/********************************************************************
+ * Generate the stimuli for the top-level testbench 
+ * The simulation consists of two phases: configuration phase and operation phase
+ * Configuration bits are loaded serially. 
+ * This is actually what we do for a physical FPGA
+ *******************************************************************/
+static 
+void print_verilog_top_testbench_bitstream(std::fstream& fp,
+                                           const e_config_protocol_type& sram_orgz_type,
+                                           const BitstreamManager& bitstream_manager,
+                                           const std::vector<ConfigBitId>& fabric_bitstream) {
+  /* Branch on the type of configuration protocol */
+  switch (sram_orgz_type) {
+  case CONFIG_MEM_STANDALONE:
+    /* TODO */
+    break;
+  case CONFIG_MEM_SCAN_CHAIN:
+    print_verilog_top_testbench_configuration_chain_bitstream(fp, bitstream_manager, fabric_bitstream);
+    break;
+  case CONFIG_MEM_MEMORY_BANK:
+    /* TODO */
+    break;
+  default: 
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid SRAM organization type!\n");
+    exit(1);
+  }
+}
+
+/********************************************************************
+ * The top-level function to generate a testbench, in order to verify: 
+ * 1. Configuration phase of the FPGA fabric, where the bitstream is 
+ *    loaded to the configuration protocol of the FPGA fabric
+ * 2. Operating phase of the FPGA fabric, where input stimuli are
+ *    fed to the I/Os of the FPGA fabric
+ *                                    +----------+
+ *                                    |   FPGA   |       +------------+
+ *                             +----->|  Fabric  |------>|            |
+ *                             |      |          |       |            |
+ *                             |      +----------+       |            |
+ *                             |                         | Output     | 
+ *   random_input_vectors -----+                         | Vector     |---->Functional correct?
+ *                             |                         | Comparator |    
+ *                             |      +-----------+      |            |
+ *                             |      |  Input    |      |            |
+ *                             +----->| Benchmark |----->|            |
+ *                                    +-----------+      +------------+
+ *
+ *******************************************************************/
+void print_verilog_top_testbench(const ModuleManager& module_manager,
+                                 const BitstreamManager& bitstream_manager,
+                                 const std::vector<ConfigBitId>& fabric_bitstream,
+                                 const e_config_protocol_type& sram_orgz_type,
+                                 const CircuitLibrary& circuit_lib,
+                                 const std::vector<CircuitPortId>& global_ports,
+                                 const AtomContext& atom_ctx,
+                                 const PlacementContext& place_ctx, 
+                                 const IoLocationMap& io_location_map,
+                                 const std::string& circuit_name,
+                                 const std::string& verilog_fname,
+                                 const std::string& verilog_dir,
+                                 const SimulationSetting& simulation_parameters) {
+
+  std::string timer_message = std::string("Write autocheck testbench for FPGA top-level Verilog netlist for '") + circuit_name + std::string("'");
+
+  /* Start time count */
+  vtr::ScopedStartFinishTimer timer(timer_message);
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
+
+  /* Validate the file stream */
+  check_file_stream(verilog_fname.c_str(), fp);
+
+  /* Generate a brief description on the Verilog file*/
+  std::string title = std::string("FPGA Verilog Testbench for Top-level netlist of Design: ") + circuit_name;
+  print_verilog_file_header(fp, title); 
+
+  /* Print preprocessing flags and external netlists */
+  print_verilog_include_defines_preproc_file(fp, verilog_dir);
+
+  /* Find the top_module */
+  ModuleId top_module = module_manager.find_module(generate_fpga_top_module_name());
+  VTR_ASSERT(true == module_manager.valid_module_id(top_module));
+
+  /* Preparation: find all the clock ports */
+  std::vector<std::string> clock_port_names = find_atom_netlist_clock_port_names(atom_ctx.nlist);
+
+  /* Start of testbench */
+  print_verilog_top_testbench_ports(fp, module_manager, top_module, 
+                                    atom_ctx, clock_port_names,
+                                    sram_orgz_type, circuit_name);
+
+  /* Find the clock period */
+  float prog_clock_period = (1./simulation_parameters.programming_clock_frequency());
+  float op_clock_period = (1./simulation_parameters.operating_clock_frequency());
+  /* Estimate the number of configuration clock cycles 
+   * by traversing the linked-list and count the number of SRAM=1 or BL=1&WL=1 in it.
+   * We plus 1 additional config clock cycle here because we need to reset everything during the first clock cycle
+   */
+  size_t num_config_clock_cycles = 1 + fabric_bitstream.size();
+
+  /* Generate stimuli for general control signals */
+  print_verilog_top_testbench_generic_stimulus(fp,
+                                               num_config_clock_cycles,
+                                               prog_clock_period,
+                                               op_clock_period,
+                                               VERILOG_SIM_TIMESCALE);
+
+  /* Generate stimuli for global ports or connect them to existed signals */
+  print_verilog_top_testbench_global_ports_stimuli(fp,
+                                                   module_manager, top_module,
+                                                   circuit_lib, global_ports);
+
+  /* Instanciate FPGA top-level module */
+  print_verilog_testbench_fpga_instance(fp, module_manager, top_module, 
+                                        std::string(TOP_TESTBENCH_FPGA_INSTANCE_NAME)); 
+  
+  /* Connect I/Os to benchmark I/Os or constant driver */
+  print_verilog_testbench_connect_fpga_ios(fp, module_manager, top_module,
+                                           atom_ctx, place_ctx, io_location_map, 
+                                           std::string(), 
+                                           std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX), 
+                                           (size_t)VERILOG_DEFAULT_SIGNAL_INIT_VALUE);
+
+  /* Instanciate input benchmark */
+  print_verilog_top_testbench_benchmark_instance(fp, 
+                                                 circuit_name,
+                                                 atom_ctx);
+
+  /* Print tasks used for loading bitstreams */
+  print_verilog_top_testbench_load_bitstream_task(fp, sram_orgz_type);
+
+  /* load bitstream to FPGA fabric in a configuration phase */
+  print_verilog_top_testbench_bitstream(fp, sram_orgz_type,
+                                        bitstream_manager, fabric_bitstream);
+
+  /* Add stimuli for reset, set, clock and iopad signals */
+  print_verilog_testbench_random_stimuli(fp, atom_ctx, 
+                                         std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX),
+                                         BasicPort(std::string(TOP_TB_OP_CLOCK_PORT_NAME), 1));
+
+  /* Add output autocheck */
+  print_verilog_testbench_check(fp, 
+                                std::string(AUTOCHECKED_SIMULATION_FLAG),
+                                std::string(TOP_TESTBENCH_SIM_START_PORT_NAME),
+                                std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX),
+                                std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX),
+                                std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX),
+                                std::string(TOP_TESTBENCH_ERROR_COUNTER),
+                                atom_ctx, clock_port_names, std::string(TOP_TB_OP_CLOCK_PORT_NAME));
+
+  /* Find simulation time */
+  float simulation_time = find_simulation_time_period(VERILOG_SIM_TIMESCALE,
+                                                      num_config_clock_cycles,
+										              1./simulation_parameters.programming_clock_frequency(),
+                                                      simulation_parameters.num_clock_cycles(),
+                                                      1./simulation_parameters.operating_clock_frequency());
+
+
+  /* Add Icarus requirement */
+  print_verilog_timeout_and_vcd(fp, 
+                                std::string(ICARUS_SIMULATOR_FLAG),
+                                std::string(circuit_name + std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_MODULE_POSTFIX)),
+                                std::string(circuit_name + std::string("_formal.vcd")), 
+                                std::string(TOP_TESTBENCH_SIM_START_PORT_NAME),
+                                std::string(TOP_TESTBENCH_ERROR_COUNTER),
+                                (int)simulation_time);
+
+
+  /* Testbench ends*/
+  print_verilog_module_end(fp, std::string(circuit_name) + std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_MODULE_POSTFIX));
+
+  /* Close the file stream */
+  fp.close();
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.h b/openfpga/src/fpga_verilog/verilog_top_testbench.h
new file mode 100644
index 000000000..e2e652eb8
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_top_testbench.h
@@ -0,0 +1,39 @@
+#ifndef VERILOG_TOP_TESTBENCH
+#define VERILOG_TOP_TESTBENCH
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <string>
+#include <vector>
+#include "module_manager.h"
+#include "bitstream_manager.h"
+#include "circuit_library.h"
+#include "vpr_context.h"
+#include "io_location_map.h"
+#include "simulation_setting.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void print_verilog_top_testbench(const ModuleManager& module_manager,
+                                 const BitstreamManager& bitstream_manager,
+                                 const std::vector<ConfigBitId>& fabric_bitstream,
+                                 const e_config_protocol_type& sram_orgz_type,
+                                 const CircuitLibrary& circuit_lib,
+                                 const std::vector<CircuitPortId>& global_ports,
+                                 const AtomContext& atom_ctx,
+                                 const PlacementContext& place_ctx, 
+                                 const IoLocationMap& io_location_map,
+                                 const std::string& circuit_name,
+                                 const std::string& verilog_fname,
+                                 const std::string& verilog_dir,
+                                 const SimulationSetting& simulation_parameters);
+
+} /* end namespace openfpga */
+
+#endif

From f558405887418a25d233fe1d4ec4afeb7197c68e Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 27 Feb 2020 12:33:09 -0700
Subject: [PATCH 218/645] ported verilog testbench generator online. Split from
 fabric generator. Testing to be done

---
 openfpga/src/base/openfpga_verilog.cpp        |  46 +++++-
 openfpga/src/base/openfpga_verilog.h          |   3 +
 .../src/base/openfpga_verilog_command.cpp     | 137 +++++++++++++-----
 ...options.cpp => fabric_verilog_options.cpp} |  30 +---
 ...log_options.h => fabric_verilog_options.h} |  10 +-
 openfpga/src/fpga_verilog/verilog_api.cpp     | 130 +++++++++++++++--
 openfpga/src/fpga_verilog/verilog_api.h       |  19 ++-
 .../verilog_auxiliary_netlists.cpp            |  23 ++-
 .../fpga_verilog/verilog_auxiliary_netlists.h |   7 +-
 .../verilog_preconfig_top_module.h            |   5 +-
 openfpga/src/fpga_verilog/verilog_submodule.h |   2 +-
 .../verilog_testbench_options.cpp             |  97 +++++++++++++
 .../fpga_verilog/verilog_testbench_options.h  |  62 ++++++++
 13 files changed, 459 insertions(+), 112 deletions(-)
 rename openfpga/src/fpga_verilog/{verilog_options.cpp => fabric_verilog_options.cpp} (75%)
 rename openfpga/src/fpga_verilog/{verilog_options.h => fabric_verilog_options.h} (89%)
 create mode 100644 openfpga/src/fpga_verilog/verilog_testbench_options.cpp
 create mode 100644 openfpga/src/fpga_verilog/verilog_testbench_options.h

diff --git a/openfpga/src/base/openfpga_verilog.cpp b/openfpga/src/base/openfpga_verilog.cpp
index 72b8fb100..2a6c88241 100644
--- a/openfpga/src/base/openfpga_verilog.cpp
+++ b/openfpga/src/base/openfpga_verilog.cpp
@@ -15,7 +15,7 @@
 namespace openfpga {
 
 /********************************************************************
- * A wrapper function to call the fabric_verilog function of FPGA-Verilog 
+ * A wrapper function to call the fabric Verilog generator of FPGA-Verilog 
  *******************************************************************/
 void write_fabric_verilog(OpenfpgaContext& openfpga_ctx,
                           const Command& cmd, const CommandContext& cmd_context) {
@@ -26,9 +26,6 @@ void write_fabric_verilog(OpenfpgaContext& openfpga_ctx,
   CommandOptionId opt_include_signal_init = cmd.option("include_signal_init");
   CommandOptionId opt_support_icarus_simulator = cmd.option("support_icarus_simulator");
   CommandOptionId opt_print_user_defined_template = cmd.option("print_user_defined_template");
-  CommandOptionId opt_print_top_testbench = cmd.option("print_top_testbench");
-  CommandOptionId opt_print_formal_verification_top_netlist = cmd.option("print_formal_verification_top_netlist");
-  CommandOptionId opt_print_autocheck_top_testbench = cmd.option("print_autocheck_top_testbench");
   CommandOptionId opt_verbose = cmd.option("verbose");
 
   /* This is an intermediate data structure which is designed to modularize the FPGA-Verilog
@@ -41,9 +38,6 @@ void write_fabric_verilog(OpenfpgaContext& openfpga_ctx,
   options.set_include_signal_init(cmd_context.option_enable(cmd, opt_include_signal_init));
   options.set_support_icarus_simulator(cmd_context.option_enable(cmd, opt_support_icarus_simulator));
   options.set_print_user_defined_template(cmd_context.option_enable(cmd, opt_print_user_defined_template));
-  options.set_print_top_testbench(cmd_context.option_enable(cmd, opt_print_top_testbench));
-  options.set_print_formal_verification_top_netlist(cmd_context.option_enable(cmd, opt_print_formal_verification_top_netlist));
-  options.set_print_autocheck_top_testbench(cmd_context.option_value(cmd, opt_print_autocheck_top_testbench));
   options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
   options.set_compress_routing(openfpga_ctx.flow_manager().compress_routing());
   
@@ -56,4 +50,42 @@ void write_fabric_verilog(OpenfpgaContext& openfpga_ctx,
                       options);
 } 
 
+/********************************************************************
+ * A wrapper function to call the Verilog testbench generator of FPGA-Verilog 
+ *******************************************************************/
+void write_verilog_testbench(OpenfpgaContext& openfpga_ctx,
+                             const Command& cmd, const CommandContext& cmd_context) {
+
+  CommandOptionId opt_output_dir = cmd.option("file");
+  CommandOptionId opt_reference_benchmark = cmd.option("reference_verilog_file_path");
+  CommandOptionId opt_print_top_testbench = cmd.option("print_top_testbench");
+  CommandOptionId opt_print_formal_verification_top_netlist = cmd.option("print_formal_verification_top_netlist");
+  CommandOptionId opt_print_preconfig_top_testbench = cmd.option("print_preconfig_top_testbench");
+  CommandOptionId opt_print_simulation_ini = cmd.option("print_simulation_ini");
+  CommandOptionId opt_verbose = cmd.option("verbose");
+
+  /* This is an intermediate data structure which is designed to modularize the FPGA-Verilog
+   * Keep it independent from any other outside data structures
+   */
+  VerilogTestbenchOption options;
+  options.set_output_directory(cmd_context.option_value(cmd, opt_output_dir));
+  options.set_reference_verilog_file_path(cmd_context.option_value(cmd, opt_reference_benchmark));
+  options.set_print_formal_verification_top_netlist(cmd_context.option_enable(cmd, opt_print_formal_verification_top_netlist));
+  options.set_print_preconfig_top_testbench(cmd_context.option_enable(cmd, opt_print_preconfig_top_testbench));
+  options.set_print_top_testbench(cmd_context.option_enable(cmd, opt_print_top_testbench));
+  options.set_print_simulation_ini(cmd_context.option_value(cmd, opt_print_simulation_ini));
+  options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
+  
+  fpga_verilog_testbench(openfpga_ctx.module_graph(),
+                         openfpga_ctx.bitstream_manager(),
+                         openfpga_ctx.fabric_bitstream(),
+                         g_vpr_ctx.atom(),
+                         g_vpr_ctx.placement(),
+                         openfpga_ctx.io_location_map(),
+                         openfpga_ctx.arch().circuit_lib,
+                         openfpga_ctx.arch().sim_setting,
+                         openfpga_ctx.arch().config_protocol.type(),
+                         options);
+} 
+
 } /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_verilog.h b/openfpga/src/base/openfpga_verilog.h
index a62d19411..faf8cf6b0 100644
--- a/openfpga/src/base/openfpga_verilog.h
+++ b/openfpga/src/base/openfpga_verilog.h
@@ -18,6 +18,9 @@ namespace openfpga {
 void write_fabric_verilog(OpenfpgaContext& openfpga_ctx,
                           const Command& cmd, const CommandContext& cmd_context); 
 
+void write_verilog_testbench(OpenfpgaContext& openfpga_ctx,
+                             const Command& cmd, const CommandContext& cmd_context); 
+
 } /* end namespace openfpga */
 
 #endif
diff --git a/openfpga/src/base/openfpga_verilog_command.cpp b/openfpga/src/base/openfpga_verilog_command.cpp
index 7eb7674b9..29c0ee73a 100644
--- a/openfpga/src/base/openfpga_verilog_command.cpp
+++ b/openfpga/src/base/openfpga_verilog_command.cpp
@@ -11,6 +11,99 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
+/********************************************************************
+ * - Add a command to Shell environment: generate fabric Verilog 
+ * - Add associated options 
+ * - Add command dependency
+ *******************************************************************/
+static 
+void add_openfpga_write_fabric_verilog_command(openfpga::Shell<OpenfpgaContext>& shell,
+                                               const ShellCommandClassId& cmd_class_id,
+                                               const ShellCommandId& shell_cmd_build_fabric_id) {
+  Command shell_cmd("write_fabric_verilog");
+
+  /* Add an option '--file' in short '-f'*/
+  CommandOptionId output_opt = shell_cmd.add_option("file", true, "Specify the output directory for Verilog netlists");
+  shell_cmd.set_option_short_name(output_opt, "f");
+  shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING);
+
+  /* Add an option '--explicit_port_mapping' */
+  shell_cmd.add_option("explicit_port_mapping", false, "Use explicit port mapping in Verilog netlists");
+
+  /* Add an option '--include_timing' */
+  shell_cmd.add_option("include_timing", false, "Enable timing annotation in Verilog netlists");
+
+  /* Add an option '--include_signal_init' */
+  shell_cmd.add_option("include_signal_init", false, "Initialize all the signals in Verilog netlists");
+
+  /* Add an option '--support_icarus_simulator' */
+  shell_cmd.add_option("support_icarus_simulator", false, "Fine-tune Verilog netlists to support icarus simulator");
+
+  /* Add an option '--print_user_defined_template' */
+  shell_cmd.add_option("print_user_defined_template", false, "Generate a template Verilog files for user-defined circuit models");
+
+  /* Add an option '--verbose' */
+  shell_cmd.add_option("verbose", false, "Enable verbose output");
+  
+  /* Add command 'write_fabric_verilog' to the Shell */
+  ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "generate Verilog netlists modeling full FPGA fabric");
+  shell.set_command_class(shell_cmd_id, cmd_class_id);
+  shell.set_command_execute_function(shell_cmd_id, write_verilog_testbench);
+
+  /* The 'build_fabric' command should NOT be executed before 'link_openfpga_arch' */
+  std::vector<ShellCommandId> cmd_dependency;
+  cmd_dependency.push_back(shell_cmd_build_fabric_id);
+  shell.set_command_dependency(shell_cmd_id, cmd_dependency);
+}
+
+/********************************************************************
+ * - Add a command to Shell environment: write Verilog testbench
+ * - Add associated options 
+ * - Add command dependency
+ *******************************************************************/
+static 
+void add_openfpga_write_verilog_testbench_command(openfpga::Shell<OpenfpgaContext>& shell,
+                                                  const ShellCommandClassId& cmd_class_id,
+                                                  const ShellCommandId& shell_cmd_build_fabric_id) {
+  Command shell_cmd("write_verilog_testbench");
+
+  /* Add an option '--file' in short '-f'*/
+  CommandOptionId output_opt = shell_cmd.add_option("file", true, "Specify the output directory for Verilog netlists");
+  shell_cmd.set_option_short_name(output_opt, "f");
+  shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING);
+
+  /* Add an option '--reference_benchmark_file_path'*/
+  CommandOptionId ref_bm_opt = shell_cmd.add_option("reference_benchmark_file_path", true, "Specify the file path to the reference Verilog netlist");
+  shell_cmd.set_option_require_value(ref_bm_opt, openfpga::OPT_STRING);
+
+  /* Add an option '--print_top_testbench' */
+  shell_cmd.add_option("print_top_testbench", false, "Generate a full testbench for top-level fabric module with autocheck capability");
+
+  /* Add an option '--print_formal_verification_top_netlist' */
+  shell_cmd.add_option("print_formal_verification_top_netlist", false, "Generate a top-level module which can be used in formal verification");
+
+  /* Add an option '--print_preconfig_top_testbench' */
+  CommandOptionId preconfig_tb_opt = shell_cmd.add_option("print_preconfig_top_testbench", false, "Generate a pre-configured testbench for top-level fabric module with autocheck capability");
+  shell_cmd.set_option_require_value(preconfig_tb_opt, openfpga::OPT_STRING);
+
+  /* Add an option '--print_simulation_ini' */
+  CommandOptionId sim_ini_opt = shell_cmd.add_option("print_simulation_ini", false, "Generate a .ini file as an exchangeable file to enable HDL simulations");
+  shell_cmd.set_option_require_value(sim_ini_opt, openfpga::OPT_STRING);
+
+  /* Add an option '--verbose' */
+  shell_cmd.add_option("verbose", false, "Enable verbose output");
+  
+  /* Add command to the Shell */
+  ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "generate Verilog testbenches for full FPGA fabric");
+  shell.set_command_class(shell_cmd_id, cmd_class_id);
+  shell.set_command_execute_function(shell_cmd_id, write_fabric_verilog);
+
+  /* The command should NOT be executed before 'build_fabric' */
+  std::vector<ShellCommandId> cmd_dependency;
+  cmd_dependency.push_back(shell_cmd_build_fabric_id);
+  shell.set_command_dependency(shell_cmd_id, cmd_dependency);
+}
+
 void add_openfpga_verilog_commands(openfpga::Shell<OpenfpgaContext>& shell) {
   /* Get the unique id of 'build_fabric' command which is to be used in creating the dependency graph */
   const ShellCommandId& shell_cmd_build_fabric_id = shell.command(std::string("build_fabric"));
@@ -19,42 +112,18 @@ void add_openfpga_verilog_commands(openfpga::Shell<OpenfpgaContext>& shell) {
   ShellCommandClassId openfpga_verilog_cmd_class = shell.add_command_class("FPGA-Verilog");
 
   /******************************** 
-   * Command 'wirte_fabric_verilog' 
+   * Command 'write_fabric_verilog' 
    */
-  Command shell_cmd_write_fabric_verilog("write_fabric_verilog");
-  /* Add an option '--file' in short '-f'*/
-  CommandOptionId fabric_verilog_output_opt = shell_cmd_write_fabric_verilog.add_option("file", true, "Specify the output directory for Verilog netlists");
-  shell_cmd_write_fabric_verilog.set_option_short_name(fabric_verilog_output_opt, "f");
-  shell_cmd_write_fabric_verilog.set_option_require_value(fabric_verilog_output_opt, openfpga::OPT_STRING);
-  /* Add an option '--explicit_port_mapping' */
-  shell_cmd_write_fabric_verilog.add_option("explicit_port_mapping", false, "Use explicit port mapping in Verilog netlists");
-  /* Add an option '--include_timing' */
-  shell_cmd_write_fabric_verilog.add_option("include_timing", false, "Enable timing annotation in Verilog netlists");
-  /* Add an option '--include_signal_init' */
-  shell_cmd_write_fabric_verilog.add_option("include_signal_init", false, "Initialize all the signals in Verilog netlists");
-  /* Add an option '--support_icarus_simulator' */
-  shell_cmd_write_fabric_verilog.add_option("support_icarus_simulator", false, "Fine-tune Verilog netlists to support icarus simulator");
-  /* Add an option '--print_user_defined_template' */
-  shell_cmd_write_fabric_verilog.add_option("print_user_defined_template", false, "Generate a template Verilog files for user-defined circuit models");
-  /* Add an option '--print_top_testbench' */
-  shell_cmd_write_fabric_verilog.add_option("print_top_testbench", false, "Generate a testbench for top-level fabric module");
-  /* Add an option '--print_formal_verification_top_netlist' */
-  shell_cmd_write_fabric_verilog.add_option("print_formal_verification_top_netlist", false, "Generate a top-level module which can be used in formal verification");
-  /* Add an option '--print_autocheck_top_testbench' */
-  CommandOptionId fabric_verilog_autocheck_tb_opt = shell_cmd_write_fabric_verilog.add_option("print_autocheck_top_testbench", false, "Generate a testbench for top-level fabric module with autocheck capability");
-  shell_cmd_write_fabric_verilog.set_option_require_value(fabric_verilog_autocheck_tb_opt, openfpga::OPT_STRING);
-  /* Add an option '--verbose' */
-  shell_cmd_write_fabric_verilog.add_option("verbose", false, "Enable verbose output");
-  
-  /* Add command 'write_fabric_verilog' to the Shell */
-  ShellCommandId shell_cmd_write_fabric_verilog_id = shell.add_command(shell_cmd_write_fabric_verilog, "generate Verilog netlists modeling full FPGA fabric");
-  shell.set_command_class(shell_cmd_write_fabric_verilog_id, openfpga_verilog_cmd_class);
-  shell.set_command_execute_function(shell_cmd_write_fabric_verilog_id, write_fabric_verilog);
+  add_openfpga_write_fabric_verilog_command(shell,
+                                            openfpga_verilog_cmd_class,
+                                            shell_cmd_build_fabric_id);
 
-  /* The 'build_fabric' command should NOT be executed before 'link_openfpga_arch' */
-  std::vector<ShellCommandId> cmd_dependency_write_fabric_verilog;
-  cmd_dependency_write_fabric_verilog.push_back(shell_cmd_build_fabric_id);
-  shell.set_command_dependency(shell_cmd_write_fabric_verilog_id, cmd_dependency_write_fabric_verilog);
+  /******************************** 
+   * Command 'write_verilog_testbench' 
+   */
+  add_openfpga_write_verilog_testbench_command(shell,
+                                               openfpga_verilog_cmd_class,
+                                               shell_cmd_build_fabric_id);
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/fpga_verilog/verilog_options.cpp b/openfpga/src/fpga_verilog/fabric_verilog_options.cpp
similarity index 75%
rename from openfpga/src/fpga_verilog/verilog_options.cpp
rename to openfpga/src/fpga_verilog/fabric_verilog_options.cpp
index b3b398dd7..ba843ef20 100644
--- a/openfpga/src/fpga_verilog/verilog_options.cpp
+++ b/openfpga/src/fpga_verilog/fabric_verilog_options.cpp
@@ -3,7 +3,7 @@
  ******************************************************************************/
 #include "vtr_assert.h"
 
-#include "verilog_options.h"
+#include "fabric_verilog_options.h"
 
 /* begin namespace openfpga */
 namespace openfpga {
@@ -52,22 +52,6 @@ bool FabricVerilogOption::compress_routing() const {
   return compress_routing_;
 }
 
-bool FabricVerilogOption::print_top_testbench() const {
-  return print_top_testbench_;
-}
-
-bool FabricVerilogOption::print_formal_verification_top_netlist() const {
-  return print_formal_verification_top_netlist_;
-}
-
-bool FabricVerilogOption::print_autocheck_top_testbench() const {
-  return false == reference_verilog_file_path_.empty();
-}
-
-std::string FabricVerilogOption::reference_verilog_file_path() const {
-  return reference_verilog_file_path_;
-}
-
 bool FabricVerilogOption::print_user_defined_template() const {
   return print_user_defined_template_;
 }
@@ -103,18 +87,6 @@ void FabricVerilogOption::set_compress_routing(const bool& enabled) {
   compress_routing_ = enabled;
 }
 
-void FabricVerilogOption::set_print_top_testbench(const bool& enabled) {
-  print_top_testbench_ = enabled;
-}
-
-void FabricVerilogOption::set_print_formal_verification_top_netlist(const bool& enabled) {
-  print_formal_verification_top_netlist_ = enabled;
-}
-
-void FabricVerilogOption::set_print_autocheck_top_testbench(const std::string& reference_verilog_file_path) {
-  reference_verilog_file_path_ = reference_verilog_file_path;
-}
-
 void FabricVerilogOption::set_print_user_defined_template(const bool& enabled) {
   print_user_defined_template_ = enabled;
 }
diff --git a/openfpga/src/fpga_verilog/verilog_options.h b/openfpga/src/fpga_verilog/fabric_verilog_options.h
similarity index 89%
rename from openfpga/src/fpga_verilog/verilog_options.h
rename to openfpga/src/fpga_verilog/fabric_verilog_options.h
index 48e32086b..38ef05f9a 100644
--- a/openfpga/src/fpga_verilog/verilog_options.h
+++ b/openfpga/src/fpga_verilog/fabric_verilog_options.h
@@ -1,5 +1,5 @@
-#ifndef VERILOG_OPTIONS_H
-#define VERILOG_OPTIONS_H
+#ifndef FABRIC_VERILOG_OPTIONS_H
+#define FABRIC_VERILOG_OPTIONS_H
 
 /********************************************************************
  * Include header files required by the data structure definition
@@ -10,11 +10,7 @@
 namespace openfpga {
 
 /********************************************************************
- * FlowManager aims to resolve the dependency between OpenFPGA functional
- * code blocks
- * It can provide flags for downstream modules about if the data structures
- * they require have already been constructed
- *
+ * Options for Fabric Verilog generator
  *******************************************************************/
 class FabricVerilogOption {
   public: /* Public constructor */
diff --git a/openfpga/src/fpga_verilog/verilog_api.cpp b/openfpga/src/fpga_verilog/verilog_api.cpp
index 645033d65..527ec5a56 100644
--- a/openfpga/src/fpga_verilog/verilog_api.cpp
+++ b/openfpga/src/fpga_verilog/verilog_api.cpp
@@ -20,6 +20,10 @@
 #include "verilog_grid.h"
 #include "verilog_top_module.h"
 
+#include "verilog_preconfig_top_module.h"
+#include "verilog_formal_random_top_testbench.h"
+#include "verilog_top_testbench.h"
+
 /* Header file for this source file */
 #include "verilog_api.h"
 
@@ -27,17 +31,18 @@
 namespace openfpga {
 
 /********************************************************************
- * Top-level function of FPGA-Verilog
+ * A top-level function of FPGA-Verilog which focuses on fabric Verilog generation
  * This function will generate
- * 1. primitive modules required by the full fabric
- *    which are LUTs, routing multiplexer, logic gates, transmission-gates etc.
- * 2. Routing modules, which are Switch Blocks (SBs) and Connection Blocks (CBs)
- * 3. Logic block modules, which are Configuration Logic Blocks (CLBs)
- * 4. FPGA module, which are the full FPGA fabric with configuration protocol
- * 5. A wrapper module, which encapsulate the FPGA module in a Verilog module which have the same port as the input benchmark 
- * 6. Testbench, where a FPGA module is configured with a bitstream and then driven by input vectors
- * 7. Pre-configured testbench, which can skip the configuration phase and pre-configure the FPGA module. This testbench is created for quick verification and formal verification purpose.
- * 8. Verilog netlist including preprocessing flags and all the Verilog netlists that have been generated
+ *  - primitive modules required by the full fabric
+ *  - which are LUTs, routing multiplexer, logic gates, transmission-gates etc.
+ *  - Routing modules, which are Switch Blocks (SBs) and Connection Blocks (CBs)
+ *  - Logic block modules, which are Configuration Logic Blocks (CLBs)
+ *  - FPGA module, which are the full FPGA fabric with configuration protocol
+ *
+ * Note: 
+ *  - Please do NOT include ANY testbench generation in this function!!!
+ *    It is about the fabric itself, independent from any implementation
+ *    All the testbench generation should be in the function fpga_testbench_verilog()
  *
  * TODO: We should use module manager as a constant here. 
  * All the modification should be done before this writer!
@@ -75,9 +80,6 @@ void fpga_fabric_verilog(ModuleManager& module_manager,
   print_verilog_preprocessing_flags_netlist(std::string(src_dir_path),
                                             options);
 
-  print_verilog_simulation_preprocessing_flags(std::string(src_dir_path),
-                                               options);
-
   /* Generate primitive Verilog modules, which are corner stones of FPGA fabric
    * Note that this function MUST be called before Verilog generation of
    * core logic (i.e., logic blocks and routing resources) !!!
@@ -121,4 +123,106 @@ void fpga_fabric_verilog(ModuleManager& module_manager,
            module_manager.num_modules());  
 }
 
+
+/********************************************************************
+ * A top-level function of FPGA-Verilog which focuses on fabric Verilog generation
+ * This function will generate
+ *  - A wrapper module, which encapsulate the FPGA module in a Verilog module which have the same port as the input benchmark 
+ *  - Testbench, where a FPGA module is configured with a bitstream and then driven by input vectors
+ *  - Pre-configured testbench, which can skip the configuration phase and pre-configure the FPGA module.
+ *    This testbench is created for quick verification and formal verification purpose.
+ *  - Verilog netlist including preprocessing flags and all the Verilog netlists that have been generated
+ ********************************************************************/
+void fpga_verilog_testbench(const ModuleManager& module_manager,
+                            const BitstreamManager& bitstream_manager, 
+                            const std::vector<ConfigBitId>& fabric_bitstream, 
+                            const AtomContext& atom_ctx, 
+                            const PlacementContext& place_ctx, 
+                            const IoLocationMap& io_location_map,
+                            const CircuitLibrary& circuit_lib,
+                            const SimulationSetting& simulation_setting,
+                            const e_config_protocol_type& config_protocol_type,
+                            const VerilogTestbenchOption& options) {
+
+  vtr::ScopedStartFinishTimer timer("Write Verilog testbenches for FPGA fabric\n");
+
+  std::string src_dir_path = format_dir_path(options.output_directory());
+
+  std::string netlist_name = atom_ctx.nlist.netlist_name();
+
+  /* Create directories */
+  create_dir_path(src_dir_path.c_str());
+
+  /* TODO: check if this works here. This function was in fabric generator */
+  print_verilog_simulation_preprocessing_flags(std::string(src_dir_path),
+                                               options);
+
+  /* Collect global ports from the circuit library:
+   * TODO: should we place this in the OpenFPGA context?
+   */
+  std::vector<CircuitPortId> global_ports = find_circuit_library_global_ports(circuit_lib);
+
+  /* Generate wrapper module for FPGA fabric (mapped by the input benchmark and pre-configured testbench for verification */
+  if (true == options.print_formal_verification_top_netlist()) {
+    std::string formal_verification_top_netlist_file_path = src_dir_path + netlist_name 
+                                                          + std::string(FORMAL_VERIFICATION_VERILOG_FILE_POSTFIX);
+    print_verilog_preconfig_top_module(module_manager, bitstream_manager,
+                                       circuit_lib, global_ports,
+                                       atom_ctx, place_ctx, io_location_map,
+                                       netlist_name,
+                                       formal_verification_top_netlist_file_path,
+                                       src_dir_path);
+  }
+
+  if (true == options.print_preconfig_top_testbench()) {
+    /* Generate top-level testbench using random vectors */
+    std::string random_top_testbench_file_path = src_dir_path + netlist_name 
+                                               + std::string(RANDOM_TOP_TESTBENCH_VERILOG_FILE_POSTFIX);
+    print_verilog_random_top_testbench(netlist_name,
+                                       random_top_testbench_file_path, 
+                                       src_dir_path,
+                                       atom_ctx,  
+                                       simulation_setting);
+  }
+
+  /* Generate full testbench for verification, including configuration phase and operating phase */
+  if (true == options.print_top_testbench()) {
+    std::string top_testbench_file_path = src_dir_path + netlist_name
+                                        + std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_FILE_POSTFIX);
+    print_verilog_top_testbench(module_manager,
+                                bitstream_manager, fabric_bitstream,
+                                config_protocol_type,
+                                circuit_lib, global_ports,
+                                atom_ctx, place_ctx, io_location_map,
+                                netlist_name,
+                                top_testbench_file_path,
+                                src_dir_path,
+                                simulation_setting);
+  }
+ 
+  /* TODO: Generate exchangeable files which contains simulation settings 
+  if (true == options.print_simulation_ini()) {
+    std::string simulation_ini_file_name;
+    if (true != options.simulation_ini_path()) {
+      simulation_ini_file_name = options.simulation_ini_path();
+    }
+    print_verilog_simulation_info(simulation_ini_file_name,
+                                  format_dir_path(chomped_parent_dir),
+                                  netlist_name,
+                                  src_dir_path,
+                                  bitstream_manager.bits().size(),
+                                  simulation_setting.num_clock_cycle(),
+                                  simulation_setting.programming_clock_frequency(),
+                                  simulation_setting.operating_clock_frequency());
+  }
+  */
+
+  /* Generate a Verilog file including all the netlists that have been generated */
+  print_include_netlists(src_dir_path,
+                         netlist_name,
+                         options.reference_verilog_file_path(),
+                         circuit_lib);
+
+}
+
 } /* end namespace openfpga */
diff --git a/openfpga/src/fpga_verilog/verilog_api.h b/openfpga/src/fpga_verilog/verilog_api.h
index 7494a5a8f..587987425 100644
--- a/openfpga/src/fpga_verilog/verilog_api.h
+++ b/openfpga/src/fpga_verilog/verilog_api.h
@@ -7,14 +7,17 @@
 
 #include <string>
 #include <vector>
-#include "vpr_types.h"
 #include "mux_library.h"
 #include "circuit_library.h"
 #include "vpr_context.h"
 #include "vpr_device_annotation.h"
 #include "device_rr_gsb.h"
 #include "module_manager.h"
-#include "verilog_options.h"
+#include "bitstream_manager.h"
+#include "simulation_setting.h"
+#include "io_location_map.h"
+#include "fabric_verilog_options.h"
+#include "verilog_testbench_options.h"
 
 /********************************************************************
  * Function declaration
@@ -31,6 +34,18 @@ void fpga_fabric_verilog(ModuleManager& module_manager,
                          const DeviceRRGSB& device_rr_gsb,
                          const FabricVerilogOption& options);
 
+void fpga_verilog_testbench(const ModuleManager& module_manager,
+                            const BitstreamManager& bitstream_manager, 
+                            const std::vector<ConfigBitId>& fabric_bitstream, 
+                            const AtomContext& atom_ctx, 
+                            const PlacementContext& place_ctx, 
+                            const IoLocationMap& io_location_map,
+                            const CircuitLibrary& circuit_lib,
+                            const SimulationSetting& simulation_parameters,
+                            const e_config_protocol_type& config_protocol_type,
+                            const VerilogTestbenchOption& options);
+
+
 } /* end namespace openfpga */
 
 #endif
diff --git a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
index f1a12798d..20552c29f 100644
--- a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
+++ b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
@@ -115,7 +115,7 @@ void print_include_netlists(const std::string& src_dir,
  * which are used enable/disable some features in FPGA Verilog modules
  *******************************************************************/
 void print_verilog_preprocessing_flags_netlist(const std::string& src_dir,
-                                               const FabricVerilogOption& fpga_verilog_opts) {
+                                               const FabricVerilogOption& fabric_verilog_opts) {
 
   std::string verilog_fname = src_dir + std::string(DEFINES_VERILOG_FILE_NAME);
 
@@ -130,25 +130,19 @@ void print_verilog_preprocessing_flags_netlist(const std::string& src_dir,
   print_verilog_file_header(fp, std::string("Preprocessing flags to enable/disable features in FPGA Verilog modules")); 
 
   /* To enable timing */
-  if (true == fpga_verilog_opts.include_timing()) {
+  if (true == fabric_verilog_opts.include_timing()) {
     print_verilog_define_flag(fp, std::string(VERILOG_TIMING_PREPROC_FLAG), 1);
     fp << std::endl;
   } 
 
   /* To enable timing */
-  if (true == fpga_verilog_opts.include_signal_init()) {
+  if (true == fabric_verilog_opts.include_signal_init()) {
     print_verilog_define_flag(fp, std::string(VERILOG_SIGNAL_INIT_PREPROC_FLAG), 1);
     fp << std::endl;
   } 
 
-  /* To enable formal verfication flag */
-  if (true == fpga_verilog_opts.print_formal_verification_top_netlist()) {
-    print_verilog_define_flag(fp, std::string(VERILOG_FORMAL_VERIFICATION_PREPROC_FLAG), 1);
-    fp << std::endl;
-  } 
-
   /* To enable functional verfication with Icarus */
-  if (true == fpga_verilog_opts.support_icarus_simulator()) {
+  if (true == fabric_verilog_opts.support_icarus_simulator()) {
     print_verilog_define_flag(fp, std::string(ICARUS_SIMULATOR_FLAG), 1);
     fp << std::endl;
   } 
@@ -161,7 +155,7 @@ void print_verilog_preprocessing_flags_netlist(const std::string& src_dir,
  * Print a Verilog file containing simulation-related preprocessing flags
  *******************************************************************/
 void print_verilog_simulation_preprocessing_flags(const std::string& src_dir,
-                                                  const FabricVerilogOption& fpga_verilog_opts) {
+                                                  const VerilogTestbenchOption& verilog_testbench_opts) {
 
   std::string verilog_fname = src_dir + std::string(DEFINES_VERILOG_SIMULATION_FILE_NAME);
 
@@ -176,19 +170,20 @@ void print_verilog_simulation_preprocessing_flags(const std::string& src_dir,
   print_verilog_file_header(fp, std::string("Preprocessing flags to enable/disable simulation features")); 
 
   /* To enable manualy checked simulation */
-  if (true == fpga_verilog_opts.print_top_testbench()) {
+  if (true == verilog_testbench_opts.print_top_testbench()) {
     print_verilog_define_flag(fp, std::string(INITIAL_SIMULATION_FLAG), 1);
     fp << std::endl;
   } 
 
   /* To enable auto-checked simulation */
-  if (true == fpga_verilog_opts.print_autocheck_top_testbench()) {
+  if ( (true == verilog_testbench_opts.print_preconfig_top_testbench())
+    || (true == verilog_testbench_opts.print_top_testbench()) ) {
     print_verilog_define_flag(fp, std::string(AUTOCHECKED_SIMULATION_FLAG), 1);
     fp << std::endl;
   } 
 
   /* To enable pre-configured FPGA simulation */
-  if (true == fpga_verilog_opts.print_formal_verification_top_netlist()) {
+  if (true == verilog_testbench_opts.print_formal_verification_top_netlist()) {
     print_verilog_define_flag(fp, std::string(FORMAL_SIMULATION_FLAG), 1);
     fp << std::endl;
   } 
diff --git a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h
index 42f3b0042..291ca8915 100644
--- a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h
+++ b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h
@@ -6,7 +6,8 @@
  *******************************************************************/
 #include <string>
 #include "circuit_library.h"
-#include "verilog_options.h"
+#include "fabric_verilog_options.h"
+#include "verilog_testbench_options.h"
 
 /********************************************************************
  * Function declaration
@@ -21,10 +22,10 @@ void print_include_netlists(const std::string& src_dir,
                             const CircuitLibrary& circuit_lib);
 
 void print_verilog_preprocessing_flags_netlist(const std::string& src_dir,
-                                               const FabricVerilogOption& fpga_verilog_opts);
+                                               const FabricVerilogOption& fabric_verilog_opts);
 
 void print_verilog_simulation_preprocessing_flags(const std::string& src_dir,
-                                                  const FabricVerilogOption& fpga_verilog_opts);
+                                                  const VerilogTestbenchOption& verilog_testbench_opts);
 
 } /* end namespace openfpga */
 
diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.h b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.h
index 0c8e54708..59f777a6c 100644
--- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.h
+++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.h
@@ -6,10 +6,11 @@
  *******************************************************************/
 #include <vector>
 #include <string>
-#include "circuit_types.h" 
-#include "vpr_types.h" 
+#include "circuit_library.h" 
+#include "vpr_context.h" 
 #include "module_manager.h" 
 #include "bitstream_manager.h" 
+#include "io_location_map.h" 
 
 /********************************************************************
  * Function declaration
diff --git a/openfpga/src/fpga_verilog/verilog_submodule.h b/openfpga/src/fpga_verilog/verilog_submodule.h
index 4f7cb511c..88e1ce965 100644
--- a/openfpga/src/fpga_verilog/verilog_submodule.h
+++ b/openfpga/src/fpga_verilog/verilog_submodule.h
@@ -6,7 +6,7 @@
  *******************************************************************/
 #include "module_manager.h"
 #include "mux_library.h"
-#include "verilog_options.h"
+#include "fabric_verilog_options.h"
 
 /********************************************************************
  * Function declaration
diff --git a/openfpga/src/fpga_verilog/verilog_testbench_options.cpp b/openfpga/src/fpga_verilog/verilog_testbench_options.cpp
new file mode 100644
index 000000000..f1ef64daa
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_testbench_options.cpp
@@ -0,0 +1,97 @@
+/******************************************************************************
+ * Memember functions for data structure VerilogTestbenchOption
+ ******************************************************************************/
+#include "vtr_assert.h"
+
+#include "verilog_testbench_options.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/**************************************************
+ * Public Constructors
+ *************************************************/
+VerilogTestbenchOption::VerilogTestbenchOption() {
+  output_directory_.clear();
+  reference_verilog_file_path_.clear();
+  print_preconfig_top_testbench_ = false;
+  print_formal_verification_top_netlist_ = false;
+  print_top_testbench_ = false;
+  simulation_ini_path_.clear();
+  verbose_output_ = false;
+}
+
+/**************************************************
+ * Public Accessors 
+ *************************************************/
+std::string VerilogTestbenchOption::output_directory() const {
+  return output_directory_;
+}
+
+std::string VerilogTestbenchOption::reference_verilog_file_path() const {
+  return reference_verilog_file_path_;
+}
+
+bool VerilogTestbenchOption::print_formal_verification_top_netlist() const {
+  return print_formal_verification_top_netlist_;
+}
+
+bool VerilogTestbenchOption::print_preconfig_top_testbench() const {
+  return print_preconfig_top_testbench_;
+}
+
+bool VerilogTestbenchOption::print_top_testbench() const {
+  return print_top_testbench_;
+}
+
+bool VerilogTestbenchOption::print_simulation_ini() const {
+  return !simulation_ini_path_.empty();
+}
+
+std::string VerilogTestbenchOption::simulation_ini_path() const {
+  return simulation_ini_path_;
+}
+
+bool VerilogTestbenchOption::verbose_output() const {
+  return verbose_output_;
+}
+
+/******************************************************************************
+ * Private Mutators
+ ******************************************************************************/
+void VerilogTestbenchOption::set_output_directory(const std::string& output_dir) {
+  output_directory_ = output_dir;
+}
+
+void VerilogTestbenchOption::set_reference_verilog_file_path(const std::string& reference_verilog_file_path) {
+  reference_verilog_file_path_ = reference_verilog_file_path;
+  /* Chain effect on other options: 
+   * Enable/disable the print_preconfig_top_testbench and print_top_testbench
+   */
+  set_print_preconfig_top_testbench(print_preconfig_top_testbench_); 
+  set_print_top_testbench(print_top_testbench_); 
+}
+ 
+void VerilogTestbenchOption::set_print_formal_verification_top_netlist(const bool& enabled) {
+  print_formal_verification_top_netlist_ = enabled;
+}
+
+void VerilogTestbenchOption::set_print_preconfig_top_testbench(const bool& enabled) {
+  print_preconfig_top_testbench_ = enabled
+                                 && print_formal_verification_top_netlist_
+                                 && (!reference_verilog_file_path_.empty());
+}
+
+void VerilogTestbenchOption::set_print_top_testbench(const bool& enabled) {
+  print_top_testbench_ = enabled && (!reference_verilog_file_path_.empty());
+}
+
+void VerilogTestbenchOption::set_print_simulation_ini(const std::string& simulation_ini_path) {
+  simulation_ini_path_ = simulation_ini_path;
+}
+
+void VerilogTestbenchOption::set_verbose_output(const bool& enabled) {
+  verbose_output_ = enabled;
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_verilog/verilog_testbench_options.h b/openfpga/src/fpga_verilog/verilog_testbench_options.h
new file mode 100644
index 000000000..d393b11c8
--- /dev/null
+++ b/openfpga/src/fpga_verilog/verilog_testbench_options.h
@@ -0,0 +1,62 @@
+#ifndef VERILOG_TESTBENCH_OPTIONS_H
+#define VERILOG_TESTBENCH_OPTIONS_H
+
+/********************************************************************
+ * Include header files required by the data structure definition
+ *******************************************************************/
+#include <string>
+
+/* Begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Options for Verilog Testbench generator
+ * Typicall usage:
+ *   VerilogTestbench verilog_tb_opt();
+ *   // Set options
+ *   ...
+ *
+ *******************************************************************/
+class VerilogTestbenchOption {
+  public: /* Public constructor */
+    /* Set default options */
+    VerilogTestbenchOption();
+  public: /* Public accessors */
+    std::string output_directory() const;
+    std::string reference_verilog_file_path() const;
+    bool print_formal_verification_top_netlist() const;
+    bool print_preconfig_top_testbench() const;
+    bool print_top_testbench() const;
+    bool print_simulation_ini() const;
+    std::string simulation_ini_path() const;
+    bool verbose_output() const;
+  public: /* Public validator */
+    bool validate() const;
+  public: /* Public mutators */
+    void set_output_directory(const std::string& output_dir);
+    /* The reference verilog file path is the key parameters that will have an impact on other options:
+     *  - print_preconfig_top_testbench
+     *  - print_top_testbench
+     * If the file path is empty, the above testbench generation will not be enabled 
+     */
+    void set_reference_verilog_file_path(const std::string& reference_verilog_file_path);
+    void set_print_formal_verification_top_netlist(const bool& enabled);
+    /* The preconfig top testbench generation can be enabled only when formal verification top netlist is enabled */
+    void set_print_preconfig_top_testbench(const bool& enabled);
+    void set_print_top_testbench(const bool& enabled);
+    void set_print_simulation_ini(const std::string& simulation_ini_path);
+    void set_verbose_output(const bool& enabled);
+  private: /* Internal Data */
+    std::string output_directory_;
+    std::string reference_verilog_file_path_;
+    bool print_formal_verification_top_netlist_;
+    bool print_preconfig_top_testbench_;
+    bool print_top_testbench_;
+    /* Print simulation ini is enabled only when the path is not empty */
+    std::string simulation_ini_path_;
+    bool verbose_output_;
+};
+
+} /* End namespace openfpga*/
+
+#endif

From 078f72320fb7979243d5c8eea895afa7a0908b07 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 27 Feb 2020 13:24:26 -0700
Subject: [PATCH 219/645] debugging Verilog testbench generator. Bug spotted in
 using renamed atom_block and clock ports

---
 openfpga/src/base/openfpga_verilog.cpp        |  4 ++--
 .../src/base/openfpga_verilog_command.cpp     |  7 +++----
 openfpga/src/fpga_verilog/verilog_api.cpp     |  2 +-
 .../verilog_testbench_options.cpp             | 19 +++++++++++--------
 .../fpga_verilog/verilog_testbench_options.h  |  6 +++---
 openfpga/test_script/s298_k6_frac.openfpga    |  5 ++++-
 6 files changed, 24 insertions(+), 19 deletions(-)

diff --git a/openfpga/src/base/openfpga_verilog.cpp b/openfpga/src/base/openfpga_verilog.cpp
index 2a6c88241..41057ad34 100644
--- a/openfpga/src/base/openfpga_verilog.cpp
+++ b/openfpga/src/base/openfpga_verilog.cpp
@@ -57,7 +57,7 @@ void write_verilog_testbench(OpenfpgaContext& openfpga_ctx,
                              const Command& cmd, const CommandContext& cmd_context) {
 
   CommandOptionId opt_output_dir = cmd.option("file");
-  CommandOptionId opt_reference_benchmark = cmd.option("reference_verilog_file_path");
+  CommandOptionId opt_reference_benchmark = cmd.option("reference_benchmark_file_path");
   CommandOptionId opt_print_top_testbench = cmd.option("print_top_testbench");
   CommandOptionId opt_print_formal_verification_top_netlist = cmd.option("print_formal_verification_top_netlist");
   CommandOptionId opt_print_preconfig_top_testbench = cmd.option("print_preconfig_top_testbench");
@@ -69,7 +69,7 @@ void write_verilog_testbench(OpenfpgaContext& openfpga_ctx,
    */
   VerilogTestbenchOption options;
   options.set_output_directory(cmd_context.option_value(cmd, opt_output_dir));
-  options.set_reference_verilog_file_path(cmd_context.option_value(cmd, opt_reference_benchmark));
+  options.set_reference_benchmark_file_path(cmd_context.option_value(cmd, opt_reference_benchmark));
   options.set_print_formal_verification_top_netlist(cmd_context.option_enable(cmd, opt_print_formal_verification_top_netlist));
   options.set_print_preconfig_top_testbench(cmd_context.option_enable(cmd, opt_print_preconfig_top_testbench));
   options.set_print_top_testbench(cmd_context.option_enable(cmd, opt_print_top_testbench));
diff --git a/openfpga/src/base/openfpga_verilog_command.cpp b/openfpga/src/base/openfpga_verilog_command.cpp
index 29c0ee73a..3d4f7784b 100644
--- a/openfpga/src/base/openfpga_verilog_command.cpp
+++ b/openfpga/src/base/openfpga_verilog_command.cpp
@@ -48,7 +48,7 @@ void add_openfpga_write_fabric_verilog_command(openfpga::Shell<OpenfpgaContext>&
   /* Add command 'write_fabric_verilog' to the Shell */
   ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "generate Verilog netlists modeling full FPGA fabric");
   shell.set_command_class(shell_cmd_id, cmd_class_id);
-  shell.set_command_execute_function(shell_cmd_id, write_verilog_testbench);
+  shell.set_command_execute_function(shell_cmd_id, write_fabric_verilog);
 
   /* The 'build_fabric' command should NOT be executed before 'link_openfpga_arch' */
   std::vector<ShellCommandId> cmd_dependency;
@@ -83,8 +83,7 @@ void add_openfpga_write_verilog_testbench_command(openfpga::Shell<OpenfpgaContex
   shell_cmd.add_option("print_formal_verification_top_netlist", false, "Generate a top-level module which can be used in formal verification");
 
   /* Add an option '--print_preconfig_top_testbench' */
-  CommandOptionId preconfig_tb_opt = shell_cmd.add_option("print_preconfig_top_testbench", false, "Generate a pre-configured testbench for top-level fabric module with autocheck capability");
-  shell_cmd.set_option_require_value(preconfig_tb_opt, openfpga::OPT_STRING);
+  shell_cmd.add_option("print_preconfig_top_testbench", false, "Generate a pre-configured testbench for top-level fabric module with autocheck capability");
 
   /* Add an option '--print_simulation_ini' */
   CommandOptionId sim_ini_opt = shell_cmd.add_option("print_simulation_ini", false, "Generate a .ini file as an exchangeable file to enable HDL simulations");
@@ -96,7 +95,7 @@ void add_openfpga_write_verilog_testbench_command(openfpga::Shell<OpenfpgaContex
   /* Add command to the Shell */
   ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "generate Verilog testbenches for full FPGA fabric");
   shell.set_command_class(shell_cmd_id, cmd_class_id);
-  shell.set_command_execute_function(shell_cmd_id, write_fabric_verilog);
+  shell.set_command_execute_function(shell_cmd_id, write_verilog_testbench);
 
   /* The command should NOT be executed before 'build_fabric' */
   std::vector<ShellCommandId> cmd_dependency;
diff --git a/openfpga/src/fpga_verilog/verilog_api.cpp b/openfpga/src/fpga_verilog/verilog_api.cpp
index 527ec5a56..ed4b28982 100644
--- a/openfpga/src/fpga_verilog/verilog_api.cpp
+++ b/openfpga/src/fpga_verilog/verilog_api.cpp
@@ -220,7 +220,7 @@ void fpga_verilog_testbench(const ModuleManager& module_manager,
   /* Generate a Verilog file including all the netlists that have been generated */
   print_include_netlists(src_dir_path,
                          netlist_name,
-                         options.reference_verilog_file_path(),
+                         options.reference_benchmark_file_path(),
                          circuit_lib);
 
 }
diff --git a/openfpga/src/fpga_verilog/verilog_testbench_options.cpp b/openfpga/src/fpga_verilog/verilog_testbench_options.cpp
index f1ef64daa..0214fe6e5 100644
--- a/openfpga/src/fpga_verilog/verilog_testbench_options.cpp
+++ b/openfpga/src/fpga_verilog/verilog_testbench_options.cpp
@@ -13,7 +13,7 @@ namespace openfpga {
  *************************************************/
 VerilogTestbenchOption::VerilogTestbenchOption() {
   output_directory_.clear();
-  reference_verilog_file_path_.clear();
+  reference_benchmark_file_path_.clear();
   print_preconfig_top_testbench_ = false;
   print_formal_verification_top_netlist_ = false;
   print_top_testbench_ = false;
@@ -28,8 +28,8 @@ std::string VerilogTestbenchOption::output_directory() const {
   return output_directory_;
 }
 
-std::string VerilogTestbenchOption::reference_verilog_file_path() const {
-  return reference_verilog_file_path_;
+std::string VerilogTestbenchOption::reference_benchmark_file_path() const {
+  return reference_benchmark_file_path_;
 }
 
 bool VerilogTestbenchOption::print_formal_verification_top_netlist() const {
@@ -63,8 +63,8 @@ void VerilogTestbenchOption::set_output_directory(const std::string& output_dir)
   output_directory_ = output_dir;
 }
 
-void VerilogTestbenchOption::set_reference_verilog_file_path(const std::string& reference_verilog_file_path) {
-  reference_verilog_file_path_ = reference_verilog_file_path;
+void VerilogTestbenchOption::set_reference_benchmark_file_path(const std::string& reference_benchmark_file_path) {
+  reference_benchmark_file_path_ = reference_benchmark_file_path;
   /* Chain effect on other options: 
    * Enable/disable the print_preconfig_top_testbench and print_top_testbench
    */
@@ -78,12 +78,15 @@ void VerilogTestbenchOption::set_print_formal_verification_top_netlist(const boo
 
 void VerilogTestbenchOption::set_print_preconfig_top_testbench(const bool& enabled) {
   print_preconfig_top_testbench_ = enabled
-                                 && print_formal_verification_top_netlist_
-                                 && (!reference_verilog_file_path_.empty());
+                                 && (!reference_benchmark_file_path_.empty());
+  /* Enable print formal verification top_netlist if this is enabled */
+  if (true == print_preconfig_top_testbench_) {
+    print_formal_verification_top_netlist_ = true;
+  }
 }
 
 void VerilogTestbenchOption::set_print_top_testbench(const bool& enabled) {
-  print_top_testbench_ = enabled && (!reference_verilog_file_path_.empty());
+  print_top_testbench_ = enabled && (!reference_benchmark_file_path_.empty());
 }
 
 void VerilogTestbenchOption::set_print_simulation_ini(const std::string& simulation_ini_path) {
diff --git a/openfpga/src/fpga_verilog/verilog_testbench_options.h b/openfpga/src/fpga_verilog/verilog_testbench_options.h
index d393b11c8..d18bfa224 100644
--- a/openfpga/src/fpga_verilog/verilog_testbench_options.h
+++ b/openfpga/src/fpga_verilog/verilog_testbench_options.h
@@ -23,7 +23,7 @@ class VerilogTestbenchOption {
     VerilogTestbenchOption();
   public: /* Public accessors */
     std::string output_directory() const;
-    std::string reference_verilog_file_path() const;
+    std::string reference_benchmark_file_path() const;
     bool print_formal_verification_top_netlist() const;
     bool print_preconfig_top_testbench() const;
     bool print_top_testbench() const;
@@ -39,7 +39,7 @@ class VerilogTestbenchOption {
      *  - print_top_testbench
      * If the file path is empty, the above testbench generation will not be enabled 
      */
-    void set_reference_verilog_file_path(const std::string& reference_verilog_file_path);
+    void set_reference_benchmark_file_path(const std::string& reference_benchmark_file_path);
     void set_print_formal_verification_top_netlist(const bool& enabled);
     /* The preconfig top testbench generation can be enabled only when formal verification top netlist is enabled */
     void set_print_preconfig_top_testbench(const bool& enabled);
@@ -48,7 +48,7 @@ class VerilogTestbenchOption {
     void set_verbose_output(const bool& enabled);
   private: /* Internal Data */
     std::string output_directory_;
-    std::string reference_verilog_file_path_;
+    std::string reference_benchmark_file_path_;
     bool print_formal_verification_top_netlist_;
     bool print_preconfig_top_testbench_;
     bool print_top_testbench_;
diff --git a/openfpga/test_script/s298_k6_frac.openfpga b/openfpga/test_script/s298_k6_frac.openfpga
index 0b2e3cc13..eb09da42e 100644
--- a/openfpga/test_script/s298_k6_frac.openfpga
+++ b/openfpga/test_script/s298_k6_frac.openfpga
@@ -33,9 +33,12 @@ repack #--verbose
 #  - Output the fabric-independent bitstream to a file
 fpga_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
 
-# Write the Verilog netlit for FPGA fabric
+# Write the Verilog netlist for FPGA fabric
 #  - Enable the use of explicit port mapping in Verilog netlist
 write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
 
+# Write the Verilog testbench for FPGA fabric
+write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src --reference_benchmark_file_path /var/tmp/xtang/s298.v --print_top_testbench --print_preconfig_top_testbench
+
 # Finish and exit OpenFPGA
 exit

From b010fc1983c1686ba0885e9b1bcef9ed37389c14 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 27 Feb 2020 13:28:21 -0700
Subject: [PATCH 220/645] add warning to force formal_verification_top_netlist
 enabled

---
 openfpga/src/fpga_verilog/verilog_testbench_options.cpp | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/openfpga/src/fpga_verilog/verilog_testbench_options.cpp b/openfpga/src/fpga_verilog/verilog_testbench_options.cpp
index 0214fe6e5..8cd2969f2 100644
--- a/openfpga/src/fpga_verilog/verilog_testbench_options.cpp
+++ b/openfpga/src/fpga_verilog/verilog_testbench_options.cpp
@@ -2,6 +2,7 @@
  * Memember functions for data structure VerilogTestbenchOption
  ******************************************************************************/
 #include "vtr_assert.h"
+#include "vtr_log.h"
 
 #include "verilog_testbench_options.h"
 
@@ -81,7 +82,10 @@ void VerilogTestbenchOption::set_print_preconfig_top_testbench(const bool& enabl
                                  && (!reference_benchmark_file_path_.empty());
   /* Enable print formal verification top_netlist if this is enabled */
   if (true == print_preconfig_top_testbench_) {
-    print_formal_verification_top_netlist_ = true;
+    if (false == print_formal_verification_top_netlist_) { 
+      VTR_LOG_WARN("Forcely enable to print top-level Verilog netlist in formal verification purpose as print pre-configured top-level Verilog testbench is enabled\n");
+      print_formal_verification_top_netlist_ = true;
+    }
   }
 }
 

From 9b769cd8e4c839aee6f4e67e9a5bd41ca496a8e2 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 27 Feb 2020 16:37:20 -0700
Subject: [PATCH 221/645] bug fix for using renamed i/o names

---
 openfpga/src/base/openfpga_verilog.cpp        |   1 +
 openfpga/src/fpga_verilog/verilog_api.cpp     |   4 +
 openfpga/src/fpga_verilog/verilog_api.h       |   2 +
 .../verilog_formal_random_top_testbench.cpp   |  32 +++--
 .../verilog_formal_random_top_testbench.h     |   1 +
 .../verilog_preconfig_top_module.cpp          |  18 ++-
 .../verilog_preconfig_top_module.h            |   2 +
 .../fpga_verilog/verilog_testbench_utils.cpp  | 118 ++++++++++++++----
 .../fpga_verilog/verilog_testbench_utils.h    |   6 +
 .../fpga_verilog/verilog_top_testbench.cpp    |  23 ++--
 .../src/fpga_verilog/verilog_top_testbench.h  |   2 +
 11 files changed, 163 insertions(+), 46 deletions(-)

diff --git a/openfpga/src/base/openfpga_verilog.cpp b/openfpga/src/base/openfpga_verilog.cpp
index 41057ad34..1ce23a1d4 100644
--- a/openfpga/src/base/openfpga_verilog.cpp
+++ b/openfpga/src/base/openfpga_verilog.cpp
@@ -82,6 +82,7 @@ void write_verilog_testbench(OpenfpgaContext& openfpga_ctx,
                          g_vpr_ctx.atom(),
                          g_vpr_ctx.placement(),
                          openfpga_ctx.io_location_map(),
+                         openfpga_ctx.vpr_netlist_annotation(),
                          openfpga_ctx.arch().circuit_lib,
                          openfpga_ctx.arch().sim_setting,
                          openfpga_ctx.arch().config_protocol.type(),
diff --git a/openfpga/src/fpga_verilog/verilog_api.cpp b/openfpga/src/fpga_verilog/verilog_api.cpp
index ed4b28982..286188a75 100644
--- a/openfpga/src/fpga_verilog/verilog_api.cpp
+++ b/openfpga/src/fpga_verilog/verilog_api.cpp
@@ -139,6 +139,7 @@ void fpga_verilog_testbench(const ModuleManager& module_manager,
                             const AtomContext& atom_ctx, 
                             const PlacementContext& place_ctx, 
                             const IoLocationMap& io_location_map,
+                            const VprNetlistAnnotation& netlist_annotation, 
                             const CircuitLibrary& circuit_lib,
                             const SimulationSetting& simulation_setting,
                             const e_config_protocol_type& config_protocol_type,
@@ -169,6 +170,7 @@ void fpga_verilog_testbench(const ModuleManager& module_manager,
     print_verilog_preconfig_top_module(module_manager, bitstream_manager,
                                        circuit_lib, global_ports,
                                        atom_ctx, place_ctx, io_location_map,
+                                       netlist_annotation,
                                        netlist_name,
                                        formal_verification_top_netlist_file_path,
                                        src_dir_path);
@@ -182,6 +184,7 @@ void fpga_verilog_testbench(const ModuleManager& module_manager,
                                        random_top_testbench_file_path, 
                                        src_dir_path,
                                        atom_ctx,  
+                                       netlist_annotation,
                                        simulation_setting);
   }
 
@@ -194,6 +197,7 @@ void fpga_verilog_testbench(const ModuleManager& module_manager,
                                 config_protocol_type,
                                 circuit_lib, global_ports,
                                 atom_ctx, place_ctx, io_location_map,
+                                netlist_annotation,
                                 netlist_name,
                                 top_testbench_file_path,
                                 src_dir_path,
diff --git a/openfpga/src/fpga_verilog/verilog_api.h b/openfpga/src/fpga_verilog/verilog_api.h
index 587987425..66eb069ba 100644
--- a/openfpga/src/fpga_verilog/verilog_api.h
+++ b/openfpga/src/fpga_verilog/verilog_api.h
@@ -16,6 +16,7 @@
 #include "bitstream_manager.h"
 #include "simulation_setting.h"
 #include "io_location_map.h"
+#include "vpr_netlist_annotation.h"
 #include "fabric_verilog_options.h"
 #include "verilog_testbench_options.h"
 
@@ -40,6 +41,7 @@ void fpga_verilog_testbench(const ModuleManager& module_manager,
                             const AtomContext& atom_ctx, 
                             const PlacementContext& place_ctx, 
                             const IoLocationMap& io_location_map,
+                            const VprNetlistAnnotation& netlist_annotation, 
                             const CircuitLibrary& circuit_lib,
                             const SimulationSetting& simulation_parameters,
                             const e_config_protocol_type& config_protocol_type,
diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
index 71f7df873..2154a8513 100644
--- a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
@@ -55,7 +55,8 @@ static
 void print_verilog_top_random_testbench_ports(std::fstream& fp,
                                               const std::string& circuit_name,
                                               const std::vector<std::string>& clock_port_names,
-                                              const AtomContext& atom_ctx) {
+                                              const AtomContext& atom_ctx,
+                                              const VprNetlistAnnotation& netlist_annotation) {
   /* Validate the file stream */
   valid_file_stream(fp);
  
@@ -72,7 +73,7 @@ void print_verilog_top_random_testbench_ports(std::fstream& fp,
   /* Add an empty line as splitter */
   fp << std::endl;
 
-  print_verilog_testbench_shared_ports(fp, atom_ctx,
+  print_verilog_testbench_shared_ports(fp, atom_ctx, netlist_annotation,
                                        std::string(BENCHMARK_PORT_POSTFIX),
                                        std::string(FPGA_PORT_POSTFIX),
                                        std::string(CHECKFLAG_PORT_POSTFIX),
@@ -94,7 +95,8 @@ void print_verilog_top_random_testbench_ports(std::fstream& fp,
 static
 void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp, 
                                                            const std::string& reference_verilog_top_name,
-                                                           const AtomContext& atom_ctx) {
+                                                           const AtomContext& atom_ctx,
+                                                           const VprNetlistAnnotation& netlist_annotation) {
   /* Validate the file stream */
   valid_file_stream(fp);
 
@@ -111,7 +113,7 @@ void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp,
                                              std::string(),
                                              std::string(),
                                              std::string(BENCHMARK_PORT_POSTFIX),
-                                             atom_ctx,
+                                             atom_ctx, netlist_annotation,
                                              false);
 
   print_verilog_comment(fp, std::string("----- End reference Benchmark Instanication -------"));
@@ -132,7 +134,8 @@ void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp,
 static
 void print_verilog_random_testbench_fpga_instance(std::fstream& fp,
                                                   const std::string& circuit_name,
-                                                  const AtomContext& atom_ctx) {
+                                                  const AtomContext& atom_ctx,
+                                                  const VprNetlistAnnotation& netlist_annotation) {
   /* Validate the file stream */
   valid_file_stream(fp);
 
@@ -144,7 +147,7 @@ void print_verilog_random_testbench_fpga_instance(std::fstream& fp,
                                              std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX),
                                              std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX),
                                              std::string(FPGA_PORT_POSTFIX),
-                                             atom_ctx,
+                                             atom_ctx, netlist_annotation,
                                              true);
 
   print_verilog_comment(fp, std::string("----- End FPGA Fabric Instanication -------"));
@@ -182,6 +185,7 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
                                         const std::string& verilog_fname,
                                         const std::string& verilog_dir,
                                         const AtomContext& atom_ctx,
+                                        const VprNetlistAnnotation& netlist_annotation,
                                         const SimulationSetting& simulation_parameters) {
   std::string timer_message = std::string("Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by '") + circuit_name.c_str() + std::string("'");
 
@@ -208,13 +212,13 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
   std::vector<std::string> clock_port_names = find_atom_netlist_clock_port_names(atom_ctx.nlist);
 
   /* Start of testbench */
-  print_verilog_top_random_testbench_ports(fp, circuit_name, clock_port_names, atom_ctx);
+  print_verilog_top_random_testbench_ports(fp, circuit_name, clock_port_names, atom_ctx, netlist_annotation);
 
   /* Call defined top-level module */
-  print_verilog_random_testbench_fpga_instance(fp, circuit_name, atom_ctx);
+  print_verilog_random_testbench_fpga_instance(fp, circuit_name, atom_ctx, netlist_annotation);
 
   /* Call defined benchmark */
-  print_verilog_top_random_testbench_benchmark_instance(fp, circuit_name, atom_ctx);
+  print_verilog_top_random_testbench_benchmark_instance(fp, circuit_name, atom_ctx, netlist_annotation);
 
   /* Find clock port to be used */
   BasicPort clock_port = generate_verilog_testbench_clock_port(clock_port_names, std::string(DEFAULT_CLOCK_NAME));
@@ -222,8 +226,10 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
   /* Add stimuli for reset, set, clock and iopad signals */
   print_verilog_testbench_clock_stimuli(fp, simulation_parameters, 
                                         clock_port);
-  print_verilog_testbench_random_stimuli(fp, atom_ctx, 
-                                         std::string(CHECKFLAG_PORT_POSTFIX), clock_port);
+  print_verilog_testbench_random_stimuli(fp, atom_ctx,
+                                         netlist_annotation, 
+                                         std::string(CHECKFLAG_PORT_POSTFIX),
+                                         clock_port);
 
   print_verilog_testbench_check(fp, 
                                 std::string(AUTOCHECKED_SIMULATION_FLAG),
@@ -233,7 +239,9 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
                                 std::string(CHECKFLAG_PORT_POSTFIX),
                                 std::string(ERROR_COUNTER),
                                 atom_ctx,
-                                clock_port_names, std::string(DEFAULT_CLOCK_NAME));
+                                netlist_annotation, 
+                                clock_port_names,
+                                std::string(DEFAULT_CLOCK_NAME));
 
   int simulation_time = find_operating_phase_simulation_time(MAGIC_NUMBER_FOR_SIMULATION_TIME,
                                                              simulation_parameters.num_clock_cycles(),
diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.h b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.h
index f73b49fc1..88692ae4f 100644
--- a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.h
+++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.h
@@ -19,6 +19,7 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
                                         const std::string& verilog_fname,
                                         const std::string& verilog_dir,
                                         const AtomContext& atom_ctx,
+                                        const VprNetlistAnnotation& netlist_annotation,
                                         const SimulationSetting& simulation_parameters);
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
index e2bceb75d..000879230 100644
--- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
+++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
@@ -34,7 +34,8 @@ namespace openfpga {
 static 
 void print_verilog_preconfig_top_module_ports(std::fstream& fp, 
                                               const std::string& circuit_name,
-                                              const AtomContext& atom_ctx) {
+                                              const AtomContext& atom_ctx,
+                                              const VprNetlistAnnotation& netlist_annotation) {
 
   /* Validate the file stream */
   valid_file_stream(fp);
@@ -58,11 +59,18 @@ void print_verilog_preconfig_top_module_ports(std::fstream& fp,
       && (AtomBlockType::OUTPAD != atom_ctx.nlist.block_type(atom_blk)) ) {
       continue;
     }
+
+    /* The block may be renamed as it contains special characters which violate Verilog syntax */
+    std::string block_name = atom_ctx.nlist.block_name(atom_blk);
+    if (true == netlist_annotation.is_block_renamed(atom_blk)) {
+      block_name = netlist_annotation.block_name(atom_blk);
+    } 
+
     if (0 < port_counter) { 
       fp << "," << std::endl;
     }
     /* Both input and output ports have only size of 1 */
-    BasicPort module_port(std::string(atom_ctx.nlist.block_name(atom_blk) + std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX)), 1); 
+    BasicPort module_port(std::string(block_name + std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX)), 1); 
     fp << generate_verilog_port(port_type2type_map[atom_ctx.nlist.block_type(atom_blk)], module_port);  
 
     /* Update port counter */
@@ -375,6 +383,7 @@ void print_verilog_preconfig_top_module(const ModuleManager& module_manager,
                                         const AtomContext& atom_ctx,
                                         const PlacementContext& place_ctx,
                                         const IoLocationMap& io_location_map,
+                                        const VprNetlistAnnotation& netlist_annotation, 
                                         const std::string& circuit_name,
                                         const std::string& verilog_fname,
                                         const std::string& verilog_dir) {
@@ -400,7 +409,7 @@ void print_verilog_preconfig_top_module(const ModuleManager& module_manager,
   print_verilog_include_netlist(fp, std::string(verilog_dir + std::string(DEFINES_VERILOG_SIMULATION_FILE_NAME)));  
 
   /* Print module declaration and ports */
-  print_verilog_preconfig_top_module_ports(fp, circuit_name, atom_ctx);
+  print_verilog_preconfig_top_module_ports(fp, circuit_name, atom_ctx, netlist_annotation);
 
   /* Find the top_module */
   ModuleId top_module = module_manager.find_module(generate_fpga_top_module_name());
@@ -423,7 +432,8 @@ void print_verilog_preconfig_top_module(const ModuleManager& module_manager,
 
   /* Connect I/Os to benchmark I/Os or constant driver */
   print_verilog_testbench_connect_fpga_ios(fp, module_manager, top_module,
-                                           atom_ctx, place_ctx, io_location_map, 
+                                           atom_ctx, place_ctx, io_location_map,
+                                           netlist_annotation, 
                                            std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX), 
                                            std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX), 
                                            (size_t)VERILOG_DEFAULT_SIGNAL_INIT_VALUE);
diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.h b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.h
index 59f777a6c..499cafea9 100644
--- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.h
+++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.h
@@ -11,6 +11,7 @@
 #include "module_manager.h" 
 #include "bitstream_manager.h" 
 #include "io_location_map.h" 
+#include "vpr_netlist_annotation.h" 
 
 /********************************************************************
  * Function declaration
@@ -26,6 +27,7 @@ void print_verilog_preconfig_top_module(const ModuleManager& module_manager,
                                         const AtomContext& atom_ctx,
                                         const PlacementContext& place_ctx,
                                         const IoLocationMap& io_location_map,
+                                        const VprNetlistAnnotation& netlist_annotation, 
                                         const std::string& circuit_name,
                                         const std::string& verilog_fname,
                                         const std::string& verilog_dir);
diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
index e73fe5ee4..395d80493 100644
--- a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
+++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
@@ -58,6 +58,7 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp,
                                                 const std::string& module_output_port_postfix,
                                                 const std::string& output_port_postfix,
                                                 const AtomContext& atom_ctx,
+                                                const VprNetlistAnnotation& netlist_annotation,
                                                 const bool& use_explicit_port_map) {
   /* Validate the file stream */
   valid_file_stream(fp);
@@ -71,6 +72,13 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp,
       && (AtomBlockType::OUTPAD != atom_ctx.nlist.block_type(atom_blk)) ) {
       continue;
     }
+
+    /* The block may be renamed as it contains special characters which violate Verilog syntax */
+    std::string block_name = atom_ctx.nlist.block_name(atom_blk);
+    if (true == netlist_annotation.is_block_renamed(atom_blk)) {
+      block_name = netlist_annotation.block_name(atom_blk);
+    } 
+
     /* The first port does not need a comma */
     if(0 < port_counter){
       fp << "," << std::endl;
@@ -79,9 +87,9 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp,
     if (AtomBlockType::INPAD == atom_ctx.nlist.block_type(atom_blk)) {
       fp << "\t\t";
       if (true == use_explicit_port_map) {
-        fp << "." << atom_ctx.nlist.block_name(atom_blk) << module_input_port_postfix << "(";
+        fp << "." << block_name << module_input_port_postfix << "(";
       }
-      fp << atom_ctx.nlist.block_name(atom_blk);
+      fp << block_name;
       if (true == use_explicit_port_map) {
         fp << ")";
       }
@@ -89,9 +97,9 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp,
       VTR_ASSERT_SAFE(AtomBlockType::OUTPAD == atom_ctx.nlist.block_type(atom_blk));
       fp << "\t\t";
       if (true == use_explicit_port_map) {
-        fp << "." << atom_ctx.nlist.block_name(atom_blk) << module_output_port_postfix << "(";
+        fp << "." << block_name << module_output_port_postfix << "(";
       }
-      fp << atom_ctx.nlist.block_name(atom_blk) << output_port_postfix;
+      fp << block_name << output_port_postfix;
       if (true == use_explicit_port_map) {
         fp << ")";
       }
@@ -115,6 +123,7 @@ void print_verilog_testbench_connect_fpga_ios(std::fstream& fp,
                                               const AtomContext& atom_ctx,
                                               const PlacementContext& place_ctx,
                                               const IoLocationMap& io_location_map,
+                                              const VprNetlistAnnotation& netlist_annotation,
                                               const std::string& io_input_port_name_postfix,
                                               const std::string& io_output_port_name_postfix,
                                               const size_t& unused_io_value) {
@@ -152,21 +161,27 @@ void print_verilog_testbench_connect_fpga_ios(std::fstream& fp,
     VTR_ASSERT(io_index < module_mapped_io_port.get_width());
     module_mapped_io_port.set_width(io_index, io_index);
 
+    /* The block may be renamed as it contains special characters which violate Verilog syntax */
+    std::string block_name = atom_ctx.nlist.block_name(atom_blk);
+    if (true == netlist_annotation.is_block_renamed(atom_blk)) {
+      block_name = netlist_annotation.block_name(atom_blk);
+    } 
+
     /* Create the port for benchmark I/O, due to BLIF benchmark, each I/O always has a size of 1 
      * In addition, the input and output ports may have different postfix in naming
      * due to verification context! Here, we give full customization on naming 
      */
     BasicPort benchmark_io_port;
     if (AtomBlockType::INPAD == atom_ctx.nlist.block_type(atom_blk)) {
-      benchmark_io_port.set_name(std::string(atom_ctx.nlist.block_name(atom_blk) + io_input_port_name_postfix)); 
+      benchmark_io_port.set_name(std::string(block_name + io_input_port_name_postfix)); 
       benchmark_io_port.set_width(1);
-      print_verilog_comment(fp, std::string("----- Blif Benchmark input " + atom_ctx.nlist.block_name(atom_blk) + " is mapped to FPGA IOPAD " + module_mapped_io_port.get_name() + "[" + std::to_string(io_index) + "] -----"));
+      print_verilog_comment(fp, std::string("----- Blif Benchmark input " + block_name + " is mapped to FPGA IOPAD " + module_mapped_io_port.get_name() + "[" + std::to_string(io_index) + "] -----"));
       print_verilog_wire_connection(fp, module_mapped_io_port, benchmark_io_port, false);
     } else {
       VTR_ASSERT(AtomBlockType::OUTPAD == atom_ctx.nlist.block_type(atom_blk));
-      benchmark_io_port.set_name(std::string(atom_ctx.nlist.block_name(atom_blk) + io_output_port_name_postfix)); 
+      benchmark_io_port.set_name(std::string(block_name + io_output_port_name_postfix)); 
       benchmark_io_port.set_width(1);
-      print_verilog_comment(fp, std::string("----- Blif Benchmark output " + atom_ctx.nlist.block_name(atom_blk) + " is mapped to FPGA IOPAD " + module_mapped_io_port.get_name() + "[" + std::to_string(io_index) + "] -----"));
+      print_verilog_comment(fp, std::string("----- Blif Benchmark output " + block_name + " is mapped to FPGA IOPAD " + module_mapped_io_port.get_name() + "[" + std::to_string(io_index) + "] -----"));
       print_verilog_wire_connection(fp, benchmark_io_port, module_mapped_io_port, false);
     }
 
@@ -281,6 +296,7 @@ void print_verilog_testbench_check(std::fstream& fp,
                                    const std::string& check_flag_port_postfix,
                                    const std::string& error_counter_name,
                                    const AtomContext& atom_ctx,
+                                   const VprNetlistAnnotation& netlist_annotation,
                                    const std::vector<std::string>& clock_port_names,
                                    const std::string& default_clock_name) {
 
@@ -314,14 +330,20 @@ void print_verilog_testbench_check(std::fstream& fp,
       continue;
     }
 
+    /* The block may be renamed as it contains special characters which violate Verilog syntax */
+    std::string block_name = atom_ctx.nlist.block_name(atom_blk);
+    if (true == netlist_annotation.is_block_renamed(atom_blk)) {
+      block_name = netlist_annotation.block_name(atom_blk);
+    } 
+
     if (AtomBlockType::OUTPAD == atom_ctx.nlist.block_type(atom_blk)) {
-     fp << "\t\t\tif(!(" << atom_ctx.nlist.block_name(atom_blk) << fpga_port_postfix;
-     fp << " === " << atom_ctx.nlist.block_name(atom_blk) << benchmark_port_postfix;
-     fp << ") && !(" << atom_ctx.nlist.block_name(atom_blk) << benchmark_port_postfix;
+     fp << "\t\t\tif(!(" << block_name << fpga_port_postfix;
+     fp << " === " << block_name << benchmark_port_postfix;
+     fp << ") && !(" << block_name << benchmark_port_postfix;
      fp << " === 1'bx)) begin" << std::endl;
-     fp << "\t\t\t\t" << atom_ctx.nlist.block_name(atom_blk) << check_flag_port_postfix << " <= 1'b1;" << std::endl;
+     fp << "\t\t\t\t" << block_name << check_flag_port_postfix << " <= 1'b1;" << std::endl;
      fp << "\t\t\tend else begin" << std::endl;
-     fp << "\t\t\t\t" << atom_ctx.nlist.block_name(atom_blk) << check_flag_port_postfix << "<= 1'b0;" << std::endl;
+     fp << "\t\t\t\t" << block_name << check_flag_port_postfix << "<= 1'b0;" << std::endl;
      fp << "\t\t\tend" << std::endl; 
     }
   } 
@@ -337,10 +359,16 @@ void print_verilog_testbench_check(std::fstream& fp,
       continue;
     }
 
-    fp << "\talways@(posedge " << atom_ctx.nlist.block_name(atom_blk) << check_flag_port_postfix << ") begin" << std::endl;
-    fp << "\t\tif(" << atom_ctx.nlist.block_name(atom_blk) << check_flag_port_postfix << ") begin" << std::endl;
+    /* The block may be renamed as it contains special characters which violate Verilog syntax */
+    std::string block_name = atom_ctx.nlist.block_name(atom_blk);
+    if (true == netlist_annotation.is_block_renamed(atom_blk)) {
+      block_name = netlist_annotation.block_name(atom_blk);
+    } 
+
+    fp << "\talways@(posedge " << block_name << check_flag_port_postfix << ") begin" << std::endl;
+    fp << "\t\tif(" << block_name << check_flag_port_postfix << ") begin" << std::endl;
     fp << "\t\t\t" << error_counter_name << " = " << error_counter_name << " + 1;" << std::endl;
-    fp << "\t\t\t$display(\"Mismatch on " << atom_ctx.nlist.block_name(atom_blk) << fpga_port_postfix << " at time = " << std::string("%t") << "\", $realtime);" << std::endl;
+    fp << "\t\t\t$display(\"Mismatch on " << block_name << fpga_port_postfix << " at time = " << std::string("%t") << "\", $realtime);" << std::endl;
     fp << "\t\tend" << std::endl;
     fp << "\tend" << std::endl;
 
@@ -393,6 +421,7 @@ void print_verilog_testbench_clock_stimuli(std::fstream& fp,
  *******************************************************************/
 void print_verilog_testbench_random_stimuli(std::fstream& fp,
                                             const AtomContext& atom_ctx,
+                                            const VprNetlistAnnotation& netlist_annotation,
                                             const std::string& check_flag_port_postfix,
                                             const BasicPort& clock_port) {
   /* Validate the file stream */
@@ -409,9 +438,15 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp,
       continue;
     }
 
+    /* The block may be renamed as it contains special characters which violate Verilog syntax */
+    std::string block_name = atom_ctx.nlist.block_name(atom_blk);
+    if (true == netlist_annotation.is_block_renamed(atom_blk)) {
+      block_name = netlist_annotation.block_name(atom_blk);
+    } 
+
     /* TODO: find the clock inputs will be initialized later */
     if (AtomBlockType::INPAD == atom_ctx.nlist.block_type(atom_blk)) {
-      fp << "\t\t" << atom_ctx.nlist.block_name(atom_blk) << " <= 1'b0;" << std::endl;
+      fp << "\t\t" << block_name << " <= 1'b0;" << std::endl;
     }
   }
 
@@ -425,8 +460,14 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp,
       continue;
     }
 
+    /* The block may be renamed as it contains special characters which violate Verilog syntax */
+    std::string block_name = atom_ctx.nlist.block_name(atom_blk);
+    if (true == netlist_annotation.is_block_renamed(atom_blk)) {
+      block_name = netlist_annotation.block_name(atom_blk);
+    } 
+
     /* Each logical block assumes a single-width port */
-    BasicPort output_port(std::string(atom_ctx.nlist.block_name(atom_blk) + check_flag_port_postfix), 1); 
+    BasicPort output_port(std::string(block_name + check_flag_port_postfix), 1); 
     fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, output_port) << " <= 1'b0;" << std::endl;
   }
 
@@ -463,9 +504,15 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp,
       continue;
     }
 
+    /* The block may be renamed as it contains special characters which violate Verilog syntax */
+    std::string block_name = atom_ctx.nlist.block_name(atom_blk);
+    if (true == netlist_annotation.is_block_renamed(atom_blk)) {
+      block_name = netlist_annotation.block_name(atom_blk);
+    } 
+
     /* TODO: find the clock inputs will be initialized later */
     if (AtomBlockType::INPAD != atom_ctx.nlist.block_type(atom_blk)) {
-      fp << "\t\t" << atom_ctx.nlist.block_name(atom_blk) << " <= $random;" << std::endl;
+      fp << "\t\t" << block_name << " <= $random;" << std::endl;
     }
   }
 
@@ -486,6 +533,7 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp,
  *******************************************************************/
 void print_verilog_testbench_shared_ports(std::fstream& fp,
                                           const AtomContext& atom_ctx,
+                                          const VprNetlistAnnotation& netlist_annotation,
                                           const std::string& benchmark_output_port_postfix,
                                           const std::string& fpga_output_port_postfix,
                                           const std::string& check_flag_port_postfix,
@@ -501,10 +549,16 @@ void print_verilog_testbench_shared_ports(std::fstream& fp,
       continue;
     }
 
+    /* The block may be renamed as it contains special characters which violate Verilog syntax */
+    std::string block_name = atom_ctx.nlist.block_name(atom_blk);
+    if (true == netlist_annotation.is_block_renamed(atom_blk)) {
+      block_name = netlist_annotation.block_name(atom_blk);
+    } 
+
     /* TODO: Skip clocks because they are handled in another function */
    
     /* Each logical block assumes a single-width port */
-    BasicPort input_port(atom_ctx.nlist.block_name(atom_blk), 1); 
+    BasicPort input_port(block_name, 1); 
     fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, input_port) << ";" << std::endl;
   }
 
@@ -520,8 +574,14 @@ void print_verilog_testbench_shared_ports(std::fstream& fp,
       continue;
     }
 
+    /* The block may be renamed as it contains special characters which violate Verilog syntax */
+    std::string block_name = atom_ctx.nlist.block_name(atom_blk);
+    if (true == netlist_annotation.is_block_renamed(atom_blk)) {
+      block_name = netlist_annotation.block_name(atom_blk);
+    } 
+
     /* Each logical block assumes a single-width port */
-    BasicPort output_port(std::string(atom_ctx.nlist.block_name(atom_blk) + fpga_output_port_postfix), 1); 
+    BasicPort output_port(std::string(block_name + fpga_output_port_postfix), 1); 
     fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, output_port) << ";" << std::endl;
   }
 
@@ -542,8 +602,14 @@ void print_verilog_testbench_shared_ports(std::fstream& fp,
       continue;
     }
 
+    /* The block may be renamed as it contains special characters which violate Verilog syntax */
+    std::string block_name = atom_ctx.nlist.block_name(atom_blk);
+    if (true == netlist_annotation.is_block_renamed(atom_blk)) {
+      block_name = netlist_annotation.block_name(atom_blk);
+    } 
+
     /* Each logical block assumes a single-width port */
-    BasicPort output_port(std::string(atom_ctx.nlist.block_name(atom_blk) + benchmark_output_port_postfix), 1); 
+    BasicPort output_port(std::string(block_name + benchmark_output_port_postfix), 1); 
     fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, output_port) << ";" << std::endl;
   }
 
@@ -558,8 +624,14 @@ void print_verilog_testbench_shared_ports(std::fstream& fp,
       continue;
     }
 
+    /* The block may be renamed as it contains special characters which violate Verilog syntax */
+    std::string block_name = atom_ctx.nlist.block_name(atom_blk);
+    if (true == netlist_annotation.is_block_renamed(atom_blk)) {
+      block_name = netlist_annotation.block_name(atom_blk);
+    } 
+
     /* Each logical block assumes a single-width port */
-    BasicPort output_port(std::string(atom_ctx.nlist.block_name(atom_blk) + check_flag_port_postfix), 1); 
+    BasicPort output_port(std::string(block_name + check_flag_port_postfix), 1); 
     fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, output_port) << ";" << std::endl;
   }
 
diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.h b/openfpga/src/fpga_verilog/verilog_testbench_utils.h
index 7de04deeb..e9a481380 100644
--- a/openfpga/src/fpga_verilog/verilog_testbench_utils.h
+++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.h
@@ -10,6 +10,7 @@
 #include "module_manager.h"
 #include "vpr_context.h"
 #include "io_location_map.h"
+#include "vpr_netlist_annotation.h"
 #include "simulation_setting.h"
 
 /********************************************************************
@@ -31,6 +32,7 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp,
                                                 const std::string& module_output_port_postfix,
                                                 const std::string& output_port_postfix,
                                                 const AtomContext& atom_ctx,
+                                                const VprNetlistAnnotation& netlist_annotation,
                                                 const bool& use_explicit_port_map);
 
 void print_verilog_testbench_connect_fpga_ios(std::fstream& fp,
@@ -39,6 +41,7 @@ void print_verilog_testbench_connect_fpga_ios(std::fstream& fp,
                                               const AtomContext& atom_ctx,
                                               const PlacementContext& place_ctx,
                                               const IoLocationMap& io_location_map,
+                                              const VprNetlistAnnotation& netlist_annotation,
                                               const std::string& io_input_port_name_postfix,
                                               const std::string& io_output_port_name_postfix,
                                               const size_t& unused_io_value);
@@ -62,6 +65,7 @@ void print_verilog_testbench_check(std::fstream& fp,
                                    const std::string& check_flag_port_postfix,
                                    const std::string& error_counter_name,
                                    const AtomContext& atom_ctx,
+                                   const VprNetlistAnnotation& netlist_annotation,
                                    const std::vector<std::string>& clock_port_names,
                                    const std::string& default_clock_name);
 
@@ -71,11 +75,13 @@ void print_verilog_testbench_clock_stimuli(std::fstream& fp,
 
 void print_verilog_testbench_random_stimuli(std::fstream& fp,
                                             const AtomContext& atom_ctx,
+                                            const VprNetlistAnnotation& netlist_annotation,
                                             const std::string& check_flag_port_postfix,
                                             const BasicPort& clock_port);
 
 void print_verilog_testbench_shared_ports(std::fstream& fp,
                                           const AtomContext& atom_ctx,
+                                          const VprNetlistAnnotation& netlist_annotation,
                                           const std::string& benchmark_output_port_postfix,
                                           const std::string& fpga_output_port_postfix,
                                           const std::string& check_flag_port_postfix,
diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
index 6159d1751..76bc1ea49 100644
--- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
@@ -307,6 +307,7 @@ void print_verilog_top_testbench_ports(std::fstream& fp,
                                        const ModuleManager& module_manager,
                                        const ModuleId& top_module,
                                        const AtomContext& atom_ctx,
+                                       const VprNetlistAnnotation& netlist_annotation,
                                        const std::vector<std::string>& clock_port_names,
                                        const e_config_protocol_type& sram_orgz_type,
                                        const std::string& circuit_name){
@@ -397,7 +398,7 @@ void print_verilog_top_testbench_ports(std::fstream& fp,
     print_verilog_wire_connection(fp, clock_port, op_clock_port, false);
   }
 
-  print_verilog_testbench_shared_ports(fp, atom_ctx,
+  print_verilog_testbench_shared_ports(fp, atom_ctx, netlist_annotation,
                                        std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX),
                                        std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX),
                                        std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX),
@@ -416,7 +417,8 @@ void print_verilog_top_testbench_ports(std::fstream& fp,
 static
 void print_verilog_top_testbench_benchmark_instance(std::fstream& fp, 
                                                     const std::string& reference_verilog_top_name,
-                                                    const AtomContext& atom_ctx) {
+                                                    const AtomContext& atom_ctx,
+                                                    const VprNetlistAnnotation& netlist_annotation) {
   /* Validate the file stream */
   valid_file_stream(fp);
 
@@ -433,7 +435,7 @@ void print_verilog_top_testbench_benchmark_instance(std::fstream& fp,
                                              std::string(),
                                              std::string(),
                                              std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX),
-                                             atom_ctx,
+                                             atom_ctx, netlist_annotation,
                                              false);
 
   print_verilog_comment(fp, std::string("----- End reference Benchmark Instanication -------"));
@@ -766,6 +768,7 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
                                  const AtomContext& atom_ctx,
                                  const PlacementContext& place_ctx, 
                                  const IoLocationMap& io_location_map,
+                                 const VprNetlistAnnotation& netlist_annotation,
                                  const std::string& circuit_name,
                                  const std::string& verilog_fname,
                                  const std::string& verilog_dir,
@@ -799,7 +802,7 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
 
   /* Start of testbench */
   print_verilog_top_testbench_ports(fp, module_manager, top_module, 
-                                    atom_ctx, clock_port_names,
+                                    atom_ctx, netlist_annotation, clock_port_names,
                                     sram_orgz_type, circuit_name);
 
   /* Find the clock period */
@@ -829,7 +832,8 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
   
   /* Connect I/Os to benchmark I/Os or constant driver */
   print_verilog_testbench_connect_fpga_ios(fp, module_manager, top_module,
-                                           atom_ctx, place_ctx, io_location_map, 
+                                           atom_ctx, place_ctx, io_location_map,
+                                           netlist_annotation, 
                                            std::string(), 
                                            std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX), 
                                            (size_t)VERILOG_DEFAULT_SIGNAL_INIT_VALUE);
@@ -837,7 +841,8 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
   /* Instanciate input benchmark */
   print_verilog_top_testbench_benchmark_instance(fp, 
                                                  circuit_name,
-                                                 atom_ctx);
+                                                 atom_ctx,
+                                                 netlist_annotation);
 
   /* Print tasks used for loading bitstreams */
   print_verilog_top_testbench_load_bitstream_task(fp, sram_orgz_type);
@@ -848,6 +853,7 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
 
   /* Add stimuli for reset, set, clock and iopad signals */
   print_verilog_testbench_random_stimuli(fp, atom_ctx, 
+                                         netlist_annotation, 
                                          std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX),
                                          BasicPort(std::string(TOP_TB_OP_CLOCK_PORT_NAME), 1));
 
@@ -859,7 +865,10 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
                                 std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX),
                                 std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX),
                                 std::string(TOP_TESTBENCH_ERROR_COUNTER),
-                                atom_ctx, clock_port_names, std::string(TOP_TB_OP_CLOCK_PORT_NAME));
+                                atom_ctx,
+                                netlist_annotation, 
+                                clock_port_names,
+                                std::string(TOP_TB_OP_CLOCK_PORT_NAME));
 
   /* Find simulation time */
   float simulation_time = find_simulation_time_period(VERILOG_SIM_TIMESCALE,
diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.h b/openfpga/src/fpga_verilog/verilog_top_testbench.h
index e2e652eb8..5684b37e2 100644
--- a/openfpga/src/fpga_verilog/verilog_top_testbench.h
+++ b/openfpga/src/fpga_verilog/verilog_top_testbench.h
@@ -11,6 +11,7 @@
 #include "circuit_library.h"
 #include "vpr_context.h"
 #include "io_location_map.h"
+#include "vpr_netlist_annotation.h"
 #include "simulation_setting.h"
 
 /********************************************************************
@@ -29,6 +30,7 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
                                  const AtomContext& atom_ctx,
                                  const PlacementContext& place_ctx, 
                                  const IoLocationMap& io_location_map,
+                                 const VprNetlistAnnotation& netlist_annotation, 
                                  const std::string& circuit_name,
                                  const std::string& verilog_fname,
                                  const std::string& verilog_dir,

From ae899f3b11a3516146b3ae1a74953eb4261e4ee0 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 27 Feb 2020 16:51:55 -0700
Subject: [PATCH 222/645] bug fixed for clock names

---
 .../verilog_formal_random_top_testbench.cpp           |  3 ++-
 .../src/fpga_verilog/verilog_preconfig_top_module.cpp |  2 +-
 openfpga/src/fpga_verilog/verilog_testbench_utils.cpp |  4 ++++
 openfpga/src/fpga_verilog/verilog_testbench_utils.h   |  1 +
 openfpga/src/fpga_verilog/verilog_top_testbench.cpp   |  3 ++-
 openfpga/src/utils/openfpga_atom_netlist_utils.cpp    | 11 +++++++++--
 openfpga/src/utils/openfpga_atom_netlist_utils.h      |  4 +++-
 .../SRC/fpga_x2p/verilog/verilog_testbench_utils.cpp  |  1 -
 8 files changed, 22 insertions(+), 7 deletions(-)

diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
index 2154a8513..4e2d129c5 100644
--- a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
@@ -74,6 +74,7 @@ void print_verilog_top_random_testbench_ports(std::fstream& fp,
   fp << std::endl;
 
   print_verilog_testbench_shared_ports(fp, atom_ctx, netlist_annotation,
+                                       clock_port_names,
                                        std::string(BENCHMARK_PORT_POSTFIX),
                                        std::string(FPGA_PORT_POSTFIX),
                                        std::string(CHECKFLAG_PORT_POSTFIX),
@@ -209,7 +210,7 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
   print_verilog_include_netlist(fp, std::string(verilog_dir + std::string(DEFINES_VERILOG_SIMULATION_FILE_NAME)));  
 
   /* Preparation: find all the clock ports */
-  std::vector<std::string> clock_port_names = find_atom_netlist_clock_port_names(atom_ctx.nlist);
+  std::vector<std::string> clock_port_names = find_atom_netlist_clock_port_names(atom_ctx.nlist, netlist_annotation);
 
   /* Start of testbench */
   print_verilog_top_random_testbench_ports(fp, circuit_name, clock_port_names, atom_ctx, netlist_annotation);
diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
index 000879230..695d9275f 100644
--- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
+++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
@@ -423,7 +423,7 @@ void print_verilog_preconfig_top_module(const ModuleManager& module_manager,
                                         std::string(FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME)); 
 
   /* Find clock ports in benchmark */
-  std::vector<std::string> benchmark_clock_port_names = find_atom_netlist_clock_port_names(atom_ctx.nlist);
+  std::vector<std::string> benchmark_clock_port_names = find_atom_netlist_clock_port_names(atom_ctx.nlist, netlist_annotation);
 
   /* Connect FPGA top module global ports to constant or benchmark global signals! */
   print_verilog_preconfig_top_module_connect_global_ports(fp, module_manager, top_module,
diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
index 395d80493..8d3e856c7 100644
--- a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
+++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
@@ -534,6 +534,7 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp,
 void print_verilog_testbench_shared_ports(std::fstream& fp,
                                           const AtomContext& atom_ctx,
                                           const VprNetlistAnnotation& netlist_annotation,
+                                          const std::vector<std::string>& clock_port_names,
                                           const std::string& benchmark_output_port_postfix,
                                           const std::string& fpga_output_port_postfix,
                                           const std::string& check_flag_port_postfix,
@@ -556,6 +557,9 @@ void print_verilog_testbench_shared_ports(std::fstream& fp,
     } 
 
     /* TODO: Skip clocks because they are handled in another function */
+    if (clock_port_names.end() != std::find(clock_port_names.begin(), clock_port_names.end(), block_name)) {
+      continue;
+    }
    
     /* Each logical block assumes a single-width port */
     BasicPort input_port(block_name, 1); 
diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.h b/openfpga/src/fpga_verilog/verilog_testbench_utils.h
index e9a481380..61d5929c8 100644
--- a/openfpga/src/fpga_verilog/verilog_testbench_utils.h
+++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.h
@@ -82,6 +82,7 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp,
 void print_verilog_testbench_shared_ports(std::fstream& fp,
                                           const AtomContext& atom_ctx,
                                           const VprNetlistAnnotation& netlist_annotation,
+                                          const std::vector<std::string>& clock_port_names,
                                           const std::string& benchmark_output_port_postfix,
                                           const std::string& fpga_output_port_postfix,
                                           const std::string& check_flag_port_postfix,
diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
index 76bc1ea49..f64558dda 100644
--- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
@@ -399,6 +399,7 @@ void print_verilog_top_testbench_ports(std::fstream& fp,
   }
 
   print_verilog_testbench_shared_ports(fp, atom_ctx, netlist_annotation,
+                                       clock_port_names,
                                        std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX),
                                        std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX),
                                        std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX),
@@ -798,7 +799,7 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
   VTR_ASSERT(true == module_manager.valid_module_id(top_module));
 
   /* Preparation: find all the clock ports */
-  std::vector<std::string> clock_port_names = find_atom_netlist_clock_port_names(atom_ctx.nlist);
+  std::vector<std::string> clock_port_names = find_atom_netlist_clock_port_names(atom_ctx.nlist, netlist_annotation);
 
   /* Start of testbench */
   print_verilog_top_testbench_ports(fp, module_manager, top_module, 
diff --git a/openfpga/src/utils/openfpga_atom_netlist_utils.cpp b/openfpga/src/utils/openfpga_atom_netlist_utils.cpp
index d2786e88d..8d1876f90 100644
--- a/openfpga/src/utils/openfpga_atom_netlist_utils.cpp
+++ b/openfpga/src/utils/openfpga_atom_netlist_utils.cpp
@@ -18,14 +18,21 @@ namespace openfpga {
 
 /***************************************************************************************
  * Find the names of all the atom blocks that drive clock nets 
+ * This function will find if the block has been renamed due to contain sensitive characters
+ * that violates the Verilog syntax
  ***************************************************************************************/
-std::vector<std::string> find_atom_netlist_clock_port_names(const AtomNetlist& atom_nlist) {
+std::vector<std::string> find_atom_netlist_clock_port_names(const AtomNetlist& atom_nlist,
+                                                            const VprNetlistAnnotation& netlist_annotation) {
   std::vector<std::string> clock_names;
 
   std::set<AtomPinId> clock_pins = find_netlist_logical_clock_drivers(atom_nlist);
   for (const AtomPinId& clock_pin : clock_pins) {
     const AtomBlockId& atom_blk = atom_nlist.port_block(atom_nlist.pin_port(clock_pin));
-    clock_names.push_back(atom_nlist.block_name(atom_blk));
+    std::string block_name = atom_nlist.block_name(atom_blk);
+    if (true == netlist_annotation.is_block_renamed(atom_blk)) {
+      block_name = netlist_annotation.block_name(atom_blk);
+    }
+    clock_names.push_back(block_name);
   }
 
   return clock_names;
diff --git a/openfpga/src/utils/openfpga_atom_netlist_utils.h b/openfpga/src/utils/openfpga_atom_netlist_utils.h
index 180181687..dfa5743a2 100644
--- a/openfpga/src/utils/openfpga_atom_netlist_utils.h
+++ b/openfpga/src/utils/openfpga_atom_netlist_utils.h
@@ -7,6 +7,7 @@
 #include <vector>
 #include <string>
 #include "atom_netlist.h"
+#include "vpr_netlist_annotation.h"
 
 /********************************************************************
  * Function declaration
@@ -15,7 +16,8 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-std::vector<std::string> find_atom_netlist_clock_port_names(const AtomNetlist& atom_nlist);
+std::vector<std::string> find_atom_netlist_clock_port_names(const AtomNetlist& atom_nlist,
+                                                            const VprNetlistAnnotation& netlist_annotation);
 
 } /* end namespace openfpga */
 
diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.cpp
index ee2a80ea6..9293c7cf6 100644
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.cpp
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.cpp
@@ -479,7 +479,6 @@ void print_verilog_testbench_shared_ports(std::fstream& fp,
   /* Validate the file stream */
   check_file_handler(fp);
 
-
   /* Instantiate register for inputs stimulis */
   print_verilog_comment(fp, std::string("----- Shared inputs -------"));
   for (const t_logical_block& lb : L_logical_blocks) {

From 65c81e14b2281ef2f366f9aa1379ed9baf2dd50e Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 27 Feb 2020 18:01:47 -0700
Subject: [PATCH 223/645] add simulation ini file writer

---
 openfpga/CMakeLists.txt                       |  1 +
 .../fpga_verilog/simulation_info_writer.cpp   | 67 +++++++++++++++++++
 .../src/fpga_verilog/simulation_info_writer.h | 26 +++++++
 openfpga/src/fpga_verilog/verilog_api.cpp     | 13 ++--
 .../verilog_auxiliary_netlists.cpp            |  1 -
 openfpga/src/fpga_verilog/verilog_constants.h |  3 +
 .../verilog_formal_random_top_testbench.cpp   |  1 -
 openfpga/test_script/s298_k6_frac.openfpga    |  2 +-
 8 files changed, 103 insertions(+), 11 deletions(-)
 create mode 100644 openfpga/src/fpga_verilog/simulation_info_writer.cpp
 create mode 100644 openfpga/src/fpga_verilog/simulation_info_writer.h

diff --git a/openfpga/CMakeLists.txt b/openfpga/CMakeLists.txt
index 1e3ae7f13..1cdd56a32 100644
--- a/openfpga/CMakeLists.txt
+++ b/openfpga/CMakeLists.txt
@@ -22,6 +22,7 @@ target_link_libraries(libopenfpga
                       libarchopenfpga
                       libopenfpgashell
                       libopenfpgautil
+                      libini
                       libvtrutil
                       libvpr8)
 
diff --git a/openfpga/src/fpga_verilog/simulation_info_writer.cpp b/openfpga/src/fpga_verilog/simulation_info_writer.cpp
new file mode 100644
index 000000000..fbbb7e83c
--- /dev/null
+++ b/openfpga/src/fpga_verilog/simulation_info_writer.cpp
@@ -0,0 +1,67 @@
+/*********************************************************************
+ * This function includes the writer for generating exchangeable
+ * information, in order to interface different simulators   
+ ********************************************************************/
+#include <cmath>
+#include <ctime>
+#include <map>
+#define MINI_CASE_SENSITIVE
+#include "ini.h"
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_time.h"
+
+#include "simulation_utils.h"
+
+#include "verilog_constants.h"
+#include "simulation_info_writer.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/*********************************************************************
+ * Top-level function to write an ini file which contains exchangeable
+ * information, in order to interface different Verilog simulators
+ ********************************************************************/
+void print_verilog_simulation_info(const std::string& ini_fname,
+                                   const std::string& circuit_name,
+                                   const std::string& src_dir,
+                                   const size_t& num_program_clock_cycles,
+                                   const int& num_operating_clock_cycles,
+                                   const float& prog_clock_freq,
+                                   const float& op_clock_freq) {
+
+  std::string timer_message = std::string("Write exchangeable file containing simulation information '") + ini_fname + std::string("'");
+
+  /* Start time count */
+  vtr::ScopedStartFinishTimer timer(timer_message);
+
+  /* Use default name if user does not provide one */
+  VTR_ASSERT(true != ini_fname.empty());
+
+  mINI::INIStructure ini;
+  // std::map<char, int> units_map;
+  // units_map['s']=1;  // units_map['ms']=1E-3;  // units_map['us']=1E-6;
+  // units_map['ns']=1E-9;  // units_map['ps']=1E-12;  // units_map['fs']=1E-15;
+
+  /* Compute simulation time period */
+  float simulation_time_period = find_simulation_time_period(1E-3,
+                                                             num_program_clock_cycles,
+                                                             1. / prog_clock_freq,
+                                                             num_operating_clock_cycles,
+                                                             1. / op_clock_freq);
+  ini["SIMULATION_DECK"]["PROJECTNAME "] = "ModelSimProject";
+  ini["SIMULATION_DECK"]["BENCHMARK "] = circuit_name;
+  ini["SIMULATION_DECK"]["TOP_TB"] = circuit_name + std::string(FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX);
+  ini["SIMULATION_DECK"]["SIMTIME "] = std::to_string(simulation_time_period);
+  ini["SIMULATION_DECK"]["UNIT "] = "ms";
+  ini["SIMULATION_DECK"]["VERILOG_PATH "] = std::string(src_dir);
+  ini["SIMULATION_DECK"]["VERILOG_FILE1"] = std::string(DEFINES_VERILOG_FILE_NAME);
+  ini["SIMULATION_DECK"]["VERILOG_FILE2"] = std::string(circuit_name + std::string(TOP_INCLUDE_NETLIST_FILE_NAME_POSTFIX));
+
+  mINI::INIFile file(ini_fname);
+  file.generate(ini, true);
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_verilog/simulation_info_writer.h b/openfpga/src/fpga_verilog/simulation_info_writer.h
new file mode 100644
index 000000000..a9a8bdcb1
--- /dev/null
+++ b/openfpga/src/fpga_verilog/simulation_info_writer.h
@@ -0,0 +1,26 @@
+#ifndef SIMULATION_INFO_WRITER_H
+#define SIMULATION_INFO_WRITER_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <string>
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void print_verilog_simulation_info(const std::string& ini_fname,
+                                   const std::string& circuit_name,
+                                   const std::string& src_dir,
+                                   const size_t& num_program_clock_cycles,
+                                   const int& num_operating_clock_cycles,
+                                   const float& prog_clock_freq,
+                                   const float& op_clock_freq);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/fpga_verilog/verilog_api.cpp b/openfpga/src/fpga_verilog/verilog_api.cpp
index 286188a75..dc332db58 100644
--- a/openfpga/src/fpga_verilog/verilog_api.cpp
+++ b/openfpga/src/fpga_verilog/verilog_api.cpp
@@ -23,6 +23,7 @@
 #include "verilog_preconfig_top_module.h"
 #include "verilog_formal_random_top_testbench.h"
 #include "verilog_top_testbench.h"
+#include "simulation_info_writer.h"
 
 /* Header file for this source file */
 #include "verilog_api.h"
@@ -204,22 +205,18 @@ void fpga_verilog_testbench(const ModuleManager& module_manager,
                                 simulation_setting);
   }
  
-  /* TODO: Generate exchangeable files which contains simulation settings 
+  /* Generate exchangeable files which contains simulation settings */
   if (true == options.print_simulation_ini()) {
-    std::string simulation_ini_file_name;
-    if (true != options.simulation_ini_path()) {
-      simulation_ini_file_name = options.simulation_ini_path();
-    }
+    std::string simulation_ini_file_name = options.simulation_ini_path();
+    VTR_ASSERT(true != options.simulation_ini_path().empty());
     print_verilog_simulation_info(simulation_ini_file_name,
-                                  format_dir_path(chomped_parent_dir),
                                   netlist_name,
                                   src_dir_path,
                                   bitstream_manager.bits().size(),
-                                  simulation_setting.num_clock_cycle(),
+                                  simulation_setting.num_clock_cycles(),
                                   simulation_setting.programming_clock_frequency(),
                                   simulation_setting.operating_clock_frequency());
   }
-  */
 
   /* Generate a Verilog file including all the netlists that have been generated */
   print_include_netlists(src_dir_path,
diff --git a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
index 20552c29f..9419f4172 100644
--- a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
+++ b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
@@ -23,7 +23,6 @@ namespace openfpga {
 /********************************************************************
  * Local constant variables
  *******************************************************************/
-constexpr char* TOP_INCLUDE_NETLIST_FILE_NAME_POSTFIX = "_include_netlists.v";
 
 /********************************************************************
  * Print a file that includes all the netlists that have been generated
diff --git a/openfpga/src/fpga_verilog/verilog_constants.h b/openfpga/src/fpga_verilog/verilog_constants.h
index c8a01d375..797a00574 100644
--- a/openfpga/src/fpga_verilog/verilog_constants.h
+++ b/openfpga/src/fpga_verilog/verilog_constants.h
@@ -22,6 +22,7 @@ constexpr char* MODELSIM_SIMULATION_TIME_UNIT = "ms";
 constexpr char* ICARUS_SIMULATOR_FLAG = "ICARUS_SIMULATOR"; // the flag to enable specific Verilog code in testbenches
 // End of Icarus variables and flag
 
+constexpr char* TOP_INCLUDE_NETLIST_FILE_NAME_POSTFIX = "_include_netlists.v";
 constexpr char* VERILOG_TOP_POSTFIX = "_top.v";
 constexpr char* FORMAL_VERIFICATION_VERILOG_FILE_POSTFIX = "_top_formal_verification.v"; 
 constexpr char* TOP_TESTBENCH_VERILOG_FILE_POSTFIX = "_top_tb.v"; /* !!! must be consist with the modelsim_testbench_module_postfix */ 
@@ -52,6 +53,8 @@ constexpr char* FORMAL_VERIFICATION_TOP_MODULE_POSTFIX = "_top_formal_verificati
 constexpr char* FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX = "_fm";
 constexpr char* FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME = "U0_formal_verification";
 
+constexpr char* FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX = "_top_formal_verification_random_tb";
+
 #define VERILOG_DEFAULT_SIGNAL_INIT_VALUE 0
 
 #endif
diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
index 4e2d129c5..7aef8a72f 100644
--- a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
@@ -31,7 +31,6 @@ namespace openfpga {
 /********************************************************************
  * Local variables used only in this file
  *******************************************************************/
-constexpr char* FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX = "_top_formal_verification_random_tb";
 constexpr char* FPGA_PORT_POSTFIX = "_gfpga";
 constexpr char* BENCHMARK_PORT_POSTFIX = "_bench";
 constexpr char* CHECKFLAG_PORT_POSTFIX = "_flag";
diff --git a/openfpga/test_script/s298_k6_frac.openfpga b/openfpga/test_script/s298_k6_frac.openfpga
index eb09da42e..d79fc3b9b 100644
--- a/openfpga/test_script/s298_k6_frac.openfpga
+++ b/openfpga/test_script/s298_k6_frac.openfpga
@@ -38,7 +38,7 @@ fpga_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepene
 write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
 
 # Write the Verilog testbench for FPGA fabric
-write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src --reference_benchmark_file_path /var/tmp/xtang/s298.v --print_top_testbench --print_preconfig_top_testbench
+write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src --reference_benchmark_file_path /var/tmp/xtang/s298.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
 
 # Finish and exit OpenFPGA
 exit

From 8322b1623d3e60709e147e73413e824a0e5b237e Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 27 Feb 2020 19:30:36 -0700
Subject: [PATCH 224/645] start porting SDC generator

---
 openfpga/src/fpga_sdc/sdc_option.cpp | 125 +++++++++++++++++++++++++++
 openfpga/src/fpga_sdc/sdc_option.h   |  53 ++++++++++++
 2 files changed, 178 insertions(+)
 create mode 100644 openfpga/src/fpga_sdc/sdc_option.cpp
 create mode 100644 openfpga/src/fpga_sdc/sdc_option.h

diff --git a/openfpga/src/fpga_sdc/sdc_option.cpp b/openfpga/src/fpga_sdc/sdc_option.cpp
new file mode 100644
index 000000000..4b8c4666f
--- /dev/null
+++ b/openfpga/src/fpga_sdc/sdc_option.cpp
@@ -0,0 +1,125 @@
+/********************************************************************
+ * Member functions for a data structure which includes all the options for the SDC generator
+ ********************************************************************/
+#include "sdc_option.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Public Constructors
+ ********************************************************************/
+SdcOption::SdcOption(const std::string& sdc_dir) {
+  sdc_dir_ = sdc_dir;
+  constrain_global_port_ = false;
+  constrain_grid_ = false;
+  constrain_sb_ = false;
+  constrain_cb_ = false;
+  constrain_configurable_memory_outputs_ = false;
+  constrain_routing_multiplexer_outputs_ = false;
+  constrain_switch_block_outputs_ = false;
+}
+
+/********************************************************************
+ * Public accessors
+ ********************************************************************/
+std::string SdcOption::sdc_dir() const {
+  return sdc_dir_;
+}
+
+bool SdcOption::generate_sdc() const {
+  return generate_sdc_pnr() && generate_sdc_analysis_;
+}
+
+bool SdcOption::generate_sdc_pnr() const {
+  return constrain_global_port_ 
+      || constrain_grid_
+      || constrain_sb_
+      || constrain_cb_
+      || constrain_configurable_memory_outputs_
+      || constrain_routing_multiplexer_outputs_
+      || constrain_switch_block_outputs_;
+}
+
+bool SdcOption::generate_sdc_analysis() const {
+  return generate_sdc_analysis_;
+}
+
+bool SdcOption::constrain_global_port() const {
+  return constrain_global_port_;
+}
+
+bool SdcOption::constrain_grid() const {
+  return constrain_grid_;
+}
+
+bool SdcOption::constrain_sb() const {
+  return constrain_sb_;
+}
+
+bool SdcOption::constrain_cb() const {
+  return constrain_cb_;
+}
+
+bool SdcOption::constrain_configurable_memory_outputs() const {
+  return constrain_configurable_memory_outputs_;
+}
+
+bool SdcOption::constrain_routing_multiplexer_outputs() const {
+  return constrain_routing_multiplexer_outputs_;
+}
+
+bool SdcOption::constrain_switch_block_outputs() const {
+  return constrain_switch_block_outputs_;
+}
+
+/********************************************************************
+ * Public mutators
+ ********************************************************************/
+void SdcOption::set_sdc_dir(const std::string& sdc_dir) {
+  sdc_dir_ = sdc_dir;
+}
+
+void SdcOption::set_generate_sdc_pnr(const bool& generate_sdc_pnr) {
+  constrain_global_port_ = generate_sdc_pnr;
+  constrain_grid_ = generate_sdc_pnr;
+  constrain_sb_ = generate_sdc_pnr;
+  constrain_cb_ = generate_sdc_pnr;
+  constrain_configurable_memory_outputs_ = generate_sdc_pnr;
+  constrain_routing_multiplexer_outputs_ = generate_sdc_pnr;
+  constrain_switch_block_outputs_ = generate_sdc_pnr;
+}
+
+void SdcOption::set_generate_sdc_analysis(const bool& generate_sdc_analysis) {
+  generate_sdc_analysis_ = generate_sdc_analysis;
+}
+
+void SdcOption::set_constrain_global_port(const bool& constrain_global_port) {
+  constrain_global_port_ = constrain_global_port;
+}
+
+void SdcOption::set_constrain_grid(const bool& constrain_grid) {
+  constrain_grid_ = constrain_grid;
+}
+
+void SdcOption::set_constrain_sb(const bool& constrain_sb) {
+  constrain_sb_ = constrain_sb;
+}
+
+void SdcOption::set_constrain_cb(const bool& constrain_cb) {
+  constrain_cb_ = constrain_cb;
+}
+
+void SdcOption::set_constrain_configurable_memory_outputs(const bool& constrain_config_mem_outputs) {
+  constrain_configurable_memory_outputs_ = constrain_config_mem_outputs;
+}
+
+void SdcOption::set_constrain_routing_multiplexer_outputs(const bool& constrain_routing_mux_outputs) {
+  constrain_routing_multiplexer_outputs_ = constrain_routing_mux_outputs;
+}
+
+void SdcOption::set_constrain_switch_block_outputs(const bool& constrain_sb_outputs) {
+  constrain_switch_block_outputs_ = constrain_sb_outputs;
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_sdc/sdc_option.h b/openfpga/src/fpga_sdc/sdc_option.h
new file mode 100644
index 000000000..d53c08e94
--- /dev/null
+++ b/openfpga/src/fpga_sdc/sdc_option.h
@@ -0,0 +1,53 @@
+#ifndef SDC_OPTION_H
+#define SDC_OPTION_H
+
+/********************************************************************
+ * A data structure to include all the options for the SDC generator
+ ********************************************************************/
+
+#include <string>
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+class SdcOption {
+  public: /* Public Constructors */
+    SdcOption(const std::string& sdc_dir);
+  public: /* Public accessors */
+    std::string sdc_dir() const;
+    bool generate_sdc() const;
+    bool generate_sdc_pnr() const;
+    bool generate_sdc_analysis() const;
+    bool constrain_global_port() const;
+    bool constrain_grid() const;
+    bool constrain_sb() const;
+    bool constrain_cb() const;
+    bool constrain_configurable_memory_outputs() const;
+    bool constrain_routing_multiplexer_outputs() const;
+    bool constrain_switch_block_outputs() const;
+  public: /* Public mutators */
+    void set_sdc_dir(const std::string& sdc_dir);
+    void set_generate_sdc_pnr(const bool& generate_sdc_pnr);
+    void set_generate_sdc_analysis(const bool& generate_sdc_analysis);
+    void set_constrain_global_port(const bool& constrain_global_port);
+    void set_constrain_grid(const bool& constrain_grid);
+    void set_constrain_sb(const bool& constrain_sb);
+    void set_constrain_cb(const bool& constrain_cb);
+    void set_constrain_configurable_memory_outputs(const bool& constrain_config_mem_outputs);
+    void set_constrain_routing_multiplexer_outputs(const bool& constrain_routing_mux_outputs);
+    void set_constrain_switch_block_outputs(const bool& constrain_sb_outputs);
+  private: /* Internal data */
+    std::string sdc_dir_;
+    bool constrain_global_port_; 
+    bool constrain_grid_; 
+    bool constrain_sb_;
+    bool constrain_cb_;
+    bool constrain_configurable_memory_outputs_;
+    bool constrain_routing_multiplexer_outputs_;
+    bool constrain_switch_block_outputs_;
+    bool generate_sdc_analysis_; 
+};
+
+} /* end namespace openfpga */
+
+#endif

From 78476ca7749c146f17950875aa04edf49d893188 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 27 Feb 2020 19:36:28 -0700
Subject: [PATCH 225/645] adapt sdc writer utils

---
 openfpga/src/fpga_sdc/sdc_writer_naming.h  |  20 ++
 openfpga/src/fpga_sdc/sdc_writer_utils.cpp | 202 +++++++++++++++++++++
 openfpga/src/fpga_sdc/sdc_writer_utils.h   |  62 +++++++
 3 files changed, 284 insertions(+)
 create mode 100644 openfpga/src/fpga_sdc/sdc_writer_naming.h
 create mode 100644 openfpga/src/fpga_sdc/sdc_writer_utils.cpp
 create mode 100644 openfpga/src/fpga_sdc/sdc_writer_utils.h

diff --git a/openfpga/src/fpga_sdc/sdc_writer_naming.h b/openfpga/src/fpga_sdc/sdc_writer_naming.h
new file mode 100644
index 000000000..9783e29f2
--- /dev/null
+++ b/openfpga/src/fpga_sdc/sdc_writer_naming.h
@@ -0,0 +1,20 @@
+#ifndef SDC_WRITER_NAMING_H
+#define SDC_WRITER_NAMING_H
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+constexpr char* SDC_FILE_NAME_POSTFIX = ".sdc";
+
+constexpr char* SDC_GLOBAL_PORTS_FILE_NAME = "global_ports.sdc";
+constexpr char* SDC_BENCHMARK_ANALYSIS_FILE_NAME= "fpga_top_analysis.sdc";
+constexpr char* SDC_DISABLE_CONFIG_MEM_OUTPUTS_FILE_NAME = "disable_configurable_memory_outputs.sdc";
+constexpr char* SDC_DISABLE_MUX_OUTPUTS_FILE_NAME = "disable_routing_multiplexer_outputs.sdc";
+constexpr char* SDC_DISABLE_SB_OUTPUTS_FILE_NAME = "disable_sb_outputs.sdc";
+constexpr char* SDC_CB_FILE_NAME = "cb.sdc";
+
+constexpr char* SDC_ANALYSIS_FILE_NAME = "fpga_top_analysis.sdc";
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/fpga_sdc/sdc_writer_utils.cpp b/openfpga/src/fpga_sdc/sdc_writer_utils.cpp
new file mode 100644
index 000000000..328f87ce6
--- /dev/null
+++ b/openfpga/src/fpga_sdc/sdc_writer_utils.cpp
@@ -0,0 +1,202 @@
+/********************************************************************
+ * This file include most utilized functions to be used in SDC writers 
+ *******************************************************************/
+#include <chrono>
+#include <ctime>
+#include <iomanip>
+
+/* Headers from openfpgautil library */
+#include "openfpga_digest.h"
+
+#include "sdc_writer_utils.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Write a head (description) in SDC file 
+ *******************************************************************/
+void print_sdc_file_header(std::fstream& fp,
+                           const std::string& usage) {
+
+  valid_file_stream(fp);
+
+  auto end = std::chrono::system_clock::now(); 
+  std::time_t end_time = std::chrono::system_clock::to_time_t(end);
+
+  fp << "#############################################" << std::endl;
+  fp << "#\tSynopsys Design Constraints (SDC)" << std::endl;
+  fp << "#\tFor FPGA fabric " << std::endl;
+  fp << "#\tDescription: " << usage << std::endl;
+  fp << "#\tAuthor: Xifan TANG " << std::endl;
+  fp << "#\tOrganization: University of Utah " << std::endl;
+  fp << "#\tDate: " << std::ctime(&end_time);
+  fp << "#############################################" << std::endl;
+  fp << std::endl;
+}
+
+/********************************************************************
+ * Write a port in SDC format
+ *******************************************************************/
+std::string generate_sdc_port(const BasicPort& port) {
+  std::string sdc_line;
+
+  std::string size_str = "[" + std::to_string(port.get_lsb()) + ":" + std::to_string(port.get_msb()) + "]";
+
+  /* Only connection require a format of <port_name>[<lsb>:<msb>]
+   * others require a format of <port_type> [<lsb>:<msb>] <port_name> 
+   */
+  /* When LSB == MSB, we can use a simplified format <port_type>[<lsb>]*/
+  if ( 1 == port.get_width()) {
+    size_str = "[" + std::to_string(port.get_lsb()) + "]";
+  }
+  sdc_line = port.get_name() + size_str;
+
+  return sdc_line;
+}
+
+/********************************************************************
+ * Constrain a path between two ports of a module with a given maximum timing value
+ *******************************************************************/
+void print_pnr_sdc_constrain_max_delay(std::fstream& fp,
+                                       const std::string& src_instance_name,
+                                       const std::string& src_port_name,
+                                       const std::string& des_instance_name,
+                                       const std::string& des_port_name,
+                                       const float& delay) {
+  /* Validate file stream */
+  valid_file_stream(fp);
+
+  fp << "set_max_delay";
+
+  fp << " -from ";
+  if (!src_instance_name.empty()) {
+    fp << src_instance_name << "/";
+  }
+  fp << src_port_name;
+
+  fp << " -to ";
+ 
+  if (!des_instance_name.empty()) {
+    fp << des_instance_name << "/";
+  }
+  fp << des_port_name;
+
+  fp << " " << std::setprecision(10) << delay;
+
+  fp << std::endl;
+}
+
+/********************************************************************
+ * Constrain a path between two ports of a module with a given timing value
+ * Note: this function uses set_max_delay !!!
+ *******************************************************************/
+void print_pnr_sdc_constrain_module_port2port_timing(std::fstream& fp,
+                                                     const ModuleManager& module_manager,
+                                                     const ModuleId& input_parent_module_id, 
+                                                     const ModulePortId& module_input_port_id, 
+                                                     const ModuleId& output_parent_module_id, 
+                                                     const ModulePortId& module_output_port_id, 
+                                                     const float& tmax) {
+  print_pnr_sdc_constrain_max_delay(fp,
+                                    module_manager.module_name(input_parent_module_id),
+                                    generate_sdc_port(module_manager.module_port(input_parent_module_id, module_input_port_id)),
+                                    module_manager.module_name(output_parent_module_id),
+                                    generate_sdc_port(module_manager.module_port(output_parent_module_id, module_output_port_id)),
+                                    tmax);
+
+}
+
+/********************************************************************
+ * Constrain a path between two ports of a module with a given timing value
+ * This function will NOT output the module name
+ * Note: this function uses set_max_delay !!!
+ *******************************************************************/
+void print_pnr_sdc_constrain_port2port_timing(std::fstream& fp,
+                                              const ModuleManager& module_manager,
+                                              const ModuleId& input_parent_module_id, 
+                                              const ModulePortId& module_input_port_id, 
+                                              const ModuleId& output_parent_module_id, 
+                                              const ModulePortId& module_output_port_id, 
+                                              const float& tmax) {
+  print_pnr_sdc_constrain_max_delay(fp,
+                                    std::string(),
+                                    generate_sdc_port(module_manager.module_port(input_parent_module_id, module_input_port_id)),
+                                    std::string(),
+                                    generate_sdc_port(module_manager.module_port(output_parent_module_id, module_output_port_id)),
+                                    tmax);
+
+}
+
+/********************************************************************
+ * Disable timing for a port 
+ *******************************************************************/
+void print_sdc_disable_port_timing(std::fstream& fp,
+                                   const BasicPort& port) {
+  /* Validate file stream */
+  valid_file_stream(fp);
+
+  fp << "set_disable_timing ";
+
+  fp << generate_sdc_port(port);
+
+  fp << std::endl;
+}
+
+/********************************************************************
+ * Set the input delay for a port in SDC format 
+ * Note that the input delay will be bounded by a clock port
+ *******************************************************************/
+void print_sdc_set_port_input_delay(std::fstream& fp,
+                                    const BasicPort& port,
+                                    const BasicPort& clock_port,
+                                    const float& delay) {
+  /* Validate file stream */
+  valid_file_stream(fp);
+
+  fp << "set_input_delay ";
+
+  fp << "-clock ";
+
+  fp << generate_sdc_port(clock_port);
+
+  fp << " -max ";
+ 
+  fp << std::setprecision(10) << delay;
+
+  fp << " ";
+
+  fp << generate_sdc_port(port);
+
+  fp << std::endl;
+}
+
+/********************************************************************
+ * Set the output delay for a port in SDC format 
+ * Note that the output delay will be bounded by a clock port
+ *******************************************************************/
+void print_sdc_set_port_output_delay(std::fstream& fp,
+                                     const BasicPort& port,
+                                     const BasicPort& clock_port,
+                                     const float& delay) {
+  /* Validate file stream */
+  valid_file_stream(fp);
+
+  fp << "set_output_delay ";
+
+  fp << "-clock ";
+
+  fp << generate_sdc_port(clock_port);
+
+  fp << " -max ";
+ 
+  fp << std::setprecision(10) << delay;
+
+  fp << " ";
+
+  fp << generate_sdc_port(port);
+
+  fp << std::endl;
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_sdc/sdc_writer_utils.h b/openfpga/src/fpga_sdc/sdc_writer_utils.h
new file mode 100644
index 000000000..4e0d86839
--- /dev/null
+++ b/openfpga/src/fpga_sdc/sdc_writer_utils.h
@@ -0,0 +1,62 @@
+#ifndef SDC_WRITER_UTILS_H
+#define SDC_WRITER_UTILS_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <fstream>
+#include <string>
+#include "openfpga_port.h"
+#include "module_manager.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void print_sdc_file_header(std::fstream& fp,
+                           const std::string& usage);
+
+std::string generate_sdc_port(const BasicPort& port);
+
+void print_pnr_sdc_constrain_max_delay(std::fstream& fp,
+                                       const std::string& src_instance_name,
+                                       const std::string& src_port_name,
+                                       const std::string& des_instance_name,
+                                       const std::string& des_port_name,
+                                       const float& delay);
+
+void print_pnr_sdc_constrain_module_port2port_timing(std::fstream& fp,
+                                                     const ModuleManager& module_manager,
+                                                     const ModuleId& input_parent_module_id, 
+                                                     const ModulePortId& module_input_port_id, 
+                                                     const ModuleId& output_parent_module_id, 
+                                                     const ModulePortId& module_output_port_id, 
+                                                     const float& tmax);
+
+void print_pnr_sdc_constrain_port2port_timing(std::fstream& fp,
+                                              const ModuleManager& module_manager,
+                                              const ModuleId& input_parent_module_id, 
+                                              const ModulePortId& module_input_port_id, 
+                                              const ModuleId& output_parent_module_id, 
+                                              const ModulePortId& module_output_port_id, 
+                                              const float& tmax);
+
+void print_sdc_disable_port_timing(std::fstream& fp,
+                                   const BasicPort& port);
+
+void print_sdc_set_port_input_delay(std::fstream& fp,
+                                    const BasicPort& port,
+                                    const BasicPort& clock_port,
+                                    const float& delay);
+
+void print_sdc_set_port_output_delay(std::fstream& fp,
+                                     const BasicPort& port,
+                                     const BasicPort& clock_port,
+                                     const float& delay);
+
+} /* end namespace openfpga */
+
+#endif

From d136ac236f6f831b4f0167e6023389d856085a1a Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 27 Feb 2020 19:39:57 -0700
Subject: [PATCH 226/645] adapt sdc memory utils

---
 openfpga/src/fpga_sdc/sdc_memory_utils.cpp | 69 ++++++++++++++++++++++
 openfpga/src/fpga_sdc/sdc_memory_utils.h   | 25 ++++++++
 2 files changed, 94 insertions(+)
 create mode 100644 openfpga/src/fpga_sdc/sdc_memory_utils.cpp
 create mode 100644 openfpga/src/fpga_sdc/sdc_memory_utils.h

diff --git a/openfpga/src/fpga_sdc/sdc_memory_utils.cpp b/openfpga/src/fpga_sdc/sdc_memory_utils.cpp
new file mode 100644
index 000000000..1910b4197
--- /dev/null
+++ b/openfpga/src/fpga_sdc/sdc_memory_utils.cpp
@@ -0,0 +1,69 @@
+/********************************************************************
+ * Most utilized function used to constrain memory cells in FPGA
+ * fabric using SDC commands
+ *******************************************************************/
+
+/* Headers from openfpgautil library */
+#include "openfpga_digest.h"
+
+#include "sdc_writer_utils.h"
+
+#include "sdc_memory_utils.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Print SDC commands to disable outputs of all the configurable memory modules
+ * in a given module 
+ * This function will be executed in a recursive way, 
+ * using a Depth-First Search (DFS) strategy
+ * It will iterate over all the configurable children under each module
+ * and print a SDC command to disable its outputs
+ *******************************************************************/
+void rec_print_pnr_sdc_disable_configurable_memory_module_output(std::fstream& fp, 
+                                                                 const ModuleManager& module_manager, 
+                                                                 const ModuleId& parent_module,
+                                                                 const std::string& parent_module_path) {
+
+  /* For each configurable child, we will go one level down in priority */
+  for (size_t child_index = 0; child_index < module_manager.configurable_children(parent_module).size(); ++child_index) {
+    std::string child_module_path = parent_module_path;
+    ModuleId child_module_id = module_manager.configurable_children(parent_module)[child_index];
+    size_t child_instance_id = module_manager.configurable_child_instances(parent_module)[child_index];
+    if (true == module_manager.instance_name(parent_module, child_module_id, child_instance_id).empty()) {
+      /* Give a default name <module_name>_<instance_id>_ */
+      child_module_path += module_manager.module_name(child_module_id); 
+      child_module_path += "_";
+      child_module_path += std::to_string(child_instance_id);
+      child_module_path += "_";
+    } else {
+      child_module_path += module_manager.instance_name(parent_module, child_module_id, child_instance_id);
+    }
+    child_module_path = format_dir_path(child_module_path);
+
+    rec_print_pnr_sdc_disable_configurable_memory_module_output(fp, module_manager, 
+                                                                child_module_id, 
+                                                                child_module_path);
+  }
+
+  /* If there is no configurable children any more, this is a leaf module, print a SDC command for disable timing */
+  if (0 < module_manager.configurable_children(parent_module).size()) {
+    return;
+  }
+
+  /* Validate file stream */
+  valid_file_stream(fp);
+
+  /* Disable timing for each output port of this module */
+  for (const BasicPort& output_port : module_manager.module_ports_by_type(parent_module, ModuleManager::MODULE_OUTPUT_PORT)) {
+    for (const size_t& pin : output_port.pins()) {
+      BasicPort output_pin(output_port.get_name(), pin, pin);
+      fp << "set_disable_timing ";
+      fp << parent_module_path << generate_sdc_port(output_pin);
+      fp << std::endl;
+    }
+  }
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_sdc/sdc_memory_utils.h b/openfpga/src/fpga_sdc/sdc_memory_utils.h
new file mode 100644
index 000000000..7fbf92294
--- /dev/null
+++ b/openfpga/src/fpga_sdc/sdc_memory_utils.h
@@ -0,0 +1,25 @@
+#ifndef SDC_MEMORY_UTILS_H
+#define SDC_MEMORY_UTILS_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <fstream>
+#include <string>
+#include "module_manager.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void rec_print_pnr_sdc_disable_configurable_memory_module_output(std::fstream& fp, 
+                                                                 const ModuleManager& module_manager, 
+                                                                 const ModuleId& parent_module,
+                                                                 const std::string& parent_module_path);
+
+} /* end namespace openfpga */
+
+#endif

From b4ed931ac6903824fd1567006de0e7b508ae3a53 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 27 Feb 2020 20:35:56 -0700
Subject: [PATCH 227/645] adapt sdc routing writer

---
 .../src/fpga_sdc/pnr_sdc_routing_writer.cpp   | 411 ++++++++++++++++++
 .../src/fpga_sdc/pnr_sdc_routing_writer.h     |  42 ++
 2 files changed, 453 insertions(+)
 create mode 100644 openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp
 create mode 100644 openfpga/src/fpga_sdc/pnr_sdc_routing_writer.h

diff --git a/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp
new file mode 100644
index 000000000..348ee3dac
--- /dev/null
+++ b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp
@@ -0,0 +1,411 @@
+/********************************************************************
+ * This file includes functions that print SDC (Synopsys Design Constraint) 
+ * files in physical design tools, i.e., Place & Route (PnR) tools
+ * The SDC files are used to constrain the physical design for each routing modules
+ * in FPGA fabric, such as Switch Blocks (SBs) and Connection Blocks (CBs)
+ *
+ * Note that this is different from the SDC to constrain VPR Place&Route
+ * engine! These SDCs are designed for PnR to generate FPGA layouts!!!
+ *******************************************************************/
+#include <ctime>
+#include <fstream>
+
+/* Headers from vtrutil library */
+#include "vtr_log.h"
+#include "vtr_assert.h"
+#include "vtr_time.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_port.h"
+#include "openfpga_side_manager.h"
+#include "openfpga_digest.h"
+
+#include "mux_utils.h"
+
+#include "openfpga_naming.h"
+
+#include "openfpga_rr_graph_utils.h"
+#include "build_routing_module_utils.h"
+
+#include "sdc_writer_naming.h"
+#include "sdc_writer_utils.h"
+#include "pnr_sdc_routing_writer.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Find the timing constraints between the inputs and outputs of a routing
+ * multiplexer in a Switch Block
+ *******************************************************************/
+static 
+float find_pnr_sdc_switch_tmax(const t_rr_switch_inf& switch_inf) {
+  return switch_inf.R * switch_inf.Cout + switch_inf.Tdel;
+}
+
+/********************************************************************
+ * Set timing constraints between the inputs and outputs of a routing
+ * multiplexer in a Switch Block
+ *******************************************************************/
+static 
+void print_pnr_sdc_constrain_sb_mux_timing(std::fstream& fp,
+                                           const ModuleManager& module_manager,
+                                           const ModuleId& sb_module, 
+                                           const RRGraph& rr_graph,
+                                           const RRGSB& rr_gsb,
+                                           const e_side& output_node_side,
+                                           const RRNodeId& output_rr_node) {
+  /* Validate file stream */
+  valid_file_stream(fp);
+
+  VTR_ASSERT(  ( CHANX == rr_graph.node_type(output_rr_node) )
+            || ( CHANY == rr_graph.node_type(output_rr_node) ));
+
+  /* Find the module port corresponding to the output rr_node */
+  ModulePortId module_output_port = find_switch_block_module_chan_port(module_manager, 
+                                                                       sb_module,
+                                                                       rr_graph, 
+                                                                       rr_gsb, 
+                                                                       output_node_side,
+                                                                       output_rr_node,
+                                                                       OUT_PORT);
+
+  /* Find the module port corresponding to the fan-in rr_nodes of the output rr_node */
+  std::vector<ModulePortId> module_input_ports = find_switch_block_module_input_ports(module_manager,
+                                                                                      sb_module, 
+                                                                                      rr_graph, 
+                                                                                      rr_gsb, 
+                                                                                      get_rr_graph_configurable_driver_nodes(rr_graph, output_rr_node));
+
+  /* Find timing constraints for each path (edge) */
+  std::map<ModulePortId, float> switch_delays;
+  size_t edge_counter = 0;
+  for (const RREdgeId& edge : rr_graph.node_configurable_in_edges(output_rr_node)) {
+    /* Get the switch delay */
+    const RRSwitchId& driver_switch = rr_graph.edge_switch(edge);
+    switch_delays[module_input_ports[edge_counter]] = find_pnr_sdc_switch_tmax(rr_graph.get_switch(driver_switch));
+    edge_counter++;
+  }
+
+  /* Find the starting points */
+  for (const ModulePortId& module_input_port : module_input_ports) {
+    /* Constrain a path */
+    print_pnr_sdc_constrain_port2port_timing(fp,
+                                             module_manager, 
+                                             sb_module, module_input_port, 
+                                             sb_module, module_output_port,
+                                             switch_delays[module_input_port]);
+  }
+}
+
+/********************************************************************
+ * Set timing constraints between the inputs and outputs of SBs, 
+ * which are connected by routing multiplexers with the given delays
+ * specified in architectural XML file
+ *
+ * To enable block by block timing constraining, we generate the SDC
+ * file for each unique SB module
+ *******************************************************************/
+static 
+void print_pnr_sdc_constrain_sb_timing(const std::string& sdc_dir,
+                                       const ModuleManager& module_manager,
+                                       const RRGraph& rr_graph,
+                                       const RRGSB& rr_gsb) {
+
+  /* Create the file name for Verilog netlist */
+  vtr::Point<size_t> gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
+  std::string sdc_fname(sdc_dir + generate_switch_block_module_name(gsb_coordinate) + std::string(SDC_FILE_NAME_POSTFIX));
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(sdc_fname, std::fstream::out | std::fstream::trunc);
+
+  /* Validate file stream */
+  check_file_stream(sdc_fname.c_str(), fp);
+
+  std::string sb_module_name = generate_switch_block_module_name(gsb_coordinate);
+  ModuleId sb_module = module_manager.find_module(sb_module_name);
+  VTR_ASSERT(true == module_manager.valid_module_id(sb_module));
+
+  /* Generate the descriptions*/
+  print_sdc_file_header(fp, std::string("Constrain timing of Switch Block " + sb_module_name + " for PnR"));
+
+  for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
+    SideManager side_manager(side);
+    for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) {
+      const RRNodeId& chan_rr_node = rr_gsb.get_chan_node(side_manager.get_side(), itrack);
+      /* We only care the output port and it should indicate a SB mux */
+      if (OUT_PORT != rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) { 
+        continue; 
+      }
+      /* Constrain thru wires */
+      if (false != rr_gsb.is_sb_node_passing_wire(rr_graph, side_manager.get_side(), itrack)) {
+        continue;
+      } 
+      /* This is a MUX, constrain all the paths from an input to an output */
+      print_pnr_sdc_constrain_sb_mux_timing(fp,
+                                            module_manager, sb_module, 
+                                            rr_graph,
+                                            rr_gsb,
+                                            side_manager.get_side(),
+                                            chan_rr_node);
+    }
+  }
+
+  /* Close file handler */
+  fp.close();
+}
+
+/********************************************************************
+ * Print SDC timing constraints for Switch blocks
+ * This function is designed for flatten routing hierarchy
+ *******************************************************************/
+void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_dir,
+                                                       const ModuleManager& module_manager,
+                                                       const RRGraph& rr_graph,
+                                                       const DeviceRRGSB& device_rr_gsb) {
+
+  /* Start time count */
+  vtr::ScopedStartFinishTimer timer("Generating SDC for constrain Switch Block timing for P&R flow");
+
+  /* Get the range of SB array */
+  vtr::Point<size_t> sb_range = device_rr_gsb.get_gsb_range();
+  /* Go for each SB */
+  for (size_t ix = 0; ix < sb_range.x(); ++ix) {
+    for (size_t iy = 0; iy < sb_range.y(); ++iy) {
+      const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
+      if (false == rr_gsb.is_sb_exist()) {
+        continue;
+      }
+      print_pnr_sdc_constrain_sb_timing(sdc_dir,
+                                        module_manager,
+                                        rr_graph,
+                                        rr_gsb);
+    }
+  }
+}
+
+/********************************************************************
+ * Print SDC timing constraints for Switch blocks
+ * This function is designed for compact routing hierarchy
+ *******************************************************************/
+void print_pnr_sdc_compact_routing_constrain_sb_timing(const std::string& sdc_dir,
+                                                       const ModuleManager& module_manager,
+                                                       const RRGraph& rr_graph,
+                                                       const DeviceRRGSB& device_rr_gsb) {
+
+  /* Start time count */
+  vtr::ScopedStartFinishTimer timer("Generating SDC for constrain Switch Block timing for P&R flow");
+
+  for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_module(); ++isb) {
+    const RRGSB& rr_gsb = device_rr_gsb.get_sb_unique_module(isb);
+    if (false == rr_gsb.is_sb_exist()) {
+      continue;
+    }
+    print_pnr_sdc_constrain_sb_timing(sdc_dir,
+                                      module_manager,
+                                      rr_graph,
+                                      rr_gsb);
+  }
+}
+
+/********************************************************************
+ * Set timing constraints between the inputs and outputs of a routing
+ * multiplexer in a Connection Block
+ *******************************************************************/
+static 
+void print_pnr_sdc_constrain_cb_mux_timing(std::fstream& fp,
+                                           const ModuleManager& module_manager,
+                                           const ModuleId& cb_module, 
+                                           const RRGraph& rr_graph,
+                                           const RRGSB& rr_gsb,
+                                           const t_rr_type& cb_type,
+                                           const RRNodeId& output_rr_node) {
+  /* Validate file stream */
+  valid_file_stream(fp);
+
+  VTR_ASSERT(IPIN == rr_graph.node_type(output_rr_node));
+  
+  /* We have OPINs since we may have direct connections:
+   * These connections should be handled by other functions in the compact_netlist.c 
+   * So we just return here for OPINs 
+   */
+  if (0 == get_rr_graph_configurable_driver_nodes(rr_graph, output_rr_node).size()) {
+    return;
+  }
+
+  /* Find the module port corresponding to the output rr_node */
+  ModulePortId module_output_port = find_connection_block_module_ipin_port(module_manager, 
+                                                                           cb_module,
+                                                                           rr_graph, 
+                                                                           rr_gsb, 
+                                                                           output_rr_node);
+
+  /* Find the module port corresponding to the fan-in rr_nodes of the output rr_node */
+  std::vector<ModulePortId> module_input_ports = find_connection_block_module_input_ports(module_manager,
+                                                                                          cb_module, 
+                                                                                          rr_graph, 
+                                                                                          rr_gsb, 
+                                                                                          cb_type,
+                                                                                          get_rr_graph_configurable_driver_nodes(rr_graph, output_rr_node));
+
+  /* Find timing constraints for each path (edge) */
+  std::map<ModulePortId, float> switch_delays;
+  size_t edge_counter = 0;
+  for (const RREdgeId& edge : rr_graph.node_configurable_in_edges(output_rr_node)) {
+    /* Get the switch delay */
+    const RRSwitchId& driver_switch = rr_graph.edge_switch(edge);
+    switch_delays[module_input_ports[edge_counter]] = find_pnr_sdc_switch_tmax(rr_graph.get_switch(driver_switch));
+    edge_counter++;
+  }
+
+  /* Find the starting points */
+  for (const ModulePortId& module_input_port : module_input_ports) {
+    /* Constrain a path */
+    print_pnr_sdc_constrain_port2port_timing(fp,
+                                             module_manager, 
+                                             cb_module, module_input_port, 
+                                             cb_module, module_output_port,
+                                             switch_delays[module_input_port]);
+  }
+}
+
+
+/********************************************************************
+ * Print SDC timing constraints for a Connection block 
+ * This function is designed for compact routing hierarchy
+ *******************************************************************/
+static 
+void print_pnr_sdc_constrain_cb_timing(const std::string& sdc_dir,
+                                       const ModuleManager& module_manager,
+                                       const RRGraph& rr_graph,
+                                       const RRGSB& rr_gsb, 
+                                       const t_rr_type& cb_type) {
+  /* Create the netlist */
+  vtr::Point<size_t> gsb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type));
+
+  /* Find the module name and create a SDC file for it */
+  std::string sdc_fname(sdc_dir + generate_connection_block_module_name(cb_type, gsb_coordinate) + std::string(SDC_FILE_NAME_POSTFIX));
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(sdc_fname, std::fstream::out | std::fstream::trunc);
+
+  /* Validate file stream */
+  check_file_stream(sdc_fname.c_str(), fp);
+
+  std::string cb_module_name = generate_connection_block_module_name(cb_type, gsb_coordinate); 
+  ModuleId cb_module = module_manager.find_module(cb_module_name);
+  VTR_ASSERT(true == module_manager.valid_module_id(cb_module));
+
+  /* Generate the descriptions*/
+  print_sdc_file_header(fp, std::string("Constrain timing of Connection Block " + cb_module_name + " for PnR"));
+
+  std::vector<enum e_side> cb_sides = rr_gsb.get_cb_ipin_sides(cb_type);
+
+  for (size_t side = 0; side < cb_sides.size(); ++side) {
+    enum e_side cb_ipin_side = cb_sides[side];
+    SideManager side_manager(cb_ipin_side);
+    for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) {
+      const RRNodeId& ipin_rr_node = rr_gsb.get_ipin_node(cb_ipin_side, inode);
+      print_pnr_sdc_constrain_cb_mux_timing(fp,
+                                            module_manager, cb_module, 
+                                            rr_graph, rr_gsb, cb_type,
+                                            ipin_rr_node);
+    }
+  }
+
+  /* Close file handler */
+  fp.close();
+}
+
+/********************************************************************
+ * Iterate over all the connection blocks in a device
+ * and print SDC file for each of them 
+ *******************************************************************/
+static 
+void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_dir,
+                                                       const ModuleManager& module_manager, 
+                                                       const RRGraph& rr_graph,
+                                                       const DeviceRRGSB& device_rr_gsb,
+                                                       const t_rr_type& cb_type) {
+  /* Build unique X-direction connection block modules */
+  vtr::Point<size_t> cb_range = device_rr_gsb.get_gsb_range();
+
+  for (size_t ix = 0; ix < cb_range.x(); ++ix) {
+    for (size_t iy = 0; iy < cb_range.y(); ++iy) {
+      /* Check if the connection block exists in the device!
+       * Some of them do NOT exist due to heterogeneous blocks (height > 1) 
+       * We will skip those modules
+       */
+      const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
+      if (false == rr_gsb.is_cb_exist(cb_type)) {
+        continue;
+      }
+      print_pnr_sdc_constrain_cb_timing(sdc_dir,
+                                        module_manager,
+                                        rr_graph, 
+                                        rr_gsb, 
+                                        cb_type);
+
+    }
+  }
+}
+
+/********************************************************************
+ * Iterate over all the connection blocks in a device
+ * and print SDC file for each of them 
+ *******************************************************************/
+void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_dir,
+                                                       const ModuleManager& module_manager, 
+                                                       const RRGraph& rr_graph,
+                                                       const DeviceRRGSB& device_rr_gsb) {
+
+  /* Start time count */
+  vtr::ScopedStartFinishTimer timer("Generating SDC for constrain Connection Block timing for P&R flow");
+
+  print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_dir, module_manager, 
+                                                    rr_graph,
+                                                    device_rr_gsb,
+                                                    CHANX);
+
+  print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_dir, module_manager, 
+                                                    rr_graph,
+                                                    device_rr_gsb,
+                                                    CHANY);
+}
+
+/********************************************************************
+ * Print SDC timing constraints for Connection blocks
+ * This function is designed for compact routing hierarchy
+ *******************************************************************/
+void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_dir,
+                                                       const ModuleManager& module_manager,
+                                                       const RRGraph& rr_graph,
+                                                       const DeviceRRGSB& device_rr_gsb) {
+
+  /* Start time count */
+  vtr::ScopedStartFinishTimer timer("Generating SDC for constrain Connection Block timing for P&R flow");
+
+  /* Print SDC for unique X-direction connection block modules */
+  for (size_t icb = 0; icb < device_rr_gsb.get_num_cb_unique_module(CHANX); ++icb) {
+    const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANX, icb);
+    print_pnr_sdc_constrain_cb_timing(sdc_dir,
+                                      module_manager,
+                                      rr_graph, 
+                                      unique_mirror, 
+                                      CHANX);
+  }
+
+  /* Print SDC for unique Y-direction connection block modules */
+  for (size_t icb = 0; icb < device_rr_gsb.get_num_cb_unique_module(CHANY); ++icb) {
+    const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANY, icb);
+    print_pnr_sdc_constrain_cb_timing(sdc_dir,
+                                      module_manager,
+                                      rr_graph, 
+                                      unique_mirror, 
+                                      CHANY);
+  }
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.h b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.h
new file mode 100644
index 000000000..65ce60ca8
--- /dev/null
+++ b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.h
@@ -0,0 +1,42 @@
+#ifndef PNR_SDC_ROUTING_WRITER_H
+#define PNR_SDC_ROUTING_WRITER_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <string>
+#include <vector>
+#include "module_manager.h"
+#include "device_rr_gsb.h"
+#include "rr_graph_obj.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_dir,
+                                                       const ModuleManager& module_manager,
+                                                       const RRGraph& rr_graph,
+                                                       const DeviceRRGSB& device_rr_gsb);
+
+void print_pnr_sdc_compact_routing_constrain_sb_timing(const std::string& sdc_dir,
+                                                       const ModuleManager& module_manager,
+                                                       const RRGraph& rr_graph,
+                                                       const DeviceRRGSB& device_rr_gsb);
+
+void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_dir,
+                                                       const ModuleManager& module_manager, 
+                                                       const RRGraph& rr_graph,
+                                                       const DeviceRRGSB& device_rr_gsb);
+
+void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_dir,
+                                                       const ModuleManager& module_manager,
+                                                       const RRGraph& rr_graph,
+                                                       const DeviceRRGSB& device_rr_gsb);
+
+} /* end namespace openfpga */
+
+#endif

From fdcb9829037c83be39d3e3328fc3fa0678a2e6bb Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 27 Feb 2020 21:06:33 -0700
Subject: [PATCH 228/645] adapt pnr sdc grid writer

---
 openfpga/src/fabric/build_grid_modules.cpp    |   1 -
 openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp | 346 ++++++++++++++++++
 openfpga/src/fpga_sdc/pnr_sdc_grid_writer.h   |  27 ++
 3 files changed, 373 insertions(+), 1 deletion(-)
 create mode 100644 openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp
 create mode 100644 openfpga/src/fpga_sdc/pnr_sdc_grid_writer.h

diff --git a/openfpga/src/fabric/build_grid_modules.cpp b/openfpga/src/fabric/build_grid_modules.cpp
index 17ecc67e2..a5c346025 100644
--- a/openfpga/src/fabric/build_grid_modules.cpp
+++ b/openfpga/src/fabric/build_grid_modules.cpp
@@ -1103,7 +1103,6 @@ void build_grid_modules(ModuleManager& module_manager,
                                    duplicate_grid_pin,
                                    verbose);
       } 
-      continue;
     } else {
       /* For CLB and heterogenenous blocks */
       build_physical_tile_module(module_manager, circuit_lib,
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp
new file mode 100644
index 000000000..ea7702a12
--- /dev/null
+++ b/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp
@@ -0,0 +1,346 @@
+/********************************************************************
+ * This file includes functions that print SDC (Synopsys Design Constraint) 
+ * files in physical design tools, i.e., Place & Route (PnR) tools
+ * The SDC files are used to constrain the physical design for each grid
+ * (CLBs, heterogeneous blocks etc.)
+ *
+ * Note that this is different from the SDC to constrain VPR Place&Route
+ * engine! These SDCs are designed for PnR to generate FPGA layouts!!!
+ *******************************************************************/
+#include <ctime>
+#include <fstream>
+
+/* Headers from vtrutil library */
+#include "vtr_log.h"
+#include "vtr_assert.h"
+#include "vtr_time.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_port.h"
+#include "openfpga_digest.h"
+#include "openfpga_side_manager.h"
+
+
+#include "openfpga_interconnect_types.h"
+#include "vpr_utils.h"
+#include "mux_utils.h"
+
+#include "openfpga_reserved_words.h"
+#include "openfpga_naming.h"
+#include "pb_type_utils.h"
+#include "pb_graph_utils.h"
+
+#include "sdc_writer_naming.h"
+#include "sdc_writer_utils.h"
+#include "pnr_sdc_grid_writer.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Print pin-to-pin timing constraints for a given interconnection
+ * at an output port of a pb_graph node
+ *******************************************************************/
+static 
+void print_pnr_sdc_constrain_pb_pin_interc_timing(std::fstream& fp,
+                                                  const ModuleManager& module_manager,
+                                                  const ModuleId& parent_module,
+                                                  t_pb_graph_pin* des_pb_graph_pin,
+                                                  t_mode* physical_mode) {
+
+  /* Validate file stream */ 
+  valid_file_stream(fp);
+
+  /* 1. identify pin interconnection type, 
+   * 2. Identify the number of fan-in (Consider interconnection edges of only selected mode)
+   * 3. Print SDC timing constraints
+   */
+  t_interconnect* cur_interc = pb_graph_pin_interc(des_pb_graph_pin, physical_mode);
+  size_t fan_in = pb_graph_pin_inputs(des_pb_graph_pin, cur_interc).size();
+  if ((nullptr == cur_interc) || (0 == fan_in)) { 
+    /* No interconnection matched */
+    return;
+  }
+
+  /* Print pin-to-pin SDC contraint here */ 
+  /* For more than one mode defined, the direct interc has more than one input_edge ,
+   * We need to find which edge is connected the pin we want
+   */
+  for (int iedge = 0; iedge < des_pb_graph_pin->num_input_edges; iedge++) {
+    if (cur_interc != des_pb_graph_pin->input_edges[iedge]->interconnect) {
+      continue;
+    }
+
+    /* Source pin, node, pb_type*/
+    t_pb_graph_pin* src_pb_graph_pin = des_pb_graph_pin->input_edges[iedge]->input_pins[0];
+    t_pb_graph_node* src_pb_graph_node = src_pb_graph_pin->parent_node;
+    /* Des pin, node, pb_type */
+    t_pb_graph_node* des_pb_graph_node  = des_pb_graph_pin->parent_node;
+
+    /* Find the src module in module manager */
+    std::string src_module_name = generate_physical_block_module_name(src_pb_graph_pin->parent_node->pb_type);
+    ModuleId src_module = module_manager.find_module(src_module_name);
+    VTR_ASSERT(true == module_manager.valid_module_id(src_module));
+
+    ModulePortId src_module_port_id = module_manager.find_module_port(src_module, generate_pb_type_port_name(src_pb_graph_pin->port));
+    VTR_ASSERT(true == module_manager.valid_module_port_id(src_module, src_module_port_id));
+
+    /* Generate the name of the des instance name 
+     * If des module is not the parent module, it is a child module.
+     * We should find the instance id 
+     */
+    std::string src_instance_name = src_module_name; 
+    if (parent_module != src_module) {
+      src_instance_name = module_manager.module_name(parent_module) + std::string("/"); 
+      /* Instance id is actually the placement index */
+      size_t instance_id = src_pb_graph_node->placement_index;
+      if (true == module_manager.instance_name(parent_module, src_module, instance_id).empty()) {  
+        src_instance_name += src_module_name; 
+        src_instance_name += "_";
+        src_instance_name += std::to_string(instance_id);
+        src_instance_name += "_";
+      } else {
+        src_instance_name += module_manager.instance_name(parent_module, src_module, instance_id);  
+      }
+    }
+
+    /* Generate src port information */
+    BasicPort src_port = module_manager.module_port(src_module, src_module_port_id);
+    src_port.set_width(src_pb_graph_pin->pin_number, src_pb_graph_pin->pin_number);
+
+    /* Find the des module in module manager */
+    std::string des_module_name = generate_physical_block_module_name(des_pb_graph_pin->parent_node->pb_type);
+    ModuleId des_module = module_manager.find_module(des_module_name);
+    VTR_ASSERT(true == module_manager.valid_module_id(des_module));
+    ModulePortId des_module_port_id = module_manager.find_module_port(des_module, generate_pb_type_port_name(des_pb_graph_pin->port));
+    VTR_ASSERT(true == module_manager.valid_module_port_id(des_module, des_module_port_id));
+
+    /* Generate the name of the des instance name 
+     * If des module is not the parent module, it is a child module.
+     * We should find the instance id 
+     */
+    std::string des_instance_name = des_module_name; 
+    if (parent_module != des_module) {
+      des_instance_name = module_manager.module_name(parent_module) + std::string("/"); 
+      /* Instance id is actually the placement index */
+      size_t instance_id = des_pb_graph_node->placement_index;
+      if (true == module_manager.instance_name(parent_module, des_module, instance_id).empty()) {  
+        des_instance_name += des_module_name; 
+        des_instance_name += "_";
+        des_instance_name += std::to_string(instance_id);
+        des_instance_name += "_";
+      } else {
+        des_instance_name += module_manager.instance_name(parent_module, des_module, instance_id);  
+      }
+    }
+
+    /* Generate des port information */
+    BasicPort des_port = module_manager.module_port(des_module, des_module_port_id);
+    des_port.set_width(des_pb_graph_pin->pin_number, des_pb_graph_pin->pin_number);
+
+    /* Print a SDC timing constraint */
+    print_pnr_sdc_constrain_max_delay(fp, 
+                                      src_instance_name, 
+                                      generate_sdc_port(src_port),
+                                      des_instance_name, 
+                                      generate_sdc_port(des_port),
+                                      des_pb_graph_pin->input_edges[iedge]->delay_max);
+  }
+}
+
+/********************************************************************
+ * Print port-to-port timing constraints which source from
+ * an output port of a pb_graph node
+ *******************************************************************/
+static 
+void print_pnr_sdc_constrain_pb_interc_timing(std::fstream& fp,
+                                              const ModuleManager& module_manager,
+                                              const ModuleId& parent_module,
+                                              t_pb_graph_node* des_pb_graph_node,
+                                              const e_circuit_pb_port_type& pb_port_type,
+                                              t_mode* physical_mode) {
+  /* Validate file stream */ 
+  valid_file_stream(fp);
+
+  switch (pb_port_type) {
+  case CIRCUIT_PB_PORT_INPUT: {
+    for (int iport = 0; iport < des_pb_graph_node->num_input_ports; ++iport) {
+      for (int ipin = 0; ipin < des_pb_graph_node->num_input_pins[iport]; ++ipin) {
+        /* If this is a idle block, we set 0 to the selected edge*/
+        /* Get the selected edge of current pin*/
+        print_pnr_sdc_constrain_pb_pin_interc_timing(fp, 
+                                                     module_manager, parent_module, 
+                                                     &(des_pb_graph_node->input_pins[iport][ipin]),
+                                                     physical_mode);
+      }
+    }
+    break;
+  }
+  case CIRCUIT_PB_PORT_OUTPUT: {
+    for (int iport = 0; iport < des_pb_graph_node->num_output_ports; ++iport) {
+      for (int ipin = 0; ipin < des_pb_graph_node->num_output_pins[iport]; ++ipin) {
+        print_pnr_sdc_constrain_pb_pin_interc_timing(fp,
+                                                     module_manager, parent_module, 
+                                                     &(des_pb_graph_node->output_pins[iport][ipin]),
+                                                     physical_mode);
+      }
+    }
+    break;
+  }
+  case CIRCUIT_PB_PORT_CLOCK: {
+    /* Do NOT constrain clock here, it should be handled by Clock Tree Synthesis */
+    break;
+  }
+  default:
+   VTR_LOGF_ERROR(__FILE__, __LINE__,
+                  "Invalid pb port type!\n");
+    exit(1);
+  }
+}
+
+/********************************************************************
+ * This function will generate a SDC file for each pb_type,
+ * constraining the pin-to-pin timing between 
+ * 1. input port of parent_pb_graph_node and input port of child_pb_graph_nodes
+ * 2. output port of parent_pb_graph_node and output port of child_pb_graph_nodes
+ * 3. output port of child_pb_graph_node and input port of child_pb_graph_nodes
+ *******************************************************************/
+static 
+void print_pnr_sdc_constrain_pb_graph_node_timing(const std::string& sdc_dir,
+                                                  const ModuleManager& module_manager,
+                                                  t_pb_graph_node* parent_pb_graph_node,
+                                                  t_mode* physical_mode) {
+
+  /* Get the pb_type definition related to the node */
+  t_pb_type* physical_pb_type = parent_pb_graph_node->pb_type; 
+  std::string pb_module_name = generate_physical_block_module_name(physical_pb_type);
+
+  /* Find the pb module in module manager */
+  ModuleId pb_module = module_manager.find_module(pb_module_name);
+  VTR_ASSERT(true == module_manager.valid_module_id(pb_module));
+
+  /* Create the file name for SDC */
+  std::string sdc_fname(sdc_dir + pb_module_name + std::string(SDC_FILE_NAME_POSTFIX));
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(sdc_fname, std::fstream::out | std::fstream::trunc);
+
+  check_file_stream(sdc_fname.c_str(), fp);
+
+  /* Generate the descriptions*/
+  print_sdc_file_header(fp, std::string("Timing constraints for Grid " + pb_module_name + " in PnR"));
+
+  /* We check output_pins of cur_pb_graph_node and its the input_edges
+   * Built the interconnections between outputs of cur_pb_graph_node and outputs of child_pb_graph_node
+   *   child_pb_graph_node.output_pins -----------------> cur_pb_graph_node.outpins
+   *                                        /|\
+   *                                         |
+   *                         input_pins,   edges,       output_pins
+   */ 
+  print_pnr_sdc_constrain_pb_interc_timing(fp,
+                                           module_manager, pb_module,
+                                           parent_pb_graph_node, 
+                                           CIRCUIT_PB_PORT_OUTPUT,
+                                           physical_mode);
+  
+  /* We check input_pins of child_pb_graph_node and its the input_edges
+   * Built the interconnections between inputs of cur_pb_graph_node and inputs of child_pb_graph_node
+   *   cur_pb_graph_node.input_pins -----------------> child_pb_graph_node.input_pins
+   *                                        /|\
+   *                                         |
+   *                         input_pins,   edges,       output_pins
+   */ 
+  for (int ipb = 0; ipb < physical_mode->num_pb_type_children; ++ipb) {
+    for (int jpb = 0; jpb < physical_mode->pb_type_children[ipb].num_pb; ++jpb) {
+      t_pb_graph_node* child_pb_graph_node = &(parent_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb][jpb]);
+      /* For each child_pb_graph_node input pins*/
+      print_pnr_sdc_constrain_pb_interc_timing(fp,
+                                               module_manager, pb_module,
+                                               child_pb_graph_node, 
+                                               CIRCUIT_PB_PORT_INPUT,
+                                               physical_mode);
+      /* Do NOT constrain clock here, it should be handled by Clock Tree Synthesis */
+    }
+  }
+  
+  /* Close file handler */
+  fp.close();
+}
+
+/********************************************************************
+ * Recursively print SDC timing constraints for a pb_type
+ * This function will generate a SDC file for each pb_type,
+ * constraining the pin-to-pin timing
+ *******************************************************************/
+static 
+void rec_print_pnr_sdc_constrain_pb_graph_timing(const std::string& sdc_dir,
+                                                 const ModuleManager& module_manager,
+                                                 const VprDeviceAnnotation& device_annotation,
+                                                 t_pb_graph_node* parent_pb_graph_node) {
+  /* Validate pb_graph node */
+  if (nullptr == parent_pb_graph_node) {
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid parent_pb_graph_node.\n");
+    exit(1);
+  }
+
+  /* Get the pb_type */
+  t_pb_type* parent_pb_type = parent_pb_graph_node->pb_type;
+
+  /* No need to constrain the primitive node */
+  if (true == is_primitive_pb_type(parent_pb_type)) {
+    return;
+  }
+
+  /* Note we only go through the graph through the physical modes. 
+   * which we build the modules 
+   */
+  t_mode* physical_mode = device_annotation.physical_mode(parent_pb_type);  
+
+  /* Write a SDC file for this pb_type */
+  print_pnr_sdc_constrain_pb_graph_node_timing(sdc_dir,
+                                               module_manager,
+                                               parent_pb_graph_node,
+                                               physical_mode);
+
+  /* Go recursively to the lower level in the pb_graph
+   * Note that we assume a full hierarchical P&R, we will only visit pb_graph_node of unique pb_type 
+   */
+  for (int ipb = 0; ipb < physical_mode->num_pb_type_children; ++ipb) {
+    rec_print_pnr_sdc_constrain_pb_graph_timing(sdc_dir, module_manager, 
+                                                device_annotation,
+                                                &(parent_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb][0]));
+  }
+}
+
+/********************************************************************
+ * Top-level function to print timing constraints for pb_types
+ *******************************************************************/
+void print_pnr_sdc_constrain_grid_timing(const std::string& sdc_dir,
+                                         const DeviceContext& device_ctx,
+                                         const VprDeviceAnnotation& device_annotation,
+                                         const ModuleManager& module_manager) {
+
+  /* Start time count */
+  vtr::ScopedStartFinishTimer timer("Generating SDC for constraining grid timing for P&R flow");
+
+  for (const t_physical_tile_type& physical_tile : device_ctx.physical_tile_types) {
+    /* Bypass empty type or nullptr */
+    if (true == is_empty_type(&physical_tile)) {
+      continue;
+    } else {
+      VTR_ASSERT(1 == physical_tile.equivalent_sites.size());
+      t_pb_graph_node* pb_graph_head = physical_tile.equivalent_sites[0]->pb_graph_head;
+      if (nullptr == pb_graph_head) {
+        continue;
+      }
+      /* Special for I/O block, generate one module for each border side */
+      rec_print_pnr_sdc_constrain_pb_graph_timing(sdc_dir, module_manager, 
+                                                  device_annotation,
+                                                  pb_graph_head);
+    }
+  }
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.h b/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.h
new file mode 100644
index 000000000..91c1b7030
--- /dev/null
+++ b/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.h
@@ -0,0 +1,27 @@
+#ifndef PNR_SDC_GRID_WRITER_H
+#define PNR_SDC_GRID_WRITER_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <string>
+#include <vector>
+#include "vpr_context.h"
+#include "vpr_device_annotation.h"
+#include "module_manager.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void print_pnr_sdc_constrain_grid_timing(const std::string& sdc_dir,
+                                         const DeviceContext& device_ctx,
+                                         const VprDeviceAnnotation& device_annotation,
+                                         const ModuleManager& module_manager);
+
+} /* end namespace openfpga */
+
+#endif

From 89c51b70e353543ccbcd5d477988a5516e2685f0 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 28 Feb 2020 09:48:58 -0700
Subject: [PATCH 229/645] split sdc option into two categories which will be
 called by different commands

---
 openfpga/src/fpga_sdc/analysis_sdc_option.cpp | 39 ++++++++++++++
 openfpga/src/fpga_sdc/analysis_sdc_option.h   | 30 +++++++++++
 .../{sdc_option.cpp => pnr_sdc_option.cpp}    | 52 +++++++------------
 .../{sdc_option.h => pnr_sdc_option.h}        | 13 ++---
 4 files changed, 94 insertions(+), 40 deletions(-)
 create mode 100644 openfpga/src/fpga_sdc/analysis_sdc_option.cpp
 create mode 100644 openfpga/src/fpga_sdc/analysis_sdc_option.h
 rename openfpga/src/fpga_sdc/{sdc_option.cpp => pnr_sdc_option.cpp} (60%)
 rename openfpga/src/fpga_sdc/{sdc_option.h => pnr_sdc_option.h} (85%)

diff --git a/openfpga/src/fpga_sdc/analysis_sdc_option.cpp b/openfpga/src/fpga_sdc/analysis_sdc_option.cpp
new file mode 100644
index 000000000..444e73fb4
--- /dev/null
+++ b/openfpga/src/fpga_sdc/analysis_sdc_option.cpp
@@ -0,0 +1,39 @@
+/********************************************************************
+ * Member functions for a data structure which includes all the options for the SDC generator
+ ********************************************************************/
+#include "analysis_sdc_option.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Public Constructors
+ ********************************************************************/
+AnalysisSdcOption::AnalysisSdcOption(const std::string& sdc_dir) {
+  sdc_dir_ = sdc_dir;
+  generate_sdc_analysis_ = false;
+}
+
+/********************************************************************
+ * Public accessors
+ ********************************************************************/
+std::string AnalysisSdcOption::sdc_dir() const {
+  return sdc_dir_;
+}
+
+bool AnalysisSdcOption::generate_sdc_analysis() const {
+  return generate_sdc_analysis_;
+}
+
+/********************************************************************
+ * Public mutators
+ ********************************************************************/
+void AnalysisSdcOption::set_sdc_dir(const std::string& sdc_dir) {
+  sdc_dir_ = sdc_dir;
+}
+
+void AnalysisSdcOption::set_generate_sdc_analysis(const bool& generate_sdc_analysis) {
+  generate_sdc_analysis_ = generate_sdc_analysis;
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_sdc/analysis_sdc_option.h b/openfpga/src/fpga_sdc/analysis_sdc_option.h
new file mode 100644
index 000000000..514e5e81c
--- /dev/null
+++ b/openfpga/src/fpga_sdc/analysis_sdc_option.h
@@ -0,0 +1,30 @@
+#ifndef ANALYSIS_SDC_OPTION_H
+#define ANALYSIS_SDC_OPTION_H
+
+/********************************************************************
+ * A data structure to include all the options for the SDC generator
+ * in purpose of analyzing users' implementations
+ ********************************************************************/
+
+#include <string>
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+class AnalysisSdcOption {
+  public: /* Public Constructors */
+    AnalysisSdcOption(const std::string& sdc_dir);
+  public: /* Public accessors */
+    std::string sdc_dir() const;
+    bool generate_sdc_analysis() const;
+  public: /* Public mutators */
+    void set_sdc_dir(const std::string& sdc_dir);
+    void set_generate_sdc_analysis(const bool& generate_sdc_analysis);
+  private: /* Internal data */
+    std::string sdc_dir_;
+    bool generate_sdc_analysis_; 
+};
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/fpga_sdc/sdc_option.cpp b/openfpga/src/fpga_sdc/pnr_sdc_option.cpp
similarity index 60%
rename from openfpga/src/fpga_sdc/sdc_option.cpp
rename to openfpga/src/fpga_sdc/pnr_sdc_option.cpp
index 4b8c4666f..3a3906b50 100644
--- a/openfpga/src/fpga_sdc/sdc_option.cpp
+++ b/openfpga/src/fpga_sdc/pnr_sdc_option.cpp
@@ -1,7 +1,7 @@
 /********************************************************************
  * Member functions for a data structure which includes all the options for the SDC generator
  ********************************************************************/
-#include "sdc_option.h"
+#include "pnr_sdc_option.h"
 
 /* begin namespace openfpga */
 namespace openfpga {
@@ -9,7 +9,7 @@ namespace openfpga {
 /********************************************************************
  * Public Constructors
  ********************************************************************/
-SdcOption::SdcOption(const std::string& sdc_dir) {
+PnrSdcOption::PnrSdcOption(const std::string& sdc_dir) {
   sdc_dir_ = sdc_dir;
   constrain_global_port_ = false;
   constrain_grid_ = false;
@@ -23,15 +23,11 @@ SdcOption::SdcOption(const std::string& sdc_dir) {
 /********************************************************************
  * Public accessors
  ********************************************************************/
-std::string SdcOption::sdc_dir() const {
+std::string PnrSdcOption::sdc_dir() const {
   return sdc_dir_;
 }
 
-bool SdcOption::generate_sdc() const {
-  return generate_sdc_pnr() && generate_sdc_analysis_;
-}
-
-bool SdcOption::generate_sdc_pnr() const {
+bool PnrSdcOption::generate_sdc_pnr() const {
   return constrain_global_port_ 
       || constrain_grid_
       || constrain_sb_
@@ -41,46 +37,42 @@ bool SdcOption::generate_sdc_pnr() const {
       || constrain_switch_block_outputs_;
 }
 
-bool SdcOption::generate_sdc_analysis() const {
-  return generate_sdc_analysis_;
-}
-
-bool SdcOption::constrain_global_port() const {
+bool PnrSdcOption::constrain_global_port() const {
   return constrain_global_port_;
 }
 
-bool SdcOption::constrain_grid() const {
+bool PnrSdcOption::constrain_grid() const {
   return constrain_grid_;
 }
 
-bool SdcOption::constrain_sb() const {
+bool PnrSdcOption::constrain_sb() const {
   return constrain_sb_;
 }
 
-bool SdcOption::constrain_cb() const {
+bool PnrSdcOption::constrain_cb() const {
   return constrain_cb_;
 }
 
-bool SdcOption::constrain_configurable_memory_outputs() const {
+bool PnrSdcOption::constrain_configurable_memory_outputs() const {
   return constrain_configurable_memory_outputs_;
 }
 
-bool SdcOption::constrain_routing_multiplexer_outputs() const {
+bool PnrSdcOption::constrain_routing_multiplexer_outputs() const {
   return constrain_routing_multiplexer_outputs_;
 }
 
-bool SdcOption::constrain_switch_block_outputs() const {
+bool PnrSdcOption::constrain_switch_block_outputs() const {
   return constrain_switch_block_outputs_;
 }
 
 /********************************************************************
  * Public mutators
  ********************************************************************/
-void SdcOption::set_sdc_dir(const std::string& sdc_dir) {
+void PnrSdcOption::set_sdc_dir(const std::string& sdc_dir) {
   sdc_dir_ = sdc_dir;
 }
 
-void SdcOption::set_generate_sdc_pnr(const bool& generate_sdc_pnr) {
+void PnrSdcOption::set_generate_sdc_pnr(const bool& generate_sdc_pnr) {
   constrain_global_port_ = generate_sdc_pnr;
   constrain_grid_ = generate_sdc_pnr;
   constrain_sb_ = generate_sdc_pnr;
@@ -90,35 +82,31 @@ void SdcOption::set_generate_sdc_pnr(const bool& generate_sdc_pnr) {
   constrain_switch_block_outputs_ = generate_sdc_pnr;
 }
 
-void SdcOption::set_generate_sdc_analysis(const bool& generate_sdc_analysis) {
-  generate_sdc_analysis_ = generate_sdc_analysis;
-}
-
-void SdcOption::set_constrain_global_port(const bool& constrain_global_port) {
+void PnrSdcOption::set_constrain_global_port(const bool& constrain_global_port) {
   constrain_global_port_ = constrain_global_port;
 }
 
-void SdcOption::set_constrain_grid(const bool& constrain_grid) {
+void PnrSdcOption::set_constrain_grid(const bool& constrain_grid) {
   constrain_grid_ = constrain_grid;
 }
 
-void SdcOption::set_constrain_sb(const bool& constrain_sb) {
+void PnrSdcOption::set_constrain_sb(const bool& constrain_sb) {
   constrain_sb_ = constrain_sb;
 }
 
-void SdcOption::set_constrain_cb(const bool& constrain_cb) {
+void PnrSdcOption::set_constrain_cb(const bool& constrain_cb) {
   constrain_cb_ = constrain_cb;
 }
 
-void SdcOption::set_constrain_configurable_memory_outputs(const bool& constrain_config_mem_outputs) {
+void PnrSdcOption::set_constrain_configurable_memory_outputs(const bool& constrain_config_mem_outputs) {
   constrain_configurable_memory_outputs_ = constrain_config_mem_outputs;
 }
 
-void SdcOption::set_constrain_routing_multiplexer_outputs(const bool& constrain_routing_mux_outputs) {
+void PnrSdcOption::set_constrain_routing_multiplexer_outputs(const bool& constrain_routing_mux_outputs) {
   constrain_routing_multiplexer_outputs_ = constrain_routing_mux_outputs;
 }
 
-void SdcOption::set_constrain_switch_block_outputs(const bool& constrain_sb_outputs) {
+void PnrSdcOption::set_constrain_switch_block_outputs(const bool& constrain_sb_outputs) {
   constrain_switch_block_outputs_ = constrain_sb_outputs;
 }
 
diff --git a/openfpga/src/fpga_sdc/sdc_option.h b/openfpga/src/fpga_sdc/pnr_sdc_option.h
similarity index 85%
rename from openfpga/src/fpga_sdc/sdc_option.h
rename to openfpga/src/fpga_sdc/pnr_sdc_option.h
index d53c08e94..a485a1946 100644
--- a/openfpga/src/fpga_sdc/sdc_option.h
+++ b/openfpga/src/fpga_sdc/pnr_sdc_option.h
@@ -1,8 +1,9 @@
-#ifndef SDC_OPTION_H
-#define SDC_OPTION_H
+#ifndef PNR_SDC_OPTION_H
+#define PNR_SDC_OPTION_H
 
 /********************************************************************
  * A data structure to include all the options for the SDC generator
+ * in purpose of constraining physical design of FPGA fabric in back-end flow
  ********************************************************************/
 
 #include <string>
@@ -10,14 +11,12 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-class SdcOption {
+class PnrSdcOption {
   public: /* Public Constructors */
-    SdcOption(const std::string& sdc_dir);
+    PnrSdcOption(const std::string& sdc_dir);
   public: /* Public accessors */
     std::string sdc_dir() const;
-    bool generate_sdc() const;
     bool generate_sdc_pnr() const;
-    bool generate_sdc_analysis() const;
     bool constrain_global_port() const;
     bool constrain_grid() const;
     bool constrain_sb() const;
@@ -28,7 +27,6 @@ class SdcOption {
   public: /* Public mutators */
     void set_sdc_dir(const std::string& sdc_dir);
     void set_generate_sdc_pnr(const bool& generate_sdc_pnr);
-    void set_generate_sdc_analysis(const bool& generate_sdc_analysis);
     void set_constrain_global_port(const bool& constrain_global_port);
     void set_constrain_grid(const bool& constrain_grid);
     void set_constrain_sb(const bool& constrain_sb);
@@ -45,7 +43,6 @@ class SdcOption {
     bool constrain_configurable_memory_outputs_;
     bool constrain_routing_multiplexer_outputs_;
     bool constrain_switch_block_outputs_;
-    bool generate_sdc_analysis_; 
 };
 
 } /* end namespace openfpga */

From e45fa18c4ced231d17390e0e1b5fae655b4614bb Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 28 Feb 2020 10:06:35 -0700
Subject: [PATCH 230/645] adapt PnR SDC writer

---
 openfpga/src/fpga_sdc/pnr_sdc_writer.cpp | 432 +++++++++++++++++++++++
 openfpga/src/fpga_sdc/pnr_sdc_writer.h   |  37 ++
 2 files changed, 469 insertions(+)
 create mode 100644 openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
 create mode 100644 openfpga/src/fpga_sdc/pnr_sdc_writer.h

diff --git a/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
new file mode 100644
index 000000000..e418bc620
--- /dev/null
+++ b/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
@@ -0,0 +1,432 @@
+/********************************************************************
+ * This file includes functions that print SDC (Synopsys Design Constraint) 
+ * files in physical design tools, i.e., Place & Route (PnR) tools
+ * The SDC files are used to constrain the physical design for each module
+ * in FPGA fabric, such as Configurable Logic Blocks (CLBs), 
+ * Heterogeneous blocks, Switch Blocks (SBs) and Connection Blocks (CBs)
+ *
+ * Note that this is different from the SDC to constrain VPR Place&Route
+ * engine! These SDCs are designed for PnR to generate FPGA layouts!!!
+ *******************************************************************/
+#include <ctime>
+#include <fstream>
+#include <iomanip>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_time.h"
+#include "vtr_log.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_port.h"
+#include "openfpga_digest.h"
+
+#include "mux_utils.h"
+
+#include "openfpga_naming.h"
+
+#include "sdc_writer_naming.h"
+#include "sdc_writer_utils.h"
+#include "sdc_memory_utils.h"
+#include "pnr_sdc_routing_writer.h"
+#include "pnr_sdc_grid_writer.h"
+#include "pnr_sdc_writer.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Local variables
+ *******************************************************************/
+constexpr float SDC_FIXED_PROG_CLOCK_PERIOD = 100;
+constexpr float SDC_FIXED_CLOCK_PERIOD = 10;
+
+/********************************************************************
+ * Print a SDC file to constrain the global ports of FPGA fabric
+ * in particular clock ports
+ * 
+ * For programming clock, we give a fixed period, while for operating
+ * clock, we constrain with critical path delay 
+ *******************************************************************/
+static 
+void print_pnr_sdc_global_ports(const std::string& sdc_dir, 
+                                const float& critical_path_delay,
+                                const CircuitLibrary& circuit_lib,
+                                const std::vector<CircuitPortId>& global_ports) {
+
+  /* Create the file name for Verilog netlist */
+  std::string sdc_fname(sdc_dir + std::string(SDC_GLOBAL_PORTS_FILE_NAME));
+
+  /* Start time count */
+  std::string timer_message = std::string("Generating SDC for constraining clocks for P&R flow '") + sdc_fname + std::string("'");
+  vtr::ScopedStartFinishTimer timer(timer_message);
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(sdc_fname, std::fstream::out | std::fstream::trunc);
+
+  check_file_stream(sdc_fname.c_str(), fp);
+
+  /* Generate the descriptions*/
+  print_sdc_file_header(fp, std::string("Clock contraints for PnR"));
+
+  /* Get clock port from the global port */
+  for (const CircuitPortId& clock_port : global_ports) {
+    if (CIRCUIT_MODEL_PORT_CLOCK != circuit_lib.port_type(clock_port)) {
+      continue;
+    }
+    /* Reach here, it means a clock port and we need print constraints */
+    float clock_period = critical_path_delay; 
+
+    /* For programming clock, we give a fixed period */
+    if (true == circuit_lib.port_is_prog(clock_port)) {
+      clock_period = SDC_FIXED_PROG_CLOCK_PERIOD;
+      /* Print comments */
+      fp << "##################################################" << std::endl; 
+      fp << "# Create programmable clock                       " << std::endl;
+      fp << "##################################################" << std::endl; 
+    } else {
+      /* Print comments */
+      fp << "##################################################" << std::endl; 
+      fp << "# Create clock                                    " << std::endl;
+      fp << "##################################################" << std::endl; 
+    }
+
+    for (const size_t& pin : circuit_lib.pins(clock_port)) {
+      BasicPort port_to_constrain(circuit_lib.port_prefix(clock_port), pin, pin);
+
+      fp << "create_clock ";
+      fp << generate_sdc_port(port_to_constrain) << "-period ";
+      fp << std::setprecision(10) << clock_period;
+      fp << " -waveform {0 ";
+      fp << std::setprecision(10) << clock_period / 2;
+      fp << "}" << std::endl;
+
+      fp << std::endl;
+    }
+  }
+
+  /* For non-clock port from the global port: give a fixed period */
+  for (const CircuitPortId& global_port : global_ports) {
+    if (CIRCUIT_MODEL_PORT_CLOCK == circuit_lib.port_type(global_port)) {
+      continue;
+    }
+
+    /* Print comments */
+    fp << "##################################################" << std::endl; 
+    fp << "# Constrain other global ports                    " << std::endl;
+    fp << "##################################################" << std::endl; 
+
+    /* Reach here, it means a non-clock global port and we need print constraints */
+    float clock_period = SDC_FIXED_CLOCK_PERIOD; 
+    for (const size_t& pin : circuit_lib.pins(global_port)) {
+      BasicPort port_to_constrain(circuit_lib.port_prefix(global_port), pin, pin);
+      fp << "create_clock ";
+      fp << generate_sdc_port(port_to_constrain) << "-period ";
+      fp << std::setprecision(10) << clock_period;
+      fp << " -waveform {0 ";
+      fp << std::setprecision(10) << clock_period / 2;
+      fp << "} ";
+      fp << "[list [get_ports { " << generate_sdc_port(port_to_constrain) << "}]]" << std::endl;
+
+      fp << "set_drive 0 " << generate_sdc_port(port_to_constrain) << std::endl;
+     
+      fp << std::endl;
+    }
+  }
+
+  /* Close file handler */
+  fp.close();
+}
+
+/********************************************************************
+ * Break combinational loops in FPGA fabric, which mainly come from
+ * configurable memory cells. 
+ * To handle this, we disable the outputs of memory cells
+ *******************************************************************/
+static 
+void print_pnr_sdc_constrain_configurable_memory_outputs(const std::string& sdc_dir,
+                                                         const ModuleManager& module_manager,
+                                                         const ModuleId& top_module) {
+
+  /* Create the file name for Verilog netlist */
+  std::string sdc_fname(sdc_dir + std::string(SDC_DISABLE_CONFIG_MEM_OUTPUTS_FILE_NAME));
+
+  /* Start time count */
+  std::string timer_message = std::string("Generating SDC to disable configurable memory outputs for P&R flow '") + sdc_fname + std::string("'");
+  vtr::ScopedStartFinishTimer timer(timer_message);
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(sdc_fname, std::fstream::out | std::fstream::trunc);
+
+  check_file_stream(sdc_fname.c_str(), fp);
+
+  /* Generate the descriptions*/
+  print_sdc_file_header(fp, std::string("Disable configurable memory outputs for PnR"));
+
+  /* Go recursively in the module manager, starting from the top-level module: instance id of the top-level module is 0 by default */
+  rec_print_pnr_sdc_disable_configurable_memory_module_output(fp, module_manager, top_module, 
+                                                              format_dir_path(module_manager.module_name(top_module)));
+
+  /* Close file handler */
+  fp.close();
+}
+
+/********************************************************************
+ * Break combinational loops in FPGA fabric, which mainly come from 
+ * loops of multiplexers.
+ * To handle this, we disable the timing at outputs of routing multiplexers
+ *******************************************************************/
+static 
+void print_sdc_disable_routing_multiplexer_outputs(const std::string& sdc_dir,
+                                                   const MuxLibrary& mux_lib,
+                                                   const CircuitLibrary& circuit_lib,
+                                                   const ModuleManager& module_manager) {
+  /* Create the file name for Verilog netlist */
+  std::string sdc_fname(sdc_dir + std::string(SDC_DISABLE_MUX_OUTPUTS_FILE_NAME));
+
+  /* Start time count */
+  std::string timer_message = std::string("Generating SDC to disable routing multiplexer outputs for P&R flow '") + sdc_fname + std::string("'");
+  vtr::ScopedStartFinishTimer timer(timer_message);
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(sdc_fname, std::fstream::out | std::fstream::trunc);
+
+  check_file_stream(sdc_fname.c_str(), fp);
+
+  /* Generate the descriptions*/
+  print_sdc_file_header(fp, std::string("Disable routing multiplexer outputs for PnR"));
+
+  /* Iterate over the MUX modules */
+  for (const MuxId& mux_id : mux_lib.muxes()) {
+    const CircuitModelId& mux_model = mux_lib.mux_circuit_model(mux_id);
+    
+    /* Skip LUTs, we only care about multiplexers here */
+    if (CIRCUIT_MODEL_MUX != circuit_lib.model_type(mux_model)) {
+      continue;
+    }
+
+    const MuxGraph& mux_graph = mux_lib.mux_graph(mux_id);
+    std::string mux_module_name = generate_mux_subckt_name(circuit_lib, mux_model, 
+                                                           find_mux_num_datapath_inputs(circuit_lib, mux_model, mux_graph.num_inputs()), 
+                                                           std::string(""));
+    /* Find the module name in module manager */
+    ModuleId mux_module = module_manager.find_module(mux_module_name);
+    VTR_ASSERT(true == module_manager.valid_module_id(mux_module));
+     
+    /* Disable the timing for the output ports */ 
+    for (const BasicPort& output_port : module_manager.module_ports_by_type(mux_module, ModuleManager::MODULE_OUTPUT_PORT)) {
+      fp << "set_disable_timing [get_pins -filter \"name =~ " << output_port.get_name() << "*\" ";
+      fp << "-of [get_cells -hier -filter \"ref_lib_cell_name == " << mux_module_name << "\"]]" << std::endl;
+      fp << std::endl;
+    }
+  }
+
+  /* Close file handler */
+  fp.close();
+}
+
+/********************************************************************
+ * Break combinational loops in FPGA fabric, which mainly come from 
+ * loops of multiplexers.
+ * To handle this, we disable the timing at outputs of Switch blocks
+ * This function is designed for flatten routing hierarchy
+ *******************************************************************/
+static 
+void print_pnr_sdc_flatten_routing_disable_switch_block_outputs(const std::string& sdc_dir,
+                                                                const ModuleManager& module_manager,
+                                                                const DeviceRRGSB& device_rr_gsb) {
+  /* Create the file name for Verilog netlist */
+  std::string sdc_fname(sdc_dir + std::string(SDC_DISABLE_SB_OUTPUTS_FILE_NAME));
+
+  /* Start time count */
+  std::string timer_message = std::string("Generating SDC to disable switch block outputs for P&R flow '") + sdc_fname + std::string("'");
+  vtr::ScopedStartFinishTimer timer(timer_message);
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(sdc_fname, std::fstream::out | std::fstream::trunc);
+
+  check_file_stream(sdc_fname.c_str(), fp);
+
+  /* Generate the descriptions*/
+  print_sdc_file_header(fp, std::string("Disable Switch Block outputs for PnR"));
+
+  /* Get the range of SB array */
+  vtr::Point<size_t> sb_range = device_rr_gsb.get_gsb_range();
+  /* Go for each SB */
+  for (size_t ix = 0; ix < sb_range.x(); ++ix) {
+    for (size_t iy = 0; iy < sb_range.y(); ++iy) {
+      const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
+
+      if (false == rr_gsb.is_sb_exist()) {
+        continue;
+      }
+
+      vtr::Point<size_t> gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
+      std::string sb_instance_name = generate_switch_block_module_name(gsb_coordinate); 
+
+      ModuleId sb_module = module_manager.find_module(sb_instance_name);
+      VTR_ASSERT(true == module_manager.valid_module_id(sb_module));
+
+      /* Disable the outputs of the module */
+      for (const BasicPort& output_port : module_manager.module_ports_by_type(sb_module, ModuleManager::MODULE_OUTPUT_PORT)) {
+        fp << "set_disable_timing " << sb_instance_name << "/" << output_port.get_name() << std::endl;
+        fp << std::endl;
+      }
+    }
+  }
+  
+  /* Close file handler */
+  fp.close();
+}
+
+/********************************************************************
+ * Break combinational loops in FPGA fabric, which mainly come from 
+ * loops of multiplexers.
+ * To handle this, we disable the timing at outputs of Switch blocks
+ * This function is designed for compact routing hierarchy
+ *******************************************************************/
+static 
+void print_pnr_sdc_compact_routing_disable_switch_block_outputs(const std::string& sdc_dir,
+                                                                const ModuleManager& module_manager,
+                                                                const ModuleId& top_module,
+                                                                const DeviceRRGSB& device_rr_gsb) {
+  /* Create the file name for Verilog netlist */
+  std::string sdc_fname(sdc_dir + std::string(SDC_DISABLE_SB_OUTPUTS_FILE_NAME));
+
+  /* Start time count */
+  std::string timer_message = std::string("Generating SDC to disable switch block outputs for P&R flow '") + sdc_fname + std::string("'");
+  vtr::ScopedStartFinishTimer timer(timer_message);
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(sdc_fname, std::fstream::out | std::fstream::trunc);
+
+  check_file_stream(sdc_fname.c_str(), fp);
+
+  /* Generate the descriptions*/
+  print_sdc_file_header(fp, std::string("Disable Switch Block outputs for PnR"));
+
+  /* Build unique switch block modules */
+  for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_module(); ++isb) {
+    const RRGSB& rr_gsb = device_rr_gsb.get_sb_unique_module(isb);
+    vtr::Point<size_t> gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
+    std::string sb_module_name = generate_switch_block_module_name(gsb_coordinate); 
+
+    ModuleId sb_module = module_manager.find_module(sb_module_name);
+    VTR_ASSERT(true == module_manager.valid_module_id(sb_module));
+
+    /* Find all the instances in the top-level module */
+    for (const size_t& instance_id : module_manager.child_module_instances(top_module, sb_module)) {
+      std::string sb_instance_name = module_manager.instance_name(top_module, sb_module, instance_id);
+      /* Disable the outputs of the module */
+      for (const BasicPort& output_port : module_manager.module_ports_by_type(sb_module, ModuleManager::MODULE_OUTPUT_PORT)) {
+        fp << "set_disable_timing " << sb_instance_name << "/" << output_port.get_name() << std::endl;
+        fp << std::endl;
+      }
+    }
+  }
+  
+  /* Close file handler */
+  fp.close();
+}
+
+/********************************************************************
+ * Top-level function to print a number of SDC files in different purpose
+ * This function will generate files upon the options provided by users
+ * 1. Design constraints for CLBs
+ * 2. Design constraints for Switch Blocks
+ * 3. Design constraints for Connection Blocks 
+ * 4. Design constraints for breaking the combinational loops in FPGA fabric
+ *******************************************************************/
+void print_pnr_sdc(const PnrSdcOption& sdc_options,
+                   const float& critical_path_delay,
+                   const DeviceContext& device_ctx,
+                   const VprDeviceAnnotation& device_annotation,
+                   const DeviceRRGSB& device_rr_gsb,
+                   const ModuleManager& module_manager,
+                   const MuxLibrary& mux_lib,
+                   const CircuitLibrary& circuit_lib,
+                   const std::vector<CircuitPortId>& global_ports,
+                   const bool& compact_routing_hierarchy) {
+  
+  /* Constrain global ports */
+  if (true == sdc_options.constrain_global_port()) {
+    print_pnr_sdc_global_ports(sdc_options.sdc_dir(), critical_path_delay, circuit_lib, global_ports);
+  }
+
+  std::string top_module_name = generate_fpga_top_module_name();
+  ModuleId top_module = module_manager.find_module(top_module_name);
+  VTR_ASSERT(true == module_manager.valid_module_id(top_module));
+
+  /* Output Design Constraints to disable outputs of memory cells */
+  if (true == sdc_options.constrain_configurable_memory_outputs()) {
+    print_pnr_sdc_constrain_configurable_memory_outputs(sdc_options.sdc_dir(), module_manager, top_module); 
+  } 
+
+  /* Break loops from Multiplexer Output */
+  if (true == sdc_options.constrain_routing_multiplexer_outputs()) {
+    print_sdc_disable_routing_multiplexer_outputs(sdc_options.sdc_dir(),
+                                                  mux_lib, circuit_lib,
+                                                  module_manager);
+  }
+
+  /* Break loops from any SB output */
+  if (true == sdc_options.constrain_switch_block_outputs()) {
+    if (true == compact_routing_hierarchy) {
+      print_pnr_sdc_compact_routing_disable_switch_block_outputs(sdc_options.sdc_dir(),
+                                                                 module_manager, top_module,
+                                                                 device_rr_gsb);
+    } else {
+      VTR_ASSERT_SAFE (false == compact_routing_hierarchy);
+      print_pnr_sdc_flatten_routing_disable_switch_block_outputs(sdc_options.sdc_dir(),
+                                                                 module_manager,
+                                                                 device_rr_gsb);
+    }
+  }
+
+  /* Output routing constraints for Switch Blocks */
+  if (true == sdc_options.constrain_sb()) {
+    if (true == compact_routing_hierarchy) {
+      print_pnr_sdc_compact_routing_constrain_sb_timing(sdc_options.sdc_dir(),
+                                                        module_manager,
+                                                        device_ctx.rr_graph,
+                                                        device_rr_gsb);
+    } else {
+	  VTR_ASSERT_SAFE (false == compact_routing_hierarchy);
+      print_pnr_sdc_flatten_routing_constrain_sb_timing(sdc_options.sdc_dir(),
+                                                        module_manager,
+                                                        device_ctx.rr_graph,
+                                                        device_rr_gsb);
+    }
+  }
+
+  /* Output routing constraints for Connection Blocks */
+  if (true == sdc_options.constrain_cb()) {
+    if (true == compact_routing_hierarchy) {
+      print_pnr_sdc_compact_routing_constrain_cb_timing(sdc_options.sdc_dir(),
+                                                        module_manager,
+                                                        device_ctx.rr_graph,
+                                                        device_rr_gsb);
+    } else {
+	  VTR_ASSERT_SAFE (false == compact_routing_hierarchy);
+      print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_options.sdc_dir(),
+                                                        module_manager, 
+                                                        device_ctx.rr_graph,
+                                                        device_rr_gsb);
+    }
+  }
+
+  /* Output Timing constraints for Programmable blocks */
+  if (true == sdc_options.constrain_grid()) {
+    print_pnr_sdc_constrain_grid_timing(sdc_options.sdc_dir(),
+                                        device_ctx,
+                                        device_annotation,
+                                        module_manager);
+  }
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_writer.h b/openfpga/src/fpga_sdc/pnr_sdc_writer.h
new file mode 100644
index 000000000..cdadbf19d
--- /dev/null
+++ b/openfpga/src/fpga_sdc/pnr_sdc_writer.h
@@ -0,0 +1,37 @@
+#ifndef PNR_SDC_WRITER_H
+#define PNR_SDC_WRITER_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <string>
+#include <vector>
+#include "vpr_context.h"
+#include "vpr_device_annotation.h"
+#include "device_rr_gsb.h"
+#include "module_manager.h"
+#include "mux_library.h"
+#include "circuit_library.h"
+#include "pnr_sdc_option.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void print_pnr_sdc(const PnrSdcOption& sdc_options,
+                   const float& critical_path_delay,
+                   const DeviceContext& device_ctx,
+                   const VprDeviceAnnotation& device_annotation,
+                   const DeviceRRGSB& device_rr_gsb,
+                   const ModuleManager& module_manager,
+                   const MuxLibrary& mux_lib,
+                   const CircuitLibrary& circuit_lib,
+                   const std::vector<CircuitPortId>& global_ports,
+                   const bool& compact_routing_hierarchy);
+
+} /* end namespace openfpga */
+
+#endif

From 092e10afda7c2e2496b638220684bbc2422489db Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 28 Feb 2020 11:14:50 -0700
Subject: [PATCH 231/645] bring pnr sdc generator online and fixed minor bugs
 in bitstream writing

---
 openfpga/src/base/openfpga_bitstream.cpp      |  8 ++
 openfpga/src/base/openfpga_sdc.cpp            | 80 +++++++++++++++++++
 openfpga/src/base/openfpga_sdc.h              | 23 ++++++
 openfpga/src/base/openfpga_sdc_command.cpp    | 79 ++++++++++++++++++
 openfpga/src/base/openfpga_sdc_command.h      | 21 +++++
 openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp |  2 +-
 .../src/fpga_sdc/pnr_sdc_routing_writer.cpp   |  8 +-
 openfpga/src/fpga_sdc/pnr_sdc_writer.cpp      | 10 +--
 openfpga/src/main.cpp                         |  4 +
 openfpga/test_script/s298_k6_frac.openfpga    | 13 ++-
 10 files changed, 236 insertions(+), 12 deletions(-)
 create mode 100644 openfpga/src/base/openfpga_sdc.cpp
 create mode 100644 openfpga/src/base/openfpga_sdc.h
 create mode 100644 openfpga/src/base/openfpga_sdc_command.cpp
 create mode 100644 openfpga/src/base/openfpga_sdc_command.h

diff --git a/openfpga/src/base/openfpga_bitstream.cpp b/openfpga/src/base/openfpga_bitstream.cpp
index 08fa7bf16..e732dee92 100644
--- a/openfpga/src/base/openfpga_bitstream.cpp
+++ b/openfpga/src/base/openfpga_bitstream.cpp
@@ -5,6 +5,9 @@
 #include "vtr_time.h"
 #include "vtr_log.h"
 
+/* Headers from openfpgautil library */
+#include "openfpga_digest.h"
+
 #include "build_device_bitstream.h"
 #include "bitstream_writer.h"
 #include "build_fabric_bitstream.h"
@@ -30,6 +33,11 @@ void fpga_bitstream(OpenfpgaContext& openfpga_ctx,
                                                                     cmd_context.option_enable(cmd, opt_verbose));
 
   if (true == cmd_context.option_enable(cmd, opt_file)) {
+    std::string src_dir_path = find_path_dir_name(cmd_context.option_value(cmd, opt_file));
+
+    /* Create directories */
+    create_dir_path(src_dir_path.c_str());
+
     write_arch_independent_bitstream_to_xml_file(openfpga_ctx.bitstream_manager(),
                                                  cmd_context.option_value(cmd, opt_file));
   }
diff --git a/openfpga/src/base/openfpga_sdc.cpp b/openfpga/src/base/openfpga_sdc.cpp
new file mode 100644
index 000000000..4fce8d552
--- /dev/null
+++ b/openfpga/src/base/openfpga_sdc.cpp
@@ -0,0 +1,80 @@
+/********************************************************************
+ * This file includes functions to compress the hierachy of routing architecture
+ *******************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_time.h"
+#include "vtr_log.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_digest.h"
+
+#include "circuit_library_utils.h"
+#include "pnr_sdc_writer.h"
+#include "openfpga_sdc.h"
+
+/* Include global variables of VPR */
+#include "globals.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * A wrapper function to call the PnR SDC generator of FPGA-SDC
+ *******************************************************************/
+void write_pnr_sdc(OpenfpgaContext& openfpga_ctx,
+                   const Command& cmd, const CommandContext& cmd_context) {
+
+  CommandOptionId opt_output_dir = cmd.option("file");
+  CommandOptionId opt_constrain_global_port = cmd.option("constrain_global_port");
+  CommandOptionId opt_constrain_grid = cmd.option("constrain_grid");
+  CommandOptionId opt_constrain_sb = cmd.option("constrain_sb");
+  CommandOptionId opt_constrain_cb = cmd.option("constrain_cb");
+  CommandOptionId opt_constrain_configurable_memory_outputs = cmd.option("constrain_configurable_memory_outputs");
+  CommandOptionId opt_constrain_routing_multiplexer_outputs = cmd.option("constrain_routing_multiplexer_outputs");
+  CommandOptionId opt_constrain_switch_block_outputs = cmd.option("constrain_switch_block_outputs");
+
+  /* This is an intermediate data structure which is designed to modularize the FPGA-SDC
+   * Keep it independent from any other outside data structures
+   */
+  std::string sdc_dir_path = format_dir_path(cmd_context.option_value(cmd, opt_output_dir));
+
+  /* Create directories */
+  create_dir_path(sdc_dir_path.c_str());
+
+  PnrSdcOption options(sdc_dir_path);
+
+  options.set_constrain_global_port(cmd_context.option_enable(cmd, opt_constrain_global_port));
+  options.set_constrain_grid(cmd_context.option_enable(cmd, opt_constrain_grid));
+  options.set_constrain_sb(cmd_context.option_enable(cmd, opt_constrain_sb));
+  options.set_constrain_cb(cmd_context.option_enable(cmd, opt_constrain_cb));
+  options.set_constrain_configurable_memory_outputs(cmd_context.option_enable(cmd, opt_constrain_configurable_memory_outputs));
+  options.set_constrain_routing_multiplexer_outputs(cmd_context.option_enable(cmd, opt_constrain_routing_multiplexer_outputs));
+  options.set_constrain_switch_block_outputs(cmd_context.option_enable(cmd, opt_constrain_switch_block_outputs));
+
+  /* We first turn on default sdc option and then disable part of them by following users' options */
+  if (false == options.generate_sdc_pnr()) {
+    options.set_generate_sdc_pnr(true);
+  }
+
+  /* Collect global ports from the circuit library:
+   * TODO: should we place this in the OpenFPGA context?
+   */
+  std::vector<CircuitPortId> global_ports = find_circuit_library_global_ports(openfpga_ctx.arch().circuit_lib);
+  
+  /* Execute only when sdc is enabled */
+  if (true == options.generate_sdc_pnr()) { 
+    print_pnr_sdc(options,
+                  0, /* TODO: add critical path stats to OpenFPGA context */
+                  //openfpga_ctx.vpr_timing_annotation().critical_path_delay();
+                  g_vpr_ctx.device(),
+                  openfpga_ctx.vpr_device_annotation(),
+                  openfpga_ctx.device_rr_gsb(),
+                  openfpga_ctx.module_graph(),
+                  openfpga_ctx.mux_lib(),
+                  openfpga_ctx.arch().circuit_lib,
+                  global_ports,
+                  openfpga_ctx.flow_manager().compress_routing());
+  }
+} 
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_sdc.h b/openfpga/src/base/openfpga_sdc.h
new file mode 100644
index 000000000..4e48964f3
--- /dev/null
+++ b/openfpga/src/base/openfpga_sdc.h
@@ -0,0 +1,23 @@
+#ifndef OPENFPGA_SDC_H
+#define OPENFPGA_SDC_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "command.h"
+#include "command_context.h"
+#include "openfpga_context.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void write_pnr_sdc(OpenfpgaContext& openfpga_ctx,
+                   const Command& cmd, const CommandContext& cmd_context); 
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/base/openfpga_sdc_command.cpp b/openfpga/src/base/openfpga_sdc_command.cpp
new file mode 100644
index 000000000..cf31d73b0
--- /dev/null
+++ b/openfpga/src/base/openfpga_sdc_command.cpp
@@ -0,0 +1,79 @@
+/********************************************************************
+ * Add commands to the OpenFPGA shell interface, 
+ * in purpose of generate SDC files
+ * - write_pnr_sdc : generate SDC to constrain the back-end flow for FPGA fabric
+ * - write_analysis_sdc: TODO: generate SDC based on users' implementations
+ *******************************************************************/
+#include "openfpga_sdc.h"
+#include "openfpga_sdc_command.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * - Add a command to Shell environment: generate PnR SDC 
+ * - Add associated options 
+ * - Add command dependency
+ *******************************************************************/
+static 
+void add_openfpga_write_pnr_sdc_command(openfpga::Shell<OpenfpgaContext>& shell,
+                                        const ShellCommandClassId& cmd_class_id,
+                                        const ShellCommandId& shell_cmd_build_fabric_id) {
+  Command shell_cmd("write_pnr_sdc");
+
+  /* Add an option '--file' in short '-f'*/
+  CommandOptionId output_opt = shell_cmd.add_option("file", true, "Specify the output directory for SDC files");
+  shell_cmd.set_option_short_name(output_opt, "f");
+  shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING);
+
+  /* Add an option '--constrain_global_port' */
+  shell_cmd.add_option("constrain_global_port", false, "Constrain all the global ports of FPGA fabric");
+
+  /* Add an option '--constrain_grid' */
+  shell_cmd.add_option("constrain_grid", false, "Constrain all the grids of FPGA fabric");
+
+  /* Add an option '--constrain_sb' */
+  shell_cmd.add_option("constrain_sb", false, "Constrain all the switch blocks of FPGA fabric");
+
+  /* Add an option '--constrain_cb' */
+  shell_cmd.add_option("constrain_cb", false, "Constrain all the connection blocks of FPGA fabric");
+
+  /* Add an option '--constrain_configurable_memory_outputs' */
+  shell_cmd.add_option("constrain_configurable_memory_outputs", false, "Constrain all the outputs of configurable memories of FPGA fabric");
+
+  /* Add an option '--constrain_routing_multiplexer_outputs' */
+  shell_cmd.add_option("constrain_routing_multiplexer_outputs", false, "Constrain all the outputs of routing multiplexer of FPGA fabric");
+
+  /* Add an option '--constrain_switch_block_outputs' */
+  shell_cmd.add_option("constrain_switch_block_outputs", false, "Constrain all the outputs of switch blocks of FPGA fabric");
+
+  /* Add an option '--verbose' */
+  shell_cmd.add_option("verbose", false, "Enable verbose output");
+  
+  /* Add command 'write_fabric_verilog' to the Shell */
+  ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "generate SDC files to constrain the backend flow for FPGA fabric");
+  shell.set_command_class(shell_cmd_id, cmd_class_id);
+  shell.set_command_execute_function(shell_cmd_id, write_pnr_sdc);
+
+  /* The 'build_fabric' command should NOT be executed before 'link_openfpga_arch' */
+  std::vector<ShellCommandId> cmd_dependency;
+  cmd_dependency.push_back(shell_cmd_build_fabric_id);
+  shell.set_command_dependency(shell_cmd_id, cmd_dependency);
+}
+
+void add_openfpga_sdc_commands(openfpga::Shell<OpenfpgaContext>& shell) {
+  /* Get the unique id of 'build_fabric' command which is to be used in creating the dependency graph */
+  const ShellCommandId& shell_cmd_build_fabric_id = shell.command(std::string("build_fabric"));
+
+  /* Add a new class of commands */
+  ShellCommandClassId openfpga_sdc_cmd_class = shell.add_command_class("FPGA-SDC");
+
+  /******************************** 
+   * Command 'write_fabric_verilog' 
+   */
+  add_openfpga_write_pnr_sdc_command(shell,
+                                     openfpga_sdc_cmd_class,
+                                     shell_cmd_build_fabric_id);
+} 
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_sdc_command.h b/openfpga/src/base/openfpga_sdc_command.h
new file mode 100644
index 000000000..9fbeb42a5
--- /dev/null
+++ b/openfpga/src/base/openfpga_sdc_command.h
@@ -0,0 +1,21 @@
+#ifndef OPENFPGA_SDC_COMMAND_H
+#define OPENFPGA_SDC_COMMAND_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "shell.h"
+#include "openfpga_context.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void add_openfpga_sdc_commands(openfpga::Shell<OpenfpgaContext>& shell); 
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp
index ea7702a12..f8ce1c703 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp
+++ b/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp
@@ -323,7 +323,7 @@ void print_pnr_sdc_constrain_grid_timing(const std::string& sdc_dir,
                                          const ModuleManager& module_manager) {
 
   /* Start time count */
-  vtr::ScopedStartFinishTimer timer("Generating SDC for constraining grid timing for P&R flow");
+  vtr::ScopedStartFinishTimer timer("Write SDC for constraining grid timing for P&R flow");
 
   for (const t_physical_tile_type& physical_tile : device_ctx.physical_tile_types) {
     /* Bypass empty type or nullptr */
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp
index 348ee3dac..dcb5b6849 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp
+++ b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp
@@ -166,7 +166,7 @@ void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_di
                                                        const DeviceRRGSB& device_rr_gsb) {
 
   /* Start time count */
-  vtr::ScopedStartFinishTimer timer("Generating SDC for constrain Switch Block timing for P&R flow");
+  vtr::ScopedStartFinishTimer timer("Write SDC for constrain Switch Block timing for P&R flow");
 
   /* Get the range of SB array */
   vtr::Point<size_t> sb_range = device_rr_gsb.get_gsb_range();
@@ -195,7 +195,7 @@ void print_pnr_sdc_compact_routing_constrain_sb_timing(const std::string& sdc_di
                                                        const DeviceRRGSB& device_rr_gsb) {
 
   /* Start time count */
-  vtr::ScopedStartFinishTimer timer("Generating SDC for constrain Switch Block timing for P&R flow");
+  vtr::ScopedStartFinishTimer timer("Write SDC for constrain Switch Block timing for P&R flow");
 
   for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_module(); ++isb) {
     const RRGSB& rr_gsb = device_rr_gsb.get_sb_unique_module(isb);
@@ -362,7 +362,7 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_di
                                                        const DeviceRRGSB& device_rr_gsb) {
 
   /* Start time count */
-  vtr::ScopedStartFinishTimer timer("Generating SDC for constrain Connection Block timing for P&R flow");
+  vtr::ScopedStartFinishTimer timer("Write SDC for constrain Connection Block timing for P&R flow");
 
   print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_dir, module_manager, 
                                                     rr_graph,
@@ -385,7 +385,7 @@ void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_di
                                                        const DeviceRRGSB& device_rr_gsb) {
 
   /* Start time count */
-  vtr::ScopedStartFinishTimer timer("Generating SDC for constrain Connection Block timing for P&R flow");
+  vtr::ScopedStartFinishTimer timer("Write SDC for constrain Connection Block timing for P&R flow");
 
   /* Print SDC for unique X-direction connection block modules */
   for (size_t icb = 0; icb < device_rr_gsb.get_num_cb_unique_module(CHANX); ++icb) {
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
index e418bc620..aa1895014 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
+++ b/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
@@ -58,7 +58,7 @@ void print_pnr_sdc_global_ports(const std::string& sdc_dir,
   std::string sdc_fname(sdc_dir + std::string(SDC_GLOBAL_PORTS_FILE_NAME));
 
   /* Start time count */
-  std::string timer_message = std::string("Generating SDC for constraining clocks for P&R flow '") + sdc_fname + std::string("'");
+  std::string timer_message = std::string("Write SDC for constraining clocks for P&R flow '") + sdc_fname + std::string("'");
   vtr::ScopedStartFinishTimer timer(timer_message);
 
   /* Create the file stream */
@@ -153,7 +153,7 @@ void print_pnr_sdc_constrain_configurable_memory_outputs(const std::string& sdc_
   std::string sdc_fname(sdc_dir + std::string(SDC_DISABLE_CONFIG_MEM_OUTPUTS_FILE_NAME));
 
   /* Start time count */
-  std::string timer_message = std::string("Generating SDC to disable configurable memory outputs for P&R flow '") + sdc_fname + std::string("'");
+  std::string timer_message = std::string("Write SDC to disable configurable memory outputs for P&R flow '") + sdc_fname + std::string("'");
   vtr::ScopedStartFinishTimer timer(timer_message);
 
   /* Create the file stream */
@@ -187,7 +187,7 @@ void print_sdc_disable_routing_multiplexer_outputs(const std::string& sdc_dir,
   std::string sdc_fname(sdc_dir + std::string(SDC_DISABLE_MUX_OUTPUTS_FILE_NAME));
 
   /* Start time count */
-  std::string timer_message = std::string("Generating SDC to disable routing multiplexer outputs for P&R flow '") + sdc_fname + std::string("'");
+  std::string timer_message = std::string("Write SDC to disable routing multiplexer outputs for P&R flow '") + sdc_fname + std::string("'");
   vtr::ScopedStartFinishTimer timer(timer_message);
 
   /* Create the file stream */
@@ -242,7 +242,7 @@ void print_pnr_sdc_flatten_routing_disable_switch_block_outputs(const std::strin
   std::string sdc_fname(sdc_dir + std::string(SDC_DISABLE_SB_OUTPUTS_FILE_NAME));
 
   /* Start time count */
-  std::string timer_message = std::string("Generating SDC to disable switch block outputs for P&R flow '") + sdc_fname + std::string("'");
+  std::string timer_message = std::string("Write SDC to disable switch block outputs for P&R flow '") + sdc_fname + std::string("'");
   vtr::ScopedStartFinishTimer timer(timer_message);
 
   /* Create the file stream */
@@ -298,7 +298,7 @@ void print_pnr_sdc_compact_routing_disable_switch_block_outputs(const std::strin
   std::string sdc_fname(sdc_dir + std::string(SDC_DISABLE_SB_OUTPUTS_FILE_NAME));
 
   /* Start time count */
-  std::string timer_message = std::string("Generating SDC to disable switch block outputs for P&R flow '") + sdc_fname + std::string("'");
+  std::string timer_message = std::string("Write SDC to disable switch block outputs for P&R flow '") + sdc_fname + std::string("'");
   vtr::ScopedStartFinishTimer timer(timer_message);
 
   /* Create the file stream */
diff --git a/openfpga/src/main.cpp b/openfpga/src/main.cpp
index c018db4bf..b2c9d2e6c 100644
--- a/openfpga/src/main.cpp
+++ b/openfpga/src/main.cpp
@@ -14,6 +14,7 @@
 #include "openfpga_setup_command.h"
 #include "openfpga_verilog_command.h"
 #include "openfpga_bitstream_command.h"
+#include "openfpga_sdc_command.h"
 #include "basic_command.h"
 
 #include "openfpga_title.h"
@@ -60,6 +61,9 @@ int main(int argc, char** argv) {
   /* Add openfpga bitstream commands */
   openfpga::add_openfpga_bitstream_commands(shell);
 
+  /* Add openfpga sdc commands */
+  openfpga::add_openfpga_sdc_commands(shell);
+
   /* Add basic commands: exit, help, etc. 
    * Note:
    * This MUST be the last command group to be added! 
diff --git a/openfpga/test_script/s298_k6_frac.openfpga b/openfpga/test_script/s298_k6_frac.openfpga
index d79fc3b9b..a5c2c3669 100644
--- a/openfpga/test_script/s298_k6_frac.openfpga
+++ b/openfpga/test_script/s298_k6_frac.openfpga
@@ -35,10 +35,19 @@ fpga_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepene
 
 # Write the Verilog netlist for FPGA fabric
 #  - Enable the use of explicit port mapping in Verilog netlist
-write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
+write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
 
 # Write the Verilog testbench for FPGA fabric
-write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src --reference_benchmark_file_path /var/tmp/xtang/s298.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/s298.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here 
+write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
 
 # Finish and exit OpenFPGA
 exit

From de8425874c68adf9113a84606410f37135dee56d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 28 Feb 2020 11:24:39 -0700
Subject: [PATCH 232/645] use user defined critical path delay in SDC
 generation

---
 openfpga/src/base/openfpga_sdc.cpp       |  4 ++--
 openfpga/src/fpga_sdc/pnr_sdc_writer.cpp | 23 +++++++++++------------
 openfpga/src/fpga_sdc/pnr_sdc_writer.h   |  3 ++-
 3 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/openfpga/src/base/openfpga_sdc.cpp b/openfpga/src/base/openfpga_sdc.cpp
index 4fce8d552..eaa2b9941 100644
--- a/openfpga/src/base/openfpga_sdc.cpp
+++ b/openfpga/src/base/openfpga_sdc.cpp
@@ -64,8 +64,8 @@ void write_pnr_sdc(OpenfpgaContext& openfpga_ctx,
   /* Execute only when sdc is enabled */
   if (true == options.generate_sdc_pnr()) { 
     print_pnr_sdc(options,
-                  0, /* TODO: add critical path stats to OpenFPGA context */
-                  //openfpga_ctx.vpr_timing_annotation().critical_path_delay();
+                  1./openfpga_ctx.arch().sim_setting.programming_clock_frequency(),
+                  1./openfpga_ctx.arch().sim_setting.operating_clock_frequency(),
                   g_vpr_ctx.device(),
                   openfpga_ctx.vpr_device_annotation(),
                   openfpga_ctx.device_rr_gsb(),
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
index aa1895014..9d1478037 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
+++ b/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
@@ -35,12 +35,6 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-/********************************************************************
- * Local variables
- *******************************************************************/
-constexpr float SDC_FIXED_PROG_CLOCK_PERIOD = 100;
-constexpr float SDC_FIXED_CLOCK_PERIOD = 10;
-
 /********************************************************************
  * Print a SDC file to constrain the global ports of FPGA fabric
  * in particular clock ports
@@ -50,7 +44,8 @@ constexpr float SDC_FIXED_CLOCK_PERIOD = 10;
  *******************************************************************/
 static 
 void print_pnr_sdc_global_ports(const std::string& sdc_dir, 
-                                const float& critical_path_delay,
+                                const float& programming_critical_path_delay,
+                                const float& operating_critical_path_delay,
                                 const CircuitLibrary& circuit_lib,
                                 const std::vector<CircuitPortId>& global_ports) {
 
@@ -76,11 +71,11 @@ void print_pnr_sdc_global_ports(const std::string& sdc_dir,
       continue;
     }
     /* Reach here, it means a clock port and we need print constraints */
-    float clock_period = critical_path_delay; 
+    float clock_period = operating_critical_path_delay; 
 
     /* For programming clock, we give a fixed period */
     if (true == circuit_lib.port_is_prog(clock_port)) {
-      clock_period = SDC_FIXED_PROG_CLOCK_PERIOD;
+      clock_period = programming_critical_path_delay;
       /* Print comments */
       fp << "##################################################" << std::endl; 
       fp << "# Create programmable clock                       " << std::endl;
@@ -118,7 +113,7 @@ void print_pnr_sdc_global_ports(const std::string& sdc_dir,
     fp << "##################################################" << std::endl; 
 
     /* Reach here, it means a non-clock global port and we need print constraints */
-    float clock_period = SDC_FIXED_CLOCK_PERIOD; 
+    float clock_period = operating_critical_path_delay; 
     for (const size_t& pin : circuit_lib.pins(global_port)) {
       BasicPort port_to_constrain(circuit_lib.port_prefix(global_port), pin, pin);
       fp << "create_clock ";
@@ -343,7 +338,8 @@ void print_pnr_sdc_compact_routing_disable_switch_block_outputs(const std::strin
  * 4. Design constraints for breaking the combinational loops in FPGA fabric
  *******************************************************************/
 void print_pnr_sdc(const PnrSdcOption& sdc_options,
-                   const float& critical_path_delay,
+                   const float& programming_critical_path_delay,
+                   const float& operating_critical_path_delay,
                    const DeviceContext& device_ctx,
                    const VprDeviceAnnotation& device_annotation,
                    const DeviceRRGSB& device_rr_gsb,
@@ -355,7 +351,10 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options,
   
   /* Constrain global ports */
   if (true == sdc_options.constrain_global_port()) {
-    print_pnr_sdc_global_ports(sdc_options.sdc_dir(), critical_path_delay, circuit_lib, global_ports);
+    print_pnr_sdc_global_ports(sdc_options.sdc_dir(),
+                               programming_critical_path_delay,
+                               operating_critical_path_delay,
+                               circuit_lib, global_ports);
   }
 
   std::string top_module_name = generate_fpga_top_module_name();
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_writer.h b/openfpga/src/fpga_sdc/pnr_sdc_writer.h
index cdadbf19d..1016d57da 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_writer.h
+++ b/openfpga/src/fpga_sdc/pnr_sdc_writer.h
@@ -22,7 +22,8 @@
 namespace openfpga {
 
 void print_pnr_sdc(const PnrSdcOption& sdc_options,
-                   const float& critical_path_delay,
+                   const float& programming_critical_path_delay,
+                   const float& operating_critical_path_delay,
                    const DeviceContext& device_ctx,
                    const VprDeviceAnnotation& device_annotation,
                    const DeviceRRGSB& device_rr_gsb,

From 542fadaaae12f53953254dec0ee8bbe7c93b6dc8 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 28 Feb 2020 12:10:27 -0700
Subject: [PATCH 233/645] allow users to use VPR critical path delay in
 OpenFPGA simulation

---
 openfpga/src/base/openfpga_link_arch.cpp      | 50 +++++++++++++++++++
 .../k6_frac_N10_40nm_openfpga.xml             |  2 +-
 2 files changed, 51 insertions(+), 1 deletion(-)

diff --git a/openfpga/src/base/openfpga_link_arch.cpp b/openfpga/src/base/openfpga_link_arch.cpp
index 9dc1e38c7..799a88a2a 100644
--- a/openfpga/src/base/openfpga_link_arch.cpp
+++ b/openfpga/src/base/openfpga_link_arch.cpp
@@ -7,6 +7,11 @@
 #include "vtr_assert.h"
 #include "vtr_log.h"
 
+/* Headers from vpr library */
+#include "timing_info.h"
+#include "AnalysisDelayCalculator.h"
+#include "net_delay.h"
+
 #include "vpr_device_annotation.h"
 #include "pb_type_utils.h"
 #include "annotate_pb_types.h"
@@ -46,6 +51,47 @@ bool is_vpr_rr_graph_supported(const RRGraph& rr_graph) {
   return true;
 }
 
+/********************************************************************
+ * Annotate simulation setting based on VPR results
+ *  - If the operating clock frequency is set to follow the vpr timing results,
+ *    we will set a new operating clock frequency here
+ *  - If the number of clock cycles in simulation is set to be automatically determined,
+ *    we will infer the number based on the average signal density
+ *******************************************************************/
+static 
+void annotate_simulation_setting(const AtomContext& atom_ctx, 
+                                 SimulationSetting& sim_setting) {
+
+  /* Find if the operating frequency is binded to vpr results */
+  if (0. == sim_setting.operating_clock_frequency()) {
+    VTR_LOG("User specified the operating clock frequency to use VPR results\n");
+    /* Run timing analysis and collect critical path delay
+     * This code is copied from function vpr_analysis() in vpr_api.h 
+     * Should keep updated to latest VPR code base
+     * Note:
+     *   - MUST mention in documentation that VPR should be run in timing enabled mode
+     */
+    vtr::vector<ClusterNetId, float*> net_delay;
+    vtr::t_chunk net_delay_ch;
+    /* Load the net delays */
+    net_delay = alloc_net_delay(&net_delay_ch);
+    load_net_delay_from_routing(net_delay);
+
+    /* Do final timing analysis */
+    auto analysis_delay_calc = std::make_shared<AnalysisDelayCalculator>(atom_ctx.nlist, atom_ctx.lookup, net_delay);
+    auto timing_info = make_setup_hold_timing_info(analysis_delay_calc);
+    timing_info->update();
+
+    /* Get critical path delay. Update simulation settings */
+    float T_crit = timing_info->least_slack_critical_path().delay() * (1. + sim_setting.operating_clock_frequency_slack());
+    sim_setting.set_operating_clock_frequency(1 / T_crit); 
+    VTR_LOG("Use VPR critical path delay %g [ns] with a %g [%] slack in OpenFPGA.\n",
+            T_crit / 1e9, sim_setting.operating_clock_frequency_slack() * 100);
+  }
+  VTR_LOG("Will apply operating clock frequency %g [MHz] to simulations\n",
+          sim_setting.operating_clock_frequency() / 1e6);
+}
+
 /********************************************************************
  * Top-level function to link openfpga architecture to VPR, including:
  * - physical pb_type
@@ -118,6 +164,10 @@ void link_arch(OpenfpgaContext& openfpga_ctx,
                          g_vpr_ctx.clustering(),
                          g_vpr_ctx.placement(),
                          openfpga_ctx.mutable_vpr_placement_annotation());
+
+  /* TODO: Annotate the number of clock cycles and clock frequency by following VPR results */
+  annotate_simulation_setting(g_vpr_ctx.atom(),
+                              openfpga_ctx.mutable_arch().sim_setting);
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
index 2f318cbaa..2e9350f51 100644
--- a/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
@@ -232,7 +232,7 @@
 </openfpga_architecture>
 <openfpga_simulation_setting>
   <clock_setting>
-    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
+    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
     <programming frequency="10e6"/>
   </clock_setting>
   <simulator_option>

From 80bb2baae5a99582bce671b56dc240553d5ea86b Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 28 Feb 2020 14:29:01 -0700
Subject: [PATCH 234/645] start verification and bug fixing

---
 .../verilog_auxiliary_netlists.cpp             |  6 ++++++
 .../verilog_formal_random_top_testbench.cpp    |  1 +
 .../fpga_verilog/verilog_testbench_utils.cpp   | 14 +++++++++++++-
 .../src/fpga_verilog/verilog_testbench_utils.h |  1 +
 .../src/fpga_verilog/verilog_top_testbench.cpp |  1 +
 .../k6_frac_N10_40nm_openfpga.xml              |  4 ++--
 openfpga/test_script/s298_k6_frac.openfpga     |  2 +-
 openfpga/test_vpr_arch/k6_frac_N10_40nm.xml    | 18 ++++++++++++------
 8 files changed, 37 insertions(+), 10 deletions(-)

diff --git a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
index 9419f4172..fd01a462f 100644
--- a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
+++ b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
@@ -183,6 +183,12 @@ void print_verilog_simulation_preprocessing_flags(const std::string& src_dir,
 
   /* To enable pre-configured FPGA simulation */
   if (true == verilog_testbench_opts.print_formal_verification_top_netlist()) {
+    print_verilog_define_flag(fp, std::string(VERILOG_FORMAL_VERIFICATION_PREPROC_FLAG), 1);
+    fp << std::endl;
+  } 
+
+  /* To enable pre-configured FPGA simulation */
+  if (true == verilog_testbench_opts.print_preconfig_top_testbench()) {
     print_verilog_define_flag(fp, std::string(FORMAL_SIMULATION_FLAG), 1);
     fp << std::endl;
   } 
diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
index 7aef8a72f..fa4f68938 100644
--- a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
@@ -228,6 +228,7 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
                                         clock_port);
   print_verilog_testbench_random_stimuli(fp, atom_ctx,
                                          netlist_annotation, 
+                                         clock_port_names, 
                                          std::string(CHECKFLAG_PORT_POSTFIX),
                                          clock_port);
 
diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
index 8d3e856c7..e952d13c4 100644
--- a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
+++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
@@ -5,6 +5,7 @@
  * Note: please try to avoid using global variables in this file
  * so that we can make it free to use anywhere
  *******************************************************************/
+#include <algorithm>
 #include <iomanip>
 
 /* Headers from vtrutil library */
@@ -422,6 +423,7 @@ void print_verilog_testbench_clock_stimuli(std::fstream& fp,
 void print_verilog_testbench_random_stimuli(std::fstream& fp,
                                             const AtomContext& atom_ctx,
                                             const VprNetlistAnnotation& netlist_annotation,
+                                            const std::vector<std::string>& clock_port_names,
                                             const std::string& check_flag_port_postfix,
                                             const BasicPort& clock_port) {
   /* Validate the file stream */
@@ -444,6 +446,11 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp,
       block_name = netlist_annotation.block_name(atom_blk);
     } 
 
+    /* Bypass clock ports */
+    if (clock_port_names.end() != std::find(clock_port_names.begin(), clock_port_names.end(), block_name)) {
+      continue;
+    }
+
     /* TODO: find the clock inputs will be initialized later */
     if (AtomBlockType::INPAD == atom_ctx.nlist.block_type(atom_blk)) {
       fp << "\t\t" << block_name << " <= 1'b0;" << std::endl;
@@ -510,8 +517,13 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp,
       block_name = netlist_annotation.block_name(atom_blk);
     } 
 
+    /* Bypass clock ports */
+    if (clock_port_names.end() != std::find(clock_port_names.begin(), clock_port_names.end(), block_name)) {
+      continue;
+    }
+
     /* TODO: find the clock inputs will be initialized later */
-    if (AtomBlockType::INPAD != atom_ctx.nlist.block_type(atom_blk)) {
+    if (AtomBlockType::INPAD == atom_ctx.nlist.block_type(atom_blk)) {
       fp << "\t\t" << block_name << " <= $random;" << std::endl;
     }
   }
diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.h b/openfpga/src/fpga_verilog/verilog_testbench_utils.h
index 61d5929c8..5e0bd69f9 100644
--- a/openfpga/src/fpga_verilog/verilog_testbench_utils.h
+++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.h
@@ -76,6 +76,7 @@ void print_verilog_testbench_clock_stimuli(std::fstream& fp,
 void print_verilog_testbench_random_stimuli(std::fstream& fp,
                                             const AtomContext& atom_ctx,
                                             const VprNetlistAnnotation& netlist_annotation,
+                                            const std::vector<std::string>& clock_port_names,
                                             const std::string& check_flag_port_postfix,
                                             const BasicPort& clock_port);
 
diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
index f64558dda..911c6defb 100644
--- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
@@ -855,6 +855,7 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
   /* Add stimuli for reset, set, clock and iopad signals */
   print_verilog_testbench_random_stimuli(fp, atom_ctx, 
                                          netlist_annotation, 
+                                         clock_port_names, 
                                          std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX),
                                          BasicPort(std::string(TOP_TB_OP_CLOCK_PORT_NAME), 1));
 
diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
index 2e9350f51..d02d62d88 100644
--- a/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
@@ -168,11 +168,11 @@
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
        <pass_gate_logic circuit_model_name="TGATE"/>
-       <port type="input" prefix="pReset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
        <port type="input" prefix="D" size="1"/>
        <port type="output" prefix="Q" size="1"/>
        <port type="output" prefix="Qb" size="1"/>
-       <port type="clock" prefix="prog_clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
     </circuit_model>
     <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
       <design_technology type="cmos"/>
diff --git a/openfpga/test_script/s298_k6_frac.openfpga b/openfpga/test_script/s298_k6_frac.openfpga
index a5c2c3669..5423493e3 100644
--- a/openfpga/test_script/s298_k6_frac.openfpga
+++ b/openfpga/test_script/s298_k6_frac.openfpga
@@ -1,5 +1,5 @@
 # Run VPR for the s298 design
-vpr ./test_vpr_arch/k6_frac_N10_40nm.xml ./test_blif/s298.blif --write_rr_graph example_rr_graph.xml
+vpr ./test_vpr_arch/k6_frac_N10_40nm.xml ./test_blif/s298.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml
 
 # Read OpenFPGA architecture definition
 read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml
index 97001c497..44e2ef289 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml
@@ -45,19 +45,22 @@
     </model>
   </models>
   <tiles>
+    <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+         If you need to register the I/O, define clocks in the circuit models
+         These clocks can be handled in back-end
+     -->
     <tile name="io" capacity="8" area="0">
       <equivalent_sites>
         <site pb_type="io"/>
       </equivalent_sites>
       <input name="outpad" num_pins="1"/>
       <output name="inpad" num_pins="1"/>
-      <clock name="clock" num_pins="1"/>
       <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
       <pinlocations pattern="custom">
-        <loc side="left">io.outpad io.inpad io.clock</loc>
-        <loc side="top">io.outpad io.inpad io.clock</loc>
-        <loc side="right">io.outpad io.inpad io.clock</loc>
-        <loc side="bottom">io.outpad io.inpad io.clock</loc>
+        <loc side="left">io.outpad io.inpad</loc>
+        <loc side="top">io.outpad io.inpad</loc>
+        <loc side="right">io.outpad io.inpad</loc>
+        <loc side="bottom">io.outpad io.inpad</loc>
       </pinlocations>
     </tile>
     <tile name="clb" area="53894">
@@ -145,7 +148,10 @@
     <pb_type name="io">
       <input name="outpad" num_pins="1"/>
       <output name="inpad" num_pins="1"/>
-      <clock name="clock" num_pins="1"/>
+      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+           If you need to register the I/O, define clocks in the circuit models
+           These clocks can be handled in back-end
+       -->
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->

From a6c2d2c7d1e2bcdd81199f350969ee180f3e2e29 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 28 Feb 2020 14:46:01 -0700
Subject: [PATCH 235/645] bug fixed for io location mapping

---
 openfpga/src/fabric/build_top_module.cpp                  | 2 +-
 openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml | 3 ++-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/openfpga/src/fabric/build_top_module.cpp b/openfpga/src/fabric/build_top_module.cpp
index 7af79d46c..707ff8971 100644
--- a/openfpga/src/fabric/build_top_module.cpp
+++ b/openfpga/src/fabric/build_top_module.cpp
@@ -172,8 +172,8 @@ vtr::Matrix<size_t> add_top_module_grid_instances(ModuleManager& module_manager,
        */
       for (int z = 0; z < grids[io_coordinate.x()][io_coordinate.y()].type->capacity; ++z) {
         io_location_map.set_io_index(io_coordinate.x(), io_coordinate.y(), z, io_counter);
+        io_counter++;
       }
-      io_counter++;
     }
   }
 
diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
index d02d62d88..9644530da 100644
--- a/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
@@ -232,7 +232,8 @@
 </openfpga_architecture>
 <openfpga_simulation_setting>
   <clock_setting>
-    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
+    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
+    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
     <programming frequency="10e6"/>
   </clock_setting>
   <simulator_option>

From 05ebd77d7dc57e280015af3ff1b51e489d4dfea4 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 28 Feb 2020 15:41:32 -0700
Subject: [PATCH 236/645] start debugging with micro benchmarks. Spot problem
 in local routing

---
 openfpga/test_blif/and.blif                   |  8 ++
 openfpga/test_blif/and.v                      | 14 +++
 openfpga/test_blif/s298.blif                  | 90 -------------------
 ..._k6_frac.openfpga => and_k6_frac.openfpga} |  4 +-
 4 files changed, 24 insertions(+), 92 deletions(-)
 create mode 100644 openfpga/test_blif/and.blif
 create mode 100644 openfpga/test_blif/and.v
 delete mode 100644 openfpga/test_blif/s298.blif
 rename openfpga/test_script/{s298_k6_frac.openfpga => and_k6_frac.openfpga} (88%)

diff --git a/openfpga/test_blif/and.blif b/openfpga/test_blif/and.blif
new file mode 100644
index 000000000..67d978741
--- /dev/null
+++ b/openfpga/test_blif/and.blif
@@ -0,0 +1,8 @@
+.model top
+.inputs a b
+.outputs c
+
+.names a b c
+11 1
+
+.end
diff --git a/openfpga/test_blif/and.v b/openfpga/test_blif/and.v
new file mode 100644
index 000000000..876f1c6fe
--- /dev/null
+++ b/openfpga/test_blif/and.v
@@ -0,0 +1,14 @@
+`timescale 1ns / 1ps
+
+module top(
+  a,
+  b,
+  c);
+
+input wire a;
+input wire b;
+output wire c;
+
+assign c = a & b;
+
+endmodule
diff --git a/openfpga/test_blif/s298.blif b/openfpga/test_blif/s298.blif
deleted file mode 100644
index c588a6e0a..000000000
--- a/openfpga/test_blif/s298.blif
+++ /dev/null
@@ -1,90 +0,0 @@
-# Benchmark "s298" written by ABC on Tue Mar 12 09:40:31 2019
-.model s298
-.inputs clock G0 G1 G2
-.outputs G117 G132 G66 G118 G133 G67
-
-.latch        n21        G10 re      clock  0
-.latch        n26        G11 re      clock  0
-.latch        n31        G12 re      clock  0
-.latch        n36        G13 re      clock  0
-.latch        n41        G14 re      clock  0
-.latch        n46        G15 re      clock  0
-.latch        n51        G66 re      clock  0
-.latch        n55        G67 re      clock  0
-.latch        n59       G117 re      clock  0
-.latch        n63       G118 re      clock  0
-.latch        n67       G132 re      clock  0
-.latch        n71       G133 re      clock  0
-.latch        n75        G22 re      clock  0
-.latch        n80        G23 re      clock  0
-
-.names n56 n57 G10 n63
-0-0 1
-11- 1
-.names G15 G11 G13 G22 G14 G12 n56
-01---- 1
-0-0--- 1
-0--0-- 1
-0---1- 1
-0----1 1
--11000 1
-.names G14 G13 G12 G118 G11 n57
-01--- 1
-100-0 1
-1-11- 1
--1-1- 1
-.names n56 n59_1 G10 n67
-0-0 1
-11- 1
-.names G14 G13 G12 G132 G11 n59_1
-100-0 1
-11-1- 1
-1-11- 1
-.names G0 G10 n21
-00 1
-.names G10 G11 G0 G12 G13 n26
-010-- 1
-1001- 1
-100-0 1
-.names G12 G0 G11 G10 n31
-0011 1
-100- 1
-10-0 1
-.names G13 G0 G11 G12 G10 n36
-00111 1
-1001- 1
-1010- 1
-10--0 1
-.names n65 G14 G0 n41
-000 1
-110 1
-.names G23 G10 G13 G11 G12 n65
-1---- 0
--1100 0
-.names G0 n56 n46
-00 1
-.names n56 G66 G14 G13 G12 n51
-111-1 1
-11-1- 1
-1-01- 1
-.names n56 G13 G14 G11 G67 G12 n55
-1000-- 1
-10-1-0 1
-111-1- 1
-1-1-11 1
-.names n56 G13 G117 G14 G12 G11 n59
-10-0-- 1
-10--01 1
-1111-- 1
-1-111- 1
-.names n56 G14 G12 G13 G133 G11 n71
-1010-1 1
-111-1- 1
-11-11- 1
-.names G2 G22 G0 n75
-010 1
-100 1
-.names G1 G23 G0 n80
-010 1
-100 1
-.end
diff --git a/openfpga/test_script/s298_k6_frac.openfpga b/openfpga/test_script/and_k6_frac.openfpga
similarity index 88%
rename from openfpga/test_script/s298_k6_frac.openfpga
rename to openfpga/test_script/and_k6_frac.openfpga
index 5423493e3..51a1c5ae2 100644
--- a/openfpga/test_script/s298_k6_frac.openfpga
+++ b/openfpga/test_script/and_k6_frac.openfpga
@@ -1,5 +1,5 @@
 # Run VPR for the s298 design
-vpr ./test_vpr_arch/k6_frac_N10_40nm.xml ./test_blif/s298.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml
+vpr ./test_vpr_arch/k6_frac_N10_40nm.xml ./test_blif/and.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml
 
 # Read OpenFPGA architecture definition
 read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
@@ -43,7 +43,7 @@ write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port
 #  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/s298.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
+write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
 
 # Write the SDC files for PnR backend
 #  - Turn on every options here 

From 9fd184e3ab9280c7a8e87552d372e80bb09a33e7 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 28 Feb 2020 15:42:18 -0700
Subject: [PATCH 237/645] rm out-of-date script

---
 openfpga/test_script/s298.openfpga | 14 --------------
 1 file changed, 14 deletions(-)
 delete mode 100644 openfpga/test_script/s298.openfpga

diff --git a/openfpga/test_script/s298.openfpga b/openfpga/test_script/s298.openfpga
deleted file mode 100644
index 216f6d8c4..000000000
--- a/openfpga/test_script/s298.openfpga
+++ /dev/null
@@ -1,14 +0,0 @@
-# Run VPR for the s298 design
-vpr ./test_vpr_arch/k6_N10_40nm.xml ./test_blif/s298.blif
-
-# Read OpenFPGA architecture definition
-read_openfpga_arch -f ./test_openfpga_arch/k6_N10_40nm_openfpga.xml
-
-# Annotate the OpenFPGA architecture to VPR data base
-link_openfpga_arch
-
-# Check and correct any naming conflicts in the BLIF netlist
-check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
-
-# Finish and exit OpenFPGA
-exit

From 3807a940f4d7ec953db576f6117f9f38c791ebe5 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 28 Feb 2020 16:45:50 -0700
Subject: [PATCH 238/645] fixed critical bugs in bitstream generation and now
 we pass microbenchmarks

---
 openfpga/src/fpga_bitstream/build_grid_bitstream.cpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
index 253798c86..f69b57ae6 100644
--- a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
+++ b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
@@ -168,7 +168,8 @@ void build_physical_block_pin_interc_bitstream(BitstreamManager& bitstream_manag
       for (t_pb_graph_pin* src_pb_graph_pin : pb_graph_pin_inputs(des_pb_graph_pin, cur_interc)) {
         const PhysicalPbId& src_pb_id = physical_pb.find_pb(src_pb_graph_pin->parent_node);
         /* If the src pb id is not valid, we bypass it */
-        if ( (true != physical_pb.valid_pb_id(src_pb_id))
+        if ( (true == physical_pb.valid_pb_id(src_pb_id))
+          && (AtomNetId::INVALID() != physical_pb.pb_graph_pin_atom_net(des_pb_id, des_pb_graph_pin))
           && (physical_pb.pb_graph_pin_atom_net(src_pb_id, src_pb_graph_pin) == physical_pb.pb_graph_pin_atom_net(des_pb_id, des_pb_graph_pin))) {
           break;
         }

From 7b18f7cd098e19a941776b5374e82f20c5f88e04 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 29 Feb 2020 13:29:16 -0700
Subject: [PATCH 239/645] now the auto select number of clocks in simulation is
 online

---
 openfpga/src/base/openfpga_context.h         |   5 +
 openfpga/src/base/openfpga_link_arch.cpp     | 135 +++++++-
 openfpga/src/base/openfpga_setup_command.cpp | 317 +++++++++++++------
 openfpga/test_script/and_k6_frac.openfpga    |   2 +-
 4 files changed, 365 insertions(+), 94 deletions(-)

diff --git a/openfpga/src/base/openfpga_context.h b/openfpga/src/base/openfpga_context.h
index 4b6cdf2d2..20e235a35 100644
--- a/openfpga/src/base/openfpga_context.h
+++ b/openfpga/src/base/openfpga_context.h
@@ -60,6 +60,7 @@ class OpenfpgaContext : public Context  {
     const openfpga::BitstreamManager& bitstream_manager() const { return bitstream_manager_; }
     const std::vector<openfpga::ConfigBitId>& fabric_bitstream() const { return fabric_bitstream_; }
     const openfpga::IoLocationMap& io_location_map() { return io_location_map_; }
+    const std::unordered_map<AtomNetId, t_net_power>& net_activity() { return net_activity_; }
   public:  /* Public mutators */
     openfpga::Arch& mutable_arch() { return arch_; }
     openfpga::VprDeviceAnnotation& mutable_vpr_device_annotation() { return vpr_device_annotation_; }
@@ -75,6 +76,7 @@ class OpenfpgaContext : public Context  {
     openfpga::BitstreamManager& mutable_bitstream_manager() { return bitstream_manager_; }
     std::vector<openfpga::ConfigBitId>& mutable_fabric_bitstream() { return fabric_bitstream_; }
     openfpga::IoLocationMap& mutable_io_location_map() { return io_location_map_; }
+    std::unordered_map<AtomNetId, t_net_power>& mutable_net_activity() { return net_activity_; }
   private: /* Internal data */
     /* Data structure to store information from read_openfpga_arch library */
     openfpga::Arch arch_;
@@ -110,6 +112,9 @@ class OpenfpgaContext : public Context  {
     /* Bitstream database */
     openfpga::BitstreamManager bitstream_manager_;
     std::vector<openfpga::ConfigBitId> fabric_bitstream_;
+
+    /* Net activities of users' implementation */
+    std::unordered_map<AtomNetId, t_net_power> net_activity_; 
  
     /* Flow status */
     openfpga::FlowManager flow_manager_;
diff --git a/openfpga/src/base/openfpga_link_arch.cpp b/openfpga/src/base/openfpga_link_arch.cpp
index 799a88a2a..fe89b7024 100644
--- a/openfpga/src/base/openfpga_link_arch.cpp
+++ b/openfpga/src/base/openfpga_link_arch.cpp
@@ -2,6 +2,9 @@
  * This file includes functions to read an OpenFPGA architecture file
  * which are built on the libarchopenfpga library
  *******************************************************************/
+#include <cmath>
+#include <iterator>
+
 /* Headers from vtrutil library */
 #include "vtr_time.h"
 #include "vtr_assert.h"
@@ -11,6 +14,7 @@
 #include "timing_info.h"
 #include "AnalysisDelayCalculator.h"
 #include "net_delay.h"
+#include "read_activity.h"
 
 #include "vpr_device_annotation.h"
 #include "pb_type_utils.h"
@@ -51,6 +55,108 @@ bool is_vpr_rr_graph_supported(const RRGraph& rr_graph) {
   return true;
 }
 
+/********************************************************************
+ * Find the number of clock cycles in simulation based on the average signal density
+ *******************************************************************/
+static 
+size_t recommend_num_sim_clock_cycle(const AtomContext& atom_ctx,
+                                     const std::unordered_map<AtomNetId, t_net_power>& net_activity, 
+                                     const float& sim_window_size) {
+  size_t recmd_num_sim_clock_cycle = 0;
+
+  float avg_density = 0.;
+  size_t net_cnt = 0;
+
+  float weighted_avg_density = 0.;
+  size_t weighted_net_cnt = 0;
+
+  /* get the average density of all the nets */
+  for (const AtomNetId& atom_net : atom_ctx.nlist.nets()) {
+    /* Skip the nets without any activity annotation */
+    if (0 == net_activity.count(atom_net)) {
+      continue;
+    }
+
+    /* Only care non-zero density nets */
+    if (0. == net_activity.at(atom_net).density) {
+      continue;
+    }
+
+    avg_density += net_activity.at(atom_net).density; 
+    net_cnt++;
+
+    /* Consider the weight of fan-out */
+    size_t net_weight; 
+    if (0 == std::distance(atom_ctx.nlist.net_sinks(atom_net).begin(), atom_ctx.nlist.net_sinks(atom_net).end())) {
+      net_weight = 1;
+    } else {
+      VTR_ASSERT(0 < std::distance(atom_ctx.nlist.net_sinks(atom_net).begin(), atom_ctx.nlist.net_sinks(atom_net).end()));
+      net_weight = std::distance(atom_ctx.nlist.net_sinks(atom_net).begin(), atom_ctx.nlist.net_sinks(atom_net).end());
+    }
+    weighted_avg_density += net_activity.at(atom_net).density* net_weight;
+    weighted_net_cnt += net_weight;
+  }
+  avg_density = avg_density / net_cnt; 
+  weighted_avg_density = weighted_avg_density / weighted_net_cnt; 
+
+  /* Sort the net density */
+  std::vector<float> net_densities;
+  net_densities.reserve(net_cnt);
+  for (const AtomNetId& atom_net : atom_ctx.nlist.nets()) {
+    /* Skip the nets without any activity annotation */
+    if (0 == net_activity.count(atom_net)) {
+      continue;
+    }
+
+    /* Only care non-zero density nets */
+    if (0. == net_activity.at(atom_net).density) {
+      continue;
+    }
+
+    net_densities.push_back(net_activity.at(atom_net).density);
+  }
+  std::sort(net_densities.begin(), net_densities.end());
+  /* Get the median */
+  float median_density = 0.;
+  /* check for even case */
+  if (net_cnt % 2 != 0) { 
+    median_density = net_densities[size_t(net_cnt / 2)];
+  } else {              
+    median_density = 0.5 * (net_densities[size_t((net_cnt - 1) / 2)] + net_densities[size_t((net_cnt - 1) / 2)]);
+  }
+
+  /* It may be more reasonable to use median 
+   * But, if median density is 0, we use average density
+  */
+  if ((0. == median_density) && (0. == avg_density)) {
+    recmd_num_sim_clock_cycle = 1;
+    VTR_LOG_WARN("All the signal density is zero!\nNumber of clock cycles in simulations are set to be %ld!\n",
+                 recmd_num_sim_clock_cycle);
+  } else if (0. == avg_density) {
+      recmd_num_sim_clock_cycle = (int)round(1 / median_density); 
+  } else if (0. == median_density) {
+      recmd_num_sim_clock_cycle = (int)round(1 / avg_density);
+  } else {
+    /* add a sim window size to balance the weight of average density and median density
+     * In practice, we find that there could be huge difference between avereage and median values 
+     * For a reasonable number of simulation clock cycles, we do this window size.
+     */
+    recmd_num_sim_clock_cycle = (int)round(1 / (sim_window_size * avg_density + (1 - sim_window_size) * median_density ));
+  }
+  
+  VTR_ASSERT(0 < recmd_num_sim_clock_cycle);
+
+  VTR_LOG("Average net density: %.2f\n", avg_density);
+  VTR_LOG("Median net density: %.2f\n", median_density);
+  VTR_LOG("Average net density after weighting: %.2f\n", weighted_avg_density);
+  VTR_LOG("Window size set for Simulation: %.2f\n", sim_window_size);
+  VTR_LOG("Net density after Window size : %.2f\n", 
+          (sim_window_size * avg_density + (1 - sim_window_size) * median_density));
+  VTR_LOG("Recommend no. of clock cycles: %ld\n", recmd_num_sim_clock_cycle);
+
+  return recmd_num_sim_clock_cycle; 
+}
+
 /********************************************************************
  * Annotate simulation setting based on VPR results
  *  - If the operating clock frequency is set to follow the vpr timing results,
@@ -60,6 +166,7 @@ bool is_vpr_rr_graph_supported(const RRGraph& rr_graph) {
  *******************************************************************/
 static 
 void annotate_simulation_setting(const AtomContext& atom_ctx, 
+                                 const std::unordered_map<AtomNetId, t_net_power>& net_activity, 
                                  SimulationSetting& sim_setting) {
 
   /* Find if the operating frequency is binded to vpr results */
@@ -90,6 +197,19 @@ void annotate_simulation_setting(const AtomContext& atom_ctx,
   }
   VTR_LOG("Will apply operating clock frequency %g [MHz] to simulations\n",
           sim_setting.operating_clock_frequency() / 1e6);
+
+  if (0. == sim_setting.num_clock_cycles()) {
+    /* Find the number of clock cycles to be used in simulation by average over the signal activity */
+
+    VTR_LOG("User specified the number of operating clock cycles to be inferred from signal activities\n");
+    size_t num_clock_cycles = recommend_num_sim_clock_cycle(atom_ctx,
+                                                            net_activity, 
+                                                            0.5);
+    sim_setting.set_num_clock_cycles(num_clock_cycles);
+
+    VTR_LOG("Will apply %lu operating clock cycles to simulations\n",
+            sim_setting.num_clock_cycles());
+  }
 }
 
 /********************************************************************
@@ -105,6 +225,7 @@ void link_arch(OpenfpgaContext& openfpga_ctx,
 
   vtr::ScopedStartFinishTimer timer("Link OpenFPGA architecture to VPR architecture");
 
+  CommandOptionId opt_activity_file = cmd.option("activity_file");
   CommandOptionId opt_verbose = cmd.option("verbose");
 
   /* Annotate pb_type graphs
@@ -165,8 +286,20 @@ void link_arch(OpenfpgaContext& openfpga_ctx,
                          g_vpr_ctx.placement(),
                          openfpga_ctx.mutable_vpr_placement_annotation());
 
-  /* TODO: Annotate the number of clock cycles and clock frequency by following VPR results */
+  /* Read activity file is manadatory in the following flow-run settings
+   * - When users specify that number of clock cycles 
+   *   should be inferred from FPGA implmentation
+   * - When FPGA-SPICE is enabled
+   */
+  openfpga_ctx.mutable_net_activity() = read_activity(g_vpr_ctx.atom().nlist,
+                                                      cmd_context.option_value(cmd, opt_activity_file).c_str());
+
+  /* TODO: Annotate the number of clock cycles and clock frequency by following VPR results
+   * We SHOULD create a new simulation setting for OpenFPGA use only
+   * Avoid overwrite the raw data achieved when parsing!!!
+   */
   annotate_simulation_setting(g_vpr_ctx.atom(),
+                              openfpga_ctx.net_activity(),
                               openfpga_ctx.mutable_arch().sim_setting);
 } 
 
diff --git a/openfpga/src/base/openfpga_setup_command.cpp b/openfpga/src/base/openfpga_setup_command.cpp
index e84227187..e3354d046 100644
--- a/openfpga/src/base/openfpga_setup_command.cpp
+++ b/openfpga/src/base/openfpga_setup_command.cpp
@@ -14,9 +14,199 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
+/********************************************************************
+ * - Add a command to Shell environment: read_openfpga_arch
+ * - Add associated options 
+ * - Add command dependency
+ *******************************************************************/
+static 
+ShellCommandId add_openfpga_read_arch_command(openfpga::Shell<OpenfpgaContext>& shell,
+                                              const ShellCommandClassId& cmd_class_id) {
+  Command shell_cmd("read_openfpga_arch");
+
+  /* Add an option '--file' in short '-f'*/
+  CommandOptionId opt_arch_file = shell_cmd.add_option("file", true, "file path to the architecture XML");
+  shell_cmd.set_option_short_name(opt_arch_file, "f");
+  shell_cmd.set_option_require_value(opt_arch_file, openfpga::OPT_STRING);
+
+  /* Add command 'read_openfpga_arch' to the Shell */
+  ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "read OpenFPGA architecture file");
+  shell.set_command_class(shell_cmd_id, cmd_class_id);
+  shell.set_command_execute_function(shell_cmd_id, read_arch);
+
+  return shell_cmd_id;
+}
+
+/********************************************************************
+ * - Add a command to Shell environment: write_openfpga_arch
+ * - Add associated options 
+ * - Add command dependency
+ *******************************************************************/
+static 
+ShellCommandId add_openfpga_write_arch_command(openfpga::Shell<OpenfpgaContext>& shell,
+                                               const ShellCommandClassId& cmd_class_id,
+                                               const std::vector<ShellCommandId>& dependent_cmds) {
+  Command shell_cmd("write_openfpga_arch");
+  /* Add an option '--file' in short '-f'*/
+  CommandOptionId opt_file = shell_cmd.add_option("file", true, "file path to the architecture XML");
+  shell_cmd.set_option_short_name(opt_file, "f");
+  shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING);
+
+  /* Add command 'write_openfpga_arch' to the Shell */
+  ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "write OpenFPGA architecture file");
+  shell.set_command_class(shell_cmd_id, cmd_class_id);
+  shell.set_command_const_execute_function(shell_cmd_id, write_arch);
+
+  /* The 'write_openfpga_arch' command should NOT be executed before 'read_openfpga_arch' */
+  shell.set_command_dependency(shell_cmd_id, dependent_cmds);
+
+  return shell_cmd_id;
+}
+
+/********************************************************************
+ * - Add a command to Shell environment: link_openfpga_arch
+ * - Add associated options 
+ * - Add command dependency
+ *******************************************************************/
+static 
+ShellCommandId add_openfpga_link_arch_command(openfpga::Shell<OpenfpgaContext>& shell,
+                                              const ShellCommandClassId& cmd_class_id,
+                                              const std::vector<ShellCommandId>& dependent_cmds) {
+  Command shell_cmd("link_openfpga_arch");
+
+  /* Add an option '--activity_file'*/
+  CommandOptionId opt_act_file = shell_cmd.add_option("activity_file", true, "file path to the signal activity");
+  shell_cmd.set_option_require_value(opt_act_file, openfpga::OPT_STRING);
+
+  /* Add an option '--verbose' */
+  shell_cmd.add_option("verbose", false, "Show verbose outputs");
+  
+  /* Add command 'link_openfpga_arch' to the Shell */
+  ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "Bind OpenFPGA architecture to VPR");
+  shell.set_command_class(shell_cmd_id, cmd_class_id);
+  shell.set_command_execute_function(shell_cmd_id, link_arch);
+
+  /* The 'link_openfpga_arch' command should NOT be executed before 'read_openfpga_arch' and 'vpr' */
+  shell.set_command_dependency(shell_cmd_id, dependent_cmds);
+
+  return shell_cmd_id;
+}
+
+/********************************************************************
+ * - Add a command to Shell environment: check_netlist_naming_conflict
+ * - Add associated options 
+ * - Add command dependency
+ *******************************************************************/
+static 
+ShellCommandId add_openfpga_check_netlist_naming_conflict_command(openfpga::Shell<OpenfpgaContext>& shell,
+                                                                  const ShellCommandClassId& cmd_class_id,
+                                                                  const std::vector<ShellCommandId>& dependent_cmds) {
+
+  Command shell_cmd("check_netlist_naming_conflict");
+
+  /* Add an option '--fix' */
+  shell_cmd.add_option("fix", false, "Apply correction to any conflicts found");
+
+  /* Add an option '--report' */
+  CommandOptionId opt_rpt = shell_cmd.add_option("report", false, "Output a report file about what any correction applied");
+  shell_cmd.set_option_require_value(opt_rpt, openfpga::OPT_STRING);
+
+  /* Add command 'check_netlist_naming_conflict' to the Shell */
+  ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "Check any block/net naming in users' BLIF netlist violates the syntax of fabric generator");
+  shell.set_command_class(shell_cmd_id, cmd_class_id);
+  shell.set_command_execute_function(shell_cmd_id, check_netlist_naming_conflict);
+
+  /* The 'link_openfpga_arch' command should NOT be executed before 'vpr' */
+  shell.set_command_dependency(shell_cmd_id, dependent_cmds);
+
+  return shell_cmd_id;
+}
+
+/********************************************************************
+ * - Add a command to Shell environment: pb_pin_fixup
+ * - Add associated options 
+ * - Add command dependency
+ *******************************************************************/
+static 
+ShellCommandId add_openfpga_pb_pin_fixup_command(openfpga::Shell<OpenfpgaContext>& shell,
+                                                 const ShellCommandClassId& cmd_class_id,
+                                                 const std::vector<ShellCommandId>& dependent_cmds) {
+
+  Command shell_cmd("pb_pin_fixup");
+  /* Add an option '--verbose' */
+  shell_cmd.add_option("verbose", false, "Show verbose outputs");
+
+  /* Add command 'pb_pin_fixup' to the Shell */
+  ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "Fix up the packing results due to pin swapping during routing stage");
+  shell.set_command_class(shell_cmd_id, cmd_class_id);
+  shell.set_command_execute_function(shell_cmd_id, pb_pin_fixup);
+
+  /* The 'pb_pin_fixup' command should NOT be executed before 'read_openfpga_arch' and 'vpr' */
+  shell.set_command_dependency(shell_cmd_id, dependent_cmds);
+
+  return shell_cmd_id;
+}
+
+/********************************************************************
+ * - Add a command to Shell environment: lut_truth_table_fixup
+ * - Add associated options 
+ * - Add command dependency
+ *******************************************************************/
+static 
+ShellCommandId add_openfpga_lut_truth_table_fixup_command(openfpga::Shell<OpenfpgaContext>& shell,
+                                                          const ShellCommandClassId& cmd_class_id,
+                                                          const std::vector<ShellCommandId>& dependent_cmds) {
+
+  Command shell_cmd("lut_truth_table_fixup");
+  /* Add an option '--verbose' */
+  shell_cmd.add_option("verbose", false, "Show verbose outputs");
+
+  /* Add command 'lut_truth_table_fixup' to the Shell */
+  ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "Fix up the truth table of Look-Up Tables due to pin swapping during packing stage");
+  shell.set_command_class(shell_cmd_id, cmd_class_id);
+  shell.set_command_execute_function(shell_cmd_id, lut_truth_table_fixup);
+
+  /* The 'lut_truth_table_fixup' command should NOT be executed before 'read_openfpga_arch' and 'vpr' */
+  shell.set_command_dependency(shell_cmd_id, dependent_cmds);
+
+  return shell_cmd_id;
+}
+
+/********************************************************************
+ * - Add a command to Shell environment: build_fabric
+ * - Add associated options 
+ * - Add command dependency
+ *******************************************************************/
+static 
+ShellCommandId add_openfpga_build_fabric_command(openfpga::Shell<OpenfpgaContext>& shell,
+                                                 const ShellCommandClassId& cmd_class_id,
+                                                 const std::vector<ShellCommandId>& dependent_cmds) {
+
+  Command shell_cmd("build_fabric");
+
+  /* Add an option '--compress_routing' */
+  shell_cmd.add_option("compress_routing", false, "Compress the number of unique routing modules by identifying the unique GSBs");
+
+  /* Add an option '--duplicate_grid_pin' */
+  shell_cmd.add_option("duplicate_grid_pin", false, "Duplicate the pins on the same side of a grid");
+
+  /* Add an option '--verbose' */
+  shell_cmd.add_option("verbose", false, "Show verbose outputs");
+
+  /* Add command 'compact_routing_hierarchy' to the Shell */
+  ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "Build the FPGA fabric in a graph of modules");
+  shell.set_command_class(shell_cmd_id, cmd_class_id);
+  shell.set_command_execute_function(shell_cmd_id, build_fabric);
+
+  /* The 'build_fabric' command should NOT be executed before 'link_openfpga_arch' */
+  shell.set_command_dependency(shell_cmd_id, dependent_cmds);
+
+  return shell_cmd_id;
+}
+
 void add_openfpga_setup_commands(openfpga::Shell<OpenfpgaContext>& shell) {
   /* Get the unique id of 'vpr' command which is to be used in creating the dependency graph */
-  const ShellCommandId& shell_cmd_vpr_id = shell.command(std::string("vpr"));
+  const ShellCommandId& vpr_cmd_id = shell.command(std::string("vpr"));
 
   /* Add a new class of commands */
   ShellCommandClassId openfpga_setup_cmd_class = shell.add_command_class("OpenFPGA setup");
@@ -24,119 +214,62 @@ void add_openfpga_setup_commands(openfpga::Shell<OpenfpgaContext>& shell) {
   /******************************** 
    * Command 'read_openfpga_arch' 
    */
-  Command shell_cmd_read_arch("read_openfpga_arch");
-  /* Add an option '--file' in short '-f'*/
-  CommandOptionId read_arch_opt_file = shell_cmd_read_arch.add_option("file", true, "file path to the architecture XML");
-  shell_cmd_read_arch.set_option_short_name(read_arch_opt_file, "f");
-  shell_cmd_read_arch.set_option_require_value(read_arch_opt_file, openfpga::OPT_STRING);
-  
-  /* Add command 'read_openfpga_arch' to the Shell */
-  ShellCommandId shell_cmd_read_arch_id = shell.add_command(shell_cmd_read_arch, "read OpenFPGA architecture file");
-  shell.set_command_class(shell_cmd_read_arch_id, openfpga_setup_cmd_class);
-  shell.set_command_execute_function(shell_cmd_read_arch_id, read_arch);
+  ShellCommandId read_arch_cmd_id = add_openfpga_read_arch_command(shell,
+                                                                   openfpga_setup_cmd_class);
 
   /******************************** 
    * Command 'write_openfpga_arch' 
    */
-  Command shell_cmd_write_arch("write_openfpga_arch");
-  /* Add an option '--file' in short '-f'*/
-  CommandOptionId write_arch_opt_file = shell_cmd_write_arch.add_option("file", true, "file path to the architecture XML");
-  shell_cmd_write_arch.set_option_short_name(write_arch_opt_file, "f");
-  shell_cmd_write_arch.set_option_require_value(write_arch_opt_file, openfpga::OPT_STRING);
-
-  /* Add command 'write_openfpga_arch' to the Shell */
-  ShellCommandId shell_cmd_write_arch_id = shell.add_command(shell_cmd_write_arch, "write OpenFPGA architecture file");
-  shell.set_command_class(shell_cmd_write_arch_id, openfpga_setup_cmd_class);
-  shell.set_command_const_execute_function(shell_cmd_write_arch_id, write_arch);
-  /* The 'write_openfpga_arch' command should NOT be executed before 'read_openfpga_arch' */
-  shell.set_command_dependency(shell_cmd_write_arch_id, std::vector<ShellCommandId>(1, shell_cmd_read_arch_id));
+  std::vector<ShellCommandId> write_arch_dependent_cmds(1, read_arch_cmd_id);
+  add_openfpga_write_arch_command(shell,
+                                  openfpga_setup_cmd_class,
+                                  write_arch_dependent_cmds);
 
   /******************************** 
    * Command 'link_openfpga_arch' 
    */
-  Command shell_cmd_link_openfpga_arch("link_openfpga_arch");
-  /* Add an option '--verbose' */
-  shell_cmd_link_openfpga_arch.add_option("verbose", false, "Show verbose outputs");
-  
-  /* Add command 'link_openfpga_arch' to the Shell */
-  ShellCommandId shell_cmd_link_openfpga_arch_id = shell.add_command(shell_cmd_link_openfpga_arch, "Bind OpenFPGA architecture to VPR");
-  shell.set_command_class(shell_cmd_link_openfpga_arch_id, openfpga_setup_cmd_class);
-  shell.set_command_execute_function(shell_cmd_link_openfpga_arch_id, link_arch);
-  /* The 'link_openfpga_arch' command should NOT be executed before 'read_openfpga_arch' and 'vpr' */
-  std::vector<ShellCommandId> cmd_dependency_link_openfpga_arch;
-  cmd_dependency_link_openfpga_arch.push_back(shell_cmd_read_arch_id);
-  cmd_dependency_link_openfpga_arch.push_back(shell_cmd_vpr_id);
-  shell.set_command_dependency(shell_cmd_link_openfpga_arch_id, cmd_dependency_link_openfpga_arch);
-
+  std::vector<ShellCommandId> link_arch_dependent_cmds;
+  link_arch_dependent_cmds.push_back(read_arch_cmd_id);
+  link_arch_dependent_cmds.push_back(vpr_cmd_id);
+  ShellCommandId link_arch_cmd_id = add_openfpga_link_arch_command(shell,
+                                                                   openfpga_setup_cmd_class,
+                                                                   link_arch_dependent_cmds);
   /******************************************* 
    * Command 'check_netlist_naming_conflict'
    */ 
-  Command shell_cmd_check_netlist_naming_conflict("check_netlist_naming_conflict");
-  /* Add an option '--fix' */
-  shell_cmd_check_netlist_naming_conflict.add_option("fix", false, "Apply correction to any conflicts found");
-  /* Add an option '--report' */
-  CommandOptionId check_netlist_opt_rpt = shell_cmd_check_netlist_naming_conflict.add_option("report", false, "Output a report file about what any correction applied");
-  shell_cmd_check_netlist_naming_conflict.set_option_require_value(check_netlist_opt_rpt, openfpga::OPT_STRING);
-
-  /* Add command 'check_netlist_naming_conflict' to the Shell */
-  ShellCommandId shell_cmd_check_netlist_naming_conflict_id = shell.add_command(shell_cmd_check_netlist_naming_conflict, "Check any block/net naming in users' BLIF netlist violates the syntax of fabric generator");
-  shell.set_command_class(shell_cmd_check_netlist_naming_conflict_id, openfpga_setup_cmd_class);
-  shell.set_command_execute_function(shell_cmd_check_netlist_naming_conflict_id, check_netlist_naming_conflict);
-  /* The 'link_openfpga_arch' command should NOT be executed before 'vpr' */
-  std::vector<ShellCommandId> cmd_dependency_check_netlist_naming_conflict(1, shell_cmd_vpr_id);
-  shell.set_command_dependency(shell_cmd_link_openfpga_arch_id, cmd_dependency_check_netlist_naming_conflict);
+  std::vector<ShellCommandId> nlist_naming_dependent_cmds;
+  nlist_naming_dependent_cmds.push_back(vpr_cmd_id);
+  add_openfpga_check_netlist_naming_conflict_command(shell,
+                                                     openfpga_setup_cmd_class,
+                                                     nlist_naming_dependent_cmds);
 
   /******************************** 
    * Command 'pb_pin_fixup' 
    */
-  Command shell_cmd_pb_pin_fixup("pb_pin_fixup");
-  /* Add an option '--verbose' */
-  shell_cmd_pb_pin_fixup.add_option("verbose", false, "Show verbose outputs");
-
-  /* Add command 'pb_pin_fixup' to the Shell */
-  ShellCommandId shell_cmd_pb_pin_fixup_id = shell.add_command(shell_cmd_pb_pin_fixup, "Fix up the packing results due to pin swapping during routing stage");
-  shell.set_command_class(shell_cmd_pb_pin_fixup_id, openfpga_setup_cmd_class);
-  shell.set_command_execute_function(shell_cmd_pb_pin_fixup_id, pb_pin_fixup);
-  /* The 'pb_pin_fixup' command should NOT be executed before 'read_openfpga_arch' and 'vpr' */
-  std::vector<ShellCommandId> cmd_dependency_pb_pin_fixup;
-  cmd_dependency_pb_pin_fixup.push_back(shell_cmd_read_arch_id);
-  cmd_dependency_pb_pin_fixup.push_back(shell_cmd_vpr_id);
-  shell.set_command_dependency(shell_cmd_pb_pin_fixup_id, cmd_dependency_pb_pin_fixup);
+  std::vector<ShellCommandId> pb_pin_fixup_dependent_cmds;
+  pb_pin_fixup_dependent_cmds.push_back(read_arch_cmd_id);
+  pb_pin_fixup_dependent_cmds.push_back(vpr_cmd_id);
+  add_openfpga_pb_pin_fixup_command(shell,
+                                    openfpga_setup_cmd_class,
+                                    pb_pin_fixup_dependent_cmds);
 
   /******************************** 
    * Command 'lut_truth_table_fixup' 
    */
-  Command shell_cmd_lut_truth_table_fixup("lut_truth_table_fixup");
-  /* Add an option '--verbose' */
-  shell_cmd_lut_truth_table_fixup.add_option("verbose", false, "Show verbose outputs");
-
-  /* Add command 'lut_truth_table_fixup' to the Shell */
-  ShellCommandId shell_cmd_lut_truth_table_fixup_id = shell.add_command(shell_cmd_lut_truth_table_fixup, "Fix up the truth table of Look-Up Tables due to pin swapping during packing stage");
-  shell.set_command_class(shell_cmd_lut_truth_table_fixup_id, openfpga_setup_cmd_class);
-  shell.set_command_execute_function(shell_cmd_lut_truth_table_fixup_id, lut_truth_table_fixup);
-  /* The 'lut_truth_table_fixup' command should NOT be executed before 'read_openfpga_arch' and 'vpr' */
-  std::vector<ShellCommandId> cmd_dependency_lut_truth_table_fixup;
-  cmd_dependency_lut_truth_table_fixup.push_back(shell_cmd_read_arch_id);
-  cmd_dependency_lut_truth_table_fixup.push_back(shell_cmd_vpr_id);
-  shell.set_command_dependency(shell_cmd_lut_truth_table_fixup_id, cmd_dependency_lut_truth_table_fixup);
-
+  std::vector<ShellCommandId> lut_tt_fixup_dependent_cmds;
+  lut_tt_fixup_dependent_cmds.push_back(read_arch_cmd_id);
+  lut_tt_fixup_dependent_cmds.push_back(vpr_cmd_id);
+  add_openfpga_lut_truth_table_fixup_command(shell,
+                                             openfpga_setup_cmd_class,
+                                             lut_tt_fixup_dependent_cmds);
   /******************************** 
    * Command 'build_fabric' 
    */
-  Command shell_cmd_build_fabric("build_fabric");
-  /* Add an option '--verbose' */
-  shell_cmd_build_fabric.add_option("compress_routing", false, "Compress the number of unique routing modules by identifying the unique GSBs");
-  shell_cmd_build_fabric.add_option("duplicate_grid_pin", false, "Duplicate the pins on the same side of a grid");
-  shell_cmd_build_fabric.add_option("verbose", false, "Show verbose outputs");
-
-  /* Add command 'compact_routing_hierarchy' to the Shell */
-  ShellCommandId shell_cmd_build_fabric_id = shell.add_command(shell_cmd_build_fabric, "Build the FPGA fabric in a graph of modules");
-  shell.set_command_class(shell_cmd_build_fabric_id, openfpga_setup_cmd_class);
-  shell.set_command_execute_function(shell_cmd_build_fabric_id, build_fabric);
-  /* The 'build_fabric' command should NOT be executed before 'link_openfpga_arch' */
-  std::vector<ShellCommandId> cmd_dependency_build_fabric;
-  cmd_dependency_build_fabric.push_back(shell_cmd_link_openfpga_arch_id);
-  shell.set_command_dependency(shell_cmd_build_fabric_id, cmd_dependency_build_fabric);
+  std::vector<ShellCommandId> build_fabric_dependent_cmds;
+  build_fabric_dependent_cmds.push_back(link_arch_cmd_id);
+  add_openfpga_build_fabric_command(shell,
+                                    openfpga_setup_cmd_class,
+                                    build_fabric_dependent_cmds);
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/test_script/and_k6_frac.openfpga b/openfpga/test_script/and_k6_frac.openfpga
index 51a1c5ae2..8a16f8cb5 100644
--- a/openfpga/test_script/and_k6_frac.openfpga
+++ b/openfpga/test_script/and_k6_frac.openfpga
@@ -8,7 +8,7 @@ read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
 #write_openfpga_arch -f ./arch_echo.xml
 
 # Annotate the OpenFPGA architecture to VPR data base
-link_openfpga_arch #--verbose
+link_openfpga_arch --activity_file ./test_blif/and.act #--verbose
 
 # Check and correct any naming conflicts in the BLIF netlist
 check_netlist_naming_conflict --fix --report ./netlist_renaming.xml

From aa66042dfb0a5063f7b3746f4cdad77c056ce59d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 29 Feb 2020 15:19:02 -0700
Subject: [PATCH 240/645] move simulation setting annotation to a separated
 source file

---
 .../annotate_simulation_setting.cpp           | 227 ++++++++++++++++++
 .../annotation/annotate_simulation_setting.h  |  23 ++
 openfpga/src/base/openfpga_link_arch.cpp      | 163 +------------
 3 files changed, 251 insertions(+), 162 deletions(-)
 create mode 100644 openfpga/src/annotation/annotate_simulation_setting.cpp
 create mode 100644 openfpga/src/annotation/annotate_simulation_setting.h

diff --git a/openfpga/src/annotation/annotate_simulation_setting.cpp b/openfpga/src/annotation/annotate_simulation_setting.cpp
new file mode 100644
index 000000000..a42816297
--- /dev/null
+++ b/openfpga/src/annotation/annotate_simulation_setting.cpp
@@ -0,0 +1,227 @@
+/********************************************************************
+ * This file includes functions that are used to annotate pb_graph_node
+ * and pb_graph_pins from VPR to OpenFPGA
+ *******************************************************************/
+#include <cmath>
+#include <iterator>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+/* Headers from vpr library */
+#include "timing_info.h"
+#include "AnalysisDelayCalculator.h"
+#include "net_delay.h"
+
+#include "annotate_simulation_setting.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Find the average signal density for all the nets of user's benchmark
+ *******************************************************************/
+static 
+float average_atom_net_signal_density(const AtomContext& atom_ctx,
+                                      const std::unordered_map<AtomNetId, t_net_power>& net_activity) {
+  float avg_density = 0.;
+  size_t net_cnt = 0;
+
+  /* get the average density of all the nets */
+  for (const AtomNetId& atom_net : atom_ctx.nlist.nets()) {
+    /* Skip the nets without any activity annotation */
+    if (0 == net_activity.count(atom_net)) {
+      continue;
+    }
+
+    /* Only care non-zero density nets */
+    if (0. == net_activity.at(atom_net).density) {
+      continue;
+    }
+
+    avg_density += net_activity.at(atom_net).density; 
+    net_cnt++;
+  }
+
+  return avg_density / net_cnt; 
+}                                     
+
+/********************************************************************
+ * Find the average signal density for all the nets of user's benchmark
+ * by applying a weight to each net density
+ *******************************************************************/
+static 
+float average_weighted_atom_net_signal_density(const AtomContext& atom_ctx,
+                                               const std::unordered_map<AtomNetId, t_net_power>& net_activity) {
+
+  float weighted_avg_density = 0.;
+  size_t weighted_net_cnt = 0;
+
+  /* get the average density of all the nets */
+  for (const AtomNetId& atom_net : atom_ctx.nlist.nets()) {
+    /* Skip the nets without any activity annotation */
+    if (0 == net_activity.count(atom_net)) {
+      continue;
+    }
+
+    /* Only care non-zero density nets */
+    if (0. == net_activity.at(atom_net).density) {
+      continue;
+    }
+
+    /* Consider the weight of fan-out */
+    size_t net_weight; 
+    if (0 == std::distance(atom_ctx.nlist.net_sinks(atom_net).begin(), atom_ctx.nlist.net_sinks(atom_net).end())) {
+      net_weight = 1;
+    } else {
+      VTR_ASSERT(0 < std::distance(atom_ctx.nlist.net_sinks(atom_net).begin(), atom_ctx.nlist.net_sinks(atom_net).end()));
+      net_weight = std::distance(atom_ctx.nlist.net_sinks(atom_net).begin(), atom_ctx.nlist.net_sinks(atom_net).end());
+    }
+    weighted_avg_density += net_activity.at(atom_net).density* net_weight;
+    weighted_net_cnt += net_weight;
+  }
+
+  return weighted_avg_density / weighted_net_cnt; 
+}
+
+/********************************************************************
+ * Find median of signal density of all the nets 
+ *******************************************************************/
+static 
+size_t median_atom_net_signal_density(const AtomContext& atom_ctx,
+                                      const std::unordered_map<AtomNetId, t_net_power>& net_activity) {
+  /* Sort the net density */
+  std::vector<float> net_densities;
+
+  net_densities.reserve(net_activity.size());
+
+  for (const AtomNetId& atom_net : atom_ctx.nlist.nets()) {
+    /* Skip the nets without any activity annotation */
+    if (0 == net_activity.count(atom_net)) {
+      continue;
+    }
+
+    net_densities.push_back(net_activity.at(atom_net).density);
+  }
+  std::sort(net_densities.begin(), net_densities.end());
+
+  /* Get the median */
+  /* check for even case */
+  if (net_densities.size() % 2 != 0) { 
+    return net_densities[size_t(net_densities.size() / 2)];
+  }            
+  
+  return 0.5 * (net_densities[size_t((net_densities.size() - 1) / 2)] + net_densities[size_t((net_densities.size() - 1) / 2)]);
+}
+
+/********************************************************************
+ * Find the number of clock cycles in simulation based on the average signal density
+ *******************************************************************/
+static 
+size_t recommend_num_sim_clock_cycle(const AtomContext& atom_ctx,
+                                     const std::unordered_map<AtomNetId, t_net_power>& net_activity, 
+                                     const float& sim_window_size) {
+
+  float average_density = average_atom_net_signal_density(atom_ctx, net_activity);
+  float average_weighted_density = average_weighted_atom_net_signal_density(atom_ctx, net_activity);
+  float median_density = median_atom_net_signal_density(atom_ctx, net_activity);
+
+  VTR_LOG("Average net density: %.2f\n",
+          average_density);
+  VTR_LOG("Median net density: %.2f\n",
+          median_density);
+  VTR_LOG("Average net density after weighting: %.2f\n",
+          average_weighted_density);
+
+  /* We have three choices in selecting the number of clock cycles based on signal density
+   * 1. average signal density 
+   * 2. median signal density
+   * 3. a mixed of average and median signal density 
+   */
+  size_t recmd_num_clock_cycles = 0;
+  if ( (0. == median_density) 
+    && (0. == average_density) ) {
+    recmd_num_clock_cycles = 1;
+    VTR_LOG_WARN("All the signal density is zero!\nNumber of clock cycles in simulations are set to be %ld!\n",
+                 recmd_num_clock_cycles);
+  } else if (0. == average_density) {
+    recmd_num_clock_cycles = (size_t)round(1 / median_density); 
+  } else if (0. == median_density) {
+    recmd_num_clock_cycles = (size_t)round(1 / average_density);
+  } else {
+    /* add a sim window size to balance the weight of average density and median density
+     * In practice, we find that there could be huge difference between avereage and median values 
+     * For a reasonable number of simulation clock cycles, we do this window size.
+     */
+    recmd_num_clock_cycles = (size_t)round(1 / (sim_window_size * average_density + (1 - sim_window_size) * median_density ));
+
+    VTR_LOG("Window size set for simulation: %.2f\n",
+            sim_window_size);
+    VTR_LOG("Net density after applying window size : %.2f\n", 
+            (sim_window_size * average_density + (1 - sim_window_size) * median_density));
+  }
+  
+  VTR_ASSERT(0 < recmd_num_clock_cycles);
+
+  return recmd_num_clock_cycles; 
+}
+
+/********************************************************************
+ * Annotate simulation setting based on VPR results
+ *  - If the operating clock frequency is set to follow the vpr timing results,
+ *    we will set a new operating clock frequency here
+ *  - If the number of clock cycles in simulation is set to be automatically determined,
+ *    we will infer the number based on the average signal density
+ *******************************************************************/
+void annotate_simulation_setting(const AtomContext& atom_ctx, 
+                                 const std::unordered_map<AtomNetId, t_net_power>& net_activity, 
+                                 SimulationSetting& sim_setting) {
+
+  /* Find if the operating frequency is binded to vpr results */
+  if (0. == sim_setting.operating_clock_frequency()) {
+    VTR_LOG("User specified the operating clock frequency to use VPR results\n");
+    /* Run timing analysis and collect critical path delay
+     * This code is copied from function vpr_analysis() in vpr_api.h 
+     * Should keep updated to latest VPR code base
+     * Note:
+     *   - MUST mention in documentation that VPR should be run in timing enabled mode
+     */
+    vtr::vector<ClusterNetId, float*> net_delay;
+    vtr::t_chunk net_delay_ch;
+    /* Load the net delays */
+    net_delay = alloc_net_delay(&net_delay_ch);
+    load_net_delay_from_routing(net_delay);
+
+    /* Do final timing analysis */
+    auto analysis_delay_calc = std::make_shared<AnalysisDelayCalculator>(atom_ctx.nlist, atom_ctx.lookup, net_delay);
+    auto timing_info = make_setup_hold_timing_info(analysis_delay_calc);
+    timing_info->update();
+
+    /* Get critical path delay. Update simulation settings */
+    float T_crit = timing_info->least_slack_critical_path().delay() * (1. + sim_setting.operating_clock_frequency_slack());
+    sim_setting.set_operating_clock_frequency(1 / T_crit); 
+    VTR_LOG("Use VPR critical path delay %g [ns] with a %g [%] slack in OpenFPGA.\n",
+            T_crit / 1e9, sim_setting.operating_clock_frequency_slack() * 100);
+  }
+  VTR_LOG("Will apply operating clock frequency %g [MHz] to simulations\n",
+          sim_setting.operating_clock_frequency() / 1e6);
+
+  if (0. == sim_setting.num_clock_cycles()) {
+    /* Find the number of clock cycles to be used in simulation 
+     * by average over the signal activity 
+     */
+    VTR_LOG("User specified the number of operating clock cycles to be inferred from signal activities\n");
+
+    /* Use a fixed simulation window size now. TODO: this could be specified by users */
+    size_t num_clock_cycles = recommend_num_sim_clock_cycle(atom_ctx,
+                                                            net_activity, 
+                                                            0.5);
+    sim_setting.set_num_clock_cycles(num_clock_cycles);
+
+    VTR_LOG("Will apply %lu operating clock cycles to simulations\n",
+            sim_setting.num_clock_cycles());
+  }
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/annotation/annotate_simulation_setting.h b/openfpga/src/annotation/annotate_simulation_setting.h
new file mode 100644
index 000000000..b4db463a9
--- /dev/null
+++ b/openfpga/src/annotation/annotate_simulation_setting.h
@@ -0,0 +1,23 @@
+#ifndef ANNOTATE_SIMULATION_SETTING_H
+#define ANNOTATE_SIMULATION_SETTING_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "vpr_context.h"
+#include "openfpga_context.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void annotate_simulation_setting(const AtomContext& atom_ctx, 
+                                 const std::unordered_map<AtomNetId, t_net_power>& net_activity, 
+                                 SimulationSetting& sim_setting);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/base/openfpga_link_arch.cpp b/openfpga/src/base/openfpga_link_arch.cpp
index fe89b7024..e0e52f878 100644
--- a/openfpga/src/base/openfpga_link_arch.cpp
+++ b/openfpga/src/base/openfpga_link_arch.cpp
@@ -2,8 +2,6 @@
  * This file includes functions to read an OpenFPGA architecture file
  * which are built on the libarchopenfpga library
  *******************************************************************/
-#include <cmath>
-#include <iterator>
 
 /* Headers from vtrutil library */
 #include "vtr_time.h"
@@ -11,9 +9,6 @@
 #include "vtr_log.h"
 
 /* Headers from vpr library */
-#include "timing_info.h"
-#include "AnalysisDelayCalculator.h"
-#include "net_delay.h"
 #include "read_activity.h"
 
 #include "vpr_device_annotation.h"
@@ -22,6 +17,7 @@
 #include "annotate_pb_graph.h"
 #include "annotate_routing.h"
 #include "annotate_rr_graph.h"
+#include "annotate_simulation_setting.h"
 #include "mux_library_builder.h"
 #include "build_tile_direct.h"
 #include "annotate_placement.h"
@@ -55,163 +51,6 @@ bool is_vpr_rr_graph_supported(const RRGraph& rr_graph) {
   return true;
 }
 
-/********************************************************************
- * Find the number of clock cycles in simulation based on the average signal density
- *******************************************************************/
-static 
-size_t recommend_num_sim_clock_cycle(const AtomContext& atom_ctx,
-                                     const std::unordered_map<AtomNetId, t_net_power>& net_activity, 
-                                     const float& sim_window_size) {
-  size_t recmd_num_sim_clock_cycle = 0;
-
-  float avg_density = 0.;
-  size_t net_cnt = 0;
-
-  float weighted_avg_density = 0.;
-  size_t weighted_net_cnt = 0;
-
-  /* get the average density of all the nets */
-  for (const AtomNetId& atom_net : atom_ctx.nlist.nets()) {
-    /* Skip the nets without any activity annotation */
-    if (0 == net_activity.count(atom_net)) {
-      continue;
-    }
-
-    /* Only care non-zero density nets */
-    if (0. == net_activity.at(atom_net).density) {
-      continue;
-    }
-
-    avg_density += net_activity.at(atom_net).density; 
-    net_cnt++;
-
-    /* Consider the weight of fan-out */
-    size_t net_weight; 
-    if (0 == std::distance(atom_ctx.nlist.net_sinks(atom_net).begin(), atom_ctx.nlist.net_sinks(atom_net).end())) {
-      net_weight = 1;
-    } else {
-      VTR_ASSERT(0 < std::distance(atom_ctx.nlist.net_sinks(atom_net).begin(), atom_ctx.nlist.net_sinks(atom_net).end()));
-      net_weight = std::distance(atom_ctx.nlist.net_sinks(atom_net).begin(), atom_ctx.nlist.net_sinks(atom_net).end());
-    }
-    weighted_avg_density += net_activity.at(atom_net).density* net_weight;
-    weighted_net_cnt += net_weight;
-  }
-  avg_density = avg_density / net_cnt; 
-  weighted_avg_density = weighted_avg_density / weighted_net_cnt; 
-
-  /* Sort the net density */
-  std::vector<float> net_densities;
-  net_densities.reserve(net_cnt);
-  for (const AtomNetId& atom_net : atom_ctx.nlist.nets()) {
-    /* Skip the nets without any activity annotation */
-    if (0 == net_activity.count(atom_net)) {
-      continue;
-    }
-
-    /* Only care non-zero density nets */
-    if (0. == net_activity.at(atom_net).density) {
-      continue;
-    }
-
-    net_densities.push_back(net_activity.at(atom_net).density);
-  }
-  std::sort(net_densities.begin(), net_densities.end());
-  /* Get the median */
-  float median_density = 0.;
-  /* check for even case */
-  if (net_cnt % 2 != 0) { 
-    median_density = net_densities[size_t(net_cnt / 2)];
-  } else {              
-    median_density = 0.5 * (net_densities[size_t((net_cnt - 1) / 2)] + net_densities[size_t((net_cnt - 1) / 2)]);
-  }
-
-  /* It may be more reasonable to use median 
-   * But, if median density is 0, we use average density
-  */
-  if ((0. == median_density) && (0. == avg_density)) {
-    recmd_num_sim_clock_cycle = 1;
-    VTR_LOG_WARN("All the signal density is zero!\nNumber of clock cycles in simulations are set to be %ld!\n",
-                 recmd_num_sim_clock_cycle);
-  } else if (0. == avg_density) {
-      recmd_num_sim_clock_cycle = (int)round(1 / median_density); 
-  } else if (0. == median_density) {
-      recmd_num_sim_clock_cycle = (int)round(1 / avg_density);
-  } else {
-    /* add a sim window size to balance the weight of average density and median density
-     * In practice, we find that there could be huge difference between avereage and median values 
-     * For a reasonable number of simulation clock cycles, we do this window size.
-     */
-    recmd_num_sim_clock_cycle = (int)round(1 / (sim_window_size * avg_density + (1 - sim_window_size) * median_density ));
-  }
-  
-  VTR_ASSERT(0 < recmd_num_sim_clock_cycle);
-
-  VTR_LOG("Average net density: %.2f\n", avg_density);
-  VTR_LOG("Median net density: %.2f\n", median_density);
-  VTR_LOG("Average net density after weighting: %.2f\n", weighted_avg_density);
-  VTR_LOG("Window size set for Simulation: %.2f\n", sim_window_size);
-  VTR_LOG("Net density after Window size : %.2f\n", 
-          (sim_window_size * avg_density + (1 - sim_window_size) * median_density));
-  VTR_LOG("Recommend no. of clock cycles: %ld\n", recmd_num_sim_clock_cycle);
-
-  return recmd_num_sim_clock_cycle; 
-}
-
-/********************************************************************
- * Annotate simulation setting based on VPR results
- *  - If the operating clock frequency is set to follow the vpr timing results,
- *    we will set a new operating clock frequency here
- *  - If the number of clock cycles in simulation is set to be automatically determined,
- *    we will infer the number based on the average signal density
- *******************************************************************/
-static 
-void annotate_simulation_setting(const AtomContext& atom_ctx, 
-                                 const std::unordered_map<AtomNetId, t_net_power>& net_activity, 
-                                 SimulationSetting& sim_setting) {
-
-  /* Find if the operating frequency is binded to vpr results */
-  if (0. == sim_setting.operating_clock_frequency()) {
-    VTR_LOG("User specified the operating clock frequency to use VPR results\n");
-    /* Run timing analysis and collect critical path delay
-     * This code is copied from function vpr_analysis() in vpr_api.h 
-     * Should keep updated to latest VPR code base
-     * Note:
-     *   - MUST mention in documentation that VPR should be run in timing enabled mode
-     */
-    vtr::vector<ClusterNetId, float*> net_delay;
-    vtr::t_chunk net_delay_ch;
-    /* Load the net delays */
-    net_delay = alloc_net_delay(&net_delay_ch);
-    load_net_delay_from_routing(net_delay);
-
-    /* Do final timing analysis */
-    auto analysis_delay_calc = std::make_shared<AnalysisDelayCalculator>(atom_ctx.nlist, atom_ctx.lookup, net_delay);
-    auto timing_info = make_setup_hold_timing_info(analysis_delay_calc);
-    timing_info->update();
-
-    /* Get critical path delay. Update simulation settings */
-    float T_crit = timing_info->least_slack_critical_path().delay() * (1. + sim_setting.operating_clock_frequency_slack());
-    sim_setting.set_operating_clock_frequency(1 / T_crit); 
-    VTR_LOG("Use VPR critical path delay %g [ns] with a %g [%] slack in OpenFPGA.\n",
-            T_crit / 1e9, sim_setting.operating_clock_frequency_slack() * 100);
-  }
-  VTR_LOG("Will apply operating clock frequency %g [MHz] to simulations\n",
-          sim_setting.operating_clock_frequency() / 1e6);
-
-  if (0. == sim_setting.num_clock_cycles()) {
-    /* Find the number of clock cycles to be used in simulation by average over the signal activity */
-
-    VTR_LOG("User specified the number of operating clock cycles to be inferred from signal activities\n");
-    size_t num_clock_cycles = recommend_num_sim_clock_cycle(atom_ctx,
-                                                            net_activity, 
-                                                            0.5);
-    sim_setting.set_num_clock_cycles(num_clock_cycles);
-
-    VTR_LOG("Will apply %lu operating clock cycles to simulations\n",
-            sim_setting.num_clock_cycles());
-  }
-}
-
 /********************************************************************
  * Top-level function to link openfpga architecture to VPR, including:
  * - physical pb_type

From a17c14c363551c94939bd7f0cbd4261f2f2115bf Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 2 Mar 2020 10:39:19 -0700
Subject: [PATCH 241/645] clean-up command addition and add fabric bitstream
 building to sample script

---
 .../src/base/openfpga_bitstream_command.cpp   | 132 ++++++++++++------
 openfpga/src/base/openfpga_sdc_command.cpp    |  23 +--
 openfpga/src/base/openfpga_setup_command.cpp  |  19 ++-
 .../src/base/openfpga_verilog_command.cpp     |  40 +++---
 openfpga/test_script/and_k6_frac.openfpga     |   5 +-
 5 files changed, 144 insertions(+), 75 deletions(-)

diff --git a/openfpga/src/base/openfpga_bitstream_command.cpp b/openfpga/src/base/openfpga_bitstream_command.cpp
index 96201b6c7..b64696d79 100644
--- a/openfpga/src/base/openfpga_bitstream_command.cpp
+++ b/openfpga/src/base/openfpga_bitstream_command.cpp
@@ -11,6 +11,88 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
+/********************************************************************
+ * - Add a command to Shell environment: repack
+ * - Add associated options 
+ * - Add command dependency
+ *******************************************************************/
+static 
+ShellCommandId add_openfpga_repack_command(openfpga::Shell<OpenfpgaContext>& shell,
+                                           const ShellCommandClassId& cmd_class_id,
+                                           const std::vector<ShellCommandId>& dependent_cmds) {
+  Command shell_cmd("repack");
+  /* Add an option '--verbose' */
+  shell_cmd.add_option("verbose", false, "Enable verbose output");
+  
+  /* Add command 'repack' to the Shell */
+  ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "Pack physical programmable logic blocks");
+  shell.set_command_class(shell_cmd_id, cmd_class_id);
+  shell.set_command_execute_function(shell_cmd_id, repack);
+
+  /* Add command dependency to the Shell */
+  shell.set_command_dependency(shell_cmd_id, dependent_cmds);
+
+  return shell_cmd_id;
+}
+
+/********************************************************************
+ * - Add a command to Shell environment: build_architecture_bitstream
+ * - Add associated options 
+ * - Add command dependency
+ *******************************************************************/
+static 
+ShellCommandId add_openfpga_arch_bitstream_command(openfpga::Shell<OpenfpgaContext>& shell,
+                                                   const ShellCommandClassId& cmd_class_id,
+                                                   const std::vector<ShellCommandId>& dependent_cmds) {
+  Command shell_cmd("build_architecture_bitstream");
+
+  /* Add an option '--file' in short '-f'*/
+  CommandOptionId opt_file = shell_cmd.add_option("file", true, "file path to output the bitstream database");
+  shell_cmd.set_option_short_name(opt_file, "f");
+  shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING);
+
+  /* Add an option '--verbose' */
+  shell_cmd.add_option("verbose", false, "Enable verbose output");
+  
+  /* Add command 'build_architecture_bitstream' to the Shell */
+  ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "Build fabric-independent bitstream database");
+  shell.set_command_class(shell_cmd_id, cmd_class_id);
+  shell.set_command_execute_function(shell_cmd_id, fpga_bitstream);
+
+  /* Add command dependency to the Shell */
+  shell.set_command_dependency(shell_cmd_id, dependent_cmds);
+
+  return shell_cmd_id;
+}
+
+/********************************************************************
+ * - Add a command to Shell environment: build_fabric_bitstream
+ * - Add associated options 
+ * - Add command dependency
+ *******************************************************************/
+static 
+ShellCommandId add_openfpga_fabric_bitstream_command(openfpga::Shell<OpenfpgaContext>& shell,
+                                                     const ShellCommandClassId& cmd_class_id,
+                                                     const std::vector<ShellCommandId>& dependent_cmds) {
+  Command shell_cmd("build_fabric_bitstream");
+
+  /* Add an option '--verbose' */
+  shell_cmd.add_option("verbose", false, "Enable verbose output");
+
+  /* Add command 'fabric_bitstream' to the Shell */
+  ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "Reorganize the fabric-independent bitstream for the FPGA fabric created by FPGA-Verilog");
+  shell.set_command_class(shell_cmd_id, cmd_class_id);
+  shell.set_command_execute_function(shell_cmd_id, build_fabric_bitstream);
+
+  /* Add command dependency to the Shell */
+  shell.set_command_dependency(shell_cmd_id, dependent_cmds);
+
+  return shell_cmd_id;
+}
+
+/********************************************************************
+ * Top-level function to add all the commands related to FPGA-Bitstream
+ *******************************************************************/
 void add_openfpga_bitstream_commands(openfpga::Shell<OpenfpgaContext>& shell) {
   /* Get the unique id of 'build_fabric' command which is to be used in creating the dependency graph */
   const ShellCommandId& shell_cmd_build_fabric_id = shell.command(std::string("build_fabric"));
@@ -21,58 +103,26 @@ void add_openfpga_bitstream_commands(openfpga::Shell<OpenfpgaContext>& shell) {
   /******************************** 
    * Command 'repack' 
    */
-  Command shell_cmd_repack("repack");
-  /* Add an option '--verbose' */
-  shell_cmd_repack.add_option("verbose", false, "Enable verbose output");
-  
-  /* Add command 'repack' to the Shell */
-  ShellCommandId shell_cmd_repack_id = shell.add_command(shell_cmd_repack, "Pack physical programmable logic blocks");
-  shell.set_command_class(shell_cmd_repack_id, openfpga_bitstream_cmd_class);
-  shell.set_command_execute_function(shell_cmd_repack_id, repack);
-
   /* The 'repack' command should NOT be executed before 'build_fabric' */
   std::vector<ShellCommandId> cmd_dependency_repack;
   cmd_dependency_repack.push_back(shell_cmd_build_fabric_id);
-  shell.set_command_dependency(shell_cmd_repack_id, cmd_dependency_repack);
+  ShellCommandId shell_cmd_repack_id = add_openfpga_repack_command(shell, openfpga_bitstream_cmd_class, cmd_dependency_repack);
 
   /******************************** 
-   * Command 'fpga_bitstream' 
+   * Command 'build_architecture_bitstream' 
    */
-  Command shell_cmd_fpga_bitstream("fpga_bitstream");
-
-  /* Add an option '--file' in short '-f'*/
-  CommandOptionId fpga_bitstream_opt_file = shell_cmd_fpga_bitstream.add_option("file", true, "file path to output the bitstream database");
-  shell_cmd_fpga_bitstream.set_option_short_name(fpga_bitstream_opt_file, "f");
-  shell_cmd_fpga_bitstream.set_option_require_value(fpga_bitstream_opt_file, openfpga::OPT_STRING);
-  /* Add an option '--verbose' */
-  shell_cmd_fpga_bitstream.add_option("verbose", false, "Enable verbose output");
-  
-  /* Add command 'fpga_bitstream' to the Shell */
-  ShellCommandId shell_cmd_fpga_bitstream_id = shell.add_command(shell_cmd_fpga_bitstream, "Build bitstream database");
-  shell.set_command_class(shell_cmd_fpga_bitstream_id, openfpga_bitstream_cmd_class);
-  shell.set_command_execute_function(shell_cmd_fpga_bitstream_id, fpga_bitstream);
-
-  /* The 'fpga_bitstream' command should NOT be executed before 'repack' */
-  std::vector<ShellCommandId> cmd_dependency_fpga_bitstream;
-  cmd_dependency_fpga_bitstream.push_back(shell_cmd_repack_id);
-  shell.set_command_dependency(shell_cmd_fpga_bitstream_id, cmd_dependency_fpga_bitstream);
+  /* The 'build_architecture_bitstream' command should NOT be executed before 'repack' */
+  std::vector<ShellCommandId> cmd_dependency_arch_bitstream;
+  cmd_dependency_arch_bitstream.push_back(shell_cmd_repack_id);
+  ShellCommandId shell_cmd_arch_bitstream_id = add_openfpga_arch_bitstream_command(shell, openfpga_bitstream_cmd_class, cmd_dependency_arch_bitstream);
 
   /******************************** 
    * Command 'build_fabric_bitstream' 
    */
-  Command shell_cmd_fabric_bitstream("build_fabric_bitstream");
-  /* Add an option '--verbose' */
-  shell_cmd_fabric_bitstream.add_option("verbose", false, "Enable verbose output");
-
-  /* Add command 'fabric_bitstream' to the Shell */
-  ShellCommandId shell_cmd_fabric_bitstream_id = shell.add_command(shell_cmd_fabric_bitstream, "Reorganize the fabric-independent bitstream for the FPGA fabric created by FPGA-Verilog");
-  shell.set_command_class(shell_cmd_fabric_bitstream_id, openfpga_bitstream_cmd_class);
-  shell.set_command_execute_function(shell_cmd_fabric_bitstream_id, build_fabric_bitstream);
-
-  /* The 'fabric_bitstream' command should NOT be executed before 'fpga_bitstream' */
+  /* The 'build_fabric_bitstream' command should NOT be executed before 'build_architecture_bitstream' */
   std::vector<ShellCommandId> cmd_dependency_fabric_bitstream;
-  cmd_dependency_fabric_bitstream.push_back(shell_cmd_fpga_bitstream_id);
-  shell.set_command_dependency(shell_cmd_fabric_bitstream_id, cmd_dependency_fabric_bitstream);
+  cmd_dependency_fabric_bitstream.push_back(shell_cmd_arch_bitstream_id);
+  add_openfpga_fabric_bitstream_command(shell, openfpga_bitstream_cmd_class, cmd_dependency_fabric_bitstream);
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_sdc_command.cpp b/openfpga/src/base/openfpga_sdc_command.cpp
index cf31d73b0..799fad4e6 100644
--- a/openfpga/src/base/openfpga_sdc_command.cpp
+++ b/openfpga/src/base/openfpga_sdc_command.cpp
@@ -16,9 +16,9 @@ namespace openfpga {
  * - Add command dependency
  *******************************************************************/
 static 
-void add_openfpga_write_pnr_sdc_command(openfpga::Shell<OpenfpgaContext>& shell,
-                                        const ShellCommandClassId& cmd_class_id,
-                                        const ShellCommandId& shell_cmd_build_fabric_id) {
+ShellCommandId add_openfpga_write_pnr_sdc_command(openfpga::Shell<OpenfpgaContext>& shell,
+                                                  const ShellCommandClassId& cmd_class_id,
+                                                  const std::vector<ShellCommandId>& dependent_cmds) {
   Command shell_cmd("write_pnr_sdc");
 
   /* Add an option '--file' in short '-f'*/
@@ -55,25 +55,28 @@ void add_openfpga_write_pnr_sdc_command(openfpga::Shell<OpenfpgaContext>& shell,
   shell.set_command_class(shell_cmd_id, cmd_class_id);
   shell.set_command_execute_function(shell_cmd_id, write_pnr_sdc);
 
-  /* The 'build_fabric' command should NOT be executed before 'link_openfpga_arch' */
-  std::vector<ShellCommandId> cmd_dependency;
-  cmd_dependency.push_back(shell_cmd_build_fabric_id);
-  shell.set_command_dependency(shell_cmd_id, cmd_dependency);
+  /* Add command dependency to the Shell */
+  shell.set_command_dependency(shell_cmd_id, dependent_cmds);
+
+  return shell_cmd_id;
 }
 
 void add_openfpga_sdc_commands(openfpga::Shell<OpenfpgaContext>& shell) {
   /* Get the unique id of 'build_fabric' command which is to be used in creating the dependency graph */
-  const ShellCommandId& shell_cmd_build_fabric_id = shell.command(std::string("build_fabric"));
+  const ShellCommandId& build_fabric_id = shell.command(std::string("build_fabric"));
 
   /* Add a new class of commands */
   ShellCommandClassId openfpga_sdc_cmd_class = shell.add_command_class("FPGA-SDC");
 
   /******************************** 
-   * Command 'write_fabric_verilog' 
+   * Command 'write_pnr_sdc' 
    */
+  /* The 'write_pnr_sdc' command should NOT be executed before 'build_fabric' */
+  std::vector<ShellCommandId> pnr_sdc_cmd_dependency;
+  pnr_sdc_cmd_dependency.push_back(build_fabric_id);
   add_openfpga_write_pnr_sdc_command(shell,
                                      openfpga_sdc_cmd_class,
-                                     shell_cmd_build_fabric_id);
+                                     pnr_sdc_cmd_dependency);
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_setup_command.cpp b/openfpga/src/base/openfpga_setup_command.cpp
index e3354d046..0d7393c26 100644
--- a/openfpga/src/base/openfpga_setup_command.cpp
+++ b/openfpga/src/base/openfpga_setup_command.cpp
@@ -57,7 +57,7 @@ ShellCommandId add_openfpga_write_arch_command(openfpga::Shell<OpenfpgaContext>&
   shell.set_command_class(shell_cmd_id, cmd_class_id);
   shell.set_command_const_execute_function(shell_cmd_id, write_arch);
 
-  /* The 'write_openfpga_arch' command should NOT be executed before 'read_openfpga_arch' */
+  /* Add command dependency to the Shell */
   shell.set_command_dependency(shell_cmd_id, dependent_cmds);
 
   return shell_cmd_id;
@@ -86,7 +86,7 @@ ShellCommandId add_openfpga_link_arch_command(openfpga::Shell<OpenfpgaContext>&
   shell.set_command_class(shell_cmd_id, cmd_class_id);
   shell.set_command_execute_function(shell_cmd_id, link_arch);
 
-  /* The 'link_openfpga_arch' command should NOT be executed before 'read_openfpga_arch' and 'vpr' */
+  /* Add command dependency to the Shell */
   shell.set_command_dependency(shell_cmd_id, dependent_cmds);
 
   return shell_cmd_id;
@@ -116,7 +116,7 @@ ShellCommandId add_openfpga_check_netlist_naming_conflict_command(openfpga::Shel
   shell.set_command_class(shell_cmd_id, cmd_class_id);
   shell.set_command_execute_function(shell_cmd_id, check_netlist_naming_conflict);
 
-  /* The 'link_openfpga_arch' command should NOT be executed before 'vpr' */
+  /* Add command dependency to the Shell */
   shell.set_command_dependency(shell_cmd_id, dependent_cmds);
 
   return shell_cmd_id;
@@ -133,6 +133,7 @@ ShellCommandId add_openfpga_pb_pin_fixup_command(openfpga::Shell<OpenfpgaContext
                                                  const std::vector<ShellCommandId>& dependent_cmds) {
 
   Command shell_cmd("pb_pin_fixup");
+
   /* Add an option '--verbose' */
   shell_cmd.add_option("verbose", false, "Show verbose outputs");
 
@@ -141,7 +142,7 @@ ShellCommandId add_openfpga_pb_pin_fixup_command(openfpga::Shell<OpenfpgaContext
   shell.set_command_class(shell_cmd_id, cmd_class_id);
   shell.set_command_execute_function(shell_cmd_id, pb_pin_fixup);
 
-  /* The 'pb_pin_fixup' command should NOT be executed before 'read_openfpga_arch' and 'vpr' */
+  /* Add command dependency to the Shell */
   shell.set_command_dependency(shell_cmd_id, dependent_cmds);
 
   return shell_cmd_id;
@@ -166,7 +167,7 @@ ShellCommandId add_openfpga_lut_truth_table_fixup_command(openfpga::Shell<Openfp
   shell.set_command_class(shell_cmd_id, cmd_class_id);
   shell.set_command_execute_function(shell_cmd_id, lut_truth_table_fixup);
 
-  /* The 'lut_truth_table_fixup' command should NOT be executed before 'read_openfpga_arch' and 'vpr' */
+  /* Add command dependency to the Shell */
   shell.set_command_dependency(shell_cmd_id, dependent_cmds);
 
   return shell_cmd_id;
@@ -198,7 +199,7 @@ ShellCommandId add_openfpga_build_fabric_command(openfpga::Shell<OpenfpgaContext
   shell.set_command_class(shell_cmd_id, cmd_class_id);
   shell.set_command_execute_function(shell_cmd_id, build_fabric);
 
-  /* The 'build_fabric' command should NOT be executed before 'link_openfpga_arch' */
+  /* Add command dependency to the Shell */
   shell.set_command_dependency(shell_cmd_id, dependent_cmds);
 
   return shell_cmd_id;
@@ -220,6 +221,7 @@ void add_openfpga_setup_commands(openfpga::Shell<OpenfpgaContext>& shell) {
   /******************************** 
    * Command 'write_openfpga_arch' 
    */
+  /* The 'write_openfpga_arch' command should NOT be executed before 'read_openfpga_arch' */
   std::vector<ShellCommandId> write_arch_dependent_cmds(1, read_arch_cmd_id);
   add_openfpga_write_arch_command(shell,
                                   openfpga_setup_cmd_class,
@@ -228,6 +230,7 @@ void add_openfpga_setup_commands(openfpga::Shell<OpenfpgaContext>& shell) {
   /******************************** 
    * Command 'link_openfpga_arch' 
    */
+  /* The 'link_openfpga_arch' command should NOT be executed before 'vpr' */
   std::vector<ShellCommandId> link_arch_dependent_cmds;
   link_arch_dependent_cmds.push_back(read_arch_cmd_id);
   link_arch_dependent_cmds.push_back(vpr_cmd_id);
@@ -237,6 +240,7 @@ void add_openfpga_setup_commands(openfpga::Shell<OpenfpgaContext>& shell) {
   /******************************************* 
    * Command 'check_netlist_naming_conflict'
    */ 
+  /* The 'check_netlist_naming_conflict' command should NOT be executed before 'vpr' */
   std::vector<ShellCommandId> nlist_naming_dependent_cmds;
   nlist_naming_dependent_cmds.push_back(vpr_cmd_id);
   add_openfpga_check_netlist_naming_conflict_command(shell,
@@ -246,6 +250,7 @@ void add_openfpga_setup_commands(openfpga::Shell<OpenfpgaContext>& shell) {
   /******************************** 
    * Command 'pb_pin_fixup' 
    */
+  /* The 'pb_pin_fixup' command should NOT be executed before 'read_openfpga_arch' and 'vpr' */
   std::vector<ShellCommandId> pb_pin_fixup_dependent_cmds;
   pb_pin_fixup_dependent_cmds.push_back(read_arch_cmd_id);
   pb_pin_fixup_dependent_cmds.push_back(vpr_cmd_id);
@@ -256,6 +261,7 @@ void add_openfpga_setup_commands(openfpga::Shell<OpenfpgaContext>& shell) {
   /******************************** 
    * Command 'lut_truth_table_fixup' 
    */
+  /* The 'lut_truth_table_fixup' command should NOT be executed before 'read_openfpga_arch' and 'vpr' */
   std::vector<ShellCommandId> lut_tt_fixup_dependent_cmds;
   lut_tt_fixup_dependent_cmds.push_back(read_arch_cmd_id);
   lut_tt_fixup_dependent_cmds.push_back(vpr_cmd_id);
@@ -265,6 +271,7 @@ void add_openfpga_setup_commands(openfpga::Shell<OpenfpgaContext>& shell) {
   /******************************** 
    * Command 'build_fabric' 
    */
+  /* The 'build_fabric' command should NOT be executed before 'link_openfpga_arch' */
   std::vector<ShellCommandId> build_fabric_dependent_cmds;
   build_fabric_dependent_cmds.push_back(link_arch_cmd_id);
   add_openfpga_build_fabric_command(shell,
diff --git a/openfpga/src/base/openfpga_verilog_command.cpp b/openfpga/src/base/openfpga_verilog_command.cpp
index 3d4f7784b..71fad80f0 100644
--- a/openfpga/src/base/openfpga_verilog_command.cpp
+++ b/openfpga/src/base/openfpga_verilog_command.cpp
@@ -17,9 +17,9 @@ namespace openfpga {
  * - Add command dependency
  *******************************************************************/
 static 
-void add_openfpga_write_fabric_verilog_command(openfpga::Shell<OpenfpgaContext>& shell,
-                                               const ShellCommandClassId& cmd_class_id,
-                                               const ShellCommandId& shell_cmd_build_fabric_id) {
+ShellCommandId add_openfpga_write_fabric_verilog_command(openfpga::Shell<OpenfpgaContext>& shell,
+                                                         const ShellCommandClassId& cmd_class_id,
+                                                         const std::vector<ShellCommandId>& dependent_cmds) {
   Command shell_cmd("write_fabric_verilog");
 
   /* Add an option '--file' in short '-f'*/
@@ -50,10 +50,10 @@ void add_openfpga_write_fabric_verilog_command(openfpga::Shell<OpenfpgaContext>&
   shell.set_command_class(shell_cmd_id, cmd_class_id);
   shell.set_command_execute_function(shell_cmd_id, write_fabric_verilog);
 
-  /* The 'build_fabric' command should NOT be executed before 'link_openfpga_arch' */
-  std::vector<ShellCommandId> cmd_dependency;
-  cmd_dependency.push_back(shell_cmd_build_fabric_id);
-  shell.set_command_dependency(shell_cmd_id, cmd_dependency);
+  /* Add command dependency to the Shell */
+  shell.set_command_dependency(shell_cmd_id, dependent_cmds);
+
+  return shell_cmd_id;
 }
 
 /********************************************************************
@@ -62,9 +62,9 @@ void add_openfpga_write_fabric_verilog_command(openfpga::Shell<OpenfpgaContext>&
  * - Add command dependency
  *******************************************************************/
 static 
-void add_openfpga_write_verilog_testbench_command(openfpga::Shell<OpenfpgaContext>& shell,
-                                                  const ShellCommandClassId& cmd_class_id,
-                                                  const ShellCommandId& shell_cmd_build_fabric_id) {
+ShellCommandId add_openfpga_write_verilog_testbench_command(openfpga::Shell<OpenfpgaContext>& shell,
+                                                            const ShellCommandClassId& cmd_class_id,
+                                                            const std::vector<ShellCommandId>& dependent_cmds) {
   Command shell_cmd("write_verilog_testbench");
 
   /* Add an option '--file' in short '-f'*/
@@ -97,15 +97,15 @@ void add_openfpga_write_verilog_testbench_command(openfpga::Shell<OpenfpgaContex
   shell.set_command_class(shell_cmd_id, cmd_class_id);
   shell.set_command_execute_function(shell_cmd_id, write_verilog_testbench);
 
-  /* The command should NOT be executed before 'build_fabric' */
-  std::vector<ShellCommandId> cmd_dependency;
-  cmd_dependency.push_back(shell_cmd_build_fabric_id);
-  shell.set_command_dependency(shell_cmd_id, cmd_dependency);
+  /* Add command dependency to the Shell */
+  shell.set_command_dependency(shell_cmd_id, dependent_cmds);
+
+  return shell_cmd_id;
 }
 
 void add_openfpga_verilog_commands(openfpga::Shell<OpenfpgaContext>& shell) {
   /* Get the unique id of 'build_fabric' command which is to be used in creating the dependency graph */
-  const ShellCommandId& shell_cmd_build_fabric_id = shell.command(std::string("build_fabric"));
+  const ShellCommandId& build_fabric_cmd_id = shell.command(std::string("build_fabric"));
 
   /* Add a new class of commands */
   ShellCommandClassId openfpga_verilog_cmd_class = shell.add_command_class("FPGA-Verilog");
@@ -113,16 +113,22 @@ void add_openfpga_verilog_commands(openfpga::Shell<OpenfpgaContext>& shell) {
   /******************************** 
    * Command 'write_fabric_verilog' 
    */
+  /* The 'write_fabric_verilog' command should NOT be executed before 'build_fabric' */
+  std::vector<ShellCommandId> fabric_verilog_dependent_cmds;
+  fabric_verilog_dependent_cmds.push_back(build_fabric_cmd_id);
   add_openfpga_write_fabric_verilog_command(shell,
                                             openfpga_verilog_cmd_class,
-                                            shell_cmd_build_fabric_id);
+                                            fabric_verilog_dependent_cmds);
 
   /******************************** 
    * Command 'write_verilog_testbench' 
    */
+  /* The command 'write_verilog_testbench' should NOT be executed before 'build_fabric' */
+  std::vector<ShellCommandId> verilog_testbench_dependent_cmds;
+  verilog_testbench_dependent_cmds.push_back(build_fabric_cmd_id);
   add_openfpga_write_verilog_testbench_command(shell,
                                                openfpga_verilog_cmd_class,
-                                               shell_cmd_build_fabric_id);
+                                               verilog_testbench_dependent_cmds);
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/test_script/and_k6_frac.openfpga b/openfpga/test_script/and_k6_frac.openfpga
index 8a16f8cb5..1018887f1 100644
--- a/openfpga/test_script/and_k6_frac.openfpga
+++ b/openfpga/test_script/and_k6_frac.openfpga
@@ -31,7 +31,10 @@ repack #--verbose
 
 # Build the bitstream 
 #  - Output the fabric-independent bitstream to a file
-fpga_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
+build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
 
 # Write the Verilog netlist for FPGA fabric
 #  - Enable the use of explicit port mapping in Verilog netlist

From 543cff58b9ecd6cbaded489988387e3e9f2fd3a5 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 2 Mar 2020 13:44:08 -0700
Subject: [PATCH 242/645] start porting analysis SDC writer

---
 .../fpga_sdc/analysis_sdc_writer_utils.cpp    | 236 ++++++++++++++++++
 .../src/fpga_sdc/analysis_sdc_writer_utils.h  |  57 +++++
 2 files changed, 293 insertions(+)
 create mode 100644 openfpga/src/fpga_sdc/analysis_sdc_writer_utils.cpp
 create mode 100644 openfpga/src/fpga_sdc/analysis_sdc_writer_utils.h

diff --git a/openfpga/src/fpga_sdc/analysis_sdc_writer_utils.cpp b/openfpga/src/fpga_sdc/analysis_sdc_writer_utils.cpp
new file mode 100644
index 000000000..511271915
--- /dev/null
+++ b/openfpga/src/fpga_sdc/analysis_sdc_writer_utils.cpp
@@ -0,0 +1,236 @@
+/********************************************************************
+ * This file includes most utilized functions 
+ * that are used to output a SDC file
+ * in order to constrain a FPGA fabric (P&Red netlist) mapped to a benchmark 
+ *******************************************************************/
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_digest.h"
+
+#include "sdc_writer_utils.h"
+#include "analysis_sdc_writer_utils.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Identify if a node should be disabled during analysis SDC generation
+ *******************************************************************/
+bool is_rr_node_to_be_disable_for_analysis(const VprRoutingAnnotation& routing_annotation,
+                                           const RRNodeId& cur_rr_node) {
+  /* Conditions to enable timing analysis for a node 
+   * 1st condition: it have a valid net_number 
+   * TODO: 2nd condition: it is not an parasitic net 
+   */
+  return ClusterNetId::INVALID() == routing_annotation.rr_node_net(cur_rr_node);
+}
+
+/********************************************************************
+ * Disable all the unused inputs of routing multiplexers, which are not used by benchmark 
+ * Here, we start from each input of a routing module, and traverse forward to the sink 
+ * port of the module net whose source is the input
+ * We will find the instance name which is the parent of the sink port, and search the 
+ * net id through the instance_name_to_net_map 
+ * The the net id does not match the net id of this input, we will disable the sink port!
+ *
+ *                   parent_module
+ *                 +-----------------------
+ *                 |           MUX instance A
+ *                 |          +-----------
+ *   input_port--->|--+---x-->| sink port (disable! net_id = Y) 
+ *   (net_id = X)  |  |       +----------
+ *                 |  |        MUX instance B
+ *                 |  |       +----------
+ *                 |  +------>| sink port (do not disable! net_id = X)
+ *
+ *******************************************************************/
+void disable_analysis_module_input_pin_net_sinks(std::fstream& fp,
+                                                 const ModuleManager& module_manager,
+                                                 const ModuleId& parent_module,
+                                                 const std::string& parent_instance_name,
+                                                 const ModulePortId& module_input_port,
+                                                 const size_t& module_input_pin,
+                                                 const VprRoutingAnnotation& routing_annotation,
+                                                 const RRNodeId& input_rr_node,
+                                                 const std::map<std::string, ClusterNetId> mux_instance_to_net_map) {
+  /* Validate file stream */
+  valid_file_stream(fp);
+
+  /* Find the module net which sources from this port! */
+  ModuleNetId module_net = module_manager.module_instance_port_net(parent_module, parent_module, 0, module_input_port, module_input_pin); 
+  VTR_ASSERT(true == module_manager.valid_module_net_id(parent_module, module_net));
+
+  /* Touch each sink of the net! */
+  for (const ModuleNetSinkId& sink_id : module_manager.module_net_sinks(parent_module, module_net)) {
+    ModuleId sink_module = module_manager.net_sink_modules(parent_module, module_net)[sink_id]; 
+    size_t sink_instance = module_manager.net_sink_instances(parent_module, module_net)[sink_id]; 
+
+    /* Skip when sink module is the parent module, 
+     * the output ports of parent modules have been disabled/enabled already! 
+     */
+    if (sink_module == parent_module) {
+      continue;
+    }
+
+    std::string sink_instance_name = module_manager.instance_name(parent_module, sink_module, sink_instance);
+    bool disable_timing = false;
+    /* Check if this node is used by benchmark  */
+    if (true == is_rr_node_to_be_disable_for_analysis(routing_annotation, input_rr_node)) {
+      /* Disable all the sinks! */
+      disable_timing = true;
+    } else {
+      std::map<std::string, ClusterNetId>::const_iterator it = mux_instance_to_net_map.find(sink_instance_name);
+      if (it != mux_instance_to_net_map.end()) {
+        /* See if the net id matches. If does not match, we should disable! */
+        if (routing_annotation.rr_node_net(input_rr_node) != mux_instance_to_net_map.at(sink_instance_name)) {
+          disable_timing = true;
+        }
+      }
+    }
+
+    /* Time to write SDC command to disable timing or not */
+    if (false == disable_timing) {
+      continue;
+    }
+
+    BasicPort sink_port = module_manager.module_port(sink_module, module_manager.net_sink_ports(parent_module, module_net)[sink_id]);
+    sink_port.set_width(module_manager.net_sink_pins(parent_module, module_net)[sink_id],
+                        module_manager.net_sink_pins(parent_module, module_net)[sink_id]);
+    /* Get the input id that is used! Disable the unused inputs! */
+    fp << "set_disable_timing ";
+    fp << parent_instance_name << "/";
+    fp << sink_instance_name << "/";
+    fp << generate_sdc_port(sink_port);
+    fp << std::endl;
+  }
+}
+
+/********************************************************************
+ * Disable all the unused inputs of routing multiplexers, which are not used by benchmark 
+ * Here, we start from each input of a routing module, and traverse forward to the sink 
+ * port of the module net whose source is the input
+ * We will find the instance name which is the parent of the sink port, and search the 
+ * net id through the instance_name_to_net_map 
+ * The the net id does not match the net id of this input, we will disable the sink port!
+ *
+ *                   parent_module
+ *                 +-----------------------
+ *                 |           MUX instance A
+ *                 |          +-----------
+ *   input_port--->|--+---x-->| sink port (disable! net_id = Y) 
+ *   (net_id = X)  |  |       +----------
+ *                 |  |        MUX instance B
+ *                 |  |       +----------
+ *                 |  +------>| sink port (do not disable! net_id = X)
+ *
+ *******************************************************************/
+void disable_analysis_module_input_port_net_sinks(std::fstream& fp,
+                                                  const ModuleManager& module_manager,
+                                                  const ModuleId& parent_module,
+                                                  const std::string& parent_instance_name,
+                                                  const ModulePortId& module_input_port,
+                                                  const VprRoutingAnnotation& routing_annotation,
+                                                  const RRNodeId& input_rr_node,
+                                                  const std::map<std::string, ClusterNetId> mux_instance_to_net_map) {
+  /* Validate file stream */
+  valid_file_stream(fp);
+
+  /* Find the module net which sources from this port! */
+  for (const size_t& pin : module_manager.module_port(parent_module, module_input_port).pins()) {
+    disable_analysis_module_input_pin_net_sinks(fp, module_manager, parent_module,
+                                                parent_instance_name,
+                                                module_input_port, pin,
+                                                routing_annotation, input_rr_node,
+                                                mux_instance_to_net_map);
+  }
+}
+
+/********************************************************************
+ * Disable all the unused inputs of routing multiplexers, which are not used by benchmark 
+ * Here, we start from each output of a child module, and traverse forward to the sink 
+ * port of the module net whose source is the input
+ * We will find the instance name which is the parent of the sink port, and search the 
+ * net id through the instance_name_to_net_map 
+ * The the net id does not match the net id of this input, we will disable the sink port!
+ *
+ *                         Parent_module
+ *                         +---------------------------------------------
+ *                         |
+ *                         |    +--------------------------------------------+
+ *                         |    |     MUX                  child_module      |
+ *                         |    |    +-------------+       +-----------+     |
+ *                         |    +--->| Routing     |------>|           |     |
+ *    input_pin0(netA) --->|----x--->| Multiplexer | netA  | output_pin|-----+
+ *                         |         +-------------+       |           | netA
+ *                         |                               |           |
+ *
+
+ *
+ *******************************************************************/
+void disable_analysis_module_output_pin_net_sinks(std::fstream& fp,
+                                                  const ModuleManager& module_manager,
+                                                  const ModuleId& parent_module,
+                                                  const std::string& parent_instance_name,
+                                                  const ModuleId& child_module,
+                                                  const size_t& child_instance,
+                                                  const ModulePortId& child_module_port,
+                                                  const size_t& child_module_pin,
+                                                  const VprRoutingAnnotation& routing_annotation,
+                                                  const RRNodeId& output_rr_node,
+                                                  const std::map<std::string, ClusterNetId> mux_instance_to_net_map) {
+  /* Validate file stream */
+  valid_file_stream(fp);
+
+  /* Find the module net which sources from this port! */
+  ModuleNetId module_net = module_manager.module_instance_port_net(parent_module, child_module, child_instance, child_module_port, child_module_pin); 
+  VTR_ASSERT(true == module_manager.valid_module_net_id(parent_module, module_net));
+
+  /* Touch each sink of the net! */
+  for (const ModuleNetSinkId& sink_id : module_manager.module_net_sinks(parent_module, module_net)) {
+    ModuleId sink_module = module_manager.net_sink_modules(parent_module, module_net)[sink_id]; 
+    size_t sink_instance = module_manager.net_sink_instances(parent_module, module_net)[sink_id]; 
+
+    /* Skip when sink module is the parent module, 
+     * the output ports of parent modules have been disabled/enabled already! 
+     */
+    if (sink_module == parent_module) {
+      continue;
+    }
+
+    std::string sink_instance_name = module_manager.instance_name(parent_module, sink_module, sink_instance);
+    bool disable_timing = false;
+    /* Check if this node is used by benchmark  */
+    if (true == is_rr_node_to_be_disable_for_analysis(routing_annotation, output_rr_node)) {
+      /* Disable all the sinks! */
+      disable_timing = true;
+    } else {
+      std::map<std::string, ClusterNetId>::const_iterator it = mux_instance_to_net_map.find(sink_instance_name);
+      if (it != mux_instance_to_net_map.end()) {
+        /* See if the net id matches. If does not match, we should disable! */
+        if (routing_annotation.rr_node_net(output_rr_node) != mux_instance_to_net_map.at(sink_instance_name)) {
+          disable_timing = true;
+        }
+      }
+    }
+
+    /* Time to write SDC command to disable timing or not */
+    if (false == disable_timing) {
+      continue;
+    }
+
+    BasicPort sink_port = module_manager.module_port(sink_module, module_manager.net_sink_ports(parent_module, module_net)[sink_id]);
+    sink_port.set_width(module_manager.net_sink_pins(parent_module, module_net)[sink_id],
+                        module_manager.net_sink_pins(parent_module, module_net)[sink_id]);
+    /* Get the input id that is used! Disable the unused inputs! */
+    fp << "set_disable_timing ";
+    fp << parent_instance_name << "/";
+    fp << sink_instance_name << "/";
+    fp << generate_sdc_port(sink_port);
+    fp << std::endl;
+  }
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_sdc/analysis_sdc_writer_utils.h b/openfpga/src/fpga_sdc/analysis_sdc_writer_utils.h
new file mode 100644
index 000000000..12b0dc362
--- /dev/null
+++ b/openfpga/src/fpga_sdc/analysis_sdc_writer_utils.h
@@ -0,0 +1,57 @@
+#ifndef ANALYSIS_SDC_WRITER_UTILS_H
+#define ANALYSIS_SDC_WRITER_UTILS_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <fstream>
+#include <string>
+#include <map>
+#include "module_manager.h"
+#include "rr_graph_obj.h"
+#include "vpr_routing_annotation.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+bool is_rr_node_to_be_disable_for_analysis(const VprRoutingAnnotation& routing_annotation,
+                                           const RRNodeId& cur_rr_node);
+
+void disable_analysis_module_input_pin_net_sinks(std::fstream& fp,
+                                                 const ModuleManager& module_manager,
+                                                 const ModuleId& parent_module,
+                                                 const std::string& parent_instance_name,
+                                                 const ModulePortId& module_input_port,
+                                                 const size_t& module_input_pin,
+                                                 const VprRoutingAnnotation& routing_annotation,
+                                                 const RRNodeId& input_rr_node,
+                                                 const std::map<std::string, ClusterNetId> mux_instance_to_net_map);
+
+void disable_analysis_module_input_port_net_sinks(std::fstream& fp,
+                                                  const ModuleManager& module_manager,
+                                                  const ModuleId& parent_module,
+                                                  const std::string& parent_instance_name,
+                                                  const ModulePortId& module_input_port,
+                                                  const VprRoutingAnnotation& routing_annotation,
+                                                  const RRNodeId& input_rr_node,
+                                                  const std::map<std::string, ClusterNetId> mux_instance_to_net_map);
+
+void disable_analysis_module_output_pin_net_sinks(std::fstream& fp,
+                                                  const ModuleManager& module_manager,
+                                                  const ModuleId& parent_module,
+                                                  const std::string& parent_instance_name,
+                                                  const ModuleId& child_module,
+                                                  const size_t& child_instance,
+                                                  const ModulePortId& child_module_port,
+                                                  const size_t& child_module_pin,
+                                                  const VprRoutingAnnotation& routing_annotation,
+                                                  const RRNodeId& output_rr_node,
+                                                  const std::map<std::string, ClusterNetId> mux_instance_to_net_map);
+
+} /* end namespace openfpga */
+
+#endif

From 647418353924aa22348c747df4a898288db01667 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 2 Mar 2020 14:29:58 -0700
Subject: [PATCH 243/645] adapt analysis SDC writer for routing modules

---
 .../fpga_sdc/analysis_sdc_routing_writer.cpp  | 528 ++++++++++++++++++
 .../fpga_sdc/analysis_sdc_routing_writer.h    |  35 ++
 2 files changed, 563 insertions(+)
 create mode 100644 openfpga/src/fpga_sdc/analysis_sdc_routing_writer.cpp
 create mode 100644 openfpga/src/fpga_sdc/analysis_sdc_routing_writer.h

diff --git a/openfpga/src/fpga_sdc/analysis_sdc_routing_writer.cpp b/openfpga/src/fpga_sdc/analysis_sdc_routing_writer.cpp
new file mode 100644
index 000000000..f9384af04
--- /dev/null
+++ b/openfpga/src/fpga_sdc/analysis_sdc_routing_writer.cpp
@@ -0,0 +1,528 @@
+/********************************************************************
+ * This file includes functions that are used to output a SDC file
+ * that constrain routing modules of a FPGA fabric (P&Red netlist) 
+ * using a benchmark 
+ *******************************************************************/
+#include <map>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_digest.h"
+#include "openfpga_side_manager.h"
+#include "openfpga_port.h"
+
+#include "openfpga_reserved_words.h"
+#include "openfpga_naming.h"
+
+#include "sdc_writer_utils.h"
+#include "analysis_sdc_writer_utils.h"
+#include "analysis_sdc_routing_writer.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * This function will disable 
+ * 1. all the unused port (unmapped by a benchmark) of a connection block
+ * 2. all the unused inputs (unmapped by a benchmark) of routing multiplexers 
+ *    in a connection block
+ *******************************************************************/
+static 
+void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp, 
+                                                    const ModuleManager& module_manager, 
+                                                    const RRGraph& rr_graph, 
+                                                    const VprRoutingAnnotation& routing_annotation, 
+                                                    const DeviceRRGSB& device_rr_gsb,
+                                                    const RRGSB& rr_gsb, 
+                                                    const t_rr_type& cb_type,
+                                                    const bool& compact_routing_hierarchy) {
+  /* Validate file stream */
+  valid_file_stream(fp);
+
+  vtr::Point<size_t> gsb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type));
+
+  std::string cb_instance_name = generate_connection_block_module_name(cb_type, gsb_coordinate);
+
+  /* If we use the compact routing hierarchy, we need to find the module name !*/
+  vtr::Point<size_t> cb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type));
+  if (true == compact_routing_hierarchy) {
+    vtr::Point<size_t> cb_coord(rr_gsb.get_x(), rr_gsb.get_y());
+    /* Note: use GSB coordinate when inquire for unique modules!!! */
+    const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(cb_type, cb_coord);
+    cb_coordinate.set_x(unique_mirror.get_cb_x(cb_type)); 
+    cb_coordinate.set_y(unique_mirror.get_cb_y(cb_type)); 
+  }
+
+  std::string cb_module_name = generate_connection_block_module_name(cb_type, cb_coordinate);
+
+  ModuleId cb_module = module_manager.find_module(cb_module_name);
+  VTR_ASSERT(true == module_manager.valid_module_id(cb_module));
+
+  /* Print comments */
+  fp << "##################################################" << std::endl; 
+  fp << "# Disable timing for Connection block " << cb_module_name << std::endl;
+  fp << "##################################################" << std::endl; 
+
+  /* Disable all the input port (routing tracks), which are not used by benchmark */
+  for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) {
+    const RRNodeId& chan_node = rr_gsb.get_chan_node(rr_gsb.get_cb_chan_side(cb_type), itrack);
+    /* Check if this node is used by benchmark  */
+    if (false == is_rr_node_to_be_disable_for_analysis(routing_annotation, chan_node)) {
+      continue;
+    }
+
+    /* Disable both input of the routing track if it is not used! */
+    std::string port_name = generate_cb_module_track_port_name(cb_type,
+                                                               itrack,  
+                                                               IN_PORT);
+
+    /* Ensure we have this port in the module! */
+    ModulePortId module_port = module_manager.find_module_port(cb_module, port_name);
+    VTR_ASSERT(true == module_manager.valid_module_port_id(cb_module, module_port));
+
+    fp << "set_disable_timing ";
+    fp << cb_instance_name << "/";
+    fp << generate_sdc_port(module_manager.module_port(cb_module, module_port));
+    fp << std::endl;
+  }
+
+  /* Disable all the output port (routing tracks), which are not used by benchmark */
+  for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) {
+    const RRNodeId& chan_node = rr_gsb.get_chan_node(rr_gsb.get_cb_chan_side(cb_type), itrack);
+    /* Check if this node is used by benchmark  */
+    if (false == is_rr_node_to_be_disable_for_analysis(routing_annotation, chan_node)) {
+      continue;
+    }
+
+    /* Disable both input of the routing track if it is not used! */
+    std::string port_name = generate_cb_module_track_port_name(cb_type,
+                                                               itrack,  
+                                                               OUT_PORT);
+
+    /* Ensure we have this port in the module! */
+    ModulePortId module_port = module_manager.find_module_port(cb_module, port_name);
+    VTR_ASSERT(true == module_manager.valid_module_port_id(cb_module, module_port));
+
+    fp << "set_disable_timing ";
+    fp << cb_instance_name << "/";
+    fp << generate_sdc_port(module_manager.module_port(cb_module, module_port));
+    fp << std::endl;
+  }
+
+  /* Build a map between mux_instance name and net_num */
+  std::map<std::string, ClusterNetId> mux_instance_to_net_map;
+
+  /* Disable all the output port (grid input pins), which are not used by benchmark */
+  std::vector<enum e_side> cb_sides = rr_gsb.get_cb_ipin_sides(cb_type);
+
+  for (size_t side = 0; side < cb_sides.size(); ++side) {
+    enum e_side cb_ipin_side = cb_sides[side];
+    for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) {
+      RRNodeId ipin_node = rr_gsb.get_ipin_node(cb_ipin_side, inode);
+
+      /* Find the MUX instance that drives the IPIN! */
+      std::string mux_instance_name = generate_cb_mux_instance_name(CONNECTION_BLOCK_MUX_INSTANCE_PREFIX, rr_graph.node_side(ipin_node), inode, std::string(""));
+      mux_instance_to_net_map[mux_instance_name] = routing_annotation.rr_node_net(ipin_node);  
+
+      if (false == is_rr_node_to_be_disable_for_analysis(routing_annotation, ipin_node)) {
+        continue;
+      }
+
+      if (0 == std::distance(rr_graph.node_configurable_in_edges(ipin_node).begin(), rr_graph.node_configurable_in_edges(ipin_node).end())) {
+        continue;
+      }
+
+      std::string port_name = generate_cb_module_grid_port_name(cb_ipin_side,
+                                                                rr_graph.node_pin_num(ipin_node)); 
+
+      /* Find the port in unique mirror! */
+      if (true == compact_routing_hierarchy) {
+        /* Note: use GSB coordinate when inquire for unique modules!!! */
+        vtr::Point<size_t> cb_coord(rr_gsb.get_x(), rr_gsb.get_y());
+        const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(cb_type, cb_coord);
+        const RRNodeId& unique_mirror_ipin_node = unique_mirror.get_ipin_node(cb_ipin_side, inode);
+        port_name = generate_cb_module_grid_port_name(cb_ipin_side, 
+                                                      rr_graph.node_pin_num(unique_mirror_ipin_node)); 
+      }
+
+      /* Ensure we have this port in the module! */
+      ModulePortId module_port = module_manager.find_module_port(cb_module, port_name);
+      VTR_ASSERT(true == module_manager.valid_module_port_id(cb_module, module_port));
+
+      fp << "set_disable_timing ";
+      fp << cb_instance_name << "/";
+      fp << generate_sdc_port(module_manager.module_port(cb_module, module_port));
+      fp << std::endl;
+    }
+  }
+
+  /* Disable all the unused inputs of routing multiplexers, which are not used by benchmark 
+   * Here, we start from each input of the Connection Blocks, and traverse forward to the sink 
+   * port of the module net whose source is the input
+   * We will find the instance name which is the parent of the sink port, and search the 
+   * net id through the instance_name_to_net_map 
+   * The the net id does not match the net id of this input, we will disable the sink port!
+   *
+   *                   cb_module
+   *                 +-----------------------
+   *                 |           MUX instance A
+   *                 |          +-----------
+   *   input_port--->|--+---x-->| sink port (disable!)
+   *                 |  |       +----------
+   *                 |  |        MUX instance B
+   *                 |  |       +----------
+   *                 |  +------>| sink port (do not disable!)
+   */ 
+  for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) {
+    const RRNodeId& chan_node = rr_gsb.get_chan_node(rr_gsb.get_cb_chan_side(cb_type), itrack);
+
+    /* Disable both input of the routing track if it is not used! */
+    std::string port_name = generate_cb_module_track_port_name(cb_type,
+                                                               itrack,  
+                                                               OUT_PORT);
+
+    /* Ensure we have this port in the module! */
+    ModulePortId module_port = module_manager.find_module_port(cb_module, port_name);
+    VTR_ASSERT(true == module_manager.valid_module_port_id(cb_module, module_port));
+
+    disable_analysis_module_input_port_net_sinks(fp, 
+                                                 module_manager, cb_module,
+                                                 cb_instance_name,
+                                                 module_port,
+                                                 routing_annotation,
+                                                 chan_node,
+                                                 mux_instance_to_net_map);
+  }
+}
+
+/********************************************************************
+ * Iterate over all the connection blocks in a device
+ * and disable unused ports for each of them 
+ *******************************************************************/
+static 
+void print_analysis_sdc_disable_unused_cb_ports(std::fstream& fp,
+                                                const ModuleManager& module_manager, 
+                                                const RRGraph& rr_graph, 
+                                                const VprRoutingAnnotation& routing_annotation, 
+                                                const DeviceRRGSB& device_rr_gsb,
+                                                const t_rr_type& cb_type,
+                                                const bool& compact_routing_hierarchy) {
+  /* Build unique X-direction connection block modules */
+  vtr::Point<size_t> cb_range = device_rr_gsb.get_gsb_range();
+
+  for (size_t ix = 0; ix < cb_range.x(); ++ix) {
+    for (size_t iy = 0; iy < cb_range.y(); ++iy) {
+      /* Check if the connection block exists in the device!
+       * Some of them do NOT exist due to heterogeneous blocks (height > 1) 
+       * We will skip those modules
+       */
+      const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
+      if (false == rr_gsb.is_cb_exist(cb_type)) {
+        continue;
+      }
+
+      print_analysis_sdc_disable_cb_unused_resources(fp, 
+                                                     module_manager, 
+                                                     rr_graph, 
+                                                     routing_annotation, 
+                                                     device_rr_gsb, 
+                                                     rr_gsb, 
+                                                     cb_type,
+                                                     compact_routing_hierarchy);
+    }
+  }
+}
+
+/********************************************************************
+ * Iterate over all the connection blocks in a device
+ * and disable unused ports for each of them 
+ *******************************************************************/
+void print_analysis_sdc_disable_unused_cbs(std::fstream& fp,
+                                           const ModuleManager& module_manager, 
+                                           const RRGraph& rr_graph, 
+                                           const VprRoutingAnnotation& routing_annotation, 
+                                           const DeviceRRGSB& device_rr_gsb,
+                                           const bool& compact_routing_hierarchy) {
+
+  print_analysis_sdc_disable_unused_cb_ports(fp, module_manager, 
+                                             rr_graph, 
+                                             routing_annotation,
+                                             device_rr_gsb,
+                                             CHANX, compact_routing_hierarchy);
+
+  print_analysis_sdc_disable_unused_cb_ports(fp, module_manager, 
+                                             rr_graph, 
+                                             routing_annotation,
+                                             device_rr_gsb,
+                                             CHANY, compact_routing_hierarchy);
+}
+
+/********************************************************************
+ * This function will disable 
+ * 1. all the unused port (unmapped by a benchmark) of a switch block
+ * 2. all the unused inputs (unmapped by a benchmark) of routing multiplexers 
+ *    in a switch block
+ *******************************************************************/
+static 
+void print_analysis_sdc_disable_sb_unused_resources(std::fstream& fp, 
+                                                    const ModuleManager& module_manager, 
+                                                    const RRGraph& rr_graph, 
+                                                    const VprRoutingAnnotation& routing_annotation, 
+                                                    const DeviceRRGSB& device_rr_gsb,
+                                                    const RRGSB& rr_gsb, 
+                                                    const bool& compact_routing_hierarchy) {
+  /* Validate file stream */
+  valid_file_stream(fp);
+
+  vtr::Point<size_t> gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
+
+  std::string sb_instance_name = generate_switch_block_module_name(gsb_coordinate);
+
+  /* If we use the compact routing hierarchy, we need to find the module name !*/
+  vtr::Point<size_t> sb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
+  if (true == compact_routing_hierarchy) {
+    vtr::Point<size_t> sb_coord(rr_gsb.get_x(), rr_gsb.get_y());
+    /* Note: use GSB coordinate when inquire for unique modules!!! */
+    const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(sb_coord);
+    sb_coordinate.set_x(unique_mirror.get_sb_x()); 
+    sb_coordinate.set_y(unique_mirror.get_sb_y()); 
+  }
+
+  std::string sb_module_name = generate_switch_block_module_name(sb_coordinate);
+
+  ModuleId sb_module = module_manager.find_module(sb_module_name);
+  VTR_ASSERT(true == module_manager.valid_module_id(sb_module));
+
+  /* Print comments */
+  fp << "##################################################" << std::endl; 
+  fp << "# Disable timing for Switch block " << sb_module_name << std::endl;
+  fp << "##################################################" << std::endl; 
+
+  /* Build a map between mux_instance name and net_num */
+  std::map<std::string, ClusterNetId> mux_instance_to_net_map;
+
+  /* Disable all the input/output port (routing tracks), which are not used by benchmark */
+  for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
+    SideManager side_manager(side);
+
+    for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) {
+      const RRNodeId& chan_node = rr_gsb.get_chan_node(side_manager.get_side(), itrack);
+
+      std::string port_name = generate_sb_module_track_port_name(rr_graph.node_type(rr_gsb.get_chan_node(side_manager.get_side(), itrack)),
+                                                                 side_manager.get_side(), itrack,  
+                                                                 rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack));
+
+      if (true == compact_routing_hierarchy) {
+        /* Note: use GSB coordinate when inquire for unique modules!!! */
+        vtr::Point<size_t> sb_coord(rr_gsb.get_x(), rr_gsb.get_y());
+        const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(sb_coord);
+        port_name = generate_sb_module_track_port_name(rr_graph.node_type(unique_mirror.get_chan_node(side_manager.get_side(), itrack)),
+                                                       side_manager.get_side(), itrack,  
+                                                       unique_mirror.get_chan_node_direction(side_manager.get_side(), itrack));
+      }
+
+      /* Ensure we have this port in the module! */
+      ModulePortId module_port = module_manager.find_module_port(sb_module, port_name);
+      VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module, module_port));
+
+      /* Cache the net name for routing tracks which are outputs of the switch block */
+      if (OUT_PORT == rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) {
+        /* Generate the name of mux instance related to this output node */
+        std::string mux_instance_name = generate_sb_memory_instance_name(SWITCH_BLOCK_MUX_INSTANCE_PREFIX, side_manager.get_side(), itrack, std::string(""));
+        mux_instance_to_net_map[mux_instance_name] = routing_annotation.rr_node_net(chan_node);
+      }
+
+      /* Check if this node is used by benchmark  */
+      if (false == is_rr_node_to_be_disable_for_analysis(routing_annotation, chan_node)) {
+        continue;
+      }
+
+      fp << "set_disable_timing ";
+      fp << sb_instance_name << "/";
+      fp << generate_sdc_port(module_manager.module_port(sb_module, module_port));
+      fp << std::endl;
+    }
+  }
+
+  /* Disable all the input port (grid output pins), which are not used by benchmark */
+  for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
+    SideManager side_manager(side);
+
+    for (size_t inode = 0; inode < rr_gsb.get_num_opin_nodes(side_manager.get_side()); ++inode) {
+      const RRNodeId& opin_node = rr_gsb.get_opin_node(side_manager.get_side(), inode);
+
+      std::string port_name = generate_sb_module_grid_port_name(side_manager.get_side(), 
+                                                                rr_graph.node_side(opin_node),
+                                                                rr_graph.node_pin_num(opin_node)); 
+
+      if (true == compact_routing_hierarchy) {
+        /* Note: use GSB coordinate when inquire for unique modules!!! */
+        vtr::Point<size_t> sb_coord(rr_gsb.get_x(), rr_gsb.get_y());
+        const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(sb_coord);
+        const RRNodeId& unique_mirror_opin_node = unique_mirror.get_opin_node(side_manager.get_side(), inode);
+
+        port_name = generate_sb_module_grid_port_name(side_manager.get_side(),
+                                                      rr_graph.node_side(unique_mirror_opin_node),
+                                                      rr_graph.node_pin_num(unique_mirror_opin_node)); 
+      }
+
+
+      /* Ensure we have this port in the module! */
+      ModulePortId module_port = module_manager.find_module_port(sb_module, port_name);
+      VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module, module_port));
+
+      /* Check if this node is used by benchmark  */
+      if (false == is_rr_node_to_be_disable_for_analysis(routing_annotation, opin_node)) {
+        continue;
+      }
+
+      fp << "set_disable_timing ";
+      fp << sb_instance_name << "/";
+      fp << generate_sdc_port(module_manager.module_port(sb_module, module_port));
+      fp << std::endl;
+    }
+  }
+
+  /* Disable all the unused inputs of routing multiplexers, which are not used by benchmark 
+   * Here, we start from each input of the Switch Blocks, and traverse forward to the sink 
+   * port of the module net whose source is the input
+   * We will find the instance name which is the parent of the sink port, and search the 
+   * net id through the instance_name_to_net_map 
+   * The the net id does not match the net id of this input, we will disable the sink port!
+   *
+   *                   sb_module
+   *                 +-----------------------
+   *                 |           MUX instance A
+   *                 |          +-----------
+   *   input_port--->|--+---x-->| sink port (disable! net_id = Y) 
+   *   (net_id = X)  |  |       +----------
+   *                 |  |        MUX instance B
+   *                 |  |       +----------
+   *                 |  +------>| sink port (do not disable! net_id = X)
+   *
+   * Because the input ports of a SB module come from 
+   * 1. Grid output pins
+   * 2. routing tracks
+   * We will walk through these ports and do conditionally disable_timing
+   */ 
+
+  /* Iterate over input ports coming from grid output pins */
+  for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
+    SideManager side_manager(side);
+
+    for (size_t inode = 0; inode < rr_gsb.get_num_opin_nodes(side_manager.get_side()); ++inode) {
+      const RRNodeId& opin_node = rr_gsb.get_opin_node(side_manager.get_side(), inode);
+
+      std::string port_name = generate_sb_module_grid_port_name(side_manager.get_side(),
+                                                                rr_graph.node_side(opin_node),
+                                                                rr_graph.node_pin_num(opin_node)); 
+
+      if (true == compact_routing_hierarchy) {
+        /* Note: use GSB coordinate when inquire for unique modules!!! */
+        vtr::Point<size_t> sb_coord(rr_gsb.get_x(), rr_gsb.get_y());
+        const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(sb_coord);
+        const RRNodeId& unique_mirror_opin_node = unique_mirror.get_opin_node(side_manager.get_side(), inode);
+
+        port_name = generate_sb_module_grid_port_name(side_manager.get_side(),
+                                                      rr_graph.node_side(unique_mirror_opin_node),
+                                                      rr_graph.node_pin_num(unique_mirror_opin_node)); 
+      }
+
+
+      /* Ensure we have this port in the module! */
+      ModulePortId module_port = module_manager.find_module_port(sb_module, port_name);
+      VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module, module_port));
+
+      disable_analysis_module_input_port_net_sinks(fp, module_manager,
+                                                   sb_module,
+                                                   sb_instance_name,
+                                                   module_port,
+                                                   routing_annotation,
+                                                   opin_node,
+                                                   mux_instance_to_net_map);
+    }
+  }
+
+  /* Iterate over input ports coming from routing tracks */
+  for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
+    SideManager side_manager(side);
+
+    for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) {
+      /* Skip output ports, they have already been disabled or not */
+      if (OUT_PORT == rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) {
+        continue;
+      }
+
+      const RRNodeId& chan_node = rr_gsb.get_chan_node(side_manager.get_side(), itrack);
+
+      std::string port_name = generate_sb_module_track_port_name(rr_graph.node_type(chan_node),
+                                                                 side_manager.get_side(), itrack,  
+                                                                 rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack));
+
+      if (true == compact_routing_hierarchy) {
+        /* Note: use GSB coordinate when inquire for unique modules!!! */
+        vtr::Point<size_t> sb_coord(rr_gsb.get_x(), rr_gsb.get_y());
+        const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(sb_coord);
+        const RRNodeId& unique_mirror_chan_node = unique_mirror.get_chan_node(side_manager.get_side(), itrack);
+
+        port_name = generate_sb_module_track_port_name(rr_graph.node_type(unique_mirror_chan_node),
+                                                       side_manager.get_side(), itrack,  
+                                                       unique_mirror.get_chan_node_direction(side_manager.get_side(), itrack));
+      }
+
+
+      /* Ensure we have this port in the module! */
+      ModulePortId module_port = module_manager.find_module_port(sb_module, port_name);
+      VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module, module_port));
+
+      disable_analysis_module_input_port_net_sinks(fp, module_manager,
+                                                   sb_module,
+                                                   sb_instance_name,
+                                                   module_port,
+                                                   routing_annotation,
+                                                   chan_node,
+                                                   mux_instance_to_net_map);
+    }
+  }
+}
+
+
+/********************************************************************
+ * Iterate over all the connection blocks in a device
+ * and disable unused ports for each of them 
+ *******************************************************************/
+void print_analysis_sdc_disable_unused_sbs(std::fstream& fp,
+                                           const ModuleManager& module_manager, 
+                                           const RRGraph& rr_graph, 
+                                           const VprRoutingAnnotation& routing_annotation, 
+                                           const DeviceRRGSB& device_rr_gsb,
+                                           const bool& compact_routing_hierarchy) {
+
+  /* Build unique X-direction connection block modules */
+  vtr::Point<size_t> sb_range = device_rr_gsb.get_gsb_range();
+
+  for (size_t ix = 0; ix < sb_range.x(); ++ix) {
+    for (size_t iy = 0; iy < sb_range.y(); ++iy) {
+      /* Check if the connection block exists in the device!
+       * Some of them do NOT exist due to heterogeneous blocks (height > 1) 
+       * We will skip those modules
+       */
+      const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
+      if (false == rr_gsb.is_sb_exist()) {
+        continue;
+      }
+
+      print_analysis_sdc_disable_sb_unused_resources(fp,
+                                                     module_manager, 
+                                                     rr_graph, 
+                                                     routing_annotation, 
+                                                     device_rr_gsb, 
+                                                     rr_gsb, 
+                                                     compact_routing_hierarchy);
+    }
+  }
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_sdc/analysis_sdc_routing_writer.h b/openfpga/src/fpga_sdc/analysis_sdc_routing_writer.h
new file mode 100644
index 000000000..a5ea3249e
--- /dev/null
+++ b/openfpga/src/fpga_sdc/analysis_sdc_routing_writer.h
@@ -0,0 +1,35 @@
+#ifndef ANALYSIS_SDC_ROUTING_WRITER_H
+#define ANALYSIS_SDC_ROUTING_WRITER_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <fstream>
+#include <vector>
+#include "module_manager.h"
+#include "device_rr_gsb.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void print_analysis_sdc_disable_unused_cbs(std::fstream& fp,
+                                           const ModuleManager& module_manager, 
+                                           const RRGraph& rr_graph, 
+                                           const VprRoutingAnnotation& routing_annotation, 
+                                           const DeviceRRGSB& device_rr_gsb,
+                                           const bool& compact_routing_hierarchy);
+
+void print_analysis_sdc_disable_unused_sbs(std::fstream& fp,
+                                           const ModuleManager& module_manager, 
+                                           const RRGraph& rr_graph, 
+                                           const VprRoutingAnnotation& routing_annotation, 
+                                           const DeviceRRGSB& device_rr_gsb,
+                                           const bool& compact_routing_hierarchy);
+
+} /* end namespace openfpga */
+
+#endif

From 24f7416c7130f2ce97a3f8032ec51d19caada5cd Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 2 Mar 2020 17:15:01 -0700
Subject: [PATCH 244/645] adapt analysis SDC writer for grids

---
 .../src/fpga_sdc/analysis_sdc_grid_writer.cpp | 640 ++++++++++++++++++
 .../src/fpga_sdc/analysis_sdc_grid_writer.h   |  31 +
 .../fpga_sdc/analysis_sdc_routing_writer.cpp  |  36 +-
 .../fpga_sdc/analysis_sdc_routing_writer.h    |   3 +
 .../fpga_sdc/analysis_sdc_writer_utils.cpp    |  29 +-
 .../src/fpga_sdc/analysis_sdc_writer_utils.h  |  16 +-
 6 files changed, 718 insertions(+), 37 deletions(-)
 create mode 100644 openfpga/src/fpga_sdc/analysis_sdc_grid_writer.cpp
 create mode 100644 openfpga/src/fpga_sdc/analysis_sdc_grid_writer.h

diff --git a/openfpga/src/fpga_sdc/analysis_sdc_grid_writer.cpp b/openfpga/src/fpga_sdc/analysis_sdc_grid_writer.cpp
new file mode 100644
index 000000000..19d501a79
--- /dev/null
+++ b/openfpga/src/fpga_sdc/analysis_sdc_grid_writer.cpp
@@ -0,0 +1,640 @@
+/********************************************************************
+ * This file includes functions that are used to write SDC commands
+ * to disable unused ports of grids, such as Configurable Logic Block
+ * (CLBs), heterogeneous blocks, etc.
+ *******************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_digest.h"
+
+/* Headers from vprutil library */
+#include "vpr_utils.h"
+
+#include "openfpga_reserved_words.h"
+#include "openfpga_naming.h"
+
+#include "pb_type_utils.h"
+
+#include "sdc_writer_utils.h" 
+#include "analysis_sdc_writer_utils.h" 
+#include "analysis_sdc_grid_writer.h" 
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Recursively visit all the pb_types in the hierarchy 
+ * and disable all the ports
+ *
+ * Note: it is a must to disable all the ports in all the child pb_types!
+ * This can prohibit timing analyzer to consider any FF-to-FF path or 
+ * combinatinal path inside an unused grid, when finding critical paths!!!
+ *******************************************************************/
+static 
+void rec_print_analysis_sdc_disable_unused_pb_graph_nodes(std::fstream& fp, 
+                                                          const VprDeviceAnnotation& device_annotation,
+                                                          const ModuleManager& module_manager,
+                                                          const ModuleId& parent_module,
+                                                          const std::string& hierarchy_name,
+                                                          t_pb_graph_node* physical_pb_graph_node) {
+  t_pb_type* physical_pb_type = physical_pb_graph_node->pb_type;
+
+  /* Validate file stream */
+  valid_file_stream(fp);
+    
+  /* Disable all the ports of current module (parent_module)!
+   * Hierarchy name already includes the instance name of parent_module 
+   */
+  fp << "set_disable_timing ";
+  fp << hierarchy_name; 
+  fp << "/*";
+  fp << std::endl;
+
+  /* Return if this is the primitive pb_type */
+  if (true == is_primitive_pb_type(physical_pb_type)) {
+    return;
+  }
+
+  /* Go recursively */
+  t_mode* physical_mode = device_annotation.physical_mode(physical_pb_type);
+
+  /* Disable all the ports by iterating over its instance in the parent module */
+  for (int ichild = 0; ichild < physical_mode->num_pb_type_children; ++ichild) {
+    /* Generate the name of the Verilog module for this child */
+    std::string child_module_name = generate_physical_block_module_name(&(physical_mode->pb_type_children[ichild]));
+
+    ModuleId child_module = module_manager.find_module(child_module_name);
+    VTR_ASSERT(true == module_manager.valid_module_id(child_module));
+
+    /* Each child may exist multiple times in the hierarchy*/
+    for (int inst = 0; inst < physical_mode->pb_type_children[ichild].num_pb; ++inst) {
+      std::string child_instance_name = module_manager.instance_name(parent_module, child_module, module_manager.child_module_instances(parent_module, child_module)[inst]);
+      /* Must have a valid instance name!!! */
+      VTR_ASSERT(false == child_instance_name.empty()); 
+
+      std::string updated_hierarchy_name = hierarchy_name + std::string("/") + child_instance_name + std::string("/");
+
+      rec_print_analysis_sdc_disable_unused_pb_graph_nodes(fp, device_annotation, module_manager, child_module, hierarchy_name, 
+                                                           &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ichild][inst])); 
+    }
+  }
+}
+
+/********************************************************************
+ * Disable an unused pin of a pb_graph_node (parent_module) 
+ *******************************************************************/
+static
+void disable_pb_graph_node_unused_pin(std::fstream& fp, 
+                                      const ModuleManager& module_manager,
+                                      const ModuleId& parent_module,
+                                      const std::string& hierarchy_name,
+                                      const t_pb_graph_pin* pb_graph_pin,
+                                      const PhysicalPb& physical_pb,
+                                      const PhysicalPbId& pb_id) {
+  /* Validate file stream */
+  valid_file_stream(fp);
+    
+  /* Identify if the pb_graph_pin has been used or not
+   * TODO: identify if this is a parasitic net
+   */ 
+  if (AtomNetId::INVALID() != physical_pb.pb_graph_pin_atom_net(pb_id, pb_graph_pin)) {
+    /* Used pin; Nothing to do */
+    return;
+  }
+
+  /* Reach here, it means that this pin is not used. Disable timing analysis for the pin */
+  /* Find the module port by name */
+  std::string module_port_name = generate_pb_type_port_name(pb_graph_pin->port);
+  ModulePortId module_port = module_manager.find_module_port(parent_module, module_port_name);
+  VTR_ASSERT(true == module_manager.valid_module_port_id(parent_module, module_port));
+  BasicPort port_to_disable = module_manager.module_port(parent_module, module_port);
+  port_to_disable.set_width(pb_graph_pin->pin_number, pb_graph_pin->pin_number);
+
+  fp << "set_disable_timing ";
+  fp << hierarchy_name; 
+  fp << "/";
+  fp << generate_sdc_port(port_to_disable);
+  fp << std::endl;
+}
+
+/********************************************************************
+ * Disable unused input ports and output ports of this pb_graph_node (parent_module) 
+ * This function will iterate over all the input pins, output pins
+ * of the physical_pb_graph_node, and check if they are mapped
+ * For unused pins, we will find the port in parent_module
+ * and then print SDC commands to disable them
+ *******************************************************************/
+static
+void disable_pb_graph_node_unused_pins(std::fstream& fp, 
+                                       const ModuleManager& module_manager,
+                                       const ModuleId& parent_module,
+                                       const std::string& hierarchy_name,
+                                       t_pb_graph_node* physical_pb_graph_node,
+                                       const PhysicalPb& physical_pb) {
+  const PhysicalPbId& pb_id = physical_pb.find_pb(physical_pb_graph_node);
+  VTR_ASSERT(true == physical_pb.valid_pb_id(pb_id));
+
+  /* Disable unused input pins */
+  for (int iport = 0; iport < physical_pb_graph_node->num_input_ports; ++iport) {
+    for (int ipin = 0; ipin < physical_pb_graph_node->num_input_pins[iport]; ++ipin) {
+      disable_pb_graph_node_unused_pin(fp, module_manager, parent_module,
+                                       hierarchy_name,
+                                       &(physical_pb_graph_node->input_pins[iport][ipin]),
+                                       physical_pb, pb_id);
+    }
+  }
+
+  /* Disable unused output pins */
+  for (int iport = 0; iport < physical_pb_graph_node->num_output_ports; ++iport) {
+    for (int ipin = 0; ipin < physical_pb_graph_node->num_output_pins[iport]; ++ipin) {
+      disable_pb_graph_node_unused_pin(fp, module_manager, parent_module,
+                                       hierarchy_name,
+                                       &(physical_pb_graph_node->output_pins[iport][ipin]),
+                                       physical_pb, pb_id);
+    }
+  }
+
+  /* Disable unused clock pins */
+  for (int iport = 0; iport < physical_pb_graph_node->num_clock_ports; ++iport) {
+    for (int ipin = 0; ipin < physical_pb_graph_node->num_clock_pins[iport]; ++ipin) {
+      disable_pb_graph_node_unused_pin(fp, module_manager, parent_module,
+                                       hierarchy_name,
+                                       &(physical_pb_graph_node->clock_pins[iport][ipin]),
+                                       physical_pb, pb_id);
+    }
+  }
+}
+
+/********************************************************************
+ * Disable unused inputs of routing multiplexers of this pb_graph_node 
+ * This function will first cache the nets for each input and output pins 
+ * and store the results in a mux_name-to-net mapping
+ *******************************************************************/
+static 
+void disable_pb_graph_node_unused_mux_inputs(std::fstream& fp, 
+                                             const VprDeviceAnnotation& device_annotation,
+                                             const ModuleManager& module_manager,
+                                             const ModuleId& parent_module,
+                                             const std::string& hierarchy_name,
+                                             t_pb_graph_node* physical_pb_graph_node,
+                                             const PhysicalPb& physical_pb) {
+
+  t_pb_type* physical_pb_type = physical_pb_graph_node->pb_type;
+
+  t_mode* physical_mode = device_annotation.physical_mode(physical_pb_type);
+
+  std::map<std::string, AtomNetId> mux_instance_to_net_map;
+
+  /* Cache the nets for each input pins of each child pb_graph_node */
+  for (int ichild = 0; ichild < physical_mode->num_pb_type_children; ++ichild) {
+    for (int inst = 0; inst < physical_mode->pb_type_children[ichild].num_pb; ++inst) {
+
+      t_pb_graph_node* child_pb_graph_node = &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ichild][inst]); 
+
+      /* Cache the nets for input pins of the child pb_graph_node */
+      for (int iport = 0; iport < child_pb_graph_node->num_input_ports; ++iport) {
+        for (int ipin = 0; ipin < child_pb_graph_node->num_input_pins[iport]; ++ipin) {
+          const PhysicalPbId& pb_id = physical_pb.find_pb(child_pb_graph_node); 
+          VTR_ASSERT(true == physical_pb.valid_pb_id(pb_id));
+          /* Generate the mux name */ 
+          std::string mux_instance_name = generate_pb_mux_instance_name(GRID_MUX_INSTANCE_PREFIX, &(child_pb_graph_node->input_pins[iport][ipin]), std::string(""));
+          /* Cache the net */
+          mux_instance_to_net_map[mux_instance_name] = physical_pb.pb_graph_pin_atom_net(pb_id, &(child_pb_graph_node->input_pins[iport][ipin]));
+        }
+      }
+
+      /* Cache the nets for clock pins of the child pb_graph_node */
+      for (int iport = 0; iport < child_pb_graph_node->num_clock_ports; ++iport) {
+        for (int ipin = 0; ipin < child_pb_graph_node->num_clock_pins[iport]; ++ipin) {
+          const PhysicalPbId& pb_id = physical_pb.find_pb(child_pb_graph_node); 
+          /* Generate the mux name */ 
+          std::string mux_instance_name = generate_pb_mux_instance_name(GRID_MUX_INSTANCE_PREFIX, &(child_pb_graph_node->clock_pins[iport][ipin]), std::string(""));
+          /* Cache the net */
+          mux_instance_to_net_map[mux_instance_name] = physical_pb.pb_graph_pin_atom_net(pb_id, &(child_pb_graph_node->clock_pins[iport][ipin]));
+        }
+      }
+
+    }
+  }
+
+  /* Cache the nets for each output pins of this pb_graph_node */
+  for (int iport = 0; iport < physical_pb_graph_node->num_output_ports; ++iport) {
+    for (int ipin = 0; ipin < physical_pb_graph_node->num_output_pins[iport]; ++ipin) {
+      const PhysicalPbId& pb_id = physical_pb.find_pb(physical_pb_graph_node); 
+      /* Generate the mux name */ 
+      std::string mux_instance_name = generate_pb_mux_instance_name(GRID_MUX_INSTANCE_PREFIX, &(physical_pb_graph_node->output_pins[iport][ipin]), std::string(""));
+      /* Cache the net */
+      mux_instance_to_net_map[mux_instance_name] = physical_pb.pb_graph_pin_atom_net(pb_id, &(physical_pb_graph_node->output_pins[iport][ipin]));
+    }
+  }
+
+  /* Now disable unused inputs of routing multiplexers, by tracing from input pins of the parent_module */ 
+  for (int iport = 0; iport < physical_pb_graph_node->num_input_ports; ++iport) {
+    for (int ipin = 0; ipin < physical_pb_graph_node->num_input_pins[iport]; ++ipin) {
+      /* Find the module port by name */
+      std::string module_port_name = generate_pb_type_port_name(physical_pb_graph_node->input_pins[iport][ipin].port);
+      ModulePortId module_port = module_manager.find_module_port(parent_module, module_port_name);
+      VTR_ASSERT(true == module_manager.valid_module_port_id(parent_module, module_port));
+
+      const PhysicalPbId& pb_id = physical_pb.find_pb(physical_pb_graph_node); 
+      const AtomNetId& mapped_net = physical_pb.pb_graph_pin_atom_net(pb_id, &(physical_pb_graph_node->input_pins[iport][ipin])); 
+
+      disable_analysis_module_input_pin_net_sinks(fp, module_manager, parent_module,
+                                                  hierarchy_name,
+                                                  module_port, ipin,
+                                                  mapped_net,
+                                                  mux_instance_to_net_map);
+    }
+  }
+
+  for (int iport = 0; iport < physical_pb_graph_node->num_clock_ports; ++iport) {
+    for (int ipin = 0; ipin < physical_pb_graph_node->num_clock_pins[iport]; ++ipin) {
+      /* Find the module port by name */
+      std::string module_port_name = generate_pb_type_port_name(physical_pb_graph_node->clock_pins[iport][ipin].port);
+      ModulePortId module_port = module_manager.find_module_port(parent_module, module_port_name);
+      VTR_ASSERT(true == module_manager.valid_module_port_id(parent_module, module_port));
+
+      const PhysicalPbId& pb_id = physical_pb.find_pb(physical_pb_graph_node); 
+      const AtomNetId& mapped_net = physical_pb.pb_graph_pin_atom_net(pb_id, &(physical_pb_graph_node->clock_pins[iport][ipin])); 
+
+      disable_analysis_module_input_pin_net_sinks(fp, module_manager, parent_module,
+                                                  hierarchy_name,
+                                                  module_port, ipin,
+                                                  mapped_net,
+                                                  mux_instance_to_net_map);
+    }
+  }
+
+  /* Now disable unused inputs of routing multiplexers, by tracing from output pins of the child_module */ 
+  for (int ichild = 0; ichild < physical_mode->num_pb_type_children; ++ichild) {
+    /* Generate the name of the Verilog module for this child */
+    std::string child_module_name = generate_physical_block_module_name(&(physical_mode->pb_type_children[ichild]));
+
+    ModuleId child_module = module_manager.find_module(child_module_name);
+    VTR_ASSERT(true == module_manager.valid_module_id(child_module));
+
+    for (int inst = 0; inst < physical_mode->pb_type_children[ichild].num_pb; ++inst) {
+
+      t_pb_graph_node* child_pb_graph_node = &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ichild][inst]); 
+
+      for (int iport = 0; iport < child_pb_graph_node->num_output_ports; ++iport) {
+        for (int ipin = 0; ipin < child_pb_graph_node->num_output_pins[iport]; ++ipin) {
+          /* Find the module port by name */
+          std::string module_port_name = generate_pb_type_port_name(child_pb_graph_node->output_pins[iport][ipin].port);
+          ModulePortId module_port = module_manager.find_module_port(child_module, module_port_name);
+          VTR_ASSERT(true == module_manager.valid_module_port_id(child_module, module_port));
+
+          const PhysicalPbId& pb_id = physical_pb.find_pb(child_pb_graph_node); 
+          const AtomNetId& mapped_net = physical_pb.pb_graph_pin_atom_net(pb_id, &(child_pb_graph_node->output_pins[iport][ipin])); 
+
+          /* Corner case: if the pb_graph_pin has no fan-out we will skip this pin */
+          if (0 == child_pb_graph_node->output_pins[iport][ipin].num_output_edges) {
+            continue;
+          }
+
+          disable_analysis_module_output_pin_net_sinks(fp, module_manager, parent_module,
+                                                       hierarchy_name,
+                                                       child_module, inst, 
+                                                       module_port, ipin,
+                                                       mapped_net, 
+                                                       mux_instance_to_net_map);
+        }
+      }
+    }
+  }
+}
+
+/********************************************************************
+ * Recursively visit all the pb_types in the hierarchy 
+ * and disable all the unused resources, including:
+ * 1. input ports
+ * 2. output ports
+ * 3. unused inputs of routing multiplexers
+ *
+ * As this function is executed in a recursive way. 
+ * To avoid repeated disable timing for ports, during each run of this function,
+ * only the unused input ports, output ports of the parent module will be disabled.
+ * In addition, we will cache all the net ids mapped to the input ports of 
+ * child modules, and the net ids mapped to the output ports of parent module.
+ * As such, we can trace from 
+ * 1. the input ports of parent module to disable unused inputs of routing multiplexer
+ *    which drives the inputs of child modules
+ *                      
+ *                          Parent_module
+ *                         +---------------------------------------------
+ *                         |          MUX                  child_module
+ *                         |         +-------------+       +--------
+ *    input_pin0(netA) --->|-------->| Routing     |------>|
+ *    input_pin1(netB) --->|----x--->| Multiplexer | netA  |
+ *                         |         +-------------+       |
+ *                         |                               |
+ *
+ * 2. the output ports of child module to disable unused inputs of routing multiplexer
+ *    which drives the outputs of parent modules
+ *
+ *   Case 1: 
+ *                                  parent_module
+ *         --------------------------------------+
+ *         child_module                          |
+ *        -------------+                         |
+ *                     |    +-------------+      |
+ *  output_pin0 (netA) |--->| Routing     |----->|---->
+ *  output_pin1 (netB) |-x->| Multiplexer | netA |
+ *                     |    +-------------+      |
+ *
+ *    Case 2: 
+ *
+ *                         Parent_module
+ *                         +---------------------------------------------
+ *                         |
+ *                         |    +--------------------------------------------+
+ *                         |    |     MUX                  child_module      |
+ *                         |    |    +-------------+       +-----------+     |
+ *                         |    +--->| Routing     |------>|           |     |
+ *    input_pin0(netA) --->|----x--->| Multiplexer | netA  | output_pin|-----+
+ *                         |         +-------------+       |           | netA
+ *                         |                               |           |
+ *
+ *
+ * Note: it is a must to disable all the ports in all the child pb_types!
+ * This can prohibit timing analyzer to consider any FF-to-FF path or 
+ * combinatinal path inside an unused grid, when finding critical paths!!!
+ *******************************************************************/
+static 
+void rec_print_analysis_sdc_disable_pb_graph_node_unused_resources(std::fstream& fp, 
+                                                                   const VprDeviceAnnotation& device_annotation,
+                                                                   const ModuleManager& module_manager,
+                                                                   const ModuleId& parent_module,
+                                                                   const std::string& hierarchy_name,
+                                                                   t_pb_graph_node* physical_pb_graph_node,
+                                                                   const PhysicalPb& physical_pb) {
+  t_pb_type* physical_pb_type = physical_pb_graph_node->pb_type;
+
+  /* Disable unused input ports and output ports of this pb_graph_node (parent_module) */
+  disable_pb_graph_node_unused_pins(fp, module_manager, parent_module,
+                                    hierarchy_name, physical_pb_graph_node, physical_pb); 
+
+  /* Return if this is the primitive pb_type 
+   * Note: this must return before we disable any unused inputs of routing multiplexer!
+   * This is due to that primitive pb_type does NOT contain any routing multiplexers inside!!!   
+   */
+  if (true == is_primitive_pb_type(physical_pb_type)) {
+    return;
+  }
+
+  /* Disable unused inputs of routing multiplexers of this pb_graph_node */
+  disable_pb_graph_node_unused_mux_inputs(fp, device_annotation,
+                                          module_manager, parent_module, 
+                                          hierarchy_name, physical_pb_graph_node,
+                                          physical_pb);
+
+
+  t_mode* physical_mode = device_annotation.physical_mode(physical_pb_type);
+
+  /* Disable all the ports by iterating over its instance in the parent module */
+  for (int ichild = 0; ichild < physical_mode->num_pb_type_children; ++ichild) {
+    /* Generate the name of the Verilog module for this child */
+    std::string child_module_name = generate_physical_block_module_name(&(physical_mode->pb_type_children[ichild]));
+
+    ModuleId child_module = module_manager.find_module(child_module_name);
+    VTR_ASSERT(true == module_manager.valid_module_id(child_module));
+
+    /* Each child may exist multiple times in the hierarchy*/
+    for (int inst = 0; inst < physical_pb_type->modes[physical_mode->index].pb_type_children[ichild].num_pb; ++inst) {
+      std::string child_instance_name = module_manager.instance_name(parent_module, child_module, module_manager.child_module_instances(parent_module, child_module)[inst]);
+      /* Must have a valid instance name!!! */
+      VTR_ASSERT(false == child_instance_name.empty()); 
+
+      std::string updated_hierarchy_name = hierarchy_name + std::string("/") + child_instance_name + std::string("/");
+
+      rec_print_analysis_sdc_disable_pb_graph_node_unused_resources(fp, device_annotation,
+                                                                    module_manager, child_module, hierarchy_name, 
+                                                                    &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ichild][inst]), 
+                                                                    physical_pb); 
+    }
+  }
+}
+
+/********************************************************************
+ * This function can work in two differnt modes:
+ * 1. For partially unused pb blocks
+ * ---------------------------------
+ * Disable the timing for only unused resources in a physical block
+ * We have to walk through pb_graph node, port by port and pin by pin.
+ * Identify which pins have not been used, and then disable the timing 
+ * for these ports. 
+ * Plus, for input ports, we will trace the routing multiplexers
+ * and disable the timing for unused inputs.
+ *
+ * 2. For fully unused pb_blocks
+ * ----------------------------- 
+ * Disable the timing for a fully unused grid!
+ * This is very straightforward!
+ * Just walk through each pb_type and disable all the ports using wildcards
+ *******************************************************************/
+static 
+void print_analysis_sdc_disable_pb_block_unused_resources(std::fstream& fp,
+                                                          t_physical_tile_type_ptr grid_type,
+                                                          const vtr::Point<size_t>& grid_coordinate,
+                                                          const VprDeviceAnnotation& device_annotation,
+                                                          const ModuleManager& module_manager,
+                                                          const std::string& grid_instance_name,
+                                                          const size_t& grid_z,
+                                                          const PhysicalPb& physical_pb,
+                                                          const bool& unused_block) {
+  /* If the block is partially unused, we should have a physical pb */
+  if (false == unused_block) {
+    VTR_ASSERT(false == physical_pb.empty());
+  }
+
+  VTR_ASSERT(1 == grid_type->equivalent_sites.size());
+  t_pb_graph_node* pb_graph_head = grid_type->equivalent_sites[0]->pb_graph_head; 
+  VTR_ASSERT(nullptr != pb_graph_head);
+
+  /* Find an unique name to the pb instance in this grid
+   * Note: this must be consistent with the instance name we used in build_grid_module()!!!
+   */
+  /* TODO: validate that the instance name is used in module manager!!! */
+  std::string pb_module_name = generate_physical_block_module_name(pb_graph_head->pb_type);
+  std::string pb_instance_name = generate_physical_block_instance_name(pb_graph_head->pb_type, grid_z);
+
+  ModuleId pb_module = module_manager.find_module(pb_module_name);
+  VTR_ASSERT(true == module_manager.valid_module_id(pb_module));
+
+  /* Print comments */
+  fp << "#######################################" << std::endl; 
+ 
+  if (true == unused_block) {
+    fp << "# Disable Timing for unused grid[" << grid_coordinate.x() << "][" << grid_coordinate.y() << "][" << grid_z << "]" << std::endl;
+  } else {
+    VTR_ASSERT_SAFE(false == unused_block);
+    fp << "# Disable Timing for unused resources in grid[" << grid_coordinate.x() << "][" << grid_coordinate.y() << "][" << grid_z << "]" << std::endl;
+  }
+
+  fp << "#######################################" << std::endl; 
+
+  std::string hierarchy_name = grid_instance_name + std::string("/") + pb_instance_name + std::string("/");
+
+  /* Go recursively through the pb_graph hierarchy, and disable all the ports level by level */
+  if (true == unused_block) {
+    rec_print_analysis_sdc_disable_unused_pb_graph_nodes(fp, device_annotation,
+                                                         module_manager, pb_module, hierarchy_name,
+                                                         pb_graph_head); 
+  } else { 
+    VTR_ASSERT_SAFE(false == unused_block);
+    rec_print_analysis_sdc_disable_pb_graph_node_unused_resources(fp, device_annotation,
+                                                                  module_manager, pb_module, hierarchy_name,
+                                                                  pb_graph_head, physical_pb); 
+  }
+}
+
+/********************************************************************
+ * Disable the timing for a fully unused grid!
+ * This is very straightforward!
+ * Just walk through each pb_type and disable all the ports using wildcards
+ *******************************************************************/
+static 
+void print_analysis_sdc_disable_unused_grid(std::fstream& fp, 
+                                            const vtr::Point<size_t>& grid_coordinate,
+                                            const DeviceGrid& grids, 
+                                            const VprDeviceAnnotation& device_annotation,
+                                            const VprClusteringAnnotation& cluster_annotation,
+                                            const VprPlacementAnnotation& place_annotation,
+                                            const ModuleManager& module_manager,
+                                            const e_side& border_side) {
+  /* Validate file stream */
+  valid_file_stream(fp);
+
+  t_physical_tile_type_ptr grid_type = grids[grid_coordinate.x()][grid_coordinate.y()].type;
+  /* Bypass conditions for grids : 
+   * 1. EMPTY type, which is by nature unused
+   * 2. Offset > 0, which has already been processed when offset = 0
+   */
+  if ( (true == is_empty_type(grid_type))
+    || (0 < grids[grid_coordinate.x()][grid_coordinate.y()].width_offset)
+    || (0 < grids[grid_coordinate.x()][grid_coordinate.y()].height_offset) ) {
+    return;
+  }
+
+  /* Find an unique name to the grid instane
+   * Note: this must be consistent with the instance name we used in build_top_module()!!!
+   */
+  /* TODO: validate that the instance name is used in module manager!!! */
+  std::string grid_module_name_prefix(GRID_MODULE_NAME_PREFIX);
+  std::string grid_module_name = generate_grid_block_module_name(grid_module_name_prefix, std::string(grid_type->name), is_io_type(grid_type), border_side);
+  std::string grid_instance_name = generate_grid_block_instance_name(grid_module_name_prefix, std::string(grid_type->name), is_io_type(grid_type), border_side, grid_coordinate);
+
+  ModuleId grid_module = module_manager.find_module(grid_module_name);
+  VTR_ASSERT(true == module_manager.valid_module_id(grid_module));
+
+  /* Print comments */
+  fp << "#######################################" << std::endl; 
+  fp << "# Disable Timing for grid[" << grid_coordinate.x() << "][" << grid_coordinate.y() << "]" << std::endl;
+  fp << "#######################################" << std::endl; 
+
+  /* For used grid, find the unused rr_node in the local rr_graph 
+   * and then disable each port which is not used
+   * as well as the unused inputs of routing multiplexers!
+   */
+  size_t grid_z = 0;
+  for (const ClusterBlockId& blk_id : place_annotation.grid_blocks(grid_coordinate)) {
+    if (ClusterBlockId::INVALID() != blk_id) { 
+      const PhysicalPb& physical_pb = cluster_annotation.physical_pb(blk_id);
+      print_analysis_sdc_disable_pb_block_unused_resources(fp, grid_type, grid_coordinate,
+                                                           device_annotation,
+                                                           module_manager, grid_instance_name, grid_z,
+                                                           physical_pb, false);
+    } else {
+      VTR_ASSERT(ClusterBlockId::INVALID() == blk_id);
+      /* For unused grid, disable all the pins in the physical_pb_type */
+      print_analysis_sdc_disable_pb_block_unused_resources(fp, grid_type, grid_coordinate,
+                                                           device_annotation, 
+                                                           module_manager, grid_instance_name, grid_z,
+                                                           PhysicalPb(), true);
+    }
+    grid_z++;
+  }
+}
+
+/********************************************************************
+ * Top-level function writes SDC commands to disable unused ports 
+ * of grids, such as Configurable Logic Block (CLBs), heterogeneous blocks, etc.
+ *
+ * This function will iterate over all the grids available in the FPGA fabric
+ * It will disable the timing analysis for
+ * 1. Grids, which are totally not used (no logic has been mapped to)
+ * 2. Unused part of grids, including the ports, inputs of routing multiplexers 
+ *
+ * Note that it is a must to disable the unused inputs of routing multiplexers
+ * because it will cause unexpected paths in timing analysis
+ * For example:
+ *                           +---------------------+
+ *     inputA (net0) ------->|                     |
+ *                           | Routing multiplexer |----> output (net0)
+ *     inputB (net1) ------->|                     |
+ *                           +---------------------+
+ *
+ * During timing analysis, the path from inputA to output should be considered
+ * while the path from inputB to output should NOT be considered!!!
+ *
+ *******************************************************************/
+void print_analysis_sdc_disable_unused_grids(std::fstream& fp, 
+                                             const DeviceGrid& grids, 
+                                             const VprDeviceAnnotation& device_annotation,
+                                             const VprClusteringAnnotation& cluster_annotation,
+                                             const VprPlacementAnnotation& place_annotation,
+                                             const ModuleManager& module_manager) {
+
+  /* Process unused core grids */
+  for (size_t ix = 1; ix < grids.width() - 1; ++ix) {
+    for (size_t iy = 1; iy < grids.height() - 1; ++iy) {
+      /* We should not meet any I/O grid */
+      VTR_ASSERT(false != is_io_type(grids[ix][iy].type));
+
+      print_analysis_sdc_disable_unused_grid(fp, vtr::Point<size_t>(ix, iy),
+                                             grids, device_annotation, cluster_annotation, place_annotation,
+                                             module_manager, NUM_SIDES);
+    }
+  }
+
+  /* Instanciate I/O grids */
+  /* Create the coordinate range for each side of FPGA fabric */
+  std::vector<e_side> io_sides{TOP, RIGHT, BOTTOM, LEFT};
+  std::map<e_side, std::vector<vtr::Point<size_t>>> io_coordinates;
+
+  /* TOP side*/
+  for (size_t ix = 1; ix < grids.width() - 1; ++ix) { 
+    io_coordinates[TOP].push_back(vtr::Point<size_t>(ix, grids.height() - 1));
+  } 
+
+  /* RIGHT side */
+  for (size_t iy = 1; iy < grids.height() - 1; ++iy) { 
+    io_coordinates[RIGHT].push_back(vtr::Point<size_t>(grids.width() - 1, iy));
+  } 
+
+  /* BOTTOM side*/
+  for (size_t ix = 1; ix < grids.width() - 1; ++ix) { 
+    io_coordinates[BOTTOM].push_back(vtr::Point<size_t>(ix, 0));
+  } 
+
+  /* LEFT side */
+  for (size_t iy = 1; iy < grids.height() - 1; ++iy) { 
+    io_coordinates[LEFT].push_back(vtr::Point<size_t>(0, iy));
+  }
+
+  /* Add instances of I/O grids to top_module */
+  for (const e_side& io_side : io_sides) {
+    for (const vtr::Point<size_t>& io_coordinate : io_coordinates[io_side]) {
+      /* We should not meet any I/O grid */
+      VTR_ASSERT(true == is_io_type(grids[io_coordinate.x()][io_coordinate.y()].type));
+
+      print_analysis_sdc_disable_unused_grid(fp, io_coordinate,
+                                             grids, device_annotation, cluster_annotation, place_annotation,
+                                             module_manager, io_side);
+    }
+  }
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_sdc/analysis_sdc_grid_writer.h b/openfpga/src/fpga_sdc/analysis_sdc_grid_writer.h
new file mode 100644
index 000000000..be01bbf28
--- /dev/null
+++ b/openfpga/src/fpga_sdc/analysis_sdc_grid_writer.h
@@ -0,0 +1,31 @@
+#ifndef ANALYSIS_SDC_GRID_WRITER_H
+#define ANALYSIS_SDC_GRID_WRITER_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <fstream>
+#include <vector>
+#include "device_grid.h"
+#include "module_manager.h"
+#include "vpr_device_annotation.h"
+#include "vpr_clustering_annotation.h"
+#include "vpr_placement_annotation.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void print_analysis_sdc_disable_unused_grids(std::fstream& fp, 
+                                             const DeviceGrid& grids, 
+                                             const VprDeviceAnnotation& device_annotation,
+                                             const VprClusteringAnnotation& cluster_annotation,
+                                             const VprPlacementAnnotation& place_annotation,
+                                             const ModuleManager& module_manager);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/fpga_sdc/analysis_sdc_routing_writer.cpp b/openfpga/src/fpga_sdc/analysis_sdc_routing_writer.cpp
index f9384af04..d210ecacd 100644
--- a/openfpga/src/fpga_sdc/analysis_sdc_routing_writer.cpp
+++ b/openfpga/src/fpga_sdc/analysis_sdc_routing_writer.cpp
@@ -31,6 +31,7 @@ namespace openfpga {
  *******************************************************************/
 static 
 void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp, 
+                                                    const AtomContext& atom_ctx, 
                                                     const ModuleManager& module_manager, 
                                                     const RRGraph& rr_graph, 
                                                     const VprRoutingAnnotation& routing_annotation, 
@@ -112,7 +113,7 @@ void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp,
   }
 
   /* Build a map between mux_instance name and net_num */
-  std::map<std::string, ClusterNetId> mux_instance_to_net_map;
+  std::map<std::string, AtomNetId> mux_instance_to_net_map;
 
   /* Disable all the output port (grid input pins), which are not used by benchmark */
   std::vector<enum e_side> cb_sides = rr_gsb.get_cb_ipin_sides(cb_type);
@@ -124,7 +125,7 @@ void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp,
 
       /* Find the MUX instance that drives the IPIN! */
       std::string mux_instance_name = generate_cb_mux_instance_name(CONNECTION_BLOCK_MUX_INSTANCE_PREFIX, rr_graph.node_side(ipin_node), inode, std::string(""));
-      mux_instance_to_net_map[mux_instance_name] = routing_annotation.rr_node_net(ipin_node);  
+      mux_instance_to_net_map[mux_instance_name] = atom_ctx.lookup.atom_net(routing_annotation.rr_node_net(ipin_node));  
 
       if (false == is_rr_node_to_be_disable_for_analysis(routing_annotation, ipin_node)) {
         continue;
@@ -187,12 +188,13 @@ void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp,
     ModulePortId module_port = module_manager.find_module_port(cb_module, port_name);
     VTR_ASSERT(true == module_manager.valid_module_port_id(cb_module, module_port));
 
+    AtomNetId mapped_atom_net = atom_ctx.lookup.atom_net(routing_annotation.rr_node_net(chan_node)); 
+
     disable_analysis_module_input_port_net_sinks(fp, 
                                                  module_manager, cb_module,
                                                  cb_instance_name,
                                                  module_port,
-                                                 routing_annotation,
-                                                 chan_node,
+                                                 mapped_atom_net,
                                                  mux_instance_to_net_map);
   }
 }
@@ -203,6 +205,7 @@ void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp,
  *******************************************************************/
 static 
 void print_analysis_sdc_disable_unused_cb_ports(std::fstream& fp,
+                                                const AtomContext& atom_ctx, 
                                                 const ModuleManager& module_manager, 
                                                 const RRGraph& rr_graph, 
                                                 const VprRoutingAnnotation& routing_annotation, 
@@ -224,6 +227,7 @@ void print_analysis_sdc_disable_unused_cb_ports(std::fstream& fp,
       }
 
       print_analysis_sdc_disable_cb_unused_resources(fp, 
+                                                     atom_ctx, 
                                                      module_manager, 
                                                      rr_graph, 
                                                      routing_annotation, 
@@ -240,19 +244,22 @@ void print_analysis_sdc_disable_unused_cb_ports(std::fstream& fp,
  * and disable unused ports for each of them 
  *******************************************************************/
 void print_analysis_sdc_disable_unused_cbs(std::fstream& fp,
+                                           const AtomContext& atom_ctx, 
                                            const ModuleManager& module_manager, 
                                            const RRGraph& rr_graph, 
                                            const VprRoutingAnnotation& routing_annotation, 
                                            const DeviceRRGSB& device_rr_gsb,
                                            const bool& compact_routing_hierarchy) {
 
-  print_analysis_sdc_disable_unused_cb_ports(fp, module_manager, 
+  print_analysis_sdc_disable_unused_cb_ports(fp, atom_ctx,
+                                             module_manager, 
                                              rr_graph, 
                                              routing_annotation,
                                              device_rr_gsb,
                                              CHANX, compact_routing_hierarchy);
 
-  print_analysis_sdc_disable_unused_cb_ports(fp, module_manager, 
+  print_analysis_sdc_disable_unused_cb_ports(fp, atom_ctx,
+                                             module_manager, 
                                              rr_graph, 
                                              routing_annotation,
                                              device_rr_gsb,
@@ -267,6 +274,7 @@ void print_analysis_sdc_disable_unused_cbs(std::fstream& fp,
  *******************************************************************/
 static 
 void print_analysis_sdc_disable_sb_unused_resources(std::fstream& fp, 
+                                                    const AtomContext& atom_ctx, 
                                                     const ModuleManager& module_manager, 
                                                     const RRGraph& rr_graph, 
                                                     const VprRoutingAnnotation& routing_annotation, 
@@ -301,7 +309,7 @@ void print_analysis_sdc_disable_sb_unused_resources(std::fstream& fp,
   fp << "##################################################" << std::endl; 
 
   /* Build a map between mux_instance name and net_num */
-  std::map<std::string, ClusterNetId> mux_instance_to_net_map;
+  std::map<std::string, AtomNetId> mux_instance_to_net_map;
 
   /* Disable all the input/output port (routing tracks), which are not used by benchmark */
   for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
@@ -331,7 +339,7 @@ void print_analysis_sdc_disable_sb_unused_resources(std::fstream& fp,
       if (OUT_PORT == rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) {
         /* Generate the name of mux instance related to this output node */
         std::string mux_instance_name = generate_sb_memory_instance_name(SWITCH_BLOCK_MUX_INSTANCE_PREFIX, side_manager.get_side(), itrack, std::string(""));
-        mux_instance_to_net_map[mux_instance_name] = routing_annotation.rr_node_net(chan_node);
+        mux_instance_to_net_map[mux_instance_name] = atom_ctx.lookup.atom_net(routing_annotation.rr_node_net(chan_node));
       }
 
       /* Check if this node is used by benchmark  */
@@ -435,12 +443,13 @@ void print_analysis_sdc_disable_sb_unused_resources(std::fstream& fp,
       ModulePortId module_port = module_manager.find_module_port(sb_module, port_name);
       VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module, module_port));
 
+      AtomNetId mapped_atom_net = atom_ctx.lookup.atom_net(routing_annotation.rr_node_net(opin_node));
+
       disable_analysis_module_input_port_net_sinks(fp, module_manager,
                                                    sb_module,
                                                    sb_instance_name,
                                                    module_port,
-                                                   routing_annotation,
-                                                   opin_node,
+                                                   mapped_atom_net,
                                                    mux_instance_to_net_map);
     }
   }
@@ -477,12 +486,13 @@ void print_analysis_sdc_disable_sb_unused_resources(std::fstream& fp,
       ModulePortId module_port = module_manager.find_module_port(sb_module, port_name);
       VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module, module_port));
 
+      AtomNetId mapped_atom_net = atom_ctx.lookup.atom_net(routing_annotation.rr_node_net(chan_node));
+
       disable_analysis_module_input_port_net_sinks(fp, module_manager,
                                                    sb_module,
                                                    sb_instance_name,
                                                    module_port,
-                                                   routing_annotation,
-                                                   chan_node,
+                                                   mapped_atom_net,
                                                    mux_instance_to_net_map);
     }
   }
@@ -494,6 +504,7 @@ void print_analysis_sdc_disable_sb_unused_resources(std::fstream& fp,
  * and disable unused ports for each of them 
  *******************************************************************/
 void print_analysis_sdc_disable_unused_sbs(std::fstream& fp,
+                                           const AtomContext& atom_ctx, 
                                            const ModuleManager& module_manager, 
                                            const RRGraph& rr_graph, 
                                            const VprRoutingAnnotation& routing_annotation, 
@@ -515,6 +526,7 @@ void print_analysis_sdc_disable_unused_sbs(std::fstream& fp,
       }
 
       print_analysis_sdc_disable_sb_unused_resources(fp,
+                                                     atom_ctx, 
                                                      module_manager, 
                                                      rr_graph, 
                                                      routing_annotation, 
diff --git a/openfpga/src/fpga_sdc/analysis_sdc_routing_writer.h b/openfpga/src/fpga_sdc/analysis_sdc_routing_writer.h
index a5ea3249e..7322fc8f6 100644
--- a/openfpga/src/fpga_sdc/analysis_sdc_routing_writer.h
+++ b/openfpga/src/fpga_sdc/analysis_sdc_routing_writer.h
@@ -6,6 +6,7 @@
  *******************************************************************/
 #include <fstream>
 #include <vector>
+#include "vpr_context.h"
 #include "module_manager.h"
 #include "device_rr_gsb.h"
 
@@ -17,6 +18,7 @@
 namespace openfpga {
 
 void print_analysis_sdc_disable_unused_cbs(std::fstream& fp,
+                                           const AtomContext& atom_ctx, 
                                            const ModuleManager& module_manager, 
                                            const RRGraph& rr_graph, 
                                            const VprRoutingAnnotation& routing_annotation, 
@@ -24,6 +26,7 @@ void print_analysis_sdc_disable_unused_cbs(std::fstream& fp,
                                            const bool& compact_routing_hierarchy);
 
 void print_analysis_sdc_disable_unused_sbs(std::fstream& fp,
+                                           const AtomContext& atom_ctx, 
                                            const ModuleManager& module_manager, 
                                            const RRGraph& rr_graph, 
                                            const VprRoutingAnnotation& routing_annotation, 
diff --git a/openfpga/src/fpga_sdc/analysis_sdc_writer_utils.cpp b/openfpga/src/fpga_sdc/analysis_sdc_writer_utils.cpp
index 511271915..8ac184b61 100644
--- a/openfpga/src/fpga_sdc/analysis_sdc_writer_utils.cpp
+++ b/openfpga/src/fpga_sdc/analysis_sdc_writer_utils.cpp
@@ -53,9 +53,8 @@ void disable_analysis_module_input_pin_net_sinks(std::fstream& fp,
                                                  const std::string& parent_instance_name,
                                                  const ModulePortId& module_input_port,
                                                  const size_t& module_input_pin,
-                                                 const VprRoutingAnnotation& routing_annotation,
-                                                 const RRNodeId& input_rr_node,
-                                                 const std::map<std::string, ClusterNetId> mux_instance_to_net_map) {
+                                                 const AtomNetId& mapped_net,
+                                                 const std::map<std::string, AtomNetId> mux_instance_to_net_map) {
   /* Validate file stream */
   valid_file_stream(fp);
 
@@ -78,14 +77,14 @@ void disable_analysis_module_input_pin_net_sinks(std::fstream& fp,
     std::string sink_instance_name = module_manager.instance_name(parent_module, sink_module, sink_instance);
     bool disable_timing = false;
     /* Check if this node is used by benchmark  */
-    if (true == is_rr_node_to_be_disable_for_analysis(routing_annotation, input_rr_node)) {
+    if (AtomNetId::INVALID() == mapped_net) {
       /* Disable all the sinks! */
       disable_timing = true;
     } else {
-      std::map<std::string, ClusterNetId>::const_iterator it = mux_instance_to_net_map.find(sink_instance_name);
+      std::map<std::string, AtomNetId>::const_iterator it = mux_instance_to_net_map.find(sink_instance_name);
       if (it != mux_instance_to_net_map.end()) {
         /* See if the net id matches. If does not match, we should disable! */
-        if (routing_annotation.rr_node_net(input_rr_node) != mux_instance_to_net_map.at(sink_instance_name)) {
+        if (mapped_net != mux_instance_to_net_map.at(sink_instance_name)) {
           disable_timing = true;
         }
       }
@@ -132,9 +131,8 @@ void disable_analysis_module_input_port_net_sinks(std::fstream& fp,
                                                   const ModuleId& parent_module,
                                                   const std::string& parent_instance_name,
                                                   const ModulePortId& module_input_port,
-                                                  const VprRoutingAnnotation& routing_annotation,
-                                                  const RRNodeId& input_rr_node,
-                                                  const std::map<std::string, ClusterNetId> mux_instance_to_net_map) {
+                                                  const AtomNetId& mapped_net,
+                                                  const std::map<std::string, AtomNetId> mux_instance_to_net_map) {
   /* Validate file stream */
   valid_file_stream(fp);
 
@@ -143,7 +141,7 @@ void disable_analysis_module_input_port_net_sinks(std::fstream& fp,
     disable_analysis_module_input_pin_net_sinks(fp, module_manager, parent_module,
                                                 parent_instance_name,
                                                 module_input_port, pin,
-                                                routing_annotation, input_rr_node,
+                                                mapped_net,
                                                 mux_instance_to_net_map);
   }
 }
@@ -178,9 +176,8 @@ void disable_analysis_module_output_pin_net_sinks(std::fstream& fp,
                                                   const size_t& child_instance,
                                                   const ModulePortId& child_module_port,
                                                   const size_t& child_module_pin,
-                                                  const VprRoutingAnnotation& routing_annotation,
-                                                  const RRNodeId& output_rr_node,
-                                                  const std::map<std::string, ClusterNetId> mux_instance_to_net_map) {
+                                                  const AtomNetId& mapped_net,
+                                                  const std::map<std::string, AtomNetId> mux_instance_to_net_map) {
   /* Validate file stream */
   valid_file_stream(fp);
 
@@ -203,14 +200,14 @@ void disable_analysis_module_output_pin_net_sinks(std::fstream& fp,
     std::string sink_instance_name = module_manager.instance_name(parent_module, sink_module, sink_instance);
     bool disable_timing = false;
     /* Check if this node is used by benchmark  */
-    if (true == is_rr_node_to_be_disable_for_analysis(routing_annotation, output_rr_node)) {
+    if (AtomNetId::INVALID() == mapped_net) {
       /* Disable all the sinks! */
       disable_timing = true;
     } else {
-      std::map<std::string, ClusterNetId>::const_iterator it = mux_instance_to_net_map.find(sink_instance_name);
+      std::map<std::string, AtomNetId>::const_iterator it = mux_instance_to_net_map.find(sink_instance_name);
       if (it != mux_instance_to_net_map.end()) {
         /* See if the net id matches. If does not match, we should disable! */
-        if (routing_annotation.rr_node_net(output_rr_node) != mux_instance_to_net_map.at(sink_instance_name)) {
+        if (mapped_net != mux_instance_to_net_map.at(sink_instance_name)) {
           disable_timing = true;
         }
       }
diff --git a/openfpga/src/fpga_sdc/analysis_sdc_writer_utils.h b/openfpga/src/fpga_sdc/analysis_sdc_writer_utils.h
index 12b0dc362..3e5582f94 100644
--- a/openfpga/src/fpga_sdc/analysis_sdc_writer_utils.h
+++ b/openfpga/src/fpga_sdc/analysis_sdc_writer_utils.h
@@ -9,6 +9,7 @@
 #include <map>
 #include "module_manager.h"
 #include "rr_graph_obj.h"
+#include "atom_netlist_fwd.h"
 #include "vpr_routing_annotation.h"
 
 /********************************************************************
@@ -27,18 +28,16 @@ void disable_analysis_module_input_pin_net_sinks(std::fstream& fp,
                                                  const std::string& parent_instance_name,
                                                  const ModulePortId& module_input_port,
                                                  const size_t& module_input_pin,
-                                                 const VprRoutingAnnotation& routing_annotation,
-                                                 const RRNodeId& input_rr_node,
-                                                 const std::map<std::string, ClusterNetId> mux_instance_to_net_map);
+                                                 const AtomNetId& mapped_net,
+                                                 const std::map<std::string, AtomNetId> mux_instance_to_net_map);
 
 void disable_analysis_module_input_port_net_sinks(std::fstream& fp,
                                                   const ModuleManager& module_manager,
                                                   const ModuleId& parent_module,
                                                   const std::string& parent_instance_name,
                                                   const ModulePortId& module_input_port,
-                                                  const VprRoutingAnnotation& routing_annotation,
-                                                  const RRNodeId& input_rr_node,
-                                                  const std::map<std::string, ClusterNetId> mux_instance_to_net_map);
+                                                  const AtomNetId& mapped_net,
+                                                  const std::map<std::string, AtomNetId> mux_instance_to_net_map);
 
 void disable_analysis_module_output_pin_net_sinks(std::fstream& fp,
                                                   const ModuleManager& module_manager,
@@ -48,9 +47,8 @@ void disable_analysis_module_output_pin_net_sinks(std::fstream& fp,
                                                   const size_t& child_instance,
                                                   const ModulePortId& child_module_port,
                                                   const size_t& child_module_pin,
-                                                  const VprRoutingAnnotation& routing_annotation,
-                                                  const RRNodeId& output_rr_node,
-                                                  const std::map<std::string, ClusterNetId> mux_instance_to_net_map);
+                                                  const AtomNetId& mapped_net,
+                                                  const std::map<std::string, AtomNetId> mux_instance_to_net_map);
 
 } /* end namespace openfpga */
 

From 037c7e5c43ceb6f98190ebaa18faab8b08dad74c Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 2 Mar 2020 17:58:44 -0700
Subject: [PATCH 245/645] adapt top-level function for  analysis SDC writer

---
 openfpga/src/base/openfpga_context.h          |   4 +-
 .../fpga_sdc/analysis_sdc_routing_writer.h    |   1 +
 openfpga/src/fpga_sdc/analysis_sdc_writer.cpp | 284 ++++++++++++++++++
 openfpga/src/fpga_sdc/analysis_sdc_writer.h   |  28 ++
 4 files changed, 315 insertions(+), 2 deletions(-)
 create mode 100644 openfpga/src/fpga_sdc/analysis_sdc_writer.cpp
 create mode 100644 openfpga/src/fpga_sdc/analysis_sdc_writer.h

diff --git a/openfpga/src/base/openfpga_context.h b/openfpga/src/base/openfpga_context.h
index 20e235a35..d4320915f 100644
--- a/openfpga/src/base/openfpga_context.h
+++ b/openfpga/src/base/openfpga_context.h
@@ -59,8 +59,8 @@ class OpenfpgaContext : public Context  {
     const openfpga::FlowManager& flow_manager() const { return flow_manager_; }
     const openfpga::BitstreamManager& bitstream_manager() const { return bitstream_manager_; }
     const std::vector<openfpga::ConfigBitId>& fabric_bitstream() const { return fabric_bitstream_; }
-    const openfpga::IoLocationMap& io_location_map() { return io_location_map_; }
-    const std::unordered_map<AtomNetId, t_net_power>& net_activity() { return net_activity_; }
+    const openfpga::IoLocationMap& io_location_map() const { return io_location_map_; }
+    const std::unordered_map<AtomNetId, t_net_power>& net_activity() const { return net_activity_; }
   public:  /* Public mutators */
     openfpga::Arch& mutable_arch() { return arch_; }
     openfpga::VprDeviceAnnotation& mutable_vpr_device_annotation() { return vpr_device_annotation_; }
diff --git a/openfpga/src/fpga_sdc/analysis_sdc_routing_writer.h b/openfpga/src/fpga_sdc/analysis_sdc_routing_writer.h
index 7322fc8f6..e50bc73b6 100644
--- a/openfpga/src/fpga_sdc/analysis_sdc_routing_writer.h
+++ b/openfpga/src/fpga_sdc/analysis_sdc_routing_writer.h
@@ -9,6 +9,7 @@
 #include "vpr_context.h"
 #include "module_manager.h"
 #include "device_rr_gsb.h"
+#include "vpr_routing_annotation.h"
 
 /********************************************************************
  * Function declaration
diff --git a/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp b/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp
new file mode 100644
index 000000000..d9699d9b0
--- /dev/null
+++ b/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp
@@ -0,0 +1,284 @@
+/********************************************************************
+ * This file includes functions that are used to output a SDC file
+ * that constrain a FPGA fabric (P&Red netlist) using a benchmark 
+ *******************************************************************/
+#include <ctime>
+#include <fstream>
+#include <iomanip>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_time.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_digest.h"
+#include "openfpga_port.h"
+
+#include "mux_utils.h"
+
+#include "openfpga_naming.h"
+#include "openfpga_atom_netlist_utils.h"
+
+#include "sdc_writer_naming.h"
+#include "sdc_writer_utils.h"
+#include "sdc_memory_utils.h"
+
+#include "analysis_sdc_grid_writer.h"
+#include "analysis_sdc_routing_writer.h"
+#include "analysis_sdc_writer.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Generate SDC constaints for inputs and outputs
+ * We consider the top module in formal verification purpose here
+ * which is easier 
+ *******************************************************************/
+static 
+void print_analysis_sdc_io_delays(std::fstream& fp,
+                                  const AtomContext& atom_ctx,
+                                  const PlacementContext& place_ctx,
+                                  const VprNetlistAnnotation& netlist_annotation,
+                                  const IoLocationMap& io_location_map,
+                                  const ModuleManager& module_manager,
+                                  const ModuleId& top_module,
+                                  const CircuitLibrary& circuit_lib,
+                                  const std::vector<CircuitPortId>& global_ports,
+                                  const float& critical_path_delay) {
+  /* Validate the file stream */
+  valid_file_stream(fp);
+
+  /* Print comments */
+  fp << "##################################################" << std::endl; 
+  fp << "# Create clock                                    " << std::endl;
+  fp << "##################################################" << std::endl; 
+
+  /* Get clock port from the global port */
+  std::vector<BasicPort> operating_clock_ports;
+  for (const CircuitPortId& clock_port : global_ports) {
+    if (CIRCUIT_MODEL_PORT_CLOCK != circuit_lib.port_type(clock_port)) {
+      continue;
+    }
+    /* We only constrain operating clock here! */
+    if (true == circuit_lib.port_is_prog(clock_port)) {
+      continue;
+    }
+   
+    /* Find the module port and Update the operating port list */
+    ModulePortId module_port = module_manager.find_module_port(top_module, circuit_lib.port_prefix(clock_port)); 
+    operating_clock_ports.push_back(module_manager.module_port(top_module, module_port));
+  }
+
+  for (const BasicPort& operating_clock_port : operating_clock_ports) {
+    /* Reach here, it means a clock port and we need print constraints */
+    fp << "create_clock ";
+    fp << generate_sdc_port(operating_clock_port);
+    fp << " -period " << std::setprecision(10) << critical_path_delay;
+    fp << " -waveform {0 " << std::setprecision(10) << critical_path_delay / 2 << "}";
+    fp << std::endl;
+
+    /* Add an empty line as a splitter */
+    fp << std::endl;
+  }
+
+  /* There should be only one operating clock!
+   * TODO: this should be changed when developing multi-clock support!!!
+   */
+  VTR_ASSERT(1 == operating_clock_ports.size());
+
+  /* In this function, we support only 1 type of I/Os */
+  VTR_ASSERT(1 == module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPIO_PORT).size());
+  BasicPort module_io_port = module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPIO_PORT)[0];
+
+  /* Keep tracking which I/Os have been used */
+  std::vector<bool> io_used(module_io_port.get_width(), false);
+
+  /* Find clock ports in benchmark */
+  std::vector<std::string> benchmark_clock_port_names = find_atom_netlist_clock_port_names(atom_ctx.nlist, netlist_annotation);
+
+  /* Print comments */
+  fp << "##################################################" << std::endl; 
+  fp << "# Create input and output delays for used I/Os    " << std::endl;
+  fp << "##################################################" << std::endl; 
+
+  for (const AtomBlockId& atom_blk : atom_ctx.nlist.blocks()) {
+    /* Bypass non-I/O atom blocks ! */
+    if ( (AtomBlockType::INPAD != atom_ctx.nlist.block_type(atom_blk))
+      && (AtomBlockType::OUTPAD != atom_ctx.nlist.block_type(atom_blk)) ) {
+      continue;
+    }
+
+    /* clock net or constant generator should be disabled in timing analysis */
+    if (benchmark_clock_port_names.end() != std::find(benchmark_clock_port_names.begin(), benchmark_clock_port_names.end(), atom_ctx.nlist.block_name(atom_blk))) {
+      continue;
+    }
+
+    /* Find the index of the mapped GPIO in top-level FPGA fabric */
+    size_t io_index = io_location_map.io_index(place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.x,
+                                               place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.y,
+                                               place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.z);
+
+    /* Ensure that IO index is in range */
+    BasicPort module_mapped_io_port = module_io_port; 
+    /* Set the port pin index */ 
+    VTR_ASSERT(io_index < module_mapped_io_port.get_width());
+    module_mapped_io_port.set_width(io_index, io_index);
+
+    /* For input I/O, we set an input delay constraint correlated to the operating clock
+     * For output I/O, we set an output delay constraint correlated to the operating clock
+     */
+    if (AtomBlockType::INPAD == atom_ctx.nlist.block_type(atom_blk)) {
+      print_sdc_set_port_input_delay(fp, module_mapped_io_port,
+                                     operating_clock_ports[0], critical_path_delay);
+    } else {
+      VTR_ASSERT(AtomBlockType::OUTPAD == atom_ctx.nlist.block_type(atom_blk));
+      print_sdc_set_port_output_delay(fp, module_mapped_io_port,
+                                      operating_clock_ports[0], critical_path_delay);
+    }
+
+    /* Mark this I/O has been used/wired */
+    io_used[io_index] = true;
+  }
+
+  /* Add an empty line as a splitter */
+  fp << std::endl;
+
+  /* Print comments */
+  fp << "##################################################" << std::endl; 
+  fp << "# Disable timing for unused I/Os    " << std::endl;
+  fp << "##################################################" << std::endl; 
+
+  /* Wire the unused iopads to a constant */
+  for (size_t io_index = 0; io_index < io_used.size(); ++io_index) {
+    /* Bypass used iopads */
+    if (true == io_used[io_index]) {
+      continue;
+    }
+
+    /* Wire to a contant */
+    BasicPort module_unused_io_port = module_io_port; 
+    /* Set the port pin index */ 
+    module_unused_io_port.set_width(io_index, io_index);
+    print_sdc_disable_port_timing(fp, module_unused_io_port);
+  }
+
+  /* Add an empty line as a splitter */
+  fp << std::endl;
+}
+
+/********************************************************************
+ * Disable the timing for all the global port except the operating clock ports
+ *******************************************************************/
+static 
+void print_analysis_sdc_disable_global_ports(std::fstream& fp,
+                                             const ModuleManager& module_manager,
+                                             const ModuleId& top_module,
+                                             const CircuitLibrary& circuit_lib,
+                                             const std::vector<CircuitPortId>& global_ports) {
+  /* Validate file stream */
+  valid_file_stream(fp);
+
+  /* Print comments */
+  fp << "##################################################" << std::endl; 
+  fp << "# Disable timing for global ports                 " << std::endl;
+  fp << "##################################################" << std::endl; 
+
+  for (const CircuitPortId& global_port : global_ports) {
+    /* Skip operating clock here! */
+    if ( (CIRCUIT_MODEL_PORT_CLOCK == circuit_lib.port_type(global_port)) 
+      && (false == circuit_lib.port_is_prog(global_port)) ) {
+      continue;
+    }
+
+    ModulePortId module_port = module_manager.find_module_port(top_module, circuit_lib.port_prefix(global_port)); 
+    BasicPort port_to_disable = module_manager.module_port(top_module, module_port);
+
+    print_sdc_disable_port_timing(fp, port_to_disable);
+  }
+}
+
+/********************************************************************
+ * Top-level function outputs a SDC file
+ * that constrain a FPGA fabric (P&Red netlist) using a benchmark 
+ *******************************************************************/
+void print_analysis_sdc(const std::string& sdc_dir,
+                        const float& critical_path_delay,
+                        const VprContext& vpr_ctx, 
+                        const OpenfpgaContext& openfpga_ctx,
+                        const std::vector<CircuitPortId>& global_ports,
+                        const bool& compact_routing_hierarchy) {
+  /* Create the file name for Verilog netlist */
+  std::string sdc_fname(sdc_dir + std::string(SDC_ANALYSIS_FILE_NAME));
+
+  std::string timer_message = std::string("Generating SDC for Timing/Power analysis on the mapped FPGA '")
+                            + sdc_fname
+                            + std::string("'");
+
+  /* Start time count */
+  vtr::ScopedStartFinishTimer timer(timer_message);
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(sdc_fname, std::fstream::out | std::fstream::trunc);
+
+  /* Validate file stream */
+  check_file_stream(sdc_fname.c_str(), fp);
+
+  /* Generate the descriptions*/
+  print_sdc_file_header(fp, std::string("Constrain for Timing/Power analysis on the mapped FPGA"));
+
+  /* Find the top_module */
+  ModuleId top_module = openfpga_ctx.module_graph().find_module(generate_fpga_top_module_name());
+  VTR_ASSERT(true == openfpga_ctx.module_graph().valid_module_id(top_module));
+
+  /* Create clock and set I/O ports with input/output delays */
+  print_analysis_sdc_io_delays(fp,
+                               vpr_ctx.atom(), vpr_ctx.placement(),
+                               openfpga_ctx.vpr_netlist_annotation(), openfpga_ctx.io_location_map(),
+                               openfpga_ctx.module_graph(), top_module, 
+                               openfpga_ctx.arch().circuit_lib, global_ports,
+                               critical_path_delay);
+
+  /* Disable the timing for global ports */
+  print_analysis_sdc_disable_global_ports(fp,
+                                          openfpga_ctx.module_graph(), top_module,
+                                          openfpga_ctx.arch().circuit_lib, global_ports);
+
+  /* Disable the timing for configuration cells */ 
+  rec_print_pnr_sdc_disable_configurable_memory_module_output(fp, 
+                                                              openfpga_ctx.module_graph(), top_module, 
+                                                              format_dir_path(openfpga_ctx.module_graph().module_name(top_module)));
+
+
+  /* Disable timing for unused routing resources in connection blocks */
+  print_analysis_sdc_disable_unused_cbs(fp,
+                                        vpr_ctx.atom(), 
+                                        openfpga_ctx.module_graph(),
+                                        vpr_ctx.device().rr_graph,
+                                        openfpga_ctx.vpr_routing_annotation(),
+                                        openfpga_ctx.device_rr_gsb(), 
+                                        compact_routing_hierarchy);
+
+  /* Disable timing for unused routing resources in switch blocks */
+  print_analysis_sdc_disable_unused_sbs(fp,
+                                        vpr_ctx.atom(), 
+                                        openfpga_ctx.module_graph(),
+                                        vpr_ctx.device().rr_graph,
+                                        openfpga_ctx.vpr_routing_annotation(),
+                                        openfpga_ctx.device_rr_gsb(), 
+                                        compact_routing_hierarchy);
+
+  /* Disable timing for unused routing resources in grids (programmable blocks) */
+  print_analysis_sdc_disable_unused_grids(fp,
+                                          vpr_ctx.device().grid,
+                                          openfpga_ctx.vpr_device_annotation(),
+                                          openfpga_ctx.vpr_clustering_annotation(),
+                                          openfpga_ctx.vpr_placement_annotation(),
+                                          openfpga_ctx.module_graph());
+
+  /* Close file handler */
+  fp.close();
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_sdc/analysis_sdc_writer.h b/openfpga/src/fpga_sdc/analysis_sdc_writer.h
new file mode 100644
index 000000000..158dda9f4
--- /dev/null
+++ b/openfpga/src/fpga_sdc/analysis_sdc_writer.h
@@ -0,0 +1,28 @@
+#ifndef ANALYSIS_SDC_WRITER_H
+#define ANALYSIS_SDC_WRITER_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <string>
+#include <vector>
+#include "vpr_context.h"
+#include "openfpga_context.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void print_analysis_sdc(const std::string& sdc_dir,
+                        const float& critical_path_delay,
+                        const VprContext& vpr_ctx, 
+                        const OpenfpgaContext& openfpga_ctx,
+                        const std::vector<CircuitPortId>& global_ports,
+                        const bool& compact_routing_hierarchy);
+
+} /* end namespace openfpga */
+
+#endif

From 3241d8bd3746c4e776c9e268b495242c42e45278 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 2 Mar 2020 19:54:18 -0700
Subject: [PATCH 246/645] put analysis sdc writer online. Minor bug in redudant
 '/' to be fixed

---
 openfpga/src/base/openfpga_sdc.cpp            | 35 ++++++++++++++++
 openfpga/src/base/openfpga_sdc.h              |  3 ++
 openfpga/src/base/openfpga_sdc_command.cpp    | 41 +++++++++++++++++++
 .../src/fpga_sdc/analysis_sdc_grid_writer.cpp |  9 ++--
 openfpga/src/fpga_sdc/analysis_sdc_writer.cpp |  4 +-
 openfpga/src/fpga_sdc/analysis_sdc_writer.h   |  3 +-
 .../fpga_sdc/analysis_sdc_writer_utils.cpp    |  4 +-
 openfpga/test_script/and_k6_frac.openfpga     |  3 ++
 8 files changed, 92 insertions(+), 10 deletions(-)

diff --git a/openfpga/src/base/openfpga_sdc.cpp b/openfpga/src/base/openfpga_sdc.cpp
index eaa2b9941..8b708f133 100644
--- a/openfpga/src/base/openfpga_sdc.cpp
+++ b/openfpga/src/base/openfpga_sdc.cpp
@@ -10,6 +10,7 @@
 
 #include "circuit_library_utils.h"
 #include "pnr_sdc_writer.h"
+#include "analysis_sdc_writer.h"
 #include "openfpga_sdc.h"
 
 /* Include global variables of VPR */
@@ -77,4 +78,38 @@ void write_pnr_sdc(OpenfpgaContext& openfpga_ctx,
   }
 } 
 
+/********************************************************************
+ * A wrapper function to call the analysis SDC generator of FPGA-SDC
+ *******************************************************************/
+void write_analysis_sdc(OpenfpgaContext& openfpga_ctx,
+                        const Command& cmd, const CommandContext& cmd_context) {
+
+  CommandOptionId opt_output_dir = cmd.option("file");
+
+  /* This is an intermediate data structure which is designed to modularize the FPGA-SDC
+   * Keep it independent from any other outside data structures
+   */
+  std::string sdc_dir_path = format_dir_path(cmd_context.option_value(cmd, opt_output_dir));
+
+  /* Create directories */
+  create_dir_path(sdc_dir_path.c_str());
+
+  AnalysisSdcOption options(sdc_dir_path);
+  options.set_generate_sdc_analysis(true);
+
+  /* Collect global ports from the circuit library:
+   * TODO: should we place this in the OpenFPGA context?
+   */
+  std::vector<CircuitPortId> global_ports = find_circuit_library_global_ports(openfpga_ctx.arch().circuit_lib);
+
+  if (true == options.generate_sdc_analysis()) {
+    print_analysis_sdc(options,
+                       1./openfpga_ctx.arch().sim_setting.operating_clock_frequency(),
+                       g_vpr_ctx, 
+                       openfpga_ctx,
+                       global_ports,
+                       openfpga_ctx.flow_manager().compress_routing());
+  }
+}
+
 } /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_sdc.h b/openfpga/src/base/openfpga_sdc.h
index 4e48964f3..110a8cd72 100644
--- a/openfpga/src/base/openfpga_sdc.h
+++ b/openfpga/src/base/openfpga_sdc.h
@@ -18,6 +18,9 @@ namespace openfpga {
 void write_pnr_sdc(OpenfpgaContext& openfpga_ctx,
                    const Command& cmd, const CommandContext& cmd_context); 
 
+void write_analysis_sdc(OpenfpgaContext& openfpga_ctx,
+                        const Command& cmd, const CommandContext& cmd_context);
+
 } /* end namespace openfpga */
 
 #endif
diff --git a/openfpga/src/base/openfpga_sdc_command.cpp b/openfpga/src/base/openfpga_sdc_command.cpp
index 799fad4e6..91d65aa0a 100644
--- a/openfpga/src/base/openfpga_sdc_command.cpp
+++ b/openfpga/src/base/openfpga_sdc_command.cpp
@@ -61,6 +61,36 @@ ShellCommandId add_openfpga_write_pnr_sdc_command(openfpga::Shell<OpenfpgaContex
   return shell_cmd_id;
 }
 
+/********************************************************************
+ * - Add a command to Shell environment: generate PnR SDC 
+ * - Add associated options 
+ * - Add command dependency
+ *******************************************************************/
+static 
+ShellCommandId add_openfpga_write_analysis_sdc_command(openfpga::Shell<OpenfpgaContext>& shell,
+                                                       const ShellCommandClassId& cmd_class_id,
+                                                       const std::vector<ShellCommandId>& dependent_cmds) {
+  Command shell_cmd("write_analysis_sdc");
+
+  /* Add an option '--file' in short '-f'*/
+  CommandOptionId output_opt = shell_cmd.add_option("file", true, "Specify the output directory for SDC files");
+  shell_cmd.set_option_short_name(output_opt, "f");
+  shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING);
+
+  /* Add an option '--verbose' */
+  shell_cmd.add_option("verbose", false, "Enable verbose output");
+  
+  /* Add command 'write_fabric_verilog' to the Shell */
+  ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "generate SDC files for timing analysis a PnRed FPGA fabric mapped by a benchmark");
+  shell.set_command_class(shell_cmd_id, cmd_class_id);
+  shell.set_command_execute_function(shell_cmd_id, write_analysis_sdc);
+
+  /* Add command dependency to the Shell */
+  shell.set_command_dependency(shell_cmd_id, dependent_cmds);
+
+  return shell_cmd_id;
+}
+
 void add_openfpga_sdc_commands(openfpga::Shell<OpenfpgaContext>& shell) {
   /* Get the unique id of 'build_fabric' command which is to be used in creating the dependency graph */
   const ShellCommandId& build_fabric_id = shell.command(std::string("build_fabric"));
@@ -77,6 +107,17 @@ void add_openfpga_sdc_commands(openfpga::Shell<OpenfpgaContext>& shell) {
   add_openfpga_write_pnr_sdc_command(shell,
                                      openfpga_sdc_cmd_class,
                                      pnr_sdc_cmd_dependency);
+
+  /******************************** 
+   * Command 'write_analysis_sdc' 
+   */
+  /* The 'write_analysis_sdc' command should NOT be executed before 'build_fabric' */
+  std::vector<ShellCommandId> analysis_sdc_cmd_dependency;
+  analysis_sdc_cmd_dependency.push_back(build_fabric_id);
+  add_openfpga_write_analysis_sdc_command(shell,
+                                          openfpga_sdc_cmd_class,
+                                          analysis_sdc_cmd_dependency);
+
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/fpga_sdc/analysis_sdc_grid_writer.cpp b/openfpga/src/fpga_sdc/analysis_sdc_grid_writer.cpp
index 19d501a79..d868df992 100644
--- a/openfpga/src/fpga_sdc/analysis_sdc_grid_writer.cpp
+++ b/openfpga/src/fpga_sdc/analysis_sdc_grid_writer.cpp
@@ -49,7 +49,7 @@ void rec_print_analysis_sdc_disable_unused_pb_graph_nodes(std::fstream& fp,
    */
   fp << "set_disable_timing ";
   fp << hierarchy_name; 
-  fp << "/*";
+  fp << "*";
   fp << std::endl;
 
   /* Return if this is the primitive pb_type */
@@ -74,7 +74,7 @@ void rec_print_analysis_sdc_disable_unused_pb_graph_nodes(std::fstream& fp,
       /* Must have a valid instance name!!! */
       VTR_ASSERT(false == child_instance_name.empty()); 
 
-      std::string updated_hierarchy_name = hierarchy_name + std::string("/") + child_instance_name + std::string("/");
+      std::string updated_hierarchy_name = hierarchy_name + child_instance_name + std::string("/");
 
       rec_print_analysis_sdc_disable_unused_pb_graph_nodes(fp, device_annotation, module_manager, child_module, hierarchy_name, 
                                                            &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ichild][inst])); 
@@ -114,7 +114,6 @@ void disable_pb_graph_node_unused_pin(std::fstream& fp,
 
   fp << "set_disable_timing ";
   fp << hierarchy_name; 
-  fp << "/";
   fp << generate_sdc_port(port_to_disable);
   fp << std::endl;
 }
@@ -407,7 +406,7 @@ void rec_print_analysis_sdc_disable_pb_graph_node_unused_resources(std::fstream&
       /* Must have a valid instance name!!! */
       VTR_ASSERT(false == child_instance_name.empty()); 
 
-      std::string updated_hierarchy_name = hierarchy_name + std::string("/") + child_instance_name + std::string("/");
+      std::string updated_hierarchy_name = hierarchy_name + child_instance_name + std::string("/");
 
       rec_print_analysis_sdc_disable_pb_graph_node_unused_resources(fp, device_annotation,
                                                                     module_manager, child_module, hierarchy_name, 
@@ -591,7 +590,7 @@ void print_analysis_sdc_disable_unused_grids(std::fstream& fp,
   for (size_t ix = 1; ix < grids.width() - 1; ++ix) {
     for (size_t iy = 1; iy < grids.height() - 1; ++iy) {
       /* We should not meet any I/O grid */
-      VTR_ASSERT(false != is_io_type(grids[ix][iy].type));
+      VTR_ASSERT(false == is_io_type(grids[ix][iy].type));
 
       print_analysis_sdc_disable_unused_grid(fp, vtr::Point<size_t>(ix, iy),
                                              grids, device_annotation, cluster_annotation, place_annotation,
diff --git a/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp b/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp
index d9699d9b0..de9dfb55d 100644
--- a/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp
+++ b/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp
@@ -202,14 +202,14 @@ void print_analysis_sdc_disable_global_ports(std::fstream& fp,
  * Top-level function outputs a SDC file
  * that constrain a FPGA fabric (P&Red netlist) using a benchmark 
  *******************************************************************/
-void print_analysis_sdc(const std::string& sdc_dir,
+void print_analysis_sdc(const AnalysisSdcOption& option,
                         const float& critical_path_delay,
                         const VprContext& vpr_ctx, 
                         const OpenfpgaContext& openfpga_ctx,
                         const std::vector<CircuitPortId>& global_ports,
                         const bool& compact_routing_hierarchy) {
   /* Create the file name for Verilog netlist */
-  std::string sdc_fname(sdc_dir + std::string(SDC_ANALYSIS_FILE_NAME));
+  std::string sdc_fname(option.sdc_dir() + std::string(SDC_ANALYSIS_FILE_NAME));
 
   std::string timer_message = std::string("Generating SDC for Timing/Power analysis on the mapped FPGA '")
                             + sdc_fname
diff --git a/openfpga/src/fpga_sdc/analysis_sdc_writer.h b/openfpga/src/fpga_sdc/analysis_sdc_writer.h
index 158dda9f4..c3d08794a 100644
--- a/openfpga/src/fpga_sdc/analysis_sdc_writer.h
+++ b/openfpga/src/fpga_sdc/analysis_sdc_writer.h
@@ -8,6 +8,7 @@
 #include <vector>
 #include "vpr_context.h"
 #include "openfpga_context.h"
+#include "analysis_sdc_option.h"
 
 /********************************************************************
  * Function declaration
@@ -16,7 +17,7 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-void print_analysis_sdc(const std::string& sdc_dir,
+void print_analysis_sdc(const AnalysisSdcOption& option,
                         const float& critical_path_delay,
                         const VprContext& vpr_ctx, 
                         const OpenfpgaContext& openfpga_ctx,
diff --git a/openfpga/src/fpga_sdc/analysis_sdc_writer_utils.cpp b/openfpga/src/fpga_sdc/analysis_sdc_writer_utils.cpp
index 8ac184b61..974940eb9 100644
--- a/openfpga/src/fpga_sdc/analysis_sdc_writer_utils.cpp
+++ b/openfpga/src/fpga_sdc/analysis_sdc_writer_utils.cpp
@@ -100,7 +100,7 @@ void disable_analysis_module_input_pin_net_sinks(std::fstream& fp,
                         module_manager.net_sink_pins(parent_module, module_net)[sink_id]);
     /* Get the input id that is used! Disable the unused inputs! */
     fp << "set_disable_timing ";
-    fp << parent_instance_name << "/";
+    fp << parent_instance_name;
     fp << sink_instance_name << "/";
     fp << generate_sdc_port(sink_port);
     fp << std::endl;
@@ -223,7 +223,7 @@ void disable_analysis_module_output_pin_net_sinks(std::fstream& fp,
                         module_manager.net_sink_pins(parent_module, module_net)[sink_id]);
     /* Get the input id that is used! Disable the unused inputs! */
     fp << "set_disable_timing ";
-    fp << parent_instance_name << "/";
+    fp << parent_instance_name;
     fp << sink_instance_name << "/";
     fp << generate_sdc_port(sink_port);
     fp << std::endl;
diff --git a/openfpga/test_script/and_k6_frac.openfpga b/openfpga/test_script/and_k6_frac.openfpga
index 1018887f1..4133dcea5 100644
--- a/openfpga/test_script/and_k6_frac.openfpga
+++ b/openfpga/test_script/and_k6_frac.openfpga
@@ -52,5 +52,8 @@ write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_
 #  - Turn on every options here 
 write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
 
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
+
 # Finish and exit OpenFPGA
 exit

From 7fcd27e00076e4500c1eeceb8a70d4ead4c0f7ca Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 3 Mar 2020 12:29:58 -0700
Subject: [PATCH 247/645] now we give explicit instance name to each
 interconnect inside grid. Thus resolve the problem in sdc writer

---
 openfpga/src/base/openfpga_naming.cpp            | 13 +++++++++++++
 openfpga/src/base/openfpga_naming.h              |  3 +++
 openfpga/src/fabric/build_grid_modules.cpp       |  6 ++++++
 .../src/fpga_sdc/analysis_sdc_grid_writer.cpp    | 16 ++++++++++++++--
 .../src/fpga_sdc/analysis_sdc_writer_utils.cpp   |  4 ++++
 .../src/fpga_verilog/verilog_module_writer.cpp   |  4 +++-
 6 files changed, 43 insertions(+), 3 deletions(-)

diff --git a/openfpga/src/base/openfpga_naming.cpp b/openfpga/src/base/openfpga_naming.cpp
index fab27a12b..9bfad01a2 100644
--- a/openfpga/src/base/openfpga_naming.cpp
+++ b/openfpga/src/base/openfpga_naming.cpp
@@ -17,6 +17,19 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
+/************************************************
+ * A generic function to generate the instance name
+ * in the following format:
+ * <instance_name>_<id>_
+ * This is mainly used by module manager to give a default
+ * name for each instance when outputting the module
+ * in Verilog/SPICE format
+ ***********************************************/
+std::string generate_instance_name(const std::string& instance_name,
+                                   const size_t& instance_id) {
+  return instance_name + std::string("_") + std::to_string(instance_id) + std::string("_");
+}
+
 /************************************************
  * Generate the node name for a multiplexing structure 
  * Case 1 : If there is an intermediate buffer followed by,
diff --git a/openfpga/src/base/openfpga_naming.h b/openfpga/src/base/openfpga_naming.h
index 13d4c56c0..e4f1ee8f8 100644
--- a/openfpga/src/base/openfpga_naming.h
+++ b/openfpga/src/base/openfpga_naming.h
@@ -23,6 +23,9 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
+std::string generate_instance_name(const std::string& instance_name,
+                                   const size_t& instance_id);
+
 std::string generate_mux_node_name(const size_t& node_level, 
                                    const bool& add_buffer_postfix);
 
diff --git a/openfpga/src/fabric/build_grid_modules.cpp b/openfpga/src/fabric/build_grid_modules.cpp
index a5c346025..2ee5527e7 100644
--- a/openfpga/src/fabric/build_grid_modules.cpp
+++ b/openfpga/src/fabric/build_grid_modules.cpp
@@ -428,6 +428,12 @@ void add_module_pb_graph_pin_interc(ModuleManager& module_manager,
     size_t wire_instance = module_manager.num_instance(pb_module, wire_module);
     module_manager.add_child_module(pb_module, wire_module);
 
+    /* Give an instance name: this name should be consistent with the block name given in SDC generator,
+     * If you want to bind the SDC generation to modules
+     */
+    std::string wire_instance_name = generate_instance_name(module_manager.module_name(wire_module), wire_instance);
+    module_manager.set_child_instance_name(pb_module, wire_module, wire_instance, wire_instance_name);
+
     /* Ensure input and output ports of the wire model has only 1 pin respectively */
     VTR_ASSERT(1 == circuit_lib.port_size(interc_model_inputs[0]));
     VTR_ASSERT(1 == circuit_lib.port_size(interc_model_outputs[0]));
diff --git a/openfpga/src/fpga_sdc/analysis_sdc_grid_writer.cpp b/openfpga/src/fpga_sdc/analysis_sdc_grid_writer.cpp
index d868df992..d9a85280b 100644
--- a/openfpga/src/fpga_sdc/analysis_sdc_grid_writer.cpp
+++ b/openfpga/src/fpga_sdc/analysis_sdc_grid_writer.cpp
@@ -47,6 +47,10 @@ void rec_print_analysis_sdc_disable_unused_pb_graph_nodes(std::fstream& fp,
   /* Disable all the ports of current module (parent_module)!
    * Hierarchy name already includes the instance name of parent_module 
    */
+  fp << "#######################################" << std::endl; 
+  fp << "# Disable all the ports for pb_graph_node " << physical_pb_graph_node->pb_type->name << "[" << physical_pb_graph_node->placement_index << "]" << std::endl;
+  fp << "#######################################" << std::endl; 
+
   fp << "set_disable_timing ";
   fp << hierarchy_name; 
   fp << "*";
@@ -76,7 +80,7 @@ void rec_print_analysis_sdc_disable_unused_pb_graph_nodes(std::fstream& fp,
 
       std::string updated_hierarchy_name = hierarchy_name + child_instance_name + std::string("/");
 
-      rec_print_analysis_sdc_disable_unused_pb_graph_nodes(fp, device_annotation, module_manager, child_module, hierarchy_name, 
+      rec_print_analysis_sdc_disable_unused_pb_graph_nodes(fp, device_annotation, module_manager, child_module, updated_hierarchy_name, 
                                                            &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ichild][inst])); 
     }
   }
@@ -135,6 +139,10 @@ void disable_pb_graph_node_unused_pins(std::fstream& fp,
   const PhysicalPbId& pb_id = physical_pb.find_pb(physical_pb_graph_node);
   VTR_ASSERT(true == physical_pb.valid_pb_id(pb_id));
 
+  fp << "#######################################" << std::endl; 
+  fp << "# Disable unused pins for pb_graph_node " << physical_pb_graph_node->pb_type->name << "[" << physical_pb_graph_node->placement_index << "]" << std::endl;
+  fp << "#######################################" << std::endl; 
+
   /* Disable unused input pins */
   for (int iport = 0; iport < physical_pb_graph_node->num_input_ports; ++iport) {
     for (int ipin = 0; ipin < physical_pb_graph_node->num_input_pins[iport]; ++ipin) {
@@ -180,6 +188,10 @@ void disable_pb_graph_node_unused_mux_inputs(std::fstream& fp,
                                              t_pb_graph_node* physical_pb_graph_node,
                                              const PhysicalPb& physical_pb) {
 
+  fp << "#######################################" << std::endl; 
+  fp << "# Disable unused mux_inputs for pb_graph_node " << physical_pb_graph_node->pb_type->name << "[" << physical_pb_graph_node->placement_index << "]" << std::endl;
+  fp << "#######################################" << std::endl; 
+
   t_pb_type* physical_pb_type = physical_pb_graph_node->pb_type;
 
   t_mode* physical_mode = device_annotation.physical_mode(physical_pb_type);
@@ -409,7 +421,7 @@ void rec_print_analysis_sdc_disable_pb_graph_node_unused_resources(std::fstream&
       std::string updated_hierarchy_name = hierarchy_name + child_instance_name + std::string("/");
 
       rec_print_analysis_sdc_disable_pb_graph_node_unused_resources(fp, device_annotation,
-                                                                    module_manager, child_module, hierarchy_name, 
+                                                                    module_manager, child_module, updated_hierarchy_name, 
                                                                     &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ichild][inst]), 
                                                                     physical_pb); 
     }
diff --git a/openfpga/src/fpga_sdc/analysis_sdc_writer_utils.cpp b/openfpga/src/fpga_sdc/analysis_sdc_writer_utils.cpp
index 974940eb9..f761cafea 100644
--- a/openfpga/src/fpga_sdc/analysis_sdc_writer_utils.cpp
+++ b/openfpga/src/fpga_sdc/analysis_sdc_writer_utils.cpp
@@ -98,6 +98,8 @@ void disable_analysis_module_input_pin_net_sinks(std::fstream& fp,
     BasicPort sink_port = module_manager.module_port(sink_module, module_manager.net_sink_ports(parent_module, module_net)[sink_id]);
     sink_port.set_width(module_manager.net_sink_pins(parent_module, module_net)[sink_id],
                         module_manager.net_sink_pins(parent_module, module_net)[sink_id]);
+
+    VTR_ASSERT(!sink_instance_name.empty());
     /* Get the input id that is used! Disable the unused inputs! */
     fp << "set_disable_timing ";
     fp << parent_instance_name;
@@ -221,6 +223,8 @@ void disable_analysis_module_output_pin_net_sinks(std::fstream& fp,
     BasicPort sink_port = module_manager.module_port(sink_module, module_manager.net_sink_ports(parent_module, module_net)[sink_id]);
     sink_port.set_width(module_manager.net_sink_pins(parent_module, module_net)[sink_id],
                         module_manager.net_sink_pins(parent_module, module_net)[sink_id]);
+
+    VTR_ASSERT(!sink_instance_name.empty());
     /* Get the input id that is used! Disable the unused inputs! */
     fp << "set_disable_timing ";
     fp << parent_instance_name;
diff --git a/openfpga/src/fpga_verilog/verilog_module_writer.cpp b/openfpga/src/fpga_verilog/verilog_module_writer.cpp
index 15a5bc28d..59f863701 100644
--- a/openfpga/src/fpga_verilog/verilog_module_writer.cpp
+++ b/openfpga/src/fpga_verilog/verilog_module_writer.cpp
@@ -16,6 +16,8 @@
 #include "openfpga_port.h"
 #include "openfpga_digest.h"
 
+#include "openfpga_naming.h"
+
 #include "module_manager_utils.h"
 #include "verilog_port_types.h"
 #include "verilog_writer_utils.h"
@@ -371,7 +373,7 @@ void write_verilog_instance_to_file(std::fstream& fp,
    * if not, we use a default name <name>_<num_instance_in_parent_module> 
    */
   if (true == module_manager.instance_name(parent_module, child_module, instance_id).empty()) {
-    fp << module_manager.module_name(child_module) << "_" << instance_id << "_" << " (" << std::endl;
+    fp << generate_instance_name(module_manager.module_name(child_module), instance_id) << " (" << std::endl;
   } else {
     fp << module_manager.instance_name(parent_module, child_module, instance_id) << " (" << std::endl;
   }

From aed3b01800a1ae185f8d6105d43013077a3d169e Mon Sep 17 00:00:00 2001
From: AurelienUoU <u1235811@lnissrv4.eng.utah.edu>
Date: Wed, 4 Mar 2020 09:09:06 -0700
Subject: [PATCH 248/645] Directlist extension bug fix

---
 .../module_builder/build_top_module_directs.cpp    | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_directs.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_directs.cpp
index 6179e4d4c..06d3339d1 100644
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_directs.cpp
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_directs.cpp
@@ -285,9 +285,9 @@ vtr::Point<size_t> find_intra_direct_destination_coordinate(const vtr::Point<siz
      *  +------+  
      *  | Grid | ny
      *  +------+
+     *     ^     .
      *     |     .
      *     |     .
-     *     v     .
      *  +------+
      *  | Grid | 1
      *  +------+
@@ -301,14 +301,14 @@ vtr::Point<size_t> find_intra_direct_destination_coordinate(const vtr::Point<siz
      *  +------+  
      *  | Grid | ny
      *  +------+
-     *     ^     .
      *     |     .
      *     |     .
+     *     v     .
      *  +------+
      *  | Grid | 1
      *  +------+
      */
-    if (NEGATIVE_DIR == direct.y_dir) {
+    if (POSITIVE_DIR == direct.y_dir) {
       std::reverse(second_search_space.begin(), second_search_space.end());
     }
   }
@@ -361,7 +361,7 @@ vtr::Point<size_t> find_intra_direct_destination_coordinate(const vtr::Point<siz
      *
      *     1      ...     nx
      *  +------+       +------+
-     *  | Grid |------>| Grid |
+     *  | Grid |<------| Grid |
      *  +------+       +------+
      */
     for (size_t ix = 1 ; ix < device_size.x() - 1; ++ix) {
@@ -373,10 +373,10 @@ vtr::Point<size_t> find_intra_direct_destination_coordinate(const vtr::Point<siz
      *
      *     1      ...     nx
      *  +------+       +------+
-     *  | Grid |<------| Grid |
+     *  | Grid |------>| Grid |
      *  +------+       +------+
      */
-    if (NEGATIVE_DIR == direct.x_dir) {
+    if (POSITIVE_DIR == direct.x_dir) {
       std::reverse(second_search_space.begin(), second_search_space.end());
     }
   }
@@ -472,7 +472,7 @@ void add_top_module_nets_inter_clb2clb_direct_connections(ModuleManager& module_
           next_col_src_grid_coords.push_back(vtr::Point<size_t>(ix, iy));
         }
         /* For positive y- direction, we should start from y = 1 */
-        if (POSITIVE_DIR == direct.y_dir) {
+        if (NEGATIVE_DIR == direct.y_dir) {
           std::reverse(next_col_src_grid_coords.begin(), next_col_src_grid_coords.end());
         }
         vtr::Point<size_t> src_clb_coord = find_grid_coordinate_given_type(device_size, grids, next_col_src_grid_coords, direct.from_clb_type); 

From 524798799c0dd41faf01507fb4843a6a8a3354ac Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 4 Mar 2020 11:21:34 -0700
Subject: [PATCH 249/645] start adapting tileable rr_graph builder. Bring
 channel node detail data structure online

---
 .../tileable_rr_graph/chan_node_details.cpp   | 292 ++++++++++++++++++
 vpr/src/tileable_rr_graph/chan_node_details.h |  80 +++++
 2 files changed, 372 insertions(+)
 create mode 100644 vpr/src/tileable_rr_graph/chan_node_details.cpp
 create mode 100644 vpr/src/tileable_rr_graph/chan_node_details.h

diff --git a/vpr/src/tileable_rr_graph/chan_node_details.cpp b/vpr/src/tileable_rr_graph/chan_node_details.cpp
new file mode 100644
index 000000000..b9a2cac07
--- /dev/null
+++ b/vpr/src/tileable_rr_graph/chan_node_details.cpp
@@ -0,0 +1,292 @@
+/************************************************************************
+ *  This file contains member functions for class ChanNodeDetails
+ ***********************************************************************/
+#include <cassert>
+#include <algorithm>
+#include "chan_node_details.h"
+
+/************************************************************************
+ *  Constructors 
+ ***********************************************************************/
+ChanNodeDetails::ChanNodeDetails(const ChanNodeDetails& src) {
+  /* duplicate */
+  size_t chan_width = src.get_chan_width();
+  this->reserve(chan_width); 
+  for (size_t itrack = 0; itrack < chan_width; ++itrack) {
+    track_node_ids_.push_back(src.get_track_node_id(itrack));
+    track_direction_.push_back(src.get_track_direction(itrack));
+    seg_ids_.push_back(src.get_track_segment_id(itrack));
+    seg_length_.push_back(src.get_track_segment_length(itrack));
+    track_start_.push_back(src.is_track_start(itrack));
+    track_end_.push_back(src.is_track_end(itrack));
+  }
+}
+
+ChanNodeDetails::ChanNodeDetails() {
+  this->clear();
+}
+
+/************************************************************************
+ *  Accessors
+ ***********************************************************************/
+size_t ChanNodeDetails::get_chan_width() const {
+  assert(validate_chan_width());
+  return track_node_ids_.size();
+}
+
+size_t ChanNodeDetails::get_track_node_id(const size_t& track_id) const {
+  assert(validate_track_id(track_id));
+  return track_node_ids_[track_id];
+}
+
+/* Return a copy of vector */
+std::vector<size_t> ChanNodeDetails::get_track_node_ids() const {
+  std::vector<size_t> copy;
+  for (size_t inode = 0; inode < get_chan_width(); ++inode) {
+    copy.push_back(track_node_ids_[inode]);
+  } 
+  return copy;
+}
+
+e_direction ChanNodeDetails::get_track_direction(const size_t& track_id) const {
+  assert(validate_track_id(track_id));
+  return track_direction_[track_id];
+}
+
+size_t ChanNodeDetails::get_track_segment_length(const size_t& track_id) const {
+  assert(validate_track_id(track_id));
+  return seg_length_[track_id];
+}
+
+size_t ChanNodeDetails::get_track_segment_id(const size_t& track_id) const {
+  assert(validate_track_id(track_id));
+  return seg_ids_[track_id];
+}
+
+bool   ChanNodeDetails::is_track_start(const size_t& track_id) const {
+  assert(validate_track_id(track_id));
+  return track_start_[track_id];
+}
+
+bool   ChanNodeDetails::is_track_end(const size_t& track_id) const {
+  assert(validate_track_id(track_id));
+  return track_end_[track_id];
+}
+
+/* Track_id is the starting point of group (whose is_start should be true) 
+ * This function will try to find the track_ids with the same directionality as track_id and seg_length
+ * A group size is the number of such nodes between the starting points (include the 1st starting point) 
+ */
+std::vector<size_t> ChanNodeDetails::get_seg_group(const size_t& track_id) const {
+  assert(validate_chan_width());
+  assert(validate_track_id(track_id));
+  assert(is_track_start(track_id));
+  
+  std::vector<size_t> group;
+  /* Make sure a clean start */
+  group.clear();
+
+  for (size_t itrack = track_id; itrack < get_chan_width(); ++itrack) {
+    if ( (get_track_direction(itrack) != get_track_direction(track_id) )
+      || (get_track_segment_id(itrack) != get_track_segment_id(track_id)) ) {
+      /* Bypass any nodes in different direction and segment information*/
+      continue;
+    }
+    if ( (false == is_track_start(itrack)) 
+      || ( (true == is_track_start(itrack)) && (itrack == track_id)) ) {
+      group.push_back(itrack);
+      continue;
+    }
+    /* Stop if this another starting point */
+    if (true == is_track_start(itrack)) {
+      break;
+    }
+  }  
+  return group;
+}
+
+/* Get a list of track_ids with the given list of track indices */
+std::vector<size_t> ChanNodeDetails::get_seg_group_node_id(const std::vector<size_t>& seg_group) const {
+  std::vector<size_t> group;
+  /* Make sure a clean start */
+  group.clear();
+
+  for (size_t id = 0; id < seg_group.size(); ++id) {
+    assert(validate_track_id(seg_group[id]));
+    group.push_back(get_track_node_id(seg_group[id]));
+  }
+
+  return group;
+}
+
+/* Get the number of tracks that starts in this routing channel */
+size_t ChanNodeDetails::get_num_starting_tracks(const e_direction& track_direction) const {
+  size_t counter = 0;
+  for (size_t itrack = 0; itrack < get_chan_width(); ++itrack) {
+    /* Bypass unmatched track_direction */
+    if (track_direction != get_track_direction(itrack)) {
+      continue;
+    }
+    if (false == is_track_start(itrack)) {
+      continue;
+    } 
+    counter++;
+  }  
+  return counter;
+}
+
+/* Get the number of tracks that ends in this routing channel */
+size_t ChanNodeDetails::get_num_ending_tracks(const e_direction& track_direction) const {
+  size_t counter = 0;
+  for (size_t itrack = 0; itrack < get_chan_width(); ++itrack) {
+    /* Bypass unmatched track_direction */
+    if (track_direction != get_track_direction(itrack)) {
+      continue;
+    }
+    if (false == is_track_end(itrack)) {
+      continue;
+    } 
+    counter++;
+  }  
+  return counter;
+}
+
+
+/************************************************************************
+ *  Mutators
+ ***********************************************************************/
+/* Reserve the capacitcy of vectors */
+void ChanNodeDetails::reserve(const size_t& chan_width) {
+  track_node_ids_.reserve(chan_width);
+  track_direction_.reserve(chan_width);
+  seg_length_.reserve(chan_width);
+  seg_ids_.reserve(chan_width);
+  track_start_.reserve(chan_width);
+  track_end_.reserve(chan_width);
+}
+
+/* Add a track to the channel */
+void ChanNodeDetails::add_track(const size_t& track_node_id, const e_direction& track_direction,
+                                const size_t& seg_id, const size_t& seg_length,
+                                const size_t& is_start, const size_t& is_end) {
+  track_node_ids_.push_back(track_node_id);
+  track_direction_.push_back(track_direction);
+  seg_ids_.push_back(seg_id);
+  seg_length_.push_back(seg_length);
+  track_start_.push_back(is_start);
+  track_end_.push_back(is_end);
+}
+
+/* Update the node_id of a given track */
+void ChanNodeDetails::set_track_node_id(const size_t& track_index, const size_t& track_node_id) {
+  assert(validate_track_id(track_index));
+  track_node_ids_[track_index] = track_node_id; 
+}
+
+/* Update the node_ids from a vector */
+void ChanNodeDetails::set_track_node_ids(const std::vector<size_t>& track_node_ids) {
+  /* the size of vector should match chan_width */
+  assert ( get_chan_width() == track_node_ids.size() );
+  for (size_t inode = 0; inode < track_node_ids.size(); ++inode) {
+    track_node_ids_[inode] = track_node_ids[inode]; 
+  }
+}
+
+/* Set tracks with a given direction to start */
+void ChanNodeDetails::set_tracks_start(const e_direction& track_direction) {
+  for (size_t inode = 0; inode < get_chan_width(); ++inode) {
+    /* Bypass non-match tracks */
+    if (track_direction != get_track_direction(inode)) {
+      continue; /* Pass condition*/
+    }
+    track_start_[inode] = true;
+  }
+}
+
+/* Set tracks with a given direction to end */
+void ChanNodeDetails::set_tracks_end(const e_direction& track_direction) {
+  for (size_t inode = 0; inode < get_chan_width(); ++inode) {
+    /* Bypass non-match tracks */
+    if (track_direction != get_track_direction(inode)) {
+      continue; /* Pass condition*/
+    }
+    track_end_[inode] = true;
+  }
+}
+
+/* rotate the track_node_id by an offset */
+void ChanNodeDetails::rotate_track_node_id(const size_t& offset, const e_direction& track_direction, const bool& counter_rotate) {
+  /* Direct return if offset = 0*/
+  if (0 == offset) {
+    return;
+  }
+ 
+  /* Rotate the node_ids by groups
+   * A group begins from a track_start and ends before another track_start  
+   */
+  assert(validate_chan_width());
+  for (size_t itrack = 0; itrack < get_chan_width(); ++itrack) { 
+    /* Bypass non-start segment */
+    if (false == is_track_start(itrack) ) {
+      continue;
+    }
+    /* Bypass segments do not match track_direction */
+    if (track_direction != get_track_direction(itrack) ) {
+      continue;
+    }
+    /* Find the group nodes */
+    std::vector<size_t> track_group = get_seg_group(itrack);
+    /* Build a vector of the node ids of the tracks */
+    std::vector<size_t> track_group_node_id = get_seg_group_node_id(track_group);
+    /* adapt offset to the range of track_group_node_id */
+    size_t actual_offset = offset % track_group_node_id.size();
+    /* Rotate or Counter rotate */
+    if (true == counter_rotate) {
+      std::rotate(track_group_node_id.rbegin(), track_group_node_id.rbegin() + actual_offset, track_group_node_id.rend());
+    } else {
+      std::rotate(track_group_node_id.begin(), track_group_node_id.begin() + actual_offset, track_group_node_id.end());
+    }
+    /* Update the node_ids */
+    for (size_t inode = 0; inode < track_group.size(); ++inode) {
+      track_node_ids_[track_group[inode]] = track_group_node_id[inode];
+    }
+  }
+  return;
+}
+
+void ChanNodeDetails::clear() {
+  track_node_ids_.clear();
+  track_direction_.clear();
+  seg_ids_.clear();
+  seg_length_.clear();
+  track_start_.clear();
+  track_end_.clear();
+}
+
+/************************************************************************
+ *  Validators 
+ ***********************************************************************/
+bool ChanNodeDetails::validate_chan_width() const {
+  size_t chan_width = track_node_ids_.size();
+  if ( (chan_width == track_direction_.size())
+     &&(chan_width == seg_ids_.size())
+     &&(chan_width == seg_length_.size())
+     &&(chan_width == track_start_.size())
+     &&(chan_width == track_end_.size()) ) {
+    return true;
+  }
+  return false;
+}
+
+bool ChanNodeDetails::validate_track_id(const size_t& track_id) const {
+  if ( (track_id < track_node_ids_.size()) 
+    && (track_id < track_direction_.size()) 
+    && (track_id < seg_ids_.size()) 
+    && (track_id < seg_length_.size()) 
+    && (track_id < track_start_.size()) 
+    && (track_id < track_end_.size()) ) {
+    return true;
+  } 
+  return false;
+}
+
diff --git a/vpr/src/tileable_rr_graph/chan_node_details.h b/vpr/src/tileable_rr_graph/chan_node_details.h
new file mode 100644
index 000000000..abb595965
--- /dev/null
+++ b/vpr/src/tileable_rr_graph/chan_node_details.h
@@ -0,0 +1,80 @@
+/************************************************************************
+ *  This file contains a class to model the details of routing node
+ *  in a channel:
+ *  1. segment information: length, frequency etc.
+ *  2. starting point of segment
+ *  3. ending point of segment
+ *  4. potentail track_id(ptc_num) of each segment
+ ***********************************************************************/
+
+/* IMPORTANT:
+ * The following preprocessing flags are added to 
+ * avoid compilation error when this headers are included in more than 1 times 
+ */
+#ifndef CHAN_NODE_DETAILS_H
+#define CHAN_NODE_DETAILS_H
+
+/*
+ * Notes in include header files in a head file 
+ * Only include the neccessary header files 
+ * that is required by the data types in the function/class declarations!
+ */
+/* Header files should be included in a sequence */
+/* Standard header files required go first */
+#include <vector>
+#include "vpr_types.h"
+
+/************************************************************************
+ *  ChanNodeDetails records segment length, directionality and starting of routing tracks
+ *    +---------------------------------+
+ *    | Index | Direction | Start Point |
+ *    +---------------------------------+
+ *    |   0   | --------> |   Yes       |
+ *    +---------------------------------+
+ ***********************************************************************/
+
+
+class ChanNodeDetails {
+  public : /* Constructor */
+    ChanNodeDetails(const ChanNodeDetails&); /* Duplication */
+    ChanNodeDetails(); /* Initilization */
+  public: /* Accessors */
+    size_t get_chan_width() const;
+    size_t get_track_node_id(const size_t& track_id) const;
+    std::vector<size_t> get_track_node_ids() const;
+    e_direction get_track_direction(const size_t& track_id) const;
+    size_t get_track_segment_length(const size_t& track_id) const;
+    size_t get_track_segment_id(const size_t& track_id) const;
+    bool is_track_start(const size_t& track_id) const;
+    bool is_track_end(const size_t& track_id) const;
+    std::vector<size_t> get_seg_group(const size_t& track_id) const;
+    std::vector<size_t> get_seg_group_node_id(const std::vector<size_t>& seg_group) const;
+    size_t get_num_starting_tracks(const e_direction& track_direction) const;
+    size_t get_num_ending_tracks(const e_direction& track_direction) const;
+  public: /* Mutators */
+    void reserve(const size_t& chan_width); /* Reserve the capacitcy of vectors */
+    void add_track(const size_t& track_node_id, const e_direction& track_direction,
+                   const size_t& seg_id, const size_t& seg_length,
+                   const size_t& is_start, const size_t& is_end);
+    void set_track_node_id(const size_t& track_index, const size_t& track_node_id);
+    void set_track_node_ids(const std::vector<size_t>& track_node_ids);
+    void set_tracks_start(const e_direction& track_direction);
+    void set_tracks_end(const e_direction& track_direction);
+    void rotate_track_node_id(const size_t& offset,
+                              const e_direction& track_direction,
+                              const bool& counter_rotate); /* rotate the track_node_id by an offset */
+    void clear();
+  private: /* validators */
+    bool validate_chan_width() const;
+    bool validate_track_id(const size_t& track_id) const;
+  private: /* Internal data */ 
+    std::vector<size_t> track_node_ids_; /* indices of each track */
+    std::vector<e_direction> track_direction_; /* direction of each track */
+    std::vector<size_t> seg_ids_; /* id of segment of each track */
+    std::vector<size_t> seg_length_; /* Length of each segment */
+    std::vector<bool>   track_start_; /* flag to identify if this is the starting point of the track */
+    std::vector<bool>   track_end_; /* flag to identify if this is the ending point of the track */
+};
+
+#endif 
+

From 4b7d2221d1d6caedcf1b007b1fb4f3a46d6a094c Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 4 Mar 2020 13:55:53 -0700
Subject: [PATCH 250/645] adapt rr_graph builder utilized functions and move
 rr_graph utils from openfpga to vpr

---
 .../tileable_rr_graph/chan_node_details.cpp   |   4 +
 vpr/src/tileable_rr_graph/chan_node_details.h |  31 +-
 .../openfpga_rr_graph_utils.cpp               |   0
 .../openfpga_rr_graph_utils.h                 |   0
 .../rr_graph_builder_utils.cpp                | 289 ++++++++++++++++++
 .../rr_graph_builder_utils.h                  |  69 +++++
 6 files changed, 375 insertions(+), 18 deletions(-)
 rename {openfpga/src/utils => vpr/src/tileable_rr_graph}/openfpga_rr_graph_utils.cpp (100%)
 rename {openfpga/src/utils => vpr/src/tileable_rr_graph}/openfpga_rr_graph_utils.h (100%)
 create mode 100644 vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp
 create mode 100644 vpr/src/tileable_rr_graph/rr_graph_builder_utils.h

diff --git a/vpr/src/tileable_rr_graph/chan_node_details.cpp b/vpr/src/tileable_rr_graph/chan_node_details.cpp
index b9a2cac07..f52188d93 100644
--- a/vpr/src/tileable_rr_graph/chan_node_details.cpp
+++ b/vpr/src/tileable_rr_graph/chan_node_details.cpp
@@ -5,6 +5,9 @@
 #include <algorithm>
 #include "chan_node_details.h"
 
+/* begin namespace openfpga */
+namespace openfpga {
+
 /************************************************************************
  *  Constructors 
  ***********************************************************************/
@@ -290,3 +293,4 @@ bool ChanNodeDetails::validate_track_id(const size_t& track_id) const {
   return false;
 }
 
+} /* end namespace openfpga */
diff --git a/vpr/src/tileable_rr_graph/chan_node_details.h b/vpr/src/tileable_rr_graph/chan_node_details.h
index abb595965..e991b07e0 100644
--- a/vpr/src/tileable_rr_graph/chan_node_details.h
+++ b/vpr/src/tileable_rr_graph/chan_node_details.h
@@ -1,3 +1,12 @@
+#ifndef CHAN_NODE_DETAILS_H
+#define CHAN_NODE_DETAILS_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <vector>
+#include "vpr_types.h"
+
 /************************************************************************
  *  This file contains a class to model the details of routing node
  *  in a channel:
@@ -7,22 +16,8 @@
  *  4. potentail track_id(ptc_num) of each segment
  ***********************************************************************/
 
-/* IMPORTANT:
- * The following preprocessing flags are added to 
- * avoid compilation error when this headers are included in more than 1 times 
- */
-#ifndef CHAN_NODE_DETAILS_H
-#define CHAN_NODE_DETAILS_H
-
-/*
- * Notes in include header files in a head file 
- * Only include the neccessary header files 
- * that is required by the data types in the function/class declarations!
- */
-/* Header files should be included in a sequence */
-/* Standard header files required go first */
-#include <vector>
-#include "vpr_types.h"
+/* begin namespace openfpga */
+namespace openfpga {
 
 /************************************************************************
  *  ChanNodeDetails records segment length, directionality and starting of routing tracks
@@ -33,7 +28,6 @@
  *    +---------------------------------+
  ***********************************************************************/
 
-
 class ChanNodeDetails {
   public : /* Constructor */
     ChanNodeDetails(const ChanNodeDetails&); /* Duplication */
@@ -76,5 +70,6 @@ class ChanNodeDetails {
     std::vector<bool>   track_end_; /* flag to identify if this is the ending point of the track */
 };
 
-#endif 
+} /* end namespace openfpga */
 
+#endif 
diff --git a/openfpga/src/utils/openfpga_rr_graph_utils.cpp b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp
similarity index 100%
rename from openfpga/src/utils/openfpga_rr_graph_utils.cpp
rename to vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp
diff --git a/openfpga/src/utils/openfpga_rr_graph_utils.h b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.h
similarity index 100%
rename from openfpga/src/utils/openfpga_rr_graph_utils.h
rename to vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.h
diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp
new file mode 100644
index 000000000..209d8a80b
--- /dev/null
+++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp
@@ -0,0 +1,289 @@
+/************************************************************************
+ *  This file contains most utilized functions for rr_graph builders 
+ ***********************************************************************/
+#include <vector>
+#include <algorithm>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+#include "vpr_utils.h"
+
+#include "rr_graph_builder_utils.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/************************************************************************
+ * Get the class index of a grid pin 
+ ***********************************************************************/
+int get_grid_pin_class_index(const t_grid_tile& cur_grid,
+                             const int pin_index) {
+  /* check */
+  VTR_ASSERT(pin_index < cur_grid.type->num_pins);
+  return cur_grid.type->pin_class[pin_index];
+}
+
+/* Deteremine the side of a io grid */
+e_side determine_io_grid_pin_side(const vtr::Point<size_t>& device_size, 
+                                  const vtr::Point<size_t>& grid_coordinate) {
+  /* TOP side IO of FPGA */
+  if (device_size.y() == grid_coordinate.y()) {
+    return BOTTOM; /* Such I/O has only Bottom side pins */
+  } else if (device_size.x() == grid_coordinate.x()) { /* RIGHT side IO of FPGA */
+    return LEFT; /* Such I/O has only Left side pins */
+  } else if (0 == grid_coordinate.y()) { /* BOTTOM side IO of FPGA */
+    return TOP; /* Such I/O has only Top side pins */
+  } else if (0 == grid_coordinate.x()) { /* LEFT side IO of FPGA */
+    return RIGHT; /* Such I/O has only Right side pins */
+  } else {
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "I/O Grid is in the center part of FPGA! Currently unsupported!\n");
+    exit(1);
+  }
+}
+
+/************************************************************************
+ * Get a list of pin_index for a grid (either OPIN or IPIN)
+ * For IO_TYPE, only one side will be used, we consider one side of pins 
+ * For others, we consider all the sides  
+ ***********************************************************************/
+std::vector<int> get_grid_side_pins(const t_grid_tile& cur_grid, 
+                                    const e_pin_type& pin_type, 
+                                    const e_side& pin_side, 
+                                    const int& pin_width,
+                                    const int& pin_height) {
+  std::vector<int> pin_list; 
+  /* Make sure a clear start */
+  pin_list.clear();
+
+  for (int ipin = 0; ipin < cur_grid.type->num_pins; ++ipin) {
+    int class_id = cur_grid.type->pin_class[ipin];
+    if ( (1 == cur_grid.type->pinloc[pin_width][pin_height][pin_side][ipin]) 
+      && (pin_type == cur_grid.type->class_inf[class_id].type) ) {
+      pin_list.push_back(ipin);
+    }
+  }
+  return pin_list;
+}
+
+/************************************************************************
+ * Get the number of pins for a grid (either OPIN or IPIN)
+ * For IO_TYPE, only one side will be used, we consider one side of pins 
+ * For others, we consider all the sides  
+ ***********************************************************************/
+size_t get_grid_num_pins(const t_grid_tile& cur_grid, 
+                         const e_pin_type& pin_type, 
+                         const e_side& io_side) {
+  size_t num_pins = 0;
+
+  /* For IO_TYPE sides */
+  for (const e_side& side : {TOP, RIGHT, BOTTOM, LEFT}) {
+    /* skip unwanted sides */
+    if ( (true == is_io_type(cur_grid.type))
+      && (side != io_side) ) { 
+      continue;
+    }
+    /* Get pin list */
+    for (int width = 0; width < cur_grid.type->width; ++width) {
+      for (int height = 0; height < cur_grid.type->height; ++height) {
+        std::vector<int> pin_list = get_grid_side_pins(cur_grid, pin_type, side, width, height);
+        num_pins += pin_list.size();
+      }
+    } 
+  }
+
+  return num_pins;
+}
+
+/************************************************************************
+ * Get the number of pins for a grid (either OPIN or IPIN)
+ * For IO_TYPE, only one side will be used, we consider one side of pins 
+ * For others, we consider all the sides  
+ ***********************************************************************/
+size_t get_grid_num_classes(const t_grid_tile& cur_grid, 
+                            const e_pin_type& pin_type) {
+  size_t num_classes = 0;
+
+  for (int iclass = 0; iclass < cur_grid.type->num_class; ++iclass) {
+    /* Bypass unmatched pin_type */
+    if (pin_type != cur_grid.type->class_inf[iclass].type) {
+      continue;
+    }
+    num_classes++;
+  }
+
+  return num_classes;
+}
+
+/************************************************************************
+ * Get the track_id of a routing track w.r.t its coordinator 
+ * In tileable routing architecture, the track_id changes SB by SB.
+ * Therefore the track_ids are stored in a vector, indexed by the relative coordinator
+ * based on the starting point of the track
+ * For routing tracks in INC_DIRECTION
+ * (xlow, ylow) should be the starting point 
+ * 
+ * (xlow, ylow)                                      (xhigh, yhigh)
+ *  track_id[0]  -------------------------------> track_id[xhigh - xlow + yhigh - ylow]
+ *
+ * For routing tracks in DEC_DIRECTION
+ * (xhigh, yhigh) should be the starting point 
+ *
+ * (xlow, ylow)                                      (xhigh, yhigh)
+ *  track_id[0]  <------------------------------- track_id[xhigh - xlow + yhigh - ylow]
+ *
+ *
+ ***********************************************************************/
+short get_rr_node_actual_track_id(const RRGraph& rr_graph,
+                                  const RRNodeId& track_rr_node,
+                                  const vtr::Point<size_t>& coord,
+                                  const vtr::vector<RRNodeId, std::vector<size_t>>& tileable_rr_graph_node_track_ids) {
+  vtr::Point<size_t> low_coord(rr_graph.node_xlow(track_rr_node), rr_graph.node_ylow(track_rr_node));
+  size_t offset = (int)abs((int)coord.x() -  (int)low_coord.x() + (int)coord.y() - (int)low_coord.y());
+  return tileable_rr_graph_node_track_ids[track_rr_node][offset];
+}
+
+/************************************************************************
+ * Get the ptc of a routing track in the channel where it ends
+ * For routing tracks in INC_DIRECTION
+ * the ptc is the last of track_ids
+ *
+ * For routing tracks in DEC_DIRECTION
+ * the ptc is the first of track_ids
+ ***********************************************************************/
+short get_track_rr_node_end_track_id(const RRGraph& rr_graph,
+                                     const RRNodeId& track_rr_node,
+                                     const vtr::vector<RRNodeId, std::vector<size_t>>& tileable_rr_graph_node_track_ids) {
+  /* Make sure we have CHANX or CHANY */
+  VTR_ASSERT( (CHANX == rr_graph.node_type(track_rr_node))
+           || (CHANY == rr_graph.node_type(track_rr_node)) );
+ 
+  if (INC_DIRECTION == rr_graph.node_direction(track_rr_node)) {
+    return tileable_rr_graph_node_track_ids[track_rr_node].back(); 
+  }
+
+  VTR_ASSERT(DEC_DIRECTION == rr_graph.node_direction(track_rr_node));
+  return tileable_rr_graph_node_track_ids[track_rr_node].front(); 
+}
+
+/************************************************************************
+ * Find the number of nodes in the same class
+ * in a routing resource graph
+ ************************************************************************/
+short find_rr_graph_num_nodes(const RRGraph& rr_graph,
+                              const std::vector<t_rr_type>& node_types) {
+  short counter = 0;
+
+  for (const RRNodeId& node : rr_graph.nodes()) {
+    /* Bypass the nodes not in the class */
+    if (node_types.end() == std::find(node_types.begin(), node_types.end(), rr_graph.node_type(node))) {
+      continue;
+    }
+    counter++; 
+  } 
+
+  return counter;
+}
+
+/************************************************************************
+ * Find the maximum fan-in for a given class of nodes
+ * in a routing resource graph
+ ************************************************************************/
+short find_rr_graph_max_fan_in(const RRGraph& rr_graph,
+                               const std::vector<t_rr_type>& node_types) {
+  short max_fan_in = 0;
+
+  for (const RRNodeId& node : rr_graph.nodes()) {
+    /* Bypass the nodes not in the class */
+    if (node_types.end() == std::find(node_types.begin(), node_types.end(), rr_graph.node_type(node))) {
+      continue;
+    }
+    max_fan_in = std::max(rr_graph.node_fan_in(node), max_fan_in); 
+  } 
+
+  return max_fan_in;
+}
+
+/************************************************************************
+ * Find the minimum fan-in for a given class of nodes
+ * in a routing resource graph
+ ************************************************************************/
+short find_rr_graph_min_fan_in(const RRGraph& rr_graph,
+                               const std::vector<t_rr_type>& node_types) {
+  short min_fan_in = 0;
+
+  for (const RRNodeId& node : rr_graph.nodes()) {
+    /* Bypass the nodes not in the class */
+    if (node_types.end() == std::find(node_types.begin(), node_types.end(), rr_graph.node_type(node))) {
+      continue;
+    }
+    min_fan_in = std::min(rr_graph.node_fan_in(node), min_fan_in); 
+  } 
+
+
+  return min_fan_in;
+}
+
+/************************************************************************
+ * Find the average fan-in for a given class of nodes
+ * in a routing resource graph
+ ************************************************************************/
+short find_rr_graph_average_fan_in(const RRGraph& rr_graph,
+                                   const std::vector<t_rr_type>& node_types) {
+  /* Get the maximum SB mux size */
+  size_t sum = 0;
+  size_t counter = 0;
+
+  for (const RRNodeId& node : rr_graph.nodes()) {
+    /* Bypass the nodes not in the class */
+    if (node_types.end() == std::find(node_types.begin(), node_types.end(), rr_graph.node_type(node))) {
+      continue;
+    }
+
+    sum += rr_graph.node_fan_in(node); 
+    counter++;
+  } 
+
+  return sum / counter;
+}
+
+/************************************************************************
+ * Print statistics of multiplexers in a routing resource graph  
+ ************************************************************************/
+void print_rr_graph_mux_stats(const RRGraph& rr_graph) {
+
+  /* Print MUX size distribution */
+  std::vector<t_rr_type> sb_node_types;
+  sb_node_types.push_back(CHANX);
+  sb_node_types.push_back(CHANY);
+
+  /* Print statistics */
+  VTR_LOG("------------------------------------------------\n");
+  VTR_LOG("Total No. of Switch Block multiplexer size: %d\n",
+          find_rr_graph_num_nodes(rr_graph, sb_node_types));
+  VTR_LOG("Maximum Switch Block multiplexer size: %d\n",
+          find_rr_graph_max_fan_in(rr_graph, sb_node_types));
+  VTR_LOG("Minimum Switch Block multiplexer size: %d\n",
+          find_rr_graph_min_fan_in(rr_graph, sb_node_types));
+  VTR_LOG("Average Switch Block multiplexer size: %lu\n",
+          find_rr_graph_average_fan_in(rr_graph, sb_node_types));
+  VTR_LOG("------------------------------------------------\n");
+
+  /* Get the maximum CB mux size */
+  std::vector<t_rr_type> cb_node_types(1, IPIN);
+
+  VTR_LOG("------------------------------------------------\n");
+  VTR_LOG("Total No. of Connection Block Multiplexer size: %d\n",
+          find_rr_graph_num_nodes(rr_graph, cb_node_types));
+  VTR_LOG("Maximum Connection Block Multiplexer size: %d\n",
+          find_rr_graph_max_fan_in(rr_graph, cb_node_types));
+  VTR_LOG("Minimum Connection Block Multiplexer size: %d\n",
+          find_rr_graph_min_fan_in(rr_graph, cb_node_types));
+  VTR_LOG("Average Connection Block Multiplexer size: %lu\n",
+          find_rr_graph_average_fan_in(rr_graph, cb_node_types));
+  VTR_LOG("------------------------------------------------\n");
+}
+
+} /* end namespace openfpga */
diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h
new file mode 100644
index 000000000..f67acb038
--- /dev/null
+++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h
@@ -0,0 +1,69 @@
+#ifndef RR_GRAPH_BUILDER_UTILS_H
+#define RR_GRAPH_BUILDER_UTILS_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "device_grid.h"
+#include "rr_graph_obj.h"
+#include "vtr_geometry.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+int get_grid_pin_class_index(const t_grid_tile& cur_grid,
+                             const int pin_index);
+
+e_side determine_io_grid_pin_side(const vtr::Point<size_t>& device_size, 
+                                  const vtr::Point<size_t>& grid_coordinate);
+
+std::vector<int> get_grid_side_pins(const t_grid_tile& cur_grid, 
+                                    const e_pin_type& pin_type, 
+                                    const e_side& pin_side, 
+                                    const int& pin_width,
+                                    const int& pin_height);
+
+size_t get_grid_num_pins(const t_grid_tile& cur_grid, 
+                         const e_pin_type& pin_type, 
+                         const e_side& io_side);
+
+size_t get_grid_num_classes(const t_grid_tile& cur_grid, 
+                            const e_pin_type& pin_type);
+
+short get_rr_node_actual_track_id(const RRGraph& rr_graph,
+                                  const RRNodeId& track_rr_node,
+                                  const vtr::Point<size_t>& coord,
+                                  const vtr::vector<RRNodeId, std::vector<size_t>>& tileable_rr_graph_node_track_ids);
+
+vtr::Point<size_t> get_track_rr_node_start_coordinator(const RRGraph& rr_graph,
+                                                       const RRNodeId& track_rr_node);
+
+vtr::Point<size_t> get_track_rr_node_end_coordinator(const RRGraph& rr_graph,
+                                                     const RRNodeId& track_rr_node);
+
+short get_track_rr_node_end_track_id(const RRGraph& rr_graph,
+                                     const RRNodeId& track_rr_node,
+                                     const vtr::vector<RRNodeId, std::vector<size_t>>& tileable_rr_graph_node_track_ids);
+
+short find_rr_graph_num_nodes(const RRGraph& rr_graph,
+                              const std::vector<t_rr_type>& node_types);
+
+short find_rr_graph_max_fan_in(const RRGraph& rr_graph,
+                               const std::vector<t_rr_type>& node_types);
+
+short find_rr_graph_min_fan_in(const RRGraph& rr_graph,
+                               const std::vector<t_rr_type>& node_types);
+
+short find_rr_graph_average_fan_in(const RRGraph& rr_graph,
+                                   const std::vector<t_rr_type>& node_types);
+
+void print_rr_graph_mux_stats(const RRGraph& rr_graph);
+
+} /* end namespace openfpga */
+
+#endif
+

From 6e83154703dc8960cfe2a9ca94725d012c39840a Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 4 Mar 2020 14:14:28 -0700
Subject: [PATCH 251/645] move rr_gsb and rr_chan to tileable rr_graph builder

---
 vpr/CMakeLists.txt                                | 15 ++++++++-------
 .../src/tileable_rr_graph}/rr_chan.cpp            |  0
 .../src/tileable_rr_graph}/rr_chan.h              |  0
 .../src/tileable_rr_graph}/rr_gsb.cpp             |  0
 .../src/tileable_rr_graph}/rr_gsb.h               |  0
 5 files changed, 8 insertions(+), 7 deletions(-)
 rename {openfpga/src/annotation => vpr/src/tileable_rr_graph}/rr_chan.cpp (100%)
 rename {openfpga/src/annotation => vpr/src/tileable_rr_graph}/rr_chan.h (100%)
 rename {openfpga/src/annotation => vpr/src/tileable_rr_graph}/rr_gsb.cpp (100%)
 rename {openfpga/src/annotation => vpr/src/tileable_rr_graph}/rr_gsb.h (100%)

diff --git a/vpr/CMakeLists.txt b/vpr/CMakeLists.txt
index 4d06b1e1a..592fa2edb 100644
--- a/vpr/CMakeLists.txt
+++ b/vpr/CMakeLists.txt
@@ -56,13 +56,14 @@ set_target_properties(libvpr8 PROPERTIES PREFIX "") #Avoid extra 'lib' prefix
 
 #Specify link-time dependancies
 target_link_libraries(libvpr8
-                        libvtrutil
-                        libarchfpga
-                        libsdcparse
-                        libblifparse
-                        libtatum
-                        libargparse
-                        libpugixml)
+                      libvtrutil
+                      libopenfpgautil
+                      libarchfpga
+                      libsdcparse
+                      libblifparse
+                      libtatum
+                      libargparse
+                      libpugixml)
 
 #link graphics library only when graphics set to on
 if (VPR_USE_EZGL STREQUAL "on")
diff --git a/openfpga/src/annotation/rr_chan.cpp b/vpr/src/tileable_rr_graph/rr_chan.cpp
similarity index 100%
rename from openfpga/src/annotation/rr_chan.cpp
rename to vpr/src/tileable_rr_graph/rr_chan.cpp
diff --git a/openfpga/src/annotation/rr_chan.h b/vpr/src/tileable_rr_graph/rr_chan.h
similarity index 100%
rename from openfpga/src/annotation/rr_chan.h
rename to vpr/src/tileable_rr_graph/rr_chan.h
diff --git a/openfpga/src/annotation/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp
similarity index 100%
rename from openfpga/src/annotation/rr_gsb.cpp
rename to vpr/src/tileable_rr_graph/rr_gsb.cpp
diff --git a/openfpga/src/annotation/rr_gsb.h b/vpr/src/tileable_rr_graph/rr_gsb.h
similarity index 100%
rename from openfpga/src/annotation/rr_gsb.h
rename to vpr/src/tileable_rr_graph/rr_gsb.h

From 4455615980b40516860801d782c4dc5fedb60e25 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 4 Mar 2020 14:21:35 -0700
Subject: [PATCH 252/645] adapt tileable routing channel detail builder

---
 .../tileable_chan_details_builder.cpp         | 244 ++++++++++++++++++
 .../tileable_chan_details_builder.h           |  26 ++
 2 files changed, 270 insertions(+)
 create mode 100644 vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp
 create mode 100644 vpr/src/tileable_rr_graph/tileable_chan_details_builder.h

diff --git a/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp
new file mode 100644
index 000000000..5259c9445
--- /dev/null
+++ b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp
@@ -0,0 +1,244 @@
+/************************************************************************
+ *  This file contains a builder for the ChanNodeDetails data structure 
+ *  Different from VPR rr_graph builders, this builder aims to create a 
+ *  highly regular routing channel. Thus, it is called tileable, 
+ *  which brings significant advantage in producing large FPGA fabrics.
+ ***********************************************************************/
+#include <vector>
+#include <algorithm>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+#include "tileable_chan_details_builder.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/************************************************************************
+ * Generate the number of tracks for each types of routing segments
+ * w.r.t. the frequency of each of segments and channel width
+ * Note that if we dertermine the number of tracks per type using
+ *     chan_width * segment_frequency / total_freq may cause 
+ * The total track num may not match the chan_width, 
+ * therefore, we assign tracks one by one until we meet the frequency requirement
+ * In this way, we can assign the number of tracks with repect to frequency 
+ ***********************************************************************/
+static 
+std::vector<size_t> get_num_tracks_per_seg_type(const size_t& chan_width, 
+                                                const std::vector<t_segment_inf>& segment_inf, 
+                                                const bool& use_full_seg_groups) {
+  std::vector<size_t> result;
+  std::vector<double> demand;
+  /* Make sure a clean start */
+  result.resize(segment_inf.size());
+  demand.resize(segment_inf.size());
+
+  /* Scale factor so we can divide by any length
+   * and still use integers */
+  /* Get the sum of frequency */
+  size_t scale = 1;
+  size_t freq_sum = 0;
+  for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) {
+    scale *= segment_inf[iseg].length;
+    freq_sum += segment_inf[iseg].frequency;
+  }
+  size_t reduce = scale * freq_sum;
+
+  /* Init assignments to 0 and set the demand values */
+  /* Get the fraction of each segment type considering the frequency:
+   * num_track_per_seg = chan_width * (freq_of_seg / sum_freq)
+   */
+  for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) {
+    result[iseg] = 0;
+    demand[iseg] = scale * chan_width * segment_inf[iseg].frequency;
+    if (true == use_full_seg_groups) {
+      demand[iseg] /= segment_inf[iseg].length;
+    }
+  }
+
+  /* check if the sum of num_tracks, matches the chan_width */
+  /* Keep assigning tracks until we use them up */
+  size_t assigned = 0;
+  size_t size = 0;
+  size_t imax = 0;
+  while (assigned < chan_width) {
+    /* Find current maximum demand */
+    double max = 0;
+    for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) {
+      if (demand[iseg] > max) {
+        imax = iseg;
+      }
+      max = std::max(demand[iseg], max); 
+    }
+
+    /* Assign tracks to the type and reduce the types demand */
+    size = (use_full_seg_groups ? segment_inf[imax].length : 1);
+    demand[imax] -= reduce;
+    result[imax] += size;
+    assigned += size;
+  }
+
+  /* Undo last assignment if we were closer to goal without it */
+  if ((assigned - chan_width) > (size / 2)) {
+    result[imax] -= size;
+  }
+
+  return result;
+} 
+
+/************************************************************************
+ * Adapt the number of channel width to a tileable routing architecture
+ ***********************************************************************/
+int adapt_to_tileable_route_chan_width(const int& chan_width, 
+                                       const std::vector<t_segment_inf>& segment_infs) {
+  int tileable_chan_width = 0;
+  
+  /* Estimate the number of segments per type by the given ChanW*/ 
+  std::vector<size_t> num_tracks_per_seg_type = get_num_tracks_per_seg_type(chan_width, 
+                                                                            segment_infs, 
+                                                                            true); /* Force to use the full segment group */
+  /* Sum-up the number of tracks */
+  for (size_t iseg = 0; iseg < num_tracks_per_seg_type.size(); ++iseg) {
+    tileable_chan_width += num_tracks_per_seg_type[iseg];
+  }
+  
+  return tileable_chan_width;
+}
+
+/************************************************************************
+ * Build details of routing tracks in a channel 
+ * The function will 
+ * 1. Assign the segments for each routing channel,
+ *    To be specific, for each routing track, we assign a routing segment.
+ *    The assignment is subject to users' specifications, such as 
+ *    a. length of each type of segment
+ *    b. frequency of each type of segment.
+ *    c. routing channel width
+ *
+ * 2. The starting point of each segment in the channel will be assigned
+ *    For each segment group with same directionality (tracks have the same length),
+ *    every L track will be a starting point (where L denotes the length of segments)
+ *    In this case, if the number of tracks is not a multiple of L,
+ *    indeed we may have some <L segments. This can be considered as a side effect.
+ *    But still the rr_graph is tileable, which is the first concern!
+ *
+ *    Here is a quick example of Length-4 wires in a W=12 routing channel
+ *    +---------------------------------------+--------------+
+ *    | Index |   Direction  | Starting Point | Ending Point |
+ *    +---------------------------------------+--------------+
+ *    |   0   | MUX--------> |   Yes          |  No          |
+ *    +---------------------------------------+--------------+
+ *    |   1   | <--------MUX |   Yes          |  No          |
+ *    +---------------------------------------+--------------+
+ *    |   2   |   -------->  |   No           |  No          |
+ *    +---------------------------------------+--------------+
+ *    |   3   | <--------    |   No           |  No          |
+ *    +---------------------------------------+--------------+
+ *    |   4   |    --------> |   No           |  No          |
+ *    +---------------------------------------+--------------+
+ *    |   5   | <--------    |   No           |  No          |
+ *    +---------------------------------------+--------------+
+ *    |   7   | -------->MUX |   No           |  Yes         |
+ *    +---------------------------------------+--------------+
+ *    |   8   | MUX<-------- |   No           |  Yes         |
+ *    +---------------------------------------+--------------+
+ *    |   9   | MUX--------> |   Yes          |  No          |
+ *    +---------------------------------------+--------------+
+ *    |   10  | <--------MUX |   Yes          |  No          |
+ *    +---------------------------------------+--------------+
+ *    |   11  | -------->MUX |   No           |  Yes         |
+ *    +------------------------------------------------------+
+ *    |   12  | <--------    |   No           |  No          |
+ *    +------------------------------------------------------+
+ *
+ * 3. SPECIAL for fringes: TOP|RIGHT|BOTTOM|RIGHT
+ *    if device_side is NUM_SIDES, we assume this channel does not locate on borders
+ *    All segments will start and ends with no exception
+ *
+ * 4. IMPORTANT: we should be aware that channel width maybe different 
+ *    in X-direction and Y-direction channels!!!
+ *    So we will load segment details for different channels 
+ ***********************************************************************/
+ChanNodeDetails build_unidir_chan_node_details(const size_t& chan_width, const size_t& max_seg_length,
+                                               const enum e_side& device_side, 
+                                               const std::vector<t_segment_inf>& segment_inf) {
+  ChanNodeDetails chan_node_details;
+  size_t actual_chan_width = chan_width;
+  /* Correct the chan_width: it should be an even number */
+  if (0 != actual_chan_width % 2) {
+    actual_chan_width++; /* increment it to be even */
+  }
+  VTR_ASSERT(0 == actual_chan_width % 2);
+  
+  /* Reserve channel width */
+  chan_node_details.reserve(chan_width);
+  /* Return if zero width is forced */
+  if (0 == actual_chan_width) {
+    return chan_node_details; 
+  }
+
+  /* Find the number of segments required by each group */
+  std::vector<size_t> num_tracks = get_num_tracks_per_seg_type(actual_chan_width/2, segment_inf, false);  
+
+  /* Add node to ChanNodeDetails */
+  size_t cur_track = 0;
+  for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) {
+    /* segment length will be set to maxium segment length if this is a longwire */
+    size_t seg_len = segment_inf[iseg].length;
+    if (true == segment_inf[iseg].longline) {
+       seg_len = max_seg_length;
+    } 
+    for (size_t itrack = 0; itrack < num_tracks[iseg]; ++itrack) {
+      bool seg_start = false;
+      bool seg_end = false;
+      /* Every first track of a group of Length-N wires, we set a starting point */
+      if (0 == itrack % seg_len) {
+        seg_start = true;
+      }
+      /* Every last track of a group of Length-N wires or this is the last track in this group, we set an ending point */
+      if ( (seg_len - 1 == itrack % seg_len) 
+        || (itrack == num_tracks[iseg] - 1) ) {
+        seg_end = true;
+      }
+      /* Since this is a unidirectional routing architecture,
+       * Add a pair of tracks, 1 INC_DIRECTION track and 1 DEC_DIRECTION track 
+       */
+      chan_node_details.add_track(cur_track, INC_DIRECTION, iseg, seg_len, seg_start, seg_end);
+      cur_track++;
+      chan_node_details.add_track(cur_track, DEC_DIRECTION, iseg, seg_len, seg_start, seg_end);
+      cur_track++;
+    }    
+  }
+  /* Check if all the tracks have been satisified */ 
+  VTR_ASSERT(cur_track == actual_chan_width);
+
+  /* If this is on the border of a device, segments should start */
+  switch (device_side) {
+  case TOP:
+  case RIGHT:
+    /* INC_DIRECTION should all end */
+    chan_node_details.set_tracks_end(INC_DIRECTION);
+    /* DEC_DIRECTION should all start */
+    chan_node_details.set_tracks_start(DEC_DIRECTION);
+    break;
+  case BOTTOM:
+  case LEFT:
+    /* INC_DIRECTION should all start */
+    chan_node_details.set_tracks_start(INC_DIRECTION);
+    /* DEC_DIRECTION should all end */
+    chan_node_details.set_tracks_end(DEC_DIRECTION);
+    break;
+  case NUM_SIDES:
+    break;
+  default:
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid device_side!\n");
+    exit(1);
+  }
+
+  return chan_node_details; 
+}
+
+} /* end namespace openfpga */
diff --git a/vpr/src/tileable_rr_graph/tileable_chan_details_builder.h b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.h
new file mode 100644
index 000000000..cc111541f
--- /dev/null
+++ b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.h
@@ -0,0 +1,26 @@
+#ifndef TILEABLE_CHAN_DETAILS_BUILDER_H 
+#define TILEABLE_CHAN_DETAILS_BUILDER_H 
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <vector>
+#include "physical_types.h"
+#include "chan_node_details.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+int adapt_to_tileable_route_chan_width(const int& chan_width, const std::vector<t_segment_inf>& segment_inf);
+
+ChanNodeDetails build_unidir_chan_node_details(const size_t& chan_width, const size_t& max_seg_length,
+                                               const e_side& device_side, 
+                                               const std::vector<t_segment_inf>& segment_inf);
+
+} /* end namespace openfpga */
+
+#endif

From 646ee9093780276fc46819d697dc3e448476d518 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 4 Mar 2020 18:19:53 -0700
Subject: [PATCH 253/645] bring tileable gsb builder for rr_graph online

---
 vpr/src/device/clb2clb_directs.h              |   16 +
 vpr/src/route/rr_graph.cpp                    |   12 +-
 vpr/src/tileable_rr_graph/rr_chan.cpp         |    6 +-
 vpr/src/tileable_rr_graph/rr_chan.h           |    2 +-
 vpr/src/tileable_rr_graph/rr_gsb.cpp          |    2 +-
 vpr/src/tileable_rr_graph/rr_gsb.h            |    4 +-
 .../tileable_rr_graph_gsb.cpp                 | 1296 +++++++++++++++++
 .../tileable_rr_graph/tileable_rr_graph_gsb.h |   80 +
 8 files changed, 1401 insertions(+), 17 deletions(-)
 create mode 100644 vpr/src/device/clb2clb_directs.h
 create mode 100755 vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp
 create mode 100755 vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h

diff --git a/vpr/src/device/clb2clb_directs.h b/vpr/src/device/clb2clb_directs.h
new file mode 100644
index 000000000..7cc54bb88
--- /dev/null
+++ b/vpr/src/device/clb2clb_directs.h
@@ -0,0 +1,16 @@
+#ifndef CLB2CLB_DIRECTS_H
+#define CLB2CLB_DIRECTS_H
+
+#include "physical_types.h"
+
+struct t_clb_to_clb_directs {
+    t_physical_tile_type_ptr from_clb_type;
+    int from_clb_pin_start_index;
+    int from_clb_pin_end_index;
+    t_physical_tile_type_ptr to_clb_type;
+    int to_clb_pin_start_index;
+    int to_clb_pin_end_index;
+    int switch_index; //The switch type used by this direct connection
+};
+
+#endif
diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp
index e17a0c912..ae6e2593e 100644
--- a/vpr/src/route/rr_graph.cpp
+++ b/vpr/src/route/rr_graph.cpp
@@ -41,6 +41,8 @@
 #include "rr_graph_obj_util.h"
 #include "check_rr_graph_obj.h"
 
+#include "clb2clb_directs.h"
+
 //#define VERBOSE
 
 struct t_mux {
@@ -55,16 +57,6 @@ struct t_mux_size_distribution {
     t_mux_size_distribution* next;
 };
 
-struct t_clb_to_clb_directs {
-    t_physical_tile_type_ptr from_clb_type;
-    int from_clb_pin_start_index;
-    int from_clb_pin_end_index;
-    t_physical_tile_type_ptr to_clb_type;
-    int to_clb_pin_start_index;
-    int to_clb_pin_end_index;
-    int switch_index; //The switch type used by this direct connection
-};
-
 struct t_pin_loc {
     int pin_index;
     int width_offset;
diff --git a/vpr/src/tileable_rr_graph/rr_chan.cpp b/vpr/src/tileable_rr_graph/rr_chan.cpp
index b85d1b917..9d23372e5 100644
--- a/vpr/src/tileable_rr_graph/rr_chan.cpp
+++ b/vpr/src/tileable_rr_graph/rr_chan.cpp
@@ -127,8 +127,8 @@ std::vector<RRSegmentId> RRChan::get_segment_ids() const {
 }
 
 /* Get a list of nodes whose segment_id is specified  */
-std::vector<RRNodeId> RRChan::get_node_ids_by_segment_ids(const RRSegmentId& seg_id) const {
-  std::vector<RRNodeId> node_list;
+std::vector<size_t> RRChan::get_node_ids_by_segment_ids(const RRSegmentId& seg_id) const {
+  std::vector<size_t> node_list;
 
   /* make sure a clean start */
   node_list.clear();
@@ -137,7 +137,7 @@ std::vector<RRNodeId> RRChan::get_node_ids_by_segment_ids(const RRSegmentId& seg
   for (size_t inode = 0; inode < get_chan_width(); ++inode) {
     /* Try to find the node_segment id in the list */
     if ( seg_id == node_segments_[inode] ) {
-      node_list.push_back(nodes_[inode]);
+      node_list.push_back(inode);
     }
   }
 
diff --git a/vpr/src/tileable_rr_graph/rr_chan.h b/vpr/src/tileable_rr_graph/rr_chan.h
index ab8bb6617..3277bb173 100644
--- a/vpr/src/tileable_rr_graph/rr_chan.h
+++ b/vpr/src/tileable_rr_graph/rr_chan.h
@@ -54,7 +54,7 @@ class RRChan {
     RRSegmentId get_node_segment(const size_t& track_num) const;
     bool is_mirror(const RRGraph& rr_graph, const RRChan& cand) const; /* evaluate if two RR_chan is mirror to each other */
     std::vector<RRSegmentId> get_segment_ids() const; /* Get a list of segments used in this routing channel */
-    std::vector<RRNodeId> get_node_ids_by_segment_ids(const RRSegmentId& seg_id) const; /* Get a list of segments used in this routing channel */
+    std::vector<size_t> get_node_ids_by_segment_ids(const RRSegmentId& seg_id) const; /* Get a list of segments used in this routing channel */
   public: /* Mutators */
     /* copy */
     void set(const RRChan&); 
diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp
index cd57d8e6b..5b558fffd 100644
--- a/vpr/src/tileable_rr_graph/rr_gsb.cpp
+++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp
@@ -117,7 +117,7 @@ std::vector<RRSegmentId> RRGSB::get_chan_segment_ids(const e_side& side) const {
 }
 
 /* Get a list of rr_nodes whose sed_id is specified */
-std::vector<RRNodeId> RRGSB::get_chan_node_ids_by_segment_ids(const e_side& side,
+std::vector<size_t> RRGSB::get_chan_node_ids_by_segment_ids(const e_side& side,
                                                               const RRSegmentId& seg_id) const {
   return chan_node_[size_t(side)].get_node_ids_by_segment_ids(seg_id);
 } 
diff --git a/vpr/src/tileable_rr_graph/rr_gsb.h b/vpr/src/tileable_rr_graph/rr_gsb.h
index 4541c88dd..f582d7ce3 100644
--- a/vpr/src/tileable_rr_graph/rr_gsb.h
+++ b/vpr/src/tileable_rr_graph/rr_gsb.h
@@ -77,8 +77,8 @@ class RRGSB {
     std::vector<RRSegmentId> get_chan_segment_ids(const e_side& side) const; 
 
     /* Get a list of segments used in this routing channel */
-    std::vector<RRNodeId> get_chan_node_ids_by_segment_ids(const e_side& side,
-                                                           const RRSegmentId& seg_id) const; 
+    std::vector<size_t> get_chan_node_ids_by_segment_ids(const e_side& side,
+                                                         const RRSegmentId& seg_id) const; 
 
     /* get a rr_node at a given side and track_id */
     RRNodeId get_chan_node(const e_side& side, const size_t& track_id) const; 
diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp
new file mode 100755
index 000000000..332a44e94
--- /dev/null
+++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp
@@ -0,0 +1,1296 @@
+/************************************************************************
+ *  This file contains a builder for track-to-track connections inside a 
+ *  tileable General Switch Block (GSB).
+ ***********************************************************************/
+#include <vector>
+#include <cmath>
+#include <algorithm>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_side_manager.h"
+
+#include "vpr_utils.h"
+#include "rr_graph_obj_util.h"
+#include "openfpga_rr_graph_utils.h"
+#include "rr_graph_builder_utils.h"
+#include "tileable_chan_details_builder.h"
+#include "tileable_rr_graph_gsb.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/************************************************************************
+ * Internal data structures
+ ***********************************************************************/
+typedef std::vector<std::vector<int>> t_track_group;
+
+/************************************************************************
+ * A enumeration to list the status of a track inside a GSB
+ * 1. start; 2. end; 3. passing
+ * This is used to group tracks which ease the building of
+ * track-to-track mapping matrix
+ ***********************************************************************/
+enum e_track_status {
+  TRACK_START,
+  TRACK_END,
+  TRACK_PASS,
+  NUM_TRACK_STATUS /* just a place holder to get the number of status */
+};
+
+/************************************************************************
+ * Check if a track starts from this GSB or not 
+ * (xlow, ylow) should be same as the GSB side coordinate 
+ *
+ * Check if a track ends at this GSB or not 
+ * (xhigh, yhigh) should be same as the GSB side coordinate 
+ ***********************************************************************/
+static 
+enum e_track_status determine_track_status_of_gsb(const RRGraph& rr_graph,
+                                                  const RRGSB& rr_gsb, 
+                                                  const enum e_side& gsb_side, 
+                                                  const size_t& track_id) {
+  enum e_track_status track_status = TRACK_PASS;
+  /* Get the rr_node */
+  RRNodeId track_node = rr_gsb.get_chan_node(gsb_side, track_id);
+  /* Get the coordinates */
+  vtr::Point<size_t> side_coordinate = rr_gsb.get_side_block_coordinate(gsb_side); 
+
+  /* Get the coordinate of where the track starts */
+  vtr::Point<size_t> track_start = get_track_rr_node_start_coordinate(rr_graph, track_node);
+
+  /* INC_DIRECTION start_track: (xlow, ylow) should be same as the GSB side coordinate */
+  /* DEC_DIRECTION start_track: (xhigh, yhigh) should be same as the GSB side coordinate */
+  if (  (track_start.x() == side_coordinate.x())
+     && (track_start.y() == side_coordinate.y()) 
+     && (OUT_PORT == rr_gsb.get_chan_node_direction(gsb_side, track_id)) ) {
+    /* Double check: start track should be an OUTPUT PORT of the GSB */
+    track_status = TRACK_START;
+  }
+
+  /* Get the coordinate of where the track ends */
+  vtr::Point<size_t> track_end = get_track_rr_node_end_coordinate(rr_graph, track_node);
+
+  /* INC_DIRECTION end_track: (xhigh, yhigh) should be same as the GSB side coordinate */ 
+  /* DEC_DIRECTION end_track: (xlow, ylow) should be same as the GSB side coordinate */ 
+  if (  (track_end.x() == side_coordinate.x())
+     && (track_end.y() == side_coordinate.y()) 
+     && (IN_PORT == rr_gsb.get_chan_node_direction(gsb_side, track_id)) ) {
+    /* Double check: end track should be an INPUT PORT of the GSB */
+    track_status = TRACK_END;
+  }
+
+  return track_status;
+}
+
+/************************************************************************
+ * Check if the GSB is in the Connection Block (CB) population list of the segment
+ * SB population of a L4 wire: 1 0 0 1
+ *
+ *                            +----+    +----+    +----+    +----+
+ *                            | CB |--->| CB |--->| CB |--->| CB |
+ *                            +----+    +----+    +----+    +----+
+ *  Engage CB connection       Yes       No        No        Yes
+ *
+ *  We will find the offset between gsb_side_coordinate and (xlow,ylow) of the track
+ *  Use the offset to check if the tracks should engage in this GSB connection
+ ***********************************************************************/
+static 
+bool is_gsb_in_track_cb_population(const RRGraph& rr_graph,
+                                   const RRGSB& rr_gsb, 
+                                   const e_side& gsb_side, 
+                                   const int& track_id,
+                                   const std::vector<t_segment_inf>& segment_inf) {
+  /* Get the rr_node */
+  RRNodeId track_node = rr_gsb.get_chan_node(gsb_side, track_id);
+  /* Get the coordinates */
+  vtr::Point<size_t> side_coordinate = rr_gsb.get_side_block_coordinate(gsb_side); 
+
+  vtr::Point<size_t> track_start = get_track_rr_node_start_coordinate(rr_graph, track_node);
+
+  /* Get the offset */
+  size_t offset = std::abs((int)side_coordinate.x() - (int)track_start.x()) 
+                + std::abs((int)side_coordinate.y() - (int)track_start.y()); 
+  
+  /* Get segment id */
+  RRSegmentId seg_id = rr_gsb.get_chan_node_segment(gsb_side, track_id);
+  /* validate offset */
+  VTR_ASSERT(offset < segment_inf[size_t(seg_id)].cb.size());
+
+  /* Get the SB population */
+  bool in_cb_population = false;
+  if (true == segment_inf[size_t(seg_id)].cb[offset]) {  
+    in_cb_population = true;
+  }
+
+  return in_cb_population;
+}
+
+/************************************************************************
+ * Check if the GSB is in the Switch Block (SB) population list of the segment
+ * SB population of a L3 wire: 1 0 0 1
+ *
+ *                            +----+    +----+    +----+    +----+
+ *                            | SB |--->| SB |--->| SB |--->| SB |
+ *                            +----+    +----+    +----+    +----+
+ *  Engage SB connection       Yes       No        No        Yes
+ *
+ *  We will find the offset between gsb_side_coordinate and (xlow,ylow) of the track
+ *  Use the offset to check if the tracks should engage in this GSB connection
+ ***********************************************************************/
+static 
+bool is_gsb_in_track_sb_population(const RRGraph& rr_graph,
+                                   const RRGSB& rr_gsb, 
+                                   const e_side& gsb_side, 
+                                   const int& track_id,
+                                   const std::vector<t_segment_inf>& segment_inf) {
+  /* Get the rr_node */
+  const RRNodeId& track_node = rr_gsb.get_chan_node(gsb_side, track_id);
+  /* Get the coordinates */
+  vtr::Point<size_t> side_coordinate = rr_gsb.get_side_block_coordinate(gsb_side); 
+
+  vtr::Point<size_t> track_start = get_track_rr_node_start_coordinate(rr_graph, track_node);
+
+  /* Get the offset */
+  size_t offset = std::abs((int)side_coordinate.x() - (int)track_start.x()) 
+                + std::abs((int)side_coordinate.y() - (int)track_start.y()); 
+  
+  /* Get segment id */
+  RRSegmentId seg_id = rr_gsb.get_chan_node_segment(gsb_side, track_id);
+  /* validate offset */
+  VTR_ASSERT(offset < segment_inf[size_t(seg_id)].sb.size());
+
+  /* Get the SB population */
+  bool in_sb_population = false;
+  if (true == segment_inf[size_t(seg_id)].sb[offset]) {  
+    in_sb_population = true;
+  }
+
+  return in_sb_population;
+}
+
+/************************************************************************
+ * Create a list of track_id based on the to_track and num_to_tracks
+ * We consider the following list [to_track, to_track + Fs/3 - 1]
+ * if the [to_track + Fs/3 - 1] exceeds the num_to_tracks, we start over from 0!
+***********************************************************************/
+static 
+std::vector<size_t> get_to_track_list(const int& Fs, const int& to_track, const int& num_to_tracks) {
+  std::vector<size_t> to_tracks;
+
+  for (int i = 0; i < Fs; i = i + 3) {  
+    /* TODO: currently, for Fs > 3, I always search the next from_track until Fs is satisfied 
+     * The optimal track selection should be done in a more scientific way!!! 
+     */
+    int to_track_i = to_track + i;
+    /* make sure the track id is still in range */
+    if ( to_track_i > num_to_tracks - 1) {
+      to_track_i = to_track_i % num_to_tracks; 
+    }
+    /* Ensure we are in the range */
+    VTR_ASSERT(to_track_i < num_to_tracks);
+    /* from track must be connected */
+    to_tracks.push_back(to_track_i);
+  }
+  return to_tracks;
+}
+
+/************************************************************************
+ * This function aims to return the track indices that drive the from_track
+ * in a Switch Block 
+ * The track_ids to return will depend on different topologies of SB
+ *  SUBSET, UNIVERSAL, and WILTON. 
+ ***********************************************************************/
+static 
+std::vector<size_t> get_switch_block_to_track_id(const e_switch_block_type& switch_block_type, 
+                                                 const int& Fs,
+                                                 const e_side& from_side,
+                                                 const int& from_track,
+                                                 const e_side& to_side, 
+                                                 const int& num_to_tracks) {
+
+  /* This routine returns the track number to which the from_track should     
+   * connect.  It supports any Fs % 3 == 0, switch blocks.
+   */
+  std::vector<size_t> to_tracks;
+
+  /* TODO: currently, for Fs > 3, I always search the next from_track until Fs is satisfied 
+   * The optimal track selection should be done in a more scientific way!!! 
+   */
+  VTR_ASSERT(0 == Fs % 3);
+
+  /* Adapt from_track to fit in the range of num_to_tracks */
+  size_t actual_from_track = from_track % num_to_tracks; 
+
+  switch (switch_block_type) {
+  case SUBSET: /* NB:  Global routing uses SUBSET too */
+    to_tracks = get_to_track_list(Fs, actual_from_track, num_to_tracks);
+    /* Finish, we return */
+    return to_tracks;
+  case UNIVERSAL:
+    if (  (from_side == LEFT)
+       || (from_side == RIGHT) ) {  
+     /* For the prev_side, to_track is from_track 
+      * For the next_side, to_track is num_to_tracks - 1 - from_track 
+      * For the opposite_side, to_track is always from_track
+      */
+      SideManager side_manager(from_side);
+      if ( (to_side == side_manager.get_opposite()) 
+        || (to_side == side_manager.get_rotate_counterclockwise()) ) {
+        to_tracks = get_to_track_list(Fs, actual_from_track, num_to_tracks);
+      } else if (to_side == side_manager.get_rotate_clockwise()) {
+        to_tracks = get_to_track_list(Fs, num_to_tracks - 1 - actual_from_track, num_to_tracks);
+      }
+    }
+
+    if (  (from_side ==  TOP)
+       || (from_side == BOTTOM) ) {  
+    /* For the next_side, to_track is from_track 
+     * For the prev_side, to_track is num_to_tracks - 1 - from_track 
+     * For the opposite_side, to_track is always from_track
+     */
+      SideManager side_manager(from_side);
+      if ( (to_side == side_manager.get_opposite()) 
+        || (to_side == side_manager.get_rotate_clockwise()) ) {
+        to_tracks = get_to_track_list(Fs, actual_from_track, num_to_tracks);
+      } else if (to_side == side_manager.get_rotate_counterclockwise()) {
+        to_tracks = get_to_track_list(Fs, num_to_tracks - 1 - actual_from_track, num_to_tracks);
+      }
+    }
+    /* Finish, we return */
+    return to_tracks;
+    /* End switch_block_type == UNIVERSAL case. */
+  case WILTON:
+    /* See S. Wilton Phd thesis, U of T, 1996 p. 103 for details on following. */
+    if (from_side == LEFT) {
+      if (to_side == RIGHT) { /* CHANX to CHANX */
+        to_tracks = get_to_track_list(Fs, actual_from_track, num_to_tracks);
+      } else if (to_side == TOP) { /* from CHANX to CHANY */
+        to_tracks = get_to_track_list(Fs, (num_to_tracks - actual_from_track ) % num_to_tracks, num_to_tracks);
+      } else if (to_side == BOTTOM) {
+        to_tracks = get_to_track_list(Fs, (num_to_tracks + actual_from_track - 1) % num_to_tracks, num_to_tracks);
+      }
+    } else if (from_side == RIGHT) {
+      if (to_side == LEFT) { /* CHANX to CHANX */
+        to_tracks = get_to_track_list(Fs, actual_from_track, num_to_tracks);
+      } else if (to_side == TOP) { /* from CHANX to CHANY */
+        to_tracks = get_to_track_list(Fs, (num_to_tracks + actual_from_track - 1) % num_to_tracks, num_to_tracks);
+      } else if (to_side == BOTTOM) {
+        to_tracks = get_to_track_list(Fs, (2 * num_to_tracks - 2 - actual_from_track) % num_to_tracks, num_to_tracks);
+      }
+    } else if (from_side == BOTTOM) {
+      if (to_side == TOP) { /* CHANY to CHANY */
+        to_tracks = get_to_track_list(Fs, actual_from_track, num_to_tracks);
+      } else if (to_side == LEFT) { /* from CHANY to CHANX */
+        to_tracks = get_to_track_list(Fs, (actual_from_track + 1) % num_to_tracks, num_to_tracks);
+      } else if (to_side == RIGHT) {
+        to_tracks = get_to_track_list(Fs, (2 * num_to_tracks - 2 - actual_from_track) % num_to_tracks, num_to_tracks);
+      }
+    } else if (from_side == TOP) {
+      if (to_side == BOTTOM) { /* CHANY to CHANY */
+        to_tracks = get_to_track_list(Fs, from_track, num_to_tracks);
+      } else if (to_side == LEFT) { /* from CHANY to CHANX */
+        to_tracks = get_to_track_list(Fs, (num_to_tracks - actual_from_track) % num_to_tracks, num_to_tracks);
+      } else if (to_side == RIGHT) {
+        to_tracks = get_to_track_list(Fs, (actual_from_track + 1) % num_to_tracks, num_to_tracks);
+      }
+    }
+    /* Finish, we return */
+    return to_tracks;
+  /* End switch_block_type == WILTON case. */
+  default:
+    VTR_LOGF_ERROR(__FILE__, __LINE__, 
+                   "Invalid switch block pattern !\n");
+    exit(1);
+  }
+
+  return to_tracks;
+}
+
+
+/************************************************************************
+ * Build the track_to_track_map[from_side][0..chan_width-1][to_side][track_indices] 
+ * For a group of from_track nodes and to_track nodes
+ * For each side of from_tracks, we call a routine to get the list of to_tracks
+ * Then, we fill the track2track_map
+ ***********************************************************************/
+static 
+void build_gsb_one_group_track_to_track_map(const RRGraph& rr_graph, 
+                                            const RRGSB& rr_gsb, 
+                                            const e_switch_block_type& sb_type, 
+                                            const int& Fs,
+                                            const bool& wire_opposite_side,
+                                            const t_track_group& from_tracks, /* [0..gsb_side][track_indices] */
+                                            const t_track_group& to_tracks, /* [0..gsb_side][track_indices] */
+                                            t_track2track_map& track2track_map) {
+  for (size_t side = 0; side < from_tracks.size(); ++side) {
+    SideManager side_manager(side);
+    e_side from_side = side_manager.get_side();
+    /* Find the other sides where the start tracks will locate */
+    std::vector<e_side> to_track_sides;
+    /* 0. opposite side */
+    to_track_sides.push_back(side_manager.get_opposite());
+    /* 1. prev side */
+    /* Previous side definition: TOP => LEFT; RIGHT=>TOP; BOTTOM=>RIGHT; LEFT=>BOTTOM */
+    to_track_sides.push_back(side_manager.get_rotate_counterclockwise()); 
+    /* 2. next side */
+    /* Next side definition: TOP => RIGHT; RIGHT=>BOTTOM; BOTTOM=>LEFT; LEFT=>TOP */
+    to_track_sides.push_back(side_manager.get_rotate_clockwise()); 
+    
+    for (size_t inode = 0; inode < from_tracks[side].size(); ++inode) {
+      for (size_t to_side_id = 0; to_side_id < to_track_sides.size(); ++to_side_id) {
+        enum e_side to_side = to_track_sides[to_side_id];
+        SideManager to_side_manager(to_side);
+        size_t to_side_index = to_side_manager.to_size_t();
+        /* Bypass those to_sides have no nodes  */
+        if (0 == to_tracks[to_side_index].size()) {
+          continue;
+        }
+        /* Bypass those from_side is same as to_side */
+        if (from_side == to_side) {
+          continue;
+        }
+        /* Bypass those from_side is opposite to to_side if required */
+        if ( (true == wire_opposite_side) 
+          && (to_side_manager.get_opposite() == from_side) ) {
+          continue;
+        }
+        /* Get other track_ids depending on the switch block pattern */
+        /* Find the track ids that will start at the other sides */
+        std::vector<size_t> to_track_ids = get_switch_block_to_track_id(sb_type, Fs, from_side, inode, 
+                                                                        to_side, 
+                                                                        to_tracks[to_side_index].size()); 
+        /* Update the track2track_map: */
+        for (size_t to_track_id = 0; to_track_id < to_track_ids.size(); ++to_track_id) {
+          size_t from_side_index = side_manager.to_size_t();
+          size_t from_track_index = from_tracks[side][inode];
+          /* Check the id is still in the range !*/
+          VTR_ASSERT( to_track_ids[to_track_id] < to_tracks[to_side_index].size() );
+          size_t to_track_index = to_tracks[to_side_index][to_track_ids[to_track_id]];
+          //printf("from_track(size=%lu): %lu , to_track_ids[%lu]:%lu, to_track_index: %lu in a group of %lu tracks\n", 
+          //       from_tracks[side].size(), inode, to_track_id, to_track_ids[to_track_id], 
+          //       to_track_index, to_tracks[to_side_index].size());
+          const RRNodeId& to_track_node = rr_gsb.get_chan_node(to_side, to_track_index);
+          VTR_ASSERT(true == rr_graph.valid_node_id(to_track_node));
+
+          /* from_track should be IN_PORT */
+          VTR_ASSERT(IN_PORT == rr_gsb.get_chan_node_direction(from_side, from_track_index)); 
+          /* to_track should be OUT_PORT */
+          VTR_ASSERT(OUT_PORT == rr_gsb.get_chan_node_direction(to_side, to_track_index)); 
+
+          /* Check if the to_track_node is already in the list ! */
+          std::vector<RRNodeId>::iterator it = std::find(track2track_map[from_side_index][from_track_index].begin(),
+                                                         track2track_map[from_side_index][from_track_index].end(),
+                                                         to_track_node);
+          if (it != track2track_map[from_side_index][from_track_index].end()) {
+             continue; /* the node_id is already in the list, go for the next */
+          }
+          /* Clear, we should add to the list */
+          track2track_map[from_side_index][from_track_index].push_back(to_track_node);
+        }
+      }
+    }
+  }
+}
+
+/************************************************************************
+ * Build the track_to_track_map[from_side][0..chan_width-1][to_side][track_indices] 
+ * based on the existing routing resources in the General Switch Block (GSB)
+ * The track_indices is the indices of tracks that the node at from_side and [0..chan_width-1] will drive 
+ * IMPORTANT: the track_indices are the indicies in the GSB context, but not the rr_graph!!!
+ * We separate the connections into two groups:
+ * Group 1: the routing tracks start from this GSB 
+ *          We will apply switch block patterns (SUBSET, UNIVERSAL, WILTON) 
+ * Group 2: the routing tracks do not start from this GSB (bypassing wires)
+ *          We will apply switch block patterns (SUBSET, UNIVERSAL, WILTON) 
+ *          but we will check the Switch Block (SB) population of these 
+ *          routing segments, and determine which requires connections
+ *          
+ *                         CHANY  CHANY  CHANY CHANY
+ *                          [0]    [1]    [2]   [3]
+ *                   start  yes    no     yes   no            
+ *        end             +-------------------------+           start    Group 1      Group 2
+ *         no    CHANX[0] |           TOP           |  CHANX[0]  yes   TOP/BOTTOM   TOP/BOTTOM
+ *                        |                         |                  CHANY[0,2]   CHANY[1,3]
+ *        yes    CHANX[1] |                         |  CHANX[1]  no
+ *                        |  LEFT           RIGHT   |
+ *         no    CHANX[2] |                         |  CHANX[2]  yes
+ *                        |                         |
+ *        yes    CHANX[3] |         BOTTOM          |  CHANX[3]  no
+ *                        +-------------------------+           
+ *                         CHANY  CHANY  CHANY CHANY
+ *                          [0]    [1]    [2]   [3]
+ *                   start  yes    no     yes   no            
+ *            
+ * The mapping is done in the following steps: (For each side of the GSB)
+ * 1. Build a list of tracks that will start from this side
+ *    if a track starts, its xlow/ylow is the same as the x,y of this gsb
+ * 2. Build a list of tracks on the other sides belonging to Group 1.
+ *    Take the example of RIGHT side, we will collect 
+ *    a. tracks that will end at the LEFT side 
+ *    b. tracks that will start at the TOP side
+ *    c. tracks that will start at the BOTTOM side
+ * 3. Apply switch block patterns to Group 1 (SUBSET, UNIVERSAL, WILTON) 
+ * 4. Build a list of tracks on the other sides belonging to Group 1.
+ *    Take the example of RIGHT side, we will collect 
+ *    a. tracks that will bypass at the TOP side
+ *    b. tracks that will bypass at the BOTTOM side
+ * 5. Apply switch block patterns to Group 2 (SUBSET, UNIVERSAL, WILTON) 
+ ***********************************************************************/
+t_track2track_map build_gsb_track_to_track_map(const RRGraph& rr_graph,
+                                               const RRGSB& rr_gsb,
+                                               const e_switch_block_type& sb_type, 
+                                               const int& Fs,
+                                               const e_switch_block_type& sb_subtype, 
+                                               const int& subFs,
+                                               const bool& wire_opposite_side,
+                                               const std::vector<t_segment_inf>& segment_inf) {
+  t_track2track_map track2track_map; /* [0..gsb_side][0..chan_width][track_indices] */
+
+  /* Categorize tracks into 3 groups: 
+   * (1) tracks will start here 
+   * (2) tracks will end here 
+   * (2) tracks will just pass through the SB */
+  t_track_group start_tracks; /* [0..gsb_side][track_indices] */
+  t_track_group end_tracks; /* [0..gsb_side][track_indices] */
+  t_track_group pass_tracks; /* [0..gsb_side][track_indices] */
+
+  /* resize to the number of sides */
+  start_tracks.resize(rr_gsb.get_num_sides());
+  end_tracks.resize(rr_gsb.get_num_sides());
+  pass_tracks.resize(rr_gsb.get_num_sides());
+
+  /* Walk through each side */
+  for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
+    SideManager side_manager(side);
+    e_side gsb_side = side_manager.get_side();
+    /* Build a list of tracks that will start from this side */
+    for (size_t inode = 0; inode < rr_gsb.get_chan_width(gsb_side); ++inode) {
+      /* We need to check Switch block population of this track 
+       * The track node will not be considered if there supposed to be no SB at this position 
+       */
+      if (false == is_gsb_in_track_sb_population(rr_graph, rr_gsb, gsb_side, inode, segment_inf)) {
+        continue; /* skip this node and go to the next */
+      }
+      /* check if this track will start from here */
+      enum e_track_status track_status = determine_track_status_of_gsb(rr_graph, rr_gsb, gsb_side, inode);
+
+      switch (track_status) {
+      case TRACK_START:
+        /* update starting track list */
+        start_tracks[side].push_back(inode);
+        break;
+      case TRACK_END:
+        /* Update end track list */
+        end_tracks[side].push_back(inode);
+        break;
+      case TRACK_PASS:
+        /* Update passing track list */
+        /* Note that the pass_track should be IN_PORT only !!! */
+        if (IN_PORT == rr_gsb.get_chan_node_direction(gsb_side, inode)) {
+          pass_tracks[side].push_back(inode);
+        }
+        break;
+      default:
+        VTR_LOGF_ERROR(__FILE__, __LINE__,
+                       "Invalid track status!\n");
+        exit(1);
+      }
+    }
+  }
+
+  /* Allocate track2track map */
+  track2track_map.resize(rr_gsb.get_num_sides());
+  for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
+    SideManager side_manager(side);
+    enum e_side gsb_side = side_manager.get_side();
+    /* allocate track2track_map[gsb_side] */
+    track2track_map[side].resize(rr_gsb.get_chan_width(gsb_side));
+    for (size_t inode = 0; inode < rr_gsb.get_chan_width(gsb_side); ++inode) {
+      /* allocate track2track_map[gsb_side][inode] */
+      track2track_map[side][inode].clear();
+    }
+  }
+
+  /* For Group 1: we build connections between end_tracks and start_tracks*/
+  build_gsb_one_group_track_to_track_map(rr_graph, rr_gsb, 
+                                         sb_type, Fs,
+                                         true, /* End tracks should always to wired to start tracks */ 
+                                         end_tracks, start_tracks,
+                                         track2track_map);
+
+  /* For Group 2: we build connections between end_tracks and start_tracks*/
+  /* Currently, I use the same Switch Block pattern for the passing tracks and end tracks,
+   * TODO: This can be improved with different patterns! 
+   */
+  build_gsb_one_group_track_to_track_map(rr_graph, rr_gsb, 
+                                         sb_subtype, subFs,
+                                         wire_opposite_side, /* Pass tracks may not be wired to start tracks */ 
+                                         pass_tracks, start_tracks, 
+                                         track2track_map);
+
+  return track2track_map;
+}
+
+/* Build a RRChan Object with the given channel type and coorindators */
+static 
+RRChan build_one_tileable_rr_chan(const vtr::Point<size_t>& chan_coordinate, 
+                                  const t_rr_type& chan_type, 
+                                  const RRGraph& rr_graph, 
+                                  const ChanNodeDetails& chan_details) {
+  std::vector<RRNodeId> chan_rr_nodes;
+
+  /* Create a rr_chan object and check if it is unique in the graph */
+  RRChan rr_chan;
+
+  /* Fill the information */
+  rr_chan.set_type(chan_type); 
+
+  /* Collect rr_nodes for this channel */
+  chan_rr_nodes = find_rr_graph_chan_nodes(rr_graph,
+                                           chan_coordinate.x(), chan_coordinate.y(),
+                                           chan_type);
+
+  /* Reserve */
+  /* rr_chan.reserve_node(size_t(chan_width)); */
+
+  /* Fill the rr_chan */  
+  for (size_t itrack = 0; itrack < chan_rr_nodes.size(); ++itrack) {
+    size_t iseg = chan_details.get_track_segment_id(itrack); 
+    rr_chan.add_node(rr_graph, chan_rr_nodes[itrack], RRSegmentId(iseg));
+  }
+
+  return rr_chan;
+}
+
+/***********************************************************************
+ * Build a General Switch Block (GSB) 
+ * which includes:
+ * [I] A Switch Box subckt consists of following ports:
+ * 1. Channel Y [x][y] inputs 
+ * 2. Channel X [x+1][y] inputs
+ * 3. Channel Y [x][y-1] outputs
+ * 4. Channel X [x][y] outputs
+ * 5. Grid[x][y+1] Right side outputs pins
+ * 6. Grid[x+1][y+1] Left side output pins
+ * 7. Grid[x+1][y+1] Bottom side output pins
+ * 8. Grid[x+1][y] Top side output pins
+ * 9. Grid[x+1][y] Left side output pins
+ * 10. Grid[x][y] Right side output pins
+ * 11. Grid[x][y] Top side output pins
+ * 12. Grid[x][y+1] Bottom side output pins
+ *
+ *    --------------          --------------
+ *    |            |   CBY    |            |
+ *    |    Grid    |  ChanY   |    Grid    |
+ *    |  [x][y+1]  | [x][y+1] | [x+1][y+1] |
+ *    |            |          |            |
+ *    --------------          --------------
+ *                  ----------
+ *     ChanX & CBX  | Switch |     ChanX 
+ *       [x][y]     |   Box  |    [x+1][y]
+ *                  | [x][y] |
+ *                  ----------
+ *    --------------          --------------
+ *    |            |          |            |
+ *    |    Grid    |  ChanY   |    Grid    |
+ *    |   [x][y]   |  [x][y]  |  [x+1][y]  |
+ *    |            |          |            |
+ *    --------------          --------------
+ * For channels chanY with INC_DIRECTION on the top side, they should be marked as outputs
+ * For channels chanY with DEC_DIRECTION on the top side, they should be marked as inputs
+ * For channels chanY with INC_DIRECTION on the bottom side, they should be marked as inputs
+ * For channels chanY with DEC_DIRECTION on the bottom side, they should be marked as outputs
+ * For channels chanX with INC_DIRECTION on the left side, they should be marked as inputs
+ * For channels chanX with DEC_DIRECTION on the left side, they should be marked as outputs
+ * For channels chanX with INC_DIRECTION on the right side, they should be marked as outputs
+ * For channels chanX with DEC_DIRECTION on the right side, they should be marked as inputs
+ *
+ * [II] A X-direction Connection Block [x][y]
+ * The connection block shares the same routing channel[x][y] with the Switch Block
+ * We just need to fill the ipin nodes at TOP and BOTTOM sides 
+ * as well as properly fill the ipin_grid_side information
+ * [III] A Y-direction Connection Block [x][y+1]
+ * The connection block shares the same routing channel[x][y+1] with the Switch Block
+ * We just need to fill the ipin nodes at LEFT and RIGHT sides 
+ * as well as properly fill the ipin_grid_side information
+ ***********************************************************************/
+RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, 
+                                const RRGraph& rr_graph,
+                                const std::vector<size_t>& device_chan_width, 
+                                const std::vector<t_segment_inf>& segment_inf,
+                                const vtr::Point<size_t>& gsb_coordinate) {
+  /* Create an object to return */
+  RRGSB rr_gsb;
+
+  /* Check */
+  VTR_ASSERT(gsb_coordinate.x() <= grids.width()); 
+  VTR_ASSERT(gsb_coordinate.y() <= grids.height()); 
+
+  /* Coordinator initialization */
+  rr_gsb.set_coordinate(gsb_coordinate.x(), gsb_coordinate.y());
+
+  /* Basic information*/
+  rr_gsb.init_num_sides(4); /* Fixed number of sides */
+
+  /* Find all rr_nodes of channels */
+  /* SideManager: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */
+  for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
+    /* Local variables inside this for loop */
+    SideManager side_manager(side);
+    vtr::Point<size_t> coordinate = rr_gsb.get_side_block_coordinate(side_manager.get_side());
+    RRChan rr_chan;
+    std::vector<std::vector<RRNodeId>> temp_opin_rr_nodes(2);
+    enum e_side opin_grid_side[2] = {NUM_SIDES, NUM_SIDES};
+    enum PORTS chan_dir_to_port_dir_mapping[2] = {OUT_PORT, IN_PORT}; /* 0: INC_DIRECTION => ?; 1: DEC_DIRECTION => ? */
+
+    /* Build a segment details, where we need the segment ids for building rr_chan  
+     * We do not care starting and ending points here, so set chan_side as NUM_SIDES 
+     */
+    ChanNodeDetails chanx_details = build_unidir_chan_node_details(device_chan_width[0], grids.width() - 1, 
+                                                                   NUM_SIDES, segment_inf); 
+    ChanNodeDetails chany_details = build_unidir_chan_node_details(device_chan_width[1], grids.height() - 1, 
+                                                                   NUM_SIDES, segment_inf); 
+
+    switch (side) {
+    case TOP: /* TOP = 0 */
+      /* For the bording, we should take special care */
+      if (gsb_coordinate.y() == grids.height() - 1) {
+        rr_gsb.clear_one_side(side_manager.get_side());
+        break;
+      }
+      /* Routing channels*/
+      /* SideManager: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */
+      /* Create a rr_chan object and check if it is unique in the graph */
+      rr_chan = build_one_tileable_rr_chan(coordinate, CHANY, rr_graph, chany_details);
+      chan_dir_to_port_dir_mapping[0] = OUT_PORT; /* INC_DIRECTION => OUT_PORT */
+      chan_dir_to_port_dir_mapping[1] =  IN_PORT; /* DEC_DIRECTION => IN_PORT */
+
+      /* Assign grid side of OPIN */
+      /* Grid[x][y+1] RIGHT side outputs pins */
+      opin_grid_side[0] = RIGHT;
+      /* Grid[x+1][y+1] left side outputs pins */
+      opin_grid_side[1] = LEFT; 
+
+      /* Build the Switch block: opin and opin_grid_side */
+      /* Include Grid[x][y+1] RIGHT side outputs pins */
+      temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes(rr_graph, grids, 
+                                                       gsb_coordinate.x(), gsb_coordinate.y() + 1,
+                                                       OPIN, opin_grid_side[0]);
+      /* Include Grid[x+1][y+1] Left side output pins */
+      temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes(rr_graph, grids, 
+                                                       gsb_coordinate.x() + 1, gsb_coordinate.y() + 1,
+                                                       OPIN, opin_grid_side[1]);
+
+      break;
+    case RIGHT: /* RIGHT = 1 */
+      /* For the bording, we should take special care */
+      if (gsb_coordinate.x() == grids.width() - 1) {
+        rr_gsb.clear_one_side(side_manager.get_side());
+        break;
+      }
+      /* Routing channels*/
+      /* SideManager: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */
+      /* Collect rr_nodes for Tracks for top: chany[x][y+1] */
+      /* Create a rr_chan object and check if it is unique in the graph */
+      rr_chan = build_one_tileable_rr_chan(coordinate, CHANX, rr_graph, chanx_details);
+      chan_dir_to_port_dir_mapping[0] = OUT_PORT; /* INC_DIRECTION => OUT_PORT */
+      chan_dir_to_port_dir_mapping[1] =  IN_PORT; /* DEC_DIRECTION => IN_PORT */
+
+      /* Assign grid side of OPIN */
+      /* Grid[x+1][y+1] BOTTOM side outputs pins */
+      opin_grid_side[0] = BOTTOM;
+      /* Grid[x+1][y] TOP side outputs pins */
+      opin_grid_side[1] = TOP;
+
+      /* Build the Switch block: opin and opin_grid_side */
+      /* include Grid[x+1][y+1] Bottom side output pins */
+      temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes(rr_graph, grids, 
+                                                       gsb_coordinate.x() + 1, gsb_coordinate.y() + 1,
+                                                       OPIN, opin_grid_side[0]);
+      /* include Grid[x+1][y] Top side output pins */
+      temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes(rr_graph, grids, 
+                                                       gsb_coordinate.x() + 1, gsb_coordinate.y(),
+                                                       OPIN, opin_grid_side[1]);
+      break;
+    case BOTTOM: /* BOTTOM = 2*/
+      /* For the bording, we should take special care */
+      if (gsb_coordinate.y() == 0) {
+        rr_gsb.clear_one_side(side_manager.get_side());
+        break;
+      }
+      /* Routing channels*/
+      /* SideManager: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */
+      /* Collect rr_nodes for Tracks for bottom: chany[x][y] */
+      /* Create a rr_chan object and check if it is unique in the graph */
+      rr_chan = build_one_tileable_rr_chan(coordinate, CHANY, rr_graph, chany_details);
+      chan_dir_to_port_dir_mapping[0] =  IN_PORT; /* INC_DIRECTION => IN_PORT */
+      chan_dir_to_port_dir_mapping[1] = OUT_PORT; /* DEC_DIRECTION => OUT_PORT */
+
+      /* Assign grid side of OPIN */
+      /* Grid[x+1][y] LEFT side outputs pins */
+      opin_grid_side[0] = LEFT;
+      /* Grid[x][y] RIGHT side outputs pins */
+      opin_grid_side[1] = RIGHT;
+
+      /* Build the Switch block: opin and opin_grid_side */
+      /* include Grid[x+1][y] Left side output pins */
+      temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes(rr_graph, grids, 
+                                                       gsb_coordinate.x() + 1, gsb_coordinate.y(),
+                                                       OPIN, opin_grid_side[0]);
+      /* include Grid[x][y] Right side output pins */
+      temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes(rr_graph, grids, 
+                                                       gsb_coordinate.x(), gsb_coordinate.y(),
+                                                       OPIN, opin_grid_side[1]);
+      break;
+    case LEFT: /* LEFT = 3 */
+      /* For the bording, we should take special care */
+      if (gsb_coordinate.x() == 0) {
+        rr_gsb.clear_one_side(side_manager.get_side());
+        break;
+      }
+      /* Routing channels*/
+      /* SideManager: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */
+      /* Collect rr_nodes for Tracks for left: chanx[x][y] */
+      /* Create a rr_chan object and check if it is unique in the graph */
+      rr_chan = build_one_tileable_rr_chan(coordinate, CHANX, rr_graph, chanx_details);
+      chan_dir_to_port_dir_mapping[0] =  IN_PORT; /* INC_DIRECTION => IN_PORT */
+      chan_dir_to_port_dir_mapping[1] = OUT_PORT; /* DEC_DIRECTION => OUT_PORT */
+
+      /* Grid[x][y+1] BOTTOM side outputs pins */
+      opin_grid_side[0] = BOTTOM;
+      /* Grid[x][y] TOP side outputs pins */
+      opin_grid_side[1] = TOP;
+
+      /* Build the Switch block: opin and opin_grid_side */
+      /* include Grid[x][y+1] Bottom side outputs pins */
+      temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes(rr_graph, grids, 
+                                                       gsb_coordinate.x(), gsb_coordinate.y() + 1,
+                                                       OPIN, opin_grid_side[0]);
+      /* include Grid[x][y] Top side output pins */
+      temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes(rr_graph, grids, 
+                                                       gsb_coordinate.x(), gsb_coordinate.y(),
+                                                       OPIN, opin_grid_side[1]);
+
+      break;
+    default:
+      VTR_LOGF_ERROR(__FILE__, __LINE__,
+                     "Invalid side index!\n");
+      exit(1);
+    }
+
+    /* Organize a vector of port direction */
+    if (0 < rr_chan.get_chan_width()) {
+      std::vector<enum PORTS> rr_chan_dir;
+      rr_chan_dir.resize(rr_chan.get_chan_width());
+      for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) {
+        /* Identify the directionality, record it in rr_node_direction */
+        if (INC_DIRECTION == rr_graph.node_direction(rr_chan.get_node(itrack))) {
+          rr_chan_dir[itrack] = chan_dir_to_port_dir_mapping[0];
+        } else {
+          VTR_ASSERT(DEC_DIRECTION == rr_graph.node_direction(rr_chan.get_node(itrack)));
+          rr_chan_dir[itrack] = chan_dir_to_port_dir_mapping[1];
+        }
+      }
+      /* Fill chan_rr_nodes */
+      rr_gsb.add_chan_node(side_manager.get_side(), rr_chan, rr_chan_dir);
+    }
+
+    /* Fill opin_rr_nodes */
+    /* Copy from temp_opin_rr_node to opin_rr_node */
+    for (const RRNodeId& inode : temp_opin_rr_nodes[0]) {
+      /* Grid[x+1][y+1] Bottom side outputs pins */
+      rr_gsb.add_opin_node(inode, side_manager.get_side());
+    }
+    for (const RRNodeId& inode : temp_opin_rr_nodes[1]) {
+      /* Grid[x+1][y] TOP side outputs pins */
+      rr_gsb.add_opin_node(inode, side_manager.get_side());
+    }
+
+    /* Clean ipin_rr_nodes */
+    /* We do not have any IPIN for a Switch Block */
+    rr_gsb.clear_ipin_nodes(side_manager.get_side());
+
+    /* Clear the temp data */
+    temp_opin_rr_nodes[0].clear();
+    temp_opin_rr_nodes[1].clear();
+    opin_grid_side[0] = NUM_SIDES;
+    opin_grid_side[1] = NUM_SIDES;
+  }
+
+  /* SideManager: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */
+  for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
+    /* Local variables inside this for loop */
+    SideManager side_manager(side);
+    size_t ix; 
+    size_t iy; 
+    enum e_side chan_side;
+    std::vector<RRNodeId> temp_ipin_rr_nodes;
+    enum e_side ipin_rr_node_grid_side;
+   
+    switch (side) {
+    case TOP: /* TOP = 0 */
+      /* For the bording, we should take special care */
+      /* Check if left side chan width is 0 or not */
+      chan_side = LEFT;
+      /* Build the connection block: ipin and ipin_grid_side */
+      /* BOTTOM side INPUT Pins of Grid[x][y+1] */
+      ix = rr_gsb.get_sb_x(); 
+      iy = rr_gsb.get_sb_y() + 1; 
+      ipin_rr_node_grid_side = BOTTOM; 
+      break;
+    case RIGHT: /* RIGHT = 1 */
+      /* For the bording, we should take special care */
+      /* Check if TOP side chan width is 0 or not */
+      chan_side = TOP;
+      /* Build the connection block: ipin and ipin_grid_side */
+      /* LEFT side INPUT Pins of Grid[x+1][y+1] */
+      ix = rr_gsb.get_sb_x() + 1; 
+      iy = rr_gsb.get_sb_y() + 1; 
+      ipin_rr_node_grid_side = LEFT; 
+      break;
+    case BOTTOM: /* BOTTOM = 2*/
+      /* For the bording, we should take special care */
+      /* Check if left side chan width is 0 or not */
+      chan_side = LEFT;
+      /* Build the connection block: ipin and ipin_grid_side */
+      /* TOP side INPUT Pins of Grid[x][y] */
+      ix = rr_gsb.get_sb_x(); 
+      iy = rr_gsb.get_sb_y(); 
+      ipin_rr_node_grid_side = TOP; 
+      break;
+    case LEFT: /* LEFT = 3 */
+      /* For the bording, we should take special care */
+      /* Check if left side chan width is 0 or not */
+      chan_side = TOP;
+      /* Build the connection block: ipin and ipin_grid_side */
+      /* RIGHT side INPUT Pins of Grid[x][y+1] */
+      ix = rr_gsb.get_sb_x(); 
+      iy = rr_gsb.get_sb_y() + 1; 
+      ipin_rr_node_grid_side = RIGHT; 
+      break;
+    default:
+      VTR_LOGF_ERROR(__FILE__, __LINE__,
+                     "Invalid side index!\n");
+      exit(1);
+    }
+    
+    /* If there is no channel at this side, we skip ipin_node annotation */
+    if (0 == rr_gsb.get_chan_width(chan_side)) {
+      continue;
+    }
+    /* Collect IPIN rr_nodes*/ 
+    temp_ipin_rr_nodes = find_rr_graph_grid_nodes(rr_graph, grids, 
+                                                  ix, iy, IPIN, ipin_rr_node_grid_side);
+    /* Fill the ipin nodes of RRGSB */ 
+    for (const RRNodeId& inode : temp_ipin_rr_nodes) {
+      rr_gsb.add_ipin_node(inode, side_manager.get_side());
+    }
+    /* Clear the temp data */
+    temp_ipin_rr_nodes.clear();
+  }
+
+  return rr_gsb;
+}
+
+/************************************************************************
+ * Create edges for each rr_node of a General Switch Blocks (GSB):
+ * 1. create edges between CHANX | CHANY and IPINs (connections inside connection blocks) 
+ * 2. create edges between OPINs, CHANX and CHANY (connections inside switch blocks) 
+ * 3. create edges between OPINs and IPINs (direct-connections) 
+ ***********************************************************************/
+void build_edges_for_one_tileable_rr_gsb(RRGraph& rr_graph, 
+                                         const RRGSB& rr_gsb,
+                                         const t_track2pin_map& track2ipin_map,
+                                         const t_pin2track_map& opin2track_map,
+                                         const t_track2track_map& track2track_map,
+                                         const vtr::vector<RRNodeId, RRSwitchId> rr_node_driver_switches) {
+  
+  /* Walk through each sides */ 
+  for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
+    SideManager side_manager(side);
+    enum e_side gsb_side = side_manager.get_side();
+
+    /* Find OPINs */  
+    for (size_t inode = 0; inode < rr_gsb.get_num_opin_nodes(gsb_side); ++inode) {
+      const RRNodeId& opin_node = rr_gsb.get_opin_node(gsb_side, inode); 
+
+      /* 1. create edges between OPINs and CHANX|CHANY, using opin2track_map */
+      /* add edges to the opin_node */
+      for (const RRNodeId& track_node : opin2track_map[gsb_side][inode]) {
+        rr_graph.create_edge(opin_node, track_node, rr_node_driver_switches[track_node]);
+      }
+    }
+
+    /* Find  CHANX or CHANY */
+    /* For TRACKs to IPINs, we only care LEFT and TOP sides 
+     * Skip RIGHT and BOTTOM for the ipin2track_map since they should be handled in other GSBs 
+     */
+    if ( (side_manager.get_side() == rr_gsb.get_cb_chan_side(CHANX))
+      || (side_manager.get_side() == rr_gsb.get_cb_chan_side(CHANY)) ) {
+      /* 2. create edges between CHANX|CHANY and IPINs, using ipin2track_map */
+      for (size_t inode = 0; inode < rr_gsb.get_chan_width(gsb_side); ++inode) {
+        const RRNodeId& chan_node = rr_gsb.get_chan_node(gsb_side, inode); 
+        for (const RRNodeId& ipin_node : track2ipin_map[gsb_side][inode]) {
+          rr_graph.create_edge(chan_node, ipin_node, rr_node_driver_switches[ipin_node]);
+        }
+      }
+    }
+
+    /* 3. create edges between CHANX|CHANY and CHANX|CHANY, using track2track_map */
+    for (size_t inode = 0; inode < rr_gsb.get_chan_width(gsb_side); ++inode) {
+      const RRNodeId& chan_node = rr_gsb.get_chan_node(gsb_side, inode); 
+      for (const RRNodeId& track_node : track2track_map[gsb_side][inode]) {
+        rr_graph.create_edge(chan_node, track_node, rr_node_driver_switches[track_node]);
+      }
+    }
+  }
+}
+
+/************************************************************************
+ * Build track2ipin_map for an IPIN  
+ * 1. build a list of routing tracks which are allowed for connections
+ *    We will check the Connection Block (CB) population of each routing track. 
+ *    By comparing current chan_y - ylow, we can determine if a CB connection
+ *    is required for each routing track
+ * 2. Divide the routing tracks by segment types, so that we can balance
+ *    the connections between IPINs and different types of routing tracks.
+ * 3. Scale the Fc of each pin to the actual number of routing tracks
+ *    actual_Fc = (int) Fc * num_tracks / chan_width
+ ***********************************************************************/
+static 
+void build_gsb_one_ipin_track2pin_map(const RRGraph& rr_graph, 
+                                      const RRGSB& rr_gsb, 
+                                      const enum e_side& ipin_side, 
+                                      const size_t& ipin_node_id, 
+                                      const size_t& Fc, 
+                                      const size_t& offset, 
+                                      const std::vector<t_segment_inf>& segment_inf, 
+                                      t_track2pin_map& track2ipin_map) {
+  /* Get a list of segment_ids*/
+  enum e_side chan_side = rr_gsb.get_cb_chan_side(ipin_side);
+  SideManager chan_side_manager(chan_side);
+  std::vector<RRSegmentId> seg_list = rr_gsb.get_chan_segment_ids(chan_side);
+  size_t chan_width = rr_gsb.get_chan_width(chan_side);
+  SideManager ipin_side_manager(ipin_side);
+  const RRNodeId& ipin_node = rr_gsb.get_ipin_node(ipin_side, ipin_node_id);
+
+  for (size_t iseg = 0; iseg < seg_list.size(); ++iseg) {
+    /* Get a list of node that have the segment id */
+    std::vector<size_t> track_list = rr_gsb.get_chan_node_ids_by_segment_ids(chan_side, seg_list[iseg]);
+    /* Refine the track_list: keep those will have connection blocks in the GSB */
+    std::vector<size_t> actual_track_list;
+    for (size_t inode = 0; inode < track_list.size(); ++inode) {
+      /* Check if tracks allow connection blocks in the GSB*/
+      if (false == is_gsb_in_track_cb_population(rr_graph, rr_gsb, chan_side, track_list[inode], segment_inf)) {
+         continue; /* Bypass condition */
+      }
+      /* Push the node to actual_track_list  */
+      actual_track_list.push_back(track_list[inode]);
+    }
+    /* Check the actual track list */
+    VTR_ASSERT(0 == actual_track_list.size() % 2);
+   
+    /* Scale Fc  */
+    int actual_Fc = std::ceil((float)Fc * (float)actual_track_list.size() / (float)chan_width); 
+    /* Minimum Fc should be 2 : ensure we will connect to a pair of routing tracks */
+    actual_Fc = std::max(1, actual_Fc);
+    /* Compute the step between two connection from this IPIN to tracks: 
+     * step = W' / Fc', W' and Fc' are the adapted W and Fc from actual_track_list and Fc_in 
+     */
+    size_t track_step = std::floor((float)actual_track_list.size() / (float)actual_Fc);
+    /* Make sure step should be at least 2 */
+    track_step = std::max(1, (int)track_step);
+    /* Adapt offset to the range of actual_track_list */
+    size_t actual_offset = offset % actual_track_list.size();
+    /* rotate the track list by an offset */
+    if (0 < actual_offset) {
+      std::rotate(actual_track_list.begin(), actual_track_list.begin() + actual_offset, actual_track_list.end());   
+    }
+
+    /* Assign tracks: since we assign 2 track per round, we increment itrack by 2* step  */
+    int track_cnt = 0;
+    /* Keep assigning until we meet the Fc requirement */
+    for (size_t itrack = 0; itrack < actual_track_list.size(); itrack = itrack + 2 * track_step) {
+      /* Update pin2track map */ 
+      size_t chan_side_index = chan_side_manager.to_size_t();
+      /* itrack may exceed the size of actual_track_list, adapt it */
+      size_t actual_itrack = itrack % actual_track_list.size();
+      /* track_index may exceed the chan_width(), adapt it */
+      size_t track_index = actual_track_list[actual_itrack] % chan_width;
+
+      track2ipin_map[chan_side_index][track_index].push_back(ipin_node);
+
+      /* track_index may exceed the chan_width(), adapt it */
+      track_index = (actual_track_list[actual_itrack] + 1) % chan_width;
+
+      track2ipin_map[chan_side_index][track_index].push_back(ipin_node);
+
+      track_cnt += 2;
+    }
+
+    /* Ensure the number of tracks is similar to Fc */
+    /* Give a warning if Fc is < track_cnt */
+    /*
+    if (actual_Fc != track_cnt) {
+      vpr_printf(TIO_MESSAGE_INFO, 
+                 "IPIN Node(%lu) will have a different Fc(=%lu) than specified(=%lu)!\n",
+                 ipin_node - rr_graph->rr_node, track_cnt, actual_Fc);
+    }
+    */
+  }
+}
+
+/************************************************************************
+ * Build opin2track_map for an OPIN  
+ * 1. build a list of routing tracks which are allowed for connections
+ *    We will check the Switch Block (SB) population of each routing track. 
+ *    By comparing current chan_y - ylow, we can determine if a SB connection
+ *    is required for each routing track
+ * 2. Divide the routing tracks by segment types, so that we can balance
+ *    the connections between OPINs and different types of routing tracks.
+ * 3. Scale the Fc of each pin to the actual number of routing tracks
+ *    actual_Fc = (int) Fc * num_tracks / chan_width
+ ***********************************************************************/
+static 
+void build_gsb_one_opin_pin2track_map(const RRGraph& rr_graph, 
+                                      const RRGSB& rr_gsb, 
+                                      const enum e_side& opin_side, 
+                                      const size_t& opin_node_id, 
+                                      const size_t& Fc, 
+                                      const size_t& offset, 
+                                      const std::vector<t_segment_inf>& segment_inf, 
+                                      t_pin2track_map& opin2track_map) {
+  /* Get a list of segment_ids*/
+  std::vector<RRSegmentId> seg_list = rr_gsb.get_chan_segment_ids(opin_side);
+  enum e_side chan_side = opin_side;
+  size_t chan_width = rr_gsb.get_chan_width(chan_side);
+  SideManager opin_side_manager(opin_side);
+
+  for (size_t iseg = 0; iseg < seg_list.size(); ++iseg) {
+    /* Get a list of node that have the segment id */
+    std::vector<size_t> track_list = rr_gsb.get_chan_node_ids_by_segment_ids(chan_side, seg_list[iseg]);
+    /* Refine the track_list: keep those will have connection blocks in the GSB */
+    std::vector<size_t> actual_track_list;
+    for (size_t inode = 0; inode < track_list.size(); ++inode) {
+      /* Check if tracks allow connection blocks in the GSB*/
+      if (false == is_gsb_in_track_sb_population(rr_graph, rr_gsb, chan_side, 
+                                                 track_list[inode], segment_inf)) {
+         continue; /* Bypass condition */
+      }
+      if (TRACK_START != determine_track_status_of_gsb(rr_graph, rr_gsb, chan_side, track_list[inode])) {
+         continue; /* Bypass condition */
+      }
+      /* Push the node to actual_track_list  */
+      actual_track_list.push_back(track_list[inode]);
+    }
+
+    /* Go the next segment if offset is zero or actual_track_list is empty */    
+    if (0 == actual_track_list.size()) {
+      continue;
+    }
+   
+    /* Scale Fc  */
+    int actual_Fc = std::ceil((float)Fc * (float)actual_track_list.size() / (float)chan_width); 
+    /* Minimum Fc should be 1 : ensure we will drive 1 routing track */
+    actual_Fc = std::max(1, actual_Fc);
+    /* Compute the step between two connection from this IPIN to tracks: 
+     * step = W' / Fc', W' and Fc' are the adapted W and Fc from actual_track_list and Fc_in 
+    */
+    size_t track_step = std::floor((float)actual_track_list.size() / (float)actual_Fc);
+    /* Track step mush be a multiple of 2!!!*/
+    /* Make sure step should be at least 1 */
+    track_step = std::max(1, (int)track_step);
+    /* Adapt offset to the range of actual_track_list */
+    size_t actual_offset = offset % actual_track_list.size();
+
+    /* No need to rotate if offset is zero */    
+    if (0 < actual_offset) {
+      /* rotate the track list by an offset */
+      std::rotate(actual_track_list.begin(), actual_track_list.begin() + actual_offset, actual_track_list.end());   
+    }
+
+    /* Assign tracks  */
+    int track_cnt = 0;
+    /* Keep assigning until we meet the Fc requirement */
+    for (size_t itrack = 0; itrack < actual_track_list.size(); itrack = itrack + track_step) {
+      /* Update pin2track map */ 
+      size_t opin_side_index = opin_side_manager.to_size_t();
+      /* itrack may exceed the size of actual_track_list, adapt it */
+      size_t actual_itrack = itrack % actual_track_list.size();
+      size_t track_index = actual_track_list[actual_itrack];
+      const RRNodeId& track_rr_node_index = rr_gsb.get_chan_node(chan_side, track_index);
+      opin2track_map[opin_side_index][opin_node_id].push_back(track_rr_node_index);
+      /* update track counter */
+      track_cnt++;
+      /* Stop when we have enough Fc: this may lead to some tracks have zero drivers. 
+       * So I comment it. And we just make sure its track_cnt >= actual_Fc
+      if (actual_Fc == track_cnt) {
+        break;
+      }
+      */
+    }
+
+    /* Ensure the number of tracks is similar to Fc */
+    /* Give a warning if Fc is < track_cnt */
+    /*
+    if (actual_Fc != track_cnt) {
+      vpr_printf(TIO_MESSAGE_INFO, 
+                 "OPIN Node(%lu) will have a different Fc(=%lu) than specified(=%lu)!\n",
+                 opin_node_id, track_cnt, actual_Fc);
+    }
+    */
+  }
+  
+  return;
+}
+
+
+/************************************************************************
+ * Build the track_to_ipin_map[gsb_side][0..chan_width-1][ipin_indices] 
+ * based on the existing routing resources in the General Switch Block (GSB)
+ * This function supports both X-directional and Y-directional tracks 
+ * The mapping is done in the following steps:
+ * 1. Build ipin_to_track_map[gsb_side][0..num_ipin_nodes-1][track_indices]
+ *    For each IPIN, we ensure at least one connection to the tracks.
+ *    Then, we assign IPINs to tracks evenly while satisfying the actual_Fc 
+ * 2. Convert the ipin_to_track_map to track_to_ipin_map
+ ***********************************************************************/
+t_track2pin_map build_gsb_track_to_ipin_map(const RRGraph& rr_graph,
+                                            const RRGSB& rr_gsb, 
+                                            const DeviceGrid& grids, 
+                                            const std::vector<t_segment_inf>& segment_inf, 
+                                            int** Fc_in) {
+  t_track2pin_map track2ipin_map;
+  /* Resize the matrix */ 
+  track2ipin_map.resize(rr_gsb.get_num_sides());
+  
+  /* offset counter: it aims to balance the track-to-IPIN for each connection block */
+  size_t offset_size = 0;
+  std::vector<size_t> offset;
+  for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
+    SideManager side_manager(side);
+    enum e_side ipin_side = side_manager.get_side();
+    /* Get the chan_side */
+    enum e_side chan_side = rr_gsb.get_cb_chan_side(ipin_side);
+    SideManager chan_side_manager(chan_side);
+    /* resize offset to the maximum chan_side*/
+    offset_size = std::max(offset_size, chan_side_manager.to_size_t() + 1);
+  }
+  /* Initial offset */
+  offset.resize(offset_size);
+  offset.assign(offset.size(), 0);
+     
+  /* Walk through each side */
+  for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
+    SideManager side_manager(side);
+    enum e_side ipin_side = side_manager.get_side();
+    /* Get the chan_side */
+    enum e_side chan_side = rr_gsb.get_cb_chan_side(ipin_side);
+    SideManager chan_side_manager(chan_side);
+    /* This track2pin mapping is for Connection Blocks, so we only care two sides! */
+    /* Get channel width and resize the matrix */
+    size_t chan_width = rr_gsb.get_chan_width(chan_side);
+    track2ipin_map[chan_side_manager.to_size_t()].resize(chan_width); 
+    /* Find the ipin/opin nodes */
+    for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(ipin_side); ++inode) {
+      const RRNodeId& ipin_node = rr_gsb.get_ipin_node(ipin_side, inode);
+      /* Skip EMPTY type */
+      if (true == is_empty_type(grids[rr_graph.node_xlow(ipin_node)][rr_graph.node_ylow(ipin_node)].type)) {
+        continue;
+      }
+      int grid_type_index = grids[rr_graph.node_xlow(ipin_node)][rr_graph.node_ylow(ipin_node)].type->index; 
+      /* Get Fc of the ipin */
+      int ipin_Fc = Fc_in[grid_type_index][rr_graph.node_pin_num(ipin_node)];
+      /* skip Fc = 0 */
+      if ( (-1 == ipin_Fc)
+        || (0 == ipin_Fc) ) { 
+        continue;
+      }
+      /* Build track2ipin_map for this IPIN */
+      build_gsb_one_ipin_track2pin_map(rr_graph, rr_gsb, ipin_side, inode, ipin_Fc, 
+                                       /* Give an offset for the first track that this ipin will connect to */
+                                       offset[chan_side_manager.to_size_t()], 
+                                       segment_inf, track2ipin_map);
+      /* update offset */
+      offset[chan_side_manager.to_size_t()] += 2;
+      //printf("offset[%lu]=%lu\n", chan_side_manager.to_size_t(), offset[chan_side_manager.to_size_t()]);
+    }
+  }
+
+  return track2ipin_map;
+}
+
+/************************************************************************
+ * Build the opin_to_track_map[gsb_side][0..num_opin_nodes-1][track_indices] 
+ * based on the existing routing resources in the General Switch Block (GSB)
+ * This function supports both X-directional and Y-directional tracks 
+ * The mapping is done in the following steps:
+ * 1. Build a list of routing tracks whose starting points locate at this GSB
+ *    (xlow - gsb_x == 0)
+ * 2. Divide the routing tracks by segment types, so that we can balance
+ *    the connections between OPINs and different types of routing tracks.
+ * 3. Scale the Fc of each pin to the actual number of routing tracks
+ *    actual_Fc = (int) Fc * num_tracks / chan_width
+ ***********************************************************************/
+t_pin2track_map build_gsb_opin_to_track_map(const RRGraph& rr_graph,
+                                            const RRGSB& rr_gsb, 
+                                            const DeviceGrid& grids, 
+                                            const std::vector<t_segment_inf>& segment_inf, 
+                                            int** Fc_out) {
+  t_pin2track_map opin2track_map;
+  /* Resize the matrix */ 
+  opin2track_map.resize(rr_gsb.get_num_sides());
+  
+  /* offset counter: it aims to balance the OPIN-to-track for each switch block */
+  std::vector<size_t> offset;
+  /* Get the chan_side: which is the same as the opin side  */
+  offset.resize(rr_gsb.get_num_sides());
+  /* Initial offset */
+  offset.assign(offset.size(), 0);
+     
+  /* Walk through each side */
+  for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
+    SideManager side_manager(side);
+    enum e_side opin_side = side_manager.get_side();
+    /* Get the chan_side */
+    /* This track2pin mapping is for Connection Blocks, so we only care two sides! */
+    /* Get channel width and resize the matrix */
+    size_t num_opin_nodes = rr_gsb.get_num_opin_nodes(opin_side);
+    opin2track_map[side].resize(num_opin_nodes); 
+    /* Find the ipin/opin nodes */
+    for (size_t inode = 0; inode < num_opin_nodes; ++inode) {
+      const RRNodeId& opin_node = rr_gsb.get_opin_node(opin_side, inode);
+      /* Skip EMPTY type */
+      if (true == is_empty_type(grids[rr_graph.node_xlow(opin_node)][rr_graph.node_ylow(opin_node)].type)) {
+        continue;
+      }
+      int grid_type_index = grids[rr_graph.node_xlow(opin_node)][rr_graph.node_ylow(opin_node)].type->index; 
+      /* Get Fc of the ipin */
+      int opin_Fc = Fc_out[grid_type_index][rr_graph.node_pin_num(opin_node)];
+      /* skip Fc = 0 or unintialized, those pins are in the <directlist> */
+      if ( (-1 == opin_Fc)
+        || (0 == opin_Fc) ) { 
+        continue;
+      }
+      /* Build track2ipin_map for this IPIN */
+      build_gsb_one_opin_pin2track_map(rr_graph, rr_gsb, opin_side, inode, opin_Fc, 
+                                       /* Give an offset for the first track that this ipin will connect to */
+                                       offset[side_manager.to_size_t()], 
+                                       segment_inf, opin2track_map);
+      /* update offset: aim to rotate starting tracks by 1*/
+      offset[side_manager.to_size_t()] += 1;
+    }
+
+    /* Check:
+     * 1. We want to ensure that each OPIN will drive at least one track
+     * 2. We want to ensure that each track will be driven by at least 1 OPIN */
+  }
+
+  return opin2track_map;
+}
+
+} /* end namespace openfpga */
diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h
new file mode 100755
index 000000000..170249f74
--- /dev/null
+++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h
@@ -0,0 +1,80 @@
+#ifndef TILEABLE_RR_GRAPH_GSB_H
+#define TILEABLE_RR_GRAPH_GSB_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <vector>
+
+#include "vtr_vector.h"
+#include "vtr_geometry.h"
+
+#include "physical_types.h"
+#include "device_grid.h"
+
+#include "rr_gsb.h"
+#include "rr_graph_obj.h"
+#include "clb2clb_directs.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/************************************************************************
+ * Data stuctures related to the functions 
+ ***********************************************************************/
+typedef std::vector<std::vector<std::vector<RRNodeId>>> t_track2track_map;
+typedef std::vector<std::vector<std::vector<RRNodeId>>> t_track2pin_map;
+typedef std::vector<std::vector<std::vector<RRNodeId>>> t_pin2track_map;
+
+/************************************************************************
+ * Functions 
+ ***********************************************************************/
+t_track2track_map build_gsb_track_to_track_map(const RRGraph& rr_graph,
+                                               const RRGSB& rr_gsb,
+                                               const e_switch_block_type& sb_type, 
+                                               const int& Fs,
+                                               const e_switch_block_type& sb_subtype, 
+                                               const int& subFs,
+                                               const bool& wire_opposite_side,
+                                               const std::vector<t_segment_inf>& segment_inf);
+
+RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, 
+                                const RRGraph& rr_graph,
+                                const std::vector<size_t>& device_chan_width, 
+                                const std::vector<t_segment_inf>& segment_inf,
+                                const vtr::Point<size_t>& gsb_coordinate);
+
+void build_edges_for_one_tileable_rr_gsb(RRGraph& rr_graph, 
+                                         const RRGSB& rr_gsb,
+                                         const t_track2pin_map& track2ipin_map,
+                                         const t_pin2track_map& opin2track_map,
+                                         const t_track2track_map& track2track_map,
+                                         const vtr::vector<RRNodeId, RRSwitchId> rr_node_driver_switches);
+
+t_track2pin_map build_gsb_track_to_ipin_map(const RRGraph& rr_graph,
+                                            const RRGSB& rr_gsb, 
+                                            const DeviceGrid& grids, 
+                                            const std::vector<t_segment_inf>& segment_inf, 
+                                            int** Fc_in);
+
+t_pin2track_map build_gsb_opin_to_track_map(const RRGraph& rr_graph,
+                                            const RRGSB& rr_gsb, 
+                                            const DeviceGrid& grids, 
+                                            const std::vector<t_segment_inf>& segment_inf, 
+                                            int** Fc_out);
+
+void build_direct_connections_for_one_gsb(RRGraph& rr_graph,
+                                          const DeviceGrid& grids,
+                                          const vtr::Point<size_t>& from_grid_coordinate,
+                                          const RRSwitchId& delayless_switch, 
+                                          const std::vector<t_direct_inf>& directs, 
+                                          const std::vector<t_clb_to_clb_directs>& clb_to_clb_directs);
+
+} /* end namespace openfpga */
+
+#endif
+

From de62ce8872757347c2e05dc905aa8843e392fd60 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 5 Mar 2020 15:34:04 -0700
Subject: [PATCH 254/645] add node builder for tileable rr_graph builder

---
 .../rr_graph_builder_utils.cpp                | 190 ++++++++++
 .../rr_graph_builder_utils.h                  |  18 +
 vpr/src/tileable_rr_graph/rr_gsb.h            |  10 +-
 .../tileable_chan_details_builder.cpp         |  40 +--
 .../tileable_chan_details_builder.h           |   6 +-
 .../tileable_rr_graph_gsb.cpp                 |   4 +-
 .../tileable_rr_graph_node_builder.cpp        | 340 ++++++++++++++++++
 .../tileable_rr_graph_node_builder.h          |  31 ++
 8 files changed, 607 insertions(+), 32 deletions(-)
 create mode 100644 vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp
 create mode 100644 vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h

diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp
index 209d8a80b..47926e8c7 100644
--- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp
+++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp
@@ -117,6 +117,196 @@ size_t get_grid_num_classes(const t_grid_tile& cur_grid,
   return num_classes;
 }
 
+/************************************************************************
+ * Idenfity if a X-direction routing channel exist in the fabric
+ * This could be entirely possible that a routig channel
+ * is in the middle of a multi-width and multi-height grid
+ *
+ * As the chanx always locates on top of a grid with the same coord
+ *
+ *     +----------+
+ *     |   CHANX  |
+ *     |  [x][y]  |
+ *     +----------+
+ *
+ *     +----------+
+ *     |   Grid   |   height_offset = height - 1
+ *     |  [x][y]  |
+ *     +----------+
+ *
+ *     +----------+
+ *     |  Grid    |   height_offset = height - 2
+ *     | [x][y-1] |
+ *     +----------+
+ *  If the CHANX is in the middle of a multi-width and multi-height grid
+ *  it should locate at a grid whose height_offset is lower than the its height defined in physical_tile
+ *  When height_offset == height - 1, it means that the grid is at the top side of this multi-width and multi-height block
+ ***********************************************************************/
+bool is_chanx_exist(const DeviceGrid& grids,
+                    const vtr::Point<size_t>& chanx_coord) {
+  return (grids[chanx_coord.x()][chanx_coord.y()].height_offset == grids[chanx_coord.x()][chanx_coord.y()].type->height - 1);
+}
+
+/************************************************************************
+ * Idenfity if a Y-direction routing channel exist in the fabric
+ * This could be entirely possible that a routig channel
+ * is in the middle of a multi-width and multi-height grid
+ *
+ * As the chany always locates on right of a grid with the same coord
+ *
+ * +-----------+  +---------+  +--------+
+ * |   Grid    |  |  Grid   |  |  CHANY |
+ * | [x-1][y]  |  | [x][y]  |  | [x][y] |
+ * +-----------+  +---------+  +--------+
+ *  width_offset   width_offset
+ *  = width - 2   = width -1
+ *  If the CHANY is in the middle of a multi-width and multi-height grid
+ *  it should locate at a grid whose width_offset is lower than the its width defined in physical_tile
+ *  When height_offset == height - 1, it means that the grid is at the top side of this multi-width and multi-height block
+ ***********************************************************************/
+bool is_chany_exist(const DeviceGrid& grids,
+                    const vtr::Point<size_t>& chany_coord) {
+  return (grids[chany_coord.x()][chany_coord.y()].width_offset == grids[chany_coord.y()][chany_coord.y()].type->width - 1);
+}
+
+/************************************************************************
+ * Identify if a X-direction routing channel is at the right side of a 
+ * multi-height grid
+ *
+ *     +-----------------+
+ *     |                 |
+ *     |                 |  +-------------+
+ *     |      Grid       |  |   CHANX     |
+ *     |    [x-1][y]     |  |   [x][y]    |
+ *     |                 |  +-------------+
+ *     |                 |
+ *     +-----------------+
+ ***********************************************************************/
+bool is_chanx_right_to_multi_height_grid(const DeviceGrid& grids,
+                                         const vtr::Point<size_t>& chanx_coord) {
+  VTR_ASSERT(0 < chanx_coord.x());
+  if (1 == chanx_coord.x()) {
+    /* This is already the LEFT side of FPGA fabric,
+     * it is the same results as chanx is right to a multi-height grid
+     */
+    return true;
+  }
+  
+  /* We check the left neighbor of chanx, if it does not exist, the chanx is left to a multi-height grid */
+  vtr::Point<size_t> left_chanx_coord(chanx_coord.x() - 1, chanx_coord.y());
+  if (false == is_chanx_exist(grids, left_chanx_coord)) {
+    return true;
+  }
+
+  return false;
+}
+
+/************************************************************************
+ * Identify if a X-direction routing channel is at the left side of a 
+ * multi-height grid
+ *
+ *                            +-----------------+
+ *                            |                 |
+ *        +---------------+   |                 | 
+ *        |    CHANX      |   |      Grid       | 
+ *        |    [x][y]     |   |    [x+1][y]     | 
+ *        +---------------+   |                 |
+ *                            |                 |
+ *                            +-----------------+
+ ***********************************************************************/
+bool is_chanx_left_to_multi_height_grid(const DeviceGrid& grids,
+                                        const vtr::Point<size_t>& chanx_coord) {
+  VTR_ASSERT(chanx_coord.x() < grids.width() - 1);
+  if (grids.width() - 2 == chanx_coord.x()) {
+    /* This is already the RIGHT side of FPGA fabric,
+     * it is the same results as chanx is right to a multi-height grid
+     */
+    return true;
+  }
+  
+  /* We check the right neighbor of chanx, if it does not exist, the chanx is left to a multi-height grid */
+  vtr::Point<size_t> right_chanx_coord(chanx_coord.x() + 1, chanx_coord.y());
+  if (false == is_chanx_exist(grids, right_chanx_coord)) {
+    return true;
+  }
+
+  return false;
+}
+
+/************************************************************************
+ * Identify if a Y-direction routing channel is at the top side of a 
+ * multi-width grid
+ * 
+ *          +--------+
+ *          | CHANY  |
+ *          | [x][y] | 
+ *          +--------+
+ *
+ *     +-----------------+
+ *     |                 |
+ *     |                 | 
+ *     |      Grid       | 
+ *     |    [x-1][y]     | 
+ *     |                 | 
+ *     |                 |
+ *     +-----------------+
+ ***********************************************************************/
+bool is_chany_top_to_multi_width_grid(const DeviceGrid& grids,
+                                      const vtr::Point<size_t>& chany_coord) {
+  VTR_ASSERT(0 < chany_coord.y());
+  if (1 == chany_coord.y()) {
+    /* This is already the BOTTOM side of FPGA fabric,
+     * it is the same results as chany is at the top of a multi-width grid
+     */
+    return true;
+  }
+  
+  /* We check the bottom neighbor of chany, if it does not exist, the chany is left to a multi-height grid */
+  vtr::Point<size_t> bottom_chany_coord(chany_coord.x(), chany_coord.y() - 1);
+  if (false == is_chany_exist(grids, bottom_chany_coord)) {
+    return true;
+  }
+
+  return false;
+}
+
+/************************************************************************
+ * Identify if a Y-direction routing channel is at the bottom side of a 
+ * multi-width grid
+ * 
+ *     +-----------------+
+ *     |                 |
+ *     |                 | 
+ *     |      Grid       | 
+ *     |    [x+1][y]     | 
+ *     |                 | 
+ *     |                 |
+ *     +-----------------+
+ *          +--------+
+ *          | CHANY  |
+ *          | [x][y] | 
+ *          +--------+
+ *
+ ***********************************************************************/
+bool is_chany_bottom_to_multi_width_grid(const DeviceGrid& grids,
+                                         const vtr::Point<size_t>& chany_coord) {
+  VTR_ASSERT(chany_coord.y() < grids.height() - 1);
+  if (grids.height() - 2 == chany_coord.y()) {
+    /* This is already the TOP side of FPGA fabric,
+     * it is the same results as chany is at the bottom of a multi-width grid
+     */
+    return true;
+  }
+  
+  /* We check the top neighbor of chany, if it does not exist, the chany is left to a multi-height grid */
+  vtr::Point<size_t> top_chany_coord(chany_coord.x(), chany_coord.y() + 1);
+  if (false == is_chany_exist(grids, top_chany_coord)) {
+    return true;
+  }
+
+  return false;
+}
+
 /************************************************************************
  * Get the track_id of a routing track w.r.t its coordinator 
  * In tileable routing architecture, the track_id changes SB by SB.
diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h
index f67acb038..1367466d4 100644
--- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h
+++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h
@@ -34,6 +34,24 @@ size_t get_grid_num_pins(const t_grid_tile& cur_grid,
 size_t get_grid_num_classes(const t_grid_tile& cur_grid, 
                             const e_pin_type& pin_type);
 
+bool is_chanx_exist(const DeviceGrid& grids,
+                    const vtr::Point<size_t>& chanx_coord);
+
+bool is_chany_exist(const DeviceGrid& grids,
+                    const vtr::Point<size_t>& chany_coord);
+
+bool is_chanx_right_to_multi_height_grid(const DeviceGrid& grids,
+                                         const vtr::Point<size_t>& chanx_coord);
+
+bool is_chanx_left_to_multi_height_grid(const DeviceGrid& grids,
+                                        const vtr::Point<size_t>& chanx_coord);
+
+bool is_chany_top_to_multi_width_grid(const DeviceGrid& grids,
+                                      const vtr::Point<size_t>& chany_coord);
+
+bool is_chany_bottom_to_multi_width_grid(const DeviceGrid& grids,
+                                         const vtr::Point<size_t>& chany_coord);
+
 short get_rr_node_actual_track_id(const RRGraph& rr_graph,
                                   const RRNodeId& track_rr_node,
                                   const vtr::Point<size_t>& coord,
diff --git a/vpr/src/tileable_rr_graph/rr_gsb.h b/vpr/src/tileable_rr_graph/rr_gsb.h
index f582d7ce3..8d729139a 100644
--- a/vpr/src/tileable_rr_graph/rr_gsb.h
+++ b/vpr/src/tileable_rr_graph/rr_gsb.h
@@ -19,11 +19,11 @@ namespace openfpga {
  * 2. A X-direction Connection block locates at the left side of the switch block
  * 2. A Y-direction Connection block locates at the top side of the switch block
  *
- *                               +---------------------------------+
- *                               |          Y-direction CB         |
- *                               |              [x][y + 1]         |
- *                               +---------------------------------+
- *                  
+ *  +-------------+              +---------------------------------+
+ *  |             |              |          Y-direction CB         |
+ *  |    Grid     |              |              [x][y + 1]         |
+ *  |  [x][y+1]   |              +---------------------------------+
+ *  +-------------+ 
  *                                          TOP SIDE
  *  +-------------+              +---------------------------------+
  *  |             |              | OPIN_NODE CHAN_NODES OPIN_NODES |
diff --git a/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp
index 5259c9445..23c1d7c07 100644
--- a/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp
+++ b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp
@@ -161,8 +161,10 @@ int adapt_to_tileable_route_chan_width(const int& chan_width,
  *    in X-direction and Y-direction channels!!!
  *    So we will load segment details for different channels 
  ***********************************************************************/
-ChanNodeDetails build_unidir_chan_node_details(const size_t& chan_width, const size_t& max_seg_length,
-                                               const enum e_side& device_side, 
+ChanNodeDetails build_unidir_chan_node_details(const size_t& chan_width,
+                                               const size_t& max_seg_length,
+                                               const bool& force_start, 
+                                               const bool& force_end, 
                                                const std::vector<t_segment_inf>& segment_inf) {
   ChanNodeDetails chan_node_details;
   size_t actual_chan_width = chan_width;
@@ -180,7 +182,7 @@ ChanNodeDetails build_unidir_chan_node_details(const size_t& chan_width, const s
   }
 
   /* Find the number of segments required by each group */
-  std::vector<size_t> num_tracks = get_num_tracks_per_seg_type(actual_chan_width/2, segment_inf, false);  
+  std::vector<size_t> num_tracks = get_num_tracks_per_seg_type(actual_chan_width / 2, segment_inf, false);  
 
   /* Add node to ChanNodeDetails */
   size_t cur_track = 0;
@@ -188,7 +190,7 @@ ChanNodeDetails build_unidir_chan_node_details(const size_t& chan_width, const s
     /* segment length will be set to maxium segment length if this is a longwire */
     size_t seg_len = segment_inf[iseg].length;
     if (true == segment_inf[iseg].longline) {
-       seg_len = max_seg_length;
+      seg_len = max_seg_length;
     } 
     for (size_t itrack = 0; itrack < num_tracks[iseg]; ++itrack) {
       bool seg_start = false;
@@ -213,29 +215,21 @@ ChanNodeDetails build_unidir_chan_node_details(const size_t& chan_width, const s
   }
   /* Check if all the tracks have been satisified */ 
   VTR_ASSERT(cur_track == actual_chan_width);
-
-  /* If this is on the border of a device, segments should start */
-  switch (device_side) {
-  case TOP:
-  case RIGHT:
-    /* INC_DIRECTION should all end */
-    chan_node_details.set_tracks_end(INC_DIRECTION);
-    /* DEC_DIRECTION should all start */
-    chan_node_details.set_tracks_start(DEC_DIRECTION);
-    break;
-  case BOTTOM:
-  case LEFT:
+  
+  /* If this is on the border of a device/heterogeneous blocks, segments should start/end */
+  if (true == force_start) {
     /* INC_DIRECTION should all start */
     chan_node_details.set_tracks_start(INC_DIRECTION);
     /* DEC_DIRECTION should all end */
     chan_node_details.set_tracks_end(DEC_DIRECTION);
-    break;
-  case NUM_SIDES:
-    break;
-  default:
-    VTR_LOGF_ERROR(__FILE__, __LINE__,
-                   "Invalid device_side!\n");
-    exit(1);
+  }
+
+  /* If this is on the border of a device/heterogeneous blocks, segments should start/end */
+  if (true == force_end) {
+    /* INC_DIRECTION should all end */
+    chan_node_details.set_tracks_end(INC_DIRECTION);
+    /* DEC_DIRECTION should all start */
+    chan_node_details.set_tracks_start(DEC_DIRECTION);
   }
 
   return chan_node_details; 
diff --git a/vpr/src/tileable_rr_graph/tileable_chan_details_builder.h b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.h
index cc111541f..b1a1198b9 100644
--- a/vpr/src/tileable_rr_graph/tileable_chan_details_builder.h
+++ b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.h
@@ -17,8 +17,10 @@ namespace openfpga {
 
 int adapt_to_tileable_route_chan_width(const int& chan_width, const std::vector<t_segment_inf>& segment_inf);
 
-ChanNodeDetails build_unidir_chan_node_details(const size_t& chan_width, const size_t& max_seg_length,
-                                               const e_side& device_side, 
+ChanNodeDetails build_unidir_chan_node_details(const size_t& chan_width,
+                                               const size_t& max_seg_length,
+                                               const bool& force_start, 
+                                               const bool& force_end, 
                                                const std::vector<t_segment_inf>& segment_inf);
 
 } /* end namespace openfpga */
diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp
index 332a44e94..9cbc69dff 100755
--- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp
+++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp
@@ -651,9 +651,9 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids,
      * We do not care starting and ending points here, so set chan_side as NUM_SIDES 
      */
     ChanNodeDetails chanx_details = build_unidir_chan_node_details(device_chan_width[0], grids.width() - 1, 
-                                                                   NUM_SIDES, segment_inf); 
+                                                                   false, false, segment_inf); 
     ChanNodeDetails chany_details = build_unidir_chan_node_details(device_chan_width[1], grids.height() - 1, 
-                                                                   NUM_SIDES, segment_inf); 
+                                                                   false, false, segment_inf); 
 
     switch (side) {
     case TOP: /* TOP = 0 */
diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp
new file mode 100644
index 000000000..c8dbe38b1
--- /dev/null
+++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp
@@ -0,0 +1,340 @@
+/************************************************************************
+ *  This file contains functions that are used to allocate nodes 
+ *  for the tileable routing resource graph builder
+ ***********************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+#include "vtr_geometry.h"
+
+#include "vpr_utils.h"
+
+#include "rr_graph_builder_utils.h"
+#include "tileable_chan_details_builder.h"
+#include "tileable_rr_graph_node_builder.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/************************************************************************
+ * Find the number output pins by considering all the grid
+ ***********************************************************************/
+static 
+size_t estimate_num_grid_rr_nodes_by_type(const DeviceGrid& grids,
+                                          const t_rr_type& node_type) {
+  size_t num_grid_rr_nodes = 0;
+
+  for (size_t ix = 0; ix < grids.width(); ++ix) {
+    for (size_t iy = 0; iy < grids.height(); ++iy) { 
+
+      /* Skip EMPTY tiles */
+      if (true == is_empty_type(grids[ix][iy].type)) {
+        continue;
+      }
+
+      /* Skip height > 1 or width > 1 tiles (mostly heterogeneous blocks) */
+      if ( (0 < grids[ix][iy].width_offset)
+        || (0 < grids[ix][iy].height_offset) ) {
+        continue;
+      }
+
+      enum e_side io_side = NUM_SIDES;
+
+      /* If this is the block on borders, we consider IO side */
+      if (true == is_io_type(grids[ix][iy].type)) {
+        vtr::Point<size_t> io_device_size(grids.width() - 1, grids.height() - 1);
+        vtr::Point<size_t> grid_coordinate(ix, iy);
+        io_side = determine_io_grid_pin_side(io_device_size, grid_coordinate);
+      }
+
+      switch (node_type) {
+      case OPIN:
+        /* get the number of OPINs */
+        num_grid_rr_nodes += get_grid_num_pins(grids[ix][iy], DRIVER, io_side);
+        break;
+      case IPIN:
+        /* get the number of IPINs */
+        num_grid_rr_nodes += get_grid_num_pins(grids[ix][iy], RECEIVER, io_side);
+        break;
+      case SOURCE:
+        /* SOURCE: number of classes whose type is DRIVER */
+        num_grid_rr_nodes += get_grid_num_classes(grids[ix][iy], DRIVER);
+        break;
+      case SINK: 
+        /* SINK: number of classes whose type is RECEIVER */
+        num_grid_rr_nodes += get_grid_num_classes(grids[ix][iy], RECEIVER);
+        break;
+      default:
+        VTR_LOGF_ERROR(__FILE__, __LINE__,
+                       "Invalid routing resource node!\n");
+        exit(1);
+      }
+    }
+  }
+
+  return num_grid_rr_nodes; 
+}
+
+/************************************************************************
+ * For X-direction Channel: CHANX
+ * We pair each x-direction routing channel to the grid below it
+ * as they share the same coordinate
+ *
+ * As such, the range of CHANX coordinate starts from x = 1, y = 0
+ * which is the grid (I/O) at the left bottom of the fabric
+ * 
+ * As such, the range of CHANX coordinate ends to x = width - 2, y = height - 2
+ * which is the grid at the top right of the core fabric
+ * Note that the I/O ring is 
+ *
+ *                             TOP SIDE OF FPGA
+ *
+ *           +-------------+       +-------------+        +---------------------+
+ *           |     Grid    |       |     Grid    |   ...  |    Grid             |
+ *           |    [1][0]   |       |    [2][0]   |        | [width-2][height-1] |
+ *           +-------------+       +-------------+        +---------------------+
+ *
+ *           +-------------+       +-------------+        +---------------------+
+ *           |  X-Channel  |       |  X-Channel  |   ...  |  X-Channel          |
+ *           |    [1][0]   |       |   [2][0]    |        | [width-2][height-2] |
+ *           +-------------+       +-------------+        +---------------------+
+ *
+ *           +-------------+       +-------------+        +---------------------+
+ *           |     Grid    |       |     Grid    |   ...  |    Grid             |
+ *           |    [1][0]   |       |    [2][0]   |        | [width-2][height-2] |
+ *           +-------------+       +-------------+        +---------------------+
+ *              
+ *                 ...                   ...                    ...
+ *     
+ *           +-------------+       +-------------+        +--------------+
+ *           |  X-Channel  |       |  X-Channel  |   ...  |  X-Channel   |
+ *           |    [1][1]   |       |   [2][1]    |        | [width-2][1] |
+ *           +-------------+       +-------------+        +--------------+
+ *
+ *  LEFT     +-------------+       +-------------+        +--------------+          RIGHT
+ *  SIDE     |     Grid    |       |     Grid    |   ...  |    Grid      |          SIDE 
+ *  GRID     |    [1][1]   |       |    [2][1]   |        | [width-2][1] |          GRID
+ *           +-------------+       +-------------+        +--------------+
+ *
+ *           +-------------+       +-------------+        +--------------+
+ *           |  X-Channel  |       |  X-Channel  |   ...  |  X-Channel   |
+ *           |    [1][0]   |       |   [2][0]    |        | [width-2][0] |
+ *           +-------------+       +-------------+        +--------------+
+ *
+ *           +-------------+       +-------------+        +--------------+
+ *           |     Grid    |       |     Grid    |   ...  |    Grid      |
+ *           |    [1][0]   |       |    [2][0]   |        | [width-2][0] |
+ *           +-------------+       +-------------+        +--------------+
+ *
+ *                                 BOTTOM SIDE OF FPGA
+ *
+ *  The figure above describe how the X-direction routing channels are 
+ *  organized in a homogeneous FPGA fabric 
+ *  Note that we talk about general-purpose uni-directional routing architecture here 
+ *  It means that a routing track may span across multiple grids
+ *  However, the hard limits are as follows
+ *  All the routing tracks will start at the most LEFT routing channel
+ *  All the routing tracks will end at the most RIGHT routing channel
+ *
+ *  Things will become more complicated in terms of track starting and end
+ *  in the context of heterogeneous FPGAs
+ *  We may have a grid which span multiple column and rows, as exemplified in the figure below
+ *  In such case,
+ *  all the routing tracks [x-1][y] at the left side of the grid [x][y] are forced to end 
+ *  all the routing tracks [x+2][y] at the right side of the grid [x][y] are forced to start
+ *  And there are no routing tracks inside the grid[x][y]
+ *  It means that X-channel [x][y] & [x+1][y] will no exist
+ *
+ *   +------------+     +-------------+       +-------------+        +--------------+
+ *   | X-Channel  |     |  X-Channel  |       |  X-Channel  |        |  X-Channel   |
+ *   | [x-1][y+2] |     |   [x][y+2]  |       | [x+1][y+2]  |        |  [x+2][y+2]  |
+ *   +------------+     +-------------+       +-------------+        +--------------+
+ *
+ *   +------------+     +-----------------------------------+        +--------------+
+ *   |    Grid    |     |                                   |        |    Grid      |
+ *   | [x-1][y+1] |     |                                   |        |  [x+2][y+1]  |
+ *   +------------+     |                                   |        +--------------+
+ *                      |                                   |
+ *   +------------+     |                                   |        +--------------+
+ *   | X-channel  |     |               Grid                |        |  X-Channel   |
+ *   | [x-1][y]   |     |        [x][y] - [x+1][y+1]        |        |   [x+2][y]   |
+ *   +------------+     |                                   |        +--------------+
+ *                      |                                   |
+ *   +------------+     |                                   |        +--------------+
+ *   |   Grid     |     |                                   |        |    Grid      |
+ *   |  [x-1][y]  |     |                                   |        |   [x+2][y]   |
+ *   +------------+     +-----------------------------------+        +--------------+
+ *
+ *
+ *
+ ***********************************************************************/
+static 
+size_t estimate_num_chanx_rr_nodes(const DeviceGrid& grids,
+                                   const size_t& chan_width,
+                                   const std::vector<t_segment_inf>& segment_infs) {
+  size_t num_chanx_rr_nodes = 0;
+
+  for (size_t iy = 0; iy < grids.height() - 1; ++iy) { 
+    for (size_t ix = 1; ix < grids.width() - 1; ++ix) {
+      vtr::Point<size_t> chanx_coord(ix, iy);
+
+      /* Bypass if the routing channel does not exist */
+      if (false == is_chanx_exist(grids, chanx_coord)) {
+        continue;
+      }
+
+      bool force_start = false;
+      bool force_end = false;
+
+      /* All the tracks have to start when 
+       *  - the routing channel touch the RIGHT side a heterogeneous block
+       *  - the routing channel touch the LEFT side of FPGA
+       */
+      if (true == is_chanx_right_to_multi_height_grid(grids, chanx_coord)) {
+        force_start = true;
+      }
+
+      /* All the tracks have to end when 
+       *  - the routing channel touch the LEFT side a heterogeneous block
+       *  - the routing channel touch the RIGHT side of FPGA
+       */
+      if (true == is_chanx_left_to_multi_height_grid(grids, chanx_coord)) {
+        force_end = true;
+      }
+    
+      /* Evaluate if the routing channel locates in the middle of a grid */
+      ChanNodeDetails chanx_details = build_unidir_chan_node_details(chan_width, grids.width() - 2, force_start, force_end, segment_infs); 
+      /* When an INC_DIRECTION CHANX starts, we need a new rr_node */
+      num_chanx_rr_nodes += chanx_details.get_num_starting_tracks(INC_DIRECTION);
+      /* When an DEC_DIRECTION CHANX ends, we need a new rr_node */
+      num_chanx_rr_nodes += chanx_details.get_num_ending_tracks(DEC_DIRECTION);
+    }
+  }
+
+  return num_chanx_rr_nodes;
+}
+
+/************************************************************************
+ * Estimate the number of CHANY rr_nodes for Y-direction routing channels
+ * The technical rationale is very similar to the X-direction routing channel
+ * Refer to the detailed explanation there
+ ***********************************************************************/
+static 
+size_t estimate_num_chany_rr_nodes(const DeviceGrid& grids,
+                                   const size_t& chan_width,
+                                   const std::vector<t_segment_inf>& segment_infs) {
+  size_t num_chany_rr_nodes = 0;
+
+  for (size_t ix = 0; ix < grids.width() - 1; ++ix) {
+    for (size_t iy = 1; iy < grids.height() - 1; ++iy) { 
+      vtr::Point<size_t> chany_coord(ix, iy);
+
+      /* Bypass if the routing channel does not exist */
+      if (false == is_chany_exist(grids, chany_coord)) {
+        continue;
+      }
+
+      bool force_start = false;
+      bool force_end = false;
+
+      /* All the tracks have to start when 
+       *  - the routing channel touch the TOP side a heterogeneous block
+       *  - the routing channel touch the BOTTOM side of FPGA
+       */
+      if (true == is_chany_top_to_multi_width_grid(grids, chany_coord)) {
+        force_start = true;
+      }
+
+      /* All the tracks have to end when 
+       *  - the routing channel touch the BOTTOM side a heterogeneous block
+       *  - the routing channel touch the TOP side of FPGA
+       */
+      if (true == is_chany_bottom_to_multi_width_grid(grids, chany_coord)) {
+        force_end = true;
+      }
+
+      ChanNodeDetails chany_details = build_unidir_chan_node_details(chan_width, grids.height() - 2, force_start, force_end, segment_infs); 
+      /* When an INC_DIRECTION CHANX starts, we need a new rr_node */
+      num_chany_rr_nodes += chany_details.get_num_starting_tracks(INC_DIRECTION);
+      /* When an DEC_DIRECTION CHANX ends, we need a new rr_node */
+      num_chany_rr_nodes += chany_details.get_num_ending_tracks(DEC_DIRECTION);
+    }
+  }
+
+  return num_chany_rr_nodes;
+}
+
+/************************************************************************
+ * Estimate the number of nodes by each type in a routing resource graph
+ ***********************************************************************/
+static 
+std::vector<size_t> estimate_num_rr_nodes(const DeviceGrid& grids,
+                                          const vtr::Point<size_t>& chan_width,
+                                          const std::vector<t_segment_inf>& segment_infs) {
+
+  /* Reset the OPIN, IPIN, SOURCE, SINK counter to be zero */
+  std::vector<size_t> num_rr_nodes_per_type(NUM_RR_TYPES, 0);
+
+  /**
+   * 1 Find number of rr nodes related to grids
+   */
+  num_rr_nodes_per_type[OPIN] = estimate_num_grid_rr_nodes_by_type(grids, OPIN);
+  num_rr_nodes_per_type[IPIN] = estimate_num_grid_rr_nodes_by_type(grids, IPIN);
+  num_rr_nodes_per_type[SOURCE] = estimate_num_grid_rr_nodes_by_type(grids, SOURCE);
+  num_rr_nodes_per_type[SINK] = estimate_num_grid_rr_nodes_by_type(grids, SINK);
+
+  /**
+   * 2. Assign the segments for each routing channel,
+   *    To be specific, for each routing track, we assign a routing segment.
+   *    The assignment is subject to users' specifications, such as 
+   *    a. length of each type of segment
+   *    b. frequency of each type of segment.
+   *    c. routing channel width
+   *
+   *    SPECIAL for fringes:
+   *    All segments will start and ends with no exception
+   *
+   *    IMPORTANT: we should be aware that channel width maybe different 
+   *    in X-direction and Y-direction channels!!!
+   *    So we will load segment details for different channels 
+   */
+  num_rr_nodes_per_type[CHANX] = estimate_num_chanx_rr_nodes(grids, chan_width.x(), segment_infs);
+  num_rr_nodes_per_type[CHANY] = estimate_num_chany_rr_nodes(grids, chan_width.y(), segment_infs);
+
+  return num_rr_nodes_per_type;
+}
+
+/************************************************************************
+ * Allocate rr_nodes to a rr_graph object 
+ * This function just allocate the memory and ensure its efficiency
+ * It will NOT fill detailed information for each node!!!
+ *
+ * Note: ensure that there are NO nodes in the rr_graph
+ ***********************************************************************/
+void alloc_rr_graph_nodes(RRGraph& rr_graph,
+                          const DeviceGrid& grids,
+                          const vtr::Point<size_t>& chan_width,
+                          const std::vector<t_segment_inf>& segment_infs) {
+  VTR_ASSERT(0 == rr_graph.nodes().size());
+
+  std::vector<size_t> num_rr_nodes_per_type = estimate_num_rr_nodes(grids, chan_width, segment_infs);
+
+  /* Reserve the number of node to be memory efficient */  
+  size_t num_nodes = 0;
+  for (const size_t& num_node_per_type : num_rr_nodes_per_type) {
+    num_nodes += num_node_per_type;
+  }
+
+  rr_graph.reserve_nodes(num_nodes);
+
+  /* Add nodes by types */
+  for (const t_rr_type& node_type : {SOURCE, SINK, IPIN, OPIN, CHANX, CHANY}) {
+    for (size_t inode = 0; inode < num_rr_nodes_per_type[size_t(node_type)]; ++inode) {
+      rr_graph.create_node(node_type);
+    }
+  }
+
+  VTR_ASSERT(num_nodes == rr_graph.nodes().size());
+}
+
+} /* end namespace openfpga */
diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h
new file mode 100644
index 000000000..a263324fe
--- /dev/null
+++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h
@@ -0,0 +1,31 @@
+#ifndef TILEABLE_RR_GRAPH_NODE_BUILDER_H
+#define TILEABLE_RR_GRAPH_NODE_BUILDER_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_geometry.h"
+
+/* Headers from readarch library */
+#include "physical_types.h"
+
+/* Headers from vpr library */
+#include "rr_graph_obj.h"
+#include "device_grid.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void alloc_rr_graph_nodes(RRGraph& rr_graph,
+                          const DeviceGrid& grids,
+                          const vtr::Point<size_t>& chan_width,
+                          const std::vector<t_segment_inf>& segment_infs);
+
+} /* end namespace openfpga */
+
+#endif

From 850788eacea0934cbfa7ec2e3f983e6b482c335b Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 5 Mar 2020 17:15:49 -0700
Subject: [PATCH 255/645] adapt tileable rr_graph node builder for rr_graph
 object

---
 .../tileable_rr_graph_node_builder.cpp        | 330 +++++++++++++++++-
 .../tileable_rr_graph_node_builder.h          |  15 +-
 2 files changed, 332 insertions(+), 13 deletions(-)

diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp
index c8dbe38b1..34347befc 100644
--- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp
+++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp
@@ -7,8 +7,14 @@
 #include "vtr_log.h"
 #include "vtr_geometry.h"
 
+/* Headers from openfpgautil library */
+#include "openfpga_side_manager.h"
+
+#include "vpr_types.h"
 #include "vpr_utils.h"
 
+#include "rr_node.h"
+
 #include "rr_graph_builder_utils.h"
 #include "tileable_chan_details_builder.h"
 #include "tileable_rr_graph_node_builder.h"
@@ -311,10 +317,11 @@ std::vector<size_t> estimate_num_rr_nodes(const DeviceGrid& grids,
  *
  * Note: ensure that there are NO nodes in the rr_graph
  ***********************************************************************/
-void alloc_rr_graph_nodes(RRGraph& rr_graph,
-                          const DeviceGrid& grids,
-                          const vtr::Point<size_t>& chan_width,
-                          const std::vector<t_segment_inf>& segment_infs) {
+void alloc_tileable_rr_graph_nodes(RRGraph& rr_graph,
+                                   vtr::vector<RRNodeId, RRSwitchId>& rr_node_driver_switches, 
+                                   const DeviceGrid& grids,
+                                   const vtr::Point<size_t>& chan_width,
+                                   const std::vector<t_segment_inf>& segment_infs) {
   VTR_ASSERT(0 == rr_graph.nodes().size());
 
   std::vector<size_t> num_rr_nodes_per_type = estimate_num_rr_nodes(grids, chan_width, segment_infs);
@@ -327,14 +334,319 @@ void alloc_rr_graph_nodes(RRGraph& rr_graph,
 
   rr_graph.reserve_nodes(num_nodes);
 
-  /* Add nodes by types */
-  for (const t_rr_type& node_type : {SOURCE, SINK, IPIN, OPIN, CHANX, CHANY}) {
-    for (size_t inode = 0; inode < num_rr_nodes_per_type[size_t(node_type)]; ++inode) {
-      rr_graph.create_node(node_type);
+  rr_node_driver_switches.reserve(num_nodes); 
+}
+
+/************************************************************************
+ * Configure OPIN rr_nodes for this grid 
+ * coordinates: xlow, ylow, xhigh, yhigh, 
+ * features: capacity, ptc_num (pin_num),
+ *
+ * Note: this function should be applied ONLY to grid with 0 width offset and 0 height offset!!!
+ ***********************************************************************/
+static 
+void load_one_grid_opin_nodes_basic_info(RRGraph& rr_graph,
+                                         vtr::vector<RRNodeId, RRSwitchId>& rr_node_driver_switches, 
+                                         const vtr::Point<size_t>& grid_coordinate, 
+                                         const t_grid_tile& cur_grid, 
+                                         const e_side& io_side, 
+                                         const RRSwitchId& delayless_switch) {
+  SideManager io_side_manager(io_side);
+
+  /* Walk through the width height of each grid,
+   * get pins and configure the rr_nodes
+   */
+  for (int width = 0; width < cur_grid.type->width; ++width) {
+    for (int height = 0; height < cur_grid.type->height; ++height) {
+      /* Walk through sides */
+      for (size_t side = 0; side < NUM_SIDES; ++side) {
+        SideManager side_manager(side);
+        /* skip unwanted sides */
+        if ( (true == is_io_type(cur_grid.type))
+          && (side != io_side_manager.to_size_t()) ) { 
+          continue;
+        }
+        /* Find OPINs */
+        /* Configure pins by pins */
+        std::vector<int> opin_list = get_grid_side_pins(cur_grid, DRIVER, side_manager.get_side(),
+                                                        width, height);
+        for (const int& pin_num : opin_list) {
+          /* Create a new node and fill information */
+          const RRNodeId& node = rr_graph.create_node(OPIN);
+ 
+          /* node bounding box */
+          rr_graph.set_node_bounding_box(node, vtr::Rect<short>(grid_coordinate.x() + width,
+                                                                grid_coordinate.x() + width,
+                                                                grid_coordinate.y() + height,
+                                                                grid_coordinate.y() + height));
+          rr_graph.set_node_side(node, side_manager.get_side());  
+          rr_graph.set_node_pin_num(node, pin_num);  
+
+          rr_graph.set_node_capacity(node, 1);
+
+          /* cost index is a FIXED value for OPIN */
+          rr_graph.set_node_cost_index(node, OPIN_COST_INDEX); 
+
+          /* Switch info */
+          VTR_ASSERT(size_t(node) == rr_node_driver_switches.size());
+          rr_node_driver_switches.push_back(delayless_switch); 
+
+          /* RC data */
+          rr_graph.set_node_rc_data_index(node, find_create_rr_rc_data(0., 0.));
+
+        } /* End of loading OPIN rr_nodes */
+      } /* End of side enumeration */
+    } /* End of height enumeration */
+  } /* End of width enumeration */
+}
+
+/************************************************************************
+ * Configure IPIN rr_nodes for this grid 
+ * coordinates: xlow, ylow, xhigh, yhigh, 
+ * features: capacity, ptc_num (pin_num),
+ *
+ * Note: this function should be applied ONLY to grid with 0 width offset and 0 height offset!!!
+ ***********************************************************************/
+static 
+void load_one_grid_ipin_nodes_basic_info(RRGraph& rr_graph,
+                                         vtr::vector<RRNodeId, RRSwitchId>& rr_node_driver_switches, 
+                                         const vtr::Point<size_t>& grid_coordinate, 
+                                         const t_grid_tile& cur_grid, 
+                                         const e_side& io_side, 
+                                         const RRSwitchId& wire_to_ipin_switch) {
+  SideManager io_side_manager(io_side);
+
+  /* Walk through the width and height of each grid,
+   * get pins and configure the rr_nodes
+   */
+  for (int width = 0; width < cur_grid.type->width; ++width) {
+    for (int height = 0; height < cur_grid.type->height; ++height) {
+      /* Walk through sides */
+      for (size_t side = 0; side < NUM_SIDES; ++side) {
+        SideManager side_manager(side);
+        /* skip unwanted sides */
+        if ( (true == is_io_type(cur_grid.type))
+          && (side != io_side_manager.to_size_t()) ) { 
+          continue;
+        }
+
+        /* Find IPINs */
+        /* Configure pins by pins */
+        std::vector<int> ipin_list = get_grid_side_pins(cur_grid, RECEIVER, side_manager.get_side(), width, height);
+        for (const int& pin_num : ipin_list) {
+          /* Create a new node and fill information */
+          const RRNodeId& node = rr_graph.create_node(IPIN);
+ 
+          /* node bounding box */
+          rr_graph.set_node_bounding_box(node, vtr::Rect<short>(grid_coordinate.x() + width,
+                                                                grid_coordinate.x() + width,
+                                                                grid_coordinate.y() + height,
+                                                                grid_coordinate.y() + height));
+          rr_graph.set_node_side(node, side_manager.get_side());  
+          rr_graph.set_node_pin_num(node, pin_num);  
+
+          rr_graph.set_node_capacity(node, 1);
+
+          /* cost index is a FIXED value for OPIN */
+          rr_graph.set_node_cost_index(node, IPIN_COST_INDEX); 
+
+          /* Switch info */
+          VTR_ASSERT(size_t(node) == rr_node_driver_switches.size());
+          rr_node_driver_switches.push_back(wire_to_ipin_switch); 
+
+          /* RC data */
+          rr_graph.set_node_rc_data_index(node, find_create_rr_rc_data(0., 0.));
+
+        } /* End of loading IPIN rr_nodes */
+      } /* End of side enumeration */
+    } /* End of height enumeration */
+  } /* End of width enumeration */
+}
+
+/************************************************************************
+ * Configure SOURCE rr_nodes for this grid 
+ * coordinates: xlow, ylow, xhigh, yhigh, 
+ * features: capacity, ptc_num (pin_num),
+ *
+ * Note: this function should be applied ONLY to grid with 0 width offset and 0 height offset!!!
+ ***********************************************************************/
+static 
+void load_one_grid_source_nodes_basic_info(RRGraph& rr_graph,
+                                           vtr::vector<RRNodeId, RRSwitchId>& rr_node_driver_switches, 
+                                           const vtr::Point<size_t>& grid_coordinate, 
+                                           const t_grid_tile& cur_grid, 
+                                           const e_side& io_side, 
+                                           const RRSwitchId& delayless_switch) {
+  SideManager io_side_manager(io_side);
+
+  /* Set a SOURCE rr_node for each DRIVER class */
+  for (int iclass = 0; iclass < cur_grid.type->num_class; ++iclass) {
+    /* Set a SINK rr_node for the OPIN */
+    if (DRIVER != cur_grid.type->class_inf[iclass].type) {
+      continue; 
+    } 
+
+    /* Create a new node and fill information */
+    const RRNodeId& node = rr_graph.create_node(SOURCE);
+
+    /* node bounding box */
+    rr_graph.set_node_bounding_box(node, vtr::Rect<short>(grid_coordinate.x(),
+                                                          grid_coordinate.x(),
+                                                          grid_coordinate.y(),
+                                                          grid_coordinate.y()));
+    rr_graph.set_node_class_num(node, iclass);  
+
+    rr_graph.set_node_capacity(node, 1);
+
+    /* The capacity should be the number of pins in this class*/ 
+    rr_graph.set_node_capacity(node, cur_grid.type->class_inf[iclass].num_pins); 
+
+    /* cost index is a FIXED value for SOURCE */
+    rr_graph.set_node_cost_index(node, SOURCE_COST_INDEX); 
+
+    /* Switch info */
+    VTR_ASSERT(size_t(node) == rr_node_driver_switches.size());
+    rr_node_driver_switches.push_back(delayless_switch); 
+
+    /* RC data */
+    rr_graph.set_node_rc_data_index(node, find_create_rr_rc_data(0., 0.));
+
+  } /* End of class enumeration */
+}
+
+/************************************************************************
+ * Configure SINK rr_nodes for this grid 
+ * coordinates: xlow, ylow, xhigh, yhigh, 
+ * features: capacity, ptc_num (pin_num),
+ *
+ * Note: this function should be applied ONLY to grid with 0 width offset and 0 height offset!!!
+ ***********************************************************************/
+static 
+void load_one_grid_sink_nodes_basic_info(RRGraph& rr_graph,
+                                         vtr::vector<RRNodeId, RRSwitchId>& rr_node_driver_switches, 
+                                         const vtr::Point<size_t>& grid_coordinate, 
+                                         const t_grid_tile& cur_grid, 
+                                         const e_side& io_side, 
+                                         const RRSwitchId& delayless_switch) {
+  SideManager io_side_manager(io_side);
+
+  /* Set a SINK rr_node for each RECEIVER class */
+  for (int iclass = 0; iclass < cur_grid.type->num_class; ++iclass) {
+    /* Set a SINK rr_node for the OPIN */
+    if (RECEIVER != cur_grid.type->class_inf[iclass].type) {
+      continue; 
+    }
+
+    /* Create a new node and fill information */
+    const RRNodeId& node = rr_graph.create_node(SINK);
+
+    /* node bounding box */
+    rr_graph.set_node_bounding_box(node, vtr::Rect<short>(grid_coordinate.x(),
+                                                          grid_coordinate.x(),
+                                                          grid_coordinate.y(),
+                                                          grid_coordinate.y()));
+    rr_graph.set_node_class_num(node, iclass);  
+
+    rr_graph.set_node_capacity(node, 1);
+
+    /* The capacity should be the number of pins in this class*/ 
+    rr_graph.set_node_capacity(node, cur_grid.type->class_inf[iclass].num_pins); 
+
+    /* cost index is a FIXED value for SINK */
+    rr_graph.set_node_cost_index(node, SINK_COST_INDEX); 
+
+    /* Switch info */
+    VTR_ASSERT(size_t(node) == rr_node_driver_switches.size());
+    rr_node_driver_switches.push_back(delayless_switch); 
+
+    /* RC data */
+    rr_graph.set_node_rc_data_index(node, find_create_rr_rc_data(0., 0.));
+
+  } /* End of class enumeration */
+}
+
+/************************************************************************
+ * Create all the rr_nodes for grids
+ ***********************************************************************/
+static 
+void load_grid_nodes_basic_info(RRGraph& rr_graph,
+                                vtr::vector<RRNodeId, RRSwitchId>& rr_node_driver_switches, 
+                                const DeviceGrid& grids, 
+                                const RRSwitchId& wire_to_ipin_switch,
+                                const RRSwitchId& delayless_switch) {
+
+  for (size_t iy = 0; iy < grids.height(); ++iy) { 
+    for (size_t ix = 0; ix < grids.width(); ++ix) {
+      /* Skip EMPTY tiles */
+      if (true == is_empty_type(grids[ix][iy].type)) {
+        continue;
+      }
+
+      /* We only build rr_nodes for grids with width_offset = 0 and height_offset = 0 */
+      if ( (0 < grids[ix][iy].width_offset)
+        || (0 < grids[ix][iy].height_offset) ) {
+        continue;
+      }
+
+      vtr::Point<size_t> grid_coordinate(ix, iy);
+      enum e_side io_side = NUM_SIDES;
+
+      /* If this is the block on borders, we consider IO side */
+      if (true == is_io_type(grids[ix][iy].type)) {
+        vtr::Point<size_t> io_device_size(grids.width() - 1, grids.height() - 1);
+        io_side = determine_io_grid_pin_side(io_device_size, grid_coordinate);
+      }
+
+      /* Configure source rr_nodes for this grid */
+      load_one_grid_source_nodes_basic_info(rr_graph,
+                                            rr_node_driver_switches, 
+                                            grid_coordinate, 
+                                            grids[ix][iy], 
+                                            io_side, 
+                                            delayless_switch);
+
+      /* Configure sink rr_nodes for this grid */
+      load_one_grid_sink_nodes_basic_info(rr_graph,
+                                          rr_node_driver_switches, 
+                                          grid_coordinate, 
+                                          grids[ix][iy], 
+                                          io_side, 
+                                          delayless_switch);
+
+      /* Configure opin rr_nodes for this grid */
+      load_one_grid_opin_nodes_basic_info(rr_graph,
+                                            rr_node_driver_switches, 
+                                            grid_coordinate, 
+                                            grids[ix][iy], 
+                                            io_side, 
+                                            delayless_switch);
+
+      /* Configure ipin rr_nodes for this grid */
+      load_one_grid_ipin_nodes_basic_info(rr_graph,
+                                          rr_node_driver_switches, 
+                                          grid_coordinate, 
+                                          grids[ix][iy], 
+                                          io_side, 
+                                          wire_to_ipin_switch);
+
     }
   }
+}
+
+/************************************************************************
+ * Create all the rr_nodes covering both grids and routing channels
+ ***********************************************************************/
+void create_tileable_rr_graph_nodes(RRGraph& rr_graph,
+                                    vtr::vector<RRNodeId, RRSwitchId>& rr_node_driver_switches, 
+                                    const DeviceGrid& grids, 
+                                    const RRSwitchId& wire_to_ipin_switch,
+                                    const RRSwitchId& delayless_switch) {
+  load_grid_nodes_basic_info(rr_graph,
+                             rr_node_driver_switches, 
+                             grids, 
+                             wire_to_ipin_switch,
+                             delayless_switch);
 
-  VTR_ASSERT(num_nodes == rr_graph.nodes().size());
 }
 
 } /* end namespace openfpga */
diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h
index a263324fe..7cd8c673a 100644
--- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h
+++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h
@@ -21,10 +21,17 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-void alloc_rr_graph_nodes(RRGraph& rr_graph,
-                          const DeviceGrid& grids,
-                          const vtr::Point<size_t>& chan_width,
-                          const std::vector<t_segment_inf>& segment_infs);
+void alloc_tileable_rr_graph_nodes(RRGraph& rr_graph,
+                                   vtr::vector<RRNodeId, RRSwitchId>& driver_switches, 
+                                   const DeviceGrid& grids,
+                                   const vtr::Point<size_t>& chan_width,
+                                   const std::vector<t_segment_inf>& segment_infs);
+
+void create_tileable_rr_graph_nodes(RRGraph& rr_graph,
+                                    vtr::vector<RRNodeId, RRSwitchId>& rr_node_driver_switches, 
+                                    const DeviceGrid& grids, 
+                                    const RRSwitchId& wire_to_ipin_switch,
+                                    const RRSwitchId& delayless_switch);
 
 } /* end namespace openfpga */
 

From 5067dd846e8919754fe41d55a78ce3fbd482c2ef Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 5 Mar 2020 17:47:48 -0700
Subject: [PATCH 256/645] adapting channel rr_node builder for tileable
 rr_graph

---
 .../tileable_rr_graph/chan_node_details.cpp   |  33 +++---
 .../tileable_rr_graph_node_builder.cpp        | 105 ++++++++++++++++++
 2 files changed, 123 insertions(+), 15 deletions(-)

diff --git a/vpr/src/tileable_rr_graph/chan_node_details.cpp b/vpr/src/tileable_rr_graph/chan_node_details.cpp
index f52188d93..ef2df157e 100644
--- a/vpr/src/tileable_rr_graph/chan_node_details.cpp
+++ b/vpr/src/tileable_rr_graph/chan_node_details.cpp
@@ -1,8 +1,11 @@
 /************************************************************************
  *  This file contains member functions for class ChanNodeDetails
  ***********************************************************************/
-#include <cassert>
 #include <algorithm>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+
 #include "chan_node_details.h"
 
 /* begin namespace openfpga */
@@ -33,12 +36,12 @@ ChanNodeDetails::ChanNodeDetails() {
  *  Accessors
  ***********************************************************************/
 size_t ChanNodeDetails::get_chan_width() const {
-  assert(validate_chan_width());
+  VTR_ASSERT(validate_chan_width());
   return track_node_ids_.size();
 }
 
 size_t ChanNodeDetails::get_track_node_id(const size_t& track_id) const {
-  assert(validate_track_id(track_id));
+  VTR_ASSERT(validate_track_id(track_id));
   return track_node_ids_[track_id];
 }
 
@@ -52,27 +55,27 @@ std::vector<size_t> ChanNodeDetails::get_track_node_ids() const {
 }
 
 e_direction ChanNodeDetails::get_track_direction(const size_t& track_id) const {
-  assert(validate_track_id(track_id));
+  VTR_ASSERT(validate_track_id(track_id));
   return track_direction_[track_id];
 }
 
 size_t ChanNodeDetails::get_track_segment_length(const size_t& track_id) const {
-  assert(validate_track_id(track_id));
+  VTR_ASSERT(validate_track_id(track_id));
   return seg_length_[track_id];
 }
 
 size_t ChanNodeDetails::get_track_segment_id(const size_t& track_id) const {
-  assert(validate_track_id(track_id));
+  VTR_ASSERT(validate_track_id(track_id));
   return seg_ids_[track_id];
 }
 
 bool   ChanNodeDetails::is_track_start(const size_t& track_id) const {
-  assert(validate_track_id(track_id));
+  VTR_ASSERT(validate_track_id(track_id));
   return track_start_[track_id];
 }
 
 bool   ChanNodeDetails::is_track_end(const size_t& track_id) const {
-  assert(validate_track_id(track_id));
+  VTR_ASSERT(validate_track_id(track_id));
   return track_end_[track_id];
 }
 
@@ -81,9 +84,9 @@ bool   ChanNodeDetails::is_track_end(const size_t& track_id) const {
  * A group size is the number of such nodes between the starting points (include the 1st starting point) 
  */
 std::vector<size_t> ChanNodeDetails::get_seg_group(const size_t& track_id) const {
-  assert(validate_chan_width());
-  assert(validate_track_id(track_id));
-  assert(is_track_start(track_id));
+  VTR_ASSERT(validate_chan_width());
+  VTR_ASSERT(validate_track_id(track_id));
+  VTR_ASSERT(is_track_start(track_id));
   
   std::vector<size_t> group;
   /* Make sure a clean start */
@@ -115,7 +118,7 @@ std::vector<size_t> ChanNodeDetails::get_seg_group_node_id(const std::vector<siz
   group.clear();
 
   for (size_t id = 0; id < seg_group.size(); ++id) {
-    assert(validate_track_id(seg_group[id]));
+    VTR_ASSERT(validate_track_id(seg_group[id]));
     group.push_back(get_track_node_id(seg_group[id]));
   }
 
@@ -182,14 +185,14 @@ void ChanNodeDetails::add_track(const size_t& track_node_id, const e_direction&
 
 /* Update the node_id of a given track */
 void ChanNodeDetails::set_track_node_id(const size_t& track_index, const size_t& track_node_id) {
-  assert(validate_track_id(track_index));
+  VTR_ASSERT(validate_track_id(track_index));
   track_node_ids_[track_index] = track_node_id; 
 }
 
 /* Update the node_ids from a vector */
 void ChanNodeDetails::set_track_node_ids(const std::vector<size_t>& track_node_ids) {
   /* the size of vector should match chan_width */
-  assert ( get_chan_width() == track_node_ids.size() );
+  VTR_ASSERT ( get_chan_width() == track_node_ids.size() );
   for (size_t inode = 0; inode < track_node_ids.size(); ++inode) {
     track_node_ids_[inode] = track_node_ids[inode]; 
   }
@@ -227,7 +230,7 @@ void ChanNodeDetails::rotate_track_node_id(const size_t& offset, const e_directi
   /* Rotate the node_ids by groups
    * A group begins from a track_start and ends before another track_start  
    */
-  assert(validate_chan_width());
+  VTR_ASSERT(validate_chan_width());
   for (size_t itrack = 0; itrack < get_chan_width(); ++itrack) { 
     /* Bypass non-start segment */
     if (false == is_track_start(itrack) ) {
diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp
index 34347befc..0ea35af13 100644
--- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp
+++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp
@@ -633,6 +633,111 @@ void load_grid_nodes_basic_info(RRGraph& rr_graph,
   }
 }
 
+/************************************************************************
+ * Initialize the basic information of routing track rr_nodes
+ * coordinates: xlow, ylow, xhigh, yhigh, 
+ * features: capacity, track_ids, ptc_num, direction 
+ ***********************************************************************/
+static 
+void load_one_chan_rr_nodes_basic_info(RRGraph& rr_graph,
+                                       vtr::vector<RRNodeId, RRSwitchId>& rr_node_driver_switches, 
+                                       std::map<RRNodeId, std::vector<size_t>>& rr_node_track_ids,
+                                       const vtr::Point<size_t>& chan_coordinate, 
+                                       const t_rr_type& chan_type,
+                                       ChanNodeDetails& chan_details,
+                                       const std::vector<t_segment_inf>& segment_infs,
+                                       const int& cost_index_offset) {
+  /* Check each node_id(potential ptc_num) in the channel :
+   * If this is a starting point, we set a new rr_node with xlow/ylow, ptc_num
+   * If this is a ending point, we set xhigh/yhigh and track_ids
+   * For other nodes, we set changes in track_ids
+   */
+  for (size_t itrack = 0; itrack < chan_details.get_chan_width(); ++itrack) {
+    /* For INC direction, a starting point requires a new chan rr_node  */
+    if ( ( (true == chan_details.is_track_start(itrack))
+        && (INC_DIRECTION == chan_details.get_track_direction(itrack)) ) 
+    /* For DEC direction, an ending point requires a new chan rr_node  */
+      ||
+       ( (true == chan_details.is_track_end(itrack))
+      && (DEC_DIRECTION == chan_details.get_track_direction(itrack)) ) ) {
+
+      /* Create a new chan rr_node  */
+      const RRNodeId& node = rr_graph.create_node(chan_type);
+    
+      rr_graph.set_node_xlow(node, chan_coordinate.x());
+      rr_graph.set_node_ylow(node, chan_coordinate.y());
+
+      rr_graph.set_node_direction(node, chan_details.get_track_direction(itrack)); 
+      rr_graph.set_node_track_num(node, itrack);
+      rr_node_track_ids[node].push_back(itrack);
+
+      rr_graph.set_node_capacity(node, 1); 
+
+      /* assign switch id */
+      size_t seg_id = chan_details.get_track_segment_id(itrack);
+      VTR_ASSERT(size_t(node) == rr_node_driver_switches.size());
+      rr_node_driver_switches.push_back(RRSwitchId(segment_infs[seg_id].arch_opin_switch)); 
+
+      /* Update chan_details with node_id */
+      chan_details.set_track_node_id(itrack, size_t(node));
+
+      /* cost index depends on the segment index */
+      rr_graph.set_node_cost_index(node, cost_index_offset + seg_id); 
+      /* Finish here, go to next */
+    }
+
+    /* For INC direction, an ending point requires an update on xhigh and yhigh  */
+    if (   ( (true == chan_details.is_track_end(itrack))
+          && (INC_DIRECTION == chan_details.get_track_direction(itrack)) ) 
+       ||
+       /* For DEC direction, an starting point requires an update on xlow and ylow  */
+           ( (true == chan_details.is_track_start(itrack))
+          && (DEC_DIRECTION == chan_details.get_track_direction(itrack)) ) ) {
+
+      /* Get the node_id */
+      const RRNodeId& rr_node_id = RRNodeId(chan_details.get_track_node_id(itrack));
+
+      /* Do a quick check, make sure we do not mistakenly modify other nodes */
+      VTR_ASSERT(chan_type == rr_graph.node_type(rr_node_id));
+      VTR_ASSERT(chan_details.get_track_direction(itrack) == rr_graph.node_direction(rr_node_id));
+
+      /* set xhigh/yhigh and push changes to track_ids */
+      rr_graph.set_node_xhigh(rr_node_id, chan_coordinate.x());
+      rr_graph.set_node_yhigh(rr_node_id, chan_coordinate.y());
+
+      /* Do not update track_ids for length-1 wires, they should have only 1 track_id */
+      if ( (rr_graph.node_xhigh(rr_node_id) > rr_graph.node_xlow(rr_node_id))
+        || (rr_graph.node_yhigh(rr_node_id) > rr_graph.node_ylow(rr_node_id)) ) {
+        rr_node_track_ids[rr_node_id].push_back(itrack);
+      }
+      /* Finish here, go to next */
+    }
+
+    /* Finish processing starting and ending tracks */
+    if ( (true == chan_details.is_track_start(itrack))
+      || (true == chan_details.is_track_end(itrack)) ) {
+      /* Finish here, go to next */
+      continue;
+    }
+
+    /* For other nodes, we get the node_id and just update track_ids */
+    /* Ensure those nodes are neither starting nor ending points */
+    VTR_ASSERT( (false == chan_details.is_track_start(itrack))
+             && (false == chan_details.is_track_end(itrack)) );
+
+    /* Get the node_id */
+    const RRNodeId& rr_node_id = RRNodeId(chan_details.get_track_node_id(itrack));
+
+    /* Do a quick check, make sure we do not mistakenly modify other nodes */
+    VTR_ASSERT(chan_type == rr_graph.node_type(rr_node_id));
+    VTR_ASSERT(chan_details.get_track_direction(itrack) == rr_graph.node_direction(rr_node_id));
+
+    /* Update track_ids */
+    rr_node_track_ids[rr_node_id].push_back(itrack);
+    /* Finish here, go to next */
+  }
+} 
+
 /************************************************************************
  * Create all the rr_nodes covering both grids and routing channels
  ***********************************************************************/

From 328488f357190e598c44f926d46839ce175d25e6 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 5 Mar 2020 20:15:16 -0700
Subject: [PATCH 257/645] adapt chan rr node builder to use rr_graph obj

---
 .../tileable_rr_graph_node_builder.cpp        | 227 ++++++++++++++++++
 .../tileable_rr_graph_node_builder.h          |   4 +
 2 files changed, 231 insertions(+)

diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp
index 0ea35af13..2928ed335 100644
--- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp
+++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp
@@ -738,12 +738,222 @@ void load_one_chan_rr_nodes_basic_info(RRGraph& rr_graph,
   }
 } 
 
+/************************************************************************
+ * Initialize the basic information of X-channel rr_nodes:
+ * coordinates: xlow, ylow, xhigh, yhigh, 
+ * features: capacity, track_ids, ptc_num, direction 
+ * grid_info : pb_graph_pin
+ ***********************************************************************/
+static 
+void load_chanx_rr_nodes_basic_info(RRGraph& rr_graph, 
+                                    vtr::vector<RRNodeId, RRSwitchId>& rr_node_driver_switches, 
+                                    std::map<RRNodeId, std::vector<size_t>>& rr_node_track_ids,
+                                    const DeviceGrid& grids,
+                                    const size_t& chan_width,
+                                    const std::vector<t_segment_inf>& segment_infs) {
+
+  /* For X-direction Channel: CHANX */
+  for (size_t iy = 0; iy < grids.height() - 1; ++iy) { 
+    /* Keep a vector of node_ids for the channels, because we will rotate them when walking through ix */
+    std::vector<size_t> track_node_ids;
+
+    for (size_t ix = 1; ix < grids.width() - 1; ++ix) {
+      vtr::Point<size_t> chanx_coord(ix, iy);
+
+      /* Bypass if the routing channel does not exist */
+      if (false == is_chanx_exist(grids, chanx_coord)) {
+        continue;
+      }
+
+      bool force_start = false;
+      bool force_end = false;
+
+      /* All the tracks have to start when 
+       *  - the routing channel touch the RIGHT side a heterogeneous block
+       *  - the routing channel touch the LEFT side of FPGA
+       */
+      if (true == is_chanx_right_to_multi_height_grid(grids, chanx_coord)) {
+        force_start = true;
+      }
+
+      /* All the tracks have to end when 
+       *  - the routing channel touch the LEFT side a heterogeneous block
+       *  - the routing channel touch the RIGHT side of FPGA
+       */
+      if (true == is_chanx_left_to_multi_height_grid(grids, chanx_coord)) {
+        force_end = true;
+      }
+
+      ChanNodeDetails chanx_details = build_unidir_chan_node_details(chan_width, grids.width() - 2, 
+                                                                     force_start, force_end, segment_infs); 
+      /* Force node_ids from the previous chanx */
+      if (0 < track_node_ids.size()) {
+        /* Rotate should be done based on a typical case of routing tracks.
+         * Tracks on the borders are not regularly started and ended, 
+         * which causes the node_rotation malfunction  
+         */
+        ChanNodeDetails chanx_details_tt = build_unidir_chan_node_details(chan_width, grids.width() - 2,
+                                                                          false, false, segment_infs); 
+        chanx_details_tt.set_track_node_ids(track_node_ids);
+
+        /* Rotate the chanx_details by an offset of ix - 1, the distance to the most left channel */
+        /* For INC_DIRECTION, we use clockwise rotation 
+         * node_id A ---->   -----> node_id D
+         * node_id B ---->  / ----> node_id A
+         * node_id C ----> /  ----> node_id B
+         * node_id D ---->    ----> node_id C 
+         */
+        chanx_details_tt.rotate_track_node_id(1, INC_DIRECTION, true);
+        /* For DEC_DIRECTION, we use clockwise rotation 
+         * node_id A <-----    <----- node_id B
+         * node_id B <----- \  <----- node_id C
+         * node_id C <-----  \ <----- node_id D
+         * node_id D <-----    <----- node_id A 
+         */
+        chanx_details_tt.rotate_track_node_id(1, DEC_DIRECTION, false);
+
+        track_node_ids = chanx_details_tt.get_track_node_ids();
+        chanx_details.set_track_node_ids(track_node_ids);
+      }
+
+      /* Configure CHANX in this channel */
+      load_one_chan_rr_nodes_basic_info(rr_graph,
+                                        rr_node_driver_switches,
+                                        rr_node_track_ids,
+                                        chanx_coord, CHANX, 
+                                        chanx_details, 
+                                        segment_infs, 
+                                        CHANX_COST_INDEX_START);
+      /* Get a copy of node_ids */
+      track_node_ids = chanx_details.get_track_node_ids();
+    }
+  }
+}
+
+/************************************************************************
+ * Initialize the basic information of Y-channel rr_nodes:
+ * coordinates: xlow, ylow, xhigh, yhigh, 
+ * features: capacity, track_ids, ptc_num, direction 
+ ***********************************************************************/
+static 
+void load_chany_rr_nodes_basic_info(RRGraph& rr_graph, 
+                                    vtr::vector<RRNodeId, RRSwitchId>& rr_node_driver_switches, 
+                                    std::map<RRNodeId, std::vector<size_t>>& rr_node_track_ids,
+                                    const DeviceGrid& grids,
+                                    const size_t& chan_width,
+                                    const std::vector<t_segment_inf>& segment_infs) {
+
+  /* For Y-direction Channel: CHANY */
+  for (size_t ix = 0; ix < grids.width() - 1; ++ix) {
+    /* Keep a vector of node_ids for the channels, because we will rotate them when walking through ix */
+    std::vector<size_t> track_node_ids;
+
+    for (size_t iy = 1; iy < grids.height() - 1; ++iy) { 
+      vtr::Point<size_t> chany_coord(ix, iy);
+
+      /* Bypass if the routing channel does not exist */
+      if (false == is_chany_exist(grids, chany_coord)) {
+        continue;
+      }
+
+      bool force_start = false;
+      bool force_end = false;
+
+      /* All the tracks have to start when 
+       *  - the routing channel touch the TOP side a heterogeneous block
+       *  - the routing channel touch the BOTTOM side of FPGA
+       */
+      if (true == is_chany_top_to_multi_width_grid(grids, chany_coord)) {
+        force_start = true;
+      }
+
+      /* All the tracks have to end when 
+       *  - the routing channel touch the BOTTOM side a heterogeneous block
+       *  - the routing channel touch the TOP side of FPGA
+       */
+      if (true == is_chany_bottom_to_multi_width_grid(grids, chany_coord)) {
+        force_end = true;
+      }
+
+      ChanNodeDetails chany_details = build_unidir_chan_node_details(chan_width, grids.height() - 2,
+                                                                     force_start, force_end, segment_infs); 
+      /* Force node_ids from the previous chanx */
+      if (0 < track_node_ids.size()) {
+        /* Rotate should be done based on a typical case of routing tracks.
+         * Tracks on the borders are not regularly started and ended, 
+         * which causes the node_rotation malfunction  
+         */
+        ChanNodeDetails chany_details_tt = build_unidir_chan_node_details(chan_width, grids.height() - 2,
+                                                                          false, false, segment_infs); 
+
+        chany_details_tt.set_track_node_ids(track_node_ids);
+        /* Rotate the chany_details by an offset of 1*/
+        /* For INC_DIRECTION, we use clockwise rotation 
+         * node_id A ---->   -----> node_id D
+         * node_id B ---->  / ----> node_id A
+         * node_id C ----> /  ----> node_id B
+         * node_id D ---->    ----> node_id C 
+         */
+        chany_details_tt.rotate_track_node_id(1, INC_DIRECTION, true);
+        /* For DEC_DIRECTION, we use clockwise rotation 
+         * node_id A <-----    <----- node_id B
+         * node_id B <----- \  <----- node_id C
+         * node_id C <-----  \ <----- node_id D
+         * node_id D <-----    <----- node_id A 
+         */
+        chany_details_tt.rotate_track_node_id(1, DEC_DIRECTION, false);
+
+        track_node_ids = chany_details_tt.get_track_node_ids();
+        chany_details.set_track_node_ids(track_node_ids);
+      }
+      /* Configure CHANX in this channel */
+      load_one_chan_rr_nodes_basic_info(rr_graph,
+                                        rr_node_driver_switches, 
+                                        rr_node_track_ids, 
+                                        chany_coord, CHANY, 
+                                        chany_details, 
+                                        segment_infs, 
+                                        CHANX_COST_INDEX_START + segment_infs.size());
+      /* Get a copy of node_ids */
+      track_node_ids = chany_details.get_track_node_ids();
+    }
+  }
+}
+
+/************************************************************************
+ * Reverse the track_ids of CHANX and CHANY nodes in DEC_DIRECTION
+ * This is required as the track ids are allocated in the sequence
+ * of incrementing x and y
+ * However, DEC direction routing tracks should have a reversed sequence in 
+ * track ids 
+ ***********************************************************************/
+static 
+void reverse_dec_chan_rr_node_track_ids(const RRGraph& rr_graph, 
+                                        std::map<RRNodeId, std::vector<size_t>>& rr_node_track_ids) {
+  for (const RRNodeId& node : rr_graph.nodes()) {
+    /* Bypass condition: only focus on CHANX and CHANY in DEC_DIRECTION */
+    if ( (CHANX != rr_graph.node_type(node))
+      && (CHANY != rr_graph.node_type(node)) ) {
+      continue;
+    }
+    /* Reach here, we must have a node of CHANX or CHANY */
+    if (DEC_DIRECTION != rr_graph.node_direction(node)) {
+      continue;
+    }
+    std::reverse(rr_node_track_ids[node].begin(),
+                 rr_node_track_ids[node].end() );
+  }
+}
+
 /************************************************************************
  * Create all the rr_nodes covering both grids and routing channels
  ***********************************************************************/
 void create_tileable_rr_graph_nodes(RRGraph& rr_graph,
                                     vtr::vector<RRNodeId, RRSwitchId>& rr_node_driver_switches, 
+                                    std::map<RRNodeId, std::vector<size_t>>& rr_node_track_ids,
                                     const DeviceGrid& grids, 
+                                    const vtr::Point<size_t>& chan_width, 
+                                    const std::vector<t_segment_inf>& segment_infs,
                                     const RRSwitchId& wire_to_ipin_switch,
                                     const RRSwitchId& delayless_switch) {
   load_grid_nodes_basic_info(rr_graph,
@@ -752,6 +962,23 @@ void create_tileable_rr_graph_nodes(RRGraph& rr_graph,
                              wire_to_ipin_switch,
                              delayless_switch);
 
+  load_chanx_rr_nodes_basic_info(rr_graph, 
+                                 rr_node_driver_switches, 
+                                 rr_node_track_ids, 
+                                 grids,
+                                 chan_width.x(),
+                                 segment_infs);
+
+  load_chany_rr_nodes_basic_info(rr_graph, 
+                                 rr_node_driver_switches, 
+                                 rr_node_track_ids, 
+                                 grids,
+                                 chan_width.y(),
+                                 segment_infs);
+
+  reverse_dec_chan_rr_node_track_ids(rr_graph, 
+                                     rr_node_track_ids);
+
 }
 
 } /* end namespace openfpga */
diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h
index 7cd8c673a..a69cd187c 100644
--- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h
+++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h
@@ -29,10 +29,14 @@ void alloc_tileable_rr_graph_nodes(RRGraph& rr_graph,
 
 void create_tileable_rr_graph_nodes(RRGraph& rr_graph,
                                     vtr::vector<RRNodeId, RRSwitchId>& rr_node_driver_switches, 
+                                    std::map<RRNodeId, std::vector<size_t>>& rr_node_track_ids,
                                     const DeviceGrid& grids, 
+                                    const vtr::Point<size_t>& chan_width, 
+                                    const std::vector<t_segment_inf>& segment_infs,
                                     const RRSwitchId& wire_to_ipin_switch,
                                     const RRSwitchId& delayless_switch);
 
+
 } /* end namespace openfpga */
 
 #endif

From 8d350ee22ff41af0877a9781715b3d44bacf58c5 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 5 Mar 2020 20:50:21 -0700
Subject: [PATCH 258/645] adapt tileable rr_graph edge builder to rr_graph
 object

---
 .../tileable_rr_graph_edge_builder.cpp        | 169 ++++++++++++++++++
 .../tileable_rr_graph_edge_builder.h          |  42 +++++
 .../tileable_rr_graph_gsb.cpp                 |   8 +-
 .../tileable_rr_graph/tileable_rr_graph_gsb.h |   4 +-
 4 files changed, 217 insertions(+), 6 deletions(-)
 create mode 100644 vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp
 create mode 100644 vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h

diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp
new file mode 100644
index 000000000..185e4923b
--- /dev/null
+++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp
@@ -0,0 +1,169 @@
+/************************************************************************
+ *  This file contains functions that are used to build edges
+ *  between nodes of a tileable routing resource graph
+ ***********************************************************************/
+#include <algorithm>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+#include "vtr_time.h"
+
+#include "vpr_utils.h"
+
+#include "rr_graph_builder_utils.h"
+#include "tileable_rr_graph_gsb.h"
+#include "tileable_rr_graph_edge_builder.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/************************************************************************
+ * Build the edges for all the SOURCE and SINKs nodes:
+ * 1. create edges between SOURCE and OPINs
+ ***********************************************************************/
+static 
+void build_rr_graph_edges_for_source_nodes(RRGraph& rr_graph,
+                                           const vtr::vector<RRNodeId, RRSwitchId>& rr_node_driver_switches,
+                                           const DeviceGrid& grids) {
+  for (const RRNodeId& node : rr_graph.nodes()) {
+    /* Bypass all the non OPIN nodes */
+    if (OPIN != rr_graph.node_type(node)) {
+      continue;
+    }
+    /* Now, we have an OPIN node, we get the source node index */
+    short xlow = rr_graph.node_xlow(node); 
+    short ylow = rr_graph.node_ylow(node); 
+    short src_node_class_num = get_grid_pin_class_index(grids[xlow][ylow], 
+                                                        rr_graph.node_pin_num(node));
+
+    /* Create edges between SOURCE and OPINs */
+    const RRNodeId& src_node = rr_graph.find_node(xlow - grids[xlow][ylow].width_offset,
+                                                  ylow - grids[xlow][ylow].height_offset,
+                                                  SOURCE, src_node_class_num);
+    VTR_ASSERT(true == rr_graph.valid_node_id(src_node));
+
+    /* add edges to the src_node */
+    rr_graph.create_edge(src_node, node, rr_node_driver_switches[node]);
+  }
+}
+
+/************************************************************************
+ * Build the edges for all the SINKs nodes:
+ * 1. create edges between IPINs and SINKs
+ ***********************************************************************/
+static 
+void build_rr_graph_edges_for_sink_nodes(RRGraph& rr_graph,
+                                         const vtr::vector<RRNodeId, RRSwitchId>& rr_node_driver_switches,
+                                         const DeviceGrid& grids) {
+  for (const RRNodeId& node : rr_graph.nodes()) {
+    /* Bypass all the non IPIN nodes */
+    if (IPIN != rr_graph.node_type(node)) {
+      continue;
+    }
+    /* Now, we have an OPIN node, we get the source node index */
+    short xlow = rr_graph.node_xlow(node); 
+    short ylow = rr_graph.node_ylow(node); 
+    short sink_node_class_num = get_grid_pin_class_index(grids[xlow][ylow], 
+                                                         rr_graph.node_pin_num(node));
+    /* 1. create edges between IPINs and SINKs */
+    const RRNodeId& sink_node = rr_graph.find_node(xlow - grids[xlow][ylow].width_offset,
+                                                   ylow - grids[xlow][ylow].height_offset,
+                                                   SINK, sink_node_class_num);
+    VTR_ASSERT(true == rr_graph.valid_node_id(sink_node));
+
+    /* add edges to connect the IPIN node to SINK nodes */
+    rr_graph.create_edge(node, sink_node, rr_node_driver_switches[sink_node]);
+  }
+}
+
+/************************************************************************
+ * Build the edges of each rr_node tile by tile:
+ * We classify rr_nodes into a general switch block (GSB) data structure
+ * where we create edges to each rr_nodes in the GSB with respect to
+ * Fc_in and Fc_out, switch block patterns 
+ * For each GSB: 
+ * 1. create edges between CHANX | CHANY and IPINs (connections inside connection blocks)
+ * 2. create edges between OPINs, CHANX and CHANY (connections inside switch blocks)
+ * 3. create edges between OPINs and IPINs (direct-connections)
+ ***********************************************************************/
+void build_rr_graph_edges(RRGraph& rr_graph, 
+                          const vtr::vector<RRNodeId, RRSwitchId>& rr_node_driver_switches,
+                          const DeviceGrid& grids,
+                          const vtr::Point<size_t>& device_chan_width, 
+                          const std::vector<t_segment_inf>& segment_inf,
+                          int** Fc_in, int** Fc_out,
+                          const e_switch_block_type& sb_type, const int& Fs,
+                          const e_switch_block_type& sb_subtype, const int& subFs,
+                          const bool& wire_opposite_side) {
+
+  /* Create edges for SOURCE and SINK nodes for a tileable rr_graph */
+  build_rr_graph_edges_for_source_nodes(rr_graph, rr_node_driver_switches, grids);
+  build_rr_graph_edges_for_sink_nodes(rr_graph, rr_node_driver_switches, grids);
+
+  vtr::Point<size_t> gsb_range(grids.width() - 2, grids.height() - 2);
+
+  /* Go Switch Block by Switch Block */
+  for (size_t ix = 0; ix <= gsb_range.x(); ++ix) {
+    for (size_t iy = 0; iy <= gsb_range.y(); ++iy) { 
+      //vpr_printf(TIO_MESSAGE_INFO, "Building edges for GSB[%lu][%lu]\n", ix, iy);
+
+      vtr::Point<size_t> gsb_coord(ix, iy);
+      /* Create a GSB object */
+      const RRGSB& rr_gsb = build_one_tileable_rr_gsb(grids, rr_graph,
+                                                      device_chan_width, segment_inf,
+                                                      gsb_coord);
+
+      /* adapt the track_to_ipin_lookup for the GSB nodes */      
+      t_track2pin_map track2ipin_map; /* [0..track_gsb_side][0..num_tracks][ipin_indices] */
+      track2ipin_map = build_gsb_track_to_ipin_map(rr_graph, rr_gsb, grids, segment_inf, Fc_in);
+
+      /* adapt the opin_to_track_map for the GSB nodes */      
+      t_pin2track_map opin2track_map; /* [0..gsb_side][0..num_opin_node][track_indices] */
+      opin2track_map = build_gsb_opin_to_track_map(rr_graph, rr_gsb, grids, segment_inf, Fc_out);
+
+      /* adapt the switch_block_conn for the GSB nodes */      
+      t_track2track_map sb_conn; /* [0..from_gsb_side][0..chan_width-1][track_indices] */
+      sb_conn = build_gsb_track_to_track_map(rr_graph, rr_gsb, 
+                                             sb_type, Fs, sb_subtype, subFs, wire_opposite_side, 
+                                             segment_inf);
+
+      /* Build edges for a GSB */
+      build_edges_for_one_tileable_rr_gsb(rr_graph, rr_gsb,
+                                          track2ipin_map, opin2track_map, 
+                                          sb_conn, rr_node_driver_switches);
+      /* Finish this GSB, go to the next*/
+    }
+  }
+}
+
+/************************************************************************
+ * Build direct edges for Grids *
+ ***********************************************************************/
+void build_rr_graph_direct_connections(RRGraph& rr_graph, 
+                                       const DeviceGrid& grids, 
+                                       const RRSwitchId& delayless_switch, 
+                                       const std::vector<t_direct_inf>& directs, 
+                                       const std::vector<t_clb_to_clb_directs>& clb_to_clb_directs) {
+  for (size_t ix = 0; ix < grids.width(); ++ix) {
+    for (size_t iy = 0; iy < grids.height(); ++iy) { 
+      /* Skip EMPTY tiles */
+      if (true == is_empty_type(grids[ix][iy].type)) {
+        continue;
+      }
+      /* Skip height > 1 or width > 1 tiles (mostly heterogeneous blocks) */
+      if ( (0 < grids[ix][iy].width_offset)
+        || (0 < grids[ix][iy].height_offset) ) {
+        continue;
+      }
+      vtr::Point<size_t> from_grid_coordinate(ix, iy);
+      build_direct_connections_for_one_gsb(rr_graph,
+                                           grids,
+                                           from_grid_coordinate,
+                                           delayless_switch, 
+                                           directs, clb_to_clb_directs);
+    }
+  }
+}
+ 
+} /* end namespace openfpga */
diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h
new file mode 100644
index 000000000..34c2ced24
--- /dev/null
+++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h
@@ -0,0 +1,42 @@
+#ifndef TILEABLE_RR_GRAPH_EDGE_BUILDER_H
+#define TILEABLE_RR_GRAPH_EDGE_BUILDER_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <vector>
+
+/* Headers from vtrutil library */
+#include "vtr_geometry.h"
+
+#include "physical_types.h"
+#include "device_grid.h"
+#include "rr_graph_obj.h"
+#include "clb2clb_directs.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void build_rr_graph_edges(RRGraph& rr_graph, 
+                          const vtr::vector<RRNodeId, RRSwitchId>& rr_node_driver_switches,
+                          const DeviceGrid& grids,
+                          const vtr::Point<size_t>& device_chan_width, 
+                          const std::vector<t_segment_inf>& segment_inf,
+                          int** Fc_in, int** Fc_out,
+                          const e_switch_block_type& sb_type, const int& Fs,
+                          const e_switch_block_type& sb_subtype, const int& subFs,
+                          const bool& wire_opposite_side);
+
+void build_rr_graph_direct_connections(RRGraph& rr_graph, 
+                                       const DeviceGrid& grids, 
+                                       const RRSwitchId& delayless_switch, 
+                                       const std::vector<t_direct_inf>& directs, 
+                                       const std::vector<t_clb_to_clb_directs>& clb_to_clb_directs);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp
index 9cbc69dff..e2bf6e4ce 100755
--- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp
+++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp
@@ -620,7 +620,7 @@ RRChan build_one_tileable_rr_chan(const vtr::Point<size_t>& chan_coordinate,
  ***********************************************************************/
 RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, 
                                 const RRGraph& rr_graph,
-                                const std::vector<size_t>& device_chan_width, 
+                                const vtr::Point<size_t>& device_chan_width, 
                                 const std::vector<t_segment_inf>& segment_inf,
                                 const vtr::Point<size_t>& gsb_coordinate) {
   /* Create an object to return */
@@ -650,9 +650,9 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids,
     /* Build a segment details, where we need the segment ids for building rr_chan  
      * We do not care starting and ending points here, so set chan_side as NUM_SIDES 
      */
-    ChanNodeDetails chanx_details = build_unidir_chan_node_details(device_chan_width[0], grids.width() - 1, 
+    ChanNodeDetails chanx_details = build_unidir_chan_node_details(device_chan_width.x(), grids.width() - 1, 
                                                                    false, false, segment_inf); 
-    ChanNodeDetails chany_details = build_unidir_chan_node_details(device_chan_width[1], grids.height() - 1, 
+    ChanNodeDetails chany_details = build_unidir_chan_node_details(device_chan_width.y(), grids.height() - 1, 
                                                                    false, false, segment_inf); 
 
     switch (side) {
@@ -907,7 +907,7 @@ void build_edges_for_one_tileable_rr_gsb(RRGraph& rr_graph,
                                          const t_track2pin_map& track2ipin_map,
                                          const t_pin2track_map& opin2track_map,
                                          const t_track2track_map& track2track_map,
-                                         const vtr::vector<RRNodeId, RRSwitchId> rr_node_driver_switches) {
+                                         const vtr::vector<RRNodeId, RRSwitchId>& rr_node_driver_switches) {
   
   /* Walk through each sides */ 
   for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h
index 170249f74..7c7568fb9 100755
--- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h
+++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h
@@ -44,7 +44,7 @@ t_track2track_map build_gsb_track_to_track_map(const RRGraph& rr_graph,
 
 RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, 
                                 const RRGraph& rr_graph,
-                                const std::vector<size_t>& device_chan_width, 
+                                const vtr::Point<size_t>& device_chan_width, 
                                 const std::vector<t_segment_inf>& segment_inf,
                                 const vtr::Point<size_t>& gsb_coordinate);
 
@@ -53,7 +53,7 @@ void build_edges_for_one_tileable_rr_gsb(RRGraph& rr_graph,
                                          const t_track2pin_map& track2ipin_map,
                                          const t_pin2track_map& opin2track_map,
                                          const t_track2track_map& track2track_map,
-                                         const vtr::vector<RRNodeId, RRSwitchId> rr_node_driver_switches);
+                                         const vtr::vector<RRNodeId, RRSwitchId>& rr_node_driver_switches);
 
 t_track2pin_map build_gsb_track_to_ipin_map(const RRGraph& rr_graph,
                                             const RRGSB& rr_gsb, 

From 441de129366d77d218bb6d0b18642f4cea1782ad Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 6 Mar 2020 14:43:12 -0700
Subject: [PATCH 259/645] adapt Fc in gsb connection builder to use VPR8 Fc
 builder

---
 .../tileable_rr_graph_edge_builder.cpp        |  3 +-
 .../tileable_rr_graph_edge_builder.h          |  4 +-
 .../tileable_rr_graph_gsb.cpp                 | 57 +++++++++++++------
 .../tileable_rr_graph/tileable_rr_graph_gsb.h |  4 +-
 4 files changed, 47 insertions(+), 21 deletions(-)

diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp
index 185e4923b..fd2d4db62 100644
--- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp
+++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp
@@ -92,7 +92,8 @@ void build_rr_graph_edges(RRGraph& rr_graph,
                           const DeviceGrid& grids,
                           const vtr::Point<size_t>& device_chan_width, 
                           const std::vector<t_segment_inf>& segment_inf,
-                          int** Fc_in, int** Fc_out,
+                          const std::vector<vtr::Matrix<int>>& Fc_in,
+                          const std::vector<vtr::Matrix<int>>& Fc_out,
                           const e_switch_block_type& sb_type, const int& Fs,
                           const e_switch_block_type& sb_subtype, const int& subFs,
                           const bool& wire_opposite_side) {
diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h
index 34c2ced24..4a643fcda 100644
--- a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h
+++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h
@@ -7,6 +7,7 @@
 #include <vector>
 
 /* Headers from vtrutil library */
+#include "vtr_ndmatrix.h"
 #include "vtr_geometry.h"
 
 #include "physical_types.h"
@@ -26,7 +27,8 @@ void build_rr_graph_edges(RRGraph& rr_graph,
                           const DeviceGrid& grids,
                           const vtr::Point<size_t>& device_chan_width, 
                           const std::vector<t_segment_inf>& segment_inf,
-                          int** Fc_in, int** Fc_out,
+                          const std::vector<vtr::Matrix<int>>& Fc_in,
+                          const std::vector<vtr::Matrix<int>>& Fc_out,
                           const e_switch_block_type& sb_type, const int& Fs,
                           const e_switch_block_type& sb_subtype, const int& subFs,
                           const bool& wire_opposite_side);
diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp
index e2bf6e4ce..cca9e001c 100755
--- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp
+++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp
@@ -966,7 +966,7 @@ void build_gsb_one_ipin_track2pin_map(const RRGraph& rr_graph,
                                       const RRGSB& rr_gsb, 
                                       const enum e_side& ipin_side, 
                                       const size_t& ipin_node_id, 
-                                      const size_t& Fc, 
+                                      const std::vector<int>& Fc, 
                                       const size_t& offset, 
                                       const std::vector<t_segment_inf>& segment_inf, 
                                       t_track2pin_map& track2ipin_map) {
@@ -995,7 +995,7 @@ void build_gsb_one_ipin_track2pin_map(const RRGraph& rr_graph,
     VTR_ASSERT(0 == actual_track_list.size() % 2);
    
     /* Scale Fc  */
-    int actual_Fc = std::ceil((float)Fc * (float)actual_track_list.size() / (float)chan_width); 
+    int actual_Fc = std::ceil((float)Fc[iseg] * (float)actual_track_list.size() / (float)chan_width); 
     /* Minimum Fc should be 2 : ensure we will connect to a pair of routing tracks */
     actual_Fc = std::max(1, actual_Fc);
     /* Compute the step between two connection from this IPIN to tracks: 
@@ -1060,7 +1060,7 @@ void build_gsb_one_opin_pin2track_map(const RRGraph& rr_graph,
                                       const RRGSB& rr_gsb, 
                                       const enum e_side& opin_side, 
                                       const size_t& opin_node_id, 
-                                      const size_t& Fc, 
+                                      const std::vector<int>& Fc,
                                       const size_t& offset, 
                                       const std::vector<t_segment_inf>& segment_inf, 
                                       t_pin2track_map& opin2track_map) {
@@ -1094,7 +1094,7 @@ void build_gsb_one_opin_pin2track_map(const RRGraph& rr_graph,
     }
    
     /* Scale Fc  */
-    int actual_Fc = std::ceil((float)Fc * (float)actual_track_list.size() / (float)chan_width); 
+    int actual_Fc = std::ceil((float)Fc[iseg] * (float)actual_track_list.size() / (float)chan_width); 
     /* Minimum Fc should be 1 : ensure we will drive 1 routing track */
     actual_Fc = std::max(1, actual_Fc);
     /* Compute the step between two connection from this IPIN to tracks: 
@@ -1144,8 +1144,6 @@ void build_gsb_one_opin_pin2track_map(const RRGraph& rr_graph,
     }
     */
   }
-  
-  return;
 }
 
 
@@ -1163,7 +1161,7 @@ t_track2pin_map build_gsb_track_to_ipin_map(const RRGraph& rr_graph,
                                             const RRGSB& rr_gsb, 
                                             const DeviceGrid& grids, 
                                             const std::vector<t_segment_inf>& segment_inf, 
-                                            int** Fc_in) {
+                                            const std::vector<vtr::Matrix<int>>& Fc_in) {
   t_track2pin_map track2ipin_map;
   /* Resize the matrix */ 
   track2ipin_map.resize(rr_gsb.get_num_sides());
@@ -1202,16 +1200,29 @@ t_track2pin_map build_gsb_track_to_ipin_map(const RRGraph& rr_graph,
       if (true == is_empty_type(grids[rr_graph.node_xlow(ipin_node)][rr_graph.node_ylow(ipin_node)].type)) {
         continue;
       }
+
       int grid_type_index = grids[rr_graph.node_xlow(ipin_node)][rr_graph.node_ylow(ipin_node)].type->index; 
       /* Get Fc of the ipin */
-      int ipin_Fc = Fc_in[grid_type_index][rr_graph.node_pin_num(ipin_node)];
-      /* skip Fc = 0 */
-      if ( (-1 == ipin_Fc)
-        || (0 == ipin_Fc) ) { 
+      /* skip Fc = 0 or unintialized, those pins are in the <directlist> */
+      bool skip_conn2track = true; 
+      std::vector<int> ipin_Fc_out;
+      for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) {
+        int ipin_Fc = Fc_in[grid_type_index][rr_graph.node_pin_num(ipin_node)][iseg];
+        ipin_Fc_out.push_back(ipin_Fc);
+        if (0 != ipin_Fc) { 
+          skip_conn2track = false;
+          break;
+        }
+      }
+
+      if (true == skip_conn2track) {
         continue;
       }
+
+      VTR_ASSERT(ipin_Fc_out.size() == segment_inf.size());
+
       /* Build track2ipin_map for this IPIN */
-      build_gsb_one_ipin_track2pin_map(rr_graph, rr_gsb, ipin_side, inode, ipin_Fc, 
+      build_gsb_one_ipin_track2pin_map(rr_graph, rr_gsb, ipin_side, inode, ipin_Fc_out, 
                                        /* Give an offset for the first track that this ipin will connect to */
                                        offset[chan_side_manager.to_size_t()], 
                                        segment_inf, track2ipin_map);
@@ -1240,7 +1251,7 @@ t_pin2track_map build_gsb_opin_to_track_map(const RRGraph& rr_graph,
                                             const RRGSB& rr_gsb, 
                                             const DeviceGrid& grids, 
                                             const std::vector<t_segment_inf>& segment_inf, 
-                                            int** Fc_out) {
+                                            const std::vector<vtr::Matrix<int>>& Fc_out) {
   t_pin2track_map opin2track_map;
   /* Resize the matrix */ 
   opin2track_map.resize(rr_gsb.get_num_sides());
@@ -1269,15 +1280,27 @@ t_pin2track_map build_gsb_opin_to_track_map(const RRGraph& rr_graph,
         continue;
       }
       int grid_type_index = grids[rr_graph.node_xlow(opin_node)][rr_graph.node_ylow(opin_node)].type->index; 
+
       /* Get Fc of the ipin */
-      int opin_Fc = Fc_out[grid_type_index][rr_graph.node_pin_num(opin_node)];
       /* skip Fc = 0 or unintialized, those pins are in the <directlist> */
-      if ( (-1 == opin_Fc)
-        || (0 == opin_Fc) ) { 
+      bool skip_conn2track = true; 
+      std::vector<int> opin_Fc_out;
+      for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) {
+        int opin_Fc = Fc_out[grid_type_index][rr_graph.node_pin_num(opin_node)][iseg];
+        opin_Fc_out.push_back(opin_Fc);
+        if (0 != opin_Fc) { 
+          skip_conn2track = false;
+          break;
+        }
+      }
+
+      if (true == skip_conn2track) {
         continue;
       }
+      VTR_ASSERT(opin_Fc_out.size() == segment_inf.size());
+
       /* Build track2ipin_map for this IPIN */
-      build_gsb_one_opin_pin2track_map(rr_graph, rr_gsb, opin_side, inode, opin_Fc, 
+      build_gsb_one_opin_pin2track_map(rr_graph, rr_gsb, opin_side, inode, opin_Fc_out, 
                                        /* Give an offset for the first track that this ipin will connect to */
                                        offset[side_manager.to_size_t()], 
                                        segment_inf, opin2track_map);
diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h
index 7c7568fb9..adf6118fb 100755
--- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h
+++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h
@@ -59,13 +59,13 @@ t_track2pin_map build_gsb_track_to_ipin_map(const RRGraph& rr_graph,
                                             const RRGSB& rr_gsb, 
                                             const DeviceGrid& grids, 
                                             const std::vector<t_segment_inf>& segment_inf, 
-                                            int** Fc_in);
+                                            const std::vector<vtr::Matrix<int>>& Fc_in);
 
 t_pin2track_map build_gsb_opin_to_track_map(const RRGraph& rr_graph,
                                             const RRGSB& rr_gsb, 
                                             const DeviceGrid& grids, 
                                             const std::vector<t_segment_inf>& segment_inf, 
-                                            int** Fc_out);
+                                            const std::vector<vtr::Matrix<int>>& Fc_out);
 
 void build_direct_connections_for_one_gsb(RRGraph& rr_graph,
                                           const DeviceGrid& grids,

From 441a30710084631f5da10a07c5a253a407b1cd5c Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 6 Mar 2020 14:54:40 -0700
Subject: [PATCH 260/645] add routing chan width corrector to rr_graph builder
 utils

---
 .../tileable_rr_graph/rr_graph_builder_utils.cpp  | 15 +++++++++++++++
 .../tileable_rr_graph/rr_graph_builder_utils.h    |  2 ++
 .../tileable_chan_details_builder.cpp             |  7 ++-----
 3 files changed, 19 insertions(+), 5 deletions(-)

diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp
index 47926e8c7..446518faf 100644
--- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp
+++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp
@@ -15,6 +15,21 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
+/************************************************************************
+ * Correct number of routing channel width to be compatible to 
+ * uni-directional routing architecture
+ ***********************************************************************/
+size_t find_unidir_routing_channel_width(const size_t& chan_width) {
+  size_t actual_chan_width = chan_width;
+  /* Correct the chan_width: it should be an even number */
+  if (0 != actual_chan_width % 2) {
+    actual_chan_width++; /* increment it to be even */
+  }
+  VTR_ASSERT(0 == actual_chan_width % 2);
+
+  return actual_chan_width;
+}
+
 /************************************************************************
  * Get the class index of a grid pin 
  ***********************************************************************/
diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h
index 1367466d4..b63afa59d 100644
--- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h
+++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h
@@ -15,6 +15,8 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
+size_t find_unidir_routing_channel_width(const size_t& chan_width);
+
 int get_grid_pin_class_index(const t_grid_tile& cur_grid,
                              const int pin_index);
 
diff --git a/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp
index 23c1d7c07..ec02b1bb1 100644
--- a/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp
+++ b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp
@@ -11,6 +11,7 @@
 #include "vtr_assert.h"
 #include "vtr_log.h"
 
+#include "rr_graph_builder_utils.h"
 #include "tileable_chan_details_builder.h"
 
 /* begin namespace openfpga */
@@ -167,11 +168,7 @@ ChanNodeDetails build_unidir_chan_node_details(const size_t& chan_width,
                                                const bool& force_end, 
                                                const std::vector<t_segment_inf>& segment_inf) {
   ChanNodeDetails chan_node_details;
-  size_t actual_chan_width = chan_width;
-  /* Correct the chan_width: it should be an even number */
-  if (0 != actual_chan_width % 2) {
-    actual_chan_width++; /* increment it to be even */
-  }
+  size_t actual_chan_width = find_unidir_routing_channel_width(chan_width);
   VTR_ASSERT(0 == actual_chan_width % 2);
   
   /* Reserve channel width */

From 3eb59d201f10308870304022cbacfa65b065ae96 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 6 Mar 2020 15:24:26 -0700
Subject: [PATCH 261/645] adapt top function of tileable rr_graph builder

---
 vpr/src/device/rr_graph_obj.h                 |  12 +-
 vpr/src/route/check_rr_graph.h                |   1 +
 vpr/src/route/rr_graph.cpp                    |  56 +--
 vpr/src/route/rr_graph.h                      |  27 ++
 .../tileable_chan_details_builder.cpp         |   1 -
 .../tileable_chan_details_builder.h           |   4 +
 .../tileable_rr_graph_builder.cpp             | 323 ++++++++++++++++++
 .../tileable_rr_graph_builder.h               |  38 +++
 8 files changed, 413 insertions(+), 49 deletions(-)
 create mode 100644 vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp
 create mode 100644 vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h

diff --git a/vpr/src/device/rr_graph_obj.h b/vpr/src/device/rr_graph_obj.h
index 08abf682c..648934554 100644
--- a/vpr/src/device/rr_graph_obj.h
+++ b/vpr/src/device/rr_graph_obj.h
@@ -583,6 +583,12 @@ class RRGraph {
     /* Validate is the edge id does exist in the RRGraph */
     bool valid_edge_id(const RREdgeId& edge) const;
 
+    /* Validate switch list */
+    bool valid_switch_id(const RRSwitchId& switch_id) const;
+
+    /* Validate segment list */
+    bool valid_segment_id(const RRSegmentId& segment_id) const;
+
   public: /* Mutators */
     /* Reserve the lists of nodes, edges, switches etc. to be memory efficient. 
      * This function is mainly used to reserve memory space inside RRGraph,
@@ -835,12 +841,6 @@ class RRGraph {
     bool validate_edge_src_nodes() const;
     bool validate_edge_sink_nodes() const;
 
-    /* Validate switch list */
-    bool valid_switch_id(const RRSwitchId& switch_id) const;
-
-    /* Validate segment list */
-    bool valid_segment_id(const RRSegmentId& segment_id) const;
-
   private: /* Internal Data */
     /* Node related data */
     size_t num_nodes_;                              /* Range of node ids */
diff --git a/vpr/src/route/check_rr_graph.h b/vpr/src/route/check_rr_graph.h
index 71d435e70..2416fe666 100644
--- a/vpr/src/route/check_rr_graph.h
+++ b/vpr/src/route/check_rr_graph.h
@@ -1,6 +1,7 @@
 #ifndef CHECK_RR_GRAPH_H
 #define CHECK_RR_GRAPH_H
 #include "physical_types.h"
+#include "vpr_context.h"
 
 void check_rr_graph(const t_graph_type graph_type,
                     const DeviceGrid& grid,
diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp
index ae6e2593e..50f2799d9 100644
--- a/vpr/src/route/rr_graph.cpp
+++ b/vpr/src/route/rr_graph.cpp
@@ -236,30 +236,12 @@ void uniquify_edges(t_rr_edge_info_set& rr_edges_to_create);
 void alloc_and_load_edges(RRGraph& rr_graph,
                           const t_rr_edge_info_set& rr_edges_to_create);
 
-static void alloc_and_load_rr_switch_inf(const int num_arch_switches,
-                                         const float R_minW_nmos,
-                                         const float R_minW_pmos,
-                                         const int wire_to_arch_ipin_switch,
-                                         int* wire_to_rr_ipin_switch);
-
-static 
-t_rr_switch_inf create_rr_switch_from_arch_switch(int arch_switch_idx,
-                                                  const float R_minW_nmos,
-                                                  const float R_minW_pmos);
-
 static void remap_rr_node_switch_indices(const t_arch_switch_fanin& switch_fanin);
 
 static void load_rr_switch_inf(const int num_arch_switches, const float R_minW_nmos, const float R_minW_pmos, const t_arch_switch_fanin& switch_fanin);
 
 static void alloc_rr_switch_inf(t_arch_switch_fanin& switch_fanin);
 
-static void rr_graph_externals(const std::vector<t_segment_inf>& segment_inf,
-                               int max_chan_width,
-                               int wire_to_rr_ipin_switch,
-                               enum e_base_cost_type base_cost_type);
-
-static t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const t_direct_inf* directs, const int num_directs, const int delayless_switch);
-
 static void free_type_track_to_pin_map(t_track_to_pin_lookup& track_to_pin_map,
                                        const std::vector<t_physical_tile_type>& types,
                                        int max_chan_width);
@@ -267,15 +249,6 @@ static void free_type_track_to_pin_map(t_track_to_pin_lookup& track_to_pin_map,
 static t_seg_details* alloc_and_load_global_route_seg_details(const int global_route_switch,
                                                               int* num_seg_details = nullptr);
 
-static std::vector<vtr::Matrix<int>> alloc_and_load_actual_fc(const std::vector<t_physical_tile_type>& types,
-                                                              const int max_pins,
-                                                              const std::vector<t_segment_inf>& segment_inf,
-                                                              const int* sets_per_seg_type,
-                                                              const int max_chan_width,
-                                                              const e_fc_type fc_type,
-                                                              const enum e_directionality directionality,
-                                                              bool* Fc_clipped);
-
 static RRNodeId pick_best_direct_connect_target_rr_node(const RRGraph& rr_graph,
                                                         const RRNodeId& from_rr,
                                                         const std::vector<RRNodeId>& candidate_rr_nodes);
@@ -836,7 +809,7 @@ static void build_rr_graph(const t_graph_type graph_type,
  * and count how many different fan-ins exist for each arch switch.
  * Then we create these rr switches and update the switch indices
  * of rr_nodes to index into the rr_switch_inf array. */
-static void alloc_and_load_rr_switch_inf(const int num_arch_switches, const float R_minW_nmos, const float R_minW_pmos, const int wire_to_arch_ipin_switch, int* wire_to_rr_ipin_switch) {
+void alloc_and_load_rr_switch_inf(const int num_arch_switches, const float R_minW_nmos, const float R_minW_pmos, const int wire_to_arch_ipin_switch, int* wire_to_rr_ipin_switch) {
     /* we will potentially be creating a couple of versions of each arch switch where
      * each version corresponds to a different fan-in. We will need to fill device_ctx.rr_switch_inf
      * with this expanded list of switches.
@@ -962,7 +935,6 @@ static void load_rr_switch_inf(const int num_arch_switches, const float R_minW_n
 
 }
 
-static 
 t_rr_switch_inf create_rr_switch_from_arch_switch(int arch_switch_idx,
                                                   const float R_minW_nmos,
                                                   const float R_minW_pmos) {
@@ -1057,10 +1029,10 @@ static void remap_rr_node_switch_indices(const t_arch_switch_fanin& switch_fanin
     }
 }
 
-static void rr_graph_externals(const std::vector<t_segment_inf>& segment_inf,
-                               int max_chan_width,
-                               int wire_to_rr_ipin_switch,
-                               enum e_base_cost_type base_cost_type) {
+void rr_graph_externals(const std::vector<t_segment_inf>& segment_inf,
+                        int max_chan_width,
+                        int wire_to_rr_ipin_switch,
+                        enum e_base_cost_type base_cost_type) {
     auto& device_ctx = g_vpr_ctx.device();
 
     add_rr_graph_C_from_switches(device_ctx.rr_switch_inf[wire_to_rr_ipin_switch].Cin);
@@ -1152,14 +1124,14 @@ static t_seg_details* alloc_and_load_global_route_seg_details(const int global_r
 }
 
 /* Calculates the number of track connections from each block pin to each segment type */
-static std::vector<vtr::Matrix<int>> alloc_and_load_actual_fc(const std::vector<t_physical_tile_type>& types,
-                                                              const int max_pins,
-                                                              const std::vector<t_segment_inf>& segment_inf,
-                                                              const int* sets_per_seg_type,
-                                                              const int max_chan_width,
-                                                              const e_fc_type fc_type,
-                                                              const enum e_directionality directionality,
-                                                              bool* Fc_clipped) {
+std::vector<vtr::Matrix<int>> alloc_and_load_actual_fc(const std::vector<t_physical_tile_type>& types,
+                                                       const int max_pins,
+                                                       const std::vector<t_segment_inf>& segment_inf,
+                                                       const int* sets_per_seg_type,
+                                                       const int max_chan_width,
+                                                       const e_fc_type fc_type,
+                                                       const enum e_directionality directionality,
+                                                       bool* Fc_clipped) {
     //Initialize Fc of all blocks to zero
     auto zeros = vtr::Matrix<int>({size_t(max_pins), segment_inf.size()}, 0);
     std::vector<vtr::Matrix<int>> Fc(types.size(), zeros);
@@ -2775,7 +2747,7 @@ static void build_unidir_rr_opins(const int i, const int j,
  * This data structure supplements the the info in the "directs" data structure
  * TODO: The function that does this parsing in placement is poorly done because it lacks generality on heterogeniety, should replace with this one
  */
-static t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const t_direct_inf* directs, const int num_directs, int delayless_switch) {
+t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const t_direct_inf* directs, const int num_directs, int delayless_switch) {
     int i;
     t_clb_to_clb_directs* clb_to_clb_directs;
     char *tile_name, *port_name;
diff --git a/vpr/src/route/rr_graph.h b/vpr/src/route/rr_graph.h
index 1f60b1afc..35ddcc138 100644
--- a/vpr/src/route/rr_graph.h
+++ b/vpr/src/route/rr_graph.h
@@ -7,6 +7,7 @@
 #define INCLUDE_TRACK_BUFFERS false
 
 #include "device_grid.h"
+#include "clb2clb_directs.h"
 
 enum e_graph_type {
     GRAPH_GLOBAL, /* One node per channel with wire capacity > 1 and full connectivity */
@@ -56,4 +57,30 @@ void load_rr_switch_from_arch_switch(int arch_switch_idx,
 
 t_non_configurable_rr_sets identify_non_configurable_rr_sets();
 
+void rr_graph_externals(const std::vector<t_segment_inf>& segment_inf,
+                        int max_chan_width,
+                        int wire_to_rr_ipin_switch,
+                        enum e_base_cost_type base_cost_type);
+
+void alloc_and_load_rr_switch_inf(const int num_arch_switches,
+                                  const float R_minW_nmos,
+                                  const float R_minW_pmos,
+                                  const int wire_to_arch_ipin_switch,
+                                  int* wire_to_rr_ipin_switch);
+
+t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const t_direct_inf* directs, const int num_directs, const int delayless_switch);
+
+std::vector<vtr::Matrix<int>> alloc_and_load_actual_fc(const std::vector<t_physical_tile_type>& types,
+                                                       const int max_pins,
+                                                       const std::vector<t_segment_inf>& segment_inf,
+                                                       const int* sets_per_seg_type,
+                                                       const int max_chan_width,
+                                                       const e_fc_type fc_type,
+                                                       const enum e_directionality directionality,
+                                                       bool* Fc_clipped);
+
+t_rr_switch_inf create_rr_switch_from_arch_switch(int arch_switch_idx,
+                                                  const float R_minW_nmos,
+                                                  const float R_minW_pmos);
+
 #endif
diff --git a/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp
index ec02b1bb1..67c8dbe27 100644
--- a/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp
+++ b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp
@@ -26,7 +26,6 @@ namespace openfpga {
  * therefore, we assign tracks one by one until we meet the frequency requirement
  * In this way, we can assign the number of tracks with repect to frequency 
  ***********************************************************************/
-static 
 std::vector<size_t> get_num_tracks_per_seg_type(const size_t& chan_width, 
                                                 const std::vector<t_segment_inf>& segment_inf, 
                                                 const bool& use_full_seg_groups) {
diff --git a/vpr/src/tileable_rr_graph/tileable_chan_details_builder.h b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.h
index b1a1198b9..e6adb7162 100644
--- a/vpr/src/tileable_rr_graph/tileable_chan_details_builder.h
+++ b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.h
@@ -15,6 +15,10 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
+std::vector<size_t> get_num_tracks_per_seg_type(const size_t& chan_width, 
+                                                const std::vector<t_segment_inf>& segment_inf, 
+                                                const bool& use_full_seg_groups);
+
 int adapt_to_tileable_route_chan_width(const int& chan_width, const std::vector<t_segment_inf>& segment_inf);
 
 ChanNodeDetails build_unidir_chan_node_details(const size_t& chan_width,
diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp
new file mode 100644
index 000000000..d9f98d895
--- /dev/null
+++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp
@@ -0,0 +1,323 @@
+/************************************************************************
+ *  This file contains a builder for the complex rr_graph data structure 
+ *  Different from VPR rr_graph builders, this builder aims to create a 
+ *  highly regular rr_graph, where each Connection Block (CB), Switch 
+ *  Block (SB) is the same (except for those on the borders). Thus, the
+ *  rr_graph is called tileable, which brings significant advantage in 
+ *  producing large FPGA fabrics.
+ ***********************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_time.h"
+#include "vtr_log.h"
+#include "vtr_memory.h"
+
+#include "vpr_error.h"
+#include "vpr_utils.h"
+
+#include "rr_graph.h"
+#include "check_rr_graph.h"
+#include "check_rr_graph_obj.h"
+
+#include "rr_graph_builder_utils.h"
+#include "tileable_chan_details_builder.h"
+#include "tileable_rr_graph_node_builder.h"
+#include "tileable_rr_graph_edge_builder.h"
+#include "tileable_rr_graph_builder.h"
+
+#include "globals.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/************************************************************************
+ * Main function of this file
+ * Builder for a detailed uni-directional tileable rr_graph
+ * Global graph is not supported here, the VPR rr_graph generator can be used  
+ * It follows the procedures to complete the rr_graph generation
+ * 1. Assign the segments for each routing channel,
+ *    To be specific, for each routing track, we assign a routing segment.
+ *    The assignment is subject to users' specifications, such as 
+ *    a. length of each type of segment
+ *    b. frequency of each type of segment.
+ *    c. routing channel width
+ * 2. Estimate the number of nodes in the rr_graph
+ *    This will estimate the number of 
+ *    a. IPINs, input pins of each grid
+ *    b. OPINs, output pins of each grid
+ *    c. SOURCE, virtual node which drives OPINs
+ *    d. SINK, virtual node which is connected to IPINs
+ *    e. CHANX and CHANY, routing segments of each channel
+ * 3. Create the connectivity of OPINs
+ *    a. Evenly assign connections to OPINs to routing tracks
+ *    b. the connection pattern should be same across the fabric
+ * 4. Create the connectivity of IPINs 
+ *    a. Evenly assign connections from routing tracks to IPINs
+ *    b. the connection pattern should be same across the fabric
+ * 5. Create the switch block patterns, 
+ *    It is based on the type of switch block, the supported patterns are 
+ *    a. Disjoint, which connects routing track (i)th from (i)th and (i)th routing segments
+ *    b. Universal, which connects routing track (i)th from (i)th and (M-i)th routing segments
+ *    c. Wilton, which rotates the connection of Disjoint by 1 track
+ * 6. Allocate rr_graph, fill the node information
+ *    For each node, fill
+ *    a. basic information: coordinate(xlow, xhigh, ylow, yhigh), ptc_num
+ *    b. edges (both incoming and outcoming)
+ *    c. handle direct-connections
+ * 7. Build fast look-up for the rr_graph 
+ * 8. Allocate external data structures
+ *    a. cost_index
+ *    b. RC tree
+ ***********************************************************************/
+void build_tileable_unidir_rr_graph(const std::vector<t_physical_tile_type>& types,
+                                    const DeviceGrid& grids,
+                                    const t_chan_width& chan_width,
+                                    const e_switch_block_type& sb_type, const int& Fs, 
+                                    const e_switch_block_type& sb_subtype, const int& subFs, 
+                                    const std::vector<t_segment_inf>& segment_inf,
+                                    const int& delayless_switch, 
+                                    const int& wire_to_arch_ipin_switch,
+                                    const float R_minW_nmos,
+                                    const float R_minW_pmos,
+                                    const enum e_base_cost_type& base_cost_type, 
+                                    const t_direct_inf *directs, 
+                                    const int& num_directs,
+                                    int* wire_to_rr_ipin_switch,
+                                    const bool& wire_opposite_side,
+                                    int *Warnings) { 
+
+  vtr::ScopedStartFinishTimer timer("Build tileable routing resource graph");
+
+  /* Reset warning flag */
+  *Warnings = RR_GRAPH_NO_WARN;
+
+  /* Create a matrix of grid */
+  /* Create a vector of channel width, we support X-direction and Y-direction has different W */
+  vtr::Point<size_t> device_chan_width(chan_width.x_max, chan_width.y_max);
+
+  VTR_LOG("X-direction routing channel width is %lu\n", device_chan_width.x());
+  VTR_LOG("Y-direction routing channel width is %lu\n", device_chan_width.y());
+
+  /* Get a mutable device ctx so that we have a mutable rr_graph */
+  DeviceContext& device_ctx = g_vpr_ctx.mutable_device();
+
+  /* The number of segments are in general small, reserve segments may not bring
+   * significant memory efficiency */
+  device_ctx.rr_graph.reserve_segments(segment_inf.size());
+  /* Create the segments */
+  for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) {
+    device_ctx.rr_graph.create_segment(segment_inf[iseg]);
+  }
+
+  /* TODO: Load architecture switch to rr_graph switches 
+   * Draft the switches as internal data of RRGraph object
+   * These are temporary switches copied from arch switches
+   * We use them to build the edges 
+   * We will reset all the switches in the function 
+   *   alloc_and_load_rr_switch_inf()
+   */
+  /* TODO: Spot the switch id in the architecture switch list */
+  RRSwitchId wire_to_ipin_rr_switch = RRSwitchId::INVALID(); 
+  RRSwitchId delayless_rr_switch = RRSwitchId::INVALID();
+
+  device_ctx.rr_graph.reserve_switches(device_ctx.num_arch_switches);
+  /* Create the switches */
+  for (int iswitch = 0; iswitch < device_ctx.num_arch_switches; ++iswitch) {
+    const t_rr_switch_inf& temp_rr_switch = create_rr_switch_from_arch_switch(iswitch, R_minW_nmos, R_minW_pmos);
+    RRSwitchId rr_switch = device_ctx.rr_graph.create_switch(temp_rr_switch);
+    if (iswitch == wire_to_arch_ipin_switch) {
+      wire_to_ipin_rr_switch = rr_switch;
+    }
+    if (iswitch == delayless_switch) {
+      delayless_rr_switch = rr_switch;
+    }
+  }
+  /* Validate the special switches */
+  VTR_ASSERT(true == device_ctx.rr_graph.valid_switch_id(wire_to_ipin_rr_switch)); 
+  VTR_ASSERT(true == device_ctx.rr_graph.valid_switch_id(delayless_rr_switch)); 
+
+  /* A temp data about the driver switch ids for each rr_node */
+  vtr::vector<RRNodeId, RRSwitchId> rr_node_driver_switches; 
+
+  /* A temp data about the track ids for each CHANX and CHANY rr_node */
+  std::map<RRNodeId, std::vector<size_t>> rr_node_track_ids;
+
+  /************************
+   * Allocate the rr_nodes 
+   ************************/
+  alloc_tileable_rr_graph_nodes(device_ctx.rr_graph,
+                                rr_node_driver_switches,
+                                grids,
+                                device_chan_width,
+                                segment_inf);
+
+  /************************
+   * Create all the rr_nodes 
+   ************************/
+  create_tileable_rr_graph_nodes(device_ctx.rr_graph,
+                                 rr_node_driver_switches,
+                                 rr_node_track_ids,
+                                 grids,
+                                 device_chan_width,
+                                 segment_inf,
+                                 wire_to_ipin_rr_switch,
+                                 delayless_rr_switch); 
+
+  /************************************************************************
+   * Create the connectivity of OPINs
+   *   a. Evenly assign connections to OPINs to routing tracks
+   *   b. the connection pattern should be same across the fabric
+   *
+   * Create the connectivity of IPINs 
+   *   a. Evenly assign connections from routing tracks to IPINs
+   *   b. the connection pattern should be same across the fabric
+   ***********************************************************************/
+  /* Global routing uses a single longwire track */
+  int max_chan_width = find_unidir_routing_channel_width(chan_width.max);
+  VTR_ASSERT(max_chan_width > 0);
+
+  /* get maximum number of pins across all blocks */
+  int max_pins = types[0].num_pins;
+  for (const auto& type : types) {
+    if (is_empty_type(&type)) {
+      continue;
+    }
+
+    if (type.num_pins > max_pins) {
+      max_pins = type.num_pins;
+    }
+  }
+    
+  /* Fc assignment still uses the old function from VPR.
+   * Should use tileable version so that we have can have full control
+   */
+  std::vector<size_t> num_tracks = get_num_tracks_per_seg_type(max_chan_width / 2, segment_inf, false);  
+  int* sets_per_seg_type = (int*)vtr::malloc(sizeof(int) * segment_inf.size());
+  VTR_ASSERT(num_tracks.size() == segment_inf.size());
+  for (size_t iseg = 0; iseg < num_tracks.size(); ++iseg) {
+    sets_per_seg_type[iseg] = num_tracks[iseg];
+  }
+
+  bool Fc_clipped = false;
+  /* [0..num_types-1][0..num_pins-1] */
+  std::vector<vtr::Matrix<int>> Fc_in;
+  Fc_in = alloc_and_load_actual_fc(types, max_pins, segment_inf, sets_per_seg_type, max_chan_width,
+                                   e_fc_type::IN, UNI_DIRECTIONAL, &Fc_clipped);
+  if (Fc_clipped) {
+    *Warnings |= RR_GRAPH_WARN_FC_CLIPPED;
+  }
+
+  Fc_clipped = false;
+  /* [0..num_types-1][0..num_pins-1] */
+  std::vector<vtr::Matrix<int>> Fc_out;
+  Fc_out = alloc_and_load_actual_fc(types, max_pins, segment_inf, sets_per_seg_type, max_chan_width,
+                                    e_fc_type::OUT, UNI_DIRECTIONAL, &Fc_clipped);
+
+  if (Fc_clipped) {
+    *Warnings |= RR_GRAPH_WARN_FC_CLIPPED;
+  }
+
+  /************************************************************************
+   * Build the connections tile by tile:
+   * We classify rr_nodes into a general switch block (GSB) data structure
+   * where we create edges to each rr_nodes in the GSB with respect to
+   * Fc_in and Fc_out, switch block patterns 
+   * In addition, we will also handle direct-connections:
+   * Add edges that bridge OPINs and IPINs to the rr_graph
+   ***********************************************************************/
+  /* Create edges for a tileable rr_graph */
+  build_rr_graph_edges(device_ctx.rr_graph,
+                       rr_node_driver_switches,
+                       grids,
+                       device_chan_width,
+                       segment_inf, 
+                       Fc_in, Fc_out,
+                       sb_type, Fs, sb_subtype, subFs,
+                       wire_opposite_side);
+
+  /************************************************************************
+   * Build direction connection lists
+   * TODO: use tile direct builder
+   ***********************************************************************/
+  /* Create data structure of direct-connections */
+  t_clb_to_clb_directs* clb_to_clb_directs = NULL;
+  if (num_directs > 0) {
+    clb_to_clb_directs = alloc_and_load_clb_to_clb_directs(directs, num_directs, delayless_switch);
+  }
+  std::vector<t_direct_inf> arch_directs;
+  std::vector<t_clb_to_clb_directs> clb2clb_directs;
+  for (int idirect = 0; idirect < num_directs; ++idirect) {
+    arch_directs.push_back(directs[idirect]);
+    clb2clb_directs.push_back(clb_to_clb_directs[idirect]);
+  }
+
+  build_rr_graph_direct_connections(device_ctx.rr_graph, grids, delayless_rr_switch, 
+                                    arch_directs, clb2clb_directs);
+
+  /* First time to build edges so that we can remap the architecture switch to rr_switch
+   * This is a must-do before function alloc_and_load_rr_switch_inf() 
+   */
+  device_ctx.rr_graph.rebuild_node_edges();
+
+  /* Allocate and load routing resource switches, which are derived from the switches from the architecture file,
+   * based on their fanin in the rr graph. This routine also adjusts the rr nodes to point to these new rr switches */
+  alloc_and_load_rr_switch_inf(device_ctx.num_arch_switches, R_minW_nmos, R_minW_pmos, wire_to_arch_ipin_switch, wire_to_rr_ipin_switch);
+
+  /* Save the channel widths for the newly constructed graph */
+  device_ctx.chan_width = chan_width;
+
+  /************************************************************************
+   * Allocate external data structures
+   *  a. cost_index
+   *  b. RC tree
+   ***********************************************************************/
+  rr_graph_externals(segment_inf, max_chan_width,
+                     *wire_to_rr_ipin_switch, base_cost_type);
+
+  /* Rebuild the link between RRGraph node and segments 
+   * Should be called only AFTER the function
+   * rr_graph_externals()
+   */
+  for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) {
+    if ( (CHANX != device_ctx.rr_graph.node_type(inode))
+      && (CHANY != device_ctx.rr_graph.node_type(inode)) ) {
+      continue;
+    }
+    short irc_data = device_ctx.rr_graph.node_cost_index(inode);
+    short iseg = device_ctx.rr_indexed_data[irc_data].seg_index;
+    device_ctx.rr_graph.set_node_segment(inode, RRSegmentId(iseg));
+  }
+
+  /************************************************************************
+   * Sanitizer for the rr_graph, check connectivities of rr_nodes
+   ***********************************************************************/
+  /* Essential check for rr_graph, build look-up and  */
+  if (false == device_ctx.rr_graph.validate()) {
+    /* Error out if built-in validator of rr_graph fails */
+    vpr_throw(VPR_ERROR_ROUTE,
+              __FILE__,
+              __LINE__,
+              "Fundamental errors occurred when validating rr_graph object!\n");
+  }
+
+  check_rr_graph(GRAPH_UNIDIR, grids, types);
+  /* Error out if advanced checker of rr_graph fails */
+  if (false == check_rr_graph(device_ctx.rr_graph)) {
+    vpr_throw(VPR_ERROR_ROUTE,
+              __FILE__,
+              __LINE__,
+              "Advanced checking rr_graph object fails! Routing may still work "
+              "but not smooth\n");
+  }
+
+  /************************************************************************
+   * Free all temp stucts 
+   ***********************************************************************/
+  free(sets_per_seg_type);
+
+  if (nullptr != clb_to_clb_directs) {
+    free(clb_to_clb_directs);
+  }
+}
+
+} /* end namespace openfpga */
diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h
new file mode 100644
index 000000000..601c7de18
--- /dev/null
+++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h
@@ -0,0 +1,38 @@
+#ifndef TILEABLE_RR_GRAPH_BUILDER_H
+#define TILEABLE_RR_GRAPH_BUILDER_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <vector>
+
+#include "physical_types.h"
+#include "device_grid.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void build_tileable_unidir_rr_graph(const std::vector<t_physical_tile_type>& types,
+                                    const DeviceGrid& grids,
+                                    const t_chan_width& chan_width,
+                                    const e_switch_block_type& sb_type, const int& Fs, 
+                                    const e_switch_block_type& sb_subtype, const int& subFs, 
+                                    const std::vector<t_segment_inf>& segment_inf,
+                                    const int& delayless_switch, 
+                                    const int& wire_to_arch_ipin_switch,
+                                    const float R_minW_nmos,
+                                    const float R_minW_pmos,
+                                    const enum e_base_cost_type& base_cost_type, 
+                                    const t_direct_inf *directs, 
+                                    const int& num_directs,
+                                    int* wire_to_rr_ipin_switch,
+                                    const bool& wire_opposite_side,
+                                    int *Warnings); 
+
+} /* end namespace openfpga */
+
+#endif

From 245a379c4fbb27b280c84fe279d0437bb597b5d4 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 6 Mar 2020 16:03:00 -0700
Subject: [PATCH 262/645] start plug in tileable rr_graph builder

---
 vpr/src/base/vpr_context.h                    |  5 ++
 vpr/src/base/vpr_types.h                      |  6 ++
 vpr/src/route/rr_graph.cpp                    | 75 ++++++++++------
 .../tileable_rr_graph_builder.cpp             |  3 +
 .../tileable_rr_graph_gsb.cpp                 | 90 +++++++++++++++++++
 5 files changed, 153 insertions(+), 26 deletions(-)

diff --git a/vpr/src/base/vpr_context.h b/vpr/src/base/vpr_context.h
index 487382480..d823c921b 100644
--- a/vpr/src/base/vpr_context.h
+++ b/vpr/src/base/vpr_context.h
@@ -148,6 +148,11 @@ struct DeviceContext : public Context {
     /* RRGraph object */
     RRGraph rr_graph;
 
+    /* Track ids for each rr_node in the rr_graph.
+     * This is used by drawer for tileable routing resource graph
+     */
+    std::map<RRNodeId, std::vector<size_t>> rr_node_track_ids;
+
     /* Structures to define the routing architecture of the FPGA.           */
     std::vector<t_rr_node> rr_nodes; /* autogenerated in build_rr_graph */
 
diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h
index dee5fd7e6..009887d71 100644
--- a/vpr/src/base/vpr_types.h
+++ b/vpr/src/base/vpr_types.h
@@ -1004,6 +1004,12 @@ struct t_det_routing_arch {
     enum e_switch_block_type switch_block_type;
     std::vector<t_switchblock_inf> switchblocks;
 
+    /* Xifan Tang: subtype of switch blocks.
+     * Sub type and Fs are applied to pass tracks
+     */
+    int subFs;
+    enum e_switch_block_type switch_block_subtype;
+
     short global_route_switch;
     short delayless_switch;
     int wire_to_arch_ipin_switch;
diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp
index 50f2799d9..b21310ad4 100644
--- a/vpr/src/route/rr_graph.cpp
+++ b/vpr/src/route/rr_graph.cpp
@@ -41,6 +41,8 @@
 #include "rr_graph_obj_util.h"
 #include "check_rr_graph_obj.h"
 
+#include "tileable_rr_graph_builder.h"
+
 #include "clb2clb_directs.h"
 
 //#define VERBOSE
@@ -318,33 +320,54 @@ void create_rr_graph(const t_graph_type graph_type,
 
         free_rr_graph();
 
-        build_rr_graph(graph_type,
-                       block_types,
-                       grid,
-                       nodes_per_chan,
-                       det_routing_arch->switch_block_type,
-                       det_routing_arch->Fs,
-                       det_routing_arch->switchblocks,
-                       num_arch_switches,
-                       segment_inf,
-                       det_routing_arch->global_route_switch,
-                       det_routing_arch->wire_to_arch_ipin_switch,
-                       det_routing_arch->delayless_switch,
-                       det_routing_arch->R_minW_nmos,
-                       det_routing_arch->R_minW_pmos,
-                       base_cost_type,
-                       trim_empty_channels,
-                       trim_obs_channels,
-                       directs, num_directs,
-                       &det_routing_arch->wire_to_rr_ipin_switch,
-                       Warnings);
+        if (GRAPH_UNIDIR_TILEABLE != graph_type) {
+            build_rr_graph(graph_type,
+                           block_types,
+                           grid,
+                           nodes_per_chan,
+                           det_routing_arch->switch_block_type,
+                           det_routing_arch->Fs,
+                           det_routing_arch->switchblocks,
+                           num_arch_switches,
+                           segment_inf,
+                           det_routing_arch->global_route_switch,
+                           det_routing_arch->wire_to_arch_ipin_switch,
+                           det_routing_arch->delayless_switch,
+                           det_routing_arch->R_minW_nmos,
+                           det_routing_arch->R_minW_pmos,
+                           base_cost_type,
+                           trim_empty_channels,
+                           trim_obs_channels,
+                           directs, num_directs,
+                           &det_routing_arch->wire_to_rr_ipin_switch,
+                           Warnings);
 
-        if (clock_modeling == DEDICATED_NETWORK) {
-            ClockRRGraphBuilder::create_and_append_clock_rr_graph(segment_inf,
-                                                                  det_routing_arch->R_minW_nmos,
-                                                                  det_routing_arch->R_minW_pmos,
-                                                                  det_routing_arch->wire_to_rr_ipin_switch,
-                                                                  base_cost_type);
+          if (clock_modeling == DEDICATED_NETWORK) {
+              ClockRRGraphBuilder::create_and_append_clock_rr_graph(segment_inf,
+                                                                    det_routing_arch->R_minW_nmos,
+                                                                    det_routing_arch->R_minW_pmos,
+                                                                    det_routing_arch->wire_to_rr_ipin_switch,
+                                                                    base_cost_type);
+          }
+        } else {
+          /* We do not support dedicated network for clocks in tileable rr_graph generation */
+           openfpga::build_tileable_unidir_rr_graph(block_types,
+                                                    grid,
+                                                    nodes_per_chan,
+                                                    det_routing_arch->switch_block_type,
+                                                    det_routing_arch->Fs,
+                                                    det_routing_arch->switch_block_subtype,
+                                                    det_routing_arch->subFs,
+                                                    segment_inf,
+                                                    det_routing_arch->wire_to_arch_ipin_switch,
+                                                    det_routing_arch->delayless_switch,
+                                                    det_routing_arch->R_minW_nmos,
+                                                    det_routing_arch->R_minW_pmos,
+                                                    base_cost_type,
+                                                    directs, num_directs,
+                                                    &det_routing_arch->wire_to_rr_ipin_switch,
+                                                    false, /* Do not allow passing tracks to be wired to the same routing channels */
+                                                    Warnings);
         }
 
         /* Xifan Tang - Create rr_graph object: load rr_nodes to the object */
diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp
index d9f98d895..f103fb545 100644
--- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp
+++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp
@@ -266,6 +266,9 @@ void build_tileable_unidir_rr_graph(const std::vector<t_physical_tile_type>& typ
   /* Save the channel widths for the newly constructed graph */
   device_ctx.chan_width = chan_width;
 
+  /* Save the track ids for tileable routing resource graph */
+  device_ctx.rr_node_track_ids = rr_node_track_ids;
+
   /************************************************************************
    * Allocate external data structures
    *  a. cost_index
diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp
index cca9e001c..b37265dfb 100755
--- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp
+++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp
@@ -1316,4 +1316,94 @@ t_pin2track_map build_gsb_opin_to_track_map(const RRGraph& rr_graph,
   return opin2track_map;
 }
 
+/************************************************************************
+ * Add all direct clb-pin-to-clb-pin edges to given opin  
+ ***********************************************************************/
+void build_direct_connections_for_one_gsb(RRGraph& rr_graph,
+                                          const DeviceGrid& grids,
+                                          const vtr::Point<size_t>& from_grid_coordinate,
+                                          const RRSwitchId& delayless_switch, 
+                                          const std::vector<t_direct_inf>& directs, 
+                                          const std::vector<t_clb_to_clb_directs>& clb_to_clb_directs) {
+  VTR_ASSERT(directs.size() == clb_to_clb_directs.size());
+
+  const t_grid_tile& from_grid = grids[from_grid_coordinate.x()][from_grid_coordinate.y()];
+  t_physical_tile_type_ptr grid_type = from_grid.type;
+
+  /* Iterate through all direct connections */
+  for (size_t i = 0; i < directs.size(); ++i) {
+    /* Bypass unmatched direct clb-to-clb connections */
+    if (grid_type != clb_to_clb_directs[i].from_clb_type) {
+      continue;
+    }
+
+    /* This opin is specified to connect directly to an ipin, 
+     * now compute which ipin to connect to 
+     */
+    vtr::Point<size_t> to_grid_coordinate(from_grid_coordinate.x() + directs[i].x_offset, 
+                                          from_grid_coordinate.y() + directs[i].y_offset);
+
+    /* Bypass unmatched direct clb-to-clb connections */
+    t_physical_tile_type_ptr to_grid_type = grids[to_grid_coordinate.x()][to_grid_coordinate.y()].type;
+    /* Check if to_grid if the same grid */
+    if (to_grid_type != clb_to_clb_directs[i].to_clb_type) {
+      continue;
+    }
+
+    bool swap;
+    int max_index, min_index;
+    /* Compute index of opin with regards to given pins */ 
+    if ( clb_to_clb_directs[i].from_clb_pin_start_index 
+        > clb_to_clb_directs[i].from_clb_pin_end_index) {
+      swap = true;
+      max_index = clb_to_clb_directs[i].from_clb_pin_start_index;
+      min_index = clb_to_clb_directs[i].from_clb_pin_end_index;
+    } else {
+      swap = false;
+      min_index = clb_to_clb_directs[i].from_clb_pin_start_index;
+      max_index = clb_to_clb_directs[i].from_clb_pin_end_index;
+    }
+
+    /* get every opin in the range */
+    for (int opin = min_index; opin <= max_index; ++opin) {
+      int offset = opin - min_index;
+
+      if (  (to_grid_coordinate.x() < grids.width() - 1) 
+         && (to_grid_coordinate.y() < grids.height() - 1) ) { 
+        int ipin = OPEN;
+        if ( clb_to_clb_directs[i].to_clb_pin_start_index 
+          > clb_to_clb_directs[i].to_clb_pin_end_index) {
+          if (true == swap) {
+            ipin = clb_to_clb_directs[i].to_clb_pin_end_index + offset;
+          } else {
+            ipin = clb_to_clb_directs[i].to_clb_pin_start_index - offset;
+          }
+        } else {
+          if(true == swap) {
+            ipin = clb_to_clb_directs[i].to_clb_pin_end_index - offset;
+          } else {
+            ipin = clb_to_clb_directs[i].to_clb_pin_start_index + offset;
+          }
+        }
+
+        /* Get the pin index in the rr_graph */
+        int from_grid_width_ofs = from_grid.width_offset;
+        int from_grid_height_ofs = from_grid.height_offset;
+        int to_grid_width_ofs = grids[to_grid_coordinate.x()][to_grid_coordinate.y()].width_offset;
+        int to_grid_height_ofs = grids[to_grid_coordinate.x()][to_grid_coordinate.y()].height_offset;
+        const RRNodeId& opin_node_id = rr_graph.find_node(from_grid_coordinate.x() - from_grid_width_ofs, 
+                                                          from_grid_coordinate.y() - from_grid_height_ofs, 
+                                                          OPIN, opin);
+        const RRNodeId& ipin_node_id = rr_graph.find_node(to_grid_coordinate.x() - to_grid_width_ofs, 
+                                                          to_grid_coordinate.y() - to_grid_height_ofs, 
+                                                          IPIN, ipin);
+        /* add edges to the opin_node */
+        rr_graph.create_edge(opin_node_id, ipin_node_id,
+                             delayless_switch);
+      }
+    }
+  }
+}
+
+
 } /* end namespace openfpga */

From 5be118d695ed6682e6bf6e5a78a0062511cee7a2 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 6 Mar 2020 16:18:45 -0700
Subject: [PATCH 263/645] tileable rr_graph builder ready to debug

---
 libs/libarchfpga/src/physical_types.h       |  4 ++++
 libs/libarchfpga/src/read_xml_arch_file.cpp | 21 ++++++++++++++++++---
 openfpga/test_vpr_arch/k6_frac_N10_40nm.xml |  4 ++--
 vpr/src/base/SetupVPR.cpp                   |  2 ++
 4 files changed, 26 insertions(+), 5 deletions(-)

diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h
index c72a57378..d1cfae62a 100644
--- a/libs/libarchfpga/src/physical_types.h
+++ b/libs/libarchfpga/src/physical_types.h
@@ -1589,13 +1589,17 @@ struct t_clock_arch_spec {
 /*   Detailed routing architecture */
 struct t_arch {
     char* architecture_id; //Secure hash digest of the architecture file to uniquely identify this architecture
+    
+    bool tileable;
 
     t_chan_width_dist Chans;
     enum e_switch_block_type SBType;
+    enum e_switch_block_type SBSubType;
     std::vector<t_switchblock_inf> switchblocks;
     float R_minW_nmos;
     float R_minW_pmos;
     int Fs;
+    int subFs;
     float grid_logic_tile_area;
     std::vector<t_segment_inf> Segments;
     t_arch_switch_inf* Switches = nullptr;
diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp
index 32381faca..1c2bba875 100644
--- a/libs/libarchfpga/src/read_xml_arch_file.cpp
+++ b/libs/libarchfpga/src/read_xml_arch_file.cpp
@@ -2533,8 +2533,10 @@ static void ProcessModelPorts(pugi::xml_node port_group, t_model* model, std::se
 static void ProcessLayout(pugi::xml_node layout_tag, t_arch* arch, const pugiutil::loc_data& loc_data) {
     VTR_ASSERT(layout_tag.name() == std::string("layout"));
 
-    //Expect no attributes on <layout>
-    expect_only_attributes(layout_tag, {}, loc_data);
+    //Expect only tileable attributes on <layout>
+    //expect_only_attributes(layout_tag, {"tileable"}, loc_data);
+
+    arch->tileable = get_attribute(layout_tag, "tileable", loc_data).as_bool();
 
     //Count the number of <auto_layout> or <fixed_layout> tags
     size_t auto_layout_cnt = 0;
@@ -2882,7 +2884,7 @@ static void ProcessDevice(pugi::xml_node Node, t_arch* arch, t_default_fc_spec&
 
     //<switch_block> tag
     Cur = get_single_child(Node, "switch_block", loc_data);
-    expect_only_attributes(Cur, {"type", "fs"}, loc_data);
+    //expect_only_attributes(Cur, {"type", "fs", "sub_type", "sub_fs"}, loc_data);
     Prop = get_attribute(Cur, "type", loc_data).value();
     if (strcmp(Prop, "wilton") == 0) {
         arch->SBType = WILTON;
@@ -2898,8 +2900,21 @@ static void ProcessDevice(pugi::xml_node Node, t_arch* arch, t_default_fc_spec&
                        "Unknown property %s for switch block type x\n", Prop);
     }
 
+    Prop = get_attribute(Cur, "sub_type", loc_data, BoolToReqOpt(false)).value();
+    if (strcmp(Prop, "wilton") == 0) {
+        arch->SBSubType = WILTON;
+    } else if (strcmp(Prop, "universal") == 0) {
+        arch->SBSubType = UNIVERSAL;
+    } else if (strcmp(Prop, "subset") == 0) {
+        arch->SBSubType = SUBSET;
+    } else {
+        archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur),
+                       "Unknown property %s for switch block subtype x\n", Prop);
+    }
+
     ReqOpt CUSTOM_SWITCHBLOCK_REQD = BoolToReqOpt(!custom_switch_block);
     arch->Fs = get_attribute(Cur, "fs", loc_data, CUSTOM_SWITCHBLOCK_REQD).as_int(3);
+    arch->subFs = get_attribute(Cur, "sub_fs", loc_data,  BoolToReqOpt(false)).as_int(3);
 
     Cur = get_single_child(Node, "default_fc", loc_data, ReqOpt::OPTIONAL);
     if (Cur) {
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml
index 44e2ef289..f5a4b31fa 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml
@@ -76,7 +76,7 @@
   </tiles>
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
-  <layout>
+  <layout tileable="true">
     <auto_layout aspect_ratio="1.0">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
@@ -110,7 +110,7 @@
       <x distr="uniform" peak="1.000000"/>
       <y distr="uniform" peak="1.000000"/>
     </chan_width_distr>
-    <switch_block type="wilton" fs="3"/>
+    <switch_block type="wilton" fs="3" sub_type="subset" sub_fs="3"/>
     <connection_block input_switch_name="ipin_cblock"/>
   </device>
   <switchlist>
diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp
index 4fd21004e..0cf69a9bb 100644
--- a/vpr/src/base/SetupVPR.cpp
+++ b/vpr/src/base/SetupVPR.cpp
@@ -309,9 +309,11 @@ static void SetupSwitches(const t_arch& Arch,
 static void SetupRoutingArch(const t_arch& Arch,
                              t_det_routing_arch* RoutingArch) {
     RoutingArch->switch_block_type = Arch.SBType;
+    RoutingArch->switch_block_subtype = Arch.SBSubType;
     RoutingArch->R_minW_nmos = Arch.R_minW_nmos;
     RoutingArch->R_minW_pmos = Arch.R_minW_pmos;
     RoutingArch->Fs = Arch.Fs;
+    RoutingArch->subFs = Arch.subFs;
     RoutingArch->directionality = BI_DIRECTIONAL;
     if (Arch.Segments.size()) {
         RoutingArch->directionality = Arch.Segments[0].directionality;

From f54f46483bcfe56808992773ac017681d7caccd3 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 6 Mar 2020 17:02:22 -0700
Subject: [PATCH 264/645] start debugging tileable rr_graph generator

---
 vpr/src/base/vpr_api.cpp   | 5 +++++
 vpr/src/route/rr_graph.cpp | 1 +
 2 files changed, 6 insertions(+)

diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp
index f2900d0d2..53ec0e732 100644
--- a/vpr/src/base/vpr_api.cpp
+++ b/vpr/src/base/vpr_api.cpp
@@ -829,6 +829,11 @@ void vpr_create_rr_graph(t_vpr_setup& vpr_setup, const t_arch& arch, int chan_wi
         graph_type = GRAPH_GLOBAL;
     } else {
         graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR);
+        /* Branch on tileable routing */
+        if ( (UNI_DIRECTIONAL == det_routing_arch->directionality)
+          && (true == arch.tileable) ) {
+            graph_type = GRAPH_UNIDIR_TILEABLE;
+        }
     }
 
     int warnings = 0;
diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp
index b21310ad4..f80c450c7 100644
--- a/vpr/src/route/rr_graph.cpp
+++ b/vpr/src/route/rr_graph.cpp
@@ -1504,6 +1504,7 @@ void free_rr_graph() {
 
     /* Xifan Tang - Clear the rr_graph object */
     device_ctx.rr_graph.clear();
+    device_ctx.rr_node_track_ids.clear();
 }
 
 static void build_rr_sinks_sources(const int i,

From c36c3020521c62a557cf838f0f9f608f7cd9b3a9 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 6 Mar 2020 17:16:53 -0700
Subject: [PATCH 265/645] looks like tileable routing is working

---
 .../tileable_rr_graph/tileable_rr_graph_node_builder.cpp  | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp
index 2928ed335..57f98b584 100644
--- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp
+++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp
@@ -376,8 +376,8 @@ void load_one_grid_opin_nodes_basic_info(RRGraph& rr_graph,
  
           /* node bounding box */
           rr_graph.set_node_bounding_box(node, vtr::Rect<short>(grid_coordinate.x() + width,
-                                                                grid_coordinate.x() + width,
                                                                 grid_coordinate.y() + height,
+                                                                grid_coordinate.x() + width,
                                                                 grid_coordinate.y() + height));
           rr_graph.set_node_side(node, side_manager.get_side());  
           rr_graph.set_node_pin_num(node, pin_num);  
@@ -439,8 +439,8 @@ void load_one_grid_ipin_nodes_basic_info(RRGraph& rr_graph,
  
           /* node bounding box */
           rr_graph.set_node_bounding_box(node, vtr::Rect<short>(grid_coordinate.x() + width,
-                                                                grid_coordinate.x() + width,
                                                                 grid_coordinate.y() + height,
+                                                                grid_coordinate.x() + width,
                                                                 grid_coordinate.y() + height));
           rr_graph.set_node_side(node, side_manager.get_side());  
           rr_graph.set_node_pin_num(node, pin_num);  
@@ -491,8 +491,8 @@ void load_one_grid_source_nodes_basic_info(RRGraph& rr_graph,
 
     /* node bounding box */
     rr_graph.set_node_bounding_box(node, vtr::Rect<short>(grid_coordinate.x(),
-                                                          grid_coordinate.x(),
                                                           grid_coordinate.y(),
+                                                          grid_coordinate.x(),
                                                           grid_coordinate.y()));
     rr_graph.set_node_class_num(node, iclass);  
 
@@ -542,8 +542,8 @@ void load_one_grid_sink_nodes_basic_info(RRGraph& rr_graph,
 
     /* node bounding box */
     rr_graph.set_node_bounding_box(node, vtr::Rect<short>(grid_coordinate.x(),
-                                                          grid_coordinate.x(),
                                                           grid_coordinate.y(),
+                                                          grid_coordinate.x(),
                                                           grid_coordinate.y()));
     rr_graph.set_node_class_num(node, iclass);  
 

From 37423729ec9ad92a51fa13ac7aadbe728b7b511e Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 7 Mar 2020 15:44:57 -0700
Subject: [PATCH 266/645] bug fixing for naming the duplicated pins

---
 openfpga/src/base/openfpga_naming.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/openfpga/src/base/openfpga_naming.cpp b/openfpga/src/base/openfpga_naming.cpp
index 9bfad01a2..530db8cc6 100644
--- a/openfpga/src/base/openfpga_naming.cpp
+++ b/openfpga/src/base/openfpga_naming.cpp
@@ -496,7 +496,7 @@ std::string generate_grid_duplicated_port_name(const size_t& width,
   port_name += std::to_string(width);
   port_name += std::string("_height_");
   port_name += std::to_string(height);
-  port_name += std::string("_pin_");
+  port_name += std::string("__pin_");
   port_name += std::to_string(pin_id);
   port_name += std::string("_");
 

From e48c2b116d9007a7de15ec05d01cf59fc3046734 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 7 Mar 2020 15:46:12 -0700
Subject: [PATCH 267/645] bug fixing for duplicated grid pin names

---
 vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp
index 64e54be65..4f1e21d80 100644
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp
@@ -484,7 +484,7 @@ std::string generate_grid_duplicated_port_name(const size_t& height,
   std::string port_name = std::string(side_manager.to_string());
   port_name += std::string("_height_");
   port_name += std::to_string(height);
-  port_name += std::string("_pin_");
+  port_name += std::string("__pin_");
   port_name += std::to_string(pin_id);
   port_name += std::string("_");
 

From ca92c2717f28b9a32629967c6bdee3db01b214d9 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 7 Mar 2020 16:00:32 -0700
Subject: [PATCH 268/645] bug fix for tile directs

---
 openfpga/src/tile_direct/build_tile_direct.cpp | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/openfpga/src/tile_direct/build_tile_direct.cpp b/openfpga/src/tile_direct/build_tile_direct.cpp
index a99370a0b..676fa8291 100644
--- a/openfpga/src/tile_direct/build_tile_direct.cpp
+++ b/openfpga/src/tile_direct/build_tile_direct.cpp
@@ -203,9 +203,9 @@ vtr::Point<size_t> find_inter_direct_destination_coordinate(const DeviceGrid& gr
      *  +------+  
      *  | Grid | ny
      *  +------+
+     *     ^     .
      *     |     .
      *     |     .
-     *     v     .
      *  +------+
      *  | Grid | 1
      *  +------+
@@ -219,14 +219,14 @@ vtr::Point<size_t> find_inter_direct_destination_coordinate(const DeviceGrid& gr
      *  +------+  
      *  | Grid | ny
      *  +------+
-     *     ^     .
      *     |     .
      *     |     .
+     *     v     .
      *  +------+
      *  | Grid | 1
      *  +------+
      */
-    if (NEGATIVE_DIR == arch_direct.y_dir(arch_direct_id)) {
+    if (POSITIVE_DIR == arch_direct.y_dir(arch_direct_id)) {
       std::reverse(second_search_space.begin(), second_search_space.end());
     }
   }
@@ -279,7 +279,7 @@ vtr::Point<size_t> find_inter_direct_destination_coordinate(const DeviceGrid& gr
      *
      *     1      ...     nx
      *  +------+       +------+
-     *  | Grid |------>| Grid |
+     *  | Grid |<------| Grid |
      *  +------+       +------+
      */
     for (size_t ix = 1 ; ix < grids.width() - 1; ++ix) {
@@ -291,10 +291,10 @@ vtr::Point<size_t> find_inter_direct_destination_coordinate(const DeviceGrid& gr
      *
      *     1      ...     nx
      *  +------+       +------+
-     *  | Grid |<------| Grid |
+     *  | Grid |------>| Grid |
      *  +------+       +------+
      */
-    if (NEGATIVE_DIR == arch_direct.x_dir(arch_direct_id)) {
+    if (POSITIVE_DIR == arch_direct.x_dir(arch_direct_id)) {
       std::reverse(second_search_space.begin(), second_search_space.end());
     }
   }
@@ -515,7 +515,7 @@ void build_inter_column_row_tile_direct(TileDirect& tile_direct,
         next_col_src_grid_coords.push_back(vtr::Point<size_t>(ix, iy));
       }
       /* For positive y- direction, we should start from y = 1 */
-      if (POSITIVE_DIR == arch_direct.y_dir(arch_direct_id)) {
+      if (NEGATIVE_DIR == arch_direct.y_dir(arch_direct_id)) {
         std::reverse(next_col_src_grid_coords.begin(), next_col_src_grid_coords.end());
       }
 

From 0fbf3fca412a306297510ec85f26e9cc26381522 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 7 Mar 2020 23:30:55 -0700
Subject: [PATCH 269/645] start developing edge sorting inside RRGSB

---
 vpr/src/tileable_rr_graph/rr_gsb.cpp | 93 +++++++++++++++++++++++++++-
 vpr/src/tileable_rr_graph/rr_gsb.h   | 61 ++++++++++++++++--
 2 files changed, 145 insertions(+), 9 deletions(-)

diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp
index 5b558fffd..1390a9714 100644
--- a/vpr/src/tileable_rr_graph/rr_gsb.cpp
+++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp
@@ -22,8 +22,13 @@ namespace openfpga {
 RRGSB::RRGSB() {
   /* Set a clean start! */
   coordinate_.set(0, 0);
+
+  chan_node_.clear();
   chan_node_direction_.clear();
+  chan_node_in_edges_.clear();
+
   ipin_node_.clear();
+
   opin_node_.clear();
 }
 
@@ -184,10 +189,10 @@ RRNodeId RRGSB::get_opin_node(const e_side& side, const size_t& node_id) const {
   VTR_ASSERT(side_manager.validate());
  
   /* Ensure the side is valid in the context of this switch block */ 
-  VTR_ASSERT( validate_side(side) );
+  VTR_ASSERT(validate_side(side) );
 
   /* Ensure the track is valid in the context of this switch block at a specific side */ 
-  VTR_ASSERT( validate_opin_node_id(side, node_id) );
+  VTR_ASSERT(validate_opin_node_id(side, node_id) );
   
   return opin_node_[side_manager.to_size_t()][node_id]; 
 } 
@@ -731,7 +736,9 @@ void RRGSB::init_num_sides(const size_t& num_sides) {
 }
 
 /* Add a node to the chan_node_ list and also assign its direction in chan_node_direction_ */
-void RRGSB::add_chan_node(const e_side& node_side, RRChan& rr_chan, const std::vector<enum PORTS>& rr_chan_dir) {
+void RRGSB::add_chan_node(const e_side& node_side,
+                          const RRChan& rr_chan,
+                          const std::vector<enum PORTS>& rr_chan_dir) {
   /* Validate: 1. side is valid, the type of node is valid */
   VTR_ASSERT(validate_side(node_side));
 
@@ -757,6 +764,86 @@ void RRGSB::add_opin_node(const RRNodeId& node, const e_side& node_side) {
   opin_node_[size_t(node_side)].push_back(node);
 } 
 
+void RRGSB::sort_chan_node_in_edges(const RRGraph& rr_graph,
+                                    const e_side& chan_side,
+                                    const size_t& track_id) {
+  std::map<size_t, std::map<size_t, RREdgeId>> from_grid_edge_map;
+  std::map<size_t, std::map<size_t, RREdgeId>> from_track_edge_map;
+
+  const RRNodeId& chan_node = chan_node_[size_t(chan_side)].get_node(track_id); 
+  
+  /* Count the edges and ensure every of them has been sorted */
+  size_t edge_counter = 0;
+
+  /* For each incoming edge, find the node side and index in this GSB.
+   * and cache these. Then we will use the data to sort the edge in the 
+   * following sequence:
+   *  0----------------------------------------------------------------> num_in_edges()
+   *  |<--TOP side-->|<--RIGHT side-->|<--BOTTOM side-->|<--LEFT side-->|
+   *  For each side, the edge will be sorted by the node index starting from 0 
+   *  For each side, the edge from grid pins will be the 1st part
+   *  while the edge from routing tracks will be the 2nd part
+   */
+  for (const RREdgeId& edge : rr_graph.node_in_edges(chan_node)) {
+    /* We care the source node of this edge, and it should be an input of the GSB!!! */
+    const RRNodeId& src_node = rr_graph.edge_src_node(edge);
+    e_side side = NUM_SIDES;
+    int index = 0;
+    get_node_side_and_index(rr_graph, src_node, IN_PORT, side, index);
+
+    /* Must have valid side and index */
+    VTR_ASSERT(NUM_SIDES != side);
+    VTR_ASSERT(OPEN != index);
+
+    if (OPIN == rr_graph.node_type(src_node)) {
+      from_grid_edge_map[side][index] = edge;
+    } else {
+      VTR_ASSERT( (CHANX == rr_graph.node_type(src_node))
+               || (CHANY == rr_graph.node_type(src_node)) );
+      from_track_edge_map[side][index] = edge;
+    }
+    
+    edge_counter++;
+  }
+
+  /* Store the sorted edge */
+  for (size_t side = 0; side < get_num_sides(); ++side) {
+    /* Edges from grid outputs are the 1st part */
+    for (size_t opin_id = 0; opin_id < opin_node_[side].size(); ++opin_id) {
+      if ( (0 < from_grid_edge_map.count(side))
+        && (0 < from_grid_edge_map.at(side).count(opin_id)) ) {
+        chan_node_in_edges_[size_t(chan_side)][track_id].push_back(from_grid_edge_map[side][opin_id]);
+      }
+    }
+ 
+    /* Edges from routing tracks are the 2nd part */
+    for (size_t itrack = 0; itrack < chan_node_[side].get_chan_width(); ++itrack) {
+      if ( (0 < from_track_edge_map.count(side))
+        && (0 < from_track_edge_map.at(side).count(itrack)) ) {
+        chan_node_in_edges_[size_t(chan_side)][track_id].push_back(from_track_edge_map[side][itrack]);
+      }
+    }
+  }
+
+  VTR_ASSERT(edge_counter == chan_node_in_edges_[size_t(chan_side)][track_id].size());
+} 
+
+void RRGSB::sort_chan_node_in_edges(const RRGraph& rr_graph) {
+  /* Allocate here, as sort edge is optional, we do not allocate when adding nodes */
+  chan_node_in_edges_.resize(get_num_sides());
+
+  for (size_t side = 0; side < get_num_sides(); ++side) {
+    SideManager side_manager(side);
+    chan_node_in_edges_[side].resize(chan_node_[side].get_chan_width());
+    for (size_t track_id = 0; track_id < chan_node_[side].get_chan_width(); ++track_id) {
+      /* Only sort the output nodes */
+      if (OUT_PORT == chan_node_direction_[side][track_id]) { 
+        sort_chan_node_in_edges(rr_graph, side_manager.get_side(), track_id); 
+      }
+    }
+  }
+}
+
 /************************************************************************
  * Public Mutators: clean-up functions
  ***********************************************************************/
diff --git a/vpr/src/tileable_rr_graph/rr_gsb.h b/vpr/src/tileable_rr_graph/rr_gsb.h
index 8d729139a..76633bcb2 100644
--- a/vpr/src/tileable_rr_graph/rr_gsb.h
+++ b/vpr/src/tileable_rr_graph/rr_gsb.h
@@ -173,12 +173,35 @@ class RRGSB {
     vtr::Point<size_t> get_side_block_coordinate(const e_side& side) const;
     vtr::Point<size_t> get_grid_coordinate() const;
   public: /* Mutators */
-    void set(const RRGSB& src); /* get a copy from a source */
+    /* get a copy from a source */
+    void set(const RRGSB& src);
     void set_coordinate(const size_t& x, const size_t& y);
-    void init_num_sides(const size_t& num_sides); /* Allocate the vectors with the given number of sides */
-    void add_chan_node(const e_side& node_side, RRChan& rr_chan, const std::vector<enum PORTS>& rr_chan_dir); /* Add a node to the chan_rr_node_ list and also assign its direction in chan_rr_node_direction_ */
-    void add_ipin_node(const RRNodeId& node, const e_side& node_side); /* Add a node to the chan_rr_node_ list and also assign its direction in chan_rr_node_direction_ */
-    void add_opin_node(const RRNodeId& node, const e_side& node_side); /* Add a node to the chan_rr_node_ list and also assign its direction in chan_rr_node_direction_ */
+
+    /* Allocate the vectors with the given number of sides */
+    void init_num_sides(const size_t& num_sides);
+
+    /* Add a node to the chan_rr_node_ list and also
+     * assign its direction in chan_rr_node_direction_
+     */
+    void add_chan_node(const e_side& node_side,
+                       const RRChan& rr_chan,
+                       const std::vector<enum PORTS>& rr_chan_dir);
+
+    /* Add a node to the chan_rr_node_ list and also 
+     * assign its direction in chan_rr_node_direction_
+     */
+    void add_ipin_node(const RRNodeId& node,
+                       const e_side& node_side);
+
+    /* Add a node to the chan_rr_node_ list and also 
+     * assign its direction in chan_rr_node_direction_
+     */
+    void add_opin_node(const RRNodeId& node,
+                       const e_side& node_side);
+
+    /* Sort all the incoming edges for routing channel rr_node */
+    void sort_chan_node_in_edges(const RRGraph& rr_graph);
+
   public: /* Mutators: cleaners */
     void clear();
 
@@ -193,6 +216,13 @@ class RRGSB {
 
     /* Clean chan/opin/ipin nodes at one side */
     void clear_one_side(const e_side& node_side); 
+
+  private: /* Private Mutators: edge sorting */
+    /* Sort all the incoming edges for one channel rr_node */
+    void sort_chan_node_in_edges(const RRGraph& rr_graph,
+                                 const e_side& chan_side,
+                                 const size_t& track_id);
+
   private: /* internal functions */
     bool is_sb_node_mirror(const RRGraph& rr_graph,
                            const RRGSB& cand,
@@ -217,10 +247,29 @@ class RRGSB {
   private: /* Internal Data */
     /* Coordinator */
     vtr::Point<size_t> coordinate_;
-    /* Routing channel data */
+
+    /* Routing channel data
+     * Each GSB may have four sides of routing track nodes
+     */
+    /* Node id in rr_graph denoting each routing track */
     std::vector<RRChan>  chan_node_;
+
+    /* Direction of a port when the channel node appear in the GSB module */
     std::vector<std::vector<PORTS>>  chan_node_direction_; 
 
+    /* Sequence of edge ids for each routing channel node,
+     * this is sorted by the location of edge source nodes in the context of GSB 
+     * The edge sorting is critical to uniquify the routing modules in OpenFPGA
+     * This is due to that VPR allocate and sort edges randomly when building the rr_graph
+     * As a result, previous nodes of a chan node may be the same in different GSBs 
+     * but their sequence is not. This will cause graph comparison to fail when uniquifying 
+     * the routing modules. Therefore, edge sorting can be done inside the GSB 
+     *
+     * Storage organization:
+     *   [chan_side][chan_node][edge_id_in_gsb_context]
+     */ 
+    std::vector<std::vector<std::vector<RREdgeId>>> chan_node_in_edges_;
+
     /* Logic Block Inputs data */
     std::vector<std::vector<RRNodeId>>  ipin_node_;
 

From b219b096ee89ff0decf3913bc8c53512f787df07 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 8 Mar 2020 13:54:49 -0600
Subject: [PATCH 270/645] hotfix on removing dangling inputs from GSB, which
 are CLB direct output

---
 .../k6_N10_sram_chain_HC_template.xml         |  5 +++++
 ...k6_N10_sram_chain_HC_tileable_template.xml |  4 ++++
 .../fpga_x2p/base/fpga_x2p_unique_routing.c   |  8 +++++++
 .../verilog/verilog_module_writer.cpp         | 22 ++++++++++++++-----
 4 files changed, 34 insertions(+), 5 deletions(-)

diff --git a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml
index 9af75ba69..cf2b87542 100644
--- a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml
+++ b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml
@@ -499,6 +499,11 @@
       <cb type="pattern">1 1 1 1</cb>
     </segment>
   </segmentlist>
+
+  <directlist>
+    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
+  </directlist>
+
   <!--switch_segment_patterns>
     <pattern type="unbuf_sb" seg_length="1" seg_type="unidir" pattern_length="2">
       <unbuf_mux name="1"/>
diff --git a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml
index 4cea2b20c..912c7701a 100644
--- a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml
+++ b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml
@@ -499,6 +499,10 @@
       <cb type="pattern">1 1 1 1</cb>
     </segment>
   </segmentlist>
+
+  <directlist>
+    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
+  </directlist>
   <!--switch_segment_patterns>
     <pattern type="unbuf_sb" seg_length="1" seg_type="unidir" pattern_length="2">
       <unbuf_mux name="1"/>
diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c
index e8ac5a4e4..c2f520d4d 100644
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c
@@ -1032,10 +1032,18 @@ RRGSB build_rr_gsb(DeviceCoordinator& device_range,
     /* Fill opin_rr_nodes */
     /* Copy from temp_opin_rr_node to opin_rr_node */
     for (int inode = 0; inode < temp_num_opin_rr_nodes[0]; ++inode) {
+      /* Skip Fc = 0  pins, they should NOT appear in the GSB connection */
+      if (0. == grid[temp_opin_rr_node[0][inode]->xlow][temp_opin_rr_node[0][inode]->ylow].type->Fc[temp_opin_rr_node[0][inode]->ptc_num]) {
+        continue;
+      }
       /* Grid[x+1][y+1] Bottom side outputs pins */
       rr_gsb.add_opin_node(temp_opin_rr_node[0][inode], side_manager.get_side(), opin_grid_side[0]);
     }
     for (int inode = 0; inode < temp_num_opin_rr_nodes[1]; ++inode) {
+      /* Skip Fc = 0  pins, they should NOT appear in the GSB connection */
+      if (0. == grid[temp_opin_rr_node[1][inode]->xlow][temp_opin_rr_node[1][inode]->ylow].type->Fc[temp_opin_rr_node[1][inode]->ptc_num]) {
+        continue;
+      }
       /* Grid[x+1][y] TOP side outputs pins */
       rr_gsb.add_opin_node(temp_opin_rr_node[1][inode], side_manager.get_side(), opin_grid_side[1]);
     }
diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp
index 88ed3b2fc..a5cf3b59f 100644
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp
@@ -20,9 +20,21 @@
  *******************************************************************/
 static 
 std::string generate_verilog_undriven_local_wire_name(const ModuleManager& module_manager, 
-                                                      const ModuleId& module, 
-                                                      const ModulePortId& module_port_id) {
-  return module_manager.module_port(module, module_port_id).get_name();
+                                                      const ModuleId& parent, 
+                                                      const ModuleId& child, 
+                                                      const size_t& instance_id, 
+                                                      const ModulePortId& child_port_id) {
+  std::string wire_name;
+  if (!module_manager.instance_name(parent, child, instance_id).empty()) {
+    wire_name = module_manager.instance_name(parent, child, instance_id);
+  } else {
+    wire_name = module_manager.module_name(parent) + std::string("_") + std::to_string(instance_id); 
+    wire_name += std::string("_");
+  }
+  
+  wire_name += module_manager.module_port(child, child_port_id).get_name();
+  
+  return wire_name;
 }
 
 /********************************************************************
@@ -164,7 +176,7 @@ std::map<std::string, std::vector<BasicPort>> find_verilog_module_local_wires(co
         }
         /* Reach here, we need a local wire, we will create a port only for the undriven pins of the port! */
         BasicPort instance_port;
-        instance_port.set_name(generate_verilog_undriven_local_wire_name(module_manager, child, child_port_id));
+        instance_port.set_name(generate_verilog_undriven_local_wire_name(module_manager, module_id, child, instance, child_port_id));
         /* We give the same port name as child module, this case happens to global ports */
         instance_port.set_width(*std::min_element(undriven_pins.begin(), undriven_pins.end()),
                                 *std::max_element(undriven_pins.begin(), undriven_pins.end())); 
@@ -401,7 +413,7 @@ void write_verilog_instance_to_file(std::fstream& fp,
         BasicPort instance_port;
         if (ModuleNetId::INVALID() == net) {
           /* We give the same port name as child module, this case happens to global ports */
-          instance_port.set_name(generate_verilog_undriven_local_wire_name(module_manager, child_module, child_port_id));
+          instance_port.set_name(generate_verilog_undriven_local_wire_name(module_manager, parent_module, child_module, instance_id, child_port_id));
           instance_port.set_width(child_pin, child_pin); 
         } else {
           /* Find the name for this child port */

From 0c7aa2581dda2c3bbe9729f194a6d2ad3eb205b9 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 8 Mar 2020 14:58:56 -0600
Subject: [PATCH 271/645] update vpr8 version with hotfix on undriven pins in
 GSB

---
 openfpga/src/annotation/annotate_rr_graph.cpp | 15 ++++++++++++
 openfpga/src/fabric/build_grid_modules.cpp    |  4 ++--
 .../fpga_verilog/verilog_module_writer.cpp    | 24 +++++++++++++++----
 3 files changed, 36 insertions(+), 7 deletions(-)

diff --git a/openfpga/src/annotation/annotate_rr_graph.cpp b/openfpga/src/annotation/annotate_rr_graph.cpp
index d0097ced6..880edc74d 100644
--- a/openfpga/src/annotation/annotate_rr_graph.cpp
+++ b/openfpga/src/annotation/annotate_rr_graph.cpp
@@ -257,10 +257,25 @@ RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx,
     /* Fill opin_rr_nodes */
     /* Copy from temp_opin_rr_node to opin_rr_node */
     for (const RRNodeId& inode : temp_opin_rr_nodes[0]) {
+      /* Skip those has no configurable outgoing, they should NOT appear in the GSB connection
+       * This is for those grid output pins used by direct connections
+       */
+      if (0 == std::distance(vpr_device_ctx.rr_graph.node_configurable_out_edges(inode).begin(),
+                             vpr_device_ctx.rr_graph.node_configurable_out_edges(inode).end())) {
+        continue;
+      }
       /* Grid[x+1][y+1] Bottom side outputs pins */
       rr_gsb.add_opin_node(inode, side_manager.get_side());
     }
     for (const RRNodeId& inode : temp_opin_rr_nodes[1]) {
+      /* Skip those has no configurable outgoing, they should NOT appear in the GSB connection
+       * This is for those grid output pins used by direct connections
+       */
+      if (0 == std::distance(vpr_device_ctx.rr_graph.node_configurable_out_edges(inode).begin(),
+                             vpr_device_ctx.rr_graph.node_configurable_out_edges(inode).end())) {
+        continue;
+      }
+
       /* Grid[x+1][y] TOP side outputs pins */
       rr_gsb.add_opin_node(inode, side_manager.get_side());
     }
diff --git a/openfpga/src/fabric/build_grid_modules.cpp b/openfpga/src/fabric/build_grid_modules.cpp
index 2ee5527e7..1562b2f3c 100644
--- a/openfpga/src/fabric/build_grid_modules.cpp
+++ b/openfpga/src/fabric/build_grid_modules.cpp
@@ -263,7 +263,7 @@ void build_primitive_block_module(ModuleManager& module_manager,
   /* Add all the nets to connect configuration ports from memory module to primitive modules
    * This is a one-shot addition that covers all the memory modules in this primitive module!
    */
-  if (false == memory_modules.empty()) {
+  if (0 < module_manager.configurable_children(primitive_module).size()) {
     add_module_nets_memory_config_bus(module_manager, primitive_module, 
                                       sram_orgz_type, circuit_lib.design_tech_type(sram_model));
   }
@@ -878,7 +878,7 @@ void rec_build_logical_tile_modules(ModuleManager& module_manager,
   /* Add module nets to connect memory cells inside
    * This is a one-shot addition that covers all the memory modules in this pb module!
    */
-  if (false == memory_modules.empty()) {
+  if (0 < module_manager.configurable_children(pb_module).size()) {
     add_module_nets_memory_config_bus(module_manager, pb_module, 
                                       sram_orgz_type, circuit_lib.design_tech_type(sram_model));
   }
diff --git a/openfpga/src/fpga_verilog/verilog_module_writer.cpp b/openfpga/src/fpga_verilog/verilog_module_writer.cpp
index 59f863701..34c2c4be7 100644
--- a/openfpga/src/fpga_verilog/verilog_module_writer.cpp
+++ b/openfpga/src/fpga_verilog/verilog_module_writer.cpp
@@ -32,11 +32,25 @@ namespace openfpga {
  *******************************************************************/
 static 
 std::string generate_verilog_undriven_local_wire_name(const ModuleManager& module_manager, 
-                                                      const ModuleId& module, 
-                                                      const ModulePortId& module_port_id) {
-  return module_manager.module_port(module, module_port_id).get_name();
+                                                      const ModuleId& parent, 
+                                                      const ModuleId& child, 
+                                                      const size_t& instance_id, 
+                                                      const ModulePortId& child_port_id) {
+  std::string wire_name;
+  if (!module_manager.instance_name(parent, child, instance_id).empty()) {
+    wire_name = module_manager.instance_name(parent, child, instance_id);
+  } else {
+    wire_name = module_manager.module_name(parent) + std::string("_") + std::to_string(instance_id); 
+    wire_name += std::string("_");
+  }
+  
+  wire_name += std::string("_undriven_");
+  wire_name += module_manager.module_port(child, child_port_id).get_name();
+  
+  return wire_name;
 }
 
+
 /********************************************************************
  * Name a net for a local wire for a verilog module 
  * 1. If this is a local wire, name it after the <src_module_name>_<instance_id>_<src_port_name>
@@ -176,7 +190,7 @@ std::map<std::string, std::vector<BasicPort>> find_verilog_module_local_wires(co
         }
         /* Reach here, we need a local wire, we will create a port only for the undriven pins of the port! */
         BasicPort instance_port;
-        instance_port.set_name(generate_verilog_undriven_local_wire_name(module_manager, child, child_port_id));
+        instance_port.set_name(generate_verilog_undriven_local_wire_name(module_manager, module_id, child, instance, child_port_id));
         /* We give the same port name as child module, this case happens to global ports */
         instance_port.set_width(*std::min_element(undriven_pins.begin(), undriven_pins.end()),
                                 *std::max_element(undriven_pins.begin(), undriven_pins.end())); 
@@ -413,7 +427,7 @@ void write_verilog_instance_to_file(std::fstream& fp,
         BasicPort instance_port;
         if (ModuleNetId::INVALID() == net) {
           /* We give the same port name as child module, this case happens to global ports */
-          instance_port.set_name(generate_verilog_undriven_local_wire_name(module_manager, child_module, child_port_id));
+          instance_port.set_name(generate_verilog_undriven_local_wire_name(module_manager, parent_module, child_module, instance_id, child_port_id));
           instance_port.set_width(child_pin, child_pin); 
         } else {
           /* Find the name for this child port */

From f9499afe04943720c5444dc902691846568f1d44 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 8 Mar 2020 15:00:01 -0600
Subject: [PATCH 272/645] remove unused variable

---
 openfpga/src/fabric/build_grid_modules.cpp | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/openfpga/src/fabric/build_grid_modules.cpp b/openfpga/src/fabric/build_grid_modules.cpp
index 1562b2f3c..a59afa242 100644
--- a/openfpga/src/fabric/build_grid_modules.cpp
+++ b/openfpga/src/fabric/build_grid_modules.cpp
@@ -238,12 +238,6 @@ void build_primitive_block_module(ModuleManager& module_manager,
   std::string memory_module_name = generate_memory_module_name(circuit_lib, primitive_model, sram_model, std::string(MEMORY_MODULE_POSTFIX));
   ModuleId memory_module = module_manager.find_module(memory_module_name);
 
-  /* Vectors to record all the memory modules have been added
-   * They are used to add module nets of configuration bus
-   */
-  std::vector<ModuleId> memory_modules;
-  std::vector<size_t> memory_instances;
-
   /* If there is no memory module required, we can skip the assocated net addition */
   if (ModuleId::INVALID() != memory_module) {
     size_t memory_instance_id = module_manager.num_instance(primitive_module, memory_module); 

From 7a7f8374b3e71b856bc0d7d5e9b49f1a57fe9341 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 8 Mar 2020 15:24:34 -0600
Subject: [PATCH 273/645] start deploying edge sorting in uniquifying SB
 modules

---
 vpr/src/tileable_rr_graph/rr_gsb.cpp | 42 ++++++++++++++++++++++------
 vpr/src/tileable_rr_graph/rr_gsb.h   |  5 ++++
 2 files changed, 38 insertions(+), 9 deletions(-)

diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp
index 1390a9714..009da112a 100644
--- a/vpr/src/tileable_rr_graph/rr_gsb.cpp
+++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp
@@ -141,6 +141,36 @@ RRNodeId RRGSB::get_chan_node(const e_side& side, const size_t& track_id) const
   return chan_node_[side_manager.to_size_t()].get_node(track_id); 
 } 
 
+std::vector<RREdgeId> RRGSB::get_chan_node_in_edges(const RRGraph& rr_graph, 
+                                                    const e_side& side,
+                                                    const size_t& track_id) const {
+  SideManager side_manager(side);
+  VTR_ASSERT(side_manager.validate());
+ 
+  /* Ensure the side is valid in the context of this switch block */ 
+  VTR_ASSERT( validate_side(side) );
+
+  /* Ensure the track is valid in the context of this switch block at a specific side */ 
+  VTR_ASSERT( validate_track_id(side, track_id) );
+
+  /* The chan node must be an output port for the GSB, we allow users to access input edges*/
+  VTR_ASSERT(OUT_PORT == get_chan_node_direction(side, track_id));
+
+  /* if sorted, we give sorted edges
+   * if not sorted, we give the empty vector
+   */
+  if (0 == chan_node_in_edges_.size()) {
+    std::vector<RREdgeId> unsorted_edges;
+    for (const RREdgeId& edge : rr_graph.node_in_edges(get_chan_node(side, track_id))) {
+      unsorted_edges.push_back(edge);
+    }
+
+    return unsorted_edges;
+  } 
+
+  return chan_node_in_edges_[side_manager.to_size_t()][track_id];
+}
+
 /* get the segment id of a channel rr_node */
 RRSegmentId RRGSB::get_chan_node_segment(const e_side& side, const size_t& track_id) const {
   SideManager side_manager(side);
@@ -929,15 +959,9 @@ bool RRGSB::is_sb_node_mirror(const RRGraph& rr_graph,
     return false;
   }
 
-  std::vector<RREdgeId> node_in_edges;
-  for (const RREdgeId& edge : rr_graph.node_in_edges(node)) {
-    node_in_edges.push_back(edge);
-  }
-
-  std::vector<RREdgeId> cand_node_in_edges;
-  for (const RREdgeId& edge : rr_graph.node_in_edges(cand_node)) {
-    cand_node_in_edges.push_back(edge);
-  }
+  /* Use unsorted/sorted edges */
+  std::vector<RREdgeId> node_in_edges = get_chan_node_in_edges(rr_graph, node_side, track_id);
+  std::vector<RREdgeId> cand_node_in_edges = cand. get_chan_node_in_edges(rr_graph, node_side, track_id);
   VTR_ASSERT(node_in_edges.size() == cand_node_in_edges.size());
 
   for (size_t iedge = 0; iedge < node_in_edges.size(); ++iedge) {
diff --git a/vpr/src/tileable_rr_graph/rr_gsb.h b/vpr/src/tileable_rr_graph/rr_gsb.h
index 76633bcb2..816f4b249 100644
--- a/vpr/src/tileable_rr_graph/rr_gsb.h
+++ b/vpr/src/tileable_rr_graph/rr_gsb.h
@@ -83,6 +83,11 @@ class RRGSB {
     /* get a rr_node at a given side and track_id */
     RRNodeId get_chan_node(const e_side& side, const size_t& track_id) const; 
 
+    /* get all the sorted incoming edges for a rr_node at a given side and track_id */
+    std::vector<RREdgeId> get_chan_node_in_edges(const RRGraph& rr_graph, 
+                                                 const e_side& side,
+                                                 const size_t& track_id) const; 
+
     /* get the segment id of a channel rr_node */
     RRSegmentId get_chan_node_segment(const e_side& side, const size_t& track_id) const; 
 

From 5558932762dab2e7d1b0c9fa09165268eae06c58 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 8 Mar 2020 15:31:41 -0600
Subject: [PATCH 274/645] use sorted edges in building routing modules

---
 .../src/fabric/build_routing_module_utils.cpp | 19 +++++++++++++++++++
 .../src/fabric/build_routing_module_utils.h   |  5 +++++
 openfpga/src/fabric/build_routing_modules.cpp |  2 +-
 3 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/openfpga/src/fabric/build_routing_module_utils.cpp b/openfpga/src/fabric/build_routing_module_utils.cpp
index c717604c5..00094079b 100644
--- a/openfpga/src/fabric/build_routing_module_utils.cpp
+++ b/openfpga/src/fabric/build_routing_module_utils.cpp
@@ -17,6 +17,25 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
+/************************************************************************
+ * Find the configurable driver nodes for a node in the rr_graph
+ ***********************************************************************/
+std::vector<RRNodeId> get_rr_gsb_chan_node_configurable_driver_nodes(const RRGraph& rr_graph,
+                                                                     const RRGSB& rr_gsb,
+                                                                     const e_side& chan_side,
+                                                                     const size_t& track_id) {
+  std::vector<RRNodeId> driver_nodes;
+  for (const RREdgeId& edge : rr_gsb.get_chan_node_in_edges(rr_graph, chan_side, track_id)) {
+    /* Bypass non-configurable edges */
+    if (false == rr_graph.edge_is_configurable(edge)) {
+      continue;
+    } 
+    driver_nodes.push_back(rr_graph.edge_src_node(edge));
+  }
+
+  return driver_nodes;
+}
+
 /*********************************************************************
  * Generate a port for a routing track of a swtich block
  ********************************************************************/
diff --git a/openfpga/src/fabric/build_routing_module_utils.h b/openfpga/src/fabric/build_routing_module_utils.h
index 257a788cb..611118e3e 100644
--- a/openfpga/src/fabric/build_routing_module_utils.h
+++ b/openfpga/src/fabric/build_routing_module_utils.h
@@ -17,6 +17,11 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
+std::vector<RRNodeId> get_rr_gsb_chan_node_configurable_driver_nodes(const RRGraph& rr_graph,
+                                                                     const RRGSB& rr_gsb,
+                                                                     const e_side& chan_side,
+                                                                     const size_t& track_id);
+
 ModulePortId find_switch_block_module_chan_port(const ModuleManager& module_manager, 
                                                 const ModuleId& sb_module,
                                                 const RRGraph& rr_graph,
diff --git a/openfpga/src/fabric/build_routing_modules.cpp b/openfpga/src/fabric/build_routing_modules.cpp
index a08a0680f..9abaa874d 100644
--- a/openfpga/src/fabric/build_routing_modules.cpp
+++ b/openfpga/src/fabric/build_routing_modules.cpp
@@ -227,7 +227,7 @@ void build_switch_block_interc_modules(ModuleManager& module_manager,
 
   /* Determine if the interc lies inside a channel wire, that is interc between segments */
   if (false == rr_gsb.is_sb_node_passing_wire(rr_graph, chan_side, chan_node_id)) {
-    driver_rr_nodes = get_rr_graph_configurable_driver_nodes(rr_graph, cur_rr_node);
+    driver_rr_nodes = get_rr_gsb_chan_node_configurable_driver_nodes(rr_graph, rr_gsb, chan_side, chan_node_id);
     /* Special: if there are zero-driver nodes. We skip here */
     if (0 == driver_rr_nodes.size()) {
       return; 

From b80e26e711e80a4cee0dbfffb0a90ec89c6163ee Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 8 Mar 2020 15:36:47 -0600
Subject: [PATCH 275/645] update bitstream generator to use sorted edges

---
 .../src/fabric/build_routing_module_utils.cpp | 19 -------------------
 .../src/fabric/build_routing_module_utils.h   |  5 -----
 openfpga/src/fabric/build_routing_modules.cpp |  1 +
 .../build_routing_bitstream.cpp               |  2 +-
 openfpga/src/utils/rr_gsb_utils.cpp           | 19 +++++++++++++++++++
 openfpga/src/utils/rr_gsb_utils.h             |  5 +++++
 6 files changed, 26 insertions(+), 25 deletions(-)

diff --git a/openfpga/src/fabric/build_routing_module_utils.cpp b/openfpga/src/fabric/build_routing_module_utils.cpp
index 00094079b..c717604c5 100644
--- a/openfpga/src/fabric/build_routing_module_utils.cpp
+++ b/openfpga/src/fabric/build_routing_module_utils.cpp
@@ -17,25 +17,6 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-/************************************************************************
- * Find the configurable driver nodes for a node in the rr_graph
- ***********************************************************************/
-std::vector<RRNodeId> get_rr_gsb_chan_node_configurable_driver_nodes(const RRGraph& rr_graph,
-                                                                     const RRGSB& rr_gsb,
-                                                                     const e_side& chan_side,
-                                                                     const size_t& track_id) {
-  std::vector<RRNodeId> driver_nodes;
-  for (const RREdgeId& edge : rr_gsb.get_chan_node_in_edges(rr_graph, chan_side, track_id)) {
-    /* Bypass non-configurable edges */
-    if (false == rr_graph.edge_is_configurable(edge)) {
-      continue;
-    } 
-    driver_nodes.push_back(rr_graph.edge_src_node(edge));
-  }
-
-  return driver_nodes;
-}
-
 /*********************************************************************
  * Generate a port for a routing track of a swtich block
  ********************************************************************/
diff --git a/openfpga/src/fabric/build_routing_module_utils.h b/openfpga/src/fabric/build_routing_module_utils.h
index 611118e3e..257a788cb 100644
--- a/openfpga/src/fabric/build_routing_module_utils.h
+++ b/openfpga/src/fabric/build_routing_module_utils.h
@@ -17,11 +17,6 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-std::vector<RRNodeId> get_rr_gsb_chan_node_configurable_driver_nodes(const RRGraph& rr_graph,
-                                                                     const RRGSB& rr_gsb,
-                                                                     const e_side& chan_side,
-                                                                     const size_t& track_id);
-
 ModulePortId find_switch_block_module_chan_port(const ModuleManager& module_manager, 
                                                 const ModuleId& sb_module,
                                                 const RRGraph& rr_graph,
diff --git a/openfpga/src/fabric/build_routing_modules.cpp b/openfpga/src/fabric/build_routing_modules.cpp
index 9abaa874d..da216ec75 100644
--- a/openfpga/src/fabric/build_routing_modules.cpp
+++ b/openfpga/src/fabric/build_routing_modules.cpp
@@ -19,6 +19,7 @@
 #include "openfpga_reserved_words.h"
 #include "openfpga_naming.h"
 
+#include "rr_gsb_utils.h"
 #include "openfpga_rr_graph_utils.h"
 #include "module_manager_utils.h"
 #include "build_module_graph_utils.h"
diff --git a/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp b/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp
index 5b4fadb09..faef05174 100644
--- a/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp
+++ b/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp
@@ -114,7 +114,7 @@ void build_switch_block_interc_bitstream(BitstreamManager& bitstream_manager,
 
   /* Determine if the interc lies inside a channel wire, that is interc between segments */
   if (false == rr_gsb.is_sb_node_passing_wire(rr_graph, chan_side, chan_node_id)) {
-    driver_rr_nodes = get_rr_graph_configurable_driver_nodes(rr_graph, cur_rr_node);
+    driver_rr_nodes = get_rr_gsb_chan_node_configurable_driver_nodes(rr_graph, rr_gsb, chan_side, chan_node_id);
     /* Special: if there are zero-driver nodes. We skip here */
     if (0 == driver_rr_nodes.size()) {
       return; 
diff --git a/openfpga/src/utils/rr_gsb_utils.cpp b/openfpga/src/utils/rr_gsb_utils.cpp
index 3f332e6db..90b63bff4 100644
--- a/openfpga/src/utils/rr_gsb_utils.cpp
+++ b/openfpga/src/utils/rr_gsb_utils.cpp
@@ -36,4 +36,23 @@ bool connection_block_contain_only_routing_tracks(const RRGSB& rr_gsb,
   return routing_track_only;
 }
 
+/************************************************************************
+ * Find the configurable driver nodes for a node in the rr_graph
+ ***********************************************************************/
+std::vector<RRNodeId> get_rr_gsb_chan_node_configurable_driver_nodes(const RRGraph& rr_graph,
+                                                                     const RRGSB& rr_gsb,
+                                                                     const e_side& chan_side,
+                                                                     const size_t& track_id) {
+  std::vector<RRNodeId> driver_nodes;
+  for (const RREdgeId& edge : rr_gsb.get_chan_node_in_edges(rr_graph, chan_side, track_id)) {
+    /* Bypass non-configurable edges */
+    if (false == rr_graph.edge_is_configurable(edge)) {
+      continue;
+    } 
+    driver_nodes.push_back(rr_graph.edge_src_node(edge));
+  }
+
+  return driver_nodes;
+}
+
 } /* end namespace openfpga */
diff --git a/openfpga/src/utils/rr_gsb_utils.h b/openfpga/src/utils/rr_gsb_utils.h
index 57e3e23fc..175734db4 100644
--- a/openfpga/src/utils/rr_gsb_utils.h
+++ b/openfpga/src/utils/rr_gsb_utils.h
@@ -18,6 +18,11 @@ namespace openfpga {
 bool connection_block_contain_only_routing_tracks(const RRGSB& rr_gsb,
                                                   const t_rr_type& cb_type);
 
+std::vector<RRNodeId> get_rr_gsb_chan_node_configurable_driver_nodes(const RRGraph& rr_graph,
+                                                                     const RRGSB& rr_gsb,
+                                                                     const e_side& chan_side,
+                                                                     const size_t& track_id);
+
 } /* end namespace openfpga */
 
 #endif

From aff73bdd748a0e2f0caf8c0b03db93227a2a232a Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 8 Mar 2020 15:59:53 -0600
Subject: [PATCH 276/645] deployed edge sorting and make it as an option to
 link_arch command

---
 openfpga/src/annotation/annotate_rr_graph.cpp | 27 ++++++++++++++++---
 openfpga/src/annotation/annotate_rr_graph.h   |  3 +++
 openfpga/src/annotation/device_rr_gsb.cpp     | 20 +++++++++++---
 openfpga/src/annotation/device_rr_gsb.h       | 10 ++++---
 openfpga/src/base/openfpga_link_arch.cpp      |  6 +++++
 openfpga/src/base/openfpga_setup_command.cpp  |  3 +++
 openfpga/test_script/and_k6_frac.openfpga     |  2 +-
 7 files changed, 59 insertions(+), 12 deletions(-)

diff --git a/openfpga/src/annotation/annotate_rr_graph.cpp b/openfpga/src/annotation/annotate_rr_graph.cpp
index 880edc74d..4af681c71 100644
--- a/openfpga/src/annotation/annotate_rr_graph.cpp
+++ b/openfpga/src/annotation/annotate_rr_graph.cpp
@@ -387,12 +387,12 @@ void annotate_device_rr_gsb(const DeviceContext& vpr_device_ctx,
   /* For each switch block, determine the size of array */
   for (size_t ix = 0; ix < gsb_range.x(); ++ix) {
     for (size_t iy = 0; iy < gsb_range.y(); ++iy) {
-      /* Here we give the builder the fringe coordinates so that it can handle the GSBs at the borderside correctly */
+      /* Here we give the builder the fringe coordinates so that it can handle the GSBs at the borderside correctly
+       * sort drive_rr_nodes should be called if required by users
+       */
       const RRGSB& rr_gsb = build_rr_gsb(vpr_device_ctx, 
                                          vtr::Point<size_t>(vpr_device_ctx.grid.width() - 2, vpr_device_ctx.grid.height() - 2), 
                                          vtr::Point<size_t>(ix, iy));
-      /* TODO: sort drive_rr_nodes should be done when building the tileable rr_graph */
-      //sort_rr_gsb_drive_rr_nodes(rr_gsb);
  
       /* Add to device_rr_gsb */
       vtr::Point<size_t> gsb_coordinate = rr_gsb.get_sb_coordinate();
@@ -409,6 +409,27 @@ void annotate_device_rr_gsb(const DeviceContext& vpr_device_ctx,
           gsb_range.x() * gsb_range.y());
 }
 
+/********************************************************************
+ * Sort all the incoming edges for each channel node which are
+ * output ports of the GSB
+ *******************************************************************/
+void sort_device_rr_gsb_chan_node_in_edges(const RRGraph& rr_graph,
+                                           DeviceRRGSB& device_rr_gsb) {
+  vtr::ScopedStartFinishTimer timer("Sort incoming edges for each routing track output node of General Switch Block(GSB)");
+
+  /* Note that the GSB array is smaller than the grids by 1 column and 1 row!!! */
+  vtr::Point<size_t> gsb_range = device_rr_gsb.get_gsb_range();
+
+  /* For each switch block, determine the size of array */
+  for (size_t ix = 0; ix < gsb_range.x(); ++ix) {
+    for (size_t iy = 0; iy < gsb_range.y(); ++iy) {
+      vtr::Point<size_t> gsb_coordinate(ix, iy);
+      RRGSB& rr_gsb = device_rr_gsb.get_mutable_gsb(gsb_coordinate);
+      rr_gsb.sort_chan_node_in_edges(rr_graph);
+    } 
+  }
+}
+
 /********************************************************************
  * Build the link between rr_graph switches to their physical circuit models 
  * The binding is done based on the name of rr_switches defined in the
diff --git a/openfpga/src/annotation/annotate_rr_graph.h b/openfpga/src/annotation/annotate_rr_graph.h
index d4550639f..69346a481 100644
--- a/openfpga/src/annotation/annotate_rr_graph.h
+++ b/openfpga/src/annotation/annotate_rr_graph.h
@@ -19,6 +19,9 @@ void annotate_device_rr_gsb(const DeviceContext& vpr_device_ctx,
                             DeviceRRGSB& device_rr_gsb,
                             const bool& verbose_output);
 
+void sort_device_rr_gsb_chan_node_in_edges(const RRGraph& rr_graph,
+                                           DeviceRRGSB& device_rr_gsb);
+
 void annotate_rr_graph_circuit_models(const DeviceContext& vpr_device_ctx, 
                                       const Arch& openfpga_arch,
                                       VprDeviceAnnotation& vpr_device_annotation,
diff --git a/openfpga/src/annotation/device_rr_gsb.cpp b/openfpga/src/annotation/device_rr_gsb.cpp
index 6fa808823..1fcb16109 100644
--- a/openfpga/src/annotation/device_rr_gsb.cpp
+++ b/openfpga/src/annotation/device_rr_gsb.cpp
@@ -28,13 +28,13 @@ vtr::Point<size_t> DeviceRRGSB::get_gsb_range() const {
 } 
 
 /* Get a rr switch block in the array with a coordinate */
-const RRGSB DeviceRRGSB::get_gsb(const vtr::Point<size_t>& coordinate) const {
+const RRGSB& DeviceRRGSB::get_gsb(const vtr::Point<size_t>& coordinate) const {
   VTR_ASSERT(validate_coordinate(coordinate));
   return rr_gsb_[coordinate.x()][coordinate.y()];
 } 
 
 /* Get a rr switch block in the array with a coordinate */
-const RRGSB DeviceRRGSB::get_gsb(const size_t& x, const size_t& y) const { 
+const RRGSB& DeviceRRGSB::get_gsb(const size_t& x, const size_t& y) const { 
   vtr::Point<size_t> coordinate(x, y);  
   return get_gsb(coordinate);
 }
@@ -87,7 +87,7 @@ size_t DeviceRRGSB::get_num_gsb_unique_module() const {
 } 
 
 /* Get a rr switch block which a unique mirror */ 
-const RRGSB DeviceRRGSB::get_sb_unique_module(const size_t& index) const {
+const RRGSB& DeviceRRGSB::get_sb_unique_module(const size_t& index) const {
   VTR_ASSERT (validate_sb_unique_module_index(index));
   
   return rr_gsb_[sb_unique_module_[index].x()][sb_unique_module_[index].y()];
@@ -130,7 +130,7 @@ const RRGSB& DeviceRRGSB::get_cb_unique_module(const t_rr_type& cb_type, const v
 } 
 
 /* Give a coordinate of a rr switch block, and return its unique mirror */ 
-const RRGSB DeviceRRGSB::get_sb_unique_module(const vtr::Point<size_t>& coordinate) const {
+const RRGSB& DeviceRRGSB::get_sb_unique_module(const vtr::Point<size_t>& coordinate) const {
   VTR_ASSERT(validate_coordinate(coordinate));
   size_t sb_unique_module_id = sb_unique_module_id_[coordinate.x()][coordinate.y()];  
   return get_sb_unique_module(sb_unique_module_id);
@@ -193,6 +193,18 @@ void DeviceRRGSB::add_rr_gsb(const vtr::Point<size_t>& coordinate,
   rr_gsb_[coordinate.x()][coordinate.y()] = rr_gsb; 
 }
 
+/* Get a rr switch block in the array with a coordinate */
+RRGSB& DeviceRRGSB::get_mutable_gsb(const vtr::Point<size_t>& coordinate) {
+  VTR_ASSERT(validate_coordinate(coordinate));
+  return rr_gsb_[coordinate.x()][coordinate.y()];
+} 
+
+/* Get a rr switch block in the array with a coordinate */
+RRGSB& DeviceRRGSB::get_mutable_gsb(const size_t& x, const size_t& y) { 
+  vtr::Point<size_t> coordinate(x, y);  
+  return get_mutable_gsb(coordinate);
+}
+
 /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
 void DeviceRRGSB::build_cb_unique_module(const RRGraph& rr_graph, const t_rr_type& cb_type) {
   /* Make sure a clean start */
diff --git a/openfpga/src/annotation/device_rr_gsb.h b/openfpga/src/annotation/device_rr_gsb.h
index eae0afa1d..4d8aad401 100644
--- a/openfpga/src/annotation/device_rr_gsb.h
+++ b/openfpga/src/annotation/device_rr_gsb.h
@@ -28,12 +28,12 @@ class DeviceRRGSB {
   public: /* Contructors */
   public: /* Accessors */
     vtr::Point<size_t> get_gsb_range() const; /* get the max coordinate of the switch block array */
-    const RRGSB get_gsb(const vtr::Point<size_t>& coordinate) const; /* Get a rr switch block in the array with a coordinate */
-    const RRGSB get_gsb(const size_t& x, const size_t& y) const; /* Get a rr switch block in the array with a coordinate */
+    const RRGSB& get_gsb(const vtr::Point<size_t>& coordinate) const; /* Get a rr switch block in the array with a coordinate */
+    const RRGSB& get_gsb(const size_t& x, const size_t& y) const; /* Get a rr switch block in the array with a coordinate */
     size_t get_num_gsb_unique_module() const; /* get the number of unique mirrors of GSB */
     size_t get_num_sb_unique_module() const; /* get the number of unique mirrors of switch blocks */
-    const RRGSB get_sb_unique_module(const size_t& index) const; /* Get a rr switch block which a unique mirror */ 
-    const RRGSB get_sb_unique_module(const vtr::Point<size_t>& coordinate) const; /* Get a rr switch block which a unique mirror */ 
+    const RRGSB& get_sb_unique_module(const size_t& index) const; /* Get a rr switch block which a unique mirror */ 
+    const RRGSB& get_sb_unique_module(const vtr::Point<size_t>& coordinate) const; /* Get a rr switch block which a unique mirror */ 
     const RRGSB& get_cb_unique_module(const t_rr_type& cb_type, const size_t& index) const; /* Get a rr switch block which a unique mirror */ 
     const RRGSB& get_cb_unique_module(const t_rr_type& cb_type, const vtr::Point<size_t>& coordinate) const;
     size_t get_num_cb_unique_module(const t_rr_type& cb_type) const; /* get the number of unique mirrors of CBs */
@@ -43,6 +43,8 @@ class DeviceRRGSB {
     void reserve_sb_unique_submodule_id(const vtr::Point<size_t>& coordinate); /* Pre-allocate the rr_sb_unique_module_id matrix that the device requires */ 
     void resize_upon_need(const vtr::Point<size_t>& coordinate); /* Resize the rr_switch_block array if needed */ 
     void add_rr_gsb(const vtr::Point<size_t>& coordinate, const RRGSB& rr_gsb); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
+    RRGSB& get_mutable_gsb(const vtr::Point<size_t>& coordinate); /* Get a rr switch block in the array with a coordinate */
+    RRGSB& get_mutable_gsb(const size_t& x, const size_t& y); /* Get a rr switch block in the array with a coordinate */
     void build_unique_module(const RRGraph& rr_graph); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */
     void clear(); /* clean the content */
   private: /* Internal cleaners */
diff --git a/openfpga/src/base/openfpga_link_arch.cpp b/openfpga/src/base/openfpga_link_arch.cpp
index e0e52f878..5c0d6c582 100644
--- a/openfpga/src/base/openfpga_link_arch.cpp
+++ b/openfpga/src/base/openfpga_link_arch.cpp
@@ -65,6 +65,7 @@ void link_arch(OpenfpgaContext& openfpga_ctx,
   vtr::ScopedStartFinishTimer timer("Link OpenFPGA architecture to VPR architecture");
 
   CommandOptionId opt_activity_file = cmd.option("activity_file");
+  CommandOptionId opt_sort_edge = cmd.option("sort_gsb_chan_node_in_edges");
   CommandOptionId opt_verbose = cmd.option("verbose");
 
   /* Annotate pb_type graphs
@@ -111,6 +112,11 @@ void link_arch(OpenfpgaContext& openfpga_ctx,
                          openfpga_ctx.mutable_device_rr_gsb(),
                          cmd_context.option_enable(cmd, opt_verbose));
 
+  if (true == cmd_context.option_enable(cmd, opt_sort_edge)) {
+    sort_device_rr_gsb_chan_node_in_edges(g_vpr_ctx.device().rr_graph,
+                                          openfpga_ctx.mutable_device_rr_gsb());
+  } 
+
   /* Build multiplexer library */
   openfpga_ctx.mutable_mux_lib() = build_device_mux_library(g_vpr_ctx.device(),
                                                             const_cast<const OpenfpgaContext&>(openfpga_ctx)); 
diff --git a/openfpga/src/base/openfpga_setup_command.cpp b/openfpga/src/base/openfpga_setup_command.cpp
index 0d7393c26..0bbc8b2a2 100644
--- a/openfpga/src/base/openfpga_setup_command.cpp
+++ b/openfpga/src/base/openfpga_setup_command.cpp
@@ -78,6 +78,9 @@ ShellCommandId add_openfpga_link_arch_command(openfpga::Shell<OpenfpgaContext>&
   CommandOptionId opt_act_file = shell_cmd.add_option("activity_file", true, "file path to the signal activity");
   shell_cmd.set_option_require_value(opt_act_file, openfpga::OPT_STRING);
 
+  /* Add an option '--sort_gsb_chan_node_in_edges'*/
+  shell_cmd.add_option("sort_gsb_chan_node_in_edges", false, "Sort all the incoming edges for each routing track output node in General Switch Blocks (GSBs)");
+
   /* Add an option '--verbose' */
   shell_cmd.add_option("verbose", false, "Show verbose outputs");
   
diff --git a/openfpga/test_script/and_k6_frac.openfpga b/openfpga/test_script/and_k6_frac.openfpga
index 4133dcea5..872af950d 100644
--- a/openfpga/test_script/and_k6_frac.openfpga
+++ b/openfpga/test_script/and_k6_frac.openfpga
@@ -8,7 +8,7 @@ read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
 #write_openfpga_arch -f ./arch_echo.xml
 
 # Annotate the OpenFPGA architecture to VPR data base
-link_openfpga_arch --activity_file ./test_blif/and.act #--verbose
+link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose
 
 # Check and correct any naming conflicts in the BLIF netlist
 check_netlist_naming_conflict --fix --report ./netlist_renaming.xml

From 3aca7b498cdfb27a06d33b8124224e6686aacd32 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 9 Mar 2020 09:34:21 -0600
Subject: [PATCH 277/645] Show help desk when a command is called inside shell
 without satisfying the dependency

---
 libopenfpga/libopenfpgashell/src/shell.tpp | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/libopenfpga/libopenfpgashell/src/shell.tpp b/libopenfpga/libopenfpgashell/src/shell.tpp
index 72ebe5168..5bd4ec56c 100644
--- a/libopenfpga/libopenfpgashell/src/shell.tpp
+++ b/libopenfpga/libopenfpgashell/src/shell.tpp
@@ -373,6 +373,8 @@ void Shell<T>::execute_command(const char* cmd_line,
     if (false == command_status_[dep_cmd]) {
       VTR_LOG("Command '%s' is required to be executed before command '%s'!\n",
               commands_[dep_cmd].name().c_str(), commands_[cmd_id].name().c_str());
+      /* Echo the command help desk */
+      print_command_options(commands_[cmd_id]);
       return;
     } 
   }

From d61ae5561baec620329e98db2c4b975ba4984d46 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 9 Mar 2020 09:44:19 -0600
Subject: [PATCH 278/645] start cleanup the documentation for openfpga shell

---
 docs/source/z_reference.bib | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/source/z_reference.bib b/docs/source/z_reference.bib
index c0aded955..d087acd7d 100644
--- a/docs/source/z_reference.bib
+++ b/docs/source/z_reference.bib
@@ -83,7 +83,7 @@ month={Oct},}
 }
 
 @INPROCEEDINGS{XTang_FPL_2019,
-author={X. {Tang} and E. {Giacomin} and A. {Alacchi} and B. {Chauviere} and P. {Gaillardon}},
+author={X. Tang and E. Giacomin and A. Alacchi and B. Chauviere and P. Gaillardon},
 booktitle={2019 29th International Conference on Field Programmable Logic and Applications (FPL)},
 title={OpenFPGA: An Opensource Framework Enabling Rapid Prototyping of Customizable FPGAs},
 year={2019},

From f821e60405fae493cb90bd12ab50d1c82039e7ba Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 9 Mar 2020 10:15:16 -0600
Subject: [PATCH 279/645] clean up deadlinks in doc

---
 docs/source/contact.rst                        |   6 +++---
 .../fpga_verilog/figures/verification_step.png | Bin 0 -> 183723 bytes
 docs/source/fpga_verilog/file_organization.rst |   2 +-
 docs/source/fpga_verilog/func_verify.rst       |   4 ++--
 docs/source/tutorials/getting_started.rtf      |  11 -----------
 5 files changed, 6 insertions(+), 17 deletions(-)
 create mode 100644 docs/source/fpga_verilog/figures/verification_step.png
 delete mode 100644 docs/source/tutorials/getting_started.rtf

diff --git a/docs/source/contact.rst b/docs/source/contact.rst
index accebded6..469defe1a 100644
--- a/docs/source/contact.rst
+++ b/docs/source/contact.rst
@@ -1,15 +1,15 @@
 .. _contact:
-   
+
 Contact
 =======
-
+   
 General questions:
 
 Prof. Pierre-Emmanuel Gaillardon 
 
 pierre-emmanuel.gaillardon@utah.edu
 
-Technical Details about FPGA-SPICE/Verilog/Bitstream:
+Technical Details about FPGA-SPICE/Verilog/Bitstream/SDC:
 
 Dr. Xifan Tang
 
diff --git a/docs/source/fpga_verilog/figures/verification_step.png b/docs/source/fpga_verilog/figures/verification_step.png
new file mode 100644
index 0000000000000000000000000000000000000000..7512f10291fa57aba6a2f0c373e52ebdce18411a
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diff --git a/docs/source/fpga_verilog/file_organization.rst b/docs/source/fpga_verilog/file_organization.rst
index 59e794422..0c223a822 100644
--- a/docs/source/fpga_verilog/file_organization.rst
+++ b/docs/source/fpga_verilog/file_organization.rst
@@ -1,5 +1,5 @@
 Hierarchy of Verilog Output Files
-============================
+=================================
 
 All the generated Verilog Netlists are located in the <verilog_dir>/SRC as you specify in the command-line options. Under the <verilog_dir>/SRC, FPGA-Verilog creates the top file name_top.v and some folders: lb (logic blocks), routing and sub_modules. 
 
diff --git a/docs/source/fpga_verilog/func_verify.rst b/docs/source/fpga_verilog/func_verify.rst
index d28ea0ea1..cbb8af96c 100644
--- a/docs/source/fpga_verilog/func_verify.rst
+++ b/docs/source/fpga_verilog/func_verify.rst
@@ -7,6 +7,6 @@ The point of the verification step is to check that the FPGA reproduces the righ
 
 .. _fig_ModelSim:
 
-.. figure:: ./figures/Verification_step.pdf
-   :scale: 100%
+.. figure:: figures/verification_step.png
+   :scale: 50%
    :alt: Functional Verification using ModelSim
diff --git a/docs/source/tutorials/getting_started.rtf b/docs/source/tutorials/getting_started.rtf
deleted file mode 100644
index f094182ef..000000000
--- a/docs/source/tutorials/getting_started.rtf
+++ /dev/null
@@ -1,11 +0,0 @@
-{\rtf1\ansi\ansicpg1252\cocoartf1561\cocoasubrtf400
-{\fonttbl\f0\fswiss\fcharset0 Helvetica;}
-{\colortbl;\red255\green255\blue255;}
-{\*\expandedcolortbl;;}
-\margl1440\margr1440\vieww10800\viewh8400\viewkind0
-\pard\tx566\tx1133\tx1700\tx2267\tx2834\tx3401\tx3968\tx4535\tx5102\tx5669\tx6236\tx6803\pardirnatural\partightenfactor0
-
-\f0\fs24 \cf0 01 Getting Started\
-=================================================\
-\
-**Under Construction**}
\ No newline at end of file

From 73da4a1d6ee98b48fcb5c9dfbcdf6263ee338282 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 9 Mar 2020 10:32:03 -0600
Subject: [PATCH 280/645] rework motivation for FPGA-Verilog and FPGA-Bitstream
 in documentation

---
 docs/source/motivation.rst | 11 ++++-------
 1 file changed, 4 insertions(+), 7 deletions(-)

diff --git a/docs/source/motivation.rst b/docs/source/motivation.rst
index f2f6b34eb..7d068ac52 100644
--- a/docs/source/motivation.rst
+++ b/docs/source/motivation.rst
@@ -20,19 +20,16 @@ The technical details can be found in our ICCD’15 paper :cite:`XTang_ICCD_2015
 FPGA-Verilog
 ------------
 
-On a second note, it is becoming more and more necessary to have fast access to the Verilog code of the structures and architectures researchers want to study. We think that some issues cannot be studies through VPR only and a complete overview is possible through a more extensive workflow. One of the prerequisites for this is the generation of the Verilog which enables Place & Route and Signoff analysis. While VPR allows the researcher to have access to fast results if the characteristics of the system are well known by the user, it is quite limited otherwise. In the same way, it is quite hard to study the same architecture across multiple technology nodes without substantial knowledge of it. 
-
-This motivates us to generate the Verilog code of the architecture to enable a second level of research concerning the architectures to be explored. This Verilog code encompasses the whole design and is divided into multiple sub-directories for targetted analysis or a global one. This is left to the choice of the user. 
-
-In this manual, we present FPGA-Verilog. This extension enables the generation of a fully functional Verilog code enabling a deeper understanding of the architectures of the FPGAs. We introduce different options to this module to do the verification of the system. This will be presented in more depth in the FPGA-Bitstream section.
+Driven by the strong need in data processing applications, Field Programmable Gate Arrays (FPGAs) are playing an ever-increasing role as programmable accelerators in modern
+computing systems. To fully unlock processing capabilities for domain-specific applications, FPGA architectures have to be tailored for seamless cooperation with other computing resources. However, prototyping and bringing to production a customized FPGA is a costly and complex endeavor even for industrial vendors. OpenFPGA, an opensource framework, aims to rapid prototype of customizable FPGA architectures through a semi-custom design approach. We propose an XML-to-Prototype design flow, where the Verilog netlists of a full FPGA fabric can be autogenerated using an extension of the XML language from the VTR framework and then fed into a back-end flow to generate production-ready layouts. 
 
 The technical details can be found in our TVLSI'19 paper :cite:`XTang_TVLSI_2019` and FPL'19 paper :cite:`XTang_FPL_2019`.
 
 FPGA-Bitstream
 --------------
 
-To have the right functionality on top of the FPGA generated, it is necessary to have a Bitstream generation which programs the FPGA. For this reason, we generate a Bitstream and some testbenches in parallel which allow the user to do some functional verification of the system to make sure that the functionality is respected. This includes three different testbenches. First, the FPGA is configured then the clock runs with random patterns are generated to test the functionality. Secondly, the FPGA can be configured in parallel to the testbench itself to do a comparison of the signals and check the validity. Finally, the configuration can be skipped to directly have access to the functioning of the system and reduce the processing time.
+EDA support is essential for end-users to implement designs on a customized FPGA. OpenFPGA provides a general-purpose bitstream generator FPGA-Bitstream for any architecture that can be described by VPR. As the native CAD tool for any customized FPGA that is produced by FPGA-Verilog, FPGA-Bitstream is ready to use once users finalize the XML-based architecture description file. This eliminates the huge engineering efforts spent on developing bitstream generator for customized FPGAs.
 
-This will be explained in more depth in the FPGA-Bitstream section.
+Using FPGA-Bitstream, users can launch (1) Verilog-to-Bitstream flow. This is the typical implementation flow for end-users; (2) Verilog-to-Verification flow. OpenFPGA can output Verilog testbenches with self-testing features to validate users' implemetations on their customized FPGA fabrics.
 
 The technical details can be found in our TVLSI'19 paper :cite:`XTang_TVLSI_2019` and FPL'19 paper :cite:`XTang_FPL_2019`.

From af6319a6b0aa0cce22545d7cc975b80a538c8417 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 9 Mar 2020 11:27:25 -0600
Subject: [PATCH 281/645] reworked motivation in documentation

---
 docs/Makefile                               |   2 +-
 docs/source/figures/openfpga_flow.png       | Bin 0 -> 175182 bytes
 docs/source/figures/openfpga_motivation.png | Bin 0 -> 279950 bytes
 docs/source/motivation.rst                  |  69 +++++++++++++++-----
 4 files changed, 55 insertions(+), 16 deletions(-)
 create mode 100644 docs/source/figures/openfpga_flow.png
 create mode 100644 docs/source/figures/openfpga_motivation.png

diff --git a/docs/Makefile b/docs/Makefile
index 1f299ec6b..6f26ca799 100644
--- a/docs/Makefile
+++ b/docs/Makefile
@@ -3,7 +3,7 @@
 
 # You can set these variables from the command line.
 SPHINXOPTS    =
-SPHINXBUILD   = sphinx-build
+SPHINXBUILD   = sphinx-build-3.6
 SOURCEDIR     = source
 BUILDDIR      = build
 
diff --git a/docs/source/figures/openfpga_flow.png b/docs/source/figures/openfpga_flow.png
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diff --git a/docs/source/motivation.rst b/docs/source/motivation.rst
index 7d068ac52..d52370f66 100644
--- a/docs/source/motivation.rst
+++ b/docs/source/motivation.rst
@@ -1,6 +1,60 @@
 Motivation
 ==========
 
+OpenFPGA aims to be an open-source framework that enables rapid prototyping of customizable FPGA architectures. As shown in :numref:`fig_openfpga_motivation`, a conventional approach will take a large group of experienced engineers more than one year to achieve production-ready layout and assoicated CAD tools. In fact, most of the engineering efforts are spent on manual layouts and developing ad-hoc CAD support.
+
+.. _fig_openfpga_motivation:
+
+.. figure:: ./figures/openfpga_motivation.png
+   :scale: 50%
+   :alt: OpenFPGA: a fast prototyping framework for customizable FPGAs
+
+   Comparison on engineering time and effort to prototype an FPGA using OpenFPGA and conventional approaches
+
+Using OpenFPGA, the development cycle in both hardware and software can be significantly accelerated. OpenFPGA can automatically generate Verilog netlists describing a full FPGA fabric based on an XML-based description file. Thanks to modern semi-custom design tools, production-ready layout generation can be achieved within 24 hours. To help sign-off, OpenFPGA can auto-generate Verilog testbenches to validate the correctness of FPGA fabric using modern verification tools.
+OpenFPGA also provides native bitstream generation support based the same XML-based description file used in Verilog generation. This avoid the recurring engineering in developing CAD tools for different FPGAs. Once the FPGA architecture is finalized, the CAD tool is ready to use.
+
+OpenFPGA can support any architecture that VPR can describe, covering most of the architecture enhancements available in modern FPGAs, and hence unlocks a large design space in prototyping customizable FPGAs. In addition, OpenFPGA provides enriched syntax which allows users to customized primitive circuit designed downto transistor-level parameters. This helps developers to customize the P.P.A. (Power, Performance and Area) to the best. All these features open the door of prototyping/studying flexible FPGAs to a small group of junior engineers or researchers. 
+
+In terms of tool functionality, OpenFPGA consists of the following parts: FPGA-Verilog, FPGA-SDC, FPGA-Bitstream and FPGA-SPICE.
+The rest of this section will focus on detailed motivation on each of them, as depicted in :numref:`fig_openfpga_flow`. 
+
+.. _fig_openfpga_flow:
+
+.. figure:: ./figures/openfpga_flow.png
+   :scale: 50%
+   :alt: Design flows avaiable in OpenFPGA
+
+   Design flows in different purposes using OpenFPGA
+
+
+FPGA-Verilog
+------------
+
+Driven by the strong need in data processing applications, Field Programmable Gate Arrays (FPGAs) are playing an ever-increasing role as programmable accelerators in modern
+computing systems. To fully unlock processing capabilities for domain-specific applications, FPGA architectures have to be tailored for seamless cooperation with other computing resources. However, prototyping and bringing to production a customized FPGA is a costly and complex endeavor even for industrial vendors. OpenFPGA, an opensource framework, aims to rapid prototype of customizable FPGA architectures through a semi-custom design approach. We propose an XML-to-Prototype design flow, where the Verilog netlists of a full FPGA fabric can be autogenerated using an extension of the XML language from the VTR framework and then fed into a back-end flow to generate production-ready layouts. 
+
+The technical details can be found in our TVLSI'19 paper :cite:`XTang_TVLSI_2019` and FPL'19 paper :cite:`XTang_FPL_2019`.
+
+FPGA-SDC
+--------
+
+Design constraints are indepensible in modern ASIC design flows to guarantee the performance level.
+OpenFPGA includes a rich SDC generator in the OpenFPGA framework to deal with both PnR constraints and sign-off timing analysis.
+Our flow automatically generates two sets of SDC files. The first set of SDC is designed for the P&R flow, where all the combinational loops are broken to enable wellcontrolled timing-driven P&R. In addition, there are SDC files devoted to constrain pin-to-pin timing for all the resources in FPGAs, in order to obtain nicely constrained and homogeneous delays across the fabric. The second set of SDC is designed for the timing analysis of a benchmark at the post P&R stage.
+
+The technical details can be found in our FPL'19 paper :cite:`XTang_FPL_2019`.
+
+
+FPGA-Bitstream
+--------------
+
+EDA support is essential for end-users to implement designs on a customized FPGA. OpenFPGA provides a general-purpose bitstream generator FPGA-Bitstream for any architecture that can be described by VPR. As the native CAD tool for any customized FPGA that is produced by FPGA-Verilog, FPGA-Bitstream is ready to use once users finalize the XML-based architecture description file. This eliminates the huge engineering efforts spent on developing bitstream generator for customized FPGAs.
+
+Using FPGA-Bitstream, users can launch (1) Verilog-to-Bitstream flow. This is the typical implementation flow for end-users; (2) Verilog-to-Verification flow. OpenFPGA can output Verilog testbenches with self-testing features to validate users' implemetations on their customized FPGA fabrics.
+
+The technical details can be found in our TVLSI'19 paper :cite:`XTang_TVLSI_2019` and FPL'19 paper :cite:`XTang_FPL_2019`.
+
 FPGA-SPICE
 ----------
 
@@ -17,19 +71,4 @@ In the appendix, we introduce the hierarchy of the generated SPICE netlists and
 
 The technical details can be found in our ICCD’15 paper :cite:`XTang_ICCD_2015` and TVLSI'19 paper :cite:`XTang_TVLSI_2019`.
 
-FPGA-Verilog
-------------
 
-Driven by the strong need in data processing applications, Field Programmable Gate Arrays (FPGAs) are playing an ever-increasing role as programmable accelerators in modern
-computing systems. To fully unlock processing capabilities for domain-specific applications, FPGA architectures have to be tailored for seamless cooperation with other computing resources. However, prototyping and bringing to production a customized FPGA is a costly and complex endeavor even for industrial vendors. OpenFPGA, an opensource framework, aims to rapid prototype of customizable FPGA architectures through a semi-custom design approach. We propose an XML-to-Prototype design flow, where the Verilog netlists of a full FPGA fabric can be autogenerated using an extension of the XML language from the VTR framework and then fed into a back-end flow to generate production-ready layouts. 
-
-The technical details can be found in our TVLSI'19 paper :cite:`XTang_TVLSI_2019` and FPL'19 paper :cite:`XTang_FPL_2019`.
-
-FPGA-Bitstream
---------------
-
-EDA support is essential for end-users to implement designs on a customized FPGA. OpenFPGA provides a general-purpose bitstream generator FPGA-Bitstream for any architecture that can be described by VPR. As the native CAD tool for any customized FPGA that is produced by FPGA-Verilog, FPGA-Bitstream is ready to use once users finalize the XML-based architecture description file. This eliminates the huge engineering efforts spent on developing bitstream generator for customized FPGAs.
-
-Using FPGA-Bitstream, users can launch (1) Verilog-to-Bitstream flow. This is the typical implementation flow for end-users; (2) Verilog-to-Verification flow. OpenFPGA can output Verilog testbenches with self-testing features to validate users' implemetations on their customized FPGA fabrics.
-
-The technical details can be found in our TVLSI'19 paper :cite:`XTang_TVLSI_2019` and FPL'19 paper :cite:`XTang_FPL_2019`.

From 3c7fd30e12a9f540623c3bcd40b4faed8a90d778 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 9 Mar 2020 13:58:24 -0600
Subject: [PATCH 282/645] merged tutorial to online documentation and reworked
 compilation guidelines

---
 README.md                                     |   2 +-
 docs/source/index.rst                         |  16 +---
 docs/source/motivation.rst                    |   6 --
 docs/source/tutorials/compile.rst             |  68 ++++++++++++++
 docs/source/{ => tutorials}/eda_flow.rst      |  43 +--------
 .../{ => tutorials}/figures/eda_flow.pdf      | Bin
 .../{ => tutorials}/figures/eda_flow.png      | Bin
 .../source/tutorials/figures}/frac_lut8.pdf   | Bin
 .../source/tutorials/figures}/fract_lut6.pdf  | Bin
 docs/source/tutorials/index.rst               |  12 ++-
 docs/source/{ => tutorials}/run_fpga_flow.rst |   0
 docs/source/{ => tutorials}/run_fpga_task.rst |   0
 tutorials/building.md                         |  54 -----------
 tutorials/fpga_flow/folder_organization.md    |  30 ------
 tutorials/fpga_flow/how2use.md                |  88 ------------------
 tutorials/fpga_flow/options.md                |  75 ---------------
 tutorials/tutorial_index.md                   |  20 ----
 17 files changed, 82 insertions(+), 332 deletions(-)
 create mode 100644 docs/source/tutorials/compile.rst
 rename docs/source/{ => tutorials}/eda_flow.rst (61%)
 rename docs/source/{ => tutorials}/figures/eda_flow.pdf (100%)
 rename docs/source/{ => tutorials}/figures/eda_flow.png (100%)
 rename {tutorials/images/architectures_schematics => docs/source/tutorials/figures}/frac_lut8.pdf (100%)
 rename {tutorials/images/architectures_schematics => docs/source/tutorials/figures}/fract_lut6.pdf (100%)
 rename docs/source/{ => tutorials}/run_fpga_flow.rst (100%)
 rename docs/source/{ => tutorials}/run_fpga_task.rst (100%)
 delete mode 100644 tutorials/building.md
 delete mode 100644 tutorials/fpga_flow/folder_organization.md
 delete mode 100644 tutorials/fpga_flow/how2use.md
 delete mode 100644 tutorials/fpga_flow/options.md
 delete mode 100644 tutorials/tutorial_index.md

diff --git a/README.md b/README.md
index c75d2e705..efc0d0ad3 100644
--- a/README.md
+++ b/README.md
@@ -6,7 +6,7 @@
 The OpenFPGA framework is the **first open-source FPGA IP generator** supporting highly-customizable homogeneous FPGA architectures. OpenFPGA provides a full set of EDA support for customized FPGAs, including Verilog-to-bitstream generation and self-testing verification [testbenches/scripts](./testbenches/scripts) OpenFPGA opens the door to democratizing FPGA technology and EDA techniques, with agile prototyping approaches and constantly evolving EDA tools for chip designers and researchers.
 
 ## Compilation
-Dependencies and help using docker can be found at [**./tutorials/building.md**](./tutorials/building.md).
+Dependencies and help using docker can be found [**here**](./docs/source/tutorials/building.rst).
 
 **Compilation Steps:**
 ```bash
diff --git a/docs/source/index.rst b/docs/source/index.rst
index 51fd1b119..9f4dd36d8 100644
--- a/docs/source/index.rst
+++ b/docs/source/index.rst
@@ -12,14 +12,10 @@ Welcome to OpenFPGA's documentation!
    motivation
 
 .. toctree::
+   :maxdepth: 2
    :caption: Getting Started
 
-   eda_flow
-
-   run_fpga_flow
-
-   run_fpga_task
-
+   tutorials/index
 
 .. toctree::
    :maxdepth: 2
@@ -33,12 +29,6 @@ Welcome to OpenFPGA's documentation!
 
    fpga_bitstream/index
 
-.. toctree::
-   :maxdepth: 2
-   :caption: User Guide
-
-   tutorials/index
-
 .. toctree::
    :maxdepth: 2
    :caption: Appendix
@@ -52,8 +42,6 @@ For more information on the Yosys see yosys_doc_ or yosys_github_
 
 For more information on the original FPGA architecture description language see xml_vtr_
 
-
-
 Indices and tables
 ==================
 
diff --git a/docs/source/motivation.rst b/docs/source/motivation.rst
index d52370f66..2dd4447df 100644
--- a/docs/source/motivation.rst
+++ b/docs/source/motivation.rst
@@ -65,10 +65,4 @@ FPGA-SPICE aims at generating SPICE netlists and testbenches for the FPGA archit
 
 SPICE modeling for FPGA architectures requires detailed transistor-level modeling for all the circuit elements within the considered FPGA architecture. However, current VPR architectural description language :cite:`JLuu_FPGA_2011` does not offer enough transistor-level parameters to model the most common circuit modules, such as multiplexers and LUTs. Therefore, we develop an extension on the VPR architectural description language to model the transistor-level circuit designs.
 
-In this manual, we will introduce how to use FPGA-SPICE to conduct an accurate power analysis. First, we give an overview of the design flow of FPGA-SPICE-based tool suites. Then, we show the command-line options of FPGA-SPICE. Afterward, we introduce the extension of architectural language and the transistor-level design supports. Finally, we present how to simulate the generated SPICE netlists and testbenches. 
-
-In the appendix, we introduce the hierarchy of the generated SPICE netlists and testbenches, to help you customize the SPICE netlists. We also attach an example of an architecture XML file for your interest.
-
 The technical details can be found in our ICCD’15 paper :cite:`XTang_ICCD_2015` and TVLSI'19 paper :cite:`XTang_TVLSI_2019`.
-
-
diff --git a/docs/source/tutorials/compile.rst b/docs/source/tutorials/compile.rst
new file mode 100644
index 000000000..cfa4dbe44
--- /dev/null
+++ b/docs/source/tutorials/compile.rst
@@ -0,0 +1,68 @@
+How to Compile
+==============
+
+General Compilation Guidelines
+------------------------------
+OpenFPGA uses CMake to generate the Makefile scripts
+In general, please follow the steps to compile
+
+::
+
+  git clone https://github.com/LNIS-Projects/OpenFPGA.git
+  cd OpenFPGA
+  mkdir build
+  cd build            
+  cmake ..  -DCMAKE_BUILD_TYPE=debug 
+  make                             
+
+.. note:: OpenFPGA requires gcc/g++ version >5
+
+.. note:: cmake3.12+ is recommended to compile OpenFPGA with GUI
+
+.. note:: recommand to use ``make -j`` to accelerate the compilation
+
+Quick Compilation Verification
+To quickly verify the tool is well compiled, user can run the following command from OpenFPGA root repository
+
+::
+
+  python3 openfpga_flow/scripts/run_fpga_task.py compilation_verification --debug --show_thread_logs
+
+Dependencies
+------------
+Full list of dependencies can be found at travis_setup_link_
+In particular, OpenFPGA requires specific versions for the following dependencies:
+
+:cmake:
+  version >3.12 for graphical interface
+
+:iverilog:
+  version 10.1+ is required to run Verilog-to-Verification flow
+
+.. _travis_setup_link: https://github.com/LNIS-Projects/OpenFPGA/blob/0cfb88a49f152aab0a06f309ff160f222bb51ed7/.travis.yml#L34
+
+Docker
+------
+If some of these dependencies are not installed on your machine, you can choose to use a Docker (the Docker tool needs to be installed).
+For the ease of the customer first experience, a Dockerfile is provided in the OpenFPGA folder. A container ready to use can be created with the following command
+
+::
+
+  docker run lnis/open_fpga:release
+
+.. note:: This command is for quick testing. If you want to conserve your work, you should certainly use other options, such as ``-v``.
+
+Otherwise, a container where you can build OpenFPGA yourself can be created with the following commands
+
+::
+
+  docker build . -t open_fpga
+  docker run -it --rm -v $PWD:/localfile/OpenFPGA -w="/localfile/OpenFPGA" open_fpga bash
+
+For more information about dock, see dock_download_link_
+
+.. _dock_download_link: https://www.docker.com/products/docker-desktop
+
+To build the tool, go in the OpenFPGA folder and follow the compilation steps
+
+.. note:: Using docker, you cannot use ``make -j``, errors will happen
diff --git a/docs/source/eda_flow.rst b/docs/source/tutorials/eda_flow.rst
similarity index 61%
rename from docs/source/eda_flow.rst
rename to docs/source/tutorials/eda_flow.rst
index 038b984af..446098d60 100644
--- a/docs/source/eda_flow.rst
+++ b/docs/source/tutorials/eda_flow.rst
@@ -5,7 +5,7 @@ As illustrated in :numref:`fig_eda_flow`, FPGA-SPICE creates a modified VTR flow
 
 .. _fig_eda_flow:
 
-.. figure:: figures/eda_flow.png
+.. figure:: ./figures/eda_flow.png
    :scale: 50%
    :alt: map to buried treasure
 
@@ -14,44 +14,3 @@ As illustrated in :numref:`fig_eda_flow`, FPGA-SPICE creates a modified VTR flow
 FPGA-Verilog is the part of the flow in charge of the Verilog and the semi-custom design flow. In our case, we use Cadence Innovus. The goal is to get the full-FPGA layout to complete the analysis provided by FPGA-SPICE. By having the layout, we can get an area analysis on the one hand and have new information concerning the power analysis. For instance, having the layout allows the user to have new information on the circuit such as the parasitics. 
 
 FPGA-Bitstream is the part of the flow in charge of the functional verification of the produced FPGA. Testbenches are generated by FPGA-Verilog and are combined with the full FPGA fabric in Modelsim. A bitstream is generated at the same time as the testbenches. This bitstream configures the FPGA with the functionality given by the user to VPR at the beginning of the flow. First, we configure the FPGA with the bitstream, and then waveforms are sent onto the I/O pads to check the functionality.
-
-
-How to compile
-==============
-Guides can be found in the *compilation* directory in the main folder. We tested it for MacOS High Sierra 10.13.4, Ubuntu 18.04 and Red Hat 7.5. This list is not exhaustive as other distributions could work as well.
-
-As a general rule, the compilation follows these steps:
-
-1) You clone the repository with:
-git clone --recurse-submodules https://github.com/LNIS-Projects/OpenFPGA,git
-
-Two different approaches exist from then on: Either you need the full flow, or you just need the extended version of VPR.
-If you need the full flow:
-
-2) Go into the folder you just cloned and make the different submodules through a global Makefile:
-cd OpenFPGA 
-mkdir build (*if folder doesn't already exist*)
-cd build
-cmake ..
-make OR make -j (*if you have multiple cores, this will make the compilation way faster*) 
-
-If you only need vpr:
-cd OpenFPGA 
-mkdir build (if folder doesn't already exist)
-cd build
-cmake ..
-make vpr/make vpr -j
-
-3) Architectures, circuits and already written scripts exist to allow you to test the flow without having to provide any new information to the system. For this:
-cd vpr7_x2p
-cd vpr
-source ./go_fpga_verilog/spice.sh
-
-They are scripts linking to a testing architecture and a simple circuit.
-
-4) If you only need to see the new options implemented in vpr, do:
-./vpr
-
-This step will show you all the different options which were added on top of VPR to enable deeper analysis of FPGA architectures.
-
-The released package includes a version of VPR with FPGA-SPICE, Verilog and Bitstream support, Yosys and ACE2.
diff --git a/docs/source/figures/eda_flow.pdf b/docs/source/tutorials/figures/eda_flow.pdf
similarity index 100%
rename from docs/source/figures/eda_flow.pdf
rename to docs/source/tutorials/figures/eda_flow.pdf
diff --git a/docs/source/figures/eda_flow.png b/docs/source/tutorials/figures/eda_flow.png
similarity index 100%
rename from docs/source/figures/eda_flow.png
rename to docs/source/tutorials/figures/eda_flow.png
diff --git a/tutorials/images/architectures_schematics/frac_lut8.pdf b/docs/source/tutorials/figures/frac_lut8.pdf
similarity index 100%
rename from tutorials/images/architectures_schematics/frac_lut8.pdf
rename to docs/source/tutorials/figures/frac_lut8.pdf
diff --git a/tutorials/images/architectures_schematics/fract_lut6.pdf b/docs/source/tutorials/figures/fract_lut6.pdf
similarity index 100%
rename from tutorials/images/architectures_schematics/fract_lut6.pdf
rename to docs/source/tutorials/figures/fract_lut6.pdf
diff --git a/docs/source/tutorials/index.rst b/docs/source/tutorials/index.rst
index 562a00bbb..e1cae21ac 100644
--- a/docs/source/tutorials/index.rst
+++ b/docs/source/tutorials/index.rst
@@ -1,10 +1,18 @@
 .. _tutorials:
-   Tutorials
+   Getting Started
  
 .. toctree::
    :maxdepth: 2
 
-   getting_started
+   compile
+
+   eda_flow
+
+   run_fpga_flow
+
+   run_fpga_task
+
+   
   
 
    
diff --git a/docs/source/run_fpga_flow.rst b/docs/source/tutorials/run_fpga_flow.rst
similarity index 100%
rename from docs/source/run_fpga_flow.rst
rename to docs/source/tutorials/run_fpga_flow.rst
diff --git a/docs/source/run_fpga_task.rst b/docs/source/tutorials/run_fpga_task.rst
similarity index 100%
rename from docs/source/run_fpga_task.rst
rename to docs/source/tutorials/run_fpga_task.rst
diff --git a/tutorials/building.md b/tutorials/building.md
deleted file mode 100644
index badf9bab5..000000000
--- a/tutorials/building.md
+++ /dev/null
@@ -1,54 +0,0 @@
-# How to build?
-
-## Dependencies
-OpenFPGA requires all the following dependencies:
-- autoconf
-- automake
-- bash
-- bison
-- build-essential
-- cmake (version 3.12 for graphical interface or at least 3.X)
-- ctags
-- curl
-- doxygen
-- flex
-- fontconfig
-- g++-8
-- gcc-8
-- g++-4.9
-- gcc-4.9
-- gdb
-- git
-- gperf
-- iverilog
-- libcairo2-dev
-- libevent-dev
-- libfontconfig1-dev
-- liblist-moreutils-perl
-- libncurses5-dev
-- libx11-dev
-- libxft-dev
-- libxml++2.6-dev
-- perl
-- python
-- texinfo
-- time
-- valgrind
-- zip
-- qt5-default
-
-## Docker
-If some of these dependencies are not installed on your machine, you can choose to use a Docker (the Docker tool needs to be installed). For the ease of the customer first experience, a Dockerfile is provided in the OpenFPGA folder. A container ready to use can be created with the following command:
-- docker run lnis/open_fpga:release <br />
-*Warning: This command is for quick testing. If you want to conserve your work, you should certainly use other options, such as "-v".*
-
-Otherwise, a container where you can build OpenFPGA yourself can be created with the following commands:
-- docker build . -t open_fpga
-- docker run -it --rm -v $PWD:/localfile/OpenFPGA -w="/localfile/OpenFPGA" open_fpga bash<br />
-[*docker download link*](https://www.docker.com/products/docker-desktop)
-
-## Building
-To build the tool, go in the OpenFPGA folder and do:
-- mkdir build && cd build
-- cmake .. -DCMAKE_BUILD_TYPE=debug
-- make (*WARNING using docker you cannot use "make -j", errors will happen*)
diff --git a/tutorials/fpga_flow/folder_organization.md b/tutorials/fpga_flow/folder_organization.md
deleted file mode 100644
index 172f10782..000000000
--- a/tutorials/fpga_flow/folder_organization.md
+++ /dev/null
@@ -1,30 +0,0 @@
-# fpga_flow folder organization
-
-The fpga_flow folder is organized as follow:
-* **arch**: contains architectures description files
-* **benchmarks**: contains Verilog and blif benchmarks + lists
-* **configs**: contains configuration files to run fpga_flow.pl
-* **scripts**: contains all the scripts required to run the flow
-* **tech**: contains xml tech files for power estimation
-
-## arch
-In this folder are saved the architecture files. These files are Hardware description for the FPGA written in XML. This folder contains 3 sub-folders:
-- **fpga_spice**: contains existing architecture ready to use.
-- **template**: contains template architecture which contain keyword to replace
-- **generated**: empty at the beginning, will host rewritten template
-
-## benchmarks
-This folder contains benchmarks to implement in the FPGA. it's divided in 3 folders:
-- **Blif**: Contains .blif and .act file to use in OpenFPGA. Benchmarks are divided in folder with the same name as the top module
-- **Verilog**: Contains Verilog netlist of benchmarks to use in OpenFPGA. Each project is saved in a folder with the same name as the top module.
-- **List**: Contains files with a list of benchmarks to run in one flow. More details are available in [fpga_flow tutorial](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/fpga_flow/how2use.md#benchmark-list)
-
-## configs
-This folder contains configuration files required by openFPGA flow. They specify path to tools and benchmarks as well as flow utilization mode. More details are available in [fpga_flow tutorial](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/fpga_flow/how2use.md#configuration-file)
-
-## scripts
-This folder contains scripts call by OpenFPGA flow. Some of them can be used out of the flow as **pro_blif.pl** and **rewrite_path_in_file.pl** which respectively rewrite a blif file with 3 members on a ".latch" module to let it have 5 and replace a keyword in a file.<br />
-Any script provide help if call without argument.
-
-## tech
-This folder contains XML files describing the technology used. These files are used during power analysis.
diff --git a/tutorials/fpga_flow/how2use.md b/tutorials/fpga_flow/how2use.md
deleted file mode 100644
index 905adb5d1..000000000
--- a/tutorials/fpga_flow/how2use.md
+++ /dev/null
@@ -1,88 +0,0 @@
-# FPGA Flow
-This tutorial will help the user to understand how to use the OpenFPGA flow.<br />
-During this tutorial, we consider that the user starts in the OpenFPGA folder and we will use tips and information provided in [tutorial index](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/tutorial_index.md#tips-and-informations). Details on how the folder is organized are available [here](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/fpga_flow/folder_organization.md).
-
-## Running fpga_flow.pl
-A script example can be found at OPENFPGAPATHKEYWORD/fpga_flow/tuto_fpga_flow.sh.
-
-### Experiment
-cd fpga_flow<br />
-./tuto_fpga_flow.sh<br />
-
-### Explanation
-The *fpga_flow.pl* script takes an architecture description file (.xml), generates its netlists and generates a bitstream to implement a benchmark on the FPGA fabric and verifis its correct implementation.<br />
-When you open the perl script, you can see that 2 scripts are called. The first one is **rewrite_path_in_file.pl** which allows us to make this tutorial generic by generating full path to the dependencies.<br />
-The second one is **fpga_flow.pl**. This script launches the OpenFPGA flow and can be used with many different [options](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/fpga_flow/options.md).<br />
-There are 3 important things to observe here:
-- All the FPGA-Verilog options have been activated
-- fpga_flow.pl calls a configuration file through the "config_file" variable
-- fpga_flow.pl calls a list of benchmark to be implemented and tested through the "bench_txt" variable
-
-### Configuration File
-In this file, paths have to be defined as **absolute** paths as relative paths could lead to errors.<br />
-The file is organized in 3 parts: 
-* **dir_path**: provides all the tool and repository paths
-* **flow_conf**: provides information on how the flow runs
-* **csv_tags**: *to be completed*
-
-When empty, the file is as follow:
-
-[dir_path]<br />
-script_base = OPENFPGAPATHKEYWORD/fpga_flow/scripts<br />
-benchmark_dir = *<Path to the folder containing all sources of the design>*<br />
-yosys_path = OPENFPGAPATHKEYWORD/yosys<br />
-odin2_path = not_used<br />
-cirkit_path = not_used<br />
-abc_path = OPENFPGAPATHKEYWORD/abc<br />
-abc_mccl_path = OPENFPGAPATHKEYWORD/abc<br />
-abc_with_bb_support_path = OPENFPGAPATHKEYWORD/abc<br />
-mpack1_path = not_used<br />
-m2net_path = not_used<br />
-mpack2_path = not_used<br />
-vpr_path = OPENFPGAPATHKEYWORD/vpr7_x2p/vpr<br />
-rpt_dir = *<wherever you want logs to be saved>*<br />
-ace_path = OPENFPGAPATHKEYWORD/ace2<br />
-
-[flow_conf]<br />
-flow_type = yosys_vpr *to use verilog input*<br />
-vpr_arch = *<wherever the architecture file is saved>*<br />
-mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK<br />
-m2net_conf = not_used<br />
-mpack2_arch = not_used<br />
-power_tech_xml = *<wherever the xml tech file is saved>*<br />
-
-[csv_tags]<br />
-mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf:<br />
-mpack2_tags = BLE Number:|BLE Fill Rate: <br />
-vpr_tags = Netlist clb blocks:|Final critical path:|Total logic delay:|total net delay:|Total routing area:|Total used logic block area:|Total wirelength:|Packing took|Placement took|Routing took|Average net density:|Median net density:|Recommend no. of clock cycles:<br />
-vpr_power_tags = PB Types|Routing|Switch Box|Connection Box|Primitives|Interc Structures|lut6|ff<br />
-
-*This example file can be found at OPENFPGAPATHKEYWORD/fpga_flow/configs/tutorial/tuto.conf*
-
-### Benchmark List
-The benchmark folder contains 3 sub-folders:
-* **Blif**: contains .blif and .act of benchmarks
-* **List**: contains all benchmark list files
-* **Verilog**: contains Verilog designs
-
-Blif and Verilog folders are organized by folders using the name of the projects. **The folder, top module and top module file must share the same name.**<br />
-The benchmark list file can contain as many benchmarks as available in the same folder targetted by the "benchmark_dir" variable from the configuration file. It's written as:<br />
-top_module/*.v,<int_value>; where <int_value> is the number of channel/wire between each block.
-
-*This example file can be found at OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/List/tuto_benchmark.txt*
-
-
-## Modifying the Flow
-Once the dependencies are understood, the flow can be modified by changing the architecture file and the route channel width.
-
-### Experiment
-* cd OPENFPGAPATHKEYWORD/fpga_flow/configs/tutorial
-* replace the architecture "k6_N10_sram_chain_HC_template.xml" and "k6_N10_sram_chain_HC.xml" respectively with "k8_N10_sram_chain_FC_template.xml" and "k8_N10_sram_chain_FC.xml" in tuto.conf
-* cd OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/List
-* replace "200" with "300" in tuto_benchmark.txt
-* cd OPENFPGAPATHKEYWORD/fpga_flow
-* replace the architecture "k6_N10_sram_chain_HC_template.xml" and "k6_N10_sram_chain_HC.xml" respectively with "k8_N10_sram_chain_FC_template.xml" and "k8_N10_sram_chain_FC.xml" in tuto_fpga_flow.sh
-* ./tuto_fpga_flow.sh
-
-### Explanations
-With this last experiment, the [**K6 architecture**](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/images/architectures_schematics/frac_lut6.pdf) was replaced by a [**K8 architecture**](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/images/architectures_schematics/frac_lut8.pdf), which means that an 8-input fracturable LUT (implemented by LUT6 and LUT4 with 2 shared inputs) is used. This architecture provides more modes for the CLB and the crossbar which is changed from a half-connected to a fully connected, implying bigger multiplexors between the CLB and LUT inputs. These requirements in term of interconnection will lead an increase in the routing channel width. Indeed, if the routing channel is too low, it could be impossible to route a benchmark or the FPGA output could be delayed.
diff --git a/tutorials/fpga_flow/options.md b/tutorials/fpga_flow/options.md
deleted file mode 100644
index 38932d0c1..000000000
--- a/tutorials/fpga_flow/options.md
+++ /dev/null
@@ -1,75 +0,0 @@
-# OpenFPGA flow options
-
-Usage -> **fpga_flow *-options <value>* **<br />
-Mandatory options: <br />
-- -conf <file> : *specify the basic configuration files for fpga_flow*
-- -benchmark <file> : *the configuration file contains benchmark file names*
-- -rpt <file> : *CSV file consists of data*
-- -N <int> : *N-LUT/Matrix*
-
-## Other Options:
-### General
-- -matlab_rpt <data_name> : *.m file consists of data compatible to matlab scripts. Specify the data name to be appeared in the script*
-- -I <int> : *Number of inputs of a CLB, mandatory when mpack1 flow is chosen*
-- -K <int> : *K-LUT, mandatory when standard flow is chosen*
-- -M <int> : *M-Matrix, mandatory when mpack1 flow is chosen*
-- -power : *run power estimation oriented flow*
-- -black_box_ace: *run activity estimation with black box support. It increase the power.*
-- -remove_designs: *remove all the old results.*
-- -multi_thread <int>: *turn on the mutli-thread mode, specify the number of threads*
-- -multi_task <int>: *turn on the mutli-task mode*
-- -parse_results_only : *only parse the flow results and write CSV report.*
-- -debug : *debug mode*
-- -help : *print usage*
-- -end_flow_with_test: *Uses Icarus Verilog simulator to verified bencmark implementation*
-### ODIN II
-- -min_hard_adder_size: *min. size of hard adder in carry chain defined in Arch XML.(Default:1)*
-- -mem_size: *size of memory, mandatory when VTR/VTR_MCCL/VTR_MIG_MCCL flow is chosen*
-- -odin2_carry_chain_support: *turn on the carry_chain support only valid for VTR_MCCL/VTR_MIG_MCCL flow *
-### ABC
-- -abc_scl : *run ABC optimization for sequential circuits, mandatory when VTR flow is selected.*
-- -abc_verilog_rewrite : *run ABC to convert a blif netlist to a Verilog netlist.*
-### ACE
-- -ace_p <float> : *specify the default signal probablity of PIs in ACE2.*
-- -ace_d <float> : *specify the default signal density of PIs in ACE2.*
-### VPR - Original Version
-- -vpr_timing_pack_off : *turn off the timing-driven pack for vpr.*
-- -vpr_place_clb_pin_remap: *turn on place_clb_pin_remap in VPR.*
-- -vpr_max_router_iteration <int> : *specify the max router iteration in VPR.*
-- -vpr_route_breadthfirst : *use the breadth-first routing algorithm of VPR.*
-- -vpr_use_tileable_route_chan_width: *turn on the conversion to tileable_route_chan_width in VPR.*
-- -min_route_chan_width <float> : *turn on routing with <float>* min_route_chan_width.*
-- -fix_route_chan_width : *turn on routing with a fixed route_chan_width, defined in benchmark configuration file.*
-### VPR - FPGA-X2P Extension
-- -vpr_fpga_x2p_rename_illegal_port : *turn on renaming illegal ports option of VPR FPGA SPICE*
-- -vpr_fpga_x2p_signal_density_weight <float>: *specify the option signal_density_weight of VPR FPGA SPICE*
-- -vpr_fpga_x2p_sim_window_size <float>: *specify the option sim_window_size of VPR FPGA SPICE*
-- -vpr_fpga_x2p_compact_routing_hierarchy : *allow routing block modularization*
-### VPR - FPGA-SPICE Extension
-- -vpr_fpga_spice <task_file> : *turn on SPICE netlists print-out in VPR, specify a task file*
-- -vpr_fpga_spice_sim_mt_num <int>: *specify the option sim_mt_num of VPR FPGA SPICE*
-- -vpr_fpga_spice_print_component_tb : *print component-level testbenches in VPR FPGA SPICE*
-- -vpr_fpga_spice_print_grid_tb : *print Grid-level testbenches in VPR FPGA SPICE*
-- -vpr_fpga_spice_print_top_tb : *print full-chip testbench in VPR FPGA SPICE*
-- -vpr_fpga_spice_leakage_only : *turn on leakage_only mode in VPR FPGA SPICE*
-- -vpr_fpga_spice_parasitic_net_estimation_off : *turn off parasitic_net_estimation in VPR FPGA SPICE*
-- -vpr_fpga_spice_testbench_load_extraction_off : *turn off testbench_load_extraction in VPR FPGA SPICE*
-- -vpr_fpga_spice_simulator_path <string> : *Specify simulator path*
-### VPR - FPGA-Verilog Extension
-- -vpr_fpga_verilog : *turn on OpenFPGA Verilog Generator*
-- -vpr_fpga_verilog_dir <verilog_path>: *provides the path where generated verilog files will be written*
-- -vpr_fpga_verilog_include_timing : *turn on printing delay specification in Verilog files*
-- -vpr_fpga_verilog_include_signal_init : *turn on printing signal initialization in Verilog files*
-- -vpr_fpga_verilog_print_autocheck_top_testbench: *turn on printing autochecked top-level testbench for OpenFPGA Verilog Generator*
-- -vpr_fpga_verilog_formal_verification_top_netlist : *turn on printing formal top Verilog files*
-- -vpr_fpga_verilog_include_icarus_simulator : *Add syntax and definition required to use Icarus Verilog simulator*
-- -vpr_fpga_verilog_print_user_defined_template : *Generates a template of hierarchy modules and their port mapping*
-- -vpr_fpga_verilog_print_report_timing_tcl : *Generates tcl script useful for timing report generation*
-- -vpr_fpga_verilog_report_timing_rpt_path <path_to_generate_reports> : *Specify path for report timing*
-- -vpr_fpga_verilog_print_sdc_pnr : *Generates sdc file to constraint Hardware P&R*
-- -vpr_fpga_verilog_print_sdc_analysis : *Generates sdc file to do STA*
-- -vpr_fpga_verilog_print_top_tb : *turn on printing top-level testbench for OpenFPGA Verilog Generator*
-- -vpr_fpga_verilog_print_input_blif_tb : *turn on printing testbench for input blif file in OpenFPGA Verilog Generator*
-- -vpr_fpga_verilog_print_modelsim_autodeck <modelsim.ini_path>: *turn on printing modelsim simulation script*
-### VPR - FPGA-Bitstream Extension
-- -vpr_fpga_bitstream_generator: *turn on FPGA-SPICE bitstream generator*
diff --git a/tutorials/tutorial_index.md b/tutorials/tutorial_index.md
deleted file mode 100644
index bbf95ff86..000000000
--- a/tutorials/tutorial_index.md
+++ /dev/null
@@ -1,20 +0,0 @@
-# Tutorial Introduction
-OpenFPGA is an IP Verilog Generator allowing reliable and fast testing of homogeneous FPGA architectures.<br />
-Its main goal is to easily and efficiently generated a complete customizable FPGA and uses a semi-custom design flow.<br /><br />
-In order to help you get in touch with the software, we provide few tutorials which are organized as follow:
-* [Building the tool and his dependencies](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/building.md)
-* [Launching the flow and understand how it works](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/fpga_flow/how2use.md)
-* Architecture modification
-
-## Folder Organization
-OpenFPGA repository is organized as follow:
-* **abc**: open source synthesys tool
-* **ace2**: abc extension generating .act files
-* **ace2**: abc extension generating activity files (.act)
-* **vpr7_x2p**: sources of modified vpr
-* **yosys**: opensource synthesys tool
-* **fpga_flow**: scripts and dependencies to run the complete flow
-
-## Tips and Information
-Some keywords will be used during in the tutorials:
-* OPENFPGAPATHKEYWORD: refers to OpenFPGA folder full path

From 751735bf412adb3b71d49537d6157e6b80d16341 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 9 Mar 2020 17:40:33 -0600
Subject: [PATCH 283/645] update documentation in simulation setting syntax

---
 docs/source/arch_lang/addon_vpr_syntax.rst    |  37 +++++
 ...cuit_modules.rst => annotate_vpr_arch.rst} |  16 +-
 ...ircuit_modules.rst => circuit_library.rst} |  22 ++-
 .../arch_lang/circuit_model_examples.rst      |  24 +--
 ...terconnect.rst => direct_interconnect.rst} |  53 +++---
 docs/source/arch_lang/generality.rst          |  40 ++++-
 docs/source/arch_lang/index.rst               |  17 +-
 ...sim_setting.rst => simulation_setting.rst} | 154 +++++++++++++++++-
 .../{tech_lib.rst => technology_library.rst}  |   6 +-
 docs/source/contact.rst                       |   2 +-
 docs/source/fpga_bitstream/index.rst          |   5 +-
 docs/source/fpga_spice/index.rst              |   5 +-
 docs/source/fpga_verilog/index.rst            |   5 +-
 docs/source/index.rst                         |   6 +-
 docs/source/motivation.rst                    |  12 +-
 docs/source/tutorials/compile.rst             |  14 +-
 docs/source/tutorials/eda_flow.rst            |   6 +-
 17 files changed, 337 insertions(+), 87 deletions(-)
 create mode 100644 docs/source/arch_lang/addon_vpr_syntax.rst
 rename docs/source/arch_lang/{link_circuit_modules.rst => annotate_vpr_arch.rst} (97%)
 rename docs/source/arch_lang/{circuit_modules.rst => circuit_library.rst} (97%)
 rename docs/source/arch_lang/{interconnect.rst => direct_interconnect.rst} (50%)
 rename docs/source/arch_lang/{spice_sim_setting.rst => simulation_setting.rst} (56%)
 rename docs/source/arch_lang/{tech_lib.rst => technology_library.rst} (96%)

diff --git a/docs/source/arch_lang/addon_vpr_syntax.rst b/docs/source/arch_lang/addon_vpr_syntax.rst
new file mode 100644
index 000000000..7122c9870
--- /dev/null
+++ b/docs/source/arch_lang/addon_vpr_syntax.rst
@@ -0,0 +1,37 @@
+.. _addon_vpr_syntax:
+
+Additional Syntax to Original VPR XML
+-------------------------------------
+
+.. warning:: Note this is only applicable to VPR8!
+
+  
+Each ``<pb_type>`` should contain a ``<mode>`` that describe the physical implementation of the ``<pb_type>``. Note that this is fully compatible to the VPR architecture XML syntax.
+  
+``<model>`` should include the models that describe the primitive ``<pb_type>`` in physical mode.
+  
+``<layout>`` may include additioinal syntax to enable tileable routing resource graph generation
+
+.. option:: tileable="<bool>"
+
+  Turn on/off tileable routing resource graph generator
+
+``<switch_block>`` may include addition syntax to enable different connectivity for pass tracks
+
+.. option:: sub_type="<string>"
+  
+  Connecting type for pass tracks in each switch block
+  If not specified, the pass tracks will the same connecting patterns as start/end tracks, which are defined in ``type``
+
+.. option:: sub_Fs="<int>"
+
+  Connectivity parameter for pass tracks in each switch block. Must be a multiple of 3.
+  If not specified, the pass tracks will the same connectivity as start/end tracks, which are defined in ``fs``
+
+.. note:: Currently, OpenFPGA only supports uni-directional routing architectures
+
+.. note:: Currently, OpenFPGA only supports 1 ``<equivalent_sites>`` to be defined under each ``<tile>``
+
+.. note:: OpenFPGA require explicit names to be defined for each routing segement in ``<segmentlist>`` 
+
+
diff --git a/docs/source/arch_lang/link_circuit_modules.rst b/docs/source/arch_lang/annotate_vpr_arch.rst
similarity index 97%
rename from docs/source/arch_lang/link_circuit_modules.rst
rename to docs/source/arch_lang/annotate_vpr_arch.rst
index fc2a27256..25b0e5d3e 100644
--- a/docs/source/arch_lang/link_circuit_modules.rst
+++ b/docs/source/arch_lang/annotate_vpr_arch.rst
@@ -1,9 +1,11 @@
-Link circuit modules
---------------------
+.. _annotate_vpr_arch:
+
+Bind circuit modules to VPR architecture 
+----------------------------------------
 Each defined circuit model should be linked to an FPGA module defined in the original part of architecture descriptions. It helps FPGA-circuit creating the circuit netlists for logic/routing blocks. Since the original part lacks such support, we create a few XML properties to link to Circuit models.
 
 SRAM
-====
+~~~~
 
 To link the defined circuit model of SRAM into the FPGA architecture description, a new line in XML format should be added under the XML node device. The new XML node is named as sram, which defines the area of an SRAM and the name of the circuit model to be linked. An example is shown as follows:
 
@@ -42,7 +44,7 @@ Here is an example.
 
 
 Switch Boxes
-=============
+~~~~~~~~~~~~
 
 Original VPR architecture description contains an XML node called switchlist under which all the multiplexers of switch blocks are described.
 To link a defined circuit model to a multiplexer in the switch blocks, a new XML property circuit_model_name should be added to the descriptions.
@@ -59,7 +61,7 @@ Here is an example:
 
 
 Connection Blocks
-==================
+~~~~~~~~~~~~~~~~~
 
 To link the defined circuit model of the multiplexer to the Connection Blocks, a circuit_model_name should be added to the definition of Connection Blocks switches.  However, the original architecture descriptions do not offer a switch description for connection boxes as they do for the switch blocks.
 Therefore, FPGA-circuit requires a new XML node called **cblock** under the root XML node architecture, where a switch for connection blocks can be defined.
@@ -75,7 +77,7 @@ Here is the example:
 * **circuit_model_name:** should match a circuit model whose type is mux defined under module_circuit_models.
 
 Channel Wire Segments
-=====================
+~~~~~~~~~~~~~~~~~~~~~
 
 Similar to the Switch Boxes and Connection Blocks, the channel wire segments in the original architecture descriptions can be adapted to provide a link to the defined circuit model.
 
@@ -88,7 +90,7 @@ Similar to the Switch Boxes and Connection Blocks, the channel wire segments in
 * circuit_model_name: should match a circuit model whose type is chan_wire defined under module_circuit_models.
 
 Primitive Blocks inside Multi-mode Configurable Logic Blocks
-=============================================================
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 The architecture description employs a hierarchy of ``pb_types`` to depict the sub-modules and complex interconnections inside logic blocks. Each leaf node and interconnection in the pb_type hierarchy should be linked to a circuit model.
 Each primitive block, i.e., the leaf ``pb_types``, should be linked to a valid circuit model, using the XML syntax ``circuit_model_name``.
diff --git a/docs/source/arch_lang/circuit_modules.rst b/docs/source/arch_lang/circuit_library.rst
similarity index 97%
rename from docs/source/arch_lang/circuit_modules.rst
rename to docs/source/arch_lang/circuit_library.rst
index e7f4e736a..138544bb2 100644
--- a/docs/source/arch_lang/circuit_modules.rst
+++ b/docs/source/arch_lang/circuit_library.rst
@@ -1,13 +1,15 @@
-Define Circuit-level Modules
-============================
+.. _circuit_library:
+
+Circuit Library
+---------------
 
 To support FPGA Verilog/SPICE, Verily and Bitstream Generator, physical modules containing gate-level and transistor-level features are required for FPGA primitive blocks.
 The physical modules are defined in XML syntax, similar to the original VPR FPGA architecture description language.
 
 For each module that appears in the FPGA architecture, a circuit model should be defined. In the definition of a circuit model, the user can specify if the Verilog/SPICE netlist of the module is either auto-generated or user-defined.
 
-Define circuit_models
----------------------
+Circuit Model Attributes
+~~~~~~~~~~~~~~~~~~~~~~~~
 
 .. code-block:: xml
 
@@ -43,8 +45,8 @@ Define circuit_models
 .. note:: Under the XML node circuit_model, the features of transistor-level designs can be defined. In the following table, we show the common features supported for all the modules.  Then, we will introduce unique features supported only for some circuit models types.
 
 
-Transistor level
-----------------
+Design Technology-related Attributes
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 .. code-block:: xml
 
@@ -65,6 +67,14 @@ Transistor level
 
 .. note:: Currently, the RRAM-based designs are only supported for multiplexers.
 
+
+Input/Output Buffer
+~~~~~~~~~~~~~~~~~~~
+
+Circuit Port Attributes
+~~~~~~~~~~~~~~~~~~~~~~~
+
+
 * input_buffer and output_buffer:
     
     * **exist:** [on|off]. Define the existence of the input_buffer or output_buffer. Note that the existence is valid for all the inputs and outputs. Note that if users want only part of the inputs (or outputs) to be buffered, this is not supported here. A solution can be building a user-defined Verilog/SPICE netlist.
diff --git a/docs/source/arch_lang/circuit_model_examples.rst b/docs/source/arch_lang/circuit_model_examples.rst
index 26cb27e13..7e6a50229 100644
--- a/docs/source/arch_lang/circuit_model_examples.rst
+++ b/docs/source/arch_lang/circuit_model_examples.rst
@@ -1,9 +1,11 @@
+.. _circuit_model_examples:
+
 Circuit model examples
-======================
+----------------------
 The next subsections are dedicated to detailed examples of each circuit model type. Through these examples, we give a global overview of the different implementations which are available for the user.
 
 Inverters and Buffers
----------------------
+~~~~~~~~~~~~~~~~~~~~~
 
 .. code-block:: xml
 
@@ -131,7 +133,7 @@ This example shows:
 
 
 Pass-gate Logic
----------------
+~~~~~~~~~~~~~~~
 
 .. code-block:: xml
 
@@ -212,7 +214,7 @@ This example shows:
 
 
 SRAMs
------
+~~~~~
 
 .. code-block:: xml
 
@@ -231,7 +233,7 @@ SRAMs
 .. note:: The support SRAM modules should have a BL and a WL when the memory-bank-style configuration circuit is declared. Note that the WL should be the write/read enable signal, while BL is the data input.
 
 Logic gates
------------
+~~~~~~~~~~~
 
 .. code-block:: xml
 
@@ -250,7 +252,7 @@ Logic gates
 .. note:: It may happen that the port sequence in generated Verilog netlists has conflicts with the port sequence in standard and customized cells. To avoid this, users can set the XML keyword ``dump_explicit_port_map`` to be true, which enables explicit port mapping are dumped. Users can specify the pin/port name in the standard cell library using the XML keyword ``lib_name``.
 
 Multiplexers
-------------
+~~~~~~~~~~~~
 
 .. code-block:: xml
 
@@ -353,7 +355,7 @@ If we arbitrarily fix the number of Mux entries at 4, the following code could i
 	* The number of entries parametrized by ``size`` in input port-type.
 
 Look-Up Tables
---------------
+~~~~~~~~~~~~~~
 
 .. code-block:: xml
 
@@ -425,7 +427,7 @@ The code describing this LUT is:
 	* How each blocks is defined
 
 Flip-Flops
-----------
+~~~~~~~~~~
 
 .. code-block:: xml
 
@@ -509,7 +511,7 @@ The code describing this FF is:
 	* 1 port, ``clk``, defined as global
 
 Hard Logics
------------
+~~~~~~~~~~~
 
 .. code-block:: xml
 
@@ -533,7 +535,7 @@ Instructions of defining design parameters:
 * **port:** two types of ports (``input`` and ``output``) should be defined. If the user provides a user-defined Verilog/SPICE netlist, the bandwidth of ports should be defined to the same as the Verilog/SPICE netlist.
 
 Routing Wire Segments
----------------------
+~~~~~~~~~~~~~~~~~~~~~
 
 FPGA-Verilog/SPICE provides two types of Verilog/SPICE models for the wire segments in FPGA architecture:
 
@@ -596,7 +598,7 @@ The code describing this wire is:
 	* How to use this circuit_model to auto-generate the Verilog/SPICE netlist
 
 I/O pads
---------
+~~~~~~~~
 
 .. code-block:: xml
 
diff --git a/docs/source/arch_lang/interconnect.rst b/docs/source/arch_lang/direct_interconnect.rst
similarity index 50%
rename from docs/source/arch_lang/interconnect.rst
rename to docs/source/arch_lang/direct_interconnect.rst
index a6542ccb5..21b91b74b 100644
--- a/docs/source/arch_lang/interconnect.rst
+++ b/docs/source/arch_lang/direct_interconnect.rst
@@ -1,10 +1,12 @@
-Interconnection extensions
-==========================
+.. _direct_interconnect:
+
+Inter-Tile Direct Interconnection extensions
+--------------------------------------------
 
 This section introduces extensions on the architecture description file about existing interconnection description.
 
 Directlist
-----------
+~~~~~~~~~~
 
 The original direct connections in the directlist section are documented here_. Its description is given below:
 
@@ -26,40 +28,49 @@ Our extension include three more options:
     <direct name="string" from_pin="string" to_pin="string" x_offset="int" y_offset="int" z_offset="int" switch_name="string" interconnection_type="string" x_dir="string" y_dir="string"/>
   </directlist>
 
-.. note:: these options are optional. However, if *interconnection_type* is set *x_dir* and *y_dir* are required.
+.. note:: these options are optional. However, if `interconnection_type` is set `x_dir` and `y_dir` are required.
 
-* **interconnection_type**: [``NONE`` | ``column`` | ``row``], specifies if it applies on a column or a row ot if it doesn't apply.
+.. option:: interconnection_type="<string>"
 
-* **x_dir**: [``positive`` | ``negative``], specifies if the next cell to connect has a bigger or lower x value. Considering a coordinate system where (0,0) is the origin at the bottom left and *x* and *y* are positives: 
+  the type of interconnection should be a string.
+  Available types are ``NONE`` | ``column`` | ``row``, specifies if it applies on a column or a row ot if it doesn't apply.
 
-    * x_dir="positive": 
+.. option:: x_dir="<string>"
 
-        * interconnection_type="column": a column will be connected to a column on the **right**, if it exists.
+  Available directionalities are ``positive`` | ``negative``, specifies if the next cell to connect has a bigger or lower ``x`` value.
+  Considering a coordinate system where (0,0) is the origin at the bottom left and ``x`` and ``y`` are positives: 
 
-        * interconnection_type="row": the most on the **right** cell from a row connection will connect the most on the **left** cell of next row, if it exists.
+    - x_dir="positive": 
 
-    * x_dir="negative": 
+        - interconnection_type="column": a column will be connected to a column on the ``right``, if it exists.
 
-        * interconnection_type="column": a column will be connected to a column on the **left**, if it exists.
+        - interconnection_type="row": the most on the ``right`` cell from a row connection will connect the most on the ``left`` cell of next row, if it exists.
 
-        * interconnection_type="row": the most on the **left** cell from a row connection will connect the most on the **right** cell of next row, if it exists.
+    - x_dir="negative": 
 
-* **y_dir**: [``positive`` | ``negative``], specifies if the next cell to connect has a bigger or lower x value. Considering a coordinate system where (0,0) is the origin at the bottom left and *x* and *y* are positives:
+        - interconnection_type="column": a column will be connected to a column on the ``left``, if it exists.
 
-    * y_dir="positive": 
+        - interconnection_type="row": the most on the ``left`` cell from a row connection will connect the most on the ``right`` cell of next row, if it exists.
 
-        * interconnection_type="column": the **bottom** cell of a column will be connected to the next column **top** cell, if it exists.
+.. option:: y_dir="<string>"
 
-        * interconnection_type="row": a row will be connected on an **above** row, if it exists.
+  Available directionalities are ``positive`` | ``negative``, specifies if the next cell to connect has a bigger or lower x value.
+  Considering a coordinate system where (0,0) is the origin at the bottom left and `x` and `y` are positives:
 
-    * y_dir="negative": 
+    - y_dir="positive": 
 
-        * interconnection_type="column": the **top** cell of a column will be connected to the next column **bottom** cell, if it exists.
+        - interconnection_type="column": the ``bottom`` cell of a column will be connected to the next column ``top`` cell, if it exists.
 
-        * interconnection_type="row": a row will be connected on a row **below**, if it exists.
+        - interconnection_type="row": a row will be connected on an ``above`` row, if it exists.
+
+    - y_dir="negative": 
+
+        - interconnection_type="column": the ``top`` cell of a column will be connected to the next column ``bottom`` cell, if it exists.
+
+        - interconnection_type="row": a row will be connected on a row ``below``, if it exists.
 
 Example
--------
+~~~~~~~
 
 For this example, we will study a scan-chain implementation. The description could be:
 
@@ -81,7 +92,7 @@ For this example, we will study a scan-chain implementation. The description cou
 In this figure, the red arrows represent the initial direct connection. The green arrows represent the point to point connection to connect all the columns of CLB.
 
 Truth table
------------
+~~~~~~~~~~~
 
 A point to point connection can be applied in different ways than showed in the example section. To help the designer implement his point to point connection, a truth table with our new parameters id provided below.
 
diff --git a/docs/source/arch_lang/generality.rst b/docs/source/arch_lang/generality.rst
index 02da8e8ab..d594ff896 100644
--- a/docs/source/arch_lang/generality.rst
+++ b/docs/source/arch_lang/generality.rst
@@ -1,8 +1,46 @@
+.. _generality:
+
 General Hierarchy
-=================
+-----------------
+
+For OpenFPGA using VPR7
+~~~~~~~~~~~~~~~~~~~~~~~
+
 The extension of the VPR architectural description language is developed as an independent branch of the original one. Most of the FPGA-SPICE descriptions are located under a XML node called <spice_settings>, which is a child node under the root node <architecture>. 
 Under the <spice_settings>, some child node is created for describing SPICE simulation settings, technology library and transistor-level modeling of circuit modules.
 In the following sub-sections, we will introduce the structures of these XML nodes and the parameters provided.
 
+For OpenFPGA using VPR8
+~~~~~~~~~~~~~~~~~~~~~~~
+
+OpenFPGA uses a separated XML file other than the VPR8 architecture description file.
+This is to keep a loose integration to VPR8 so that OpenFPGA can easily integrate any future version of VPR with least engineering effort.
+However, to implement a physical FPGA, OpenFPGA requires the original VPR XML to include full physical design details.
+Full syntax can be found in :ref:`addon_vpr_syntax`.
+
+The OpenFPGA architecture description XML file consisting of the following parts:
+
+  - ``<openfpga_architecture>`` contains architecture-level information, such as device-level description, circuit-level and architecture annotations to original VPR architecture XML. It consists of the following code blocks
+
+    - ``<circuit_library>`` includes a number of ``circuit_model``, each of which describe a primitive block in FPGA architecture, such as Look-Up Tables and multiplexers. Full syntax can be found in :ref:`circuit_library`.
+    - ``<technology_library>`` includes transistor-level parameters, where users can specify which transistor models are going to be used when building the ``circuit models``. 
+    - ``<configuration_protocol>`` includes detailed description on the configuration protocols to be used in FPGA fabric.
+    - ``<connection_block>`` includes annotation on the connection block definition ``<connection_block>`` in original VPR XML
+    - ``<switch_block>`` includes annotation on the switch block definition ``<switchlist>`` in original VPR XML
+    - ``<routing_segment>`` includes annotation on the routing segment definition ``<segmentlist>`` in original VPR XML
+    - ``<direct_connection>`` includes annotation on the inter-tile direct connection definitioin ``<directlist>`` in original VPR XML
+    - ``<pb_type_annotation>`` includes annotation on the programmable block architecture ``<complexblocklist>`` in original VPR XML
+
+  - ``<openfpga_simulation_setting>`` includes all the parameters to be used in generate testbenches in simulation purpose. Full syntax can be found in :ref:`simulation_setting`.
+
+    - ``<clock_setting>`` defines the clock-related settings in simulation, such as clock frequency and number of clock cycles to be used
+    - ``<simulator_option>`` defines universal options available in both HDL and SPICE simulators. This is mainly used by FPGA-SPICE
+    - ``<monte_carlo>`` defines critical parameters to be used in monte-carlo simulations. This is used by FPGA-SPICE
+    - ``<measurement_setting>`` defines the parameters used to measure signal slew and delays. This is used by FPGA-SPICE
+    - ``<stimulus>`` defines the parameters used to generate voltage stimuli in testbenches. This is used by FPGA-SPICE
+
+.. note:: ``<technology_library>`` will be applied to ``circuit_model`` when running FPGA-SPICE. It will not impact FPGA-Verilog, FPGA-Bitstream, FPGA-SDC.
+
+.. note:: the parameters in ``<clock_setting>`` will be applied to both FPGA-Verilog and FPGA-SPICE simulations
 
 
diff --git a/docs/source/arch_lang/index.rst b/docs/source/arch_lang/index.rst
index 86edc3886..52fd17caa 100644
--- a/docs/source/arch_lang/index.rst
+++ b/docs/source/arch_lang/index.rst
@@ -1,6 +1,3 @@
-Extended Architecture Description Language
-==========================================
-
 .. _arch_lang:
    Extended FPGA Architecture Description Language
  
@@ -9,16 +6,18 @@ Extended Architecture Description Language
 
    generality
 
-   interconnect
-   
-   spice_sim_setting
+   addon_vpr_syntax
 
-   tech_lib
+   direct_interconnect 
+   
+   simulation_setting
+
+   technology_library
   
-   circuit_modules
+   circuit_library
   
    circuit_model_examples
   
-   link_circuit_modules
+   annotate_vpr_arch
 
    
diff --git a/docs/source/arch_lang/spice_sim_setting.rst b/docs/source/arch_lang/simulation_setting.rst
similarity index 56%
rename from docs/source/arch_lang/spice_sim_setting.rst
rename to docs/source/arch_lang/simulation_setting.rst
index 3beda6e51..1b63e8c17 100644
--- a/docs/source/arch_lang/spice_sim_setting.rst
+++ b/docs/source/arch_lang/simulation_setting.rst
@@ -1,5 +1,11 @@
-Parameters for SPICE simulation settings
-========================================
+.. _simulation_setting:
+
+Simulation settings
+-------------------
+
+For OpenFPGA using VPR7
+~~~~~~~~~~~~~~~~~~~~~~~
+
 All the parameters that need to be defined in the HSPICE simulations are located under a child node called <parameters>, which is under its father node <spice_settings>. 
 The parameters are divided into three categories and can be defined in three XML nodes, <options>, <measure> and <stimulate>, respectively. 
 
@@ -130,5 +136,149 @@ Define the starting and ending point in measuring the delay between two signals
 * **input_thres_pct:** the starting point in measuring the delay of a falling edge. It is expressed as a percentage of the maximum voltage of a signal. For example, upper_thres_pct=0.5 is depicted in :numref:`fig_meas_edge`. 
     
 * **output_thres_pct:** the ending point in measuring the delay of a falling edge. It is expressed as a percentage of the maximum voltage of a signal. For example, lower_thres_pct=0. 5 is depicted in :numref:`fig_meas_edge`.
+
+
+For OpenFPGA using VPR8
+~~~~~~~~~~~~~~~~~~~~~~~
+
+All the simulation settings are stored under the XML node ``<openfpga_simulation_setting>``
+General organization is as follows
+
+.. code-block:: xml
+
+    <openfpga_simulation_setting>
+      <clock_setting>
+        <operating frequency="<int>|<string>" num_cycles="<int>|<string>" slack="<float>"/>
+        <programming frequency="<int>"/>
+      </clock_setting>
+      <simulator_option>
+        <operating_condition temperature="<int>"/>
+        <output_log verbose="<bool>" captab="<bool>"/>
+        <accuracy type="<string>" value="<float>"/>
+        <runtime fast_simulation="<bool>"/>
+      </simulator_option>
+      <monte_carlo num_simulation_points="<int>"/>
+      <measurement_setting>
+        <slew>
+          <rise upper_thres_pct="<float>" lower_thres_pct="<float>"/>
+          <fall upper_thres_pct="<float>" lower_thres_pct="<float>"/>
+        </slew>
+        <delay>
+          <rise input_thres_pct="<float>" output_thres_pct="<float>"/>
+          <fall input_thres_pct="<float>" output_thres_pct="<float>"/>
+        </delay>
+      </measurement_setting>
+      <stimulus>
+        <clock>
+          <rise slew_type="<string>" slew_time="<float>"/>
+          <fall slew_type="<string>" slew_time="<float>"/>
+        </clock>
+        <input>
+          <rise slew_type="<string>" slew_time="<float>"/>
+          <fall slew_type="<string>" slew_time="<float>"/>
+        </input>
+      </stimulus>
+    </openfpga_simulation_setting>
+
+Clock Setting
+^^^^^^^^^^^^^
+Clock setting focuses on defining the clock periods to applied on FPGA fabrics
+As a programmable device, an FPGA has two types of clocks. 
+The first is the operating clock, which is applied by users' implementations.
+The second is the programming clock, which is applied on the configuration protocol to load users' implementation to FPGA fabric.
+OpenFPGA allows users to freely define these clocks as well as the number of clock cycles.
+We should the full syntax in the code block below and then provide details on each of them.
+
+.. code-block:: xml
+
+  <clock_setting>
+    <operating frequency="<float>|<string>" num_cycles="<int>|<string>" slack="<float>"/>
+    <programming frequency="<float>"/>
+  </clock_setting>
+
+Operating clock setting
+```````````````````````
+Operating clocks are defined under the XML node ``<operating>``
+
+- ``frequency="<float|string>``
+  Specify frequency of the operating clock. OpenFPGA allows users to specify an absolute value in the unit of ``[Hz]`` 
+  Alternatively, users can bind the frequency to the maximum clock frequency analyzed by VPR STA engine.
+  This is very useful to validate the maximum operating frequency for users' implementations
+  In such case, the value of this attribute should be a reserved word ``auto``.
+
+- ``num_cycles="<int>|<string>"``
+  can be either ``auto`` or an integer. When set to ``auto``, OpenFPGA will infer the number of clock cycles from the average/median of all the signal activities.
+  When set to an integer, OpenFPGA will use the given number of clock cycles in HDL and SPICE simulations.
+
+- ``slack="<float>"``
+  add a margin to the critical path delay in the HDL and SPICE simulations.
+  This parameter is applied to the critical path delay provided by VPR STA engine.
+  So it is only valid when option ``frequency`` is set to ``auto``.
+  This aims to compensate any inaccuracy in STA results.
+  Typically, the slack value is between ``0`` and ``1``. 
+  For example, ``slack=0.2`` implies that the actual clock period in simulations is 120% of the critical path delay reported by VPR. 
+
+.. note:: Only valid when option ``frequency`` is set to ``auto``
+
+.. warning:: Avoid to use a negative slack! This may cause your simulation to fail!
+
+Programming clock setting
+`````````````````````````
+Programming clocks are defined under the XML node ``<programming>``
+
+- ``frequency="<float>"``
+  Specify the frequency of the programming clock using an absolute value in the unit of ``[Hz]`` 
+  This frequency is used in testbenches for programming phase simulation.
+
+.. note:: Programming clock frequency is typically much slower than the operating clock and strongly depends on the process technology. Suggest to characterize the speed of your configuration protocols before specifying a value!
+
+Simulator Option
+^^^^^^^^^^^^^^^^
+This XML node includes universal options available in both HDL and SPICE simulators.
+
+.. note:: This is mainly used by FPGA-SPICE
+
+``<operating_condition temperature="<int>"/>``
+  Specify the temperature which will be defined in SPICE netlists. In the top SPICE netlists, it will show as 
+
+.. code-block:: python
+
+    .temp <int>
+
+``<output_log verbose="<bool>" captab="<bool>"/>``
+  Specify the options in outputting simulation results to log files
+
+- ``verbose="true|false"``
+
+  Specify if the simulation waveforms should be printed out after SPICE simulations. If turned on, it will show in all the SPICE netlists
+
+.. code-block:: python
+  
+  .option POST
+
+.. note:: when the SPICE netlists are large or a long simulation duration is defined, the post option is recommended to be off. If not, huge disk space will be occupied by the waveform files.
+
+- ``captab="true|false"``
+  Specify if the capacitances of all the nodes in the SPICE netlists will be printed out. If turned on, it will show inn the top-level SPICE netlists
+
+.. code-block:: python
+
+  .option CAPTAB 
+
+.. note:: When turned on, the SPICE simulation runtime may increase.
+
+``<accuracy type="<string>" value="<float>"/>``
+  Specify the simulation steps (accuracy) to be used
+
+- ``type="abs|frac"``
+
+  Specify the type of transient step in SPICE simulation. 
+
+    * When ``abs`` is selected, the accuracy should be the absolute value, such as ``1e-12``. 
+
+    * When ``frac`` is selected, the accuracy is the number of simulation points in a clock cycle period, for example, 100.
     
+- ``value="<float>"``
+
+  Specify the transient step in SPICE simulation. Typically, the smaller the step is, the higher the accuracy that can be reached while the long simulation runtime is. The recommended accuracy is between 0.1ps and 0.01ps, which generates good accuracy and runtime is not significantly long. 
     
diff --git a/docs/source/arch_lang/tech_lib.rst b/docs/source/arch_lang/technology_library.rst
similarity index 96%
rename from docs/source/arch_lang/tech_lib.rst
rename to docs/source/arch_lang/technology_library.rst
index 264d1bc1a..7ec621f55 100644
--- a/docs/source/arch_lang/tech_lib.rst
+++ b/docs/source/arch_lang/technology_library.rst
@@ -1,5 +1,7 @@
-Technology library Declaration
-==============================
+.. _technology_library_syntax:
+
+Technology library
+------------------
 
 .. code-block:: xml
 
diff --git a/docs/source/contact.rst b/docs/source/contact.rst
index 469defe1a..1e7e1e801 100644
--- a/docs/source/contact.rst
+++ b/docs/source/contact.rst
@@ -1,7 +1,7 @@
 .. _contact:
 
 Contact
-=======
+~~~~~~~
    
 General questions:
 
diff --git a/docs/source/fpga_bitstream/index.rst b/docs/source/fpga_bitstream/index.rst
index 44a1e0312..6380cc322 100644
--- a/docs/source/fpga_bitstream/index.rst
+++ b/docs/source/fpga_bitstream/index.rst
@@ -1,8 +1,5 @@
-FPGA-Bitstream
-==============
-
 .. _fpga_bitstream:
-   User Manual for FPGA Bitstream Generator
+   FPGA-Bitstream
  
 .. toctree::
    :maxdepth: 2
diff --git a/docs/source/fpga_spice/index.rst b/docs/source/fpga_spice/index.rst
index c147f8e90..c9c04568a 100644
--- a/docs/source/fpga_spice/index.rst
+++ b/docs/source/fpga_spice/index.rst
@@ -1,8 +1,5 @@
-FPGA-SPICE: SPICE Auto-Generation
-====================================
-
 .. _fpga_spice:
-   User Manual for FPGA-SPICE support
+   FPGA-SPICE
  
 .. toctree::
   
diff --git a/docs/source/fpga_verilog/index.rst b/docs/source/fpga_verilog/index.rst
index b5ef00c9f..2ea55c478 100644
--- a/docs/source/fpga_verilog/index.rst
+++ b/docs/source/fpga_verilog/index.rst
@@ -1,8 +1,5 @@
-FPGA-Verilog: Verilog Auto-Generation
--------------------------------------
-
 .. _fpga_verilog:
-   User Manual for FPGA Verilog Generator 
+   FPGA-Verilog
  
 .. toctree::
    :maxdepth: 2
diff --git a/docs/source/index.rst b/docs/source/index.rst
index 9f4dd36d8..34beae468 100644
--- a/docs/source/index.rst
+++ b/docs/source/index.rst
@@ -19,10 +19,14 @@ Welcome to OpenFPGA's documentation!
 
 .. toctree::
    :maxdepth: 2
-   :caption: Tools Guide
+   :caption: Architecture Description Language
 
    arch_lang/index
 
+.. toctree::
+   :maxdepth: 2
+   :caption: OpenFPGA Tools
+
    fpga_spice/index
 
    fpga_verilog/index
diff --git a/docs/source/motivation.rst b/docs/source/motivation.rst
index 2dd4447df..01ae7da54 100644
--- a/docs/source/motivation.rst
+++ b/docs/source/motivation.rst
@@ -1,5 +1,5 @@
-Motivation
-==========
+Why OpenFPGA?
+-------------
 
 OpenFPGA aims to be an open-source framework that enables rapid prototyping of customizable FPGA architectures. As shown in :numref:`fig_openfpga_motivation`, a conventional approach will take a large group of experienced engineers more than one year to achieve production-ready layout and assoicated CAD tools. In fact, most of the engineering efforts are spent on manual layouts and developing ad-hoc CAD support.
 
@@ -29,7 +29,7 @@ The rest of this section will focus on detailed motivation on each of them, as d
 
 
 FPGA-Verilog
-------------
+~~~~~~~~~~~~
 
 Driven by the strong need in data processing applications, Field Programmable Gate Arrays (FPGAs) are playing an ever-increasing role as programmable accelerators in modern
 computing systems. To fully unlock processing capabilities for domain-specific applications, FPGA architectures have to be tailored for seamless cooperation with other computing resources. However, prototyping and bringing to production a customized FPGA is a costly and complex endeavor even for industrial vendors. OpenFPGA, an opensource framework, aims to rapid prototype of customizable FPGA architectures through a semi-custom design approach. We propose an XML-to-Prototype design flow, where the Verilog netlists of a full FPGA fabric can be autogenerated using an extension of the XML language from the VTR framework and then fed into a back-end flow to generate production-ready layouts. 
@@ -37,7 +37,7 @@ computing systems. To fully unlock processing capabilities for domain-specific a
 The technical details can be found in our TVLSI'19 paper :cite:`XTang_TVLSI_2019` and FPL'19 paper :cite:`XTang_FPL_2019`.
 
 FPGA-SDC
---------
+~~~~~~~~
 
 Design constraints are indepensible in modern ASIC design flows to guarantee the performance level.
 OpenFPGA includes a rich SDC generator in the OpenFPGA framework to deal with both PnR constraints and sign-off timing analysis.
@@ -47,7 +47,7 @@ The technical details can be found in our FPL'19 paper :cite:`XTang_FPL_2019`.
 
 
 FPGA-Bitstream
---------------
+~~~~~~~~~~~~~~
 
 EDA support is essential for end-users to implement designs on a customized FPGA. OpenFPGA provides a general-purpose bitstream generator FPGA-Bitstream for any architecture that can be described by VPR. As the native CAD tool for any customized FPGA that is produced by FPGA-Verilog, FPGA-Bitstream is ready to use once users finalize the XML-based architecture description file. This eliminates the huge engineering efforts spent on developing bitstream generator for customized FPGAs.
 
@@ -56,7 +56,7 @@ Using FPGA-Bitstream, users can launch (1) Verilog-to-Bitstream flow. This is th
 The technical details can be found in our TVLSI'19 paper :cite:`XTang_TVLSI_2019` and FPL'19 paper :cite:`XTang_FPL_2019`.
 
 FPGA-SPICE
-----------
+~~~~~~~~~~
 
 The built-in timing and power analysis engines of VPR are based on analytical models :cite:`VBetz_Book_1999,JGoeders_FPT_2012`. Analytical model-based analysis can promise accuracy only on a limited number of circuit designs for which the model is valid. As the technology advancements create more opportunities on circuit designs and FPGA architectures, the analytical power model require to be updated to follow the new trends. However, without referring to simulation results, the analytical power models cannot prove their accuracy. SPICE simulators have the advantages of generality and accuracy over analytical models. For this reason, SPICE simulation results are often selected to check the accuracy of analytical models. Therefore, there is a strong need for a simulation-based power analysis approach for FPGAs, which can support general circuit designs.
 
diff --git a/docs/source/tutorials/compile.rst b/docs/source/tutorials/compile.rst
index cfa4dbe44..6844740d2 100644
--- a/docs/source/tutorials/compile.rst
+++ b/docs/source/tutorials/compile.rst
@@ -1,8 +1,10 @@
-How to Compile
-==============
+.. _compile:
 
-General Compilation Guidelines
-------------------------------
+How to Compile
+--------------
+
+General Guidelines
+~~~~~~~~~~~~~~~~~~
 OpenFPGA uses CMake to generate the Makefile scripts
 In general, please follow the steps to compile
 
@@ -29,7 +31,7 @@ To quickly verify the tool is well compiled, user can run the following command
   python3 openfpga_flow/scripts/run_fpga_task.py compilation_verification --debug --show_thread_logs
 
 Dependencies
-------------
+~~~~~~~~~~~~
 Full list of dependencies can be found at travis_setup_link_
 In particular, OpenFPGA requires specific versions for the following dependencies:
 
@@ -42,7 +44,7 @@ In particular, OpenFPGA requires specific versions for the following dependencie
 .. _travis_setup_link: https://github.com/LNIS-Projects/OpenFPGA/blob/0cfb88a49f152aab0a06f309ff160f222bb51ed7/.travis.yml#L34
 
 Docker
-------
+~~~~~~
 If some of these dependencies are not installed on your machine, you can choose to use a Docker (the Docker tool needs to be installed).
 For the ease of the customer first experience, a Dockerfile is provided in the OpenFPGA folder. A container ready to use can be created with the following command
 
diff --git a/docs/source/tutorials/eda_flow.rst b/docs/source/tutorials/eda_flow.rst
index 446098d60..31cffa0ca 100644
--- a/docs/source/tutorials/eda_flow.rst
+++ b/docs/source/tutorials/eda_flow.rst
@@ -1,5 +1,7 @@
-EDA flow
-========
+.. _eda_flow:
+
+Supported EDA flows in OpenFPGA
+-------------------------------
 
 As illustrated in :numref:`fig_eda_flow`, FPGA-SPICE creates a modified VTR flow. All the input files for VPR do not need modifications except the architecture description XML. As simulation-based power analysis requires the transistor-level netlists, we extend the architecture description language to support transistor-level modeling (See details in "Tools Guide>Extended Architecture Description Language"). FPGA-SPICE, embedded in VPR, outputs the SPICE netlists and testbenches according to placement and routing results when enabled by command-line options. (See each "FPGA-*Branch*" about command-line options available) Besides automatically generating all the SPICE netlists, FPGA-SPICE supports user-defined SPICE netlists for modules. We believe the support on user-defined SPICE netlists allows FPGA-SPICE to be general enough to support novel circuit designs and even technologies. (See "FPGA-SPICE... > Create Customized SPICE Modules" for guidelines in customizing your FPGA-SPICE compatible SPICE netlists.) With the dumped SPICE netlists and testbenches, a SPICE simulator, i.e., HSPICE, can be called to conduct a power analysis. FPGA-SPICE automatically generates a shell script, which brings convenience for users to run all the simulations (See "FPGA-SPICE... > Run SPICE simulation").
 

From cb7e4a1dfa1c78ec8550d70742e8e7fb7fcc9358 Mon Sep 17 00:00:00 2001
From: Xifan Tang <tangxifan@gmail.com>
Date: Mon, 9 Mar 2020 20:03:37 -0600
Subject: [PATCH 284/645] finish documentation the simulation settings in VPR8
 integration

---
 docs/source/arch_lang/simulation_setting.rst | 98 +++++++++++++++++++-
 docs/source/arch_lang/technology_library.rst |  2 +-
 2 files changed, 95 insertions(+), 5 deletions(-)

diff --git a/docs/source/arch_lang/simulation_setting.rst b/docs/source/arch_lang/simulation_setting.rst
index 1b63e8c17..c6d9c1545 100644
--- a/docs/source/arch_lang/simulation_setting.rst
+++ b/docs/source/arch_lang/simulation_setting.rst
@@ -200,6 +200,8 @@ Operating clock setting
 ```````````````````````
 Operating clocks are defined under the XML node ``<operating>``
 
+.. option:: <operating frequency="<float>|<string>" num_cycles="<int>|<string>" slack="<float>"/>
+
 - ``frequency="<float|string>``
   Specify frequency of the operating clock. OpenFPGA allows users to specify an absolute value in the unit of ``[Hz]`` 
   Alternatively, users can bind the frequency to the maximum clock frequency analyzed by VPR STA engine.
@@ -226,6 +228,8 @@ Programming clock setting
 `````````````````````````
 Programming clocks are defined under the XML node ``<programming>``
 
+.. option:: <programming frequency="<float>"/>
+
 - ``frequency="<float>"``
   Specify the frequency of the programming clock using an absolute value in the unit of ``[Hz]`` 
   This frequency is used in testbenches for programming phase simulation.
@@ -238,14 +242,23 @@ This XML node includes universal options available in both HDL and SPICE simulat
 
 .. note:: This is mainly used by FPGA-SPICE
 
-``<operating_condition temperature="<int>"/>``
+Operating condition
+```````````````````
+
+.. option:: <operating_condition temperature="<int>"/>``
+
+- ``temperature="<int>"``
   Specify the temperature which will be defined in SPICE netlists. In the top SPICE netlists, it will show as 
 
 .. code-block:: python
 
     .temp <int>
 
-``<output_log verbose="<bool>" captab="<bool>"/>``
+Output logs
+```````````
+
+.. option:: <output_log verbose="<bool>" captab="<bool>"/>``
+
   Specify the options in outputting simulation results to log files
 
 - ``verbose="true|false"``
@@ -259,7 +272,7 @@ This XML node includes universal options available in both HDL and SPICE simulat
 .. note:: when the SPICE netlists are large or a long simulation duration is defined, the post option is recommended to be off. If not, huge disk space will be occupied by the waveform files.
 
 - ``captab="true|false"``
-  Specify if the capacitances of all the nodes in the SPICE netlists will be printed out. If turned on, it will show inn the top-level SPICE netlists
+  Specify if the capacitances of all the nodes in the SPICE netlists will be printed out. If turned on, it will show in the top-level SPICE netlists
 
 .. code-block:: python
 
@@ -267,7 +280,11 @@ This XML node includes universal options available in both HDL and SPICE simulat
 
 .. note:: When turned on, the SPICE simulation runtime may increase.
 
-``<accuracy type="<string>" value="<float>"/>``
+Simulation Accuracy
+```````````````````
+
+.. option:: <accuracy type="<string>" value="<float>"/>``
+
   Specify the simulation steps (accuracy) to be used
 
 - ``type="abs|frac"``
@@ -281,4 +298,77 @@ This XML node includes universal options available in both HDL and SPICE simulat
 - ``value="<float>"``
 
   Specify the transient step in SPICE simulation. Typically, the smaller the step is, the higher the accuracy that can be reached while the long simulation runtime is. The recommended accuracy is between 0.1ps and 0.01ps, which generates good accuracy and runtime is not significantly long. 
+
+Simulation Speed
+````````````````
     
+.. option:: <runtime fast_simulation="<bool>"/>
+
+  Specify if any runtime optimization will be applied to the simulator.  
+
+- ``fast_simulation="true|false"``
+
+  Specify if fast simulation is turned on for the simulator.  
+
+   If turned on, it will show in the top-level SPICE netlists
+
+.. code-block:: python
+
+  .option fast 
+
+Monte Carlo Simulation
+``````````````````````
+
+.. option:: <monte_carlo num_simulation_points="<int>"/>
+   
+   Run SPICE simulations in monte carlo mode.
+   This is mainly for FPGA-SPICE
+   When turned on, FPGA-SPICE will apply the device variation defined in :ref:`technology_library` to monte carlo simulation
+
+- ``num_simulation_points="<int>"``
+
+  Specify the number of simulation points to be considered in monte carlo.
+  The larger the number is, the longer simulation time will be but more accurate the results will be.
+
+Measurement Setting
+```````````````````
+- Users can define the parameters in measuring the slew of signals, under XML node ``<slew>``
+
+- Users can define the parameters in measuring the delay of signals, under XML node ``<delay>``
+
+Both delay and slew measurement share the same syntax in defining the upper and lower voltage thresholds.
+
+.. option:: <rise|fall upper_thres_pct="<float>" lower_thres_pct="<float>"/>
+
+  Define the starting and ending point in measuring the slew of a rising or a falling edge of a signal.
+    
+  - ``upper_thres_pct="<float>"`` the ending point in measuring the slew of a rising edge. It is expressed as a percentage of the maximum voltage of a signal. For example, the meaning of upper_thres_pct=0.95 is depicted in :numref:`fig_measure_edge`. 
+    
+  - ``lower_thres_pct="<float>"`` the starting point in measuring the slew of a rising edge. It is expressed as a percentage of the maximum voltage of a signal. For example, the meaning of lower_thres_pct=0.05 is depicted in :numref:`fig_measure_edge`.
+
+.. _fig_measure_edge:
+
+.. figure:: figures/meas_edge.png 
+   :scale: 80%
+   :alt: map to buried traesure
+  
+   An illustrative example on measuring the slew and delay of signals
+
+Stimulus Setting
+````````````````
+Users can define the slew time of input and clock signals to be applied to FPGA I/Os in testbenches under XML node ``<clock>`` and ``<input>`` respectively.
+This is used by FPGA-SPICE in generating testbenches
+
+.. option:: <rise|fall slew_type="<string>" slew_time="<float>"/>
+
+  Specify the slew rate of an input or clock signal at rising or falling edge 
+
+  - ``slew_type="[abs|frac]"`` specify the type of slew time definition at the rising or falling edge of a lock/input port.
+
+    * The type of ``abs`` implies that the slew time is the absolute value. For example, ``slew_type="abs" slew_time="20e-12"`` means that the slew of a clock signal is 20ps. 
+    * The type of ``frac`` means that the slew time is related to the period (frequency) of the clock signal. For example, ``slew_type="frac" slew_time="0.05"`` means that the slew of a clock signal takes 5% of the period of the clock.
+
+  - ``slew_time="<float>"`` specify the slew rate of an input or clock signal at the rising/falling edge. 
+ 
+  :numref:`fig_measure_edge` depicts the definition of the slew and delays of signals and the parameters that can be supported by FPGA-SPICE.
+
diff --git a/docs/source/arch_lang/technology_library.rst b/docs/source/arch_lang/technology_library.rst
index 7ec621f55..180c45de5 100644
--- a/docs/source/arch_lang/technology_library.rst
+++ b/docs/source/arch_lang/technology_library.rst
@@ -1,4 +1,4 @@
-.. _technology_library_syntax:
+.. _technology_library:
 
 Technology library
 ------------------

From d14fa16905996e501dffa394dfe458b10e39323b Mon Sep 17 00:00:00 2001
From: Xifan Tang <tangxifan@gmail.com>
Date: Mon, 9 Mar 2020 21:17:25 -0600
Subject: [PATCH 285/645] finish documentation update on technology library

---
 docs/source/arch_lang/technology_library.rst | 109 +++++++++++++++++++
 1 file changed, 109 insertions(+)

diff --git a/docs/source/arch_lang/technology_library.rst b/docs/source/arch_lang/technology_library.rst
index 180c45de5..1b1598cce 100644
--- a/docs/source/arch_lang/technology_library.rst
+++ b/docs/source/arch_lang/technology_library.rst
@@ -3,6 +3,9 @@
 Technology library
 ------------------
 
+For OpenFPGA using VPR7
+~~~~~~~~~~~~~~~~~~~~~~~
+
 .. code-block:: xml
 
   <tech_lib lib_type=�string� transistor_type=�string� lib_path=�string� nominal_vdd=�float�/>
@@ -34,3 +37,109 @@ Technology library
   
 * **min_width:** specify the minimum width of p/n type transistor. This parameter will be used in building inverter, buffer, etc. as a base number for transistor sizing. 
   
+For OpenFPGA using VPR8
+~~~~~~~~~~~~~~~~~~~~~~~
+
+Technology library aims to describe transistor-level parameters to be applied to the physical design of FPGAs. In addition to transistor models, technology library also supports the definition of process variations on any transistor models. 
+General organization is as follows.
+
+.. code-block:: xml
+
+  <technology_library>
+    <device_library>
+      <device_model name="<string>" type="<string>">
+        <lib type="<string>" corner="<string>" ref="<string>" path="<string>"/>
+        <design vdd="<float>" pn_ratio="<float>"/>
+        <pmos name="<string>" chan_length="<float>" min_width="<float>" variation="<string>"/>
+        <nmos name="<string>" chan_length="<float>" min_width="<float>" variation="<string>"/>
+        <rram rlrs="<float>" rhrs="<float>" variation="<string>"/> 
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="<string>" abs_deviation="<float>" num_sigma="<int>"/>
+    </variation_library>
+  </technology_library>
+
+Device Library
+^^^^^^^^^^^^^^
+Device library contains detailed description on device models, such as transistors and Resistive Random Access Memories (RRAMs).
+A device library may consist of a number of ``<device_model>`` and each of them denotes a different transistor model.
+
+A device model represents a transistor/RRAM model available in users' technology library.
+
+.. option:: <device_model name="<string>" type="<string>">
+  
+  Specify the name and type of a device model
+  
+  - ``name="<string>"`` is the unique name of the device model in the context of ``<device_library>``. 
+  - ``type="transistor|rram"`` is the type of device model in terms of functionality
+    Currently, OpenFPGA supports two types: transistor and RRAM.
+
+.. note:: the name of ``<device_model>`` may not be the name in users' technology library.
+
+.. option:: <lib type="<string>" corner="<string>" ref="<string>" path="<string>"/>
+  Specify the technology library that defines the device model
+
+  - ``type="academia|industry"``  For the industry library, FPGA-SPICE will use ``.lib <lib_file_path>`` to include the library file in SPICE netlists. For academia library, FPGA-SPICE will use ``.include <lib_file_path>`` to include the library file in SPICE netlists
+
+  - ``corner="<string>"`` is the process corner name available in technology library. 
+    For example, the type of transistors can be ``TT``, ``SS`` and ``FF`` *etc*.
+
+  - ``ref="<string>"`` specify the reference of in calling a transistor model. In SPICE netlists, define a transistor follows the convention: 
+
+  .. code-block:: xml
+
+    <model_ref><trans_name> <ports> <model_name>
+
+  The reference depends on the technology and the type of library. For example, the PTM bulk model uses “M� as the reference while the PTM FinFET model uses “X� as the reference.
+
+  - ``path="<string>"`` specify the path of the technology library file. For example: 
+
+  .. code-block:: xml 
+
+    lib_path=/home/tech/45nm.pm.
+
+.. option:: <design vdd="<float>" pn_ratio="<float>"/>
+
+   Specify transistor-level design parameters
+
+   - ``vdd="<float>"`` specify the working voltage for the technology. The voltage will be used as the supply voltage in all the SPICE netlists.
+ 
+   - ``pn_ratio="<float>"`` specify the ratio between *p*-type and *n*-type transistors. The ratio will be used when building circuit structures such as inverters, buffers, etc.
+
+.. option:: <pmos|nmos name="<string>" chan_length="<float>" min_width="<float>" variation="<string>"/>
+  
+  Specify device-level parameters for transistors
+
+  - ``name="<string>"`` specify the name of the p/n type transistor, which can be found in the manual of the technology provider.
+
+  - ``chan_length="<float>"`` specify the channel length of *p/n* type transistor.
+  
+  - ``min_width="<float>"`` specify the minimum width of *p/n* type transistor. This parameter will be used in building inverter, buffer, *etc*. as a base number for transistor sizing. 
+
+  - ``variation="<string>"`` specify the variation name defined in the ``<variation_library>`` 
+
+.. option:: <rram rlrs="<float>" rhrs="<float>" variation="<string>"/> 
+
+  Specify device-level parameters for RRAMs
+
+  - ``rlrs="<float>"`` specify the resistance of Low Resistance State (LRS) of a RRAM device
+
+  - ``rhrs="<float>"`` specify the resistance of High Resistance State (HRS) of a RRAM device 
+
+  - ``variation="<string>"`` specify the variation name defined in the ``<variation_library>`` 
+
+Variation Library
+^^^^^^^^^^^^^^^^^
+Variation library contains detailed description on device variations specified by users.
+A variation library may consist of a number of ``<variation>`` and each of them denotes a different variation parameter.
+
+.. option:: <variation name="<string>" abs_deviation="<float>" num_sigma="<int>"/>
+  
+  Specify detail variation parameters
+
+  - ``name="<string>"`` is the unique name of the device variation in the context of ``<variation_library>``.  The name will be used in ``<device_model>`` to bind variations
+  
+  - ``abs_variation="<float>"`` is the absolute deviation of a variation
+
+  - ``num_sigma="<int>"`` is the standard deviation of a variation

From 2a3c5b98a52d64e5e58cf9732e8149090c0629da Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 9 Mar 2020 21:25:13 -0600
Subject: [PATCH 286/645] minor format fix in documentation

---
 docs/source/arch_lang/technology_library.rst | 1 +
 1 file changed, 1 insertion(+)

diff --git a/docs/source/arch_lang/technology_library.rst b/docs/source/arch_lang/technology_library.rst
index 1b1598cce..5089f9f2e 100644
--- a/docs/source/arch_lang/technology_library.rst
+++ b/docs/source/arch_lang/technology_library.rst
@@ -78,6 +78,7 @@ A device model represents a transistor/RRAM model available in users' technology
 .. note:: the name of ``<device_model>`` may not be the name in users' technology library.
 
 .. option:: <lib type="<string>" corner="<string>" ref="<string>" path="<string>"/>
+
   Specify the technology library that defines the device model
 
   - ``type="academia|industry"``  For the industry library, FPGA-SPICE will use ``.lib <lib_file_path>`` to include the library file in SPICE netlists. For academia library, FPGA-SPICE will use ``.include <lib_file_path>`` to include the library file in SPICE netlists

From 54dfdc0cc1a4d28955916befa1294c6b2499cba6 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 10 Mar 2020 12:18:12 -0600
Subject: [PATCH 287/645] update general documentation on circuit library

---
 docs/source/arch_lang/circuit_library.rst    | 183 ++++++++++++++++++-
 docs/source/arch_lang/simulation_setting.rst |   1 -
 2 files changed, 176 insertions(+), 8 deletions(-)

diff --git a/docs/source/arch_lang/circuit_library.rst b/docs/source/arch_lang/circuit_library.rst
index 138544bb2..04f0039b4 100644
--- a/docs/source/arch_lang/circuit_library.rst
+++ b/docs/source/arch_lang/circuit_library.rst
@@ -3,13 +3,16 @@
 Circuit Library
 ---------------
 
+For OpenFPGA using VPR7
+~~~~~~~~~~~~~~~~~~~~~~~
+
 To support FPGA Verilog/SPICE, Verily and Bitstream Generator, physical modules containing gate-level and transistor-level features are required for FPGA primitive blocks.
 The physical modules are defined in XML syntax, similar to the original VPR FPGA architecture description language.
 
 For each module that appears in the FPGA architecture, a circuit model should be defined. In the definition of a circuit model, the user can specify if the Verilog/SPICE netlist of the module is either auto-generated or user-defined.
 
 Circuit Model Attributes
-~~~~~~~~~~~~~~~~~~~~~~~~
+^^^^^^^^^^^^^^^^^^^^^^^^
 
 .. code-block:: xml
 
@@ -46,7 +49,7 @@ Circuit Model Attributes
 
 
 Design Technology-related Attributes
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 .. code-block:: xml
 
@@ -68,12 +71,8 @@ Design Technology-related Attributes
 .. note:: Currently, the RRAM-based designs are only supported for multiplexers.
 
 
-Input/Output Buffer
-~~~~~~~~~~~~~~~~~~~
-
 Circuit Port Attributes
-~~~~~~~~~~~~~~~~~~~~~~~
-
+^^^^^^^^^^^^^^^^^^^^^^^
 
 * input_buffer and output_buffer:
     
@@ -112,3 +111,173 @@ Circuit Port Attributes
 .. note::  Different types of ``circuit_model`` have different XML syntax, with which users can highly customize their circuit topologies. See refer to examples of ``circuit_model`` for more details.
 
 .. note:: Note that we have a list of reserved port names, which indicate the usage of these ports when building FPGA fabrics. Please do not use ``mem_out``, ``mem_inv``, ``bl``, ``wl``, ``blb``, ``wlb``, ``ccff_head`` and ``ccff_tail``.
+
+For OpenFPGA using VPR8
+~~~~~~~~~~~~~~~~~~~~~~~
+
+Circuit design is a dominant factor in Power, Performance, Area (P.P.A.) of FPGA fabrics.
+Upon practical applications, the hardware engineers may select various circuits to implement their FPGA fabrics.
+For instance, a ultra-low-power FPGA may be built with ulta-low-power circuit cells while a high-performance FPGA may use absolutely different circuit cells.
+OpenFPGA provide enriched XML syntax for users to highly customize their circuits in FPGA fabric.
+
+In the XML file, users can define a library of circuits, each of which corresponds to a primitive module required in the FPGA architecture.
+Users can specify if the Verilog/SPICE netlist of the module is either auto-generated by OpenFPGA or provided by themselves.
+As such, OpenFPGA can support any circuit design, leading to high flexibility in building FPGA fabrics.
+
+In principle, a circuit library consists of a number of ``<circuit_model>``, each of which correspond to a circuit design.
+OpenFPGA supports a wide range of circuit designs.
+The ``<circuit_model>`` could be as small as a cornerstone cell, such as inverter, buffer *etc*., or as large as a hardware IP, such as Block RAM.
+
+.. code-block:: xml
+
+  <circuit_library>
+    <circuit_model type="<string>" name="<string>">
+      <!-- Detailed circuit-level design parameters -->
+    </circuit_model>
+    <!-- More circuit models -->
+  </circuit_library>
+
+Currently, OpenFPGA supports the following categories of circuits:
+
+  - inverters/buffers
+  - pass-gate logic, including transmission gates and pass transistors
+  - standard cell logic gates, including AND, OR and MUX2
+  - metal wires
+  - multiplexers
+  - flip-flops
+  - Look-Up Tables, including single-output and multi-output fracturable LUTs
+  - Statis Random Access Memory (SRAM)
+  - scan-chain flip-flops
+  - I/O pad
+  - hardware IPs 
+
+Circuit Model
+^^^^^^^^^^^^^
+
+As OpenFPGA supports many types of circuit models and their circuit-level implementation could be really different, each type of circuit model has special syntax to customize their designs.
+However, most circuit models share the common generality in XML language.
+Here, we focus these common syntax and we will detail special syntax in :ref:`circuit_model_examples`
+
+.. code-block:: xml
+
+  <circuit_model type="<string>" name="<string>" prefix="<string>" is_default="<bool>" spice_netlist="<string>" verilog_netlist="<string>" dump_structural_verilog="<bool>">
+    <design_technology type="<string>"/>
+    <input_buffer exist="<string>" circuit_model_name="<string>"/>
+    <output_buffer exist="<string>" circuit_model_name="<string>"/>
+    <pass_gate_logic type="<string>" circuit_model_name="<string>"/>
+    <port type="<string>" prefix="<string>" lib_name="<string>" size="<int>" default_val="<int>" circuit_model_name="<string>" mode_select="<bool>" is_global="<bool>" is_set="<bool>" is_reset="<bool>" is_config_enable="<bool>"/>
+    <!-- more ports -->
+  </circuit_model>
+
+.. option:: <circuit_model type="<string>" name="<string>" prefix="<string>" is_default="<bool>"
+  spice_netlist="<string>" verilog_netlist="<string>" dump_structural_verilog="<bool>">
+  
+  Specify the general attributes for a circuit model
+
+  - ``type="inv_buf|pass_gate|gate|mux|wire|chan_wire|sram|lut|ff|ccff|hard_logic|iopad"`` Specify the type of circuit model. For the circuit models in the type of mux/wire/chan_wire/lut, FPGA-Verilog/SPICE can auto-generate Verilog/SPICE netlists. For the rest, FPGA-Verilog/SPICE requires a user-defined Verilog/SPICE netlist.
+
+  - ``name="<string>"`` Specify the name of this circuit model. The name should be unique and will be used to create the Verilog/SPICE module in Verilog/SPICE netlists. Note that for a customized Verilog/SPICE netlist, the name defined here MUST be the name in the customized Verilog/SPICE netlist. FPGA-Verilog/SPICE will check if the given name is conflicted with any reserved words.
+
+  - ``prefix="<string>"`` Specify the name of the ``<circuit_model>`` to shown in the auto-generated Verilog/SPICE netlists. The prefix can be the same as the name defined above. And again, the prefix should be unique
+
+  - ``is_default="true|false"``  Specify this circuit model is the default one for those in the same types. If a primitive module in VPR architecture is not linked to any circuit model by users, FPGA-Verilog/SPICE will find the default circuit model defined in the same type.
+
+  - ``spice_netlist="<string>"`` Specify the path and file name of a customized SPICE netlist. For some modules such as SRAMs, FFs, I/O pads, FPGA-SPICE does not support auto-generation of the transistor-level sub-circuits because their circuit design is highly dependent on the technology nodes. These circuit designs should be specified by users. For the other modules that can be auto-generated by FPGA-SPICE, the user can also define a custom netlist.
+
+  - ``verilog_netlist="<string>"`` Specify the path and file name of a customized Verilog netlist. For some modules such as SRAMs, FFs, I/O pads, FPGA-Verilog does not support auto-generation of the transistor-level sub-circuits because their circuit design is highly dependent on the technology nodes. These circuit designs should be specified by users. For the other modules that can be auto-generated by FPGA-Verilog, the user can also define a custom netlist.
+
+  - ``dump_structural_verilog="true|false"`` When the value of this keyword is set to be true, Verilog generator will output gate-level netlists of this module, instead of behavior-level. Gate-level netlists bring more opportunities in layout-level optimization while behavior-level is more suitable for high-speed formal verification and easier in debugging with HDL simulators.
+
+.. warning:: ``prefix`` may be deprecated soon
+
+.. note:: Multiplexers cannot be user-defined.
+
+.. note:: For a circuit model type, only one circuit model can be set as default.
+
+.. note:: If ``<spice_netlist>`` or ``<verilog_netlist>`` are not specified, FPGA-Verilog/SPICE auto-generates the Verilog/SPICE netlists for multiplexers, wires, and LUTs.
+
+.. note:: The user-defined netlists, such as LUTs, the decoding methodology should comply with the auto-generated LUTs!!!
+
+Design Technology
+^^^^^^^^^^^^^^^^^
+
+.. option:: <design_technology type="string"/>
+
+  Specify the design technology applied to a ``<circuit_model>``
+
+    - ``type="cmos|rram"`` Specify the type of design technology of the ``<circuit_model>``. Currently, OpenFPGA supports CMOS and RRAM technology for circuit models.
+      CMOS technology can be applied to any types of ``<circuit_model>``, while RRAM technology is only applicable to multiplexers and SRAMs 
+
+.. note:: Each ``<circuit_model>`` may have different technologies
+
+Input and Output Buffers
+^^^^^^^^^^^^^^^^^^^^^^^^
+
+.. option:: <input_buffer exist="<string>" circuit_model_name="<string>"/>
+
+  - ``exist="true|false"`` Define the existence of the input buffer. Note that the existence is valid for all the inputs.
+
+  - ``circuit_model_name="<string>"`` Specify the name of circuit model which is used to implement input buffer, the type of specified circuit model should be ``inv_buf``.
+
+.. option:: <output_buffer exist="<string>" circuit_model_name="<string>"/>
+
+  - ``exist="true|false"`` Define the existence of the output buffer. Note that the existence is valid for all the outputs. Note that if users want only part of the inputs (or outputs) to be buffered, this is not supported here. A solution can be building a user-defined Verilog/SPICE netlist.
+
+  - ``circuit_model_name="<string>"`` Specify the name of circuit model which is used to implement the output buffer, the type of specified circuit model should be ``inv_buf``.
+
+.. note:: If users want only part of the inputs (or outputs) to be buffered, this is not supported here. A solution can be building a user-defined Verilog/SPICE netlist.
+
+Pass Gate Logic
+^^^^^^^^^^^^^^^
+
+.. option:: <pass_gate_logic circuit_model_name="<string>"/>
+
+  - ``circuit_model_name="<string>"`` Specify the name of the circuit model which is used to implement pass-gate logic, the type of specified circuit model should be ``pass_gate``.
+
+.. note:: pass-gate logic are used in building multiplexers and LUTs.
+
+
+Circuit Port
+^^^^^^^^^^^^
+
+A circuit model may consist of a number of ports. The port list is mandatory in any ``circuit_model`` and must be consistent to any user-defined netlists. 
+
+.. option:: <port type="<string>" prefix="<string>" lib_name="<string>" size="<int>"
+  default_val="<int>" circuit_model_name="<string>" mode_select="<bool>"
+  is_global="<bool>" is_set="<bool>" is_reset="<bool>" is_config_enable="<bool>"/>
+
+  Define the attributes for a port of a circuit model.
+
+  - ``type="input|output|sram|clock"`` Specify the type of the port, i.e., the directionality and usage. For programmable modules, such as multiplexers and LUTs, SRAM ports MUST be defined. For registers, such as FFs and memory banks, clock ports MUST be defined.
+
+  - ``prefix=<string>`` the name of the port to appear in the autogenerated netlists. Each port will be shown as ``<prefix>[i]`` in Verilog/SPICE netlists.
+
+  - ``lib_name=<string>`` the name of the port defined in standard cells or customized cells. If not specified, this attribute will be the same as ``prefix``.
+
+  - ``size=<int>`` bandwidth of the port. MUST be larger than zero.
+
+  - ``default_val="<int>"`` Specify default logic value for a port, which is used as the initial logic value of this port in testbench generation. Can be either 0 or 1. We assume each pin of this port has the same default value.
+
+  - ``circuit_model_name="<string>"`` Specify the name of the circuit model which is connected to this port.
+
+  - ``mode_select="true|false"`` Specify if this port controls the mode switching in a configurable logic block. This is due to that a configurable logic block can operate in different modes, which is controlled by SRAM bits.
+
+  - ``is_global="true|false"`` can be either ``true`` or ``false``. Specify if this port is a global port, which will be routed globally. Note that when multiple global ports are defined with the same name, these global ports will be short-wired together.
+
+  - ``is_set="true|false"`` Specify if this port controls a set signal. All the set ports are connected to global set voltage stimuli in testbenches.
+
+  - ``is_reset="true|false"`` Specify if this port controls a reset signal. All the reset ports are connected to a global reset voltage stimuli in testbenches.
+
+  - ``is_config_enable="true|false"`` Specify if this port controls a configuration-enable signal. Only valid when ``is_global`` is ``true``. This port is only enabled during FPGA configuration, and always disabled during FPGA operation. All the ``config_enable`` ports are connected to global configuration-enable voltage stimuli in testbenches.
+
+.. note:: ``sram`` and ``clock`` ports are considered as inputs in terms of directionality
+
+.. note:: ``circuit_model_name`` is only valid when the type of this port is ``sram``.
+
+.. note:: ``mode_select`` is only valid when the type of this port is ``sram``.
+
+.. note:: ``is_set``, ``is_reset`` and ``is_config_enable`` are only valid when ``is_global`` is ``true``. 
+
+.. note::  Different types of ``circuit_model`` have different XML syntax, with which users can highly customize their circuit topologies. See refer to examples of :ref:``circuit_model_example`` for more details.
+
+.. note:: Note that we have a list of reserved port names, which indicate the usage of these ports when building FPGA fabrics. Please do not use ``mem_out``, ``mem_inv``, ``bl``, ``wl``, ``blb``, ``wlb``, ``ccff_head`` and ``ccff_tail``.
diff --git a/docs/source/arch_lang/simulation_setting.rst b/docs/source/arch_lang/simulation_setting.rst
index c6d9c1545..d50067843 100644
--- a/docs/source/arch_lang/simulation_setting.rst
+++ b/docs/source/arch_lang/simulation_setting.rst
@@ -371,4 +371,3 @@ This is used by FPGA-SPICE in generating testbenches
   - ``slew_time="<float>"`` specify the slew rate of an input or clock signal at the rising/falling edge. 
  
   :numref:`fig_measure_edge` depicts the definition of the slew and delays of signals and the parameters that can be supported by FPGA-SPICE.
-

From 8db257946ca57826983b912a9caf376e88cc231c Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 10 Mar 2020 12:18:39 -0600
Subject: [PATCH 288/645] remove backport in travis setup. The link is dead
 now. Plus we no longer need the backport for a newer version of cmake

---
 .travis.yml | 1 -
 1 file changed, 1 deletion(-)

diff --git a/.travis.yml b/.travis.yml
index f06eb8db1..0b5ce92fb 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -29,7 +29,6 @@ matrix:
         apt:
           sources:
           - ubuntu-toolchain-r-test # For newer GCC
-          - george-edison55-precise-backports # For cmake
           - llvm_toolchain-trusty-7
           packages:
           - autoconf

From 7195564455886f7c19b5f6c88293b2724d94c810 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 10 Mar 2020 16:17:20 -0600
Subject: [PATCH 289/645] reworked circuit model examples in documentation. Now
 we are consistent to latest syntax

---
 docs/source/arch_lang/circuit_library.rst     |   6 +-
 .../arch_lang/circuit_model_examples.rst      | 601 +++++++++++-------
 2 files changed, 374 insertions(+), 233 deletions(-)

diff --git a/docs/source/arch_lang/circuit_library.rst b/docs/source/arch_lang/circuit_library.rst
index 04f0039b4..b28acafea 100644
--- a/docs/source/arch_lang/circuit_library.rst
+++ b/docs/source/arch_lang/circuit_library.rst
@@ -250,11 +250,11 @@ A circuit model may consist of a number of ports. The port list is mandatory in
 
   - ``type="input|output|sram|clock"`` Specify the type of the port, i.e., the directionality and usage. For programmable modules, such as multiplexers and LUTs, SRAM ports MUST be defined. For registers, such as FFs and memory banks, clock ports MUST be defined.
 
-  - ``prefix=<string>`` the name of the port to appear in the autogenerated netlists. Each port will be shown as ``<prefix>[i]`` in Verilog/SPICE netlists.
+  - ``prefix="<string>"`` the name of the port to appear in the autogenerated netlists. Each port will be shown as ``<prefix>[i]`` in Verilog/SPICE netlists.
 
-  - ``lib_name=<string>`` the name of the port defined in standard cells or customized cells. If not specified, this attribute will be the same as ``prefix``.
+  - ``lib_name="<string>"`` the name of the port defined in standard cells or customized cells. If not specified, this attribute will be the same as ``prefix``.
 
-  - ``size=<int>`` bandwidth of the port. MUST be larger than zero.
+  - ``size="<int>"`` bandwidth of the port. MUST be larger than zero.
 
   - ``default_val="<int>"`` Specify default logic value for a port, which is used as the initial logic value of this port in testbench generation. Can be either 0 or 1. We assume each pin of this port has the same default value.
 
diff --git a/docs/source/arch_lang/circuit_model_examples.rst b/docs/source/arch_lang/circuit_model_examples.rst
index 7e6a50229..a4472c01d 100644
--- a/docs/source/arch_lang/circuit_model_examples.rst
+++ b/docs/source/arch_lang/circuit_model_examples.rst
@@ -2,34 +2,36 @@
 
 Circuit model examples
 ----------------------
-The next subsections are dedicated to detailed examples of each circuit model type. Through these examples, we give a global overview of the different implementations which are available for the user.
+As circuit model in different types have various special syntax.
+Here, we will provide detailed examples on each type of ``circuit_model``.
+These examples may be considered as template for users to craft their own ``circuit_model``.
 
 Inverters and Buffers
 ~~~~~~~~~~~~~~~~~~~~~
 
+Template
+````````
+
 .. code-block:: xml
 
-  <circuit_model type="inv_buf" name="string" prefix="string" netlist="string" is_default="int">
-    <design_technology type="cmos" topology="string" size="int" tapered="off"/>
-    <port type="input" prefix="string" size="int"/>
-    <port type="output" prefix="string" size="int"/>
+  <circuit_model type="inv_buf" name="<string>" prefix="<string>" netlist="<string>" is_default="<int>">
+    <design_technology type="cmos" topology="<string>" size="<int>" num_level="<int>" f_per_stage="<float>"/>
+    <port type="input" prefix="<string>" size="<int>"/>
+    <port type="output" prefix="<string>" size="<int>"/>
   </circuit_model>
 
-.. note:: customized Verilog/SPICE netlists are not currently supported for inverters and buffers.
+.. option:: <design_technology type="cmos" topology="<string>" size="<int>" num_level="<int>" f_per_stage="<float>"/>
 
-* design_technology:
+  - ``topology="inverter|buffer"`` Specify the type of this component, can be either an inverter or a buffer.
 
-	* **topology:** [``inverter`` | ``buffer``]. Specify the type of this component, can be either an inverter or a buffer.
+  - ``size="<int>"`` Specify the driving strength of inverter/buffer. For a buffer, the size is the driving strength of the inverter at the second level. Note that we consider a two-level structure for a buffer here.
 
-	* **size:** Specify the driving strength of inverter/buffer. For a buffer, the size is the driving strength of the inverter at the second level. We consider a two-level structure for a buffer here. The support for multi-level structure of a buffer will be introduced in the tapered options.
+  - ``num_level="<int>"`` Define the number of levels of a tapered inverter/buffer. This is required when users need an inverter or a buffer consisting of >2 stages 
 
-	* **tapered:** [``on`` | ``off``]. Define if the buffer is a tapered (multi-level) buffer. When ``on`` is defined, the following parameter are required.*
+  - ``f_per_stage="<float>"`` Define the ratio of driving strength between the levels of a tapered inverter/buffer. Default value is 4.
 
-		* **tap_drive_level:** Define the number of levels of a tapered buffer. This parameter is valid only when tapered is turned on.
-
-		* **f_per_stage:** Define the ratio of driving strength between the levels of a tapered driver. This parameter is valid only when tapered is turned on. Default value is 4.
-
-**Inverter x1 example**
+Inverter 1x Example
+```````````````````
 
 :numref:`fig_inv1` is the inverter symbol depicted in this example.
 
@@ -37,9 +39,9 @@ Inverters and Buffers
 
 .. figure:: ./figures/Inverter_1.png
    :scale: 100%
-   :alt: classical inverter x1 symbol
+   :alt: classical inverter 1x symbol
 
-   Classical inverter x1 symbol.
+   Classical inverter 1x symbol.
 
 The XML code describing this inverter is:
 
@@ -52,18 +54,20 @@ The XML code describing this inverter is:
   </circuit_model>
 
 This example shows:
-	* The topology chosen as inverter
-	* Size of 1 for the output strength
-	* The tapered parameter is not declared and is off by default
 
-**Power-gated Inverter x1 example**
+  - The topology chosen as inverter
+  - Size of 1 for the output strength
+  - The tapered parameter is not declared and is ``false`` by default
+
+Power-gated Inverter 1x example
+```````````````````````````````
 
 The XML code describing an inverter which can be power-gated by the control signals ``EN`` and ``ENB`` :
 
 .. code-block:: xml
 
   <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1">
-    <design_technology type="cmos" topology="inverter" size="3" tapered="off" power_gated="true"/>
+    <design_technology type="cmos" topology="inverter" size="3" power_gated="true"/>
     <port type="input" prefix="in" size="1" lib_name="I"/>
     <port type="input" prefix="EN" size="1" lib_name="EN" is_global="true" default_val="0" is_config_enable="true"/>
     <port type="input" prefix="ENB" size="1" lib_name="ENB" is_global="true" default_val="1" is_config_enable="true"/>
@@ -72,15 +76,16 @@ The XML code describing an inverter which can be power-gated by the control sign
 
 .. note:: For power-gated inverters: all the control signals must be set as ``config_enable`` so that the testbench generation will generate testing waveforms. If the power-gated inverters are auto-generated , all the ``config_enable`` signals must be ``global`` signals as well. If the pwoer-gated inverters come from user-defined netlists, restrictions on ``global`` signals are free.
 
-**Buffer x2 example**
+Buffer 2x example
+`````````````````
 
 :numref:`fig_buff` is the buffer symbol depicted in this example.
 
 .. _fig_buff:
 
 .. figure:: ./figures/Buffer.png
-   :scale: 100%
-   :alt: buffer symbol composed by 2 inverter, its output strength equal 2
+   :scale: 50%
+   :alt: buffer symbol composed by 2 inverter, its output strength equals to 2
 
    Buffer made by two inverter, with an output strength of 2.
 
@@ -95,19 +100,20 @@ The XML code describing this buffer is:
   </circuit_model>
 
 This example shows:
-	* The topology chosen as buffer
-	* Size of 2 for the output strength
-	* The tapered parameter is not declared and is off by default
+  - The topology chosen as buffer
+  - Size of 2 for the output strength
+  - The tapered parameter is not declared and is ``false`` by default
 
 
-**Tapered inverter x16 example**
+Tapered inverter 16x example
+````````````````````````````
 
 :numref:`fig_invtap4` is the tapered inverter symbol depicted this example.
 
 .. _fig_invtap4:
 
 .. figure:: ./figures/Tapered_inverter.png
-   :scale: 100%
+   :scale: 50%
    :alt: tapered inverter composed by 3 inverter for an output strength = 16
 
    Inverter with high output strength made by 3 stage of inverter.
@@ -117,62 +123,65 @@ The XML code describing this inverter is:
 .. code-block:: xml
 
   <circuit_model type="inv_buf" name="tapdrive4" prefix="tapdrive4">
-    <design_technology type="cmos" topology=�inverter" size="1" tapered="on" tap_drive_level="3" 
-	f_per_stage="4"/>
+    <design_technology type="cmos" topology=�inverter" size="1" num_level="3" f_per_stage="4"/>
     <port type="input" prefix="in" size="1"/>
     <port type="output" prefix="out" size="1"/>
   </circuit_model>
 
 
 This example shows:
-	* The topology chosen as inverter
-	* Size of 1 for the first stage output strength
-	* The tapered parameter is on. Then the required sub parameters are declared
-		* The number of stage is set to 3 by tap_drive_level
-		* f_per_stage is set to 4. Then 2nd stage output strength is 4* the 1st stage output strength (so 4*1 = 4) and the 3rd stage output strength is 4* the 2nd stage output strength (so 4*4 =  16).
-
+  - The topology chosen as inverter
+  - Size of 1 for the first stage output strength
+  - The number of stage is set to 3 by
+  - f_per_stage is set to 4. Then 2nd stage output strength is 4* the 1st stage output strength (so 4*1 = 4) and the 3rd stage output strength is 4* the 2nd stage output strength (so 4*4 =  16).
 
 Pass-gate Logic
 ~~~~~~~~~~~~~~~
 
+Template
+````````
+
 .. code-block:: xml
 
-  <circuit_model type="pass_gate" name="string" prefix="string" netlist="string" is_default="int">
-    <design_technology type="cmos" topology="string" nmos_size="int" pmos_size="int"/>
-    <input_buffer exist="string" circuit_model_name="string" />
-    <output_buffer exist="string" circuit_model_name="string" />
-    <port type="input" prefix="string" size="int"/>
-    <port type="output" prefix="string" size="int"/>
+  <circuit_model type="pass_gate" name="<string>" prefix="<string>" netlist="<string>" is_default="<int>">
+    <design_technology type="cmos" topology="<string>" nmos_size="<float>" pmos_size="<float>"/>
+    <input_buffer exist="false"/>
+    <output_buffer exist="false"/>
+    <port type="input" prefix="<string>" size="<int>"/>
+    <port type="output" prefix="<string>" size="<int>"/>
   </circuit_model>
 
-.. note:: customized Verilog/SPICE netlists are not currently supported for pass-gate logics.
+.. note:: Please do not add input and output buffers to pass-gate logic.
 
-* design_technology:
+.. option:: <design_technology type="cmos" topology="<string>" nmos_size="<float>" pmos_size="<float>"/>
 
-	* **topology:** [``transmission_gate`` | ``pass_transistor``]. The transmission gate consists of a NMOS transistor and a PMOS transistor. The pass transistor consists of a NMOS transistor.
+  - ``topology="transmission_gate|pass_transistor"`` Specify the circuit topology for the pass-gate logic. A transmission gate consists of a *n*-type transistor and a *p*-type transistor. The pass transistor consists of only a  *n*-type transistor.
 
-	* **nmos_size:** the size of NMOS transistor in a transmission gate or pass_transistor, expressed in terms of the min_width defined in XML node <transistors>.
+  - ``nmos_size="<float>"`` the size of *n*-type transistor in a transmission gate or pass_transistor, expressed in terms of the minimum width ``min_width`` defined in the transistor model in :ref:`technology_library`.
 
-	* **pmos_size:** the size of PMOS transistor in a transmission gate, expressed in terms of the min_width defined in XML node <transistors>.
+  - ``pmos_size="<float>"`` the size of *p*-type transistor in a transmission gate, expressed in terms of the minimum width ``min_width`` defined in the transistor model in :ref:`technology_library`.
 
-**Transmission-gate example**
+.. note:: ``nmos_size`` and ``pmos_size`` are required for FPGA-SPICE
+
+Transmission-gate Example
+`````````````````````````
 
 :numref:`fig_passgate` is the pass-gate symbol depicted in this example.
 
 .. _fig_passgate:
 
 .. figure:: ./figures/pass-gate.png
-   :scale: 60%
+   :scale: 30%
    :alt: pmos and nmos transistortors forming a pass-gate
 
-   Pass-gate made by pmos ans nmos association.
+   Pass-gate made by a *p*-type and a *n*-type transistors.
 
 The XML code describing this pass-gate is:
 
 .. code-block:: xml
 
   <circuit_model type="pass_gate" name="tgate" prefix="tgate">
-    <design_technology type="cmos" topology="transmission_gate"/>
+    <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
     <port type="input" prefix="in" size="1"/>
     <port type="input" prefix="sram" size="1"/>
     <port type="input" prefix="sramb" size="1"/>
@@ -180,18 +189,18 @@ The XML code describing this pass-gate is:
   </circuit_model>
 
 This example shows:
-	* Topology is ``transmission_gate``, which means the component need entries for each transistor gate (pmos and nmos)
-	* 3 inputs considered, 1 for signal and 2 to control the transistors gates
-	* No input or output buffer used, these parameters can be uninitialized
+  - A ``transmission_gate`` built with a *n*-type transistor in the size of 1 and a *p*-type transistor in the size of 2.
+  - 3 inputs considered, 1 for datapath signal and 2 to turn on/off the transistors gates
 
-**Pass-transistor example**
+Pass-transistor Example
+```````````````````````
 
 :numref:`fig_passtran` is the pass-gate symbol depicted in this example.
 
 .. _fig_passtran:
 
 .. figure:: ./figures/pass_transistor.png
-   :scale: 50%
+   :scale: 30%
    :alt: nmos transistortor forming a pass-gate
 
    Pass-gate made by a nmos transistor.
@@ -208,22 +217,23 @@ The XML code describing this pass-gate is:
   </circuit_model>
 
 This example shows:
-	* Topology is ``pass_transistor``, which means the component need an entry for the transistor gate (nmos)
-	* 2 inputs considered, 1 for signal and 1 to control the transistor gate
-	* No input or output buffer used, these parameters can be uninitialized
-
+  - A ``pass_transistor`` build with a *n*-type transistor in the size of 1 
+  - 2 inputs considered, 1 for datapath signal and 1 to turn on/off the transistor gate
 
 SRAMs
 ~~~~~
 
+Template
+````````
+
 .. code-block:: xml
 
-  <circuit_model type="sram" name="string" prefix="string" netlist="string"/>
+  <circuit_model type="sram" name="<string>" prefix="<string>" verilog_netlist="<string>" spice_netlist="<string>"/>
     <design_technology type="cmos"/>
-    <input_buffer exist="string" circuit_model_name="string"/>
-    <output_buffer exist="string" circuit_model_name="string"/>
-    <port type="input" prefix="string" size="int"/>
-    <port type="output" prefix="string" size="int"/>
+    <input_buffer exist="<string>" circuit_model_name="<string>"/>
+    <output_buffer exist="<string>" circuit_model_name="<string>"/>
+    <port type="input" prefix="<string>" size="<int>"/>
+    <port type="output" prefix="<string>" size="<int>"/>
   </circuit_model>
 
 .. note::  The circuit designs of SRAMs are highly dependent on the technology node and well optimized by engineers. Therefore, FPGA-Verilog/SPICE requires users to provide their customized SRAM Verilog/SPICE/Verilog netlists. A sample Verilog/SPICE netlist of SRAM can be found in the directory SpiceNetlists in the released package. FPGA-Verilog/SPICE assumes that all the LUTs and MUXes employ the SRAM circuit design. Therefore, currently only one SRAM type is allowed to be defined.
@@ -235,64 +245,93 @@ SRAMs
 Logic gates
 ~~~~~~~~~~~
 
+The circuit model in the type of ``gate`` aims to support direct mapping to standard cells or customized cells provided by technology vendors or users. 
+
+Template
+````````
+
 .. code-block:: xml
 
-  <circuit_model type="gate" name="string" prefix="string" netlist="string" dump_explicit_port_map="true|false"/>
-    <design_technology type="cmos" topology="string"/>
-    <input_buffer exist="string" circuit_model_name="string"/>
-    <output_buffer exist="string" circuit_model_name="string"/>
-    <port type="input" prefix="string" lib_name="string" size="int"/>
-    <port type="output" prefix="string" lib_name="string" size="int"/>
+  <circuit_model type="gate" name="<string>" prefix="<string>" spice_netlist="<string>" verilog_netlist="<string>"/>
+    <design_technology type="cmos" topology="<string>"/>
+    <input_buffer exist="<string>" circuit_model_name="<string>"/>
+    <output_buffer exist="<string>" circuit_model_name="<string>"/>
+    <port type="input" prefix="<string>" lib_name="<string>" size="<int>"/>
+    <port type="output" prefix="<string>" lib_name="<string>" size="<int>"/>
   </circuit_model>
 
-.. note::  The circuit model in the type of gate aims to support direct mapping to standard cells or customized cells provided by technology vendors or users. 
 
-.. note:: The logic functionality of a gate can be defined through the XML keyword ``topology``. Currently, OpenFPGA supports AND, OR and MUX2 gates. As for standard cells, the size of each port is limited to 1. Currently, only 2-input and single-output logic gates are supported.
+.. option:: <design_technology type="cmos" topology="<string>"/>
+  
+  - ``topology="AND|OR|MUX2"`` Specify the logic functionality of a gate. As for standard cells, the size of each port is limited to 1. Currently, only 2-input and single-output logic gates are supported.
 
-.. note:: It may happen that the port sequence in generated Verilog netlists has conflicts with the port sequence in standard and customized cells. To avoid this, users can set the XML keyword ``dump_explicit_port_map`` to be true, which enables explicit port mapping are dumped. Users can specify the pin/port name in the standard cell library using the XML keyword ``lib_name``.
+2-input OR Gate Example
+```````````````````````
+
+.. code-block:: xml
+
+    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
+      <design_technology type="cmos" topology="OR"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="a b" out_port="out">
+        10e-12 8e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="a b" out_port="out">
+        10e-12 7e-12
+      </delay_matrix>
+    </circuit_model>
+
+This example shows:
+  - A 2-input OR gate without any input and output buffers
+  - Propagation delay from input ``a`` to ``out`` is 10ps in rising edge and and 8ps in falling edge
+  - Propagation delay from input ``b`` to ``out`` is 10ps in rising edge and 7ps in falling edge
 
 Multiplexers
 ~~~~~~~~~~~~
 
+Template
+````````
+
 .. code-block:: xml
 
-  <circuit_model type="mux" name="string" prefix="string" is_default="int">
-    <design_technology type="string" structure="string" num_level="int" add_const_input="string" const_input_val="int" local_encoder="string" ron="float" roff="float" prog_transistor_size="float"/>
-    <input_buffer exist="string" circuit_model_name="string"/>
-    <output_buffer exist="string" circuit_model_name="string"/>
-    <pass_gate_logic type="string" circuit_model_name="string"/>
-    <port type="input" prefix="string" size="int"/>
-    <port type="output" prefix="string" size="int"/>
-    <port type="sram" prefix="string" size="int"/>
+  <circuit_model type="mux" name="<string>" prefix="<string>">
+    <design_technology type="<string>" structure="<string>" num_level="<int>" add_const_input="<bool>" const_input_val="<int>" local_encoder="<bool>"/>
+    <input_buffer exist="<string>" circuit_model_name="<string>"/>
+    <output_buffer exist="<string>" circuit_model_name="<string>"/>
+    <pass_gate_logic type="<string>" circuit_model_name="<string>"/>
+    <port type="input" prefix="<string>" size="<int>"/>
+    <port type="output" prefix="<string>" size="<int>"/>
+    <port type="sram" prefix="<string>" size="<int>"/>
   </circuit_model>
 
-.. note:: customized Verilog/SPICE netlists are not currently supported for multiplexers.
+.. note:: user-defined Verilog/SPICE netlists are not currently supported for multiplexers.
 
-* design_technology:
+.. option:: <design_technology type="<string>" structure="<string>" num_level="<int>" add_const_input="<bool>" const_input_val="<int>" local_encoder="<bool>"/>
 
-	* **structure:** can be [``tree`` \| ``multi-level`` \| ``one-level``]. The structure options are valid for SRAM-based multiplexers. For RRAM-based multiplexers, currently we only support the circuit design in [5]. If ``multi-level`` the following parameter is required:
+  - ``structure="tree|multi-level|one-level"`` Specify the multiplexer structure for a multiplexer. The structure option is only valid for SRAM-based multiplexers. For RRAM-based multiplexers, currently we only support the one-level structure
 
-		* **num_level:** specify the number of levels when multi-level structure is selected, only.
+  - ``num_level="<int>"`` Specify the number of levels when ``multi-level`` structure is selected.
     
-    * **add_const_input:** can be [``true`` \| ``false``]. When enabled, an extra input will be added to the multiplexer circuits defined in this ``circuit_model``. For example, an 4-input multiplexer will be turned to a 5-input multiplexer. The extra input will be wired to a constant value, which can be specified through the XML syntax ``const_input_val``. The constant value can be either 0 or 1 (By default it is 0). Note that adding such input will help reducing the leakage power of FPGA and parasitic signal activities, with a limited area overhead.
+  - ``add_const_input="true|false"`` Specify if an extra input should be added to the multiplexer circuits. For example, an 4-input multiplexer will be turned to a 5-input multiplexer. The extra input will be wired to a constant value, which can be specified through the XML syntax ``const_input_val``.
 
-		* **const_input_val:** specify the constant value, to which the extra input will be connected. This syntax is only valid when the ``add_const_input`` is set to true.
+    .. note::  Adding an extra constant input will help reducing the leakage power of FPGA and parasitic signal activities, with a limited area overhead.
+
+  - ``const_input_val="0|1"`` Specify the constant value, to which the extra input will be connected. By default it is 0. This syntax is only valid when the ``add_const_input`` is set to true. 
   
-    * **local_encoder:** can be [``true`` \| ``false``]. When enabled, an local encoder will be added to the multiplexer circuits defined in this ``circuit_model``. The local encoder will be interface the SRAM inputs of multiplexing structure and SRAMs. It can encode the one-hot codes (that drive the select port of multiplexing structure) to a binary code. For example, 8-bit ``00000001`` will be encoded to 3-bit ``000``. This will help reduce the number of SRAM cells used in FPGAs as well as configuration time (especially for scan-chain configuration protocols). But it may cost an area overhead.  
+  - ``local_encoder="true|false"``. Specify if a local encoder should be added to the multiplexer circuits. The local encoder will interface the SRAM inputs of multiplexing structure and SRAMs. It can encode the one-hot codes (that drive the select port of multiplexing structure) to a binary code. For example, 8-bit ``00000001`` will be encoded to 3-bit ``000``. This will help reduce the number of SRAM cells used in FPGAs as well as configuration time (especially for scan-chain configuration protocols). But it may cost an area overhead.  
 
-        .. note:: Local encoders are only applicable for one-level and multi-level multiplexers. Tree-like multiplexers are already encoded in their nature.
+    .. note:: Local encoders are only applicable for one-level and multi-level multiplexers. Tree-like multiplexers are already encoded in their nature.
 
-    * **prog_transistor_size:** valid only when the type of design technology is ``rram``. Specify the size of programming transistors used in the RRAM-based multiplexer, we use only n-type transistor and the size should be expressed in terms of the min_width defined in XML node ``transistors``. If type of design technology is ``rram``, then the following parameters are required:
-
-		* **ron:** valid only when the type of design technology is rram. Specify the on-resistance of the RRAM device used in the RRAM-based multiplexer. 
-
-		* **roff:** valid only when the type of design technology is rram. Specify the off-resistance of the RRAM device used in the RRAM-based multiplexer. 
-
-* port: for a multiplexer, the three types of ports, ``input``, ``output`` and ``sram`` should be defined. 
+.. note:: A multiplexer should have only three types of ports, ``input``, ``output`` and ``sram``, which are all mandatory. 
 
 .. note:: For tree-like multiplexers, they can be built with standard cell MUX2. To enable this, users should define a ``circuit_model``, which describes a 2-input multiplexer (See details and examples in how to define a logic gate using ``circuit_model``. In this case, the ``circuit_model_name`` in the ``pass_gate_logic`` should be the name of MUX2 ``circuit_model``.
 
-**Mux 1 level example**
+One-level Mux Example
+`````````````````````
 
 :numref:`fig_mux1` illustrates an example of multiplexer modelling, which consists of input/output buffers and a transmission-gate-based tree structure.
 
@@ -318,12 +357,15 @@ The code describing this Multiplexer is:
     <port type="sram" prefix="sram" size="4"/> 
   </circuit_model>
 
-**This example shows:**
-	* Each circuit model composing the Multiplexer
-	* The possibility to select the input or output buffers
-	* The possibility to select the pass-gate inside the Mux.
+This example shows:
+  - A one-level 4-input CMOS multiplexer 
+  - All the inputs will be buffered using the circuit model ``inv1x``
+  - All the outputs will be buffered using the circuit model ``tapbuf4``
+  - The multiplexer will be built by transmission gate using the circuit model ``tgate``
+  - The multiplexer will have 4 inputs and 4 SRAMs to control which datapath to propagate
 
-**Mux-tree example**
+Tree-like Multiplexer Example
+`````````````````````````````
 
 :numref:`fig_mux` illustrates an example of multiplexer modelling, which consists of input/output buffers and a transmission-gate-based tree structure.
 
@@ -349,61 +391,101 @@ If we arbitrarily fix the number of Mux entries at 4, the following code could i
     <port type="sram" prefix="sram" size="3"/>
   </circuit_model>
 
-**This example shows:**
-	* The tree topology, 4 entries split in 2 2-to-1 Muxes then another one make the final selection.
-	* The possibility to select the input or output buffers
-	* The number of entries parametrized by ``size`` in input port-type.
+This example shows:
+  - A tree-like 4-input CMOS multiplexer 
+  - All the inputs will be buffered using the circuit model ``inv1x``
+  - All the outputs will be buffered using the circuit model ``tapbuf4``
+  - The multiplexer will be built by transmission gate using the circuit model ``tgate``
+  - The multiplexer will have 4 inputs and 3 SRAMs to control which datapath to propagate
 
 Look-Up Tables
 ~~~~~~~~~~~~~~
 
+Template
+````````
+
 .. code-block:: xml
 
-  <circuit_model type="lut" name="string" prefix="string" is_default="int" netlist="string"/>
-    <design_technology type="cmos" fracturable_lut="true|false"/>
-    <input_buffer exist="string" circuit_model_name="string"/>
-    <output_buffer exist="string" circuit_model_name="string"/>
-    <lut_input_buffer exist="string" circuit_model_name="string"/>
-    <lut_intermediate_buffer exist="string" circuit_model_name="string" location_map="string"/>
-    <lut_input_inverter exist="string" circuit_model_name="string"/>
-    <pass_gate_logic type="string" circuit_model_name="string"/>
-    <port type="input" prefix="string" size="int" tri_state_map="----11" circuit_model_name="string"/>
-    <port type="output" prefix="string" size="int" lut_frac_level="int" lut_output_mask="int"/>
-    <port type="sram" prefix="string" size="int" mode_select="true|false" circuit_model_name="string" default_val="0|1"/>
+  <circuit_model type="lut" name="<string>" prefix="<string>" spice_netlist="<string>" verilog_netlist="<string>"/>
+    <design_technology type="cmos" fracturable_lut="<bool>"/>
+    <input_buffer exist="<string>" circuit_model_name="<string>"/>
+    <output_buffer exist="<string>" circuit_model_name="<string>"/>
+    <lut_input_buffer exist="<string>" circuit_model_name="<string>"/>
+    <lut_input_inverter exist="<string>" circuit_model_name="<string>"/>
+    <lut_intermediate_buffer exist="<string>" circuit_model_name="<string>" location_map="<string>"/>
+    <pass_gate_logic type="<string>" circuit_model_name="<string>"/>
+    <port type="input" prefix="<string>" size="<int>" tri_state_map="<string>" circuit_model_name="<string>"/>
+    <port type="output" prefix="<string>" size="<int>" lut_frac_level="<int>" lut_output_mask="<int>"/>
+    <port type="sram" prefix="<string>" size="<int>" mode_select="<bool>" circuit_model_name="<string>" default_val="<int>"/>
   </circuit_model>
 
 .. note:: The Verilog/SPICE netlists of LUT can be auto-generated or customized.
   The auto-generated LUTs are based on a tree-like multiplexer, whose gates of the transistors are used as the inputs of LUTs and the drains/sources of the transistors are used for configurable memories (SRAMs).
   The LUT provided in customized Verilog/SPICE netlist should have the same decoding methodology as the traditional LUT.
 
-Additional design parameters for LUTs:
+.. option:: <lut_input_buffer exist="<string>" circuit_model_name="<string>"/>
 
-* **lut_input_buffer:** Define transistor-level description for the buffer for the inputs of a LUT (gates of the internal multiplexer). Use keyword circuit_model_name to specify the circuit_model that containing details of the circuit. 
+  Define transistor-level description for the buffer for the inputs of a LUT (gates of the internal multiplexer).
 
-* **lut_input_inverter:** Define transistor-level description for the inverter for the inputs of a LUT (gates of the internal multiplexer). Use keyword circuit_model_name to specify the circuit_model that containing details of the circuit. 
+  - ``exist="true|false"`` Specify if the input buffer should exist for LUT inputs
 
+  - ``circuit_model_name="<string>"`` Specify the ``circuit_model`` that will be used to build the input buffers
 
-* **lut_intermediate_buffer:** Define transistor-level description for the buffer locating at intermediate stages of internal multiplexer of a LUT. Use keyword circuit_model_name to specify the circuit_model that containing details of the circuit. To customize the location, users can define an integer array in the XML keyword location_map. For example, "-1-1-" indicates buffer inseration to every two stages of the LUT multiplexer tree, considering a 6-input LUT. 
+.. note:: In the context of LUT, ``input_buffer`` corresponds to the buffer for the datapath inputs of multiplexers inside a LUT. ``lut_input_buffer`` corresponds to the buffer at the inputs of a LUT
 
+.. option:: <lut_input_inverter exist="<string>" circuit_model_name="<string>"/>
 
-Instructions of defining design parameters:
+  Define transistor-level description for the inverter for the inputs of a LUT (gates of the internal multiplexer).
 
-* **input_buffer:** Specify the buffer/inverter that connects the SRAM outputs to the inputs of multiplexer.
+  - ``exist="true|false"`` Specify if the input buffer should exist for LUT inputs
 
-* **pass_gate_logic:** Specify the pass-gates of the internal multiplexer, the same as the multiplexers.
+  - ``circuit_model_name="<string>"`` Specify the ``circuit_model`` that will be used to build the input inverters
 
-* **port:** three types of ports (input, output and sram) should be defined. If the user provides an customized Verilog/SPICE netlist, the bandwidth of ports should be defined to the same as the Verilog/SPICE netlist. To support customizable LUTs, each type of port contain special keywords. For input ports, the keyword tri_state_map aims to customize which inputs are fixed to constant values when the LUT is in fracturable modes. For example, ``tri_state_map`` ="----11" indicates that the last two inputs will be fixed to be logic '1' when a 6-input LUT is in fracturable modes. The circuit_model_name of input port is used to specify which logic gates will be used to tri-state the inputs in fracturable LUT modes. It is required to use an AND gate to force logic '0' or an OR gate to force logic '1' for the input ports. For output ports, the keyword lut_frac_level is used to specify the level in LUT multiplexer tree where the output port are wired to. For example, lut_frac_level="4" in a fracturable LUT6 means that the output are potentially wired to the 4th stage of a LUT multiplexer and it is an output of a LUT4. The keyword lut_output_mask describes which fracturable outputs are used. For instance, in a 6-LUT, there are potentially four LUT4 outputs can be wired out. lut_output_mask="0,2" indicates that only the first and the thrid LUT4 outputs will be used in fracturable mode. Note that the size of the output port should be consistent to the length of lut_output_mask. 
+.. option:: <lut_intermediate_buffer exist="<string>" circuit_model_name="<string>" location_map="<string>"/>
 
-* **SRAM port for mode selection:** To enable switch between different operating modes, the SRAM bits of a fracturable LUT consists of two parts: configuration memory and mode selecting. The SRAM port for mode selection is specified through the XML keyword mode_select. Note that the size of such SRAM port should be consistent to the number of 1s or 0s in the ``tri_state_map``.
+  Define transistor-level description for the buffer locating at intermediate stages of internal multiplexer of a LUT. 
 
-**LUT example**
+  - ``exist="true|false"`` Specify if the input buffer should exist at intermediate stages
+
+  - ``circuit_model_name="<string>"`` Specify the ``circuit_model`` that will be used to build these buffers
+
+  - ``location_map="[1|-]"`` Customize the location of buffers in intermediate stages. Users can define an integer array consisting of '1' and '-'. For example, ``-1-1-`` indicates buffer inseration to every two stages of the LUT multiplexer tree, considering a 6-input LUT. 
+
+.. note:: For a LUT, three types of ports (``input``, ``output`` and ``sram``) should be defined. If the user provides an customized Verilog/SPICE netlist, the bandwidth of ports should be defined to the same as the Verilog/SPICE netlist. To support customizable LUTs, each type of port contain special keywords. 
+
+.. option:: <port type="input" prefix="<string>" size="<int>" tri_state_map="<string>" circuit_model_name="<string>"/>
+
+  - ``tri_state_map="[-|1]"`` Customize which inputs are fixed to constant values when the LUT is in fracturable modes. For example, ``tri_state_map="----11"`` indicates that the last two inputs will be fixed to be logic '1' when a 6-input LUT is in fracturable modes. 
+
+  - ``circuit_model_name="<string>"`` Specify the circuit model to build logic gates in order to tri-state the inputs in fracturable LUT modes. It is required to use an ``AND`` gate to force logic '0' or an ``OR`` gate to force logic '1' for the input ports.
+
+.. option:: <port type="output" prefix="<string>" size="<int>" lut_frac_level="<int>" lut_output_mask="<int>"/>
+
+  - ``lut_frac_level="<int>"`` Specify the level in LUT multiplexer tree where the output port are wired to. For example, ``lut_frac_level="4"`` in a fracturable LUT6 means that the output are potentially wired to the 4th stage of a LUT multiplexer and it is an output of a LUT4. 
+  
+  - ``lut_output_mask="<int>"`` Describe which fracturable outputs are used. For instance, in a 6-LUT, there are potentially four LUT4 outputs can be wired out. ``lut_output_mask="0,2"`` indicates that only the first and the thrid LUT4 outputs will be used in fracturable mode.
+
+.. note:: The size of the output port should be consistent to the length of ``lut_output_mask``. 
+
+.. option:: <port type="sram" prefix="<string>" size="<int>" mode_select="<bool>" circuit_model_name="<string>" default_val="<int>"/>
+
+  - ``mode_select="true|false"`` Specify if this port is used to switch the LUT between different operating modes, the SRAM bits of a fracturable LUT consists of two parts: configuration memory and mode selecting.
+
+  - ``circuit_model_name="<string>"`` Specify the circuit model to be drive the SRAM port. Typically, the circuit model should be in the type of ``ccff`` or ``sram``.
+
+  - ``default_val="0|1"`` Specify the default value for the SRAM port. The default value will be used in generating testbenches for unused LUTs
+
+.. note:: The size of a mode-selection SRAM port should be consistent to the number of '1s' or '0s' in the ``tri_state_map``.
+
+Single-Output LUT Example
+`````````````````````````
 
 :numref:`fig_lut` illustrates an example of LUT modeling, which consists of input/output buffers and a transmission-gate-based tree structure.
 
 .. _fig_lut:
 
 .. figure:: ./figures/lut.png
-   :scale: 100%
+   :scale: 80%
    :alt: Detailed LUT composition
 
    An example of a LUT with transistor-level design parameters.
@@ -416,52 +498,90 @@ The code describing this LUT is:
     <input_buffer exist="on" circuit_model="inv1x"/>
     <output_buffer exist="on" circuit_model_name="inv1x"/>
     <lut_input_buffer exist="on" circuit_model_name="buf2"/>
+    <lut_input_inverter exist="on" circuit_model_name="inv1x"/>
     <pass_gate_logic circuit_model_name="tgate"/>
     <port type="input" prefix="in" size="6"/>
     <port type="output" prefix="out" size="1"/>
     <port type="sram" prefix="sram" size="64"/>
   </circuit_model>
 
-**This example shows:**
-	* The difference between ``input_buffer`` and ``lut_input_buffer`` and that they are independent.
-	* How each blocks is defined
+This example shows:
+  - A 6-input LUT which is configurable by 64 SRAM cells.
+  - The multiplexer inside LUT will be built with transmission gate using circuuit model ``inv1x``
+  - There are no internal buffered inserted to any intermediate stage of a LUT
+
+Fracturable LUT Example
+`````````````````````````
+
+.. code-block:: xml
+
+  <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
+    <design_technology type="cmos" fracturable_lut="true"/>
+    <input_buffer exist="true" circuit_model_name="inv1x"/>
+    <output_buffer exist="true" circuit_model_name="inv1x"/>
+    <lut_input_inverter exist="true" circuit_model_name="inv1x"/>
+    <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+    <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
+    <pass_gate_logic circuit_model_name="tgate"/>
+    <port type="input" prefix="in" size="6" tri_state_map="-----1" circuit_model_name="OR2"/>
+    <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
+    <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
+    <port type="sram" prefix="sram" size="64"/>
+    <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="ccff" default_val="1"/>
+  </circuit_model>
+
+This example shows:
+  - Fracturable 6-input LUT which is configurable by 65 SRAM cells.
+  - Intermedate buffers are added to every two stages of the internal multiplexer
+  - There is a SRAM cell to switch the operating mode of this LUT, configured by a configuration-chain flip-flop ``ccff``
+  - The last input ``in[5]`` of LUT will be tri-stated in dual-LUT5 mode.
+  - An 2-input OR gate will be wired to the last input ``in[5]`` to tri-state the input. The mode-select SRAM will be wired to an input of the OR gate. 
+    It means that when the mode-selection bit is '1', the LUT will operate in dual-LUT5 mode.
+  - There will be two outputs wired to the 5th stage of routing multiplexer (the outputs of dual 5-input LUTs) 
+  - By default, the mode-selection configuration bit will be '1', indicating that by default the LUT will operate in dual-LUT5 mode.
 
 Flip-Flops
 ~~~~~~~~~~
 
+Template
+````````
+
 .. code-block:: xml
 
-  <circuit_model type="ff" name="string" prefix="string" netlist="string"/>
+  <circuit_model type="ccff|ff" name="<string>" prefix="<string>" spice_netlist="<string>" verilog_netlist="<string>"/>
     <design_technology type="cmos"/>
-    <input_buffer exist="string" circuit_model_name="string"/>
-    <output_buffer exist="string" circuit_model_name="string"/>
-    <port type="input" prefix="string" size="int"/>
-    <port type="output" prefix="string" size="int"/>
-    <port type="clock" prefix="string" size="int"/>
+    <input_buffer exist="<string>" circuit_model_name="<string>"/>
+    <output_buffer exist="<string>" circuit_model_name="<string>"/>
+    <port type="input" prefix="<string>" size="<int>"/>
+    <port type="output" prefix="<string>" size="<int>"/>
+    <port type="clock" prefix="<string>" size="<int>"/>
   </circuit_model>
 
 .. note:: The circuit designs of flip-flops are highly dependent on the technology node and well optimized by engineers. Therefore, FPGA-Verilog/SPICE requires users to provide their customized FF Verilog/SPICE/Verilog netlists. A sample Verilog/SPICE netlist of FF can be found in the directory SpiceNetlists in the released package.
   
-  The information of input and output buffer should be clearly specified according to the customized Verilog/SPICE netlist! The existence of input/output buffers will influence the decision in creating testbenches, which may leads to larger errors in power analysis.
+  The information of input and output buffer should be clearly specified according to the customized SPICE netlist! The existence of input/output buffers will influence the decision in creating SPICE testbenches, which may leads to larger errors in power analysis.
 
-  FPGA-Verilog/SPICE currently support only one clock domain in the FPGA. Therefore there should be only one clock port to be defined and the size of the clock port should be 1.
+.. note:: FPGA-Verilog/SPICE currently support only one clock domain in the FPGA. Therefore there should be only one clock port to be defined and the size of the clock port should be 1.
 
-Instructions of defining design parameters:
+.. option:: <circuit_model type="ccff|ff" name="<string>" prefix="<string>" spice_netlist="<string>" verilog_netlist="<string>"/>
 
-* **circuit_model type:** can be ``ff`` or ``scff``. FF is typical Flip-Flop, SCFF is Scan-Chain Flip-Flop
+  - ``type="ccff|ff"`` Specify the type of a flip-flop. ``ff`` is a regular flip-flop while ``ccff`` denotes a configuration-chain flip-flop
 
-* **port:** three types of ports (``input``, ``output`` and ``clock``) should be defined. If the user provides a customized Verilog/SPICE netlist, the bandwidth of ports should be defined to the same as the Verilog/SPICE netlist.
+.. note:: A flip-flop should have three types of ports, ``input``, ``output`` and ``clock``.
 
-.. note:: In a valid FPGA architecture, users should provide at least either a SCFF or a SRAM, so that the configurations can loaded to core logic. 
+.. note:: If the user provides a customized Verilog/SPICE netlist, the bandwidth of ports should be defined to the same as the Verilog/SPICE netlist.
 
-**FF example**
+.. note:: In a valid FPGA architecture, users should provide at least either a ``ccff`` or ``sram`` circuit model, so that the configurations can loaded to core logic. 
 
-:numref:`fig_ff` illustrates an example of LUT modeling, which consists of input/output buffers and a transmission-gate-based tree structure.
+Flip-Flop example
+`````````````````
+
+:numref:`fig_ff` illustrates an example of regular flip-flop.
 
 .. _fig_ff:
 
 .. figure:: ./figures/FF.png
-   :scale: 100%
+   :scale: 50%
    :alt: FF symbol
 
    An example of classical Flip-Flop.
@@ -470,27 +590,28 @@ The code describing this FF is:
 
 .. code-block:: xml
 
-  <circuit_model type="ff" name="dff" prefix="dff" verilog_netlist="ff.v">
-    <port type="input" prefix="D" size="1"/>
-    <port type="input" prefix="Set" size="1" is_global="true"/>
-    <port type="input" prefix="Reset" size="1" is_global="true"/>
-    <port type="output" prefix="Q" size="1"/>
-    <port type="clock" prefix="clk" size="1" is_global="true"/>
+  <circuit_model type="ff" name="dff" prefix="dff" verilog_netlist="ff.v" spice_netlist="ff.sp">
+    <port type="input" prefix="D" lib_name="D" size="1"/>
+    <port type="input" prefix="Set" lib_name="S" size="1" is_global="true"/>
+    <port type="input" prefix="Reset" lib_name="R" size="1" is_global="true"/>
+    <port type="output" prefix="Q" lib_name="Q" size="1"/>
+    <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true"/>
   </circuit_model>
 
-**This example shows:**
-	* Circuit model type as ``ff``
-	* The verilog netlist file associated to this component ``ff.v``
-	* 3 ports, ``Set``, ``Reset`` and ``clk``, defined as global
+This example shows:
+  - A regular flip-flop which is defined in a Verilog netlist ``ff.v`` and a SPICE netlist ``ff.sp``
+  - The flip-flop has ``set`` and ``reset`` functionalities
+  - The flip-flop port names defined differently in standard cell library and VPR architecture. The ``lib_name`` capture the port name defined in standard cells, while ``prefix`` capture the port name defined in ``pb_type`` of VPR architecture file
 
-**SCFF example**
+Configuration-chain Flip-flop Example
+`````````````````````````````````````
 
-:numref:`fig_scff` illustrates an example of LUT modeling, which consists of input/output buffers and a transmission-gate-based tree structure.
+:numref:`fig_ccff` illustrates an example of scan-chain flop-flop used to build a configuration chain.
 
-.. _fig_scff:
+.. _fig_ccff:
 
 .. figure:: ./figures/scff.png
-   :scale: 100%
+   :scale: 50%
    :alt: SCFF symbol
 
    An example of a Scan-Chain Flip-Flop.
@@ -499,85 +620,103 @@ The code describing this FF is:
 
 .. code-block:: xml
 
-  <circuit_model type="scff" name="scff" prefix="scff" verilog_netlist="scff.v">
+  <circuit_model type="ccff" name="ccff" prefix="ccff" verilog_netlist="ccff.v" spice_netlist="ccff.sp">
     <port type="input" prefix="D" size="1"/>
     <port type="output" prefix="Q" size="2"/>
-    <port type="clock" prefix="clk" size="1" is_global="true"/>
+    <port type="clock" prefix="CK" size="1" is_global="true"/>
   </circuit_model>
 
-**This example shows:**
-	* Circuit model type as ``scff``
-	* The verilog netlist file associated to this component ``scff.v``
-	* 1 port, ``clk``, defined as global
+This example shows:
+  - A configuration-chain flip-flop which is defined in a Verilog netlist ``ccff.v`` and a SPICE netlist ``ccff.sp``
+  - The flip-flop has a global clock port, ``CK``, which will be wired a global programming clock 
 
 Hard Logics
 ~~~~~~~~~~~
 
+Template
+````````
+
 .. code-block:: xml
 
-  <circuit_model type="hardlogic" name="string" prefix="string" netlist="string"/>
+  <circuit_model type="hardlogic" name="<string>" prefix="<string>" verilog_netlist="<string>" spice_netlist="<string>"/>
     <design_technology type="cmos"/>
-    <input_buffer exist="string" circuit_model_name="string"/>
-    <output_buffer exist="string" circuit_model_name="string"/>
-    <port type="input" prefix="string" size="int"/>
-    <port type="output" prefix="string" size="int"/>
+    <input_buffer exist="<string>" circuit_model_name="<string>"/>
+    <output_buffer exist="<string>" circuit_model_name="<string>"/>
+    <port type="input" prefix="<string>" size="<int>"/>
+    <port type="output" prefix="<string>" size="<int>"/>
   </circuit_model>
 
 .. note:: Hard logics are defined for non-configurable resources in FPGA architectures, such as adders, multipliers and RAM blocks.
   Their circuit designs are highly dependent on the technology node and well optimized by engineers.
-  As more functional units are included in FPGA architecture, it is impossible to auto-generate these functional units [3].
-  Therefore, FPGA-Verilog/SPICE requires users to provide their customized Verilog/SPICE netlists. A sample Verilog/SPICE netlist of a 1-bit adder can be found in the directory SpiceNetlists in the released package.
+  As more functional units are included in FPGA architecture, it is impossible to auto-generate these functional units.
+  Therefore, FPGA-Verilog/SPICE requires users to provide their customized Verilog/SPICE netlists.
 
-  The information of input and output buffer should be clearly specified according to the customized Verilog/SPICE netlist! The existence of input/output buffers will influence the decision in creating testbenches, which may leads to larger errors in power analysis.
+.. note:: Examples can be found in hard_logic_example_link_
 
-Instructions of defining design parameters:
+.. _hard_logic_example_link: https://github.com/LNIS-Projects/OpenFPGA/tree/master/openfpga_flow/VerilogNetlists
 
-* **port:** two types of ports (``input`` and ``output``) should be defined. If the user provides a user-defined Verilog/SPICE netlist, the bandwidth of ports should be defined to the same as the Verilog/SPICE netlist.
+.. note::  The information of input and output buffer should be clearly specified according to the customized Verilog/SPICE netlist! The existence of input/output buffers will influence the decision in creating SPICE testbenches, which may leads to larger errors in power analysis.
+
+1-bit Full Adder Example
+````````````````````````
+
+.. code-block:: xml
+
+  <circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="adder.sp" verilog_netlist="adder.v">
+    <design_technology type="cmos"/>
+    <input_buffer exist="true" circuit_model_name="inv1x"/>
+    <output_buffer exist="true" circuit_model_name="inv1x"/>
+    <port type="input" prefix="a" size="1"/>
+    <port type="input" prefix="b" size="1"/>
+    <port type="input" prefix="cin" size="1"/>
+    <port type="output" prefix="cout" size="1"/>
+    <port type="output" prefix="sumout" size="1"/>
+  </circuit_model>
 
 Routing Wire Segments
 ~~~~~~~~~~~~~~~~~~~~~
 
-FPGA-Verilog/SPICE provides two types of Verilog/SPICE models for the wire segments in FPGA architecture:
+FPGA architecture requires two type of  wire segments:
 
-	* One type is called ``wire``, which targets the local wires inside the logic blocks. The wire has one input and one output, directly connecting the output of a driver and the input of the downstream unit, respectively
-	* The other type is called ``chan_wire``, especially targeting the channel wires. The channel wires have one input and two outputs, one of which is connected to the inputs of Connection Boxes while the other is connected to the inputs of Switch Boxes. Two outputs are created because from the view of layout, the inputs of Connection Boxes are typically connected to the middle point of channel wires, which has less parasitic resistances and capacitances than connected to the ending point.
+  - ``wire``, which targets the local wires inside the logic blocks. The wire has one input and one output, directly connecting the output of a driver and the input of the downstream unit, respectively
+  - ``chan_wire``, especially targeting the channel wires. The channel wires have one input and two outputs, one of which is connected to the inputs of Connection Boxes while the other is connected to the inputs of Switch Boxes. Two outputs are created because from the view of layout, the inputs of Connection Boxes are typically connected to the middle point of channel wires, which has less parasitic resistances and capacitances than connected to the ending point.
+
+Template
+````````
 
 .. code-block:: xml
 
-  <circuit_model type="string" name="string" prefix="string" netlist="string"/>
+  <circuit_model type="wire|cham_wire" name="<string>" prefix="<string>" spice_netlist="<string>" verilog_netlist="<string>"/>
     <design_technology type="cmos"/>
-    <input_buffer exist="string" circuit_model_name="string"/>
-    <output_buffer exist="string" circuit_model_name="string"/>
-    <port type="input" prefix="string" size="int"/>
-    <port type="output" prefix="string" size="int"/>
-    <wire_param model_type="string" res_val="float" cap_val="float" level="int"/>
+    <input_buffer exist="<string>" circuit_model_name="<string>"/>
+    <output_buffer exist="<string>" circuit_model_name="<string>"/>
+    <port type="input" prefix="<string>" size="<int>"/>
+    <port type="output" prefix="<string>" size="<int>"/>
+    <wire_param model_type="<string>" R="<float>" C="<float>" num_level="<int>"/>
   </circuit_model>
 
 .. note:: FPGA-Verilog/SPICE can auto-generate the Verilog/SPICE model for wires while also allows users to provide their customized Verilog/SPICE netlists.
 
-  The information of input and output buffer should be clearly specified according to the customized netlist! The existence of input/output buffers will influence the decision in creating testbenches, which may leads to larger errors in power analysis.
+.. note:: The information of input and output buffer should be clearly specified according to the customized netlist! The existence of input/output buffers will influence the decision in creating testbenches, which may leads to larger errors in power analysis.
 
-Instructions of defining design parameters:
+.. option:: <wire_param model_type="<string>" R="<float>" C="<float>" num_level="<int>"/>
 
-* **type:** can be [``wire`` | ``chan_wire``]. The Verilog/SPICE model wire targets the local wire inside the logic block while the chan_wire targets the channel wires in global routing.
+  - ``model_type="pi|T"`` Specify the type of RC models for this wire segement. Currently, OpenFPGA supports the π-type and T-type multi-level RC models.
+  - ``R="<float>"`` Specify the total resistance of the wire
+  - ``C="<float>"`` Specify the total capacitance of the wire.
+  - ``num_level="<int>"`` Specify the number of levels of the RC wire model.
 
-* **port:** two types of ports (``input`` and ``output``) should be defined. If the user provides an customized Verilog/SPICE netlist, the bandwidth of ports should be defined to the same as the Verilog/SPICE netlist.
+.. note:: wire parameters are essential for FPGA-SPICE to accurately model wire parasitics
 
-* **wire_param:**
-
-	* **model_type:** can be [``pi`` | ``T``], corresponding to the π-type and T-type RC wire models.
-	* **res_val:** specify the total resistance of the wire
-	* **cap_val:** specify the total capacitance of the wire.
-	* **level:** specify the number of levels of the RC wire model.
-
-**Chan-Wire example**
+Routing Track Wire Example
+``````````````````````````
 
 :numref:`fig_wire` depicts the modeling for a length-2 channel wire.
 
 .. _fig_wire:
 
 .. figure:: ./figures/wire.png
-   :scale: 100%
+   :scale: 80%
    :alt: map to buried treasure
 
    An example of a length-2 channel wire modeling
@@ -589,46 +728,45 @@ The code describing this wire is:
   <circuit_model type="chan_wire" name="segment0" prefix="chan_wire"/>
     <design_technology type="cmos"/>
     <port type="input" prefix="mux_out" size="1"/>
-    <port type="output" prefix="cb_sb" size="2"/>
+    <port type="output" prefix="cb_sb" size="1"/>
     <wire_param model_type="pi" res_val="103.84" cap_val="13.80e-15" level="1"/>
   </circuit_model>
 
-**This example shows**
-	* How to use the ``wire_param`` for a π-type RC wire model
-	* How to use this circuit_model to auto-generate the Verilog/SPICE netlist
+This example shows
+  - A routing track wire has 1 input and output 
+  - The routing wire will be modelled as a 1-level π-type RC wire model with a total resistance of 103.84Ohm and a total capacitance of 13.89fF
 
 I/O pads
 ~~~~~~~~
 
+Template
+````````
+
 .. code-block:: xml
 
-  <circuit_model type="iopads" name="string" prefix="string" netlist="string"/>
+  <circuit_model type="iopad" name="<string>" prefix="<string>" spice_netlist="<string>" verilog_netlist="<string>"/>
     <design_technology type="cmos"/>
-    <input_buffer exist="string" circuit_model_name="string"/>
-    <output_buffer exist="string" circuit_model_name="string"/>
-    <port type="input" prefix="string" size="int"/>
-    <port type="output" prefix="string" size="int"/>
-    <port type="sram" prefix="string" size="int" mode_select="true|false" 
-	circuit_model_name="string" default_val="int"/>
+    <input_buffer exist="<string>" circuit_model_name="<string>"/>
+    <output_buffer exist="<string>" circuit_model_name="<string>"/>
+    <port type="input" prefix="<string>" size="<int>"/>
+    <port type="output" prefix="<string>" size="<int>"/>
+    <port type="sram" prefix="<string>" size="<int>" mode_select="<bool>" circuit_model_name="<string>" default_val="<int>"/>
   </circuit_model>
 
 .. note::  The circuit designs of I/O pads are highly dependent on the technology node and well optimized by engineers.
   Therefore, FPGA-Verilog/SPICE requires users to provide their customized Verilog/SPICE/Verilog netlists. A sample Verilog/SPICE netlist of an I/O pad can be found in the directory SpiceNetlists in the released package.
 
-  The information of input and output buffer should be clearly specified according to the customized netlist! The existence of input/output buffers will influence the decision in creating testbenches, which may leads to larger errors in power analysis.
+.. note:: The information of input and output buffer should be clearly specified according to the customized netlist! The existence of input/output buffers will influence the decision in creating testbenches, which may leads to larger errors in power analysis.
 
-Instructions of defining design parameters:
+I/O Pad Example
+```````````````
 
-* **port:** four types of ports (``input``, ``output``, ``inout`` and ``sram``) should be defined. If the user provides a user-defined Verilog/SPICE netlist, the bandwidth of ports should be defined to the same as the Verilog/SPICE netlist.
-
-**IO-pad example**
-
-:numref:`fig_iopad` depicts an IO-Pad.
+:numref:`fig_iopad` depicts an I/O pad.
 
 .. _fig_iopad:
 
 .. figure:: ./figures/iopad.png
-   :scale: 100%
+   :scale: 50%
    :alt: IO-Pad symbol
 
    An example of an IO-Pad
@@ -637,16 +775,19 @@ The code describing this IO-Pad is:
 
 .. code-block:: xml
 
-  <circuit_model type="iopad" name="iopad" prefix="iopad" verilog_netlist="io.v">
+  <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="io.sp" verilog_netlist="io.v">
+    <design_technology type="cmos"/>
+    <input_buffer exist="true" circuit_model_name="INVTX1"/>
+    <output_buffer exist="true" circuit_model_name="INVTX1"/>
+    <pass_gate_logic circuit_model_name="TGATE"/>
     <port type="inout" prefix="pad" size="1"/>
-    <port type="sram" prefix="dir" size="1" circuit_model_name="scff"/>
-    <port type="input" prefix="data_in" size="1"/>
-    <port type="input" prefix="zin" size="1" is_global="true"/>
-    <port type="output" prefix="data out" size="1"/>
+    <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="ccff" default_val="1"/>
+    <port type="input" prefix="outpad" size="1"/>
+    <port type="output" prefix="inpad" size="1"/>
   </circuit_model>
 
-**This example shows**
-
-	* The association of the verilog netlist file ``io.v``
-	* The inout pad port_type, which means as inout as output.
-	* The instantiation of a SCFF as sram
+This example shows
+  - A general purpose I/O cell defined in Verilog netlist ``io.sp`` and SPICE netlist ``io.sp`` 
+  - The I/O cell has an ``inout`` port as the bi-directional port
+  - The directionality of I/O can be controlled by a configuration-chain flip-flop defined in circuit model ``ccff``
+  - If unused, the I/O cell have be configured to '1'

From 089cc5e86ecd71b7f872de7d2a3fc0fbf6db1e70 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 10 Mar 2020 16:51:50 -0600
Subject: [PATCH 290/645] update documentation on circuit model annotation on
 VPR architecture

---
 docs/source/arch_lang/annotate_vpr_arch.rst | 194 +++++++++-----------
 docs/source/arch_lang/circuit_library.rst   |  18 +-
 2 files changed, 102 insertions(+), 110 deletions(-)

diff --git a/docs/source/arch_lang/annotate_vpr_arch.rst b/docs/source/arch_lang/annotate_vpr_arch.rst
index 25b0e5d3e..205cfe84e 100644
--- a/docs/source/arch_lang/annotate_vpr_arch.rst
+++ b/docs/source/arch_lang/annotate_vpr_arch.rst
@@ -4,23 +4,16 @@ Bind circuit modules to VPR architecture
 ----------------------------------------
 Each defined circuit model should be linked to an FPGA module defined in the original part of architecture descriptions. It helps FPGA-circuit creating the circuit netlists for logic/routing blocks. Since the original part lacks such support, we create a few XML properties to link to Circuit models.
 
-SRAM
-~~~~
-
-To link the defined circuit model of SRAM into the FPGA architecture description, a new line in XML format should be added under the XML node device. The new XML node is named as sram, which defines the area of an SRAM and the name of the circuit model to be linked. An example is shown as follows:
+Configuration Protocol
+~~~~~~~~~~~~~~~~~~~~~~
 
 .. code-block:: xml
 
-  <sram area=�int� circuit_model_name=�string�>
+  <configuration_protocol>
+    <organization type="<string>" circuit_model_name="<string>"/>
+  </configuration_protocol>
 
-  <sram>
-    <spice organization="string" circuit_model_name="scff"/>
-    <verilog organization="string" circuit_model_name="scff"/>
-  </sram>
-
-* **area:** is expressed in terms of the number of minimum width transistors. The SRAM area defined in this line is used in the area estimation of global routing multiplexers. circuit_model_name should match the name of the circuit model that has been defined under XML node module_circuit_model. The type of the linked circuit model should be sram.
-
-* **organization:** [scan-chain|memory_bank|standalone], is the type of configuration circuits.
+ - ``type="scan_chain|memory_bank|standalone"`` Specify the type of configuration circuits.
 
 :numref:`fig_sram` illustrates an example where a memory organization using memory decoders and 6-transistor SRAMs.
 
@@ -32,19 +25,12 @@ To link the defined circuit model of SRAM into the FPGA architecture description
  
    Example of a memory organization using memory decoders 
 
-.. note:: Currently circuit only supports standalone memory organization.
+.. note:: Currently FPGA-SPICE only supports standalone memory organization.
 
 .. note:: Currently RRAM-based FPGA only supports memory-bank organization for Verilog Generator.
 
-Here is an example.
-
-.. code-block:: xml
-
-  <sram area=�4� circuit_model_name=�sram6T�>
-
-
-Switch Boxes
-~~~~~~~~~~~~
+Switch Blocks
+~~~~~~~~~~~~~
 
 Original VPR architecture description contains an XML node called switchlist under which all the multiplexers of switch blocks are described.
 To link a defined circuit model to a multiplexer in the switch blocks, a new XML property circuit_model_name should be added to the descriptions.
@@ -53,28 +39,27 @@ Here is an example:
 
 .. code-block:: xml
 
-  <switchlist>
-    <switch type=�mux� name=�string� R=�float� Cin=�float� Cout=�float� Tdel=�float� mux_trans_size=�float� buf_size=�float� circuit_model_name=�string�/>
-  </switchlist>
+  <switch_block>
+    <switch type="mux" name="<string>" circuit_model_name="<string>"/>
+  </switch_block>
 
-* **circuit_model_name:** should match a circuit model whose type is mux defined under module_circuit_models.
+ - ``circuit_model_name="<string>"`` should match a circuit model whose type is ``mux`` defined in :ref:`circuit_library`.
 
 
 Connection Blocks
 ~~~~~~~~~~~~~~~~~
 
-To link the defined circuit model of the multiplexer to the Connection Blocks, a circuit_model_name should be added to the definition of Connection Blocks switches.  However, the original architecture descriptions do not offer a switch description for connection boxes as they do for the switch blocks.
-Therefore, FPGA-circuit requires a new XML node called **cblock** under the root XML node architecture, where a switch for connection blocks can be defined.
+To link the defined circuit model of the multiplexer to the Connection Blocks, a ``circuit_model_name`` should be annotated to the definition of Connection Blocks switches.  
 
 Here is the example:
 
 .. code-block:: xml
 
-  <cblock>
-    <switch type=�mux� name=�string� R=�float� Cin=�float� Cout=�float� Tdel=�float� mux_trans_size=�float� buf_size=�float� circuit_model_name=�string�/>
-  </cblock>
+  <connection_block>
+    <switch type="ipin_cblock" name="<string>" circuit_model_name="<string>"/>
+  </connection_block>
 
-* **circuit_model_name:** should match a circuit model whose type is mux defined under module_circuit_models.
+ - ``circuit_model_name="<string>"`` should match a circuit model whose type is ``mux`` defined in :ref:`circuit_library`.
 
 Channel Wire Segments
 ~~~~~~~~~~~~~~~~~~~~~
@@ -84,10 +69,10 @@ Similar to the Switch Boxes and Connection Blocks, the channel wire segments in
 .. code-block:: xml
 
   <segmentlist>
-    <segment freq=�float� length=�int� type=�string� Rmetal=�float� Cmetal=�float� circuit_model_name=�string�/>
+    <segment name="<string>" circuit_model_name="<string>"/>
   </segmentlist>
 
-* circuit_model_name: should match a circuit model whose type is chan_wire defined under module_circuit_models.
+ - ``circuit_model_name="<string>"`` should match a circuit model whose type is ``chan_wire`` defined in :ref:`circuit_library`.
 
 Primitive Blocks inside Multi-mode Configurable Logic Blocks
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -97,85 +82,86 @@ Each primitive block, i.e., the leaf ``pb_types``, should be linked to a valid c
 The ``circuit_model_name`` should match the given name of a ``circuit_model`` defined by users.
 
 .. code-block:: xml
+
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle" physical_mode_name="physical"/>
+    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="0"/>
+    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
+    <!-- Binding operating pb_type to physical pb_type -->
+    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="1" physical_pb_type_index_factor="0.5">
+      <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:4]"/>
+      <port name="out" physical_mode_port="lut5_out" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="0">
+      <!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:5]"/>
+      <port name="out" physical_mode_port="lut6_out"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
   
-  <!-- Multi-mode BLE -->
-  <pb_type name="ble" num_pb="10" physical_mode_name="ble_phy"/>
-    <!-- Physical implementation of BLE shown in Fig. :ref:`` --> 
-    <mode name="ble_phy" disabled_in_packing="true"/>
-      <!-- Define a 6-input LUT in BLE and link it to circuit model -->
-      <pb_type name="flut6_phy" circuit_model_name="frac_lut6">
-        <input name="in" num_pins="6"/>
-        <output name="lut4_out" num_pins="4"/>
-        <output name="lut5_out" num_pins="2"/>
-        <output name="lut6_out" num_pins="1"/>
-      </pb_type>
-      <pb_type name="lut4_phy" circuit_model_name="lut4">
-        <input name="in" num_pins="4"/>
-        <output name="out" num_pins="1"/>
-      </pb_type>
-      <pb_type name="adder_phy" num_pb="2" circuit_model_name="adder">
-        <input name="a" num_pins="1"/>
-        <input name="b" num_pins="1"/>
-        <input name="cin" num_pins="1"/>
-        <output name="cout" num_pins="1"/>
-        <output name="sumout" num_pins="1"/>
-      </pb_type>
-      <pb_type name="ff_phy" num_pb="2" circuit_model_name="dff">
-        <input name="D" num_pins="1"/>
-        <output name="Q" num_pins="1"/>
-        <clock name="clk" num_pins="1"/>
-      </pb_type>
-      <interconnect>
-      <!-- Routing multiplexers are omitted in this example. -->
-      </interconnect>
-    </mode>
-    <!-- Arithmetic mode of BLE shown in Fig. 2(b)-->
-    <mode name="flut4_arithmetic"/>
-      <pb_type name="flut4_arith" num_pb="4"/>
-        <!-- Define a virtual 4-input LUT in BLE and link it to physical 6-input LUT defined at LINE 6 -->
-        <pb_type name="lut4" mode_bits="01" physical_pb_type_name="flut6_phy">
-          <!-- Define an input port and link it to its physical port defined at LINE 7 -->
-          <input name="in" num_pins="4" physical_mode_pin="in[3:0]"/>
-          <!-- Define an output port and link it to its physical port defined at LINE 8 -->
-          <output name="out" num_pins="1" physical_mode_pin="lut4_out"/>
-        </pb_type>
-        <pb_type name="adder" num_pb="2" physical_pb_type_name="adder_phy">
-          <input name="a" num_pins="1" physical_mode_pin="a"/>
-          <input name="b" num_pins="1" physical_mode_pin="b"/>
-          <input name="cin" num_pins="1" physical_mode_pin="cin"/>
-          <output name="cout" num_pins="1" physical_mode_pin="cout"/>
-          <output name="sumout" num_pins="1" physical_mode_pin="sumout"/>
-        </pb_type>
-        <pb_type name="ff" num_pb="2" physical_pb_type_name="ff_phy">
-          <input name="D" num_pins="1" physical_mode_pin="D"/>
-          <output name="Q" num_pins="1" physical_mode_pin="Q"/>
-          <clock name="clk" num_pins="1" physical_mode_pin="clk"/>
-        </pb_type>
-        <interconnect>
-        <!-- Routing multiplexers are omitted in this example. Full details can be found in [21] -->
-        </interconnect>
-      </pb_type>
-    </mode>
-  <!-- More operating modes can be defined -->
-  </pb_type>
+.. option:: <pb_type name="<string>" physical_mode_name="<string>">
 
-* **physical_mode_name:** tell the name of the mode that describes the physical implementation of the configurable block. This is critical in modeling actual circuit designs and architecture of an FPGA. Typically, only one physical_mode should be specified for each multi-mode ``pb_type``.
+  Specify a physical mode for multi-mode ``pb_type`` defined in VPR architecture.
 
-* **idle_mode_name:** tell the name of the mode that the ``pb_type`` is configured to be by default. This is critical in building circuit netlists for unused logic blocks.
+  .. note:: This should be applied to non-primitive ``pb_type``, i.e., ``pb_type`` have child ``pb_type``.
 
-* **circuit_model_name:** should match a circuit model defined under ``module_circuit_models``. The ``circuit_model_name`` is mandatory for every leaf ``pb_type`` in a physical_mode ``pb_type``. For the interconnection type direct, the type of the linked circuit model should be wire. For multiplexers, the type of linked circuit model should be ``mux``. For complete, the type of the linked circuit model can be either ``mux`` or ``wire``, depending on the case.
+  - ``name="<string>"`` specifiy the full name of a ``pb_type`` in the hierarchy of VPR architecture.
 
-* **mode_bits** specifies the configuration bits for the ``circuit_model`` when operating at an operating mode. The length of ``mode_bits`` should match the ``port`` size defined in ``circuit_model``. The ``mode_bits`` should be derived from circuit designs while users are responsible for its correctness. FPGA-Bitstreamm will add the ``mode_bits`` during bitstream generation.
+  - ``physical_mode_name="<string>"`` Specify the name of the mode that describes the physical implementation of the configurable block. This is critical in modeling actual circuit designs and architecture of an FPGA. Typically, only one ``physical_mode`` should be specified for each multi-mode ``pb_type``.
 
-* **physical_pb_type_name** creates the link on ``pb_type`` between operating and physical modes. This syntax is mandatory for every leaf ``pb_type`` in an operating mode ``pb_type``. It should be a valid name of leaf ``pb_type`` in physical mode.   
+.. note:: OpenFPGA will infer the physical mode for a single-mode ``pb_type`` defined in VPR architecture
 
-* **physical_pb_type_index_factor** aims to align the indices for ``pb_type`` between operating and physical modes, especially when an operating mode contains multiple ``pb_type`` (``num_pb``>1) that are linked to the same physical ``pb_type``. When ``physical_pb_type_name`` is larger than 1, the  index of ``pb_type`` will be multipled by the given factor. 
+.. option:: <pb_type name="<string>" physical_pb_type_name="<string>" circuit_model_name="<string>" 
+  mode_bits="<int>" physical_pb_type_index_factor="<float>" physical_pb_type_index_offset="<int>">
 
-* **physical_pb_type_index_offset** aims to align the indices for ``pb_type`` between operating and physical modes, especially when an operating mode contains multiple ``pb_type`` (``num_pb``>1) that are linked to the same physical ``pb_type``. When ``physical_pb_type_name`` is larger than 1, the  index of ``pb_type`` will be shifted by the given factor. 
+  Specify the physical implementation for a primitive ``pb_type`` in VPR architecture
 
-* **physical_mode_pin** creates the linke on ``port`` of ``pb_type`` between operating and physical modes. This syntax is mandatory for every leaf ``pb_type`` in an operating mode ``pb_type``. It should be a valid ``port`` name of leaf ``pb_type`` in physical mode and the port size should also match. 
+  .. note:: This should be applied to primitive ``pb_type``, i.e., ``pb_type`` have no children.
 
-* **physical_mode_pin_rotate_offset** aims to align the pin indices for ``port`` of ``pb_type`` between operating and physical modes, especially when an operating mode contains multiple ``pb_type`` (``num_pb``>1) that are linked to the same physical ``pb_type``. When ``physical_mode_pin_rotate_offset`` is larger than zero, the pin index of ``pb_type`` (whose index is large than 1) will be shifted by the given offset. 
+  - ``name="<string>"`` specifiy the full name of a ``pb_type`` in the hierarchy of VPR architecture.
+
+  - ``physical_pb_type_name=<string>`` creates the link on ``pb_type`` between operating and physical modes. This syntax is mandatory for every primitive ``pb_type`` in an operating mode ``pb_type``. It should be a valid name of primitive ``pb_type`` in physical mode.   
+
+  - ``circuit_model_name="<string>"`` Specify a circuit model to implement a ``pb_type`` in VPR architecture. The ``circuit_model_name`` is mandatory for every primitive``pb_type`` in a physical_mode ``pb_type``.
+
+  - ``mode_bits="<int>"`` Specify the configuration bits for the ``circuit_model`` when operating at an operating mode. The length of ``mode_bits`` should match the ``port`` size defined in ``circuit_model``. The ``mode_bits`` should be derived from circuit designs while users are responsible for its correctness. FPGA-Bitstreamm will add the ``mode_bits`` during bitstream generation.
+
+  - ``physical_pb_type_index_factor="<float>"`` aims to align the indices for ``pb_type`` between operating and physical modes, especially when an operating mode contains multiple ``pb_type`` (``num_pb``>1) that are linked to the same physical ``pb_type``. When ``physical_pb_type_name`` is larger than 1, the  index of ``pb_type`` will be multipled by the given factor. 
+
+  - ``physical_pb_type_index_offset=<int>`` aims to align the indices for ``pb_type`` between operating and physical modes, especially when an operating mode contains multiple ``pb_type`` (``num_pb``>1) that are linked to the same physical ``pb_type``. When ``physical_pb_type_name`` is larger than 1, the  index of ``pb_type`` will be shifted by the given factor. 
+
+.. option:: <interconnect name="<string>" circuit_model_name="<string>">
+
+  - ``name="<string>"`` specifiy the name of a ``interconnect`` in VPR architecture. Different from ``pb_type``, hierarchical name is not required here.
+
+  - ``circuit_model_name="<string>"`` For the interconnection type direct, the type of the linked circuit model should be wire. For multiplexers, the type of linked circuit model should be ``mux``. For complete, the type of the linked circuit model can be either ``mux`` or ``wire``, depending on the case.
+
+.. option:: <port name="<string>" physical_mode_port="<string>" physical_mode_pin_rotate_offset="<int>"/>
+
+   Link a port of an operating ``pb_type`` to a port of a physical ``pb_type``
+
+  - ``name="<string>"`` specifiy the name of a ``port`` in VPR architecture. Different from ``pb_type``, hierarchical name is not required here.
+
+  - ``physical_mode_pin="<string>" creates the link of ``port`` of ``pb_type`` between operating and physical modes. This syntax is mandatory for every primitive ``pb_type`` in an operating mode ``pb_type``. It should be a valid ``port`` name of leaf ``pb_type`` in physical mode and the port size should also match. 
+
+  - ``physical_mode_pin_rotate_offset="<int>"`` aims to align the pin indices for ``port`` of ``pb_type`` between operating and physical modes, especially when an operating mode contains multiple ``pb_type`` (``num_pb``>1) that are linked to the same physical ``pb_type``. When ``physical_mode_pin_rotate_offset`` is larger than zero, the pin index of ``pb_type`` (whose index is large than 1) will be shifted by the given offset. 
 
 .. note::
   It is highly recommended that only one physical mode is defined for a multi-mode configurable block. Try not to use nested physical mode definition. This will ease the debugging and lead to clean XML description. 
diff --git a/docs/source/arch_lang/circuit_library.rst b/docs/source/arch_lang/circuit_library.rst
index b28acafea..52d906fea 100644
--- a/docs/source/arch_lang/circuit_library.rst
+++ b/docs/source/arch_lang/circuit_library.rst
@@ -250,18 +250,30 @@ A circuit model may consist of a number of ports. The port list is mandatory in
 
   - ``type="input|output|sram|clock"`` Specify the type of the port, i.e., the directionality and usage. For programmable modules, such as multiplexers and LUTs, SRAM ports MUST be defined. For registers, such as FFs and memory banks, clock ports MUST be defined.
 
+    .. note:: ``sram`` and ``clock`` ports are considered as inputs in terms of directionality
+
   - ``prefix="<string>"`` the name of the port to appear in the autogenerated netlists. Each port will be shown as ``<prefix>[i]`` in Verilog/SPICE netlists.
 
+    .. note:: if the circuit model is binded to a ``pb_type`` in VPR architecture, ``prefix`` must match the port name defined in ``pb_type``
+
   - ``lib_name="<string>"`` the name of the port defined in standard cells or customized cells. If not specified, this attribute will be the same as ``prefix``.
 
+    .. note:: if the circuit model comes from a standard cell library, using ``lib_name`` is recommended. This is because 
+      - the port names defined in ``pb_type`` are very diffrerent from the standard cells
+      - the port sequence is very different 
+
   - ``size="<int>"`` bandwidth of the port. MUST be larger than zero.
 
   - ``default_val="<int>"`` Specify default logic value for a port, which is used as the initial logic value of this port in testbench generation. Can be either 0 or 1. We assume each pin of this port has the same default value.
 
   - ``circuit_model_name="<string>"`` Specify the name of the circuit model which is connected to this port.
 
+    .. note:: ``circuit_model_name`` is only valid when the type of this port is ``sram``.
+
   - ``mode_select="true|false"`` Specify if this port controls the mode switching in a configurable logic block. This is due to that a configurable logic block can operate in different modes, which is controlled by SRAM bits.
 
+    .. note:: ``mode_select`` is only valid when the type of this port is ``sram``.
+
   - ``is_global="true|false"`` can be either ``true`` or ``false``. Specify if this port is a global port, which will be routed globally. Note that when multiple global ports are defined with the same name, these global ports will be short-wired together.
 
   - ``is_set="true|false"`` Specify if this port controls a set signal. All the set ports are connected to global set voltage stimuli in testbenches.
@@ -270,12 +282,6 @@ A circuit model may consist of a number of ports. The port list is mandatory in
 
   - ``is_config_enable="true|false"`` Specify if this port controls a configuration-enable signal. Only valid when ``is_global`` is ``true``. This port is only enabled during FPGA configuration, and always disabled during FPGA operation. All the ``config_enable`` ports are connected to global configuration-enable voltage stimuli in testbenches.
 
-.. note:: ``sram`` and ``clock`` ports are considered as inputs in terms of directionality
-
-.. note:: ``circuit_model_name`` is only valid when the type of this port is ``sram``.
-
-.. note:: ``mode_select`` is only valid when the type of this port is ``sram``.
-
 .. note:: ``is_set``, ``is_reset`` and ``is_config_enable`` are only valid when ``is_global`` is ``true``. 
 
 .. note::  Different types of ``circuit_model`` have different XML syntax, with which users can highly customize their circuit topologies. See refer to examples of :ref:``circuit_model_example`` for more details.

From 0da6f00af5b115a96ba75d191d567e48ee4c6e8f Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 10 Mar 2020 17:29:35 -0600
Subject: [PATCH 291/645] start reworking the openfpga tool documentation

---
 docs/source/fpga_bitstream/command_line_usage.rst | 4 ++--
 docs/source/fpga_bitstream/file_organization.rst  | 2 +-
 docs/source/fpga_bitstream/index.rst              | 2 ++
 docs/source/fpga_spice/command_line_usage.rst     | 4 ++--
 docs/source/fpga_spice/customize_subckt.rst       | 2 +-
 docs/source/fpga_spice/file_organization.rst      | 2 +-
 docs/source/fpga_spice/index.rst                  | 3 +++
 docs/source/fpga_spice/spice_simulation.rst       | 2 +-
 docs/source/fpga_verilog/command_line_usage.rst   | 4 ++--
 docs/source/fpga_verilog/file_organization.rst    | 2 +-
 docs/source/fpga_verilog/func_verify.rst          | 2 +-
 docs/source/fpga_verilog/index.rst                | 2 ++
 docs/source/fpga_verilog/sc_flow.rst              | 2 +-
 13 files changed, 20 insertions(+), 13 deletions(-)

diff --git a/docs/source/fpga_bitstream/command_line_usage.rst b/docs/source/fpga_bitstream/command_line_usage.rst
index 278bee494..43fffe97e 100644
--- a/docs/source/fpga_bitstream/command_line_usage.rst
+++ b/docs/source/fpga_bitstream/command_line_usage.rst
@@ -1,5 +1,5 @@
-Command-line Options for FPGA Bitstream Generator
-=================================================
+Command-line Options
+~~~~~~~~~~~~~~~~~~~~
 
 All the command line options of FPGA-Bitstream can be shown by calling the help menu of VPR. Here are all the FPGA-Verilog-related options that you can find:
 
diff --git a/docs/source/fpga_bitstream/file_organization.rst b/docs/source/fpga_bitstream/file_organization.rst
index 1cc152d40..c8476d1f9 100644
--- a/docs/source/fpga_bitstream/file_organization.rst
+++ b/docs/source/fpga_bitstream/file_organization.rst
@@ -1,5 +1,5 @@
 Bistream Output File Format
-============================
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 FPGA-Bitstream can generate two types of bitstreams:
 * Generic bitstreams, where configuration bits are organized out-of-order in a database. We output the generic bitstream to a XML format, which is easy to debug. As shown in the following XML code, configuration bits are organized block by block, where each block could be a LUT, a routing multiplexer `etc`. Each ``bitstream_block`` includes two sets of information: 
diff --git a/docs/source/fpga_bitstream/index.rst b/docs/source/fpga_bitstream/index.rst
index 6380cc322..9fb992ace 100644
--- a/docs/source/fpga_bitstream/index.rst
+++ b/docs/source/fpga_bitstream/index.rst
@@ -1,3 +1,5 @@
+FPGA-Bitstream
+--------------
 .. _fpga_bitstream:
    FPGA-Bitstream
  
diff --git a/docs/source/fpga_spice/command_line_usage.rst b/docs/source/fpga_spice/command_line_usage.rst
index 129c05e05..e7c261ab3 100644
--- a/docs/source/fpga_spice/command_line_usage.rst
+++ b/docs/source/fpga_spice/command_line_usage.rst
@@ -1,5 +1,5 @@
-Command-line Options for FPGA SPICE Generator
-=================================================
+Command-line Options
+~~~~~~~~~~~~~~~~~~~~
 All the command line options of FPGA-SPICE can be shown by calling the help menu of VPR. Here are all the FPGA-SPICE-related options that you can find:
 
 FPGA-SPICE Supported Options::
diff --git a/docs/source/fpga_spice/customize_subckt.rst b/docs/source/fpga_spice/customize_subckt.rst
index fca30912f..e62d3578b 100644
--- a/docs/source/fpga_spice/customize_subckt.rst
+++ b/docs/source/fpga_spice/customize_subckt.rst
@@ -1,5 +1,5 @@
 Create Customized SPICE Modules
-===============================
+-------------------------------
 To make sure the customized SPICE netlists can be correctly included in FPGA-SPICE, the following rules should be fully respected:
 
 1.    The customized SPICE netlists could contain multiple sub-circuits but the names of these sub-circuits should not be conflicted with any reserved words.. Here is an example of defining a sub-circuit in SPICE netlists. The <subckt_name> should be a unique one, which should not be conflicted with any reserved words.
diff --git a/docs/source/fpga_spice/file_organization.rst b/docs/source/fpga_spice/file_organization.rst
index 4a099bc95..f9a2f8575 100644
--- a/docs/source/fpga_spice/file_organization.rst
+++ b/docs/source/fpga_spice/file_organization.rst
@@ -1,5 +1,5 @@
 Hierarchy of SPICE Output Files
-===============================
+-------------------------------
 
 All the generated SPICE netlists are located in the <spice_dir> as you specify in the command-line options.
 Under the <spice_dir>, FPGA-SPICE creates a number of folders:  include, subckt, lut_tb, dff_tb, grid_tb, pb_mux_tb, cb_mux_tb, sb_mux_tb, top_tb, results. Under the <spice_dir>, FPGA-SPICE also creates a shell script called run_hspice_sim.sh, which run all the simulations for all the testbenches.
diff --git a/docs/source/fpga_spice/index.rst b/docs/source/fpga_spice/index.rst
index c9c04568a..f09b1bea0 100644
--- a/docs/source/fpga_spice/index.rst
+++ b/docs/source/fpga_spice/index.rst
@@ -1,7 +1,10 @@
+FPGA-SPICE
+----------
 .. _fpga_spice:
    FPGA-SPICE
  
 .. toctree::
+   :maxdepth: 2
   
    command_line_usage
 
diff --git a/docs/source/fpga_spice/spice_simulation.rst b/docs/source/fpga_spice/spice_simulation.rst
index f0aa7e2d0..29173d0b8 100644
--- a/docs/source/fpga_spice/spice_simulation.rst
+++ b/docs/source/fpga_spice/spice_simulation.rst
@@ -1,5 +1,5 @@
 Run SPICE simulation
-====================
+--------------------
 
 * Simulation results 
 
diff --git a/docs/source/fpga_verilog/command_line_usage.rst b/docs/source/fpga_verilog/command_line_usage.rst
index 656b2ecef..2e963319d 100644
--- a/docs/source/fpga_verilog/command_line_usage.rst
+++ b/docs/source/fpga_verilog/command_line_usage.rst
@@ -1,5 +1,5 @@
-Command-line Options for FPGA-Verilog Generator
-=================================================
+Command-line Options
+~~~~~~~~~~~~~~~~~~~~
 
 All the command line options of FPGA-Verilog can be shown by calling the help menu of VPR. Here are all the FPGA-Verilog-related options that you can find:
 
diff --git a/docs/source/fpga_verilog/file_organization.rst b/docs/source/fpga_verilog/file_organization.rst
index 0c223a822..181be2295 100644
--- a/docs/source/fpga_verilog/file_organization.rst
+++ b/docs/source/fpga_verilog/file_organization.rst
@@ -1,5 +1,5 @@
 Hierarchy of Verilog Output Files
-=================================
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 All the generated Verilog Netlists are located in the <verilog_dir>/SRC as you specify in the command-line options. Under the <verilog_dir>/SRC, FPGA-Verilog creates the top file name_top.v and some folders: lb (logic blocks), routing and sub_modules. 
 
diff --git a/docs/source/fpga_verilog/func_verify.rst b/docs/source/fpga_verilog/func_verify.rst
index cbb8af96c..a21a01c1e 100644
--- a/docs/source/fpga_verilog/func_verify.rst
+++ b/docs/source/fpga_verilog/func_verify.rst
@@ -1,5 +1,5 @@
 Perform Functionality Verification
-==================================
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 If the --fpga_verilog_print_modelsim_autodeck option is selected, it is possible to directly generate scripts for Modelsim. Inside of the Verilog directory specified with --fpga_verilog_dir can be found name_runsim.tcl scripts which perform the functional verification onto the FPGA generated. 
 
diff --git a/docs/source/fpga_verilog/index.rst b/docs/source/fpga_verilog/index.rst
index 2ea55c478..db8740fa0 100644
--- a/docs/source/fpga_verilog/index.rst
+++ b/docs/source/fpga_verilog/index.rst
@@ -1,3 +1,5 @@
+FPGA-Verilog
+------------
 .. _fpga_verilog:
    FPGA-Verilog
  
diff --git a/docs/source/fpga_verilog/sc_flow.rst b/docs/source/fpga_verilog/sc_flow.rst
index 03a9069fe..f89d71db2 100644
--- a/docs/source/fpga_verilog/sc_flow.rst
+++ b/docs/source/fpga_verilog/sc_flow.rst
@@ -1,5 +1,5 @@
 From Verilog to Layout
-======================
+~~~~~~~~~~~~~~~~~~~~~~
 
 The generated Verilog code can be used through a semi-custom design flow to generate the layout.
 

From 9f743f7f4ed3d42fae3b1c7128b9a6415280d5bb Mon Sep 17 00:00:00 2001
From: Xifan Tang <tangxifan@gmail.com>
Date: Tue, 10 Mar 2020 20:54:42 -0600
Subject: [PATCH 292/645] add openfpga shell documentation

---
 docs/source/index.rst                         |   2 +
 docs/source/openfpga_shell/index.rst          |  14 ++
 .../openfpga_shell/launch_openfpga_shell.rst  |  21 ++
 .../openfpga_shell/openfpga_commands.rst      | 184 ++++++++++++++++++
 .../source/openfpga_shell/openfpga_script.rst |  72 +++++++
 5 files changed, 293 insertions(+)
 create mode 100644 docs/source/openfpga_shell/index.rst
 create mode 100644 docs/source/openfpga_shell/launch_openfpga_shell.rst
 create mode 100644 docs/source/openfpga_shell/openfpga_commands.rst
 create mode 100644 docs/source/openfpga_shell/openfpga_script.rst

diff --git a/docs/source/index.rst b/docs/source/index.rst
index 34beae468..d3452b771 100644
--- a/docs/source/index.rst
+++ b/docs/source/index.rst
@@ -27,6 +27,8 @@ Welcome to OpenFPGA's documentation!
    :maxdepth: 2
    :caption: OpenFPGA Tools
 
+   openfpga_shell/index
+
    fpga_spice/index
 
    fpga_verilog/index
diff --git a/docs/source/openfpga_shell/index.rst b/docs/source/openfpga_shell/index.rst
new file mode 100644
index 000000000..0aa515e23
--- /dev/null
+++ b/docs/source/openfpga_shell/index.rst
@@ -0,0 +1,14 @@
+OpenFPGA Interface
+------------------
+
+.. _openfpga_shell:
+   OpenFPGA Shell
+ 
+.. toctree::
+   :maxdepth: 2
+
+   launch_openfpga_shell
+
+   openfpga_script
+  
+   openfpga_commands
diff --git a/docs/source/openfpga_shell/launch_openfpga_shell.rst b/docs/source/openfpga_shell/launch_openfpga_shell.rst
new file mode 100644
index 000000000..3ef6e9fb5
--- /dev/null
+++ b/docs/source/openfpga_shell/launch_openfpga_shell.rst
@@ -0,0 +1,21 @@
+.. _launch_openfpga_shell:
+
+Launch OpenFPGA Shell
+---------------------
+
+OpenFPGA employs a shell-like user interface, in order to integrate all the tools in a well-modularized way.
+Currently, OpenFPGA shell is an unified platform to call ``vpr``, ``FPGA-Verilog``, ``FPGA-Bitstream``, ``FPGA-SDC`` and ``FPGA-SPICE``.
+To launch OpenFPGA shell, users can choose two modes.
+
+.. option::	--interactive or -i
+
+  Launch OpenFPGA in interactive mode where users type-in command by command and get runtime results
+
+.. option::	--file or -f
+
+  Launch OpenFPGA in script mode where users write commands in scripts and FPGA will execute them
+
+.. option::	--help or -h
+	
+  Show the help desk
+
diff --git a/docs/source/openfpga_shell/openfpga_commands.rst b/docs/source/openfpga_shell/openfpga_commands.rst
new file mode 100644
index 000000000..79c95d248
--- /dev/null
+++ b/docs/source/openfpga_shell/openfpga_commands.rst
@@ -0,0 +1,184 @@
+.. _openfpga_commands:
+
+Commands
+--------
+
+As OpenFPGA integrates various tools, the commands are categorized into different classes:
+
+Basic Commands
+~~~~~~~~~~~~~~
+
+.. option:: help
+
+  Show help desk to list all the available commands
+
+.. option:: exit
+
+  Exit OpenFPGA shell
+
+VPR
+~~~
+
+.. option:: vpr
+  
+  OpenFPGA allows users to call ``vpr`` in the standard way as documented in vtr project.
+
+Setup OpenFPGA
+~~~~~~~~~~~~~~
+
+.. option:: read_openfpga_arch
+
+  Read the XML architecture file required by OpenFPGA
+
+  - ``--file`` or ``-f`` Specify the file name 
+
+  - ``--verbose`` Show verbose log
+
+.. option:: write_openfpga_arch
+
+  Write the OpenFPGA XML architecture file to a file
+
+  - ``--file`` or ``-f`` Specify the file name 
+
+  - ``--verbose`` Show verbose log
+
+.. option:: link_openfpga_arch
+
+  Annotate the OpenFPGA architecture to VPR data base
+
+  - ``--activity_file`` Specify the signal activity file
+
+  - ``--sort_gsb_chan_node_in_edges`` Sort the edges for the routing tracks in General Switch Blocks (GSBs). Strongly recommand to turn this on for uniquifying the routing modules
+
+  - ``--verbose`` Show verbose log
+
+.. option:: check_netlist_naming_conflict 
+
+  Check and correct any naming conflicts in the BLIF netlist
+  This is strongly recommended. Otherwise, the outputted Verilog netlists may not be compiled successfully.
+
+  .. note:: This command may be deprecated in future when merged to VPR upstream
+  
+  - ``--fix`` Apply fix-up to the names that violate the syntax
+
+  - ``--report <.xml>`` Report the naming fix-up to a log file
+
+.. option:: pb_pin_fixup
+
+  Apply fix-up to clustering nets based on routing results
+  This is strongly recommended. Otherwise, the bitstream generation may be wrong
+
+  .. note:: This command may be deprecated in future when merged to VPR upstream
+  
+  - ``--verbose`` Show verbose log
+   
+.. option:: lut_truth_table_fixup
+
+  Apply fix-up to Look-Up Table truth tables based on packing results
+
+  .. note:: This command may be deprecated in future when merged to VPR upstream
+
+  - ``--verbose`` Show verbose log
+  
+.. option:: build_fabric
+
+  Build the module graph. This is a must-run command before launching FPGA-Verilog, FPGA-Bitstream, FPGA-SDC and FPGA-SPICE
+
+  - ``--compress_routing`` Enable compression on routing architecture modules. Strongly recommend this as it will minimize the number of routing modules to be outputted. It can reduce the netlist size significantly.
+  
+  - ``--duplicate_grid_pin`` Enable pin duplication on grid modules. This is optional unless ultra-dense layout generation is needed
+
+  - ``--verbose`` Show verbose log
+  
+FPGA-Bitstream
+~~~~~~~~~~~~~~
+
+.. option:: repack
+
+  Repack the netlist to physical pbs
+  This must be done before bitstream generator and testbench generation
+  Strongly recommend it is done after all the fix-up have been applied
+   
+  - ``--verbose`` Show verbose log
+
+.. option:: build_architecture_bitstream
+
+  Decode VPR implementing results to an fabric-independent bitstream database 
+  
+  - ``--file`` or ``-f`` Output the fabric-independent bitstream to an XML file
+  
+  - ``--verbose`` Show verbose log
+
+.. option:: build_fabric_bitstream
+
+  Reorganize the bitstream database for a specific FPGA fabric
+
+  - ``--verbose`` Show verbose log
+  
+FPGA-Verilog
+~~~~~~~~~~~~
+
+.. option:: write_fabric_verilog
+
+  Write the Verilog netlist for FPGA fabric based on module graph
+
+  - ``--file`` or ``-f`` Specify the output directory for the Verilog netlists
+
+  - ``--explict_port_mapping`` Use explict port mapping when writing the Verilog netlists
+
+  - ``--include_timing`` Output timing information to Verilog netlists for primitive modules
+ 
+  - ``--include_signal_init`` Output signal initialization to Verilog netlists for primitive modules
+
+  - ``--support_icarus_simulator`` Output Verilog netlists with syntax that iVerilog simulatorcan accept
+
+  - ``--print_user_defined_template`` Output a template Verilog netlist for all the user-defined ``circuit models`` in :ref:`circuit_library`. This aims to help engineers to check what is the port sequence required by top-level Verilog netlists
+
+  - ``--verbose`` Show verbose log
+
+.. option:: write_verilog_testbench
+ 
+  Write the Verilog testbench for FPGA fabric
+
+  - ``--file`` or ``-f`` The output directory for all the testbench netlists. We suggest the use of same output directory as fabric Verilog netlists
+
+  - ``--reference_benchmark_file_path`` Must specify the reference benchmark Verilog file if you want to output any testbenches
+
+  - ``--print_top_testbench`` Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+
+  - ``--print_formal_verification_top_netlist`` Generate a top-level module which can be used in formal verification
+
+  - ``--print_preconfig_top_testbench`` Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+
+  - ``--print_simulation_ini`` Output an exchangeable simulation ini file, which is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+
+FPGA-SDC
+~~~~~~~~
+
+.. option:: write_pnr_sdc
+ 
+  Write the SDC files for PnR backend
+  
+  - ``--file`` or ``-f`` Specify the output directory for SDC files
+
+  - ``--constrain_global_port`` Constrain all the global ports of FPGA fabric
+
+  - ``--constrain_grid`` Constrain all the grids of FPGA fabric
+
+  - `--constrain_sb`` Constrain all the switch blocks of FPGA fabric
+
+  - ``--constrain_cb`` Constrain all the connection blocks of FPGA fabric
+
+  - ``--constrain_configurable_memory_outputs`` Constrain all the outputs of configurable memories of FPGA fabric
+
+  - ``--constrain_routing_multiplexer_outputs`` Constrain all the outputs of routing multiplexer of FPGA fabric
+
+  - ``--constrain_switch_block_outputs`` Constrain all the outputs of switch blocks of FPGA fabric
+  
+  - ``--verbose`` Enable verbose output
+
+.. option:: write_analysis_sdc
+
+  Write the SDC to run timing analysis for a mapped FPGA fabric
+
+  - ``--file`` or ``-f`` Specify the output directory for SDC files
diff --git a/docs/source/openfpga_shell/openfpga_script.rst b/docs/source/openfpga_shell/openfpga_script.rst
new file mode 100644
index 000000000..dde33a044
--- /dev/null
+++ b/docs/source/openfpga_shell/openfpga_script.rst
@@ -0,0 +1,72 @@
+.. _openfpga_script_format:
+
+OpenFPGA Script Format
+----------------------
+
+OpenFPGA accepts a simplified tcl-like script format.
+Commented lines are started with `#`.
+Note that comments can be added inline or as a new line.
+
+The following is an example.
+
+.. code-block:: python
+
+  # Run VPR for the s298 design
+  vpr ./test_vpr_arch/k6_frac_N10_40nm.xml ./test_blif/and.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml
+  
+  # Read OpenFPGA architecture definition
+  read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+  
+  # Write out the architecture XML as a proof
+  #write_openfpga_arch -f ./arch_echo.xml
+  
+  # Annotate the OpenFPGA architecture to VPR data base
+  link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose
+  
+  # Check and correct any naming conflicts in the BLIF netlist
+  check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+  
+  # Apply fix-up to clustering nets based on routing results
+  pb_pin_fixup --verbose
+  
+  # Apply fix-up to Look-Up Table truth tables based on packing results
+  lut_truth_table_fixup #--verbose
+  
+  # Build the module graph 
+  #  - Enabled compression on routing architecture modules
+  #  - Enable pin duplication on grid modules 
+  build_fabric --compress_routing --duplicate_grid_pin #--verbose
+  
+  # Repack the netlist to physical pbs
+  # This must be done before bitstream generator and testbench generation
+  # Strongly recommend it is done after all the fix-up have been applied
+  repack #--verbose
+  
+  # Build the bitstream 
+  #  - Output the fabric-independent bitstream to a file
+  build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
+  
+  # Build fabric-dependent bitstream
+  build_fabric_bitstream --verbose
+  
+  # Write the Verilog netlist for FPGA fabric
+  #  - Enable the use of explicit port mapping in Verilog netlist
+  write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
+  
+  # Write the Verilog testbench for FPGA fabric
+  #  - We suggest the use of same output directory as fabric Verilog netlists
+  #  - Must specify the reference benchmark file if you want to output any testbenches
+  #  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+  #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+  #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+  write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
+  
+  # Write the SDC files for PnR backend
+  #  - Turn on every options here 
+  write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
+  
+  # Write the SDC to run timing analysis for a mapped FPGA fabric
+  write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
+  
+  # Finish and exit OpenFPGA
+  exit

From b941ac8a4abd8ba917ebecf4a9e0ea1eeca27b0a Mon Sep 17 00:00:00 2001
From: Xifan Tang <tangxifan@gmail.com>
Date: Tue, 10 Mar 2020 20:58:00 -0600
Subject: [PATCH 293/645] remove deprecated options

---
 .../fpga_bitstream/command_line_usage.rst     | 14 -----
 docs/source/fpga_bitstream/index.rst          |  2 -
 .../fpga_verilog/command_line_usage.rst       | 55 -------------------
 docs/source/fpga_verilog/index.rst            |  2 -
 4 files changed, 73 deletions(-)
 delete mode 100644 docs/source/fpga_bitstream/command_line_usage.rst
 delete mode 100644 docs/source/fpga_verilog/command_line_usage.rst

diff --git a/docs/source/fpga_bitstream/command_line_usage.rst b/docs/source/fpga_bitstream/command_line_usage.rst
deleted file mode 100644
index 43fffe97e..000000000
--- a/docs/source/fpga_bitstream/command_line_usage.rst
+++ /dev/null
@@ -1,14 +0,0 @@
-Command-line Options
-~~~~~~~~~~~~~~~~~~~~
-
-All the command line options of FPGA-Bitstream can be shown by calling the help menu of VPR. Here are all the FPGA-Verilog-related options that you can find:
-
-FPGA-Verilog Supported Option::	
-	
-	--fpga_bitstream_generator
-
-.. csv-table:: Commmand-line Option of FPGA-Bitstream
-   :header: "Command Options", "Description"
-   :widths: 15, 30
-
-   "--fpga_bitstream_generator", "Turn on the FPGA-Bitstream and output a .bitstream file containing FPGA configuration."
diff --git a/docs/source/fpga_bitstream/index.rst b/docs/source/fpga_bitstream/index.rst
index 9fb992ace..6e1123899 100644
--- a/docs/source/fpga_bitstream/index.rst
+++ b/docs/source/fpga_bitstream/index.rst
@@ -6,8 +6,6 @@ FPGA-Bitstream
 .. toctree::
    :maxdepth: 2
   
-   command_line_usage
-
    file_organization
  
    
diff --git a/docs/source/fpga_verilog/command_line_usage.rst b/docs/source/fpga_verilog/command_line_usage.rst
deleted file mode 100644
index 2e963319d..000000000
--- a/docs/source/fpga_verilog/command_line_usage.rst
+++ /dev/null
@@ -1,55 +0,0 @@
-Command-line Options
-~~~~~~~~~~~~~~~~~~~~
-
-All the command line options of FPGA-Verilog can be shown by calling the help menu of VPR. Here are all the FPGA-Verilog-related options that you can find:
-
-FPGA-Verilog Supported Options::	
-	
-	--fpga_verilog
-	--fpga_verilog_dir <directory_path_of_dumped_verilog_files>
-	--fpga_verilog_include_timing
-	--fpga_verilog_include_signal_init
-	--fpga_verilog_print_modelsim_autodeck <modelsim_ini_path>
-	--fpga_verilog_print_top_testbench 
-	--fpga_verilog_print_autocheck_top_testbench <reference_verilog_file_path>
-	--fpga_verilog_print_formal_verification_top_netlist
-	--fpga_verilog_include_icarus_simulator
-
-
-.. csv-table:: Commmand-line Options of FPGA-Verilog
-   :header: "Command Options", "Description"
-   :widths: 15, 30
-
-   "--fpga_verilog", "Turn on the FPGA-Verilog."
-   "--fpga_verilog_dir <dir_path>", "Specify the directory that all the Verilog files will be outputted to <dir_path> is the destination directory."
-   "--fpga_verilog_include_timing", "Includes the timings found in the XML file."
-   "--fpga_verilog_init_sim", "Initializes the simulation for ModelSim."
-   "--fpga_verilog_print_modelsim_autodeck", "Generates the scripts necessary to the ModelSim simulation."
-   "--fpga_verilog_modelsim_ini_path <string>", "Gives the path for the .ini necessary to ModelSim."
-   "--fpga_verilog_print_top_testbench", "Print the full-chip-level testbench for the FPGA. Determines the type of autodeck."
-   "--fpga_verilog_print_top_auto_testbench \
-   <path_to_the_verilog_benchmark>", "Prints the testbench associated with the given benchmark. Determines the type of autodeck."
-   "--fpga_verilog_dir <dir_path>", "Specify the directory where all the Verilog files will be outputted to. <dir_path> is the destination directory."
-   "--fpga_verilog_include_timing", "Includes the timings found in the XML architecture description file."
-   "--fpga_verilog_include_signal_init", "Set all nets to random value to be close of a real power-on case"
-   "--fpga_verilog_print_modelsim_autodeck <modelsim_ini_path>", "Generates the scripts necessary to the ModelSim simulation and specify the path to modelsim.ini file."
-   "--fpga_verilog_print_top_testbench", "Prints the full-chip-level testbench for the FPGA, which includes programming phase and operationg phase (random patterns)."
-   "--fpga_verilog_print_autocheck_top_testbench \
-   <reference_verilog_file_path>", "Prints a testbench stimulating the generated FPGA and the initial benchmark to compare stimuli responses, which includes programming phase and operationg phase (random patterns)"
-   "--fpga_verilog_print_formal_verification_top_netlist", "Prints a Verilog top file compliant with formal verification tools. With this top file the FPGA is initialy programmed. It also prints a testbench with random patterns, which can be manually or automatically check regarding previous options."
-   "--fpga_verilog_include_icarus_simulator", "Activates waveforms .vcd file generation and simulation timeout, which are required for Icarus Verilog simulator"
-   "--fpga_verilog_print_input_blif_testbench", "Generates a Verilog test-bench to use with input blif file"
-   "--fpga_verilog_print_report_timing_tcl", "Generates tcl commands to run STA analysis with TO COMPLETE TOOL"
-   "--fpga_verilog_report_timing_rpt_path <path_to_generate_reports>", "Specifies path where report timing are written"
-   "--fpga_verilog_print_sdc_pnr", "Generates SDC constraints to PNR"
-   "--fpga_verilog_print_sdc_analysis", "Generates SDC to run timing analysis in PNR tool"
-   "--fpga_verilog_print_user_defined_template", "Generates a template of hierarchy modules and their port mapping"
-
-.. note:: The selected directory will contain the *Verilog top file* and three other folders. The folders are: 
-
-	* **sub_module:** contains each module verilog file and is more detailed in the next part *Verilog Output File Format*. 
-	* **routing:** contains the Verilog for the connection blocks and the switch boxes. 
-	* **lb:** contains the grids Verilog files.
-
-
-
diff --git a/docs/source/fpga_verilog/index.rst b/docs/source/fpga_verilog/index.rst
index db8740fa0..e9f93cdf5 100644
--- a/docs/source/fpga_verilog/index.rst
+++ b/docs/source/fpga_verilog/index.rst
@@ -6,8 +6,6 @@ FPGA-Verilog
 .. toctree::
    :maxdepth: 2
   
-   command_line_usage
-
    file_organization
  
    func_verify

From 1d766d2a70cf4b375dea15a618365da4a0b4d861 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 11 Mar 2020 10:22:30 -0600
Subject: [PATCH 294/645] minor format fix on documentation

---
 docs/source/arch_lang/annotate_vpr_arch.rst      |  8 ++++----
 docs/source/fpga_spice/index.rst                 |  3 +++
 docs/source/fpga_verilog/index.rst               |  1 +
 docs/source/openfpga_shell/openfpga_commands.rst | 11 +++++++----
 4 files changed, 15 insertions(+), 8 deletions(-)

diff --git a/docs/source/arch_lang/annotate_vpr_arch.rst b/docs/source/arch_lang/annotate_vpr_arch.rst
index 205cfe84e..ce570084d 100644
--- a/docs/source/arch_lang/annotate_vpr_arch.rst
+++ b/docs/source/arch_lang/annotate_vpr_arch.rst
@@ -13,7 +13,7 @@ Configuration Protocol
     <organization type="<string>" circuit_model_name="<string>"/>
   </configuration_protocol>
 
- - ``type="scan_chain|memory_bank|standalone"`` Specify the type of configuration circuits.
+- ``type="scan_chain|memory_bank|standalone"`` Specify the type of configuration circuits.
 
 :numref:`fig_sram` illustrates an example where a memory organization using memory decoders and 6-transistor SRAMs.
 
@@ -43,7 +43,7 @@ Here is an example:
     <switch type="mux" name="<string>" circuit_model_name="<string>"/>
   </switch_block>
 
- - ``circuit_model_name="<string>"`` should match a circuit model whose type is ``mux`` defined in :ref:`circuit_library`.
+- ``circuit_model_name="<string>"`` should match a circuit model whose type is ``mux`` defined in :ref:`circuit_library`.
 
 
 Connection Blocks
@@ -59,7 +59,7 @@ Here is the example:
     <switch type="ipin_cblock" name="<string>" circuit_model_name="<string>"/>
   </connection_block>
 
- - ``circuit_model_name="<string>"`` should match a circuit model whose type is ``mux`` defined in :ref:`circuit_library`.
+- ``circuit_model_name="<string>"`` should match a circuit model whose type is ``mux`` defined in :ref:`circuit_library`.
 
 Channel Wire Segments
 ~~~~~~~~~~~~~~~~~~~~~
@@ -72,7 +72,7 @@ Similar to the Switch Boxes and Connection Blocks, the channel wire segments in
     <segment name="<string>" circuit_model_name="<string>"/>
   </segmentlist>
 
- - ``circuit_model_name="<string>"`` should match a circuit model whose type is ``chan_wire`` defined in :ref:`circuit_library`.
+- ``circuit_model_name="<string>"`` should match a circuit model whose type is ``chan_wire`` defined in :ref:`circuit_library`.
 
 Primitive Blocks inside Multi-mode Configurable Logic Blocks
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/docs/source/fpga_spice/index.rst b/docs/source/fpga_spice/index.rst
index f09b1bea0..4cdffcc0f 100644
--- a/docs/source/fpga_spice/index.rst
+++ b/docs/source/fpga_spice/index.rst
@@ -1,5 +1,8 @@
 FPGA-SPICE
 ----------
+
+.. warning:: FPGA-SPICE has not been integrated to VPR8 version yet. Please the following tool guide is for VPR7 version now
+
 .. _fpga_spice:
    FPGA-SPICE
  
diff --git a/docs/source/fpga_verilog/index.rst b/docs/source/fpga_verilog/index.rst
index e9f93cdf5..85d278ae6 100644
--- a/docs/source/fpga_verilog/index.rst
+++ b/docs/source/fpga_verilog/index.rst
@@ -1,5 +1,6 @@
 FPGA-Verilog
 ------------
+
 .. _fpga_verilog:
    FPGA-Verilog
  
diff --git a/docs/source/openfpga_shell/openfpga_commands.rst b/docs/source/openfpga_shell/openfpga_commands.rst
index 79c95d248..edb2bf0ad 100644
--- a/docs/source/openfpga_shell/openfpga_commands.rst
+++ b/docs/source/openfpga_shell/openfpga_commands.rst
@@ -57,7 +57,7 @@ Setup OpenFPGA
   Check and correct any naming conflicts in the BLIF netlist
   This is strongly recommended. Otherwise, the outputted Verilog netlists may not be compiled successfully.
 
-  .. note:: This command may be deprecated in future when merged to VPR upstream
+  .. warning:: This command may be deprecated in future when it is merged to VPR upstream
   
   - ``--fix`` Apply fix-up to the names that violate the syntax
 
@@ -68,7 +68,7 @@ Setup OpenFPGA
   Apply fix-up to clustering nets based on routing results
   This is strongly recommended. Otherwise, the bitstream generation may be wrong
 
-  .. note:: This command may be deprecated in future when merged to VPR upstream
+  .. warning:: This command may be deprecated in future when it is merged to VPR upstream
   
   - ``--verbose`` Show verbose log
    
@@ -76,19 +76,22 @@ Setup OpenFPGA
 
   Apply fix-up to Look-Up Table truth tables based on packing results
 
-  .. note:: This command may be deprecated in future when merged to VPR upstream
+  .. warning:: This command may be deprecated in future when it is merged to VPR upstream
 
   - ``--verbose`` Show verbose log
   
 .. option:: build_fabric
 
-  Build the module graph. This is a must-run command before launching FPGA-Verilog, FPGA-Bitstream, FPGA-SDC and FPGA-SPICE
+  Build the module graph.
 
   - ``--compress_routing`` Enable compression on routing architecture modules. Strongly recommend this as it will minimize the number of routing modules to be outputted. It can reduce the netlist size significantly.
   
   - ``--duplicate_grid_pin`` Enable pin duplication on grid modules. This is optional unless ultra-dense layout generation is needed
 
   - ``--verbose`` Show verbose log
+
+  .. note:: This is a must-run command before launching FPGA-Verilog, FPGA-Bitstream, FPGA-SDC and FPGA-SPICE
+
   
 FPGA-Bitstream
 ~~~~~~~~~~~~~~

From 2a260a05aaafdf6eaf8071c34ebb81c6119dcc31 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 11 Mar 2020 10:40:59 -0600
Subject: [PATCH 295/645] add a microbenchmark `and_latch` to test LUTs in
 wired mode

---
 openfpga/test_blif/and_latch.act              |  5 ++
 openfpga/test_blif/and_latch.blif             | 11 ++++
 openfpga/test_blif/and_latch.v                | 23 ++++++++
 openfpga/test_script/and_k6_frac.openfpga     |  2 +-
 .../test_script/and_latch_k6_frac.openfpga    | 59 +++++++++++++++++++
 5 files changed, 99 insertions(+), 1 deletion(-)
 create mode 100644 openfpga/test_blif/and_latch.act
 create mode 100644 openfpga/test_blif/and_latch.blif
 create mode 100644 openfpga/test_blif/and_latch.v
 create mode 100644 openfpga/test_script/and_latch_k6_frac.openfpga

diff --git a/openfpga/test_blif/and_latch.act b/openfpga/test_blif/and_latch.act
new file mode 100644
index 000000000..8089a8969
--- /dev/null
+++ b/openfpga/test_blif/and_latch.act
@@ -0,0 +1,5 @@
+a 0.492800 0.201000
+b 0.502000 0.197200
+clk 0.500000 2.000000
+d 0.240200 0.171200
+c 0.240200 0.044100
diff --git a/openfpga/test_blif/and_latch.blif b/openfpga/test_blif/and_latch.blif
new file mode 100644
index 000000000..a1925fffa
--- /dev/null
+++ b/openfpga/test_blif/and_latch.blif
@@ -0,0 +1,11 @@
+# Benchmark "top" written by ABC on Wed Mar 11 10:36:28 2020
+.model top
+.inputs a b clk
+.outputs c d
+
+.latch c d  re clk 0
+
+.names a b c
+11 1
+
+.end
diff --git a/openfpga/test_blif/and_latch.v b/openfpga/test_blif/and_latch.v
new file mode 100644
index 000000000..893cdf7a4
--- /dev/null
+++ b/openfpga/test_blif/and_latch.v
@@ -0,0 +1,23 @@
+`timescale 1ns / 1ps
+
+module top(
+  clk,
+  a,
+  b,
+  c,
+  d);
+
+input wire clk;
+
+input wire a;
+input wire b;
+output wire c;
+output reg d;
+
+assign c = a & b;
+
+always @(posedge clk) begin
+  d <= c;
+end
+
+endmodule
diff --git a/openfpga/test_script/and_k6_frac.openfpga b/openfpga/test_script/and_k6_frac.openfpga
index 872af950d..63746cd71 100644
--- a/openfpga/test_script/and_k6_frac.openfpga
+++ b/openfpga/test_script/and_k6_frac.openfpga
@@ -1,4 +1,4 @@
-# Run VPR for the s298 design
+# Run VPR for the 'and' design
 vpr ./test_vpr_arch/k6_frac_N10_40nm.xml ./test_blif/and.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml
 
 # Read OpenFPGA architecture definition
diff --git a/openfpga/test_script/and_latch_k6_frac.openfpga b/openfpga/test_script/and_latch_k6_frac.openfpga
new file mode 100644
index 000000000..210bdcf28
--- /dev/null
+++ b/openfpga/test_script/and_latch_k6_frac.openfpga
@@ -0,0 +1,59 @@
+# Run VPR for the 'and_latch' design
+vpr ./test_vpr_arch/k6_frac_N10_40nm.xml ./test_blif/and_latch.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+
+# Write out the architecture XML as a proof
+#write_openfpga_arch -f ./arch_echo.xml
+
+# Annotate the OpenFPGA architecture to VPR data base
+link_openfpga_arch --activity_file ./test_blif/and_latch.act --sort_gsb_chan_node_in_edges #--verbose
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to clustering nets based on routing results
+pb_pin_fixup --verbose
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup #--verbose
+
+# Build the module graph 
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules 
+build_fabric --compress_routing --duplicate_grid_pin #--verbose
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream 
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here 
+write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
+
+# Finish and exit OpenFPGA
+exit

From 8e796f152f47bb5b6a93704f3c640dec5e5a2f10 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 11 Mar 2020 21:05:06 -0600
Subject: [PATCH 296/645] add comments to lb_router about how-to-use

---
 openfpga/src/repack/lb_router.h | 44 +++++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/openfpga/src/repack/lb_router.h b/openfpga/src/repack/lb_router.h
index c1d82ca1c..698dcc26f 100644
--- a/openfpga/src/repack/lb_router.h
+++ b/openfpga/src/repack/lb_router.h
@@ -25,6 +25,50 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
+/********************************************************************
+ * A connection-driven router for programmable logic blocks
+ * The router supports routing multiple nets on a LbRRGraph object
+ * which models the routing resources in a programmable logic block
+ *
+ * Note: 
+ *   - This router will not build/allocate a LbRRGraph object
+ *     Users must do it OUTSIDE this object!!!
+ *   - This router supports multiple sources for single net
+ *     which is more capable the original VPR lb_router
+ *
+ * How to use the router:
+ *
+ *  // Create your own routing resource graph 
+ *  LbRRGraph lb_rr_graph = <your_lb_rr_graph_builder>();
+ *
+ *  // Create a router object
+ *  LbRouter lb_router(lb_rr_graph);
+ *
+ *  // Add nets to be routed 
+ *  std::vector<LbRRNodeId> source_nodes = <find_your_source_node_in_your_lb_rr_graph>();
+ *  std::vector<LbRRNodeId> sink_nodes = <find_your_sink_node_in_your_lb_rr_graph>();
+ *  LbNetId net = lb_router.create_net_to_route(source_nodes, sink_nodes);
+ *  // Add more nets
+ *
+ *  // Initialize the modes to expand routing
+ *  // This is a must-do before running the router in the purpose of repacking!!!
+ *  lb_router.set_physical_pb_modes(lb_rr_graph, device_annotation); 
+ *
+ *  // Run the router 
+ *  bool route_success = lb_router.try_route(lb_rr_graph, atom_ctx.nlist, verbose);
+ *
+ *  // Check routing status 
+ *  if (true == route_success) {
+ *    // Succeed
+ *  }
+ *
+ *  // Read out routing results
+ *  // Here is an example to check which nodes are mapped to the 'net' created before
+ *  std::vector<LbRRNodeId> routed_nodes = lb_router.net_routed_nodes(net);
+ *
+ *******************************************************************/
+
+
 class LbRouter {
   public: /* Strong ids */
     struct net_id_tag;

From 17a1c61b9d0bd81eb718502ee01191e066233265 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 11 Mar 2020 21:10:16 -0600
Subject: [PATCH 297/645] minor change in variable names in lb_router

---
 openfpga/src/repack/lb_router.cpp             | 26 +++++++++----------
 .../k6_frac_N10_40nm_openfpga.xml             |  2 +-
 2 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/openfpga/src/repack/lb_router.cpp b/openfpga/src/repack/lb_router.cpp
index c1b67b804..faddbea8c 100644
--- a/openfpga/src/repack/lb_router.cpp
+++ b/openfpga/src/repack/lb_router.cpp
@@ -237,24 +237,24 @@ bool LbRouter::try_route(const LbRRGraph& lb_rr_graph,
     unsigned int inet;
     /* Iterate across all nets internal to logic block */
     for (inet = 0; inet < lb_net_ids_.size() && !is_impossible; inet++) {
-      NetId idx = NetId(inet);
-      if (is_skip_route_net(lb_rr_graph, lb_net_rt_trees_[idx])) {
+      NetId net_idx = NetId(inet);
+      if (is_skip_route_net(lb_rr_graph, lb_net_rt_trees_[net_idx])) {
         continue;
       }
 
-      commit_remove_rt(lb_rr_graph, lb_net_rt_trees_[idx], RT_REMOVE, mode_map);
-      free_net_rt(lb_net_rt_trees_[idx]);
-      lb_net_rt_trees_[idx] = nullptr;
-      add_source_to_rt(idx);
+      commit_remove_rt(lb_rr_graph, lb_net_rt_trees_[net_idx], RT_REMOVE, mode_map);
+      free_net_rt(lb_net_rt_trees_[net_idx]);
+      lb_net_rt_trees_[net_idx] = nullptr;
+      add_source_to_rt(net_idx);
 
       /* Route each sink of net */
-      for (unsigned int itarget = 1; itarget < lb_net_terminals_[idx].size() && !is_impossible; itarget++) {
+      for (unsigned int itarget = 1; itarget < lb_net_terminals_[net_idx].size() && !is_impossible; itarget++) {
         pq_.clear();
         /* Get lowest cost next node, repeat until a path is found or if it is impossible to route */
 
-        expand_rt(idx, idx);
+        expand_rt(net_idx, net_idx);
 
-        is_impossible = try_expand_nodes(atom_nlist, lb_rr_graph, idx, exp_node, itarget, mode_status_.expand_all_modes, verbosity);
+        is_impossible = try_expand_nodes(atom_nlist, lb_rr_graph, net_idx, exp_node, itarget, mode_status_.expand_all_modes, verbosity);
 
         if (is_impossible && !mode_status_.expand_all_modes) {
           mode_status_.try_expand_all_modes = true;
@@ -262,15 +262,15 @@ bool LbRouter::try_route(const LbRRGraph& lb_rr_graph,
           break;
         }
 
-        if (exp_node.node_index == lb_net_terminals_[idx][itarget]) {
+        if (exp_node.node_index == lb_net_terminals_[net_idx][itarget]) {
           /* Net terminal is routed, add this to the route tree, clear data structures, and keep going */
-          is_impossible = add_to_rt(lb_net_rt_trees_[idx], exp_node.node_index, idx);
+          is_impossible = add_to_rt(lb_net_rt_trees_[net_idx], exp_node.node_index, net_idx);
         }
 
         if (is_impossible) {
           VTR_LOG("Routing was impossible!\n");
         } else if (mode_status_.expand_all_modes) {
-          is_impossible = route_has_conflict(lb_rr_graph, lb_net_rt_trees_[idx]);
+          is_impossible = route_has_conflict(lb_rr_graph, lb_net_rt_trees_[net_idx]);
           if (is_impossible) {
             VTR_LOG("Routing was impossible due to modes!\n");
           }
@@ -288,7 +288,7 @@ bool LbRouter::try_route(const LbRRGraph& lb_rr_graph,
       }
 
       if (!is_impossible) {
-        commit_remove_rt(lb_rr_graph, lb_net_rt_trees_[idx], RT_COMMIT, mode_map);
+        commit_remove_rt(lb_rr_graph, lb_net_rt_trees_[net_idx], RT_COMMIT, mode_map);
         if (mode_status_.is_mode_conflict) {
           is_impossible = true;
         }
diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
index 9644530da..b750f9736 100644
--- a/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
@@ -218,7 +218,7 @@
     <pb_type name="clb.fle[n2_lut5].lut5inter.ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="1" physical_pb_type_index_factor="0.5">
       <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
       <port name="in" physical_mode_port="in[0:4]"/>
-      <port name="out" physical_mode_port="lut5_out" physical_mode_pin_rotate_offset="1"/>
+      <port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
     </pb_type>
     <pb_type name="clb.fle[n2_lut5].lut5inter.ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
     <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="0">

From cd50155e2931252d5fc2ff00e55eef572a831fcc Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 12 Mar 2020 10:24:38 -0600
Subject: [PATCH 298/645] rename variables in lb router

---
 openfpga/src/repack/lb_router.cpp | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/openfpga/src/repack/lb_router.cpp b/openfpga/src/repack/lb_router.cpp
index faddbea8c..e5d656686 100644
--- a/openfpga/src/repack/lb_router.cpp
+++ b/openfpga/src/repack/lb_router.cpp
@@ -248,13 +248,13 @@ bool LbRouter::try_route(const LbRRGraph& lb_rr_graph,
       add_source_to_rt(net_idx);
 
       /* Route each sink of net */
-      for (unsigned int itarget = 1; itarget < lb_net_terminals_[net_idx].size() && !is_impossible; itarget++) {
+      for (unsigned int isink = 1; isink < lb_net_terminals_[net_idx].size() && !is_impossible; isink++) {
         pq_.clear();
         /* Get lowest cost next node, repeat until a path is found or if it is impossible to route */
 
         expand_rt(net_idx, net_idx);
 
-        is_impossible = try_expand_nodes(atom_nlist, lb_rr_graph, net_idx, exp_node, itarget, mode_status_.expand_all_modes, verbosity);
+        is_impossible = try_expand_nodes(atom_nlist, lb_rr_graph, net_idx, exp_node, isink, mode_status_.expand_all_modes, verbosity);
 
         if (is_impossible && !mode_status_.expand_all_modes) {
           mode_status_.try_expand_all_modes = true;
@@ -262,7 +262,7 @@ bool LbRouter::try_route(const LbRRGraph& lb_rr_graph,
           break;
         }
 
-        if (exp_node.node_index == lb_net_terminals_[net_idx][itarget]) {
+        if (exp_node.node_index == lb_net_terminals_[net_idx][isink]) {
           /* Net terminal is routed, add this to the route tree, clear data structures, and keep going */
           is_impossible = add_to_rt(lb_net_rt_trees_[net_idx], exp_node.node_index, net_idx);
         }

From a1f19e776e4d259d81e0f0706b113555500069a5 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 12 Mar 2020 11:05:38 -0600
Subject: [PATCH 299/645] Add comments to lb router and extract a private
 function for routing a single net

---
 openfpga/src/repack/lb_router.cpp | 129 ++++++++++++++++++------------
 openfpga/src/repack/lb_router.h   |   7 ++
 2 files changed, 83 insertions(+), 53 deletions(-)

diff --git a/openfpga/src/repack/lb_router.cpp b/openfpga/src/repack/lb_router.cpp
index e5d656686..c37c59b74 100644
--- a/openfpga/src/repack/lb_router.cpp
+++ b/openfpga/src/repack/lb_router.cpp
@@ -202,6 +202,80 @@ void LbRouter::set_physical_pb_modes(const LbRRGraph& lb_rr_graph,
   }
 }
 
+bool LbRouter::try_route_net(const LbRRGraph& lb_rr_graph,
+                             const AtomNetlist& atom_nlist,
+                             const NetId& net_idx,
+                             t_expansion_node& exp_node,
+                             std::unordered_map<const t_pb_graph_node*, const t_mode*>& mode_map,
+                             const int& verbosity) {
+
+  bool is_impossible = false;
+
+  if (is_skip_route_net(lb_rr_graph, lb_net_rt_trees_[net_idx])) {
+    return true;
+  }
+
+  commit_remove_rt(lb_rr_graph, lb_net_rt_trees_[net_idx], RT_REMOVE, mode_map);
+  free_net_rt(lb_net_rt_trees_[net_idx]);
+  lb_net_rt_trees_[net_idx] = nullptr;
+  add_source_to_rt(net_idx);
+
+  /* Route each sink of net */
+  for (size_t isink = 1; isink < lb_net_terminals_[net_idx].size() && !is_impossible; ++isink) {
+    pq_.clear();
+    /* Get lowest cost next node, repeat until a path is found or if it is impossible to route */
+
+    expand_rt(net_idx, net_idx);
+
+    is_impossible = try_expand_nodes(atom_nlist, lb_rr_graph, net_idx, exp_node, isink, mode_status_.expand_all_modes, verbosity);
+
+    if (is_impossible && !mode_status_.expand_all_modes) {
+      mode_status_.try_expand_all_modes = true;
+      mode_status_.expand_all_modes = true;
+      break;
+    }
+
+    if (exp_node.node_index == lb_net_terminals_[net_idx][isink]) {
+      /* Net terminal is routed, add this to the route tree, clear data structures, and keep going */
+      is_impossible = add_to_rt(lb_net_rt_trees_[net_idx], exp_node.node_index, net_idx);
+    }
+
+    if (is_impossible) {
+      VTR_LOG("Routing was impossible!\n");
+    } else if (mode_status_.expand_all_modes) {
+      is_impossible = route_has_conflict(lb_rr_graph, lb_net_rt_trees_[net_idx]);
+      if (is_impossible) {
+        VTR_LOG("Routing was impossible due to modes!\n");
+      }
+    }
+
+    explore_id_index_++;
+    if (explore_id_index_ > 2000000000) {
+      /* overflow protection */
+      for (const LbRRNodeId& id : lb_rr_graph.nodes()) {
+        explored_node_tb_[id].explored_id = OPEN;
+        explored_node_tb_[id].enqueue_id = OPEN;
+        explore_id_index_ = 1;
+      }
+    }
+  }
+
+  /* If routing succeed so far, we will try to save(commit) results
+   * to route tree.
+   * During this process, we will check if there is any 
+   * nodes using different modes under the same pb_type
+   * If so, we have conflicts and routing is considered to be failure
+   */
+  if (!is_impossible) {
+    commit_remove_rt(lb_rr_graph, lb_net_rt_trees_[net_idx], RT_COMMIT, mode_map);
+    if (mode_status_.is_mode_conflict) {
+      is_impossible = true;
+    }
+  }
+
+  return !is_impossible;
+}
+
 bool LbRouter::try_route(const LbRRGraph& lb_rr_graph,
                          const AtomNetlist& atom_nlist,
                          const int& verbosity) {
@@ -238,60 +312,9 @@ bool LbRouter::try_route(const LbRRGraph& lb_rr_graph,
     /* Iterate across all nets internal to logic block */
     for (inet = 0; inet < lb_net_ids_.size() && !is_impossible; inet++) {
       NetId net_idx = NetId(inet);
-      if (is_skip_route_net(lb_rr_graph, lb_net_rt_trees_[net_idx])) {
-        continue;
-      }
 
-      commit_remove_rt(lb_rr_graph, lb_net_rt_trees_[net_idx], RT_REMOVE, mode_map);
-      free_net_rt(lb_net_rt_trees_[net_idx]);
-      lb_net_rt_trees_[net_idx] = nullptr;
-      add_source_to_rt(net_idx);
-
-      /* Route each sink of net */
-      for (unsigned int isink = 1; isink < lb_net_terminals_[net_idx].size() && !is_impossible; isink++) {
-        pq_.clear();
-        /* Get lowest cost next node, repeat until a path is found or if it is impossible to route */
-
-        expand_rt(net_idx, net_idx);
-
-        is_impossible = try_expand_nodes(atom_nlist, lb_rr_graph, net_idx, exp_node, isink, mode_status_.expand_all_modes, verbosity);
-
-        if (is_impossible && !mode_status_.expand_all_modes) {
-          mode_status_.try_expand_all_modes = true;
-          mode_status_.expand_all_modes = true;
-          break;
-        }
-
-        if (exp_node.node_index == lb_net_terminals_[net_idx][isink]) {
-          /* Net terminal is routed, add this to the route tree, clear data structures, and keep going */
-          is_impossible = add_to_rt(lb_net_rt_trees_[net_idx], exp_node.node_index, net_idx);
-        }
-
-        if (is_impossible) {
-          VTR_LOG("Routing was impossible!\n");
-        } else if (mode_status_.expand_all_modes) {
-          is_impossible = route_has_conflict(lb_rr_graph, lb_net_rt_trees_[net_idx]);
-          if (is_impossible) {
-            VTR_LOG("Routing was impossible due to modes!\n");
-          }
-        }
-
-        explore_id_index_++;
-        if (explore_id_index_ > 2000000000) {
-          /* overflow protection */
-          for (const LbRRNodeId& id : lb_rr_graph.nodes()) {
-            explored_node_tb_[id].explored_id = OPEN;
-            explored_node_tb_[id].enqueue_id = OPEN;
-            explore_id_index_ = 1;
-          }
-        }
-      }
-
-      if (!is_impossible) {
-        commit_remove_rt(lb_rr_graph, lb_net_rt_trees_[net_idx], RT_COMMIT, mode_map);
-        if (mode_status_.is_mode_conflict) {
-          is_impossible = true;
-        }
+      if (false == try_route_net(lb_rr_graph, atom_nlist, net_idx, exp_node, mode_map, verbosity)) {
+        is_impossible = true;
       }
     }
 
diff --git a/openfpga/src/repack/lb_router.h b/openfpga/src/repack/lb_router.h
index 698dcc26f..0d7d4b9af 100644
--- a/openfpga/src/repack/lb_router.h
+++ b/openfpga/src/repack/lb_router.h
@@ -320,6 +320,13 @@ class LbRouter {
                           const bool& try_other_modes,
                           const int& verbosity);
 
+    bool try_route_net(const LbRRGraph& lb_rr_graph,
+                       const AtomNetlist& atom_nlist,
+                       const NetId& net_idx,
+                       t_expansion_node& exp_node,
+                       std::unordered_map<const t_pb_graph_node*, const t_mode*>& mode_map,
+                       const int& verbosity);
+
   private :  /* Private validators */
     /** 
      * Validate if the rr_graph is the one we used to initialize the router 

From 689c50dff1bba28569dcffc8d04111c638a0a189 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 12 Mar 2020 11:36:31 -0600
Subject: [PATCH 300/645] label the routing status for each sink in lb_router

---
 openfpga/src/repack/lb_router.cpp | 45 +++++++++++++++++++++++--------
 1 file changed, 34 insertions(+), 11 deletions(-)

diff --git a/openfpga/src/repack/lb_router.cpp b/openfpga/src/repack/lb_router.cpp
index c37c59b74..80bb5a3f6 100644
--- a/openfpga/src/repack/lb_router.cpp
+++ b/openfpga/src/repack/lb_router.cpp
@@ -209,7 +209,8 @@ bool LbRouter::try_route_net(const LbRRGraph& lb_rr_graph,
                              std::unordered_map<const t_pb_graph_node*, const t_mode*>& mode_map,
                              const int& verbosity) {
 
-  bool is_impossible = false;
+  std::vector<bool> sink_routed(lb_net_terminals_[net_idx].size(), false);
+  sink_routed[0] = true; /* Deposite true for source node */
 
   if (is_skip_route_net(lb_rr_graph, lb_net_rt_trees_[net_idx])) {
     return true;
@@ -221,15 +222,28 @@ bool LbRouter::try_route_net(const LbRRGraph& lb_rr_graph,
   add_source_to_rt(net_idx);
 
   /* Route each sink of net */
-  for (size_t isink = 1; isink < lb_net_terminals_[net_idx].size() && !is_impossible; ++isink) {
+  for (size_t isink = 1; isink < lb_net_terminals_[net_idx].size(); ++isink) {
+    /* Check if last sink failed in routing
+     * If failed, the routing is not possible for this net
+     */
+    if (1 < isink) {
+      if (false == sink_routed[isink - 1]) {
+        break;
+      }
+    }
+
     pq_.clear();
     /* Get lowest cost next node, repeat until a path is found or if it is impossible to route */
 
     expand_rt(net_idx, net_idx);
 
-    is_impossible = try_expand_nodes(atom_nlist, lb_rr_graph, net_idx, exp_node, isink, mode_status_.expand_all_modes, verbosity);
+    /* If we managed to expand the nodes to the sink, routing for this sink is done.
+     * If not, we failed in routing.
+     * Therefore, the output of try_expand_nodes() is inverted
+     */
+    sink_routed[isink] = !try_expand_nodes(atom_nlist, lb_rr_graph, net_idx, exp_node, isink, mode_status_.expand_all_modes, verbosity);
 
-    if (is_impossible && !mode_status_.expand_all_modes) {
+    if (false == sink_routed[isink] && !mode_status_.expand_all_modes) {
       mode_status_.try_expand_all_modes = true;
       mode_status_.expand_all_modes = true;
       break;
@@ -237,14 +251,14 @@ bool LbRouter::try_route_net(const LbRRGraph& lb_rr_graph,
 
     if (exp_node.node_index == lb_net_terminals_[net_idx][isink]) {
       /* Net terminal is routed, add this to the route tree, clear data structures, and keep going */
-      is_impossible = add_to_rt(lb_net_rt_trees_[net_idx], exp_node.node_index, net_idx);
+      sink_routed[isink] = !add_to_rt(lb_net_rt_trees_[net_idx], exp_node.node_index, net_idx);
     }
 
-    if (is_impossible) {
+    if (false == sink_routed[isink]) {
       VTR_LOG("Routing was impossible!\n");
     } else if (mode_status_.expand_all_modes) {
-      is_impossible = route_has_conflict(lb_rr_graph, lb_net_rt_trees_[net_idx]);
-      if (is_impossible) {
+      sink_routed[isink] = !route_has_conflict(lb_rr_graph, lb_net_rt_trees_[net_idx]);
+      if (false == sink_routed[isink]) {
         VTR_LOG("Routing was impossible due to modes!\n");
       }
     }
@@ -260,20 +274,29 @@ bool LbRouter::try_route_net(const LbRRGraph& lb_rr_graph,
     }
   }
 
+  /* Check the routing status for all the sinks */
+  bool route_succeed = true;
+  for (const bool& sink_status : sink_routed) {
+    if (false == sink_status) {
+      route_succeed = false;
+      break;
+    }
+  }
+
   /* If routing succeed so far, we will try to save(commit) results
    * to route tree.
    * During this process, we will check if there is any 
    * nodes using different modes under the same pb_type
    * If so, we have conflicts and routing is considered to be failure
    */
-  if (!is_impossible) {
+  if (true == route_succeed) {
     commit_remove_rt(lb_rr_graph, lb_net_rt_trees_[net_idx], RT_COMMIT, mode_map);
     if (mode_status_.is_mode_conflict) {
-      is_impossible = true;
+      route_succeed = false;
     }
   }
 
-  return !is_impossible;
+  return route_succeed;
 }
 
 bool LbRouter::try_route(const LbRRGraph& lb_rr_graph,

From f1e8e784109c6ee1fe292bf5f3956ed8c0f252df Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 12 Mar 2020 11:47:42 -0600
Subject: [PATCH 301/645] minor code formatting

---
 openfpga/src/repack/lb_router.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/openfpga/src/repack/lb_router.cpp b/openfpga/src/repack/lb_router.cpp
index 80bb5a3f6..1098a8b46 100644
--- a/openfpga/src/repack/lb_router.cpp
+++ b/openfpga/src/repack/lb_router.cpp
@@ -212,7 +212,7 @@ bool LbRouter::try_route_net(const LbRRGraph& lb_rr_graph,
   std::vector<bool> sink_routed(lb_net_terminals_[net_idx].size(), false);
   sink_routed[0] = true; /* Deposite true for source node */
 
-  if (is_skip_route_net(lb_rr_graph, lb_net_rt_trees_[net_idx])) {
+  if (true == is_skip_route_net(lb_rr_graph, lb_net_rt_trees_[net_idx])) {
     return true;
   }
 

From c40675ca9d23426d01dd3986f49bdcd1f4fc5004 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 12 Mar 2020 11:55:25 -0600
Subject: [PATCH 302/645] minor code formatting

---
 openfpga/src/repack/lb_router.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/openfpga/src/repack/lb_router.cpp b/openfpga/src/repack/lb_router.cpp
index 1098a8b46..ac6d2a49d 100644
--- a/openfpga/src/repack/lb_router.cpp
+++ b/openfpga/src/repack/lb_router.cpp
@@ -243,7 +243,7 @@ bool LbRouter::try_route_net(const LbRRGraph& lb_rr_graph,
      */
     sink_routed[isink] = !try_expand_nodes(atom_nlist, lb_rr_graph, net_idx, exp_node, isink, mode_status_.expand_all_modes, verbosity);
 
-    if (false == sink_routed[isink] && !mode_status_.expand_all_modes) {
+    if (false == sink_routed[isink] && false == mode_status_.expand_all_modes) {
       mode_status_.try_expand_all_modes = true;
       mode_status_.expand_all_modes = true;
       break;
@@ -291,7 +291,7 @@ bool LbRouter::try_route_net(const LbRRGraph& lb_rr_graph,
    */
   if (true == route_succeed) {
     commit_remove_rt(lb_rr_graph, lb_net_rt_trees_[net_idx], RT_COMMIT, mode_map);
-    if (mode_status_.is_mode_conflict) {
+    if (true == mode_status_.is_mode_conflict) {
       route_succeed = false;
     }
   }

From f0b22aaa115682af36df60b04daaa73be3465f1a Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 12 Mar 2020 13:44:14 -0600
Subject: [PATCH 303/645] Make lb router support multiple sources to be routed

---
 openfpga/src/repack/lb_router.cpp | 254 +++++++++++++++++-------------
 openfpga/src/repack/lb_router.h   |  31 +++-
 2 files changed, 171 insertions(+), 114 deletions(-)

diff --git a/openfpga/src/repack/lb_router.cpp b/openfpga/src/repack/lb_router.cpp
index ac6d2a49d..1be68cc51 100644
--- a/openfpga/src/repack/lb_router.cpp
+++ b/openfpga/src/repack/lb_router.cpp
@@ -73,12 +73,14 @@ std::vector<LbRRNodeId> LbRouter::net_routed_nodes(const NetId& net) const {
 
   std::vector<LbRRNodeId> routed_nodes;
 
-  t_trace* rt_tree = lb_net_rt_trees_[net];
-  if (nullptr == rt_tree) {
-    return routed_nodes;
+  for (size_t isrc = 0; isrc < lb_net_sources_[net].size(); ++isrc) { 
+    t_trace* rt_tree = lb_net_rt_trees_[net][isrc];
+    if (nullptr == rt_tree) {
+      return routed_nodes;
+    }
+    /* Walk through the routing tree of the net */
+    rec_collect_trace_nodes(rt_tree, routed_nodes);  
   }
-  /* Walk through the routing tree of the net */
-  rec_collect_trace_nodes(rt_tree, routed_nodes);  
 
   return routed_nodes;  
 }
@@ -152,13 +154,12 @@ LbRouter::NetId LbRouter::create_net_to_route(const LbRRNodeId& source, const st
 
   /* Allocate other attributes */
   lb_net_atom_net_ids_.push_back(AtomNetId::INVALID());
-  lb_net_atom_pins_.emplace_back();
+  lb_net_atom_source_pins_.emplace_back();
+  lb_net_atom_sink_pins_.emplace_back();
   
-  std::vector<LbRRNodeId> net_terminals = terminals;
-  net_terminals.insert(net_terminals.begin(), source);
-
-  lb_net_terminals_.push_back(net_terminals);
-  lb_net_rt_trees_.push_back(nullptr);
+  lb_net_sources_.push_back(std::vector<LbRRNodeId>(1, source));
+  lb_net_sinks_.push_back(terminals);
+  lb_net_rt_trees_.push_back(std::vector<t_trace*>(1, nullptr));
 
   return net;
 }
@@ -170,8 +171,8 @@ void LbRouter::add_net_atom_net_id(const NetId& net, const AtomNetId& atom_net)
 
 void LbRouter::add_net_atom_pins(const NetId& net, const AtomPinId& src_pin, const std::vector<AtomPinId>& terminal_pins) {
   VTR_ASSERT(true == valid_net_id(net));
-  lb_net_atom_pins_[net] = terminal_pins;
-  lb_net_atom_pins_[net].insert(lb_net_atom_pins_[net].begin(), src_pin);
+  lb_net_atom_sink_pins_[net] = terminal_pins;
+  lb_net_atom_source_pins_[net] = std::vector<AtomPinId>(1, src_pin);
 }
 
 void LbRouter::set_physical_pb_modes(const LbRRGraph& lb_rr_graph,
@@ -209,67 +210,69 @@ bool LbRouter::try_route_net(const LbRRGraph& lb_rr_graph,
                              std::unordered_map<const t_pb_graph_node*, const t_mode*>& mode_map,
                              const int& verbosity) {
 
-  std::vector<bool> sink_routed(lb_net_terminals_[net_idx].size(), false);
-  sink_routed[0] = true; /* Deposite true for source node */
+  std::vector<bool> sink_routed(lb_net_sinks_[net_idx].size(), false);
 
-  if (true == is_skip_route_net(lb_rr_graph, lb_net_rt_trees_[net_idx])) {
-    return true;
-  }
+  for (size_t isrc = 0; isrc < lb_net_sources_[net_idx].size(); ++isrc) {
 
-  commit_remove_rt(lb_rr_graph, lb_net_rt_trees_[net_idx], RT_REMOVE, mode_map);
-  free_net_rt(lb_net_rt_trees_[net_idx]);
-  lb_net_rt_trees_[net_idx] = nullptr;
-  add_source_to_rt(net_idx);
+    if (true == is_skip_route_net(lb_rr_graph, lb_net_rt_trees_[net_idx][isrc])) {
+      return true;
+    }
 
-  /* Route each sink of net */
-  for (size_t isink = 1; isink < lb_net_terminals_[net_idx].size(); ++isink) {
-    /* Check if last sink failed in routing
-     * If failed, the routing is not possible for this net
-     */
-    if (1 < isink) {
-      if (false == sink_routed[isink - 1]) {
+    commit_remove_rt(lb_rr_graph, lb_net_rt_trees_[net_idx][isrc], RT_REMOVE, mode_map);
+    free_net_rt(lb_net_rt_trees_[net_idx][isrc]);
+    lb_net_rt_trees_[net_idx][isrc] = nullptr;
+    add_source_to_rt(net_idx, isrc);
+
+    /* Route each sink of net */
+    for (size_t isink = 0; isink < lb_net_sinks_[net_idx].size(); ++isink) {
+      /* Check if last sink failed in routing
+       * If failed, the routing is not possible for this net
+       */
+      if (0 < isink) {
+        if (false == sink_routed[isink - 1]) {
+          break;
+        }
+      }
+
+      pq_.clear();
+      /* Get lowest cost next node, repeat until a path is found or if it is impossible to route */
+
+      expand_rt(net_idx, net_idx, isrc);
+
+      /* If we managed to expand the nodes to the sink, routing for this sink is done.
+       * If not, we failed in routing.
+       * Therefore, the output of try_expand_nodes() is inverted
+       */
+      sink_routed[isink] = !try_expand_nodes(atom_nlist, lb_rr_graph, net_idx, exp_node, isrc, isink, mode_status_.expand_all_modes, verbosity);
+
+      if (false == sink_routed[isink] && false == mode_status_.expand_all_modes) {
+        mode_status_.try_expand_all_modes = true;
+        mode_status_.expand_all_modes = true;
         break;
       }
-    }
 
-    pq_.clear();
-    /* Get lowest cost next node, repeat until a path is found or if it is impossible to route */
-
-    expand_rt(net_idx, net_idx);
-
-    /* If we managed to expand the nodes to the sink, routing for this sink is done.
-     * If not, we failed in routing.
-     * Therefore, the output of try_expand_nodes() is inverted
-     */
-    sink_routed[isink] = !try_expand_nodes(atom_nlist, lb_rr_graph, net_idx, exp_node, isink, mode_status_.expand_all_modes, verbosity);
-
-    if (false == sink_routed[isink] && false == mode_status_.expand_all_modes) {
-      mode_status_.try_expand_all_modes = true;
-      mode_status_.expand_all_modes = true;
-      break;
-    }
-
-    if (exp_node.node_index == lb_net_terminals_[net_idx][isink]) {
-      /* Net terminal is routed, add this to the route tree, clear data structures, and keep going */
-      sink_routed[isink] = !add_to_rt(lb_net_rt_trees_[net_idx], exp_node.node_index, net_idx);
-    }
-
-    if (false == sink_routed[isink]) {
-      VTR_LOG("Routing was impossible!\n");
-    } else if (mode_status_.expand_all_modes) {
-      sink_routed[isink] = !route_has_conflict(lb_rr_graph, lb_net_rt_trees_[net_idx]);
-      if (false == sink_routed[isink]) {
-        VTR_LOG("Routing was impossible due to modes!\n");
+      if (exp_node.node_index == lb_net_sinks_[net_idx][isink]) {
+        /* Net terminal is routed, add this to the route tree, clear data structures, and keep going */
+        sink_routed[isink] = !add_to_rt(lb_net_rt_trees_[net_idx][isrc], exp_node.node_index, net_idx);
       }
-    }
 
-    explore_id_index_++;
-    if (explore_id_index_ > 2000000000) {
-      /* overflow protection */
-      for (const LbRRNodeId& id : lb_rr_graph.nodes()) {
-        explored_node_tb_[id].explored_id = OPEN;
-        explored_node_tb_[id].enqueue_id = OPEN;
-        explore_id_index_ = 1;
+      if (false == sink_routed[isink]) {
+        VTR_LOG("Routing was impossible!\n");
+      } else if (mode_status_.expand_all_modes) {
+        sink_routed[isink] = !route_has_conflict(lb_rr_graph, lb_net_rt_trees_[net_idx][isrc]);
+        if (false == sink_routed[isink]) {
+          VTR_LOG("Routing was impossible due to modes!\n");
+        }
+      }
+
+      explore_id_index_++;
+      if (explore_id_index_ > 2000000000) {
+        /* overflow protection */
+        for (const LbRRNodeId& id : lb_rr_graph.nodes()) {
+          explored_node_tb_[id].explored_id = OPEN;
+          explored_node_tb_[id].enqueue_id = OPEN;
+          explore_id_index_ = 1;
+        }
       }
     }
   }
@@ -290,9 +293,11 @@ bool LbRouter::try_route_net(const LbRRGraph& lb_rr_graph,
    * If so, we have conflicts and routing is considered to be failure
    */
   if (true == route_succeed) {
-    commit_remove_rt(lb_rr_graph, lb_net_rt_trees_[net_idx], RT_COMMIT, mode_map);
-    if (true == mode_status_.is_mode_conflict) {
-      route_succeed = false;
+    for (size_t isrc = 1; isrc < lb_net_sources_[net_idx].size(); ++isrc) {
+      commit_remove_rt(lb_rr_graph, lb_net_rt_trees_[net_idx][isrc], RT_COMMIT, mode_map);
+      if (true == mode_status_.is_mode_conflict) {
+        route_succeed = false;
+      }
     }
   }
 
@@ -351,14 +356,18 @@ bool LbRouter::try_route(const LbRRGraph& lb_rr_graph,
                atom_nlist.net_name(lb_net_atom_net_ids_[NetId(inet)]).c_str(),
                lb_type_->name);
       VTR_LOGV(verbosity < 3,
-               "\tNet source pin '%s'\n",
-               lb_rr_graph.node_pb_graph_pin(lb_net_terminals_[NetId(inet)][0])->to_string().c_str()); 
-      VTR_LOGV(verbosity < 3,
-               "\tNet sink pins:\n");
-      for (size_t isink = 1; isink < lb_net_terminals_[NetId(inet)].size(); ++isink) {
+               "\tNet source pin:\n"); 
+      for (size_t isrc = 0; isrc < lb_net_sources_[NetId(inet)].size(); ++isrc) {
         VTR_LOGV(verbosity < 3,
                  "\t\t%s\n",
-                 lb_rr_graph.node_pb_graph_pin(lb_net_terminals_[NetId(inet)][isink])->to_string().c_str()); 
+                 lb_rr_graph.node_pb_graph_pin(lb_net_sources_[NetId(inet)][isrc])->to_string().c_str()); 
+      }
+      VTR_LOGV(verbosity < 3,
+               "\tNet sink pins:\n");
+      for (size_t isink = 0; isink < lb_net_sinks_[NetId(inet)].size(); ++isink) {
+        VTR_LOGV(verbosity < 3,
+                 "\t\t%s\n",
+                 lb_rr_graph.node_pb_graph_pin(lb_net_sinks_[NetId(inet)][isink])->to_string().c_str()); 
       }
       VTR_LOGV(verbosity < 3,
                "Please check your architecture XML to see if it is routable\n");
@@ -385,8 +394,8 @@ void LbRouter::fix_duplicate_equivalent_pins(const AtomContext& atom_ctx,
   for (const NetId& ilb_net : lb_net_ids_) {
     //Collect all the sink terminals indicies which target a particular node
     std::map<LbRRNodeId, std::vector<int>> duplicate_terminals;
-    for (size_t iterm = 1; iterm < lb_net_terminals_[ilb_net].size(); ++iterm) {
-      LbRRNodeId node = lb_net_terminals_[ilb_net][iterm];
+    for (size_t iterm = 0; iterm < lb_net_sinks_[ilb_net].size(); ++iterm) {
+      LbRRNodeId node = lb_net_sinks_[ilb_net][iterm];
 
       duplicate_terminals[node].push_back(iterm);
     }
@@ -398,8 +407,8 @@ void LbRouter::fix_duplicate_equivalent_pins(const AtomContext& atom_ctx,
       for (size_t idup_term = 0; idup_term < kv.second.size(); ++idup_term) {
         int iterm = kv.second[idup_term]; //The index in terminals which is duplicated
 
-        VTR_ASSERT(lb_net_atom_pins_[ilb_net].size() == lb_net_terminals_[ilb_net].size());
-        AtomPinId atom_pin = lb_net_atom_pins_[ilb_net][iterm];
+        VTR_ASSERT(lb_net_atom_sink_pins_[ilb_net].size() == lb_net_sinks_[ilb_net].size());
+        AtomPinId atom_pin = lb_net_atom_sink_pins_[ilb_net][iterm];
         VTR_ASSERT(atom_pin);
 
         const t_pb_graph_pin* pb_graph_pin = find_pb_graph_pin(atom_ctx.nlist, atom_ctx.lookup, atom_pin);
@@ -421,10 +430,10 @@ void LbRouter::fix_duplicate_equivalent_pins(const AtomContext& atom_ctx,
         VTR_ASSERT(1 == lb_rr_graph.node_out_edges(pin_index, &(pb_graph_pin->parent_node->pb_type->modes[0])).size());
         LbRRNodeId sink_index = lb_rr_graph.edge_sink_node(lb_rr_graph.node_out_edges(pin_index, &(pb_graph_pin->parent_node->pb_type->modes[0]))[0]);
         VTR_ASSERT(LB_SINK == lb_rr_graph.node_type(sink_index));
-        VTR_ASSERT_MSG(sink_index == lb_net_terminals_[ilb_net][iterm], "Remapped pin must be connected to original sink");
+        VTR_ASSERT_MSG(sink_index == lb_net_sinks_[ilb_net][iterm], "Remapped pin must be connected to original sink");
 
         //Change the target
-        lb_net_terminals_[ilb_net][iterm] = pin_index;
+        lb_net_sinks_[ilb_net][iterm] = pin_index;
       }
     }
   }
@@ -590,11 +599,11 @@ bool LbRouter::add_to_rt(t_trace* rt, const LbRRNodeId& node_index, const NetId&
   return false;
 }
 
-void LbRouter::add_source_to_rt(const NetId& inet) {
+void LbRouter::add_source_to_rt(const NetId& inet, const size_t& isrc) {
   /* TODO: Validate net id */
-  VTR_ASSERT(nullptr == lb_net_rt_trees_[inet]);
-  lb_net_rt_trees_[inet] = new t_trace;
-  lb_net_rt_trees_[inet]->current_node = lb_net_terminals_[inet][0];
+  VTR_ASSERT(nullptr == lb_net_rt_trees_[inet][isrc]);
+  lb_net_rt_trees_[inet][isrc] = new t_trace;
+  lb_net_rt_trees_[inet][isrc]->current_node = lb_net_sources_[inet][isrc];
 }
 
 void LbRouter::expand_rt_rec(t_trace* rt,
@@ -620,10 +629,11 @@ void LbRouter::expand_rt_rec(t_trace* rt,
 }
 
 void LbRouter::expand_rt(const NetId& inet,
-                         const NetId& irt_net) {
+                         const NetId& irt_net,
+                         const size_t& isrc) {
   VTR_ASSERT(pq_.empty());
 
-  expand_rt_rec(lb_net_rt_trees_[inet], LbRRNodeId::INVALID(), irt_net, explore_id_index_);
+  expand_rt_rec(lb_net_rt_trees_[inet][isrc], LbRRNodeId::INVALID(), irt_net, explore_id_index_);
 }
 
 void LbRouter::expand_edges(const LbRRGraph& lb_rr_graph,
@@ -758,6 +768,7 @@ bool LbRouter::try_expand_nodes(const AtomNetlist& atom_nlist,
                                 const LbRRGraph& lb_rr_graph,
                                 const NetId& lb_net,
                                 t_expansion_node& exp_node,
+                                const int& isrc,
                                 const int& itarget,
                                 const bool& try_other_modes,
                                 const int& verbosity) {
@@ -771,10 +782,10 @@ bool LbRouter::try_expand_nodes(const AtomNetlist& atom_nlist,
       if (verbosity > 3) {
         //Print detailed debug info
         AtomNetId net_id = lb_net_atom_net_ids_[lb_net];
-        AtomPinId driver_pin = lb_net_atom_pins_[lb_net][0];
-        AtomPinId sink_pin = lb_net_atom_pins_[lb_net][itarget];
-        LbRRNodeId driver_rr_node = lb_net_terminals_[lb_net][0];
-        LbRRNodeId sink_rr_node = lb_net_terminals_[lb_net][itarget];
+        AtomPinId driver_pin = lb_net_atom_source_pins_[lb_net][isrc];
+        AtomPinId sink_pin = lb_net_atom_sink_pins_[lb_net][itarget];
+        LbRRNodeId driver_rr_node = lb_net_sources_[lb_net][isrc];
+        LbRRNodeId sink_rr_node = lb_net_sinks_[lb_net][itarget];
 
         VTR_LOG("\t\t\tNo possible routing path from %s to %s: needed for net '%s' from net pin '%s'",
                 describe_lb_rr_node(lb_rr_graph, driver_rr_node).c_str(),
@@ -796,16 +807,16 @@ bool LbRouter::try_expand_nodes(const AtomNetlist& atom_nlist,
          */
         explored_node_tb_[exp_inode].explored_id = explore_id_index_;
         explored_node_tb_[exp_inode].prev_index = exp_node.prev_index;
-        if (exp_inode != lb_net_terminals_[lb_net][itarget]) {
+        if (exp_inode != lb_net_sinks_[lb_net][itarget]) {
           if (!try_other_modes) {
-            expand_node(lb_rr_graph, exp_node, lb_net_terminals_[lb_net].size() - 1);
+            expand_node(lb_rr_graph, exp_node, lb_net_sinks_[lb_net].size());
           } else {
-            expand_node_all_modes(lb_rr_graph, exp_node, lb_net_terminals_[lb_net].size() - 1);
+            expand_node_all_modes(lb_rr_graph, exp_node, lb_net_sinks_[lb_net].size());
           }
         }
       }
     }
-  } while (exp_node.node_index != lb_net_terminals_[lb_net][itarget] && !is_impossible);
+  } while (exp_node.node_index != lb_net_sinks_[lb_net][itarget] && !is_impossible);
 
   return is_impossible;
 }
@@ -828,37 +839,62 @@ bool LbRouter::check_net(const LbRRGraph& lb_rr_graph,
   if (false == atom_nlist.valid_net_id(lb_net_atom_net_ids_[net])) {
     return false;
   }
-  if (lb_net_atom_pins_[net].size() != lb_net_terminals_[net].size()) {
+  if (lb_net_atom_sink_pins_[net].size() != lb_net_sinks_[net].size()) {
     VTR_LOGF_ERROR(__FILE__, __LINE__,
                    "Net '%lu' has unmatched atom pins and terminals.\n",
                    size_t(net));
     return false;
   }
   /* We must have 1 source and >1 terminal */
-  if (2 > lb_net_terminals_[net].size()) {
+  if (1 > lb_net_sources_[net].size()) {
     VTR_LOGF_ERROR(__FILE__, __LINE__,
-                   "Net '%lu' has only %lu terminal.\n",
-                   size_t(net), lb_net_terminals_[net].size());
+                   "Net '%lu' has only %lu sources.\n",
+                   size_t(net), lb_net_sources_[net].size());
+    return false;
+  } 
+
+  if (1 > lb_net_sinks_[net].size()) {
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Net '%lu' has only %lu sinks.\n",
+                   size_t(net), lb_net_sinks_[net].size());
     return false;
   } 
   /* Each node must be valid */
-  for (const LbRRNodeId& node : lb_net_terminals_[net]) {
+  for (const LbRRNodeId& node : lb_net_sources_[net]) {
     if (false == lb_rr_graph.valid_node_id(node)) {
       VTR_LOGF_ERROR(__FILE__, __LINE__,
-                     "Net '%lu' has invalid terminal node in lb_rr_graph.\n",
+                     "Net '%lu' has invalid sink node in lb_rr_graph.\n",
                      size_t(net));
       return false;
     }
   }
+  for (const LbRRNodeId& node : lb_net_sinks_[net]) {
+    if (false == lb_rr_graph.valid_node_id(node)) {
+      VTR_LOGF_ERROR(__FILE__, __LINE__,
+                     "Net '%lu' has invalid sink node in lb_rr_graph.\n",
+                     size_t(net));
+      return false;
+    }
+  }
+
   /* Each atom pin must be valid */
-  for (const AtomPinId& pin : lb_net_atom_pins_[net]) {
+  for (const AtomPinId& pin : lb_net_atom_source_pins_[net]) {
     if (false == atom_nlist.valid_pin_id(pin)) {
       VTR_LOGF_ERROR(__FILE__, __LINE__,
-                     "Net '%lu' has invalid atom pin.\n",
+                     "Net '%lu' has invalid source atom pin.\n",
                      size_t(net));
       return false;
     }
   }
+  for (const AtomPinId& pin : lb_net_atom_sink_pins_[net]) {
+    if (false == atom_nlist.valid_pin_id(pin)) {
+      VTR_LOGF_ERROR(__FILE__, __LINE__,
+                     "Net '%lu' has invalid sink_ atom pin.\n",
+                     size_t(net));
+      return false;
+    }
+  }
+
 
   return true;
 }
@@ -878,8 +914,10 @@ void LbRouter::reset_explored_node_tb() {
 
 void LbRouter::reset_net_rt() {
   for (const NetId& inet : lb_net_ids_) {
-    free_net_rt(lb_net_rt_trees_[inet]);
-    lb_net_rt_trees_[inet] = nullptr;
+    for (size_t isrc = 0; isrc < lb_net_sources_[inet].size(); ++isrc) {
+      free_net_rt(lb_net_rt_trees_[inet][isrc]);
+      lb_net_rt_trees_[inet][isrc] = nullptr;
+    }
   }
 }
 
@@ -896,8 +934,10 @@ void LbRouter::clear_nets() {
 
   lb_net_ids_.clear();
   lb_net_atom_net_ids_.clear();
-  lb_net_atom_pins_.clear();
-  lb_net_terminals_.clear();
+  lb_net_atom_source_pins_.clear();
+  lb_net_atom_sink_pins_.clear();
+  lb_net_sources_.clear();
+  lb_net_sinks_.clear();
   lb_net_rt_trees_.clear();
 }
 
diff --git a/openfpga/src/repack/lb_router.h b/openfpga/src/repack/lb_router.h
index 0d7d4b9af..600ddc4a4 100644
--- a/openfpga/src/repack/lb_router.h
+++ b/openfpga/src/repack/lb_router.h
@@ -294,13 +294,14 @@ class LbRouter {
                           std::unordered_map<const t_pb_graph_node*, const t_mode*>& mode_map);
     bool is_skip_route_net(const LbRRGraph& lb_rr_graph, t_trace* rt);
     bool add_to_rt(t_trace* rt, const LbRRNodeId& node_index, const NetId& irt_net);
-    void add_source_to_rt(const NetId& inet);
+    void add_source_to_rt(const NetId& inet, const size_t& isrc);
     void expand_rt_rec(t_trace* rt,
                        const LbRRNodeId& prev_index, 
                        const NetId& irt_net,
                        const int& explore_id_index);
     void expand_rt(const NetId& inet,
-                   const NetId& irt_net);
+                   const NetId& irt_net,
+                   const size_t& isrc);
     void expand_edges(const LbRRGraph& lb_rr_graph,
                       t_mode* mode,
                       const LbRRNodeId& cur_inode,
@@ -316,6 +317,7 @@ class LbRouter {
                           const LbRRGraph& lb_rr_graph,
                           const NetId& lb_net,
                           t_expansion_node& exp_node,
+                          const int& isrc,
                           const int& itarget,
                           const bool& try_other_modes,
                           const int& verbosity);
@@ -355,11 +357,26 @@ class LbRouter {
 
   private : /* Stores all data needed by intra-logic cluster_ctx.blocks router */
     /* Logical Netlist Info */
-    vtr::vector<NetId, NetId> lb_net_ids_; /* Pointer to vector of intra logic cluster_ctx.blocks nets and their connections */
-    vtr::vector<NetId, AtomNetId> lb_net_atom_net_ids_;             /* index of atom net this intra_lb_net represents */
-    vtr::vector<NetId, std::vector<AtomPinId>> lb_net_atom_pins_;  /* AtomPin's associated with each terminal */
-    vtr::vector<NetId, std::vector<LbRRNodeId>> lb_net_terminals_; /* endpoints of the intra_lb_net, 0th position is the source, all others are sinks */
-    vtr::vector<NetId, t_trace*> lb_net_rt_trees_;               /* Route tree head */
+    /* Pointer to vector of intra logic cluster_ctx.blocks nets and their connections */
+    vtr::vector<NetId, NetId> lb_net_ids_;
+
+    /* index of atom net this intra_lb_net represents */
+    vtr::vector<NetId, AtomNetId> lb_net_atom_net_ids_;             
+
+    /* AtomPin's associated with each source nodes */
+    vtr::vector<NetId, std::vector<AtomPinId>> lb_net_atom_source_pins_;
+
+    /* AtomPin's associated with each sink nodes */
+    vtr::vector<NetId, std::vector<AtomPinId>> lb_net_atom_sink_pins_;
+
+    /* starting points of the intra_lb_net */
+    vtr::vector<NetId, std::vector<LbRRNodeId>> lb_net_sources_;
+
+    /* end points of the intra_lb_net */
+    vtr::vector<NetId, std::vector<LbRRNodeId>> lb_net_sinks_;
+
+    /* Route tree head for each source of each net */
+    vtr::vector<NetId, std::vector<t_trace*>> lb_net_rt_trees_;
 
     /* Logical-to-physical mapping info */
     vtr::vector<LbRRNodeId, t_routing_status> routing_status_; /* [0..lb_type_graph->size()-1] Stats for each logic cluster_ctx.blocks rr node instance */

From 8921905becaeba7b950279be9fd0897e4bf816e4 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 12 Mar 2020 19:21:13 -0600
Subject: [PATCH 304/645] annotate multiple-source and multiple-sink nets from
 pb to lb router

---
 openfpga/src/repack/lb_router.cpp       |   7 +-
 openfpga/src/repack/lb_router.h         |   3 +-
 openfpga/src/repack/lb_router_utils.cpp |   4 +-
 openfpga/src/repack/lb_router_utils.h   |   2 +-
 openfpga/src/repack/repack.cpp          | 104 ++++++++++++++++++++----
 5 files changed, 98 insertions(+), 22 deletions(-)

diff --git a/openfpga/src/repack/lb_router.cpp b/openfpga/src/repack/lb_router.cpp
index 1be68cc51..7cc6d080e 100644
--- a/openfpga/src/repack/lb_router.cpp
+++ b/openfpga/src/repack/lb_router.cpp
@@ -147,7 +147,8 @@ void LbRouter::rec_collect_trace_nodes(const t_trace* trace, std::vector<LbRRNod
 /**************************************************
  * Public mutators
  *************************************************/
-LbRouter::NetId LbRouter::create_net_to_route(const LbRRNodeId& source, const std::vector<LbRRNodeId>& terminals) {
+LbRouter::NetId LbRouter::create_net_to_route(const std::vector<LbRRNodeId>& sources,
+                                              const std::vector<LbRRNodeId>& terminals) {
   /* Create an new id */
   NetId net = NetId(lb_net_ids_.size());
   lb_net_ids_.push_back(net);
@@ -157,9 +158,9 @@ LbRouter::NetId LbRouter::create_net_to_route(const LbRRNodeId& source, const st
   lb_net_atom_source_pins_.emplace_back();
   lb_net_atom_sink_pins_.emplace_back();
   
-  lb_net_sources_.push_back(std::vector<LbRRNodeId>(1, source));
+  lb_net_sources_.push_back(sources);
   lb_net_sinks_.push_back(terminals);
-  lb_net_rt_trees_.push_back(std::vector<t_trace*>(1, nullptr));
+  lb_net_rt_trees_.push_back(std::vector<t_trace*>(sources.size(), nullptr));
 
   return net;
 }
diff --git a/openfpga/src/repack/lb_router.h b/openfpga/src/repack/lb_router.h
index 600ddc4a4..dcd0dc610 100644
--- a/openfpga/src/repack/lb_router.h
+++ b/openfpga/src/repack/lb_router.h
@@ -234,7 +234,8 @@ class LbRouter {
     /**
      * Add net to be routed
      */ 
-    NetId create_net_to_route(const LbRRNodeId& source, const std::vector<LbRRNodeId>& terminals);
+    NetId create_net_to_route(const std::vector<LbRRNodeId>& sources,
+                              const std::vector<LbRRNodeId>& terminals);
     void add_net_atom_net_id(const NetId& net, const AtomNetId& atom_net);
     void add_net_atom_pins(const NetId& net, const AtomPinId& src_pin, const std::vector<AtomPinId>& terminal_pins);
 
diff --git a/openfpga/src/repack/lb_router_utils.cpp b/openfpga/src/repack/lb_router_utils.cpp
index c106cd9f7..362ce4a76 100644
--- a/openfpga/src/repack/lb_router_utils.cpp
+++ b/openfpga/src/repack/lb_router_utils.cpp
@@ -17,13 +17,13 @@ namespace openfpga {
  ***************************************************************************************/
 LbRouter::NetId add_lb_router_net_to_route(LbRouter& lb_router,
                                            const LbRRGraph& lb_rr_graph,
-                                           const LbRRNodeId& source_node,
+                                           const std::vector<LbRRNodeId>& source_nodes,
                                            const std::vector<LbRRNodeId>& sink_nodes,
                                            const AtomContext& atom_ctx,
                                            const AtomNetId& atom_net_id) {
   VTR_ASSERT(0 < sink_nodes.size());
 
-  LbRouter::NetId lb_net = lb_router.create_net_to_route(source_node, sink_nodes);
+  LbRouter::NetId lb_net = lb_router.create_net_to_route(source_nodes, sink_nodes);
 
   VTR_ASSERT(AtomNetId::INVALID() != atom_net_id);
   lb_router.add_net_atom_net_id(lb_net, atom_net_id);
diff --git a/openfpga/src/repack/lb_router_utils.h b/openfpga/src/repack/lb_router_utils.h
index 129796e7d..0f8384859 100644
--- a/openfpga/src/repack/lb_router_utils.h
+++ b/openfpga/src/repack/lb_router_utils.h
@@ -18,7 +18,7 @@ namespace openfpga {
 
 LbRouter::NetId add_lb_router_net_to_route(LbRouter& lb_router,
                                            const LbRRGraph& lb_rr_graph,
-                                           const LbRRNodeId& source_node,
+                                           const std::vector<LbRRNodeId>& source_node,
                                            const std::vector<LbRRNodeId>& sink_nodes,
                                            const AtomContext& atom_ctx,
                                            const AtomNetId& atom_net_id);
diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp
index 6f312c0b7..417cb6b95 100644
--- a/openfpga/src/repack/repack.cpp
+++ b/openfpga/src/repack/repack.cpp
@@ -86,16 +86,30 @@ std::vector<LbRRNodeId> find_lb_net_physical_sink_lb_rr_nodes(const LbRRGraph& l
 
     /* if this is the root node, the physical pin is its self */
     if (nullptr == physical_sink_pin) {
-      VTR_LOG("Fail to find a physical pin for operating pin '%s'!\n",
-              sink_pin->to_string().c_str());
-    }
+      VTR_LOGF_ERROR(__FILE__, __LINE__,
+                     "Fail to find a physical pin for operating pin '%s'!\n",
+                     sink_pin->to_string().c_str());
+    } 
     VTR_ASSERT(nullptr != physical_sink_pin);
+
+    /* Sink nodes should NOT be any output pin of primitive pb_graph_node,
+     * warn that we will not include it in the sink nodes
+     */
+    if ( (true == is_primitive_pb_type(physical_sink_pin->parent_node->pb_type))
+      && (OUT_PORT == physical_sink_pin->port->type)) {
+      VTR_LOGF_ERROR(__FILE__, __LINE__,
+                     "Sink pin '%s' should NOT be an output from a primitive pb_type!\n",
+                     sink_pin->to_string().c_str());
+    }
+
     LbRRNodeId sink_lb_rr_node = lb_rr_graph.find_node(LB_INTERMEDIATE, physical_sink_pin);
     if (true != lb_rr_graph.valid_node_id(sink_lb_rr_node)) {
-      VTR_LOG("Try to find the lb_rr_node for pb_graph_pin '%s'\n",
-              physical_sink_pin->to_string().c_str());
+      VTR_LOGF_ERROR(__FILE__, __LINE__,
+                     "Fail to find the lb_rr_node for pb_graph_pin '%s'\n",
+                     physical_sink_pin->to_string().c_str());
     }
     VTR_ASSERT(true == lb_rr_graph.valid_node_id(sink_lb_rr_node));
+
     sink_nodes.push_back(sink_lb_rr_node);
   }
 
@@ -134,6 +148,12 @@ void add_lb_router_nets(LbRouter& lb_router,
   /* Build the fast look-up between pb_pin_id and pb_graph_pin pointer */
   t_pb_graph_pin** pb_graph_pin_lookup_from_index = alloc_and_load_pb_graph_pin_lookup_from_index(lb_type);
 
+  /* Cache all the source nodes and sinks node for each net
+   * net_terminal[net][0] is the list of source nodes 
+   * net_terminal[net][1] is the list of sink nodes 
+   */
+  std::map<AtomNetId, std::array<std::vector<LbRRNodeId>, 2>> net_terminals;
+
   /* Find the source nodes for the nets mapped to inputs of a clustered block */
   for (int j = 0; j < lb_type->pb_type->num_pins; j++) {
     /* Find the net mapped to this pin in clustering results*/
@@ -150,6 +170,7 @@ void add_lb_router_nets(LbRouter& lb_router,
     /* Get the source pb_graph pin and find the rr_node in logical block routing resource graph */
     const t_pb_graph_pin* source_pb_pin = get_pb_graph_node_pin_from_block_pin(block_id, j);
     VTR_ASSERT(source_pb_pin->parent_node == pb->pb_graph_node);
+
     /* Bypass output pins */
     if (OUT_PORT == source_pb_pin->port->type) {
       continue;
@@ -169,11 +190,26 @@ void add_lb_router_nets(LbRouter& lb_router,
     std::vector<LbRRNodeId> sink_lb_rr_nodes = find_lb_net_physical_sink_lb_rr_nodes(lb_rr_graph, sink_pb_graph_pins, device_annotation);
     VTR_ASSERT(sink_lb_rr_nodes.size() == sink_pb_graph_pins.size());
 
-    /* Add the net */
-    add_lb_router_net_to_route(lb_router, lb_rr_graph,
-                               source_lb_rr_node, sink_lb_rr_nodes,
-                               atom_ctx, atom_net_id);
-    net_counter++;
+    /* Cache the net */
+    if (0 < net_terminals.count(atom_net_id)) {
+      if (net_terminals[atom_net_id][0].end() == std::find(net_terminals[atom_net_id][0].begin(), 
+                                                           net_terminals[atom_net_id][0].end(),
+                                                           source_lb_rr_node)) {
+        net_terminals[atom_net_id][0].push_back(source_lb_rr_node);
+      }
+
+      for (const LbRRNodeId& sink_lb_rr_node : sink_lb_rr_nodes) {
+        if (net_terminals[atom_net_id][1].end() == std::find(net_terminals[atom_net_id][1].begin(),
+                                                             net_terminals[atom_net_id][1].end(),
+                                                             sink_lb_rr_node)) {
+          net_terminals[atom_net_id][1].push_back(sink_lb_rr_node);
+        }
+      }
+    } else {
+      net_terminals[atom_net_id][0].push_back(source_lb_rr_node);
+      net_terminals[atom_net_id][1] = sink_lb_rr_nodes;
+      net_counter++;
+    }
   }
 
   /* Find the source nodes for the nets mapped to outputs of primitive pb_graph_node */
@@ -216,16 +252,54 @@ void add_lb_router_nets(LbRouter& lb_router,
     std::vector<LbRRNodeId> sink_lb_rr_nodes = find_lb_net_physical_sink_lb_rr_nodes(lb_rr_graph, sink_pb_graph_pins, device_annotation);
     VTR_ASSERT(sink_lb_rr_nodes.size() == sink_pb_graph_pins.size());
 
-    /* Add the net */
-    add_lb_router_net_to_route(lb_router, lb_rr_graph,
-                               source_lb_rr_node, sink_lb_rr_nodes,
-                               atom_ctx, atom_net_id);
-    net_counter++;
+    /* Cache the net */
+    if (0 < net_terminals.count(atom_net_id)) {
+      if (net_terminals[atom_net_id][0].end() == std::find(net_terminals[atom_net_id][0].begin(), 
+                                                           net_terminals[atom_net_id][0].end(),
+                                                           source_lb_rr_node)) {
+        net_terminals[atom_net_id][0].push_back(source_lb_rr_node);
+      }
+
+      for (const LbRRNodeId& sink_lb_rr_node : sink_lb_rr_nodes) {
+        if (net_terminals[atom_net_id][1].end() == std::find(net_terminals[atom_net_id][1].begin(),
+                                                             net_terminals[atom_net_id][1].end(),
+                                                             sink_lb_rr_node)) {
+          net_terminals[atom_net_id][1].push_back(sink_lb_rr_node);
+        }
+      }
+    } else {
+      net_terminals[atom_net_id][0].push_back(source_lb_rr_node);
+      net_terminals[atom_net_id][1] = sink_lb_rr_nodes;
+      net_counter++;
+    }
   } 
 
   /* Free */
   free_pb_graph_pin_lookup_from_index(pb_graph_pin_lookup_from_index);
 
+  /* Add all the nets */
+  for (std::pair<AtomNetId, std::array<std::vector<LbRRNodeId>, 2>> net_terminal_pair : net_terminals) {
+    const AtomNetId& atom_net_id = net_terminal_pair.first;
+
+    /* MUST have >1 source nodes and >1 sinks nodes */
+    if (0 == net_terminal_pair.second[0].size()) {
+      VTR_LOGF_ERROR(__FILE__, __LINE__,
+                     "Net '%s' has 0 source nodes!",
+                     atom_ctx.nlist.net_name(atom_net_id).c_str());
+    }
+
+    if (0 == net_terminal_pair.second[1].size()) {
+      VTR_LOGF_ERROR(__FILE__, __LINE__,
+                     "Net '%s' has 0 sink nodes!",
+                     atom_ctx.nlist.net_name(atom_net_id).c_str());
+    }
+
+    /* Add the net */
+    add_lb_router_net_to_route(lb_router, lb_rr_graph,
+                               net_terminal_pair.second[0], net_terminal_pair.second[1],
+                               atom_ctx, atom_net_id);
+  }
+
   VTR_LOGV(verbose,
            "Added %lu nets to be routed.\n",
            net_counter);

From 29450f34726c0dc5e8593443ab6357e8fe3f7bd4 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 12 Mar 2020 20:42:41 -0600
Subject: [PATCH 305/645] debugging multi-source lb router

---
 openfpga/src/repack/lb_router.cpp             | 104 ++++++++++--------
 openfpga/src/repack/lb_router.h               |   4 +-
 .../test_script/and_latch_k6_frac.openfpga    |   4 +-
 3 files changed, 61 insertions(+), 51 deletions(-)

diff --git a/openfpga/src/repack/lb_router.cpp b/openfpga/src/repack/lb_router.cpp
index 7cc6d080e..70b8e67b0 100644
--- a/openfpga/src/repack/lb_router.cpp
+++ b/openfpga/src/repack/lb_router.cpp
@@ -209,7 +209,7 @@ bool LbRouter::try_route_net(const LbRRGraph& lb_rr_graph,
                              const NetId& net_idx,
                              t_expansion_node& exp_node,
                              std::unordered_map<const t_pb_graph_node*, const t_mode*>& mode_map,
-                             const int& verbosity) {
+                             const bool& verbosity) {
 
   std::vector<bool> sink_routed(lb_net_sinks_[net_idx].size(), false);
 
@@ -226,18 +226,15 @@ bool LbRouter::try_route_net(const LbRRGraph& lb_rr_graph,
 
     /* Route each sink of net */
     for (size_t isink = 0; isink < lb_net_sinks_[net_idx].size(); ++isink) {
-      /* Check if last sink failed in routing
-       * If failed, the routing is not possible for this net
-       */
-      if (0 < isink) {
-        if (false == sink_routed[isink - 1]) {
-          break;
-        }
+
+      /* Skip routed nets */
+      if (true == sink_routed[isink]) {
+        continue;
       }
 
       pq_.clear();
-      /* Get lowest cost next node, repeat until a path is found or if it is impossible to route */
 
+      /* Get lowest cost next node, repeat until a path is found or if it is impossible to route */
       expand_rt(net_idx, net_idx, isrc);
 
       /* If we managed to expand the nodes to the sink, routing for this sink is done.
@@ -246,10 +243,17 @@ bool LbRouter::try_route_net(const LbRRGraph& lb_rr_graph,
        */
       sink_routed[isink] = !try_expand_nodes(atom_nlist, lb_rr_graph, net_idx, exp_node, isrc, isink, mode_status_.expand_all_modes, verbosity);
 
+      if (true == sink_routed[isink]) {
+        VTR_LOGV(verbosity,
+                 "Succeed to expand routing tree from source pin '%s' to sink pin '%s'!\n",
+                 lb_rr_graph.node_pb_graph_pin(lb_net_sources_[net_idx][isrc])->to_string().c_str(),
+                 lb_rr_graph.node_pb_graph_pin(lb_net_sinks_[net_idx][isink])->to_string().c_str());
+      }
+
       if (false == sink_routed[isink] && false == mode_status_.expand_all_modes) {
         mode_status_.try_expand_all_modes = true;
         mode_status_.expand_all_modes = true;
-        break;
+        continue;
       }
 
       if (exp_node.node_index == lb_net_sinks_[net_idx][isink]) {
@@ -258,14 +262,25 @@ bool LbRouter::try_route_net(const LbRRGraph& lb_rr_graph,
       }
 
       if (false == sink_routed[isink]) {
-        VTR_LOG("Routing was impossible!\n");
+        VTR_LOGV(verbosity,
+                 "Routing was impossible from source pin '%s' to sink pin '%s'!\n",
+                 lb_rr_graph.node_pb_graph_pin(lb_net_sources_[net_idx][isrc])->to_string().c_str(),
+                 lb_rr_graph.node_pb_graph_pin(lb_net_sinks_[net_idx][isink])->to_string().c_str());
       } else if (mode_status_.expand_all_modes) {
         sink_routed[isink] = !route_has_conflict(lb_rr_graph, lb_net_rt_trees_[net_idx][isrc]);
         if (false == sink_routed[isink]) {
-          VTR_LOG("Routing was impossible due to modes!\n");
+          VTR_LOGV(verbosity,
+                   "Routing was impossible due to modes!\n");
         }
       }
 
+      if (true == sink_routed[isink]) {
+        VTR_LOGV(verbosity,
+                 "Routing succeeded from source pin '%s' to sink pin '%s'!\n",
+                 lb_rr_graph.node_pb_graph_pin(lb_net_sources_[net_idx][isrc])->to_string().c_str(),
+                 lb_rr_graph.node_pb_graph_pin(lb_net_sinks_[net_idx][isink])->to_string().c_str());
+      }
+
       explore_id_index_++;
       if (explore_id_index_ > 2000000000) {
         /* overflow protection */
@@ -275,39 +290,40 @@ bool LbRouter::try_route_net(const LbRRGraph& lb_rr_graph,
           explore_id_index_ = 1;
         }
       }
+
+      /* If routing succeed so far, we will try to save(commit) results
+       * to route tree.
+       * During this process, we will check if there is any 
+       * nodes using different modes under the same pb_type
+       * If so, we have conflicts and routing is considered to be failure
+       */
+      if (true == sink_routed[isink]) {
+        commit_remove_rt(lb_rr_graph, lb_net_rt_trees_[net_idx][isrc], RT_COMMIT, mode_map);
+        if (true == mode_status_.is_mode_conflict) {
+          sink_routed[isink] = false;
+        }
+      }
     }
   }
 
   /* Check the routing status for all the sinks */
   bool route_succeed = true;
-  for (const bool& sink_status : sink_routed) {
-    if (false == sink_status) {
+  for (size_t isink = 0; isink < sink_routed.size(); ++isink) {
+    if (false == sink_routed[isink]) {
       route_succeed = false;
+      VTR_LOGV(verbosity,
+               "Routing failed for sink pin '%s'!\n",
+               lb_rr_graph.node_pb_graph_pin(lb_net_sinks_[net_idx][isink])->to_string().c_str());
       break;
     }
   }
 
-  /* If routing succeed so far, we will try to save(commit) results
-   * to route tree.
-   * During this process, we will check if there is any 
-   * nodes using different modes under the same pb_type
-   * If so, we have conflicts and routing is considered to be failure
-   */
-  if (true == route_succeed) {
-    for (size_t isrc = 1; isrc < lb_net_sources_[net_idx].size(); ++isrc) {
-      commit_remove_rt(lb_rr_graph, lb_net_rt_trees_[net_idx][isrc], RT_COMMIT, mode_map);
-      if (true == mode_status_.is_mode_conflict) {
-        route_succeed = false;
-      }
-    }
-  }
-
   return route_succeed;
 }
 
 bool LbRouter::try_route(const LbRRGraph& lb_rr_graph,
                          const AtomNetlist& atom_nlist,
-                         const int& verbosity) {
+                         const bool& verbosity) {
   /* Validate if the rr_graph is the one we used to initialize the router */
   VTR_ASSERT(true == matched_lb_rr_graph(lb_rr_graph));
 
@@ -351,27 +367,21 @@ bool LbRouter::try_route(const LbRRGraph& lb_rr_graph,
       is_routed_ = is_route_success(lb_rr_graph);
     } else {
       --inet;
-      VTR_LOGV(verbosity < 3,
-               "Net %lu '%s' is impossible to route within proposed %s cluster\n",
-               inet,
-               atom_nlist.net_name(lb_net_atom_net_ids_[NetId(inet)]).c_str(),
-               lb_type_->name);
-      VTR_LOGV(verbosity < 3,
-               "\tNet source pin:\n"); 
+      VTR_LOG("Net %lu '%s' is impossible to route within proposed %s cluster\n",
+              inet,
+              atom_nlist.net_name(lb_net_atom_net_ids_[NetId(inet)]).c_str(),
+              lb_type_->name);
+      VTR_LOG("\tNet source pin:\n"); 
       for (size_t isrc = 0; isrc < lb_net_sources_[NetId(inet)].size(); ++isrc) {
-        VTR_LOGV(verbosity < 3,
-                 "\t\t%s\n",
-                 lb_rr_graph.node_pb_graph_pin(lb_net_sources_[NetId(inet)][isrc])->to_string().c_str()); 
+        VTR_LOG("\t\t%s\n",
+                lb_rr_graph.node_pb_graph_pin(lb_net_sources_[NetId(inet)][isrc])->to_string().c_str()); 
       }
-      VTR_LOGV(verbosity < 3,
-               "\tNet sink pins:\n");
+      VTR_LOG("\tNet sink pins:\n");
       for (size_t isink = 0; isink < lb_net_sinks_[NetId(inet)].size(); ++isink) {
-        VTR_LOGV(verbosity < 3,
-                 "\t\t%s\n",
-                 lb_rr_graph.node_pb_graph_pin(lb_net_sinks_[NetId(inet)][isink])->to_string().c_str()); 
+        VTR_LOG("\t\t%s\n",
+                lb_rr_graph.node_pb_graph_pin(lb_net_sinks_[NetId(inet)][isink])->to_string().c_str()); 
       }
-      VTR_LOGV(verbosity < 3,
-               "Please check your architecture XML to see if it is routable\n");
+      VTR_LOG("Please check your architecture XML to see if it is routable\n");
       
       is_routed_ = false;
     }
diff --git a/openfpga/src/repack/lb_router.h b/openfpga/src/repack/lb_router.h
index dcd0dc610..d865c75b9 100644
--- a/openfpga/src/repack/lb_router.h
+++ b/openfpga/src/repack/lb_router.h
@@ -256,7 +256,7 @@ class LbRouter {
      */
     bool try_route(const LbRRGraph& lb_rr_graph,
                    const AtomNetlist& atom_nlist,
-                   const int& verbosity);
+                   const bool& verbosity);
 
   private :  /* Private accessors */
     /**
@@ -328,7 +328,7 @@ class LbRouter {
                        const NetId& net_idx,
                        t_expansion_node& exp_node,
                        std::unordered_map<const t_pb_graph_node*, const t_mode*>& mode_map,
-                       const int& verbosity);
+                       const bool& verbosity);
 
   private :  /* Private validators */
     /** 
diff --git a/openfpga/test_script/and_latch_k6_frac.openfpga b/openfpga/test_script/and_latch_k6_frac.openfpga
index 210bdcf28..b41ac4450 100644
--- a/openfpga/test_script/and_latch_k6_frac.openfpga
+++ b/openfpga/test_script/and_latch_k6_frac.openfpga
@@ -27,7 +27,7 @@ build_fabric --compress_routing --duplicate_grid_pin #--verbose
 # Repack the netlist to physical pbs
 # This must be done before bitstream generator and testbench generation
 # Strongly recommend it is done after all the fix-up have been applied
-repack #--verbose
+repack --verbose
 
 # Build the bitstream 
 #  - Output the fabric-independent bitstream to a file
@@ -46,7 +46,7 @@ write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port
 #  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
+write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and_latch.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
 
 # Write the SDC files for PnR backend
 #  - Turn on every options here 

From f90dc5c2969d99933fa2af2e2bfafbbb43f11812 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 12 Mar 2020 20:44:07 -0600
Subject: [PATCH 306/645] remove redundant XML codes

---
 openfpga/test_vpr_arch/k6_N10_40nm.xml                   | 9 ---------
 openfpga/test_vpr_arch/k6_frac_N10_40nm.xml              | 9 ---------
 .../k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml       | 9 ---------
 3 files changed, 27 deletions(-)

diff --git a/openfpga/test_vpr_arch/k6_N10_40nm.xml b/openfpga/test_vpr_arch/k6_N10_40nm.xml
index d2501969d..bbd694a79 100644
--- a/openfpga/test_vpr_arch/k6_N10_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_N10_40nm.xml
@@ -296,13 +296,4 @@
     </pb_type>
     <!-- Define general purpose logic block (CLB) ends -->
   </complexblocklist>
-  <power>
-    <local_interconnect C_wire="2.5e-10"/>
-    <mux_transistor_size mux_transistor_size="3"/>
-    <FF_size FF_size="4"/>
-    <LUT_transistor_size LUT_transistor_size="4"/>
-  </power>
-  <clocks>
-    <clock buffer_size="auto" C_wire="2.5e-10"/>
-  </clocks>
 </architecture>
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml
index f5a4b31fa..51f6824f9 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml
@@ -435,13 +435,4 @@
     </pb_type>
     <!-- Define general purpose logic block (CLB) ends -->
   </complexblocklist>
-  <power>
-    <local_interconnect C_wire="2.5e-10"/>
-    <mux_transistor_size mux_transistor_size="3"/>
-    <FF_size FF_size="4"/>
-    <LUT_transistor_size LUT_transistor_size="4"/>
-  </power>
-  <clocks>
-    <clock buffer_size="auto" C_wire="2.5e-10"/>
-  </clocks>
 </architecture>
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml
index 4594c6496..af4612b61 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml
@@ -1426,13 +1426,4 @@
     </pb_type>
     <!-- Define fracturable memory end -->
   </complexblocklist>
-  <power>
-    <local_interconnect C_wire="2.5e-10"/>
-    <mux_transistor_size mux_transistor_size="3"/>
-    <FF_size FF_size="4"/>
-    <LUT_transistor_size LUT_transistor_size="4"/>
-  </power>
-  <clocks>
-    <clock buffer_size="auto" C_wire="2.5e-10"/>
-  </clocks>
 </architecture>

From 773e6da308f66252414a633cb95475181692ebc2 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 12 Mar 2020 22:53:17 -0600
Subject: [PATCH 307/645] Spot a bug in lb router where path finder fail to use
 low-occupancy node when expanding the tree

---
 openfpga/src/repack/lb_router.cpp | 89 ++++++++++++++++++++++++++-----
 openfpga/src/repack/lb_router.h   |  2 +-
 openfpga/test_blif/and_latch.act  |  1 +
 openfpga/test_blif/and_latch.blif |  5 +-
 4 files changed, 81 insertions(+), 16 deletions(-)

diff --git a/openfpga/src/repack/lb_router.cpp b/openfpga/src/repack/lb_router.cpp
index 70b8e67b0..863be81ac 100644
--- a/openfpga/src/repack/lb_router.cpp
+++ b/openfpga/src/repack/lb_router.cpp
@@ -94,6 +94,11 @@ bool LbRouter::is_route_success(const LbRRGraph& lb_rr_graph) const {
 
   for (const LbRRNodeId& inode : lb_rr_graph.nodes()) {
     if (routing_status_[inode].occ > lb_rr_graph.node_capacity(inode)) {
+      VTR_LOGV(lb_rr_graph.node_pb_graph_pin(inode),
+               "Route failed due to overuse pin '%s': occupancy '%ld' > capacity '%ld'!\n",
+               lb_rr_graph.node_pb_graph_pin(inode)->to_string().c_str(),
+               routing_status_[inode].occ,
+               lb_rr_graph.node_capacity(inode));
       return false;
     }
   }
@@ -243,18 +248,22 @@ bool LbRouter::try_route_net(const LbRRGraph& lb_rr_graph,
        */
       sink_routed[isink] = !try_expand_nodes(atom_nlist, lb_rr_graph, net_idx, exp_node, isrc, isink, mode_status_.expand_all_modes, verbosity);
 
+      /* TODO: Debug codes, to be removed
       if (true == sink_routed[isink]) {
         VTR_LOGV(verbosity,
                  "Succeed to expand routing tree from source pin '%s' to sink pin '%s'!\n",
                  lb_rr_graph.node_pb_graph_pin(lb_net_sources_[net_idx][isrc])->to_string().c_str(),
                  lb_rr_graph.node_pb_graph_pin(lb_net_sinks_[net_idx][isink])->to_string().c_str());
       }
+       */
 
+      /* IMPORTANT: We do not need expand all the modes for physical repack
       if (false == sink_routed[isink] && false == mode_status_.expand_all_modes) {
         mode_status_.try_expand_all_modes = true;
         mode_status_.expand_all_modes = true;
         continue;
       }
+       */
 
       if (exp_node.node_index == lb_net_sinks_[net_idx][isink]) {
         /* Net terminal is routed, add this to the route tree, clear data structures, and keep going */
@@ -274,33 +283,60 @@ bool LbRouter::try_route_net(const LbRRGraph& lb_rr_graph,
         }
       }
 
+      /*
       if (true == sink_routed[isink]) {
         VTR_LOGV(verbosity,
                  "Routing succeeded from source pin '%s' to sink pin '%s'!\n",
                  lb_rr_graph.node_pb_graph_pin(lb_net_sources_[net_idx][isrc])->to_string().c_str(),
                  lb_rr_graph.node_pb_graph_pin(lb_net_sinks_[net_idx][isink])->to_string().c_str());
       }
+       */
 
-      explore_id_index_++;
-      if (explore_id_index_ > 2000000000) {
-        /* overflow protection */
+      /* Increment explored node indices only when routing is successful */
+      if (true == sink_routed[isink]) {
+        explore_id_index_++;
+        if (explore_id_index_ > 2000000000) {
+          /* overflow protection */
+          for (const LbRRNodeId& id : lb_rr_graph.nodes()) {
+            explored_node_tb_[id].explored_id = OPEN;
+            explored_node_tb_[id].enqueue_id = OPEN;
+            explore_id_index_ = 1;
+          }
+        }
+      } else {
+        /* Route failed, reset the explore id index */
+        reset_explored_node_tb();
         for (const LbRRNodeId& id : lb_rr_graph.nodes()) {
           explored_node_tb_[id].explored_id = OPEN;
           explored_node_tb_[id].enqueue_id = OPEN;
           explore_id_index_ = 1;
         }
       }
+    }
 
-      /* If routing succeed so far, we will try to save(commit) results
-       * to route tree.
-       * During this process, we will check if there is any 
-       * nodes using different modes under the same pb_type
-       * If so, we have conflicts and routing is considered to be failure
-       */
+    /* If any sinks are managed to be routed, we will try to save(commit) results
+     * to route tree.
+     * During this process, we will check if there is any 
+     * nodes using different modes under the same pb_type
+     * If so, we have conflicts and routing is considered to be failure
+     */
+    bool any_sink_routed = false;
+    for (size_t isink = 0; isink < sink_routed.size(); ++isink) {
       if (true == sink_routed[isink]) {
-        commit_remove_rt(lb_rr_graph, lb_net_rt_trees_[net_idx][isrc], RT_COMMIT, mode_map);
-        if (true == mode_status_.is_mode_conflict) {
-          sink_routed[isink] = false;
+        any_sink_routed = true;
+        break;
+      }
+    }
+    if (true == any_sink_routed) {
+      commit_remove_rt(lb_rr_graph, lb_net_rt_trees_[net_idx][isrc], RT_COMMIT, mode_map);
+      if (true == mode_status_.is_mode_conflict) {
+        VTR_LOGV(verbosity,
+                 "Route fail due to mode conflicts when commiting the routing tree!\n");
+        for (size_t isink = 0; isink < sink_routed.size(); ++isink) {
+          /* Change routed sinks to failure */
+          if (true == sink_routed[isink]) {
+            sink_routed[isink] = false;
+          }
         }
       }
     }
@@ -526,6 +562,11 @@ void LbRouter::commit_remove_rt(const LbRRGraph& lb_rr_graph,
     explored_node_tb_[inode].inet = NetId::INVALID();
   }
 
+  if (op == RT_COMMIT) {
+    VTR_LOGV(lb_rr_graph.node_pb_graph_pin(inode),
+             "Commit node '%s' to routing tree\n",
+             lb_rr_graph.node_pb_graph_pin(inode)->to_string().c_str());
+  }
   routing_status_[inode].occ += incr;
   VTR_ASSERT(routing_status_[inode].occ >= 0);
 
@@ -702,11 +743,23 @@ void LbRouter::expand_edges(const LbRRGraph& lb_rr_graph,
     if (explored_node_tb_[enode.node_index].enqueue_id == explore_id_index_) {
       if (enode.cost < explored_node_tb_[enode.node_index].enqueue_cost) {
         pq_.push(enode);
+        /*
+        if (nullptr != lb_rr_graph.node_pb_graph_pin(enode.node_index)) {
+          VTR_LOG("Added node '%s' to priority queue\n",
+                  lb_rr_graph.node_pb_graph_pin(enode.node_index)->to_string().c_str());
+        }
+         */
       }
     } else {
       explored_node_tb_[enode.node_index].enqueue_id = explore_id_index_;
       explored_node_tb_[enode.node_index].enqueue_cost = enode.cost;
       pq_.push(enode);
+      /*
+      if (nullptr != lb_rr_graph.node_pb_graph_pin(enode.node_index)) {
+        VTR_LOG("Added node '%s' to priority queue\n",
+                lb_rr_graph.node_pb_graph_pin(enode.node_index)->to_string().c_str());
+      }
+       */
     }
   }
 }
@@ -732,6 +785,14 @@ void LbRouter::expand_node(const LbRRGraph& lb_rr_graph,
     }
   }
 
+  /*
+  if (nullptr != mode) {
+    VTR_LOGV(lb_rr_graph.node_pb_graph_pin(cur_node),
+             "Expand node '%s' by considering mode '%s'\n",
+             lb_rr_graph.node_pb_graph_pin(cur_node)->to_string().c_str(),
+             mode->name);
+  }
+   */
   expand_edges(lb_rr_graph, mode, cur_node, cur_cost, net_fanout);
 }
 
@@ -782,7 +843,7 @@ bool LbRouter::try_expand_nodes(const AtomNetlist& atom_nlist,
                                 const int& isrc,
                                 const int& itarget,
                                 const bool& try_other_modes,
-                                const int& verbosity) {
+                                const bool& verbosity) {
   bool is_impossible = false;
 
   do {
@@ -790,7 +851,7 @@ bool LbRouter::try_expand_nodes(const AtomNetlist& atom_nlist,
       /* No connection possible */
       is_impossible = true;
 
-      if (verbosity > 3) {
+      if (true == verbosity) {
         //Print detailed debug info
         AtomNetId net_id = lb_net_atom_net_ids_[lb_net];
         AtomPinId driver_pin = lb_net_atom_source_pins_[lb_net][isrc];
diff --git a/openfpga/src/repack/lb_router.h b/openfpga/src/repack/lb_router.h
index d865c75b9..71020d1b4 100644
--- a/openfpga/src/repack/lb_router.h
+++ b/openfpga/src/repack/lb_router.h
@@ -321,7 +321,7 @@ class LbRouter {
                           const int& isrc,
                           const int& itarget,
                           const bool& try_other_modes,
-                          const int& verbosity);
+                          const bool& verbosity);
 
     bool try_route_net(const LbRRGraph& lb_rr_graph,
                        const AtomNetlist& atom_nlist,
diff --git a/openfpga/test_blif/and_latch.act b/openfpga/test_blif/and_latch.act
index 8089a8969..61bbe1fe8 100644
--- a/openfpga/test_blif/and_latch.act
+++ b/openfpga/test_blif/and_latch.act
@@ -3,3 +3,4 @@ b 0.502000 0.197200
 clk 0.500000 2.000000
 d 0.240200 0.171200
 c 0.240200 0.044100
+n1 0.240200 0.044100
diff --git a/openfpga/test_blif/and_latch.blif b/openfpga/test_blif/and_latch.blif
index a1925fffa..dbd863d9c 100644
--- a/openfpga/test_blif/and_latch.blif
+++ b/openfpga/test_blif/and_latch.blif
@@ -3,9 +3,12 @@
 .inputs a b clk
 .outputs c d
 
-.latch c d  re clk 0
+.latch n1 d  re clk 0
 
 .names a b c
 11 1
 
+.names c n1
+1 1
+
 .end

From 81e5af464e7fddba3f6f6e6c1ab79cecc72c0afb Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 12 Mar 2020 23:58:56 -0600
Subject: [PATCH 308/645] improve lb_route to avoid routing combinational loops

---
 openfpga/src/repack/lb_router.cpp | 25 ++++++++++++++++++++++++-
 1 file changed, 24 insertions(+), 1 deletion(-)

diff --git a/openfpga/src/repack/lb_router.cpp b/openfpga/src/repack/lb_router.cpp
index 863be81ac..e37c7fcdc 100644
--- a/openfpga/src/repack/lb_router.cpp
+++ b/openfpga/src/repack/lb_router.cpp
@@ -216,12 +216,24 @@ bool LbRouter::try_route_net(const LbRRGraph& lb_rr_graph,
                              std::unordered_map<const t_pb_graph_node*, const t_mode*>& mode_map,
                              const bool& verbosity) {
 
+  /* Quick check: if all the net can be skipped, we return route succeed */
+  bool skip_route = true;
+  for (size_t isrc = 0; isrc < lb_net_sources_[net_idx].size(); ++isrc) {
+    if (false == is_skip_route_net(lb_rr_graph, lb_net_rt_trees_[net_idx][isrc])) {
+      skip_route = false;
+      break;
+    }
+  }
+  if (true == skip_route) {
+    return true;
+  }
+
   std::vector<bool> sink_routed(lb_net_sinks_[net_idx].size(), false);
 
   for (size_t isrc = 0; isrc < lb_net_sources_[net_idx].size(); ++isrc) {
 
     if (true == is_skip_route_net(lb_rr_graph, lb_net_rt_trees_[net_idx][isrc])) {
-      return true;
+      continue;
     }
 
     commit_remove_rt(lb_rr_graph, lb_net_rt_trees_[net_idx][isrc], RT_REMOVE, mode_map);
@@ -232,6 +244,17 @@ bool LbRouter::try_route_net(const LbRRGraph& lb_rr_graph,
     /* Route each sink of net */
     for (size_t isink = 0; isink < lb_net_sinks_[net_idx].size(); ++isink) {
 
+      /* Do not route the sink if it share the same pb_type as source
+       * This is actually forbidden! This will definitely create a combinational loop
+       */
+      if ( (nullptr != lb_rr_graph.node_pb_graph_pin(lb_net_sinks_[net_idx][isink]))
+        && (nullptr != lb_rr_graph.node_pb_graph_pin(lb_net_sources_[net_idx][isrc])) ) {
+        if (lb_rr_graph.node_pb_graph_pin(lb_net_sinks_[net_idx][isink])->parent_node
+         == lb_rr_graph.node_pb_graph_pin(lb_net_sources_[net_idx][isrc])->parent_node) {
+          continue;
+        }
+      }
+
       /* Skip routed nets */
       if (true == sink_routed[isink]) {
         continue;

From 808853db0bd923c39b83cc3a7340a5de22d70509 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 13 Mar 2020 12:26:37 -0600
Subject: [PATCH 309/645] critical bug fixed for find proper pb_route traceback

---
 openfpga/src/repack/lb_router.cpp |  16 ---
 openfpga/src/repack/repack.cpp    | 226 +++++++++++++++++++-----------
 2 files changed, 142 insertions(+), 100 deletions(-)

diff --git a/openfpga/src/repack/lb_router.cpp b/openfpga/src/repack/lb_router.cpp
index e37c7fcdc..f7be853b1 100644
--- a/openfpga/src/repack/lb_router.cpp
+++ b/openfpga/src/repack/lb_router.cpp
@@ -244,17 +244,6 @@ bool LbRouter::try_route_net(const LbRRGraph& lb_rr_graph,
     /* Route each sink of net */
     for (size_t isink = 0; isink < lb_net_sinks_[net_idx].size(); ++isink) {
 
-      /* Do not route the sink if it share the same pb_type as source
-       * This is actually forbidden! This will definitely create a combinational loop
-       */
-      if ( (nullptr != lb_rr_graph.node_pb_graph_pin(lb_net_sinks_[net_idx][isink]))
-        && (nullptr != lb_rr_graph.node_pb_graph_pin(lb_net_sources_[net_idx][isrc])) ) {
-        if (lb_rr_graph.node_pb_graph_pin(lb_net_sinks_[net_idx][isink])->parent_node
-         == lb_rr_graph.node_pb_graph_pin(lb_net_sources_[net_idx][isrc])->parent_node) {
-          continue;
-        }
-      }
-
       /* Skip routed nets */
       if (true == sink_routed[isink]) {
         continue;
@@ -585,11 +574,6 @@ void LbRouter::commit_remove_rt(const LbRRGraph& lb_rr_graph,
     explored_node_tb_[inode].inet = NetId::INVALID();
   }
 
-  if (op == RT_COMMIT) {
-    VTR_LOGV(lb_rr_graph.node_pb_graph_pin(inode),
-             "Commit node '%s' to routing tree\n",
-             lb_rr_graph.node_pb_graph_pin(inode)->to_string().c_str());
-  }
   routing_status_[inode].occ += incr;
   VTR_ASSERT(routing_status_[inode].occ >= 0);
 
diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp
index 417cb6b95..2d0b2c3e8 100644
--- a/openfpga/src/repack/repack.cpp
+++ b/openfpga/src/repack/repack.cpp
@@ -21,15 +21,100 @@
 namespace openfpga {
 
 /***************************************************************************************
- * Try find the pin id which is mapped to a given atom net id in the context of pb route
+ * Try find all the sink pins which is mapped to a routing trace in the context of pb route
+ * This function uses a recursive walk-through over the pb_route
+ * We will always start from the pb_route of the source pin 
+ * For each sink, 
+ * - if it is the end point of a routing tree, we add it to the sink list
+ *   - An output of top-level pb_graph_node
+ *   - An input of a primitive pb_graph_node
+ * - if it is not the end point of a routing tree, we visit the pb_route 
+ *   corresponds to the sink pin
+ *
+ * Note: when you call this function at the top-level, please provide an empty vector
+ *       of sink_pb_pins!!!
+ ***************************************************************************************/
+static 
+void rec_find_routed_sink_pb_graph_pins(const t_pb* pb,
+                                        const t_pb_graph_pin* source_pb_pin,
+                                        const AtomNetId& atom_net_id,
+                                        t_pb_graph_pin** pb_graph_pin_lookup_from_index,
+                                        std::vector<t_pb_graph_pin*>& sink_pb_pins) {
+
+  /* Bypass unused pins */
+  if (0 == pb->pb_route.count(source_pb_pin->pin_count_in_cluster)) {
+    return;
+  }
+
+  /* Get the driver pb pin id, it must be valid */
+  if (atom_net_id != pb->pb_route[source_pb_pin->pin_count_in_cluster].atom_net_id) {
+    return;
+  }
+
+  /* Check each sink nodes, if pin belongs to an input of a primitive pb_graph_node, it is what we want */
+  std::vector<t_pb_graph_pin*> sink_pb_pins_to_search;
+  for (const int& sink_pb_pin_id : pb->pb_route[source_pb_pin->pin_count_in_cluster].sink_pb_pin_ids) {
+    t_pb_graph_pin* sink_pb_pin = pb_graph_pin_lookup_from_index[sink_pb_pin_id];
+    VTR_ASSERT(nullptr != sink_pb_pin);
+
+    /* We will update sink node list only
+     * - input pins of primitive nodes
+     * - output pins of top node 
+     */ 
+    if ( (true == is_primitive_pb_type(sink_pb_pin->parent_node->pb_type))
+      && (IN_PORT == sink_pb_pin->port->type)) {
+      sink_pb_pins.push_back(sink_pb_pin);
+      continue;
+    }
+
+    if ( (true == sink_pb_pin->parent_node->is_root())
+      && (OUT_PORT == sink_pb_pin->port->type)) {
+      sink_pb_pins.push_back(sink_pb_pin);
+      continue;
+    }
+
+    /* We should find the pb_route recursively */
+    sink_pb_pins_to_search.push_back(sink_pb_pin);
+  }
+
+  for (t_pb_graph_pin* sink_pb_pin : sink_pb_pins_to_search) {
+    rec_find_routed_sink_pb_graph_pins(pb, sink_pb_pin, atom_net_id, pb_graph_pin_lookup_from_index, sink_pb_pins);
+  }
+}
+
+/***************************************************************************************
+ * A wrapper for the recursive function rec_find_route_sink_pb_graph_pins(), 
+ * we ensure that we provide a clear sink node lists 
  ***************************************************************************************/
 static 
 std::vector<t_pb_graph_pin*> find_routed_pb_graph_pins_atom_net(const t_pb* pb,
+                                                                const t_pb_graph_pin* source_pb_pin,
                                                                 const AtomNetId& atom_net_id,
                                                                 t_pb_graph_pin** pb_graph_pin_lookup_from_index) {
   std::vector<t_pb_graph_pin*> sink_pb_pins;  
 
-  /* Find the sink nodes from top-level node */
+  rec_find_routed_sink_pb_graph_pins(pb, source_pb_pin, atom_net_id, pb_graph_pin_lookup_from_index, sink_pb_pins);
+
+  return sink_pb_pins; 
+}
+
+/***************************************************************************************
+ * This function will find the actual source_pb_pin that is mapped by packed in the pb route
+ * As the inputs of clustered block may be renamed during routing,
+ * our pb_route results may lose consistency.
+ * It is possible that the source pb_pin may not be mapped during packing but
+ * be mapped during routing
+ *
+ * Note: this is ONLY applicable to the pb_pin of top-level pb_graph_node 
+ ***************************************************************************************/
+static 
+int find_pb_route_remapped_source_pb_pin(const t_pb* pb,
+                                         const t_pb_graph_pin* source_pb_pin,
+                                         const AtomNetId& atom_net_id) {
+  VTR_ASSERT(true == source_pb_pin->parent_node->is_root()); 
+
+  std::vector<int> pb_route_indices;
+
   for (int pin = 0; pin < pb->pb_graph_node->total_pb_pins; ++pin) {
     /* Bypass unused pins */
     if ((0 == pb->pb_route.count(pin)) || (AtomNetId::INVALID() == pb->pb_route[pin].atom_net_id)) {
@@ -39,27 +124,15 @@ std::vector<t_pb_graph_pin*> find_routed_pb_graph_pins_atom_net(const t_pb* pb,
     if (atom_net_id != pb->pb_route[pin].atom_net_id) {
       continue;
     }
-    /* Check each sink nodes, if pin belongs to an input of a primitive pb_graph_node, it is what we want */
-    for (const int& sink_pb_pin_id : pb->pb_route[pin].sink_pb_pin_ids) {
-      t_pb_graph_pin* sink_pb_pin = pb_graph_pin_lookup_from_index[sink_pb_pin_id];
-      VTR_ASSERT(nullptr != sink_pb_pin);
-      /* We care only
-       * - input pins of primitive nodes
-       * - output pins of top node 
-       */ 
-      if ( (true == is_primitive_pb_type(sink_pb_pin->parent_node->pb_type))
-        && (IN_PORT == sink_pb_pin->port->type)) {
-        sink_pb_pins.push_back(sink_pb_pin);
-      }
-
-      if ( (true == sink_pb_pin->parent_node->is_root())
-        && (OUT_PORT == sink_pb_pin->port->type)) {
-        sink_pb_pins.push_back(sink_pb_pin);
-      }
-    }
+    /* Only care the pin that shares the same parent_node as source_pb_pin */
+    if (source_pb_pin->parent_node == pb->pb_route[pin].pb_graph_pin->parent_node) {
+      pb_route_indices.push_back(pin);
+    } 
   }
 
-  return sink_pb_pins;
+  VTR_ASSERT(1 == pb_route_indices.size());
+
+  return pb_route_indices[0];
 }
 
 /***************************************************************************************
@@ -154,6 +227,9 @@ void add_lb_router_nets(LbRouter& lb_router,
    */
   std::map<AtomNetId, std::array<std::vector<LbRRNodeId>, 2>> net_terminals;
 
+  /* A list showing that some sinks should be touched by some sources in a multi-source net */
+  std::map<AtomNetId, std::map<LbRRNodeId, std::vector<LbRRNodeId>>> invisible_sinks;
+
   /* Find the source nodes for the nets mapped to inputs of a clustered block */
   for (int j = 0; j < lb_type->pb_type->num_pins; j++) {
     /* Find the net mapped to this pin in clustering results*/
@@ -185,31 +261,36 @@ void add_lb_router_nets(LbRouter& lb_router,
     AtomNetId atom_net_id = atom_ctx.lookup.atom_net(cluster_net_id);
     VTR_ASSERT(AtomNetId::INVALID() != atom_net_id);
 
+
+    int pb_route_index = find_pb_route_remapped_source_pb_pin(pb, source_pb_pin, atom_net_id);
+    t_pb_graph_pin* packing_source_pb_pin = get_pb_graph_node_pin_from_block_pin(block_id, pb_route_index);
+    VTR_ASSERT(nullptr != packing_source_pb_pin);
+
     /* Find all the sink pins in the pb_route, we walk through the input pins and find the pin  */
-    std::vector<t_pb_graph_pin*> sink_pb_graph_pins = find_routed_pb_graph_pins_atom_net(pb, atom_net_id, pb_graph_pin_lookup_from_index);
+    std::vector<t_pb_graph_pin*> sink_pb_graph_pins = find_routed_pb_graph_pins_atom_net(pb, packing_source_pb_pin, atom_net_id, pb_graph_pin_lookup_from_index);
     std::vector<LbRRNodeId> sink_lb_rr_nodes = find_lb_net_physical_sink_lb_rr_nodes(lb_rr_graph, sink_pb_graph_pins, device_annotation);
     VTR_ASSERT(sink_lb_rr_nodes.size() == sink_pb_graph_pins.size());
 
-    /* Cache the net */
-    if (0 < net_terminals.count(atom_net_id)) {
-      if (net_terminals[atom_net_id][0].end() == std::find(net_terminals[atom_net_id][0].begin(), 
-                                                           net_terminals[atom_net_id][0].end(),
-                                                           source_lb_rr_node)) {
-        net_terminals[atom_net_id][0].push_back(source_lb_rr_node);
-      }
-
-      for (const LbRRNodeId& sink_lb_rr_node : sink_lb_rr_nodes) {
-        if (net_terminals[atom_net_id][1].end() == std::find(net_terminals[atom_net_id][1].begin(),
-                                                             net_terminals[atom_net_id][1].end(),
-                                                             sink_lb_rr_node)) {
-          net_terminals[atom_net_id][1].push_back(sink_lb_rr_node);
-        }
-      }
-    } else {
-      net_terminals[atom_net_id][0].push_back(source_lb_rr_node);
-      net_terminals[atom_net_id][1] = sink_lb_rr_nodes;
-      net_counter++;
+    /* Printf for debugging only, may be enabled if verbose is enabled
+    VTR_LOG("Pb route for Net %s:\n", 
+            atom_ctx.nlist.net_name(atom_net_id).c_str());
+    VTR_LOG("Source node:\n\t%s -> %s\n",
+            source_pb_pin->to_string().c_str(),
+            source_pb_pin->to_string().c_str());
+    VTR_LOG("Sink nodes:\n");
+    for (t_pb_graph_pin* sink_pb_pin : sink_pb_graph_pins) {
+      VTR_LOG("\t%s\n",
+              sink_pb_pin->to_string().c_str());
     }
+     */
+
+    /* Add the net */
+    add_lb_router_net_to_route(lb_router, lb_rr_graph,
+                               std::vector<LbRRNodeId>(1, source_lb_rr_node),
+                               sink_lb_rr_nodes,
+                               atom_ctx, atom_net_id);
+
+    net_counter++;
   }
 
   /* Find the source nodes for the nets mapped to outputs of primitive pb_graph_node */
@@ -248,58 +329,35 @@ void add_lb_router_nets(LbRouter& lb_router,
     VTR_ASSERT(AtomNetId::INVALID() != atom_net_id);
 
     /* Find all the sink pins in the pb_route */
-    std::vector<t_pb_graph_pin*> sink_pb_graph_pins = find_routed_pb_graph_pins_atom_net(pb, atom_net_id, pb_graph_pin_lookup_from_index);
+    std::vector<t_pb_graph_pin*> sink_pb_graph_pins = find_routed_pb_graph_pins_atom_net(pb, source_pb_pin, atom_net_id, pb_graph_pin_lookup_from_index);
+
     std::vector<LbRRNodeId> sink_lb_rr_nodes = find_lb_net_physical_sink_lb_rr_nodes(lb_rr_graph, sink_pb_graph_pins, device_annotation);
     VTR_ASSERT(sink_lb_rr_nodes.size() == sink_pb_graph_pins.size());
 
-    /* Cache the net */
-    if (0 < net_terminals.count(atom_net_id)) {
-      if (net_terminals[atom_net_id][0].end() == std::find(net_terminals[atom_net_id][0].begin(), 
-                                                           net_terminals[atom_net_id][0].end(),
-                                                           source_lb_rr_node)) {
-        net_terminals[atom_net_id][0].push_back(source_lb_rr_node);
-      }
-
-      for (const LbRRNodeId& sink_lb_rr_node : sink_lb_rr_nodes) {
-        if (net_terminals[atom_net_id][1].end() == std::find(net_terminals[atom_net_id][1].begin(),
-                                                             net_terminals[atom_net_id][1].end(),
-                                                             sink_lb_rr_node)) {
-          net_terminals[atom_net_id][1].push_back(sink_lb_rr_node);
-        }
-      }
-    } else {
-      net_terminals[atom_net_id][0].push_back(source_lb_rr_node);
-      net_terminals[atom_net_id][1] = sink_lb_rr_nodes;
-      net_counter++;
+    /* Printf for debugging only, may be enabled if verbose is enabled
+    VTR_LOG("Pb route for Net %s:\n", 
+            atom_ctx.nlist.net_name(atom_net_id).c_str());
+    VTR_LOG("Source node:\n\t%s -> %s\n",
+            source_pb_pin->to_string().c_str(),
+            physical_source_pb_pin->to_string().c_str());
+    VTR_LOG("Sink nodes:\n");
+    for (t_pb_graph_pin* sink_pb_pin : sink_pb_graph_pins) {
+      VTR_LOG("\t%s\n",
+              sink_pb_pin->to_string().c_str());
     }
+     */
+
+    /* Add the net */
+    add_lb_router_net_to_route(lb_router, lb_rr_graph,
+                               std::vector<LbRRNodeId>(1, source_lb_rr_node),
+                               sink_lb_rr_nodes,
+                               atom_ctx, atom_net_id);
+    net_counter++;
   } 
 
   /* Free */
   free_pb_graph_pin_lookup_from_index(pb_graph_pin_lookup_from_index);
 
-  /* Add all the nets */
-  for (std::pair<AtomNetId, std::array<std::vector<LbRRNodeId>, 2>> net_terminal_pair : net_terminals) {
-    const AtomNetId& atom_net_id = net_terminal_pair.first;
-
-    /* MUST have >1 source nodes and >1 sinks nodes */
-    if (0 == net_terminal_pair.second[0].size()) {
-      VTR_LOGF_ERROR(__FILE__, __LINE__,
-                     "Net '%s' has 0 source nodes!",
-                     atom_ctx.nlist.net_name(atom_net_id).c_str());
-    }
-
-    if (0 == net_terminal_pair.second[1].size()) {
-      VTR_LOGF_ERROR(__FILE__, __LINE__,
-                     "Net '%s' has 0 sink nodes!",
-                     atom_ctx.nlist.net_name(atom_net_id).c_str());
-    }
-
-    /* Add the net */
-    add_lb_router_net_to_route(lb_router, lb_rr_graph,
-                               net_terminal_pair.second[0], net_terminal_pair.second[1],
-                               atom_ctx, atom_net_id);
-  }
-
   VTR_LOGV(verbose,
            "Added %lu nets to be routed.\n",
            net_counter);

From 3647548526bdcdbe72197d04ed78be415cbf7eb2 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 20 Mar 2020 11:07:45 -0600
Subject: [PATCH 310/645] clean up on the shell echo commands

---
 libopenfpga/libopenfpgashell/src/shell.tpp | 10 +---------
 1 file changed, 1 insertion(+), 9 deletions(-)

diff --git a/libopenfpga/libopenfpgashell/src/shell.tpp b/libopenfpga/libopenfpgashell/src/shell.tpp
index 5bd4ec56c..24ef13dea 100644
--- a/libopenfpga/libopenfpgashell/src/shell.tpp
+++ b/libopenfpga/libopenfpgashell/src/shell.tpp
@@ -320,19 +320,11 @@ void Shell<T>::print_commands() const {
     /* Print the class name */
     VTR_LOG("%s:\n", command_class_names_[cmd_class].c_str());
 
-    size_t cnt = 0;
     for (const ShellCommandId& cmd : commands_by_classes_[cmd_class]) {
       /* Print the command names in this class
        * but limited4 command per line for a clean layout
        */
-      VTR_LOG("%s", commands_[cmd].name().c_str());
-      cnt++;
-      if (4 == cnt) {
-        VTR_LOG("\n");
-        cnt = 0;
-      } else {
-        VTR_LOG("\t");
-      } 
+      VTR_LOG("\t%s\n", commands_[cmd].name().c_str());
     }
 
     /* Put a new line in the end as a splitter */

From 8d57808d07029fb7955a868314aa211ae106e53f Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 20 Mar 2020 11:08:55 -0600
Subject: [PATCH 311/645] add missing files for micro benchmarks

---
 openfpga/test_blif/and.act | 3 +++
 1 file changed, 3 insertions(+)
 create mode 100644 openfpga/test_blif/and.act

diff --git a/openfpga/test_blif/and.act b/openfpga/test_blif/and.act
new file mode 100644
index 000000000..0f77bc6b3
--- /dev/null
+++ b/openfpga/test_blif/and.act
@@ -0,0 +1,3 @@
+a 0.5 0.5
+b 0.5 0.5
+c 0.25 0.25

From a0b150f12e6c6682bb65bd8b275bca6659fa9e53 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 20 Mar 2020 14:18:59 -0600
Subject: [PATCH 312/645] adding micro architecture using adder chain

---
 libs/libarchfpga/src/read_xml_arch_file.cpp   |  25 +-
 .../and_k6_frac_adder_chain.openfpga          |  59 ++
 openfpga/test_vpr_arch/k6_frac_N10_40nm.xml   |   3 +-
 .../k6_frac_N10_adder_chain_40nm.xml          | 630 ++++++++++++++++++
 4 files changed, 706 insertions(+), 11 deletions(-)
 create mode 100644 openfpga/test_script/and_k6_frac_adder_chain.openfpga
 create mode 100644 openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml

diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp
index 1c2bba875..b3b4004b2 100644
--- a/libs/libarchfpga/src/read_xml_arch_file.cpp
+++ b/libs/libarchfpga/src/read_xml_arch_file.cpp
@@ -2900,21 +2900,26 @@ static void ProcessDevice(pugi::xml_node Node, t_arch* arch, t_default_fc_spec&
                        "Unknown property %s for switch block type x\n", Prop);
     }
 
-    Prop = get_attribute(Cur, "sub_type", loc_data, BoolToReqOpt(false)).value();
-    if (strcmp(Prop, "wilton") == 0) {
-        arch->SBSubType = WILTON;
-    } else if (strcmp(Prop, "universal") == 0) {
-        arch->SBSubType = UNIVERSAL;
-    } else if (strcmp(Prop, "subset") == 0) {
-        arch->SBSubType = SUBSET;
+    std::string sub_type_str = get_attribute(Cur, "sub_type", loc_data, BoolToReqOpt(false)).as_string("");
+    /* If not specified, we set the same value as 'type' */
+    if (!sub_type_str.empty()) {
+        if (sub_type_str == std::string("wilton")) {
+            arch->SBSubType = WILTON;
+        } else if (sub_type_str == std::string("universal")) {
+            arch->SBSubType = UNIVERSAL;
+        } else if (sub_type_str == std::string("subset")) {
+            arch->SBSubType = SUBSET;
+        } else {
+            archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur),
+                           "Unknown property %s for switch block subtype x\n", Prop);
+        }
     } else {
-        archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur),
-                       "Unknown property %s for switch block subtype x\n", Prop);
+        arch->SBSubType = arch->SBType;
     }
 
     ReqOpt CUSTOM_SWITCHBLOCK_REQD = BoolToReqOpt(!custom_switch_block);
     arch->Fs = get_attribute(Cur, "fs", loc_data, CUSTOM_SWITCHBLOCK_REQD).as_int(3);
-    arch->subFs = get_attribute(Cur, "sub_fs", loc_data,  BoolToReqOpt(false)).as_int(3);
+    arch->subFs = get_attribute(Cur, "sub_fs", loc_data,  BoolToReqOpt(false)).as_int(arch->Fs);
 
     Cur = get_single_child(Node, "default_fc", loc_data, ReqOpt::OPTIONAL);
     if (Cur) {
diff --git a/openfpga/test_script/and_k6_frac_adder_chain.openfpga b/openfpga/test_script/and_k6_frac_adder_chain.openfpga
new file mode 100644
index 000000000..2de7e14ab
--- /dev/null
+++ b/openfpga/test_script/and_k6_frac_adder_chain.openfpga
@@ -0,0 +1,59 @@
+# Run VPR for the 'and' design
+vpr ./test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml ./test_blif/and.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml
+
+## Read OpenFPGA architecture definition
+#read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+#
+## Write out the architecture XML as a proof
+##write_openfpga_arch -f ./arch_echo.xml
+#
+## Annotate the OpenFPGA architecture to VPR data base
+#link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose
+#
+## Check and correct any naming conflicts in the BLIF netlist
+#check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+#
+## Apply fix-up to clustering nets based on routing results
+#pb_pin_fixup --verbose
+#
+## Apply fix-up to Look-Up Table truth tables based on packing results
+#lut_truth_table_fixup #--verbose
+#
+## Build the module graph 
+##  - Enabled compression on routing architecture modules
+##  - Enable pin duplication on grid modules 
+#build_fabric --compress_routing --duplicate_grid_pin #--verbose
+#
+## Repack the netlist to physical pbs
+## This must be done before bitstream generator and testbench generation
+## Strongly recommend it is done after all the fix-up have been applied
+#repack #--verbose
+#
+## Build the bitstream 
+##  - Output the fabric-independent bitstream to a file
+#build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
+#
+## Build fabric-dependent bitstream
+#build_fabric_bitstream --verbose
+#
+## Write the Verilog netlist for FPGA fabric
+##  - Enable the use of explicit port mapping in Verilog netlist
+#write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
+#
+## Write the Verilog testbench for FPGA fabric
+##  - We suggest the use of same output directory as fabric Verilog netlists
+##  - Must specify the reference benchmark file if you want to output any testbenches
+##  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+##  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+##  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+#write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
+#
+## Write the SDC files for PnR backend
+##  - Turn on every options here 
+#write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
+#
+## Write the SDC to run timing analysis for a mapped FPGA fabric
+#write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
+#
+# Finish and exit OpenFPGA
+exit
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml
index 51f6824f9..8f58cb221 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml
@@ -135,6 +135,7 @@
     <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
 			     With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
 			     reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
     <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
       <mux name="0"/>
       <sb type="pattern">1 1 1 1 1</sb>
@@ -227,7 +228,7 @@
         <output name="out" num_pins="2"/>
         <clock name="clk" num_pins="1"/>
         <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical">
+        <mode name="physical" disabled_in_pack="true">
           <pb_type name="fabric" num_pb="1">
             <input name="in" num_pins="6"/>
             <output name="out" num_pins="2"/>
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
new file mode 100644
index 000000000..4bce8ac18
--- /dev/null
+++ b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
@@ -0,0 +1,630 @@
+<!-- 
+  Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with 8 total FLE inputs (2 inputs of which are shared by the 5-LUTs) 
+    with optionally registered outputs
+    Each 5-LUT has an arithemtic mode that converts it to a single-bit adder with both inputs driven by 4-LUTs (both 4-LUTs share all 4 inputs)
+    Carry chain links to vertically adjacent logic blocks
+  - Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.  
+    Height = 6, found on every (8n+2)th column
+  - Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.  
+    Height = 4, found on every (8n+6)th column
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Details on Modelling:
+
+  The electrical design of the architecture described here is NOT from an 
+  optimized, SPICED architecture.  Instead, we attempt to create a reasonable 
+  architecture file by using an existing commercial FPGA to approximate the area, 
+  delay, and power of the underlying components. This is combined with a reasonable 40 nm 
+  model of wiring and circuit design for low-level routing components, where available.
+  The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also 
+  has wiring electrical parameters that allow the wire lengths and switch patterns to be 
+  modified and you will still get reasonable delay results for the new architecture.
+  The following describes, in detail, how we obtained the various electrical values for this 
+  architecture.
+
+  Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar 
+  architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture. 
+  (n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)      
+  This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to 
+  match the overall target (a 40 nm FPGA).
+
+  We obtain delay numbers by measuring delays of routing, soft logic blocks, 
+  memories, and multipliers from test circuits on a Stratix IV GX device 
+  (EP4SGX230DF29C2X, i.e. fastest speed grade). For routing, we took the average delay of H4 and V4 
+  wires.  Rmetal and Cmetal values for the routing wires were obtained from work done by Charles 
+  Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal stack 40 nm routing) and 
+  take the R and C data from the ITRS roadmap.  
+
+  For the general purpose logic block, we assume that the area and delays of the Stratix IV 
+  crossbar is close enough to the crossbar modelled here.  
+  Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to 
+  36:1 multiplexers.  We match these parameters in this architecture.
+
+  For LUTs, we include LUT 
+  delays measured from Stratix IV which is dependant on the input used (ie. some 
+  LUT inputs are faster than others).  The CAD tools at the time of VTR 7 does 
+  not consider differences in LUT input delays.
+
+  Adder delays obtained as approximate values from a Stratix IV EP4SE230F29C3 device.  
+  Delay obtained by compiling a 256 bit adder (registered inputs and outputs, 
+  all pins except clock virtual) then measuring the delays in chip-planner, 
+  sumout delay = 0.271ns to 0.348 ns, intra-block carry delay = 0.011 ns, 
+  inter-block carry delay = 0.327 ns.  Given this data, I will approximate 
+  sumout 0.3 ns, intra-block carry-delay = 0.01 ns, and 
+  inter-block carry-delay = 0.16 ns (since Altera inter-block carry delay has 
+  overhead that we don't have, I'll approximate the delay of a simpler chain at 
+  one half what they have.  This is very rough, anything from 0.01ns to 0.327ns 
+  can be justified).
+
+  Logic block area numbers obtained by scaling overall tile area of a 65nm 
+  Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out 
+  routing area at a channel width of 300. We use a channel width of 300 because it can route 
+  all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
+  total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
+  choosing a width that provides high routability. The architecture can be routed at different channel
+  widths, but we estimate the tile size and hence the physical length of routing wires assuming
+  a channel width of 300.
+
+  Sanity checks employed:
+    1.  We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches 
+        common electrical design.
+
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <model name="adder">
+      <input_ports>
+        <port name="a" combinational_sink_ports="sumout cout"/>
+        <port name="b" combinational_sink_ports="sumout cout"/>
+        <port name="cin" combinational_sink_ports="sumout cout"/>
+      </input_ports>
+      <output_ports>
+        <port name="cout"/>
+        <port name="sumout"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="frac_lut6">
+      <input_ports>
+        <port name="in"/>
+      </input_ports>
+      <output_ports>
+        <port name="lut4_out"/>
+        <port name="lut5_out"/>
+        <port name="lut6_out"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <tile name="io" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad</loc>
+        <loc side="top">io.outpad io.inpad</loc>
+        <loc side="right">io.outpad io.inpad</loc>
+        <loc side="bottom">io.outpad io.inpad</loc>
+      </pinlocations>
+    </tile>
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
+      </fc>
+      <pinlocations pattern="spread"/>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout tileable="true">
+    <auto_layout aspect_ratio="1.0">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </auto_layout>
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	    -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+           book area formula. This means the mux transistors are about 5x minimum drive strength.
+           We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+           mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+           the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+           by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+           buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+           I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+           (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+           The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+           2.5x when looking up in Jeff's tables.
+           Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+           This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+             With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+             reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <directlist>
+    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
+  </directlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+
+      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+           If you need to register the I/O, define clocks in the circuit models
+           These clocks can be handled in back-end
+       -->
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" disabled_in_pack="true">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe fracturable logic element.  
+             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
+             The outputs of the fracturable logic element can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="10">
+        <input name="in" num_pins="6"/>
+        <input name="cin" num_pins="1"/>
+        <output name="out" num_pins="2"/>
+        <output name="cout" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- Physical mode definition begin (physical implementation of the fle) -->
+        <mode name="physical" disabled_in_pack="true">
+          <pb_type name="fabric" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="frac_logic" num_pb="1">
+              <input name="in" num_pins="6"/>
+              <output name="lut4_out" num_pins="4"/>
+              <output name="out" num_pins="2"/>
+              <!-- Define LUT -->
+              <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
+                <input name="in" num_pins="6"/>
+                <output name="lut4_out" num_pins="4"/>
+                <output name="lut5_out" num_pins="2"/>
+                <output name="lut6_out" num_pins="1"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
+                <direct name="direct2" input="frac_lut6.lut4_out" output="frac_logic.lut4_out"/>
+                <direct name="direct3" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
+                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
+                <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
+              </interconnect>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>         
+            <!-- Define adders -->
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="2">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
+              <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
+              <direct name="direct3" input="fabric.cin" output="adder[0:0].cin"/>
+              <direct name="direct4" input="adder[0:0].cout" output="adder[1:1].cin"/>
+              <direct name="direct5" input="adder[1:1].cout" output="fabric.cout"/>
+              <direct name="direct6" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
+              <direct name="direct7" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
+              <direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].b"/>
+              <direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
+              <complete name="direct10" input="fabric.clk" output="ff[1:0].clk"/>
+              <mux name="mux1" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
+                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
+              </mux>
+              <mux name="mux2" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
+                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="fabric.in"/>
+            <direct name="direct2" input="fle.cin" output="fabric.cin"/>
+            <direct name="direct3" input="fabric.out" output="fle.out"/>
+            <direct name="direct4" input="fabric.cout" output="fle.cout"/>
+            <direct name="direct5" input="fle.clk" output="fabric.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Physical mode definition end (physical implementation of the fle) -->
+        <!-- BEGIN fle mode of dual lut5 -->
+        <mode name="n2_lut5">
+          <pb_type name="ble5" num_pb="2">
+            <input name="in" num_pins="5"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Regular LUT mode -->
+            <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="5" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                  we instead take the average of these numbers to get more stable results
+                82e-12
+                173e-12
+                261e-12
+                263e-12
+                398e-12
+                -->
+              <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+              </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble5.in" output="lut5.in"/>
+              <direct name="direct2" input="lut5.out" output="ff.D">
+                <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble5.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut5.out" output="ble5.out">
+                <delay_constant max="25e-12" in_port="lut5.out" out_port="ble5.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble5.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[4:0]" output="ble5[0:0].in"/>
+            <direct name="direct2" input="fle.in[4:0]" output="ble5[1:1].in"/>
+            <complete name="direct3" input="fle.clk" output="ble5.clk"/>
+            <direct name="direct4" input="ble5.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- END fle mode of dual lut5 -->
+        <!-- BEGIN arithmetic mode of dual lut4 + adders -->
+        <mode name="arithmetic">
+          <pb_type name="arithmetic" num_pb="2">
+            <input name="in" num_pins="4"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="1"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Special dual-LUT mode that drives adder only -->
+            <pb_type name="lut4" blif_model=".names" num_pb="4" class="lut">
+              <input name="in" num_pins="4" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  -->
+              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                  195e-12
+                  195e-12
+                  195e-12
+                  195e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
+              <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
+              <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
+              <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
+                </direct>
+              <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
+                </direct>
+              <direct name="add_to_ff" input="adder.sumout" output="ff.D">
+                <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
+              </direct>
+              <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
+                <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
+              </direct>
+              <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
+                <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
+              </direct>
+              <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
+                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[3:0]" output="arithmetic[0:0].in"/>
+            <direct name="direct2" input="fle.in[3:0]" output="arithmetic[1:1].in"/>
+            <direct name="carry_in" input="fle.cin" output="arithmetic[0:0].cin">
+              <pack_pattern name="chain" in_port="fle.cin" out_port="arithmetic[0:0].cin"/>
+            </direct>
+            <direct name="carry_inter" input="arithmetic[0:0].cout" output="arithmetic[1:1].cin">
+              <pack_pattern name="chain" in_port="arithmetic[0:0].cout" out_port="arithmetic[1:1].cin"/>
+            </direct>
+            <direct name="carry_out" input="arithmetic[1:1].cout" output="fle.cout">
+              <pack_pattern name="chain" in_port="arithmetic.cout" out_port="fle.cout"/>
+            </direct>
+            <complete name="direct3" input="fle.clk" output="arithmetic.clk"/>
+            <direct name="direct4" input="arithmetic.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- n2_lut5 -->
+        <mode name="n1_lut6">
+          <pb_type name="ble6" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="6" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->
+              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+              <direct name="direct2" input="lut6.out" output="ff.D">
+                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
+            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+          </interconnect>
+        </mode>
+        <!-- n1_lut6 -->
+      </pb_type>
+      <interconnect>
+        <!-- We use a 50% depop crossbar built using small full xbars to get sets of logically equivalent pins at inputs of CLB 
+           The delays below come from Stratix IV. the delay through a connection block
+           input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+           delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+           delay within the crossbar is 95 ps. 
+           The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+           Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+           25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+           to get the part that should be marked on the crossbar.	 -->
+        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
+          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
+          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
+        </complete>
+
+        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+        </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+                 By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+                 then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+                 naive specification).
+          -->
+        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
+        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
+        <!-- Carry chain links -->
+        <direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
+          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
+        </direct>
+        <direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
+          <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
+        </direct>
+        <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
+          <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
+        </direct>
+      </interconnect>
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+  </complexblocklist>
+</architecture>

From 9837be618d25bd7a3ace45891df38343927a1f6c Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 20 Mar 2020 14:52:52 -0600
Subject: [PATCH 313/645] start debugging tile direct with micro architecture

---
 .../k6_frac_N10_adder_chain_40nm_openfpga.xml | 289 ++++++++++++++++++
 .../and_k6_frac_adder_chain.openfpga          | 108 +++----
 .../k6_frac_N10_adder_chain_40nm.xml          |   8 +-
 3 files changed, 347 insertions(+), 58 deletions(-)
 create mode 100644 openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml

diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
new file mode 100644
index 000000000..ed0de93f1
--- /dev/null
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
@@ -0,0 +1,289 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
+      <design_technology type="cmos" topology="OR"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <!--mux2to1 subckt_name="mux2to1"/-->
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <!--mux2to1 subckt_name="mux2to1"/-->
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <!--mux2to1 subckt_name="mux2to1"/-->
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <pass_gate_logic circuit_model_name="TGATE"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
+      <design_technology type="cmos" fracturable_lut="true"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="6" tri_state_map="----11" circuit_model_name="OR2"/>
+      <port type="output" prefix="lut4_out" size="4" lut_frac_level="4" lut_output_mask="0,1,2,3"/>
+      <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
+      <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
+      <port type="sram" prefix="sram" size="64"/>
+      <port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <pass_gate_logic circuit_model_name="TGATE"/>
+       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="Qb" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="inout" prefix="pad" size="1"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+      <port type="input" prefix="outpad" size="1"/>
+      <port type="output" prefix="inpad" size="1"/>
+    </circuit_model>
+    <circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="input" prefix="cin" size="1"/>
+      <port type="output" prefix="sumout" size="1"/>
+      <port type="output" prefix="cout" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle" physical_mode_name="physical"/>
+    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
+    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
+    <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="adder"/>
+    <!-- Binding operating pb_type to physical pb_type -->
+    <!-- Binding operating pb_types in mode 'n2_lut5' -->
+    <pb_type name="clb.fle[n2_lut5].ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5">
+      <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:4]"/>
+      <port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[n2_lut5].ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <!-- Binding operating pb_types in mode 'arithmetic' -->
+    <pb_type name="clb.fle[arithmetic].arithmetic.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="11" physical_pb_type_index_factor="0.25">
+      <!-- Binding the lut4 to the first 4 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:3]"/>
+      <port name="out" physical_mode_port="lut4_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[arithmetic].arithmetic.adder" physical_pb_type_name="clb.fle[physical].fabric.adder"/>
+    <pb_type name="clb.fle[arithmetic].arithmetic.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <!-- Binding operating pb_types in mode 'ble6' -->
+    <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="00">
+      <!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:5]"/>
+      <port name="out" physical_mode_port="lut6_out"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>
+<openfpga_simulation_setting>
+  <clock_setting>
+    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
+    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
+    <programming frequency="10e6"/>
+  </clock_setting>
+  <simulator_option>
+    <operating_condition temperature="25"/>
+    <output_log verbose="false" captab="false"/>
+    <accuracy type="abs" value="1e-13"/>
+    <runtime fast_simulation="true"/>
+  </simulator_option>
+  <monte_carlo num_simulation_points="2"/>
+  <measurement_setting>
+    <slew>
+      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
+      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
+    </slew>
+    <delay>
+      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
+      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
+    </delay>
+  </measurement_setting>
+  <stimulus>
+    <clock>
+      <rise slew_type="abs" slew_time="20e-12" />
+      <fall slew_type="abs" slew_time="20e-12" />
+    </clock>
+    <input>
+      <rise slew_type="abs" slew_time="25e-12" />
+      <fall slew_type="abs" slew_time="25e-12" />
+    </input>
+  </stimulus>
+</openfpga_simulation_setting>
diff --git a/openfpga/test_script/and_k6_frac_adder_chain.openfpga b/openfpga/test_script/and_k6_frac_adder_chain.openfpga
index 2de7e14ab..3f8b65f29 100644
--- a/openfpga/test_script/and_k6_frac_adder_chain.openfpga
+++ b/openfpga/test_script/and_k6_frac_adder_chain.openfpga
@@ -1,59 +1,59 @@
 # Run VPR for the 'and' design
 vpr ./test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml ./test_blif/and.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml
 
-## Read OpenFPGA architecture definition
-#read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
-#
-## Write out the architecture XML as a proof
-##write_openfpga_arch -f ./arch_echo.xml
-#
-## Annotate the OpenFPGA architecture to VPR data base
-#link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose
-#
-## Check and correct any naming conflicts in the BLIF netlist
-#check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
-#
-## Apply fix-up to clustering nets based on routing results
-#pb_pin_fixup --verbose
-#
-## Apply fix-up to Look-Up Table truth tables based on packing results
-#lut_truth_table_fixup #--verbose
-#
-## Build the module graph 
-##  - Enabled compression on routing architecture modules
-##  - Enable pin duplication on grid modules 
-#build_fabric --compress_routing --duplicate_grid_pin #--verbose
-#
-## Repack the netlist to physical pbs
-## This must be done before bitstream generator and testbench generation
-## Strongly recommend it is done after all the fix-up have been applied
-#repack #--verbose
-#
-## Build the bitstream 
-##  - Output the fabric-independent bitstream to a file
-#build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
-#
-## Build fabric-dependent bitstream
-#build_fabric_bitstream --verbose
-#
-## Write the Verilog netlist for FPGA fabric
-##  - Enable the use of explicit port mapping in Verilog netlist
-#write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
-#
-## Write the Verilog testbench for FPGA fabric
-##  - We suggest the use of same output directory as fabric Verilog netlists
-##  - Must specify the reference benchmark file if you want to output any testbenches
-##  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
-##  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
-##  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-#write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
-#
-## Write the SDC files for PnR backend
-##  - Turn on every options here 
-#write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
-#
-## Write the SDC to run timing analysis for a mapped FPGA fabric
-#write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
-#
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
+
+# Write out the architecture XML as a proof
+#write_openfpga_arch -f ./arch_echo.xml
+
+# Annotate the OpenFPGA architecture to VPR data base
+link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to clustering nets based on routing results
+pb_pin_fixup --verbose
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup #--verbose
+
+# Build the module graph 
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules 
+build_fabric --compress_routing --duplicate_grid_pin #--verbose
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream 
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here 
+write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
+
 # Finish and exit OpenFPGA
 exit
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
index 4bce8ac18..ed928c98d 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
@@ -368,15 +368,15 @@
               <direct name="direct5" input="adder[1:1].cout" output="fabric.cout"/>
               <direct name="direct6" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
               <direct name="direct7" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
-              <direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].b"/>
+              <direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
               <direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
               <complete name="direct10" input="fabric.clk" output="ff[1:0].clk"/>
-              <mux name="mux1" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+              <mux name="mux1" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
                 <!-- LUT to output is faster than FF to output on a Stratix IV -->
                 <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
                 <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
               </mux>
-              <mux name="mux2" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+              <mux name="mux2" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
                 <!-- LUT to output is faster than FF to output on a Stratix IV -->
                 <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
                 <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
@@ -455,7 +455,7 @@
             <output name="cout" num_pins="1"/>
             <clock name="clk" num_pins="1"/>
             <!-- Special dual-LUT mode that drives adder only -->
-            <pb_type name="lut4" blif_model=".names" num_pb="4" class="lut">
+            <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
               <input name="in" num_pins="4" port_class="lut_in"/>
               <output name="out" num_pins="1" port_class="lut_out"/>
               <!-- LUT timing using delay matrix -->

From a46fc9f028ab36c142314a544598c9d4ac522141 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 20 Mar 2020 14:59:46 -0600
Subject: [PATCH 314/645] add debugging information for tile direct builder

---
 openfpga/src/tile_direct/build_tile_direct.cpp              | 6 +++++-
 .../k6_frac_N10_adder_chain_40nm_openfpga.xml               | 3 +++
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/openfpga/src/tile_direct/build_tile_direct.cpp b/openfpga/src/tile_direct/build_tile_direct.cpp
index 676fa8291..ba426ce17 100644
--- a/openfpga/src/tile_direct/build_tile_direct.cpp
+++ b/openfpga/src/tile_direct/build_tile_direct.cpp
@@ -656,7 +656,11 @@ TileDirect build_device_tile_direct(const DeviceContext& device_ctx,
   /* Walk through each direct definition in the VPR arch */
   for (int idirect = 0; idirect < device_ctx.arch->num_directs; ++idirect) {
     ArchDirectId arch_direct_id = arch_direct.direct(std::string(device_ctx.arch->Directs[idirect].name));
-    VTR_ASSERT(ArchDirectId::INVALID() != arch_direct_id);
+    if (ArchDirectId::INVALID() == arch_direct_id) {
+      VTR_LOG_ERROR("Unable to find an annotation in openfpga architecture XML for <direct> '%s'!\n",
+                    device_ctx.arch->Directs[idirect].name);
+      exit(1);
+    }
     /* Build from original VPR arch definition */
     build_inner_column_row_tile_direct(tile_direct,
                                        device_ctx.arch->Directs[idirect],
diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
index ed0de93f1..2b340168e 100644
--- a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
@@ -209,6 +209,9 @@
   <routing_segment>
     <segment name="L4" circuit_model_name="chan_segment"/>
   </routing_segment>
+  <direct_connection>
+    <direct name="adder" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
+  </direct_connection>
   <pb_type_annotations>
     <!-- physical pb_type binding in complex block IO -->
     <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>

From c5049a1ec83c25ee2282fa2ee38575b0a4ebf457 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 20 Mar 2020 15:10:00 -0600
Subject: [PATCH 315/645] keep debugging tile direct connections

---
 .../k6_frac_N10_adder_chain_40nm_openfpga.xml            | 2 +-
 openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml  | 9 ++++++++-
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
index 2b340168e..98823698f 100644
--- a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
@@ -210,7 +210,7 @@
     <segment name="L4" circuit_model_name="chan_segment"/>
   </routing_segment>
   <direct_connection>
-    <direct name="adder" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
+    <direct name="adder_carry" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
   </direct_connection>
   <pb_type_annotations>
     <!-- physical pb_type binding in complex block IO -->
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
index ed928c98d..ed6e2defc 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
@@ -147,7 +147,14 @@
         <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
         <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
       </fc>
-      <pinlocations pattern="spread"/>
+      <!--  Highly recommand to customize pin location when direct connection is used!!! -->
+      <!--pinlocations pattern="spread"/-->
+      <pinlocations pattern="custom">
+        <loc side="left">clb.clk</loc>
+        <loc side="top">clb.cin</loc>
+        <loc side="right">clb.O[9:0] clb.I[19:0]</loc>
+        <loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
+      </pinlocations>
     </tile>
   </tiles>
   <!-- ODIN II specific config ends -->

From 708fda9606ed1003a2e8be53a88874684e54005d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 20 Mar 2020 16:38:58 -0600
Subject: [PATCH 316/645] fixed a bug in using tileable routing when directlist
 is enabled

---
 libs/libarchfpga/src/read_xml_arch_file.cpp   |  2 +-
 .../and_k6_frac_adder_chain.openfpga          |  2 +-
 .../k6_frac_N10_adder_chain_40nm.xml          |  6 +++--
 vpr/src/base/SetupVPR.cpp                     |  3 +++
 vpr/src/base/place_and_route.cpp              |  5 ++++
 vpr/src/base/vpr_api.cpp                      |  2 +-
 vpr/src/base/vpr_types.h                      |  3 +++
 vpr/src/route/route_common.cpp                |  5 ++++
 .../rr_graph_builder_utils.cpp                | 14 +++++++++++
 .../rr_graph_builder_utils.h                  |  3 +++
 vpr/src/tileable_rr_graph/rr_gsb.cpp          |  8 +++++++
 .../tileable_rr_graph_gsb.cpp                 | 24 +++++++++++++++++--
 12 files changed, 70 insertions(+), 7 deletions(-)

diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp
index b3b4004b2..cf7c97133 100644
--- a/libs/libarchfpga/src/read_xml_arch_file.cpp
+++ b/libs/libarchfpga/src/read_xml_arch_file.cpp
@@ -2536,7 +2536,7 @@ static void ProcessLayout(pugi::xml_node layout_tag, t_arch* arch, const pugiuti
     //Expect only tileable attributes on <layout>
     //expect_only_attributes(layout_tag, {"tileable"}, loc_data);
 
-    arch->tileable = get_attribute(layout_tag, "tileable", loc_data).as_bool();
+    arch->tileable = get_attribute(layout_tag, "tileable", loc_data).as_bool(false);
 
     //Count the number of <auto_layout> or <fixed_layout> tags
     size_t auto_layout_cnt = 0;
diff --git a/openfpga/test_script/and_k6_frac_adder_chain.openfpga b/openfpga/test_script/and_k6_frac_adder_chain.openfpga
index 3f8b65f29..156f49ff0 100644
--- a/openfpga/test_script/and_k6_frac_adder_chain.openfpga
+++ b/openfpga/test_script/and_k6_frac_adder_chain.openfpga
@@ -1,5 +1,5 @@
 # Run VPR for the 'and' design
-vpr ./test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml ./test_blif/and.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml
+vpr ./test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml
 
 # Read OpenFPGA architecture definition
 read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
index ed6e2defc..e390112e7 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
@@ -160,13 +160,15 @@
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
   <layout tileable="true">
-    <auto_layout aspect_ratio="1.0">
+    <!--auto_layout aspect_ratio="1.0"-->
+    <fixed_layout name="2x2" width="3" height="4">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
       <corners type="EMPTY" priority="101"/>
       <!--Fill with 'clb'-->
       <fill type="clb" priority="10"/>
-    </auto_layout>
+    </fixed_layout>
+    <!-- /auto_layout -->
   </layout>
   <device>
     <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp
index 0cf69a9bb..a43f5b80a 100644
--- a/vpr/src/base/SetupVPR.cpp
+++ b/vpr/src/base/SetupVPR.cpp
@@ -321,6 +321,9 @@ static void SetupRoutingArch(const t_arch& Arch,
 
     /* copy over the switch block information */
     RoutingArch->switchblocks = Arch.switchblocks;
+
+    /* Copy the tileable routing setting */
+    RoutingArch->tileable = Arch.tileable;
 }
 
 static void SetupRouterOpts(const t_options& Options, t_router_opts* RouterOpts) {
diff --git a/vpr/src/base/place_and_route.cpp b/vpr/src/base/place_and_route.cpp
index 0f47ebebb..c13a1e393 100644
--- a/vpr/src/base/place_and_route.cpp
+++ b/vpr/src/base/place_and_route.cpp
@@ -88,6 +88,11 @@ int binary_search_place_and_route(const t_placer_opts& placer_opts_ref,
         graph_type = GRAPH_GLOBAL;
     } else {
         graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR);
+        /* Branch on tileable routing */
+        if ( (UNI_DIRECTIONAL == det_routing_arch->directionality)
+          && (true == det_routing_arch->tileable) ) {
+            graph_type = GRAPH_UNIDIR_TILEABLE;
+        }
     }
 
     best_routing = alloc_saved_routing();
diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp
index 53ec0e732..16a6cc708 100644
--- a/vpr/src/base/vpr_api.cpp
+++ b/vpr/src/base/vpr_api.cpp
@@ -831,7 +831,7 @@ void vpr_create_rr_graph(t_vpr_setup& vpr_setup, const t_arch& arch, int chan_wi
         graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR);
         /* Branch on tileable routing */
         if ( (UNI_DIRECTIONAL == det_routing_arch->directionality)
-          && (true == arch.tileable) ) {
+          && (true == det_routing_arch->tileable) ) {
             graph_type = GRAPH_UNIDIR_TILEABLE;
         }
     }
diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h
index 009887d71..8d03979fd 100644
--- a/vpr/src/base/vpr_types.h
+++ b/vpr/src/base/vpr_types.h
@@ -1009,6 +1009,9 @@ struct t_det_routing_arch {
      */
     int subFs;
     enum e_switch_block_type switch_block_subtype;
+    
+    /* Xifan Tang: tileable routing */
+    bool tileable;
 
     short global_route_switch;
     short delayless_switch;
diff --git a/vpr/src/route/route_common.cpp b/vpr/src/route/route_common.cpp
index 30fd9811a..5ef55df61 100644
--- a/vpr/src/route/route_common.cpp
+++ b/vpr/src/route/route_common.cpp
@@ -269,6 +269,11 @@ bool try_route(int width_fac,
         graph_type = GRAPH_GLOBAL;
     } else {
         graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR);
+        /* Branch on tileable routing */
+        if ( (UNI_DIRECTIONAL == det_routing_arch->directionality)
+          && (true == det_routing_arch->tileable) ) {
+            graph_type = GRAPH_UNIDIR_TILEABLE;
+        }
     }
 
     /* Set the channel widths */
diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp
index 446518faf..6ec00466b 100644
--- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp
+++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp
@@ -59,6 +59,20 @@ e_side determine_io_grid_pin_side(const vtr::Point<size_t>& device_size,
   }
 }
 
+/* Deteremine the side of a pin of a grid */
+std::vector<e_side> find_grid_pin_sides(const t_grid_tile& grid, 
+                                        const size_t& pin_id) {
+  std::vector<e_side> pin_sides;
+
+  for (const e_side& side : {TOP, RIGHT, BOTTOM, LEFT} ) {
+    if (true == grid.type->pinloc[grid.width_offset][grid.height_offset][size_t(side)][pin_id]) {
+      pin_sides.push_back(side);
+    }
+  }
+
+  return pin_sides;
+}
+
 /************************************************************************
  * Get a list of pin_index for a grid (either OPIN or IPIN)
  * For IO_TYPE, only one side will be used, we consider one side of pins 
diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h
index b63afa59d..8a903f97a 100644
--- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h
+++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h
@@ -20,6 +20,9 @@ size_t find_unidir_routing_channel_width(const size_t& chan_width);
 int get_grid_pin_class_index(const t_grid_tile& cur_grid,
                              const int pin_index);
 
+std::vector<e_side> find_grid_pin_sides(const t_grid_tile& grid, 
+                                        const size_t& pin_id);
+
 e_side determine_io_grid_pin_side(const vtr::Point<size_t>& device_size, 
                                   const vtr::Point<size_t>& grid_coordinate);
 
diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp
index 009da112a..200711e35 100644
--- a/vpr/src/tileable_rr_graph/rr_gsb.cpp
+++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp
@@ -822,6 +822,14 @@ void RRGSB::sort_chan_node_in_edges(const RRGraph& rr_graph,
     get_node_side_and_index(rr_graph, src_node, IN_PORT, side, index);
 
     /* Must have valid side and index */
+    if (NUM_SIDES == side) {
+      VTR_LOG("GSB[%lu][%lu]:\n", get_x(), get_y());
+      VTR_LOG("SRC node:\n");
+      rr_graph.print_node(src_node);
+      VTR_LOG("Channel node:\n");
+      rr_graph.print_node(chan_node);
+    }
+
     VTR_ASSERT(NUM_SIDES != side);
     VTR_ASSERT(OPEN != index);
 
diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp
index b37265dfb..ad4944bb4 100755
--- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp
+++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp
@@ -1391,12 +1391,32 @@ void build_direct_connections_for_one_gsb(RRGraph& rr_graph,
         int from_grid_height_ofs = from_grid.height_offset;
         int to_grid_width_ofs = grids[to_grid_coordinate.x()][to_grid_coordinate.y()].width_offset;
         int to_grid_height_ofs = grids[to_grid_coordinate.x()][to_grid_coordinate.y()].height_offset;
+ 
+        /* Find the side of grid pins, the pin location should be unique!
+         * Pin location is required by searching a node in rr_graph 
+         */
+        std::vector<e_side> opin_grid_side = find_grid_pin_sides(from_grid, opin); 
+        VTR_ASSERT(1 == opin_grid_side.size());
+
+        std::vector<e_side> ipin_grid_side = find_grid_pin_sides(grids[to_grid_coordinate.x()][to_grid_coordinate.y()], ipin); 
+        VTR_ASSERT(1 == ipin_grid_side.size());
+
         const RRNodeId& opin_node_id = rr_graph.find_node(from_grid_coordinate.x() - from_grid_width_ofs, 
                                                           from_grid_coordinate.y() - from_grid_height_ofs, 
-                                                          OPIN, opin);
+                                                          OPIN, opin, opin_grid_side[0]);
         const RRNodeId& ipin_node_id = rr_graph.find_node(to_grid_coordinate.x() - to_grid_width_ofs, 
                                                           to_grid_coordinate.y() - to_grid_height_ofs, 
-                                                          IPIN, ipin);
+                                                          IPIN, ipin, ipin_grid_side[0]);
+        /*
+        VTR_LOG("Direct connection: from grid[%lu][%lu].pin[%lu] at side %s to grid[%lu][%lu].pin[%lu] at side %s\n",
+                from_grid_coordinate.x() - from_grid_width_ofs,
+                from_grid_coordinate.y() - from_grid_height_ofs,
+                opin, SIDE_STRING[opin_grid_side[0]],
+                to_grid_coordinate.x() - to_grid_width_ofs,
+                to_grid_coordinate.y() - to_grid_height_ofs,
+                ipin, SIDE_STRING[ipin_grid_side[0]]);
+         */
+     
         /* add edges to the opin_node */
         rr_graph.create_edge(opin_node_id, ipin_node_id,
                              delayless_switch);

From 2c0c5a061bf4f59a407133e6da4b1339d4b29d70 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 20 Mar 2020 16:53:43 -0600
Subject: [PATCH 317/645] spot a bug in assigning rr_switch in tileable routing

---
 openfpga/src/mux_lib/mux_library_builder.cpp | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/openfpga/src/mux_lib/mux_library_builder.cpp b/openfpga/src/mux_lib/mux_library_builder.cpp
index 953dbb308..3657972ff 100644
--- a/openfpga/src/mux_lib/mux_library_builder.cpp
+++ b/openfpga/src/mux_lib/mux_library_builder.cpp
@@ -53,6 +53,13 @@ void build_routing_arch_mux_library(const DeviceContext& vpr_device_ctx,
       VTR_ASSERT(1 == driver_switches.size());
       const CircuitModelId& rr_switch_circuit_model = vpr_device_annotation.rr_switch_circuit_model(driver_switches[0]);
       /* we should select a circuit model for the routing resource switch */
+      if (CircuitModelId::INVALID() == rr_switch_circuit_model) {
+        VTR_LOG_ERROR("Unable to find the circuit mode for rr_switch '%s'!\n",
+                      vpr_device_ctx.rr_graph.get_switch(driver_switches[0]).name);
+        vpr_device_ctx.rr_graph.print_node(node);
+        exit(1);
+      }
+     
       VTR_ASSERT(CircuitModelId::INVALID() != rr_switch_circuit_model);
       /* Add the mux to mux_library */
       mux_lib.add_mux(circuit_lib, rr_switch_circuit_model, vpr_device_ctx.rr_graph.node_in_edges(node).size()); 

From 060c1a41d9f5976594e05531d083dd2d4de217b4 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 20 Mar 2020 17:23:19 -0600
Subject: [PATCH 318/645] critical bug fixed for tileable routing: delayless
 and wire2ipin switch was reverted

---
 vpr/src/route/rr_graph.cpp                             |  2 +-
 .../tileable_rr_graph_node_builder.cpp                 | 10 +++++-----
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp
index f80c450c7..ebd45d7b0 100644
--- a/vpr/src/route/rr_graph.cpp
+++ b/vpr/src/route/rr_graph.cpp
@@ -359,8 +359,8 @@ void create_rr_graph(const t_graph_type graph_type,
                                                     det_routing_arch->switch_block_subtype,
                                                     det_routing_arch->subFs,
                                                     segment_inf,
-                                                    det_routing_arch->wire_to_arch_ipin_switch,
                                                     det_routing_arch->delayless_switch,
+                                                    det_routing_arch->wire_to_arch_ipin_switch,
                                                     det_routing_arch->R_minW_nmos,
                                                     det_routing_arch->R_minW_pmos,
                                                     base_cost_type,
diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp
index 57f98b584..d8c1fb23b 100644
--- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp
+++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp
@@ -615,11 +615,11 @@ void load_grid_nodes_basic_info(RRGraph& rr_graph,
 
       /* Configure opin rr_nodes for this grid */
       load_one_grid_opin_nodes_basic_info(rr_graph,
-                                            rr_node_driver_switches, 
-                                            grid_coordinate, 
-                                            grids[ix][iy], 
-                                            io_side, 
-                                            delayless_switch);
+                                          rr_node_driver_switches, 
+                                          grid_coordinate, 
+                                          grids[ix][iy], 
+                                          io_side, 
+                                          delayless_switch);
 
       /* Configure ipin rr_nodes for this grid */
       load_one_grid_ipin_nodes_basic_info(rr_graph,

From 3c37b33f17e141940201ee272e4d2a5fd29e680b Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 20 Mar 2020 17:45:50 -0600
Subject: [PATCH 319/645] critical bug fixed in edge sorting for rr_gsb

---
 openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml | 2 +-
 vpr/src/tileable_rr_graph/rr_gsb.cpp                    | 5 +++--
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
index e390112e7..b1a588eb1 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
@@ -159,7 +159,7 @@
   </tiles>
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
-  <layout tileable="true">
+  <layout tileable="false">
     <!--auto_layout aspect_ratio="1.0"-->
     <fixed_layout name="2x2" width="3" height="4">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp
index 200711e35..2d5c08e8c 100644
--- a/vpr/src/tileable_rr_graph/rr_gsb.cpp
+++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp
@@ -874,8 +874,9 @@ void RRGSB::sort_chan_node_in_edges(const RRGraph& rr_graph) {
     SideManager side_manager(side);
     chan_node_in_edges_[side].resize(chan_node_[side].get_chan_width());
     for (size_t track_id = 0; track_id < chan_node_[side].get_chan_width(); ++track_id) {
-      /* Only sort the output nodes */
-      if (OUT_PORT == chan_node_direction_[side][track_id]) { 
+      /* Only sort the output nodes and bypass passing wires */
+      if ( (OUT_PORT == chan_node_direction_[side][track_id])
+        && (false == is_sb_node_passing_wire(rr_graph, side_manager.get_side(), track_id)) ) {  
         sort_chan_node_in_edges(rr_graph, side_manager.get_side(), track_id); 
       }
     }

From 05ec86430aa86b0cf09c1aba8a1946f9c1e9ed7d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 20 Mar 2020 17:56:03 -0600
Subject: [PATCH 320/645] temp fix for direct connections. Should notify VPR
 team about this issue: delayless switch is used in direct connection but it
 is considered as configurable....which is actually NOT!

---
 openfpga/src/fabric/build_routing_modules.cpp | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/openfpga/src/fabric/build_routing_modules.cpp b/openfpga/src/fabric/build_routing_modules.cpp
index da216ec75..b00cc5dc5 100644
--- a/openfpga/src/fabric/build_routing_modules.cpp
+++ b/openfpga/src/fabric/build_routing_modules.cpp
@@ -471,6 +471,18 @@ void build_connection_block_module_short_interc(ModuleManager& module_manager,
   VTR_ASSERT_SAFE(1 == driver_rr_nodes.size());
   const RRNodeId& driver_rr_node = driver_rr_nodes[0]; 
 
+  /* Xifan Tang: VPR considers delayless switch to be configurable
+   * As a result, the direct connection is considered to be configurable...
+   * Here, I simply kick out OPINs in CB connection because they should be built
+   * in the top mopdule.
+   * 
+   * Note: this MUST BE reconsidered if we do have OPIN connected to IPINs 
+   * through a programmable multiplexer!!!
+   */
+  if (OPIN == rr_graph.node_type(driver_rr_node)) {
+    return;
+  }
+
   VTR_ASSERT((CHANX == rr_graph.node_type(driver_rr_node)) || (CHANY == rr_graph.node_type(driver_rr_node)));
 
   /* Create port description for the routing track middle output */

From 682b667a3c6a394618b50af6dc1d43d8c75819ba Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 20 Mar 2020 21:44:01 -0600
Subject: [PATCH 321/645] minor bug fix for direct connection in FPGA-SDC

---
 .../src/fpga_sdc/pnr_sdc_routing_writer.cpp   | 19 +++++++++++++++++--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp
index dcb5b6849..43572244c 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp
+++ b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp
@@ -230,7 +230,22 @@ void print_pnr_sdc_constrain_cb_mux_timing(std::fstream& fp,
    * These connections should be handled by other functions in the compact_netlist.c 
    * So we just return here for OPINs 
    */
-  if (0 == get_rr_graph_configurable_driver_nodes(rr_graph, output_rr_node).size()) {
+  std::vector<RRNodeId> input_rr_nodes = get_rr_graph_configurable_driver_nodes(rr_graph, output_rr_node);
+
+  if (0 == input_rr_nodes.size()) {
+    return;
+  }
+
+  /* Xifan Tang: VPR considers delayless switch to be configurable
+   * As a result, the direct connection is considered to be configurable...
+   * Here, I simply kick out OPINs in CB connection because they should be built
+   * in the top mopdule.
+   * 
+   * Note: this MUST BE reconsidered if we do have OPIN connected to IPINs 
+   * through a programmable multiplexer!!!
+   */
+  if ( (1 == input_rr_nodes.size())
+    && (OPIN == rr_graph.node_type(input_rr_nodes[0])) ) {
     return;
   }
 
@@ -247,7 +262,7 @@ void print_pnr_sdc_constrain_cb_mux_timing(std::fstream& fp,
                                                                                           rr_graph, 
                                                                                           rr_gsb, 
                                                                                           cb_type,
-                                                                                          get_rr_graph_configurable_driver_nodes(rr_graph, output_rr_node));
+                                                                                          input_rr_nodes);
 
   /* Find timing constraints for each path (edge) */
   std::map<ModulePortId, float> switch_delays;

From 2ff2d65e583158d333452b04e5d078e1593a5427 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 20 Mar 2020 22:12:23 -0600
Subject: [PATCH 322/645] start debugging tileable routing using larger array
 size. Bug spotted in finding chan nodes

---
 openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml | 4 ++--
 vpr/src/tileable_rr_graph/rr_gsb.cpp                    | 4 ++++
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
index b1a588eb1..c3598bd2b 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
@@ -159,9 +159,9 @@
   </tiles>
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
-  <layout tileable="false">
+  <layout tileable="true">
     <!--auto_layout aspect_ratio="1.0"-->
-    <fixed_layout name="2x2" width="3" height="4">
+    <fixed_layout name="2x2" width="4" height="4">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
       <corners type="EMPTY" priority="101"/>
diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp
index 2d5c08e8c..d3ae2bcc5 100644
--- a/vpr/src/tileable_rr_graph/rr_gsb.cpp
+++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp
@@ -444,6 +444,10 @@ bool RRGSB::is_sb_node_passing_wire(const RRGraph& rr_graph,
   /* Reach here it means that this will be a passing wire, 
    * we should be able to find the node on the opposite side of the GSB!
    */
+  if (true != is_sb_node_exist_opposite_side(rr_graph, track_node, node_side)) {
+    VTR_LOG("GSB[%lu][%lu] track node:\n", get_x(), get_y());
+    rr_graph.print_node(track_node);
+  }
   VTR_ASSERT (true == is_sb_node_exist_opposite_side(rr_graph, track_node, node_side));
 
   return true;

From 28123b80520d77d3a5c83624ca8cb1eef7984f54 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 21 Mar 2020 11:38:39 -0600
Subject: [PATCH 323/645] remove the direct connected IPIN/OPIN from RR GSB
 builder

---
 openfpga/src/annotation/annotate_rr_graph.cpp | 24 +++++++++
 .../src/tile_direct/build_tile_direct.cpp     |  3 ++
 .../k6_frac_N10_adder_chain_40nm.xml          |  2 +-
 .../openfpga_rr_graph_utils.cpp               | 52 +++++++++++++++++++
 .../openfpga_rr_graph_utils.h                 |  6 +++
 vpr/src/tileable_rr_graph/rr_gsb.cpp          |  3 +-
 6 files changed, 88 insertions(+), 2 deletions(-)

diff --git a/openfpga/src/annotation/annotate_rr_graph.cpp b/openfpga/src/annotation/annotate_rr_graph.cpp
index 4af681c71..eba72933f 100644
--- a/openfpga/src/annotation/annotate_rr_graph.cpp
+++ b/openfpga/src/annotation/annotate_rr_graph.cpp
@@ -12,6 +12,7 @@
 
 /* Headers from vpr library */
 #include "rr_graph_obj_util.h"
+#include "openfpga_rr_graph_utils.h"
 
 #include "annotate_rr_graph.h"
 
@@ -264,9 +265,18 @@ RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx,
                              vpr_device_ctx.rr_graph.node_configurable_out_edges(inode).end())) {
         continue;
       }
+
+      /* Do not consider OPINs that directly drive an IPIN
+       * they are supposed to be handled by direct connection
+       */
+      if (true == is_opin_direct_connected_ipin(vpr_device_ctx.rr_graph, inode)) { 
+        continue;
+      }
+
       /* Grid[x+1][y+1] Bottom side outputs pins */
       rr_gsb.add_opin_node(inode, side_manager.get_side());
     }
+
     for (const RRNodeId& inode : temp_opin_rr_nodes[1]) {
       /* Skip those has no configurable outgoing, they should NOT appear in the GSB connection
        * This is for those grid output pins used by direct connections
@@ -276,6 +286,13 @@ RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx,
         continue;
       }
 
+      /* Do not consider OPINs that directly drive an IPIN
+       * they are supposed to be handled by direct connection
+       */
+      if (true == is_opin_direct_connected_ipin(vpr_device_ctx.rr_graph, inode)) { 
+        continue;
+      }
+
       /* Grid[x+1][y] TOP side outputs pins */
       rr_gsb.add_opin_node(inode, side_manager.get_side());
     }
@@ -356,6 +373,13 @@ RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx,
                                                   ix, iy, IPIN, ipin_rr_node_grid_side);
     /* Fill the ipin nodes of RRGSB */ 
     for (const RRNodeId& inode : temp_ipin_rr_nodes) {
+      /* Do not consider IPINs that are directly connected by an OPIN
+       * they are supposed to be handled by direct connection
+       */
+      if (true == is_ipin_direct_connected_opin(vpr_device_ctx.rr_graph, inode)) { 
+        continue;
+      }
+ 
       rr_gsb.add_ipin_node(inode, side_manager.get_side());
     }
     /* Clear the temp data */
diff --git a/openfpga/src/tile_direct/build_tile_direct.cpp b/openfpga/src/tile_direct/build_tile_direct.cpp
index ba426ce17..2166b7a16 100644
--- a/openfpga/src/tile_direct/build_tile_direct.cpp
+++ b/openfpga/src/tile_direct/build_tile_direct.cpp
@@ -674,6 +674,9 @@ TileDirect build_device_tile_direct(const DeviceContext& device_ctx,
                                        arch_direct_id);
   } 
 
+  VTR_LOG("Built %lu tile-to-tile direct connections\n",
+          std::distance(tile_direct.directs().begin(), tile_direct.directs().end()));
+
   return tile_direct;
 }
 
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
index c3598bd2b..e66dc8b9c 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
@@ -159,7 +159,7 @@
   </tiles>
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
-  <layout tileable="true">
+  <layout tileable="false">
     <!--auto_layout aspect_ratio="1.0"-->
     <fixed_layout name="2x2" width="4" height="4">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
diff --git a/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp
index ba789b4da..a3b3da7fe 100644
--- a/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp
+++ b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp
@@ -128,4 +128,56 @@ std::vector<RRNodeId> get_rr_graph_non_configurable_driver_nodes(const RRGraph&
   return driver_nodes;
 }
 
+/************************************************************************
+ * Check if an OPIN of a rr_graph is directly driving an IPIN
+ * To meet this requirement, the OPIN must:
+ *   - Have only 1 fan-out
+ *   - The only fan-out is an IPIN
+ ***********************************************************************/
+bool is_opin_direct_connected_ipin(const RRGraph& rr_graph,
+                                   const RRNodeId& node) {
+  /* We only accept OPIN */
+  VTR_ASSERT(OPIN == rr_graph.node_type(node));
+
+  if (1 != rr_graph.node_out_edges(node).size()) {
+    return false;
+  }
+
+  VTR_ASSERT(1 == rr_graph.node_out_edges(node).size());
+  for (const RREdgeId& edge: rr_graph.node_out_edges(node)) {
+    const RRNodeId& sink_node = rr_graph.edge_sink_node(edge);
+    if (IPIN != rr_graph.node_type(sink_node)) {
+      return false;
+    }
+  }
+  
+  return true;
+}
+
+/************************************************************************
+ * Check if an IPIN of a rr_graph is directly connected to an OPIN
+ * To meet this requirement, the IPIN must:
+ *   - Have only 1 fan-in
+ *   - The only fan-in is an OPIN
+ ***********************************************************************/
+bool is_ipin_direct_connected_opin(const RRGraph& rr_graph,
+                                   const RRNodeId& node) {
+  /* We only accept IPIN */
+  VTR_ASSERT(IPIN == rr_graph.node_type(node));
+
+  if (1 != rr_graph.node_in_edges(node).size()) {
+    return false;
+  }
+
+  VTR_ASSERT(1 == rr_graph.node_in_edges(node).size());
+  for (const RREdgeId& edge: rr_graph.node_in_edges(node)) {
+    const RRNodeId& src_node = rr_graph.edge_src_node(edge);
+    if (OPIN != rr_graph.node_type(src_node)) {
+      return false;
+    }
+  }
+  
+  return true;
+}
+
 } /* end namespace openfpga */
diff --git a/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.h b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.h
index 0466892f8..ebf741f8d 100644
--- a/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.h
+++ b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.h
@@ -35,6 +35,12 @@ std::vector<RRNodeId> get_rr_graph_configurable_driver_nodes(const RRGraph& rr_g
 std::vector<RRNodeId> get_rr_graph_non_configurable_driver_nodes(const RRGraph& rr_graph,
                                                                  const RRNodeId& node);
 
+bool is_opin_direct_connected_ipin(const RRGraph& rr_graph,
+                                   const RRNodeId& node);
+
+bool is_ipin_direct_connected_opin(const RRGraph& rr_graph,
+                                   const RRNodeId& node);
+
 } /* end namespace openfpga */
 
 #endif
diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp
index d3ae2bcc5..b489182b2 100644
--- a/vpr/src/tileable_rr_graph/rr_gsb.cpp
+++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp
@@ -445,7 +445,8 @@ bool RRGSB::is_sb_node_passing_wire(const RRGraph& rr_graph,
    * we should be able to find the node on the opposite side of the GSB!
    */
   if (true != is_sb_node_exist_opposite_side(rr_graph, track_node, node_side)) {
-    VTR_LOG("GSB[%lu][%lu] track node:\n", get_x(), get_y());
+    VTR_LOG("GSB[%lu][%lu] track node[%lu] at %s:\n",
+            get_x(), get_y(), track_id, SIDE_STRING[node_side]);
     rr_graph.print_node(track_node);
   }
   VTR_ASSERT (true == is_sb_node_exist_opposite_side(rr_graph, track_node, node_side));

From 8f35f191eb57e0cdd4a88e9797d17c2b844254c3 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 21 Mar 2020 11:42:00 -0600
Subject: [PATCH 324/645] use the formalized function in FPGA-SDC to identify
 direct connection

---
 openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp
index 43572244c..dd0914d14 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp
+++ b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp
@@ -244,8 +244,7 @@ void print_pnr_sdc_constrain_cb_mux_timing(std::fstream& fp,
    * Note: this MUST BE reconsidered if we do have OPIN connected to IPINs 
    * through a programmable multiplexer!!!
    */
-  if ( (1 == input_rr_nodes.size())
-    && (OPIN == rr_graph.node_type(input_rr_nodes[0])) ) {
+  if (true == is_ipin_direct_connected_opin(rr_graph, output_rr_node)) {
     return;
   }
 

From c0e8d98c6f28a0e3cb37689c1b74ca4f09023ce8 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 21 Mar 2020 12:43:56 -0600
Subject: [PATCH 325/645] bug fixed in tile direct builder

---
 openfpga/src/base/openfpga_link_arch.cpp      |   3 +-
 .../src/fabric/build_top_module_directs.cpp   |   3 +
 .../src/tile_direct/build_tile_direct.cpp     | 356 ++++++++++++------
 openfpga/src/tile_direct/build_tile_direct.h  |   3 +-
 4 files changed, 241 insertions(+), 124 deletions(-)

diff --git a/openfpga/src/base/openfpga_link_arch.cpp b/openfpga/src/base/openfpga_link_arch.cpp
index 5c0d6c582..34c98ee8d 100644
--- a/openfpga/src/base/openfpga_link_arch.cpp
+++ b/openfpga/src/base/openfpga_link_arch.cpp
@@ -123,7 +123,8 @@ void link_arch(OpenfpgaContext& openfpga_ctx,
 
   /* Build tile direct annotation */
   openfpga_ctx.mutable_tile_direct() = build_device_tile_direct(g_vpr_ctx.device(),
-                                                                openfpga_ctx.arch().arch_direct);
+                                                                openfpga_ctx.arch().arch_direct,
+                                                                cmd_context.option_enable(cmd, opt_verbose));
 
   /* Annotate placement results */
   annotate_mapped_blocks(g_vpr_ctx.device(), 
diff --git a/openfpga/src/fabric/build_top_module_directs.cpp b/openfpga/src/fabric/build_top_module_directs.cpp
index 63d4a1882..314b5f2e8 100644
--- a/openfpga/src/fabric/build_top_module_directs.cpp
+++ b/openfpga/src/fabric/build_top_module_directs.cpp
@@ -95,6 +95,9 @@ void add_module_nets_tile_direct_connection(ModuleManager& module_manager,
   size_t src_pin_height = grids[src_clb_coord.x()][src_clb_coord.y()].type->pin_height_offset[src_tile_pin]; 
   std::string src_port_name = generate_grid_port_name(src_clb_coord, src_pin_width, src_pin_height, src_pin_grid_side, src_tile_pin, false);
   ModulePortId src_port_id = module_manager.find_module_port(src_grid_module, src_port_name); 
+  if (true != module_manager.valid_module_port_id(src_grid_module, src_port_id)) {
+    VTR_LOG("Fail to find port '%s'\n", src_port_name.c_str());
+  }
   VTR_ASSERT(true == module_manager.valid_module_port_id(src_grid_module, src_port_id));
   VTR_ASSERT(1 == module_manager.module_port(src_grid_module, src_port_id).get_width());
 
diff --git a/openfpga/src/tile_direct/build_tile_direct.cpp b/openfpga/src/tile_direct/build_tile_direct.cpp
index 2166b7a16..5e33bc502 100644
--- a/openfpga/src/tile_direct/build_tile_direct.cpp
+++ b/openfpga/src/tile_direct/build_tile_direct.cpp
@@ -39,6 +39,24 @@ std::string parse_direct_tile_name(const std::string& direct_tile_inf) {
   return tokens[0];
 }
 
+/***************************************************************************************
+ * Parse the pin name and port MSB/LSB from the direct definition  
+ * The definition string should be in the following format:
+ *   <tile_type_name>.<pin_name>[<pin_lsb>:<pin_msb>]  
+ ***************************************************************************************/
+static 
+std::string parse_direct_port(const std::string& direct_tile_inf) {
+  StringToken tokenizer(direct_tile_inf);
+  std::vector<std::string> tokens = tokenizer.split('.');
+  /* We should have only 2 elements and the first is tile name */
+  if (2 != tokens.size()) {
+    VTR_LOG_ERROR("Invalid definition on direct tile '%s'!\n\tExpect <tile_type_name>.<pin_name>[<pin_lsb>:<pin_msb>].\n",
+                  direct_tile_inf.c_str());
+  }
+
+  return tokens[1];
+}
+
 /***************************************************************************************
  * Check if a pin is located on a given side of physical tile
  * If the given side is NUM_SIDES, we will search all the sides 
@@ -364,15 +382,16 @@ static
 void build_inner_column_row_tile_direct(TileDirect& tile_direct,
                                         const t_direct_inf& vpr_direct,
                                         const DeviceContext& device_ctx,
-                                        const ArchDirectId& arch_direct_id) {
+                                        const ArchDirectId& arch_direct_id,
+                                        const bool& verbose) {
   /* Get the source tile and pin information */
   std::string from_tile_name = parse_direct_tile_name(std::string(vpr_direct.from_pin));
-  PortParser from_tile_port_parser(std::string(vpr_direct.from_pin));
+  PortParser from_tile_port_parser(parse_direct_port(std::string(vpr_direct.from_pin)));
   const BasicPort& from_tile_port = from_tile_port_parser.port();
 
   /* Get the sink tile and pin information */
   std::string to_tile_name = parse_direct_tile_name(std::string(vpr_direct.to_pin));
-  PortParser to_tile_port_parser(std::string(vpr_direct.to_pin));
+  PortParser to_tile_port_parser(parse_direct_port(std::string(vpr_direct.to_pin)));
   const BasicPort& to_tile_port = to_tile_port_parser.port();
 
   /* Walk through the device fabric and find the grid that fit the source */
@@ -387,51 +406,80 @@ void build_inner_column_row_tile_direct(TileDirect& tile_direct,
       if (from_tile_name != std::string(device_ctx.grid[x][y].type->name)) {
         continue;
       }
+
+      /* Search all the sides, the from pin may locate any side!
+       * Note: the vpr_direct.from_side is NUM_SIDES, which is unintialized
+       * This should be reported to VPR!!!
+       */
+      for (const e_side& from_side : {TOP, RIGHT, BOTTOM, LEFT}) {
       
-      /* Try to find the pin in this tile */
-      std::vector<size_t> from_pins = find_physical_tile_pin_id(device_ctx.grid[x][y].type,
-                                                                device_ctx.grid[x][y].width_offset,
-                                                                device_ctx.grid[x][y].height_offset,
-                                                                from_tile_port,
-                                                                vpr_direct.from_side);
-      /* If nothing found, we can continue */
-      if (0 == from_pins.size()) {
-        continue;
-      }
-      
-      /* We should try to the sink grid for inner-column/row direct connections */
-      vtr::Point<size_t> from_grid_coord(x, y);
-      vtr::Point<size_t> to_grid_coord(x + vpr_direct.x_offset, y + vpr_direct.y_offset);
-      if (false == is_grid_coordinate_exist_in_device(device_ctx.grid, to_grid_coord)) {
-        continue;
-      }
+        /* Try to find the pin in this tile */
+        std::vector<size_t> from_pins = find_physical_tile_pin_id(device_ctx.grid[x][y].type,
+                                                                  device_ctx.grid[x][y].width_offset,
+                                                                  device_ctx.grid[x][y].height_offset,
+                                                                  from_tile_port,
+                                                                  from_side);
+        /* If nothing found, we can continue */
+        if (0 == from_pins.size()) {
+          continue;
+        }
+        
+        /* We should try to the sink grid for inner-column/row direct connections */
+        vtr::Point<size_t> from_grid_coord(x, y);
+        vtr::Point<size_t> to_grid_coord(x + vpr_direct.x_offset, y + vpr_direct.y_offset);
+        if (false == is_grid_coordinate_exist_in_device(device_ctx.grid, to_grid_coord)) {
+          continue;
+        }
 
-      /* Bypass the grid that does not fit the from_tile name */
-      if (to_tile_name != std::string(device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].type->name)) {
-        continue;
-      }
-      /* Try to find the pin in this tile */
-      std::vector<size_t> to_pins = find_physical_tile_pin_id(device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].type,
-                                                              device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].width_offset,
-                                                              device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].height_offset,
-                                                              to_tile_port,
-                                                              vpr_direct.to_side);
-      /* If nothing found, we can continue */
-      if (0 == to_pins.size()) {
-        continue;
-      }
+        /* Bypass the grid that does not fit the from_tile name */
+        if (to_tile_name != std::string(device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].type->name)) {
+          continue;
+        }
 
-      /* If from port and to port do not match in sizes, error out */
-      if (from_pins.size() != to_pins.size()) {
-        report_direct_from_port_and_to_port_mismatch(vpr_direct, from_tile_port, to_tile_port);
-        exit(1);
-      }
+        /* Search all the sides, the to pin may locate any side!
+         * Note: the vpr_direct.to_side is NUM_SIDES, which is unintialized
+         * This should be reported to VPR!!!
+         */
+        for (const e_side& to_side : {TOP, RIGHT, BOTTOM, LEFT}) {
 
-      /* Now add the tile direct */
-      for (size_t ipin = 0; ipin < from_pins.size(); ++ipin) {
-        TileDirectId tile_direct_id = tile_direct.add_direct(from_grid_coord, vpr_direct.from_side, from_pins[ipin],
-                                                             to_grid_coord, vpr_direct.to_side, to_pins[ipin]);
-        tile_direct.set_arch_direct_id(tile_direct_id, arch_direct_id);
+          /* Try to find the pin in this tile */
+          std::vector<size_t> to_pins = find_physical_tile_pin_id(device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].type,
+                                                                  device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].width_offset,
+                                                                  device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].height_offset,
+                                                                  to_tile_port,
+                                                                  to_side);
+          /* If nothing found, we can continue */
+          if (0 == to_pins.size()) {
+            continue;
+          }
+
+          /* If from port and to port do not match in sizes, error out */
+          if (from_pins.size() != to_pins.size()) {
+            report_direct_from_port_and_to_port_mismatch(vpr_direct, from_tile_port, to_tile_port);
+            exit(1);
+          }
+
+          /* Now add the tile direct */
+          for (size_t ipin = 0; ipin < from_pins.size(); ++ipin) {
+            VTR_LOGV(verbose,
+                     "Built a inner-column/row tile-to-tile direct from %s[%lu][%lu].%s[%lu] at side '%s' to %s[%lu][%lu].%s[%lu] at side '%s'\n",
+                     from_tile_name.c_str(), x, y,
+                     from_tile_port.get_name().c_str(), from_pins[ipin],
+                     SIDE_STRING[from_side],
+                     to_tile_name.c_str(),
+                     to_grid_coord.x(), to_grid_coord.y(),
+                     to_tile_port.get_name().c_str(), to_pins[ipin],
+                     SIDE_STRING[to_side]
+                     );
+            TileDirectId tile_direct_id = tile_direct.add_direct(from_grid_coord,
+                                                                 from_side,
+                                                                 from_pins[ipin],
+                                                                 to_grid_coord,
+                                                                 to_side,
+                                                                 to_pins[ipin]);
+            tile_direct.set_arch_direct_id(tile_direct_id, arch_direct_id);
+          }
+        }
       }
     }
   }
@@ -475,16 +523,17 @@ void build_inter_column_row_tile_direct(TileDirect& tile_direct,
                                         const t_direct_inf& vpr_direct,
                                         const DeviceContext& device_ctx,
                                         const ArchDirect& arch_direct,
-                                        const ArchDirectId& arch_direct_id) {
+                                        const ArchDirectId& arch_direct_id,
+                                        const bool& verbose) {
 
   /* Get the source tile and pin information */
   std::string from_tile_name = parse_direct_tile_name(std::string(vpr_direct.from_pin));
-  PortParser from_tile_port_parser(std::string(vpr_direct.from_pin));
+  PortParser from_tile_port_parser(parse_direct_port(std::string(vpr_direct.from_pin)));
   const BasicPort& from_tile_port = from_tile_port_parser.port();
 
   /* Get the sink tile and pin information */
   std::string to_tile_name = parse_direct_tile_name(std::string(vpr_direct.to_pin));
-  PortParser to_tile_port_parser(std::string(vpr_direct.to_pin));
+  PortParser to_tile_port_parser(parse_direct_port(std::string(vpr_direct.to_pin)));
   const BasicPort& to_tile_port = to_tile_port_parser.port();
 
   /* Go through the direct connection list, see if we need intra-column/row connection here */
@@ -525,47 +574,77 @@ void build_inter_column_row_tile_direct(TileDirect& tile_direct,
       if (false == is_grid_coordinate_exist_in_device(device_ctx.grid, from_grid_coord)) {
         continue;
       }
+
+      /* Search all the sides, the from pin may locate any side!
+       * Note: the vpr_direct.from_side is NUM_SIDES, which is unintialized
+       * This should be reported to VPR!!!
+       */
+      for (const e_side& from_side : {TOP, RIGHT, BOTTOM, LEFT}) {
       
-      /* Try to find the pin in this tile */
-      std::vector<size_t> from_pins = find_physical_tile_pin_id(device_ctx.grid[from_grid_coord.x()][from_grid_coord.y()].type,
-                                                               device_ctx.grid[from_grid_coord.x()][from_grid_coord.y()].width_offset,
-                                                               device_ctx.grid[from_grid_coord.x()][from_grid_coord.y()].height_offset,
-                                                               from_tile_port,
-                                                               vpr_direct.from_side);
-      /* If nothing found, we can continue */
-      if (0 == from_pins.size()) {
-        continue;
-      }
+        /* Try to find the pin in this tile */
+        std::vector<size_t> from_pins = find_physical_tile_pin_id(device_ctx.grid[from_grid_coord.x()][from_grid_coord.y()].type,
+                                                                 device_ctx.grid[from_grid_coord.x()][from_grid_coord.y()].width_offset,
+                                                                 device_ctx.grid[from_grid_coord.x()][from_grid_coord.y()].height_offset,
+                                                                 from_tile_port,
+                                                                 from_side);
+        /* If nothing found, we can continue */
+        if (0 == from_pins.size()) {
+          continue;
+        }
 
-      /* For a valid coordinate, we can find the coordinate of the destination clb */
-       vtr::Point<size_t> to_grid_coord = find_inter_direct_destination_coordinate(device_ctx.grid, from_grid_coord, to_tile_name, arch_direct, arch_direct_id);
-       /* If destination clb is valid, we should add something */
-      if (false == is_grid_coordinate_exist_in_device(device_ctx.grid, to_grid_coord)) {
-         continue;
-      }
+        /* For a valid coordinate, we can find the coordinate of the destination clb */
+         vtr::Point<size_t> to_grid_coord = find_inter_direct_destination_coordinate(device_ctx.grid, from_grid_coord, to_tile_name, arch_direct, arch_direct_id);
+         /* If destination clb is valid, we should add something */
+        if (false == is_grid_coordinate_exist_in_device(device_ctx.grid, to_grid_coord)) {
+           continue;
+        }
 
-      /* Try to find the pin in this tile */
-      std::vector<size_t> to_pins = find_physical_tile_pin_id(device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].type,
-                                                              device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].width_offset,
-                                                              device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].height_offset,
-                                                              to_tile_port,
-                                                              vpr_direct.to_side);
-      /* If nothing found, we can continue */
-      if (0 == to_pins.size()) {
-        continue;
-      }
+        /* Search all the sides, the to pin may locate any side!
+         * Note: the vpr_direct.to_side is NUM_SIDES, which is unintialized
+         * This should be reported to VPR!!!
+         */
+        for (const e_side& to_side : {TOP, RIGHT, BOTTOM, LEFT}) {
 
-      /* If from port and to port do not match in sizes, error out */
-      if (from_pins.size() != to_pins.size()) {
-        report_direct_from_port_and_to_port_mismatch(vpr_direct, from_tile_port, to_tile_port);
-        exit(1);
-      }
+          /* Try to find the pin in this tile */
+          std::vector<size_t> to_pins = find_physical_tile_pin_id(device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].type,
+                                                                  device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].width_offset,
+                                                                  device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].height_offset,
+                                                                  to_tile_port,
+                                                                  to_side);
+          /* If nothing found, we can continue */
+          if (0 == to_pins.size()) {
+            continue;
+          }
 
-      /* Now add the tile direct */
-      for (size_t ipin = 0; ipin < from_pins.size(); ++ipin) {
-        TileDirectId tile_direct_id = tile_direct.add_direct(from_grid_coord, vpr_direct.from_side, from_pins[ipin],
-                                                             to_grid_coord, vpr_direct.to_side, to_pins[ipin]);
-        tile_direct.set_arch_direct_id(tile_direct_id, arch_direct_id);
+          /* If from port and to port do not match in sizes, error out */
+          if (from_pins.size() != to_pins.size()) {
+            report_direct_from_port_and_to_port_mismatch(vpr_direct, from_tile_port, to_tile_port);
+            exit(1);
+          }
+
+          /* Now add the tile direct */
+          for (size_t ipin = 0; ipin < from_pins.size(); ++ipin) {
+            VTR_LOGV(verbose,
+                     "Built a inter-column/row tile-to-tile direct from %s[%lu][%lu].%s[%lu] at side '%s' to %s[%lu][%lu].%s[%lu] at side '%s'\n",
+                     from_tile_name.c_str(),
+                     from_grid_coord.x(), from_grid_coord.y(),
+                     from_tile_port.get_name().c_str(), from_pins[ipin],
+                     SIDE_STRING[from_side],
+                     to_tile_name.c_str(),
+                     to_grid_coord.x(), to_grid_coord.y(),
+                     to_tile_port.get_name().c_str(), to_pins[ipin],
+                     SIDE_STRING[to_side]
+                     );
+
+            TileDirectId tile_direct_id = tile_direct.add_direct(from_grid_coord,
+                                                                 from_side,
+                                                                 from_pins[ipin],
+                                                                 to_grid_coord,
+                                                                 to_side,
+                                                                 to_pins[ipin]);
+            tile_direct.set_arch_direct_id(tile_direct_id, arch_direct_id);
+          }
+        }
       }
     }
     return; /* Go to next direct type */
@@ -599,46 +678,76 @@ void build_inter_column_row_tile_direct(TileDirect& tile_direct,
       continue;
     }
 
-    /* Try to find the pin in this tile */
-    std::vector<size_t> from_pins = find_physical_tile_pin_id(device_ctx.grid[from_grid_coord.x()][from_grid_coord.y()].type,
-                                                              device_ctx.grid[from_grid_coord.x()][from_grid_coord.y()].width_offset,
-                                                              device_ctx.grid[from_grid_coord.x()][from_grid_coord.y()].height_offset,
-                                                              from_tile_port,
-                                                              vpr_direct.from_side);
-    /* If nothing found, we can continue */
-    if (0 == from_pins.size()) {
-      continue;
-    }
+    /* Search all the sides, the from pin may locate any side!
+     * Note: the vpr_direct.from_side is NUM_SIDES, which is unintialized
+     * This should be reported to VPR!!!
+     */
+    for (const e_side& from_side : {TOP, RIGHT, BOTTOM, LEFT}) {
+      
+      /* Try to find the pin in this tile */
+      std::vector<size_t> from_pins = find_physical_tile_pin_id(device_ctx.grid[from_grid_coord.x()][from_grid_coord.y()].type,
+                                                                device_ctx.grid[from_grid_coord.x()][from_grid_coord.y()].width_offset,
+                                                                device_ctx.grid[from_grid_coord.x()][from_grid_coord.y()].height_offset,
+                                                                from_tile_port,
+                                                                from_side);
+      /* If nothing found, we can continue */
+      if (0 == from_pins.size()) {
+        continue;
+      }
 
-    /* For a valid coordinate, we can find the coordinate of the destination clb */
-    vtr::Point<size_t> to_grid_coord = find_inter_direct_destination_coordinate(device_ctx.grid, from_grid_coord, to_tile_name, arch_direct, arch_direct_id);
-    /* If destination clb is valid, we should add something */
-    if (false == is_grid_coordinate_exist_in_device(device_ctx.grid, to_grid_coord)) {
-      continue;
-    }
+      /* For a valid coordinate, we can find the coordinate of the destination clb */
+      vtr::Point<size_t> to_grid_coord = find_inter_direct_destination_coordinate(device_ctx.grid, from_grid_coord, to_tile_name, arch_direct, arch_direct_id);
+      /* If destination clb is valid, we should add something */
+      if (false == is_grid_coordinate_exist_in_device(device_ctx.grid, to_grid_coord)) {
+        continue;
+      }
 
-    /* Try to find the pin in this tile */
-    std::vector<size_t> to_pins = find_physical_tile_pin_id(device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].type,
-                                                            device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].width_offset,
-                                                            device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].height_offset,
-                                                            to_tile_port,
-                                                            vpr_direct.to_side);
-    /* If nothing found, we can continue */
-    if (0 == to_pins.size()) {
-      continue;
-    }
+      /* Search all the sides, the to pin may locate any side!
+       * Note: the vpr_direct.to_side is NUM_SIDES, which is unintialized
+       * This should be reported to VPR!!!
+       */
+      for (const e_side& to_side : {TOP, RIGHT, BOTTOM, LEFT}) {
 
-    /* If from port and to port do not match in sizes, error out */
-    if (from_pins.size() != to_pins.size()) {
-      report_direct_from_port_and_to_port_mismatch(vpr_direct, from_tile_port, to_tile_port);
-      exit(1);
-    }
+        /* Try to find the pin in this tile */
+        std::vector<size_t> to_pins = find_physical_tile_pin_id(device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].type,
+                                                                device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].width_offset,
+                                                                device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].height_offset,
+                                                                to_tile_port,
+                                                                to_side);
+        /* If nothing found, we can continue */
+        if (0 == to_pins.size()) {
+          continue;
+        }
 
-    /* Now add the tile direct */
-    for (size_t ipin = 0; ipin < from_pins.size(); ++ipin) {
-      TileDirectId tile_direct_id = tile_direct.add_direct(from_grid_coord, vpr_direct.from_side, from_pins[ipin],
-                                                           to_grid_coord, vpr_direct.to_side, to_pins[ipin]);
-      tile_direct.set_arch_direct_id(tile_direct_id, arch_direct_id);
+        /* If from port and to port do not match in sizes, error out */
+        if (from_pins.size() != to_pins.size()) {
+          report_direct_from_port_and_to_port_mismatch(vpr_direct, from_tile_port, to_tile_port);
+          exit(1);
+        }
+
+        /* Now add the tile direct */
+        for (size_t ipin = 0; ipin < from_pins.size(); ++ipin) {
+          VTR_LOGV(verbose,
+                   "Built a inter-column/row tile-to-tile direct from %s[%lu][%lu].%s[%lu] at side '%s' to %s[%lu][%lu].%s[%lu] at side '%s'\n",
+                   from_tile_name.c_str(),
+                   from_grid_coord.x(), from_grid_coord.y(),
+                   from_tile_port.get_name().c_str(), from_pins[ipin],
+                   SIDE_STRING[from_side],
+                   to_tile_name.c_str(),
+                   to_grid_coord.x(), to_grid_coord.y(),
+                   to_tile_port.get_name().c_str(), to_pins[ipin],
+                   SIDE_STRING[to_side]
+                   );
+
+          TileDirectId tile_direct_id = tile_direct.add_direct(from_grid_coord,
+                                                               from_side,
+                                                               from_pins[ipin],
+                                                               to_grid_coord,
+                                                               to_side,
+                                                               to_pins[ipin]);
+          tile_direct.set_arch_direct_id(tile_direct_id, arch_direct_id);
+        }
+      }
     }
   }
 }
@@ -648,7 +757,8 @@ void build_inter_column_row_tile_direct(TileDirect& tile_direct,
  * between tiles (programmable blocks) 
  ***************************************************************************************/
 TileDirect build_device_tile_direct(const DeviceContext& device_ctx,
-                                    const ArchDirect& arch_direct) {
+                                    const ArchDirect& arch_direct,
+                                    const bool& verbose) {
   vtr::ScopedStartFinishTimer timer("Build the annotation about direct connection between tiles");
 
   TileDirect tile_direct;
@@ -665,13 +775,15 @@ TileDirect build_device_tile_direct(const DeviceContext& device_ctx,
     build_inner_column_row_tile_direct(tile_direct,
                                        device_ctx.arch->Directs[idirect],
                                        device_ctx,
-                                       arch_direct_id);
+                                       arch_direct_id,
+                                       verbose);
     /* Build from OpenFPGA arch definition */ 
     build_inter_column_row_tile_direct(tile_direct,
                                        device_ctx.arch->Directs[idirect],
                                        device_ctx,
                                        arch_direct,
-                                       arch_direct_id);
+                                       arch_direct_id,
+                                       verbose);
   } 
 
   VTR_LOG("Built %lu tile-to-tile direct connections\n",
diff --git a/openfpga/src/tile_direct/build_tile_direct.h b/openfpga/src/tile_direct/build_tile_direct.h
index 78ca2f6b0..ed9e0c3bc 100644
--- a/openfpga/src/tile_direct/build_tile_direct.h
+++ b/openfpga/src/tile_direct/build_tile_direct.h
@@ -17,7 +17,8 @@
 namespace openfpga {
 
 TileDirect build_device_tile_direct(const DeviceContext& device_ctx,
-                                    const ArchDirect& arch_direct);
+                                    const ArchDirect& arch_direct,
+                                    const bool& verbose);
 
 } /* end namespace openfpga */
 

From 63c4669dbb5cd5787667f1f6fc219bededaaf701 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 21 Mar 2020 17:36:08 -0600
Subject: [PATCH 326/645] fixed bug in the fast look-up for tileable rr_graph

---
 .../k6_frac_N10_adder_chain_40nm.xml          |  2 +-
 vpr/src/device/rr_graph_obj.cpp               | 52 +++++++++++++++++--
 vpr/src/device/rr_graph_obj.h                 | 24 ++++++++-
 .../tileable_rr_graph_node_builder.cpp        |  8 +++
 4 files changed, 79 insertions(+), 7 deletions(-)

diff --git a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
index e66dc8b9c..c3598bd2b 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
@@ -159,7 +159,7 @@
   </tiles>
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
-  <layout tileable="false">
+  <layout tileable="true">
     <!--auto_layout aspect_ratio="1.0"-->
     <fixed_layout name="2x2" width="4" height="4">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
diff --git a/vpr/src/device/rr_graph_obj.cpp b/vpr/src/device/rr_graph_obj.cpp
index 9124ffdc7..4a6ca1256 100644
--- a/vpr/src/device/rr_graph_obj.cpp
+++ b/vpr/src/device/rr_graph_obj.cpp
@@ -145,7 +145,7 @@ short RRGraph::node_capacity(const RRNodeId& node) const {
 
 short RRGraph::node_ptc_num(const RRNodeId& node) const {
     VTR_ASSERT_SAFE(valid_node_id(node));
-    return node_ptc_nums_[node];
+    return node_ptc_nums_[node][0];
 }
 
 short RRGraph::node_pin_num(const RRNodeId& node) const {
@@ -165,6 +165,13 @@ short RRGraph::node_class_num(const RRNodeId& node) const {
     return node_ptc_num(node);
 }
 
+std::vector<short> RRGraph::node_track_ids(const RRNodeId& node) const {
+    VTR_ASSERT_MSG(node_type(node) == CHANX || node_type(node) == CHANY,
+                   "Track number valid only for CHANX/CHANY RR nodes");
+    VTR_ASSERT_SAFE(valid_node_id(node));
+    return node_ptc_nums_[node];
+}
+
 short RRGraph::node_cost_index(const RRNodeId& node) const {
     VTR_ASSERT_SAFE(valid_node_id(node));
     return node_cost_indices_[node];
@@ -823,7 +830,7 @@ RRNodeId RRGraph::create_node(const t_rr_type& type) {
     node_bounding_boxes_.emplace_back(-1, -1, -1, -1);
 
     node_capacities_.push_back(-1);
-    node_ptc_nums_.push_back(-1);
+    node_ptc_nums_.push_back(std::vector<short>(1, -1));
     node_cost_indices_.push_back(-1);
     node_directions_.push_back(NO_DIRECTION);
     node_sides_.push_back(NUM_SIDES);
@@ -999,7 +1006,18 @@ void RRGraph::set_node_capacity(const RRNodeId& node, const short& capacity) {
 void RRGraph::set_node_ptc_num(const RRNodeId& node, const short& ptc) {
     VTR_ASSERT(valid_node_id(node));
 
-    node_ptc_nums_[node] = ptc;
+    /* For CHANX and CHANY, we will resize the ptc num to length of the node
+     * For other nodes, we will always assign the first element
+     */
+    if ((CHANX == node_type(node)) || (CHANY == node_type(node))) {
+        if ((size_t)node_length(node) + 1 != node_ptc_nums_[node].size()) {
+            node_ptc_nums_[node].resize(node_length(node) + 1);
+        }
+        std::fill(node_ptc_nums_[node].begin(), node_ptc_nums_[node].end(), ptc);
+    } else {
+        VTR_ASSERT(1 == node_ptc_nums_[node].size());
+        node_ptc_nums_[node][0] = ptc;
+    }
 }
 
 void RRGraph::set_node_pin_num(const RRNodeId& node, const short& pin_id) {
@@ -1023,6 +1041,22 @@ void RRGraph::set_node_class_num(const RRNodeId& node, const short& class_id) {
     set_node_ptc_num(node, class_id);
 }
 
+void RRGraph::add_node_track_num(const RRNodeId& node,
+                                 const vtr::Point<size_t>& node_offset,
+                                 const short& track_id) {
+    VTR_ASSERT(valid_node_id(node));
+    VTR_ASSERT_MSG(node_type(node) == CHANX || node_type(node) == CHANY, "Track number valid only for CHANX/CHANY RR nodes");
+
+    if ((size_t)node_length(node) + 1 != node_ptc_nums_[node].size()) {
+        node_ptc_nums_[node].resize(node_length(node) + 1);
+    }
+
+    size_t offset = node_offset.x() - node_xlow(node) + node_offset.y() - node_ylow(node);
+    VTR_ASSERT(offset < node_ptc_nums_[node].size());
+
+    node_ptc_nums_[node][offset] = track_id;
+}
+
 void RRGraph::set_node_cost_index(const RRNodeId& node, const short& cost_index) {
     VTR_ASSERT(valid_node_id(node));
     node_cost_indices_[node] = cost_index;
@@ -1235,10 +1269,18 @@ void RRGraph::build_fast_node_lookup() const {
 
         size_t itype = node_type(node);
 
-        size_t ptc = node_ptc_num(node);
-
         for (const size_t& x : node_x) {
             for (const size_t& y : node_y) {
+                size_t ptc = node_ptc_num(node);
+                /* Routing channel nodes may have different ptc num 
+                 * Find the track ids using the x/y offset  
+                 */
+                if (CHANX == node_type(node)) {
+                    ptc = node_track_ids(node)[x - node_xlow(node)];
+                } else if (CHANY == node_type(node)) {
+                    ptc = node_track_ids(node)[y - node_ylow(node)];
+                }
+
                 if (ptc >= node_lookup_[x][y][itype].size()) {
                     node_lookup_[x][y][itype].resize(ptc + 1);
                 }
diff --git a/vpr/src/device/rr_graph_obj.h b/vpr/src/device/rr_graph_obj.h
index 648934554..12a67c150 100644
--- a/vpr/src/device/rr_graph_obj.h
+++ b/vpr/src/device/rr_graph_obj.h
@@ -413,11 +413,24 @@ class RRGraph {
      * node_class_num() is designed for routing source and sinks, which are SOURCE and SINK nodes
      *
      * Due to a useful identifier, ptc_num is used in building fast look-up 
+     *
+     * Note: routing channels CHANX and CHANY may have multiple ptc_num due to 
+     *       tileable routing architecture, where a routing track may bend 
+     *       when passing each SB
+     *       By default, we always return the first ptc_num and track_num for
+     *       these nodee, while the other ptc num is accessible through fast look-up
+     *       when searching for a routing track in a channel
+     *
+     *       For CHANX, the track id vector is the same as yhigh - ylow + 1
+     *       For CHANY, the track id vector is the same as xhigh - xlow + 1
+     *       The first track id is always the track id at (xlow, ylow)
+     *       The last track id is always the track id at (xhigh, yhigh)
      */
     short node_ptc_num(const RRNodeId& node) const;
     short node_pin_num(const RRNodeId& node) const;
     short node_track_num(const RRNodeId& node) const;
     short node_class_num(const RRNodeId& node) const;
+    std::vector<short> node_track_ids(const RRNodeId& node) const;
 
     /* Get the index of cost data in the list of cost_indexed_data data structure
      * It contains the routing cost for different nodes in the RRGraph
@@ -696,6 +709,14 @@ class RRGraph {
      */
     void set_node_class_num(const RRNodeId& node, const short& class_id);
 
+    /* Add track id for a CHANX or a CHANY node.
+     * This is mainly used by tileable rr_graph where rr_node may
+     * have different track id in different channels
+     */
+    void add_node_track_num(const RRNodeId& node,
+                            const vtr::Point<size_t>& node_offset,
+                            const short& track_id);
+
     /* Set the routing cost index for node, see node_cost_index() for details */
     /* TODO: the cost index should be changed to a StrongId!!! */
     void set_node_cost_index(const RRNodeId& node, const short& cost_index);
@@ -851,7 +872,8 @@ class RRGraph {
     vtr::vector<RRNodeId, vtr::Rect<short>> node_bounding_boxes_;
 
     vtr::vector<RRNodeId, short> node_capacities_;
-    vtr::vector<RRNodeId, short> node_ptc_nums_;
+
+    vtr::vector<RRNodeId, std::vector<short>> node_ptc_nums_;
     vtr::vector<RRNodeId, short> node_cost_indices_;
     vtr::vector<RRNodeId, e_direction> node_directions_;
     vtr::vector<RRNodeId, e_side> node_sides_;
diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp
index d8c1fb23b..7b6360877 100644
--- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp
+++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp
@@ -666,6 +666,12 @@ void load_one_chan_rr_nodes_basic_info(RRGraph& rr_graph,
     
       rr_graph.set_node_xlow(node, chan_coordinate.x());
       rr_graph.set_node_ylow(node, chan_coordinate.y());
+     
+      /* Deposit xhigh and yhigh as the same value as xlow and ylow
+       * We will update when this track ends
+       */
+      rr_graph.set_node_xhigh(node, chan_coordinate.x());
+      rr_graph.set_node_yhigh(node, chan_coordinate.y());
 
       rr_graph.set_node_direction(node, chan_details.get_track_direction(itrack)); 
       rr_graph.set_node_track_num(node, itrack);
@@ -709,6 +715,7 @@ void load_one_chan_rr_nodes_basic_info(RRGraph& rr_graph,
       if ( (rr_graph.node_xhigh(rr_node_id) > rr_graph.node_xlow(rr_node_id))
         || (rr_graph.node_yhigh(rr_node_id) > rr_graph.node_ylow(rr_node_id)) ) {
         rr_node_track_ids[rr_node_id].push_back(itrack);
+        rr_graph.add_node_track_num(rr_node_id, chan_coordinate, itrack);
       }
       /* Finish here, go to next */
     }
@@ -734,6 +741,7 @@ void load_one_chan_rr_nodes_basic_info(RRGraph& rr_graph,
 
     /* Update track_ids */
     rr_node_track_ids[rr_node_id].push_back(itrack);
+    rr_graph.add_node_track_num(rr_node_id, chan_coordinate, itrack);
     /* Finish here, go to next */
   }
 } 

From 9a518e8bb6748c408e21e01e0947a581ae264fd0 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 21 Mar 2020 18:07:00 -0600
Subject: [PATCH 327/645] bug fixed for tileable rr_graph builder for more 4x4
 fabrics

---
 openfpga/src/base/openfpga_build_fabric.cpp   | 21 +++++++++----------
 .../and_k6_frac_adder_chain.openfpga          |  2 +-
 .../k6_frac_N10_adder_chain_40nm.xml          |  2 +-
 .../tileable_rr_graph_node_builder.cpp        |  6 ++++++
 4 files changed, 18 insertions(+), 13 deletions(-)

diff --git a/openfpga/src/base/openfpga_build_fabric.cpp b/openfpga/src/base/openfpga_build_fabric.cpp
index a1e90055b..9e315500c 100644
--- a/openfpga/src/base/openfpga_build_fabric.cpp
+++ b/openfpga/src/base/openfpga_build_fabric.cpp
@@ -30,28 +30,27 @@ void compress_routing_hierarchy(OpenfpgaContext& openfpga_ctx,
 
   /* Report the stats */
   VTR_LOGV(verbose_output, 
-           "Detected %lu unique X-direction connection blocks from a total of %d (compression rate=%d%)\n",
+           "Detected %lu unique X-direction connection blocks from a total of %d (compression rate=%.2f%)\n",
            openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANX),
            find_device_rr_gsb_num_cb_modules(openfpga_ctx.device_rr_gsb(), CHANX),
-           100 * (openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANX) / find_device_rr_gsb_num_cb_modules(openfpga_ctx.device_rr_gsb(), CHANX) - 1));
+           100. * (find_device_rr_gsb_num_cb_modules(openfpga_ctx.device_rr_gsb(), CHANX) / openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANX) - 1.));
 
   VTR_LOGV(verbose_output,
-           "Detected %lu unique Y-direction connection blocks from a total of %d (compression rate=%d%)\n",
+           "Detected %lu unique Y-direction connection blocks from a total of %d (compression rate=%.2f%)\n",
            openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANY),
            find_device_rr_gsb_num_cb_modules(openfpga_ctx.device_rr_gsb(), CHANY),
-           100 * (openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANY) / find_device_rr_gsb_num_cb_modules(openfpga_ctx.device_rr_gsb(), CHANY) - 1));
+           100. * (find_device_rr_gsb_num_cb_modules(openfpga_ctx.device_rr_gsb(), CHANY) / openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANY) - 1.));
 
   VTR_LOGV(verbose_output,
-           "Detected %lu unique switch blocks from a total of %d (compression rate=%d%)\n",
+           "Detected %lu unique switch blocks from a total of %d (compression rate=%.2f%)\n",
            openfpga_ctx.device_rr_gsb().get_num_sb_unique_module(),
            find_device_rr_gsb_num_sb_modules(openfpga_ctx.device_rr_gsb()),
-           100 * (openfpga_ctx.device_rr_gsb().get_num_sb_unique_module() / find_device_rr_gsb_num_sb_modules(openfpga_ctx.device_rr_gsb()) - 1));
+           100. * (find_device_rr_gsb_num_sb_modules(openfpga_ctx.device_rr_gsb()) / openfpga_ctx.device_rr_gsb().get_num_sb_unique_module() - 1));
 
-  VTR_LOGV(verbose_output,
-           "Detected %lu unique general switch blocks from a total of %d (compression rate=%d%)\n",
-           openfpga_ctx.device_rr_gsb().get_num_gsb_unique_module(),
-           find_device_rr_gsb_num_gsb_modules(openfpga_ctx.device_rr_gsb()),
-           100 * (openfpga_ctx.device_rr_gsb().get_num_gsb_unique_module() / find_device_rr_gsb_num_gsb_modules(openfpga_ctx.device_rr_gsb()) - 1));
+  VTR_LOG("Detected %lu unique general switch blocks from a total of %d (compression rate=%.2f%)\n",
+          openfpga_ctx.device_rr_gsb().get_num_gsb_unique_module(),
+          find_device_rr_gsb_num_gsb_modules(openfpga_ctx.device_rr_gsb()),
+          100. * (find_device_rr_gsb_num_gsb_modules(openfpga_ctx.device_rr_gsb()) / openfpga_ctx.device_rr_gsb().get_num_gsb_unique_module() - 1.));
 }
 
 /********************************************************************
diff --git a/openfpga/test_script/and_k6_frac_adder_chain.openfpga b/openfpga/test_script/and_k6_frac_adder_chain.openfpga
index 156f49ff0..eb762f384 100644
--- a/openfpga/test_script/and_k6_frac_adder_chain.openfpga
+++ b/openfpga/test_script/and_k6_frac_adder_chain.openfpga
@@ -22,7 +22,7 @@ lut_truth_table_fixup #--verbose
 # Build the module graph 
 #  - Enabled compression on routing architecture modules
 #  - Enable pin duplication on grid modules 
-build_fabric --compress_routing --duplicate_grid_pin #--verbose
+build_fabric --compress_routing --duplicate_grid_pin --verbose
 
 # Repack the netlist to physical pbs
 # This must be done before bitstream generator and testbench generation
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
index c3598bd2b..9610fef06 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
@@ -161,7 +161,7 @@
   <!-- Physical descriptions begin -->
   <layout tileable="true">
     <!--auto_layout aspect_ratio="1.0"-->
-    <fixed_layout name="2x2" width="4" height="4">
+    <fixed_layout name="2x2" width="32" height="32">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
       <corners type="EMPTY" priority="101"/>
diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp
index 7b6360877..7191bc523 100644
--- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp
+++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp
@@ -739,6 +739,12 @@ void load_one_chan_rr_nodes_basic_info(RRGraph& rr_graph,
     VTR_ASSERT(chan_type == rr_graph.node_type(rr_node_id));
     VTR_ASSERT(chan_details.get_track_direction(itrack) == rr_graph.node_direction(rr_node_id));
 
+    /* Deposit xhigh and yhigh using the current chan_coordinate
+     * We will update when this track ends
+     */
+    rr_graph.set_node_xhigh(rr_node_id, chan_coordinate.x());
+    rr_graph.set_node_yhigh(rr_node_id, chan_coordinate.y());
+
     /* Update track_ids */
     rr_node_track_ids[rr_node_id].push_back(itrack);
     rr_graph.add_node_track_num(rr_node_id, chan_coordinate, itrack);

From 637be076dceb2eaf09858a5d6db101ea062bdee4 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 21 Mar 2020 18:49:20 -0600
Subject: [PATCH 328/645] adding xml writer for device rr_gsb to help debugging
 the compress routing; current compress routing is not working

---
 .../annotation/write_xml_device_rr_gsb.cpp    | 190 ++++++++++++++++++
 .../src/annotation/write_xml_device_rr_gsb.h  |  24 +++
 openfpga/src/main.cpp                         |   4 +
 .../k6_frac_N10_adder_chain_40nm.xml          |   2 +-
 4 files changed, 219 insertions(+), 1 deletion(-)
 create mode 100644 openfpga/src/annotation/write_xml_device_rr_gsb.cpp
 create mode 100644 openfpga/src/annotation/write_xml_device_rr_gsb.h

diff --git a/openfpga/src/annotation/write_xml_device_rr_gsb.cpp b/openfpga/src/annotation/write_xml_device_rr_gsb.cpp
new file mode 100644
index 000000000..cd3fb7b43
--- /dev/null
+++ b/openfpga/src/annotation/write_xml_device_rr_gsb.cpp
@@ -0,0 +1,190 @@
+/***************************************************************************************
+ * Output internal structure of DeviceRRGSB to XML format 
+ ***************************************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_log.h"
+#include "vtr_assert.h"
+#include "vtr_time.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_side_manager.h"
+#include "openfpga_digest.h"
+
+#include "openfpga_naming.h"
+#include "openfpga_rr_graph_utils.h"
+
+#include "write_xml_device_rr_gsb.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/***************************************************************************************
+ * Output internal structure (only the switch block part) of a RRGSB to XML format 
+ ***************************************************************************************/
+static 
+void write_rr_switch_block_to_xml(const std::string fname_prefix,
+                                  const RRGraph& rr_graph,
+                                  const RRGSB& rr_gsb) {
+  /* Prepare file name */
+  std::string fname(fname_prefix);
+  vtr::Point<size_t> gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
+  fname += generate_switch_block_module_name(gsb_coordinate);
+  fname += ".xml";
+
+  VTR_LOG("Output internal structure of Switch Block to '%s'\r", fname.c_str());
+
+  /* Create a file handler*/
+  std::fstream fp;
+  /* Open a file */
+  fp.open(fname, std::fstream::out | std::fstream::trunc);
+
+  /* Validate the file stream */
+  check_file_stream(fname.c_str(), fp);
+
+  /* Output location of the Switch Block */
+  fp << "<rr_gsb x=\"" << rr_gsb.get_x() << "\" y=\"" << rr_gsb.get_y() << "\""
+     << " num_sides=\"" << rr_gsb.get_num_sides() << "\">" << std::endl;
+
+  /* Output each side */ 
+  for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
+    SideManager gsb_side_manager(side);
+    enum e_side gsb_side = gsb_side_manager.get_side();
+   
+    /* Output IPIN nodes */ 
+    for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(gsb_side); ++inode) {
+      const RRNodeId& cur_rr_node = rr_gsb.get_ipin_node(gsb_side, inode);
+      /* General information of this IPIN */
+      fp << "\t<" << rr_node_typename[rr_graph.node_type(cur_rr_node)]
+         << " side=\"" << gsb_side_manager.to_string() 
+         << "\" index=\"" << inode 
+         << "\" mux_size=\"" << get_rr_graph_configurable_driver_nodes(rr_graph, cur_rr_node).size()
+         << "\">" 
+         << std::endl; 
+      /* General information of each driving nodes */
+      for (const RRNodeId& driver_node : get_rr_graph_configurable_driver_nodes(rr_graph, cur_rr_node)) {
+        /* Skip OPINs: they should be in direct connections */
+        if (OPIN == rr_graph.node_type(driver_node)) {
+          continue;
+        }
+
+        enum e_side chan_side = rr_gsb.get_cb_chan_side(gsb_side);
+        SideManager chan_side_manager(chan_side);
+
+         /* For channel node, we do not know the node direction
+         * But we are pretty sure it is either IN_PORT or OUT_PORT
+         * So we just try and find what is valid
+         */
+        int driver_node_index = rr_gsb.get_chan_node_index(chan_side, driver_node);
+        /* We must have a valide node index */
+        VTR_ASSERT(-1 != driver_node_index);
+
+        const RRSegmentId& des_segment_id = rr_gsb.get_chan_node_segment(chan_side, driver_node_index);
+
+        fp << "\t\t<driver_node type=\"" << rr_node_typename[rr_graph.node_type(driver_node)]
+           << "\" side=\"" << chan_side_manager.to_string() 
+           << "\" index=\"" << driver_node_index 
+           << "\" segment_id=\"" << size_t(des_segment_id)
+           << "\"/>" 
+           << std::endl; 
+      }
+      fp << "\t</" << rr_node_typename[rr_graph.node_type(cur_rr_node)] 
+         << ">" 
+         << std::endl; 
+    }
+
+    /* Output chan nodes */
+    for (size_t inode = 0; inode < rr_gsb.get_chan_width(gsb_side); ++inode) {
+      /* We only care OUT_PORT */
+      if (OUT_PORT != rr_gsb.get_chan_node_direction(gsb_side, inode)) {
+        continue;
+      }
+      /* Output drivers */
+      const RRNodeId& cur_rr_node = rr_gsb.get_chan_node(gsb_side, inode);
+      std::vector<RRNodeId> driver_rr_nodes = get_rr_graph_configurable_driver_nodes(rr_graph, cur_rr_node);
+
+      /* Output node information: location, index, side */
+      const RRSegmentId& src_segment_id = rr_gsb.get_chan_node_segment(gsb_side, inode);
+
+      /* Check if this node is directly connected to the node on the opposite side */
+      if (true == rr_gsb.is_sb_node_passing_wire(rr_graph, gsb_side, inode)) {
+        driver_rr_nodes.clear();
+      }
+
+      fp << "\t<" << rr_node_typename[rr_graph.node_type(cur_rr_node)]
+         << " side=\"" << gsb_side_manager.to_string() 
+         << "\" index=\"" << inode 
+         << "\" segment_id=\"" << size_t(src_segment_id)
+         << "\" mux_size=\"" << driver_rr_nodes.size()
+         << "\">" 
+         << std::endl; 
+
+      /* Direct connection: output the node on the opposite side */
+      if (0 == driver_rr_nodes.size()) {
+        SideManager oppo_side =  gsb_side_manager.get_opposite();
+        fp << "\t\t<driver_node type=\"" << rr_node_typename[rr_graph.node_type(cur_rr_node)]
+           << "\" side=\"" << oppo_side.to_string() 
+           << "\" index=\"" << rr_gsb.get_node_index(rr_graph, cur_rr_node, oppo_side.get_side(), IN_PORT) 
+           << "\" segment_id=\"" << size_t(src_segment_id)
+           << "\"/>" 
+           << std::endl; 
+      } else {
+        for (const RRNodeId& driver_rr_node : driver_rr_nodes) {
+          e_side driver_node_side = NUM_SIDES;
+          int driver_node_index = -1;
+          rr_gsb.get_node_side_and_index(rr_graph, driver_rr_node, IN_PORT, driver_node_side, driver_node_index);
+          VTR_ASSERT(-1 != driver_node_index);
+          SideManager driver_side(driver_node_side);
+
+          if (OPIN == rr_graph.node_type(driver_rr_node)) {
+            SideManager grid_side(rr_graph.node_side(driver_rr_node));
+            fp << "\t\t<driver_node type=\"" << rr_node_typename[OPIN]
+               << "\" side=\"" << driver_side.to_string() 
+               << "\" index=\"" << driver_node_index  
+               << "\" grid_side=\"" <<  grid_side.to_string() 
+               <<"\"/>" 
+               << std::endl; 
+          } else {
+            const RRSegmentId& des_segment_id = rr_gsb.get_chan_node_segment(driver_node_side, driver_node_index);
+            fp << "\t\t<driver_node type=\"" << rr_node_typename[rr_graph.node_type(driver_rr_node)]
+               << "\" side=\"" << driver_side.to_string() 
+               << "\" index=\"" << driver_node_index 
+               << "\" segment_id=\"" << size_t(des_segment_id)
+               << "\"/>" 
+               << std::endl; 
+          }
+        }  
+      }
+      fp << "\t</" << rr_node_typename[rr_graph.node_type(cur_rr_node)]
+         << ">" 
+         << std::endl; 
+    }
+  }
+
+  fp << "</rr_gsb>" 
+     << std::endl;
+
+  /* close a file */
+  fp.close();
+}
+
+/***************************************************************************************
+ * Output internal structure (only the switch block part) of all the RRGSBs
+ * in a DeviceRRGSB  to XML format 
+ ***************************************************************************************/
+void write_device_rr_gsb_to_xml(const char* sb_xml_dir, 
+                                const RRGraph& rr_graph,
+                                const DeviceRRGSB& device_rr_gsb) {
+  std::string fname_prefix = format_dir_path(std::string(sb_xml_dir));
+
+  vtr::Point<size_t> sb_range = device_rr_gsb.get_gsb_range();
+
+  /* For each switch block, an XML file will be outputted */
+  for (size_t ix = 0; ix < sb_range.x(); ++ix) {
+    for (size_t iy = 0; iy < sb_range.y(); ++iy) {
+      const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
+      write_rr_switch_block_to_xml(fname_prefix, rr_graph, rr_gsb);
+    }
+  }
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/annotation/write_xml_device_rr_gsb.h b/openfpga/src/annotation/write_xml_device_rr_gsb.h
new file mode 100644
index 000000000..06c9a0a89
--- /dev/null
+++ b/openfpga/src/annotation/write_xml_device_rr_gsb.h
@@ -0,0 +1,24 @@
+#ifndef WRITE_XML_DEVICE_RR_GSB_H
+#define WRITE_XML_DEVICE_RR_GSB_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <string>
+#include "rr_graph_obj.h"
+#include "device_rr_gsb.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void write_device_rr_gsb_to_xml(const char* sb_xml_dir,
+                                const RRGraph& rr_graph,
+                                const DeviceRRGSB& device_rr_gsb);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/main.cpp b/openfpga/src/main.cpp
index b2c9d2e6c..eb88c2c65 100644
--- a/openfpga/src/main.cpp
+++ b/openfpga/src/main.cpp
@@ -2,6 +2,7 @@
  * Build the OpenFPGA shell interface 
  *******************************************************************/
 /* Header file from vtrutil library */
+#include "vtr_time.h"
 #include "vtr_log.h"
 
 /* Header file from libopenfpgashell library */
@@ -87,11 +88,14 @@ int main(int argc, char** argv) {
   } else {
     /* Parse succeed. Start a shell */ 
     if (true == start_cmd_context.option_enable(start_cmd, opt_interactive)) {
+
+      vtr::ScopedStartFinishTimer timer("OpenFPGA operating");
       shell.run_interactive_mode(openfpga_context);
       return 0;
     } 
 
     if (true == start_cmd_context.option_enable(start_cmd, opt_script_mode)) {
+      vtr::ScopedStartFinishTimer timer("OpenFPGA operating");
       shell.run_script_mode(start_cmd_context.option_value(start_cmd, opt_script_mode).c_str(),
                             openfpga_context);
       return 0;
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
index 9610fef06..eea76837f 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
@@ -161,7 +161,7 @@
   <!-- Physical descriptions begin -->
   <layout tileable="true">
     <!--auto_layout aspect_ratio="1.0"-->
-    <fixed_layout name="2x2" width="32" height="32">
+    <fixed_layout name="4x4" width="6" height="6">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
       <corners type="EMPTY" priority="101"/>

From 7b9384f3b27e6de27b7af66d650d7524d549ed32 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 21 Mar 2020 19:40:26 -0600
Subject: [PATCH 329/645] add write_gsb command to shell interface

---
 .../annotation/write_xml_device_rr_gsb.cpp    | 24 ++++++++---
 .../src/annotation/write_xml_device_rr_gsb.h  |  3 +-
 openfpga/src/base/openfpga_setup_command.cpp  | 40 +++++++++++++++++
 openfpga/src/base/openfpga_write_gsb.cpp      | 43 +++++++++++++++++++
 openfpga/src/base/openfpga_write_gsb.h        | 23 ++++++++++
 .../src/fabric/build_top_module_directs.cpp   |  4 +-
 .../and_k6_frac_adder_chain.openfpga          |  5 ++-
 7 files changed, 134 insertions(+), 8 deletions(-)
 create mode 100644 openfpga/src/base/openfpga_write_gsb.cpp
 create mode 100644 openfpga/src/base/openfpga_write_gsb.h

diff --git a/openfpga/src/annotation/write_xml_device_rr_gsb.cpp b/openfpga/src/annotation/write_xml_device_rr_gsb.cpp
index cd3fb7b43..4fa4b1f1d 100644
--- a/openfpga/src/annotation/write_xml_device_rr_gsb.cpp
+++ b/openfpga/src/annotation/write_xml_device_rr_gsb.cpp
@@ -24,14 +24,17 @@ namespace openfpga {
 static 
 void write_rr_switch_block_to_xml(const std::string fname_prefix,
                                   const RRGraph& rr_graph,
-                                  const RRGSB& rr_gsb) {
+                                  const RRGSB& rr_gsb,
+                                  const bool& verbose) {
   /* Prepare file name */
   std::string fname(fname_prefix);
   vtr::Point<size_t> gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
   fname += generate_switch_block_module_name(gsb_coordinate);
   fname += ".xml";
 
-  VTR_LOG("Output internal structure of Switch Block to '%s'\r", fname.c_str());
+  VTR_LOGV(verbose,
+           "Output internal structure of Switch Block to '%s'\n",
+           fname.c_str());
 
   /* Create a file handler*/
   std::fstream fp;
@@ -173,18 +176,29 @@ void write_rr_switch_block_to_xml(const std::string fname_prefix,
  ***************************************************************************************/
 void write_device_rr_gsb_to_xml(const char* sb_xml_dir, 
                                 const RRGraph& rr_graph,
-                                const DeviceRRGSB& device_rr_gsb) {
-  std::string fname_prefix = format_dir_path(std::string(sb_xml_dir));
+                                const DeviceRRGSB& device_rr_gsb,
+                                const bool& verbose) {
+  std::string xml_dir_name = format_dir_path(std::string(sb_xml_dir));
+
+  /* Create directories */
+  create_dir_path(xml_dir_name.c_str());
 
   vtr::Point<size_t> sb_range = device_rr_gsb.get_gsb_range();
 
+  size_t gsb_counter = 0;
+
   /* For each switch block, an XML file will be outputted */
   for (size_t ix = 0; ix < sb_range.x(); ++ix) {
     for (size_t iy = 0; iy < sb_range.y(); ++iy) {
       const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
-      write_rr_switch_block_to_xml(fname_prefix, rr_graph, rr_gsb);
+      write_rr_switch_block_to_xml(xml_dir_name, rr_graph, rr_gsb, verbose);
+      gsb_counter++;
     }
   }
+
+  VTR_LOG("Output %lu XML files to directory '%s'\n",
+          gsb_counter,
+          xml_dir_name.c_str());
 }
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/annotation/write_xml_device_rr_gsb.h b/openfpga/src/annotation/write_xml_device_rr_gsb.h
index 06c9a0a89..a6655ab22 100644
--- a/openfpga/src/annotation/write_xml_device_rr_gsb.h
+++ b/openfpga/src/annotation/write_xml_device_rr_gsb.h
@@ -17,7 +17,8 @@ namespace openfpga {
 
 void write_device_rr_gsb_to_xml(const char* sb_xml_dir,
                                 const RRGraph& rr_graph,
-                                const DeviceRRGSB& device_rr_gsb);
+                                const DeviceRRGSB& device_rr_gsb,
+                                const bool& verbose);
 
 } /* end namespace openfpga */
 
diff --git a/openfpga/src/base/openfpga_setup_command.cpp b/openfpga/src/base/openfpga_setup_command.cpp
index 0bbc8b2a2..8f4b0cec3 100644
--- a/openfpga/src/base/openfpga_setup_command.cpp
+++ b/openfpga/src/base/openfpga_setup_command.cpp
@@ -9,6 +9,7 @@
 #include "openfpga_lut_truth_table_fixup.h"
 #include "check_netlist_naming_conflict.h"
 #include "openfpga_build_fabric.h"
+#include "openfpga_write_gsb.h"
 #include "openfpga_setup_command.h"
 
 /* begin namespace openfpga */
@@ -95,6 +96,35 @@ ShellCommandId add_openfpga_link_arch_command(openfpga::Shell<OpenfpgaContext>&
   return shell_cmd_id;
 }
 
+/********************************************************************
+ * - Add a command to Shell environment: write_gsb_to_xml
+ * - Add associated options 
+ * - Add command dependency
+ *******************************************************************/
+static 
+ShellCommandId add_openfpga_write_gsb_command(openfpga::Shell<OpenfpgaContext>& shell,
+                                              const ShellCommandClassId& cmd_class_id,
+                                              const std::vector<ShellCommandId>& dependent_cmds) {
+  Command shell_cmd("write_gsb_to_xml");
+  /* Add an option '--file' in short '-f'*/
+  CommandOptionId opt_file = shell_cmd.add_option("file", true, "path to the directory that stores the XML files");
+  shell_cmd.set_option_short_name(opt_file, "f");
+  shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING);
+
+  /* Add an option '--verbose' */
+  shell_cmd.add_option("verbose", false, "Show verbose outputs");
+
+  /* Add command 'write_openfpga_arch' to the Shell */
+  ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "write internal structures of General Switch Blocks to XML file");
+  shell.set_command_class(shell_cmd_id, cmd_class_id);
+  shell.set_command_const_execute_function(shell_cmd_id, write_gsb);
+
+  /* Add command dependency to the Shell */
+  shell.set_command_dependency(shell_cmd_id, dependent_cmds);
+
+  return shell_cmd_id;
+}
+
 /********************************************************************
  * - Add a command to Shell environment: check_netlist_naming_conflict
  * - Add associated options 
@@ -240,6 +270,16 @@ void add_openfpga_setup_commands(openfpga::Shell<OpenfpgaContext>& shell) {
   ShellCommandId link_arch_cmd_id = add_openfpga_link_arch_command(shell,
                                                                    openfpga_setup_cmd_class,
                                                                    link_arch_dependent_cmds);
+  /******************************** 
+   * Command 'write_gsb' 
+   */
+  /* The 'write_gsb' command should NOT be executed before 'link_openfpga_arch' */
+  std::vector<ShellCommandId> write_gsb_dependent_cmds;
+  write_gsb_dependent_cmds.push_back(link_arch_cmd_id);
+  add_openfpga_write_gsb_command(shell,
+                                 openfpga_setup_cmd_class,
+                                 write_gsb_dependent_cmds);
+
   /******************************************* 
    * Command 'check_netlist_naming_conflict'
    */ 
diff --git a/openfpga/src/base/openfpga_write_gsb.cpp b/openfpga/src/base/openfpga_write_gsb.cpp
new file mode 100644
index 000000000..9c367ebfb
--- /dev/null
+++ b/openfpga/src/base/openfpga_write_gsb.cpp
@@ -0,0 +1,43 @@
+/********************************************************************
+ * This file includes functions to compress the hierachy of routing architecture
+ *******************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_time.h"
+#include "vtr_log.h"
+
+#include "write_xml_device_rr_gsb.h"
+
+#include "openfpga_write_gsb.h"
+
+/* Include global variables of VPR */
+#include "globals.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Write internal structrure of all the General Switch Blocks (GSBs)
+ * to an XML file 
+ *******************************************************************/
+void write_gsb(const OpenfpgaContext& openfpga_ctx,
+               const Command& cmd, const CommandContext& cmd_context) { 
+
+  /* Check the option '--file' is enabled or not 
+   * Actually, it must be enabled as the shell interface will check 
+   * before reaching this fuction
+   */
+  CommandOptionId opt_file = cmd.option("file");
+  VTR_ASSERT(true == cmd_context.option_enable(cmd, opt_file));
+  VTR_ASSERT(false == cmd_context.option_value(cmd, opt_file).empty());
+
+  CommandOptionId opt_verbose = cmd.option("verbose");
+
+  std::string sb_file_name = cmd_context.option_value(cmd, opt_file);
+
+  write_device_rr_gsb_to_xml(sb_file_name.c_str(),
+                             g_vpr_ctx.device().rr_graph,
+                             openfpga_ctx.device_rr_gsb(),
+                             cmd_context.option_enable(cmd, opt_verbose));
+} 
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_write_gsb.h b/openfpga/src/base/openfpga_write_gsb.h
new file mode 100644
index 000000000..4f7110717
--- /dev/null
+++ b/openfpga/src/base/openfpga_write_gsb.h
@@ -0,0 +1,23 @@
+#ifndef OPENFPGA_WRITE_GSB_H
+#define OPENFPGA_WRITE_GSB_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "command.h"
+#include "command_context.h"
+#include "openfpga_context.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void write_gsb(const OpenfpgaContext& openfpga_ctx,
+               const Command& cmd, const CommandContext& cmd_context); 
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/fabric/build_top_module_directs.cpp b/openfpga/src/fabric/build_top_module_directs.cpp
index 314b5f2e8..c85fb50f1 100644
--- a/openfpga/src/fabric/build_top_module_directs.cpp
+++ b/openfpga/src/fabric/build_top_module_directs.cpp
@@ -96,7 +96,9 @@ void add_module_nets_tile_direct_connection(ModuleManager& module_manager,
   std::string src_port_name = generate_grid_port_name(src_clb_coord, src_pin_width, src_pin_height, src_pin_grid_side, src_tile_pin, false);
   ModulePortId src_port_id = module_manager.find_module_port(src_grid_module, src_port_name); 
   if (true != module_manager.valid_module_port_id(src_grid_module, src_port_id)) {
-    VTR_LOG("Fail to find port '%s'\n", src_port_name.c_str());
+    VTR_LOG_ERROR("Fail to find port '%s.%s'\n",
+                  src_module_name.c_str(),
+                  src_port_name.c_str());
   }
   VTR_ASSERT(true == module_manager.valid_module_port_id(src_grid_module, src_port_id));
   VTR_ASSERT(1 == module_manager.module_port(src_grid_module, src_port_id).get_width());
diff --git a/openfpga/test_script/and_k6_frac_adder_chain.openfpga b/openfpga/test_script/and_k6_frac_adder_chain.openfpga
index eb762f384..d151b0089 100644
--- a/openfpga/test_script/and_k6_frac_adder_chain.openfpga
+++ b/openfpga/test_script/and_k6_frac_adder_chain.openfpga
@@ -10,6 +10,9 @@ read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga
 # Annotate the OpenFPGA architecture to VPR data base
 link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose
 
+# Write GSB to XML for debugging
+write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml
+
 # Check and correct any naming conflicts in the BLIF netlist
 check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
 
@@ -22,7 +25,7 @@ lut_truth_table_fixup #--verbose
 # Build the module graph 
 #  - Enabled compression on routing architecture modules
 #  - Enable pin duplication on grid modules 
-build_fabric --compress_routing --duplicate_grid_pin --verbose
+build_fabric --compress_routing --duplicate_grid_pin #--verbose
 
 # Repack the netlist to physical pbs
 # This must be done before bitstream generator and testbench generation

From fc6abc13fd868181437253a96f6d7e5ade842504 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 21 Mar 2020 21:02:47 -0600
Subject: [PATCH 330/645] add physical tile utils to identify pins that have
 Fc=0

---
 .../build_grid_module_duplicated_pins.cpp     |  9 +++--
 .../fabric/build_top_module_connection.cpp    |  3 +-
 .../src/fabric/build_top_module_directs.cpp   |  4 +--
 .../utils/openfpga_physical_tile_utils.cpp    | 33 +++++++++++++++++++
 .../src/utils/openfpga_physical_tile_utils.h  | 24 ++++++++++++++
 openfpga/test_vpr_arch/k6_frac_N10_40nm.xml   |  6 ++--
 .../k6_frac_N10_adder_chain_40nm.xml          |  2 +-
 7 files changed, 73 insertions(+), 8 deletions(-)
 create mode 100644 openfpga/src/utils/openfpga_physical_tile_utils.cpp
 create mode 100644 openfpga/src/utils/openfpga_physical_tile_utils.h

diff --git a/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp b/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp
index d63b85998..0f4a86934 100644
--- a/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp
+++ b/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp
@@ -8,6 +8,8 @@
  *
  * Please follow this rules when creating new features!
  *******************************************************************/
+#include <algorithm>
+
 /* Headers from vtrutil library */
 #include "vtr_assert.h"
 
@@ -17,6 +19,8 @@
 #include "openfpga_naming.h"
 #include "openfpga_interconnect_types.h"
 
+#include "openfpga_physical_tile_utils.h"
+
 #include "build_grid_module_utils.h"
 #include "build_grid_module_duplicated_pins.h"
 
@@ -88,7 +92,8 @@ void add_grid_module_duplicated_pb_type_ports(ModuleManager& module_manager,
            * we do not duplicate in these cases */
           if ( (RECEIVER == pin_class_type)
             /* Xifan: I assume that each direct connection pin must have Fc=0. */
-            || ( (DRIVER == pin_class_type) && (0. == grid_type_descriptor->fc_specs[ipin].fc_value) ) ) {
+            || ( (DRIVER == pin_class_type)
+              && (0. == find_physical_tile_pin_Fc(grid_type_descriptor, ipin)) ) ) {
             vtr::Point<size_t> dummy_coordinate;
             std::string port_name = generate_grid_port_name(dummy_coordinate, iwidth, iheight, side, ipin, false);
             BasicPort grid_port(port_name, 0, 0);
@@ -169,7 +174,7 @@ void add_grid_module_net_connect_duplicated_pb_graph_pin(ModuleManager& module_m
      * Follow the traditional recipe when adding nets!  
      * Xifan: I assume that each direct connection pin must have Fc=0. 
      */
-    if (0. == grid_type_descriptor->fc_specs[grid_pin_index].fc_value) {
+    if (0. == find_physical_tile_pin_Fc(grid_type_descriptor, grid_pin_index)) {
       /* Create a net to connect the grid pin to child module pin */
       ModuleNetId net = module_manager.create_module_net(grid_module);
       /* Find the port in grid_module */
diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp
index f1895305e..0af6e3409 100644
--- a/openfpga/src/fabric/build_top_module_connection.cpp
+++ b/openfpga/src/fabric/build_top_module_connection.cpp
@@ -12,6 +12,7 @@
 #include "openfpga_naming.h"
 #include "pb_type_utils.h"
 #include "rr_gsb_utils.h"
+#include "openfpga_physical_tile_utils.h"
 
 #include "build_top_module_utils.h"
 #include "build_top_module_connection.h"
@@ -232,7 +233,7 @@ void add_top_module_nets_connect_grids_and_sb_with_duplicated_pins(ModuleManager
        * For other duplicated pins, we follow the new naming
        */
       std::string src_grid_port_name;
-      if (0. == grids[grid_coordinate.x()][grid_coordinate.y()].type->fc_specs[src_grid_pin_index].fc_value) {
+      if (0. == find_physical_tile_pin_Fc(grids[grid_coordinate.x()][grid_coordinate.y()].type, src_grid_pin_index)) {
         src_grid_port_name = generate_grid_port_name(grid_coordinate, src_grid_pin_width, src_grid_pin_height, 
                                                      rr_graph.node_side(rr_gsb.get_opin_node(side_manager.get_side(), inode)),
                                                      src_grid_pin_index, false);
diff --git a/openfpga/src/fabric/build_top_module_directs.cpp b/openfpga/src/fabric/build_top_module_directs.cpp
index c85fb50f1..81f589adb 100644
--- a/openfpga/src/fabric/build_top_module_directs.cpp
+++ b/openfpga/src/fabric/build_top_module_directs.cpp
@@ -96,8 +96,8 @@ void add_module_nets_tile_direct_connection(ModuleManager& module_manager,
   std::string src_port_name = generate_grid_port_name(src_clb_coord, src_pin_width, src_pin_height, src_pin_grid_side, src_tile_pin, false);
   ModulePortId src_port_id = module_manager.find_module_port(src_grid_module, src_port_name); 
   if (true != module_manager.valid_module_port_id(src_grid_module, src_port_id)) {
-    VTR_LOG_ERROR("Fail to find port '%s.%s'\n",
-                  src_module_name.c_str(),
+    VTR_LOG_ERROR("Fail to find port '%s[%lu][%lu].%s'\n",
+                  src_module_name.c_str(), src_clb_coord.x(), src_clb_coord.y(),
                   src_port_name.c_str());
   }
   VTR_ASSERT(true == module_manager.valid_module_port_id(src_grid_module, src_port_id));
diff --git a/openfpga/src/utils/openfpga_physical_tile_utils.cpp b/openfpga/src/utils/openfpga_physical_tile_utils.cpp
new file mode 100644
index 000000000..9b70f7f97
--- /dev/null
+++ b/openfpga/src/utils/openfpga_physical_tile_utils.cpp
@@ -0,0 +1,33 @@
+/***************************************************************************************
+ * This file includes most utilized functions that are used to acquire data from 
+ * VPR t_physical_tile_type 
+ ***************************************************************************************/
+
+/* Headers from vtrutil library */
+#include "vtr_log.h"
+#include "vtr_assert.h"
+#include "vtr_time.h"
+
+#include "openfpga_physical_tile_utils.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Find the Fc of a pin in physical tile 
+ *******************************************************************/
+float find_physical_tile_pin_Fc(t_physical_tile_type_ptr type,
+                                const int& pin) {
+  for (const t_fc_specification& fc_spec : type->fc_specs) {
+    if (fc_spec.pins.end() != std::find(fc_spec.pins.begin(), fc_spec.pins.end(), pin)) {
+      return fc_spec.fc_value; 
+    }
+  }
+  /* Every pin should have a Fc, give a wrong value */
+  VTR_LOGF_ERROR(__FILE__, __LINE__,
+                "Fail to find the Fc for %s.pin[%lu]\n",
+                type->name, pin);
+  exit(1);
+} 
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/utils/openfpga_physical_tile_utils.h b/openfpga/src/utils/openfpga_physical_tile_utils.h
new file mode 100644
index 000000000..451d931a8
--- /dev/null
+++ b/openfpga/src/utils/openfpga_physical_tile_utils.h
@@ -0,0 +1,24 @@
+#ifndef OPENFPGA_PHYSICAL_TILE_UTILS_H
+#define OPENFPGA_PHYSICAL_TILE_UTILS_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <vector>
+#include <string>
+#include "physical_types.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+float find_physical_tile_pin_Fc(t_physical_tile_type_ptr type,
+                                const int& pin);
+
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml
index 8f58cb221..2c528c13c 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml
@@ -77,13 +77,15 @@
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
   <layout tileable="true">
-    <auto_layout aspect_ratio="1.0">
+    <!--auto_layout aspect_ratio="1.0"-->
+    <fixed_layout name="2x2" width="4" height="4">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
       <corners type="EMPTY" priority="101"/>
       <!--Fill with 'clb'-->
       <fill type="clb" priority="10"/>
-    </auto_layout>
+    </fixed_layout>
+    <!-- /auto_layout -->
   </layout>
   <device>
     <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
index eea76837f..c3598bd2b 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
@@ -161,7 +161,7 @@
   <!-- Physical descriptions begin -->
   <layout tileable="true">
     <!--auto_layout aspect_ratio="1.0"-->
-    <fixed_layout name="4x4" width="6" height="6">
+    <fixed_layout name="2x2" width="4" height="4">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
       <corners type="EMPTY" priority="101"/>

From 3958ac24948cac78791d2ac6233a64ed9771a577 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 22 Mar 2020 15:26:15 -0600
Subject: [PATCH 331/645] fix bugs in flow manager on default compress routing
 problems

---
 openfpga/src/base/openfpga_build_fabric.cpp             | 2 ++
 openfpga/src/base/openfpga_flow_manager.cpp             | 8 ++++++++
 openfpga/src/base/openfpga_flow_manager.h               | 2 ++
 openfpga/test_script/and_k6_frac_adder_chain.openfpga   | 2 +-
 openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml | 2 +-
 vpr/src/tileable_rr_graph/rr_gsb.cpp                    | 2 +-
 6 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/openfpga/src/base/openfpga_build_fabric.cpp b/openfpga/src/base/openfpga_build_fabric.cpp
index 9e315500c..97c0c68be 100644
--- a/openfpga/src/base/openfpga_build_fabric.cpp
+++ b/openfpga/src/base/openfpga_build_fabric.cpp
@@ -65,6 +65,8 @@ void build_fabric(OpenfpgaContext& openfpga_ctx,
   
   if (true == cmd_context.option_enable(cmd, opt_compress_routing)) {
     compress_routing_hierarchy(openfpga_ctx, cmd_context.option_enable(cmd, opt_verbose));
+    /* Update flow manager to enable compress routing */
+    openfpga_ctx.mutable_flow_manager().set_compress_routing(true);
   }
 
   VTR_LOG("\n");
diff --git a/openfpga/src/base/openfpga_flow_manager.cpp b/openfpga/src/base/openfpga_flow_manager.cpp
index bc97f291d..1a50524df 100644
--- a/openfpga/src/base/openfpga_flow_manager.cpp
+++ b/openfpga/src/base/openfpga_flow_manager.cpp
@@ -8,6 +8,14 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
+/**************************************************
+ * Public Constructor
+ *************************************************/
+FlowManager::FlowManager() {
+  /* Turn off compress_routing as default */
+  compress_routing_ = false;
+}
+
 /**************************************************
  * Public Accessors 
  *************************************************/
diff --git a/openfpga/src/base/openfpga_flow_manager.h b/openfpga/src/base/openfpga_flow_manager.h
index 6a6ae7c75..e9f6f02c2 100644
--- a/openfpga/src/base/openfpga_flow_manager.h
+++ b/openfpga/src/base/openfpga_flow_manager.h
@@ -15,6 +15,8 @@ namespace openfpga {
  *
  *******************************************************************/
 class FlowManager {
+  public: /* Public constructor */
+    FlowManager();
   public: /* Public accessors */
     bool compress_routing() const;
   public: /* Public mutators */
diff --git a/openfpga/test_script/and_k6_frac_adder_chain.openfpga b/openfpga/test_script/and_k6_frac_adder_chain.openfpga
index d151b0089..3cdebb2b1 100644
--- a/openfpga/test_script/and_k6_frac_adder_chain.openfpga
+++ b/openfpga/test_script/and_k6_frac_adder_chain.openfpga
@@ -25,7 +25,7 @@ lut_truth_table_fixup #--verbose
 # Build the module graph 
 #  - Enabled compression on routing architecture modules
 #  - Enable pin duplication on grid modules 
-build_fabric --compress_routing --duplicate_grid_pin #--verbose
+build_fabric --compress_routing --duplicate_grid_pin --verbose
 
 # Repack the netlist to physical pbs
 # This must be done before bitstream generator and testbench generation
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
index c3598bd2b..eea76837f 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
@@ -161,7 +161,7 @@
   <!-- Physical descriptions begin -->
   <layout tileable="true">
     <!--auto_layout aspect_ratio="1.0"-->
-    <fixed_layout name="2x2" width="4" height="4">
+    <fixed_layout name="4x4" width="6" height="6">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
       <corners type="EMPTY" priority="101"/>
diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp
index b489182b2..f5d6ec6ca 100644
--- a/vpr/src/tileable_rr_graph/rr_gsb.cpp
+++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp
@@ -975,7 +975,7 @@ bool RRGSB::is_sb_node_mirror(const RRGraph& rr_graph,
 
   /* Use unsorted/sorted edges */
   std::vector<RREdgeId> node_in_edges = get_chan_node_in_edges(rr_graph, node_side, track_id);
-  std::vector<RREdgeId> cand_node_in_edges = cand. get_chan_node_in_edges(rr_graph, node_side, track_id);
+  std::vector<RREdgeId> cand_node_in_edges = cand.get_chan_node_in_edges(rr_graph, node_side, track_id);
   VTR_ASSERT(node_in_edges.size() == cand_node_in_edges.size());
 
   for (size_t iedge = 0; iedge < node_in_edges.size(); ++iedge) {

From fdf6a6bd3e853555f5c12b02b5923302e7f3f8aa Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 22 Mar 2020 15:48:11 -0600
Subject: [PATCH 332/645] use chan_node_in_edges from rr_gsb in XML writer

---
 openfpga/src/annotation/write_xml_device_rr_gsb.cpp | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/openfpga/src/annotation/write_xml_device_rr_gsb.cpp b/openfpga/src/annotation/write_xml_device_rr_gsb.cpp
index 4fa4b1f1d..906c71d70 100644
--- a/openfpga/src/annotation/write_xml_device_rr_gsb.cpp
+++ b/openfpga/src/annotation/write_xml_device_rr_gsb.cpp
@@ -103,26 +103,26 @@ void write_rr_switch_block_to_xml(const std::string fname_prefix,
       }
       /* Output drivers */
       const RRNodeId& cur_rr_node = rr_gsb.get_chan_node(gsb_side, inode);
-      std::vector<RRNodeId> driver_rr_nodes = get_rr_graph_configurable_driver_nodes(rr_graph, cur_rr_node);
+      std::vector<RREdgeId> driver_rr_edges = rr_gsb.get_chan_node_in_edges(rr_graph, gsb_side, inode);
 
       /* Output node information: location, index, side */
       const RRSegmentId& src_segment_id = rr_gsb.get_chan_node_segment(gsb_side, inode);
 
       /* Check if this node is directly connected to the node on the opposite side */
       if (true == rr_gsb.is_sb_node_passing_wire(rr_graph, gsb_side, inode)) {
-        driver_rr_nodes.clear();
+        driver_rr_edges.clear();
       }
 
       fp << "\t<" << rr_node_typename[rr_graph.node_type(cur_rr_node)]
          << " side=\"" << gsb_side_manager.to_string() 
          << "\" index=\"" << inode 
          << "\" segment_id=\"" << size_t(src_segment_id)
-         << "\" mux_size=\"" << driver_rr_nodes.size()
+         << "\" mux_size=\"" << driver_rr_edges.size()
          << "\">" 
          << std::endl; 
 
       /* Direct connection: output the node on the opposite side */
-      if (0 == driver_rr_nodes.size()) {
+      if (0 == driver_rr_edges.size()) {
         SideManager oppo_side =  gsb_side_manager.get_opposite();
         fp << "\t\t<driver_node type=\"" << rr_node_typename[rr_graph.node_type(cur_rr_node)]
            << "\" side=\"" << oppo_side.to_string() 
@@ -131,7 +131,8 @@ void write_rr_switch_block_to_xml(const std::string fname_prefix,
            << "\"/>" 
            << std::endl; 
       } else {
-        for (const RRNodeId& driver_rr_node : driver_rr_nodes) {
+        for (const RREdgeId& driver_rr_edge : driver_rr_edges) {
+          const RRNodeId& driver_rr_node = rr_graph.edge_src_node(driver_rr_edge);
           e_side driver_node_side = NUM_SIDES;
           int driver_node_index = -1;
           rr_gsb.get_node_side_and_index(rr_graph, driver_rr_node, IN_PORT, driver_node_side, driver_node_index);

From ff474d87de980607657b1f7827554d45dda3dd9e Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 22 Mar 2020 16:11:00 -0600
Subject: [PATCH 333/645] fixed critical bug in uniquifying GSBs. Now it can
 guarantee minimum number of unique GSBs

---
 openfpga/src/annotation/device_rr_gsb.cpp   |  1 +
 openfpga/src/base/openfpga_build_fabric.cpp |  2 +-
 vpr/src/tileable_rr_graph/rr_gsb.cpp        | 15 +++++++--------
 3 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/openfpga/src/annotation/device_rr_gsb.cpp b/openfpga/src/annotation/device_rr_gsb.cpp
index 1fcb16109..c10a9df9c 100644
--- a/openfpga/src/annotation/device_rr_gsb.cpp
+++ b/openfpga/src/annotation/device_rr_gsb.cpp
@@ -267,6 +267,7 @@ void DeviceRRGSB::build_sb_unique_module(const RRGraph& rr_graph) {
           break;
         }
       }
+
       /* Add to list if this is a unique mirror*/
       if (true == is_unique_module) {
         sb_unique_module_.push_back(sb_coordinate);
diff --git a/openfpga/src/base/openfpga_build_fabric.cpp b/openfpga/src/base/openfpga_build_fabric.cpp
index 97c0c68be..0e16018bd 100644
--- a/openfpga/src/base/openfpga_build_fabric.cpp
+++ b/openfpga/src/base/openfpga_build_fabric.cpp
@@ -45,7 +45,7 @@ void compress_routing_hierarchy(OpenfpgaContext& openfpga_ctx,
            "Detected %lu unique switch blocks from a total of %d (compression rate=%.2f%)\n",
            openfpga_ctx.device_rr_gsb().get_num_sb_unique_module(),
            find_device_rr_gsb_num_sb_modules(openfpga_ctx.device_rr_gsb()),
-           100. * (find_device_rr_gsb_num_sb_modules(openfpga_ctx.device_rr_gsb()) / openfpga_ctx.device_rr_gsb().get_num_sb_unique_module() - 1));
+           100. * (find_device_rr_gsb_num_sb_modules(openfpga_ctx.device_rr_gsb()) / openfpga_ctx.device_rr_gsb().get_num_sb_unique_module() - 1.));
 
   VTR_LOG("Detected %lu unique general switch blocks from a total of %d (compression rate=%.2f%)\n",
           openfpga_ctx.device_rr_gsb().get_num_gsb_unique_module(),
diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp
index f5d6ec6ca..fcb7eba11 100644
--- a/vpr/src/tileable_rr_graph/rr_gsb.cpp
+++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp
@@ -952,8 +952,6 @@ bool RRGSB::is_sb_node_mirror(const RRGraph& rr_graph,
                               const e_side& node_side, 
                               const size_t& track_id) const {
   /* Ensure rr_nodes are either the output of short-connection or multiplexer  */
-  RRNodeId node = this->get_chan_node(node_side, track_id);
-  RRNodeId cand_node = cand.get_chan_node(node_side, track_id);
   bool is_short_conkt = this->is_sb_node_passing_wire(rr_graph, node_side, track_id);
 
   if (is_short_conkt != cand.is_sb_node_passing_wire(rr_graph, node_side, track_id)) {
@@ -968,14 +966,15 @@ bool RRGSB::is_sb_node_mirror(const RRGraph& rr_graph,
     return true;
   }
 
-  /* For non-passing wires, check driving rr_nodes */
-  if (rr_graph.node_in_edges(node).size() != rr_graph.node_in_edges(cand_node).size()) {
-    return false;
-  }
-
   /* Use unsorted/sorted edges */
   std::vector<RREdgeId> node_in_edges = get_chan_node_in_edges(rr_graph, node_side, track_id);
   std::vector<RREdgeId> cand_node_in_edges = cand.get_chan_node_in_edges(rr_graph, node_side, track_id);
+
+  /* For non-passing wires, check driving rr_nodes */
+  if (node_in_edges.size() != cand_node_in_edges.size()) {
+    return false;
+  }
+
   VTR_ASSERT(node_in_edges.size() == cand_node_in_edges.size());
 
   for (size_t iedge = 0; iedge < node_in_edges.size(); ++iedge) {
@@ -984,7 +983,7 @@ bool RRGSB::is_sb_node_mirror(const RRGraph& rr_graph,
     RRNodeId src_node = rr_graph.edge_src_node(src_edge);
     RRNodeId src_cand_node = rr_graph.edge_src_node(src_cand_edge);
     /* node type should be the same  */
-    if (rr_graph.node_type(src_node) != rr_graph.node_type(cand_node)) {
+    if (rr_graph.node_type(src_node) != rr_graph.node_type(src_cand_node)) {
       return false;
     }
     /* switch type should be the same  */

From 9e4e12aae94d847f3a57b67037be20c7b33ebbe3 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 22 Mar 2020 16:13:04 -0600
Subject: [PATCH 334/645] fixed echo message in the compression rate of gsb
 uniquifying

---
 openfpga/src/base/openfpga_build_fabric.cpp | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/openfpga/src/base/openfpga_build_fabric.cpp b/openfpga/src/base/openfpga_build_fabric.cpp
index 0e16018bd..4e8b44916 100644
--- a/openfpga/src/base/openfpga_build_fabric.cpp
+++ b/openfpga/src/base/openfpga_build_fabric.cpp
@@ -33,24 +33,24 @@ void compress_routing_hierarchy(OpenfpgaContext& openfpga_ctx,
            "Detected %lu unique X-direction connection blocks from a total of %d (compression rate=%.2f%)\n",
            openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANX),
            find_device_rr_gsb_num_cb_modules(openfpga_ctx.device_rr_gsb(), CHANX),
-           100. * (find_device_rr_gsb_num_cb_modules(openfpga_ctx.device_rr_gsb(), CHANX) / openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANX) - 1.));
+           100. * ((float)find_device_rr_gsb_num_cb_modules(openfpga_ctx.device_rr_gsb(), CHANX) / (float)openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANX) - 1.));
 
   VTR_LOGV(verbose_output,
            "Detected %lu unique Y-direction connection blocks from a total of %d (compression rate=%.2f%)\n",
            openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANY),
            find_device_rr_gsb_num_cb_modules(openfpga_ctx.device_rr_gsb(), CHANY),
-           100. * (find_device_rr_gsb_num_cb_modules(openfpga_ctx.device_rr_gsb(), CHANY) / openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANY) - 1.));
+           100. * ((float)find_device_rr_gsb_num_cb_modules(openfpga_ctx.device_rr_gsb(), CHANY) / (float)openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANY) - 1.));
 
   VTR_LOGV(verbose_output,
            "Detected %lu unique switch blocks from a total of %d (compression rate=%.2f%)\n",
            openfpga_ctx.device_rr_gsb().get_num_sb_unique_module(),
            find_device_rr_gsb_num_sb_modules(openfpga_ctx.device_rr_gsb()),
-           100. * (find_device_rr_gsb_num_sb_modules(openfpga_ctx.device_rr_gsb()) / openfpga_ctx.device_rr_gsb().get_num_sb_unique_module() - 1.));
+           100. * ((float)find_device_rr_gsb_num_sb_modules(openfpga_ctx.device_rr_gsb()) / (float)openfpga_ctx.device_rr_gsb().get_num_sb_unique_module() - 1.));
 
   VTR_LOG("Detected %lu unique general switch blocks from a total of %d (compression rate=%.2f%)\n",
           openfpga_ctx.device_rr_gsb().get_num_gsb_unique_module(),
           find_device_rr_gsb_num_gsb_modules(openfpga_ctx.device_rr_gsb()),
-          100. * (find_device_rr_gsb_num_gsb_modules(openfpga_ctx.device_rr_gsb()) / openfpga_ctx.device_rr_gsb().get_num_gsb_unique_module() - 1.));
+          100. * ((float)find_device_rr_gsb_num_gsb_modules(openfpga_ctx.device_rr_gsb()) / (float)openfpga_ctx.device_rr_gsb().get_num_gsb_unique_module() - 1.));
 }
 
 /********************************************************************

From 75dfe6a045406746bcffd0c9ca463e0cfadf3254 Mon Sep 17 00:00:00 2001
From: Xifan Tang <tangxifan@gmail.com>
Date: Sun, 22 Mar 2020 16:21:35 -0600
Subject: [PATCH 335/645] update documentation for write_gsb_to_xml
 functionality

---
 docs/source/openfpga_shell/openfpga_commands.rst | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/docs/source/openfpga_shell/openfpga_commands.rst b/docs/source/openfpga_shell/openfpga_commands.rst
index edb2bf0ad..6551b7421 100644
--- a/docs/source/openfpga_shell/openfpga_commands.rst
+++ b/docs/source/openfpga_shell/openfpga_commands.rst
@@ -52,6 +52,16 @@ Setup OpenFPGA
 
   - ``--verbose`` Show verbose log
 
+.. option:: write_gsb_to_xml
+
+  Write the internal structure of General Switch Blocks (GSBs) across a FPGA fabric, including the interconnection between the nodes and node-level details, to XML files
+
+  - ``--file`` or ``-f`` Specify the output directory of the XML files. Each GSB will be written to an indepedent XML file
+
+  - ``--verbose`` Show verbose log
+
+  .. note:: This command is used to help users to study the difference between GSBs
+
 .. option:: check_netlist_naming_conflict 
 
   Check and correct any naming conflicts in the BLIF netlist

From 7e3a8e5794c9c3fd448dd76c6ae7ca838bd9b615 Mon Sep 17 00:00:00 2001
From: Xifan Tang <tangxifan@gmail.com>
Date: Sun, 22 Mar 2020 16:27:12 -0600
Subject: [PATCH 336/645] typo fixed in fpga-bitstream documentation

---
 docs/source/fpga_bitstream/file_organization.rst | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/docs/source/fpga_bitstream/file_organization.rst b/docs/source/fpga_bitstream/file_organization.rst
index c8476d1f9..d8190ac67 100644
--- a/docs/source/fpga_bitstream/file_organization.rst
+++ b/docs/source/fpga_bitstream/file_organization.rst
@@ -1,9 +1,12 @@
-Bistream Output File Format
+Bitstream Output File Format
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 FPGA-Bitstream can generate two types of bitstreams:
+
 * Generic bitstreams, where configuration bits are organized out-of-order in a database. We output the generic bitstream to a XML format, which is easy to debug. As shown in the following XML code, configuration bits are organized block by block, where each block could be a LUT, a routing multiplexer `etc`. Each ``bitstream_block`` includes two sets of information: 
+
   - ``hierarchy`` represents the location of this block in FPGA fabric.
+
   - ``bitstream`` represents the configuration bits affiliated to this block.
 
 .. code-block:: xml

From 08b46af7beb2d08a6dfd7f7eccdd1e82e2200105 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 24 Mar 2020 12:20:51 -0600
Subject: [PATCH 337/645] add micro architecture for heterogeneous FPGA with
 single-mode DPRAM

---
 .../k6_frac_N10_adder_chain_mem16K_40nm.xml   | 734 ++++++++++++++++++
 1 file changed, 734 insertions(+)
 create mode 100644 openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml

diff --git a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml
new file mode 100644
index 000000000..850eb5450
--- /dev/null
+++ b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml
@@ -0,0 +1,734 @@
+<!-- 
+  Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with 8 total FLE inputs (2 inputs of which are shared by the 5-LUTs) 
+    with optionally registered outputs
+    Each 5-LUT has an arithemtic mode that converts it to a single-bit adder with both inputs driven by 4-LUTs (both 4-LUTs share all 4 inputs)
+    Carry chain links to vertically adjacent logic blocks
+  - Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.  
+    Height = 6, found on every (8n+2)th column
+  - Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.  
+    Height = 4, found on every (8n+6)th column
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Details on Modelling:
+
+  The electrical design of the architecture described here is NOT from an 
+  optimized, SPICED architecture.  Instead, we attempt to create a reasonable 
+  architecture file by using an existing commercial FPGA to approximate the area, 
+  delay, and power of the underlying components. This is combined with a reasonable 40 nm 
+  model of wiring and circuit design for low-level routing components, where available.
+  The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also 
+  has wiring electrical parameters that allow the wire lengths and switch patterns to be 
+  modified and you will still get reasonable delay results for the new architecture.
+  The following describes, in detail, how we obtained the various electrical values for this 
+  architecture.
+
+  Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar 
+  architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture. 
+  (n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)      
+  This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to 
+  match the overall target (a 40 nm FPGA).
+
+  We obtain delay numbers by measuring delays of routing, soft logic blocks, 
+  memories, and multipliers from test circuits on a Stratix IV GX device 
+  (EP4SGX230DF29C2X, i.e. fastest speed grade). For routing, we took the average delay of H4 and V4 
+  wires.  Rmetal and Cmetal values for the routing wires were obtained from work done by Charles 
+  Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal stack 40 nm routing) and 
+  take the R and C data from the ITRS roadmap.  
+
+  For the general purpose logic block, we assume that the area and delays of the Stratix IV 
+  crossbar is close enough to the crossbar modelled here.  
+  Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to 
+  36:1 multiplexers.  We match these parameters in this architecture.
+
+  For LUTs, we include LUT 
+  delays measured from Stratix IV which is dependant on the input used (ie. some 
+  LUT inputs are faster than others).  The CAD tools at the time of VTR 7 does 
+  not consider differences in LUT input delays.
+
+  Adder delays obtained as approximate values from a Stratix IV EP4SE230F29C3 device.  
+  Delay obtained by compiling a 256 bit adder (registered inputs and outputs, 
+  all pins except clock virtual) then measuring the delays in chip-planner, 
+  sumout delay = 0.271ns to 0.348 ns, intra-block carry delay = 0.011 ns, 
+  inter-block carry delay = 0.327 ns.  Given this data, I will approximate 
+  sumout 0.3 ns, intra-block carry-delay = 0.01 ns, and 
+  inter-block carry-delay = 0.16 ns (since Altera inter-block carry delay has 
+  overhead that we don't have, I'll approximate the delay of a simpler chain at 
+  one half what they have.  This is very rough, anything from 0.01ns to 0.327ns 
+  can be justified).
+
+  Logic block area numbers obtained by scaling overall tile area of a 65nm 
+  Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out 
+  routing area at a channel width of 300. We use a channel width of 300 because it can route 
+  all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
+  total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
+  choosing a width that provides high routability. The architecture can be routed at different channel
+  widths, but we estimate the tile size and hence the physical length of routing wires assuming
+  a channel width of 300.
+
+  Sanity checks employed:
+    1.  We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches 
+        common electrical design.
+
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <model name="adder">
+      <input_ports>
+        <port name="a" combinational_sink_ports="sumout cout"/>
+        <port name="b" combinational_sink_ports="sumout cout"/>
+        <port name="cin" combinational_sink_ports="sumout cout"/>
+      </input_ports>
+      <output_ports>
+        <port name="cout"/>
+        <port name="sumout"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="frac_lut6">
+      <input_ports>
+        <port name="in"/>
+      </input_ports>
+      <output_ports>
+        <port name="lut4_out"/>
+        <port name="lut5_out"/>
+        <port name="lut6_out"/>
+      </output_ports>
+    </model>
+    <model name="dual_port_ram">
+      <input_ports>
+        <!-- write address lines -->
+        <port name="waddr" clock="clk"/>
+        <!-- read address lines -->
+        <port name="raddr" clock="clk"/>
+        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
+        <port name="d_in" clock="clk"/>
+        <!-- write enable -->
+        <port name="wen" clock="clk"/>
+        <!-- read enable -->
+        <port name="ren" clock="clk"/>
+        <!-- memories are often clocked -->
+        <port name="clk" is_clock="1"/>
+      </input_ports>
+      <output_ports>
+        <!-- output can be broken down into smaller bit widths minimum size 1 -->
+        <port name="d_out" clock="clk"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <tile name="io" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad</loc>
+        <loc side="top">io.outpad io.inpad</loc>
+        <loc side="right">io.outpad io.inpad</loc>
+        <loc side="bottom">io.outpad io.inpad</loc>
+      </pinlocations>
+    </tile>
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
+      </fc>
+      <!--  Highly recommand to customize pin location when direct connection is used!!! -->
+      <!--pinlocations pattern="spread"/-->
+      <pinlocations pattern="custom">
+        <loc side="left">clb.clk</loc>
+        <loc side="top">clb.cin</loc>
+        <loc side="right">clb.O[9:0] clb.I[19:0]</loc>
+        <loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
+      </pinlocations>
+    </tile>
+    <tile name="memory" height="2" area="548000">
+      <equivalent_sites>
+        <site pb_type="memory"/>
+      </equivalent_sites>
+      <input name="waddr" num_pins="10"/>
+      <input name="raddr" num_pins="10"/>
+      <input name="d_in" num_pins="32"/>
+      <input name="wen" num_pins="1"/>
+      <input name="ren" num_pins="1"/>
+      <output name="d_out" num_pins="32"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="spread"/>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout tileable="false">
+    <!--auto_layout aspect_ratio="1.0"-->
+    <fixed_layout name="4x4" width="5" height="4">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
+      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
+    </fixed_layout>
+    <!-- /auto_layout -->
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	    -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+           book area formula. This means the mux transistors are about 5x minimum drive strength.
+           We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+           mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+           the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+           by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+           buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+           I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+           (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+           The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+           2.5x when looking up in Jeff's tables.
+           Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+           This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+             With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+             reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <directlist>
+    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
+  </directlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+
+      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+           If you need to register the I/O, define clocks in the circuit models
+           These clocks can be handled in back-end
+       -->
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" disabled_in_pack="true">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe fracturable logic element.  
+             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
+             The outputs of the fracturable logic element can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="10">
+        <input name="in" num_pins="6"/>
+        <input name="cin" num_pins="1"/>
+        <output name="out" num_pins="2"/>
+        <output name="cout" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- Physical mode definition begin (physical implementation of the fle) -->
+        <mode name="physical" disabled_in_pack="true">
+          <pb_type name="fabric" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="frac_logic" num_pb="1">
+              <input name="in" num_pins="6"/>
+              <output name="lut4_out" num_pins="4"/>
+              <output name="out" num_pins="2"/>
+              <!-- Define LUT -->
+              <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
+                <input name="in" num_pins="6"/>
+                <output name="lut4_out" num_pins="4"/>
+                <output name="lut5_out" num_pins="2"/>
+                <output name="lut6_out" num_pins="1"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
+                <direct name="direct2" input="frac_lut6.lut4_out" output="frac_logic.lut4_out"/>
+                <direct name="direct3" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
+                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
+                <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
+              </interconnect>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>         
+            <!-- Define adders -->
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="2">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
+              <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
+              <direct name="direct3" input="fabric.cin" output="adder[0:0].cin"/>
+              <direct name="direct4" input="adder[0:0].cout" output="adder[1:1].cin"/>
+              <direct name="direct5" input="adder[1:1].cout" output="fabric.cout"/>
+              <direct name="direct6" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
+              <direct name="direct7" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
+              <direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
+              <direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
+              <complete name="direct10" input="fabric.clk" output="ff[1:0].clk"/>
+              <mux name="mux1" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
+                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
+              </mux>
+              <mux name="mux2" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
+                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="fabric.in"/>
+            <direct name="direct2" input="fle.cin" output="fabric.cin"/>
+            <direct name="direct3" input="fabric.out" output="fle.out"/>
+            <direct name="direct4" input="fabric.cout" output="fle.cout"/>
+            <direct name="direct5" input="fle.clk" output="fabric.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Physical mode definition end (physical implementation of the fle) -->
+        <!-- BEGIN fle mode of dual lut5 -->
+        <mode name="n2_lut5">
+          <pb_type name="ble5" num_pb="2">
+            <input name="in" num_pins="5"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Regular LUT mode -->
+            <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="5" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                  we instead take the average of these numbers to get more stable results
+                82e-12
+                173e-12
+                261e-12
+                263e-12
+                398e-12
+                -->
+              <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+              </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble5.in" output="lut5.in"/>
+              <direct name="direct2" input="lut5.out" output="ff.D">
+                <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble5.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut5.out" output="ble5.out">
+                <delay_constant max="25e-12" in_port="lut5.out" out_port="ble5.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble5.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[4:0]" output="ble5[0:0].in"/>
+            <direct name="direct2" input="fle.in[4:0]" output="ble5[1:1].in"/>
+            <complete name="direct3" input="fle.clk" output="ble5.clk"/>
+            <direct name="direct4" input="ble5.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- END fle mode of dual lut5 -->
+        <!-- BEGIN arithmetic mode of dual lut4 + adders -->
+        <mode name="arithmetic">
+          <pb_type name="arithmetic" num_pb="2">
+            <input name="in" num_pins="4"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="1"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Special dual-LUT mode that drives adder only -->
+            <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
+              <input name="in" num_pins="4" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  -->
+              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                  195e-12
+                  195e-12
+                  195e-12
+                  195e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
+              <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
+              <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
+              <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
+                </direct>
+              <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
+                </direct>
+              <direct name="add_to_ff" input="adder.sumout" output="ff.D">
+                <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
+              </direct>
+              <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
+                <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
+              </direct>
+              <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
+                <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
+              </direct>
+              <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
+                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[3:0]" output="arithmetic[0:0].in"/>
+            <direct name="direct2" input="fle.in[3:0]" output="arithmetic[1:1].in"/>
+            <direct name="carry_in" input="fle.cin" output="arithmetic[0:0].cin">
+              <pack_pattern name="chain" in_port="fle.cin" out_port="arithmetic[0:0].cin"/>
+            </direct>
+            <direct name="carry_inter" input="arithmetic[0:0].cout" output="arithmetic[1:1].cin">
+              <pack_pattern name="chain" in_port="arithmetic[0:0].cout" out_port="arithmetic[1:1].cin"/>
+            </direct>
+            <direct name="carry_out" input="arithmetic[1:1].cout" output="fle.cout">
+              <pack_pattern name="chain" in_port="arithmetic.cout" out_port="fle.cout"/>
+            </direct>
+            <complete name="direct3" input="fle.clk" output="arithmetic.clk"/>
+            <direct name="direct4" input="arithmetic.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- n2_lut5 -->
+        <mode name="n1_lut6">
+          <pb_type name="ble6" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="6" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->
+              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+              <direct name="direct2" input="lut6.out" output="ff.D">
+                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
+            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+          </interconnect>
+        </mode>
+        <!-- n1_lut6 -->
+      </pb_type>
+      <interconnect>
+        <!-- We use a 50% depop crossbar built using small full xbars to get sets of logically equivalent pins at inputs of CLB 
+           The delays below come from Stratix IV. the delay through a connection block
+           input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+           delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+           delay within the crossbar is 95 ps. 
+           The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+           Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+           25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+           to get the part that should be marked on the crossbar.	 -->
+        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
+          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
+          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
+        </complete>
+
+        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+        </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+                 By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+                 then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+                 naive specification).
+          -->
+        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
+        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
+        <!-- Carry chain links -->
+        <direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
+          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
+        </direct>
+        <direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
+          <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
+        </direct>
+        <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
+          <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
+        </direct>
+      </interconnect>
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+    <!-- Define single-mode dual-port memory begin -->
+    <pb_type name="memory">
+      <input name="waddr" num_pins="10"/>
+      <input name="raddr" num_pins="10"/>
+      <input name="d_in" num_pins="32"/>
+      <input name="wen" num_pins="1"/>
+      <input name="ren" num_pins="1"/>
+      <output name="d_out" num_pins="32"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Specify the 512x32=16Kbit memory block
+           Note: the delay numbers are extracted from VPR flagship XML without modification
+                 Should align to the process technology we using to create the 16K dual-port RAM
+        -->
+      <mode name="mem_512x32_dp">
+        <pb_type name="mem_512x32_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
+          <input name="waddr" num_pins="10" port_class="address"/>
+          <input name="raddr" num_pins="10" port_class="address"/>
+          <input name="d_in" num_pins="32" port_class="data_in"/>
+          <input name="wen" num_pins="1" port_class="write_en"/>
+          <input name="ren" num_pins="1" port_class="write_en"/>
+          <output name="d_out" num_pins="32" port_class="data_out"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.waddr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.raddr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.d_in" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.wen" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.ren" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_512x32_dp.d_out" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="17.9e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="waddress" input="memory.waddr" output="mem_512x32_dp.waddr">
+            <delay_constant max="132e-12" in_port="memory.waddr" out_port="mem_512x32_dp.waddr"/>
+          </direct>
+          <direct name="raddress" input="memory.raddr" output="mem_512x32_dp.raddr">
+            <delay_constant max="132e-12" in_port="memory.raddr" out_port="mem_512x32_dp.raddr"/>
+          </direct>
+          <direct name="data_input" input="memory.d_in" output="mem_512x32_dp.d_in">
+            <delay_constant max="132e-12" in_port="memory.d_in" out_port="mem_512x32_dp.d_in"/>
+          </direct>
+          <direct name="writeen" input="memory.wen" output="mem_512x32_dp.wen">
+            <delay_constant max="132e-12" in_port="memory.wen" out_port="mem_512x32_dp.wen"/>
+          </direct>
+          <direct name="readen" input="memory.ren" output="mem_512x32_dp.ren">
+            <delay_constant max="132e-12" in_port="memory.ren" out_port="mem_512x32_dp.ren"/>
+          </direct>
+          <direct name="dataout" input="mem_512x32_dp.d_out" output="memory.d_out">
+            <delay_constant max="40e-12" in_port="mem_512x32_dp.d_out" out_port="memory.d_out"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_512x32_dp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+    </pb_type>
+    <!-- Define single-mode dual-port memory end -->
+  </complexblocklist>
+</architecture>

From 8a996ceae514e2b4add1c9308f15e9bd39a8c29a Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 24 Mar 2020 13:02:35 -0600
Subject: [PATCH 338/645] bug fixed in tileable routing when heterogeneous
 blocks are considered; VPR have special rules in checking the coordinates of
 SOURCE and SINK nodes, which is very different from the OPIN and IPIN nodes
 Show respect to it here.

---
 .../test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml | 2 +-
 .../tileable_rr_graph/tileable_rr_graph_node_builder.cpp  | 8 ++++----
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml
index 850eb5450..87e6ff937 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml
@@ -193,7 +193,7 @@
   </tiles>
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
-  <layout tileable="false">
+  <layout tileable="tileable">
     <!--auto_layout aspect_ratio="1.0"-->
     <fixed_layout name="4x4" width="5" height="4">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp
index 7191bc523..da77d536e 100644
--- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp
+++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp
@@ -492,8 +492,8 @@ void load_one_grid_source_nodes_basic_info(RRGraph& rr_graph,
     /* node bounding box */
     rr_graph.set_node_bounding_box(node, vtr::Rect<short>(grid_coordinate.x(),
                                                           grid_coordinate.y(),
-                                                          grid_coordinate.x(),
-                                                          grid_coordinate.y()));
+                                                          grid_coordinate.x() + cur_grid.type->width - 1,
+                                                          grid_coordinate.y() + cur_grid.type->height - 1));
     rr_graph.set_node_class_num(node, iclass);  
 
     rr_graph.set_node_capacity(node, 1);
@@ -543,8 +543,8 @@ void load_one_grid_sink_nodes_basic_info(RRGraph& rr_graph,
     /* node bounding box */
     rr_graph.set_node_bounding_box(node, vtr::Rect<short>(grid_coordinate.x(),
                                                           grid_coordinate.y(),
-                                                          grid_coordinate.x(),
-                                                          grid_coordinate.y()));
+                                                          grid_coordinate.x() + cur_grid.type->width - 1,
+                                                          grid_coordinate.y() + cur_grid.type->height - 1));
     rr_graph.set_node_class_num(node, iclass);  
 
     rr_graph.set_node_capacity(node, 1);

From 610c71671fabd9dd1fef1bb01250a01274a83e57 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 24 Mar 2020 16:47:45 -0600
Subject: [PATCH 339/645] experimentally developing through channels inside
 multi-width and multi-height grids. Still debugging.

---
 libs/libarchfpga/src/physical_types.h         |   2 +
 libs/libarchfpga/src/read_xml_arch_file.cpp   |   3 +-
 .../k6_frac_N10_adder_chain_mem16K_40nm.xml   |   2 +-
 vpr/src/base/SetupVPR.cpp                     |   1 +
 vpr/src/base/place_and_route.cpp              |   3 +-
 vpr/src/base/vpr_api.cpp                      |   3 +-
 vpr/src/base/vpr_types.h                      |   1 +
 vpr/src/route/route_common.cpp                |   3 +-
 vpr/src/route/rr_graph.cpp                    |   1 +
 .../rr_graph_builder_utils.cpp                |  53 +++---
 .../rr_graph_builder_utils.h                  |  12 +-
 .../tileable_rr_graph_builder.cpp             |   7 +-
 .../tileable_rr_graph_builder.h               |   1 +
 .../tileable_rr_graph_node_builder.cpp        | 160 ++++++++++++------
 .../tileable_rr_graph_node_builder.h          |   6 +-
 15 files changed, 170 insertions(+), 88 deletions(-)

diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h
index d1cfae62a..f5f2c3c7e 100644
--- a/libs/libarchfpga/src/physical_types.h
+++ b/libs/libarchfpga/src/physical_types.h
@@ -1590,7 +1590,9 @@ struct t_clock_arch_spec {
 struct t_arch {
     char* architecture_id; //Secure hash digest of the architecture file to uniquely identify this architecture
     
+    /* Xifan Tang: options for tileable routing architectures */
     bool tileable;
+    bool through_channel;
 
     t_chan_width_dist Chans;
     enum e_switch_block_type SBType;
diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp
index cf7c97133..cabb17bbb 100644
--- a/libs/libarchfpga/src/read_xml_arch_file.cpp
+++ b/libs/libarchfpga/src/read_xml_arch_file.cpp
@@ -2536,7 +2536,8 @@ static void ProcessLayout(pugi::xml_node layout_tag, t_arch* arch, const pugiuti
     //Expect only tileable attributes on <layout>
     //expect_only_attributes(layout_tag, {"tileable"}, loc_data);
 
-    arch->tileable = get_attribute(layout_tag, "tileable", loc_data).as_bool(false);
+    arch->tileable = get_attribute(layout_tag, "tileable", loc_data, ReqOpt::OPTIONAL).as_bool(false);
+    arch->through_channel = get_attribute(layout_tag, "through_channel", loc_data, ReqOpt::OPTIONAL).as_bool(false);
 
     //Count the number of <auto_layout> or <fixed_layout> tags
     size_t auto_layout_cnt = 0;
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml
index 87e6ff937..9422c3a09 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml
@@ -193,7 +193,7 @@
   </tiles>
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
-  <layout tileable="tileable">
+  <layout tileable="true" through_channel="false">
     <!--auto_layout aspect_ratio="1.0"-->
     <fixed_layout name="4x4" width="5" height="4">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp
index a43f5b80a..8e806d515 100644
--- a/vpr/src/base/SetupVPR.cpp
+++ b/vpr/src/base/SetupVPR.cpp
@@ -324,6 +324,7 @@ static void SetupRoutingArch(const t_arch& Arch,
 
     /* Copy the tileable routing setting */
     RoutingArch->tileable = Arch.tileable;
+    RoutingArch->through_channel = Arch.through_channel;
 }
 
 static void SetupRouterOpts(const t_options& Options, t_router_opts* RouterOpts) {
diff --git a/vpr/src/base/place_and_route.cpp b/vpr/src/base/place_and_route.cpp
index c13a1e393..2d5946ad5 100644
--- a/vpr/src/base/place_and_route.cpp
+++ b/vpr/src/base/place_and_route.cpp
@@ -359,7 +359,8 @@ int binary_search_place_and_route(const t_placer_opts& placer_opts_ref,
                     segment_inf,
                     router_opts.base_cost_type,
                     router_opts.trim_empty_channels,
-                    router_opts.trim_obs_channels,
+                    /* Xifan tang: The trimming on obstacle(through) channel inside multi-height and multi-width grids are not open to command-line options. OpenFPGA opens this options through an XML syntax */
+                    router_opts.trim_obs_channels || det_routing_arch->through_channel,
                     router_opts.clock_modeling,
                     arch->Directs, arch->num_directs,
                     &warnings);
diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp
index 16a6cc708..846c0779a 100644
--- a/vpr/src/base/vpr_api.cpp
+++ b/vpr/src/base/vpr_api.cpp
@@ -851,7 +851,8 @@ void vpr_create_rr_graph(t_vpr_setup& vpr_setup, const t_arch& arch, int chan_wi
                     vpr_setup.Segments,
                     router_opts.base_cost_type,
                     router_opts.trim_empty_channels,
-                    router_opts.trim_obs_channels,
+                    /* Xifan tang: The trimming on obstacle(through) channel inside multi-height and multi-width grids are not open to command-line options. OpenFPGA opens this options through an XML syntax */
+                    router_opts.trim_obs_channels || det_routing_arch->through_channel,
                     router_opts.clock_modeling,
                     arch.Directs, arch.num_directs,
                     &warnings);
diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h
index 8d03979fd..f6696dd9f 100644
--- a/vpr/src/base/vpr_types.h
+++ b/vpr/src/base/vpr_types.h
@@ -1012,6 +1012,7 @@ struct t_det_routing_arch {
     
     /* Xifan Tang: tileable routing */
     bool tileable;
+    bool through_channel;
 
     short global_route_switch;
     short delayless_switch;
diff --git a/vpr/src/route/route_common.cpp b/vpr/src/route/route_common.cpp
index 5ef55df61..4e1cda2ae 100644
--- a/vpr/src/route/route_common.cpp
+++ b/vpr/src/route/route_common.cpp
@@ -236,7 +236,8 @@ void try_graph(int width_fac, const t_router_opts& router_opts, t_det_routing_ar
                     segment_inf,
                     router_opts.base_cost_type,
                     router_opts.trim_empty_channels,
-                    router_opts.trim_obs_channels,
+                    /* Xifan tang: The trimming on obstacle(through) channel inside multi-height and multi-width grids are not open to command-line options. OpenFPGA opens this options through an XML syntax */
+                    router_opts.trim_obs_channels || det_routing_arch->through_channel,
                     router_opts.clock_modeling,
                     directs, num_directs,
                     &warning_count);
diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp
index ebd45d7b0..3c8f2ea25 100644
--- a/vpr/src/route/rr_graph.cpp
+++ b/vpr/src/route/rr_graph.cpp
@@ -366,6 +366,7 @@ void create_rr_graph(const t_graph_type graph_type,
                                                     base_cost_type,
                                                     directs, num_directs,
                                                     &det_routing_arch->wire_to_rr_ipin_switch,
+                                                    trim_obs_channels, /* Allow/Prohibit through tracks across multi-height and multi-width grids */
                                                     false, /* Do not allow passing tracks to be wired to the same routing channels */
                                                     Warnings);
         }
diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp
index 6ec00466b..acead971f 100644
--- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp
+++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp
@@ -212,7 +212,8 @@ bool is_chany_exist(const DeviceGrid& grids,
  *     +-----------------+
  ***********************************************************************/
 bool is_chanx_right_to_multi_height_grid(const DeviceGrid& grids,
-                                         const vtr::Point<size_t>& chanx_coord) {
+                                         const vtr::Point<size_t>& chanx_coord,
+                                         const bool& through_channel) {
   VTR_ASSERT(0 < chanx_coord.x());
   if (1 == chanx_coord.x()) {
     /* This is already the LEFT side of FPGA fabric,
@@ -221,10 +222,12 @@ bool is_chanx_right_to_multi_height_grid(const DeviceGrid& grids,
     return true;
   }
   
-  /* We check the left neighbor of chanx, if it does not exist, the chanx is left to a multi-height grid */
-  vtr::Point<size_t> left_chanx_coord(chanx_coord.x() - 1, chanx_coord.y());
-  if (false == is_chanx_exist(grids, left_chanx_coord)) {
-    return true;
+  if (false == through_channel) {
+    /* We check the left neighbor of chanx, if it does not exist, the chanx is left to a multi-height grid */
+    vtr::Point<size_t> left_chanx_coord(chanx_coord.x() - 1, chanx_coord.y());
+    if (false == is_chanx_exist(grids, left_chanx_coord)) {
+      return true;
+    }
   }
 
   return false;
@@ -244,7 +247,8 @@ bool is_chanx_right_to_multi_height_grid(const DeviceGrid& grids,
  *                            +-----------------+
  ***********************************************************************/
 bool is_chanx_left_to_multi_height_grid(const DeviceGrid& grids,
-                                        const vtr::Point<size_t>& chanx_coord) {
+                                        const vtr::Point<size_t>& chanx_coord,
+                                        const bool& through_channel) {
   VTR_ASSERT(chanx_coord.x() < grids.width() - 1);
   if (grids.width() - 2 == chanx_coord.x()) {
     /* This is already the RIGHT side of FPGA fabric,
@@ -253,10 +257,13 @@ bool is_chanx_left_to_multi_height_grid(const DeviceGrid& grids,
     return true;
   }
   
-  /* We check the right neighbor of chanx, if it does not exist, the chanx is left to a multi-height grid */
-  vtr::Point<size_t> right_chanx_coord(chanx_coord.x() + 1, chanx_coord.y());
-  if (false == is_chanx_exist(grids, right_chanx_coord)) {
-    return true;
+
+  if (false == through_channel) {
+    /* We check the right neighbor of chanx, if it does not exist, the chanx is left to a multi-height grid */
+    vtr::Point<size_t> right_chanx_coord(chanx_coord.x() + 1, chanx_coord.y());
+    if (false == is_chanx_exist(grids, right_chanx_coord)) {
+      return true;
+    }
   }
 
   return false;
@@ -281,7 +288,8 @@ bool is_chanx_left_to_multi_height_grid(const DeviceGrid& grids,
  *     +-----------------+
  ***********************************************************************/
 bool is_chany_top_to_multi_width_grid(const DeviceGrid& grids,
-                                      const vtr::Point<size_t>& chany_coord) {
+                                      const vtr::Point<size_t>& chany_coord,
+                                      const bool& through_channel) {
   VTR_ASSERT(0 < chany_coord.y());
   if (1 == chany_coord.y()) {
     /* This is already the BOTTOM side of FPGA fabric,
@@ -290,10 +298,12 @@ bool is_chany_top_to_multi_width_grid(const DeviceGrid& grids,
     return true;
   }
   
-  /* We check the bottom neighbor of chany, if it does not exist, the chany is left to a multi-height grid */
-  vtr::Point<size_t> bottom_chany_coord(chany_coord.x(), chany_coord.y() - 1);
-  if (false == is_chany_exist(grids, bottom_chany_coord)) {
-    return true;
+  if (false == through_channel) {
+    /* We check the bottom neighbor of chany, if it does not exist, the chany is left to a multi-height grid */
+    vtr::Point<size_t> bottom_chany_coord(chany_coord.x(), chany_coord.y() - 1);
+    if (false == is_chany_exist(grids, bottom_chany_coord)) {
+      return true;
+    }
   }
 
   return false;
@@ -318,7 +328,8 @@ bool is_chany_top_to_multi_width_grid(const DeviceGrid& grids,
  *
  ***********************************************************************/
 bool is_chany_bottom_to_multi_width_grid(const DeviceGrid& grids,
-                                         const vtr::Point<size_t>& chany_coord) {
+                                         const vtr::Point<size_t>& chany_coord,
+                                         const bool& through_channel) {
   VTR_ASSERT(chany_coord.y() < grids.height() - 1);
   if (grids.height() - 2 == chany_coord.y()) {
     /* This is already the TOP side of FPGA fabric,
@@ -327,10 +338,12 @@ bool is_chany_bottom_to_multi_width_grid(const DeviceGrid& grids,
     return true;
   }
   
-  /* We check the top neighbor of chany, if it does not exist, the chany is left to a multi-height grid */
-  vtr::Point<size_t> top_chany_coord(chany_coord.x(), chany_coord.y() + 1);
-  if (false == is_chany_exist(grids, top_chany_coord)) {
-    return true;
+  if (false == through_channel) {
+    /* We check the top neighbor of chany, if it does not exist, the chany is left to a multi-height grid */
+    vtr::Point<size_t> top_chany_coord(chany_coord.x(), chany_coord.y() + 1);
+    if (false == is_chany_exist(grids, top_chany_coord)) {
+      return true;
+    }
   }
 
   return false;
diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h
index 8a903f97a..23e030d9b 100644
--- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h
+++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h
@@ -46,16 +46,20 @@ bool is_chany_exist(const DeviceGrid& grids,
                     const vtr::Point<size_t>& chany_coord);
 
 bool is_chanx_right_to_multi_height_grid(const DeviceGrid& grids,
-                                         const vtr::Point<size_t>& chanx_coord);
+                                         const vtr::Point<size_t>& chanx_coord,
+                                         const bool& through_channel);
 
 bool is_chanx_left_to_multi_height_grid(const DeviceGrid& grids,
-                                        const vtr::Point<size_t>& chanx_coord);
+                                        const vtr::Point<size_t>& chanx_coord,
+                                        const bool& through_channel);
 
 bool is_chany_top_to_multi_width_grid(const DeviceGrid& grids,
-                                      const vtr::Point<size_t>& chany_coord);
+                                      const vtr::Point<size_t>& chany_coord,
+                                      const bool& through_channel);
 
 bool is_chany_bottom_to_multi_width_grid(const DeviceGrid& grids,
-                                         const vtr::Point<size_t>& chany_coord);
+                                         const vtr::Point<size_t>& chany_coord,
+                                         const bool& through_channel);
 
 short get_rr_node_actual_track_id(const RRGraph& rr_graph,
                                   const RRNodeId& track_rr_node,
diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp
index f103fb545..23ce3b53c 100644
--- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp
+++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp
@@ -83,6 +83,7 @@ void build_tileable_unidir_rr_graph(const std::vector<t_physical_tile_type>& typ
                                     const t_direct_inf *directs, 
                                     const int& num_directs,
                                     int* wire_to_rr_ipin_switch,
+                                    const bool& through_channel,
                                     const bool& wire_opposite_side,
                                     int *Warnings) { 
 
@@ -149,7 +150,8 @@ void build_tileable_unidir_rr_graph(const std::vector<t_physical_tile_type>& typ
                                 rr_node_driver_switches,
                                 grids,
                                 device_chan_width,
-                                segment_inf);
+                                segment_inf,
+                                through_channel);
 
   /************************
    * Create all the rr_nodes 
@@ -161,7 +163,8 @@ void build_tileable_unidir_rr_graph(const std::vector<t_physical_tile_type>& typ
                                  device_chan_width,
                                  segment_inf,
                                  wire_to_ipin_rr_switch,
-                                 delayless_rr_switch); 
+                                 delayless_rr_switch,
+                                 through_channel);
 
   /************************************************************************
    * Create the connectivity of OPINs
diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h
index 601c7de18..46be3817d 100644
--- a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h
+++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h
@@ -30,6 +30,7 @@ void build_tileable_unidir_rr_graph(const std::vector<t_physical_tile_type>& typ
                                     const t_direct_inf *directs, 
                                     const int& num_directs,
                                     int* wire_to_rr_ipin_switch,
+                                    const bool& through_channel,
                                     const bool& wire_opposite_side,
                                     int *Warnings); 
 
diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp
index da77d536e..753c455ff 100644
--- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp
+++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp
@@ -177,26 +177,27 @@ size_t estimate_num_grid_rr_nodes_by_type(const DeviceGrid& grids,
 static 
 size_t estimate_num_chanx_rr_nodes(const DeviceGrid& grids,
                                    const size_t& chan_width,
-                                   const std::vector<t_segment_inf>& segment_infs) {
+                                   const std::vector<t_segment_inf>& segment_infs,
+                                   const bool& through_channel) {
   size_t num_chanx_rr_nodes = 0;
 
   for (size_t iy = 0; iy < grids.height() - 1; ++iy) { 
     for (size_t ix = 1; ix < grids.width() - 1; ++ix) {
       vtr::Point<size_t> chanx_coord(ix, iy);
 
-      /* Bypass if the routing channel does not exist */
+      /* Bypass if the routing channel does not exist when through channels are not allowed */
       if (false == is_chanx_exist(grids, chanx_coord)) {
         continue;
       }
 
       bool force_start = false;
       bool force_end = false;
-
+ 
       /* All the tracks have to start when 
        *  - the routing channel touch the RIGHT side a heterogeneous block
        *  - the routing channel touch the LEFT side of FPGA
        */
-      if (true == is_chanx_right_to_multi_height_grid(grids, chanx_coord)) {
+      if (true == is_chanx_right_to_multi_height_grid(grids, chanx_coord, through_channel)) {
         force_start = true;
       }
 
@@ -204,7 +205,7 @@ size_t estimate_num_chanx_rr_nodes(const DeviceGrid& grids,
        *  - the routing channel touch the LEFT side a heterogeneous block
        *  - the routing channel touch the RIGHT side of FPGA
        */
-      if (true == is_chanx_left_to_multi_height_grid(grids, chanx_coord)) {
+      if (true == is_chanx_left_to_multi_height_grid(grids, chanx_coord, through_channel)) {
         force_end = true;
       }
     
@@ -228,14 +229,15 @@ size_t estimate_num_chanx_rr_nodes(const DeviceGrid& grids,
 static 
 size_t estimate_num_chany_rr_nodes(const DeviceGrid& grids,
                                    const size_t& chan_width,
-                                   const std::vector<t_segment_inf>& segment_infs) {
+                                   const std::vector<t_segment_inf>& segment_infs,
+                                   const bool& through_channel) {
   size_t num_chany_rr_nodes = 0;
 
   for (size_t ix = 0; ix < grids.width() - 1; ++ix) {
     for (size_t iy = 1; iy < grids.height() - 1; ++iy) { 
       vtr::Point<size_t> chany_coord(ix, iy);
 
-      /* Bypass if the routing channel does not exist */
+      /* Bypass if the routing channel does not exist when through channels are not allowed */
       if (false == is_chany_exist(grids, chany_coord)) {
         continue;
       }
@@ -247,7 +249,7 @@ size_t estimate_num_chany_rr_nodes(const DeviceGrid& grids,
        *  - the routing channel touch the TOP side a heterogeneous block
        *  - the routing channel touch the BOTTOM side of FPGA
        */
-      if (true == is_chany_top_to_multi_width_grid(grids, chany_coord)) {
+      if (true == is_chany_top_to_multi_width_grid(grids, chany_coord, through_channel)) {
         force_start = true;
       }
 
@@ -255,7 +257,7 @@ size_t estimate_num_chany_rr_nodes(const DeviceGrid& grids,
        *  - the routing channel touch the BOTTOM side a heterogeneous block
        *  - the routing channel touch the TOP side of FPGA
        */
-      if (true == is_chany_bottom_to_multi_width_grid(grids, chany_coord)) {
+      if (true == is_chany_bottom_to_multi_width_grid(grids, chany_coord, through_channel)) {
         force_end = true;
       }
 
@@ -276,7 +278,8 @@ size_t estimate_num_chany_rr_nodes(const DeviceGrid& grids,
 static 
 std::vector<size_t> estimate_num_rr_nodes(const DeviceGrid& grids,
                                           const vtr::Point<size_t>& chan_width,
-                                          const std::vector<t_segment_inf>& segment_infs) {
+                                          const std::vector<t_segment_inf>& segment_infs,
+                                          const bool& through_channel) {
 
   /* Reset the OPIN, IPIN, SOURCE, SINK counter to be zero */
   std::vector<size_t> num_rr_nodes_per_type(NUM_RR_TYPES, 0);
@@ -304,8 +307,14 @@ std::vector<size_t> estimate_num_rr_nodes(const DeviceGrid& grids,
    *    in X-direction and Y-direction channels!!!
    *    So we will load segment details for different channels 
    */
-  num_rr_nodes_per_type[CHANX] = estimate_num_chanx_rr_nodes(grids, chan_width.x(), segment_infs);
-  num_rr_nodes_per_type[CHANY] = estimate_num_chany_rr_nodes(grids, chan_width.y(), segment_infs);
+  num_rr_nodes_per_type[CHANX] = estimate_num_chanx_rr_nodes(grids,
+                                                             chan_width.x(),
+                                                             segment_infs,
+                                                             through_channel);
+  num_rr_nodes_per_type[CHANY] = estimate_num_chany_rr_nodes(grids,
+                                                             chan_width.y(),
+                                                             segment_infs,
+                                                             through_channel);
 
   return num_rr_nodes_per_type;
 }
@@ -321,10 +330,14 @@ void alloc_tileable_rr_graph_nodes(RRGraph& rr_graph,
                                    vtr::vector<RRNodeId, RRSwitchId>& rr_node_driver_switches, 
                                    const DeviceGrid& grids,
                                    const vtr::Point<size_t>& chan_width,
-                                   const std::vector<t_segment_inf>& segment_infs) {
+                                   const std::vector<t_segment_inf>& segment_infs,
+                                   const bool& through_channel) {
   VTR_ASSERT(0 == rr_graph.nodes().size());
 
-  std::vector<size_t> num_rr_nodes_per_type = estimate_num_rr_nodes(grids, chan_width, segment_infs);
+  std::vector<size_t> num_rr_nodes_per_type = estimate_num_rr_nodes(grids,
+                                                                    chan_width,
+                                                                    segment_infs,
+                                                                    through_channel);
 
   /* Reserve the number of node to be memory efficient */  
   size_t num_nodes = 0;
@@ -764,7 +777,8 @@ void load_chanx_rr_nodes_basic_info(RRGraph& rr_graph,
                                     std::map<RRNodeId, std::vector<size_t>>& rr_node_track_ids,
                                     const DeviceGrid& grids,
                                     const size_t& chan_width,
-                                    const std::vector<t_segment_inf>& segment_infs) {
+                                    const std::vector<t_segment_inf>& segment_infs,
+                                    const bool& through_channel) {
 
   /* For X-direction Channel: CHANX */
   for (size_t iy = 0; iy < grids.height() - 1; ++iy) { 
@@ -774,8 +788,9 @@ void load_chanx_rr_nodes_basic_info(RRGraph& rr_graph,
     for (size_t ix = 1; ix < grids.width() - 1; ++ix) {
       vtr::Point<size_t> chanx_coord(ix, iy);
 
-      /* Bypass if the routing channel does not exist */
-      if (false == is_chanx_exist(grids, chanx_coord)) {
+      /* Bypass if the routing channel does not exist when through channels are not allowed */
+      if ( (false == through_channel)
+        && (false == is_chanx_exist(grids, chanx_coord))) {
         continue;
       }
 
@@ -786,7 +801,7 @@ void load_chanx_rr_nodes_basic_info(RRGraph& rr_graph,
        *  - the routing channel touch the RIGHT side a heterogeneous block
        *  - the routing channel touch the LEFT side of FPGA
        */
-      if (true == is_chanx_right_to_multi_height_grid(grids, chanx_coord)) {
+      if (true == is_chanx_right_to_multi_height_grid(grids, chanx_coord, through_channel)) {
         force_start = true;
       }
 
@@ -794,7 +809,7 @@ void load_chanx_rr_nodes_basic_info(RRGraph& rr_graph,
        *  - the routing channel touch the LEFT side a heterogeneous block
        *  - the routing channel touch the RIGHT side of FPGA
        */
-      if (true == is_chanx_left_to_multi_height_grid(grids, chanx_coord)) {
+      if (true == is_chanx_left_to_multi_height_grid(grids, chanx_coord, through_channel)) {
         force_end = true;
       }
 
@@ -810,21 +825,35 @@ void load_chanx_rr_nodes_basic_info(RRGraph& rr_graph,
                                                                           false, false, segment_infs); 
         chanx_details_tt.set_track_node_ids(track_node_ids);
 
-        /* Rotate the chanx_details by an offset of ix - 1, the distance to the most left channel */
-        /* For INC_DIRECTION, we use clockwise rotation 
-         * node_id A ---->   -----> node_id D
-         * node_id B ---->  / ----> node_id A
-         * node_id C ----> /  ----> node_id B
-         * node_id D ---->    ----> node_id C 
+        /* TODO:
+         * Do NOT rotate the tracks when the routing channel 
+         * locates inside a multi-height and multi-width grid
+         * Let the routing channel passing through the grid (if through channel is allowed!) 
+         * An example:
+         *      
+         *               +------------------------------
+         *               |                             |
+         *               |          Grid               |
+         *  track0 ----->+-----------------------------+----> track0
+         *               |                             |
          */
-        chanx_details_tt.rotate_track_node_id(1, INC_DIRECTION, true);
-        /* For DEC_DIRECTION, we use clockwise rotation 
-         * node_id A <-----    <----- node_id B
-         * node_id B <----- \  <----- node_id C
-         * node_id C <-----  \ <----- node_id D
-         * node_id D <-----    <----- node_id A 
-         */
-        chanx_details_tt.rotate_track_node_id(1, DEC_DIRECTION, false);
+        if (true == is_chanx_exist(grids, chanx_coord)) {
+          /* Rotate the chanx_details by an offset of ix - 1, the distance to the most left channel */
+          /* For INC_DIRECTION, we use clockwise rotation 
+           * node_id A ---->   -----> node_id D
+           * node_id B ---->  / ----> node_id A
+           * node_id C ----> /  ----> node_id B
+           * node_id D ---->    ----> node_id C 
+           */
+          chanx_details_tt.rotate_track_node_id(1, INC_DIRECTION, true);
+          /* For DEC_DIRECTION, we use clockwise rotation 
+           * node_id A <-----    <----- node_id B
+           * node_id B <----- \  <----- node_id C
+           * node_id C <-----  \ <----- node_id D
+           * node_id D <-----    <----- node_id A 
+           */
+          chanx_details_tt.rotate_track_node_id(1, DEC_DIRECTION, false);
+        }     
 
         track_node_ids = chanx_details_tt.get_track_node_ids();
         chanx_details.set_track_node_ids(track_node_ids);
@@ -855,7 +884,8 @@ void load_chany_rr_nodes_basic_info(RRGraph& rr_graph,
                                     std::map<RRNodeId, std::vector<size_t>>& rr_node_track_ids,
                                     const DeviceGrid& grids,
                                     const size_t& chan_width,
-                                    const std::vector<t_segment_inf>& segment_infs) {
+                                    const std::vector<t_segment_inf>& segment_infs,
+                                    const bool& through_channel) {
 
   /* For Y-direction Channel: CHANY */
   for (size_t ix = 0; ix < grids.width() - 1; ++ix) {
@@ -865,8 +895,9 @@ void load_chany_rr_nodes_basic_info(RRGraph& rr_graph,
     for (size_t iy = 1; iy < grids.height() - 1; ++iy) { 
       vtr::Point<size_t> chany_coord(ix, iy);
 
-      /* Bypass if the routing channel does not exist */
-      if (false == is_chany_exist(grids, chany_coord)) {
+      /* Bypass if the routing channel does not exist when through channel are not allowed */
+      if ( (false == through_channel)
+        && (false == is_chany_exist(grids, chany_coord))) {
         continue;
       }
 
@@ -877,7 +908,7 @@ void load_chany_rr_nodes_basic_info(RRGraph& rr_graph,
        *  - the routing channel touch the TOP side a heterogeneous block
        *  - the routing channel touch the BOTTOM side of FPGA
        */
-      if (true == is_chany_top_to_multi_width_grid(grids, chany_coord)) {
+      if (true == is_chany_top_to_multi_width_grid(grids, chany_coord, through_channel)) {
         force_start = true;
       }
 
@@ -885,7 +916,7 @@ void load_chany_rr_nodes_basic_info(RRGraph& rr_graph,
        *  - the routing channel touch the BOTTOM side a heterogeneous block
        *  - the routing channel touch the TOP side of FPGA
        */
-      if (true == is_chany_bottom_to_multi_width_grid(grids, chany_coord)) {
+      if (true == is_chany_bottom_to_multi_width_grid(grids, chany_coord, through_channel)) {
         force_end = true;
       }
 
@@ -901,21 +932,37 @@ void load_chany_rr_nodes_basic_info(RRGraph& rr_graph,
                                                                           false, false, segment_infs); 
 
         chany_details_tt.set_track_node_ids(track_node_ids);
-        /* Rotate the chany_details by an offset of 1*/
-        /* For INC_DIRECTION, we use clockwise rotation 
-         * node_id A ---->   -----> node_id D
-         * node_id B ---->  / ----> node_id A
-         * node_id C ----> /  ----> node_id B
-         * node_id D ---->    ----> node_id C 
+
+        /* TODO: 
+         * Do NOT rotate the tracks when the routing channel 
+         * locates inside a multi-height and multi-width grid
+         * Let the routing channel passing through the grid (if through channel is allowed!) 
+         * An example:
+         *      
+         *               +------------------------------
+         *               |                             |
+         *               |          Grid               |
+         *  track0 ----->+-----------------------------+----> track0
+         *               |                             |
+         * we should rotate only once at the bottom side of a grid 
          */
-        chany_details_tt.rotate_track_node_id(1, INC_DIRECTION, true);
-        /* For DEC_DIRECTION, we use clockwise rotation 
-         * node_id A <-----    <----- node_id B
-         * node_id B <----- \  <----- node_id C
-         * node_id C <-----  \ <----- node_id D
-         * node_id D <-----    <----- node_id A 
-         */
-        chany_details_tt.rotate_track_node_id(1, DEC_DIRECTION, false);
+        if (true == is_chany_exist(grids, chany_coord)) {
+          /* Rotate the chany_details by an offset of 1*/
+          /* For INC_DIRECTION, we use clockwise rotation 
+           * node_id A ---->   -----> node_id D
+           * node_id B ---->  / ----> node_id A
+           * node_id C ----> /  ----> node_id B
+           * node_id D ---->    ----> node_id C 
+           */
+          chany_details_tt.rotate_track_node_id(1, INC_DIRECTION, true);
+          /* For DEC_DIRECTION, we use clockwise rotation 
+           * node_id A <-----    <----- node_id B
+           * node_id B <----- \  <----- node_id C
+           * node_id C <-----  \ <----- node_id D
+           * node_id D <-----    <----- node_id A 
+           */
+          chany_details_tt.rotate_track_node_id(1, DEC_DIRECTION, false);
+        }
 
         track_node_ids = chany_details_tt.get_track_node_ids();
         chany_details.set_track_node_ids(track_node_ids);
@@ -969,7 +1016,8 @@ void create_tileable_rr_graph_nodes(RRGraph& rr_graph,
                                     const vtr::Point<size_t>& chan_width, 
                                     const std::vector<t_segment_inf>& segment_infs,
                                     const RRSwitchId& wire_to_ipin_switch,
-                                    const RRSwitchId& delayless_switch) {
+                                    const RRSwitchId& delayless_switch,
+                                    const bool& through_channel) {
   load_grid_nodes_basic_info(rr_graph,
                              rr_node_driver_switches, 
                              grids, 
@@ -981,14 +1029,16 @@ void create_tileable_rr_graph_nodes(RRGraph& rr_graph,
                                  rr_node_track_ids, 
                                  grids,
                                  chan_width.x(),
-                                 segment_infs);
+                                 segment_infs,
+                                 through_channel);
 
   load_chany_rr_nodes_basic_info(rr_graph, 
                                  rr_node_driver_switches, 
                                  rr_node_track_ids, 
                                  grids,
                                  chan_width.y(),
-                                 segment_infs);
+                                 segment_infs,
+                                 through_channel);
 
   reverse_dec_chan_rr_node_track_ids(rr_graph, 
                                      rr_node_track_ids);
diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h
index a69cd187c..de8e8f60b 100644
--- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h
+++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h
@@ -25,7 +25,8 @@ void alloc_tileable_rr_graph_nodes(RRGraph& rr_graph,
                                    vtr::vector<RRNodeId, RRSwitchId>& driver_switches, 
                                    const DeviceGrid& grids,
                                    const vtr::Point<size_t>& chan_width,
-                                   const std::vector<t_segment_inf>& segment_infs);
+                                   const std::vector<t_segment_inf>& segment_infs,
+                                   const bool& through_channel);
 
 void create_tileable_rr_graph_nodes(RRGraph& rr_graph,
                                     vtr::vector<RRNodeId, RRSwitchId>& rr_node_driver_switches, 
@@ -34,7 +35,8 @@ void create_tileable_rr_graph_nodes(RRGraph& rr_graph,
                                     const vtr::Point<size_t>& chan_width, 
                                     const std::vector<t_segment_inf>& segment_infs,
                                     const RRSwitchId& wire_to_ipin_switch,
-                                    const RRSwitchId& delayless_switch);
+                                    const RRSwitchId& delayless_switch,
+                                    const bool& through_channel);
 
 
 } /* end namespace openfpga */

From b6bdf78d957b625fbe3ef0b5434201075cc63990 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 24 Mar 2020 17:39:26 -0600
Subject: [PATCH 340/645] bug fixed for heterogeneous block instances in top
 module

---
 .../build_grid_module_duplicated_pins.cpp     |   2 +-
 openfpga/src/fabric/build_top_module.cpp      |  14 +
 .../fabric/build_top_module_connection.cpp    |  11 +
 openfpga/src/utils/pb_type_utils.cpp          |  14 +
 ...c_N10_adder_chain_mem16K_40nm_openfpga.xml | 310 ++++++++++++++++++
 .../and_k6_frac_adder_chain_mem16K.openfpga   |  62 ++++
 6 files changed, 412 insertions(+), 1 deletion(-)
 create mode 100644 openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
 create mode 100644 openfpga/test_script/and_k6_frac_adder_chain_mem16K.openfpga

diff --git a/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp b/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp
index 0f4a86934..e02bae403 100644
--- a/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp
+++ b/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp
@@ -163,7 +163,7 @@ void add_grid_module_net_connect_duplicated_pb_graph_pin(ModuleManager& module_m
   size_t grid_pin_index = pb_graph_pin->pin_count_in_cluster 
                         + child_instance * grid_type_descriptor->num_pins / grid_type_descriptor->capacity;
 
-  int pin_width = grid_type_descriptor->pin_height_offset[grid_pin_index];
+  int pin_width = grid_type_descriptor->pin_width_offset[grid_pin_index];
   int pin_height = grid_type_descriptor->pin_height_offset[grid_pin_index];
   for (const e_side& side : grid_pin_sides) {
     if (true != grid_type_descriptor->pinloc[pin_width][pin_height][side][grid_pin_index]) {
diff --git a/openfpga/src/fabric/build_top_module.cpp b/openfpga/src/fabric/build_top_module.cpp
index 707ff8971..83a4f0147 100644
--- a/openfpga/src/fabric/build_top_module.cpp
+++ b/openfpga/src/fabric/build_top_module.cpp
@@ -105,6 +105,13 @@ vtr::Matrix<size_t> add_top_module_grid_instances(ModuleManager& module_manager,
       /* Skip width or height > 1 tiles (mostly heterogeneous blocks) */
       if ( (0 < grids[ix][iy].width_offset)
         || (0 < grids[ix][iy].height_offset)) {
+        /* Find the root of this grid, the instance id should be valid. 
+         * We just copy it here
+         */
+        vtr::Point<size_t> root_grid_coord(ix - grids[ix][iy].width_offset,
+                                           iy - grids[ix][iy].height_offset);
+        VTR_ASSERT(size_t(-1) != grid_instance_ids[root_grid_coord.x()][root_grid_coord.y()]);
+        grid_instance_ids[ix][iy] = grid_instance_ids[root_grid_coord.x()][root_grid_coord.y()];
         continue;
       }
       /* We should not meet any I/O grid */
@@ -153,6 +160,13 @@ vtr::Matrix<size_t> add_top_module_grid_instances(ModuleManager& module_manager,
       /* Skip width, height > 1 tiles (mostly heterogeneous blocks) */
       if ( (0 < grids[io_coordinate.x()][io_coordinate.y()].width_offset)
         || (0 < grids[io_coordinate.x()][io_coordinate.y()].height_offset)) {
+        /* Find the root of this grid, the instance id should be valid. 
+         * We just copy it here
+         */
+        vtr::Point<size_t> root_grid_coord(io_coordinate.x() - grids[io_coordinate.x()][io_coordinate.y()].width_offset,
+                                           io_coordinate.y() - grids[io_coordinate.x()][io_coordinate.y()].height_offset);
+        VTR_ASSERT(size_t(-1) != grid_instance_ids[root_grid_coord.x()][root_grid_coord.y()]);
+        grid_instance_ids[io_coordinate.x()][io_coordinate.y()] = grid_instance_ids[root_grid_coord.x()][root_grid_coord.y()];
         continue;
       }
       /* We should not meet any I/O grid */
diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp
index 0af6e3409..31163db69 100644
--- a/openfpga/src/fabric/build_top_module_connection.cpp
+++ b/openfpga/src/fabric/build_top_module_connection.cpp
@@ -63,6 +63,11 @@ void add_top_module_nets_connect_grids_and_sb(ModuleManager& module_manager,
                                               const vtr::Matrix<size_t>& sb_instance_ids,
                                               const bool& compact_routing_hierarchy) {
 
+  /* Skip those Switch blocks that do not exist */
+  if (false == rr_gsb.is_sb_exist()) {
+    return;
+  }
+
   /* We could have two different coordinators, one is the instance, the other is the module */
   vtr::Point<size_t> instance_sb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
   vtr::Point<size_t> module_gsb_coordinate(rr_gsb.get_x(), rr_gsb.get_y());
@@ -179,6 +184,11 @@ void add_top_module_nets_connect_grids_and_sb_with_duplicated_pins(ModuleManager
                                                                    const vtr::Matrix<size_t>& sb_instance_ids,
                                                                    const bool& compact_routing_hierarchy) {
 
+  /* Skip those Switch blocks that do not exist */
+  if (false == rr_gsb.is_sb_exist()) {
+    return;
+  }
+
   /* We could have two different coordinators, one is the instance, the other is the module */
   vtr::Point<size_t> instance_sb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
   vtr::Point<size_t> module_gsb_coordinate(rr_gsb.get_x(), rr_gsb.get_y());
@@ -642,6 +652,7 @@ void add_top_module_nets_connect_grids_and_gsbs(ModuleManager& module_manager,
     for (size_t iy = 0; iy < gsb_range.y(); ++iy) {
       vtr::Point<size_t> gsb_coordinate(ix, iy);
       const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
+
       /* Connect the grid pins of the GSB to adjacent grids */
       if (false == duplicate_grid_pin) {
         add_top_module_nets_connect_grids_and_sb(module_manager, top_module, 
diff --git a/openfpga/src/utils/pb_type_utils.cpp b/openfpga/src/utils/pb_type_utils.cpp
index 13d7ccadb..9166a16e8 100644
--- a/openfpga/src/utils/pb_type_utils.cpp
+++ b/openfpga/src/utils/pb_type_utils.cpp
@@ -37,6 +37,20 @@ bool is_primitive_pb_type(t_pb_type* pb_type) {
     VTR_ASSERT( (std::string("wire") == std::string(pb_type->modes[0].name))
              && (std::string(pb_type->name) == std::string(pb_type->modes[1].name)));
     return true;
+  } else if (MEMORY_CLASS == pb_type->class_type) {
+    /* The only primitive memory we recognize is the one which has a mode
+     * either named after 'memory_slice' or 'memory_slice_1bit'
+     * VPR contructed 1 default mode under a regular memory, and these children
+     * are labelled as LUT_CLASS as well. OpenFPGA does not consider
+     * them as primitive as they are for CAD usage only
+     */
+    if (0 == pb_type->num_modes) {
+      return false;
+    }
+    VTR_ASSERT( (std::string("memory_slice") == std::string(pb_type->modes[0].name))
+             || (std::string("memory_slice_1bit") == std::string(pb_type->modes[0].name)));
+    return true;
+
   }
   return 0 == pb_type->num_modes;
 }
diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
new file mode 100644
index 000000000..9f37c1293
--- /dev/null
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
@@ -0,0 +1,310 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
+      <design_technology type="cmos" topology="OR"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <!--mux2to1 subckt_name="mux2to1"/-->
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <!--mux2to1 subckt_name="mux2to1"/-->
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <!--mux2to1 subckt_name="mux2to1"/-->
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <pass_gate_logic circuit_model_name="TGATE"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
+      <design_technology type="cmos" fracturable_lut="true"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="6" tri_state_map="----11" circuit_model_name="OR2"/>
+      <port type="output" prefix="lut4_out" size="4" lut_frac_level="4" lut_output_mask="0,1,2,3"/>
+      <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
+      <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
+      <port type="sram" prefix="sram" size="64"/>
+      <port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <pass_gate_logic circuit_model_name="TGATE"/>
+       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="Qb" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="inout" prefix="pad" size="1"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+      <port type="input" prefix="outpad" size="1"/>
+      <port type="output" prefix="inpad" size="1"/>
+    </circuit_model>
+    <circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="input" prefix="cin" size="1"/>
+      <port type="output" prefix="sumout" size="1"/>
+      <port type="output" prefix="cout" size="1"/>
+    </circuit_model>
+    <circuit_model type="hard_logic" name="dpram_512x32" prefix="dpram_512x32" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dpram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dpsram.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="waddr" size="10"/>
+      <port type="input" prefix="raddr" size="10"/>
+      <port type="input" prefix="d_in" size="32"/>
+      <port type="input" prefix="wen" size="1"/>
+      <port type="input" prefix="ren" size="1"/>
+      <port type="output" prefix="d_out" size="32"/>
+      <port type="clock" prefix="clk" size="1" is_global="true" default_val="0"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <direct_connection>
+    <direct name="adder_carry" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
+  </direct_connection>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle" physical_mode_name="physical"/>
+    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
+    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
+    <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="adder"/>
+    <!-- Binding operating pb_type to physical pb_type -->
+    <!-- Binding operating pb_types in mode 'n2_lut5' -->
+    <pb_type name="clb.fle[n2_lut5].ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5">
+      <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:4]"/>
+      <port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[n2_lut5].ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <!-- Binding operating pb_types in mode 'arithmetic' -->
+    <pb_type name="clb.fle[arithmetic].arithmetic.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="11" physical_pb_type_index_factor="0.25">
+      <!-- Binding the lut4 to the first 4 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:3]"/>
+      <port name="out" physical_mode_port="lut4_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[arithmetic].arithmetic.adder" physical_pb_type_name="clb.fle[physical].fabric.adder"/>
+    <pb_type name="clb.fle[arithmetic].arithmetic.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <!-- Binding operating pb_types in mode 'ble6' -->
+    <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="00">
+      <!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:5]"/>
+      <port name="out" physical_mode_port="lut6_out"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
+    <!-- End physical pb_type binding in complex block clb -->
+
+
+    <!-- physical pb_type binding in complex block memory -->
+    <pb_type name="memory[mem_512x32_dp].mem_512x32_dp" circuit_model_name="dpram_512x32"/>
+    <!-- END physical pb_type binding in complex block memory -->
+  </pb_type_annotations>
+</openfpga_architecture>
+<openfpga_simulation_setting>
+  <clock_setting>
+    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
+    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
+    <programming frequency="10e6"/>
+  </clock_setting>
+  <simulator_option>
+    <operating_condition temperature="25"/>
+    <output_log verbose="false" captab="false"/>
+    <accuracy type="abs" value="1e-13"/>
+    <runtime fast_simulation="true"/>
+  </simulator_option>
+  <monte_carlo num_simulation_points="2"/>
+  <measurement_setting>
+    <slew>
+      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
+      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
+    </slew>
+    <delay>
+      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
+      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
+    </delay>
+  </measurement_setting>
+  <stimulus>
+    <clock>
+      <rise slew_type="abs" slew_time="20e-12" />
+      <fall slew_type="abs" slew_time="20e-12" />
+    </clock>
+    <input>
+      <rise slew_type="abs" slew_time="25e-12" />
+      <fall slew_type="abs" slew_time="25e-12" />
+    </input>
+  </stimulus>
+</openfpga_simulation_setting>
diff --git a/openfpga/test_script/and_k6_frac_adder_chain_mem16K.openfpga b/openfpga/test_script/and_k6_frac_adder_chain_mem16K.openfpga
new file mode 100644
index 000000000..34ec11181
--- /dev/null
+++ b/openfpga/test_script/and_k6_frac_adder_chain_mem16K.openfpga
@@ -0,0 +1,62 @@
+# Run VPR for the 'and' design
+vpr ./test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
+
+# Write out the architecture XML as a proof
+#write_openfpga_arch -f ./arch_echo.xml
+
+# Annotate the OpenFPGA architecture to VPR data base
+link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose
+
+# Write GSB to XML for debugging
+write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to clustering nets based on routing results
+pb_pin_fixup --verbose
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup #--verbose
+
+# Build the module graph 
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules 
+build_fabric --compress_routing --duplicate_grid_pin --verbose
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream 
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here 
+write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
+
+# Finish and exit OpenFPGA
+exit

From 787dc8ce83d5956bf85e7a7a3769a322d612ebe6 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 25 Mar 2020 11:16:04 -0600
Subject: [PATCH 341/645] added ASCII OpenFPGA logo in shell interface

---
 openfpga/src/base/openfpga_title.cpp | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/openfpga/src/base/openfpga_title.cpp b/openfpga/src/base/openfpga_title.cpp
index ae4ce80c4..41616c8bd 100644
--- a/openfpga/src/base/openfpga_title.cpp
+++ b/openfpga/src/base/openfpga_title.cpp
@@ -11,6 +11,13 @@
 const char* create_openfpga_title() {
   std::string title;
 
+  title += std::string("\n");
+  title += std::string("            ___                   _____ ____   ____    _     \n"); 
+  title += std::string("           / _ \\ _ __   ___ _ __ |  ___|  _ \\ / ___|  / \\    \n"); 
+  title += std::string("          | | | | '_ \\ / _ \\ '_ \\| |_  | |_) | |  _  / _ \\   \n"); 
+  title += std::string("          | |_| | |_) |  __/ | | |  _| |  __/| |_| |/ ___ \\  \n"); 
+  title += std::string("           \\___/| .__/ \\___|_| |_|_|   |_|    \\____/_/   \\_\\ \n"); 
+  title += std::string("                |_|                                          \n"); 
   title += std::string("\n");
   title += std::string("               OpenFPGA: An Open-source FPGA IP Generator\n");
   title += std::string("                     Versatile Place and Route (VPR)\n");

From c2e5d6b8e273f819259510102fad4e72a6d1b1e5 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 25 Mar 2020 14:38:13 -0600
Subject: [PATCH 342/645] add options to dsiable SDC for non-clock global ports

---
 openfpga/src/base/openfpga_sdc.cpp            |   2 +
 openfpga/src/base/openfpga_sdc_command.cpp    |   3 +
 openfpga/src/fpga_sdc/pnr_sdc_global_port.cpp | 192 ++++++++++++++++++
 openfpga/src/fpga_sdc/pnr_sdc_global_port.h   |  27 +++
 openfpga/src/fpga_sdc/pnr_sdc_option.cpp      |   9 +
 openfpga/src/fpga_sdc/pnr_sdc_option.h        |   3 +
 openfpga/src/fpga_sdc/pnr_sdc_writer.cpp      | 103 +---------
 7 files changed, 239 insertions(+), 100 deletions(-)
 create mode 100644 openfpga/src/fpga_sdc/pnr_sdc_global_port.cpp
 create mode 100644 openfpga/src/fpga_sdc/pnr_sdc_global_port.h

diff --git a/openfpga/src/base/openfpga_sdc.cpp b/openfpga/src/base/openfpga_sdc.cpp
index 8b708f133..a83d0b797 100644
--- a/openfpga/src/base/openfpga_sdc.cpp
+++ b/openfpga/src/base/openfpga_sdc.cpp
@@ -27,6 +27,7 @@ void write_pnr_sdc(OpenfpgaContext& openfpga_ctx,
 
   CommandOptionId opt_output_dir = cmd.option("file");
   CommandOptionId opt_constrain_global_port = cmd.option("constrain_global_port");
+  CommandOptionId opt_constrain_non_clock_global_port = cmd.option("constrain_non_clock_global_port");
   CommandOptionId opt_constrain_grid = cmd.option("constrain_grid");
   CommandOptionId opt_constrain_sb = cmd.option("constrain_sb");
   CommandOptionId opt_constrain_cb = cmd.option("constrain_cb");
@@ -45,6 +46,7 @@ void write_pnr_sdc(OpenfpgaContext& openfpga_ctx,
   PnrSdcOption options(sdc_dir_path);
 
   options.set_constrain_global_port(cmd_context.option_enable(cmd, opt_constrain_global_port));
+  options.set_constrain_non_clock_global_port(cmd_context.option_enable(cmd, opt_constrain_non_clock_global_port));
   options.set_constrain_grid(cmd_context.option_enable(cmd, opt_constrain_grid));
   options.set_constrain_sb(cmd_context.option_enable(cmd, opt_constrain_sb));
   options.set_constrain_cb(cmd_context.option_enable(cmd, opt_constrain_cb));
diff --git a/openfpga/src/base/openfpga_sdc_command.cpp b/openfpga/src/base/openfpga_sdc_command.cpp
index 91d65aa0a..7d194ba5b 100644
--- a/openfpga/src/base/openfpga_sdc_command.cpp
+++ b/openfpga/src/base/openfpga_sdc_command.cpp
@@ -29,6 +29,9 @@ ShellCommandId add_openfpga_write_pnr_sdc_command(openfpga::Shell<OpenfpgaContex
   /* Add an option '--constrain_global_port' */
   shell_cmd.add_option("constrain_global_port", false, "Constrain all the global ports of FPGA fabric");
 
+  /* Add an option '--constrain_non_clock_global_port' */
+  shell_cmd.add_option("constrain_non_clock_global_port", false, "Constrain all the non-clock global ports as clock ports of FPGA fabric");
+
   /* Add an option '--constrain_grid' */
   shell_cmd.add_option("constrain_grid", false, "Constrain all the grids of FPGA fabric");
 
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_global_port.cpp b/openfpga/src/fpga_sdc/pnr_sdc_global_port.cpp
new file mode 100644
index 000000000..6d56dae48
--- /dev/null
+++ b/openfpga/src/fpga_sdc/pnr_sdc_global_port.cpp
@@ -0,0 +1,192 @@
+/********************************************************************
+ * This file includes functions that print SDC (Synopsys Design Constraint) 
+ * files in physical design tools, i.e., Place & Route (PnR) tools
+ * The SDC files are used to constrain global ports for each module
+ * in FPGA fabric, such as Configurable Logic Blocks (CLBs), 
+ * Heterogeneous blocks, Switch Blocks (SBs) and Connection Blocks (CBs)
+ *
+ * Note that this is different from the SDC to constrain VPR Place&Route
+ * engine! These SDCs are designed for PnR to generate FPGA layouts!!!
+ *******************************************************************/
+#include <ctime>
+#include <fstream>
+#include <iomanip>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_time.h"
+#include "vtr_log.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_port.h"
+#include "openfpga_digest.h"
+
+#include "sdc_writer_naming.h"
+#include "sdc_writer_utils.h"
+#include "pnr_sdc_global_port.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Print SDC constraint for a clock port
+ * This format is derived from the open-source SDC syntax,
+ * which is supposed to be generic 
+ *
+ * This function is design to the SDC writer for any port
+ * wants to be treated as a clock port
+ *******************************************************************/
+static 
+void print_pnr_sdc_clock_port(std::fstream& fp, 
+                              const BasicPort& port_to_constrain,
+                              const float& clock_period) { 
+  valid_file_stream(fp);
+
+  fp << "create_clock";
+  fp << " -name " << generate_sdc_port(port_to_constrain);
+  fp << " -period " << std::setprecision(10) << clock_period;
+  fp << " -waveform {0 " << std::setprecision(10) << clock_period / 2 << "}";
+  fp << " [get_ports{" << generate_sdc_port(port_to_constrain) << "}]";
+  fp << std::endl;
+}        
+
+/********************************************************************
+ * Print SDC constraints for the clock ports which are the global ports 
+ * of FPGA fabric
+ * 
+ * For programming clock, we give a fixed period, while for operating
+ * clock, we constrain with critical path delay 
+ *******************************************************************/
+static 
+void print_pnr_sdc_global_clock_ports(std::fstream& fp, 
+                                      const float& programming_critical_path_delay,
+                                      const float& operating_critical_path_delay,
+                                      const CircuitLibrary& circuit_lib,
+                                      const std::vector<CircuitPortId>& global_ports) {
+
+  valid_file_stream(fp);
+
+  /* Get clock port from the global port */
+  for (const CircuitPortId& clock_port : global_ports) {
+    if (CIRCUIT_MODEL_PORT_CLOCK != circuit_lib.port_type(clock_port)) {
+      continue;
+    }
+    /* Reach here, it means a clock port and we need print constraints */
+    float clock_period = operating_critical_path_delay; 
+
+    /* For programming clock, we give a fixed period */
+    if (true == circuit_lib.port_is_prog(clock_port)) {
+      clock_period = programming_critical_path_delay;
+      /* Print comments */
+      fp << "##################################################" << std::endl; 
+      fp << "# Create programmable clock                       " << std::endl;
+      fp << "##################################################" << std::endl; 
+    } else {
+      /* Print comments */
+      fp << "##################################################" << std::endl; 
+      fp << "# Create clock                                    " << std::endl;
+      fp << "##################################################" << std::endl; 
+    }
+
+    for (const size_t& pin : circuit_lib.pins(clock_port)) {
+      BasicPort port_to_constrain(circuit_lib.port_prefix(clock_port), pin, pin);
+
+      print_pnr_sdc_clock_port(fp, 
+                               port_to_constrain,
+                               clock_period);
+    }
+  }
+}
+
+/********************************************************************
+ * Print SDC constraints for the non-clock ports which are the global ports 
+ * of FPGA fabric
+ * Here, we will the treat the non-clock ports as the clock ports
+ * in the CTS
+ * Note that, this may be applied to the reset, set and other global
+ * signals which do need very balanced delays to each sink
+ *******************************************************************/
+static 
+void print_pnr_sdc_global_non_clock_ports(std::fstream& fp, 
+                                          const float& operating_critical_path_delay,
+                                          const CircuitLibrary& circuit_lib,
+                                          const std::vector<CircuitPortId>& global_ports) {
+
+  valid_file_stream(fp);
+
+  /* For non-clock port from the global port: give a fixed period */
+  for (const CircuitPortId& global_port : global_ports) {
+    if (CIRCUIT_MODEL_PORT_CLOCK == circuit_lib.port_type(global_port)) {
+      continue;
+    }
+
+    /* Print comments */
+    fp << "##################################################" << std::endl; 
+    fp << "# Constrain other global ports                    " << std::endl;
+    fp << "##################################################" << std::endl; 
+
+    /* Reach here, it means a non-clock global port and we need print constraints */
+    float clock_period = operating_critical_path_delay; 
+    for (const size_t& pin : circuit_lib.pins(global_port)) {
+      BasicPort port_to_constrain(circuit_lib.port_prefix(global_port), pin, pin);
+
+      print_pnr_sdc_clock_port(fp, 
+                               port_to_constrain,
+                               clock_period);
+    }
+  }
+}
+
+/********************************************************************
+ * Print a SDC file to constrain the global ports of FPGA fabric
+ * in particular clock ports
+ *
+ * This ports to appear in this file will be treated in Clock Tree
+ * Synthesis (CTS)
+ * 
+ * For non-clock global ports, we have an option to select if they 
+ * should be treated in CTS or not
+ * In general, we do not recommend to do this
+ *******************************************************************/
+void print_pnr_sdc_global_ports(const std::string& sdc_dir, 
+                                const float& programming_critical_path_delay,
+                                const float& operating_critical_path_delay,
+                                const CircuitLibrary& circuit_lib,
+                                const std::vector<CircuitPortId>& global_ports,
+                                const bool& constrain_non_clock_port) {
+
+  /* Create the file name for Verilog netlist */
+  std::string sdc_fname(sdc_dir + std::string(SDC_GLOBAL_PORTS_FILE_NAME));
+
+  /* Start time count */
+  std::string timer_message = std::string("Write SDC for constraining clocks for P&R flow '") + sdc_fname + std::string("'");
+  vtr::ScopedStartFinishTimer timer(timer_message);
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(sdc_fname, std::fstream::out | std::fstream::trunc);
+
+  check_file_stream(sdc_fname.c_str(), fp);
+
+  /* Generate the descriptions*/
+  print_sdc_file_header(fp, std::string("Clock contraints for PnR"));
+
+  print_pnr_sdc_global_clock_ports(fp, 
+                                   programming_critical_path_delay,
+                                   operating_critical_path_delay,
+                                   circuit_lib,
+                                   global_ports);
+
+  if (true == constrain_non_clock_port) {
+    print_pnr_sdc_global_non_clock_ports(fp, 
+                                         operating_critical_path_delay,
+                                         circuit_lib,
+                                         global_ports);
+
+  }
+
+  /* Close file handler */
+  fp.close();
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_global_port.h b/openfpga/src/fpga_sdc/pnr_sdc_global_port.h
new file mode 100644
index 000000000..444482106
--- /dev/null
+++ b/openfpga/src/fpga_sdc/pnr_sdc_global_port.h
@@ -0,0 +1,27 @@
+#ifndef PNR_SDC_GLBOAL_PORT_H
+#define PNR_SDC_GLBOAL_PORT_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <string>
+#include <vector>
+#include "circuit_library.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void print_pnr_sdc_global_ports(const std::string& sdc_dir, 
+                                const float& programming_critical_path_delay,
+                                const float& operating_critical_path_delay,
+                                const CircuitLibrary& circuit_lib,
+                                const std::vector<CircuitPortId>& global_ports,
+                                const bool& constrain_non_clock_port);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_option.cpp b/openfpga/src/fpga_sdc/pnr_sdc_option.cpp
index 3a3906b50..a5143776e 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_option.cpp
+++ b/openfpga/src/fpga_sdc/pnr_sdc_option.cpp
@@ -12,6 +12,7 @@ namespace openfpga {
 PnrSdcOption::PnrSdcOption(const std::string& sdc_dir) {
   sdc_dir_ = sdc_dir;
   constrain_global_port_ = false;
+  constrain_non_clock_global_port_ = false;
   constrain_grid_ = false;
   constrain_sb_ = false;
   constrain_cb_ = false;
@@ -41,6 +42,10 @@ bool PnrSdcOption::constrain_global_port() const {
   return constrain_global_port_;
 }
 
+bool PnrSdcOption::constrain_non_clock_global_port() const {
+  return constrain_non_clock_global_port_;
+}
+
 bool PnrSdcOption::constrain_grid() const {
   return constrain_grid_;
 }
@@ -86,6 +91,10 @@ void PnrSdcOption::set_constrain_global_port(const bool& constrain_global_port)
   constrain_global_port_ = constrain_global_port;
 }
 
+void PnrSdcOption::set_constrain_non_clock_global_port(const bool& constrain_non_clock_global_port) {
+  constrain_non_clock_global_port_ = constrain_non_clock_global_port;
+}
+
 void PnrSdcOption::set_constrain_grid(const bool& constrain_grid) {
   constrain_grid_ = constrain_grid;
 }
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_option.h b/openfpga/src/fpga_sdc/pnr_sdc_option.h
index a485a1946..b81bfaefe 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_option.h
+++ b/openfpga/src/fpga_sdc/pnr_sdc_option.h
@@ -18,6 +18,7 @@ class PnrSdcOption {
     std::string sdc_dir() const;
     bool generate_sdc_pnr() const;
     bool constrain_global_port() const;
+    bool constrain_non_clock_global_port() const;
     bool constrain_grid() const;
     bool constrain_sb() const;
     bool constrain_cb() const;
@@ -28,6 +29,7 @@ class PnrSdcOption {
     void set_sdc_dir(const std::string& sdc_dir);
     void set_generate_sdc_pnr(const bool& generate_sdc_pnr);
     void set_constrain_global_port(const bool& constrain_global_port);
+    void set_constrain_non_clock_global_port(const bool& constrain_non_clock_global_port);
     void set_constrain_grid(const bool& constrain_grid);
     void set_constrain_sb(const bool& constrain_sb);
     void set_constrain_cb(const bool& constrain_cb);
@@ -37,6 +39,7 @@ class PnrSdcOption {
   private: /* Internal data */
     std::string sdc_dir_;
     bool constrain_global_port_; 
+    bool constrain_non_clock_global_port_; 
     bool constrain_grid_; 
     bool constrain_sb_;
     bool constrain_cb_;
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
index 9d1478037..b005ca6ce 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
+++ b/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
@@ -28,6 +28,7 @@
 #include "sdc_writer_naming.h"
 #include "sdc_writer_utils.h"
 #include "sdc_memory_utils.h"
+#include "pnr_sdc_global_port.h"
 #include "pnr_sdc_routing_writer.h"
 #include "pnr_sdc_grid_writer.h"
 #include "pnr_sdc_writer.h"
@@ -35,105 +36,6 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-/********************************************************************
- * Print a SDC file to constrain the global ports of FPGA fabric
- * in particular clock ports
- * 
- * For programming clock, we give a fixed period, while for operating
- * clock, we constrain with critical path delay 
- *******************************************************************/
-static 
-void print_pnr_sdc_global_ports(const std::string& sdc_dir, 
-                                const float& programming_critical_path_delay,
-                                const float& operating_critical_path_delay,
-                                const CircuitLibrary& circuit_lib,
-                                const std::vector<CircuitPortId>& global_ports) {
-
-  /* Create the file name for Verilog netlist */
-  std::string sdc_fname(sdc_dir + std::string(SDC_GLOBAL_PORTS_FILE_NAME));
-
-  /* Start time count */
-  std::string timer_message = std::string("Write SDC for constraining clocks for P&R flow '") + sdc_fname + std::string("'");
-  vtr::ScopedStartFinishTimer timer(timer_message);
-
-  /* Create the file stream */
-  std::fstream fp;
-  fp.open(sdc_fname, std::fstream::out | std::fstream::trunc);
-
-  check_file_stream(sdc_fname.c_str(), fp);
-
-  /* Generate the descriptions*/
-  print_sdc_file_header(fp, std::string("Clock contraints for PnR"));
-
-  /* Get clock port from the global port */
-  for (const CircuitPortId& clock_port : global_ports) {
-    if (CIRCUIT_MODEL_PORT_CLOCK != circuit_lib.port_type(clock_port)) {
-      continue;
-    }
-    /* Reach here, it means a clock port and we need print constraints */
-    float clock_period = operating_critical_path_delay; 
-
-    /* For programming clock, we give a fixed period */
-    if (true == circuit_lib.port_is_prog(clock_port)) {
-      clock_period = programming_critical_path_delay;
-      /* Print comments */
-      fp << "##################################################" << std::endl; 
-      fp << "# Create programmable clock                       " << std::endl;
-      fp << "##################################################" << std::endl; 
-    } else {
-      /* Print comments */
-      fp << "##################################################" << std::endl; 
-      fp << "# Create clock                                    " << std::endl;
-      fp << "##################################################" << std::endl; 
-    }
-
-    for (const size_t& pin : circuit_lib.pins(clock_port)) {
-      BasicPort port_to_constrain(circuit_lib.port_prefix(clock_port), pin, pin);
-
-      fp << "create_clock ";
-      fp << generate_sdc_port(port_to_constrain) << "-period ";
-      fp << std::setprecision(10) << clock_period;
-      fp << " -waveform {0 ";
-      fp << std::setprecision(10) << clock_period / 2;
-      fp << "}" << std::endl;
-
-      fp << std::endl;
-    }
-  }
-
-  /* For non-clock port from the global port: give a fixed period */
-  for (const CircuitPortId& global_port : global_ports) {
-    if (CIRCUIT_MODEL_PORT_CLOCK == circuit_lib.port_type(global_port)) {
-      continue;
-    }
-
-    /* Print comments */
-    fp << "##################################################" << std::endl; 
-    fp << "# Constrain other global ports                    " << std::endl;
-    fp << "##################################################" << std::endl; 
-
-    /* Reach here, it means a non-clock global port and we need print constraints */
-    float clock_period = operating_critical_path_delay; 
-    for (const size_t& pin : circuit_lib.pins(global_port)) {
-      BasicPort port_to_constrain(circuit_lib.port_prefix(global_port), pin, pin);
-      fp << "create_clock ";
-      fp << generate_sdc_port(port_to_constrain) << "-period ";
-      fp << std::setprecision(10) << clock_period;
-      fp << " -waveform {0 ";
-      fp << std::setprecision(10) << clock_period / 2;
-      fp << "} ";
-      fp << "[list [get_ports { " << generate_sdc_port(port_to_constrain) << "}]]" << std::endl;
-
-      fp << "set_drive 0 " << generate_sdc_port(port_to_constrain) << std::endl;
-     
-      fp << std::endl;
-    }
-  }
-
-  /* Close file handler */
-  fp.close();
-}
-
 /********************************************************************
  * Break combinational loops in FPGA fabric, which mainly come from
  * configurable memory cells. 
@@ -354,7 +256,8 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options,
     print_pnr_sdc_global_ports(sdc_options.sdc_dir(),
                                programming_critical_path_delay,
                                operating_critical_path_delay,
-                               circuit_lib, global_ports);
+                               circuit_lib, global_ports,
+                               sdc_options.constrain_non_clock_global_port());
   }
 
   std::string top_module_name = generate_fpga_top_module_name();

From 62b6de8437bd10d9d298255488a9247b8d0df5c6 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 25 Mar 2020 14:44:42 -0600
Subject: [PATCH 343/645] update the SDC of VPR7+OpenFPGA to be even with
 VPR8+OpenFPGA

---
 .../backend_assistant/pnr_sdc_writer.cpp      | 59 ++++++++++---------
 1 file changed, 31 insertions(+), 28 deletions(-)

diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.cpp
index eb2a33bc0..a333f95ff 100644
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.cpp
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.cpp
@@ -45,7 +45,8 @@ static
 void print_pnr_sdc_global_ports(const std::string& sdc_dir, 
                                 const float& critical_path_delay,
                                 const CircuitLibrary& circuit_lib,
-                                const std::vector<CircuitPortId>& global_ports) {
+                                const std::vector<CircuitPortId>& global_ports,
+                                const bool& constrain_non_clock_ports) {
 
   /* Create the file name for Verilog netlist */
   std::string sdc_fname(sdc_dir + std::string(SDC_GLOBAL_PORTS_FILE_NAME));
@@ -91,43 +92,45 @@ void print_pnr_sdc_global_ports(const std::string& sdc_dir,
     for (const size_t& pin : circuit_lib.pins(clock_port)) {
       BasicPort port_to_constrain(circuit_lib.port_prefix(clock_port), pin, pin);
 
-      fp << "create_clock ";
-      fp << generate_sdc_port(port_to_constrain) << "-period ";
+      fp << "create_clock -name ";
+      fp << generate_sdc_port(port_to_constrain) << " -period ";
       fp << std::setprecision(10) << clock_period;
       fp << " -waveform {0 ";
       fp << std::setprecision(10) << clock_period / 2;
-      fp << "}" << std::endl;
+      fp << "}";
+      fp << "{get_ports {" << generate_sdc_port(port_to_constrain) << "}]";
+      fp << std::endl;
 
       fp << std::endl;
     }
   }
 
-  /* For non-clock port from the global port: give a fixed period */
-  for (const CircuitPortId& global_port : global_ports) {
-    if (SPICE_MODEL_PORT_CLOCK == circuit_lib.port_type(global_port)) {
-      continue;
-    }
+  if (true == constrain_non_clock_ports) {
+    /* For non-clock port from the global port: give a fixed period */
+    for (const CircuitPortId& global_port : global_ports) {
+      if (SPICE_MODEL_PORT_CLOCK == circuit_lib.port_type(global_port)) {
+        continue;
+      }
 
-    /* Print comments */
-    fp << "##################################################" << std::endl; 
-    fp << "# Constrain other global ports                    " << std::endl;
-    fp << "##################################################" << std::endl; 
+      /* Print comments */
+      fp << "##################################################" << std::endl; 
+      fp << "# Constrain other global ports                    " << std::endl;
+      fp << "##################################################" << std::endl; 
 
-    /* Reach here, it means a non-clock global port and we need print constraints */
-    float clock_period = SDC_FIXED_CLOCK_PERIOD; 
-    for (const size_t& pin : circuit_lib.pins(global_port)) {
-      BasicPort port_to_constrain(circuit_lib.port_prefix(global_port), pin, pin);
-      fp << "create_clock ";
-      fp << generate_sdc_port(port_to_constrain) << "-period ";
-      fp << std::setprecision(10) << clock_period;
-      fp << " -waveform {0 ";
-      fp << std::setprecision(10) << clock_period / 2;
-      fp << "} ";
-      fp << "[list [get_ports { " << generate_sdc_port(port_to_constrain) << "}]]" << std::endl;
+      /* Reach here, it means a non-clock global port and we need print constraints */
+      float clock_period = SDC_FIXED_CLOCK_PERIOD; 
+      for (const size_t& pin : circuit_lib.pins(global_port)) {
+        BasicPort port_to_constrain(circuit_lib.port_prefix(global_port), pin, pin);
+        fp << "create_clock -name ";
+        fp << generate_sdc_port(port_to_constrain) << " -period ";
+        fp << std::setprecision(10) << clock_period;
+        fp << " -waveform {0 ";
+        fp << std::setprecision(10) << clock_period / 2;
+        fp << "} ";
+        fp << "[get_ports { " << generate_sdc_port(port_to_constrain) << "}]" << std::endl;
 
-      fp << "set_drive 0 " << generate_sdc_port(port_to_constrain) << std::endl;
-     
-      fp << std::endl;
+        fp << std::endl;
+      }
     }
   }
 
@@ -397,7 +400,7 @@ void print_pnr_sdc(const SdcOption& sdc_options,
   
   /* Constrain global ports */
   if (true == sdc_options.constrain_global_port()) {
-    print_pnr_sdc_global_ports(sdc_options.sdc_dir(), critical_path_delay, circuit_lib, global_ports);
+    print_pnr_sdc_global_ports(sdc_options.sdc_dir(), critical_path_delay, circuit_lib, global_ports, false);
   }
 
   std::string top_module_name = generate_fpga_top_module_name();

From 4a0128f240cca198aa4776cd55cbc2d278fd41e0 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 25 Mar 2020 14:46:31 -0600
Subject: [PATCH 344/645] minor fix on the SDC format

---
 openfpga/src/fpga_sdc/pnr_sdc_global_port.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/openfpga/src/fpga_sdc/pnr_sdc_global_port.cpp b/openfpga/src/fpga_sdc/pnr_sdc_global_port.cpp
index 6d56dae48..4e6ef4925 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_global_port.cpp
+++ b/openfpga/src/fpga_sdc/pnr_sdc_global_port.cpp
@@ -46,7 +46,7 @@ void print_pnr_sdc_clock_port(std::fstream& fp,
   fp << " -name " << generate_sdc_port(port_to_constrain);
   fp << " -period " << std::setprecision(10) << clock_period;
   fp << " -waveform {0 " << std::setprecision(10) << clock_period / 2 << "}";
-  fp << " [get_ports{" << generate_sdc_port(port_to_constrain) << "}]";
+  fp << " [get_ports {" << generate_sdc_port(port_to_constrain) << "}]";
   fp << std::endl;
 }        
 

From 3a74fb7a04d1bd9e7b54d3a9efe314c79bb2dc68 Mon Sep 17 00:00:00 2001
From: Xifan Tang <tangxifan@gmail.com>
Date: Wed, 25 Mar 2020 15:23:21 -0600
Subject: [PATCH 345/645] update documentation for the new options

---
 docs/source/openfpga_shell/openfpga_commands.rst | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/docs/source/openfpga_shell/openfpga_commands.rst b/docs/source/openfpga_shell/openfpga_commands.rst
index 6551b7421..fd44f6fbb 100644
--- a/docs/source/openfpga_shell/openfpga_commands.rst
+++ b/docs/source/openfpga_shell/openfpga_commands.rst
@@ -174,11 +174,15 @@ FPGA-SDC
   
   - ``--file`` or ``-f`` Specify the output directory for SDC files
 
-  - ``--constrain_global_port`` Constrain all the global ports of FPGA fabric
+  - ``--constrain_global_port`` Constrain all the global ports of FPGA fabric.
+
+  - ``--constrain_non_clock_global_port`` Constrain all the non-clock global ports as clocks ports of FPGA fabric
+
+    .. note:: ``constrain_global_port`` will treat these global ports in Clock Tree Synthesis (CTS), in purpose of balancing the delay to each sink. Be carefull to enable ``constrain_non_clock_global_port``, this may significanly increase the runtime of CTS as it is supposed to be routed before any other nets. This may cause routing congestion as well.
 
   - ``--constrain_grid`` Constrain all the grids of FPGA fabric
 
-  - `--constrain_sb`` Constrain all the switch blocks of FPGA fabric
+  - ``--constrain_sb`` Constrain all the switch blocks of FPGA fabric
 
   - ``--constrain_cb`` Constrain all the connection blocks of FPGA fabric
 

From 329b0a9cf1d3b5ac9a8686b8017211c981222751 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 25 Mar 2020 15:55:30 -0600
Subject: [PATCH 346/645] add options to enable SDC constraints on zero-delay
 paths

---
 openfpga/src/base/openfpga_sdc.cpp            |  2 +
 openfpga/src/base/openfpga_sdc_command.cpp    |  3 +
 openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp | 42 ++++++++----
 openfpga/src/fpga_sdc/pnr_sdc_grid_writer.h   |  3 +-
 openfpga/src/fpga_sdc/pnr_sdc_option.cpp      |  9 +++
 openfpga/src/fpga_sdc/pnr_sdc_option.h        |  3 +
 .../src/fpga_sdc/pnr_sdc_routing_writer.cpp   | 66 +++++++++++++------
 .../src/fpga_sdc/pnr_sdc_routing_writer.h     | 12 ++--
 openfpga/src/fpga_sdc/pnr_sdc_writer.cpp      | 15 +++--
 9 files changed, 114 insertions(+), 41 deletions(-)

diff --git a/openfpga/src/base/openfpga_sdc.cpp b/openfpga/src/base/openfpga_sdc.cpp
index a83d0b797..cb2e1bf72 100644
--- a/openfpga/src/base/openfpga_sdc.cpp
+++ b/openfpga/src/base/openfpga_sdc.cpp
@@ -34,6 +34,7 @@ void write_pnr_sdc(OpenfpgaContext& openfpga_ctx,
   CommandOptionId opt_constrain_configurable_memory_outputs = cmd.option("constrain_configurable_memory_outputs");
   CommandOptionId opt_constrain_routing_multiplexer_outputs = cmd.option("constrain_routing_multiplexer_outputs");
   CommandOptionId opt_constrain_switch_block_outputs = cmd.option("constrain_switch_block_outputs");
+  CommandOptionId opt_constrain_zero_delay_paths = cmd.option("constrain_zero_delay_paths");
 
   /* This is an intermediate data structure which is designed to modularize the FPGA-SDC
    * Keep it independent from any other outside data structures
@@ -53,6 +54,7 @@ void write_pnr_sdc(OpenfpgaContext& openfpga_ctx,
   options.set_constrain_configurable_memory_outputs(cmd_context.option_enable(cmd, opt_constrain_configurable_memory_outputs));
   options.set_constrain_routing_multiplexer_outputs(cmd_context.option_enable(cmd, opt_constrain_routing_multiplexer_outputs));
   options.set_constrain_switch_block_outputs(cmd_context.option_enable(cmd, opt_constrain_switch_block_outputs));
+  options.set_constrain_zero_delay_paths(cmd_context.option_enable(cmd, opt_constrain_zero_delay_paths));
 
   /* We first turn on default sdc option and then disable part of them by following users' options */
   if (false == options.generate_sdc_pnr()) {
diff --git a/openfpga/src/base/openfpga_sdc_command.cpp b/openfpga/src/base/openfpga_sdc_command.cpp
index 7d194ba5b..551b37d2b 100644
--- a/openfpga/src/base/openfpga_sdc_command.cpp
+++ b/openfpga/src/base/openfpga_sdc_command.cpp
@@ -50,6 +50,9 @@ ShellCommandId add_openfpga_write_pnr_sdc_command(openfpga::Shell<OpenfpgaContex
   /* Add an option '--constrain_switch_block_outputs' */
   shell_cmd.add_option("constrain_switch_block_outputs", false, "Constrain all the outputs of switch blocks of FPGA fabric");
 
+  /* Add an option '--constrain_zero_delay_paths' */
+  shell_cmd.add_option("constrain_zero_delay_paths", false, "Constrain zero-delay paths in FPGA fabric");
+
   /* Add an option '--verbose' */
   shell_cmd.add_option("verbose", false, "Enable verbose output");
   
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp
index f8ce1c703..c6b50d797 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp
+++ b/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp
@@ -46,7 +46,8 @@ void print_pnr_sdc_constrain_pb_pin_interc_timing(std::fstream& fp,
                                                   const ModuleManager& module_manager,
                                                   const ModuleId& parent_module,
                                                   t_pb_graph_pin* des_pb_graph_pin,
-                                                  t_mode* physical_mode) {
+                                                  t_mode* physical_mode,
+                                                  const bool& constrain_zero_delay_paths) {
 
   /* Validate file stream */ 
   valid_file_stream(fp);
@@ -138,6 +139,12 @@ void print_pnr_sdc_constrain_pb_pin_interc_timing(std::fstream& fp,
     BasicPort des_port = module_manager.module_port(des_module, des_module_port_id);
     des_port.set_width(des_pb_graph_pin->pin_number, des_pb_graph_pin->pin_number);
 
+    /* If we have a zero-delay path to contrain, we will skip unless users want so */
+    if ( (false == constrain_zero_delay_paths)
+      && (0. == des_pb_graph_pin->input_edges[iedge]->delay_max) ) {
+      continue;
+    }
+
     /* Print a SDC timing constraint */
     print_pnr_sdc_constrain_max_delay(fp, 
                                       src_instance_name, 
@@ -158,7 +165,8 @@ void print_pnr_sdc_constrain_pb_interc_timing(std::fstream& fp,
                                               const ModuleId& parent_module,
                                               t_pb_graph_node* des_pb_graph_node,
                                               const e_circuit_pb_port_type& pb_port_type,
-                                              t_mode* physical_mode) {
+                                              t_mode* physical_mode,
+                                              const bool& constrain_zero_delay_paths) {
   /* Validate file stream */ 
   valid_file_stream(fp);
 
@@ -171,7 +179,8 @@ void print_pnr_sdc_constrain_pb_interc_timing(std::fstream& fp,
         print_pnr_sdc_constrain_pb_pin_interc_timing(fp, 
                                                      module_manager, parent_module, 
                                                      &(des_pb_graph_node->input_pins[iport][ipin]),
-                                                     physical_mode);
+                                                     physical_mode,
+                                                     constrain_zero_delay_paths);
       }
     }
     break;
@@ -182,7 +191,8 @@ void print_pnr_sdc_constrain_pb_interc_timing(std::fstream& fp,
         print_pnr_sdc_constrain_pb_pin_interc_timing(fp,
                                                      module_manager, parent_module, 
                                                      &(des_pb_graph_node->output_pins[iport][ipin]),
-                                                     physical_mode);
+                                                     physical_mode,
+                                                     constrain_zero_delay_paths);
       }
     }
     break;
@@ -209,7 +219,8 @@ static
 void print_pnr_sdc_constrain_pb_graph_node_timing(const std::string& sdc_dir,
                                                   const ModuleManager& module_manager,
                                                   t_pb_graph_node* parent_pb_graph_node,
-                                                  t_mode* physical_mode) {
+                                                  t_mode* physical_mode,
+                                                  const bool& constrain_zero_delay_paths) {
 
   /* Get the pb_type definition related to the node */
   t_pb_type* physical_pb_type = parent_pb_graph_node->pb_type; 
@@ -242,7 +253,8 @@ void print_pnr_sdc_constrain_pb_graph_node_timing(const std::string& sdc_dir,
                                            module_manager, pb_module,
                                            parent_pb_graph_node, 
                                            CIRCUIT_PB_PORT_OUTPUT,
-                                           physical_mode);
+                                           physical_mode,
+                                           constrain_zero_delay_paths);
   
   /* We check input_pins of child_pb_graph_node and its the input_edges
    * Built the interconnections between inputs of cur_pb_graph_node and inputs of child_pb_graph_node
@@ -259,7 +271,8 @@ void print_pnr_sdc_constrain_pb_graph_node_timing(const std::string& sdc_dir,
                                                module_manager, pb_module,
                                                child_pb_graph_node, 
                                                CIRCUIT_PB_PORT_INPUT,
-                                               physical_mode);
+                                               physical_mode,
+                                               constrain_zero_delay_paths);
       /* Do NOT constrain clock here, it should be handled by Clock Tree Synthesis */
     }
   }
@@ -277,7 +290,8 @@ static
 void rec_print_pnr_sdc_constrain_pb_graph_timing(const std::string& sdc_dir,
                                                  const ModuleManager& module_manager,
                                                  const VprDeviceAnnotation& device_annotation,
-                                                 t_pb_graph_node* parent_pb_graph_node) {
+                                                 t_pb_graph_node* parent_pb_graph_node,
+                                                 const bool& constrain_zero_delay_paths) {
   /* Validate pb_graph node */
   if (nullptr == parent_pb_graph_node) {
     VTR_LOGF_ERROR(__FILE__, __LINE__,
@@ -302,7 +316,8 @@ void rec_print_pnr_sdc_constrain_pb_graph_timing(const std::string& sdc_dir,
   print_pnr_sdc_constrain_pb_graph_node_timing(sdc_dir,
                                                module_manager,
                                                parent_pb_graph_node,
-                                               physical_mode);
+                                               physical_mode,
+                                               constrain_zero_delay_paths);
 
   /* Go recursively to the lower level in the pb_graph
    * Note that we assume a full hierarchical P&R, we will only visit pb_graph_node of unique pb_type 
@@ -310,7 +325,8 @@ void rec_print_pnr_sdc_constrain_pb_graph_timing(const std::string& sdc_dir,
   for (int ipb = 0; ipb < physical_mode->num_pb_type_children; ++ipb) {
     rec_print_pnr_sdc_constrain_pb_graph_timing(sdc_dir, module_manager, 
                                                 device_annotation,
-                                                &(parent_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb][0]));
+                                                &(parent_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb][0]),
+                                                constrain_zero_delay_paths);
   }
 }
 
@@ -320,7 +336,8 @@ void rec_print_pnr_sdc_constrain_pb_graph_timing(const std::string& sdc_dir,
 void print_pnr_sdc_constrain_grid_timing(const std::string& sdc_dir,
                                          const DeviceContext& device_ctx,
                                          const VprDeviceAnnotation& device_annotation,
-                                         const ModuleManager& module_manager) {
+                                         const ModuleManager& module_manager,
+                                         const bool& constrain_zero_delay_paths) {
 
   /* Start time count */
   vtr::ScopedStartFinishTimer timer("Write SDC for constraining grid timing for P&R flow");
@@ -338,7 +355,8 @@ void print_pnr_sdc_constrain_grid_timing(const std::string& sdc_dir,
       /* Special for I/O block, generate one module for each border side */
       rec_print_pnr_sdc_constrain_pb_graph_timing(sdc_dir, module_manager, 
                                                   device_annotation,
-                                                  pb_graph_head);
+                                                  pb_graph_head,
+                                                  constrain_zero_delay_paths);
     }
   }
 }
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.h b/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.h
index 91c1b7030..400ca1616 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.h
+++ b/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.h
@@ -20,7 +20,8 @@ namespace openfpga {
 void print_pnr_sdc_constrain_grid_timing(const std::string& sdc_dir,
                                          const DeviceContext& device_ctx,
                                          const VprDeviceAnnotation& device_annotation,
-                                         const ModuleManager& module_manager);
+                                         const ModuleManager& module_manager,
+                                         const bool& constrain_zero_delay_paths);
 
 } /* end namespace openfpga */
 
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_option.cpp b/openfpga/src/fpga_sdc/pnr_sdc_option.cpp
index a5143776e..153ac4fac 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_option.cpp
+++ b/openfpga/src/fpga_sdc/pnr_sdc_option.cpp
@@ -19,6 +19,7 @@ PnrSdcOption::PnrSdcOption(const std::string& sdc_dir) {
   constrain_configurable_memory_outputs_ = false;
   constrain_routing_multiplexer_outputs_ = false;
   constrain_switch_block_outputs_ = false;
+  constrain_zero_delay_paths_ = false;
 }
 
 /********************************************************************
@@ -70,6 +71,10 @@ bool PnrSdcOption::constrain_switch_block_outputs() const {
   return constrain_switch_block_outputs_;
 }
 
+bool PnrSdcOption::constrain_zero_delay_paths() const {
+  return constrain_zero_delay_paths_;
+}
+
 /********************************************************************
  * Public mutators
  ********************************************************************/
@@ -119,4 +124,8 @@ void PnrSdcOption::set_constrain_switch_block_outputs(const bool& constrain_sb_o
   constrain_switch_block_outputs_ = constrain_sb_outputs;
 }
 
+void PnrSdcOption::set_constrain_zero_delay_paths(const bool& constrain_zero_delay_paths) {
+  constrain_zero_delay_paths_ = constrain_zero_delay_paths;
+}
+
 } /* end namespace openfpga */
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_option.h b/openfpga/src/fpga_sdc/pnr_sdc_option.h
index b81bfaefe..71dc1a806 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_option.h
+++ b/openfpga/src/fpga_sdc/pnr_sdc_option.h
@@ -25,6 +25,7 @@ class PnrSdcOption {
     bool constrain_configurable_memory_outputs() const;
     bool constrain_routing_multiplexer_outputs() const;
     bool constrain_switch_block_outputs() const;
+    bool constrain_zero_delay_paths() const;
   public: /* Public mutators */
     void set_sdc_dir(const std::string& sdc_dir);
     void set_generate_sdc_pnr(const bool& generate_sdc_pnr);
@@ -36,6 +37,7 @@ class PnrSdcOption {
     void set_constrain_configurable_memory_outputs(const bool& constrain_config_mem_outputs);
     void set_constrain_routing_multiplexer_outputs(const bool& constrain_routing_mux_outputs);
     void set_constrain_switch_block_outputs(const bool& constrain_sb_outputs);
+    void set_constrain_zero_delay_paths(const bool& constrain_zero_delay_paths);
   private: /* Internal data */
     std::string sdc_dir_;
     bool constrain_global_port_; 
@@ -46,6 +48,7 @@ class PnrSdcOption {
     bool constrain_configurable_memory_outputs_;
     bool constrain_routing_multiplexer_outputs_;
     bool constrain_switch_block_outputs_;
+    bool constrain_zero_delay_paths_;
 };
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp
index dd0914d14..d4f1ce522 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp
+++ b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp
@@ -54,7 +54,8 @@ void print_pnr_sdc_constrain_sb_mux_timing(std::fstream& fp,
                                            const RRGraph& rr_graph,
                                            const RRGSB& rr_gsb,
                                            const e_side& output_node_side,
-                                           const RRNodeId& output_rr_node) {
+                                           const RRNodeId& output_rr_node,
+                                           const bool& constrain_zero_delay_paths) {
   /* Validate file stream */
   valid_file_stream(fp);
 
@@ -89,6 +90,11 @@ void print_pnr_sdc_constrain_sb_mux_timing(std::fstream& fp,
 
   /* Find the starting points */
   for (const ModulePortId& module_input_port : module_input_ports) {
+    /* If we have a zero-delay path to contrain, we will skip unless users want so */
+    if ( (false == constrain_zero_delay_paths)
+      && (0. == switch_delays[module_input_port]) ) {
+      continue;
+    }
     /* Constrain a path */
     print_pnr_sdc_constrain_port2port_timing(fp,
                                              module_manager, 
@@ -110,7 +116,8 @@ static
 void print_pnr_sdc_constrain_sb_timing(const std::string& sdc_dir,
                                        const ModuleManager& module_manager,
                                        const RRGraph& rr_graph,
-                                       const RRGSB& rr_gsb) {
+                                       const RRGSB& rr_gsb,
+                                       const bool& constrain_zero_delay_paths) {
 
   /* Create the file name for Verilog netlist */
   vtr::Point<size_t> gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
@@ -148,7 +155,8 @@ void print_pnr_sdc_constrain_sb_timing(const std::string& sdc_dir,
                                             rr_graph,
                                             rr_gsb,
                                             side_manager.get_side(),
-                                            chan_rr_node);
+                                            chan_rr_node,
+                                            constrain_zero_delay_paths);
     }
   }
 
@@ -163,7 +171,8 @@ void print_pnr_sdc_constrain_sb_timing(const std::string& sdc_dir,
 void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_dir,
                                                        const ModuleManager& module_manager,
                                                        const RRGraph& rr_graph,
-                                                       const DeviceRRGSB& device_rr_gsb) {
+                                                       const DeviceRRGSB& device_rr_gsb,
+                                                       const bool& constrain_zero_delay_paths) {
 
   /* Start time count */
   vtr::ScopedStartFinishTimer timer("Write SDC for constrain Switch Block timing for P&R flow");
@@ -180,7 +189,8 @@ void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_di
       print_pnr_sdc_constrain_sb_timing(sdc_dir,
                                         module_manager,
                                         rr_graph,
-                                        rr_gsb);
+                                        rr_gsb,
+                                        constrain_zero_delay_paths);
     }
   }
 }
@@ -192,7 +202,8 @@ void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_di
 void print_pnr_sdc_compact_routing_constrain_sb_timing(const std::string& sdc_dir,
                                                        const ModuleManager& module_manager,
                                                        const RRGraph& rr_graph,
-                                                       const DeviceRRGSB& device_rr_gsb) {
+                                                       const DeviceRRGSB& device_rr_gsb,
+                                                       const bool& constrain_zero_delay_paths) {
 
   /* Start time count */
   vtr::ScopedStartFinishTimer timer("Write SDC for constrain Switch Block timing for P&R flow");
@@ -205,7 +216,8 @@ void print_pnr_sdc_compact_routing_constrain_sb_timing(const std::string& sdc_di
     print_pnr_sdc_constrain_sb_timing(sdc_dir,
                                       module_manager,
                                       rr_graph,
-                                      rr_gsb);
+                                      rr_gsb,
+                                      constrain_zero_delay_paths);
   }
 }
 
@@ -220,7 +232,8 @@ void print_pnr_sdc_constrain_cb_mux_timing(std::fstream& fp,
                                            const RRGraph& rr_graph,
                                            const RRGSB& rr_gsb,
                                            const t_rr_type& cb_type,
-                                           const RRNodeId& output_rr_node) {
+                                           const RRNodeId& output_rr_node,
+                                           const bool& constrain_zero_delay_paths) {
   /* Validate file stream */
   valid_file_stream(fp);
 
@@ -275,6 +288,12 @@ void print_pnr_sdc_constrain_cb_mux_timing(std::fstream& fp,
 
   /* Find the starting points */
   for (const ModulePortId& module_input_port : module_input_ports) {
+    /* If we have a zero-delay path to contrain, we will skip unless users want so */
+    if ( (false == constrain_zero_delay_paths)
+      && (0. == switch_delays[module_input_port]) ) {
+      continue;
+    }
+
     /* Constrain a path */
     print_pnr_sdc_constrain_port2port_timing(fp,
                                              module_manager, 
@@ -284,7 +303,6 @@ void print_pnr_sdc_constrain_cb_mux_timing(std::fstream& fp,
   }
 }
 
-
 /********************************************************************
  * Print SDC timing constraints for a Connection block 
  * This function is designed for compact routing hierarchy
@@ -294,7 +312,8 @@ void print_pnr_sdc_constrain_cb_timing(const std::string& sdc_dir,
                                        const ModuleManager& module_manager,
                                        const RRGraph& rr_graph,
                                        const RRGSB& rr_gsb, 
-                                       const t_rr_type& cb_type) {
+                                       const t_rr_type& cb_type,
+                                       const bool& constrain_zero_delay_paths) {
   /* Create the netlist */
   vtr::Point<size_t> gsb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type));
 
@@ -325,7 +344,8 @@ void print_pnr_sdc_constrain_cb_timing(const std::string& sdc_dir,
       print_pnr_sdc_constrain_cb_mux_timing(fp,
                                             module_manager, cb_module, 
                                             rr_graph, rr_gsb, cb_type,
-                                            ipin_rr_node);
+                                            ipin_rr_node,
+                                            constrain_zero_delay_paths);
     }
   }
 
@@ -342,7 +362,8 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_di
                                                        const ModuleManager& module_manager, 
                                                        const RRGraph& rr_graph,
                                                        const DeviceRRGSB& device_rr_gsb,
-                                                       const t_rr_type& cb_type) {
+                                                       const t_rr_type& cb_type,
+                                                       const bool& constrain_zero_delay_paths) {
   /* Build unique X-direction connection block modules */
   vtr::Point<size_t> cb_range = device_rr_gsb.get_gsb_range();
 
@@ -360,7 +381,8 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_di
                                         module_manager,
                                         rr_graph, 
                                         rr_gsb, 
-                                        cb_type);
+                                        cb_type,
+                                        constrain_zero_delay_paths);
 
     }
   }
@@ -373,7 +395,8 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_di
 void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_dir,
                                                        const ModuleManager& module_manager, 
                                                        const RRGraph& rr_graph,
-                                                       const DeviceRRGSB& device_rr_gsb) {
+                                                       const DeviceRRGSB& device_rr_gsb,
+                                                       const bool& constrain_zero_delay_paths) {
 
   /* Start time count */
   vtr::ScopedStartFinishTimer timer("Write SDC for constrain Connection Block timing for P&R flow");
@@ -381,12 +404,14 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_di
   print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_dir, module_manager, 
                                                     rr_graph,
                                                     device_rr_gsb,
-                                                    CHANX);
+                                                    CHANX,
+                                                    constrain_zero_delay_paths);
 
   print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_dir, module_manager, 
                                                     rr_graph,
                                                     device_rr_gsb,
-                                                    CHANY);
+                                                    CHANY,
+                                                    constrain_zero_delay_paths);
 }
 
 /********************************************************************
@@ -396,7 +421,8 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_di
 void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_dir,
                                                        const ModuleManager& module_manager,
                                                        const RRGraph& rr_graph,
-                                                       const DeviceRRGSB& device_rr_gsb) {
+                                                       const DeviceRRGSB& device_rr_gsb,
+                                                       const bool& constrain_zero_delay_paths) {
 
   /* Start time count */
   vtr::ScopedStartFinishTimer timer("Write SDC for constrain Connection Block timing for P&R flow");
@@ -408,7 +434,8 @@ void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_di
                                       module_manager,
                                       rr_graph, 
                                       unique_mirror, 
-                                      CHANX);
+                                      CHANX,
+                                      constrain_zero_delay_paths);
   }
 
   /* Print SDC for unique Y-direction connection block modules */
@@ -418,7 +445,8 @@ void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_di
                                       module_manager,
                                       rr_graph, 
                                       unique_mirror, 
-                                      CHANY);
+                                      CHANY,
+                                      constrain_zero_delay_paths);
   }
 }
 
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.h b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.h
index 65ce60ca8..0ced07938 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.h
+++ b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.h
@@ -20,22 +20,26 @@ namespace openfpga {
 void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_dir,
                                                        const ModuleManager& module_manager,
                                                        const RRGraph& rr_graph,
-                                                       const DeviceRRGSB& device_rr_gsb);
+                                                       const DeviceRRGSB& device_rr_gsb,
+                                                       const bool& constrain_zero_delay_paths);
 
 void print_pnr_sdc_compact_routing_constrain_sb_timing(const std::string& sdc_dir,
                                                        const ModuleManager& module_manager,
                                                        const RRGraph& rr_graph,
-                                                       const DeviceRRGSB& device_rr_gsb);
+                                                       const DeviceRRGSB& device_rr_gsb,
+                                                       const bool& constrain_zero_delay_paths);
 
 void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_dir,
                                                        const ModuleManager& module_manager, 
                                                        const RRGraph& rr_graph,
-                                                       const DeviceRRGSB& device_rr_gsb);
+                                                       const DeviceRRGSB& device_rr_gsb,
+                                                       const bool& constrain_zero_delay_paths);
 
 void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_dir,
                                                        const ModuleManager& module_manager,
                                                        const RRGraph& rr_graph,
-                                                       const DeviceRRGSB& device_rr_gsb);
+                                                       const DeviceRRGSB& device_rr_gsb,
+                                                       const bool& constrain_zero_delay_paths);
 
 } /* end namespace openfpga */
 
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
index b005ca6ce..b7ac5bb43 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
+++ b/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
@@ -296,13 +296,15 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options,
       print_pnr_sdc_compact_routing_constrain_sb_timing(sdc_options.sdc_dir(),
                                                         module_manager,
                                                         device_ctx.rr_graph,
-                                                        device_rr_gsb);
+                                                        device_rr_gsb,
+                                                        sdc_options.constrain_zero_delay_paths());
     } else {
 	  VTR_ASSERT_SAFE (false == compact_routing_hierarchy);
       print_pnr_sdc_flatten_routing_constrain_sb_timing(sdc_options.sdc_dir(),
                                                         module_manager,
                                                         device_ctx.rr_graph,
-                                                        device_rr_gsb);
+                                                        device_rr_gsb,
+                                                        sdc_options.constrain_zero_delay_paths());
     }
   }
 
@@ -312,13 +314,15 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options,
       print_pnr_sdc_compact_routing_constrain_cb_timing(sdc_options.sdc_dir(),
                                                         module_manager,
                                                         device_ctx.rr_graph,
-                                                        device_rr_gsb);
+                                                        device_rr_gsb,
+                                                        sdc_options.constrain_zero_delay_paths());
     } else {
 	  VTR_ASSERT_SAFE (false == compact_routing_hierarchy);
       print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_options.sdc_dir(),
                                                         module_manager, 
                                                         device_ctx.rr_graph,
-                                                        device_rr_gsb);
+                                                        device_rr_gsb,
+                                                        sdc_options.constrain_zero_delay_paths());
     }
   }
 
@@ -327,7 +331,8 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options,
     print_pnr_sdc_constrain_grid_timing(sdc_options.sdc_dir(),
                                         device_ctx,
                                         device_annotation,
-                                        module_manager);
+                                        module_manager,
+                                        sdc_options.constrain_zero_delay_paths());
   }
 }
 

From cb6afea07c87293fb4c0e0bc7080b3de28c7f39e Mon Sep 17 00:00:00 2001
From: Xifan Tang <tangxifan@gmail.com>
Date: Wed, 25 Mar 2020 16:00:25 -0600
Subject: [PATCH 347/645] update documentation on a new option in FPGA-SDC to
 constrain zero-delay paths

---
 docs/source/openfpga_shell/openfpga_commands.rst | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/docs/source/openfpga_shell/openfpga_commands.rst b/docs/source/openfpga_shell/openfpga_commands.rst
index fd44f6fbb..8f71cdb54 100644
--- a/docs/source/openfpga_shell/openfpga_commands.rst
+++ b/docs/source/openfpga_shell/openfpga_commands.rst
@@ -191,6 +191,10 @@ FPGA-SDC
   - ``--constrain_routing_multiplexer_outputs`` Constrain all the outputs of routing multiplexer of FPGA fabric
 
   - ``--constrain_switch_block_outputs`` Constrain all the outputs of switch blocks of FPGA fabric
+
+  - ``--constrain_zero_delay_paths`` Constrain all the zero-delay paths in FPGA fabric
+
+  .. note:: Zero-delay path may cause errors in some PnR tools as it is considered illegal
   
   - ``--verbose`` Enable verbose output
 

From b4221e94bbeb8864e37646f499a56b70351164a8 Mon Sep 17 00:00:00 2001
From: Xifan Tang <tangxifan@gmail.com>
Date: Wed, 25 Mar 2020 16:52:42 -0600
Subject: [PATCH 348/645] add documentation on the tileable routing and thru
 channel support

---
 docs/source/arch_lang/addon_vpr_syntax.rst    |  23 +++++++++++++++++-
 .../source/arch_lang/figures/thru_channel.png | Bin 0 -> 28647 bytes
 .../fpga_bitstream/file_organization.rst      |   2 +-
 docs/source/z_reference.bib                   |   9 +++++++
 4 files changed, 32 insertions(+), 2 deletions(-)
 create mode 100644 docs/source/arch_lang/figures/thru_channel.png

diff --git a/docs/source/arch_lang/addon_vpr_syntax.rst b/docs/source/arch_lang/addon_vpr_syntax.rst
index 7122c9870..3f51e005d 100644
--- a/docs/source/arch_lang/addon_vpr_syntax.rst
+++ b/docs/source/arch_lang/addon_vpr_syntax.rst
@@ -14,7 +14,28 @@ Each ``<pb_type>`` should contain a ``<mode>`` that describe the physical implem
 
 .. option:: tileable="<bool>"
 
-  Turn on/off tileable routing resource graph generator
+  Turn ``on``/``off`` tileable routing resource graph generator.
+  
+  Tileable routing architecture can minimize the number of unique modules in FPGA fabric to be physically implemented.
+
+  Technical details can be found in :cite:`XTang_FPT_2019`. 
+
+  .. note:: Strongly recommend to enable the tileable routing architecture when you want to PnR large FPGA fabrics, which can effectively reduce the runtime.
+
+.. option:: through_channel="<bool>"
+  
+  Allow routing channels to pass through multi-width and multi-height programable blocks. This is mainly used in heterogeneous FPGAs to increase routability, as illustrated in :numref:`fig_thru_channel`.
+  By default, it is ``off``.
+
+  .. _fig_thru_channel:
+  
+  .. figure:: ./figures/thru_channel.png
+     :scale: 80%
+     :alt: Impact of through channel
+  
+     Impact on routing architecture when through channel in multi-width and multi-height programmable blocks: (a) disabled; (b) enabled.
+
+  .. warning:: Do NOT enable if you are not using the tileable routing resource graph generator!
 
 ``<switch_block>`` may include addition syntax to enable different connectivity for pass tracks
 
diff --git a/docs/source/arch_lang/figures/thru_channel.png b/docs/source/arch_lang/figures/thru_channel.png
new file mode 100644
index 0000000000000000000000000000000000000000..26ba72ac7790539c59db15f1abee3a9d684448cc
GIT binary patch
literal 28647
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literal 0
HcmV?d00001

diff --git a/docs/source/fpga_bitstream/file_organization.rst b/docs/source/fpga_bitstream/file_organization.rst
index d8190ac67..91975fcc7 100644
--- a/docs/source/fpga_bitstream/file_organization.rst
+++ b/docs/source/fpga_bitstream/file_organization.rst
@@ -1,5 +1,5 @@
 Bitstream Output File Format
-~~~~~~~~~~~~~~~~~~~~~~~~~~~
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 FPGA-Bitstream can generate two types of bitstreams:
 
diff --git a/docs/source/z_reference.bib b/docs/source/z_reference.bib
index d087acd7d..3758761f8 100644
--- a/docs/source/z_reference.bib
+++ b/docs/source/z_reference.bib
@@ -95,3 +95,12 @@ doi={10.1109/FPL.2019.00065},
 ISSN={1946-147X},
 month={Sep.},}
 
+@INPROCEEDINGS{XTang_FPT_2019,
+author={X. Tang and E. Giacomin and A. Alacchi and P. Gaillardon},  
+booktitle={2019 International Conference on Field-Programmable Technology (ICFPT)}, 
+title={A Study on Switch Block Patterns for Tileable FPGA Routing Architectures},
+year={2019},
+volume={},
+number={},
+doi={10.1109/ICFPT47387.2019.00039},
+pages={247-250},}

From 3b3c39454b22977ce0999e979c7ffeffb95aa977 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 25 Mar 2020 17:55:28 -0600
Subject: [PATCH 349/645] update print_route() in VPR to show correct track_id
 when tileable routing is used

---
 vpr/src/route/route_common.cpp | 28 ++++++++++++++++++++++++++--
 1 file changed, 26 insertions(+), 2 deletions(-)

diff --git a/vpr/src/route/route_common.cpp b/vpr/src/route/route_common.cpp
index 4e1cda2ae..8fd661d05 100644
--- a/vpr/src/route/route_common.cpp
+++ b/vpr/src/route/route_common.cpp
@@ -1490,13 +1490,36 @@ void print_route(FILE* fp, const vtr::vector<ClusterNetId, t_traceback>& traceba
                             } else { /* IO Pad. */
                                 fprintf(fp, " Pin: ");
                             }
+                            fprintf(fp, "%d  ", device_ctx.rr_graph.node_pin_num(inode));
                             break;
 
                         case CHANX:
                         case CHANY:
                             fprintf(fp, " Track: ");
+                            /* Xifan Tang:
+                             * The routing track id depends on the direction
+                             * A routing track may have multiple track ids
+                             * The track id is the starting point of a routing track
+                             *   - INC_DIRECTION: the first track id in the list
+                             *   - DEC_DIRECTION: the last track id in the list
+                             * 
+                             * This is because (xlow, ylow) is always < (xhigh, yhigh)
+                             * which is even true for DEC_DIRECTION routing tracks
+                             */
+                            if (1 < device_ctx.rr_graph.node_track_ids(inode).size()) {
+                                fprintf(fp, "(");
+                                for (size_t itrack = 0; itrack < device_ctx.rr_graph.node_track_ids(inode).size(); ++itrack) {
+                                    if (0 < itrack) {
+                                      fprintf(fp, ", ");
+                                    }
+                                    fprintf(fp, "%d", device_ctx.rr_graph.node_track_ids(inode)[itrack]);
+                                }
+                                fprintf(fp, ")  ");
+                            } else {
+                                VTR_ASSERT(1 == device_ctx.rr_graph.node_track_ids(inode).size());
+                                fprintf(fp, "%d  ", device_ctx.rr_graph.node_track_num(inode));
+                            }
                             break;
-
                         case SOURCE:
                         case SINK:
                             if (is_io_type(device_ctx.grid[ilow][jlow].type)) {
@@ -1504,6 +1527,7 @@ void print_route(FILE* fp, const vtr::vector<ClusterNetId, t_traceback>& traceba
                             } else { /* IO Pad. */
                                 fprintf(fp, " Class: ");
                             }
+                            fprintf(fp, "%d  ", device_ctx.rr_graph.node_class_num(inode));
                             break;
 
                         default:
@@ -1513,7 +1537,7 @@ void print_route(FILE* fp, const vtr::vector<ClusterNetId, t_traceback>& traceba
                             break;
                     }
 
-                    fprintf(fp, "%d  ", device_ctx.rr_graph.node_ptc_num(inode));
+                    //fprintf(fp, "%d  ", device_ctx.rr_graph.node_ptc_num(inode));
 
                     if (!is_io_type(device_ctx.grid[ilow][jlow].type) && (rr_type == IPIN || rr_type == OPIN)) {
                         int pin_num = device_ctx.rr_graph.node_ptc_num(inode);

From 91a618466db0bb57e2f5151b3ca30c39e8b49c70 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 27 Mar 2020 10:52:48 -0600
Subject: [PATCH 350/645] bug fixing for rr_graph.clear() function

---
 openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml | 2 +-
 vpr/src/device/rr_graph_obj.cpp                                | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml
index 9422c3a09..7e4cf8e7a 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml
@@ -193,7 +193,7 @@
   </tiles>
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
-  <layout tileable="true" through_channel="false">
+  <layout tileable="true" through_channel="true">
     <!--auto_layout aspect_ratio="1.0"-->
     <fixed_layout name="4x4" width="5" height="4">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
diff --git a/vpr/src/device/rr_graph_obj.cpp b/vpr/src/device/rr_graph_obj.cpp
index 4a6ca1256..07395cee5 100644
--- a/vpr/src/device/rr_graph_obj.cpp
+++ b/vpr/src/device/rr_graph_obj.cpp
@@ -1500,6 +1500,7 @@ void RRGraph::clear_nodes() {
     node_sides_.clear();
     node_Rs_.clear();
     node_Cs_.clear();
+    node_rc_data_indices_.clear();
     node_segments_.clear();
 
     node_num_in_edges_.clear();

From 5ce078fe60190d0f88816bae66e27902b2b0fcff Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 27 Mar 2020 11:26:14 -0600
Subject: [PATCH 351/645] minor fix on rr_graph.clear()

---
 vpr/src/device/rr_graph_obj.cpp | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/vpr/src/device/rr_graph_obj.cpp b/vpr/src/device/rr_graph_obj.cpp
index 07395cee5..de8706de7 100644
--- a/vpr/src/device/rr_graph_obj.cpp
+++ b/vpr/src/device/rr_graph_obj.cpp
@@ -1011,7 +1011,7 @@ void RRGraph::set_node_ptc_num(const RRNodeId& node, const short& ptc) {
      */
     if ((CHANX == node_type(node)) || (CHANY == node_type(node))) {
         if ((size_t)node_length(node) + 1 != node_ptc_nums_[node].size()) {
-            node_ptc_nums_[node].resize(node_length(node) + 1);
+            node_ptc_nums_[node].resize((size_t)node_length(node) + 1);
         }
         std::fill(node_ptc_nums_[node].begin(), node_ptc_nums_[node].end(), ptc);
     } else {
@@ -1048,7 +1048,7 @@ void RRGraph::add_node_track_num(const RRNodeId& node,
     VTR_ASSERT_MSG(node_type(node) == CHANX || node_type(node) == CHANY, "Track number valid only for CHANX/CHANY RR nodes");
 
     if ((size_t)node_length(node) + 1 != node_ptc_nums_[node].size()) {
-        node_ptc_nums_[node].resize(node_length(node) + 1);
+        node_ptc_nums_[node].resize((size_t)node_length(node) + 1);
     }
 
     size_t offset = node_offset.x() - node_xlow(node) + node_offset.y() - node_ylow(node);
@@ -1540,4 +1540,14 @@ void RRGraph::clear() {
     clear_edges();
     clear_switches();
     clear_segments();
+
+    invalidate_fast_node_lookup();
+
+    /* Clear invalid node list */
+    invalid_node_ids_.clear();
+
+    /* Clear invalid edge list */
+    invalid_edge_ids_.clear();
+
+    clear_dirty();
 }

From e47a0a442285b2b458e2d6a95ca7b581bf11d14f Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 27 Mar 2020 11:32:44 -0600
Subject: [PATCH 352/645] add through channel architecture example

---
 .../k6_frac_N10_adder_chain_mem16K_40nm.xml   |   2 +-
 ...0_adder_chain_mem16K_thru_channel_40nm.xml | 734 ++++++++++++++++++
 2 files changed, 735 insertions(+), 1 deletion(-)
 create mode 100644 openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_thru_channel_40nm.xml

diff --git a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml
index 7e4cf8e7a..9422c3a09 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml
@@ -193,7 +193,7 @@
   </tiles>
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
-  <layout tileable="true" through_channel="true">
+  <layout tileable="true" through_channel="false">
     <!--auto_layout aspect_ratio="1.0"-->
     <fixed_layout name="4x4" width="5" height="4">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_thru_channel_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_thru_channel_40nm.xml
new file mode 100644
index 000000000..7e4cf8e7a
--- /dev/null
+++ b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_thru_channel_40nm.xml
@@ -0,0 +1,734 @@
+<!-- 
+  Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with 8 total FLE inputs (2 inputs of which are shared by the 5-LUTs) 
+    with optionally registered outputs
+    Each 5-LUT has an arithemtic mode that converts it to a single-bit adder with both inputs driven by 4-LUTs (both 4-LUTs share all 4 inputs)
+    Carry chain links to vertically adjacent logic blocks
+  - Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.  
+    Height = 6, found on every (8n+2)th column
+  - Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.  
+    Height = 4, found on every (8n+6)th column
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Details on Modelling:
+
+  The electrical design of the architecture described here is NOT from an 
+  optimized, SPICED architecture.  Instead, we attempt to create a reasonable 
+  architecture file by using an existing commercial FPGA to approximate the area, 
+  delay, and power of the underlying components. This is combined with a reasonable 40 nm 
+  model of wiring and circuit design for low-level routing components, where available.
+  The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also 
+  has wiring electrical parameters that allow the wire lengths and switch patterns to be 
+  modified and you will still get reasonable delay results for the new architecture.
+  The following describes, in detail, how we obtained the various electrical values for this 
+  architecture.
+
+  Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar 
+  architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture. 
+  (n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)      
+  This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to 
+  match the overall target (a 40 nm FPGA).
+
+  We obtain delay numbers by measuring delays of routing, soft logic blocks, 
+  memories, and multipliers from test circuits on a Stratix IV GX device 
+  (EP4SGX230DF29C2X, i.e. fastest speed grade). For routing, we took the average delay of H4 and V4 
+  wires.  Rmetal and Cmetal values for the routing wires were obtained from work done by Charles 
+  Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal stack 40 nm routing) and 
+  take the R and C data from the ITRS roadmap.  
+
+  For the general purpose logic block, we assume that the area and delays of the Stratix IV 
+  crossbar is close enough to the crossbar modelled here.  
+  Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to 
+  36:1 multiplexers.  We match these parameters in this architecture.
+
+  For LUTs, we include LUT 
+  delays measured from Stratix IV which is dependant on the input used (ie. some 
+  LUT inputs are faster than others).  The CAD tools at the time of VTR 7 does 
+  not consider differences in LUT input delays.
+
+  Adder delays obtained as approximate values from a Stratix IV EP4SE230F29C3 device.  
+  Delay obtained by compiling a 256 bit adder (registered inputs and outputs, 
+  all pins except clock virtual) then measuring the delays in chip-planner, 
+  sumout delay = 0.271ns to 0.348 ns, intra-block carry delay = 0.011 ns, 
+  inter-block carry delay = 0.327 ns.  Given this data, I will approximate 
+  sumout 0.3 ns, intra-block carry-delay = 0.01 ns, and 
+  inter-block carry-delay = 0.16 ns (since Altera inter-block carry delay has 
+  overhead that we don't have, I'll approximate the delay of a simpler chain at 
+  one half what they have.  This is very rough, anything from 0.01ns to 0.327ns 
+  can be justified).
+
+  Logic block area numbers obtained by scaling overall tile area of a 65nm 
+  Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out 
+  routing area at a channel width of 300. We use a channel width of 300 because it can route 
+  all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
+  total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
+  choosing a width that provides high routability. The architecture can be routed at different channel
+  widths, but we estimate the tile size and hence the physical length of routing wires assuming
+  a channel width of 300.
+
+  Sanity checks employed:
+    1.  We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches 
+        common electrical design.
+
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <model name="adder">
+      <input_ports>
+        <port name="a" combinational_sink_ports="sumout cout"/>
+        <port name="b" combinational_sink_ports="sumout cout"/>
+        <port name="cin" combinational_sink_ports="sumout cout"/>
+      </input_ports>
+      <output_ports>
+        <port name="cout"/>
+        <port name="sumout"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="frac_lut6">
+      <input_ports>
+        <port name="in"/>
+      </input_ports>
+      <output_ports>
+        <port name="lut4_out"/>
+        <port name="lut5_out"/>
+        <port name="lut6_out"/>
+      </output_ports>
+    </model>
+    <model name="dual_port_ram">
+      <input_ports>
+        <!-- write address lines -->
+        <port name="waddr" clock="clk"/>
+        <!-- read address lines -->
+        <port name="raddr" clock="clk"/>
+        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
+        <port name="d_in" clock="clk"/>
+        <!-- write enable -->
+        <port name="wen" clock="clk"/>
+        <!-- read enable -->
+        <port name="ren" clock="clk"/>
+        <!-- memories are often clocked -->
+        <port name="clk" is_clock="1"/>
+      </input_ports>
+      <output_ports>
+        <!-- output can be broken down into smaller bit widths minimum size 1 -->
+        <port name="d_out" clock="clk"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <tile name="io" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad</loc>
+        <loc side="top">io.outpad io.inpad</loc>
+        <loc side="right">io.outpad io.inpad</loc>
+        <loc side="bottom">io.outpad io.inpad</loc>
+      </pinlocations>
+    </tile>
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
+      </fc>
+      <!--  Highly recommand to customize pin location when direct connection is used!!! -->
+      <!--pinlocations pattern="spread"/-->
+      <pinlocations pattern="custom">
+        <loc side="left">clb.clk</loc>
+        <loc side="top">clb.cin</loc>
+        <loc side="right">clb.O[9:0] clb.I[19:0]</loc>
+        <loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
+      </pinlocations>
+    </tile>
+    <tile name="memory" height="2" area="548000">
+      <equivalent_sites>
+        <site pb_type="memory"/>
+      </equivalent_sites>
+      <input name="waddr" num_pins="10"/>
+      <input name="raddr" num_pins="10"/>
+      <input name="d_in" num_pins="32"/>
+      <input name="wen" num_pins="1"/>
+      <input name="ren" num_pins="1"/>
+      <output name="d_out" num_pins="32"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="spread"/>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout tileable="true" through_channel="true">
+    <!--auto_layout aspect_ratio="1.0"-->
+    <fixed_layout name="4x4" width="5" height="4">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
+      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
+    </fixed_layout>
+    <!-- /auto_layout -->
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	    -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+           book area formula. This means the mux transistors are about 5x minimum drive strength.
+           We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+           mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+           the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+           by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+           buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+           I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+           (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+           The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+           2.5x when looking up in Jeff's tables.
+           Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+           This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+             With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+             reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <directlist>
+    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
+  </directlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+
+      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+           If you need to register the I/O, define clocks in the circuit models
+           These clocks can be handled in back-end
+       -->
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" disabled_in_pack="true">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe fracturable logic element.  
+             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
+             The outputs of the fracturable logic element can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="10">
+        <input name="in" num_pins="6"/>
+        <input name="cin" num_pins="1"/>
+        <output name="out" num_pins="2"/>
+        <output name="cout" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- Physical mode definition begin (physical implementation of the fle) -->
+        <mode name="physical" disabled_in_pack="true">
+          <pb_type name="fabric" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="frac_logic" num_pb="1">
+              <input name="in" num_pins="6"/>
+              <output name="lut4_out" num_pins="4"/>
+              <output name="out" num_pins="2"/>
+              <!-- Define LUT -->
+              <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
+                <input name="in" num_pins="6"/>
+                <output name="lut4_out" num_pins="4"/>
+                <output name="lut5_out" num_pins="2"/>
+                <output name="lut6_out" num_pins="1"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
+                <direct name="direct2" input="frac_lut6.lut4_out" output="frac_logic.lut4_out"/>
+                <direct name="direct3" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
+                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
+                <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
+              </interconnect>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>         
+            <!-- Define adders -->
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="2">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
+              <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
+              <direct name="direct3" input="fabric.cin" output="adder[0:0].cin"/>
+              <direct name="direct4" input="adder[0:0].cout" output="adder[1:1].cin"/>
+              <direct name="direct5" input="adder[1:1].cout" output="fabric.cout"/>
+              <direct name="direct6" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
+              <direct name="direct7" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
+              <direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
+              <direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
+              <complete name="direct10" input="fabric.clk" output="ff[1:0].clk"/>
+              <mux name="mux1" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
+                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
+              </mux>
+              <mux name="mux2" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
+                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="fabric.in"/>
+            <direct name="direct2" input="fle.cin" output="fabric.cin"/>
+            <direct name="direct3" input="fabric.out" output="fle.out"/>
+            <direct name="direct4" input="fabric.cout" output="fle.cout"/>
+            <direct name="direct5" input="fle.clk" output="fabric.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Physical mode definition end (physical implementation of the fle) -->
+        <!-- BEGIN fle mode of dual lut5 -->
+        <mode name="n2_lut5">
+          <pb_type name="ble5" num_pb="2">
+            <input name="in" num_pins="5"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Regular LUT mode -->
+            <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="5" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                  we instead take the average of these numbers to get more stable results
+                82e-12
+                173e-12
+                261e-12
+                263e-12
+                398e-12
+                -->
+              <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+              </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble5.in" output="lut5.in"/>
+              <direct name="direct2" input="lut5.out" output="ff.D">
+                <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble5.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut5.out" output="ble5.out">
+                <delay_constant max="25e-12" in_port="lut5.out" out_port="ble5.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble5.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[4:0]" output="ble5[0:0].in"/>
+            <direct name="direct2" input="fle.in[4:0]" output="ble5[1:1].in"/>
+            <complete name="direct3" input="fle.clk" output="ble5.clk"/>
+            <direct name="direct4" input="ble5.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- END fle mode of dual lut5 -->
+        <!-- BEGIN arithmetic mode of dual lut4 + adders -->
+        <mode name="arithmetic">
+          <pb_type name="arithmetic" num_pb="2">
+            <input name="in" num_pins="4"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="1"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Special dual-LUT mode that drives adder only -->
+            <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
+              <input name="in" num_pins="4" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  -->
+              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                  195e-12
+                  195e-12
+                  195e-12
+                  195e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
+              <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
+              <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
+              <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
+                </direct>
+              <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
+                </direct>
+              <direct name="add_to_ff" input="adder.sumout" output="ff.D">
+                <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
+              </direct>
+              <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
+                <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
+              </direct>
+              <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
+                <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
+              </direct>
+              <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
+                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[3:0]" output="arithmetic[0:0].in"/>
+            <direct name="direct2" input="fle.in[3:0]" output="arithmetic[1:1].in"/>
+            <direct name="carry_in" input="fle.cin" output="arithmetic[0:0].cin">
+              <pack_pattern name="chain" in_port="fle.cin" out_port="arithmetic[0:0].cin"/>
+            </direct>
+            <direct name="carry_inter" input="arithmetic[0:0].cout" output="arithmetic[1:1].cin">
+              <pack_pattern name="chain" in_port="arithmetic[0:0].cout" out_port="arithmetic[1:1].cin"/>
+            </direct>
+            <direct name="carry_out" input="arithmetic[1:1].cout" output="fle.cout">
+              <pack_pattern name="chain" in_port="arithmetic.cout" out_port="fle.cout"/>
+            </direct>
+            <complete name="direct3" input="fle.clk" output="arithmetic.clk"/>
+            <direct name="direct4" input="arithmetic.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- n2_lut5 -->
+        <mode name="n1_lut6">
+          <pb_type name="ble6" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="6" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->
+              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+              <direct name="direct2" input="lut6.out" output="ff.D">
+                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
+            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+          </interconnect>
+        </mode>
+        <!-- n1_lut6 -->
+      </pb_type>
+      <interconnect>
+        <!-- We use a 50% depop crossbar built using small full xbars to get sets of logically equivalent pins at inputs of CLB 
+           The delays below come from Stratix IV. the delay through a connection block
+           input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+           delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+           delay within the crossbar is 95 ps. 
+           The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+           Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+           25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+           to get the part that should be marked on the crossbar.	 -->
+        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
+          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
+          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
+        </complete>
+
+        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+        </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+                 By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+                 then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+                 naive specification).
+          -->
+        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
+        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
+        <!-- Carry chain links -->
+        <direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
+          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
+        </direct>
+        <direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
+          <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
+        </direct>
+        <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
+          <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
+        </direct>
+      </interconnect>
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+    <!-- Define single-mode dual-port memory begin -->
+    <pb_type name="memory">
+      <input name="waddr" num_pins="10"/>
+      <input name="raddr" num_pins="10"/>
+      <input name="d_in" num_pins="32"/>
+      <input name="wen" num_pins="1"/>
+      <input name="ren" num_pins="1"/>
+      <output name="d_out" num_pins="32"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Specify the 512x32=16Kbit memory block
+           Note: the delay numbers are extracted from VPR flagship XML without modification
+                 Should align to the process technology we using to create the 16K dual-port RAM
+        -->
+      <mode name="mem_512x32_dp">
+        <pb_type name="mem_512x32_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
+          <input name="waddr" num_pins="10" port_class="address"/>
+          <input name="raddr" num_pins="10" port_class="address"/>
+          <input name="d_in" num_pins="32" port_class="data_in"/>
+          <input name="wen" num_pins="1" port_class="write_en"/>
+          <input name="ren" num_pins="1" port_class="write_en"/>
+          <output name="d_out" num_pins="32" port_class="data_out"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.waddr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.raddr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.d_in" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.wen" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.ren" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_512x32_dp.d_out" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="17.9e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="waddress" input="memory.waddr" output="mem_512x32_dp.waddr">
+            <delay_constant max="132e-12" in_port="memory.waddr" out_port="mem_512x32_dp.waddr"/>
+          </direct>
+          <direct name="raddress" input="memory.raddr" output="mem_512x32_dp.raddr">
+            <delay_constant max="132e-12" in_port="memory.raddr" out_port="mem_512x32_dp.raddr"/>
+          </direct>
+          <direct name="data_input" input="memory.d_in" output="mem_512x32_dp.d_in">
+            <delay_constant max="132e-12" in_port="memory.d_in" out_port="mem_512x32_dp.d_in"/>
+          </direct>
+          <direct name="writeen" input="memory.wen" output="mem_512x32_dp.wen">
+            <delay_constant max="132e-12" in_port="memory.wen" out_port="mem_512x32_dp.wen"/>
+          </direct>
+          <direct name="readen" input="memory.ren" output="mem_512x32_dp.ren">
+            <delay_constant max="132e-12" in_port="memory.ren" out_port="mem_512x32_dp.ren"/>
+          </direct>
+          <direct name="dataout" input="mem_512x32_dp.d_out" output="memory.d_out">
+            <delay_constant max="40e-12" in_port="mem_512x32_dp.d_out" out_port="memory.d_out"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_512x32_dp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+    </pb_type>
+    <!-- Define single-mode dual-port memory end -->
+  </complexblocklist>
+</architecture>

From 78964ce71c66362f1c389c64a44d941aade00db3 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 27 Mar 2020 11:34:39 -0600
Subject: [PATCH 353/645] update documentation on the through channel

---
 docs/source/arch_lang/addon_vpr_syntax.rst | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/docs/source/arch_lang/addon_vpr_syntax.rst b/docs/source/arch_lang/addon_vpr_syntax.rst
index 3f51e005d..1e2da988f 100644
--- a/docs/source/arch_lang/addon_vpr_syntax.rst
+++ b/docs/source/arch_lang/addon_vpr_syntax.rst
@@ -37,6 +37,8 @@ Each ``<pb_type>`` should contain a ``<mode>`` that describe the physical implem
 
   .. warning:: Do NOT enable if you are not using the tileable routing resource graph generator!
 
+  .. warning:: Current through channel supports only a fixed routing channel!
+
 ``<switch_block>`` may include addition syntax to enable different connectivity for pass tracks
 
 .. option:: sub_type="<string>"

From b09b051249090a090d890d934ae96f1c99b71880 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 27 Mar 2020 13:58:35 -0600
Subject: [PATCH 354/645] add all the test cases considering tileable, carry
 chain, direct connection and memory blocks

---
 .../test_script/and_k6_frac_tileable.openfpga |   59 +
 .../and_k6_frac_tileable_adder_chain.openfpga |   62 +
 ..._frac_tileable_adder_chain_mem16K.openfpga |   62 +
 ...e_thru_channel_adder_chain_mem16K.openfpga |   62 +
 .../and_latch_k6_frac_tileable.openfpga       |   59 +
 ...atch_k6_frac_tileable_adder_chain.openfpga |   62 +
 ..._frac_tileable_adder_chain_mem16K.openfpga |   62 +
 openfpga/test_vpr_arch/k6_N10_40nm.xml        |    2 +-
 .../test_vpr_arch/k6_N10_tileable_40nm.xml    |  299 ++++
 openfpga/test_vpr_arch/k6_frac_N10_40nm.xml   |    2 +-
 .../k6_frac_N10_adder_chain_40nm.xml          |    2 +-
 .../k6_frac_N10_adder_chain_mem16K_40nm.xml   |    2 +-
 ...rac_N10_frac_chain_depop50_mem32K_40nm.xml | 1429 -----------------
 .../k6_frac_N10_tileable_40nm.xml             |  441 +++++
 .../k6_frac_N10_tileable_adder_chain_40nm.xml |  639 ++++++++
 ...c_N10_tileable_adder_chain_mem16K_40nm.xml |  734 +++++++++
 ..._thru_channel_adder_chain_mem16K_40nm.xml} |    0
 17 files changed, 2545 insertions(+), 1433 deletions(-)
 create mode 100644 openfpga/test_script/and_k6_frac_tileable.openfpga
 create mode 100644 openfpga/test_script/and_k6_frac_tileable_adder_chain.openfpga
 create mode 100644 openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K.openfpga
 create mode 100644 openfpga/test_script/and_k6_frac_tileable_thru_channel_adder_chain_mem16K.openfpga
 create mode 100644 openfpga/test_script/and_latch_k6_frac_tileable.openfpga
 create mode 100644 openfpga/test_script/and_latch_k6_frac_tileable_adder_chain.openfpga
 create mode 100644 openfpga/test_script/and_latch_k6_frac_tileable_adder_chain_mem16K.openfpga
 create mode 100644 openfpga/test_vpr_arch/k6_N10_tileable_40nm.xml
 delete mode 100644 openfpga/test_vpr_arch/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml
 create mode 100644 openfpga/test_vpr_arch/k6_frac_N10_tileable_40nm.xml
 create mode 100644 openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml
 create mode 100644 openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml
 rename openfpga/test_vpr_arch/{k6_frac_N10_adder_chain_mem16K_thru_channel_40nm.xml => k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml} (100%)

diff --git a/openfpga/test_script/and_k6_frac_tileable.openfpga b/openfpga/test_script/and_k6_frac_tileable.openfpga
new file mode 100644
index 000000000..0731e6543
--- /dev/null
+++ b/openfpga/test_script/and_k6_frac_tileable.openfpga
@@ -0,0 +1,59 @@
+# Run VPR for the 'and' design
+vpr ./test_vpr_arch/k6_frac_N10_tileable_40nm.xml ./test_blif/and.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+
+# Write out the architecture XML as a proof
+#write_openfpga_arch -f ./arch_echo.xml
+
+# Annotate the OpenFPGA architecture to VPR data base
+link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to clustering nets based on routing results
+pb_pin_fixup --verbose
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup #--verbose
+
+# Build the module graph 
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules 
+build_fabric --compress_routing --duplicate_grid_pin #--verbose
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream 
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here 
+write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
+
+# Finish and exit OpenFPGA
+exit
diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_chain.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_chain.openfpga
new file mode 100644
index 000000000..77fa29aa1
--- /dev/null
+++ b/openfpga/test_script/and_k6_frac_tileable_adder_chain.openfpga
@@ -0,0 +1,62 @@
+# Run VPR for the 'and' design
+vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
+
+# Write out the architecture XML as a proof
+#write_openfpga_arch -f ./arch_echo.xml
+
+# Annotate the OpenFPGA architecture to VPR data base
+link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose
+
+# Write GSB to XML for debugging
+write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to clustering nets based on routing results
+pb_pin_fixup --verbose
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup #--verbose
+
+# Build the module graph 
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules 
+build_fabric --compress_routing --duplicate_grid_pin --verbose
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream 
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here 
+write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
+
+# Finish and exit OpenFPGA
+exit
diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K.openfpga
new file mode 100644
index 000000000..ed0d8cc5a
--- /dev/null
+++ b/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K.openfpga
@@ -0,0 +1,62 @@
+# Run VPR for the 'and' design
+vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
+
+# Write out the architecture XML as a proof
+#write_openfpga_arch -f ./arch_echo.xml
+
+# Annotate the OpenFPGA architecture to VPR data base
+link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose
+
+# Write GSB to XML for debugging
+write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to clustering nets based on routing results
+pb_pin_fixup --verbose
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup #--verbose
+
+# Build the module graph 
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules 
+build_fabric --compress_routing --duplicate_grid_pin --verbose
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream 
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here 
+write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
+
+# Finish and exit OpenFPGA
+exit
diff --git a/openfpga/test_script/and_k6_frac_tileable_thru_channel_adder_chain_mem16K.openfpga b/openfpga/test_script/and_k6_frac_tileable_thru_channel_adder_chain_mem16K.openfpga
new file mode 100644
index 000000000..5b1177586
--- /dev/null
+++ b/openfpga/test_script/and_k6_frac_tileable_thru_channel_adder_chain_mem16K.openfpga
@@ -0,0 +1,62 @@
+# Run VPR for the 'and' design
+vpr ./test_vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
+
+# Write out the architecture XML as a proof
+#write_openfpga_arch -f ./arch_echo.xml
+
+# Annotate the OpenFPGA architecture to VPR data base
+link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose
+
+# Write GSB to XML for debugging
+write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to clustering nets based on routing results
+pb_pin_fixup --verbose
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup #--verbose
+
+# Build the module graph 
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules 
+build_fabric --compress_routing --duplicate_grid_pin --verbose
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream 
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here 
+write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
+
+# Finish and exit OpenFPGA
+exit
diff --git a/openfpga/test_script/and_latch_k6_frac_tileable.openfpga b/openfpga/test_script/and_latch_k6_frac_tileable.openfpga
new file mode 100644
index 000000000..c89174d2d
--- /dev/null
+++ b/openfpga/test_script/and_latch_k6_frac_tileable.openfpga
@@ -0,0 +1,59 @@
+# Run VPR for the 'and_latch' design
+vpr ./test_vpr_arch/k6_frac_N10_tileable_40nm.xml ./test_blif/and_latch.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+
+# Write out the architecture XML as a proof
+#write_openfpga_arch -f ./arch_echo.xml
+
+# Annotate the OpenFPGA architecture to VPR data base
+link_openfpga_arch --activity_file ./test_blif/and_latch.act --sort_gsb_chan_node_in_edges #--verbose
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to clustering nets based on routing results
+pb_pin_fixup --verbose
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup #--verbose
+
+# Build the module graph 
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules 
+build_fabric --compress_routing --duplicate_grid_pin #--verbose
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack --verbose
+
+# Build the bitstream 
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and_latch.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here 
+write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
+
+# Finish and exit OpenFPGA
+exit
diff --git a/openfpga/test_script/and_latch_k6_frac_tileable_adder_chain.openfpga b/openfpga/test_script/and_latch_k6_frac_tileable_adder_chain.openfpga
new file mode 100644
index 000000000..ef49426d0
--- /dev/null
+++ b/openfpga/test_script/and_latch_k6_frac_tileable_adder_chain.openfpga
@@ -0,0 +1,62 @@
+# Run VPR for the 'and' design
+vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml ./test_blif/and_latch.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
+
+# Write out the architecture XML as a proof
+#write_openfpga_arch -f ./arch_echo.xml
+
+# Annotate the OpenFPGA architecture to VPR data base
+link_openfpga_arch --activity_file ./test_blif/and_latch.act --sort_gsb_chan_node_in_edges #--verbose
+
+# Write GSB to XML for debugging
+write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to clustering nets based on routing results
+pb_pin_fixup --verbose
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup #--verbose
+
+# Build the module graph 
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules 
+build_fabric --compress_routing --duplicate_grid_pin --verbose
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream 
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and_latch.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here 
+write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
+
+# Finish and exit OpenFPGA
+exit
diff --git a/openfpga/test_script/and_latch_k6_frac_tileable_adder_chain_mem16K.openfpga b/openfpga/test_script/and_latch_k6_frac_tileable_adder_chain_mem16K.openfpga
new file mode 100644
index 000000000..87c69c880
--- /dev/null
+++ b/openfpga/test_script/and_latch_k6_frac_tileable_adder_chain_mem16K.openfpga
@@ -0,0 +1,62 @@
+# Run VPR for the 'and' design
+vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml ./test_blif/and_latch.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
+
+# Write out the architecture XML as a proof
+#write_openfpga_arch -f ./arch_echo.xml
+
+# Annotate the OpenFPGA architecture to VPR data base
+link_openfpga_arch --activity_file ./test_blif/and_latch.act --sort_gsb_chan_node_in_edges #--verbose
+
+# Write GSB to XML for debugging
+write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to clustering nets based on routing results
+pb_pin_fixup --verbose
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup #--verbose
+
+# Build the module graph 
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules 
+build_fabric --compress_routing --duplicate_grid_pin --verbose
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream 
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and_latch.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here 
+write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
+
+# Finish and exit OpenFPGA
+exit
diff --git a/openfpga/test_vpr_arch/k6_N10_40nm.xml b/openfpga/test_vpr_arch/k6_N10_40nm.xml
index bbd694a79..630011e84 100644
--- a/openfpga/test_vpr_arch/k6_N10_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_N10_40nm.xml
@@ -63,7 +63,7 @@
   </tiles>
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
-  <layout>
+  <layout tileable="false">
     <auto_layout aspect_ratio="1.0">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
diff --git a/openfpga/test_vpr_arch/k6_N10_tileable_40nm.xml b/openfpga/test_vpr_arch/k6_N10_tileable_40nm.xml
new file mode 100644
index 000000000..d86d7aa62
--- /dev/null
+++ b/openfpga/test_vpr_arch/k6_N10_tileable_40nm.xml
@@ -0,0 +1,299 @@
+<!-- 
+  Architecture with no fracturable LUTs
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 6, N = 10
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Details on Modelling:
+
+  Based on flagship k6_frac_N10_mem32K_40nm.xml architecture.  This architecture has no fracturable LUTs nor any heterogeneous blocks.
+
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <tile name="io" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <clock name="clock" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad io.clock</loc>
+        <loc side="top">io.outpad io.inpad io.clock</loc>
+        <loc side="right">io.outpad io.inpad io.clock</loc>
+        <loc side="bottom">io.outpad io.inpad io.clock</loc>
+      </pinlocations>
+    </tile>
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I" num_pins="40" equivalent="full"/>
+      <output name="O" num_pins="10" equivalent="instance"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="spread"/>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout tileable="true">
+    <auto_layout aspect_ratio="1.0">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </auto_layout>
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	  -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+	       book area formula. This means the mux transistors are about 5x minimum drive strength.
+	       We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+	       mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+	       the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+	       by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+	       buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+	       I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+	       (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+	       The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+	       2.5x when looking up in Jeff's tables.
+	       Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+	       This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+			     With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+			     reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <clock name="clock" num_pins="1"/>
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" disabled_in_pack="true">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I" num_pins="40" equivalent="full"/>
+      <output name="O" num_pins="10" equivalent="instance"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe basic logic element.  
+             Each basic logic element has a 6-LUT that can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="10">
+        <input name="in" num_pins="6"/>
+        <output name="out" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- 6-LUT mode definition begin -->
+        <mode name="n1_lut6">
+          <!-- Define 6-LUT mode -->
+          <pb_type name="ble6" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Define LUT -->
+            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="6" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->
+              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                261e-12
+                261e-12
+                261e-12
+                261e-12
+                261e-12
+                261e-12
+              </delay_matrix>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+              <direct name="direct2" input="lut6.out" output="ff.D">
+                <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
+                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="ble6.in"/>
+            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+          </interconnect>
+        </mode>
+        <!-- 6-LUT mode definition end -->
+      </pb_type>
+      <interconnect>
+        <!-- We use a full crossbar to get logical equivalence at inputs of CLB 
+		     The delays below come from Stratix IV. the delay through a connection block
+		     input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+		     delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+		     delay within the crossbar is 95 ps. 
+		     The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+		     Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+		     25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+		     to get the part that should be marked on the crossbar.	 -->
+        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
+          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
+          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
+        </complete>
+        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+        </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+               By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+               then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+               naive specification).
+          -->
+        <direct name="clbouts1" input="fle[9:0].out" output="clb.O"/>
+      </interconnect>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- Place this general purpose logic block in any unspecified column -->
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+  </complexblocklist>
+</architecture>
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml
index 2c528c13c..ef9268810 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml
@@ -76,7 +76,7 @@
   </tiles>
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
-  <layout tileable="true">
+  <layout tileable="false">
     <!--auto_layout aspect_ratio="1.0"-->
     <fixed_layout name="2x2" width="4" height="4">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
index eea76837f..bbe041562 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
@@ -159,7 +159,7 @@
   </tiles>
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
-  <layout tileable="true">
+  <layout tileable="false">
     <!--auto_layout aspect_ratio="1.0"-->
     <fixed_layout name="4x4" width="6" height="6">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml
index 9422c3a09..850eb5450 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml
@@ -193,7 +193,7 @@
   </tiles>
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
-  <layout tileable="true" through_channel="false">
+  <layout tileable="false">
     <!--auto_layout aspect_ratio="1.0"-->
     <fixed_layout name="4x4" width="5" height="4">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml
deleted file mode 100644
index af4612b61..000000000
--- a/openfpga/test_vpr_arch/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml
+++ /dev/null
@@ -1,1429 +0,0 @@
-<!-- 
-  Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
-
-  - 40 nm technology
-  - General purpose logic block: 
-    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with 8 total FLE inputs (2 inputs of which are shared by the 5-LUTs) 
-    with optionally registered outputs
-    Each 5-LUT has an arithemtic mode that converts it to a single-bit adder with both inputs driven by 4-LUTs (both 4-LUTs share all 4 inputs)
-    Carry chain links to vertically adjacent logic blocks
-  - Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.  
-    Height = 6, found on every (8n+2)th column
-  - Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.  
-    Height = 4, found on every (8n+6)th column
-  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
-
-  Details on Modelling:
-
-  The electrical design of the architecture described here is NOT from an 
-  optimized, SPICED architecture.  Instead, we attempt to create a reasonable 
-  architecture file by using an existing commercial FPGA to approximate the area, 
-  delay, and power of the underlying components. This is combined with a reasonable 40 nm 
-  model of wiring and circuit design for low-level routing components, where available.
-  The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also 
-  has wiring electrical parameters that allow the wire lengths and switch patterns to be 
-  modified and you will still get reasonable delay results for the new architecture.
-  The following describes, in detail, how we obtained the various electrical values for this 
-  architecture.
-
-  Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar 
-  architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture. 
-  (n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)      
-  This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to 
-  match the overall target (a 40 nm FPGA).
-
-  We obtain delay numbers by measuring delays of routing, soft logic blocks, 
-  memories, and multipliers from test circuits on a Stratix IV GX device 
-  (EP4SGX230DF29C2X, i.e. fastest speed grade). For routing, we took the average delay of H4 and V4 
-  wires.  Rmetal and Cmetal values for the routing wires were obtained from work done by Charles 
-  Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal stack 40 nm routing) and 
-  take the R and C data from the ITRS roadmap.  
-
-  For the general purpose logic block, we assume that the area and delays of the Stratix IV 
-  crossbar is close enough to the crossbar modelled here.  
-  Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to 
-  36:1 multiplexers.  We match these parameters in this architecture.
-
-  For LUTs, we include LUT 
-  delays measured from Stratix IV which is dependant on the input used (ie. some 
-  LUT inputs are faster than others).  The CAD tools at the time of VTR 7 does 
-  not consider differences in LUT input delays.
-
-  Adder delays obtained as approximate values from a Stratix IV EP4SE230F29C3 device.  
-  Delay obtained by compiling a 256 bit adder (registered inputs and outputs, 
-  all pins except clock virtual) then measuring the delays in chip-planner, 
-  sumout delay = 0.271ns to 0.348 ns, intra-block carry delay = 0.011 ns, 
-  inter-block carry delay = 0.327 ns.  Given this data, I will approximate 
-  sumout 0.3 ns, intra-block carry-delay = 0.01 ns, and 
-  inter-block carry-delay = 0.16 ns (since Altera inter-block carry delay has 
-  overhead that we don't have, I'll approximate the delay of a simpler chain at 
-  one half what they have.  This is very rough, anything from 0.01ns to 0.327ns 
-  can be justified).
-
-  Logic block area numbers obtained by scaling overall tile area of a 65nm 
-  Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out 
-  routing area at a channel width of 300. We use a channel width of 300 because it can route 
-  all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
-  total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
-  choosing a width that provides high routability. The architecture can be routed at different channel
-  widths, but we estimate the tile size and hence the physical length of routing wires assuming
-  a channel width of 300.
-
-  Sanity checks employed:
-    1.  We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches 
-        common electrical design.
-
-
-  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
--->
-<architecture>
-  <!-- 
-       ODIN II specific config begins 
-       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
-       ".model [type_of_block]") that this architecture supports.
-
-       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
-       already special structures in blif (.names, .input, .output, and .latch) 
-       that describe them.
-  -->
-  <models>
-    <model name="multiply">
-      <input_ports>
-        <port name="a" combinational_sink_ports="out"/>
-        <port name="b" combinational_sink_ports="out"/>
-      </input_ports>
-      <output_ports>
-        <port name="out"/>
-      </output_ports>
-    </model>
-    <model name="single_port_ram">
-      <input_ports>
-        <port name="we" clock="clk"/>
-        <!-- control -->
-        <port name="addr" clock="clk"/>
-        <!-- address lines -->
-        <port name="data" clock="clk"/>
-        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
-        <port name="clk" is_clock="1"/>
-        <!-- memories are often clocked -->
-      </input_ports>
-      <output_ports>
-        <port name="out" clock="clk"/>
-        <!-- output can be broken down into smaller bit widths minimum size 1 -->
-      </output_ports>
-    </model>
-    <model name="dual_port_ram">
-      <input_ports>
-        <port name="we1" clock="clk"/>
-        <!-- write enable -->
-        <port name="we2" clock="clk"/>
-        <!-- write enable -->
-        <port name="addr1" clock="clk"/>
-        <!-- address lines -->
-        <port name="addr2" clock="clk"/>
-        <!-- address lines -->
-        <port name="data1" clock="clk"/>
-        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
-        <port name="data2" clock="clk"/>
-        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
-        <port name="clk" is_clock="1"/>
-        <!-- memories are often clocked -->
-      </input_ports>
-      <output_ports>
-        <port name="out1" clock="clk"/>
-        <!-- output can be broken down into smaller bit widths minimum size 1 -->
-        <port name="out2" clock="clk"/>
-        <!-- output can be broken down into smaller bit widths minimum size 1 -->
-      </output_ports>
-    </model>
-    <model name="adder">
-      <input_ports>
-        <port name="a" combinational_sink_ports="sumout cout"/>
-        <port name="b" combinational_sink_ports="sumout cout"/>
-        <port name="cin" combinational_sink_ports="sumout cout"/>
-      </input_ports>
-      <output_ports>
-        <port name="cout"/>
-        <port name="sumout"/>
-      </output_ports>
-    </model>
-  </models>
-  <tiles>
-    <tile name="io" capacity="8" area="0">
-      <equivalent_sites>
-        <site pb_type="io"/>
-      </equivalent_sites>
-      <input name="outpad" num_pins="1"/>
-      <output name="inpad" num_pins="1"/>
-      <clock name="clock" num_pins="1"/>
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
-      <pinlocations pattern="custom">
-        <loc side="left">io.outpad io.inpad io.clock</loc>
-        <loc side="top">io.outpad io.inpad io.clock</loc>
-        <loc side="right">io.outpad io.inpad io.clock</loc>
-        <loc side="bottom">io.outpad io.inpad io.clock</loc>
-      </pinlocations>
-    </tile>
-    <tile name="clb" area="53894">
-      <equivalent_sites>
-        <site pb_type="clb"/>
-      </equivalent_sites>
-      <input name="I1" num_pins="13" equivalent="full"/>
-      <input name="I2" num_pins="13" equivalent="full"/>
-      <input name="I3" num_pins="13" equivalent="full"/>
-      <input name="I4" num_pins="13" equivalent="full"/>
-      <input name="cin" num_pins="1"/>
-      <output name="O" num_pins="20" equivalent="none"/>
-      <output name="cout" num_pins="1"/>
-      <clock name="clk" num_pins="1"/>
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
-        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
-        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
-      </fc>
-      <pinlocations pattern="spread"/>
-    </tile>
-    <tile name="mult_36" height="4" area="396000">
-      <equivalent_sites>
-        <site pb_type="mult_36"/>
-      </equivalent_sites>
-      <input name="a" num_pins="36"/>
-      <input name="b" num_pins="36"/>
-      <output name="out" num_pins="72"/>
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
-      <pinlocations pattern="spread"/>
-    </tile>
-    <tile name="memory" height="6" area="548000">
-      <equivalent_sites>
-        <site pb_type="memory"/>
-      </equivalent_sites>
-      <input name="addr1" num_pins="15"/>
-      <input name="addr2" num_pins="15"/>
-      <input name="data" num_pins="64"/>
-      <input name="we1" num_pins="1"/>
-      <input name="we2" num_pins="1"/>
-      <output name="out" num_pins="64"/>
-      <clock name="clk" num_pins="1"/>
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
-      <pinlocations pattern="spread"/>
-    </tile>
-  </tiles>
-  <!-- ODIN II specific config ends -->
-  <!-- Physical descriptions begin -->
-  <layout>
-    <auto_layout aspect_ratio="1.0">
-      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
-      <perimeter type="io" priority="100"/>
-      <corners type="EMPTY" priority="101"/>
-      <!--Fill with 'clb'-->
-      <fill type="clb" priority="10"/>
-      <!--Column of 'mult_36' with 'EMPTY' blocks wherever a 'mult_36' does not fit. Vertical offset by 1 for perimeter.-->
-      <col type="mult_36" startx="6" starty="1" repeatx="8" priority="20"/>
-      <col type="EMPTY" startx="6" repeatx="8" starty="1" priority="19"/>
-      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
-      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
-      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
-    </auto_layout>
-  </layout>
-  <device>
-    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
-			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
-			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
-			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
-			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
-			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
-			     lined up with Stratix IV. 
-			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
-			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
-			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
-	                     by 2.5x when looking up in Jeff's tables.
-			     The delay values are lined up with Stratix IV, which has an architecture similar to this
-			     proposed FPGA, and which is also 40 nm 
-			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
-			     4x minimum drive strength buffer. -->
-    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
-    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
-     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
-	    -->
-    <area grid_logic_tile_area="0"/>
-    <chan_width_distr>
-      <x distr="uniform" peak="1.000000"/>
-      <y distr="uniform" peak="1.000000"/>
-    </chan_width_distr>
-    <switch_block type="wilton" fs="3"/>
-    <connection_block input_switch_name="ipin_cblock"/>
-  </device>
-  <switchlist>
-    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
-           book area formula. This means the mux transistors are about 5x minimum drive strength.
-           We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
-           mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
-           the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
-           by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
-           buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
-           I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
-           (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
-           The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
-           2.5x when looking up in Jeff's tables.
-           Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
-           This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
-    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
-    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
-    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
-  </switchlist>
-  <segmentlist>
-    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
-             With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
-             reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
-    <segment freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
-      <mux name="0"/>
-      <sb type="pattern">1 1 1 1 1</sb>
-      <cb type="pattern">1 1 1 1</cb>
-    </segment>
-  </segmentlist>
-  <directlist>
-    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
-  </directlist>
-  <complexblocklist>
-    <!-- Define I/O pads begin -->
-    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
-    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
-    <pb_type name="io">
-      <input name="outpad" num_pins="1"/>
-      <output name="inpad" num_pins="1"/>
-      <clock name="clock" num_pins="1"/>
-      <!-- IOs can operate as either inputs or outputs.
-	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
-	     the delays to and from registers in the I/O (and generally I/Os are registered 
-	     today and that is when you timing analyze them.
-	     -->
-      <mode name="inpad">
-        <pb_type name="inpad" blif_model=".input" num_pb="1">
-          <output name="inpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="inpad" input="inpad.inpad" output="io.inpad">
-            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-      <mode name="outpad">
-        <pb_type name="outpad" blif_model=".output" num_pb="1">
-          <input name="outpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="outpad" input="io.outpad" output="outpad.outpad">
-            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
-      <!-- IOs go on the periphery of the FPGA, for consistency, 
-          make it physically equivalent on all sides so that only one definition of I/Os is needed.
-          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
-        -->
-      <!-- Place I/Os on the sides of the FPGA -->
-      <power method="ignore"/>
-    </pb_type>
-    <!-- Define I/O pads ends -->
-    <!-- Define general purpose logic block (CLB) begin -->
-    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
-	   area is 60 L^2 yields a tile area of 84375 MWTAs.
-	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
-	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
-	   block. Note that the crossbar / local interconnect is considered part of the logic block
-	   area in this analysis. That is a lower proportion of of routing area than most academics
-	   assume, but note that the total routing area really includes the crossbar, which would push
-	   routing area up significantly, we estimate into the ~70% range. 
-	   -->
-    <pb_type name="clb">
-      <input name="I1" num_pins="13" equivalent="full"/>
-      <input name="I2" num_pins="13" equivalent="full"/>
-      <input name="I3" num_pins="13" equivalent="full"/>
-      <input name="I4" num_pins="13" equivalent="full"/>
-      <input name="cin" num_pins="1"/>
-      <output name="O" num_pins="20" equivalent="none"/>
-      <output name="cout" num_pins="1"/>
-      <clock name="clk" num_pins="1"/>
-      <!-- Describe fracturable logic element.  
-             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
-             The outputs of the fracturable logic element can be optionally registered
-        -->
-      <pb_type name="fle" num_pb="10">
-        <input name="in" num_pins="8"/>
-        <input name="cin" num_pins="1"/>
-        <output name="out" num_pins="2"/>
-        <output name="cout" num_pins="1"/>
-        <clock name="clk" num_pins="1"/>
-        <mode name="n2_lut5">
-          <pb_type name="lut5inter" num_pb="1">
-            <input name="in" num_pins="8"/>
-            <input name="cin" num_pins="1"/>
-            <output name="out" num_pins="2"/>
-            <output name="cout" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <pb_type name="ble5" num_pb="2">
-              <input name="in" num_pins="5"/>
-              <input name="cin" num_pins="1"/>
-              <output name="out" num_pins="1"/>
-              <output name="cout" num_pins="1"/>
-              <clock name="clk" num_pins="1"/>
-              <mode name="blut5">
-                <pb_type name="flut5" num_pb="1">
-                  <input name="in" num_pins="5"/>
-                  <output name="out" num_pins="1"/>
-                  <clock name="clk" num_pins="1"/>
-                  <!-- Regular LUT mode -->
-                  <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
-                    <input name="in" num_pins="5" port_class="lut_in"/>
-                    <output name="out" num_pins="1" port_class="lut_out"/>
-                    <!-- LUT timing using delay matrix -->
-                    <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                           we instead take the average of these numbers to get more stable results
-                        82e-12
-                        173e-12
-                        261e-12
-                        263e-12
-                        398e-12
-                        -->
-                    <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
-                        235e-12
-                        235e-12
-                        235e-12
-                        235e-12
-                        235e-12
-                      </delay_matrix>
-                  </pb_type>
-                  <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-                    <input name="D" num_pins="1" port_class="D"/>
-                    <output name="Q" num_pins="1" port_class="Q"/>
-                    <clock name="clk" num_pins="1" port_class="clock"/>
-                    <T_setup value="66e-12" port="ff.D" clock="clk"/>
-                    <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-                  </pb_type>
-                  <interconnect>
-                    <direct name="direct1" input="flut5.in" output="lut5.in"/>
-                    <direct name="direct2" input="lut5.out" output="ff.D">
-                      <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
-                    </direct>
-                    <direct name="direct3" input="flut5.clk" output="ff.clk"/>
-                    <mux name="mux1" input="ff.Q lut5.out" output="flut5.out">
-                      <delay_constant max="25e-12" in_port="lut5.out" out_port="flut5.out"/>
-                      <delay_constant max="45e-12" in_port="ff.Q" out_port="flut5.out"/>
-                    </mux>
-                  </interconnect>
-                </pb_type>
-                <interconnect>
-                  <direct name="direct1" input="ble5.in" output="flut5.in"/>
-                  <direct name="direct2" input="ble5.clk" output="flut5.clk"/>
-                  <direct name="direct3" input="flut5.out" output="ble5.out"/>
-                </interconnect>
-              </mode>
-              <mode name="arithmetic">
-                <pb_type name="arithmetic" num_pb="1">
-                  <input name="in" num_pins="4"/>
-                  <input name="cin" num_pins="1"/>
-                  <output name="out" num_pins="1"/>
-                  <output name="cout" num_pins="1"/>
-                  <clock name="clk" num_pins="1"/>
-                  <!-- Special dual-LUT mode that drives adder only -->
-                  <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
-                    <input name="in" num_pins="4" port_class="lut_in"/>
-                    <output name="out" num_pins="1" port_class="lut_out"/>
-                    <!-- LUT timing using delay matrix -->
-                    <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                             we instead take the average of these numbers to get more stable results
-                        82e-12
-                        173e-12
-                        261e-12
-                        263e-12
-                        -->
-                    <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
-                        195e-12
-                        195e-12
-                        195e-12
-                        195e-12
-                      </delay_matrix>
-                  </pb_type>
-                  <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
-                    <input name="a" num_pins="1"/>
-                    <input name="b" num_pins="1"/>
-                    <input name="cin" num_pins="1"/>
-                    <output name="cout" num_pins="1"/>
-                    <output name="sumout" num_pins="1"/>
-                    <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
-                    <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
-                    <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
-                    <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
-                    <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
-                    <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
-                  </pb_type>
-                  <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-                    <input name="D" num_pins="1" port_class="D"/>
-                    <output name="Q" num_pins="1" port_class="Q"/>
-                    <clock name="clk" num_pins="1" port_class="clock"/>
-                    <T_setup value="66e-12" port="ff.D" clock="clk"/>
-                    <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-                  </pb_type>
-                  <interconnect>
-                    <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
-                    <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
-                    <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
-                    <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
-                      </direct>
-                    <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
-                      </direct>
-                    <direct name="add_to_ff" input="adder.sumout" output="ff.D">
-                      <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
-                    </direct>
-                    <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
-                      <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
-                    </direct>
-                    <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
-                      <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
-                    </direct>
-                    <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
-                      <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
-                      <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out"/>
-                    </mux>
-                  </interconnect>
-                </pb_type>
-                <interconnect>
-                  <direct name="direct1" input="ble5.in[3:0]" output="arithmetic.in"/>
-                  <direct name="carry_in" input="ble5.cin" output="arithmetic.cin">
-                    <pack_pattern name="chain" in_port="ble5.cin" out_port="arithmetic.cin"/>
-                  </direct>
-                  <direct name="carry_out" input="arithmetic.cout" output="ble5.cout">
-                    <pack_pattern name="chain" in_port="arithmetic.cout" out_port="ble5.cout"/>
-                  </direct>
-                  <direct name="direct2" input="ble5.clk" output="arithmetic.clk"/>
-                  <direct name="direct3" input="arithmetic.out" output="ble5.out"/>
-                </interconnect>
-              </mode>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="lut5inter.in[4:0]" output="ble5[0:0].in"/>
-              <direct name="direct2" input="lut5inter.in[7:3]" output="ble5[1:1].in"/>
-              <direct name="direct3" input="ble5[1:0].out" output="lut5inter.out"/>
-              <direct name="carry_in" input="lut5inter.cin" output="ble5[0:0].cin">
-                <pack_pattern name="chain" in_port="lut5inter.cin" out_port="ble5[0:0].cin"/>
-              </direct>
-              <direct name="carry_out" input="ble5[1:1].cout" output="lut5inter.cout">
-                <pack_pattern name="chain" in_port="ble5[1:1].cout" out_port="lut5inter.cout"/>
-              </direct>
-              <direct name="carry_link" input="ble5[0:0].cout" output="ble5[1:1].cin">
-                <pack_pattern name="chain" in_port="ble5[0:0].cout" out_port="ble5[1:1].cout"/>
-              </direct>
-              <complete name="complete1" input="lut5inter.clk" output="ble5[1:0].clk"/>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in" output="lut5inter.in"/>
-            <direct name="direct2" input="lut5inter.out" output="fle.out"/>
-            <direct name="direct3" input="fle.clk" output="lut5inter.clk"/>
-            <direct name="carry_in" input="fle.cin" output="lut5inter.cin">
-              <pack_pattern name="chain" in_port="fle.cin" out_port="lut5inter.cin"/>
-            </direct>
-            <direct name="carry_out" input="lut5inter.cout" output="fle.cout">
-              <pack_pattern name="chain" in_port="lut5inter.cout" out_port="fle.cout"/>
-            </direct>
-          </interconnect>
-        </mode>
-        <!-- n2_lut5 -->
-        <mode name="n1_lut6">
-          <pb_type name="ble6" num_pb="1">
-            <input name="in" num_pins="6"/>
-            <output name="out" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
-              <input name="in" num_pins="6" port_class="lut_in"/>
-              <output name="out" num_pins="1" port_class="lut_out"/>
-              <!-- LUT timing using delay matrix -->
-              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                       we instead take the average of these numbers to get more stable results
-                  82e-12
-                  173e-12
-                  261e-12
-                  263e-12
-                  398e-12
-                  397e-12
-                  -->
-              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
-                  261e-12
-                  261e-12
-                  261e-12
-                  261e-12
-                  261e-12
-                  261e-12
-                </delay_matrix>
-            </pb_type>
-            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
-              <direct name="direct2" input="lut6.out" output="ff.D">
-                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
-              </direct>
-              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
-              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
-                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
-                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
-            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
-            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
-          </interconnect>
-        </mode>
-        <!-- n1_lut6 -->
-      </pb_type>
-      <interconnect>
-        <!-- We use a 50% depop crossbar built using small full xbars to get sets of logically equivalent pins at inputs of CLB 
-           The delays below come from Stratix IV. the delay through a connection block
-           input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
-           delay on the connection block input mux (modeled by Ian Kuon), so the remaining
-           delay within the crossbar is 95 ps. 
-           The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
-           Since all our outputs LUT outputs go to a BLE output, and have a delay of 
-           25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
-           to get the part that should be marked on the crossbar.	 -->
-        <!-- 50% sparsely populated local routing -->
-        <complete name="lutA" input="clb.I4 clb.I3 fle[1:0].out fle[3:2].out fle[8:8].out" output="fle[9:0].in[0:0]">
-          <delay_constant max="95e-12" in_port="clb.I4" out_port="fle.in[0:0]"/>
-          <delay_constant max="95e-12" in_port="clb.I3" out_port="fle.in[0:0]"/>
-          <delay_constant max="75e-12" in_port="fle[1:0].out" out_port="fle.in[0:0]"/>
-          <delay_constant max="75e-12" in_port="fle[3:2].out" out_port="fle.in[0:0]"/>
-          <delay_constant max="75e-12" in_port="fle[8:8].out" out_port="fle.in[0:0]"/>
-        </complete>
-        <complete name="lutB" input="clb.I3 clb.I2 fle[3:2].out fle[5:4].out fle[9:9].out" output="fle[9:0].in[1:1]">
-          <delay_constant max="95e-12" in_port="clb.I3" out_port="fle.in[1:1]"/>
-          <delay_constant max="95e-12" in_port="clb.I2" out_port="fle.in[1:1]"/>
-          <delay_constant max="75e-12" in_port="fle[3:2].out" out_port="fle.in[1:1]"/>
-          <delay_constant max="75e-12" in_port="fle[5:4].out" out_port="fle.in[1:1]"/>
-          <delay_constant max="75e-12" in_port="fle[9:9].out" out_port="fle.in[1:1]"/>
-        </complete>
-        <complete name="lutC" input="clb.I2 clb.I1 fle[5:4].out fle[7:6].out fle[8:8].out" output="fle[9:0].in[2:2]">
-          <delay_constant max="95e-12" in_port="clb.I2" out_port="fle.in[2:2]"/>
-          <delay_constant max="95e-12" in_port="clb.I1" out_port="fle.in[2:2]"/>
-          <delay_constant max="75e-12" in_port="fle[5:4].out" out_port="fle.in[2:2]"/>
-          <delay_constant max="75e-12" in_port="fle[7:6].out" out_port="fle.in[2:2]"/>
-          <delay_constant max="75e-12" in_port="fle[8:8].out" out_port="fle.in[2:2]"/>
-        </complete>
-        <complete name="lutD" input="clb.I4 clb.I2 fle[1:0].out fle[5:4].out fle[9:9].out" output="fle[9:0].in[3:3]">
-          <delay_constant max="95e-12" in_port="clb.I4" out_port="fle.in[3:3]"/>
-          <delay_constant max="95e-12" in_port="clb.I2" out_port="fle.in[3:3]"/>
-          <delay_constant max="75e-12" in_port="fle[1:0].out" out_port="fle.in[3:3]"/>
-          <delay_constant max="75e-12" in_port="fle[5:4].out" out_port="fle.in[3:3]"/>
-          <delay_constant max="75e-12" in_port="fle[9:9].out" out_port="fle.in[3:3]"/>
-        </complete>
-        <complete name="lutE" input="clb.I3 clb.I1 fle[3:2].out fle[7:6].out fle[8:8].out" output="fle[9:0].in[4:4]">
-          <delay_constant max="95e-12" in_port="clb.I3" out_port="fle.in[4:4]"/>
-          <delay_constant max="95e-12" in_port="clb.I1" out_port="fle.in[4:4]"/>
-          <delay_constant max="75e-12" in_port="fle[3:2].out" out_port="fle.in[4:4]"/>
-          <delay_constant max="75e-12" in_port="fle[7:6].out" out_port="fle.in[4:4]"/>
-          <delay_constant max="75e-12" in_port="fle[8:8].out" out_port="fle.in[4:4]"/>
-        </complete>
-        <complete name="lutF" input="clb.I4 clb.I1 fle[1:0].out fle[7:6].out fle[9:9].out" output="fle[9:0].in[5:5]">
-          <delay_constant max="95e-12" in_port="clb.I4" out_port="fle.in[5:5]"/>
-          <delay_constant max="95e-12" in_port="clb.I1" out_port="fle.in[5:5]"/>
-          <delay_constant max="75e-12" in_port="fle[1:0].out" out_port="fle.in[5:5]"/>
-          <delay_constant max="75e-12" in_port="fle[7:6].out" out_port="fle.in[5:5]"/>
-          <delay_constant max="75e-12" in_port="fle[9:9].out" out_port="fle.in[5:5]"/>
-        </complete>
-        <complete name="lutG" input="clb.I4 clb.I3 fle[1:0].out fle[3:2].out fle[8:8].out" output="fle[9:0].in[6:6]">
-          <delay_constant max="95e-12" in_port="clb.I4" out_port="fle.in[6:6]"/>
-          <delay_constant max="95e-12" in_port="clb.I3" out_port="fle.in[6:6]"/>
-          <delay_constant max="75e-12" in_port="fle[1:0].out" out_port="fle.in[6:6]"/>
-          <delay_constant max="75e-12" in_port="fle[3:2].out" out_port="fle.in[6:6]"/>
-          <delay_constant max="75e-12" in_port="fle[8:8].out" out_port="fle.in[6:6]"/>
-        </complete>
-        <complete name="lutH" input="clb.I3 clb.I2 fle[3:2].out fle[5:4].out fle[9:9].out" output="fle[9:0].in[7:7]">
-          <delay_constant max="95e-12" in_port="clb.I3" out_port="fle.in[7:7]"/>
-          <delay_constant max="95e-12" in_port="clb.I2" out_port="fle.in[7:7]"/>
-          <delay_constant max="75e-12" in_port="fle[3:2].out" out_port="fle.in[7:7]"/>
-          <delay_constant max="75e-12" in_port="fle[5:4].out" out_port="fle.in[7:7]"/>
-          <delay_constant max="75e-12" in_port="fle[9:9].out" out_port="fle.in[7:7]"/>
-        </complete>
-        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
-          </complete>
-        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
-                 By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
-                 then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
-                 naive specification).
-          -->
-        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
-        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
-        <!-- Carry chain links -->
-        <direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
-          <!-- Put all inter-block carry chain delay on this one edge -->
-          <delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
-          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
-        </direct>
-        <direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
-          <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
-        </direct>
-        <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
-          <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
-        </direct>
-      </interconnect>
-    </pb_type>
-    <!-- Define general purpose logic block (CLB) ends -->
-    <!-- Define fracturable multiplier begin -->
-    <!-- This multiplier can operate as a 36x36 multiplier that can fracture to two 18x18 multipliers each of which can further fracture to two 9x9 multipliers 
-	   For delay modelling, the 36x36 DSP multiplier in Stratix IV has a delay of 1.523 ns + 1.93 ns
-	    = 3.45 ns. The 18x18 mode doesn't need to sum four 18x18 multipliers, so it is a bit
-	   faster: 1.523 ns for the multiplier, and 1.09 ns for the multiplier output block.
-	    For the input and output interconnect delays, unlike Stratix IV, we don't
-	   have any routing/logic flexibility (crossbars) at the inputs.  There is some output muxing
-	   in Stratix IV and this architecture to select which multiplier outputs should go out (e.g.
-	   9x9 outputs, 18x18 or 36x36) so those are very close between the two architectures. 
-	   We take the conservative (slightly pessimistic)
-           approach modelling the input as the same as the Stratix IV input delay and the output delay the same as the Stratix IV DSP out delay.
-		   
-	   We estimate block area by using the published Stratix III data (which is architecturally identical to Stratix IV)
-	      (H. Wong, V. Betz and J. Rose, "Comparing FPGA vs. Custom CMOS and the Impact on Processor Microarchitecture", FPGA 2011) of 0.2623 
-		  mm^2 and scaling from 65 to 40 nm to obtain 0.0993 mm^2. That area is for a DSP block with approximately 2x the functionality of 
-		  the block we use (can implement two 36x36 multiplies instead of our 1, eight 18x18 multiplies instead of our 4, etc.). Hence we 
-		  divide the area by 2 to obtain 0.0497 mm^2. One minimum-width transistor units = 60 L^2 (where L = 40 nm), so is 518,000 MWTUS. 
-		  That area includes routing and the connection block input muxes.  Our DSP block is four 
-		  rows high, and hence includes four horizontal routing channel segments and four vertical ones, which is 4x the routing of a logic 
-		  block (single tile). It also includes 3.6x the outputs of a logic block, and 1.8x the inputs. Hence a slight overestimate of the routing
-		  area associated with our DSP block is four times that of a logic tile, where the routing area of a logic tile was calculated above (at W = 300)
-		  as 30481 MWTAs. Hence the (core, non-routing) area our DSP block is approximately 518,000 - 4 * 30,481 = 396,000 MWTUs.
-      -->
-    <pb_type name="mult_36">
-      <input name="a" num_pins="36"/>
-      <input name="b" num_pins="36"/>
-      <output name="out" num_pins="72"/>
-      <mode name="two_divisible_mult_18x18">
-        <pb_type name="divisible_mult_18x18" num_pb="2">
-          <input name="a" num_pins="18"/>
-          <input name="b" num_pins="18"/>
-          <output name="out" num_pins="36"/>
-          <!-- Model 9x9 delay and 18x18 delay as the same.  9x9 could be faster, but in Stratix IV
-	          isn't, presumably because the multiplier layout is really optimized for 18x18.
-		-->
-          <mode name="two_mult_9x9">
-            <pb_type name="mult_9x9_slice" num_pb="2">
-              <input name="A_cfg" num_pins="9"/>
-              <input name="B_cfg" num_pins="9"/>
-              <output name="OUT_cfg" num_pins="18"/>
-              <pb_type name="mult_9x9" blif_model=".subckt multiply" num_pb="1">
-                <input name="a" num_pins="9"/>
-                <input name="b" num_pins="9"/>
-                <output name="out" num_pins="18"/>
-                <delay_constant max="1.523e-9" in_port="mult_9x9.a" out_port="mult_9x9.out"/>
-                <delay_constant max="1.523e-9" in_port="mult_9x9.b" out_port="mult_9x9.out"/>
-              </pb_type>
-              <interconnect>
-                <direct name="a2a" input="mult_9x9_slice.A_cfg" output="mult_9x9.a">
-                </direct>
-                <direct name="b2b" input="mult_9x9_slice.B_cfg" output="mult_9x9.b">
-                </direct>
-                <direct name="out2out" input="mult_9x9.out" output="mult_9x9_slice.OUT_cfg">
-                </direct>
-              </interconnect>
-              <power method="pin-toggle">
-                <port name="A_cfg" energy_per_toggle="1.45e-12"/>
-                <port name="B_cfg" energy_per_toggle="1.45e-12"/>
-                <static_power power_per_instance="0.0"/>
-              </power>
-            </pb_type>
-            <interconnect>
-              <direct name="a2a" input="divisible_mult_18x18.a" output="mult_9x9_slice[1:0].A_cfg">
-              </direct>
-              <direct name="b2b" input="divisible_mult_18x18.b" output="mult_9x9_slice[1:0].B_cfg">
-              </direct>
-              <direct name="out2out" input="mult_9x9_slice[1:0].OUT_cfg" output="divisible_mult_18x18.out">
-              </direct>
-            </interconnect>
-          </mode>
-          <mode name="mult_18x18">
-            <pb_type name="mult_18x18_slice" num_pb="1">
-              <input name="A_cfg" num_pins="18"/>
-              <input name="B_cfg" num_pins="18"/>
-              <output name="OUT_cfg" num_pins="36"/>
-              <pb_type name="mult_18x18" blif_model=".subckt multiply" num_pb="1">
-                <input name="a" num_pins="18"/>
-                <input name="b" num_pins="18"/>
-                <output name="out" num_pins="36"/>
-                <delay_constant max="1.523e-9" in_port="mult_18x18.a" out_port="mult_18x18.out"/>
-                <delay_constant max="1.523e-9" in_port="mult_18x18.b" out_port="mult_18x18.out"/>
-              </pb_type>
-              <interconnect>
-                <direct name="a2a" input="mult_18x18_slice.A_cfg" output="mult_18x18.a">
-                </direct>
-                <direct name="b2b" input="mult_18x18_slice.B_cfg" output="mult_18x18.b">
-                </direct>
-                <direct name="out2out" input="mult_18x18.out" output="mult_18x18_slice.OUT_cfg">
-                </direct>
-              </interconnect>
-              <power method="pin-toggle">
-                <port name="A_cfg" energy_per_toggle="1.09e-12"/>
-                <port name="B_cfg" energy_per_toggle="1.09e-12"/>
-                <static_power power_per_instance="0.0"/>
-              </power>
-            </pb_type>
-            <interconnect>
-              <direct name="a2a" input="divisible_mult_18x18.a" output="mult_18x18_slice.A_cfg">
-              </direct>
-              <direct name="b2b" input="divisible_mult_18x18.b" output="mult_18x18_slice.B_cfg">
-              </direct>
-              <direct name="out2out" input="mult_18x18_slice.OUT_cfg" output="divisible_mult_18x18.out">
-              </direct>
-            </interconnect>
-          </mode>
-          <power method="sum-of-children"/>
-        </pb_type>
-        <interconnect>
-          <!-- Stratix IV input delay of 207ps is conservative for this architecture because this architecture does not have an input crossbar in the multiplier. 
-		   Subtract 72.5 ps delay, which is already in the connection block input mux, leading
-              -->
-          <direct name="a2a" input="mult_36.a" output="divisible_mult_18x18[1:0].a">
-            <delay_constant max="134e-12" in_port="mult_36.a" out_port="divisible_mult_18x18[1:0].a"/>
-          </direct>
-          <direct name="b2b" input="mult_36.b" output="divisible_mult_18x18[1:0].b">
-            <delay_constant max="134e-12" in_port="mult_36.b" out_port="divisible_mult_18x18[1:0].b"/>
-          </direct>
-          <direct name="out2out" input="divisible_mult_18x18[1:0].out" output="mult_36.out">
-            <delay_constant max="1.09e-9" in_port="divisible_mult_18x18[1:0].out" out_port="mult_36.out"/>
-          </direct>
-        </interconnect>
-      </mode>
-      <mode name="mult_36x36">
-        <pb_type name="mult_36x36_slice" num_pb="1">
-          <input name="A_cfg" num_pins="36"/>
-          <input name="B_cfg" num_pins="36"/>
-          <output name="OUT_cfg" num_pins="72"/>
-          <pb_type name="mult_36x36" blif_model=".subckt multiply" num_pb="1">
-            <input name="a" num_pins="36"/>
-            <input name="b" num_pins="36"/>
-            <output name="out" num_pins="72"/>
-            <delay_constant max="1.523e-9" in_port="mult_36x36.a" out_port="mult_36x36.out"/>
-            <delay_constant max="1.523e-9" in_port="mult_36x36.b" out_port="mult_36x36.out"/>
-          </pb_type>
-          <interconnect>
-            <direct name="a2a" input="mult_36x36_slice.A_cfg" output="mult_36x36.a">
-            </direct>
-            <direct name="b2b" input="mult_36x36_slice.B_cfg" output="mult_36x36.b">
-            </direct>
-            <direct name="out2out" input="mult_36x36.out" output="mult_36x36_slice.OUT_cfg">
-            </direct>
-          </interconnect>
-          <power method="pin-toggle">
-            <port name="A_cfg" energy_per_toggle="2.13e-12"/>
-            <port name="B_cfg" energy_per_toggle="2.13e-12"/>
-            <static_power power_per_instance="0.0"/>
-          </power>
-        </pb_type>
-        <interconnect>
-          <!-- Stratix IV input delay of 207ps is conservative for this architecture because this architecture does not have an input crossbar in the multiplier. 
-		   Subtract 72.5 ps delay, which is already in the connection block input mux, leading
-		   to a 134 ps delay.
-              -->
-          <direct name="a2a" input="mult_36.a" output="mult_36x36_slice.A_cfg">
-            <delay_constant max="134e-12" in_port="mult_36.a" out_port="mult_36x36_slice.A_cfg"/>
-          </direct>
-          <direct name="b2b" input="mult_36.b" output="mult_36x36_slice.B_cfg">
-            <delay_constant max="134e-12" in_port="mult_36.b" out_port="mult_36x36_slice.B_cfg"/>
-          </direct>
-          <direct name="out2out" input="mult_36x36_slice.OUT_cfg" output="mult_36.out">
-            <delay_constant max="1.93e-9" in_port="mult_36x36_slice.OUT_cfg" out_port="mult_36.out"/>
-          </direct>
-        </interconnect>
-      </mode>
-      <!-- Place this multiplier block every 8 columns from (and including) the sixth column -->
-      <power method="sum-of-children"/>
-    </pb_type>
-    <!-- Define fracturable multiplier end -->
-    <!-- Define fracturable memory begin -->
-    <!-- 32 Kb Memory that can operate from 512x64 to 32Kx1 for single-port mode and 1024x32 to 32Kx1 for dual-port mode.  
-           Area and delay based off Stratix IV 9K and 144K memories (delay from linear interpolation, Tsu(483 ps, 636 ps) Tco(1084ps, 1969ps)).  
-           Input delay = 204ps (from Stratix IV LAB line) - 72ps (this architecture does not lump connection box delay in internal delay)
-           Output delay = M9K buffer 50ps
-		   
-		   Area is obtained by appropriately scaling and adjusting the published Stratix III (which is architecturally identical to Stratix IV)
-		   data from H. Wong, V. Betz and J. Rose, "Comparing FPGA vs. Custom CMOS and the Impact on Processor Microarchitecture", FPGA 2011.
-		   Linearly interpolating (by bit count) between the M9k and M144k areas to obtain an M32k (our RAM size) point yields a 65 nm area of
-		   of 0.153 mm^2. Interpolating based on port count between the RAMs would instead yield an area of 0.209 mm^2 for our 32 kB RAM; since 
-		   bit count accounts for more area than ports for a RAM this size we choose the bit count interpolation; however, since the port interpolation
-		   is not radically different this also gives us confidence that interpolating based on bits is OK, but slightly underpredicts area.
-		   Scaling to 40 nm^2 yields .0579 mm^2, and converting to MWTUs at 60 L^2 / MWTU yields 604,000 MWTUs. This includes routing. A Stratix IV
-		   M9K RAM is one row high and hence has one routing tile (one horizonal and one vertical routing segment area). An M144k RAM has 8 such tiles.
-		   Linearly interpolating on
-		   bits to 32 kb yields 2.2 routing tiles incorporated in the area number above. The inter-block routing represents 30% of the area of a logic 
-		   tile according to D. Lewis et al, "Architectural Enhancements in Stratix V," FPGA 2013. Hence we should subtract 0.3 * 2.2 * 84,375 MWTUs to
-		   obtain a RAM core area (not including inter-block routing) of 548,000 MWTU areas for our 32 kb RAM in a 40 nm process.
-      -->
-    <pb_type name="memory">
-      <input name="addr1" num_pins="15"/>
-      <input name="addr2" num_pins="15"/>
-      <input name="data" num_pins="64"/>
-      <input name="we1" num_pins="1"/>
-      <input name="we2" num_pins="1"/>
-      <output name="out" num_pins="64"/>
-      <clock name="clk" num_pins="1"/>
-      <!-- Specify single port mode first -->
-      <mode name="mem_512x64_sp">
-        <pb_type name="mem_512x64_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
-          <input name="addr" num_pins="9" port_class="address"/>
-          <input name="data" num_pins="64" port_class="data_in"/>
-          <input name="we" num_pins="1" port_class="write_en"/>
-          <output name="out" num_pins="64" port_class="data_out"/>
-          <clock name="clk" num_pins="1" port_class="clock"/>
-          <T_setup value="509e-12" port="mem_512x64_sp.addr" clock="clk"/>
-          <T_setup value="509e-12" port="mem_512x64_sp.data" clock="clk"/>
-          <T_setup value="509e-12" port="mem_512x64_sp.we" clock="clk"/>
-          <T_clock_to_Q max="1.234e-9" port="mem_512x64_sp.out" clock="clk"/>
-          <power method="pin-toggle">
-            <port name="clk" energy_per_toggle="9.0e-12"/>
-            <static_power power_per_instance="0.0"/>
-          </power>
-        </pb_type>
-        <interconnect>
-          <direct name="address1" input="memory.addr1[8:0]" output="mem_512x64_sp.addr">
-            <delay_constant max="132e-12" in_port="memory.addr1[8:0]" out_port="mem_512x64_sp.addr"/>
-          </direct>
-          <direct name="data1" input="memory.data[63:0]" output="mem_512x64_sp.data">
-            <delay_constant max="132e-12" in_port="memory.data[63:0]" out_port="mem_512x64_sp.data"/>
-          </direct>
-          <direct name="writeen1" input="memory.we1" output="mem_512x64_sp.we">
-            <delay_constant max="132e-12" in_port="memory.we1" out_port="mem_512x64_sp.we"/>
-          </direct>
-          <direct name="dataout1" input="mem_512x64_sp.out" output="memory.out[63:0]">
-            <delay_constant max="40e-12" in_port="mem_512x64_sp.out" out_port="memory.out[63:0]"/>
-          </direct>
-          <direct name="clk" input="memory.clk" output="mem_512x64_sp.clk">
-          </direct>
-        </interconnect>
-      </mode>
-      <mode name="mem_1024x32_sp">
-        <pb_type name="mem_1024x32_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
-          <input name="addr" num_pins="10" port_class="address"/>
-          <input name="data" num_pins="32" port_class="data_in"/>
-          <input name="we" num_pins="1" port_class="write_en"/>
-          <output name="out" num_pins="32" port_class="data_out"/>
-          <clock name="clk" num_pins="1" port_class="clock"/>
-          <T_setup value="509e-12" port="mem_1024x32_sp.addr" clock="clk"/>
-          <T_setup value="509e-12" port="mem_1024x32_sp.data" clock="clk"/>
-          <T_setup value="509e-12" port="mem_1024x32_sp.we" clock="clk"/>
-          <T_clock_to_Q max="1.234e-9" port="mem_1024x32_sp.out" clock="clk"/>
-          <power method="pin-toggle">
-            <port name="clk" energy_per_toggle="9.0e-12"/>
-            <static_power power_per_instance="0.0"/>
-          </power>
-        </pb_type>
-        <interconnect>
-          <direct name="address1" input="memory.addr1[9:0]" output="mem_1024x32_sp.addr">
-            <delay_constant max="132e-12" in_port="memory.addr1[9:0]" out_port="mem_1024x32_sp.addr"/>
-          </direct>
-          <direct name="data1" input="memory.data[31:0]" output="mem_1024x32_sp.data">
-            <delay_constant max="132e-12" in_port="memory.data[31:0]" out_port="mem_1024x32_sp.data"/>
-          </direct>
-          <direct name="writeen1" input="memory.we1" output="mem_1024x32_sp.we">
-            <delay_constant max="132e-12" in_port="memory.we1" out_port="mem_1024x32_sp.we"/>
-          </direct>
-          <direct name="dataout1" input="mem_1024x32_sp.out" output="memory.out[31:0]">
-            <delay_constant max="40e-12" in_port="mem_1024x32_sp.out" out_port="memory.out[31:0]"/>
-          </direct>
-          <direct name="clk" input="memory.clk" output="mem_1024x32_sp.clk">
-          </direct>
-        </interconnect>
-      </mode>
-      <mode name="mem_2048x16_sp">
-        <pb_type name="mem_2048x16_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
-          <input name="addr" num_pins="11" port_class="address"/>
-          <input name="data" num_pins="16" port_class="data_in"/>
-          <input name="we" num_pins="1" port_class="write_en"/>
-          <output name="out" num_pins="16" port_class="data_out"/>
-          <clock name="clk" num_pins="1" port_class="clock"/>
-          <T_setup value="509e-12" port="mem_2048x16_sp.addr" clock="clk"/>
-          <T_setup value="509e-12" port="mem_2048x16_sp.data" clock="clk"/>
-          <T_setup value="509e-12" port="mem_2048x16_sp.we" clock="clk"/>
-          <T_clock_to_Q max="1.234e-9" port="mem_2048x16_sp.out" clock="clk"/>
-          <power method="pin-toggle">
-            <port name="clk" energy_per_toggle="9.0e-12"/>
-            <static_power power_per_instance="0.0"/>
-          </power>
-        </pb_type>
-        <interconnect>
-          <direct name="address1" input="memory.addr1[10:0]" output="mem_2048x16_sp.addr">
-            <delay_constant max="132e-12" in_port="memory.addr1[10:0]" out_port="mem_2048x16_sp.addr"/>
-          </direct>
-          <direct name="data1" input="memory.data[15:0]" output="mem_2048x16_sp.data">
-            <delay_constant max="132e-12" in_port="memory.data[15:0]" out_port="mem_2048x16_sp.data"/>
-          </direct>
-          <direct name="writeen1" input="memory.we1" output="mem_2048x16_sp.we">
-            <delay_constant max="132e-12" in_port="memory.we1" out_port="mem_2048x16_sp.we"/>
-          </direct>
-          <direct name="dataout1" input="mem_2048x16_sp.out" output="memory.out[15:0]">
-            <delay_constant max="40e-12" in_port="mem_2048x16_sp.out" out_port="memory.out[15:0]"/>
-          </direct>
-          <direct name="clk" input="memory.clk" output="mem_2048x16_sp.clk">
-          </direct>
-        </interconnect>
-      </mode>
-      <mode name="mem_4096x8_sp">
-        <pb_type name="mem_4096x8_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
-          <input name="addr" num_pins="12" port_class="address"/>
-          <input name="data" num_pins="8" port_class="data_in"/>
-          <input name="we" num_pins="1" port_class="write_en"/>
-          <output name="out" num_pins="8" port_class="data_out"/>
-          <clock name="clk" num_pins="1" port_class="clock"/>
-          <T_setup value="509e-12" port="mem_4096x8_sp.addr" clock="clk"/>
-          <T_setup value="509e-12" port="mem_4096x8_sp.data" clock="clk"/>
-          <T_setup value="509e-12" port="mem_4096x8_sp.we" clock="clk"/>
-          <T_clock_to_Q max="1.234e-9" port="mem_4096x8_sp.out" clock="clk"/>
-          <power method="pin-toggle">
-            <port name="clk" energy_per_toggle="9.0e-12"/>
-            <static_power power_per_instance="0.0"/>
-          </power>
-        </pb_type>
-        <interconnect>
-          <direct name="address1" input="memory.addr1[11:0]" output="mem_4096x8_sp.addr">
-            <delay_constant max="132e-12" in_port="memory.addr1[11:0]" out_port="mem_4096x8_sp.addr"/>
-          </direct>
-          <direct name="data1" input="memory.data[7:0]" output="mem_4096x8_sp.data">
-            <delay_constant max="132e-12" in_port="memory.data[7:0]" out_port="mem_4096x8_sp.data"/>
-          </direct>
-          <direct name="writeen1" input="memory.we1" output="mem_4096x8_sp.we">
-            <delay_constant max="132e-12" in_port="memory.we1" out_port="mem_4096x8_sp.we"/>
-          </direct>
-          <direct name="dataout1" input="mem_4096x8_sp.out" output="memory.out[7:0]">
-            <delay_constant max="40e-12" in_port="mem_4096x8_sp.out" out_port="memory.out[7:0]"/>
-          </direct>
-          <direct name="clk" input="memory.clk" output="mem_4096x8_sp.clk">
-          </direct>
-        </interconnect>
-      </mode>
-      <mode name="mem_8192x4_sp">
-        <pb_type name="mem_8192x4_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
-          <input name="addr" num_pins="13" port_class="address"/>
-          <input name="data" num_pins="4" port_class="data_in"/>
-          <input name="we" num_pins="1" port_class="write_en"/>
-          <output name="out" num_pins="4" port_class="data_out"/>
-          <clock name="clk" num_pins="1" port_class="clock"/>
-          <T_setup value="509e-12" port="mem_8192x4_sp.addr" clock="clk"/>
-          <T_setup value="509e-12" port="mem_8192x4_sp.data" clock="clk"/>
-          <T_setup value="509e-12" port="mem_8192x4_sp.we" clock="clk"/>
-          <T_clock_to_Q max="1.234e-9" port="mem_8192x4_sp.out" clock="clk"/>
-          <power method="pin-toggle">
-            <port name="clk" energy_per_toggle="9.0e-12"/>
-            <static_power power_per_instance="0.0"/>
-          </power>
-        </pb_type>
-        <interconnect>
-          <direct name="address1" input="memory.addr1[12:0]" output="mem_8192x4_sp.addr">
-            <delay_constant max="132e-12" in_port="memory.addr1[12:0]" out_port="mem_8192x4_sp.addr"/>
-          </direct>
-          <direct name="data1" input="memory.data[3:0]" output="mem_8192x4_sp.data">
-            <delay_constant max="132e-12" in_port="memory.data[3:0]" out_port="mem_8192x4_sp.data"/>
-          </direct>
-          <direct name="writeen1" input="memory.we1" output="mem_8192x4_sp.we">
-            <delay_constant max="132e-12" in_port="memory.we1" out_port="mem_8192x4_sp.we"/>
-          </direct>
-          <direct name="dataout1" input="mem_8192x4_sp.out" output="memory.out[3:0]">
-            <delay_constant max="40e-12" in_port="mem_8192x4_sp.out" out_port="memory.out[3:0]"/>
-          </direct>
-          <direct name="clk" input="memory.clk" output="mem_8192x4_sp.clk">
-          </direct>
-        </interconnect>
-      </mode>
-      <mode name="mem_16384x2_sp">
-        <pb_type name="mem_16384x2_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
-          <input name="addr" num_pins="14" port_class="address"/>
-          <input name="data" num_pins="2" port_class="data_in"/>
-          <input name="we" num_pins="1" port_class="write_en"/>
-          <output name="out" num_pins="2" port_class="data_out"/>
-          <clock name="clk" num_pins="1" port_class="clock"/>
-          <T_setup value="509e-12" port="mem_16384x2_sp.addr" clock="clk"/>
-          <T_setup value="509e-12" port="mem_16384x2_sp.data" clock="clk"/>
-          <T_setup value="509e-12" port="mem_16384x2_sp.we" clock="clk"/>
-          <T_clock_to_Q max="1.234e-9" port="mem_16384x2_sp.out" clock="clk"/>
-          <power method="pin-toggle">
-            <port name="clk" energy_per_toggle="9.0e-12"/>
-            <static_power power_per_instance="0.0"/>
-          </power>
-        </pb_type>
-        <interconnect>
-          <direct name="address1" input="memory.addr1[13:0]" output="mem_16384x2_sp.addr">
-            <delay_constant max="132e-12" in_port="memory.addr1[13:0]" out_port="mem_16384x2_sp.addr"/>
-          </direct>
-          <direct name="data1" input="memory.data[1:0]" output="mem_16384x2_sp.data">
-            <delay_constant max="132e-12" in_port="memory.data[1:0]" out_port="mem_16384x2_sp.data"/>
-          </direct>
-          <direct name="writeen1" input="memory.we1" output="mem_16384x2_sp.we">
-            <delay_constant max="132e-12" in_port="memory.we1" out_port="mem_16384x2_sp.we"/>
-          </direct>
-          <direct name="dataout1" input="mem_16384x2_sp.out" output="memory.out[1:0]">
-            <delay_constant max="40e-12" in_port="mem_16384x2_sp.out" out_port="memory.out[1:0]"/>
-          </direct>
-          <direct name="clk" input="memory.clk" output="mem_16384x2_sp.clk">
-          </direct>
-        </interconnect>
-      </mode>
-      <mode name="mem_32768x1_sp">
-        <pb_type name="mem_32768x1_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
-          <input name="addr" num_pins="15" port_class="address"/>
-          <input name="data" num_pins="1" port_class="data_in"/>
-          <input name="we" num_pins="1" port_class="write_en"/>
-          <output name="out" num_pins="1" port_class="data_out"/>
-          <clock name="clk" num_pins="1" port_class="clock"/>
-          <T_setup value="509e-12" port="mem_32768x1_sp.addr" clock="clk"/>
-          <T_setup value="509e-12" port="mem_32768x1_sp.data" clock="clk"/>
-          <T_setup value="509e-12" port="mem_32768x1_sp.we" clock="clk"/>
-          <T_clock_to_Q max="1.234e-9" port="mem_32768x1_sp.out" clock="clk"/>
-          <power method="pin-toggle">
-            <port name="clk" energy_per_toggle="9.0e-12"/>
-            <static_power power_per_instance="0.0"/>
-          </power>
-        </pb_type>
-        <interconnect>
-          <direct name="address1" input="memory.addr1[14:0]" output="mem_32768x1_sp.addr">
-            <delay_constant max="132e-12" in_port="memory.addr1[14:0]" out_port="mem_32768x1_sp.addr"/>
-          </direct>
-          <direct name="data1" input="memory.data[0:0]" output="mem_32768x1_sp.data">
-            <delay_constant max="132e-12" in_port="memory.data[0:0]" out_port="mem_32768x1_sp.data"/>
-          </direct>
-          <direct name="writeen1" input="memory.we1" output="mem_32768x1_sp.we">
-            <delay_constant max="132e-12" in_port="memory.we1" out_port="mem_32768x1_sp.we"/>
-          </direct>
-          <direct name="dataout1" input="mem_32768x1_sp.out" output="memory.out[0:0]">
-            <delay_constant max="40e-12" in_port="mem_32768x1_sp.out" out_port="memory.out[0:0]"/>
-          </direct>
-          <direct name="clk" input="memory.clk" output="mem_32768x1_sp.clk">
-          </direct>
-        </interconnect>
-      </mode>
-      <!-- Specify true dual port mode next -->
-      <mode name="mem_1024x32_dp">
-        <pb_type name="mem_1024x32_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
-          <input name="addr1" num_pins="10" port_class="address1"/>
-          <input name="addr2" num_pins="10" port_class="address2"/>
-          <input name="data1" num_pins="32" port_class="data_in1"/>
-          <input name="data2" num_pins="32" port_class="data_in2"/>
-          <input name="we1" num_pins="1" port_class="write_en1"/>
-          <input name="we2" num_pins="1" port_class="write_en2"/>
-          <output name="out1" num_pins="32" port_class="data_out1"/>
-          <output name="out2" num_pins="32" port_class="data_out2"/>
-          <clock name="clk" num_pins="1" port_class="clock"/>
-          <T_setup value="509e-12" port="mem_1024x32_dp.addr1" clock="clk"/>
-          <T_setup value="509e-12" port="mem_1024x32_dp.data1" clock="clk"/>
-          <T_setup value="509e-12" port="mem_1024x32_dp.we1" clock="clk"/>
-          <T_setup value="509e-12" port="mem_1024x32_dp.addr2" clock="clk"/>
-          <T_setup value="509e-12" port="mem_1024x32_dp.data2" clock="clk"/>
-          <T_setup value="509e-12" port="mem_1024x32_dp.we2" clock="clk"/>
-          <T_clock_to_Q max="1.234e-9" port="mem_1024x32_dp.out1" clock="clk"/>
-          <T_clock_to_Q max="1.234e-9" port="mem_1024x32_dp.out2" clock="clk"/>
-          <power method="pin-toggle">
-            <port name="clk" energy_per_toggle="17.9e-12"/>
-            <static_power power_per_instance="0.0"/>
-          </power>
-        </pb_type>
-        <interconnect>
-          <direct name="address1" input="memory.addr1[9:0]" output="mem_1024x32_dp.addr1">
-            <delay_constant max="132e-12" in_port="memory.addr1[9:0]" out_port="mem_1024x32_dp.addr1"/>
-          </direct>
-          <direct name="address2" input="memory.addr2[9:0]" output="mem_1024x32_dp.addr2">
-            <delay_constant max="132e-12" in_port="memory.addr2[9:0]" out_port="mem_1024x32_dp.addr2"/>
-          </direct>
-          <direct name="data1" input="memory.data[31:0]" output="mem_1024x32_dp.data1">
-            <delay_constant max="132e-12" in_port="memory.data[31:0]" out_port="mem_1024x32_dp.data1"/>
-          </direct>
-          <direct name="data2" input="memory.data[63:32]" output="mem_1024x32_dp.data2">
-            <delay_constant max="132e-12" in_port="memory.data[63:32]" out_port="mem_1024x32_dp.data2"/>
-          </direct>
-          <direct name="writeen1" input="memory.we1" output="mem_1024x32_dp.we1">
-            <delay_constant max="132e-12" in_port="memory.we1" out_port="mem_1024x32_dp.we1"/>
-          </direct>
-          <direct name="writeen2" input="memory.we2" output="mem_1024x32_dp.we2">
-            <delay_constant max="132e-12" in_port="memory.we2" out_port="mem_1024x32_dp.we2"/>
-          </direct>
-          <direct name="dataout1" input="mem_1024x32_dp.out1" output="memory.out[31:0]">
-            <delay_constant max="40e-12" in_port="mem_1024x32_dp.out1" out_port="memory.out[31:0]"/>
-          </direct>
-          <direct name="dataout2" input="mem_1024x32_dp.out2" output="memory.out[63:32]">
-            <delay_constant max="40e-12" in_port="mem_1024x32_dp.out2" out_port="memory.out[63:32]"/>
-          </direct>
-          <direct name="clk" input="memory.clk" output="mem_1024x32_dp.clk">
-          </direct>
-        </interconnect>
-      </mode>
-      <mode name="mem_2048x16_dp">
-        <pb_type name="mem_2048x16_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
-          <input name="addr1" num_pins="11" port_class="address1"/>
-          <input name="addr2" num_pins="11" port_class="address2"/>
-          <input name="data1" num_pins="16" port_class="data_in1"/>
-          <input name="data2" num_pins="16" port_class="data_in2"/>
-          <input name="we1" num_pins="1" port_class="write_en1"/>
-          <input name="we2" num_pins="1" port_class="write_en2"/>
-          <output name="out1" num_pins="16" port_class="data_out1"/>
-          <output name="out2" num_pins="16" port_class="data_out2"/>
-          <clock name="clk" num_pins="1" port_class="clock"/>
-          <T_setup value="509e-12" port="mem_2048x16_dp.addr1" clock="clk"/>
-          <T_setup value="509e-12" port="mem_2048x16_dp.data1" clock="clk"/>
-          <T_setup value="509e-12" port="mem_2048x16_dp.we1" clock="clk"/>
-          <T_setup value="509e-12" port="mem_2048x16_dp.addr2" clock="clk"/>
-          <T_setup value="509e-12" port="mem_2048x16_dp.data2" clock="clk"/>
-          <T_setup value="509e-12" port="mem_2048x16_dp.we2" clock="clk"/>
-          <T_clock_to_Q max="1.234e-9" port="mem_2048x16_dp.out1" clock="clk"/>
-          <T_clock_to_Q max="1.234e-9" port="mem_2048x16_dp.out2" clock="clk"/>
-          <power method="pin-toggle">
-            <port name="clk" energy_per_toggle="17.9e-12"/>
-            <static_power power_per_instance="0.0"/>
-          </power>
-        </pb_type>
-        <interconnect>
-          <direct name="address1" input="memory.addr1[10:0]" output="mem_2048x16_dp.addr1">
-            <delay_constant max="132e-12" in_port="memory.addr1[10:0]" out_port="mem_2048x16_dp.addr1"/>
-          </direct>
-          <direct name="address2" input="memory.addr2[10:0]" output="mem_2048x16_dp.addr2">
-            <delay_constant max="132e-12" in_port="memory.addr2[10:0]" out_port="mem_2048x16_dp.addr2"/>
-          </direct>
-          <direct name="data1" input="memory.data[15:0]" output="mem_2048x16_dp.data1">
-            <delay_constant max="132e-12" in_port="memory.data[15:0]" out_port="mem_2048x16_dp.data1"/>
-          </direct>
-          <direct name="data2" input="memory.data[31:16]" output="mem_2048x16_dp.data2">
-            <delay_constant max="132e-12" in_port="memory.data[31:16]" out_port="mem_2048x16_dp.data2"/>
-          </direct>
-          <direct name="writeen1" input="memory.we1" output="mem_2048x16_dp.we1">
-            <delay_constant max="132e-12" in_port="memory.we1" out_port="mem_2048x16_dp.we1"/>
-          </direct>
-          <direct name="writeen2" input="memory.we2" output="mem_2048x16_dp.we2">
-            <delay_constant max="132e-12" in_port="memory.we2" out_port="mem_2048x16_dp.we2"/>
-          </direct>
-          <direct name="dataout1" input="mem_2048x16_dp.out1" output="memory.out[15:0]">
-            <delay_constant max="40e-12" in_port="mem_2048x16_dp.out1" out_port="memory.out[15:0]"/>
-          </direct>
-          <direct name="dataout2" input="mem_2048x16_dp.out2" output="memory.out[31:16]">
-            <delay_constant max="40e-12" in_port="mem_2048x16_dp.out2" out_port="memory.out[31:16]"/>
-          </direct>
-          <direct name="clk" input="memory.clk" output="mem_2048x16_dp.clk">
-          </direct>
-        </interconnect>
-      </mode>
-      <mode name="mem_2048x8_dp">
-        <pb_type name="mem_2048x8_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
-          <input name="addr1" num_pins="12" port_class="address1"/>
-          <input name="addr2" num_pins="12" port_class="address2"/>
-          <input name="data1" num_pins="8" port_class="data_in1"/>
-          <input name="data2" num_pins="8" port_class="data_in2"/>
-          <input name="we1" num_pins="1" port_class="write_en1"/>
-          <input name="we2" num_pins="1" port_class="write_en2"/>
-          <output name="out1" num_pins="8" port_class="data_out1"/>
-          <output name="out2" num_pins="8" port_class="data_out2"/>
-          <clock name="clk" num_pins="1" port_class="clock"/>
-          <T_setup value="509e-12" port="mem_2048x8_dp.addr1" clock="clk"/>
-          <T_setup value="509e-12" port="mem_2048x8_dp.data1" clock="clk"/>
-          <T_setup value="509e-12" port="mem_2048x8_dp.we1" clock="clk"/>
-          <T_setup value="509e-12" port="mem_2048x8_dp.addr2" clock="clk"/>
-          <T_setup value="509e-12" port="mem_2048x8_dp.data2" clock="clk"/>
-          <T_setup value="509e-12" port="mem_2048x8_dp.we2" clock="clk"/>
-          <T_clock_to_Q max="1.234e-9" port="mem_2048x8_dp.out1" clock="clk"/>
-          <T_clock_to_Q max="1.234e-9" port="mem_2048x8_dp.out2" clock="clk"/>
-          <power method="pin-toggle">
-            <port name="clk" energy_per_toggle="17.9e-12"/>
-            <static_power power_per_instance="0.0"/>
-          </power>
-        </pb_type>
-        <interconnect>
-          <direct name="address1" input="memory.addr1[11:0]" output="mem_2048x8_dp.addr1">
-            <delay_constant max="132e-12" in_port="memory.addr1[11:0]" out_port="mem_2048x8_dp.addr1"/>
-          </direct>
-          <direct name="address2" input="memory.addr2[11:0]" output="mem_2048x8_dp.addr2">
-            <delay_constant max="132e-12" in_port="memory.addr2[11:0]" out_port="mem_2048x8_dp.addr2"/>
-          </direct>
-          <direct name="data1" input="memory.data[7:0]" output="mem_2048x8_dp.data1">
-            <delay_constant max="132e-12" in_port="memory.data[7:0]" out_port="mem_2048x8_dp.data1"/>
-          </direct>
-          <direct name="data2" input="memory.data[15:8]" output="mem_2048x8_dp.data2">
-            <delay_constant max="132e-12" in_port="memory.data[15:8]" out_port="mem_2048x8_dp.data2"/>
-          </direct>
-          <direct name="writeen1" input="memory.we1" output="mem_2048x8_dp.we1">
-            <delay_constant max="132e-12" in_port="memory.we1" out_port="mem_2048x8_dp.we1"/>
-          </direct>
-          <direct name="writeen2" input="memory.we2" output="mem_2048x8_dp.we2">
-            <delay_constant max="132e-12" in_port="memory.we2" out_port="mem_2048x8_dp.we2"/>
-          </direct>
-          <direct name="dataout1" input="mem_2048x8_dp.out1" output="memory.out[7:0]">
-            <delay_constant max="40e-12" in_port="mem_2048x8_dp.out1" out_port="memory.out[7:0]"/>
-          </direct>
-          <direct name="dataout2" input="mem_2048x8_dp.out2" output="memory.out[15:8]">
-            <delay_constant max="40e-12" in_port="mem_2048x8_dp.out2" out_port="memory.out[15:8]"/>
-          </direct>
-          <direct name="clk" input="memory.clk" output="mem_2048x8_dp.clk">
-          </direct>
-        </interconnect>
-      </mode>
-      <mode name="mem_8192x4_dp">
-        <pb_type name="mem_8192x4_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
-          <input name="addr1" num_pins="13" port_class="address1"/>
-          <input name="addr2" num_pins="13" port_class="address2"/>
-          <input name="data1" num_pins="4" port_class="data_in1"/>
-          <input name="data2" num_pins="4" port_class="data_in2"/>
-          <input name="we1" num_pins="1" port_class="write_en1"/>
-          <input name="we2" num_pins="1" port_class="write_en2"/>
-          <output name="out1" num_pins="4" port_class="data_out1"/>
-          <output name="out2" num_pins="4" port_class="data_out2"/>
-          <clock name="clk" num_pins="1" port_class="clock"/>
-          <T_setup value="509e-12" port="mem_8192x4_dp.addr1" clock="clk"/>
-          <T_setup value="509e-12" port="mem_8192x4_dp.data1" clock="clk"/>
-          <T_setup value="509e-12" port="mem_8192x4_dp.we1" clock="clk"/>
-          <T_setup value="509e-12" port="mem_8192x4_dp.addr2" clock="clk"/>
-          <T_setup value="509e-12" port="mem_8192x4_dp.data2" clock="clk"/>
-          <T_setup value="509e-12" port="mem_8192x4_dp.we2" clock="clk"/>
-          <T_clock_to_Q max="1.234e-9" port="mem_8192x4_dp.out1" clock="clk"/>
-          <T_clock_to_Q max="1.234e-9" port="mem_8192x4_dp.out2" clock="clk"/>
-          <power method="pin-toggle">
-            <port name="clk" energy_per_toggle="17.9e-12"/>
-            <static_power power_per_instance="0.0"/>
-          </power>
-        </pb_type>
-        <interconnect>
-          <direct name="address1" input="memory.addr1[12:0]" output="mem_8192x4_dp.addr1">
-            <delay_constant max="132e-12" in_port="memory.addr1[12:0]" out_port="mem_8192x4_dp.addr1"/>
-          </direct>
-          <direct name="address2" input="memory.addr2[12:0]" output="mem_8192x4_dp.addr2">
-            <delay_constant max="132e-12" in_port="memory.addr2[12:0]" out_port="mem_8192x4_dp.addr2"/>
-          </direct>
-          <direct name="data1" input="memory.data[3:0]" output="mem_8192x4_dp.data1">
-            <delay_constant max="132e-12" in_port="memory.data[3:0]" out_port="mem_8192x4_dp.data1"/>
-          </direct>
-          <direct name="data2" input="memory.data[7:4]" output="mem_8192x4_dp.data2">
-            <delay_constant max="132e-12" in_port="memory.data[7:4]" out_port="mem_8192x4_dp.data2"/>
-          </direct>
-          <direct name="writeen1" input="memory.we1" output="mem_8192x4_dp.we1">
-            <delay_constant max="132e-12" in_port="memory.we1" out_port="mem_8192x4_dp.we1"/>
-          </direct>
-          <direct name="writeen2" input="memory.we2" output="mem_8192x4_dp.we2">
-            <delay_constant max="132e-12" in_port="memory.we2" out_port="mem_8192x4_dp.we2"/>
-          </direct>
-          <direct name="dataout1" input="mem_8192x4_dp.out1" output="memory.out[3:0]">
-            <delay_constant max="40e-12" in_port="mem_8192x4_dp.out1" out_port="memory.out[3:0]"/>
-          </direct>
-          <direct name="dataout2" input="mem_8192x4_dp.out2" output="memory.out[7:4]">
-            <delay_constant max="40e-12" in_port="mem_8192x4_dp.out2" out_port="memory.out[7:4]"/>
-          </direct>
-          <direct name="clk" input="memory.clk" output="mem_8192x4_dp.clk">
-          </direct>
-        </interconnect>
-      </mode>
-      <mode name="mem_16384x2_dp">
-        <pb_type name="mem_16384x2_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
-          <input name="addr1" num_pins="14" port_class="address1"/>
-          <input name="addr2" num_pins="14" port_class="address2"/>
-          <input name="data1" num_pins="2" port_class="data_in1"/>
-          <input name="data2" num_pins="2" port_class="data_in2"/>
-          <input name="we1" num_pins="1" port_class="write_en1"/>
-          <input name="we2" num_pins="1" port_class="write_en2"/>
-          <output name="out1" num_pins="2" port_class="data_out1"/>
-          <output name="out2" num_pins="2" port_class="data_out2"/>
-          <clock name="clk" num_pins="1" port_class="clock"/>
-          <T_setup value="509e-12" port="mem_16384x2_dp.addr1" clock="clk"/>
-          <T_setup value="509e-12" port="mem_16384x2_dp.data1" clock="clk"/>
-          <T_setup value="509e-12" port="mem_16384x2_dp.we1" clock="clk"/>
-          <T_setup value="509e-12" port="mem_16384x2_dp.addr2" clock="clk"/>
-          <T_setup value="509e-12" port="mem_16384x2_dp.data2" clock="clk"/>
-          <T_setup value="509e-12" port="mem_16384x2_dp.we2" clock="clk"/>
-          <T_clock_to_Q max="1.234e-9" port="mem_16384x2_dp.out1" clock="clk"/>
-          <T_clock_to_Q max="1.234e-9" port="mem_16384x2_dp.out2" clock="clk"/>
-          <power method="pin-toggle">
-            <port name="clk" energy_per_toggle="17.9e-12"/>
-            <static_power power_per_instance="0.0"/>
-          </power>
-        </pb_type>
-        <interconnect>
-          <direct name="address1" input="memory.addr1[13:0]" output="mem_16384x2_dp.addr1">
-            <delay_constant max="132e-12" in_port="memory.addr1[13:0]" out_port="mem_16384x2_dp.addr1"/>
-          </direct>
-          <direct name="address2" input="memory.addr2[13:0]" output="mem_16384x2_dp.addr2">
-            <delay_constant max="132e-12" in_port="memory.addr2[13:0]" out_port="mem_16384x2_dp.addr2"/>
-          </direct>
-          <direct name="data1" input="memory.data[1:0]" output="mem_16384x2_dp.data1">
-            <delay_constant max="132e-12" in_port="memory.data[1:0]" out_port="mem_16384x2_dp.data1"/>
-          </direct>
-          <direct name="data2" input="memory.data[3:2]" output="mem_16384x2_dp.data2">
-            <delay_constant max="132e-12" in_port="memory.data[3:2]" out_port="mem_16384x2_dp.data2"/>
-          </direct>
-          <direct name="writeen1" input="memory.we1" output="mem_16384x2_dp.we1">
-            <delay_constant max="132e-12" in_port="memory.we1" out_port="mem_16384x2_dp.we1"/>
-          </direct>
-          <direct name="writeen2" input="memory.we2" output="mem_16384x2_dp.we2">
-            <delay_constant max="132e-12" in_port="memory.we2" out_port="mem_16384x2_dp.we2"/>
-          </direct>
-          <direct name="dataout1" input="mem_16384x2_dp.out1" output="memory.out[1:0]">
-            <delay_constant max="40e-12" in_port="mem_16384x2_dp.out1" out_port="memory.out[1:0]"/>
-          </direct>
-          <direct name="dataout2" input="mem_16384x2_dp.out2" output="memory.out[3:2]">
-            <delay_constant max="40e-12" in_port="mem_16384x2_dp.out2" out_port="memory.out[3:2]"/>
-          </direct>
-          <direct name="clk" input="memory.clk" output="mem_16384x2_dp.clk">
-          </direct>
-        </interconnect>
-      </mode>
-      <mode name="mem_32768x1_dp">
-        <pb_type name="mem_32768x1_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
-          <input name="addr1" num_pins="15" port_class="address1"/>
-          <input name="addr2" num_pins="15" port_class="address2"/>
-          <input name="data1" num_pins="1" port_class="data_in1"/>
-          <input name="data2" num_pins="1" port_class="data_in2"/>
-          <input name="we1" num_pins="1" port_class="write_en1"/>
-          <input name="we2" num_pins="1" port_class="write_en2"/>
-          <output name="out1" num_pins="1" port_class="data_out1"/>
-          <output name="out2" num_pins="1" port_class="data_out2"/>
-          <clock name="clk" num_pins="1" port_class="clock"/>
-          <T_setup value="509e-12" port="mem_32768x1_dp.addr1" clock="clk"/>
-          <T_setup value="509e-12" port="mem_32768x1_dp.data1" clock="clk"/>
-          <T_setup value="509e-12" port="mem_32768x1_dp.we1" clock="clk"/>
-          <T_setup value="509e-12" port="mem_32768x1_dp.addr2" clock="clk"/>
-          <T_setup value="509e-12" port="mem_32768x1_dp.data2" clock="clk"/>
-          <T_setup value="509e-12" port="mem_32768x1_dp.we2" clock="clk"/>
-          <T_clock_to_Q max="1.234e-9" port="mem_32768x1_dp.out1" clock="clk"/>
-          <T_clock_to_Q max="1.234e-9" port="mem_32768x1_dp.out2" clock="clk"/>
-          <power method="pin-toggle">
-            <port name="clk" energy_per_toggle="17.9e-12"/>
-            <static_power power_per_instance="0.0"/>
-          </power>
-        </pb_type>
-        <interconnect>
-          <direct name="address1" input="memory.addr1[14:0]" output="mem_32768x1_dp.addr1">
-            <delay_constant max="132e-12" in_port="memory.addr1[14:0]" out_port="mem_32768x1_dp.addr1"/>
-          </direct>
-          <direct name="address2" input="memory.addr2[14:0]" output="mem_32768x1_dp.addr2">
-            <delay_constant max="132e-12" in_port="memory.addr2[14:0]" out_port="mem_32768x1_dp.addr2"/>
-          </direct>
-          <direct name="data1" input="memory.data[0:0]" output="mem_32768x1_dp.data1">
-            <delay_constant max="132e-12" in_port="memory.data[0:0]" out_port="mem_32768x1_dp.data1"/>
-          </direct>
-          <direct name="data2" input="memory.data[1:1]" output="mem_32768x1_dp.data2">
-            <delay_constant max="132e-12" in_port="memory.data[1:1]" out_port="mem_32768x1_dp.data2"/>
-          </direct>
-          <direct name="writeen1" input="memory.we1" output="mem_32768x1_dp.we1">
-            <delay_constant max="132e-12" in_port="memory.we1" out_port="mem_32768x1_dp.we1"/>
-          </direct>
-          <direct name="writeen2" input="memory.we2" output="mem_32768x1_dp.we2">
-            <delay_constant max="132e-12" in_port="memory.we2" out_port="mem_32768x1_dp.we2"/>
-          </direct>
-          <direct name="dataout1" input="mem_32768x1_dp.out1" output="memory.out[0:0]">
-            <delay_constant max="40e-12" in_port="mem_32768x1_dp.out1" out_port="memory.out[0:0]"/>
-          </direct>
-          <direct name="dataout2" input="mem_32768x1_dp.out2" output="memory.out[1:1]">
-            <delay_constant max="40e-12" in_port="mem_32768x1_dp.out2" out_port="memory.out[1:1]"/>
-          </direct>
-          <direct name="clk" input="memory.clk" output="mem_32768x1_dp.clk">
-          </direct>
-        </interconnect>
-      </mode>
-      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
-      <!-- Place this memory block every 8 columns from (and including) the second column -->
-      <power method="sum-of-children"/>
-    </pb_type>
-    <!-- Define fracturable memory end -->
-  </complexblocklist>
-</architecture>
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_40nm.xml
new file mode 100644
index 000000000..2c528c13c
--- /dev/null
+++ b/openfpga/test_vpr_arch/k6_frac_N10_tileable_40nm.xml
@@ -0,0 +1,441 @@
+<!-- 
+  Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0.
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with all 5 inputs shared) 
+    with optionally registered outputs
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Details on Modelling:
+
+  Based on flagship k6_frac_N10_mem32K_40nm.xml architecture.
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="frac_lut6">
+      <input_ports>
+        <port name="in"/>
+      </input_ports>
+      <output_ports>
+        <port name="lut5_out"/>
+        <port name="lut6_out"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+         If you need to register the I/O, define clocks in the circuit models
+         These clocks can be handled in back-end
+     -->
+    <tile name="io" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad</loc>
+        <loc side="top">io.outpad io.inpad</loc>
+        <loc side="right">io.outpad io.inpad</loc>
+        <loc side="bottom">io.outpad io.inpad</loc>
+      </pinlocations>
+    </tile>
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I" num_pins="40" equivalent="full"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="spread"/>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout tileable="true">
+    <!--auto_layout aspect_ratio="1.0"-->
+    <fixed_layout name="2x2" width="4" height="4">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </fixed_layout>
+    <!-- /auto_layout -->
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	  -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3" sub_type="subset" sub_fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+	       book area formula. This means the mux transistors are about 5x minimum drive strength.
+	       We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+	       mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+	       the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+	       by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+	       buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+	       I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+	       (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+	       The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+	       2.5x when looking up in Jeff's tables.
+	       Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+	       This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+			     With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+			     reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+           If you need to register the I/O, define clocks in the circuit models
+           These clocks can be handled in back-end
+       -->
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" disabled_in_pack="true">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I" num_pins="40" equivalent="full"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe fracturable logic element.  
+             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
+             The outputs of the fracturable logic element can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="10">
+        <input name="in" num_pins="6"/>
+        <output name="out" num_pins="2"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- Physical mode definition begin (physical implementation of the fle) -->
+        <mode name="physical" disabled_in_pack="true">
+          <pb_type name="fabric" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="2"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="frac_logic" num_pb="1">
+              <input name="in" num_pins="6"/>
+              <output name="out" num_pins="2"/>
+              <!-- Define LUT -->
+              <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
+                <input name="in" num_pins="6"/>
+                <output name="lut5_out" num_pins="2"/>
+                <output name="lut6_out" num_pins="1"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
+                <direct name="direct2" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
+                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
+                <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
+              </interconnect>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
+              <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
+              <complete name="direct3" input="fabric.clk" output="ff[1:0].clk"/>
+              <mux name="mux1" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
+                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
+              </mux>
+              <mux name="mux2" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
+                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="fabric.in"/>
+            <direct name="direct2" input="fabric.out" output="fle.out"/>
+            <direct name="direct3" input="fle.clk" output="fabric.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Physical mode definition end (physical implementation of the fle) -->
+        <!-- Dual 5-LUT mode definition begin -->
+        <mode name="n2_lut5">
+          <pb_type name="lut5inter" num_pb="1">
+            <input name="in" num_pins="5"/>
+            <output name="out" num_pins="2"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="ble5" num_pb="2">
+              <input name="in" num_pins="5"/>
+              <output name="out" num_pins="1"/>
+              <clock name="clk" num_pins="1"/>
+              <!-- Define the LUT -->
+              <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
+                <input name="in" num_pins="5" port_class="lut_in"/>
+                <output name="out" num_pins="1" port_class="lut_out"/>
+                <!-- LUT timing using delay matrix -->
+                <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                           we instead take the average of these numbers to get more stable results
+                      82e-12
+                      173e-12
+                      261e-12
+                      263e-12
+                      398e-12
+                      -->
+                <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
+                  235e-12
+                  235e-12
+                  235e-12
+                  235e-12
+                  235e-12
+                </delay_matrix>
+              </pb_type>
+              <!-- Define the flip-flop -->
+              <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+                <input name="D" num_pins="1" port_class="D"/>
+                <output name="Q" num_pins="1" port_class="Q"/>
+                <clock name="clk" num_pins="1" port_class="clock"/>
+                <T_setup value="66e-12" port="ff.D" clock="clk"/>
+                <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="ble5.in[4:0]" output="lut5[0:0].in[4:0]"/>
+                <direct name="direct2" input="lut5[0:0].out" output="ff[0:0].D">
+                  <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
+                  <pack_pattern name="ble5" in_port="lut5[0:0].out" out_port="ff[0:0].D"/>
+                </direct>
+                <direct name="direct3" input="ble5.clk" output="ff[0:0].clk"/>
+                <mux name="mux1" input="ff[0:0].Q lut5.out[0:0]" output="ble5.out[0:0]">
+                  <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                  <delay_constant max="25e-12" in_port="lut5.out[0:0]" out_port="ble5.out[0:0]"/>
+                  <delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble5.out[0:0]"/>
+                </mux>
+              </interconnect>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="lut5inter.in" output="ble5[0:0].in"/>
+              <direct name="direct2" input="lut5inter.in" output="ble5[1:1].in"/>
+              <direct name="direct3" input="ble5[1:0].out" output="lut5inter.out"/>
+              <complete name="complete1" input="lut5inter.clk" output="ble5[1:0].clk"/>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[4:0]" output="lut5inter.in"/>
+            <direct name="direct2" input="lut5inter.out" output="fle.out"/>
+            <direct name="direct3" input="fle.clk" output="lut5inter.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Dual 5-LUT mode definition end -->
+        <!-- 6-LUT mode definition begin -->
+        <mode name="n1_lut6">
+          <!-- Define 6-LUT mode -->
+          <pb_type name="ble6" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Define LUT -->
+            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="6" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->
+              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                261e-12
+                261e-12
+                261e-12
+                261e-12
+                261e-12
+                261e-12
+              </delay_matrix>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+              <direct name="direct2" input="lut6.out" output="ff.D">
+                <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
+                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="ble6.in"/>
+            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+          </interconnect>
+        </mode>
+        <!-- 6-LUT mode definition end -->
+      </pb_type>
+      <interconnect>
+        <!-- We use a full crossbar to get logical equivalence at inputs of CLB 
+		     The delays below come from Stratix IV. the delay through a connection block
+		     input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+		     delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+		     delay within the crossbar is 95 ps. 
+		     The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+		     Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+		     25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+		     to get the part that should be marked on the crossbar.	 -->
+        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
+          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
+          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
+        </complete>
+        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+        </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+               By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+               then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+               naive specification).
+          -->
+        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
+        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
+      </interconnect>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- Place this general purpose logic block in any unspecified column -->
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+  </complexblocklist>
+</architecture>
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml
new file mode 100644
index 000000000..eea76837f
--- /dev/null
+++ b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml
@@ -0,0 +1,639 @@
+<!-- 
+  Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with 8 total FLE inputs (2 inputs of which are shared by the 5-LUTs) 
+    with optionally registered outputs
+    Each 5-LUT has an arithemtic mode that converts it to a single-bit adder with both inputs driven by 4-LUTs (both 4-LUTs share all 4 inputs)
+    Carry chain links to vertically adjacent logic blocks
+  - Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.  
+    Height = 6, found on every (8n+2)th column
+  - Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.  
+    Height = 4, found on every (8n+6)th column
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Details on Modelling:
+
+  The electrical design of the architecture described here is NOT from an 
+  optimized, SPICED architecture.  Instead, we attempt to create a reasonable 
+  architecture file by using an existing commercial FPGA to approximate the area, 
+  delay, and power of the underlying components. This is combined with a reasonable 40 nm 
+  model of wiring and circuit design for low-level routing components, where available.
+  The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also 
+  has wiring electrical parameters that allow the wire lengths and switch patterns to be 
+  modified and you will still get reasonable delay results for the new architecture.
+  The following describes, in detail, how we obtained the various electrical values for this 
+  architecture.
+
+  Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar 
+  architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture. 
+  (n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)      
+  This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to 
+  match the overall target (a 40 nm FPGA).
+
+  We obtain delay numbers by measuring delays of routing, soft logic blocks, 
+  memories, and multipliers from test circuits on a Stratix IV GX device 
+  (EP4SGX230DF29C2X, i.e. fastest speed grade). For routing, we took the average delay of H4 and V4 
+  wires.  Rmetal and Cmetal values for the routing wires were obtained from work done by Charles 
+  Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal stack 40 nm routing) and 
+  take the R and C data from the ITRS roadmap.  
+
+  For the general purpose logic block, we assume that the area and delays of the Stratix IV 
+  crossbar is close enough to the crossbar modelled here.  
+  Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to 
+  36:1 multiplexers.  We match these parameters in this architecture.
+
+  For LUTs, we include LUT 
+  delays measured from Stratix IV which is dependant on the input used (ie. some 
+  LUT inputs are faster than others).  The CAD tools at the time of VTR 7 does 
+  not consider differences in LUT input delays.
+
+  Adder delays obtained as approximate values from a Stratix IV EP4SE230F29C3 device.  
+  Delay obtained by compiling a 256 bit adder (registered inputs and outputs, 
+  all pins except clock virtual) then measuring the delays in chip-planner, 
+  sumout delay = 0.271ns to 0.348 ns, intra-block carry delay = 0.011 ns, 
+  inter-block carry delay = 0.327 ns.  Given this data, I will approximate 
+  sumout 0.3 ns, intra-block carry-delay = 0.01 ns, and 
+  inter-block carry-delay = 0.16 ns (since Altera inter-block carry delay has 
+  overhead that we don't have, I'll approximate the delay of a simpler chain at 
+  one half what they have.  This is very rough, anything from 0.01ns to 0.327ns 
+  can be justified).
+
+  Logic block area numbers obtained by scaling overall tile area of a 65nm 
+  Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out 
+  routing area at a channel width of 300. We use a channel width of 300 because it can route 
+  all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
+  total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
+  choosing a width that provides high routability. The architecture can be routed at different channel
+  widths, but we estimate the tile size and hence the physical length of routing wires assuming
+  a channel width of 300.
+
+  Sanity checks employed:
+    1.  We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches 
+        common electrical design.
+
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <model name="adder">
+      <input_ports>
+        <port name="a" combinational_sink_ports="sumout cout"/>
+        <port name="b" combinational_sink_ports="sumout cout"/>
+        <port name="cin" combinational_sink_ports="sumout cout"/>
+      </input_ports>
+      <output_ports>
+        <port name="cout"/>
+        <port name="sumout"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="frac_lut6">
+      <input_ports>
+        <port name="in"/>
+      </input_ports>
+      <output_ports>
+        <port name="lut4_out"/>
+        <port name="lut5_out"/>
+        <port name="lut6_out"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <tile name="io" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad</loc>
+        <loc side="top">io.outpad io.inpad</loc>
+        <loc side="right">io.outpad io.inpad</loc>
+        <loc side="bottom">io.outpad io.inpad</loc>
+      </pinlocations>
+    </tile>
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
+      </fc>
+      <!--  Highly recommand to customize pin location when direct connection is used!!! -->
+      <!--pinlocations pattern="spread"/-->
+      <pinlocations pattern="custom">
+        <loc side="left">clb.clk</loc>
+        <loc side="top">clb.cin</loc>
+        <loc side="right">clb.O[9:0] clb.I[19:0]</loc>
+        <loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
+      </pinlocations>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout tileable="true">
+    <!--auto_layout aspect_ratio="1.0"-->
+    <fixed_layout name="4x4" width="6" height="6">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </fixed_layout>
+    <!-- /auto_layout -->
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	    -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+           book area formula. This means the mux transistors are about 5x minimum drive strength.
+           We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+           mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+           the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+           by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+           buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+           I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+           (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+           The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+           2.5x when looking up in Jeff's tables.
+           Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+           This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+             With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+             reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <directlist>
+    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
+  </directlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+
+      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+           If you need to register the I/O, define clocks in the circuit models
+           These clocks can be handled in back-end
+       -->
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" disabled_in_pack="true">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe fracturable logic element.  
+             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
+             The outputs of the fracturable logic element can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="10">
+        <input name="in" num_pins="6"/>
+        <input name="cin" num_pins="1"/>
+        <output name="out" num_pins="2"/>
+        <output name="cout" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- Physical mode definition begin (physical implementation of the fle) -->
+        <mode name="physical" disabled_in_pack="true">
+          <pb_type name="fabric" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="frac_logic" num_pb="1">
+              <input name="in" num_pins="6"/>
+              <output name="lut4_out" num_pins="4"/>
+              <output name="out" num_pins="2"/>
+              <!-- Define LUT -->
+              <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
+                <input name="in" num_pins="6"/>
+                <output name="lut4_out" num_pins="4"/>
+                <output name="lut5_out" num_pins="2"/>
+                <output name="lut6_out" num_pins="1"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
+                <direct name="direct2" input="frac_lut6.lut4_out" output="frac_logic.lut4_out"/>
+                <direct name="direct3" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
+                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
+                <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
+              </interconnect>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>         
+            <!-- Define adders -->
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="2">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
+              <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
+              <direct name="direct3" input="fabric.cin" output="adder[0:0].cin"/>
+              <direct name="direct4" input="adder[0:0].cout" output="adder[1:1].cin"/>
+              <direct name="direct5" input="adder[1:1].cout" output="fabric.cout"/>
+              <direct name="direct6" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
+              <direct name="direct7" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
+              <direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
+              <direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
+              <complete name="direct10" input="fabric.clk" output="ff[1:0].clk"/>
+              <mux name="mux1" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
+                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
+              </mux>
+              <mux name="mux2" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
+                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="fabric.in"/>
+            <direct name="direct2" input="fle.cin" output="fabric.cin"/>
+            <direct name="direct3" input="fabric.out" output="fle.out"/>
+            <direct name="direct4" input="fabric.cout" output="fle.cout"/>
+            <direct name="direct5" input="fle.clk" output="fabric.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Physical mode definition end (physical implementation of the fle) -->
+        <!-- BEGIN fle mode of dual lut5 -->
+        <mode name="n2_lut5">
+          <pb_type name="ble5" num_pb="2">
+            <input name="in" num_pins="5"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Regular LUT mode -->
+            <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="5" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                  we instead take the average of these numbers to get more stable results
+                82e-12
+                173e-12
+                261e-12
+                263e-12
+                398e-12
+                -->
+              <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+              </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble5.in" output="lut5.in"/>
+              <direct name="direct2" input="lut5.out" output="ff.D">
+                <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble5.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut5.out" output="ble5.out">
+                <delay_constant max="25e-12" in_port="lut5.out" out_port="ble5.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble5.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[4:0]" output="ble5[0:0].in"/>
+            <direct name="direct2" input="fle.in[4:0]" output="ble5[1:1].in"/>
+            <complete name="direct3" input="fle.clk" output="ble5.clk"/>
+            <direct name="direct4" input="ble5.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- END fle mode of dual lut5 -->
+        <!-- BEGIN arithmetic mode of dual lut4 + adders -->
+        <mode name="arithmetic">
+          <pb_type name="arithmetic" num_pb="2">
+            <input name="in" num_pins="4"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="1"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Special dual-LUT mode that drives adder only -->
+            <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
+              <input name="in" num_pins="4" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  -->
+              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                  195e-12
+                  195e-12
+                  195e-12
+                  195e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
+              <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
+              <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
+              <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
+                </direct>
+              <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
+                </direct>
+              <direct name="add_to_ff" input="adder.sumout" output="ff.D">
+                <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
+              </direct>
+              <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
+                <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
+              </direct>
+              <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
+                <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
+              </direct>
+              <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
+                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[3:0]" output="arithmetic[0:0].in"/>
+            <direct name="direct2" input="fle.in[3:0]" output="arithmetic[1:1].in"/>
+            <direct name="carry_in" input="fle.cin" output="arithmetic[0:0].cin">
+              <pack_pattern name="chain" in_port="fle.cin" out_port="arithmetic[0:0].cin"/>
+            </direct>
+            <direct name="carry_inter" input="arithmetic[0:0].cout" output="arithmetic[1:1].cin">
+              <pack_pattern name="chain" in_port="arithmetic[0:0].cout" out_port="arithmetic[1:1].cin"/>
+            </direct>
+            <direct name="carry_out" input="arithmetic[1:1].cout" output="fle.cout">
+              <pack_pattern name="chain" in_port="arithmetic.cout" out_port="fle.cout"/>
+            </direct>
+            <complete name="direct3" input="fle.clk" output="arithmetic.clk"/>
+            <direct name="direct4" input="arithmetic.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- n2_lut5 -->
+        <mode name="n1_lut6">
+          <pb_type name="ble6" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="6" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->
+              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+              <direct name="direct2" input="lut6.out" output="ff.D">
+                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
+            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+          </interconnect>
+        </mode>
+        <!-- n1_lut6 -->
+      </pb_type>
+      <interconnect>
+        <!-- We use a 50% depop crossbar built using small full xbars to get sets of logically equivalent pins at inputs of CLB 
+           The delays below come from Stratix IV. the delay through a connection block
+           input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+           delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+           delay within the crossbar is 95 ps. 
+           The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+           Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+           25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+           to get the part that should be marked on the crossbar.	 -->
+        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
+          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
+          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
+        </complete>
+
+        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+        </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+                 By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+                 then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+                 naive specification).
+          -->
+        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
+        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
+        <!-- Carry chain links -->
+        <direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
+          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
+        </direct>
+        <direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
+          <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
+        </direct>
+        <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
+          <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
+        </direct>
+      </interconnect>
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+  </complexblocklist>
+</architecture>
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml
new file mode 100644
index 000000000..9422c3a09
--- /dev/null
+++ b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml
@@ -0,0 +1,734 @@
+<!-- 
+  Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with 8 total FLE inputs (2 inputs of which are shared by the 5-LUTs) 
+    with optionally registered outputs
+    Each 5-LUT has an arithemtic mode that converts it to a single-bit adder with both inputs driven by 4-LUTs (both 4-LUTs share all 4 inputs)
+    Carry chain links to vertically adjacent logic blocks
+  - Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.  
+    Height = 6, found on every (8n+2)th column
+  - Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.  
+    Height = 4, found on every (8n+6)th column
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Details on Modelling:
+
+  The electrical design of the architecture described here is NOT from an 
+  optimized, SPICED architecture.  Instead, we attempt to create a reasonable 
+  architecture file by using an existing commercial FPGA to approximate the area, 
+  delay, and power of the underlying components. This is combined with a reasonable 40 nm 
+  model of wiring and circuit design for low-level routing components, where available.
+  The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also 
+  has wiring electrical parameters that allow the wire lengths and switch patterns to be 
+  modified and you will still get reasonable delay results for the new architecture.
+  The following describes, in detail, how we obtained the various electrical values for this 
+  architecture.
+
+  Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar 
+  architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture. 
+  (n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)      
+  This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to 
+  match the overall target (a 40 nm FPGA).
+
+  We obtain delay numbers by measuring delays of routing, soft logic blocks, 
+  memories, and multipliers from test circuits on a Stratix IV GX device 
+  (EP4SGX230DF29C2X, i.e. fastest speed grade). For routing, we took the average delay of H4 and V4 
+  wires.  Rmetal and Cmetal values for the routing wires were obtained from work done by Charles 
+  Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal stack 40 nm routing) and 
+  take the R and C data from the ITRS roadmap.  
+
+  For the general purpose logic block, we assume that the area and delays of the Stratix IV 
+  crossbar is close enough to the crossbar modelled here.  
+  Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to 
+  36:1 multiplexers.  We match these parameters in this architecture.
+
+  For LUTs, we include LUT 
+  delays measured from Stratix IV which is dependant on the input used (ie. some 
+  LUT inputs are faster than others).  The CAD tools at the time of VTR 7 does 
+  not consider differences in LUT input delays.
+
+  Adder delays obtained as approximate values from a Stratix IV EP4SE230F29C3 device.  
+  Delay obtained by compiling a 256 bit adder (registered inputs and outputs, 
+  all pins except clock virtual) then measuring the delays in chip-planner, 
+  sumout delay = 0.271ns to 0.348 ns, intra-block carry delay = 0.011 ns, 
+  inter-block carry delay = 0.327 ns.  Given this data, I will approximate 
+  sumout 0.3 ns, intra-block carry-delay = 0.01 ns, and 
+  inter-block carry-delay = 0.16 ns (since Altera inter-block carry delay has 
+  overhead that we don't have, I'll approximate the delay of a simpler chain at 
+  one half what they have.  This is very rough, anything from 0.01ns to 0.327ns 
+  can be justified).
+
+  Logic block area numbers obtained by scaling overall tile area of a 65nm 
+  Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out 
+  routing area at a channel width of 300. We use a channel width of 300 because it can route 
+  all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
+  total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
+  choosing a width that provides high routability. The architecture can be routed at different channel
+  widths, but we estimate the tile size and hence the physical length of routing wires assuming
+  a channel width of 300.
+
+  Sanity checks employed:
+    1.  We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches 
+        common electrical design.
+
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <model name="adder">
+      <input_ports>
+        <port name="a" combinational_sink_ports="sumout cout"/>
+        <port name="b" combinational_sink_ports="sumout cout"/>
+        <port name="cin" combinational_sink_ports="sumout cout"/>
+      </input_ports>
+      <output_ports>
+        <port name="cout"/>
+        <port name="sumout"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="frac_lut6">
+      <input_ports>
+        <port name="in"/>
+      </input_ports>
+      <output_ports>
+        <port name="lut4_out"/>
+        <port name="lut5_out"/>
+        <port name="lut6_out"/>
+      </output_ports>
+    </model>
+    <model name="dual_port_ram">
+      <input_ports>
+        <!-- write address lines -->
+        <port name="waddr" clock="clk"/>
+        <!-- read address lines -->
+        <port name="raddr" clock="clk"/>
+        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
+        <port name="d_in" clock="clk"/>
+        <!-- write enable -->
+        <port name="wen" clock="clk"/>
+        <!-- read enable -->
+        <port name="ren" clock="clk"/>
+        <!-- memories are often clocked -->
+        <port name="clk" is_clock="1"/>
+      </input_ports>
+      <output_ports>
+        <!-- output can be broken down into smaller bit widths minimum size 1 -->
+        <port name="d_out" clock="clk"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <tile name="io" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad</loc>
+        <loc side="top">io.outpad io.inpad</loc>
+        <loc side="right">io.outpad io.inpad</loc>
+        <loc side="bottom">io.outpad io.inpad</loc>
+      </pinlocations>
+    </tile>
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
+      </fc>
+      <!--  Highly recommand to customize pin location when direct connection is used!!! -->
+      <!--pinlocations pattern="spread"/-->
+      <pinlocations pattern="custom">
+        <loc side="left">clb.clk</loc>
+        <loc side="top">clb.cin</loc>
+        <loc side="right">clb.O[9:0] clb.I[19:0]</loc>
+        <loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
+      </pinlocations>
+    </tile>
+    <tile name="memory" height="2" area="548000">
+      <equivalent_sites>
+        <site pb_type="memory"/>
+      </equivalent_sites>
+      <input name="waddr" num_pins="10"/>
+      <input name="raddr" num_pins="10"/>
+      <input name="d_in" num_pins="32"/>
+      <input name="wen" num_pins="1"/>
+      <input name="ren" num_pins="1"/>
+      <output name="d_out" num_pins="32"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="spread"/>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout tileable="true" through_channel="false">
+    <!--auto_layout aspect_ratio="1.0"-->
+    <fixed_layout name="4x4" width="5" height="4">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
+      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
+    </fixed_layout>
+    <!-- /auto_layout -->
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	    -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+           book area formula. This means the mux transistors are about 5x minimum drive strength.
+           We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+           mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+           the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+           by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+           buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+           I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+           (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+           The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+           2.5x when looking up in Jeff's tables.
+           Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+           This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+             With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+             reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <directlist>
+    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
+  </directlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+
+      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+           If you need to register the I/O, define clocks in the circuit models
+           These clocks can be handled in back-end
+       -->
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" disabled_in_pack="true">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe fracturable logic element.  
+             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
+             The outputs of the fracturable logic element can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="10">
+        <input name="in" num_pins="6"/>
+        <input name="cin" num_pins="1"/>
+        <output name="out" num_pins="2"/>
+        <output name="cout" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- Physical mode definition begin (physical implementation of the fle) -->
+        <mode name="physical" disabled_in_pack="true">
+          <pb_type name="fabric" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="frac_logic" num_pb="1">
+              <input name="in" num_pins="6"/>
+              <output name="lut4_out" num_pins="4"/>
+              <output name="out" num_pins="2"/>
+              <!-- Define LUT -->
+              <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
+                <input name="in" num_pins="6"/>
+                <output name="lut4_out" num_pins="4"/>
+                <output name="lut5_out" num_pins="2"/>
+                <output name="lut6_out" num_pins="1"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
+                <direct name="direct2" input="frac_lut6.lut4_out" output="frac_logic.lut4_out"/>
+                <direct name="direct3" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
+                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
+                <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
+              </interconnect>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>         
+            <!-- Define adders -->
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="2">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
+              <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
+              <direct name="direct3" input="fabric.cin" output="adder[0:0].cin"/>
+              <direct name="direct4" input="adder[0:0].cout" output="adder[1:1].cin"/>
+              <direct name="direct5" input="adder[1:1].cout" output="fabric.cout"/>
+              <direct name="direct6" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
+              <direct name="direct7" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
+              <direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
+              <direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
+              <complete name="direct10" input="fabric.clk" output="ff[1:0].clk"/>
+              <mux name="mux1" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
+                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
+              </mux>
+              <mux name="mux2" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
+                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="fabric.in"/>
+            <direct name="direct2" input="fle.cin" output="fabric.cin"/>
+            <direct name="direct3" input="fabric.out" output="fle.out"/>
+            <direct name="direct4" input="fabric.cout" output="fle.cout"/>
+            <direct name="direct5" input="fle.clk" output="fabric.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Physical mode definition end (physical implementation of the fle) -->
+        <!-- BEGIN fle mode of dual lut5 -->
+        <mode name="n2_lut5">
+          <pb_type name="ble5" num_pb="2">
+            <input name="in" num_pins="5"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Regular LUT mode -->
+            <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="5" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                  we instead take the average of these numbers to get more stable results
+                82e-12
+                173e-12
+                261e-12
+                263e-12
+                398e-12
+                -->
+              <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+              </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble5.in" output="lut5.in"/>
+              <direct name="direct2" input="lut5.out" output="ff.D">
+                <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble5.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut5.out" output="ble5.out">
+                <delay_constant max="25e-12" in_port="lut5.out" out_port="ble5.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble5.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[4:0]" output="ble5[0:0].in"/>
+            <direct name="direct2" input="fle.in[4:0]" output="ble5[1:1].in"/>
+            <complete name="direct3" input="fle.clk" output="ble5.clk"/>
+            <direct name="direct4" input="ble5.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- END fle mode of dual lut5 -->
+        <!-- BEGIN arithmetic mode of dual lut4 + adders -->
+        <mode name="arithmetic">
+          <pb_type name="arithmetic" num_pb="2">
+            <input name="in" num_pins="4"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="1"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Special dual-LUT mode that drives adder only -->
+            <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
+              <input name="in" num_pins="4" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  -->
+              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                  195e-12
+                  195e-12
+                  195e-12
+                  195e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
+              <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
+              <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
+              <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
+                </direct>
+              <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
+                </direct>
+              <direct name="add_to_ff" input="adder.sumout" output="ff.D">
+                <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
+              </direct>
+              <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
+                <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
+              </direct>
+              <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
+                <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
+              </direct>
+              <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
+                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[3:0]" output="arithmetic[0:0].in"/>
+            <direct name="direct2" input="fle.in[3:0]" output="arithmetic[1:1].in"/>
+            <direct name="carry_in" input="fle.cin" output="arithmetic[0:0].cin">
+              <pack_pattern name="chain" in_port="fle.cin" out_port="arithmetic[0:0].cin"/>
+            </direct>
+            <direct name="carry_inter" input="arithmetic[0:0].cout" output="arithmetic[1:1].cin">
+              <pack_pattern name="chain" in_port="arithmetic[0:0].cout" out_port="arithmetic[1:1].cin"/>
+            </direct>
+            <direct name="carry_out" input="arithmetic[1:1].cout" output="fle.cout">
+              <pack_pattern name="chain" in_port="arithmetic.cout" out_port="fle.cout"/>
+            </direct>
+            <complete name="direct3" input="fle.clk" output="arithmetic.clk"/>
+            <direct name="direct4" input="arithmetic.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- n2_lut5 -->
+        <mode name="n1_lut6">
+          <pb_type name="ble6" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="6" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->
+              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+              <direct name="direct2" input="lut6.out" output="ff.D">
+                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
+            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+          </interconnect>
+        </mode>
+        <!-- n1_lut6 -->
+      </pb_type>
+      <interconnect>
+        <!-- We use a 50% depop crossbar built using small full xbars to get sets of logically equivalent pins at inputs of CLB 
+           The delays below come from Stratix IV. the delay through a connection block
+           input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+           delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+           delay within the crossbar is 95 ps. 
+           The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+           Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+           25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+           to get the part that should be marked on the crossbar.	 -->
+        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
+          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
+          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
+        </complete>
+
+        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+        </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+                 By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+                 then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+                 naive specification).
+          -->
+        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
+        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
+        <!-- Carry chain links -->
+        <direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
+          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
+        </direct>
+        <direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
+          <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
+        </direct>
+        <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
+          <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
+        </direct>
+      </interconnect>
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+    <!-- Define single-mode dual-port memory begin -->
+    <pb_type name="memory">
+      <input name="waddr" num_pins="10"/>
+      <input name="raddr" num_pins="10"/>
+      <input name="d_in" num_pins="32"/>
+      <input name="wen" num_pins="1"/>
+      <input name="ren" num_pins="1"/>
+      <output name="d_out" num_pins="32"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Specify the 512x32=16Kbit memory block
+           Note: the delay numbers are extracted from VPR flagship XML without modification
+                 Should align to the process technology we using to create the 16K dual-port RAM
+        -->
+      <mode name="mem_512x32_dp">
+        <pb_type name="mem_512x32_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
+          <input name="waddr" num_pins="10" port_class="address"/>
+          <input name="raddr" num_pins="10" port_class="address"/>
+          <input name="d_in" num_pins="32" port_class="data_in"/>
+          <input name="wen" num_pins="1" port_class="write_en"/>
+          <input name="ren" num_pins="1" port_class="write_en"/>
+          <output name="d_out" num_pins="32" port_class="data_out"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.waddr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.raddr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.d_in" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.wen" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.ren" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_512x32_dp.d_out" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="17.9e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="waddress" input="memory.waddr" output="mem_512x32_dp.waddr">
+            <delay_constant max="132e-12" in_port="memory.waddr" out_port="mem_512x32_dp.waddr"/>
+          </direct>
+          <direct name="raddress" input="memory.raddr" output="mem_512x32_dp.raddr">
+            <delay_constant max="132e-12" in_port="memory.raddr" out_port="mem_512x32_dp.raddr"/>
+          </direct>
+          <direct name="data_input" input="memory.d_in" output="mem_512x32_dp.d_in">
+            <delay_constant max="132e-12" in_port="memory.d_in" out_port="mem_512x32_dp.d_in"/>
+          </direct>
+          <direct name="writeen" input="memory.wen" output="mem_512x32_dp.wen">
+            <delay_constant max="132e-12" in_port="memory.wen" out_port="mem_512x32_dp.wen"/>
+          </direct>
+          <direct name="readen" input="memory.ren" output="mem_512x32_dp.ren">
+            <delay_constant max="132e-12" in_port="memory.ren" out_port="mem_512x32_dp.ren"/>
+          </direct>
+          <direct name="dataout" input="mem_512x32_dp.d_out" output="memory.d_out">
+            <delay_constant max="40e-12" in_port="mem_512x32_dp.d_out" out_port="memory.d_out"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_512x32_dp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+    </pb_type>
+    <!-- Define single-mode dual-port memory end -->
+  </complexblocklist>
+</architecture>
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_thru_channel_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml
similarity index 100%
rename from openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_thru_channel_40nm.xml
rename to openfpga/test_vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml

From 7c9c2451f27463998d02bc12e0578adcc4ec4581 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 27 Mar 2020 16:03:42 -0600
Subject: [PATCH 355/645] debugging multiple io_types; bug fixed to support
 I/Os in more flexible location of FPGA fabric

---
 openfpga/src/base/openfpga_pb_pin_fixup.cpp   |   2 +-
 openfpga/src/fabric/build_grid_modules.cpp    |  17 +-
 .../utils/openfpga_physical_tile_utils.cpp    |  65 ++
 .../src/utils/openfpga_physical_tile_utils.h  |   4 +
 ...er_chain_mem16K_multi_io_capacity.openfpga |  62 ++
 ...er_chain_mem16K_multi_io_capacity_40nm.xml | 768 ++++++++++++++++++
 6 files changed, 913 insertions(+), 5 deletions(-)
 create mode 100644 openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_multi_io_capacity.openfpga
 create mode 100644 openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml

diff --git a/openfpga/src/base/openfpga_pb_pin_fixup.cpp b/openfpga/src/base/openfpga_pb_pin_fixup.cpp
index 901dbaa5f..4d1950678 100644
--- a/openfpga/src/base/openfpga_pb_pin_fixup.cpp
+++ b/openfpga/src/base/openfpga_pb_pin_fixup.cpp
@@ -64,7 +64,7 @@ void update_cluster_pin_with_post_routing_results(const DeviceContext& device_ct
                                                   const bool& verbose) {
   /* Handle each pin */
   auto logical_block = clustering_ctx.clb_nlist.block_type(blk_id);
-  auto physical_tile = pick_best_physical_type(logical_block);
+  auto physical_tile = device_ctx.grid[grid_coord.x()][grid_coord.y()].type;
 
   for (int j = 0; j < logical_block->pb_type->num_pins; j++) {
     /* Get the ptc num for the pin in rr_graph, we need t consider the z offset here
diff --git a/openfpga/src/fabric/build_grid_modules.cpp b/openfpga/src/fabric/build_grid_modules.cpp
index a59afa242..e55640834 100644
--- a/openfpga/src/fabric/build_grid_modules.cpp
+++ b/openfpga/src/fabric/build_grid_modules.cpp
@@ -18,6 +18,7 @@
 #include "openfpga_reserved_words.h"
 #include "openfpga_naming.h"
 #include "openfpga_interconnect_types.h"
+#include "openfpga_physical_tile_utils.h"
 #include "pb_type_utils.h"
 #include "pb_graph_utils.h"
 #include "module_manager_utils.h"
@@ -1093,13 +1094,21 @@ void build_grid_modules(ModuleManager& module_manager,
     if (true == is_empty_type(&physical_tile)) {
       continue;
     } else if (true == is_io_type(&physical_tile)) {
-      /* Special for I/O block, generate one module for each border side */
-      for (int iside = 0; iside < NUM_SIDES; iside++) {
-        SideManager side_manager(iside);
+      /* Special for I/O block:
+       * We will search the grids and see where the I/O blocks are located:
+       * - If a I/O block locates on border sides of FPGA fabric:
+       *   i.e., one or more from {TOP, RIGHT, BOTTOM, LEFT},
+       *   we will generate one module for each border side 
+       * - If a I/O block locates in the center of FPGA fabric:
+       *   we will generate one module with NUM_SIDES (same treatment as regular grids) 
+       */
+      std::set<e_side> io_type_sides = find_physical_io_tile_located_sides(device_ctx.grid,
+                                                                           &physical_tile);
+      for (const e_side& io_type_side : io_type_sides) {
         build_physical_tile_module(module_manager, circuit_lib,
                                    sram_orgz_type, sram_model,
                                    &physical_tile,
-                                   side_manager.get_side(),
+                                   io_type_side,
                                    duplicate_grid_pin,
                                    verbose);
       } 
diff --git a/openfpga/src/utils/openfpga_physical_tile_utils.cpp b/openfpga/src/utils/openfpga_physical_tile_utils.cpp
index 9b70f7f97..375c70a19 100644
--- a/openfpga/src/utils/openfpga_physical_tile_utils.cpp
+++ b/openfpga/src/utils/openfpga_physical_tile_utils.cpp
@@ -30,4 +30,69 @@ float find_physical_tile_pin_Fc(t_physical_tile_type_ptr type,
   exit(1);
 } 
 
+/********************************************************************
+ * Find sides/locations of a I/O physical tile in the context of a FPGA fabric
+ * The I/O grid may locate at 
+ * - one or more border of a FPGA (TOP, RIGHT, BOTTOM, LEFT)
+ *   We will collect each side that the I/O locates 
+ * - the center of a FPGA
+ *   We will add NUM_SIDEs for these I/Os
+ *******************************************************************/
+std::set<e_side> find_physical_io_tile_located_sides(const DeviceGrid& grids,
+                                                     t_physical_tile_type_ptr physical_tile) {
+  std::set<e_side> io_sides;
+  bool center_io = false;
+ 
+  /* Search the core part */
+  for (size_t ix = 1; ix < grids.width() - 1; ++ix) {
+    for (size_t iy = 1; iy < grids.height() - 1; ++iy) {
+      /* If located in center, we add a NUM_SIDES and finish */
+      if (physical_tile == grids[ix][iy].type) {
+        io_sides.insert(NUM_SIDES);
+        center_io = true;
+        break;
+      } 
+    }
+    if (true == center_io) {
+      break;
+    }
+  }  
+
+  /* Search the border side */
+  /* Create the coordinate range for each side of FPGA fabric */
+  std::vector<e_side> fpga_sides{TOP, RIGHT, BOTTOM, LEFT};
+  std::map<e_side, std::vector<vtr::Point<size_t>>> io_coordinates;
+
+  /* TOP side*/
+  for (size_t ix = 1; ix < grids.width() - 1; ++ix) { 
+    io_coordinates[TOP].push_back(vtr::Point<size_t>(ix, grids.height() - 1));
+  } 
+
+  /* RIGHT side */
+  for (size_t iy = 1; iy < grids.height() - 1; ++iy) { 
+    io_coordinates[RIGHT].push_back(vtr::Point<size_t>(grids.width() - 1, iy));
+  } 
+
+  /* BOTTOM side*/
+  for (size_t ix = 1; ix < grids.width() - 1; ++ix) { 
+    io_coordinates[BOTTOM].push_back(vtr::Point<size_t>(ix, 0));
+  } 
+
+  /* LEFT side */
+  for (size_t iy = 1; iy < grids.height() - 1; ++iy) { 
+    io_coordinates[LEFT].push_back(vtr::Point<size_t>(0, iy));
+  }
+  for (const e_side& fpga_side : fpga_sides) {
+    for (const vtr::Point<size_t>& io_coordinate : io_coordinates[fpga_side]) {
+      /* If located in center, we add a NUM_SIDES and finish */
+      if (physical_tile == grids[io_coordinate.x()][io_coordinate.y()].type) {
+        io_sides.insert(fpga_side);
+        break;
+      } 
+    }
+  }
+
+  return io_sides;
+}
+
 } /* end namespace openfpga */
diff --git a/openfpga/src/utils/openfpga_physical_tile_utils.h b/openfpga/src/utils/openfpga_physical_tile_utils.h
index 451d931a8..b2b39ab65 100644
--- a/openfpga/src/utils/openfpga_physical_tile_utils.h
+++ b/openfpga/src/utils/openfpga_physical_tile_utils.h
@@ -6,6 +6,8 @@
  *******************************************************************/
 #include <vector>
 #include <string>
+#include <set>
+#include "device_grid.h"
 #include "physical_types.h"
 
 /********************************************************************
@@ -18,6 +20,8 @@ namespace openfpga {
 float find_physical_tile_pin_Fc(t_physical_tile_type_ptr type,
                                 const int& pin);
 
+std::set<e_side> find_physical_io_tile_located_sides(const DeviceGrid& grids,
+                                                     t_physical_tile_type_ptr physical_tile);
 
 } /* end namespace openfpga */
 
diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_multi_io_capacity.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_multi_io_capacity.openfpga
new file mode 100644
index 000000000..29830f1db
--- /dev/null
+++ b/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_multi_io_capacity.openfpga
@@ -0,0 +1,62 @@
+# Run VPR for the 'and' design
+vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
+
+# Write out the architecture XML as a proof
+#write_openfpga_arch -f ./arch_echo.xml
+
+# Annotate the OpenFPGA architecture to VPR data base
+link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose
+
+# Write GSB to XML for debugging
+write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to clustering nets based on routing results
+pb_pin_fixup --verbose
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup #--verbose
+
+# Build the module graph 
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules 
+build_fabric --compress_routing --duplicate_grid_pin --verbose
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream 
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here 
+write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
+
+# Finish and exit OpenFPGA
+exit
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml
new file mode 100644
index 000000000..8eb6f32bf
--- /dev/null
+++ b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml
@@ -0,0 +1,768 @@
+<!-- 
+  Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with 8 total FLE inputs (2 inputs of which are shared by the 5-LUTs) 
+    with optionally registered outputs
+    Each 5-LUT has an arithemtic mode that converts it to a single-bit adder with both inputs driven by 4-LUTs (both 4-LUTs share all 4 inputs)
+    Carry chain links to vertically adjacent logic blocks
+  - Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.  
+    Height = 6, found on every (8n+2)th column
+  - Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.  
+    Height = 4, found on every (8n+6)th column
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Details on Modelling:
+
+  The electrical design of the architecture described here is NOT from an 
+  optimized, SPICED architecture.  Instead, we attempt to create a reasonable 
+  architecture file by using an existing commercial FPGA to approximate the area, 
+  delay, and power of the underlying components. This is combined with a reasonable 40 nm 
+  model of wiring and circuit design for low-level routing components, where available.
+  The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also 
+  has wiring electrical parameters that allow the wire lengths and switch patterns to be 
+  modified and you will still get reasonable delay results for the new architecture.
+  The following describes, in detail, how we obtained the various electrical values for this 
+  architecture.
+
+  Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar 
+  architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture. 
+  (n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)      
+  This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to 
+  match the overall target (a 40 nm FPGA).
+
+  We obtain delay numbers by measuring delays of routing, soft logic blocks, 
+  memories, and multipliers from test circuits on a Stratix IV GX device 
+  (EP4SGX230DF29C2X, i.e. fastest speed grade). For routing, we took the average delay of H4 and V4 
+  wires.  Rmetal and Cmetal values for the routing wires were obtained from work done by Charles 
+  Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal stack 40 nm routing) and 
+  take the R and C data from the ITRS roadmap.  
+
+  For the general purpose logic block, we assume that the area and delays of the Stratix IV 
+  crossbar is close enough to the crossbar modelled here.  
+  Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to 
+  36:1 multiplexers.  We match these parameters in this architecture.
+
+  For LUTs, we include LUT 
+  delays measured from Stratix IV which is dependant on the input used (ie. some 
+  LUT inputs are faster than others).  The CAD tools at the time of VTR 7 does 
+  not consider differences in LUT input delays.
+
+  Adder delays obtained as approximate values from a Stratix IV EP4SE230F29C3 device.  
+  Delay obtained by compiling a 256 bit adder (registered inputs and outputs, 
+  all pins except clock virtual) then measuring the delays in chip-planner, 
+  sumout delay = 0.271ns to 0.348 ns, intra-block carry delay = 0.011 ns, 
+  inter-block carry delay = 0.327 ns.  Given this data, I will approximate 
+  sumout 0.3 ns, intra-block carry-delay = 0.01 ns, and 
+  inter-block carry-delay = 0.16 ns (since Altera inter-block carry delay has 
+  overhead that we don't have, I'll approximate the delay of a simpler chain at 
+  one half what they have.  This is very rough, anything from 0.01ns to 0.327ns 
+  can be justified).
+
+  Logic block area numbers obtained by scaling overall tile area of a 65nm 
+  Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out 
+  routing area at a channel width of 300. We use a channel width of 300 because it can route 
+  all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
+  total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
+  choosing a width that provides high routability. The architecture can be routed at different channel
+  widths, but we estimate the tile size and hence the physical length of routing wires assuming
+  a channel width of 300.
+
+  Sanity checks employed:
+    1.  We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches 
+        common electrical design.
+
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <model name="adder">
+      <input_ports>
+        <port name="a" combinational_sink_ports="sumout cout"/>
+        <port name="b" combinational_sink_ports="sumout cout"/>
+        <port name="cin" combinational_sink_ports="sumout cout"/>
+      </input_ports>
+      <output_ports>
+        <port name="cout"/>
+        <port name="sumout"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="frac_lut6">
+      <input_ports>
+        <port name="in"/>
+      </input_ports>
+      <output_ports>
+        <port name="lut4_out"/>
+        <port name="lut5_out"/>
+        <port name="lut6_out"/>
+      </output_ports>
+    </model>
+    <model name="dual_port_ram">
+      <input_ports>
+        <!-- write address lines -->
+        <port name="waddr" clock="clk"/>
+        <!-- read address lines -->
+        <port name="raddr" clock="clk"/>
+        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
+        <port name="d_in" clock="clk"/>
+        <!-- write enable -->
+        <port name="wen" clock="clk"/>
+        <!-- read enable -->
+        <port name="ren" clock="clk"/>
+        <!-- memories are often clocked -->
+        <port name="clk" is_clock="1"/>
+      </input_ports>
+      <output_ports>
+        <!-- output can be broken down into smaller bit widths minimum size 1 -->
+        <port name="d_out" clock="clk"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <tile name="io_top" capacity="3" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="bottom">io_top.outpad io_top.inpad</loc>
+      </pinlocations>
+    </tile>
+    <tile name="io_right" capacity="2" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io_right.outpad io_right.inpad</loc>
+      </pinlocations>
+    </tile>
+    <tile name="io_bottom" capacity="1" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="top">io_bottom.outpad io_bottom.inpad</loc>
+      </pinlocations>
+    </tile>
+    <tile name="io_left" capacity="4" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="right">io_left.outpad io_left.inpad</loc>
+      </pinlocations>
+    </tile>
+
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
+      </fc>
+      <!--  Highly recommand to customize pin location when direct connection is used!!! -->
+      <!--pinlocations pattern="spread"/-->
+      <pinlocations pattern="custom">
+        <loc side="left">clb.clk</loc>
+        <loc side="top">clb.cin</loc>
+        <loc side="right">clb.O[9:0] clb.I[19:0]</loc>
+        <loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
+      </pinlocations>
+    </tile>
+    <tile name="memory" height="2" area="548000">
+      <equivalent_sites>
+        <site pb_type="memory"/>
+      </equivalent_sites>
+      <input name="waddr" num_pins="10"/>
+      <input name="raddr" num_pins="10"/>
+      <input name="d_in" num_pins="32"/>
+      <input name="wen" num_pins="1"/>
+      <input name="ren" num_pins="1"/>
+      <output name="d_out" num_pins="32"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="spread"/>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout tileable="true" through_channel="false">
+    <!--auto_layout aspect_ratio="1.0"-->
+    <fixed_layout name="4x4" width="5" height="4">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <row type="io_top" starty="H-1" priority="100"/>
+      <row type="io_bottom" starty="0" priority="100"/>
+      <col type="io_left" startx="0" priority="100"/>
+      <col type="io_right" startx="W-1" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
+      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
+    </fixed_layout>
+    <!-- /auto_layout -->
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	    -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+           book area formula. This means the mux transistors are about 5x minimum drive strength.
+           We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+           mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+           the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+           by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+           buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+           I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+           (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+           The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+           2.5x when looking up in Jeff's tables.
+           Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+           This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+             With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+             reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <directlist>
+    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
+  </directlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+
+      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+           If you need to register the I/O, define clocks in the circuit models
+           These clocks can be handled in back-end
+       -->
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" disabled_in_pack="true">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe fracturable logic element.  
+             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
+             The outputs of the fracturable logic element can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="10">
+        <input name="in" num_pins="6"/>
+        <input name="cin" num_pins="1"/>
+        <output name="out" num_pins="2"/>
+        <output name="cout" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- Physical mode definition begin (physical implementation of the fle) -->
+        <mode name="physical" disabled_in_pack="true">
+          <pb_type name="fabric" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="frac_logic" num_pb="1">
+              <input name="in" num_pins="6"/>
+              <output name="lut4_out" num_pins="4"/>
+              <output name="out" num_pins="2"/>
+              <!-- Define LUT -->
+              <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
+                <input name="in" num_pins="6"/>
+                <output name="lut4_out" num_pins="4"/>
+                <output name="lut5_out" num_pins="2"/>
+                <output name="lut6_out" num_pins="1"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
+                <direct name="direct2" input="frac_lut6.lut4_out" output="frac_logic.lut4_out"/>
+                <direct name="direct3" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
+                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
+                <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
+              </interconnect>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>         
+            <!-- Define adders -->
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="2">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
+              <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
+              <direct name="direct3" input="fabric.cin" output="adder[0:0].cin"/>
+              <direct name="direct4" input="adder[0:0].cout" output="adder[1:1].cin"/>
+              <direct name="direct5" input="adder[1:1].cout" output="fabric.cout"/>
+              <direct name="direct6" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
+              <direct name="direct7" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
+              <direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
+              <direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
+              <complete name="direct10" input="fabric.clk" output="ff[1:0].clk"/>
+              <mux name="mux1" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
+                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
+              </mux>
+              <mux name="mux2" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
+                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="fabric.in"/>
+            <direct name="direct2" input="fle.cin" output="fabric.cin"/>
+            <direct name="direct3" input="fabric.out" output="fle.out"/>
+            <direct name="direct4" input="fabric.cout" output="fle.cout"/>
+            <direct name="direct5" input="fle.clk" output="fabric.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Physical mode definition end (physical implementation of the fle) -->
+        <!-- BEGIN fle mode of dual lut5 -->
+        <mode name="n2_lut5">
+          <pb_type name="ble5" num_pb="2">
+            <input name="in" num_pins="5"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Regular LUT mode -->
+            <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="5" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                  we instead take the average of these numbers to get more stable results
+                82e-12
+                173e-12
+                261e-12
+                263e-12
+                398e-12
+                -->
+              <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+              </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble5.in" output="lut5.in"/>
+              <direct name="direct2" input="lut5.out" output="ff.D">
+                <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble5.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut5.out" output="ble5.out">
+                <delay_constant max="25e-12" in_port="lut5.out" out_port="ble5.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble5.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[4:0]" output="ble5[0:0].in"/>
+            <direct name="direct2" input="fle.in[4:0]" output="ble5[1:1].in"/>
+            <complete name="direct3" input="fle.clk" output="ble5.clk"/>
+            <direct name="direct4" input="ble5.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- END fle mode of dual lut5 -->
+        <!-- BEGIN arithmetic mode of dual lut4 + adders -->
+        <mode name="arithmetic">
+          <pb_type name="arithmetic" num_pb="2">
+            <input name="in" num_pins="4"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="1"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Special dual-LUT mode that drives adder only -->
+            <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
+              <input name="in" num_pins="4" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  -->
+              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                  195e-12
+                  195e-12
+                  195e-12
+                  195e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
+              <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
+              <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
+              <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
+                </direct>
+              <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
+                </direct>
+              <direct name="add_to_ff" input="adder.sumout" output="ff.D">
+                <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
+              </direct>
+              <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
+                <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
+              </direct>
+              <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
+                <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
+              </direct>
+              <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
+                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[3:0]" output="arithmetic[0:0].in"/>
+            <direct name="direct2" input="fle.in[3:0]" output="arithmetic[1:1].in"/>
+            <direct name="carry_in" input="fle.cin" output="arithmetic[0:0].cin">
+              <pack_pattern name="chain" in_port="fle.cin" out_port="arithmetic[0:0].cin"/>
+            </direct>
+            <direct name="carry_inter" input="arithmetic[0:0].cout" output="arithmetic[1:1].cin">
+              <pack_pattern name="chain" in_port="arithmetic[0:0].cout" out_port="arithmetic[1:1].cin"/>
+            </direct>
+            <direct name="carry_out" input="arithmetic[1:1].cout" output="fle.cout">
+              <pack_pattern name="chain" in_port="arithmetic.cout" out_port="fle.cout"/>
+            </direct>
+            <complete name="direct3" input="fle.clk" output="arithmetic.clk"/>
+            <direct name="direct4" input="arithmetic.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- n2_lut5 -->
+        <mode name="n1_lut6">
+          <pb_type name="ble6" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="6" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->
+              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+              <direct name="direct2" input="lut6.out" output="ff.D">
+                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
+            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+          </interconnect>
+        </mode>
+        <!-- n1_lut6 -->
+      </pb_type>
+      <interconnect>
+        <!-- We use a 50% depop crossbar built using small full xbars to get sets of logically equivalent pins at inputs of CLB 
+           The delays below come from Stratix IV. the delay through a connection block
+           input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+           delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+           delay within the crossbar is 95 ps. 
+           The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+           Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+           25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+           to get the part that should be marked on the crossbar.	 -->
+        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
+          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
+          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
+        </complete>
+
+        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+        </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+                 By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+                 then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+                 naive specification).
+          -->
+        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
+        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
+        <!-- Carry chain links -->
+        <direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
+          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
+        </direct>
+        <direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
+          <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
+        </direct>
+        <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
+          <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
+        </direct>
+      </interconnect>
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+    <!-- Define single-mode dual-port memory begin -->
+    <pb_type name="memory">
+      <input name="waddr" num_pins="10"/>
+      <input name="raddr" num_pins="10"/>
+      <input name="d_in" num_pins="32"/>
+      <input name="wen" num_pins="1"/>
+      <input name="ren" num_pins="1"/>
+      <output name="d_out" num_pins="32"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Specify the 512x32=16Kbit memory block
+           Note: the delay numbers are extracted from VPR flagship XML without modification
+                 Should align to the process technology we using to create the 16K dual-port RAM
+        -->
+      <mode name="mem_512x32_dp">
+        <pb_type name="mem_512x32_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
+          <input name="waddr" num_pins="10" port_class="address"/>
+          <input name="raddr" num_pins="10" port_class="address"/>
+          <input name="d_in" num_pins="32" port_class="data_in"/>
+          <input name="wen" num_pins="1" port_class="write_en"/>
+          <input name="ren" num_pins="1" port_class="write_en"/>
+          <output name="d_out" num_pins="32" port_class="data_out"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.waddr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.raddr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.d_in" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.wen" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.ren" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_512x32_dp.d_out" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="17.9e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="waddress" input="memory.waddr" output="mem_512x32_dp.waddr">
+            <delay_constant max="132e-12" in_port="memory.waddr" out_port="mem_512x32_dp.waddr"/>
+          </direct>
+          <direct name="raddress" input="memory.raddr" output="mem_512x32_dp.raddr">
+            <delay_constant max="132e-12" in_port="memory.raddr" out_port="mem_512x32_dp.raddr"/>
+          </direct>
+          <direct name="data_input" input="memory.d_in" output="mem_512x32_dp.d_in">
+            <delay_constant max="132e-12" in_port="memory.d_in" out_port="mem_512x32_dp.d_in"/>
+          </direct>
+          <direct name="writeen" input="memory.wen" output="mem_512x32_dp.wen">
+            <delay_constant max="132e-12" in_port="memory.wen" out_port="mem_512x32_dp.wen"/>
+          </direct>
+          <direct name="readen" input="memory.ren" output="mem_512x32_dp.ren">
+            <delay_constant max="132e-12" in_port="memory.ren" out_port="mem_512x32_dp.ren"/>
+          </direct>
+          <direct name="dataout" input="mem_512x32_dp.d_out" output="memory.d_out">
+            <delay_constant max="40e-12" in_port="mem_512x32_dp.d_out" out_port="memory.d_out"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_512x32_dp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+    </pb_type>
+    <!-- Define single-mode dual-port memory end -->
+  </complexblocklist>
+</architecture>

From 4bf0a63ae65527d6e310a474c44e7c8f441b94a8 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 27 Mar 2020 16:32:15 -0600
Subject: [PATCH 356/645] bug fixed for multiple io types defined in FPGA
 architectures

---
 .../src/fabric/build_top_module_connection.cpp  |  6 ++++--
 openfpga/src/fpga_verilog/verilog_grid.cpp      | 17 +++++++++++++----
 2 files changed, 17 insertions(+), 6 deletions(-)

diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp
index 31163db69..629129669 100644
--- a/openfpga/src/fabric/build_top_module_connection.cpp
+++ b/openfpga/src/fabric/build_top_module_connection.cpp
@@ -115,9 +115,10 @@ void add_top_module_nets_connect_grids_and_sb(ModuleManager& module_manager,
       /* Collect sink-related information */
       vtr::Point<size_t> sink_sb_port_coord(rr_graph.node_xlow(module_sb.get_opin_node(side_manager.get_side(), inode)),
                                             rr_graph.node_ylow(module_sb.get_opin_node(side_manager.get_side(), inode)));
+      size_t sink_grid_pin_index = rr_graph.node_pin_num(module_sb.get_opin_node(side_manager.get_side(), inode));
       std::string sink_sb_port_name = generate_sb_module_grid_port_name(side_manager.get_side(),
                                                                         rr_graph.node_side(module_sb.get_opin_node(side_manager.get_side(), inode)),
-                                                                        src_grid_pin_index); 
+                                                                        sink_grid_pin_index); 
       ModulePortId sink_sb_port_id = module_manager.find_module_port(sink_sb_module, sink_sb_port_name);
       VTR_ASSERT(true == module_manager.valid_module_port_id(sink_sb_module, sink_sb_port_id));
       BasicPort sink_sb_port =  module_manager.module_port(sink_sb_module, sink_sb_port_id); 
@@ -259,9 +260,10 @@ void add_top_module_nets_connect_grids_and_sb_with_duplicated_pins(ModuleManager
       /* Collect sink-related information */
       vtr::Point<size_t> sink_sb_port_coord(rr_graph.node_xlow(module_sb.get_opin_node(side_manager.get_side(), inode)),
                                             rr_graph.node_ylow(module_sb.get_opin_node(side_manager.get_side(), inode)));
+      size_t sink_grid_pin_index = rr_graph.node_pin_num(module_sb.get_opin_node(side_manager.get_side(), inode));
       std::string sink_sb_port_name = generate_sb_module_grid_port_name(side_manager.get_side(),
                                                                         rr_graph.node_side(module_sb.get_opin_node(side_manager.get_side(), inode)),
-                                                                        src_grid_pin_index); 
+                                                                        sink_grid_pin_index); 
       ModulePortId sink_sb_port_id = module_manager.find_module_port(sink_sb_module, sink_sb_port_name);
       VTR_ASSERT(true == module_manager.valid_module_port_id(sink_sb_module, sink_sb_port_id));
       BasicPort sink_sb_port =  module_manager.module_port(sink_sb_module, sink_sb_port_id); 
diff --git a/openfpga/src/fpga_verilog/verilog_grid.cpp b/openfpga/src/fpga_verilog/verilog_grid.cpp
index 73e69ca29..20cdd02f4 100644
--- a/openfpga/src/fpga_verilog/verilog_grid.cpp
+++ b/openfpga/src/fpga_verilog/verilog_grid.cpp
@@ -23,6 +23,7 @@
 
 #include "openfpga_reserved_words.h"
 #include "openfpga_naming.h"
+#include "openfpga_physical_tile_utils.h"
 #include "pb_type_utils.h"
 #include "circuit_library_utils.h"
 #include "module_manager_utils.h"
@@ -375,13 +376,21 @@ void print_verilog_grids(const ModuleManager& module_manager,
     if (true == is_empty_type(&physical_tile)) {
       continue;
     } else if (true == is_io_type(&physical_tile)) {
-      /* Special for I/O block, generate one module for each border side */
-      for (int iside = 0; iside < NUM_SIDES; iside++) {
-        SideManager side_manager(iside);
+      /* Special for I/O block:
+       * We will search the grids and see where the I/O blocks are located:
+       * - If a I/O block locates on border sides of FPGA fabric:
+       *   i.e., one or more from {TOP, RIGHT, BOTTOM, LEFT},
+       *   we will generate one module for each border side 
+       * - If a I/O block locates in the center of FPGA fabric:
+       *   we will generate one module with NUM_SIDES (same treatment as regular grids) 
+       */
+      std::set<e_side> io_type_sides = find_physical_io_tile_located_sides(device_ctx.grid,
+                                                                           &physical_tile);
+      for (const e_side& io_type_side : io_type_sides) {
         print_verilog_physical_tile_netlist(module_manager, netlist_names,
                                             verilog_dir, subckt_dir, 
                                             &physical_tile,
-                                            side_manager.get_side(),
+                                            io_type_side,
                                             use_explicit_mapping);
       } 
       continue;

From 34a1b61ecbed6a803583965695b0a85ec57b4460 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 27 Mar 2020 18:45:27 -0600
Subject: [PATCH 357/645] add an example FPGA architecture with AIB interface
 at the right side of I/Os

---
 ...0_tileable_adder_chain_mem16K_aib_40nm.xml | 800 ++++++++++++++++++
 1 file changed, 800 insertions(+)
 create mode 100644 openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml

diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml
new file mode 100644
index 000000000..e196cb83c
--- /dev/null
+++ b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml
@@ -0,0 +1,800 @@
+<!-- 
+  Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with 8 total FLE inputs (2 inputs of which are shared by the 5-LUTs) 
+    with optionally registered outputs
+    Each 5-LUT has an arithemtic mode that converts it to a single-bit adder with both inputs driven by 4-LUTs (both 4-LUTs share all 4 inputs)
+    Carry chain links to vertically adjacent logic blocks
+  - Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.  
+    Height = 6, found on every (8n+2)th column
+  - Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.  
+    Height = 4, found on every (8n+6)th column
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Details on Modelling:
+
+  The electrical design of the architecture described here is NOT from an 
+  optimized, SPICED architecture.  Instead, we attempt to create a reasonable 
+  architecture file by using an existing commercial FPGA to approximate the area, 
+  delay, and power of the underlying components. This is combined with a reasonable 40 nm 
+  model of wiring and circuit design for low-level routing components, where available.
+  The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also 
+  has wiring electrical parameters that allow the wire lengths and switch patterns to be 
+  modified and you will still get reasonable delay results for the new architecture.
+  The following describes, in detail, how we obtained the various electrical values for this 
+  architecture.
+
+  Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar 
+  architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture. 
+  (n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)      
+  This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to 
+  match the overall target (a 40 nm FPGA).
+
+  We obtain delay numbers by measuring delays of routing, soft logic blocks, 
+  memories, and multipliers from test circuits on a Stratix IV GX device 
+  (EP4SGX230DF29C2X, i.e. fastest speed grade). For routing, we took the average delay of H4 and V4 
+  wires.  Rmetal and Cmetal values for the routing wires were obtained from work done by Charles 
+  Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal stack 40 nm routing) and 
+  take the R and C data from the ITRS roadmap.  
+
+  For the general purpose logic block, we assume that the area and delays of the Stratix IV 
+  crossbar is close enough to the crossbar modelled here.  
+  Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to 
+  36:1 multiplexers.  We match these parameters in this architecture.
+
+  For LUTs, we include LUT 
+  delays measured from Stratix IV which is dependant on the input used (ie. some 
+  LUT inputs are faster than others).  The CAD tools at the time of VTR 7 does 
+  not consider differences in LUT input delays.
+
+  Adder delays obtained as approximate values from a Stratix IV EP4SE230F29C3 device.  
+  Delay obtained by compiling a 256 bit adder (registered inputs and outputs, 
+  all pins except clock virtual) then measuring the delays in chip-planner, 
+  sumout delay = 0.271ns to 0.348 ns, intra-block carry delay = 0.011 ns, 
+  inter-block carry delay = 0.327 ns.  Given this data, I will approximate 
+  sumout 0.3 ns, intra-block carry-delay = 0.01 ns, and 
+  inter-block carry-delay = 0.16 ns (since Altera inter-block carry delay has 
+  overhead that we don't have, I'll approximate the delay of a simpler chain at 
+  one half what they have.  This is very rough, anything from 0.01ns to 0.327ns 
+  can be justified).
+
+  Logic block area numbers obtained by scaling overall tile area of a 65nm 
+  Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out 
+  routing area at a channel width of 300. We use a channel width of 300 because it can route 
+  all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
+  total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
+  choosing a width that provides high routability. The architecture can be routed at different channel
+  widths, but we estimate the tile size and hence the physical length of routing wires assuming
+  a channel width of 300.
+
+  Sanity checks employed:
+    1.  We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches 
+        common electrical design.
+
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <model name="adder">
+      <input_ports>
+        <port name="a" combinational_sink_ports="sumout cout"/>
+        <port name="b" combinational_sink_ports="sumout cout"/>
+        <port name="cin" combinational_sink_ports="sumout cout"/>
+      </input_ports>
+      <output_ports>
+        <port name="cout"/>
+        <port name="sumout"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="frac_lut6">
+      <input_ports>
+        <port name="in"/>
+      </input_ports>
+      <output_ports>
+        <port name="lut4_out"/>
+        <port name="lut5_out"/>
+        <port name="lut6_out"/>
+      </output_ports>
+    </model>
+    <model name="dual_port_ram">
+      <input_ports>
+        <!-- write address lines -->
+        <port name="waddr" clock="clk"/>
+        <!-- read address lines -->
+        <port name="raddr" clock="clk"/>
+        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
+        <port name="d_in" clock="clk"/>
+        <!-- write enable -->
+        <port name="wen" clock="clk"/>
+        <!-- read enable -->
+        <port name="ren" clock="clk"/>
+        <!-- memories are often clocked -->
+        <port name="clk" is_clock="1"/>
+      </input_ports>
+      <output_ports>
+        <!-- output can be broken down into smaller bit widths minimum size 1 -->
+        <port name="d_out" clock="clk"/>
+      </output_ports>
+    </model>
+    <!-- AIB interface model -->
+    <model name="aib">
+      <input_ports>
+        <port name="tx_clk" is_clock="1"/>
+        <port name="rx_clk" is_clock="1"/>
+        <port name="tx_data" clock="tx_clk"/>
+      </input_ports>
+      <output_ports>
+        <!-- output can be broken down into smaller bit widths minimum size 1 -->
+        <port name="rx_data" clock="rx_clk"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <tile name="io" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad</loc>
+        <loc side="top">io.outpad io.inpad</loc>
+        <loc side="right">io.outpad io.inpad</loc>
+        <loc side="bottom">io.outpad io.inpad</loc>
+      </pinlocations>
+    </tile>
+    <!-- A mini AIB interface to be located at the right side of the FPGA
+         All the port will be accessible to the left side of the tile
+         TODO: add full control signals
+         TODO: add analog bus ports to the right side which should be GPIOs
+      -->
+    <tile name="aib" width="1" height="4" area="0">
+      <equivalent_sites>
+        <site pb_type="aib"/>
+      </equivalent_sites>
+      <clock name="tx_clk" num_pins="1"/>
+      <input name="tx_data" num_pins="80"/>
+      <clock name="rx_clk" num_pins="1"/>
+      <output name="rx_data" num_pins="80"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">aib.tx_clk aib.tx_data aib.rx_clk aib.rx_data</loc>
+      </pinlocations>
+    </tile>
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
+      </fc>
+      <!--  Highly recommand to customize pin location when direct connection is used!!! -->
+      <!--pinlocations pattern="spread"/-->
+      <pinlocations pattern="custom">
+        <loc side="left">clb.clk</loc>
+        <loc side="top">clb.cin</loc>
+        <loc side="right">clb.O[9:0] clb.I[19:0]</loc>
+        <loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
+      </pinlocations>
+    </tile>
+    <tile name="memory" height="2" area="548000">
+      <equivalent_sites>
+        <site pb_type="memory"/>
+      </equivalent_sites>
+      <input name="waddr" num_pins="10"/>
+      <input name="raddr" num_pins="10"/>
+      <input name="d_in" num_pins="32"/>
+      <input name="wen" num_pins="1"/>
+      <input name="ren" num_pins="1"/>
+      <output name="d_out" num_pins="32"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="spread"/>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout tileable="true" through_channel="false">
+    <!--auto_layout aspect_ratio="1.0"-->
+    <fixed_layout name="4x4" width="7" height="6">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="10"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="1"/>
+      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
+      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
+      <!-- Single instance of an AIB interface -->
+      <single type="aib" x="6" y="1" priority="20"/>
+    </fixed_layout>
+    <!-- /auto_layout -->
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	    -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+           book area formula. This means the mux transistors are about 5x minimum drive strength.
+           We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+           mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+           the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+           by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+           buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+           I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+           (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+           The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+           2.5x when looking up in Jeff's tables.
+           Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+           This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+             With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+             reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <directlist>
+    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
+  </directlist>
+  <complexblocklist>
+    <!-- Define AIB begin -->
+    <pb_type name="aib">
+      <clock name="tx_clk" num_pins="1"/>
+      <input name="tx_data" num_pins="80"/>
+      <clock name="rx_clk" num_pins="1"/>
+      <output name="rx_data" num_pins="80"/>
+      <mode name="physical">
+        <pb_type name="aib_core" blif_model=".subckt aib" num_pb="1">
+          <clock name="tx_clk" num_pins="1"/>
+          <input name="tx_data" num_pins="80"/>
+          <clock name="rx_clk" num_pins="1"/>
+          <output name="rx_data" num_pins="80"/>
+          <T_setup value="509e-12" port="aib_core.tx_data" clock="tx_clk"/>
+          <T_clock_to_Q max="1.234e-9" port="aib_core.tx_data" clock="tx_clk"/>
+          <T_setup value="509e-12" port="aib_core.rx_data" clock="rx_clk"/>
+          <T_clock_to_Q max="1.234e-9" port="aib_core.rx_data" clock="rx_clk"/>
+        </pb_type>
+        <interconnect>
+          <direct name="tx_clk" input="aib.tx_clk" output="aib_core.tx_clk">
+            <delay_constant max="1.394e-11" in_port="aib.tx_clk" out_port="aib_core.tx_clk"/>
+          </direct>
+          <direct name="rx_clk" input="aib.rx_clk" output="aib_core.rx_clk">
+            <delay_constant max="1.394e-11" in_port="aib.rx_clk" out_port="aib_core.rx_clk"/>
+          </direct>
+          <direct name="tx_data" input="aib.tx_data" output="aib_core.tx_data">
+            <delay_constant max="1.394e-11" in_port="aib.tx_data" out_port="aib_core.tx_data"/>
+          </direct>
+          <direct name="rx_data" input="aib_core.rx_data" output="aib.rx_data">
+            <delay_constant max="4.243e-11" in_port="aib_core.rx_data" out_port="aib.rx_data"/>
+          </direct>
+        </interconnect>
+      </mode>
+
+    </pb_type>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+
+      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+           If you need to register the I/O, define clocks in the circuit models
+           These clocks can be handled in back-end
+       -->
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" disabled_in_pack="true">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe fracturable logic element.  
+             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
+             The outputs of the fracturable logic element can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="10">
+        <input name="in" num_pins="6"/>
+        <input name="cin" num_pins="1"/>
+        <output name="out" num_pins="2"/>
+        <output name="cout" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- Physical mode definition begin (physical implementation of the fle) -->
+        <mode name="physical" disabled_in_pack="true">
+          <pb_type name="fabric" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="frac_logic" num_pb="1">
+              <input name="in" num_pins="6"/>
+              <output name="lut4_out" num_pins="4"/>
+              <output name="out" num_pins="2"/>
+              <!-- Define LUT -->
+              <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
+                <input name="in" num_pins="6"/>
+                <output name="lut4_out" num_pins="4"/>
+                <output name="lut5_out" num_pins="2"/>
+                <output name="lut6_out" num_pins="1"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
+                <direct name="direct2" input="frac_lut6.lut4_out" output="frac_logic.lut4_out"/>
+                <direct name="direct3" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
+                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
+                <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
+              </interconnect>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>         
+            <!-- Define adders -->
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="2">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
+              <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
+              <direct name="direct3" input="fabric.cin" output="adder[0:0].cin"/>
+              <direct name="direct4" input="adder[0:0].cout" output="adder[1:1].cin"/>
+              <direct name="direct5" input="adder[1:1].cout" output="fabric.cout"/>
+              <direct name="direct6" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
+              <direct name="direct7" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
+              <direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
+              <direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
+              <complete name="direct10" input="fabric.clk" output="ff[1:0].clk"/>
+              <mux name="mux1" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
+                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
+              </mux>
+              <mux name="mux2" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
+                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="fabric.in"/>
+            <direct name="direct2" input="fle.cin" output="fabric.cin"/>
+            <direct name="direct3" input="fabric.out" output="fle.out"/>
+            <direct name="direct4" input="fabric.cout" output="fle.cout"/>
+            <direct name="direct5" input="fle.clk" output="fabric.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Physical mode definition end (physical implementation of the fle) -->
+        <!-- BEGIN fle mode of dual lut5 -->
+        <mode name="n2_lut5">
+          <pb_type name="ble5" num_pb="2">
+            <input name="in" num_pins="5"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Regular LUT mode -->
+            <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="5" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                  we instead take the average of these numbers to get more stable results
+                82e-12
+                173e-12
+                261e-12
+                263e-12
+                398e-12
+                -->
+              <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+              </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble5.in" output="lut5.in"/>
+              <direct name="direct2" input="lut5.out" output="ff.D">
+                <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble5.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut5.out" output="ble5.out">
+                <delay_constant max="25e-12" in_port="lut5.out" out_port="ble5.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble5.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[4:0]" output="ble5[0:0].in"/>
+            <direct name="direct2" input="fle.in[4:0]" output="ble5[1:1].in"/>
+            <complete name="direct3" input="fle.clk" output="ble5.clk"/>
+            <direct name="direct4" input="ble5.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- END fle mode of dual lut5 -->
+        <!-- BEGIN arithmetic mode of dual lut4 + adders -->
+        <mode name="arithmetic">
+          <pb_type name="arithmetic" num_pb="2">
+            <input name="in" num_pins="4"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="1"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Special dual-LUT mode that drives adder only -->
+            <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
+              <input name="in" num_pins="4" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  -->
+              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                  195e-12
+                  195e-12
+                  195e-12
+                  195e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
+              <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
+              <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
+              <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
+                </direct>
+              <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
+                </direct>
+              <direct name="add_to_ff" input="adder.sumout" output="ff.D">
+                <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
+              </direct>
+              <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
+                <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
+              </direct>
+              <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
+                <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
+              </direct>
+              <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
+                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[3:0]" output="arithmetic[0:0].in"/>
+            <direct name="direct2" input="fle.in[3:0]" output="arithmetic[1:1].in"/>
+            <direct name="carry_in" input="fle.cin" output="arithmetic[0:0].cin">
+              <pack_pattern name="chain" in_port="fle.cin" out_port="arithmetic[0:0].cin"/>
+            </direct>
+            <direct name="carry_inter" input="arithmetic[0:0].cout" output="arithmetic[1:1].cin">
+              <pack_pattern name="chain" in_port="arithmetic[0:0].cout" out_port="arithmetic[1:1].cin"/>
+            </direct>
+            <direct name="carry_out" input="arithmetic[1:1].cout" output="fle.cout">
+              <pack_pattern name="chain" in_port="arithmetic.cout" out_port="fle.cout"/>
+            </direct>
+            <complete name="direct3" input="fle.clk" output="arithmetic.clk"/>
+            <direct name="direct4" input="arithmetic.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- n2_lut5 -->
+        <mode name="n1_lut6">
+          <pb_type name="ble6" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="6" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->
+              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+              <direct name="direct2" input="lut6.out" output="ff.D">
+                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
+            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+          </interconnect>
+        </mode>
+        <!-- n1_lut6 -->
+      </pb_type>
+      <interconnect>
+        <!-- We use a 50% depop crossbar built using small full xbars to get sets of logically equivalent pins at inputs of CLB 
+           The delays below come from Stratix IV. the delay through a connection block
+           input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+           delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+           delay within the crossbar is 95 ps. 
+           The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+           Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+           25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+           to get the part that should be marked on the crossbar.	 -->
+        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
+          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
+          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
+        </complete>
+
+        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+        </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+                 By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+                 then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+                 naive specification).
+          -->
+        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
+        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
+        <!-- Carry chain links -->
+        <direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
+          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
+        </direct>
+        <direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
+          <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
+        </direct>
+        <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
+          <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
+        </direct>
+      </interconnect>
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+    <!-- Define single-mode dual-port memory begin -->
+    <pb_type name="memory">
+      <input name="waddr" num_pins="10"/>
+      <input name="raddr" num_pins="10"/>
+      <input name="d_in" num_pins="32"/>
+      <input name="wen" num_pins="1"/>
+      <input name="ren" num_pins="1"/>
+      <output name="d_out" num_pins="32"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Specify the 512x32=16Kbit memory block
+           Note: the delay numbers are extracted from VPR flagship XML without modification
+                 Should align to the process technology we using to create the 16K dual-port RAM
+        -->
+      <mode name="mem_512x32_dp">
+        <pb_type name="mem_512x32_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
+          <input name="waddr" num_pins="10" port_class="address"/>
+          <input name="raddr" num_pins="10" port_class="address"/>
+          <input name="d_in" num_pins="32" port_class="data_in"/>
+          <input name="wen" num_pins="1" port_class="write_en"/>
+          <input name="ren" num_pins="1" port_class="write_en"/>
+          <output name="d_out" num_pins="32" port_class="data_out"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.waddr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.raddr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.d_in" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.wen" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.ren" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_512x32_dp.d_out" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="17.9e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="waddress" input="memory.waddr" output="mem_512x32_dp.waddr">
+            <delay_constant max="132e-12" in_port="memory.waddr" out_port="mem_512x32_dp.waddr"/>
+          </direct>
+          <direct name="raddress" input="memory.raddr" output="mem_512x32_dp.raddr">
+            <delay_constant max="132e-12" in_port="memory.raddr" out_port="mem_512x32_dp.raddr"/>
+          </direct>
+          <direct name="data_input" input="memory.d_in" output="mem_512x32_dp.d_in">
+            <delay_constant max="132e-12" in_port="memory.d_in" out_port="mem_512x32_dp.d_in"/>
+          </direct>
+          <direct name="writeen" input="memory.wen" output="mem_512x32_dp.wen">
+            <delay_constant max="132e-12" in_port="memory.wen" out_port="mem_512x32_dp.wen"/>
+          </direct>
+          <direct name="readen" input="memory.ren" output="mem_512x32_dp.ren">
+            <delay_constant max="132e-12" in_port="memory.ren" out_port="mem_512x32_dp.ren"/>
+          </direct>
+          <direct name="dataout" input="mem_512x32_dp.d_out" output="memory.d_out">
+            <delay_constant max="40e-12" in_port="mem_512x32_dp.d_out" out_port="memory.d_out"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_512x32_dp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+    </pb_type>
+    <!-- Define single-mode dual-port memory end -->
+  </complexblocklist>
+</architecture>

From e601a648cc5ca9646b805d802fcf02cd37b95ebb Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 27 Mar 2020 19:07:34 -0600
Subject: [PATCH 358/645] relax asseration to allow AIB (non-I/O) blocks on the
 side of FPGA fabrics

---
 openfpga/src/base/openfpga_pb_pin_fixup.cpp   |   2 -
 openfpga/src/fabric/build_top_module.cpp      |   3 +-
 .../fpga_bitstream/build_grid_bitstream.cpp   |   2 -
 .../src/fpga_sdc/analysis_sdc_grid_writer.cpp |   3 -
 ...0_adder_chain_mem16K_aib_40nm_openfpga.xml | 322 ++++++++++++++++++
 ...c_tileable_adder_chain_mem16K_aib.openfpga |  62 ++++
 6 files changed, 385 insertions(+), 9 deletions(-)
 create mode 100644 openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
 create mode 100644 openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_aib.openfpga

diff --git a/openfpga/src/base/openfpga_pb_pin_fixup.cpp b/openfpga/src/base/openfpga_pb_pin_fixup.cpp
index 4d1950678..3e6fec2f7 100644
--- a/openfpga/src/base/openfpga_pb_pin_fixup.cpp
+++ b/openfpga/src/base/openfpga_pb_pin_fixup.cpp
@@ -224,8 +224,6 @@ void update_pb_pin_with_post_routing_results(const DeviceContext& device_ctx,
       if (true == is_empty_type(device_ctx.grid[io_coord.x()][io_coord.y()].type)) {
         continue;
       }
-      /* We must have an I/O type here */
-      VTR_ASSERT(true == is_io_type(device_ctx.grid[io_coord.x()][io_coord.y()].type));
       /* Get the mapped blocks to this grid */
       for (const ClusterBlockId& cluster_blk_id : placement_ctx.grid_blocks[io_coord.x()][io_coord.y()].blocks) {
         /* Skip invalid ids */ 
diff --git a/openfpga/src/fabric/build_top_module.cpp b/openfpga/src/fabric/build_top_module.cpp
index 83a4f0147..112b32a52 100644
--- a/openfpga/src/fabric/build_top_module.cpp
+++ b/openfpga/src/fabric/build_top_module.cpp
@@ -169,8 +169,7 @@ vtr::Matrix<size_t> add_top_module_grid_instances(ModuleManager& module_manager,
         grid_instance_ids[io_coordinate.x()][io_coordinate.y()] = grid_instance_ids[root_grid_coord.x()][root_grid_coord.y()];
         continue;
       }
-      /* We should not meet any I/O grid */
-      VTR_ASSERT(true == is_io_type(grids[io_coordinate.x()][io_coordinate.y()].type));
+
       /* Add a grid module to top_module*/
       grid_instance_ids[io_coordinate.x()][io_coordinate.y()] = add_top_module_grid_instance(module_manager, top_module, grids[io_coordinate.x()][io_coordinate.y()].type, io_side, io_coordinate);
 
diff --git a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
index f69b57ae6..204b80260 100644
--- a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
+++ b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
@@ -685,8 +685,6 @@ void build_grid_bitstream(BitstreamManager& bitstream_manager,
         || (0 < grids[io_coordinate.x()][io_coordinate.y()].height_offset) ) {
         continue;
       }
-      /* We should not meet any I/O grid */
-      VTR_ASSERT(true == is_io_type(grids[io_coordinate.x()][io_coordinate.y()].type));
       build_physical_block_bitstream(bitstream_manager, top_block, module_manager,
                                      circuit_lib, mux_lib,
                                      device_annotation, cluster_annotation, 
diff --git a/openfpga/src/fpga_sdc/analysis_sdc_grid_writer.cpp b/openfpga/src/fpga_sdc/analysis_sdc_grid_writer.cpp
index d9a85280b..aa25c7e33 100644
--- a/openfpga/src/fpga_sdc/analysis_sdc_grid_writer.cpp
+++ b/openfpga/src/fpga_sdc/analysis_sdc_grid_writer.cpp
@@ -638,9 +638,6 @@ void print_analysis_sdc_disable_unused_grids(std::fstream& fp,
   /* Add instances of I/O grids to top_module */
   for (const e_side& io_side : io_sides) {
     for (const vtr::Point<size_t>& io_coordinate : io_coordinates[io_side]) {
-      /* We should not meet any I/O grid */
-      VTR_ASSERT(true == is_io_type(grids[io_coordinate.x()][io_coordinate.y()].type));
-
       print_analysis_sdc_disable_unused_grid(fp, io_coordinate,
                                              grids, device_annotation, cluster_annotation, place_annotation,
                                              module_manager, io_side);
diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
new file mode 100644
index 000000000..6d5bf7798
--- /dev/null
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
@@ -0,0 +1,322 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
+      <design_technology type="cmos" topology="OR"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <!--mux2to1 subckt_name="mux2to1"/-->
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <!--mux2to1 subckt_name="mux2to1"/-->
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <!--mux2to1 subckt_name="mux2to1"/-->
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <pass_gate_logic circuit_model_name="TGATE"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
+      <design_technology type="cmos" fracturable_lut="true"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="6" tri_state_map="----11" circuit_model_name="OR2"/>
+      <port type="output" prefix="lut4_out" size="4" lut_frac_level="4" lut_output_mask="0,1,2,3"/>
+      <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
+      <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
+      <port type="sram" prefix="sram" size="64"/>
+      <port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <pass_gate_logic circuit_model_name="TGATE"/>
+       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="Qb" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="inout" prefix="pad" size="1"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+      <port type="input" prefix="outpad" size="1"/>
+      <port type="output" prefix="inpad" size="1"/>
+    </circuit_model>
+    <circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="input" prefix="cin" size="1"/>
+      <port type="output" prefix="sumout" size="1"/>
+      <port type="output" prefix="cout" size="1"/>
+    </circuit_model>
+    <circuit_model type="hard_logic" name="dpram_512x32" prefix="dpram_512x32" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dpram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dpsram.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="waddr" size="10"/>
+      <port type="input" prefix="raddr" size="10"/>
+      <port type="input" prefix="d_in" size="32"/>
+      <port type="input" prefix="wen" size="1"/>
+      <port type="input" prefix="ren" size="1"/>
+      <port type="output" prefix="d_out" size="32"/>
+      <port type="clock" prefix="clk" size="1" is_global="true" default_val="0"/>
+    </circuit_model>
+    <circuit_model type="hard_logic" name="aib" prefix="aib" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/aib.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/aib.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="tx_data" size="80"/>
+      <port type="output" prefix="rx_data" size="80"/>
+      <port type="clock" prefix="tx_clk" size="1" default_val="0"/>
+      <port type="clock" prefix="rx_clk" size="1" default_val="0"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <direct_connection>
+    <direct name="adder_carry" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
+  </direct_connection>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block AIB-->
+    <pb_type name="aib[physical].aib_core" circuit_model_name="aib"/>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle" physical_mode_name="physical"/>
+    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
+    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
+    <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="adder"/>
+    <!-- Binding operating pb_type to physical pb_type -->
+    <!-- Binding operating pb_types in mode 'n2_lut5' -->
+    <pb_type name="clb.fle[n2_lut5].ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5">
+      <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:4]"/>
+      <port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[n2_lut5].ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <!-- Binding operating pb_types in mode 'arithmetic' -->
+    <pb_type name="clb.fle[arithmetic].arithmetic.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="11" physical_pb_type_index_factor="0.25">
+      <!-- Binding the lut4 to the first 4 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:3]"/>
+      <port name="out" physical_mode_port="lut4_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[arithmetic].arithmetic.adder" physical_pb_type_name="clb.fle[physical].fabric.adder"/>
+    <pb_type name="clb.fle[arithmetic].arithmetic.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <!-- Binding operating pb_types in mode 'ble6' -->
+    <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="00">
+      <!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:5]"/>
+      <port name="out" physical_mode_port="lut6_out"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
+    <!-- End physical pb_type binding in complex block clb -->
+
+
+    <!-- physical pb_type binding in complex block memory -->
+    <pb_type name="memory[mem_512x32_dp].mem_512x32_dp" circuit_model_name="dpram_512x32"/>
+    <!-- END physical pb_type binding in complex block memory -->
+  </pb_type_annotations>
+</openfpga_architecture>
+<openfpga_simulation_setting>
+  <clock_setting>
+    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
+    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
+    <programming frequency="10e6"/>
+  </clock_setting>
+  <simulator_option>
+    <operating_condition temperature="25"/>
+    <output_log verbose="false" captab="false"/>
+    <accuracy type="abs" value="1e-13"/>
+    <runtime fast_simulation="true"/>
+  </simulator_option>
+  <monte_carlo num_simulation_points="2"/>
+  <measurement_setting>
+    <slew>
+      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
+      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
+    </slew>
+    <delay>
+      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
+      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
+    </delay>
+  </measurement_setting>
+  <stimulus>
+    <clock>
+      <rise slew_type="abs" slew_time="20e-12" />
+      <fall slew_type="abs" slew_time="20e-12" />
+    </clock>
+    <input>
+      <rise slew_type="abs" slew_time="25e-12" />
+      <fall slew_type="abs" slew_time="25e-12" />
+    </input>
+  </stimulus>
+</openfpga_simulation_setting>
diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_aib.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_aib.openfpga
new file mode 100644
index 000000000..492c70ea6
--- /dev/null
+++ b/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_aib.openfpga
@@ -0,0 +1,62 @@
+# Run VPR for the 'and' design
+vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
+
+# Write out the architecture XML as a proof
+#write_openfpga_arch -f ./arch_echo.xml
+
+# Annotate the OpenFPGA architecture to VPR data base
+link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose
+
+# Write GSB to XML for debugging
+write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to clustering nets based on routing results
+pb_pin_fixup --verbose
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup #--verbose
+
+# Build the module graph 
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules 
+build_fabric --compress_routing --duplicate_grid_pin --verbose
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream 
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here 
+write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
+
+# Finish and exit OpenFPGA
+exit

From ff9cc50527b653127f2fa7db87d803b982f6b57b Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 27 Mar 2020 20:09:50 -0600
Subject: [PATCH 359/645] relax I/O circuit model checking to fit AIB
 interface. Adapt testbench generation for multiple types of I/O pads

---
 .../src/check_circuit_library.cpp             |   4 +-
 openfpga/src/fpga_sdc/analysis_sdc_writer.cpp | 137 ++++++++---------
 .../fpga_verilog/verilog_testbench_utils.cpp  | 139 +++++++++---------
 ...0_adder_chain_mem16K_aib_40nm_openfpga.xml |   3 +-
 4 files changed, 144 insertions(+), 139 deletions(-)

diff --git a/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp b/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp
index 93d5ae737..afe6e2173 100644
--- a/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp
+++ b/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp
@@ -462,7 +462,9 @@ void check_circuit_library(const CircuitLibrary& circuit_lib) {
   iopad_port_types_required.push_back(CIRCUIT_MODEL_PORT_INPUT);
   iopad_port_types_required.push_back(CIRCUIT_MODEL_PORT_OUTPUT);
   iopad_port_types_required.push_back(CIRCUIT_MODEL_PORT_INOUT);
-  iopad_port_types_required.push_back(CIRCUIT_MODEL_PORT_SRAM);
+  /* Some I/Os may not have SRAM port, such as AIB interface
+   * iopad_port_types_required.push_back(CIRCUIT_MODEL_PORT_SRAM);
+   */
 
   num_err += check_circuit_model_port_required(circuit_lib, CIRCUIT_MODEL_IOPAD, iopad_port_types_required);
 
diff --git a/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp b/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp
index de9dfb55d..aec9fc2e7 100644
--- a/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp
+++ b/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp
@@ -88,83 +88,84 @@ void print_analysis_sdc_io_delays(std::fstream& fp,
   VTR_ASSERT(1 == operating_clock_ports.size());
 
   /* In this function, we support only 1 type of I/Os */
-  VTR_ASSERT(1 == module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPIO_PORT).size());
-  BasicPort module_io_port = module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPIO_PORT)[0];
+  std::vector<BasicPort> module_io_ports = module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPIO_PORT);
 
-  /* Keep tracking which I/Os have been used */
-  std::vector<bool> io_used(module_io_port.get_width(), false);
+  for (const BasicPort& module_io_port : module_io_ports) {
+    /* Keep tracking which I/Os have been used */
+    std::vector<bool> io_used(module_io_port.get_width(), false);
 
-  /* Find clock ports in benchmark */
-  std::vector<std::string> benchmark_clock_port_names = find_atom_netlist_clock_port_names(atom_ctx.nlist, netlist_annotation);
+    /* Find clock ports in benchmark */
+    std::vector<std::string> benchmark_clock_port_names = find_atom_netlist_clock_port_names(atom_ctx.nlist, netlist_annotation);
 
-  /* Print comments */
-  fp << "##################################################" << std::endl; 
-  fp << "# Create input and output delays for used I/Os    " << std::endl;
-  fp << "##################################################" << std::endl; 
+    /* Print comments */
+    fp << "##################################################" << std::endl; 
+    fp << "# Create input and output delays for used I/Os    " << std::endl;
+    fp << "##################################################" << std::endl; 
 
-  for (const AtomBlockId& atom_blk : atom_ctx.nlist.blocks()) {
-    /* Bypass non-I/O atom blocks ! */
-    if ( (AtomBlockType::INPAD != atom_ctx.nlist.block_type(atom_blk))
-      && (AtomBlockType::OUTPAD != atom_ctx.nlist.block_type(atom_blk)) ) {
-      continue;
+    for (const AtomBlockId& atom_blk : atom_ctx.nlist.blocks()) {
+      /* Bypass non-I/O atom blocks ! */
+      if ( (AtomBlockType::INPAD != atom_ctx.nlist.block_type(atom_blk))
+        && (AtomBlockType::OUTPAD != atom_ctx.nlist.block_type(atom_blk)) ) {
+        continue;
+      }
+
+      /* clock net or constant generator should be disabled in timing analysis */
+      if (benchmark_clock_port_names.end() != std::find(benchmark_clock_port_names.begin(), benchmark_clock_port_names.end(), atom_ctx.nlist.block_name(atom_blk))) {
+        continue;
+      }
+
+      /* Find the index of the mapped GPIO in top-level FPGA fabric */
+      size_t io_index = io_location_map.io_index(place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.x,
+                                                 place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.y,
+                                                 place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.z);
+
+      /* Ensure that IO index is in range */
+      BasicPort module_mapped_io_port = module_io_port; 
+      /* Set the port pin index */ 
+      VTR_ASSERT(io_index < module_mapped_io_port.get_width());
+      module_mapped_io_port.set_width(io_index, io_index);
+
+      /* For input I/O, we set an input delay constraint correlated to the operating clock
+       * For output I/O, we set an output delay constraint correlated to the operating clock
+       */
+      if (AtomBlockType::INPAD == atom_ctx.nlist.block_type(atom_blk)) {
+        print_sdc_set_port_input_delay(fp, module_mapped_io_port,
+                                       operating_clock_ports[0], critical_path_delay);
+      } else {
+        VTR_ASSERT(AtomBlockType::OUTPAD == atom_ctx.nlist.block_type(atom_blk));
+        print_sdc_set_port_output_delay(fp, module_mapped_io_port,
+                                        operating_clock_ports[0], critical_path_delay);
+      }
+
+      /* Mark this I/O has been used/wired */
+      io_used[io_index] = true;
     }
 
-    /* clock net or constant generator should be disabled in timing analysis */
-    if (benchmark_clock_port_names.end() != std::find(benchmark_clock_port_names.begin(), benchmark_clock_port_names.end(), atom_ctx.nlist.block_name(atom_blk))) {
-      continue;
+    /* Add an empty line as a splitter */
+    fp << std::endl;
+
+    /* Print comments */
+    fp << "##################################################" << std::endl; 
+    fp << "# Disable timing for unused I/Os    " << std::endl;
+    fp << "##################################################" << std::endl; 
+
+    /* Wire the unused iopads to a constant */
+    for (size_t io_index = 0; io_index < io_used.size(); ++io_index) {
+      /* Bypass used iopads */
+      if (true == io_used[io_index]) {
+        continue;
+      }
+
+      /* Wire to a contant */
+      BasicPort module_unused_io_port = module_io_port; 
+      /* Set the port pin index */ 
+      module_unused_io_port.set_width(io_index, io_index);
+      print_sdc_disable_port_timing(fp, module_unused_io_port);
     }
 
-    /* Find the index of the mapped GPIO in top-level FPGA fabric */
-    size_t io_index = io_location_map.io_index(place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.x,
-                                               place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.y,
-                                               place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.z);
-
-    /* Ensure that IO index is in range */
-    BasicPort module_mapped_io_port = module_io_port; 
-    /* Set the port pin index */ 
-    VTR_ASSERT(io_index < module_mapped_io_port.get_width());
-    module_mapped_io_port.set_width(io_index, io_index);
-
-    /* For input I/O, we set an input delay constraint correlated to the operating clock
-     * For output I/O, we set an output delay constraint correlated to the operating clock
-     */
-    if (AtomBlockType::INPAD == atom_ctx.nlist.block_type(atom_blk)) {
-      print_sdc_set_port_input_delay(fp, module_mapped_io_port,
-                                     operating_clock_ports[0], critical_path_delay);
-    } else {
-      VTR_ASSERT(AtomBlockType::OUTPAD == atom_ctx.nlist.block_type(atom_blk));
-      print_sdc_set_port_output_delay(fp, module_mapped_io_port,
-                                      operating_clock_ports[0], critical_path_delay);
-    }
-
-    /* Mark this I/O has been used/wired */
-    io_used[io_index] = true;
+    /* Add an empty line as a splitter */
+    fp << std::endl;
   }
-
-  /* Add an empty line as a splitter */
-  fp << std::endl;
-
-  /* Print comments */
-  fp << "##################################################" << std::endl; 
-  fp << "# Disable timing for unused I/Os    " << std::endl;
-  fp << "##################################################" << std::endl; 
-
-  /* Wire the unused iopads to a constant */
-  for (size_t io_index = 0; io_index < io_used.size(); ++io_index) {
-    /* Bypass used iopads */
-    if (true == io_used[io_index]) {
-      continue;
-    }
-
-    /* Wire to a contant */
-    BasicPort module_unused_io_port = module_io_port; 
-    /* Set the port pin index */ 
-    module_unused_io_port.set_width(io_index, io_index);
-    print_sdc_disable_port_timing(fp, module_unused_io_port);
-  }
-
-  /* Add an empty line as a splitter */
-  fp << std::endl;
 }
 
 /********************************************************************
diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
index e952d13c4..dae42f042 100644
--- a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
+++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
@@ -132,86 +132,87 @@ void print_verilog_testbench_connect_fpga_ios(std::fstream& fp,
   valid_file_stream(fp);
 
   /* In this function, we support only 1 type of I/Os */
-  VTR_ASSERT(1 == module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPIO_PORT).size());
-  BasicPort module_io_port = module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPIO_PORT)[0];
+  std::vector<BasicPort> module_io_ports = module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPIO_PORT);
 
   /* Keep tracking which I/Os have been used */
-  std::vector<bool> io_used(module_io_port.get_width(), false);
+  for (const BasicPort& module_io_port : module_io_ports) {
+    std::vector<bool> io_used(module_io_port.get_width(), false);
 
-  /* See if this I/O should be wired to a benchmark input/output */
-  /* Add signals from blif benchmark and short-wire them to FPGA I/O PADs
-   * This brings convenience to checking functionality  
-   */
-  print_verilog_comment(fp, std::string("----- Link BLIF Benchmark I/Os to FPGA I/Os -----"));
-
-  for (const AtomBlockId& atom_blk : atom_ctx.nlist.blocks()) {
-    /* Bypass non-I/O atom blocks ! */
-    if ( (AtomBlockType::INPAD != atom_ctx.nlist.block_type(atom_blk))
-      && (AtomBlockType::OUTPAD != atom_ctx.nlist.block_type(atom_blk)) ) {
-      continue;
-    }
-
-    /* Find the index of the mapped GPIO in top-level FPGA fabric */
-    size_t io_index = io_location_map.io_index(place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.x,
-                                               place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.y,
-                                               place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.z);
-
-    /* Ensure that IO index is in range */
-    BasicPort module_mapped_io_port = module_io_port; 
-    /* Set the port pin index */ 
-    VTR_ASSERT(io_index < module_mapped_io_port.get_width());
-    module_mapped_io_port.set_width(io_index, io_index);
-
-    /* The block may be renamed as it contains special characters which violate Verilog syntax */
-    std::string block_name = atom_ctx.nlist.block_name(atom_blk);
-    if (true == netlist_annotation.is_block_renamed(atom_blk)) {
-      block_name = netlist_annotation.block_name(atom_blk);
-    } 
-
-    /* Create the port for benchmark I/O, due to BLIF benchmark, each I/O always has a size of 1 
-     * In addition, the input and output ports may have different postfix in naming
-     * due to verification context! Here, we give full customization on naming 
+    /* See if this I/O should be wired to a benchmark input/output */
+    /* Add signals from blif benchmark and short-wire them to FPGA I/O PADs
+     * This brings convenience to checking functionality  
      */
-    BasicPort benchmark_io_port;
-    if (AtomBlockType::INPAD == atom_ctx.nlist.block_type(atom_blk)) {
-      benchmark_io_port.set_name(std::string(block_name + io_input_port_name_postfix)); 
-      benchmark_io_port.set_width(1);
-      print_verilog_comment(fp, std::string("----- Blif Benchmark input " + block_name + " is mapped to FPGA IOPAD " + module_mapped_io_port.get_name() + "[" + std::to_string(io_index) + "] -----"));
-      print_verilog_wire_connection(fp, module_mapped_io_port, benchmark_io_port, false);
-    } else {
-      VTR_ASSERT(AtomBlockType::OUTPAD == atom_ctx.nlist.block_type(atom_blk));
-      benchmark_io_port.set_name(std::string(block_name + io_output_port_name_postfix)); 
-      benchmark_io_port.set_width(1);
-      print_verilog_comment(fp, std::string("----- Blif Benchmark output " + block_name + " is mapped to FPGA IOPAD " + module_mapped_io_port.get_name() + "[" + std::to_string(io_index) + "] -----"));
-      print_verilog_wire_connection(fp, benchmark_io_port, module_mapped_io_port, false);
+    print_verilog_comment(fp, std::string("----- Link BLIF Benchmark I/Os to FPGA I/Os -----"));
+
+    for (const AtomBlockId& atom_blk : atom_ctx.nlist.blocks()) {
+      /* Bypass non-I/O atom blocks ! */
+      if ( (AtomBlockType::INPAD != atom_ctx.nlist.block_type(atom_blk))
+        && (AtomBlockType::OUTPAD != atom_ctx.nlist.block_type(atom_blk)) ) {
+        continue;
+      }
+
+      /* Find the index of the mapped GPIO in top-level FPGA fabric */
+      size_t io_index = io_location_map.io_index(place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.x,
+                                                 place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.y,
+                                                 place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.z);
+
+      /* Ensure that IO index is in range */
+      BasicPort module_mapped_io_port = module_io_port; 
+      /* Set the port pin index */ 
+      VTR_ASSERT(io_index < module_mapped_io_port.get_width());
+      module_mapped_io_port.set_width(io_index, io_index);
+
+      /* The block may be renamed as it contains special characters which violate Verilog syntax */
+      std::string block_name = atom_ctx.nlist.block_name(atom_blk);
+      if (true == netlist_annotation.is_block_renamed(atom_blk)) {
+        block_name = netlist_annotation.block_name(atom_blk);
+      } 
+
+      /* Create the port for benchmark I/O, due to BLIF benchmark, each I/O always has a size of 1 
+       * In addition, the input and output ports may have different postfix in naming
+       * due to verification context! Here, we give full customization on naming 
+       */
+      BasicPort benchmark_io_port;
+      if (AtomBlockType::INPAD == atom_ctx.nlist.block_type(atom_blk)) {
+        benchmark_io_port.set_name(std::string(block_name + io_input_port_name_postfix)); 
+        benchmark_io_port.set_width(1);
+        print_verilog_comment(fp, std::string("----- Blif Benchmark input " + block_name + " is mapped to FPGA IOPAD " + module_mapped_io_port.get_name() + "[" + std::to_string(io_index) + "] -----"));
+        print_verilog_wire_connection(fp, module_mapped_io_port, benchmark_io_port, false);
+      } else {
+        VTR_ASSERT(AtomBlockType::OUTPAD == atom_ctx.nlist.block_type(atom_blk));
+        benchmark_io_port.set_name(std::string(block_name + io_output_port_name_postfix)); 
+        benchmark_io_port.set_width(1);
+        print_verilog_comment(fp, std::string("----- Blif Benchmark output " + block_name + " is mapped to FPGA IOPAD " + module_mapped_io_port.get_name() + "[" + std::to_string(io_index) + "] -----"));
+        print_verilog_wire_connection(fp, benchmark_io_port, module_mapped_io_port, false);
+      }
+
+      /* Mark this I/O has been used/wired */
+      io_used[io_index] = true;
     }
 
-    /* Mark this I/O has been used/wired */
-    io_used[io_index] = true;
-  }
+    /* Add an empty line as a splitter */
+    fp << std::endl;
 
-  /* Add an empty line as a splitter */
-  fp << std::endl;
+    /* Wire the unused iopads to a constant */
+    print_verilog_comment(fp, std::string("----- Wire unused FPGA I/Os to constants -----"));
+    for (size_t io_index = 0; io_index < io_used.size(); ++io_index) {
+      /* Bypass used iopads */
+      if (true == io_used[io_index]) {
+        continue;
+      }
 
-  /* Wire the unused iopads to a constant */
-  print_verilog_comment(fp, std::string("----- Wire unused FPGA I/Os to constants -----"));
-  for (size_t io_index = 0; io_index < io_used.size(); ++io_index) {
-    /* Bypass used iopads */
-    if (true == io_used[io_index]) {
-      continue;
+      /* Wire to a contant */
+      BasicPort module_unused_io_port = module_io_port; 
+      /* Set the port pin index */ 
+      module_unused_io_port.set_width(io_index, io_index);
+
+      std::vector<size_t> default_values(module_unused_io_port.get_width(), unused_io_value);
+      print_verilog_wire_constant_values(fp, module_unused_io_port, default_values);
     }
 
-    /* Wire to a contant */
-    BasicPort module_unused_io_port = module_io_port; 
-    /* Set the port pin index */ 
-    module_unused_io_port.set_width(io_index, io_index);
-
-    std::vector<size_t> default_values(module_unused_io_port.get_width(), unused_io_value);
-    print_verilog_wire_constant_values(fp, module_unused_io_port, default_values);
+    /* Add an empty line as a splitter */
+    fp << std::endl;
   }
-
-  /* Add an empty line as a splitter */
-  fp << std::endl;
 }
 
 /********************************************************************
diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
index 6d5bf7798..ea56fe036 100644
--- a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
@@ -209,7 +209,7 @@
       <port type="output" prefix="d_out" size="32"/>
       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0"/>
     </circuit_model>
-    <circuit_model type="hard_logic" name="aib" prefix="aib" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/aib.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/aib.v">
+    <circuit_model type="iopad" name="aib" prefix="aib" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/aib.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/aib.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
@@ -218,6 +218,7 @@
       <port type="output" prefix="rx_data" size="80"/>
       <port type="clock" prefix="tx_clk" size="1" default_val="0"/>
       <port type="clock" prefix="rx_clk" size="1" default_val="0"/>
+      <port type="inout" prefix="pad" size="80"/>
     </circuit_model>
   </circuit_library>
   <configuration_protocol>

From 07e1979498db390bb709c364336ce58fc2f3cf87 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 28 Mar 2020 15:41:26 -0600
Subject: [PATCH 360/645] add architecture examples on wide memory blocks
 (width=2). tileable routing is working

---
 ..._tileable_adder_chain_wide_mem16K.openfpga |  62 ++
 ..._tileable_adder_chain_wide_mem16K_40nm.xml | 734 ++++++++++++++++++
 .../rr_graph_builder_utils.cpp                |   6 +-
 3 files changed, 799 insertions(+), 3 deletions(-)
 create mode 100644 openfpga/test_script/and_k6_frac_tileable_adder_chain_wide_mem16K.openfpga
 create mode 100644 openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml

diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_chain_wide_mem16K.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_chain_wide_mem16K.openfpga
new file mode 100644
index 000000000..466c3bcd0
--- /dev/null
+++ b/openfpga/test_script/and_k6_frac_tileable_adder_chain_wide_mem16K.openfpga
@@ -0,0 +1,62 @@
+# Run VPR for the 'and' design
+vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
+
+# Write out the architecture XML as a proof
+#write_openfpga_arch -f ./arch_echo.xml
+
+# Annotate the OpenFPGA architecture to VPR data base
+link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose
+
+# Write GSB to XML for debugging
+write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to clustering nets based on routing results
+pb_pin_fixup --verbose
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup #--verbose
+
+# Build the module graph 
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules 
+build_fabric --compress_routing --duplicate_grid_pin --verbose
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream 
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here 
+write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
+
+# Finish and exit OpenFPGA
+exit
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml
new file mode 100644
index 000000000..f07f16c80
--- /dev/null
+++ b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml
@@ -0,0 +1,734 @@
+<!-- 
+  Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with 8 total FLE inputs (2 inputs of which are shared by the 5-LUTs) 
+    with optionally registered outputs
+    Each 5-LUT has an arithemtic mode that converts it to a single-bit adder with both inputs driven by 4-LUTs (both 4-LUTs share all 4 inputs)
+    Carry chain links to vertically adjacent logic blocks
+  - Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.  
+    Height = 6, found on every (8n+2)th column
+  - Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.  
+    Height = 4, found on every (8n+6)th column
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Details on Modelling:
+
+  The electrical design of the architecture described here is NOT from an 
+  optimized, SPICED architecture.  Instead, we attempt to create a reasonable 
+  architecture file by using an existing commercial FPGA to approximate the area, 
+  delay, and power of the underlying components. This is combined with a reasonable 40 nm 
+  model of wiring and circuit design for low-level routing components, where available.
+  The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also 
+  has wiring electrical parameters that allow the wire lengths and switch patterns to be 
+  modified and you will still get reasonable delay results for the new architecture.
+  The following describes, in detail, how we obtained the various electrical values for this 
+  architecture.
+
+  Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar 
+  architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture. 
+  (n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)      
+  This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to 
+  match the overall target (a 40 nm FPGA).
+
+  We obtain delay numbers by measuring delays of routing, soft logic blocks, 
+  memories, and multipliers from test circuits on a Stratix IV GX device 
+  (EP4SGX230DF29C2X, i.e. fastest speed grade). For routing, we took the average delay of H4 and V4 
+  wires.  Rmetal and Cmetal values for the routing wires were obtained from work done by Charles 
+  Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal stack 40 nm routing) and 
+  take the R and C data from the ITRS roadmap.  
+
+  For the general purpose logic block, we assume that the area and delays of the Stratix IV 
+  crossbar is close enough to the crossbar modelled here.  
+  Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to 
+  36:1 multiplexers.  We match these parameters in this architecture.
+
+  For LUTs, we include LUT 
+  delays measured from Stratix IV which is dependant on the input used (ie. some 
+  LUT inputs are faster than others).  The CAD tools at the time of VTR 7 does 
+  not consider differences in LUT input delays.
+
+  Adder delays obtained as approximate values from a Stratix IV EP4SE230F29C3 device.  
+  Delay obtained by compiling a 256 bit adder (registered inputs and outputs, 
+  all pins except clock virtual) then measuring the delays in chip-planner, 
+  sumout delay = 0.271ns to 0.348 ns, intra-block carry delay = 0.011 ns, 
+  inter-block carry delay = 0.327 ns.  Given this data, I will approximate 
+  sumout 0.3 ns, intra-block carry-delay = 0.01 ns, and 
+  inter-block carry-delay = 0.16 ns (since Altera inter-block carry delay has 
+  overhead that we don't have, I'll approximate the delay of a simpler chain at 
+  one half what they have.  This is very rough, anything from 0.01ns to 0.327ns 
+  can be justified).
+
+  Logic block area numbers obtained by scaling overall tile area of a 65nm 
+  Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out 
+  routing area at a channel width of 300. We use a channel width of 300 because it can route 
+  all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
+  total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
+  choosing a width that provides high routability. The architecture can be routed at different channel
+  widths, but we estimate the tile size and hence the physical length of routing wires assuming
+  a channel width of 300.
+
+  Sanity checks employed:
+    1.  We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches 
+        common electrical design.
+
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <model name="adder">
+      <input_ports>
+        <port name="a" combinational_sink_ports="sumout cout"/>
+        <port name="b" combinational_sink_ports="sumout cout"/>
+        <port name="cin" combinational_sink_ports="sumout cout"/>
+      </input_ports>
+      <output_ports>
+        <port name="cout"/>
+        <port name="sumout"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="frac_lut6">
+      <input_ports>
+        <port name="in"/>
+      </input_ports>
+      <output_ports>
+        <port name="lut4_out"/>
+        <port name="lut5_out"/>
+        <port name="lut6_out"/>
+      </output_ports>
+    </model>
+    <model name="dual_port_ram">
+      <input_ports>
+        <!-- write address lines -->
+        <port name="waddr" clock="clk"/>
+        <!-- read address lines -->
+        <port name="raddr" clock="clk"/>
+        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
+        <port name="d_in" clock="clk"/>
+        <!-- write enable -->
+        <port name="wen" clock="clk"/>
+        <!-- read enable -->
+        <port name="ren" clock="clk"/>
+        <!-- memories are often clocked -->
+        <port name="clk" is_clock="1"/>
+      </input_ports>
+      <output_ports>
+        <!-- output can be broken down into smaller bit widths minimum size 1 -->
+        <port name="d_out" clock="clk"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <tile name="io" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad</loc>
+        <loc side="top">io.outpad io.inpad</loc>
+        <loc side="right">io.outpad io.inpad</loc>
+        <loc side="bottom">io.outpad io.inpad</loc>
+      </pinlocations>
+    </tile>
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
+      </fc>
+      <!--  Highly recommand to customize pin location when direct connection is used!!! -->
+      <!--pinlocations pattern="spread"/-->
+      <pinlocations pattern="custom">
+        <loc side="left">clb.clk</loc>
+        <loc side="top">clb.cin</loc>
+        <loc side="right">clb.O[9:0] clb.I[19:0]</loc>
+        <loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
+      </pinlocations>
+    </tile>
+    <tile name="memory" width="2" height="2" area="548000">
+      <equivalent_sites>
+        <site pb_type="memory"/>
+      </equivalent_sites>
+      <input name="waddr" num_pins="10"/>
+      <input name="raddr" num_pins="10"/>
+      <input name="d_in" num_pins="32"/>
+      <input name="wen" num_pins="1"/>
+      <input name="ren" num_pins="1"/>
+      <output name="d_out" num_pins="32"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="spread"/>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout tileable="true" through_channel="false">
+    <!--auto_layout aspect_ratio="1.0"-->
+    <fixed_layout name="4x4" width="6" height="6">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
+      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
+    </fixed_layout>
+    <!-- /auto_layout -->
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	    -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+           book area formula. This means the mux transistors are about 5x minimum drive strength.
+           We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+           mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+           the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+           by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+           buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+           I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+           (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+           The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+           2.5x when looking up in Jeff's tables.
+           Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+           This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+             With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+             reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <directlist>
+    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
+  </directlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+
+      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+           If you need to register the I/O, define clocks in the circuit models
+           These clocks can be handled in back-end
+       -->
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" disabled_in_pack="true">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe fracturable logic element.  
+             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
+             The outputs of the fracturable logic element can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="10">
+        <input name="in" num_pins="6"/>
+        <input name="cin" num_pins="1"/>
+        <output name="out" num_pins="2"/>
+        <output name="cout" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- Physical mode definition begin (physical implementation of the fle) -->
+        <mode name="physical" disabled_in_pack="true">
+          <pb_type name="fabric" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="frac_logic" num_pb="1">
+              <input name="in" num_pins="6"/>
+              <output name="lut4_out" num_pins="4"/>
+              <output name="out" num_pins="2"/>
+              <!-- Define LUT -->
+              <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
+                <input name="in" num_pins="6"/>
+                <output name="lut4_out" num_pins="4"/>
+                <output name="lut5_out" num_pins="2"/>
+                <output name="lut6_out" num_pins="1"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
+                <direct name="direct2" input="frac_lut6.lut4_out" output="frac_logic.lut4_out"/>
+                <direct name="direct3" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
+                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
+                <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
+              </interconnect>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>         
+            <!-- Define adders -->
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="2">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
+              <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
+              <direct name="direct3" input="fabric.cin" output="adder[0:0].cin"/>
+              <direct name="direct4" input="adder[0:0].cout" output="adder[1:1].cin"/>
+              <direct name="direct5" input="adder[1:1].cout" output="fabric.cout"/>
+              <direct name="direct6" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
+              <direct name="direct7" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
+              <direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
+              <direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
+              <complete name="direct10" input="fabric.clk" output="ff[1:0].clk"/>
+              <mux name="mux1" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
+                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
+              </mux>
+              <mux name="mux2" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
+                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="fabric.in"/>
+            <direct name="direct2" input="fle.cin" output="fabric.cin"/>
+            <direct name="direct3" input="fabric.out" output="fle.out"/>
+            <direct name="direct4" input="fabric.cout" output="fle.cout"/>
+            <direct name="direct5" input="fle.clk" output="fabric.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Physical mode definition end (physical implementation of the fle) -->
+        <!-- BEGIN fle mode of dual lut5 -->
+        <mode name="n2_lut5">
+          <pb_type name="ble5" num_pb="2">
+            <input name="in" num_pins="5"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Regular LUT mode -->
+            <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="5" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                  we instead take the average of these numbers to get more stable results
+                82e-12
+                173e-12
+                261e-12
+                263e-12
+                398e-12
+                -->
+              <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+              </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble5.in" output="lut5.in"/>
+              <direct name="direct2" input="lut5.out" output="ff.D">
+                <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble5.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut5.out" output="ble5.out">
+                <delay_constant max="25e-12" in_port="lut5.out" out_port="ble5.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble5.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[4:0]" output="ble5[0:0].in"/>
+            <direct name="direct2" input="fle.in[4:0]" output="ble5[1:1].in"/>
+            <complete name="direct3" input="fle.clk" output="ble5.clk"/>
+            <direct name="direct4" input="ble5.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- END fle mode of dual lut5 -->
+        <!-- BEGIN arithmetic mode of dual lut4 + adders -->
+        <mode name="arithmetic">
+          <pb_type name="arithmetic" num_pb="2">
+            <input name="in" num_pins="4"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="1"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Special dual-LUT mode that drives adder only -->
+            <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
+              <input name="in" num_pins="4" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  -->
+              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                  195e-12
+                  195e-12
+                  195e-12
+                  195e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
+              <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
+              <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
+              <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
+                </direct>
+              <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
+                </direct>
+              <direct name="add_to_ff" input="adder.sumout" output="ff.D">
+                <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
+              </direct>
+              <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
+                <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
+              </direct>
+              <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
+                <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
+              </direct>
+              <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
+                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[3:0]" output="arithmetic[0:0].in"/>
+            <direct name="direct2" input="fle.in[3:0]" output="arithmetic[1:1].in"/>
+            <direct name="carry_in" input="fle.cin" output="arithmetic[0:0].cin">
+              <pack_pattern name="chain" in_port="fle.cin" out_port="arithmetic[0:0].cin"/>
+            </direct>
+            <direct name="carry_inter" input="arithmetic[0:0].cout" output="arithmetic[1:1].cin">
+              <pack_pattern name="chain" in_port="arithmetic[0:0].cout" out_port="arithmetic[1:1].cin"/>
+            </direct>
+            <direct name="carry_out" input="arithmetic[1:1].cout" output="fle.cout">
+              <pack_pattern name="chain" in_port="arithmetic.cout" out_port="fle.cout"/>
+            </direct>
+            <complete name="direct3" input="fle.clk" output="arithmetic.clk"/>
+            <direct name="direct4" input="arithmetic.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- n2_lut5 -->
+        <mode name="n1_lut6">
+          <pb_type name="ble6" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="6" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->
+              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+              <direct name="direct2" input="lut6.out" output="ff.D">
+                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
+            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+          </interconnect>
+        </mode>
+        <!-- n1_lut6 -->
+      </pb_type>
+      <interconnect>
+        <!-- We use a 50% depop crossbar built using small full xbars to get sets of logically equivalent pins at inputs of CLB 
+           The delays below come from Stratix IV. the delay through a connection block
+           input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+           delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+           delay within the crossbar is 95 ps. 
+           The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+           Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+           25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+           to get the part that should be marked on the crossbar.	 -->
+        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
+          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
+          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
+        </complete>
+
+        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+        </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+                 By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+                 then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+                 naive specification).
+          -->
+        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
+        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
+        <!-- Carry chain links -->
+        <direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
+          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
+        </direct>
+        <direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
+          <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
+        </direct>
+        <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
+          <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
+        </direct>
+      </interconnect>
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+    <!-- Define single-mode dual-port memory begin -->
+    <pb_type name="memory">
+      <input name="waddr" num_pins="10"/>
+      <input name="raddr" num_pins="10"/>
+      <input name="d_in" num_pins="32"/>
+      <input name="wen" num_pins="1"/>
+      <input name="ren" num_pins="1"/>
+      <output name="d_out" num_pins="32"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Specify the 512x32=16Kbit memory block
+           Note: the delay numbers are extracted from VPR flagship XML without modification
+                 Should align to the process technology we using to create the 16K dual-port RAM
+        -->
+      <mode name="mem_512x32_dp">
+        <pb_type name="mem_512x32_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
+          <input name="waddr" num_pins="10" port_class="address"/>
+          <input name="raddr" num_pins="10" port_class="address"/>
+          <input name="d_in" num_pins="32" port_class="data_in"/>
+          <input name="wen" num_pins="1" port_class="write_en"/>
+          <input name="ren" num_pins="1" port_class="write_en"/>
+          <output name="d_out" num_pins="32" port_class="data_out"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.waddr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.raddr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.d_in" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.wen" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.ren" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_512x32_dp.d_out" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="17.9e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="waddress" input="memory.waddr" output="mem_512x32_dp.waddr">
+            <delay_constant max="132e-12" in_port="memory.waddr" out_port="mem_512x32_dp.waddr"/>
+          </direct>
+          <direct name="raddress" input="memory.raddr" output="mem_512x32_dp.raddr">
+            <delay_constant max="132e-12" in_port="memory.raddr" out_port="mem_512x32_dp.raddr"/>
+          </direct>
+          <direct name="data_input" input="memory.d_in" output="mem_512x32_dp.d_in">
+            <delay_constant max="132e-12" in_port="memory.d_in" out_port="mem_512x32_dp.d_in"/>
+          </direct>
+          <direct name="writeen" input="memory.wen" output="mem_512x32_dp.wen">
+            <delay_constant max="132e-12" in_port="memory.wen" out_port="mem_512x32_dp.wen"/>
+          </direct>
+          <direct name="readen" input="memory.ren" output="mem_512x32_dp.ren">
+            <delay_constant max="132e-12" in_port="memory.ren" out_port="mem_512x32_dp.ren"/>
+          </direct>
+          <direct name="dataout" input="mem_512x32_dp.d_out" output="memory.d_out">
+            <delay_constant max="40e-12" in_port="mem_512x32_dp.d_out" out_port="memory.d_out"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_512x32_dp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+    </pb_type>
+    <!-- Define single-mode dual-port memory end -->
+  </complexblocklist>
+</architecture>
diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp
index acead971f..a599c8194 100644
--- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp
+++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp
@@ -195,7 +195,7 @@ bool is_chanx_exist(const DeviceGrid& grids,
  ***********************************************************************/
 bool is_chany_exist(const DeviceGrid& grids,
                     const vtr::Point<size_t>& chany_coord) {
-  return (grids[chany_coord.x()][chany_coord.y()].width_offset == grids[chany_coord.y()][chany_coord.y()].type->width - 1);
+  return (grids[chany_coord.x()][chany_coord.y()].width_offset == grids[chany_coord.x()][chany_coord.y()].type->width - 1);
 }
 
 /************************************************************************
@@ -299,7 +299,7 @@ bool is_chany_top_to_multi_width_grid(const DeviceGrid& grids,
   }
   
   if (false == through_channel) {
-    /* We check the bottom neighbor of chany, if it does not exist, the chany is left to a multi-height grid */
+    /* We check the bottom neighbor of chany, if it does not exist, the chany is top to a multi-height grid */
     vtr::Point<size_t> bottom_chany_coord(chany_coord.x(), chany_coord.y() - 1);
     if (false == is_chany_exist(grids, bottom_chany_coord)) {
       return true;
@@ -317,7 +317,7 @@ bool is_chany_top_to_multi_width_grid(const DeviceGrid& grids,
  *     |                 |
  *     |                 | 
  *     |      Grid       | 
- *     |    [x+1][y]     | 
+ *     |    [x][y+1]     | 
  *     |                 | 
  *     |                 |
  *     +-----------------+

From 5d12f499f0adbf968f5d48662fe2337c7365db57 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 29 Mar 2020 16:26:23 -0600
Subject: [PATCH 361/645] hotfix on undriven pins on the connection blocks

---
 vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c
index c2f520d4d..d3f3539e5 100644
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c
@@ -1149,6 +1149,11 @@ RRGSB build_rr_gsb(DeviceCoordinator& device_range,
                                                    LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices);
     /* Fill the ipin nodes of RRGSB */ 
     for (int inode = 0; inode < num_temp_ipin_rr_nodes; ++inode) {
+      /* Skip Fc = 0  pins, they should NOT appear in the GSB connection */
+      if (0. == grid[temp_ipin_rr_node[inode]->xlow][temp_ipin_rr_node[inode]->ylow].type->Fc[temp_ipin_rr_node[inode]->ptc_num]) {
+        continue;
+      }
+
       rr_gsb.add_ipin_node(temp_ipin_rr_node[inode], side_manager.get_side(), ipin_rr_node_grid_side);
     }
     /* Free */

From 63306ce3a09e057733e2332fc743dfe1decebdfc Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 1 Apr 2020 11:05:30 -0600
Subject: [PATCH 362/645] add comments to explain the memory organization in
 the top-level module

---
 .../src/fabric/build_top_module_memory.cpp    | 39 ++++++++++++++++++-
 1 file changed, 37 insertions(+), 2 deletions(-)

diff --git a/openfpga/src/fabric/build_top_module_memory.cpp b/openfpga/src/fabric/build_top_module_memory.cpp
index 37f67f0be..21f7a5e6c 100644
--- a/openfpga/src/fabric/build_top_module_memory.cpp
+++ b/openfpga/src/fabric/build_top_module_memory.cpp
@@ -177,7 +177,29 @@ void organize_top_module_tile_memory_modules(ModuleManager& module_manager,
  * the sequence of memory_modules and memory_instances will follow
  * a chain of tiles considering their physical location
  *
- * Inter tile connection:
+ * Inter-tile connection:
+ *
+ * Inter-tile connection always start from the I/O peripherals 
+ * and the core tiles (CLBs and heterogeneous blocks).
+ * The sequence of configuration memory will be organized as follows:
+ *   - I/O peripherals
+ *     - BOTTOM side (From left to right)
+ *     - RIGHT side (From bottom to top)
+ *     - TOP side (From left to right)
+ *     - LEFT side (From top to bottom)
+ *   - Core tiles
+ *     - Tiles at the bottom row, i.e., Tile[0..i] (From left to right)
+ *     - One row upper, i.e. Tile[i+1 .. j] (From right to left)
+ *     - Repeat until we finish all the rows
+ *
+ *   Note: the tail may not always be on the top-right corner as shown in the figure.
+ *         It may exit at the top-left corner.
+ *         This really depends on the number of rows your have in the core tile array.
+ *
+ *   Note: the organization of inter-tile aims to reduce the wire length
+ *         to connect between tiles. Therefore, it is organized as a snake
+ *         where we can avoid long wires between rows and columns
+ *
  *    +--------------------------------------------------------+
  *    |              +------+------+-----+------+              |
  *    |              | I/O  | I/O  | ... | I/O  |              |
@@ -210,7 +232,20 @@ void organize_top_module_tile_memory_modules(ModuleManager& module_manager,
  *                   +------+------+-----+------+              |
  *        head >-----------------------------------------------+
  *
- * Inner tile connection
+ * Inner tile connection:
+ *
+ *   Inside each tile, the configuration memory will be organized
+ *   in the following sequence:
+ *     - Switch Block (SB)
+ *     - X-directional Connection Block (CBX)
+ *     - Y-directional Connection Block (CBY)
+ *     - Configurable Logic Block (CLB), which could also be heterogeneous blocks
+ *
+ *   Note:
+ *     Due to multi-column and multi-width hetergeoenous blocks,
+ *     each tile may not have one or more of SB, CBX, CBY, CLB
+ *     In such case, the sequence will be respected.
+ *     The missing block will just be skipped when organizing the configuration memories.
  *
  *       Tile
  *     +---------------+----------+

From fd8248d9dd02fd05c2fac0b47e0fffcae5c0da23 Mon Sep 17 00:00:00 2001
From: Xifan Tang <tangxifan@gmail.com>
Date: Wed, 1 Apr 2020 12:35:52 -0600
Subject: [PATCH 363/645] update documentation: the addon syntax on VPR and
 configuration protocols

---
 docs/source/arch_lang/addon_vpr_syntax.rst    |  54 +++++++++++++--
 docs/source/arch_lang/annotate_vpr_arch.rst   |  65 ++++++++++++++++--
 .../arch_lang/circuit_model_examples.rst      |   4 +-
 docs/source/arch_lang/figures/ccff_fpga.png   | Bin 0 -> 78496 bytes
 4 files changed, 109 insertions(+), 14 deletions(-)
 create mode 100644 docs/source/arch_lang/figures/ccff_fpga.png

diff --git a/docs/source/arch_lang/addon_vpr_syntax.rst b/docs/source/arch_lang/addon_vpr_syntax.rst
index 1e2da988f..c6ac221a2 100644
--- a/docs/source/arch_lang/addon_vpr_syntax.rst
+++ b/docs/source/arch_lang/addon_vpr_syntax.rst
@@ -5,11 +5,18 @@ Additional Syntax to Original VPR XML
 
 .. warning:: Note this is only applicable to VPR8!
 
+Models, Complex blocks and Physical Tiles
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   
 Each ``<pb_type>`` should contain a ``<mode>`` that describe the physical implementation of the ``<pb_type>``. Note that this is fully compatible to the VPR architecture XML syntax.
   
 ``<model>`` should include the models that describe the primitive ``<pb_type>`` in physical mode.
   
+.. note:: Currently, OpenFPGA only supports 1 ``<equivalent_sites>`` to be defined under each ``<tile>``
+
+Layout
+~~~~~~
+
 ``<layout>`` may include additioinal syntax to enable tileable routing resource graph generation
 
 .. option:: tileable="<bool>"
@@ -35,15 +42,27 @@ Each ``<pb_type>`` should contain a ``<mode>`` that describe the physical implem
   
      Impact on routing architecture when through channel in multi-width and multi-height programmable blocks: (a) disabled; (b) enabled.
 
-  .. warning:: Do NOT enable if you are not using the tileable routing resource graph generator!
+  .. warning:: Do NOT enable ``through_channel`` if you are not using the tileable routing resource graph generator!
+  
+  .. warning:: Currently ``through_channel`` supports only a fixed routing channel width!
 
-  .. warning:: Current through channel supports only a fixed routing channel!
+
+A quick example to show tileable routing is enabled and through channels are disabled:
+
+.. code-block:: xml
+
+  <layout tileable="true" through_channel="false">
+  </layout>
+
+Switch Block
+~~~~~~~~~~~~
 
 ``<switch_block>`` may include addition syntax to enable different connectivity for pass tracks
 
 .. option:: sub_type="<string>"
   
   Connecting type for pass tracks in each switch block
+  The supported connecting patterns are ``subset``, ``universal`` and ``wilton``, being the same as VPR capability
   If not specified, the pass tracks will the same connecting patterns as start/end tracks, which are defined in ``type``
 
 .. option:: sub_Fs="<int>"
@@ -51,10 +70,31 @@ Each ``<pb_type>`` should contain a ``<mode>`` that describe the physical implem
   Connectivity parameter for pass tracks in each switch block. Must be a multiple of 3.
   If not specified, the pass tracks will the same connectivity as start/end tracks, which are defined in ``fs``
 
+A quick example which defines a switch block
+  - Starting/ending routing tracks are connected in the ``wilton`` pattern
+  - Each starting/ending routing track can drive 3 other starting/ending routing tracks
+  - Passing routing tracks are connected in the ``subset`` pattern
+  - Each passing routing track can drive 6 other starting/ending routing tracks
+
+.. code-block:: xml
+
+  <device>
+    <switch_block type="wilton" fs="3" sub_type="subset" sub_fs="6"/>
+  </device>
+
+Routing Segments
+~~~~~~~~~~~~~~~~
+
+OpenFPGA suggests users to give explicit names for each routing segement in ``<segmentlist>`` 
+This is used to link ``circuit_model`` to routing segments.
+
+A quick example which defines a length-4 uni-directional routing segment called ``L4`` :
+
+.. code-block:: xml
+
+  <segmentlist>
+    <segment name="L4" freq="1" length="4" type="undir"/>
+  </segmentlist>
+
 .. note:: Currently, OpenFPGA only supports uni-directional routing architectures
 
-.. note:: Currently, OpenFPGA only supports 1 ``<equivalent_sites>`` to be defined under each ``<tile>``
-
-.. note:: OpenFPGA require explicit names to be defined for each routing segement in ``<segmentlist>`` 
-
-
diff --git a/docs/source/arch_lang/annotate_vpr_arch.rst b/docs/source/arch_lang/annotate_vpr_arch.rst
index ce570084d..69aed061e 100644
--- a/docs/source/arch_lang/annotate_vpr_arch.rst
+++ b/docs/source/arch_lang/annotate_vpr_arch.rst
@@ -7,27 +7,82 @@ Each defined circuit model should be linked to an FPGA module defined in the ori
 Configuration Protocol
 ~~~~~~~~~~~~~~~~~~~~~~
 
+Configuration protocol is the circuitry designed to program an FPGA.
+As an interface, configuration protocol could be really different in FPGAs, depending on the application context.
+
+Template
+````````
+
 .. code-block:: xml
 
   <configuration_protocol>
     <organization type="<string>" circuit_model_name="<string>"/>
   </configuration_protocol>
 
-- ``type="scan_chain|memory_bank|standalone"`` Specify the type of configuration circuits.
+.. option:: type="scan_chain|memory_bank|standalone"
 
-:numref:`fig_sram` illustrates an example where a memory organization using memory decoders and 6-transistor SRAMs.
+  Specify the type of configuration circuits.
+
+  OpenFPGA supports different types of configuration protocols to program FPGA fabrics:
+    - ``scan_chain``: configurable memories are connected in a chain. Bitstream is loaded serially to program a FPGA
+    - ``memory_bank``: configurable memories are organized in an array, where each element can be accessed by an unique address to the BL/WL decoders
+    - ``standalone``: configurable memories are directly accessed through ports of FPGA fabrics. In other words, there are no protocol to control the memories. This allows full customization on the configuration protocol for hardware engineers.
+
+  .. note:: Avoid to use ``standalone`` when designing an FPGA chip. It will causes a huge number of I/Os required, far beyond any package size. It is well applicable to eFPGAs, where designers do need customized protocols between FPGA and processors. 
+
+.. warning:: Currently FPGA-SPICE only supports standalone memory organization.
+
+.. warning:: Currently RRAM-based FPGA only supports memory-bank organization for Verilog Generator.
+
+.. option:: circuit_model_name="<string>"
+
+  Specify the name of circuit model to be used as configurable memory.
+  - ``scan_chain`` requires a circuit model type of ``ccff``
+  - ``memory_bank`` requires a circuit model type of ``sram``
+  - ``standalone`` requires a circuit model type of ``sram``
+
+Configuration Chain Example
+```````````````````````````
+The following XML code describes a scan-chain circuitry to configure the core logic of FPGA, as illustrated in :numref:`fig_ccff_fpga`.
+It will use the circuit model defined in :ref:`circuit_model_examples`.
+
+.. code-block:: xml
+
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="ccff"/>
+  </configuration_protocol>
+
+.. _fig_ccff_fpga:
+
+.. figure:: figures/ccff_fpga.png
+   :scale: 60%
+   :alt: map to buried treasure
+ 
+   Example of a configuration chain to program core logic of a FPGA 
+
+Memory bank Example
+```````````````````
+The following XML code describes a memory-bank circuitry to configure the core logic of FPGA, as illustrated in :numref:`fig_sram`.
+It will use the circuit model defined in :ref:`circuit_model_examples`.
+
+.. code-block:: xml
+
+  <configuration_protocol>
+    <organization type="memory_bank" circuit_model_name="sram"/>
+  </configuration_protocol>
 
 .. _fig_sram:
 
 .. figure:: figures/sram.png
-   :scale: 100%
+   :scale: 60%
    :alt: map to buried treasure
  
    Example of a memory organization using memory decoders 
 
-.. note:: Currently FPGA-SPICE only supports standalone memory organization.
+Standalone SRAM Example
+```````````````````````
 
-.. note:: Currently RRAM-based FPGA only supports memory-bank organization for Verilog Generator.
+.. warning:: TO BE CONSTRUCTED
 
 Switch Blocks
 ~~~~~~~~~~~~~
diff --git a/docs/source/arch_lang/circuit_model_examples.rst b/docs/source/arch_lang/circuit_model_examples.rst
index a4472c01d..3a749e49d 100644
--- a/docs/source/arch_lang/circuit_model_examples.rst
+++ b/docs/source/arch_lang/circuit_model_examples.rst
@@ -734,7 +734,7 @@ The code describing this wire is:
 
 This example shows
   - A routing track wire has 1 input and output 
-  - The routing wire will be modelled as a 1-level π-type RC wire model with a total resistance of 103.84Ohm and a total capacitance of 13.89fF
+  - The routing wire will be modelled as a 1-level π-type RC wire model with a total resistance of :math:`103.84\Omega` and a total capacitance of :math:`13.89fF`
 
 I/O pads
 ~~~~~~~~
@@ -790,4 +790,4 @@ This example shows
   - A general purpose I/O cell defined in Verilog netlist ``io.sp`` and SPICE netlist ``io.sp`` 
   - The I/O cell has an ``inout`` port as the bi-directional port
   - The directionality of I/O can be controlled by a configuration-chain flip-flop defined in circuit model ``ccff``
-  - If unused, the I/O cell have be configured to '1'
+  - If unused, the I/O cell will be configured to ``1``
diff --git a/docs/source/arch_lang/figures/ccff_fpga.png b/docs/source/arch_lang/figures/ccff_fpga.png
new file mode 100644
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From 6ce0fe4ef29eccaa7d911399ddfaf492befb95ad Mon Sep 17 00:00:00 2001
From: Xifan Tang <tangxifan@gmail.com>
Date: Wed, 1 Apr 2020 12:57:28 -0600
Subject: [PATCH 364/645] doc update for FPGA-bitstream to better motivate the
 different types of bitstream

---
 .../fabric_dependent_bitstream.rst            |  7 ++++++
 ...organization.rst => generic_bitstream.rst} | 22 ++++++++++++++-----
 docs/source/fpga_bitstream/index.rst          |  9 +++++---
 3 files changed, 29 insertions(+), 9 deletions(-)
 create mode 100644 docs/source/fpga_bitstream/fabric_dependent_bitstream.rst
 rename docs/source/fpga_bitstream/{file_organization.rst => generic_bitstream.rst} (53%)

diff --git a/docs/source/fpga_bitstream/fabric_dependent_bitstream.rst b/docs/source/fpga_bitstream/fabric_dependent_bitstream.rst
new file mode 100644
index 000000000..280768c1a
--- /dev/null
+++ b/docs/source/fpga_bitstream/fabric_dependent_bitstream.rst
@@ -0,0 +1,7 @@
+Fabric-dependent Bitstream
+~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Fabric-dependent bitstream is design to be loadable to the configuration protocols of FPGAs. 
+The bitstream just sets an order to the configuration bits in the database, without duplicating the database.
+OpenFPGA framework provides a fabric-dependent bitstream generator which is aligned to our Verilog netlists.
+The fabric-dependent bitstream can be found in autogenerated Verilog testbenches.
diff --git a/docs/source/fpga_bitstream/file_organization.rst b/docs/source/fpga_bitstream/generic_bitstream.rst
similarity index 53%
rename from docs/source/fpga_bitstream/file_organization.rst
rename to docs/source/fpga_bitstream/generic_bitstream.rst
index 91975fcc7..78fbd3de4 100644
--- a/docs/source/fpga_bitstream/file_organization.rst
+++ b/docs/source/fpga_bitstream/generic_bitstream.rst
@@ -1,9 +1,21 @@
-Bitstream Output File Format
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Generic Bitstream
+~~~~~~~~~~~~~~~~~
 
-FPGA-Bitstream can generate two types of bitstreams:
+Usage
+`````
 
-* Generic bitstreams, where configuration bits are organized out-of-order in a database. We output the generic bitstream to a XML format, which is easy to debug. As shown in the following XML code, configuration bits are organized block by block, where each block could be a LUT, a routing multiplexer `etc`. Each ``bitstream_block`` includes two sets of information: 
+Generic bitstream is a fabric-independent bitstream where configuration bits are organized out-of-order in a database.
+This can be regarded as a raw bitstream used for 
+  - ``debugging``: Hardware engineers can validate if their configuration memories across the FPGA fabric are assigned to expected values 
+  - ``an exchangeable file format for bitstream assembler``: Software engineers can use the raw bitstream to build a bitstream assembler which organize the bitstream in the loadable formate to FPGA chips.
+  - ``creation of artificial bitstream``: Test engineers can craft artificial bitstreams to test each element of the FPGA fabric, which is typically not synthesizable by VPR. 
+
+.. note:: The fabric-independent bitstream cannot be directly loaded to FPGA fabrics
+
+File Format
+```````````
+
+OpenFPGA can output the generic bitstream to an XML format, which is easy to debug. As shown in the following XML code, configuration bits are organized block by block, where each block could be a LUT, a routing multiplexer `etc`. Each ``bitstream_block`` includes two sets of information: 
 
   - ``hierarchy`` represents the location of this block in FPGA fabric.
 
@@ -37,5 +49,3 @@ FPGA-Bitstream can generate two types of bitstreams:
           <bit memory_port="mem_out[15]" value="0"/>
       </bitstream>
   </bitstream_block>
-
-* Fabric-dependent bitstreams, where configuration bits are organized to be loadable to the configuration protocols of FPGAs. The bitstream just sets an order to the configuration bits in the database, without duplicating the database. OpenFPGA framework provides a fabric-dependent bitstream generator which is aligned to our Verilog netlists. The fabric-dependent bitstream can be found in autogenerated Verilog testbenches.
diff --git a/docs/source/fpga_bitstream/index.rst b/docs/source/fpga_bitstream/index.rst
index 6e1123899..e30f89354 100644
--- a/docs/source/fpga_bitstream/index.rst
+++ b/docs/source/fpga_bitstream/index.rst
@@ -1,11 +1,14 @@
 FPGA-Bitstream
 --------------
+
+FPGA-Bitstream can generate two types of bitstreams:
+
 .. _fpga_bitstream:
    FPGA-Bitstream
  
 .. toctree::
    :maxdepth: 2
   
-   file_organization
- 
-   
+   generic_bitstream
+
+   fabric_dependent_bitstream

From 32c74ad8112d9cd92b16cb332c9a27f2bd3e11bc Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 1 Apr 2020 15:46:38 -0600
Subject: [PATCH 365/645] added FPGA architecture with I/Os on the left and
 right sides

---
 ...ble_adder_chain_mem16K_reduced_io.openfpga |  62 ++
 ...ble_adder_chain_mem16K_reduced_io_40nm.xml | 737 ++++++++++++++++++
 2 files changed, 799 insertions(+)
 create mode 100644 openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_reduced_io.openfpga
 create mode 100644 openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml

diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_reduced_io.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_reduced_io.openfpga
new file mode 100644
index 000000000..22a658a73
--- /dev/null
+++ b/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_reduced_io.openfpga
@@ -0,0 +1,62 @@
+# Run VPR for the 'and' design
+vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
+
+# Write out the architecture XML as a proof
+#write_openfpga_arch -f ./arch_echo.xml
+
+# Annotate the OpenFPGA architecture to VPR data base
+link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose
+
+# Write GSB to XML for debugging
+write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to clustering nets based on routing results
+pb_pin_fixup --verbose
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup #--verbose
+
+# Build the module graph 
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules 
+build_fabric --compress_routing --duplicate_grid_pin --verbose
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream 
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here 
+write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
+
+# Finish and exit OpenFPGA
+exit
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml
new file mode 100644
index 000000000..6f8c4cfae
--- /dev/null
+++ b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml
@@ -0,0 +1,737 @@
+<!-- 
+  Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with 8 total FLE inputs (2 inputs of which are shared by the 5-LUTs) 
+    with optionally registered outputs
+    Each 5-LUT has an arithemtic mode that converts it to a single-bit adder with both inputs driven by 4-LUTs (both 4-LUTs share all 4 inputs)
+    Carry chain links to vertically adjacent logic blocks
+  - Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.  
+    Height = 6, found on every (8n+2)th column
+  - Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.  
+    Height = 4, found on every (8n+6)th column
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Details on Modelling:
+
+  The electrical design of the architecture described here is NOT from an 
+  optimized, SPICED architecture.  Instead, we attempt to create a reasonable 
+  architecture file by using an existing commercial FPGA to approximate the area, 
+  delay, and power of the underlying components. This is combined with a reasonable 40 nm 
+  model of wiring and circuit design for low-level routing components, where available.
+  The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also 
+  has wiring electrical parameters that allow the wire lengths and switch patterns to be 
+  modified and you will still get reasonable delay results for the new architecture.
+  The following describes, in detail, how we obtained the various electrical values for this 
+  architecture.
+
+  Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar 
+  architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture. 
+  (n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)      
+  This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to 
+  match the overall target (a 40 nm FPGA).
+
+  We obtain delay numbers by measuring delays of routing, soft logic blocks, 
+  memories, and multipliers from test circuits on a Stratix IV GX device 
+  (EP4SGX230DF29C2X, i.e. fastest speed grade). For routing, we took the average delay of H4 and V4 
+  wires.  Rmetal and Cmetal values for the routing wires were obtained from work done by Charles 
+  Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal stack 40 nm routing) and 
+  take the R and C data from the ITRS roadmap.  
+
+  For the general purpose logic block, we assume that the area and delays of the Stratix IV 
+  crossbar is close enough to the crossbar modelled here.  
+  Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to 
+  36:1 multiplexers.  We match these parameters in this architecture.
+
+  For LUTs, we include LUT 
+  delays measured from Stratix IV which is dependant on the input used (ie. some 
+  LUT inputs are faster than others).  The CAD tools at the time of VTR 7 does 
+  not consider differences in LUT input delays.
+
+  Adder delays obtained as approximate values from a Stratix IV EP4SE230F29C3 device.  
+  Delay obtained by compiling a 256 bit adder (registered inputs and outputs, 
+  all pins except clock virtual) then measuring the delays in chip-planner, 
+  sumout delay = 0.271ns to 0.348 ns, intra-block carry delay = 0.011 ns, 
+  inter-block carry delay = 0.327 ns.  Given this data, I will approximate 
+  sumout 0.3 ns, intra-block carry-delay = 0.01 ns, and 
+  inter-block carry-delay = 0.16 ns (since Altera inter-block carry delay has 
+  overhead that we don't have, I'll approximate the delay of a simpler chain at 
+  one half what they have.  This is very rough, anything from 0.01ns to 0.327ns 
+  can be justified).
+
+  Logic block area numbers obtained by scaling overall tile area of a 65nm 
+  Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out 
+  routing area at a channel width of 300. We use a channel width of 300 because it can route 
+  all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
+  total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
+  choosing a width that provides high routability. The architecture can be routed at different channel
+  widths, but we estimate the tile size and hence the physical length of routing wires assuming
+  a channel width of 300.
+
+  Sanity checks employed:
+    1.  We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches 
+        common electrical design.
+
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <model name="adder">
+      <input_ports>
+        <port name="a" combinational_sink_ports="sumout cout"/>
+        <port name="b" combinational_sink_ports="sumout cout"/>
+        <port name="cin" combinational_sink_ports="sumout cout"/>
+      </input_ports>
+      <output_ports>
+        <port name="cout"/>
+        <port name="sumout"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="frac_lut6">
+      <input_ports>
+        <port name="in"/>
+      </input_ports>
+      <output_ports>
+        <port name="lut4_out"/>
+        <port name="lut5_out"/>
+        <port name="lut6_out"/>
+      </output_ports>
+    </model>
+    <model name="dual_port_ram">
+      <input_ports>
+        <!-- write address lines -->
+        <port name="waddr" clock="clk"/>
+        <!-- read address lines -->
+        <port name="raddr" clock="clk"/>
+        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
+        <port name="d_in" clock="clk"/>
+        <!-- write enable -->
+        <port name="wen" clock="clk"/>
+        <!-- read enable -->
+        <port name="ren" clock="clk"/>
+        <!-- memories are often clocked -->
+        <port name="clk" is_clock="1"/>
+      </input_ports>
+      <output_ports>
+        <!-- output can be broken down into smaller bit widths minimum size 1 -->
+        <port name="d_out" clock="clk"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <tile name="io" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad</loc>
+        <loc side="top">io.outpad io.inpad</loc>
+        <loc side="right">io.outpad io.inpad</loc>
+        <loc side="bottom">io.outpad io.inpad</loc>
+      </pinlocations>
+    </tile>
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
+      </fc>
+      <!--  Highly recommand to customize pin location when direct connection is used!!! -->
+      <!--pinlocations pattern="spread"/-->
+      <pinlocations pattern="custom">
+        <loc side="left">clb.clk</loc>
+        <loc side="top">clb.cin</loc>
+        <loc side="right">clb.O[9:0] clb.I[19:0]</loc>
+        <loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
+      </pinlocations>
+    </tile>
+    <tile name="memory" height="2" area="548000">
+      <equivalent_sites>
+        <site pb_type="memory"/>
+      </equivalent_sites>
+      <input name="waddr" num_pins="10"/>
+      <input name="raddr" num_pins="10"/>
+      <input name="d_in" num_pins="32"/>
+      <input name="wen" num_pins="1"/>
+      <input name="ren" num_pins="1"/>
+      <output name="d_out" num_pins="32"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="spread"/>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout tileable="true" through_channel="false">
+    <!--auto_layout aspect_ratio="1.0"-->
+    <fixed_layout name="4x4" width="7" height="6">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="10"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="1"/>
+      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
+      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
+      <row type="EMPTY" starty="H-1" priority="11"/>
+      <row type="EMPTY" starty="0" priority="11"/>
+      <!-- Single instance of an AIB interface -->
+    </fixed_layout>
+    <!-- /auto_layout -->
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	    -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+           book area formula. This means the mux transistors are about 5x minimum drive strength.
+           We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+           mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+           the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+           by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+           buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+           I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+           (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+           The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+           2.5x when looking up in Jeff's tables.
+           Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+           This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+             With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+             reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <directlist>
+    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
+  </directlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+
+      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+           If you need to register the I/O, define clocks in the circuit models
+           These clocks can be handled in back-end
+       -->
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" disabled_in_pack="true">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe fracturable logic element.  
+             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
+             The outputs of the fracturable logic element can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="10">
+        <input name="in" num_pins="6"/>
+        <input name="cin" num_pins="1"/>
+        <output name="out" num_pins="2"/>
+        <output name="cout" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- Physical mode definition begin (physical implementation of the fle) -->
+        <mode name="physical" disabled_in_pack="true">
+          <pb_type name="fabric" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="frac_logic" num_pb="1">
+              <input name="in" num_pins="6"/>
+              <output name="lut4_out" num_pins="4"/>
+              <output name="out" num_pins="2"/>
+              <!-- Define LUT -->
+              <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
+                <input name="in" num_pins="6"/>
+                <output name="lut4_out" num_pins="4"/>
+                <output name="lut5_out" num_pins="2"/>
+                <output name="lut6_out" num_pins="1"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
+                <direct name="direct2" input="frac_lut6.lut4_out" output="frac_logic.lut4_out"/>
+                <direct name="direct3" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
+                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
+                <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
+              </interconnect>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>         
+            <!-- Define adders -->
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="2">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
+              <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
+              <direct name="direct3" input="fabric.cin" output="adder[0:0].cin"/>
+              <direct name="direct4" input="adder[0:0].cout" output="adder[1:1].cin"/>
+              <direct name="direct5" input="adder[1:1].cout" output="fabric.cout"/>
+              <direct name="direct6" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
+              <direct name="direct7" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
+              <direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
+              <direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
+              <complete name="direct10" input="fabric.clk" output="ff[1:0].clk"/>
+              <mux name="mux1" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
+                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
+              </mux>
+              <mux name="mux2" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
+                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="fabric.in"/>
+            <direct name="direct2" input="fle.cin" output="fabric.cin"/>
+            <direct name="direct3" input="fabric.out" output="fle.out"/>
+            <direct name="direct4" input="fabric.cout" output="fle.cout"/>
+            <direct name="direct5" input="fle.clk" output="fabric.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Physical mode definition end (physical implementation of the fle) -->
+        <!-- BEGIN fle mode of dual lut5 -->
+        <mode name="n2_lut5">
+          <pb_type name="ble5" num_pb="2">
+            <input name="in" num_pins="5"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Regular LUT mode -->
+            <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="5" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                  we instead take the average of these numbers to get more stable results
+                82e-12
+                173e-12
+                261e-12
+                263e-12
+                398e-12
+                -->
+              <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+              </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble5.in" output="lut5.in"/>
+              <direct name="direct2" input="lut5.out" output="ff.D">
+                <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble5.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut5.out" output="ble5.out">
+                <delay_constant max="25e-12" in_port="lut5.out" out_port="ble5.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble5.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[4:0]" output="ble5[0:0].in"/>
+            <direct name="direct2" input="fle.in[4:0]" output="ble5[1:1].in"/>
+            <complete name="direct3" input="fle.clk" output="ble5.clk"/>
+            <direct name="direct4" input="ble5.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- END fle mode of dual lut5 -->
+        <!-- BEGIN arithmetic mode of dual lut4 + adders -->
+        <mode name="arithmetic">
+          <pb_type name="arithmetic" num_pb="2">
+            <input name="in" num_pins="4"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="1"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Special dual-LUT mode that drives adder only -->
+            <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
+              <input name="in" num_pins="4" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  -->
+              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                  195e-12
+                  195e-12
+                  195e-12
+                  195e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
+              <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
+              <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
+              <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
+                </direct>
+              <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
+                </direct>
+              <direct name="add_to_ff" input="adder.sumout" output="ff.D">
+                <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
+              </direct>
+              <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
+                <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
+              </direct>
+              <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
+                <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
+              </direct>
+              <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
+                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[3:0]" output="arithmetic[0:0].in"/>
+            <direct name="direct2" input="fle.in[3:0]" output="arithmetic[1:1].in"/>
+            <direct name="carry_in" input="fle.cin" output="arithmetic[0:0].cin">
+              <pack_pattern name="chain" in_port="fle.cin" out_port="arithmetic[0:0].cin"/>
+            </direct>
+            <direct name="carry_inter" input="arithmetic[0:0].cout" output="arithmetic[1:1].cin">
+              <pack_pattern name="chain" in_port="arithmetic[0:0].cout" out_port="arithmetic[1:1].cin"/>
+            </direct>
+            <direct name="carry_out" input="arithmetic[1:1].cout" output="fle.cout">
+              <pack_pattern name="chain" in_port="arithmetic.cout" out_port="fle.cout"/>
+            </direct>
+            <complete name="direct3" input="fle.clk" output="arithmetic.clk"/>
+            <direct name="direct4" input="arithmetic.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- n2_lut5 -->
+        <mode name="n1_lut6">
+          <pb_type name="ble6" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="6" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->
+              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+              <direct name="direct2" input="lut6.out" output="ff.D">
+                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
+            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+          </interconnect>
+        </mode>
+        <!-- n1_lut6 -->
+      </pb_type>
+      <interconnect>
+        <!-- We use a 50% depop crossbar built using small full xbars to get sets of logically equivalent pins at inputs of CLB 
+           The delays below come from Stratix IV. the delay through a connection block
+           input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+           delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+           delay within the crossbar is 95 ps. 
+           The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+           Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+           25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+           to get the part that should be marked on the crossbar.	 -->
+        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
+          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
+          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
+        </complete>
+
+        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+        </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+                 By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+                 then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+                 naive specification).
+          -->
+        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
+        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
+        <!-- Carry chain links -->
+        <direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
+          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
+        </direct>
+        <direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
+          <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
+        </direct>
+        <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
+          <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
+        </direct>
+      </interconnect>
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+    <!-- Define single-mode dual-port memory begin -->
+    <pb_type name="memory">
+      <input name="waddr" num_pins="10"/>
+      <input name="raddr" num_pins="10"/>
+      <input name="d_in" num_pins="32"/>
+      <input name="wen" num_pins="1"/>
+      <input name="ren" num_pins="1"/>
+      <output name="d_out" num_pins="32"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Specify the 512x32=16Kbit memory block
+           Note: the delay numbers are extracted from VPR flagship XML without modification
+                 Should align to the process technology we using to create the 16K dual-port RAM
+        -->
+      <mode name="mem_512x32_dp">
+        <pb_type name="mem_512x32_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
+          <input name="waddr" num_pins="10" port_class="address"/>
+          <input name="raddr" num_pins="10" port_class="address"/>
+          <input name="d_in" num_pins="32" port_class="data_in"/>
+          <input name="wen" num_pins="1" port_class="write_en"/>
+          <input name="ren" num_pins="1" port_class="write_en"/>
+          <output name="d_out" num_pins="32" port_class="data_out"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.waddr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.raddr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.d_in" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.wen" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.ren" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_512x32_dp.d_out" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="17.9e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="waddress" input="memory.waddr" output="mem_512x32_dp.waddr">
+            <delay_constant max="132e-12" in_port="memory.waddr" out_port="mem_512x32_dp.waddr"/>
+          </direct>
+          <direct name="raddress" input="memory.raddr" output="mem_512x32_dp.raddr">
+            <delay_constant max="132e-12" in_port="memory.raddr" out_port="mem_512x32_dp.raddr"/>
+          </direct>
+          <direct name="data_input" input="memory.d_in" output="mem_512x32_dp.d_in">
+            <delay_constant max="132e-12" in_port="memory.d_in" out_port="mem_512x32_dp.d_in"/>
+          </direct>
+          <direct name="writeen" input="memory.wen" output="mem_512x32_dp.wen">
+            <delay_constant max="132e-12" in_port="memory.wen" out_port="mem_512x32_dp.wen"/>
+          </direct>
+          <direct name="readen" input="memory.ren" output="mem_512x32_dp.ren">
+            <delay_constant max="132e-12" in_port="memory.ren" out_port="mem_512x32_dp.ren"/>
+          </direct>
+          <direct name="dataout" input="mem_512x32_dp.d_out" output="memory.d_out">
+            <delay_constant max="40e-12" in_port="mem_512x32_dp.d_out" out_port="memory.d_out"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_512x32_dp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+    </pb_type>
+    <!-- Define single-mode dual-port memory end -->
+  </complexblocklist>
+</architecture>

From d1d3446568113b1f8439cab4b65d1b985d4469a3 Mon Sep 17 00:00:00 2001
From: ganeshgore <goreganesh007@gmail.com>
Date: Sun, 5 Apr 2020 11:36:24 -0600
Subject: [PATCH 366/645] backedup partial upgrade for fpga_flow script

---
 openfpga_flow/scripts/run_fpga_flow.py | 82 ++++++++++++++++++++++++++
 1 file changed, 82 insertions(+)

diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py
index fe5d535dd..1d67d3059 100644
--- a/openfpga_flow/scripts/run_fpga_flow.py
+++ b/openfpga_flow/scripts/run_fpga_flow.py
@@ -646,6 +646,88 @@ def run_vpr():
     ExecTime["VPREnd"] = time.time()
 
 
+def run_openfpga_shell(bench_blif, fixed_chan_width, logfile, route_only=False):
+    runfile = open("run.openfpga", 'w+'):
+    command = ["vpr",
+               args.arch_file,
+               bench_blif,
+               "--net_file", args.top_module+"_vpr.net",
+               "--place_file", args.top_module+"_vpr.place",
+               "--route_file", args.top_module+"_vpr.route",
+               "--full_stats",
+               "--activity_file", args.top_module+"_ace_out.act"]
+    # Other VPR options
+    if args.vpr_place_clb_pin_remap:
+        command += ["--place_clb_pin_remap"]
+    if args.vpr_route_breadthfirst:
+        command += ["--router_algorithm", "breadth_first"]
+    if args.vpr_max_router_iteration:
+        command += ["--max_router_iterations", args.vpr_max_router_iteration]
+    runfile.write(" ".join(command)+os.linesep)
+
+    command = ["read_openfpga_arch", "-f", args.arch_file]
+    runfile.write(" ".join(command)+os.linesep)
+
+    command = ["link_openfpga_arch", "--activity_file",
+               args.top_module+"_ace_out.act"]
+    runfile.write(" ".join(command)+os.linesep)
+
+    command = ["check_netlist_naming_conflict",
+               "--fix", "--report",
+               (args.arch_file).replace(".xml", "_renaming.xml")]
+    runfile.write(" ".join(command)+os.linesep)
+
+    runfile.write(" ".join(["pb_pin_fixup", "--verbose"])+os.linesep)
+    runfile.write(" ".join(["lut_truth_table_fixup"])+os.linesep)
+
+    command = ["build_fabric", "--compress_routing", "--duplicate_grid_pin"]
+    runfile.write(" ".join(command)+os.linesep)
+
+    runfile.write(" ".join(["repack"])+os.linesep)
+
+    if args.vpr_fpga_verilog:
+        command += ["write_verilog_testbench", "--fpga_verilog"]
+        if args.vpr_fpga_verilog_dir:
+            command += ["--fpga_verilog_dir", args.vpr_fpga_verilog_dir]
+        if args.vpr_fpga_verilog_print_top_tb:
+            command += ["--fpga_verilog_print_top_testbench"]
+        if args.vpr_fpga_verilog_print_input_blif_tb:
+            command += ["--fpga_verilog_print_input_blif_testbench"]
+        if args.vpr_fpga_verilog_print_autocheck_top_testbench:
+            command += ["--fpga_verilog_print_autocheck_top_testbench",
+                        os.path.join(args.run_dir, args.top_module+"_output_verilog.v")]
+        if args.vpr_fpga_verilog_include_timing:
+            command += ["--fpga_verilog_include_timing"]
+        if args.vpr_fpga_verilog_explicit_mapping:
+            command += ["--fpga_verilog_explicit_mapping"]
+        if args.vpr_fpga_x2p_duplicate_grid_pin:
+            command += ["--fpga_x2p_duplicate_grid_pin"]
+        if args.vpr_fpga_verilog_include_signal_init:
+            command += ["--fpga_verilog_include_signal_init"]
+        if args.vpr_fpga_verilog_formal_verification_top_netlist:
+            command += ["--fpga_verilog_print_formal_verification_top_netlist"]
+        if args.vpr_fpga_verilog_print_simulation_ini:
+            command += ["--fpga_verilog_print_simulation_ini"]
+        if args.vpr_fpga_verilog_include_icarus_simulator:
+            command += ["--fpga_verilog_include_icarus_simulator"]
+        if args.vpr_fpga_verilog_print_report_timing_tcl:
+            command += ["--fpga_verilog_print_report_timing_tcl"]
+        if args.vpr_fpga_verilog_report_timing_rpt_path:
+            command += ["--fpga_verilog_report_timing_rpt_path",
+                        args.vpr_fpga_verilog_report_timing_rpt_path]
+        if args.vpr_fpga_verilog_print_sdc_pnr:
+            command += ["--fpga_verilog_print_sdc_pnr"]
+        if args.vpr_fpga_verilog_print_user_defined_template:
+            command += ["--fpga_verilog_print_user_defined_template"]
+        if args.vpr_fpga_verilog_print_sdc_analysis:
+            command += ["--fpga_verilog_print_sdc_analysis"]
+        runfile.write(" ".join(command)+os.linesep)
+
+        if args.vpr_fpga_verilog_print_sdc_analysis:
+            command = ["write_pnr_sdc", "--fpga_bitstream_generator"]
+            runfile.write(" ".join(command)+os.linesep)
+
+
 def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False):
     command = [cad_tools["vpr_path"],
                args.arch_file,

From 836f722f2038cec4120900d8dfc1ec009e1341ac Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 5 Apr 2020 15:19:46 -0600
Subject: [PATCH 367/645] start supporting global output ports in module
 manager

---
 openfpga/src/fabric/module_manager.cpp        |   2 +-
 openfpga/src/fabric/module_manager.h          |   1 +
 .../src/fpga_verilog/verilog_writer_utils.cpp |   3 +
 openfpga/src/utils/module_manager_utils.cpp   | 166 +++++++++++++++++-
 openfpga/src/utils/module_manager_utils.h     |   6 +
 5 files changed, 170 insertions(+), 8 deletions(-)

diff --git a/openfpga/src/fabric/module_manager.cpp b/openfpga/src/fabric/module_manager.cpp
index 40f672194..7f444318e 100644
--- a/openfpga/src/fabric/module_manager.cpp
+++ b/openfpga/src/fabric/module_manager.cpp
@@ -120,7 +120,7 @@ std::string ModuleManager::module_name(const ModuleId& module_id) const {
 
 /* Get the string of a module port type */
 std::string ModuleManager::module_port_type_str(const enum e_module_port_type& port_type) const {
-  std::array<const char*, NUM_MODULE_PORT_TYPES> MODULE_PORT_TYPE_STRING = {{"GLOBAL PORTS", "GPIO PORTS", "INOUT PORTS", "INPUT PORTS", "OUTPUT PORTS", "CLOCK PORTS"}};
+  std::array<const char*, NUM_MODULE_PORT_TYPES> MODULE_PORT_TYPE_STRING = {{"GLOBAL PORTS", "SPY PORTS", "GPIO PORTS", "INOUT PORTS", "INPUT PORTS", "OUTPUT PORTS", "CLOCK PORTS"}};
   return MODULE_PORT_TYPE_STRING[port_type];
 }
 
diff --git a/openfpga/src/fabric/module_manager.h b/openfpga/src/fabric/module_manager.h
index 425b7a072..1bfbd8b49 100644
--- a/openfpga/src/fabric/module_manager.h
+++ b/openfpga/src/fabric/module_manager.h
@@ -28,6 +28,7 @@ class ModuleManager {
   public: /* Private data structures */
     enum e_module_port_type {
       MODULE_GLOBAL_PORT, /* Global inputs */
+      MODULE_SPY_PORT,    /* Global outputs, which is designed for spypads */
       MODULE_GPIO_PORT,   /* General-purpose IOs, which are data IOs of the fabric */
       MODULE_INOUT_PORT,  /* Normal (non-global) inout ports */
       MODULE_INPUT_PORT,  /* Normal (non-global) input ports */
diff --git a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp
index 95f34ab1f..b771f4752 100644
--- a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp
+++ b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp
@@ -129,6 +129,7 @@ void print_verilog_module_definition(std::fstream& fp,
   /* port type2type mapping */
   std::map<ModuleManager::e_module_port_type, enum e_dump_verilog_port_type> port_type2type_map;
   port_type2type_map[ModuleManager::MODULE_GLOBAL_PORT] = VERILOG_PORT_CONKT;
+  port_type2type_map[ModuleManager::MODULE_SPY_PORT] = VERILOG_PORT_CONKT;
   port_type2type_map[ModuleManager::MODULE_GPIO_PORT] = VERILOG_PORT_CONKT;
   port_type2type_map[ModuleManager::MODULE_INOUT_PORT] = VERILOG_PORT_CONKT;
   port_type2type_map[ModuleManager::MODULE_INPUT_PORT] = VERILOG_PORT_CONKT;
@@ -188,6 +189,7 @@ void print_verilog_module_ports(std::fstream& fp,
   /* port type2type mapping */
   std::map<ModuleManager::e_module_port_type, enum e_dump_verilog_port_type> port_type2type_map;
   port_type2type_map[ModuleManager::MODULE_GLOBAL_PORT] = VERILOG_PORT_INPUT;
+  port_type2type_map[ModuleManager::MODULE_SPY_PORT] = VERILOG_PORT_OUTPUT;
   port_type2type_map[ModuleManager::MODULE_GPIO_PORT] = VERILOG_PORT_INOUT;
   port_type2type_map[ModuleManager::MODULE_INOUT_PORT] = VERILOG_PORT_INOUT;
   port_type2type_map[ModuleManager::MODULE_INPUT_PORT] = VERILOG_PORT_INPUT;
@@ -344,6 +346,7 @@ void print_verilog_module_instance(std::fstream& fp,
   /* port type2type mapping */
   std::map<ModuleManager::e_module_port_type, enum e_dump_verilog_port_type> port_type2type_map;
   port_type2type_map[ModuleManager::MODULE_GLOBAL_PORT] = VERILOG_PORT_CONKT;
+  port_type2type_map[ModuleManager::MODULE_SPY_PORT] = VERILOG_PORT_CONKT;
   port_type2type_map[ModuleManager::MODULE_GPIO_PORT] = VERILOG_PORT_CONKT;
   port_type2type_map[ModuleManager::MODULE_INOUT_PORT] = VERILOG_PORT_CONKT;
   port_type2type_map[ModuleManager::MODULE_INPUT_PORT] = VERILOG_PORT_CONKT;
diff --git a/openfpga/src/utils/module_manager_utils.cpp b/openfpga/src/utils/module_manager_utils.cpp
index 9797763b0..5c3f4a41b 100644
--- a/openfpga/src/utils/module_manager_utils.cpp
+++ b/openfpga/src/utils/module_manager_utils.cpp
@@ -36,10 +36,20 @@ ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager,
   VTR_ASSERT(ModuleId::INVALID() != module);
 
   /* Add ports */
-  /* Find global ports and add one by one */
+  /* Find global ports and add one by one 
+   * Global input ports will be considered as global port in the context of module manager
+   * Global output ports will be considered as spy port in the context of module manager
+   */
   for (const auto& port : circuit_lib.model_global_ports(circuit_model, false)) {
     BasicPort port_info(circuit_lib.port_prefix(port), circuit_lib.port_size(port));
-    module_manager.add_port(module, port_info, ModuleManager::MODULE_GLOBAL_PORT);  
+    if (CIRCUIT_MODEL_PORT_INPUT == circuit_lib.port_type(port)) {
+      module_manager.add_port(module, port_info, ModuleManager::MODULE_GLOBAL_PORT);  
+    } else if (CIRCUIT_MODEL_PORT_CLOCK == circuit_lib.port_type(port)) {
+      module_manager.add_port(module, port_info, ModuleManager::MODULE_GLOBAL_PORT);  
+    } else {
+      VTR_ASSERT(CIRCUIT_MODEL_PORT_OUTPUT == circuit_lib.port_type(port));
+      module_manager.add_port(module, port_info, ModuleManager::MODULE_SPY_PORT);  
+    }
   }
 
   /* Find other ports and add one by one */
@@ -1011,18 +1021,30 @@ void add_module_gpio_ports_from_child_modules(ModuleManager& module_manager,
 }
 
 /********************************************************************
- * Add global ports to the module:
+ * Add global input ports to the module:
  * In this function, the following tasks are done: 
- * 1. find all the global ports from the child modules and build a list of it,
- * 2. add the ports to the pb_module
+ * 1. find all the global input ports from the child modules and build a list of it,
+ * 2. add the input ports to the pb_module
  * 3. add the module nets to connect the pb_module global ports to those of child modules
  *
+ *                             Module
+ *                           +--------------------------
+ *                           |        child[0]
+ *        input_portA[0] ----+-+---->+----------
+ *                           | |     |
+ *                           | |     +----------
+ *                           | |
+ *                           | |      child[1]
+ *                           | +---->+----------
+ *                           |       |
+ *                           |       +----------
+ *
  * Note: This function should be call ONLY after all the sub modules (instances)
  * have been added to the pb_module!
  * Otherwise, some global ports of the sub modules may be missed!
  *******************************************************************/
-void add_module_global_ports_from_child_modules(ModuleManager& module_manager, 
-                                                const ModuleId& module_id) {
+void add_module_global_input_ports_from_child_modules(ModuleManager& module_manager, 
+                                                      const ModuleId& module_id) {
   std::vector<BasicPort> global_ports_to_add;
 
   /* Iterate over the child modules */
@@ -1078,6 +1100,136 @@ void add_module_global_ports_from_child_modules(ModuleManager& module_manager,
   } 
 }
 
+/********************************************************************
+ * Add global output ports to the module:
+ * In this function, the following tasks are done: 
+ * 1. find all the global output ports from the child modules and build a list of it,
+ * 2. add the output ports to the pb_module
+ * 3. add the module nets to connect the pb_module global ports to those of child modules
+ *
+ *   Module
+ *   ----------------------+
+ *                         |
+ *   child[0]              |
+ *   -----------+          |
+ *              |----------+----> outputA[0]
+ *   -----------+          |
+ *                         |
+ *   child[1]              |
+ *   -----------+          |
+ *              |----------+----> outputA[1]
+ *   -----------+          |
+ *
+ * Note: This function should be call ONLY after all the sub modules (instances)
+ * have been added to the pb_module!
+ * Otherwise, some global ports of the sub modules may be missed!
+ *******************************************************************/
+void add_module_global_output_ports_from_child_modules(ModuleManager& module_manager, 
+                                                       const ModuleId& module_id) {
+  std::vector<BasicPort> global_ports_to_add;
+
+  /* Iterate over the child modules */
+  for (const ModuleId& child : module_manager.child_modules(module_id)) {
+    /* Iterate over the child instances */
+    for (size_t i = 0; i < module_manager.num_instance(module_id, child); ++i) {
+      /* Find all the global ports, whose port type is special */
+      for (BasicPort global_port : module_manager.module_ports_by_type(child, ModuleManager::MODULE_SPY_PORT)) {
+        /* Search in the global port list to be added, if this is unique, we update the list */
+        std::vector<BasicPort>::iterator it = std::find(global_ports_to_add.begin(), global_ports_to_add.end(), global_port);
+        if (it != global_ports_to_add.end()) {
+          /* Found in the global port with the same name, increase the port size */
+          it->expand(global_port.get_width());
+          continue; /* Finish for the port already in the list */
+        }
+        /* Reach here, this is an unique global port, update the list */
+        global_ports_to_add.push_back(global_port);
+      }
+    }
+  } 
+
+  /* Record the port id for each type of global port */
+  std::vector<ModulePortId> global_port_ids;
+  /* Add the global ports for the module */
+  for (const BasicPort& global_port_to_add : global_ports_to_add) {
+    ModulePortId port_id = module_manager.add_port(module_id, global_port_to_add, ModuleManager::MODULE_SPY_PORT);
+    global_port_ids.push_back(port_id);
+  } 
+
+  /* Add module nets to connect the global ports of the module to the global ports of the sub module */
+  /* Create a counter for each global port to record the current LSB */
+  std::vector<size_t> global_port_lsbs(global_port_ids.size(), 0);
+
+  /* Iterate over the child modules */
+  for (const ModuleId& child : module_manager.child_modules(module_id)) {
+    /* Iterate over the child instances */
+    for (const size_t& child_instance : module_manager.child_module_instances(module_id, child)) {
+      /* Find all the global ports, whose port type is special */
+      for (ModulePortId child_global_port_id : module_manager.module_port_ids_by_type(child, ModuleManager::MODULE_SPY_PORT)) {
+        /* Find the global port from the child module */
+        BasicPort child_global_port = module_manager.module_port(child, child_global_port_id);
+        /* Search in the global port list to be added, find the port id */
+        std::vector<BasicPort>::iterator it = std::find(global_ports_to_add.begin(), global_ports_to_add.end(), child_global_port);
+        VTR_ASSERT(it != global_ports_to_add.end());
+
+        /* Find the global port from the parent module */
+        size_t module_global_port_offset = it - global_ports_to_add.begin();
+        ModulePortId module_global_port_id = global_port_ids[module_global_port_offset];
+        BasicPort module_global_port = module_manager.module_port(module_id, module_global_port_id);
+        /* Current LSB should be in range */
+        VTR_ASSERT(module_global_port.get_width() > global_port_lsbs[module_global_port_offset]);
+        /* Set the global port from the parent module as the LSB recorded */
+        module_global_port.set_width(global_port_lsbs[module_global_port_offset], global_port_lsbs[module_global_port_offset]);
+        /* Update the LSB */
+        global_port_lsbs[module_global_port_offset]++;
+
+        /* The global ports should match in size */
+        VTR_ASSERT(module_global_port.get_width() == child_global_port.get_width());
+        /* For each pin of the child port, create a net and do wiring */
+        for (size_t pin_id = 0; pin_id < child_global_port.pins().size(); ++pin_id) {
+          /* Reach here, it means this is the port we want, create a net and configure its source and sink */
+          ModuleNetId net = module_manager.create_module_net(module_id);
+          module_manager.add_module_net_source(module_id, net, child, child_instance, child_global_port_id, child_global_port.pins()[pin_id]); 
+          module_manager.add_module_net_sink(module_id, net, module_id, 0, module_global_port_id, module_global_port.pins()[pin_id]); 
+          /* We finish for this child gpio port */
+        }
+      }
+    }
+  } 
+
+  /* Find check: all the LSBs of global ports should match the MSB */
+  for (size_t iport = 0; iport < global_port_ids.size(); ++iport) {
+    BasicPort module_global_port = module_manager.module_port(module_id, global_port_ids[iport]);
+    VTR_ASSERT(module_global_port.get_width() == global_port_lsbs[iport]); 
+  }
+}
+
+/********************************************************************
+ * Add global ports to the module:
+ * In this function, we will add global input ports and global output ports 
+ * which are collected from the child modules 
+ *
+ * - Input ports: the input ports will be uniquified by names
+ *                Ports with the same name will be merged to the same pin
+ *                See details inside the function
+ *
+ * - Output ports: the output ports will be uniquified by names
+ *                 Different from the input ports, output ports 
+ *                 with the same name will be merged but will have indepedent pins
+ *                 See details inside the function
+ *
+ * Note: This function should be call ONLY after all the sub modules (instances)
+ * have been added to the pb_module!
+ * Otherwise, some global ports of the sub modules may be missed!
+ *******************************************************************/
+void add_module_global_ports_from_child_modules(ModuleManager& module_manager, 
+                                                const ModuleId& module_id) {
+  /* Input ports */
+  add_module_global_input_ports_from_child_modules(module_manager, module_id);
+
+  /* Output ports */
+  add_module_global_output_ports_from_child_modules(module_manager, module_id);
+}
+
 /********************************************************************
  * Find the number of shared configuration bits for a module 
  * by selected the maximum number of shared configuration bits of child modules
diff --git a/openfpga/src/utils/module_manager_utils.h b/openfpga/src/utils/module_manager_utils.h
index 6198701ad..fcc95b8ba 100644
--- a/openfpga/src/utils/module_manager_utils.h
+++ b/openfpga/src/utils/module_manager_utils.h
@@ -108,6 +108,12 @@ size_t find_module_num_config_bits(const ModuleManager& module_manager,
                                    const CircuitModelId& sram_model,
                                    const e_config_protocol_type& sram_orgz_type);
 
+void add_module_global_input_ports_from_child_modules(ModuleManager& module_manager, 
+                                                      const ModuleId& module_id);
+
+void add_module_global_output_ports_from_child_modules(ModuleManager& module_manager, 
+                                                       const ModuleId& module_id);
+
 void add_module_global_ports_from_child_modules(ModuleManager& module_manager, 
                                                 const ModuleId& module_id);
 

From 3b63ad66576548967d9cee45d9e2099235213144 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 5 Apr 2020 15:23:07 -0600
Subject: [PATCH 368/645] add test openfpga arch XML with spy pad

---
 .../k6_frac_N10_spyio_40nm_openfpga.xml       | 268 ++++++++++++++++++
 1 file changed, 268 insertions(+)
 create mode 100644 openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml

diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml
new file mode 100644
index 000000000..9d81c5b3e
--- /dev/null
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml
@@ -0,0 +1,268 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
+      <design_technology type="cmos" topology="OR"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <!--mux2to1 subckt_name="mux2to1"/-->
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <!--mux2to1 subckt_name="mux2to1"/-->
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <!--mux2to1 subckt_name="mux2to1"/-->
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <pass_gate_logic circuit_model_name="TGATE"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
+      <design_technology type="cmos" fracturable_lut="true"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="6" tri_state_map="-----1" circuit_model_name="OR2"/>
+      <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
+      <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
+      <port type="sram" prefix="sram" size="64"/>
+      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <pass_gate_logic circuit_model_name="TGATE"/>
+       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="Qb" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="inout" prefix="pad" size="1"/>
+      <!-- A spypad for the direction port of the I/O pad, which can be visible in the fpga_top -->
+      <port type="output" prefix="dir" size="1" is_global="true"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+      <port type="input" prefix="outpad" size="1"/>
+      <port type="output" prefix="inpad" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle" physical_mode_name="physical"/>
+    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="0"/>
+    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
+    <!-- Binding operating pb_type to physical pb_type -->
+    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="1" physical_pb_type_index_factor="0.5">
+      <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:4]"/>
+      <port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="0">
+      <!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:5]"/>
+      <port name="out" physical_mode_port="lut6_out"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>
+<openfpga_simulation_setting>
+  <clock_setting>
+    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
+    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
+    <programming frequency="10e6"/>
+  </clock_setting>
+  <simulator_option>
+    <operating_condition temperature="25"/>
+    <output_log verbose="false" captab="false"/>
+    <accuracy type="abs" value="1e-13"/>
+    <runtime fast_simulation="true"/>
+  </simulator_option>
+  <monte_carlo num_simulation_points="2"/>
+  <measurement_setting>
+    <slew>
+      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
+      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
+    </slew>
+    <delay>
+      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
+      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
+    </delay>
+  </measurement_setting>
+  <stimulus>
+    <clock>
+      <rise slew_type="abs" slew_time="20e-12" />
+      <fall slew_type="abs" slew_time="20e-12" />
+    </clock>
+    <input>
+      <rise slew_type="abs" slew_time="25e-12" />
+      <fall slew_type="abs" slew_time="25e-12" />
+    </input>
+  </stimulus>
+</openfpga_simulation_setting>

From ca45efd13df7c3d99459671f2a1b629104952b20 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 5 Apr 2020 15:24:40 -0600
Subject: [PATCH 369/645] add testing script for the spy io

---
 .../and_k6_frac_tileable_spyio.openfpga       | 59 +++++++++++++++++++
 1 file changed, 59 insertions(+)
 create mode 100644 openfpga/test_script/and_k6_frac_tileable_spyio.openfpga

diff --git a/openfpga/test_script/and_k6_frac_tileable_spyio.openfpga b/openfpga/test_script/and_k6_frac_tileable_spyio.openfpga
new file mode 100644
index 000000000..7b9fa407c
--- /dev/null
+++ b/openfpga/test_script/and_k6_frac_tileable_spyio.openfpga
@@ -0,0 +1,59 @@
+# Run VPR for the 'and' design
+vpr ./test_vpr_arch/k6_frac_N10_tileable_40nm.xml ./test_blif/and.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml
+
+# Write out the architecture XML as a proof
+#write_openfpga_arch -f ./arch_echo.xml
+
+# Annotate the OpenFPGA architecture to VPR data base
+link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to clustering nets based on routing results
+pb_pin_fixup --verbose
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup #--verbose
+
+# Build the module graph 
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules 
+build_fabric --compress_routing --duplicate_grid_pin #--verbose
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream 
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here 
+write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
+
+# Finish and exit OpenFPGA
+exit

From 8b583b79179a57afb1fe0c241aa5133cad41b966 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 5 Apr 2020 16:01:25 -0600
Subject: [PATCH 370/645] debugging spy port builder in module manager

---
 .../src/check_circuit_library.cpp             |  7 ++++---
 openfpga/src/utils/module_manager_utils.cpp   | 19 +++++++++++--------
 2 files changed, 15 insertions(+), 11 deletions(-)

diff --git a/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp b/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp
index afe6e2173..2e8c1a214 100644
--- a/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp
+++ b/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp
@@ -308,8 +308,9 @@ size_t check_circuit_library_ports(const CircuitLibrary& circuit_lib) {
   /* Check global ports: make sure all the global ports are input ports */
   for (const auto& port : circuit_lib.ports()) {
     if ( (circuit_lib.port_is_global(port)) 
-      && (!circuit_lib.is_input_port(port)) ) {
-      VTR_LOG_ERROR("Circuit port (type=%s) of model (name=%s) is defined as global but not an input port!\n",
+      && (!circuit_lib.is_input_port(port)) 
+      && (!circuit_lib.is_output_port(port)) ) {
+      VTR_LOG_ERROR("Circuit port (type=%s) of model (name=%s) is defined as global but not an input/output port!\n",
                     CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(circuit_lib.port_type(port))],
                     circuit_lib.model_name(port).c_str());
       num_err++;
@@ -322,7 +323,7 @@ size_t check_circuit_library_ports(const CircuitLibrary& circuit_lib) {
         || (circuit_lib.port_is_reset(port)) 
         || (circuit_lib.port_is_config_enable(port)) )
       && (!circuit_lib.port_is_global(port)) ) {
-      VTR_LOG_ERROR("Circuit port (type=%s) of model (name=%s) is defined as a set/reset/config_enable port but  it is not global!\n",
+      VTR_LOG_ERROR("Circuit port (type=%s) of model (name=%s) is defined as a set/reset/config_enable port but it is not global!\n",
                     CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(circuit_lib.port_type(port))],
                     circuit_lib.model_name(port).c_str());
       num_err++;
diff --git a/openfpga/src/utils/module_manager_utils.cpp b/openfpga/src/utils/module_manager_utils.cpp
index 5c3f4a41b..8806003b7 100644
--- a/openfpga/src/utils/module_manager_utils.cpp
+++ b/openfpga/src/utils/module_manager_utils.cpp
@@ -1127,6 +1127,7 @@ void add_module_global_input_ports_from_child_modules(ModuleManager& module_mana
 void add_module_global_output_ports_from_child_modules(ModuleManager& module_manager, 
                                                        const ModuleId& module_id) {
   std::vector<BasicPort> global_ports_to_add;
+  std::vector<std::string> global_port_names;
 
   /* Iterate over the child modules */
   for (const ModuleId& child : module_manager.child_modules(module_id)) {
@@ -1135,14 +1136,15 @@ void add_module_global_output_ports_from_child_modules(ModuleManager& module_man
       /* Find all the global ports, whose port type is special */
       for (BasicPort global_port : module_manager.module_ports_by_type(child, ModuleManager::MODULE_SPY_PORT)) {
         /* Search in the global port list to be added, if this is unique, we update the list */
-        std::vector<BasicPort>::iterator it = std::find(global_ports_to_add.begin(), global_ports_to_add.end(), global_port);
-        if (it != global_ports_to_add.end()) {
+        std::vector<std::string>::iterator it = std::find(global_port_names.begin(), global_port_names.end(), global_port.get_name());
+        if (it != global_port_names.end()) {
           /* Found in the global port with the same name, increase the port size */
-          it->expand(global_port.get_width());
+          global_ports_to_add[it - global_port_names.begin()].expand(global_port.get_width());
           continue; /* Finish for the port already in the list */
         }
         /* Reach here, this is an unique global port, update the list */
         global_ports_to_add.push_back(global_port);
+        global_port_names.push_back(global_port.get_name());
       }
     }
   } 
@@ -1168,19 +1170,19 @@ void add_module_global_output_ports_from_child_modules(ModuleManager& module_man
         /* Find the global port from the child module */
         BasicPort child_global_port = module_manager.module_port(child, child_global_port_id);
         /* Search in the global port list to be added, find the port id */
-        std::vector<BasicPort>::iterator it = std::find(global_ports_to_add.begin(), global_ports_to_add.end(), child_global_port);
-        VTR_ASSERT(it != global_ports_to_add.end());
+        std::vector<std::string>::iterator it = std::find(global_port_names.begin(), global_port_names.end(), child_global_port.get_name());
+        VTR_ASSERT(it != global_port_names.end());
 
         /* Find the global port from the parent module */
-        size_t module_global_port_offset = it - global_ports_to_add.begin();
+        size_t module_global_port_offset = it - global_port_names.begin();
         ModulePortId module_global_port_id = global_port_ids[module_global_port_offset];
         BasicPort module_global_port = module_manager.module_port(module_id, module_global_port_id);
         /* Current LSB should be in range */
         VTR_ASSERT(module_global_port.get_width() > global_port_lsbs[module_global_port_offset]);
         /* Set the global port from the parent module as the LSB recorded */
-        module_global_port.set_width(global_port_lsbs[module_global_port_offset], global_port_lsbs[module_global_port_offset]);
+        module_global_port.set_width(global_port_lsbs[module_global_port_offset], global_port_lsbs[module_global_port_offset] + child_global_port.get_width() - 1);
         /* Update the LSB */
-        global_port_lsbs[module_global_port_offset]++;
+        global_port_lsbs[module_global_port_offset] += child_global_port.get_width();
 
         /* The global ports should match in size */
         VTR_ASSERT(module_global_port.get_width() == child_global_port.get_width());
@@ -1199,6 +1201,7 @@ void add_module_global_output_ports_from_child_modules(ModuleManager& module_man
   /* Find check: all the LSBs of global ports should match the MSB */
   for (size_t iport = 0; iport < global_port_ids.size(); ++iport) {
     BasicPort module_global_port = module_manager.module_port(module_id, global_port_ids[iport]);
+    if (module_global_port.get_width() != global_port_lsbs[iport]) 
     VTR_ASSERT(module_global_port.get_width() == global_port_lsbs[iport]); 
   }
 }

From bc47b3ca94befd33e9b78990aa26a77bad5b5693 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 5 Apr 2020 16:04:13 -0600
Subject: [PATCH 371/645] update verilog module writer to the global spy ports

---
 openfpga/src/fpga_verilog/verilog_module_writer.cpp | 1 +
 1 file changed, 1 insertion(+)

diff --git a/openfpga/src/fpga_verilog/verilog_module_writer.cpp b/openfpga/src/fpga_verilog/verilog_module_writer.cpp
index 34c2c4be7..0d6103beb 100644
--- a/openfpga/src/fpga_verilog/verilog_module_writer.cpp
+++ b/openfpga/src/fpga_verilog/verilog_module_writer.cpp
@@ -396,6 +396,7 @@ void write_verilog_instance_to_file(std::fstream& fp,
   /* port type2type mapping */
   std::map<ModuleManager::e_module_port_type, enum e_dump_verilog_port_type> port_type2type_map;
   port_type2type_map[ModuleManager::MODULE_GLOBAL_PORT] = VERILOG_PORT_CONKT;
+  port_type2type_map[ModuleManager::MODULE_SPY_PORT] = VERILOG_PORT_CONKT;
   port_type2type_map[ModuleManager::MODULE_GPIO_PORT] = VERILOG_PORT_CONKT;
   port_type2type_map[ModuleManager::MODULE_INOUT_PORT] = VERILOG_PORT_CONKT;
   port_type2type_map[ModuleManager::MODULE_INPUT_PORT] = VERILOG_PORT_CONKT;

From 5f4e7dc5d413fc143c64e91b451f7eb30a732516 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 5 Apr 2020 16:52:21 -0600
Subject: [PATCH 372/645] support gpinput and gpoutput ports in module manager
 and circuit library

---
 .../libarchopenfpga/src/circuit_library.cpp   |  16 ++
 .../libarchopenfpga/src/circuit_library.h     |   4 +
 .../src/read_xml_circuit_library.cpp          |   7 +
 openfpga/src/fabric/module_manager.cpp        |   2 +-
 openfpga/src/fabric/module_manager.h          |   3 +-
 .../fpga_verilog/verilog_module_writer.cpp    |   3 +-
 .../src/fpga_verilog/verilog_writer_utils.cpp |   9 +-
 openfpga/src/utils/module_manager_utils.cpp   | 188 +++++++-----------
 .../k6_frac_N10_spyio_40nm_openfpga.xml       |   2 +
 9 files changed, 107 insertions(+), 127 deletions(-)

diff --git a/libopenfpga/libarchopenfpga/src/circuit_library.cpp b/libopenfpga/libarchopenfpga/src/circuit_library.cpp
index 0ea7139df..cf8b8714f 100644
--- a/libopenfpga/libarchopenfpga/src/circuit_library.cpp
+++ b/libopenfpga/libarchopenfpga/src/circuit_library.cpp
@@ -892,6 +892,12 @@ size_t CircuitLibrary::port_default_value(const CircuitPortId& circuit_port_id)
   return port_default_values_[circuit_port_id];
 }
 
+/* Return a flag if the port is used in mode-selection purpuse of a circuit model */
+bool CircuitLibrary::port_is_io(const CircuitPortId& circuit_port_id) const {
+  /* validate the circuit_port_id */
+  VTR_ASSERT(valid_circuit_port_id(circuit_port_id));
+  return port_is_io_[circuit_port_id];
+}
 
 /* Return a flag if the port is used in mode-selection purpuse of a circuit model */
 bool CircuitLibrary::port_is_mode_select(const CircuitPortId& circuit_port_id) const {
@@ -1344,6 +1350,7 @@ CircuitPortId CircuitLibrary::add_model_port(const CircuitModelId& model_id,
   port_lib_names_.emplace_back();
   port_inv_prefix_.emplace_back();
   port_default_values_.push_back(-1);
+  port_is_io_.push_back(false);
   port_is_mode_select_.push_back(false);
   port_is_global_.push_back(false);
   port_is_reset_.push_back(false);
@@ -1414,6 +1421,15 @@ void CircuitLibrary::set_port_default_value(const CircuitPortId& circuit_port_id
   return;
 }
 
+/* Set the is_mode_select for a port of a circuit model */
+void CircuitLibrary::set_port_is_io(const CircuitPortId& circuit_port_id, 
+                                    const bool& is_io) {
+  /* validate the circuit_port_id */
+  VTR_ASSERT(valid_circuit_port_id(circuit_port_id));
+  port_is_io_[circuit_port_id] = is_io;
+  return;
+}
+
 /* Set the is_mode_select for a port of a circuit model */
 void CircuitLibrary::set_port_is_mode_select(const CircuitPortId& circuit_port_id, 
                                              const bool& is_mode_select) {
diff --git a/libopenfpga/libarchopenfpga/src/circuit_library.h b/libopenfpga/libarchopenfpga/src/circuit_library.h
index 8f2781349..c6a62dc27 100644
--- a/libopenfpga/libarchopenfpga/src/circuit_library.h
+++ b/libopenfpga/libarchopenfpga/src/circuit_library.h
@@ -275,6 +275,7 @@ class CircuitLibrary {
     std::string port_lib_name(const CircuitPortId& circuit_port_id) const;
     std::string port_inv_prefix(const CircuitPortId& circuit_port_id) const;
     size_t port_default_value(const CircuitPortId& circuit_port_id) const;
+    bool port_is_io(const CircuitPortId& circuit_port_id) const;
     bool port_is_mode_select(const CircuitPortId& circuit_port_id) const;
     bool port_is_global(const CircuitPortId& circuit_port_id) const;
     bool port_is_reset(const CircuitPortId& circuit_port_id) const;
@@ -346,6 +347,8 @@ class CircuitLibrary {
                              const std::string& inv_prefix);
     void set_port_default_value(const CircuitPortId& circuit_port_id, 
                                 const size_t& default_val);
+    void set_port_is_io(const CircuitPortId& circuit_port_id, 
+                        const bool& is_io);
     void set_port_is_mode_select(const CircuitPortId& circuit_port_id, 
                                  const bool& is_mode_select);
     void set_port_is_global(const CircuitPortId& circuit_port_id, 
@@ -529,6 +532,7 @@ class CircuitLibrary {
     vtr::vector<CircuitPortId, std::string> port_lib_names_;
     vtr::vector<CircuitPortId, std::string> port_inv_prefix_;
     vtr::vector<CircuitPortId, size_t> port_default_values_;
+    vtr::vector<CircuitPortId, bool> port_is_io_;
     vtr::vector<CircuitPortId, bool> port_is_mode_select_;
     vtr::vector<CircuitPortId, bool> port_is_global_;
     vtr::vector<CircuitPortId, bool> port_is_reset_;
diff --git a/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp b/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp
index af12297d1..cd8ffd1c5 100644
--- a/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp
+++ b/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp
@@ -486,6 +486,13 @@ void read_xml_circuit_port(pugi::xml_node& xml_port,
   /* Parse the port size, by default it will be 1 */
   circuit_lib.set_port_size(port, get_attribute(xml_port, "size", loc_data).as_int(1));
 
+  /* Identify if the port is for io, this is only applicable to INPUT ports.
+   * By default, it will NOT be a mode selection port
+   */
+  if (CIRCUIT_MODEL_PORT_INPUT == circuit_lib.port_type(port)) {
+    circuit_lib.set_port_is_io(port, get_attribute(xml_port, "io", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false));
+  } 
+
   /* Identify if the port is for mode selection, this is only applicable to SRAM ports.
    * By default, it will NOT be a mode selection port
    */
diff --git a/openfpga/src/fabric/module_manager.cpp b/openfpga/src/fabric/module_manager.cpp
index 7f444318e..d03af54b0 100644
--- a/openfpga/src/fabric/module_manager.cpp
+++ b/openfpga/src/fabric/module_manager.cpp
@@ -120,7 +120,7 @@ std::string ModuleManager::module_name(const ModuleId& module_id) const {
 
 /* Get the string of a module port type */
 std::string ModuleManager::module_port_type_str(const enum e_module_port_type& port_type) const {
-  std::array<const char*, NUM_MODULE_PORT_TYPES> MODULE_PORT_TYPE_STRING = {{"GLOBAL PORTS", "SPY PORTS", "GPIO PORTS", "INOUT PORTS", "INPUT PORTS", "OUTPUT PORTS", "CLOCK PORTS"}};
+  std::array<const char*, NUM_MODULE_PORT_TYPES> MODULE_PORT_TYPE_STRING = {{"GLOBAL PORTS", "GPIN PORTS", "GPOUT PORTS", "GPIO PORTS", "INOUT PORTS", "INPUT PORTS", "OUTPUT PORTS", "CLOCK PORTS"}};
   return MODULE_PORT_TYPE_STRING[port_type];
 }
 
diff --git a/openfpga/src/fabric/module_manager.h b/openfpga/src/fabric/module_manager.h
index 1bfbd8b49..cd79bde8c 100644
--- a/openfpga/src/fabric/module_manager.h
+++ b/openfpga/src/fabric/module_manager.h
@@ -28,7 +28,8 @@ class ModuleManager {
   public: /* Private data structures */
     enum e_module_port_type {
       MODULE_GLOBAL_PORT, /* Global inputs */
-      MODULE_SPY_PORT,    /* Global outputs, which is designed for spypads */
+      MODULE_GPIN_PORT,   /* General-purpose input */
+      MODULE_GPOUT_PORT,  /* General-purpose outputs, could be used for spypads */
       MODULE_GPIO_PORT,   /* General-purpose IOs, which are data IOs of the fabric */
       MODULE_INOUT_PORT,  /* Normal (non-global) inout ports */
       MODULE_INPUT_PORT,  /* Normal (non-global) input ports */
diff --git a/openfpga/src/fpga_verilog/verilog_module_writer.cpp b/openfpga/src/fpga_verilog/verilog_module_writer.cpp
index 0d6103beb..7d6883236 100644
--- a/openfpga/src/fpga_verilog/verilog_module_writer.cpp
+++ b/openfpga/src/fpga_verilog/verilog_module_writer.cpp
@@ -396,7 +396,8 @@ void write_verilog_instance_to_file(std::fstream& fp,
   /* port type2type mapping */
   std::map<ModuleManager::e_module_port_type, enum e_dump_verilog_port_type> port_type2type_map;
   port_type2type_map[ModuleManager::MODULE_GLOBAL_PORT] = VERILOG_PORT_CONKT;
-  port_type2type_map[ModuleManager::MODULE_SPY_PORT] = VERILOG_PORT_CONKT;
+  port_type2type_map[ModuleManager::MODULE_GPIN_PORT] = VERILOG_PORT_CONKT;
+  port_type2type_map[ModuleManager::MODULE_GPOUT_PORT] = VERILOG_PORT_CONKT;
   port_type2type_map[ModuleManager::MODULE_GPIO_PORT] = VERILOG_PORT_CONKT;
   port_type2type_map[ModuleManager::MODULE_INOUT_PORT] = VERILOG_PORT_CONKT;
   port_type2type_map[ModuleManager::MODULE_INPUT_PORT] = VERILOG_PORT_CONKT;
diff --git a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp
index b771f4752..90ee95e9c 100644
--- a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp
+++ b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp
@@ -129,7 +129,8 @@ void print_verilog_module_definition(std::fstream& fp,
   /* port type2type mapping */
   std::map<ModuleManager::e_module_port_type, enum e_dump_verilog_port_type> port_type2type_map;
   port_type2type_map[ModuleManager::MODULE_GLOBAL_PORT] = VERILOG_PORT_CONKT;
-  port_type2type_map[ModuleManager::MODULE_SPY_PORT] = VERILOG_PORT_CONKT;
+  port_type2type_map[ModuleManager::MODULE_GPIN_PORT] = VERILOG_PORT_CONKT;
+  port_type2type_map[ModuleManager::MODULE_GPOUT_PORT] = VERILOG_PORT_CONKT;
   port_type2type_map[ModuleManager::MODULE_GPIO_PORT] = VERILOG_PORT_CONKT;
   port_type2type_map[ModuleManager::MODULE_INOUT_PORT] = VERILOG_PORT_CONKT;
   port_type2type_map[ModuleManager::MODULE_INPUT_PORT] = VERILOG_PORT_CONKT;
@@ -189,7 +190,8 @@ void print_verilog_module_ports(std::fstream& fp,
   /* port type2type mapping */
   std::map<ModuleManager::e_module_port_type, enum e_dump_verilog_port_type> port_type2type_map;
   port_type2type_map[ModuleManager::MODULE_GLOBAL_PORT] = VERILOG_PORT_INPUT;
-  port_type2type_map[ModuleManager::MODULE_SPY_PORT] = VERILOG_PORT_OUTPUT;
+  port_type2type_map[ModuleManager::MODULE_GPIN_PORT] = VERILOG_PORT_INPUT;
+  port_type2type_map[ModuleManager::MODULE_GPOUT_PORT] = VERILOG_PORT_OUTPUT;
   port_type2type_map[ModuleManager::MODULE_GPIO_PORT] = VERILOG_PORT_INOUT;
   port_type2type_map[ModuleManager::MODULE_INOUT_PORT] = VERILOG_PORT_INOUT;
   port_type2type_map[ModuleManager::MODULE_INPUT_PORT] = VERILOG_PORT_INPUT;
@@ -346,7 +348,8 @@ void print_verilog_module_instance(std::fstream& fp,
   /* port type2type mapping */
   std::map<ModuleManager::e_module_port_type, enum e_dump_verilog_port_type> port_type2type_map;
   port_type2type_map[ModuleManager::MODULE_GLOBAL_PORT] = VERILOG_PORT_CONKT;
-  port_type2type_map[ModuleManager::MODULE_SPY_PORT] = VERILOG_PORT_CONKT;
+  port_type2type_map[ModuleManager::MODULE_GPIN_PORT] = VERILOG_PORT_CONKT;
+  port_type2type_map[ModuleManager::MODULE_GPOUT_PORT] = VERILOG_PORT_CONKT;
   port_type2type_map[ModuleManager::MODULE_GPIO_PORT] = VERILOG_PORT_CONKT;
   port_type2type_map[ModuleManager::MODULE_INOUT_PORT] = VERILOG_PORT_CONKT;
   port_type2type_map[ModuleManager::MODULE_INPUT_PORT] = VERILOG_PORT_CONKT;
diff --git a/openfpga/src/utils/module_manager_utils.cpp b/openfpga/src/utils/module_manager_utils.cpp
index 8806003b7..3c1ef2de2 100644
--- a/openfpga/src/utils/module_manager_utils.cpp
+++ b/openfpga/src/utils/module_manager_utils.cpp
@@ -42,13 +42,17 @@ ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager,
    */
   for (const auto& port : circuit_lib.model_global_ports(circuit_model, false)) {
     BasicPort port_info(circuit_lib.port_prefix(port), circuit_lib.port_size(port));
-    if (CIRCUIT_MODEL_PORT_INPUT == circuit_lib.port_type(port)) {
+    if ( (CIRCUIT_MODEL_PORT_INPUT == circuit_lib.port_type(port))
+      && (false == circuit_lib.port_is_io(port)) ) {
       module_manager.add_port(module, port_info, ModuleManager::MODULE_GLOBAL_PORT);  
     } else if (CIRCUIT_MODEL_PORT_CLOCK == circuit_lib.port_type(port)) {
       module_manager.add_port(module, port_info, ModuleManager::MODULE_GLOBAL_PORT);  
+    } else if ( (CIRCUIT_MODEL_PORT_INPUT == circuit_lib.port_type(port))
+             && (false == circuit_lib.port_is_io(port)) ) {
+      module_manager.add_port(module, port_info, ModuleManager::MODULE_GPIN_PORT);  
     } else {
       VTR_ASSERT(CIRCUIT_MODEL_PORT_OUTPUT == circuit_lib.port_type(port));
-      module_manager.add_port(module, port_info, ModuleManager::MODULE_SPY_PORT);  
+      module_manager.add_port(module, port_info, ModuleManager::MODULE_GPOUT_PORT);  
     }
   }
 
@@ -931,19 +935,35 @@ size_t find_module_num_config_bits(const ModuleManager& module_manager,
 }
 
 /********************************************************************
- * Add GPIO ports to the module:
+ * Add General purpose I/O ports to the module:
  * In this function, the following tasks are done: 
- * 1. find all the GPIO ports from the child modules and build a list of it,
- * 2. Merge all the GPIO ports with the same name
+ * 1. find all the I/O ports from the child modules and build a list of it,
+ * 2. Merge all the I/O ports with the same name
  * 3. add the ports to the pb_module
  * 4. add module nets to connect to the GPIO ports of each sub module 
+ *
+ *   Module
+ *   ----------------------+
+ *                         |
+ *   child[0]              |
+ *   -----------+          |
+ *              |----------+----> outputA[0]
+ *   -----------+          |
+ *                         |
+ *   child[1]              |
+ *   -----------+          |
+ *              |----------+----> outputA[1]
+ *   -----------+          |
+
  *
  * Note: This function should be call ONLY after all the sub modules (instances)
  * have been added to the pb_module!
  * Otherwise, some GPIO ports of the sub modules may be missed!
  *******************************************************************/
-void add_module_gpio_ports_from_child_modules(ModuleManager& module_manager, 
-                                              const ModuleId& module_id) {
+static 
+void add_module_io_ports_from_child_modules(ModuleManager& module_manager, 
+                                            const ModuleId& module_id,
+                                            const ModuleManager::e_module_port_type& module_port_type) {
   std::vector<BasicPort> gpio_ports_to_add;
 
   /* Iterate over the child modules */
@@ -951,7 +971,7 @@ void add_module_gpio_ports_from_child_modules(ModuleManager& module_manager,
     /* Iterate over the child instances */
     for (size_t i = 0; i < module_manager.num_instance(module_id, child); ++i) {
       /* Find all the global ports, whose port type is special */
-      for (BasicPort gpio_port : module_manager.module_ports_by_type(child, ModuleManager::MODULE_GPIO_PORT)) {
+      for (BasicPort gpio_port : module_manager.module_ports_by_type(child, module_port_type)) {
         /* If this port is not mergeable, we update the list */
         bool is_mergeable = false;
         for (BasicPort& gpio_port_to_add : gpio_ports_to_add) {
@@ -979,7 +999,7 @@ void add_module_gpio_ports_from_child_modules(ModuleManager& module_manager,
   std::vector<ModulePortId> gpio_port_ids;
   /* Add the gpio ports for the module */
   for (const BasicPort& gpio_port_to_add : gpio_ports_to_add) {
-    ModulePortId port_id = module_manager.add_port(module_id, gpio_port_to_add, ModuleManager::MODULE_GPIO_PORT);
+    ModulePortId port_id = module_manager.add_port(module_id, gpio_port_to_add, module_port_type);
     gpio_port_ids.push_back(port_id);
   } 
 
@@ -990,7 +1010,7 @@ void add_module_gpio_ports_from_child_modules(ModuleManager& module_manager,
     /* Iterate over the child instances */
     for (const size_t& child_instance : module_manager.child_module_instances(module_id, child)) {
       /* Find all the global ports, whose port type is special */
-      for (ModulePortId child_gpio_port_id : module_manager.module_port_ids_by_type(child, ModuleManager::MODULE_GPIO_PORT)) {
+      for (ModulePortId child_gpio_port_id : module_manager.module_port_ids_by_type(child, module_port_type)) {
         BasicPort child_gpio_port = module_manager.module_port(child, child_gpio_port_id);
         /* Find the port with the same name! */
         for (size_t iport = 0; iport < gpio_ports_to_add.size(); ++iport) {
@@ -1001,8 +1021,22 @@ void add_module_gpio_ports_from_child_modules(ModuleManager& module_manager,
           for (const size_t& pin_id : child_gpio_port.pins()) {
             /* Reach here, it means this is the port we want, create a net and configure its source and sink */
             ModuleNetId net = module_manager.create_module_net(module_id);
-            module_manager.add_module_net_source(module_id, net, module_id, 0, gpio_port_ids[iport], gpio_port_lsb[iport]); 
-            module_manager.add_module_net_sink(module_id, net, child, child_instance, child_gpio_port_id, pin_id); 
+            /* - For GPIO and GPIN ports
+             *   the source of the net is the current module 
+             *   the sink of the net is the child module
+             * - For GPOUT ports
+             *   the source of the net is the child module
+             *   the sink of the net is the current module 
+             */
+            if ( (ModuleManager::MODULE_GPIO_PORT == module_port_type)
+              || (ModuleManager::MODULE_GPIN_PORT == module_port_type) ) {
+              module_manager.add_module_net_source(module_id, net, module_id, 0, gpio_port_ids[iport], gpio_port_lsb[iport]); 
+              module_manager.add_module_net_sink(module_id, net, child, child_instance, child_gpio_port_id, pin_id); 
+            } else {
+              VTR_ASSERT(ModuleManager::MODULE_GPOUT_PORT == module_port_type);
+              module_manager.add_module_net_sink(module_id, net, module_id, 0, gpio_port_ids[iport], gpio_port_lsb[iport]); 
+              module_manager.add_module_net_source(module_id, net, child, child_instance, child_gpio_port_id, pin_id); 
+            }
             /* Update the LSB counter */
             gpio_port_lsb[iport]++;
           }
@@ -1020,6 +1054,27 @@ void add_module_gpio_ports_from_child_modules(ModuleManager& module_manager,
   }
 }
 
+/********************************************************************
+ * Add GPIO ports to the module:
+ * In this function, the following tasks are done: 
+ * 1. find all the GPIO ports from the child modules and build a list of it,
+ * 2. Merge all the GPIO ports with the same name
+ * 3. add the ports to the pb_module
+ * 4. add module nets to connect to the GPIO ports of each sub module 
+ *
+ * Note: This function should be call ONLY after all the sub modules (instances)
+ * have been added to the pb_module!
+ * Otherwise, some GPIO ports of the sub modules may be missed!
+ *******************************************************************/
+void add_module_gpio_ports_from_child_modules(ModuleManager& module_manager, 
+                                              const ModuleId& module_id) {
+  add_module_io_ports_from_child_modules(module_manager, module_id, ModuleManager::MODULE_GPIO_PORT);
+
+  add_module_io_ports_from_child_modules(module_manager, module_id, ModuleManager::MODULE_GPIN_PORT);
+
+  add_module_io_ports_from_child_modules(module_manager, module_id, ModuleManager::MODULE_GPOUT_PORT);
+}
+
 /********************************************************************
  * Add global input ports to the module:
  * In this function, the following tasks are done: 
@@ -1100,112 +1155,6 @@ void add_module_global_input_ports_from_child_modules(ModuleManager& module_mana
   } 
 }
 
-/********************************************************************
- * Add global output ports to the module:
- * In this function, the following tasks are done: 
- * 1. find all the global output ports from the child modules and build a list of it,
- * 2. add the output ports to the pb_module
- * 3. add the module nets to connect the pb_module global ports to those of child modules
- *
- *   Module
- *   ----------------------+
- *                         |
- *   child[0]              |
- *   -----------+          |
- *              |----------+----> outputA[0]
- *   -----------+          |
- *                         |
- *   child[1]              |
- *   -----------+          |
- *              |----------+----> outputA[1]
- *   -----------+          |
- *
- * Note: This function should be call ONLY after all the sub modules (instances)
- * have been added to the pb_module!
- * Otherwise, some global ports of the sub modules may be missed!
- *******************************************************************/
-void add_module_global_output_ports_from_child_modules(ModuleManager& module_manager, 
-                                                       const ModuleId& module_id) {
-  std::vector<BasicPort> global_ports_to_add;
-  std::vector<std::string> global_port_names;
-
-  /* Iterate over the child modules */
-  for (const ModuleId& child : module_manager.child_modules(module_id)) {
-    /* Iterate over the child instances */
-    for (size_t i = 0; i < module_manager.num_instance(module_id, child); ++i) {
-      /* Find all the global ports, whose port type is special */
-      for (BasicPort global_port : module_manager.module_ports_by_type(child, ModuleManager::MODULE_SPY_PORT)) {
-        /* Search in the global port list to be added, if this is unique, we update the list */
-        std::vector<std::string>::iterator it = std::find(global_port_names.begin(), global_port_names.end(), global_port.get_name());
-        if (it != global_port_names.end()) {
-          /* Found in the global port with the same name, increase the port size */
-          global_ports_to_add[it - global_port_names.begin()].expand(global_port.get_width());
-          continue; /* Finish for the port already in the list */
-        }
-        /* Reach here, this is an unique global port, update the list */
-        global_ports_to_add.push_back(global_port);
-        global_port_names.push_back(global_port.get_name());
-      }
-    }
-  } 
-
-  /* Record the port id for each type of global port */
-  std::vector<ModulePortId> global_port_ids;
-  /* Add the global ports for the module */
-  for (const BasicPort& global_port_to_add : global_ports_to_add) {
-    ModulePortId port_id = module_manager.add_port(module_id, global_port_to_add, ModuleManager::MODULE_SPY_PORT);
-    global_port_ids.push_back(port_id);
-  } 
-
-  /* Add module nets to connect the global ports of the module to the global ports of the sub module */
-  /* Create a counter for each global port to record the current LSB */
-  std::vector<size_t> global_port_lsbs(global_port_ids.size(), 0);
-
-  /* Iterate over the child modules */
-  for (const ModuleId& child : module_manager.child_modules(module_id)) {
-    /* Iterate over the child instances */
-    for (const size_t& child_instance : module_manager.child_module_instances(module_id, child)) {
-      /* Find all the global ports, whose port type is special */
-      for (ModulePortId child_global_port_id : module_manager.module_port_ids_by_type(child, ModuleManager::MODULE_SPY_PORT)) {
-        /* Find the global port from the child module */
-        BasicPort child_global_port = module_manager.module_port(child, child_global_port_id);
-        /* Search in the global port list to be added, find the port id */
-        std::vector<std::string>::iterator it = std::find(global_port_names.begin(), global_port_names.end(), child_global_port.get_name());
-        VTR_ASSERT(it != global_port_names.end());
-
-        /* Find the global port from the parent module */
-        size_t module_global_port_offset = it - global_port_names.begin();
-        ModulePortId module_global_port_id = global_port_ids[module_global_port_offset];
-        BasicPort module_global_port = module_manager.module_port(module_id, module_global_port_id);
-        /* Current LSB should be in range */
-        VTR_ASSERT(module_global_port.get_width() > global_port_lsbs[module_global_port_offset]);
-        /* Set the global port from the parent module as the LSB recorded */
-        module_global_port.set_width(global_port_lsbs[module_global_port_offset], global_port_lsbs[module_global_port_offset] + child_global_port.get_width() - 1);
-        /* Update the LSB */
-        global_port_lsbs[module_global_port_offset] += child_global_port.get_width();
-
-        /* The global ports should match in size */
-        VTR_ASSERT(module_global_port.get_width() == child_global_port.get_width());
-        /* For each pin of the child port, create a net and do wiring */
-        for (size_t pin_id = 0; pin_id < child_global_port.pins().size(); ++pin_id) {
-          /* Reach here, it means this is the port we want, create a net and configure its source and sink */
-          ModuleNetId net = module_manager.create_module_net(module_id);
-          module_manager.add_module_net_source(module_id, net, child, child_instance, child_global_port_id, child_global_port.pins()[pin_id]); 
-          module_manager.add_module_net_sink(module_id, net, module_id, 0, module_global_port_id, module_global_port.pins()[pin_id]); 
-          /* We finish for this child gpio port */
-        }
-      }
-    }
-  } 
-
-  /* Find check: all the LSBs of global ports should match the MSB */
-  for (size_t iport = 0; iport < global_port_ids.size(); ++iport) {
-    BasicPort module_global_port = module_manager.module_port(module_id, global_port_ids[iport]);
-    if (module_global_port.get_width() != global_port_lsbs[iport]) 
-    VTR_ASSERT(module_global_port.get_width() == global_port_lsbs[iport]); 
-  }
-}
-
 /********************************************************************
  * Add global ports to the module:
  * In this function, we will add global input ports and global output ports 
@@ -1228,9 +1177,6 @@ void add_module_global_ports_from_child_modules(ModuleManager& module_manager,
                                                 const ModuleId& module_id) {
   /* Input ports */
   add_module_global_input_ports_from_child_modules(module_manager, module_id);
-
-  /* Output ports */
-  add_module_global_output_ports_from_child_modules(module_manager, module_id);
 }
 
 /********************************************************************
diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml
index 9d81c5b3e..b8f5fc249 100644
--- a/openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml
@@ -181,6 +181,8 @@
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="inout" prefix="pad" size="1"/>
       <!-- A spypad for the direction port of the I/O pad, which can be visible in the fpga_top -->
+      <port type="input" prefix="din" size="1" is_global="true" is_io="true" default_value="0"/>
+      <port type="output" prefix="dout" size="1" is_global="true"/>
       <port type="output" prefix="dir" size="1" is_global="true"/>
       <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
       <port type="input" prefix="outpad" size="1"/>

From bcb86801faf0ac0022b0d5fa7dbf564217d8defa Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 5 Apr 2020 17:26:44 -0600
Subject: [PATCH 373/645] bug fixed in gpio naming for module manager ports

---
 openfpga/src/base/openfpga_naming.cpp         |  5 +-
 openfpga/src/base/openfpga_naming.h           |  3 +-
 openfpga/src/fabric/build_grid_modules.cpp    | 68 ++++++++++++++++---
 openfpga/src/utils/module_manager_utils.cpp   |  2 +-
 .../k6_frac_N10_spyio_40nm_openfpga.xml       |  2 +-
 5 files changed, 65 insertions(+), 15 deletions(-)

diff --git a/openfpga/src/base/openfpga_naming.cpp b/openfpga/src/base/openfpga_naming.cpp
index 530db8cc6..99d59afdb 100644
--- a/openfpga/src/base/openfpga_naming.cpp
+++ b/openfpga/src/base/openfpga_naming.cpp
@@ -1339,10 +1339,13 @@ std::string generate_pb_type_port_name(t_port* pb_type_port) {
  ********************************************************************/
 std::string generate_fpga_global_io_port_name(const std::string& prefix, 
                                               const CircuitLibrary& circuit_lib,
-                                              const CircuitModelId& circuit_model) {
+                                              const CircuitModelId& circuit_model,
+                                              const CircuitPortId& circuit_port) {
   std::string port_name(prefix);
   
   port_name += circuit_lib.model_name(circuit_model);
+  port_name += std::string("_");
+  port_name += circuit_lib.port_prefix(circuit_port);
    
   return port_name;
 }
diff --git a/openfpga/src/base/openfpga_naming.h b/openfpga/src/base/openfpga_naming.h
index e4f1ee8f8..40d7f05e9 100644
--- a/openfpga/src/base/openfpga_naming.h
+++ b/openfpga/src/base/openfpga_naming.h
@@ -242,7 +242,8 @@ std::string generate_pb_type_port_name(t_port* pb_type_port);
 
 std::string generate_fpga_global_io_port_name(const std::string& prefix, 
                                               const CircuitLibrary& circuit_lib,
-                                              const CircuitModelId& circuit_model);
+                                              const CircuitModelId& circuit_model,
+                                              const CircuitPortId& circuit_port);
 
 std::string generate_fpga_top_module_name();
 
diff --git a/openfpga/src/fabric/build_grid_modules.cpp b/openfpga/src/fabric/build_grid_modules.cpp
index e55640834..741632d1c 100644
--- a/openfpga/src/fabric/build_grid_modules.cpp
+++ b/openfpga/src/fabric/build_grid_modules.cpp
@@ -144,6 +144,38 @@ void add_grid_module_nets_connect_pb_type_ports(ModuleManager& module_manager,
   }
 }
 
+/********************************************************************
+ *******************************************************************/
+static 
+void add_primitive_module_fpga_global_io_port(ModuleManager& module_manager,
+                                              const ModuleId& primitive_module,
+                                              const ModuleId& logic_module,
+                                              const size_t& logic_instance_id,
+                                              const ModuleManager::e_module_port_type& module_io_port_type,
+                                              const CircuitLibrary& circuit_lib,
+                                              const CircuitModelId& primitive_model,
+                                              const CircuitPortId& circuit_port) {
+  BasicPort module_port(generate_fpga_global_io_port_name(std::string(GIO_INOUT_PREFIX), circuit_lib, primitive_model, circuit_port), circuit_lib.port_size(circuit_port));
+  ModulePortId primitive_io_port_id = module_manager.add_port(primitive_module, module_port, module_io_port_type);
+  ModulePortId logic_io_port_id = module_manager.find_module_port(logic_module, circuit_lib.port_prefix(circuit_port));
+  BasicPort logic_io_port = module_manager.module_port(logic_module, logic_io_port_id);
+  VTR_ASSERT(logic_io_port.get_width() == module_port.get_width());
+
+  /* Wire the GPIO port form primitive_module to the logic module!*/
+  for (size_t pin_id = 0; pin_id < module_port.pins().size(); ++pin_id) {      
+    ModuleNetId net = module_manager.create_module_net(primitive_module);
+    if ( (ModuleManager::MODULE_GPIO_PORT == module_io_port_type)
+      || (ModuleManager::MODULE_GPIN_PORT == module_io_port_type) ) {
+      module_manager.add_module_net_source(primitive_module, net, primitive_module, 0, primitive_io_port_id, module_port.pins()[pin_id]);
+      module_manager.add_module_net_sink(primitive_module, net, logic_module, logic_instance_id, logic_io_port_id, logic_io_port.pins()[pin_id]);
+    } else {
+      VTR_ASSERT(ModuleManager::MODULE_GPOUT_PORT == module_io_port_type);
+      module_manager.add_module_net_source(primitive_module, net, logic_module, logic_instance_id, logic_io_port_id, logic_io_port.pins()[pin_id]);
+      module_manager.add_module_net_sink(primitive_module, net, primitive_module, 0, primitive_io_port_id, module_port.pins()[pin_id]);
+    }
+  }
+}
+
 /********************************************************************
  * Print Verilog modules of a primitive node in the pb_graph_node graph
  * This generic function can support all the different types of primitive nodes
@@ -275,18 +307,32 @@ void build_primitive_block_module(ModuleManager& module_manager,
   if (CIRCUIT_MODEL_IOPAD == circuit_lib.model_type(primitive_model)) {
     std::vector<CircuitPortId> primitive_model_inout_ports = circuit_lib.model_ports_by_type(primitive_model, CIRCUIT_MODEL_PORT_INOUT);
     for (auto port : primitive_model_inout_ports) {
-      BasicPort module_port(generate_fpga_global_io_port_name(std::string(GIO_INOUT_PREFIX), circuit_lib, primitive_model), circuit_lib.port_size(port));
-      ModulePortId primitive_gpio_port_id = module_manager.add_port(primitive_module, module_port, ModuleManager::MODULE_GPIO_PORT);
-      ModulePortId logic_gpio_port_id = module_manager.find_module_port(logic_module, circuit_lib.port_prefix(port));
-      BasicPort logic_gpio_port = module_manager.module_port(logic_module, logic_gpio_port_id);
-      VTR_ASSERT(logic_gpio_port.get_width() == module_port.get_width());
+      add_primitive_module_fpga_global_io_port(module_manager, primitive_module,
+                                               logic_module, logic_instance_id,
+                                               ModuleManager::MODULE_GPIO_PORT,
+                                               circuit_lib,
+                                               primitive_model,
+                                               port);
+    }
+  }
 
-      /* Wire the GPIO port form primitive_module to the logic module!*/
-      for (size_t pin_id = 0; pin_id < module_port.pins().size(); ++pin_id) {      
-        ModuleNetId net = module_manager.create_module_net(primitive_module);
-        module_manager.add_module_net_source(primitive_module, net, primitive_module, 0, primitive_gpio_port_id, module_port.pins()[pin_id]);
-        module_manager.add_module_net_sink(primitive_module, net, logic_module, logic_instance_id, logic_gpio_port_id, logic_gpio_port.pins()[pin_id]);
-      }
+  /* Find the other i/o ports required by the primitive node, and add them to the module */
+  for (const auto& port : circuit_lib.model_global_ports(primitive_model, false)) {
+    if ( (CIRCUIT_MODEL_PORT_INPUT == circuit_lib.port_type(port))
+      && (true == circuit_lib.port_is_io(port)) ) {
+      add_primitive_module_fpga_global_io_port(module_manager, primitive_module,
+                                               logic_module, logic_instance_id,
+                                               ModuleManager::MODULE_GPIN_PORT,
+                                               circuit_lib,
+                                               primitive_model,
+                                               port);
+    } else if (CIRCUIT_MODEL_PORT_OUTPUT == circuit_lib.port_type(port)) {
+      add_primitive_module_fpga_global_io_port(module_manager, primitive_module,
+                                               logic_module, logic_instance_id,
+                                               ModuleManager::MODULE_GPOUT_PORT,
+                                               circuit_lib,
+                                               primitive_model,
+                                               port);
     }
   }
 
diff --git a/openfpga/src/utils/module_manager_utils.cpp b/openfpga/src/utils/module_manager_utils.cpp
index 3c1ef2de2..64bef2e88 100644
--- a/openfpga/src/utils/module_manager_utils.cpp
+++ b/openfpga/src/utils/module_manager_utils.cpp
@@ -48,7 +48,7 @@ ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager,
     } else if (CIRCUIT_MODEL_PORT_CLOCK == circuit_lib.port_type(port)) {
       module_manager.add_port(module, port_info, ModuleManager::MODULE_GLOBAL_PORT);  
     } else if ( (CIRCUIT_MODEL_PORT_INPUT == circuit_lib.port_type(port))
-             && (false == circuit_lib.port_is_io(port)) ) {
+             && (true == circuit_lib.port_is_io(port)) ) {
       module_manager.add_port(module, port_info, ModuleManager::MODULE_GPIN_PORT);  
     } else {
       VTR_ASSERT(CIRCUIT_MODEL_PORT_OUTPUT == circuit_lib.port_type(port));
diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml
index b8f5fc249..2b432ce86 100644
--- a/openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml
@@ -181,7 +181,7 @@
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="inout" prefix="pad" size="1"/>
       <!-- A spypad for the direction port of the I/O pad, which can be visible in the fpga_top -->
-      <port type="input" prefix="din" size="1" is_global="true" is_io="true" default_value="0"/>
+      <port type="input" prefix="din" size="1" is_global="true" io="true" default_value="0"/>
       <port type="output" prefix="dout" size="1" is_global="true"/>
       <port type="output" prefix="dir" size="1" is_global="true"/>
       <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>

From decc1dc4b25fa88a0bc69a88d9b9e32a61f8abcf Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 5 Apr 2020 17:39:30 -0600
Subject: [PATCH 374/645] debugged global gp input/output port support

---
 openfpga/src/fpga_sdc/analysis_sdc_writer.cpp   | 11 +++++++++++
 .../src/fpga_verilog/verilog_top_testbench.cpp  | 17 ++++++++++++++++-
 2 files changed, 27 insertions(+), 1 deletion(-)

diff --git a/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp b/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp
index aec9fc2e7..c188dedd8 100644
--- a/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp
+++ b/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp
@@ -192,6 +192,17 @@ void print_analysis_sdc_disable_global_ports(std::fstream& fp,
       continue;
     }
 
+    /* Skip any gpio port here! */
+    if ( (CIRCUIT_MODEL_PORT_INPUT == circuit_lib.port_type(global_port)) 
+      && (true == circuit_lib.port_is_io(global_port)) ) {
+      continue;
+    }
+
+    /* Skip any gpio port here! */
+    if (CIRCUIT_MODEL_PORT_OUTPUT == circuit_lib.port_type(global_port)) {
+      continue;
+    }
+
     ModulePortId module_port = module_manager.find_module_port(top_module, circuit_lib.port_prefix(global_port)); 
     BasicPort port_to_disable = module_manager.module_port(top_module, module_port);
 
diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
index 911c6defb..95f88bf92 100644
--- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
@@ -18,6 +18,7 @@
 
 #include "bitstream_manager_utils.h"
 
+#include "openfpga_reserved_words.h"
 #include "openfpga_naming.h"
 #include "simulation_utils.h"
 #include "openfpga_atom_netlist_utils.h"
@@ -272,9 +273,23 @@ void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp,
       continue;
     }
 
+    /* Bypass gp output signals, they do not need any drivers */
+    if (CIRCUIT_MODEL_PORT_OUTPUT == circuit_lib.port_type(model_global_port)) {
+      continue;
+    }
+
+    /* Find the port name, gpio port has special names */
+    std::string port_name;
+    if (true == circuit_lib.port_is_io(model_global_port)) {
+      port_name = generate_fpga_global_io_port_name(std::string(GIO_INOUT_PREFIX), circuit_lib, circuit_lib.port_parent_model(model_global_port), model_global_port);
+    } else {
+      VTR_ASSERT_SAFE(false == circuit_lib.port_is_io(model_global_port));
+      port_name = circuit_lib.port_prefix(model_global_port);
+    }
+
     /* Reach here, it means we have a port to deal with */
     /* Find the module port and wire it to constant values */
-    ModulePortId module_global_port = module_manager.find_module_port(top_module, circuit_lib.port_prefix(model_global_port));
+    ModulePortId module_global_port = module_manager.find_module_port(top_module, port_name);
     VTR_ASSERT(true == module_manager.valid_module_port_id(top_module, module_global_port));
 
     BasicPort module_port = module_manager.module_port(top_module, module_global_port);

From 3369d724e9c9a066cb870aef38735ed171d48b0b Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 5 Apr 2020 17:50:11 -0600
Subject: [PATCH 375/645] bug fixing in Verilog top-level testbench generation

---
 openfpga/src/fpga_verilog/verilog_top_testbench.cpp | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
index 95f88bf92..98d69c337 100644
--- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
@@ -353,6 +353,18 @@ void print_verilog_top_testbench_ports(std::fstream& fp,
   /* Add an empty line as a splitter */
   fp << std::endl;
 
+  for (const BasicPort& module_port : module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPIN_PORT)) {
+    fp << generate_verilog_port(VERILOG_PORT_WIRE, module_port) << ";" << std::endl;
+  }
+  /* Add an empty line as a splitter */
+  fp << std::endl;
+
+  for (const BasicPort& module_port : module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPOUT_PORT)) {
+    fp << generate_verilog_port(VERILOG_PORT_WIRE, module_port) << ";" << std::endl;
+  }
+  /* Add an empty line as a splitter */
+  fp << std::endl;
+
   /* Add local wires/registers that drive stimulus
    * We create these general purpose ports here,
    * and then wire them to the ports of FPGA fabric depending on their usage 

From 1a3a748dd2d6b8242f9a0a99e722577c9c815f0b Mon Sep 17 00:00:00 2001
From: Xifan Tang <tangxifan@gmail.com>
Date: Sun, 5 Apr 2020 20:12:28 -0600
Subject: [PATCH 376/645] update documentation with the support on spypads and
 global I/O ports

---
 docs/source/arch_lang/circuit_library.rst | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/docs/source/arch_lang/circuit_library.rst b/docs/source/arch_lang/circuit_library.rst
index 52d906fea..2cab83abd 100644
--- a/docs/source/arch_lang/circuit_library.rst
+++ b/docs/source/arch_lang/circuit_library.rst
@@ -270,11 +270,20 @@ A circuit model may consist of a number of ports. The port list is mandatory in
 
     .. note:: ``circuit_model_name`` is only valid when the type of this port is ``sram``.
 
+  - ``io="true|false"`` Specify if this port should be treated as an I/O port of an FPGA fabric. When this is enabled, this port of each circuit model instanciated in FPGA will be added as an I/O of an FPGA.
+
+    .. note:: ``io`` is only valid for ``input`` ports
+
   - ``mode_select="true|false"`` Specify if this port controls the mode switching in a configurable logic block. This is due to that a configurable logic block can operate in different modes, which is controlled by SRAM bits.
 
     .. note:: ``mode_select`` is only valid when the type of this port is ``sram``.
 
-  - ``is_global="true|false"`` can be either ``true`` or ``false``. Specify if this port is a global port, which will be routed globally. Note that when multiple global ports are defined with the same name, these global ports will be short-wired together.
+  - ``is_global="true|false"`` can be either ``true`` or ``false``. Specify if this port is a global port, which will be routed globally.
+
+    .. note:: For input ports, when multiple global input ports are defined with the same name, by default, these global ports will be short-wired together. When ``io`` is turned on for this port, these global ports will be independent in the FPGA fabric.
+
+    .. note:: For output ports, the global ports will be independent in the FPGA fabric 
+
 
   - ``is_set="true|false"`` Specify if this port controls a set signal. All the set ports are connected to global set voltage stimuli in testbenches.
 

From eb3b02277a6b382fe0dd182f39a200cf23dfcbd3 Mon Sep 17 00:00:00 2001
From: ganeshgore <goreganesh007@gmail.com>
Date: Mon, 6 Apr 2020 00:32:06 -0600
Subject: [PATCH 377/645] Added XML and benchmarks for testing

---
 .../arch/vpr_only_templates/k6_N10_40nm.xml   | 299 +++++++
 .../k6_N10_tileable_40nm.xml                  | 299 +++++++
 .../vpr_only_templates/k6_frac_N10_40nm.xml   | 441 ++++++++++
 .../k6_frac_N10_adder_chain_40nm.xml          | 639 ++++++++++++++
 .../k6_frac_N10_adder_chain_mem16K_40nm.xml   | 734 ++++++++++++++++
 .../k6_frac_N10_tileable_40nm.xml             | 441 ++++++++++
 .../k6_frac_N10_tileable_adder_chain_40nm.xml | 639 ++++++++++++++
 ...c_N10_tileable_adder_chain_mem16K_40nm.xml | 734 ++++++++++++++++
 ...0_tileable_adder_chain_mem16K_aib_40nm.xml | 800 ++++++++++++++++++
 ...er_chain_mem16K_multi_io_capacity_40nm.xml | 768 +++++++++++++++++
 ...ble_adder_chain_mem16K_reduced_io_40nm.xml | 737 ++++++++++++++++
 ..._tileable_adder_chain_wide_mem16K_40nm.xml | 734 ++++++++++++++++
 ...e_thru_channel_adder_chain_mem16K_40nm.xml | 734 ++++++++++++++++
 .../benchmarks/micro_benchmark/and.act        |   3 +
 .../benchmarks/micro_benchmark/and.blif       |   8 +
 .../benchmarks/micro_benchmark/and.v          |  14 +
 .../benchmarks/micro_benchmark/and_latch.act  |   6 +
 .../benchmarks/micro_benchmark/and_latch.blif |  14 +
 .../benchmarks/micro_benchmark/and_latch.v    |  23 +
 .../openfpga_arch/k6_N10_40nm_openfpga.xml    | 234 +++++
 .../k6_frac_N10_40nm_openfpga.xml             | 268 ++++++
 .../k6_frac_N10_adder_chain_40nm_openfpga.xml | 292 +++++++
 ...c_N10_adder_chain_mem16K_40nm_openfpga.xml | 310 +++++++
 ...0_adder_chain_mem16K_aib_40nm_openfpga.xml | 323 +++++++
 .../k6_frac_N10_spyio_40nm_openfpga.xml       | 270 ++++++
 25 files changed, 9764 insertions(+)
 create mode 100644 openfpga_flow/arch/vpr_only_templates/k6_N10_40nm.xml
 create mode 100644 openfpga_flow/arch/vpr_only_templates/k6_N10_tileable_40nm.xml
 create mode 100644 openfpga_flow/arch/vpr_only_templates/k6_frac_N10_40nm.xml
 create mode 100644 openfpga_flow/arch/vpr_only_templates/k6_frac_N10_adder_chain_40nm.xml
 create mode 100644 openfpga_flow/arch/vpr_only_templates/k6_frac_N10_adder_chain_mem16K_40nm.xml
 create mode 100644 openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
 create mode 100644 openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_40nm.xml
 create mode 100644 openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml
 create mode 100644 openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml
 create mode 100644 openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml
 create mode 100644 openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml
 create mode 100644 openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml
 create mode 100644 openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml
 create mode 100644 openfpga_flow/benchmarks/micro_benchmark/and.act
 create mode 100644 openfpga_flow/benchmarks/micro_benchmark/and.blif
 create mode 100644 openfpga_flow/benchmarks/micro_benchmark/and.v
 create mode 100644 openfpga_flow/benchmarks/micro_benchmark/and_latch.act
 create mode 100644 openfpga_flow/benchmarks/micro_benchmark/and_latch.blif
 create mode 100644 openfpga_flow/benchmarks/micro_benchmark/and_latch.v
 create mode 100644 openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml
 create mode 100644 openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
 create mode 100644 openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
 create mode 100644 openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
 create mode 100644 openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
 create mode 100644 openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml

diff --git a/openfpga_flow/arch/vpr_only_templates/k6_N10_40nm.xml b/openfpga_flow/arch/vpr_only_templates/k6_N10_40nm.xml
new file mode 100644
index 000000000..630011e84
--- /dev/null
+++ b/openfpga_flow/arch/vpr_only_templates/k6_N10_40nm.xml
@@ -0,0 +1,299 @@
+<!-- 
+  Architecture with no fracturable LUTs
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 6, N = 10
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Details on Modelling:
+
+  Based on flagship k6_frac_N10_mem32K_40nm.xml architecture.  This architecture has no fracturable LUTs nor any heterogeneous blocks.
+
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <tile name="io" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <clock name="clock" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad io.clock</loc>
+        <loc side="top">io.outpad io.inpad io.clock</loc>
+        <loc side="right">io.outpad io.inpad io.clock</loc>
+        <loc side="bottom">io.outpad io.inpad io.clock</loc>
+      </pinlocations>
+    </tile>
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I" num_pins="40" equivalent="full"/>
+      <output name="O" num_pins="10" equivalent="instance"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="spread"/>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout tileable="false">
+    <auto_layout aspect_ratio="1.0">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </auto_layout>
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	  -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+	       book area formula. This means the mux transistors are about 5x minimum drive strength.
+	       We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+	       mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+	       the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+	       by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+	       buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+	       I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+	       (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+	       The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+	       2.5x when looking up in Jeff's tables.
+	       Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+	       This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+			     With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+			     reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <clock name="clock" num_pins="1"/>
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" disabled_in_pack="true">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I" num_pins="40" equivalent="full"/>
+      <output name="O" num_pins="10" equivalent="instance"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe basic logic element.  
+             Each basic logic element has a 6-LUT that can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="10">
+        <input name="in" num_pins="6"/>
+        <output name="out" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- 6-LUT mode definition begin -->
+        <mode name="n1_lut6">
+          <!-- Define 6-LUT mode -->
+          <pb_type name="ble6" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Define LUT -->
+            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="6" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->
+              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                261e-12
+                261e-12
+                261e-12
+                261e-12
+                261e-12
+                261e-12
+              </delay_matrix>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+              <direct name="direct2" input="lut6.out" output="ff.D">
+                <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
+                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="ble6.in"/>
+            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+          </interconnect>
+        </mode>
+        <!-- 6-LUT mode definition end -->
+      </pb_type>
+      <interconnect>
+        <!-- We use a full crossbar to get logical equivalence at inputs of CLB 
+		     The delays below come from Stratix IV. the delay through a connection block
+		     input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+		     delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+		     delay within the crossbar is 95 ps. 
+		     The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+		     Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+		     25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+		     to get the part that should be marked on the crossbar.	 -->
+        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
+          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
+          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
+        </complete>
+        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+        </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+               By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+               then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+               naive specification).
+          -->
+        <direct name="clbouts1" input="fle[9:0].out" output="clb.O"/>
+      </interconnect>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- Place this general purpose logic block in any unspecified column -->
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+  </complexblocklist>
+</architecture>
diff --git a/openfpga_flow/arch/vpr_only_templates/k6_N10_tileable_40nm.xml b/openfpga_flow/arch/vpr_only_templates/k6_N10_tileable_40nm.xml
new file mode 100644
index 000000000..d86d7aa62
--- /dev/null
+++ b/openfpga_flow/arch/vpr_only_templates/k6_N10_tileable_40nm.xml
@@ -0,0 +1,299 @@
+<!-- 
+  Architecture with no fracturable LUTs
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 6, N = 10
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Details on Modelling:
+
+  Based on flagship k6_frac_N10_mem32K_40nm.xml architecture.  This architecture has no fracturable LUTs nor any heterogeneous blocks.
+
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <tile name="io" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <clock name="clock" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad io.clock</loc>
+        <loc side="top">io.outpad io.inpad io.clock</loc>
+        <loc side="right">io.outpad io.inpad io.clock</loc>
+        <loc side="bottom">io.outpad io.inpad io.clock</loc>
+      </pinlocations>
+    </tile>
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I" num_pins="40" equivalent="full"/>
+      <output name="O" num_pins="10" equivalent="instance"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="spread"/>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout tileable="true">
+    <auto_layout aspect_ratio="1.0">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </auto_layout>
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	  -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+	       book area formula. This means the mux transistors are about 5x minimum drive strength.
+	       We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+	       mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+	       the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+	       by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+	       buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+	       I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+	       (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+	       The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+	       2.5x when looking up in Jeff's tables.
+	       Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+	       This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+			     With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+			     reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <clock name="clock" num_pins="1"/>
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" disabled_in_pack="true">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I" num_pins="40" equivalent="full"/>
+      <output name="O" num_pins="10" equivalent="instance"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe basic logic element.  
+             Each basic logic element has a 6-LUT that can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="10">
+        <input name="in" num_pins="6"/>
+        <output name="out" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- 6-LUT mode definition begin -->
+        <mode name="n1_lut6">
+          <!-- Define 6-LUT mode -->
+          <pb_type name="ble6" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Define LUT -->
+            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="6" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->
+              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                261e-12
+                261e-12
+                261e-12
+                261e-12
+                261e-12
+                261e-12
+              </delay_matrix>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+              <direct name="direct2" input="lut6.out" output="ff.D">
+                <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
+                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="ble6.in"/>
+            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+          </interconnect>
+        </mode>
+        <!-- 6-LUT mode definition end -->
+      </pb_type>
+      <interconnect>
+        <!-- We use a full crossbar to get logical equivalence at inputs of CLB 
+		     The delays below come from Stratix IV. the delay through a connection block
+		     input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+		     delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+		     delay within the crossbar is 95 ps. 
+		     The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+		     Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+		     25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+		     to get the part that should be marked on the crossbar.	 -->
+        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
+          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
+          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
+        </complete>
+        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+        </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+               By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+               then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+               naive specification).
+          -->
+        <direct name="clbouts1" input="fle[9:0].out" output="clb.O"/>
+      </interconnect>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- Place this general purpose logic block in any unspecified column -->
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+  </complexblocklist>
+</architecture>
diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_40nm.xml b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_40nm.xml
new file mode 100644
index 000000000..aa9ca9d98
--- /dev/null
+++ b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_40nm.xml
@@ -0,0 +1,441 @@
+<!--
+  Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0.
+
+  - 40 nm technology
+  - General purpose logic block:
+    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with all 5 inputs shared)
+    with optionally registered outputs
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Details on Modelling:
+
+  Based on flagship k6_frac_N10_mem32K_40nm.xml architecture.
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!--
+       ODIN II specific config begins
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
+       already special structures in blif (.names, .input, .output, and .latch)
+       that describe them.
+  -->
+  <models>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="frac_lut6">
+      <input_ports>
+        <port name="in"/>
+      </input_ports>
+      <output_ports>
+        <port name="lut5_out"/>
+        <port name="lut6_out"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+         If you need to register the I/O, define clocks in the circuit models
+         These clocks can be handled in back-end
+     -->
+    <tile name="io" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad</loc>
+        <loc side="top">io.outpad io.inpad</loc>
+        <loc side="right">io.outpad io.inpad</loc>
+        <loc side="bottom">io.outpad io.inpad</loc>
+      </pinlocations>
+    </tile>
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I" num_pins="40" equivalent="full"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="spread"/>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout tileable="false">
+    <!--auto_layout aspect_ratio="1.0"-->
+    <fixed_layout name="2x2" width="4" height="4">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </fixed_layout>
+    <!-- /auto_layout -->
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV.
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	  -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3" sub_type="subset" sub_fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+	       book area formula. This means the mux transistors are about 5x minimum drive strength.
+	       We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
+	       mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+	       the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+	       by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified
+	       buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+	       I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout
+	       (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+	       The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
+	       2.5x when looking up in Jeff's tables.
+	       Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+	       This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
+			     With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+			     reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+           If you need to register the I/O, define clocks in the circuit models
+           These clocks can be handled in back-end
+       -->
+      <!-- A mode denotes the physical implementation of an I/O
+           This mode will be not packable but is mainly used for fabric verilog generation
+        -->
+      <mode name="physical" disabled_in_pack="true">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency,
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range.
+	   -->
+    <pb_type name="clb">
+      <input name="I" num_pins="40" equivalent="full"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe fracturable logic element.
+             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs.
+             The outputs of the fracturable logic element can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="10">
+        <input name="in" num_pins="6"/>
+        <output name="out" num_pins="2"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- Physical mode definition begin (physical implementation of the fle) -->
+        <mode name="physical" disabled_in_pack="true">
+          <pb_type name="fabric" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="2"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="frac_logic" num_pb="1">
+              <input name="in" num_pins="6"/>
+              <output name="out" num_pins="2"/>
+              <!-- Define LUT -->
+              <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
+                <input name="in" num_pins="6"/>
+                <output name="lut5_out" num_pins="2"/>
+                <output name="lut6_out" num_pins="1"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
+                <direct name="direct2" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
+                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
+                <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
+              </interconnect>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
+              <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
+              <complete name="direct3" input="fabric.clk" output="ff[1:0].clk"/>
+              <mux name="mux1" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
+                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
+              </mux>
+              <mux name="mux2" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
+                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="fabric.in"/>
+            <direct name="direct2" input="fabric.out" output="fle.out"/>
+            <direct name="direct3" input="fle.clk" output="fabric.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Physical mode definition end (physical implementation of the fle) -->
+        <!-- Dual 5-LUT mode definition begin -->
+        <mode name="n2_lut5">
+          <pb_type name="lut5inter" num_pb="1">
+            <input name="in" num_pins="5"/>
+            <output name="out" num_pins="2"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="ble5" num_pb="2">
+              <input name="in" num_pins="5"/>
+              <output name="out" num_pins="1"/>
+              <clock name="clk" num_pins="1"/>
+              <!-- Define the LUT -->
+              <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
+                <input name="in" num_pins="5" port_class="lut_in"/>
+                <output name="out" num_pins="1" port_class="lut_out"/>
+                <!-- LUT timing using delay matrix -->
+                <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                           we instead take the average of these numbers to get more stable results
+                      82e-12
+                      173e-12
+                      261e-12
+                      263e-12
+                      398e-12
+                      -->
+                <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
+                  235e-12
+                  235e-12
+                  235e-12
+                  235e-12
+                  235e-12
+                </delay_matrix>
+              </pb_type>
+              <!-- Define the flip-flop -->
+              <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+                <input name="D" num_pins="1" port_class="D"/>
+                <output name="Q" num_pins="1" port_class="Q"/>
+                <clock name="clk" num_pins="1" port_class="clock"/>
+                <T_setup value="66e-12" port="ff.D" clock="clk"/>
+                <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="ble5.in[4:0]" output="lut5[0:0].in[4:0]"/>
+                <direct name="direct2" input="lut5[0:0].out" output="ff[0:0].D">
+                  <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
+                  <pack_pattern name="ble5" in_port="lut5[0:0].out" out_port="ff[0:0].D"/>
+                </direct>
+                <direct name="direct3" input="ble5.clk" output="ff[0:0].clk"/>
+                <mux name="mux1" input="ff[0:0].Q lut5.out[0:0]" output="ble5.out[0:0]">
+                  <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                  <delay_constant max="25e-12" in_port="lut5.out[0:0]" out_port="ble5.out[0:0]"/>
+                  <delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble5.out[0:0]"/>
+                </mux>
+              </interconnect>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="lut5inter.in" output="ble5[0:0].in"/>
+              <direct name="direct2" input="lut5inter.in" output="ble5[1:1].in"/>
+              <direct name="direct3" input="ble5[1:0].out" output="lut5inter.out"/>
+              <complete name="complete1" input="lut5inter.clk" output="ble5[1:0].clk"/>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[4:0]" output="lut5inter.in"/>
+            <direct name="direct2" input="lut5inter.out" output="fle.out"/>
+            <direct name="direct3" input="fle.clk" output="lut5inter.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Dual 5-LUT mode definition end -->
+        <!-- 6-LUT mode definition begin -->
+        <mode name="n1_lut6">
+          <!-- Define 6-LUT mode -->
+          <pb_type name="ble6" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Define LUT -->
+            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="6" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->
+              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                261e-12
+                261e-12
+                261e-12
+                261e-12
+                261e-12
+                261e-12
+              </delay_matrix>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+              <direct name="direct2" input="lut6.out" output="ff.D">
+                <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
+                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="ble6.in"/>
+            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+          </interconnect>
+        </mode>
+        <!-- 6-LUT mode definition end -->
+      </pb_type>
+      <interconnect>
+        <!-- We use a full crossbar to get logical equivalence at inputs of CLB
+		     The delays below come from Stratix IV. the delay through a connection block
+		     input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps
+		     delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+		     delay within the crossbar is 95 ps.
+		     The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+		     Since all our outputs LUT outputs go to a BLE output, and have a delay of
+		     25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+		     to get the part that should be marked on the crossbar.	 -->
+        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
+          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
+          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
+        </complete>
+        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+        </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
+               By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
+               then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+               naive specification).
+          -->
+        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
+        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
+      </interconnect>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- Place this general purpose logic block in any unspecified column -->
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+  </complexblocklist>
+</architecture>
diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_adder_chain_40nm.xml b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_adder_chain_40nm.xml
new file mode 100644
index 000000000..bbe041562
--- /dev/null
+++ b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_adder_chain_40nm.xml
@@ -0,0 +1,639 @@
+<!-- 
+  Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with 8 total FLE inputs (2 inputs of which are shared by the 5-LUTs) 
+    with optionally registered outputs
+    Each 5-LUT has an arithemtic mode that converts it to a single-bit adder with both inputs driven by 4-LUTs (both 4-LUTs share all 4 inputs)
+    Carry chain links to vertically adjacent logic blocks
+  - Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.  
+    Height = 6, found on every (8n+2)th column
+  - Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.  
+    Height = 4, found on every (8n+6)th column
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Details on Modelling:
+
+  The electrical design of the architecture described here is NOT from an 
+  optimized, SPICED architecture.  Instead, we attempt to create a reasonable 
+  architecture file by using an existing commercial FPGA to approximate the area, 
+  delay, and power of the underlying components. This is combined with a reasonable 40 nm 
+  model of wiring and circuit design for low-level routing components, where available.
+  The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also 
+  has wiring electrical parameters that allow the wire lengths and switch patterns to be 
+  modified and you will still get reasonable delay results for the new architecture.
+  The following describes, in detail, how we obtained the various electrical values for this 
+  architecture.
+
+  Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar 
+  architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture. 
+  (n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)      
+  This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to 
+  match the overall target (a 40 nm FPGA).
+
+  We obtain delay numbers by measuring delays of routing, soft logic blocks, 
+  memories, and multipliers from test circuits on a Stratix IV GX device 
+  (EP4SGX230DF29C2X, i.e. fastest speed grade). For routing, we took the average delay of H4 and V4 
+  wires.  Rmetal and Cmetal values for the routing wires were obtained from work done by Charles 
+  Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal stack 40 nm routing) and 
+  take the R and C data from the ITRS roadmap.  
+
+  For the general purpose logic block, we assume that the area and delays of the Stratix IV 
+  crossbar is close enough to the crossbar modelled here.  
+  Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to 
+  36:1 multiplexers.  We match these parameters in this architecture.
+
+  For LUTs, we include LUT 
+  delays measured from Stratix IV which is dependant on the input used (ie. some 
+  LUT inputs are faster than others).  The CAD tools at the time of VTR 7 does 
+  not consider differences in LUT input delays.
+
+  Adder delays obtained as approximate values from a Stratix IV EP4SE230F29C3 device.  
+  Delay obtained by compiling a 256 bit adder (registered inputs and outputs, 
+  all pins except clock virtual) then measuring the delays in chip-planner, 
+  sumout delay = 0.271ns to 0.348 ns, intra-block carry delay = 0.011 ns, 
+  inter-block carry delay = 0.327 ns.  Given this data, I will approximate 
+  sumout 0.3 ns, intra-block carry-delay = 0.01 ns, and 
+  inter-block carry-delay = 0.16 ns (since Altera inter-block carry delay has 
+  overhead that we don't have, I'll approximate the delay of a simpler chain at 
+  one half what they have.  This is very rough, anything from 0.01ns to 0.327ns 
+  can be justified).
+
+  Logic block area numbers obtained by scaling overall tile area of a 65nm 
+  Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out 
+  routing area at a channel width of 300. We use a channel width of 300 because it can route 
+  all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
+  total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
+  choosing a width that provides high routability. The architecture can be routed at different channel
+  widths, but we estimate the tile size and hence the physical length of routing wires assuming
+  a channel width of 300.
+
+  Sanity checks employed:
+    1.  We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches 
+        common electrical design.
+
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <model name="adder">
+      <input_ports>
+        <port name="a" combinational_sink_ports="sumout cout"/>
+        <port name="b" combinational_sink_ports="sumout cout"/>
+        <port name="cin" combinational_sink_ports="sumout cout"/>
+      </input_ports>
+      <output_ports>
+        <port name="cout"/>
+        <port name="sumout"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="frac_lut6">
+      <input_ports>
+        <port name="in"/>
+      </input_ports>
+      <output_ports>
+        <port name="lut4_out"/>
+        <port name="lut5_out"/>
+        <port name="lut6_out"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <tile name="io" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad</loc>
+        <loc side="top">io.outpad io.inpad</loc>
+        <loc side="right">io.outpad io.inpad</loc>
+        <loc side="bottom">io.outpad io.inpad</loc>
+      </pinlocations>
+    </tile>
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
+      </fc>
+      <!--  Highly recommand to customize pin location when direct connection is used!!! -->
+      <!--pinlocations pattern="spread"/-->
+      <pinlocations pattern="custom">
+        <loc side="left">clb.clk</loc>
+        <loc side="top">clb.cin</loc>
+        <loc side="right">clb.O[9:0] clb.I[19:0]</loc>
+        <loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
+      </pinlocations>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout tileable="false">
+    <!--auto_layout aspect_ratio="1.0"-->
+    <fixed_layout name="4x4" width="6" height="6">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </fixed_layout>
+    <!-- /auto_layout -->
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	    -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+           book area formula. This means the mux transistors are about 5x minimum drive strength.
+           We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+           mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+           the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+           by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+           buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+           I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+           (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+           The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+           2.5x when looking up in Jeff's tables.
+           Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+           This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+             With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+             reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <directlist>
+    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
+  </directlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+
+      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+           If you need to register the I/O, define clocks in the circuit models
+           These clocks can be handled in back-end
+       -->
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" disabled_in_pack="true">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe fracturable logic element.  
+             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
+             The outputs of the fracturable logic element can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="10">
+        <input name="in" num_pins="6"/>
+        <input name="cin" num_pins="1"/>
+        <output name="out" num_pins="2"/>
+        <output name="cout" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- Physical mode definition begin (physical implementation of the fle) -->
+        <mode name="physical" disabled_in_pack="true">
+          <pb_type name="fabric" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="frac_logic" num_pb="1">
+              <input name="in" num_pins="6"/>
+              <output name="lut4_out" num_pins="4"/>
+              <output name="out" num_pins="2"/>
+              <!-- Define LUT -->
+              <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
+                <input name="in" num_pins="6"/>
+                <output name="lut4_out" num_pins="4"/>
+                <output name="lut5_out" num_pins="2"/>
+                <output name="lut6_out" num_pins="1"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
+                <direct name="direct2" input="frac_lut6.lut4_out" output="frac_logic.lut4_out"/>
+                <direct name="direct3" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
+                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
+                <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
+              </interconnect>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>         
+            <!-- Define adders -->
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="2">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
+              <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
+              <direct name="direct3" input="fabric.cin" output="adder[0:0].cin"/>
+              <direct name="direct4" input="adder[0:0].cout" output="adder[1:1].cin"/>
+              <direct name="direct5" input="adder[1:1].cout" output="fabric.cout"/>
+              <direct name="direct6" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
+              <direct name="direct7" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
+              <direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
+              <direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
+              <complete name="direct10" input="fabric.clk" output="ff[1:0].clk"/>
+              <mux name="mux1" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
+                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
+              </mux>
+              <mux name="mux2" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
+                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="fabric.in"/>
+            <direct name="direct2" input="fle.cin" output="fabric.cin"/>
+            <direct name="direct3" input="fabric.out" output="fle.out"/>
+            <direct name="direct4" input="fabric.cout" output="fle.cout"/>
+            <direct name="direct5" input="fle.clk" output="fabric.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Physical mode definition end (physical implementation of the fle) -->
+        <!-- BEGIN fle mode of dual lut5 -->
+        <mode name="n2_lut5">
+          <pb_type name="ble5" num_pb="2">
+            <input name="in" num_pins="5"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Regular LUT mode -->
+            <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="5" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                  we instead take the average of these numbers to get more stable results
+                82e-12
+                173e-12
+                261e-12
+                263e-12
+                398e-12
+                -->
+              <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+              </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble5.in" output="lut5.in"/>
+              <direct name="direct2" input="lut5.out" output="ff.D">
+                <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble5.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut5.out" output="ble5.out">
+                <delay_constant max="25e-12" in_port="lut5.out" out_port="ble5.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble5.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[4:0]" output="ble5[0:0].in"/>
+            <direct name="direct2" input="fle.in[4:0]" output="ble5[1:1].in"/>
+            <complete name="direct3" input="fle.clk" output="ble5.clk"/>
+            <direct name="direct4" input="ble5.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- END fle mode of dual lut5 -->
+        <!-- BEGIN arithmetic mode of dual lut4 + adders -->
+        <mode name="arithmetic">
+          <pb_type name="arithmetic" num_pb="2">
+            <input name="in" num_pins="4"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="1"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Special dual-LUT mode that drives adder only -->
+            <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
+              <input name="in" num_pins="4" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  -->
+              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                  195e-12
+                  195e-12
+                  195e-12
+                  195e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
+              <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
+              <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
+              <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
+                </direct>
+              <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
+                </direct>
+              <direct name="add_to_ff" input="adder.sumout" output="ff.D">
+                <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
+              </direct>
+              <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
+                <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
+              </direct>
+              <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
+                <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
+              </direct>
+              <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
+                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[3:0]" output="arithmetic[0:0].in"/>
+            <direct name="direct2" input="fle.in[3:0]" output="arithmetic[1:1].in"/>
+            <direct name="carry_in" input="fle.cin" output="arithmetic[0:0].cin">
+              <pack_pattern name="chain" in_port="fle.cin" out_port="arithmetic[0:0].cin"/>
+            </direct>
+            <direct name="carry_inter" input="arithmetic[0:0].cout" output="arithmetic[1:1].cin">
+              <pack_pattern name="chain" in_port="arithmetic[0:0].cout" out_port="arithmetic[1:1].cin"/>
+            </direct>
+            <direct name="carry_out" input="arithmetic[1:1].cout" output="fle.cout">
+              <pack_pattern name="chain" in_port="arithmetic.cout" out_port="fle.cout"/>
+            </direct>
+            <complete name="direct3" input="fle.clk" output="arithmetic.clk"/>
+            <direct name="direct4" input="arithmetic.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- n2_lut5 -->
+        <mode name="n1_lut6">
+          <pb_type name="ble6" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="6" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->
+              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+              <direct name="direct2" input="lut6.out" output="ff.D">
+                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
+            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+          </interconnect>
+        </mode>
+        <!-- n1_lut6 -->
+      </pb_type>
+      <interconnect>
+        <!-- We use a 50% depop crossbar built using small full xbars to get sets of logically equivalent pins at inputs of CLB 
+           The delays below come from Stratix IV. the delay through a connection block
+           input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+           delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+           delay within the crossbar is 95 ps. 
+           The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+           Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+           25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+           to get the part that should be marked on the crossbar.	 -->
+        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
+          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
+          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
+        </complete>
+
+        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+        </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+                 By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+                 then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+                 naive specification).
+          -->
+        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
+        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
+        <!-- Carry chain links -->
+        <direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
+          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
+        </direct>
+        <direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
+          <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
+        </direct>
+        <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
+          <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
+        </direct>
+      </interconnect>
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+  </complexblocklist>
+</architecture>
diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_adder_chain_mem16K_40nm.xml b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_adder_chain_mem16K_40nm.xml
new file mode 100644
index 000000000..850eb5450
--- /dev/null
+++ b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_adder_chain_mem16K_40nm.xml
@@ -0,0 +1,734 @@
+<!-- 
+  Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with 8 total FLE inputs (2 inputs of which are shared by the 5-LUTs) 
+    with optionally registered outputs
+    Each 5-LUT has an arithemtic mode that converts it to a single-bit adder with both inputs driven by 4-LUTs (both 4-LUTs share all 4 inputs)
+    Carry chain links to vertically adjacent logic blocks
+  - Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.  
+    Height = 6, found on every (8n+2)th column
+  - Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.  
+    Height = 4, found on every (8n+6)th column
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Details on Modelling:
+
+  The electrical design of the architecture described here is NOT from an 
+  optimized, SPICED architecture.  Instead, we attempt to create a reasonable 
+  architecture file by using an existing commercial FPGA to approximate the area, 
+  delay, and power of the underlying components. This is combined with a reasonable 40 nm 
+  model of wiring and circuit design for low-level routing components, where available.
+  The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also 
+  has wiring electrical parameters that allow the wire lengths and switch patterns to be 
+  modified and you will still get reasonable delay results for the new architecture.
+  The following describes, in detail, how we obtained the various electrical values for this 
+  architecture.
+
+  Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar 
+  architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture. 
+  (n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)      
+  This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to 
+  match the overall target (a 40 nm FPGA).
+
+  We obtain delay numbers by measuring delays of routing, soft logic blocks, 
+  memories, and multipliers from test circuits on a Stratix IV GX device 
+  (EP4SGX230DF29C2X, i.e. fastest speed grade). For routing, we took the average delay of H4 and V4 
+  wires.  Rmetal and Cmetal values for the routing wires were obtained from work done by Charles 
+  Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal stack 40 nm routing) and 
+  take the R and C data from the ITRS roadmap.  
+
+  For the general purpose logic block, we assume that the area and delays of the Stratix IV 
+  crossbar is close enough to the crossbar modelled here.  
+  Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to 
+  36:1 multiplexers.  We match these parameters in this architecture.
+
+  For LUTs, we include LUT 
+  delays measured from Stratix IV which is dependant on the input used (ie. some 
+  LUT inputs are faster than others).  The CAD tools at the time of VTR 7 does 
+  not consider differences in LUT input delays.
+
+  Adder delays obtained as approximate values from a Stratix IV EP4SE230F29C3 device.  
+  Delay obtained by compiling a 256 bit adder (registered inputs and outputs, 
+  all pins except clock virtual) then measuring the delays in chip-planner, 
+  sumout delay = 0.271ns to 0.348 ns, intra-block carry delay = 0.011 ns, 
+  inter-block carry delay = 0.327 ns.  Given this data, I will approximate 
+  sumout 0.3 ns, intra-block carry-delay = 0.01 ns, and 
+  inter-block carry-delay = 0.16 ns (since Altera inter-block carry delay has 
+  overhead that we don't have, I'll approximate the delay of a simpler chain at 
+  one half what they have.  This is very rough, anything from 0.01ns to 0.327ns 
+  can be justified).
+
+  Logic block area numbers obtained by scaling overall tile area of a 65nm 
+  Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out 
+  routing area at a channel width of 300. We use a channel width of 300 because it can route 
+  all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
+  total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
+  choosing a width that provides high routability. The architecture can be routed at different channel
+  widths, but we estimate the tile size and hence the physical length of routing wires assuming
+  a channel width of 300.
+
+  Sanity checks employed:
+    1.  We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches 
+        common electrical design.
+
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <model name="adder">
+      <input_ports>
+        <port name="a" combinational_sink_ports="sumout cout"/>
+        <port name="b" combinational_sink_ports="sumout cout"/>
+        <port name="cin" combinational_sink_ports="sumout cout"/>
+      </input_ports>
+      <output_ports>
+        <port name="cout"/>
+        <port name="sumout"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="frac_lut6">
+      <input_ports>
+        <port name="in"/>
+      </input_ports>
+      <output_ports>
+        <port name="lut4_out"/>
+        <port name="lut5_out"/>
+        <port name="lut6_out"/>
+      </output_ports>
+    </model>
+    <model name="dual_port_ram">
+      <input_ports>
+        <!-- write address lines -->
+        <port name="waddr" clock="clk"/>
+        <!-- read address lines -->
+        <port name="raddr" clock="clk"/>
+        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
+        <port name="d_in" clock="clk"/>
+        <!-- write enable -->
+        <port name="wen" clock="clk"/>
+        <!-- read enable -->
+        <port name="ren" clock="clk"/>
+        <!-- memories are often clocked -->
+        <port name="clk" is_clock="1"/>
+      </input_ports>
+      <output_ports>
+        <!-- output can be broken down into smaller bit widths minimum size 1 -->
+        <port name="d_out" clock="clk"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <tile name="io" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad</loc>
+        <loc side="top">io.outpad io.inpad</loc>
+        <loc side="right">io.outpad io.inpad</loc>
+        <loc side="bottom">io.outpad io.inpad</loc>
+      </pinlocations>
+    </tile>
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
+      </fc>
+      <!--  Highly recommand to customize pin location when direct connection is used!!! -->
+      <!--pinlocations pattern="spread"/-->
+      <pinlocations pattern="custom">
+        <loc side="left">clb.clk</loc>
+        <loc side="top">clb.cin</loc>
+        <loc side="right">clb.O[9:0] clb.I[19:0]</loc>
+        <loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
+      </pinlocations>
+    </tile>
+    <tile name="memory" height="2" area="548000">
+      <equivalent_sites>
+        <site pb_type="memory"/>
+      </equivalent_sites>
+      <input name="waddr" num_pins="10"/>
+      <input name="raddr" num_pins="10"/>
+      <input name="d_in" num_pins="32"/>
+      <input name="wen" num_pins="1"/>
+      <input name="ren" num_pins="1"/>
+      <output name="d_out" num_pins="32"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="spread"/>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout tileable="false">
+    <!--auto_layout aspect_ratio="1.0"-->
+    <fixed_layout name="4x4" width="5" height="4">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
+      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
+    </fixed_layout>
+    <!-- /auto_layout -->
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	    -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+           book area formula. This means the mux transistors are about 5x minimum drive strength.
+           We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+           mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+           the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+           by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+           buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+           I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+           (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+           The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+           2.5x when looking up in Jeff's tables.
+           Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+           This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+             With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+             reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <directlist>
+    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
+  </directlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+
+      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+           If you need to register the I/O, define clocks in the circuit models
+           These clocks can be handled in back-end
+       -->
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" disabled_in_pack="true">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe fracturable logic element.  
+             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
+             The outputs of the fracturable logic element can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="10">
+        <input name="in" num_pins="6"/>
+        <input name="cin" num_pins="1"/>
+        <output name="out" num_pins="2"/>
+        <output name="cout" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- Physical mode definition begin (physical implementation of the fle) -->
+        <mode name="physical" disabled_in_pack="true">
+          <pb_type name="fabric" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="frac_logic" num_pb="1">
+              <input name="in" num_pins="6"/>
+              <output name="lut4_out" num_pins="4"/>
+              <output name="out" num_pins="2"/>
+              <!-- Define LUT -->
+              <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
+                <input name="in" num_pins="6"/>
+                <output name="lut4_out" num_pins="4"/>
+                <output name="lut5_out" num_pins="2"/>
+                <output name="lut6_out" num_pins="1"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
+                <direct name="direct2" input="frac_lut6.lut4_out" output="frac_logic.lut4_out"/>
+                <direct name="direct3" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
+                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
+                <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
+              </interconnect>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>         
+            <!-- Define adders -->
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="2">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
+              <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
+              <direct name="direct3" input="fabric.cin" output="adder[0:0].cin"/>
+              <direct name="direct4" input="adder[0:0].cout" output="adder[1:1].cin"/>
+              <direct name="direct5" input="adder[1:1].cout" output="fabric.cout"/>
+              <direct name="direct6" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
+              <direct name="direct7" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
+              <direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
+              <direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
+              <complete name="direct10" input="fabric.clk" output="ff[1:0].clk"/>
+              <mux name="mux1" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
+                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
+              </mux>
+              <mux name="mux2" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
+                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="fabric.in"/>
+            <direct name="direct2" input="fle.cin" output="fabric.cin"/>
+            <direct name="direct3" input="fabric.out" output="fle.out"/>
+            <direct name="direct4" input="fabric.cout" output="fle.cout"/>
+            <direct name="direct5" input="fle.clk" output="fabric.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Physical mode definition end (physical implementation of the fle) -->
+        <!-- BEGIN fle mode of dual lut5 -->
+        <mode name="n2_lut5">
+          <pb_type name="ble5" num_pb="2">
+            <input name="in" num_pins="5"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Regular LUT mode -->
+            <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="5" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                  we instead take the average of these numbers to get more stable results
+                82e-12
+                173e-12
+                261e-12
+                263e-12
+                398e-12
+                -->
+              <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+              </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble5.in" output="lut5.in"/>
+              <direct name="direct2" input="lut5.out" output="ff.D">
+                <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble5.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut5.out" output="ble5.out">
+                <delay_constant max="25e-12" in_port="lut5.out" out_port="ble5.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble5.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[4:0]" output="ble5[0:0].in"/>
+            <direct name="direct2" input="fle.in[4:0]" output="ble5[1:1].in"/>
+            <complete name="direct3" input="fle.clk" output="ble5.clk"/>
+            <direct name="direct4" input="ble5.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- END fle mode of dual lut5 -->
+        <!-- BEGIN arithmetic mode of dual lut4 + adders -->
+        <mode name="arithmetic">
+          <pb_type name="arithmetic" num_pb="2">
+            <input name="in" num_pins="4"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="1"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Special dual-LUT mode that drives adder only -->
+            <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
+              <input name="in" num_pins="4" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  -->
+              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                  195e-12
+                  195e-12
+                  195e-12
+                  195e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
+              <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
+              <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
+              <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
+                </direct>
+              <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
+                </direct>
+              <direct name="add_to_ff" input="adder.sumout" output="ff.D">
+                <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
+              </direct>
+              <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
+                <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
+              </direct>
+              <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
+                <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
+              </direct>
+              <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
+                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[3:0]" output="arithmetic[0:0].in"/>
+            <direct name="direct2" input="fle.in[3:0]" output="arithmetic[1:1].in"/>
+            <direct name="carry_in" input="fle.cin" output="arithmetic[0:0].cin">
+              <pack_pattern name="chain" in_port="fle.cin" out_port="arithmetic[0:0].cin"/>
+            </direct>
+            <direct name="carry_inter" input="arithmetic[0:0].cout" output="arithmetic[1:1].cin">
+              <pack_pattern name="chain" in_port="arithmetic[0:0].cout" out_port="arithmetic[1:1].cin"/>
+            </direct>
+            <direct name="carry_out" input="arithmetic[1:1].cout" output="fle.cout">
+              <pack_pattern name="chain" in_port="arithmetic.cout" out_port="fle.cout"/>
+            </direct>
+            <complete name="direct3" input="fle.clk" output="arithmetic.clk"/>
+            <direct name="direct4" input="arithmetic.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- n2_lut5 -->
+        <mode name="n1_lut6">
+          <pb_type name="ble6" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="6" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->
+              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+              <direct name="direct2" input="lut6.out" output="ff.D">
+                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
+            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+          </interconnect>
+        </mode>
+        <!-- n1_lut6 -->
+      </pb_type>
+      <interconnect>
+        <!-- We use a 50% depop crossbar built using small full xbars to get sets of logically equivalent pins at inputs of CLB 
+           The delays below come from Stratix IV. the delay through a connection block
+           input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+           delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+           delay within the crossbar is 95 ps. 
+           The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+           Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+           25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+           to get the part that should be marked on the crossbar.	 -->
+        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
+          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
+          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
+        </complete>
+
+        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+        </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+                 By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+                 then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+                 naive specification).
+          -->
+        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
+        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
+        <!-- Carry chain links -->
+        <direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
+          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
+        </direct>
+        <direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
+          <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
+        </direct>
+        <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
+          <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
+        </direct>
+      </interconnect>
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+    <!-- Define single-mode dual-port memory begin -->
+    <pb_type name="memory">
+      <input name="waddr" num_pins="10"/>
+      <input name="raddr" num_pins="10"/>
+      <input name="d_in" num_pins="32"/>
+      <input name="wen" num_pins="1"/>
+      <input name="ren" num_pins="1"/>
+      <output name="d_out" num_pins="32"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Specify the 512x32=16Kbit memory block
+           Note: the delay numbers are extracted from VPR flagship XML without modification
+                 Should align to the process technology we using to create the 16K dual-port RAM
+        -->
+      <mode name="mem_512x32_dp">
+        <pb_type name="mem_512x32_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
+          <input name="waddr" num_pins="10" port_class="address"/>
+          <input name="raddr" num_pins="10" port_class="address"/>
+          <input name="d_in" num_pins="32" port_class="data_in"/>
+          <input name="wen" num_pins="1" port_class="write_en"/>
+          <input name="ren" num_pins="1" port_class="write_en"/>
+          <output name="d_out" num_pins="32" port_class="data_out"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.waddr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.raddr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.d_in" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.wen" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.ren" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_512x32_dp.d_out" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="17.9e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="waddress" input="memory.waddr" output="mem_512x32_dp.waddr">
+            <delay_constant max="132e-12" in_port="memory.waddr" out_port="mem_512x32_dp.waddr"/>
+          </direct>
+          <direct name="raddress" input="memory.raddr" output="mem_512x32_dp.raddr">
+            <delay_constant max="132e-12" in_port="memory.raddr" out_port="mem_512x32_dp.raddr"/>
+          </direct>
+          <direct name="data_input" input="memory.d_in" output="mem_512x32_dp.d_in">
+            <delay_constant max="132e-12" in_port="memory.d_in" out_port="mem_512x32_dp.d_in"/>
+          </direct>
+          <direct name="writeen" input="memory.wen" output="mem_512x32_dp.wen">
+            <delay_constant max="132e-12" in_port="memory.wen" out_port="mem_512x32_dp.wen"/>
+          </direct>
+          <direct name="readen" input="memory.ren" output="mem_512x32_dp.ren">
+            <delay_constant max="132e-12" in_port="memory.ren" out_port="mem_512x32_dp.ren"/>
+          </direct>
+          <direct name="dataout" input="mem_512x32_dp.d_out" output="memory.d_out">
+            <delay_constant max="40e-12" in_port="mem_512x32_dp.d_out" out_port="memory.d_out"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_512x32_dp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+    </pb_type>
+    <!-- Define single-mode dual-port memory end -->
+  </complexblocklist>
+</architecture>
diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
new file mode 100644
index 000000000..2c528c13c
--- /dev/null
+++ b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
@@ -0,0 +1,441 @@
+<!-- 
+  Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0.
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with all 5 inputs shared) 
+    with optionally registered outputs
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Details on Modelling:
+
+  Based on flagship k6_frac_N10_mem32K_40nm.xml architecture.
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="frac_lut6">
+      <input_ports>
+        <port name="in"/>
+      </input_ports>
+      <output_ports>
+        <port name="lut5_out"/>
+        <port name="lut6_out"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+         If you need to register the I/O, define clocks in the circuit models
+         These clocks can be handled in back-end
+     -->
+    <tile name="io" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad</loc>
+        <loc side="top">io.outpad io.inpad</loc>
+        <loc side="right">io.outpad io.inpad</loc>
+        <loc side="bottom">io.outpad io.inpad</loc>
+      </pinlocations>
+    </tile>
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I" num_pins="40" equivalent="full"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="spread"/>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout tileable="true">
+    <!--auto_layout aspect_ratio="1.0"-->
+    <fixed_layout name="2x2" width="4" height="4">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </fixed_layout>
+    <!-- /auto_layout -->
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	  -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3" sub_type="subset" sub_fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+	       book area formula. This means the mux transistors are about 5x minimum drive strength.
+	       We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+	       mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+	       the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+	       by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+	       buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+	       I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+	       (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+	       The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+	       2.5x when looking up in Jeff's tables.
+	       Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+	       This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+			     With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+			     reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+           If you need to register the I/O, define clocks in the circuit models
+           These clocks can be handled in back-end
+       -->
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" disabled_in_pack="true">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I" num_pins="40" equivalent="full"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe fracturable logic element.  
+             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
+             The outputs of the fracturable logic element can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="10">
+        <input name="in" num_pins="6"/>
+        <output name="out" num_pins="2"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- Physical mode definition begin (physical implementation of the fle) -->
+        <mode name="physical" disabled_in_pack="true">
+          <pb_type name="fabric" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="2"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="frac_logic" num_pb="1">
+              <input name="in" num_pins="6"/>
+              <output name="out" num_pins="2"/>
+              <!-- Define LUT -->
+              <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
+                <input name="in" num_pins="6"/>
+                <output name="lut5_out" num_pins="2"/>
+                <output name="lut6_out" num_pins="1"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
+                <direct name="direct2" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
+                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
+                <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
+              </interconnect>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
+              <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
+              <complete name="direct3" input="fabric.clk" output="ff[1:0].clk"/>
+              <mux name="mux1" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
+                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
+              </mux>
+              <mux name="mux2" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
+                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="fabric.in"/>
+            <direct name="direct2" input="fabric.out" output="fle.out"/>
+            <direct name="direct3" input="fle.clk" output="fabric.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Physical mode definition end (physical implementation of the fle) -->
+        <!-- Dual 5-LUT mode definition begin -->
+        <mode name="n2_lut5">
+          <pb_type name="lut5inter" num_pb="1">
+            <input name="in" num_pins="5"/>
+            <output name="out" num_pins="2"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="ble5" num_pb="2">
+              <input name="in" num_pins="5"/>
+              <output name="out" num_pins="1"/>
+              <clock name="clk" num_pins="1"/>
+              <!-- Define the LUT -->
+              <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
+                <input name="in" num_pins="5" port_class="lut_in"/>
+                <output name="out" num_pins="1" port_class="lut_out"/>
+                <!-- LUT timing using delay matrix -->
+                <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                           we instead take the average of these numbers to get more stable results
+                      82e-12
+                      173e-12
+                      261e-12
+                      263e-12
+                      398e-12
+                      -->
+                <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
+                  235e-12
+                  235e-12
+                  235e-12
+                  235e-12
+                  235e-12
+                </delay_matrix>
+              </pb_type>
+              <!-- Define the flip-flop -->
+              <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+                <input name="D" num_pins="1" port_class="D"/>
+                <output name="Q" num_pins="1" port_class="Q"/>
+                <clock name="clk" num_pins="1" port_class="clock"/>
+                <T_setup value="66e-12" port="ff.D" clock="clk"/>
+                <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="ble5.in[4:0]" output="lut5[0:0].in[4:0]"/>
+                <direct name="direct2" input="lut5[0:0].out" output="ff[0:0].D">
+                  <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
+                  <pack_pattern name="ble5" in_port="lut5[0:0].out" out_port="ff[0:0].D"/>
+                </direct>
+                <direct name="direct3" input="ble5.clk" output="ff[0:0].clk"/>
+                <mux name="mux1" input="ff[0:0].Q lut5.out[0:0]" output="ble5.out[0:0]">
+                  <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                  <delay_constant max="25e-12" in_port="lut5.out[0:0]" out_port="ble5.out[0:0]"/>
+                  <delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble5.out[0:0]"/>
+                </mux>
+              </interconnect>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="lut5inter.in" output="ble5[0:0].in"/>
+              <direct name="direct2" input="lut5inter.in" output="ble5[1:1].in"/>
+              <direct name="direct3" input="ble5[1:0].out" output="lut5inter.out"/>
+              <complete name="complete1" input="lut5inter.clk" output="ble5[1:0].clk"/>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[4:0]" output="lut5inter.in"/>
+            <direct name="direct2" input="lut5inter.out" output="fle.out"/>
+            <direct name="direct3" input="fle.clk" output="lut5inter.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Dual 5-LUT mode definition end -->
+        <!-- 6-LUT mode definition begin -->
+        <mode name="n1_lut6">
+          <!-- Define 6-LUT mode -->
+          <pb_type name="ble6" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Define LUT -->
+            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="6" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->
+              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                261e-12
+                261e-12
+                261e-12
+                261e-12
+                261e-12
+                261e-12
+              </delay_matrix>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+              <direct name="direct2" input="lut6.out" output="ff.D">
+                <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
+                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="ble6.in"/>
+            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+          </interconnect>
+        </mode>
+        <!-- 6-LUT mode definition end -->
+      </pb_type>
+      <interconnect>
+        <!-- We use a full crossbar to get logical equivalence at inputs of CLB 
+		     The delays below come from Stratix IV. the delay through a connection block
+		     input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+		     delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+		     delay within the crossbar is 95 ps. 
+		     The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+		     Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+		     25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+		     to get the part that should be marked on the crossbar.	 -->
+        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
+          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
+          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
+        </complete>
+        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+        </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+               By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+               then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+               naive specification).
+          -->
+        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
+        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
+      </interconnect>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- Place this general purpose logic block in any unspecified column -->
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+  </complexblocklist>
+</architecture>
diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_40nm.xml b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_40nm.xml
new file mode 100644
index 000000000..eea76837f
--- /dev/null
+++ b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_40nm.xml
@@ -0,0 +1,639 @@
+<!-- 
+  Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with 8 total FLE inputs (2 inputs of which are shared by the 5-LUTs) 
+    with optionally registered outputs
+    Each 5-LUT has an arithemtic mode that converts it to a single-bit adder with both inputs driven by 4-LUTs (both 4-LUTs share all 4 inputs)
+    Carry chain links to vertically adjacent logic blocks
+  - Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.  
+    Height = 6, found on every (8n+2)th column
+  - Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.  
+    Height = 4, found on every (8n+6)th column
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Details on Modelling:
+
+  The electrical design of the architecture described here is NOT from an 
+  optimized, SPICED architecture.  Instead, we attempt to create a reasonable 
+  architecture file by using an existing commercial FPGA to approximate the area, 
+  delay, and power of the underlying components. This is combined with a reasonable 40 nm 
+  model of wiring and circuit design for low-level routing components, where available.
+  The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also 
+  has wiring electrical parameters that allow the wire lengths and switch patterns to be 
+  modified and you will still get reasonable delay results for the new architecture.
+  The following describes, in detail, how we obtained the various electrical values for this 
+  architecture.
+
+  Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar 
+  architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture. 
+  (n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)      
+  This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to 
+  match the overall target (a 40 nm FPGA).
+
+  We obtain delay numbers by measuring delays of routing, soft logic blocks, 
+  memories, and multipliers from test circuits on a Stratix IV GX device 
+  (EP4SGX230DF29C2X, i.e. fastest speed grade). For routing, we took the average delay of H4 and V4 
+  wires.  Rmetal and Cmetal values for the routing wires were obtained from work done by Charles 
+  Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal stack 40 nm routing) and 
+  take the R and C data from the ITRS roadmap.  
+
+  For the general purpose logic block, we assume that the area and delays of the Stratix IV 
+  crossbar is close enough to the crossbar modelled here.  
+  Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to 
+  36:1 multiplexers.  We match these parameters in this architecture.
+
+  For LUTs, we include LUT 
+  delays measured from Stratix IV which is dependant on the input used (ie. some 
+  LUT inputs are faster than others).  The CAD tools at the time of VTR 7 does 
+  not consider differences in LUT input delays.
+
+  Adder delays obtained as approximate values from a Stratix IV EP4SE230F29C3 device.  
+  Delay obtained by compiling a 256 bit adder (registered inputs and outputs, 
+  all pins except clock virtual) then measuring the delays in chip-planner, 
+  sumout delay = 0.271ns to 0.348 ns, intra-block carry delay = 0.011 ns, 
+  inter-block carry delay = 0.327 ns.  Given this data, I will approximate 
+  sumout 0.3 ns, intra-block carry-delay = 0.01 ns, and 
+  inter-block carry-delay = 0.16 ns (since Altera inter-block carry delay has 
+  overhead that we don't have, I'll approximate the delay of a simpler chain at 
+  one half what they have.  This is very rough, anything from 0.01ns to 0.327ns 
+  can be justified).
+
+  Logic block area numbers obtained by scaling overall tile area of a 65nm 
+  Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out 
+  routing area at a channel width of 300. We use a channel width of 300 because it can route 
+  all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
+  total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
+  choosing a width that provides high routability. The architecture can be routed at different channel
+  widths, but we estimate the tile size and hence the physical length of routing wires assuming
+  a channel width of 300.
+
+  Sanity checks employed:
+    1.  We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches 
+        common electrical design.
+
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <model name="adder">
+      <input_ports>
+        <port name="a" combinational_sink_ports="sumout cout"/>
+        <port name="b" combinational_sink_ports="sumout cout"/>
+        <port name="cin" combinational_sink_ports="sumout cout"/>
+      </input_ports>
+      <output_ports>
+        <port name="cout"/>
+        <port name="sumout"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="frac_lut6">
+      <input_ports>
+        <port name="in"/>
+      </input_ports>
+      <output_ports>
+        <port name="lut4_out"/>
+        <port name="lut5_out"/>
+        <port name="lut6_out"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <tile name="io" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad</loc>
+        <loc side="top">io.outpad io.inpad</loc>
+        <loc side="right">io.outpad io.inpad</loc>
+        <loc side="bottom">io.outpad io.inpad</loc>
+      </pinlocations>
+    </tile>
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
+      </fc>
+      <!--  Highly recommand to customize pin location when direct connection is used!!! -->
+      <!--pinlocations pattern="spread"/-->
+      <pinlocations pattern="custom">
+        <loc side="left">clb.clk</loc>
+        <loc side="top">clb.cin</loc>
+        <loc side="right">clb.O[9:0] clb.I[19:0]</loc>
+        <loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
+      </pinlocations>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout tileable="true">
+    <!--auto_layout aspect_ratio="1.0"-->
+    <fixed_layout name="4x4" width="6" height="6">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </fixed_layout>
+    <!-- /auto_layout -->
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	    -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+           book area formula. This means the mux transistors are about 5x minimum drive strength.
+           We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+           mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+           the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+           by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+           buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+           I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+           (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+           The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+           2.5x when looking up in Jeff's tables.
+           Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+           This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+             With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+             reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <directlist>
+    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
+  </directlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+
+      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+           If you need to register the I/O, define clocks in the circuit models
+           These clocks can be handled in back-end
+       -->
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" disabled_in_pack="true">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe fracturable logic element.  
+             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
+             The outputs of the fracturable logic element can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="10">
+        <input name="in" num_pins="6"/>
+        <input name="cin" num_pins="1"/>
+        <output name="out" num_pins="2"/>
+        <output name="cout" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- Physical mode definition begin (physical implementation of the fle) -->
+        <mode name="physical" disabled_in_pack="true">
+          <pb_type name="fabric" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="frac_logic" num_pb="1">
+              <input name="in" num_pins="6"/>
+              <output name="lut4_out" num_pins="4"/>
+              <output name="out" num_pins="2"/>
+              <!-- Define LUT -->
+              <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
+                <input name="in" num_pins="6"/>
+                <output name="lut4_out" num_pins="4"/>
+                <output name="lut5_out" num_pins="2"/>
+                <output name="lut6_out" num_pins="1"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
+                <direct name="direct2" input="frac_lut6.lut4_out" output="frac_logic.lut4_out"/>
+                <direct name="direct3" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
+                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
+                <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
+              </interconnect>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>         
+            <!-- Define adders -->
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="2">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
+              <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
+              <direct name="direct3" input="fabric.cin" output="adder[0:0].cin"/>
+              <direct name="direct4" input="adder[0:0].cout" output="adder[1:1].cin"/>
+              <direct name="direct5" input="adder[1:1].cout" output="fabric.cout"/>
+              <direct name="direct6" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
+              <direct name="direct7" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
+              <direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
+              <direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
+              <complete name="direct10" input="fabric.clk" output="ff[1:0].clk"/>
+              <mux name="mux1" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
+                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
+              </mux>
+              <mux name="mux2" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
+                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="fabric.in"/>
+            <direct name="direct2" input="fle.cin" output="fabric.cin"/>
+            <direct name="direct3" input="fabric.out" output="fle.out"/>
+            <direct name="direct4" input="fabric.cout" output="fle.cout"/>
+            <direct name="direct5" input="fle.clk" output="fabric.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Physical mode definition end (physical implementation of the fle) -->
+        <!-- BEGIN fle mode of dual lut5 -->
+        <mode name="n2_lut5">
+          <pb_type name="ble5" num_pb="2">
+            <input name="in" num_pins="5"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Regular LUT mode -->
+            <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="5" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                  we instead take the average of these numbers to get more stable results
+                82e-12
+                173e-12
+                261e-12
+                263e-12
+                398e-12
+                -->
+              <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+              </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble5.in" output="lut5.in"/>
+              <direct name="direct2" input="lut5.out" output="ff.D">
+                <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble5.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut5.out" output="ble5.out">
+                <delay_constant max="25e-12" in_port="lut5.out" out_port="ble5.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble5.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[4:0]" output="ble5[0:0].in"/>
+            <direct name="direct2" input="fle.in[4:0]" output="ble5[1:1].in"/>
+            <complete name="direct3" input="fle.clk" output="ble5.clk"/>
+            <direct name="direct4" input="ble5.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- END fle mode of dual lut5 -->
+        <!-- BEGIN arithmetic mode of dual lut4 + adders -->
+        <mode name="arithmetic">
+          <pb_type name="arithmetic" num_pb="2">
+            <input name="in" num_pins="4"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="1"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Special dual-LUT mode that drives adder only -->
+            <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
+              <input name="in" num_pins="4" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  -->
+              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                  195e-12
+                  195e-12
+                  195e-12
+                  195e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
+              <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
+              <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
+              <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
+                </direct>
+              <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
+                </direct>
+              <direct name="add_to_ff" input="adder.sumout" output="ff.D">
+                <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
+              </direct>
+              <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
+                <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
+              </direct>
+              <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
+                <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
+              </direct>
+              <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
+                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[3:0]" output="arithmetic[0:0].in"/>
+            <direct name="direct2" input="fle.in[3:0]" output="arithmetic[1:1].in"/>
+            <direct name="carry_in" input="fle.cin" output="arithmetic[0:0].cin">
+              <pack_pattern name="chain" in_port="fle.cin" out_port="arithmetic[0:0].cin"/>
+            </direct>
+            <direct name="carry_inter" input="arithmetic[0:0].cout" output="arithmetic[1:1].cin">
+              <pack_pattern name="chain" in_port="arithmetic[0:0].cout" out_port="arithmetic[1:1].cin"/>
+            </direct>
+            <direct name="carry_out" input="arithmetic[1:1].cout" output="fle.cout">
+              <pack_pattern name="chain" in_port="arithmetic.cout" out_port="fle.cout"/>
+            </direct>
+            <complete name="direct3" input="fle.clk" output="arithmetic.clk"/>
+            <direct name="direct4" input="arithmetic.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- n2_lut5 -->
+        <mode name="n1_lut6">
+          <pb_type name="ble6" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="6" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->
+              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+              <direct name="direct2" input="lut6.out" output="ff.D">
+                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
+            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+          </interconnect>
+        </mode>
+        <!-- n1_lut6 -->
+      </pb_type>
+      <interconnect>
+        <!-- We use a 50% depop crossbar built using small full xbars to get sets of logically equivalent pins at inputs of CLB 
+           The delays below come from Stratix IV. the delay through a connection block
+           input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+           delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+           delay within the crossbar is 95 ps. 
+           The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+           Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+           25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+           to get the part that should be marked on the crossbar.	 -->
+        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
+          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
+          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
+        </complete>
+
+        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+        </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+                 By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+                 then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+                 naive specification).
+          -->
+        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
+        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
+        <!-- Carry chain links -->
+        <direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
+          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
+        </direct>
+        <direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
+          <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
+        </direct>
+        <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
+          <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
+        </direct>
+      </interconnect>
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+  </complexblocklist>
+</architecture>
diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml
new file mode 100644
index 000000000..9422c3a09
--- /dev/null
+++ b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml
@@ -0,0 +1,734 @@
+<!-- 
+  Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with 8 total FLE inputs (2 inputs of which are shared by the 5-LUTs) 
+    with optionally registered outputs
+    Each 5-LUT has an arithemtic mode that converts it to a single-bit adder with both inputs driven by 4-LUTs (both 4-LUTs share all 4 inputs)
+    Carry chain links to vertically adjacent logic blocks
+  - Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.  
+    Height = 6, found on every (8n+2)th column
+  - Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.  
+    Height = 4, found on every (8n+6)th column
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Details on Modelling:
+
+  The electrical design of the architecture described here is NOT from an 
+  optimized, SPICED architecture.  Instead, we attempt to create a reasonable 
+  architecture file by using an existing commercial FPGA to approximate the area, 
+  delay, and power of the underlying components. This is combined with a reasonable 40 nm 
+  model of wiring and circuit design for low-level routing components, where available.
+  The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also 
+  has wiring electrical parameters that allow the wire lengths and switch patterns to be 
+  modified and you will still get reasonable delay results for the new architecture.
+  The following describes, in detail, how we obtained the various electrical values for this 
+  architecture.
+
+  Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar 
+  architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture. 
+  (n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)      
+  This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to 
+  match the overall target (a 40 nm FPGA).
+
+  We obtain delay numbers by measuring delays of routing, soft logic blocks, 
+  memories, and multipliers from test circuits on a Stratix IV GX device 
+  (EP4SGX230DF29C2X, i.e. fastest speed grade). For routing, we took the average delay of H4 and V4 
+  wires.  Rmetal and Cmetal values for the routing wires were obtained from work done by Charles 
+  Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal stack 40 nm routing) and 
+  take the R and C data from the ITRS roadmap.  
+
+  For the general purpose logic block, we assume that the area and delays of the Stratix IV 
+  crossbar is close enough to the crossbar modelled here.  
+  Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to 
+  36:1 multiplexers.  We match these parameters in this architecture.
+
+  For LUTs, we include LUT 
+  delays measured from Stratix IV which is dependant on the input used (ie. some 
+  LUT inputs are faster than others).  The CAD tools at the time of VTR 7 does 
+  not consider differences in LUT input delays.
+
+  Adder delays obtained as approximate values from a Stratix IV EP4SE230F29C3 device.  
+  Delay obtained by compiling a 256 bit adder (registered inputs and outputs, 
+  all pins except clock virtual) then measuring the delays in chip-planner, 
+  sumout delay = 0.271ns to 0.348 ns, intra-block carry delay = 0.011 ns, 
+  inter-block carry delay = 0.327 ns.  Given this data, I will approximate 
+  sumout 0.3 ns, intra-block carry-delay = 0.01 ns, and 
+  inter-block carry-delay = 0.16 ns (since Altera inter-block carry delay has 
+  overhead that we don't have, I'll approximate the delay of a simpler chain at 
+  one half what they have.  This is very rough, anything from 0.01ns to 0.327ns 
+  can be justified).
+
+  Logic block area numbers obtained by scaling overall tile area of a 65nm 
+  Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out 
+  routing area at a channel width of 300. We use a channel width of 300 because it can route 
+  all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
+  total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
+  choosing a width that provides high routability. The architecture can be routed at different channel
+  widths, but we estimate the tile size and hence the physical length of routing wires assuming
+  a channel width of 300.
+
+  Sanity checks employed:
+    1.  We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches 
+        common electrical design.
+
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <model name="adder">
+      <input_ports>
+        <port name="a" combinational_sink_ports="sumout cout"/>
+        <port name="b" combinational_sink_ports="sumout cout"/>
+        <port name="cin" combinational_sink_ports="sumout cout"/>
+      </input_ports>
+      <output_ports>
+        <port name="cout"/>
+        <port name="sumout"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="frac_lut6">
+      <input_ports>
+        <port name="in"/>
+      </input_ports>
+      <output_ports>
+        <port name="lut4_out"/>
+        <port name="lut5_out"/>
+        <port name="lut6_out"/>
+      </output_ports>
+    </model>
+    <model name="dual_port_ram">
+      <input_ports>
+        <!-- write address lines -->
+        <port name="waddr" clock="clk"/>
+        <!-- read address lines -->
+        <port name="raddr" clock="clk"/>
+        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
+        <port name="d_in" clock="clk"/>
+        <!-- write enable -->
+        <port name="wen" clock="clk"/>
+        <!-- read enable -->
+        <port name="ren" clock="clk"/>
+        <!-- memories are often clocked -->
+        <port name="clk" is_clock="1"/>
+      </input_ports>
+      <output_ports>
+        <!-- output can be broken down into smaller bit widths minimum size 1 -->
+        <port name="d_out" clock="clk"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <tile name="io" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad</loc>
+        <loc side="top">io.outpad io.inpad</loc>
+        <loc side="right">io.outpad io.inpad</loc>
+        <loc side="bottom">io.outpad io.inpad</loc>
+      </pinlocations>
+    </tile>
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
+      </fc>
+      <!--  Highly recommand to customize pin location when direct connection is used!!! -->
+      <!--pinlocations pattern="spread"/-->
+      <pinlocations pattern="custom">
+        <loc side="left">clb.clk</loc>
+        <loc side="top">clb.cin</loc>
+        <loc side="right">clb.O[9:0] clb.I[19:0]</loc>
+        <loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
+      </pinlocations>
+    </tile>
+    <tile name="memory" height="2" area="548000">
+      <equivalent_sites>
+        <site pb_type="memory"/>
+      </equivalent_sites>
+      <input name="waddr" num_pins="10"/>
+      <input name="raddr" num_pins="10"/>
+      <input name="d_in" num_pins="32"/>
+      <input name="wen" num_pins="1"/>
+      <input name="ren" num_pins="1"/>
+      <output name="d_out" num_pins="32"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="spread"/>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout tileable="true" through_channel="false">
+    <!--auto_layout aspect_ratio="1.0"-->
+    <fixed_layout name="4x4" width="5" height="4">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
+      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
+    </fixed_layout>
+    <!-- /auto_layout -->
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	    -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+           book area formula. This means the mux transistors are about 5x minimum drive strength.
+           We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+           mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+           the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+           by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+           buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+           I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+           (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+           The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+           2.5x when looking up in Jeff's tables.
+           Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+           This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+             With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+             reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <directlist>
+    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
+  </directlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+
+      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+           If you need to register the I/O, define clocks in the circuit models
+           These clocks can be handled in back-end
+       -->
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" disabled_in_pack="true">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe fracturable logic element.  
+             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
+             The outputs of the fracturable logic element can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="10">
+        <input name="in" num_pins="6"/>
+        <input name="cin" num_pins="1"/>
+        <output name="out" num_pins="2"/>
+        <output name="cout" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- Physical mode definition begin (physical implementation of the fle) -->
+        <mode name="physical" disabled_in_pack="true">
+          <pb_type name="fabric" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="frac_logic" num_pb="1">
+              <input name="in" num_pins="6"/>
+              <output name="lut4_out" num_pins="4"/>
+              <output name="out" num_pins="2"/>
+              <!-- Define LUT -->
+              <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
+                <input name="in" num_pins="6"/>
+                <output name="lut4_out" num_pins="4"/>
+                <output name="lut5_out" num_pins="2"/>
+                <output name="lut6_out" num_pins="1"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
+                <direct name="direct2" input="frac_lut6.lut4_out" output="frac_logic.lut4_out"/>
+                <direct name="direct3" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
+                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
+                <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
+              </interconnect>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>         
+            <!-- Define adders -->
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="2">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
+              <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
+              <direct name="direct3" input="fabric.cin" output="adder[0:0].cin"/>
+              <direct name="direct4" input="adder[0:0].cout" output="adder[1:1].cin"/>
+              <direct name="direct5" input="adder[1:1].cout" output="fabric.cout"/>
+              <direct name="direct6" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
+              <direct name="direct7" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
+              <direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
+              <direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
+              <complete name="direct10" input="fabric.clk" output="ff[1:0].clk"/>
+              <mux name="mux1" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
+                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
+              </mux>
+              <mux name="mux2" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
+                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="fabric.in"/>
+            <direct name="direct2" input="fle.cin" output="fabric.cin"/>
+            <direct name="direct3" input="fabric.out" output="fle.out"/>
+            <direct name="direct4" input="fabric.cout" output="fle.cout"/>
+            <direct name="direct5" input="fle.clk" output="fabric.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Physical mode definition end (physical implementation of the fle) -->
+        <!-- BEGIN fle mode of dual lut5 -->
+        <mode name="n2_lut5">
+          <pb_type name="ble5" num_pb="2">
+            <input name="in" num_pins="5"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Regular LUT mode -->
+            <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="5" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                  we instead take the average of these numbers to get more stable results
+                82e-12
+                173e-12
+                261e-12
+                263e-12
+                398e-12
+                -->
+              <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+              </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble5.in" output="lut5.in"/>
+              <direct name="direct2" input="lut5.out" output="ff.D">
+                <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble5.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut5.out" output="ble5.out">
+                <delay_constant max="25e-12" in_port="lut5.out" out_port="ble5.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble5.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[4:0]" output="ble5[0:0].in"/>
+            <direct name="direct2" input="fle.in[4:0]" output="ble5[1:1].in"/>
+            <complete name="direct3" input="fle.clk" output="ble5.clk"/>
+            <direct name="direct4" input="ble5.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- END fle mode of dual lut5 -->
+        <!-- BEGIN arithmetic mode of dual lut4 + adders -->
+        <mode name="arithmetic">
+          <pb_type name="arithmetic" num_pb="2">
+            <input name="in" num_pins="4"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="1"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Special dual-LUT mode that drives adder only -->
+            <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
+              <input name="in" num_pins="4" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  -->
+              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                  195e-12
+                  195e-12
+                  195e-12
+                  195e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
+              <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
+              <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
+              <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
+                </direct>
+              <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
+                </direct>
+              <direct name="add_to_ff" input="adder.sumout" output="ff.D">
+                <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
+              </direct>
+              <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
+                <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
+              </direct>
+              <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
+                <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
+              </direct>
+              <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
+                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[3:0]" output="arithmetic[0:0].in"/>
+            <direct name="direct2" input="fle.in[3:0]" output="arithmetic[1:1].in"/>
+            <direct name="carry_in" input="fle.cin" output="arithmetic[0:0].cin">
+              <pack_pattern name="chain" in_port="fle.cin" out_port="arithmetic[0:0].cin"/>
+            </direct>
+            <direct name="carry_inter" input="arithmetic[0:0].cout" output="arithmetic[1:1].cin">
+              <pack_pattern name="chain" in_port="arithmetic[0:0].cout" out_port="arithmetic[1:1].cin"/>
+            </direct>
+            <direct name="carry_out" input="arithmetic[1:1].cout" output="fle.cout">
+              <pack_pattern name="chain" in_port="arithmetic.cout" out_port="fle.cout"/>
+            </direct>
+            <complete name="direct3" input="fle.clk" output="arithmetic.clk"/>
+            <direct name="direct4" input="arithmetic.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- n2_lut5 -->
+        <mode name="n1_lut6">
+          <pb_type name="ble6" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="6" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->
+              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+              <direct name="direct2" input="lut6.out" output="ff.D">
+                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
+            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+          </interconnect>
+        </mode>
+        <!-- n1_lut6 -->
+      </pb_type>
+      <interconnect>
+        <!-- We use a 50% depop crossbar built using small full xbars to get sets of logically equivalent pins at inputs of CLB 
+           The delays below come from Stratix IV. the delay through a connection block
+           input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+           delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+           delay within the crossbar is 95 ps. 
+           The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+           Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+           25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+           to get the part that should be marked on the crossbar.	 -->
+        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
+          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
+          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
+        </complete>
+
+        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+        </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+                 By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+                 then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+                 naive specification).
+          -->
+        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
+        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
+        <!-- Carry chain links -->
+        <direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
+          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
+        </direct>
+        <direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
+          <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
+        </direct>
+        <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
+          <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
+        </direct>
+      </interconnect>
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+    <!-- Define single-mode dual-port memory begin -->
+    <pb_type name="memory">
+      <input name="waddr" num_pins="10"/>
+      <input name="raddr" num_pins="10"/>
+      <input name="d_in" num_pins="32"/>
+      <input name="wen" num_pins="1"/>
+      <input name="ren" num_pins="1"/>
+      <output name="d_out" num_pins="32"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Specify the 512x32=16Kbit memory block
+           Note: the delay numbers are extracted from VPR flagship XML without modification
+                 Should align to the process technology we using to create the 16K dual-port RAM
+        -->
+      <mode name="mem_512x32_dp">
+        <pb_type name="mem_512x32_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
+          <input name="waddr" num_pins="10" port_class="address"/>
+          <input name="raddr" num_pins="10" port_class="address"/>
+          <input name="d_in" num_pins="32" port_class="data_in"/>
+          <input name="wen" num_pins="1" port_class="write_en"/>
+          <input name="ren" num_pins="1" port_class="write_en"/>
+          <output name="d_out" num_pins="32" port_class="data_out"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.waddr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.raddr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.d_in" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.wen" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.ren" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_512x32_dp.d_out" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="17.9e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="waddress" input="memory.waddr" output="mem_512x32_dp.waddr">
+            <delay_constant max="132e-12" in_port="memory.waddr" out_port="mem_512x32_dp.waddr"/>
+          </direct>
+          <direct name="raddress" input="memory.raddr" output="mem_512x32_dp.raddr">
+            <delay_constant max="132e-12" in_port="memory.raddr" out_port="mem_512x32_dp.raddr"/>
+          </direct>
+          <direct name="data_input" input="memory.d_in" output="mem_512x32_dp.d_in">
+            <delay_constant max="132e-12" in_port="memory.d_in" out_port="mem_512x32_dp.d_in"/>
+          </direct>
+          <direct name="writeen" input="memory.wen" output="mem_512x32_dp.wen">
+            <delay_constant max="132e-12" in_port="memory.wen" out_port="mem_512x32_dp.wen"/>
+          </direct>
+          <direct name="readen" input="memory.ren" output="mem_512x32_dp.ren">
+            <delay_constant max="132e-12" in_port="memory.ren" out_port="mem_512x32_dp.ren"/>
+          </direct>
+          <direct name="dataout" input="mem_512x32_dp.d_out" output="memory.d_out">
+            <delay_constant max="40e-12" in_port="mem_512x32_dp.d_out" out_port="memory.d_out"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_512x32_dp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+    </pb_type>
+    <!-- Define single-mode dual-port memory end -->
+  </complexblocklist>
+</architecture>
diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml
new file mode 100644
index 000000000..e196cb83c
--- /dev/null
+++ b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml
@@ -0,0 +1,800 @@
+<!-- 
+  Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with 8 total FLE inputs (2 inputs of which are shared by the 5-LUTs) 
+    with optionally registered outputs
+    Each 5-LUT has an arithemtic mode that converts it to a single-bit adder with both inputs driven by 4-LUTs (both 4-LUTs share all 4 inputs)
+    Carry chain links to vertically adjacent logic blocks
+  - Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.  
+    Height = 6, found on every (8n+2)th column
+  - Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.  
+    Height = 4, found on every (8n+6)th column
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Details on Modelling:
+
+  The electrical design of the architecture described here is NOT from an 
+  optimized, SPICED architecture.  Instead, we attempt to create a reasonable 
+  architecture file by using an existing commercial FPGA to approximate the area, 
+  delay, and power of the underlying components. This is combined with a reasonable 40 nm 
+  model of wiring and circuit design for low-level routing components, where available.
+  The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also 
+  has wiring electrical parameters that allow the wire lengths and switch patterns to be 
+  modified and you will still get reasonable delay results for the new architecture.
+  The following describes, in detail, how we obtained the various electrical values for this 
+  architecture.
+
+  Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar 
+  architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture. 
+  (n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)      
+  This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to 
+  match the overall target (a 40 nm FPGA).
+
+  We obtain delay numbers by measuring delays of routing, soft logic blocks, 
+  memories, and multipliers from test circuits on a Stratix IV GX device 
+  (EP4SGX230DF29C2X, i.e. fastest speed grade). For routing, we took the average delay of H4 and V4 
+  wires.  Rmetal and Cmetal values for the routing wires were obtained from work done by Charles 
+  Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal stack 40 nm routing) and 
+  take the R and C data from the ITRS roadmap.  
+
+  For the general purpose logic block, we assume that the area and delays of the Stratix IV 
+  crossbar is close enough to the crossbar modelled here.  
+  Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to 
+  36:1 multiplexers.  We match these parameters in this architecture.
+
+  For LUTs, we include LUT 
+  delays measured from Stratix IV which is dependant on the input used (ie. some 
+  LUT inputs are faster than others).  The CAD tools at the time of VTR 7 does 
+  not consider differences in LUT input delays.
+
+  Adder delays obtained as approximate values from a Stratix IV EP4SE230F29C3 device.  
+  Delay obtained by compiling a 256 bit adder (registered inputs and outputs, 
+  all pins except clock virtual) then measuring the delays in chip-planner, 
+  sumout delay = 0.271ns to 0.348 ns, intra-block carry delay = 0.011 ns, 
+  inter-block carry delay = 0.327 ns.  Given this data, I will approximate 
+  sumout 0.3 ns, intra-block carry-delay = 0.01 ns, and 
+  inter-block carry-delay = 0.16 ns (since Altera inter-block carry delay has 
+  overhead that we don't have, I'll approximate the delay of a simpler chain at 
+  one half what they have.  This is very rough, anything from 0.01ns to 0.327ns 
+  can be justified).
+
+  Logic block area numbers obtained by scaling overall tile area of a 65nm 
+  Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out 
+  routing area at a channel width of 300. We use a channel width of 300 because it can route 
+  all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
+  total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
+  choosing a width that provides high routability. The architecture can be routed at different channel
+  widths, but we estimate the tile size and hence the physical length of routing wires assuming
+  a channel width of 300.
+
+  Sanity checks employed:
+    1.  We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches 
+        common electrical design.
+
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <model name="adder">
+      <input_ports>
+        <port name="a" combinational_sink_ports="sumout cout"/>
+        <port name="b" combinational_sink_ports="sumout cout"/>
+        <port name="cin" combinational_sink_ports="sumout cout"/>
+      </input_ports>
+      <output_ports>
+        <port name="cout"/>
+        <port name="sumout"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="frac_lut6">
+      <input_ports>
+        <port name="in"/>
+      </input_ports>
+      <output_ports>
+        <port name="lut4_out"/>
+        <port name="lut5_out"/>
+        <port name="lut6_out"/>
+      </output_ports>
+    </model>
+    <model name="dual_port_ram">
+      <input_ports>
+        <!-- write address lines -->
+        <port name="waddr" clock="clk"/>
+        <!-- read address lines -->
+        <port name="raddr" clock="clk"/>
+        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
+        <port name="d_in" clock="clk"/>
+        <!-- write enable -->
+        <port name="wen" clock="clk"/>
+        <!-- read enable -->
+        <port name="ren" clock="clk"/>
+        <!-- memories are often clocked -->
+        <port name="clk" is_clock="1"/>
+      </input_ports>
+      <output_ports>
+        <!-- output can be broken down into smaller bit widths minimum size 1 -->
+        <port name="d_out" clock="clk"/>
+      </output_ports>
+    </model>
+    <!-- AIB interface model -->
+    <model name="aib">
+      <input_ports>
+        <port name="tx_clk" is_clock="1"/>
+        <port name="rx_clk" is_clock="1"/>
+        <port name="tx_data" clock="tx_clk"/>
+      </input_ports>
+      <output_ports>
+        <!-- output can be broken down into smaller bit widths minimum size 1 -->
+        <port name="rx_data" clock="rx_clk"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <tile name="io" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad</loc>
+        <loc side="top">io.outpad io.inpad</loc>
+        <loc side="right">io.outpad io.inpad</loc>
+        <loc side="bottom">io.outpad io.inpad</loc>
+      </pinlocations>
+    </tile>
+    <!-- A mini AIB interface to be located at the right side of the FPGA
+         All the port will be accessible to the left side of the tile
+         TODO: add full control signals
+         TODO: add analog bus ports to the right side which should be GPIOs
+      -->
+    <tile name="aib" width="1" height="4" area="0">
+      <equivalent_sites>
+        <site pb_type="aib"/>
+      </equivalent_sites>
+      <clock name="tx_clk" num_pins="1"/>
+      <input name="tx_data" num_pins="80"/>
+      <clock name="rx_clk" num_pins="1"/>
+      <output name="rx_data" num_pins="80"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">aib.tx_clk aib.tx_data aib.rx_clk aib.rx_data</loc>
+      </pinlocations>
+    </tile>
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
+      </fc>
+      <!--  Highly recommand to customize pin location when direct connection is used!!! -->
+      <!--pinlocations pattern="spread"/-->
+      <pinlocations pattern="custom">
+        <loc side="left">clb.clk</loc>
+        <loc side="top">clb.cin</loc>
+        <loc side="right">clb.O[9:0] clb.I[19:0]</loc>
+        <loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
+      </pinlocations>
+    </tile>
+    <tile name="memory" height="2" area="548000">
+      <equivalent_sites>
+        <site pb_type="memory"/>
+      </equivalent_sites>
+      <input name="waddr" num_pins="10"/>
+      <input name="raddr" num_pins="10"/>
+      <input name="d_in" num_pins="32"/>
+      <input name="wen" num_pins="1"/>
+      <input name="ren" num_pins="1"/>
+      <output name="d_out" num_pins="32"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="spread"/>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout tileable="true" through_channel="false">
+    <!--auto_layout aspect_ratio="1.0"-->
+    <fixed_layout name="4x4" width="7" height="6">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="10"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="1"/>
+      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
+      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
+      <!-- Single instance of an AIB interface -->
+      <single type="aib" x="6" y="1" priority="20"/>
+    </fixed_layout>
+    <!-- /auto_layout -->
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	    -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+           book area formula. This means the mux transistors are about 5x minimum drive strength.
+           We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+           mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+           the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+           by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+           buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+           I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+           (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+           The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+           2.5x when looking up in Jeff's tables.
+           Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+           This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+             With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+             reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <directlist>
+    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
+  </directlist>
+  <complexblocklist>
+    <!-- Define AIB begin -->
+    <pb_type name="aib">
+      <clock name="tx_clk" num_pins="1"/>
+      <input name="tx_data" num_pins="80"/>
+      <clock name="rx_clk" num_pins="1"/>
+      <output name="rx_data" num_pins="80"/>
+      <mode name="physical">
+        <pb_type name="aib_core" blif_model=".subckt aib" num_pb="1">
+          <clock name="tx_clk" num_pins="1"/>
+          <input name="tx_data" num_pins="80"/>
+          <clock name="rx_clk" num_pins="1"/>
+          <output name="rx_data" num_pins="80"/>
+          <T_setup value="509e-12" port="aib_core.tx_data" clock="tx_clk"/>
+          <T_clock_to_Q max="1.234e-9" port="aib_core.tx_data" clock="tx_clk"/>
+          <T_setup value="509e-12" port="aib_core.rx_data" clock="rx_clk"/>
+          <T_clock_to_Q max="1.234e-9" port="aib_core.rx_data" clock="rx_clk"/>
+        </pb_type>
+        <interconnect>
+          <direct name="tx_clk" input="aib.tx_clk" output="aib_core.tx_clk">
+            <delay_constant max="1.394e-11" in_port="aib.tx_clk" out_port="aib_core.tx_clk"/>
+          </direct>
+          <direct name="rx_clk" input="aib.rx_clk" output="aib_core.rx_clk">
+            <delay_constant max="1.394e-11" in_port="aib.rx_clk" out_port="aib_core.rx_clk"/>
+          </direct>
+          <direct name="tx_data" input="aib.tx_data" output="aib_core.tx_data">
+            <delay_constant max="1.394e-11" in_port="aib.tx_data" out_port="aib_core.tx_data"/>
+          </direct>
+          <direct name="rx_data" input="aib_core.rx_data" output="aib.rx_data">
+            <delay_constant max="4.243e-11" in_port="aib_core.rx_data" out_port="aib.rx_data"/>
+          </direct>
+        </interconnect>
+      </mode>
+
+    </pb_type>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+
+      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+           If you need to register the I/O, define clocks in the circuit models
+           These clocks can be handled in back-end
+       -->
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" disabled_in_pack="true">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe fracturable logic element.  
+             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
+             The outputs of the fracturable logic element can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="10">
+        <input name="in" num_pins="6"/>
+        <input name="cin" num_pins="1"/>
+        <output name="out" num_pins="2"/>
+        <output name="cout" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- Physical mode definition begin (physical implementation of the fle) -->
+        <mode name="physical" disabled_in_pack="true">
+          <pb_type name="fabric" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="frac_logic" num_pb="1">
+              <input name="in" num_pins="6"/>
+              <output name="lut4_out" num_pins="4"/>
+              <output name="out" num_pins="2"/>
+              <!-- Define LUT -->
+              <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
+                <input name="in" num_pins="6"/>
+                <output name="lut4_out" num_pins="4"/>
+                <output name="lut5_out" num_pins="2"/>
+                <output name="lut6_out" num_pins="1"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
+                <direct name="direct2" input="frac_lut6.lut4_out" output="frac_logic.lut4_out"/>
+                <direct name="direct3" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
+                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
+                <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
+              </interconnect>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>         
+            <!-- Define adders -->
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="2">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
+              <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
+              <direct name="direct3" input="fabric.cin" output="adder[0:0].cin"/>
+              <direct name="direct4" input="adder[0:0].cout" output="adder[1:1].cin"/>
+              <direct name="direct5" input="adder[1:1].cout" output="fabric.cout"/>
+              <direct name="direct6" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
+              <direct name="direct7" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
+              <direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
+              <direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
+              <complete name="direct10" input="fabric.clk" output="ff[1:0].clk"/>
+              <mux name="mux1" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
+                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
+              </mux>
+              <mux name="mux2" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
+                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="fabric.in"/>
+            <direct name="direct2" input="fle.cin" output="fabric.cin"/>
+            <direct name="direct3" input="fabric.out" output="fle.out"/>
+            <direct name="direct4" input="fabric.cout" output="fle.cout"/>
+            <direct name="direct5" input="fle.clk" output="fabric.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Physical mode definition end (physical implementation of the fle) -->
+        <!-- BEGIN fle mode of dual lut5 -->
+        <mode name="n2_lut5">
+          <pb_type name="ble5" num_pb="2">
+            <input name="in" num_pins="5"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Regular LUT mode -->
+            <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="5" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                  we instead take the average of these numbers to get more stable results
+                82e-12
+                173e-12
+                261e-12
+                263e-12
+                398e-12
+                -->
+              <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+              </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble5.in" output="lut5.in"/>
+              <direct name="direct2" input="lut5.out" output="ff.D">
+                <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble5.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut5.out" output="ble5.out">
+                <delay_constant max="25e-12" in_port="lut5.out" out_port="ble5.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble5.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[4:0]" output="ble5[0:0].in"/>
+            <direct name="direct2" input="fle.in[4:0]" output="ble5[1:1].in"/>
+            <complete name="direct3" input="fle.clk" output="ble5.clk"/>
+            <direct name="direct4" input="ble5.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- END fle mode of dual lut5 -->
+        <!-- BEGIN arithmetic mode of dual lut4 + adders -->
+        <mode name="arithmetic">
+          <pb_type name="arithmetic" num_pb="2">
+            <input name="in" num_pins="4"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="1"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Special dual-LUT mode that drives adder only -->
+            <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
+              <input name="in" num_pins="4" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  -->
+              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                  195e-12
+                  195e-12
+                  195e-12
+                  195e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
+              <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
+              <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
+              <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
+                </direct>
+              <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
+                </direct>
+              <direct name="add_to_ff" input="adder.sumout" output="ff.D">
+                <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
+              </direct>
+              <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
+                <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
+              </direct>
+              <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
+                <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
+              </direct>
+              <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
+                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[3:0]" output="arithmetic[0:0].in"/>
+            <direct name="direct2" input="fle.in[3:0]" output="arithmetic[1:1].in"/>
+            <direct name="carry_in" input="fle.cin" output="arithmetic[0:0].cin">
+              <pack_pattern name="chain" in_port="fle.cin" out_port="arithmetic[0:0].cin"/>
+            </direct>
+            <direct name="carry_inter" input="arithmetic[0:0].cout" output="arithmetic[1:1].cin">
+              <pack_pattern name="chain" in_port="arithmetic[0:0].cout" out_port="arithmetic[1:1].cin"/>
+            </direct>
+            <direct name="carry_out" input="arithmetic[1:1].cout" output="fle.cout">
+              <pack_pattern name="chain" in_port="arithmetic.cout" out_port="fle.cout"/>
+            </direct>
+            <complete name="direct3" input="fle.clk" output="arithmetic.clk"/>
+            <direct name="direct4" input="arithmetic.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- n2_lut5 -->
+        <mode name="n1_lut6">
+          <pb_type name="ble6" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="6" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->
+              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+              <direct name="direct2" input="lut6.out" output="ff.D">
+                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
+            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+          </interconnect>
+        </mode>
+        <!-- n1_lut6 -->
+      </pb_type>
+      <interconnect>
+        <!-- We use a 50% depop crossbar built using small full xbars to get sets of logically equivalent pins at inputs of CLB 
+           The delays below come from Stratix IV. the delay through a connection block
+           input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+           delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+           delay within the crossbar is 95 ps. 
+           The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+           Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+           25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+           to get the part that should be marked on the crossbar.	 -->
+        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
+          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
+          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
+        </complete>
+
+        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+        </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+                 By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+                 then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+                 naive specification).
+          -->
+        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
+        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
+        <!-- Carry chain links -->
+        <direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
+          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
+        </direct>
+        <direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
+          <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
+        </direct>
+        <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
+          <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
+        </direct>
+      </interconnect>
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+    <!-- Define single-mode dual-port memory begin -->
+    <pb_type name="memory">
+      <input name="waddr" num_pins="10"/>
+      <input name="raddr" num_pins="10"/>
+      <input name="d_in" num_pins="32"/>
+      <input name="wen" num_pins="1"/>
+      <input name="ren" num_pins="1"/>
+      <output name="d_out" num_pins="32"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Specify the 512x32=16Kbit memory block
+           Note: the delay numbers are extracted from VPR flagship XML without modification
+                 Should align to the process technology we using to create the 16K dual-port RAM
+        -->
+      <mode name="mem_512x32_dp">
+        <pb_type name="mem_512x32_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
+          <input name="waddr" num_pins="10" port_class="address"/>
+          <input name="raddr" num_pins="10" port_class="address"/>
+          <input name="d_in" num_pins="32" port_class="data_in"/>
+          <input name="wen" num_pins="1" port_class="write_en"/>
+          <input name="ren" num_pins="1" port_class="write_en"/>
+          <output name="d_out" num_pins="32" port_class="data_out"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.waddr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.raddr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.d_in" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.wen" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.ren" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_512x32_dp.d_out" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="17.9e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="waddress" input="memory.waddr" output="mem_512x32_dp.waddr">
+            <delay_constant max="132e-12" in_port="memory.waddr" out_port="mem_512x32_dp.waddr"/>
+          </direct>
+          <direct name="raddress" input="memory.raddr" output="mem_512x32_dp.raddr">
+            <delay_constant max="132e-12" in_port="memory.raddr" out_port="mem_512x32_dp.raddr"/>
+          </direct>
+          <direct name="data_input" input="memory.d_in" output="mem_512x32_dp.d_in">
+            <delay_constant max="132e-12" in_port="memory.d_in" out_port="mem_512x32_dp.d_in"/>
+          </direct>
+          <direct name="writeen" input="memory.wen" output="mem_512x32_dp.wen">
+            <delay_constant max="132e-12" in_port="memory.wen" out_port="mem_512x32_dp.wen"/>
+          </direct>
+          <direct name="readen" input="memory.ren" output="mem_512x32_dp.ren">
+            <delay_constant max="132e-12" in_port="memory.ren" out_port="mem_512x32_dp.ren"/>
+          </direct>
+          <direct name="dataout" input="mem_512x32_dp.d_out" output="memory.d_out">
+            <delay_constant max="40e-12" in_port="mem_512x32_dp.d_out" out_port="memory.d_out"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_512x32_dp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+    </pb_type>
+    <!-- Define single-mode dual-port memory end -->
+  </complexblocklist>
+</architecture>
diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml
new file mode 100644
index 000000000..8eb6f32bf
--- /dev/null
+++ b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml
@@ -0,0 +1,768 @@
+<!-- 
+  Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with 8 total FLE inputs (2 inputs of which are shared by the 5-LUTs) 
+    with optionally registered outputs
+    Each 5-LUT has an arithemtic mode that converts it to a single-bit adder with both inputs driven by 4-LUTs (both 4-LUTs share all 4 inputs)
+    Carry chain links to vertically adjacent logic blocks
+  - Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.  
+    Height = 6, found on every (8n+2)th column
+  - Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.  
+    Height = 4, found on every (8n+6)th column
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Details on Modelling:
+
+  The electrical design of the architecture described here is NOT from an 
+  optimized, SPICED architecture.  Instead, we attempt to create a reasonable 
+  architecture file by using an existing commercial FPGA to approximate the area, 
+  delay, and power of the underlying components. This is combined with a reasonable 40 nm 
+  model of wiring and circuit design for low-level routing components, where available.
+  The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also 
+  has wiring electrical parameters that allow the wire lengths and switch patterns to be 
+  modified and you will still get reasonable delay results for the new architecture.
+  The following describes, in detail, how we obtained the various electrical values for this 
+  architecture.
+
+  Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar 
+  architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture. 
+  (n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)      
+  This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to 
+  match the overall target (a 40 nm FPGA).
+
+  We obtain delay numbers by measuring delays of routing, soft logic blocks, 
+  memories, and multipliers from test circuits on a Stratix IV GX device 
+  (EP4SGX230DF29C2X, i.e. fastest speed grade). For routing, we took the average delay of H4 and V4 
+  wires.  Rmetal and Cmetal values for the routing wires were obtained from work done by Charles 
+  Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal stack 40 nm routing) and 
+  take the R and C data from the ITRS roadmap.  
+
+  For the general purpose logic block, we assume that the area and delays of the Stratix IV 
+  crossbar is close enough to the crossbar modelled here.  
+  Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to 
+  36:1 multiplexers.  We match these parameters in this architecture.
+
+  For LUTs, we include LUT 
+  delays measured from Stratix IV which is dependant on the input used (ie. some 
+  LUT inputs are faster than others).  The CAD tools at the time of VTR 7 does 
+  not consider differences in LUT input delays.
+
+  Adder delays obtained as approximate values from a Stratix IV EP4SE230F29C3 device.  
+  Delay obtained by compiling a 256 bit adder (registered inputs and outputs, 
+  all pins except clock virtual) then measuring the delays in chip-planner, 
+  sumout delay = 0.271ns to 0.348 ns, intra-block carry delay = 0.011 ns, 
+  inter-block carry delay = 0.327 ns.  Given this data, I will approximate 
+  sumout 0.3 ns, intra-block carry-delay = 0.01 ns, and 
+  inter-block carry-delay = 0.16 ns (since Altera inter-block carry delay has 
+  overhead that we don't have, I'll approximate the delay of a simpler chain at 
+  one half what they have.  This is very rough, anything from 0.01ns to 0.327ns 
+  can be justified).
+
+  Logic block area numbers obtained by scaling overall tile area of a 65nm 
+  Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out 
+  routing area at a channel width of 300. We use a channel width of 300 because it can route 
+  all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
+  total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
+  choosing a width that provides high routability. The architecture can be routed at different channel
+  widths, but we estimate the tile size and hence the physical length of routing wires assuming
+  a channel width of 300.
+
+  Sanity checks employed:
+    1.  We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches 
+        common electrical design.
+
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <model name="adder">
+      <input_ports>
+        <port name="a" combinational_sink_ports="sumout cout"/>
+        <port name="b" combinational_sink_ports="sumout cout"/>
+        <port name="cin" combinational_sink_ports="sumout cout"/>
+      </input_ports>
+      <output_ports>
+        <port name="cout"/>
+        <port name="sumout"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="frac_lut6">
+      <input_ports>
+        <port name="in"/>
+      </input_ports>
+      <output_ports>
+        <port name="lut4_out"/>
+        <port name="lut5_out"/>
+        <port name="lut6_out"/>
+      </output_ports>
+    </model>
+    <model name="dual_port_ram">
+      <input_ports>
+        <!-- write address lines -->
+        <port name="waddr" clock="clk"/>
+        <!-- read address lines -->
+        <port name="raddr" clock="clk"/>
+        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
+        <port name="d_in" clock="clk"/>
+        <!-- write enable -->
+        <port name="wen" clock="clk"/>
+        <!-- read enable -->
+        <port name="ren" clock="clk"/>
+        <!-- memories are often clocked -->
+        <port name="clk" is_clock="1"/>
+      </input_ports>
+      <output_ports>
+        <!-- output can be broken down into smaller bit widths minimum size 1 -->
+        <port name="d_out" clock="clk"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <tile name="io_top" capacity="3" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="bottom">io_top.outpad io_top.inpad</loc>
+      </pinlocations>
+    </tile>
+    <tile name="io_right" capacity="2" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io_right.outpad io_right.inpad</loc>
+      </pinlocations>
+    </tile>
+    <tile name="io_bottom" capacity="1" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="top">io_bottom.outpad io_bottom.inpad</loc>
+      </pinlocations>
+    </tile>
+    <tile name="io_left" capacity="4" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="right">io_left.outpad io_left.inpad</loc>
+      </pinlocations>
+    </tile>
+
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
+      </fc>
+      <!--  Highly recommand to customize pin location when direct connection is used!!! -->
+      <!--pinlocations pattern="spread"/-->
+      <pinlocations pattern="custom">
+        <loc side="left">clb.clk</loc>
+        <loc side="top">clb.cin</loc>
+        <loc side="right">clb.O[9:0] clb.I[19:0]</loc>
+        <loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
+      </pinlocations>
+    </tile>
+    <tile name="memory" height="2" area="548000">
+      <equivalent_sites>
+        <site pb_type="memory"/>
+      </equivalent_sites>
+      <input name="waddr" num_pins="10"/>
+      <input name="raddr" num_pins="10"/>
+      <input name="d_in" num_pins="32"/>
+      <input name="wen" num_pins="1"/>
+      <input name="ren" num_pins="1"/>
+      <output name="d_out" num_pins="32"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="spread"/>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout tileable="true" through_channel="false">
+    <!--auto_layout aspect_ratio="1.0"-->
+    <fixed_layout name="4x4" width="5" height="4">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <row type="io_top" starty="H-1" priority="100"/>
+      <row type="io_bottom" starty="0" priority="100"/>
+      <col type="io_left" startx="0" priority="100"/>
+      <col type="io_right" startx="W-1" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
+      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
+    </fixed_layout>
+    <!-- /auto_layout -->
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	    -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+           book area formula. This means the mux transistors are about 5x minimum drive strength.
+           We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+           mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+           the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+           by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+           buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+           I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+           (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+           The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+           2.5x when looking up in Jeff's tables.
+           Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+           This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+             With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+             reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <directlist>
+    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
+  </directlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+
+      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+           If you need to register the I/O, define clocks in the circuit models
+           These clocks can be handled in back-end
+       -->
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" disabled_in_pack="true">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe fracturable logic element.  
+             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
+             The outputs of the fracturable logic element can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="10">
+        <input name="in" num_pins="6"/>
+        <input name="cin" num_pins="1"/>
+        <output name="out" num_pins="2"/>
+        <output name="cout" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- Physical mode definition begin (physical implementation of the fle) -->
+        <mode name="physical" disabled_in_pack="true">
+          <pb_type name="fabric" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="frac_logic" num_pb="1">
+              <input name="in" num_pins="6"/>
+              <output name="lut4_out" num_pins="4"/>
+              <output name="out" num_pins="2"/>
+              <!-- Define LUT -->
+              <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
+                <input name="in" num_pins="6"/>
+                <output name="lut4_out" num_pins="4"/>
+                <output name="lut5_out" num_pins="2"/>
+                <output name="lut6_out" num_pins="1"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
+                <direct name="direct2" input="frac_lut6.lut4_out" output="frac_logic.lut4_out"/>
+                <direct name="direct3" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
+                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
+                <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
+              </interconnect>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>         
+            <!-- Define adders -->
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="2">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
+              <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
+              <direct name="direct3" input="fabric.cin" output="adder[0:0].cin"/>
+              <direct name="direct4" input="adder[0:0].cout" output="adder[1:1].cin"/>
+              <direct name="direct5" input="adder[1:1].cout" output="fabric.cout"/>
+              <direct name="direct6" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
+              <direct name="direct7" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
+              <direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
+              <direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
+              <complete name="direct10" input="fabric.clk" output="ff[1:0].clk"/>
+              <mux name="mux1" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
+                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
+              </mux>
+              <mux name="mux2" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
+                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="fabric.in"/>
+            <direct name="direct2" input="fle.cin" output="fabric.cin"/>
+            <direct name="direct3" input="fabric.out" output="fle.out"/>
+            <direct name="direct4" input="fabric.cout" output="fle.cout"/>
+            <direct name="direct5" input="fle.clk" output="fabric.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Physical mode definition end (physical implementation of the fle) -->
+        <!-- BEGIN fle mode of dual lut5 -->
+        <mode name="n2_lut5">
+          <pb_type name="ble5" num_pb="2">
+            <input name="in" num_pins="5"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Regular LUT mode -->
+            <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="5" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                  we instead take the average of these numbers to get more stable results
+                82e-12
+                173e-12
+                261e-12
+                263e-12
+                398e-12
+                -->
+              <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+              </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble5.in" output="lut5.in"/>
+              <direct name="direct2" input="lut5.out" output="ff.D">
+                <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble5.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut5.out" output="ble5.out">
+                <delay_constant max="25e-12" in_port="lut5.out" out_port="ble5.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble5.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[4:0]" output="ble5[0:0].in"/>
+            <direct name="direct2" input="fle.in[4:0]" output="ble5[1:1].in"/>
+            <complete name="direct3" input="fle.clk" output="ble5.clk"/>
+            <direct name="direct4" input="ble5.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- END fle mode of dual lut5 -->
+        <!-- BEGIN arithmetic mode of dual lut4 + adders -->
+        <mode name="arithmetic">
+          <pb_type name="arithmetic" num_pb="2">
+            <input name="in" num_pins="4"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="1"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Special dual-LUT mode that drives adder only -->
+            <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
+              <input name="in" num_pins="4" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  -->
+              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                  195e-12
+                  195e-12
+                  195e-12
+                  195e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
+              <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
+              <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
+              <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
+                </direct>
+              <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
+                </direct>
+              <direct name="add_to_ff" input="adder.sumout" output="ff.D">
+                <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
+              </direct>
+              <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
+                <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
+              </direct>
+              <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
+                <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
+              </direct>
+              <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
+                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[3:0]" output="arithmetic[0:0].in"/>
+            <direct name="direct2" input="fle.in[3:0]" output="arithmetic[1:1].in"/>
+            <direct name="carry_in" input="fle.cin" output="arithmetic[0:0].cin">
+              <pack_pattern name="chain" in_port="fle.cin" out_port="arithmetic[0:0].cin"/>
+            </direct>
+            <direct name="carry_inter" input="arithmetic[0:0].cout" output="arithmetic[1:1].cin">
+              <pack_pattern name="chain" in_port="arithmetic[0:0].cout" out_port="arithmetic[1:1].cin"/>
+            </direct>
+            <direct name="carry_out" input="arithmetic[1:1].cout" output="fle.cout">
+              <pack_pattern name="chain" in_port="arithmetic.cout" out_port="fle.cout"/>
+            </direct>
+            <complete name="direct3" input="fle.clk" output="arithmetic.clk"/>
+            <direct name="direct4" input="arithmetic.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- n2_lut5 -->
+        <mode name="n1_lut6">
+          <pb_type name="ble6" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="6" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->
+              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+              <direct name="direct2" input="lut6.out" output="ff.D">
+                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
+            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+          </interconnect>
+        </mode>
+        <!-- n1_lut6 -->
+      </pb_type>
+      <interconnect>
+        <!-- We use a 50% depop crossbar built using small full xbars to get sets of logically equivalent pins at inputs of CLB 
+           The delays below come from Stratix IV. the delay through a connection block
+           input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+           delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+           delay within the crossbar is 95 ps. 
+           The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+           Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+           25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+           to get the part that should be marked on the crossbar.	 -->
+        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
+          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
+          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
+        </complete>
+
+        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+        </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+                 By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+                 then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+                 naive specification).
+          -->
+        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
+        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
+        <!-- Carry chain links -->
+        <direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
+          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
+        </direct>
+        <direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
+          <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
+        </direct>
+        <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
+          <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
+        </direct>
+      </interconnect>
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+    <!-- Define single-mode dual-port memory begin -->
+    <pb_type name="memory">
+      <input name="waddr" num_pins="10"/>
+      <input name="raddr" num_pins="10"/>
+      <input name="d_in" num_pins="32"/>
+      <input name="wen" num_pins="1"/>
+      <input name="ren" num_pins="1"/>
+      <output name="d_out" num_pins="32"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Specify the 512x32=16Kbit memory block
+           Note: the delay numbers are extracted from VPR flagship XML without modification
+                 Should align to the process technology we using to create the 16K dual-port RAM
+        -->
+      <mode name="mem_512x32_dp">
+        <pb_type name="mem_512x32_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
+          <input name="waddr" num_pins="10" port_class="address"/>
+          <input name="raddr" num_pins="10" port_class="address"/>
+          <input name="d_in" num_pins="32" port_class="data_in"/>
+          <input name="wen" num_pins="1" port_class="write_en"/>
+          <input name="ren" num_pins="1" port_class="write_en"/>
+          <output name="d_out" num_pins="32" port_class="data_out"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.waddr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.raddr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.d_in" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.wen" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.ren" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_512x32_dp.d_out" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="17.9e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="waddress" input="memory.waddr" output="mem_512x32_dp.waddr">
+            <delay_constant max="132e-12" in_port="memory.waddr" out_port="mem_512x32_dp.waddr"/>
+          </direct>
+          <direct name="raddress" input="memory.raddr" output="mem_512x32_dp.raddr">
+            <delay_constant max="132e-12" in_port="memory.raddr" out_port="mem_512x32_dp.raddr"/>
+          </direct>
+          <direct name="data_input" input="memory.d_in" output="mem_512x32_dp.d_in">
+            <delay_constant max="132e-12" in_port="memory.d_in" out_port="mem_512x32_dp.d_in"/>
+          </direct>
+          <direct name="writeen" input="memory.wen" output="mem_512x32_dp.wen">
+            <delay_constant max="132e-12" in_port="memory.wen" out_port="mem_512x32_dp.wen"/>
+          </direct>
+          <direct name="readen" input="memory.ren" output="mem_512x32_dp.ren">
+            <delay_constant max="132e-12" in_port="memory.ren" out_port="mem_512x32_dp.ren"/>
+          </direct>
+          <direct name="dataout" input="mem_512x32_dp.d_out" output="memory.d_out">
+            <delay_constant max="40e-12" in_port="mem_512x32_dp.d_out" out_port="memory.d_out"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_512x32_dp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+    </pb_type>
+    <!-- Define single-mode dual-port memory end -->
+  </complexblocklist>
+</architecture>
diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml
new file mode 100644
index 000000000..6f8c4cfae
--- /dev/null
+++ b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml
@@ -0,0 +1,737 @@
+<!-- 
+  Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with 8 total FLE inputs (2 inputs of which are shared by the 5-LUTs) 
+    with optionally registered outputs
+    Each 5-LUT has an arithemtic mode that converts it to a single-bit adder with both inputs driven by 4-LUTs (both 4-LUTs share all 4 inputs)
+    Carry chain links to vertically adjacent logic blocks
+  - Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.  
+    Height = 6, found on every (8n+2)th column
+  - Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.  
+    Height = 4, found on every (8n+6)th column
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Details on Modelling:
+
+  The electrical design of the architecture described here is NOT from an 
+  optimized, SPICED architecture.  Instead, we attempt to create a reasonable 
+  architecture file by using an existing commercial FPGA to approximate the area, 
+  delay, and power of the underlying components. This is combined with a reasonable 40 nm 
+  model of wiring and circuit design for low-level routing components, where available.
+  The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also 
+  has wiring electrical parameters that allow the wire lengths and switch patterns to be 
+  modified and you will still get reasonable delay results for the new architecture.
+  The following describes, in detail, how we obtained the various electrical values for this 
+  architecture.
+
+  Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar 
+  architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture. 
+  (n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)      
+  This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to 
+  match the overall target (a 40 nm FPGA).
+
+  We obtain delay numbers by measuring delays of routing, soft logic blocks, 
+  memories, and multipliers from test circuits on a Stratix IV GX device 
+  (EP4SGX230DF29C2X, i.e. fastest speed grade). For routing, we took the average delay of H4 and V4 
+  wires.  Rmetal and Cmetal values for the routing wires were obtained from work done by Charles 
+  Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal stack 40 nm routing) and 
+  take the R and C data from the ITRS roadmap.  
+
+  For the general purpose logic block, we assume that the area and delays of the Stratix IV 
+  crossbar is close enough to the crossbar modelled here.  
+  Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to 
+  36:1 multiplexers.  We match these parameters in this architecture.
+
+  For LUTs, we include LUT 
+  delays measured from Stratix IV which is dependant on the input used (ie. some 
+  LUT inputs are faster than others).  The CAD tools at the time of VTR 7 does 
+  not consider differences in LUT input delays.
+
+  Adder delays obtained as approximate values from a Stratix IV EP4SE230F29C3 device.  
+  Delay obtained by compiling a 256 bit adder (registered inputs and outputs, 
+  all pins except clock virtual) then measuring the delays in chip-planner, 
+  sumout delay = 0.271ns to 0.348 ns, intra-block carry delay = 0.011 ns, 
+  inter-block carry delay = 0.327 ns.  Given this data, I will approximate 
+  sumout 0.3 ns, intra-block carry-delay = 0.01 ns, and 
+  inter-block carry-delay = 0.16 ns (since Altera inter-block carry delay has 
+  overhead that we don't have, I'll approximate the delay of a simpler chain at 
+  one half what they have.  This is very rough, anything from 0.01ns to 0.327ns 
+  can be justified).
+
+  Logic block area numbers obtained by scaling overall tile area of a 65nm 
+  Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out 
+  routing area at a channel width of 300. We use a channel width of 300 because it can route 
+  all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
+  total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
+  choosing a width that provides high routability. The architecture can be routed at different channel
+  widths, but we estimate the tile size and hence the physical length of routing wires assuming
+  a channel width of 300.
+
+  Sanity checks employed:
+    1.  We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches 
+        common electrical design.
+
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <model name="adder">
+      <input_ports>
+        <port name="a" combinational_sink_ports="sumout cout"/>
+        <port name="b" combinational_sink_ports="sumout cout"/>
+        <port name="cin" combinational_sink_ports="sumout cout"/>
+      </input_ports>
+      <output_ports>
+        <port name="cout"/>
+        <port name="sumout"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="frac_lut6">
+      <input_ports>
+        <port name="in"/>
+      </input_ports>
+      <output_ports>
+        <port name="lut4_out"/>
+        <port name="lut5_out"/>
+        <port name="lut6_out"/>
+      </output_ports>
+    </model>
+    <model name="dual_port_ram">
+      <input_ports>
+        <!-- write address lines -->
+        <port name="waddr" clock="clk"/>
+        <!-- read address lines -->
+        <port name="raddr" clock="clk"/>
+        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
+        <port name="d_in" clock="clk"/>
+        <!-- write enable -->
+        <port name="wen" clock="clk"/>
+        <!-- read enable -->
+        <port name="ren" clock="clk"/>
+        <!-- memories are often clocked -->
+        <port name="clk" is_clock="1"/>
+      </input_ports>
+      <output_ports>
+        <!-- output can be broken down into smaller bit widths minimum size 1 -->
+        <port name="d_out" clock="clk"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <tile name="io" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad</loc>
+        <loc side="top">io.outpad io.inpad</loc>
+        <loc side="right">io.outpad io.inpad</loc>
+        <loc side="bottom">io.outpad io.inpad</loc>
+      </pinlocations>
+    </tile>
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
+      </fc>
+      <!--  Highly recommand to customize pin location when direct connection is used!!! -->
+      <!--pinlocations pattern="spread"/-->
+      <pinlocations pattern="custom">
+        <loc side="left">clb.clk</loc>
+        <loc side="top">clb.cin</loc>
+        <loc side="right">clb.O[9:0] clb.I[19:0]</loc>
+        <loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
+      </pinlocations>
+    </tile>
+    <tile name="memory" height="2" area="548000">
+      <equivalent_sites>
+        <site pb_type="memory"/>
+      </equivalent_sites>
+      <input name="waddr" num_pins="10"/>
+      <input name="raddr" num_pins="10"/>
+      <input name="d_in" num_pins="32"/>
+      <input name="wen" num_pins="1"/>
+      <input name="ren" num_pins="1"/>
+      <output name="d_out" num_pins="32"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="spread"/>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout tileable="true" through_channel="false">
+    <!--auto_layout aspect_ratio="1.0"-->
+    <fixed_layout name="4x4" width="7" height="6">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="10"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="1"/>
+      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
+      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
+      <row type="EMPTY" starty="H-1" priority="11"/>
+      <row type="EMPTY" starty="0" priority="11"/>
+      <!-- Single instance of an AIB interface -->
+    </fixed_layout>
+    <!-- /auto_layout -->
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	    -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+           book area formula. This means the mux transistors are about 5x minimum drive strength.
+           We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+           mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+           the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+           by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+           buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+           I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+           (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+           The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+           2.5x when looking up in Jeff's tables.
+           Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+           This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+             With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+             reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <directlist>
+    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
+  </directlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+
+      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+           If you need to register the I/O, define clocks in the circuit models
+           These clocks can be handled in back-end
+       -->
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" disabled_in_pack="true">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe fracturable logic element.  
+             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
+             The outputs of the fracturable logic element can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="10">
+        <input name="in" num_pins="6"/>
+        <input name="cin" num_pins="1"/>
+        <output name="out" num_pins="2"/>
+        <output name="cout" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- Physical mode definition begin (physical implementation of the fle) -->
+        <mode name="physical" disabled_in_pack="true">
+          <pb_type name="fabric" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="frac_logic" num_pb="1">
+              <input name="in" num_pins="6"/>
+              <output name="lut4_out" num_pins="4"/>
+              <output name="out" num_pins="2"/>
+              <!-- Define LUT -->
+              <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
+                <input name="in" num_pins="6"/>
+                <output name="lut4_out" num_pins="4"/>
+                <output name="lut5_out" num_pins="2"/>
+                <output name="lut6_out" num_pins="1"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
+                <direct name="direct2" input="frac_lut6.lut4_out" output="frac_logic.lut4_out"/>
+                <direct name="direct3" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
+                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
+                <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
+              </interconnect>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>         
+            <!-- Define adders -->
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="2">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
+              <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
+              <direct name="direct3" input="fabric.cin" output="adder[0:0].cin"/>
+              <direct name="direct4" input="adder[0:0].cout" output="adder[1:1].cin"/>
+              <direct name="direct5" input="adder[1:1].cout" output="fabric.cout"/>
+              <direct name="direct6" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
+              <direct name="direct7" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
+              <direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
+              <direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
+              <complete name="direct10" input="fabric.clk" output="ff[1:0].clk"/>
+              <mux name="mux1" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
+                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
+              </mux>
+              <mux name="mux2" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
+                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="fabric.in"/>
+            <direct name="direct2" input="fle.cin" output="fabric.cin"/>
+            <direct name="direct3" input="fabric.out" output="fle.out"/>
+            <direct name="direct4" input="fabric.cout" output="fle.cout"/>
+            <direct name="direct5" input="fle.clk" output="fabric.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Physical mode definition end (physical implementation of the fle) -->
+        <!-- BEGIN fle mode of dual lut5 -->
+        <mode name="n2_lut5">
+          <pb_type name="ble5" num_pb="2">
+            <input name="in" num_pins="5"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Regular LUT mode -->
+            <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="5" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                  we instead take the average of these numbers to get more stable results
+                82e-12
+                173e-12
+                261e-12
+                263e-12
+                398e-12
+                -->
+              <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+              </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble5.in" output="lut5.in"/>
+              <direct name="direct2" input="lut5.out" output="ff.D">
+                <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble5.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut5.out" output="ble5.out">
+                <delay_constant max="25e-12" in_port="lut5.out" out_port="ble5.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble5.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[4:0]" output="ble5[0:0].in"/>
+            <direct name="direct2" input="fle.in[4:0]" output="ble5[1:1].in"/>
+            <complete name="direct3" input="fle.clk" output="ble5.clk"/>
+            <direct name="direct4" input="ble5.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- END fle mode of dual lut5 -->
+        <!-- BEGIN arithmetic mode of dual lut4 + adders -->
+        <mode name="arithmetic">
+          <pb_type name="arithmetic" num_pb="2">
+            <input name="in" num_pins="4"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="1"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Special dual-LUT mode that drives adder only -->
+            <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
+              <input name="in" num_pins="4" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  -->
+              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                  195e-12
+                  195e-12
+                  195e-12
+                  195e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
+              <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
+              <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
+              <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
+                </direct>
+              <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
+                </direct>
+              <direct name="add_to_ff" input="adder.sumout" output="ff.D">
+                <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
+              </direct>
+              <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
+                <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
+              </direct>
+              <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
+                <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
+              </direct>
+              <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
+                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[3:0]" output="arithmetic[0:0].in"/>
+            <direct name="direct2" input="fle.in[3:0]" output="arithmetic[1:1].in"/>
+            <direct name="carry_in" input="fle.cin" output="arithmetic[0:0].cin">
+              <pack_pattern name="chain" in_port="fle.cin" out_port="arithmetic[0:0].cin"/>
+            </direct>
+            <direct name="carry_inter" input="arithmetic[0:0].cout" output="arithmetic[1:1].cin">
+              <pack_pattern name="chain" in_port="arithmetic[0:0].cout" out_port="arithmetic[1:1].cin"/>
+            </direct>
+            <direct name="carry_out" input="arithmetic[1:1].cout" output="fle.cout">
+              <pack_pattern name="chain" in_port="arithmetic.cout" out_port="fle.cout"/>
+            </direct>
+            <complete name="direct3" input="fle.clk" output="arithmetic.clk"/>
+            <direct name="direct4" input="arithmetic.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- n2_lut5 -->
+        <mode name="n1_lut6">
+          <pb_type name="ble6" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="6" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->
+              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+              <direct name="direct2" input="lut6.out" output="ff.D">
+                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
+            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+          </interconnect>
+        </mode>
+        <!-- n1_lut6 -->
+      </pb_type>
+      <interconnect>
+        <!-- We use a 50% depop crossbar built using small full xbars to get sets of logically equivalent pins at inputs of CLB 
+           The delays below come from Stratix IV. the delay through a connection block
+           input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+           delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+           delay within the crossbar is 95 ps. 
+           The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+           Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+           25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+           to get the part that should be marked on the crossbar.	 -->
+        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
+          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
+          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
+        </complete>
+
+        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+        </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+                 By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+                 then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+                 naive specification).
+          -->
+        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
+        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
+        <!-- Carry chain links -->
+        <direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
+          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
+        </direct>
+        <direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
+          <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
+        </direct>
+        <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
+          <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
+        </direct>
+      </interconnect>
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+    <!-- Define single-mode dual-port memory begin -->
+    <pb_type name="memory">
+      <input name="waddr" num_pins="10"/>
+      <input name="raddr" num_pins="10"/>
+      <input name="d_in" num_pins="32"/>
+      <input name="wen" num_pins="1"/>
+      <input name="ren" num_pins="1"/>
+      <output name="d_out" num_pins="32"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Specify the 512x32=16Kbit memory block
+           Note: the delay numbers are extracted from VPR flagship XML without modification
+                 Should align to the process technology we using to create the 16K dual-port RAM
+        -->
+      <mode name="mem_512x32_dp">
+        <pb_type name="mem_512x32_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
+          <input name="waddr" num_pins="10" port_class="address"/>
+          <input name="raddr" num_pins="10" port_class="address"/>
+          <input name="d_in" num_pins="32" port_class="data_in"/>
+          <input name="wen" num_pins="1" port_class="write_en"/>
+          <input name="ren" num_pins="1" port_class="write_en"/>
+          <output name="d_out" num_pins="32" port_class="data_out"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.waddr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.raddr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.d_in" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.wen" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.ren" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_512x32_dp.d_out" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="17.9e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="waddress" input="memory.waddr" output="mem_512x32_dp.waddr">
+            <delay_constant max="132e-12" in_port="memory.waddr" out_port="mem_512x32_dp.waddr"/>
+          </direct>
+          <direct name="raddress" input="memory.raddr" output="mem_512x32_dp.raddr">
+            <delay_constant max="132e-12" in_port="memory.raddr" out_port="mem_512x32_dp.raddr"/>
+          </direct>
+          <direct name="data_input" input="memory.d_in" output="mem_512x32_dp.d_in">
+            <delay_constant max="132e-12" in_port="memory.d_in" out_port="mem_512x32_dp.d_in"/>
+          </direct>
+          <direct name="writeen" input="memory.wen" output="mem_512x32_dp.wen">
+            <delay_constant max="132e-12" in_port="memory.wen" out_port="mem_512x32_dp.wen"/>
+          </direct>
+          <direct name="readen" input="memory.ren" output="mem_512x32_dp.ren">
+            <delay_constant max="132e-12" in_port="memory.ren" out_port="mem_512x32_dp.ren"/>
+          </direct>
+          <direct name="dataout" input="mem_512x32_dp.d_out" output="memory.d_out">
+            <delay_constant max="40e-12" in_port="mem_512x32_dp.d_out" out_port="memory.d_out"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_512x32_dp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+    </pb_type>
+    <!-- Define single-mode dual-port memory end -->
+  </complexblocklist>
+</architecture>
diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml
new file mode 100644
index 000000000..f07f16c80
--- /dev/null
+++ b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml
@@ -0,0 +1,734 @@
+<!-- 
+  Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with 8 total FLE inputs (2 inputs of which are shared by the 5-LUTs) 
+    with optionally registered outputs
+    Each 5-LUT has an arithemtic mode that converts it to a single-bit adder with both inputs driven by 4-LUTs (both 4-LUTs share all 4 inputs)
+    Carry chain links to vertically adjacent logic blocks
+  - Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.  
+    Height = 6, found on every (8n+2)th column
+  - Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.  
+    Height = 4, found on every (8n+6)th column
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Details on Modelling:
+
+  The electrical design of the architecture described here is NOT from an 
+  optimized, SPICED architecture.  Instead, we attempt to create a reasonable 
+  architecture file by using an existing commercial FPGA to approximate the area, 
+  delay, and power of the underlying components. This is combined with a reasonable 40 nm 
+  model of wiring and circuit design for low-level routing components, where available.
+  The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also 
+  has wiring electrical parameters that allow the wire lengths and switch patterns to be 
+  modified and you will still get reasonable delay results for the new architecture.
+  The following describes, in detail, how we obtained the various electrical values for this 
+  architecture.
+
+  Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar 
+  architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture. 
+  (n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)      
+  This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to 
+  match the overall target (a 40 nm FPGA).
+
+  We obtain delay numbers by measuring delays of routing, soft logic blocks, 
+  memories, and multipliers from test circuits on a Stratix IV GX device 
+  (EP4SGX230DF29C2X, i.e. fastest speed grade). For routing, we took the average delay of H4 and V4 
+  wires.  Rmetal and Cmetal values for the routing wires were obtained from work done by Charles 
+  Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal stack 40 nm routing) and 
+  take the R and C data from the ITRS roadmap.  
+
+  For the general purpose logic block, we assume that the area and delays of the Stratix IV 
+  crossbar is close enough to the crossbar modelled here.  
+  Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to 
+  36:1 multiplexers.  We match these parameters in this architecture.
+
+  For LUTs, we include LUT 
+  delays measured from Stratix IV which is dependant on the input used (ie. some 
+  LUT inputs are faster than others).  The CAD tools at the time of VTR 7 does 
+  not consider differences in LUT input delays.
+
+  Adder delays obtained as approximate values from a Stratix IV EP4SE230F29C3 device.  
+  Delay obtained by compiling a 256 bit adder (registered inputs and outputs, 
+  all pins except clock virtual) then measuring the delays in chip-planner, 
+  sumout delay = 0.271ns to 0.348 ns, intra-block carry delay = 0.011 ns, 
+  inter-block carry delay = 0.327 ns.  Given this data, I will approximate 
+  sumout 0.3 ns, intra-block carry-delay = 0.01 ns, and 
+  inter-block carry-delay = 0.16 ns (since Altera inter-block carry delay has 
+  overhead that we don't have, I'll approximate the delay of a simpler chain at 
+  one half what they have.  This is very rough, anything from 0.01ns to 0.327ns 
+  can be justified).
+
+  Logic block area numbers obtained by scaling overall tile area of a 65nm 
+  Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out 
+  routing area at a channel width of 300. We use a channel width of 300 because it can route 
+  all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
+  total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
+  choosing a width that provides high routability. The architecture can be routed at different channel
+  widths, but we estimate the tile size and hence the physical length of routing wires assuming
+  a channel width of 300.
+
+  Sanity checks employed:
+    1.  We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches 
+        common electrical design.
+
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <model name="adder">
+      <input_ports>
+        <port name="a" combinational_sink_ports="sumout cout"/>
+        <port name="b" combinational_sink_ports="sumout cout"/>
+        <port name="cin" combinational_sink_ports="sumout cout"/>
+      </input_ports>
+      <output_ports>
+        <port name="cout"/>
+        <port name="sumout"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="frac_lut6">
+      <input_ports>
+        <port name="in"/>
+      </input_ports>
+      <output_ports>
+        <port name="lut4_out"/>
+        <port name="lut5_out"/>
+        <port name="lut6_out"/>
+      </output_ports>
+    </model>
+    <model name="dual_port_ram">
+      <input_ports>
+        <!-- write address lines -->
+        <port name="waddr" clock="clk"/>
+        <!-- read address lines -->
+        <port name="raddr" clock="clk"/>
+        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
+        <port name="d_in" clock="clk"/>
+        <!-- write enable -->
+        <port name="wen" clock="clk"/>
+        <!-- read enable -->
+        <port name="ren" clock="clk"/>
+        <!-- memories are often clocked -->
+        <port name="clk" is_clock="1"/>
+      </input_ports>
+      <output_ports>
+        <!-- output can be broken down into smaller bit widths minimum size 1 -->
+        <port name="d_out" clock="clk"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <tile name="io" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad</loc>
+        <loc side="top">io.outpad io.inpad</loc>
+        <loc side="right">io.outpad io.inpad</loc>
+        <loc side="bottom">io.outpad io.inpad</loc>
+      </pinlocations>
+    </tile>
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
+      </fc>
+      <!--  Highly recommand to customize pin location when direct connection is used!!! -->
+      <!--pinlocations pattern="spread"/-->
+      <pinlocations pattern="custom">
+        <loc side="left">clb.clk</loc>
+        <loc side="top">clb.cin</loc>
+        <loc side="right">clb.O[9:0] clb.I[19:0]</loc>
+        <loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
+      </pinlocations>
+    </tile>
+    <tile name="memory" width="2" height="2" area="548000">
+      <equivalent_sites>
+        <site pb_type="memory"/>
+      </equivalent_sites>
+      <input name="waddr" num_pins="10"/>
+      <input name="raddr" num_pins="10"/>
+      <input name="d_in" num_pins="32"/>
+      <input name="wen" num_pins="1"/>
+      <input name="ren" num_pins="1"/>
+      <output name="d_out" num_pins="32"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="spread"/>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout tileable="true" through_channel="false">
+    <!--auto_layout aspect_ratio="1.0"-->
+    <fixed_layout name="4x4" width="6" height="6">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
+      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
+    </fixed_layout>
+    <!-- /auto_layout -->
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	    -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+           book area formula. This means the mux transistors are about 5x minimum drive strength.
+           We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+           mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+           the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+           by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+           buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+           I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+           (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+           The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+           2.5x when looking up in Jeff's tables.
+           Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+           This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+             With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+             reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <directlist>
+    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
+  </directlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+
+      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+           If you need to register the I/O, define clocks in the circuit models
+           These clocks can be handled in back-end
+       -->
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" disabled_in_pack="true">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe fracturable logic element.  
+             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
+             The outputs of the fracturable logic element can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="10">
+        <input name="in" num_pins="6"/>
+        <input name="cin" num_pins="1"/>
+        <output name="out" num_pins="2"/>
+        <output name="cout" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- Physical mode definition begin (physical implementation of the fle) -->
+        <mode name="physical" disabled_in_pack="true">
+          <pb_type name="fabric" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="frac_logic" num_pb="1">
+              <input name="in" num_pins="6"/>
+              <output name="lut4_out" num_pins="4"/>
+              <output name="out" num_pins="2"/>
+              <!-- Define LUT -->
+              <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
+                <input name="in" num_pins="6"/>
+                <output name="lut4_out" num_pins="4"/>
+                <output name="lut5_out" num_pins="2"/>
+                <output name="lut6_out" num_pins="1"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
+                <direct name="direct2" input="frac_lut6.lut4_out" output="frac_logic.lut4_out"/>
+                <direct name="direct3" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
+                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
+                <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
+              </interconnect>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>         
+            <!-- Define adders -->
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="2">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
+              <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
+              <direct name="direct3" input="fabric.cin" output="adder[0:0].cin"/>
+              <direct name="direct4" input="adder[0:0].cout" output="adder[1:1].cin"/>
+              <direct name="direct5" input="adder[1:1].cout" output="fabric.cout"/>
+              <direct name="direct6" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
+              <direct name="direct7" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
+              <direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
+              <direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
+              <complete name="direct10" input="fabric.clk" output="ff[1:0].clk"/>
+              <mux name="mux1" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
+                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
+              </mux>
+              <mux name="mux2" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
+                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="fabric.in"/>
+            <direct name="direct2" input="fle.cin" output="fabric.cin"/>
+            <direct name="direct3" input="fabric.out" output="fle.out"/>
+            <direct name="direct4" input="fabric.cout" output="fle.cout"/>
+            <direct name="direct5" input="fle.clk" output="fabric.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Physical mode definition end (physical implementation of the fle) -->
+        <!-- BEGIN fle mode of dual lut5 -->
+        <mode name="n2_lut5">
+          <pb_type name="ble5" num_pb="2">
+            <input name="in" num_pins="5"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Regular LUT mode -->
+            <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="5" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                  we instead take the average of these numbers to get more stable results
+                82e-12
+                173e-12
+                261e-12
+                263e-12
+                398e-12
+                -->
+              <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+              </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble5.in" output="lut5.in"/>
+              <direct name="direct2" input="lut5.out" output="ff.D">
+                <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble5.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut5.out" output="ble5.out">
+                <delay_constant max="25e-12" in_port="lut5.out" out_port="ble5.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble5.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[4:0]" output="ble5[0:0].in"/>
+            <direct name="direct2" input="fle.in[4:0]" output="ble5[1:1].in"/>
+            <complete name="direct3" input="fle.clk" output="ble5.clk"/>
+            <direct name="direct4" input="ble5.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- END fle mode of dual lut5 -->
+        <!-- BEGIN arithmetic mode of dual lut4 + adders -->
+        <mode name="arithmetic">
+          <pb_type name="arithmetic" num_pb="2">
+            <input name="in" num_pins="4"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="1"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Special dual-LUT mode that drives adder only -->
+            <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
+              <input name="in" num_pins="4" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  -->
+              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                  195e-12
+                  195e-12
+                  195e-12
+                  195e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
+              <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
+              <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
+              <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
+                </direct>
+              <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
+                </direct>
+              <direct name="add_to_ff" input="adder.sumout" output="ff.D">
+                <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
+              </direct>
+              <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
+                <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
+              </direct>
+              <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
+                <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
+              </direct>
+              <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
+                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[3:0]" output="arithmetic[0:0].in"/>
+            <direct name="direct2" input="fle.in[3:0]" output="arithmetic[1:1].in"/>
+            <direct name="carry_in" input="fle.cin" output="arithmetic[0:0].cin">
+              <pack_pattern name="chain" in_port="fle.cin" out_port="arithmetic[0:0].cin"/>
+            </direct>
+            <direct name="carry_inter" input="arithmetic[0:0].cout" output="arithmetic[1:1].cin">
+              <pack_pattern name="chain" in_port="arithmetic[0:0].cout" out_port="arithmetic[1:1].cin"/>
+            </direct>
+            <direct name="carry_out" input="arithmetic[1:1].cout" output="fle.cout">
+              <pack_pattern name="chain" in_port="arithmetic.cout" out_port="fle.cout"/>
+            </direct>
+            <complete name="direct3" input="fle.clk" output="arithmetic.clk"/>
+            <direct name="direct4" input="arithmetic.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- n2_lut5 -->
+        <mode name="n1_lut6">
+          <pb_type name="ble6" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="6" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->
+              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+              <direct name="direct2" input="lut6.out" output="ff.D">
+                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
+            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+          </interconnect>
+        </mode>
+        <!-- n1_lut6 -->
+      </pb_type>
+      <interconnect>
+        <!-- We use a 50% depop crossbar built using small full xbars to get sets of logically equivalent pins at inputs of CLB 
+           The delays below come from Stratix IV. the delay through a connection block
+           input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+           delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+           delay within the crossbar is 95 ps. 
+           The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+           Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+           25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+           to get the part that should be marked on the crossbar.	 -->
+        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
+          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
+          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
+        </complete>
+
+        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+        </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+                 By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+                 then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+                 naive specification).
+          -->
+        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
+        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
+        <!-- Carry chain links -->
+        <direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
+          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
+        </direct>
+        <direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
+          <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
+        </direct>
+        <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
+          <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
+        </direct>
+      </interconnect>
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+    <!-- Define single-mode dual-port memory begin -->
+    <pb_type name="memory">
+      <input name="waddr" num_pins="10"/>
+      <input name="raddr" num_pins="10"/>
+      <input name="d_in" num_pins="32"/>
+      <input name="wen" num_pins="1"/>
+      <input name="ren" num_pins="1"/>
+      <output name="d_out" num_pins="32"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Specify the 512x32=16Kbit memory block
+           Note: the delay numbers are extracted from VPR flagship XML without modification
+                 Should align to the process technology we using to create the 16K dual-port RAM
+        -->
+      <mode name="mem_512x32_dp">
+        <pb_type name="mem_512x32_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
+          <input name="waddr" num_pins="10" port_class="address"/>
+          <input name="raddr" num_pins="10" port_class="address"/>
+          <input name="d_in" num_pins="32" port_class="data_in"/>
+          <input name="wen" num_pins="1" port_class="write_en"/>
+          <input name="ren" num_pins="1" port_class="write_en"/>
+          <output name="d_out" num_pins="32" port_class="data_out"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.waddr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.raddr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.d_in" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.wen" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.ren" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_512x32_dp.d_out" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="17.9e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="waddress" input="memory.waddr" output="mem_512x32_dp.waddr">
+            <delay_constant max="132e-12" in_port="memory.waddr" out_port="mem_512x32_dp.waddr"/>
+          </direct>
+          <direct name="raddress" input="memory.raddr" output="mem_512x32_dp.raddr">
+            <delay_constant max="132e-12" in_port="memory.raddr" out_port="mem_512x32_dp.raddr"/>
+          </direct>
+          <direct name="data_input" input="memory.d_in" output="mem_512x32_dp.d_in">
+            <delay_constant max="132e-12" in_port="memory.d_in" out_port="mem_512x32_dp.d_in"/>
+          </direct>
+          <direct name="writeen" input="memory.wen" output="mem_512x32_dp.wen">
+            <delay_constant max="132e-12" in_port="memory.wen" out_port="mem_512x32_dp.wen"/>
+          </direct>
+          <direct name="readen" input="memory.ren" output="mem_512x32_dp.ren">
+            <delay_constant max="132e-12" in_port="memory.ren" out_port="mem_512x32_dp.ren"/>
+          </direct>
+          <direct name="dataout" input="mem_512x32_dp.d_out" output="memory.d_out">
+            <delay_constant max="40e-12" in_port="mem_512x32_dp.d_out" out_port="memory.d_out"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_512x32_dp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+    </pb_type>
+    <!-- Define single-mode dual-port memory end -->
+  </complexblocklist>
+</architecture>
diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml
new file mode 100644
index 000000000..7e4cf8e7a
--- /dev/null
+++ b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml
@@ -0,0 +1,734 @@
+<!-- 
+  Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with 8 total FLE inputs (2 inputs of which are shared by the 5-LUTs) 
+    with optionally registered outputs
+    Each 5-LUT has an arithemtic mode that converts it to a single-bit adder with both inputs driven by 4-LUTs (both 4-LUTs share all 4 inputs)
+    Carry chain links to vertically adjacent logic blocks
+  - Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.  
+    Height = 6, found on every (8n+2)th column
+  - Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.  
+    Height = 4, found on every (8n+6)th column
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Details on Modelling:
+
+  The electrical design of the architecture described here is NOT from an 
+  optimized, SPICED architecture.  Instead, we attempt to create a reasonable 
+  architecture file by using an existing commercial FPGA to approximate the area, 
+  delay, and power of the underlying components. This is combined with a reasonable 40 nm 
+  model of wiring and circuit design for low-level routing components, where available.
+  The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also 
+  has wiring electrical parameters that allow the wire lengths and switch patterns to be 
+  modified and you will still get reasonable delay results for the new architecture.
+  The following describes, in detail, how we obtained the various electrical values for this 
+  architecture.
+
+  Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar 
+  architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture. 
+  (n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)      
+  This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to 
+  match the overall target (a 40 nm FPGA).
+
+  We obtain delay numbers by measuring delays of routing, soft logic blocks, 
+  memories, and multipliers from test circuits on a Stratix IV GX device 
+  (EP4SGX230DF29C2X, i.e. fastest speed grade). For routing, we took the average delay of H4 and V4 
+  wires.  Rmetal and Cmetal values for the routing wires were obtained from work done by Charles 
+  Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal stack 40 nm routing) and 
+  take the R and C data from the ITRS roadmap.  
+
+  For the general purpose logic block, we assume that the area and delays of the Stratix IV 
+  crossbar is close enough to the crossbar modelled here.  
+  Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to 
+  36:1 multiplexers.  We match these parameters in this architecture.
+
+  For LUTs, we include LUT 
+  delays measured from Stratix IV which is dependant on the input used (ie. some 
+  LUT inputs are faster than others).  The CAD tools at the time of VTR 7 does 
+  not consider differences in LUT input delays.
+
+  Adder delays obtained as approximate values from a Stratix IV EP4SE230F29C3 device.  
+  Delay obtained by compiling a 256 bit adder (registered inputs and outputs, 
+  all pins except clock virtual) then measuring the delays in chip-planner, 
+  sumout delay = 0.271ns to 0.348 ns, intra-block carry delay = 0.011 ns, 
+  inter-block carry delay = 0.327 ns.  Given this data, I will approximate 
+  sumout 0.3 ns, intra-block carry-delay = 0.01 ns, and 
+  inter-block carry-delay = 0.16 ns (since Altera inter-block carry delay has 
+  overhead that we don't have, I'll approximate the delay of a simpler chain at 
+  one half what they have.  This is very rough, anything from 0.01ns to 0.327ns 
+  can be justified).
+
+  Logic block area numbers obtained by scaling overall tile area of a 65nm 
+  Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out 
+  routing area at a channel width of 300. We use a channel width of 300 because it can route 
+  all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
+  total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
+  choosing a width that provides high routability. The architecture can be routed at different channel
+  widths, but we estimate the tile size and hence the physical length of routing wires assuming
+  a channel width of 300.
+
+  Sanity checks employed:
+    1.  We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches 
+        common electrical design.
+
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <model name="adder">
+      <input_ports>
+        <port name="a" combinational_sink_ports="sumout cout"/>
+        <port name="b" combinational_sink_ports="sumout cout"/>
+        <port name="cin" combinational_sink_ports="sumout cout"/>
+      </input_ports>
+      <output_ports>
+        <port name="cout"/>
+        <port name="sumout"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="frac_lut6">
+      <input_ports>
+        <port name="in"/>
+      </input_ports>
+      <output_ports>
+        <port name="lut4_out"/>
+        <port name="lut5_out"/>
+        <port name="lut6_out"/>
+      </output_ports>
+    </model>
+    <model name="dual_port_ram">
+      <input_ports>
+        <!-- write address lines -->
+        <port name="waddr" clock="clk"/>
+        <!-- read address lines -->
+        <port name="raddr" clock="clk"/>
+        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
+        <port name="d_in" clock="clk"/>
+        <!-- write enable -->
+        <port name="wen" clock="clk"/>
+        <!-- read enable -->
+        <port name="ren" clock="clk"/>
+        <!-- memories are often clocked -->
+        <port name="clk" is_clock="1"/>
+      </input_ports>
+      <output_ports>
+        <!-- output can be broken down into smaller bit widths minimum size 1 -->
+        <port name="d_out" clock="clk"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <tile name="io" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad</loc>
+        <loc side="top">io.outpad io.inpad</loc>
+        <loc side="right">io.outpad io.inpad</loc>
+        <loc side="bottom">io.outpad io.inpad</loc>
+      </pinlocations>
+    </tile>
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
+      </fc>
+      <!--  Highly recommand to customize pin location when direct connection is used!!! -->
+      <!--pinlocations pattern="spread"/-->
+      <pinlocations pattern="custom">
+        <loc side="left">clb.clk</loc>
+        <loc side="top">clb.cin</loc>
+        <loc side="right">clb.O[9:0] clb.I[19:0]</loc>
+        <loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
+      </pinlocations>
+    </tile>
+    <tile name="memory" height="2" area="548000">
+      <equivalent_sites>
+        <site pb_type="memory"/>
+      </equivalent_sites>
+      <input name="waddr" num_pins="10"/>
+      <input name="raddr" num_pins="10"/>
+      <input name="d_in" num_pins="32"/>
+      <input name="wen" num_pins="1"/>
+      <input name="ren" num_pins="1"/>
+      <output name="d_out" num_pins="32"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="spread"/>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout tileable="true" through_channel="true">
+    <!--auto_layout aspect_ratio="1.0"-->
+    <fixed_layout name="4x4" width="5" height="4">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
+      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
+    </fixed_layout>
+    <!-- /auto_layout -->
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	    -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+           book area formula. This means the mux transistors are about 5x minimum drive strength.
+           We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+           mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+           the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+           by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+           buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+           I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+           (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+           The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+           2.5x when looking up in Jeff's tables.
+           Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+           This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+             With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+             reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <directlist>
+    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
+  </directlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+
+      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+           If you need to register the I/O, define clocks in the circuit models
+           These clocks can be handled in back-end
+       -->
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" disabled_in_pack="true">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe fracturable logic element.  
+             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
+             The outputs of the fracturable logic element can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="10">
+        <input name="in" num_pins="6"/>
+        <input name="cin" num_pins="1"/>
+        <output name="out" num_pins="2"/>
+        <output name="cout" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- Physical mode definition begin (physical implementation of the fle) -->
+        <mode name="physical" disabled_in_pack="true">
+          <pb_type name="fabric" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="frac_logic" num_pb="1">
+              <input name="in" num_pins="6"/>
+              <output name="lut4_out" num_pins="4"/>
+              <output name="out" num_pins="2"/>
+              <!-- Define LUT -->
+              <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
+                <input name="in" num_pins="6"/>
+                <output name="lut4_out" num_pins="4"/>
+                <output name="lut5_out" num_pins="2"/>
+                <output name="lut6_out" num_pins="1"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
+                <direct name="direct2" input="frac_lut6.lut4_out" output="frac_logic.lut4_out"/>
+                <direct name="direct3" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
+                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
+                <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
+              </interconnect>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>         
+            <!-- Define adders -->
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="2">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
+              <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
+              <direct name="direct3" input="fabric.cin" output="adder[0:0].cin"/>
+              <direct name="direct4" input="adder[0:0].cout" output="adder[1:1].cin"/>
+              <direct name="direct5" input="adder[1:1].cout" output="fabric.cout"/>
+              <direct name="direct6" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
+              <direct name="direct7" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
+              <direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
+              <direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
+              <complete name="direct10" input="fabric.clk" output="ff[1:0].clk"/>
+              <mux name="mux1" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
+                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
+              </mux>
+              <mux name="mux2" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
+                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="fabric.in"/>
+            <direct name="direct2" input="fle.cin" output="fabric.cin"/>
+            <direct name="direct3" input="fabric.out" output="fle.out"/>
+            <direct name="direct4" input="fabric.cout" output="fle.cout"/>
+            <direct name="direct5" input="fle.clk" output="fabric.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Physical mode definition end (physical implementation of the fle) -->
+        <!-- BEGIN fle mode of dual lut5 -->
+        <mode name="n2_lut5">
+          <pb_type name="ble5" num_pb="2">
+            <input name="in" num_pins="5"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Regular LUT mode -->
+            <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="5" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                  we instead take the average of these numbers to get more stable results
+                82e-12
+                173e-12
+                261e-12
+                263e-12
+                398e-12
+                -->
+              <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+              </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble5.in" output="lut5.in"/>
+              <direct name="direct2" input="lut5.out" output="ff.D">
+                <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble5.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut5.out" output="ble5.out">
+                <delay_constant max="25e-12" in_port="lut5.out" out_port="ble5.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble5.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[4:0]" output="ble5[0:0].in"/>
+            <direct name="direct2" input="fle.in[4:0]" output="ble5[1:1].in"/>
+            <complete name="direct3" input="fle.clk" output="ble5.clk"/>
+            <direct name="direct4" input="ble5.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- END fle mode of dual lut5 -->
+        <!-- BEGIN arithmetic mode of dual lut4 + adders -->
+        <mode name="arithmetic">
+          <pb_type name="arithmetic" num_pb="2">
+            <input name="in" num_pins="4"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="1"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Special dual-LUT mode that drives adder only -->
+            <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
+              <input name="in" num_pins="4" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  -->
+              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                  195e-12
+                  195e-12
+                  195e-12
+                  195e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
+              <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
+              <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
+              <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
+                </direct>
+              <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
+                </direct>
+              <direct name="add_to_ff" input="adder.sumout" output="ff.D">
+                <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
+              </direct>
+              <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
+                <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
+              </direct>
+              <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
+                <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
+              </direct>
+              <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
+                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[3:0]" output="arithmetic[0:0].in"/>
+            <direct name="direct2" input="fle.in[3:0]" output="arithmetic[1:1].in"/>
+            <direct name="carry_in" input="fle.cin" output="arithmetic[0:0].cin">
+              <pack_pattern name="chain" in_port="fle.cin" out_port="arithmetic[0:0].cin"/>
+            </direct>
+            <direct name="carry_inter" input="arithmetic[0:0].cout" output="arithmetic[1:1].cin">
+              <pack_pattern name="chain" in_port="arithmetic[0:0].cout" out_port="arithmetic[1:1].cin"/>
+            </direct>
+            <direct name="carry_out" input="arithmetic[1:1].cout" output="fle.cout">
+              <pack_pattern name="chain" in_port="arithmetic.cout" out_port="fle.cout"/>
+            </direct>
+            <complete name="direct3" input="fle.clk" output="arithmetic.clk"/>
+            <direct name="direct4" input="arithmetic.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- n2_lut5 -->
+        <mode name="n1_lut6">
+          <pb_type name="ble6" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="6" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->
+              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+              <direct name="direct2" input="lut6.out" output="ff.D">
+                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
+            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+          </interconnect>
+        </mode>
+        <!-- n1_lut6 -->
+      </pb_type>
+      <interconnect>
+        <!-- We use a 50% depop crossbar built using small full xbars to get sets of logically equivalent pins at inputs of CLB 
+           The delays below come from Stratix IV. the delay through a connection block
+           input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+           delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+           delay within the crossbar is 95 ps. 
+           The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+           Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+           25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+           to get the part that should be marked on the crossbar.	 -->
+        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
+          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
+          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
+        </complete>
+
+        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+        </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+                 By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+                 then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+                 naive specification).
+          -->
+        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
+        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
+        <!-- Carry chain links -->
+        <direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
+          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
+        </direct>
+        <direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
+          <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
+        </direct>
+        <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
+          <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
+        </direct>
+      </interconnect>
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+    <!-- Define single-mode dual-port memory begin -->
+    <pb_type name="memory">
+      <input name="waddr" num_pins="10"/>
+      <input name="raddr" num_pins="10"/>
+      <input name="d_in" num_pins="32"/>
+      <input name="wen" num_pins="1"/>
+      <input name="ren" num_pins="1"/>
+      <output name="d_out" num_pins="32"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Specify the 512x32=16Kbit memory block
+           Note: the delay numbers are extracted from VPR flagship XML without modification
+                 Should align to the process technology we using to create the 16K dual-port RAM
+        -->
+      <mode name="mem_512x32_dp">
+        <pb_type name="mem_512x32_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
+          <input name="waddr" num_pins="10" port_class="address"/>
+          <input name="raddr" num_pins="10" port_class="address"/>
+          <input name="d_in" num_pins="32" port_class="data_in"/>
+          <input name="wen" num_pins="1" port_class="write_en"/>
+          <input name="ren" num_pins="1" port_class="write_en"/>
+          <output name="d_out" num_pins="32" port_class="data_out"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.waddr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.raddr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.d_in" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.wen" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.ren" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_512x32_dp.d_out" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="17.9e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="waddress" input="memory.waddr" output="mem_512x32_dp.waddr">
+            <delay_constant max="132e-12" in_port="memory.waddr" out_port="mem_512x32_dp.waddr"/>
+          </direct>
+          <direct name="raddress" input="memory.raddr" output="mem_512x32_dp.raddr">
+            <delay_constant max="132e-12" in_port="memory.raddr" out_port="mem_512x32_dp.raddr"/>
+          </direct>
+          <direct name="data_input" input="memory.d_in" output="mem_512x32_dp.d_in">
+            <delay_constant max="132e-12" in_port="memory.d_in" out_port="mem_512x32_dp.d_in"/>
+          </direct>
+          <direct name="writeen" input="memory.wen" output="mem_512x32_dp.wen">
+            <delay_constant max="132e-12" in_port="memory.wen" out_port="mem_512x32_dp.wen"/>
+          </direct>
+          <direct name="readen" input="memory.ren" output="mem_512x32_dp.ren">
+            <delay_constant max="132e-12" in_port="memory.ren" out_port="mem_512x32_dp.ren"/>
+          </direct>
+          <direct name="dataout" input="mem_512x32_dp.d_out" output="memory.d_out">
+            <delay_constant max="40e-12" in_port="mem_512x32_dp.d_out" out_port="memory.d_out"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_512x32_dp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+    </pb_type>
+    <!-- Define single-mode dual-port memory end -->
+  </complexblocklist>
+</architecture>
diff --git a/openfpga_flow/benchmarks/micro_benchmark/and.act b/openfpga_flow/benchmarks/micro_benchmark/and.act
new file mode 100644
index 000000000..0f77bc6b3
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/and.act
@@ -0,0 +1,3 @@
+a 0.5 0.5
+b 0.5 0.5
+c 0.25 0.25
diff --git a/openfpga_flow/benchmarks/micro_benchmark/and.blif b/openfpga_flow/benchmarks/micro_benchmark/and.blif
new file mode 100644
index 000000000..67d978741
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/and.blif
@@ -0,0 +1,8 @@
+.model top
+.inputs a b
+.outputs c
+
+.names a b c
+11 1
+
+.end
diff --git a/openfpga_flow/benchmarks/micro_benchmark/and.v b/openfpga_flow/benchmarks/micro_benchmark/and.v
new file mode 100644
index 000000000..876f1c6fe
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/and.v
@@ -0,0 +1,14 @@
+`timescale 1ns / 1ps
+
+module top(
+  a,
+  b,
+  c);
+
+input wire a;
+input wire b;
+output wire c;
+
+assign c = a & b;
+
+endmodule
diff --git a/openfpga_flow/benchmarks/micro_benchmark/and_latch.act b/openfpga_flow/benchmarks/micro_benchmark/and_latch.act
new file mode 100644
index 000000000..61bbe1fe8
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/and_latch.act
@@ -0,0 +1,6 @@
+a 0.492800 0.201000
+b 0.502000 0.197200
+clk 0.500000 2.000000
+d 0.240200 0.171200
+c 0.240200 0.044100
+n1 0.240200 0.044100
diff --git a/openfpga_flow/benchmarks/micro_benchmark/and_latch.blif b/openfpga_flow/benchmarks/micro_benchmark/and_latch.blif
new file mode 100644
index 000000000..dbd863d9c
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/and_latch.blif
@@ -0,0 +1,14 @@
+# Benchmark "top" written by ABC on Wed Mar 11 10:36:28 2020
+.model top
+.inputs a b clk
+.outputs c d
+
+.latch n1 d  re clk 0
+
+.names a b c
+11 1
+
+.names c n1
+1 1
+
+.end
diff --git a/openfpga_flow/benchmarks/micro_benchmark/and_latch.v b/openfpga_flow/benchmarks/micro_benchmark/and_latch.v
new file mode 100644
index 000000000..893cdf7a4
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/and_latch.v
@@ -0,0 +1,23 @@
+`timescale 1ns / 1ps
+
+module top(
+  clk,
+  a,
+  b,
+  c,
+  d);
+
+input wire clk;
+
+input wire a;
+input wire b;
+output wire c;
+output reg d;
+
+assign c = a & b;
+
+always @(posedge clk) begin
+  d <= c;
+end
+
+endmodule
diff --git a/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml
new file mode 100644
index 000000000..d93495f6b
--- /dev/null
+++ b/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml
@@ -0,0 +1,234 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <!--mux2to1 subckt_name="mux2to1"/-->
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <!--mux2to1 subckt_name="mux2to1"/-->
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <!--mux2to1 subckt_name="mux2to1"/-->
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <pass_gate_logic circuit_model_name="TGATE"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="lut6" prefix="lut6" dump_structural_verilog="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="6"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="64"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <pass_gate_logic circuit_model_name="TGATE"/>
+       <port type="input" prefix="pReset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="Qb" size="1"/>
+       <port type="clock" prefix="prog_clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="inout" prefix="pad" size="1"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+      <port type="input" prefix="outpad" size="1"/>
+      <port type="output" prefix="inpad" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut6].ble6.lut6" circuit_model_name="lut6"/>
+    <pb_type name="clb.fle[n1_lut6].ble6.ff" circuit_model_name="static_dff"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>
+<openfpga_simulation_setting>
+  <clock_setting>
+    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
+    <programming frequency="10e6"/>
+  </clock_setting>
+  <simulator_option>
+    <operating_condition temperature="25"/>
+    <output_log verbose="false" captab="false"/>
+    <accuracy type="abs" value="1e-13"/>
+    <runtime fast_simulation="true"/>
+  </simulator_option>
+  <monte_carlo num_simulation_points="2"/>
+  <measurement_setting>
+    <slew>
+      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
+      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
+    </slew>
+    <delay>
+      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
+      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
+    </delay>
+  </measurement_setting>
+  <stimulus>
+    <clock>
+      <rise slew_type="abs" slew_time="20e-12" />
+      <fall slew_type="abs" slew_time="20e-12" />
+    </clock>
+    <input>
+      <rise slew_type="abs" slew_time="25e-12" />
+      <fall slew_type="abs" slew_time="25e-12" />
+    </input>
+  </stimulus>
+</openfpga_simulation_setting>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
new file mode 100644
index 000000000..afb45dc1f
--- /dev/null
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
@@ -0,0 +1,268 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
+      <design_technology type="cmos" topology="OR"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
+      <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/>
+      <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <!--mux2to1 subckt_name="mux2to1"/-->
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <!--mux2to1 subckt_name="mux2to1"/-->
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <!--mux2to1 subckt_name="mux2to1"/-->
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="D" size="1"/>
+      <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+      <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+      <port type="output" prefix="Q" size="1"/>
+      <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
+      <design_technology type="cmos" fracturable_lut="true"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="6" tri_state_map="-----1" circuit_model_name="OR2"/>
+      <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
+      <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
+      <port type="sram" prefix="sram" size="64"/>
+      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+      <port type="input" prefix="D" size="1"/>
+      <port type="output" prefix="Q" size="1"/>
+      <port type="output" prefix="Qb" size="1"/>
+      <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="inout" prefix="pad" size="1"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+      <port type="input" prefix="outpad" size="1"/>
+      <port type="output" prefix="inpad" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/>
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle" physical_mode_name="physical"/>
+    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="0"/>
+    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
+    <!-- Binding operating pb_type to physical pb_type -->
+    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="1" physical_pb_type_index_factor="0.5">
+      <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:4]"/>
+      <port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="0">
+      <!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:5]"/>
+      <port name="out" physical_mode_port="lut6_out"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>
+<openfpga_simulation_setting>
+  <clock_setting>
+    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
+    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
+    <programming frequency="10e6"/>
+  </clock_setting>
+  <simulator_option>
+    <operating_condition temperature="25"/>
+    <output_log verbose="false" captab="false"/>
+    <accuracy type="abs" value="1e-13"/>
+    <runtime fast_simulation="true"/>
+  </simulator_option>
+  <monte_carlo num_simulation_points="2"/>
+  <measurement_setting>
+    <slew>
+      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
+      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
+    </slew>
+    <delay>
+      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
+      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
+    </delay>
+  </measurement_setting>
+  <stimulus>
+    <clock>
+      <rise slew_type="abs" slew_time="20e-12" />
+      <fall slew_type="abs" slew_time="20e-12" />
+    </clock>
+    <input>
+      <rise slew_type="abs" slew_time="25e-12" />
+      <fall slew_type="abs" slew_time="25e-12" />
+    </input>
+  </stimulus>
+</openfpga_simulation_setting>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
new file mode 100644
index 000000000..98823698f
--- /dev/null
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
@@ -0,0 +1,292 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
+      <design_technology type="cmos" topology="OR"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <!--mux2to1 subckt_name="mux2to1"/-->
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <!--mux2to1 subckt_name="mux2to1"/-->
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <!--mux2to1 subckt_name="mux2to1"/-->
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <pass_gate_logic circuit_model_name="TGATE"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
+      <design_technology type="cmos" fracturable_lut="true"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="6" tri_state_map="----11" circuit_model_name="OR2"/>
+      <port type="output" prefix="lut4_out" size="4" lut_frac_level="4" lut_output_mask="0,1,2,3"/>
+      <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
+      <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
+      <port type="sram" prefix="sram" size="64"/>
+      <port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <pass_gate_logic circuit_model_name="TGATE"/>
+       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="Qb" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="inout" prefix="pad" size="1"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+      <port type="input" prefix="outpad" size="1"/>
+      <port type="output" prefix="inpad" size="1"/>
+    </circuit_model>
+    <circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="input" prefix="cin" size="1"/>
+      <port type="output" prefix="sumout" size="1"/>
+      <port type="output" prefix="cout" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <direct_connection>
+    <direct name="adder_carry" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
+  </direct_connection>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle" physical_mode_name="physical"/>
+    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
+    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
+    <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="adder"/>
+    <!-- Binding operating pb_type to physical pb_type -->
+    <!-- Binding operating pb_types in mode 'n2_lut5' -->
+    <pb_type name="clb.fle[n2_lut5].ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5">
+      <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:4]"/>
+      <port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[n2_lut5].ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <!-- Binding operating pb_types in mode 'arithmetic' -->
+    <pb_type name="clb.fle[arithmetic].arithmetic.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="11" physical_pb_type_index_factor="0.25">
+      <!-- Binding the lut4 to the first 4 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:3]"/>
+      <port name="out" physical_mode_port="lut4_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[arithmetic].arithmetic.adder" physical_pb_type_name="clb.fle[physical].fabric.adder"/>
+    <pb_type name="clb.fle[arithmetic].arithmetic.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <!-- Binding operating pb_types in mode 'ble6' -->
+    <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="00">
+      <!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:5]"/>
+      <port name="out" physical_mode_port="lut6_out"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>
+<openfpga_simulation_setting>
+  <clock_setting>
+    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
+    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
+    <programming frequency="10e6"/>
+  </clock_setting>
+  <simulator_option>
+    <operating_condition temperature="25"/>
+    <output_log verbose="false" captab="false"/>
+    <accuracy type="abs" value="1e-13"/>
+    <runtime fast_simulation="true"/>
+  </simulator_option>
+  <monte_carlo num_simulation_points="2"/>
+  <measurement_setting>
+    <slew>
+      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
+      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
+    </slew>
+    <delay>
+      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
+      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
+    </delay>
+  </measurement_setting>
+  <stimulus>
+    <clock>
+      <rise slew_type="abs" slew_time="20e-12" />
+      <fall slew_type="abs" slew_time="20e-12" />
+    </clock>
+    <input>
+      <rise slew_type="abs" slew_time="25e-12" />
+      <fall slew_type="abs" slew_time="25e-12" />
+    </input>
+  </stimulus>
+</openfpga_simulation_setting>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
new file mode 100644
index 000000000..9f37c1293
--- /dev/null
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
@@ -0,0 +1,310 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
+      <design_technology type="cmos" topology="OR"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <!--mux2to1 subckt_name="mux2to1"/-->
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <!--mux2to1 subckt_name="mux2to1"/-->
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <!--mux2to1 subckt_name="mux2to1"/-->
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <pass_gate_logic circuit_model_name="TGATE"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
+      <design_technology type="cmos" fracturable_lut="true"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="6" tri_state_map="----11" circuit_model_name="OR2"/>
+      <port type="output" prefix="lut4_out" size="4" lut_frac_level="4" lut_output_mask="0,1,2,3"/>
+      <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
+      <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
+      <port type="sram" prefix="sram" size="64"/>
+      <port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <pass_gate_logic circuit_model_name="TGATE"/>
+       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="Qb" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="inout" prefix="pad" size="1"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+      <port type="input" prefix="outpad" size="1"/>
+      <port type="output" prefix="inpad" size="1"/>
+    </circuit_model>
+    <circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="input" prefix="cin" size="1"/>
+      <port type="output" prefix="sumout" size="1"/>
+      <port type="output" prefix="cout" size="1"/>
+    </circuit_model>
+    <circuit_model type="hard_logic" name="dpram_512x32" prefix="dpram_512x32" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dpram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dpsram.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="waddr" size="10"/>
+      <port type="input" prefix="raddr" size="10"/>
+      <port type="input" prefix="d_in" size="32"/>
+      <port type="input" prefix="wen" size="1"/>
+      <port type="input" prefix="ren" size="1"/>
+      <port type="output" prefix="d_out" size="32"/>
+      <port type="clock" prefix="clk" size="1" is_global="true" default_val="0"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <direct_connection>
+    <direct name="adder_carry" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
+  </direct_connection>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle" physical_mode_name="physical"/>
+    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
+    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
+    <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="adder"/>
+    <!-- Binding operating pb_type to physical pb_type -->
+    <!-- Binding operating pb_types in mode 'n2_lut5' -->
+    <pb_type name="clb.fle[n2_lut5].ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5">
+      <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:4]"/>
+      <port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[n2_lut5].ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <!-- Binding operating pb_types in mode 'arithmetic' -->
+    <pb_type name="clb.fle[arithmetic].arithmetic.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="11" physical_pb_type_index_factor="0.25">
+      <!-- Binding the lut4 to the first 4 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:3]"/>
+      <port name="out" physical_mode_port="lut4_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[arithmetic].arithmetic.adder" physical_pb_type_name="clb.fle[physical].fabric.adder"/>
+    <pb_type name="clb.fle[arithmetic].arithmetic.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <!-- Binding operating pb_types in mode 'ble6' -->
+    <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="00">
+      <!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:5]"/>
+      <port name="out" physical_mode_port="lut6_out"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
+    <!-- End physical pb_type binding in complex block clb -->
+
+
+    <!-- physical pb_type binding in complex block memory -->
+    <pb_type name="memory[mem_512x32_dp].mem_512x32_dp" circuit_model_name="dpram_512x32"/>
+    <!-- END physical pb_type binding in complex block memory -->
+  </pb_type_annotations>
+</openfpga_architecture>
+<openfpga_simulation_setting>
+  <clock_setting>
+    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
+    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
+    <programming frequency="10e6"/>
+  </clock_setting>
+  <simulator_option>
+    <operating_condition temperature="25"/>
+    <output_log verbose="false" captab="false"/>
+    <accuracy type="abs" value="1e-13"/>
+    <runtime fast_simulation="true"/>
+  </simulator_option>
+  <monte_carlo num_simulation_points="2"/>
+  <measurement_setting>
+    <slew>
+      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
+      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
+    </slew>
+    <delay>
+      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
+      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
+    </delay>
+  </measurement_setting>
+  <stimulus>
+    <clock>
+      <rise slew_type="abs" slew_time="20e-12" />
+      <fall slew_type="abs" slew_time="20e-12" />
+    </clock>
+    <input>
+      <rise slew_type="abs" slew_time="25e-12" />
+      <fall slew_type="abs" slew_time="25e-12" />
+    </input>
+  </stimulus>
+</openfpga_simulation_setting>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
new file mode 100644
index 000000000..ea56fe036
--- /dev/null
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
@@ -0,0 +1,323 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
+      <design_technology type="cmos" topology="OR"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <!--mux2to1 subckt_name="mux2to1"/-->
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <!--mux2to1 subckt_name="mux2to1"/-->
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <!--mux2to1 subckt_name="mux2to1"/-->
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <pass_gate_logic circuit_model_name="TGATE"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
+      <design_technology type="cmos" fracturable_lut="true"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="6" tri_state_map="----11" circuit_model_name="OR2"/>
+      <port type="output" prefix="lut4_out" size="4" lut_frac_level="4" lut_output_mask="0,1,2,3"/>
+      <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
+      <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
+      <port type="sram" prefix="sram" size="64"/>
+      <port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <pass_gate_logic circuit_model_name="TGATE"/>
+       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="Qb" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="inout" prefix="pad" size="1"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+      <port type="input" prefix="outpad" size="1"/>
+      <port type="output" prefix="inpad" size="1"/>
+    </circuit_model>
+    <circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="input" prefix="cin" size="1"/>
+      <port type="output" prefix="sumout" size="1"/>
+      <port type="output" prefix="cout" size="1"/>
+    </circuit_model>
+    <circuit_model type="hard_logic" name="dpram_512x32" prefix="dpram_512x32" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dpram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dpsram.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="waddr" size="10"/>
+      <port type="input" prefix="raddr" size="10"/>
+      <port type="input" prefix="d_in" size="32"/>
+      <port type="input" prefix="wen" size="1"/>
+      <port type="input" prefix="ren" size="1"/>
+      <port type="output" prefix="d_out" size="32"/>
+      <port type="clock" prefix="clk" size="1" is_global="true" default_val="0"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="aib" prefix="aib" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/aib.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/aib.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="tx_data" size="80"/>
+      <port type="output" prefix="rx_data" size="80"/>
+      <port type="clock" prefix="tx_clk" size="1" default_val="0"/>
+      <port type="clock" prefix="rx_clk" size="1" default_val="0"/>
+      <port type="inout" prefix="pad" size="80"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <direct_connection>
+    <direct name="adder_carry" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
+  </direct_connection>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block AIB-->
+    <pb_type name="aib[physical].aib_core" circuit_model_name="aib"/>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle" physical_mode_name="physical"/>
+    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
+    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
+    <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="adder"/>
+    <!-- Binding operating pb_type to physical pb_type -->
+    <!-- Binding operating pb_types in mode 'n2_lut5' -->
+    <pb_type name="clb.fle[n2_lut5].ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5">
+      <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:4]"/>
+      <port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[n2_lut5].ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <!-- Binding operating pb_types in mode 'arithmetic' -->
+    <pb_type name="clb.fle[arithmetic].arithmetic.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="11" physical_pb_type_index_factor="0.25">
+      <!-- Binding the lut4 to the first 4 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:3]"/>
+      <port name="out" physical_mode_port="lut4_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[arithmetic].arithmetic.adder" physical_pb_type_name="clb.fle[physical].fabric.adder"/>
+    <pb_type name="clb.fle[arithmetic].arithmetic.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <!-- Binding operating pb_types in mode 'ble6' -->
+    <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="00">
+      <!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:5]"/>
+      <port name="out" physical_mode_port="lut6_out"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
+    <!-- End physical pb_type binding in complex block clb -->
+
+
+    <!-- physical pb_type binding in complex block memory -->
+    <pb_type name="memory[mem_512x32_dp].mem_512x32_dp" circuit_model_name="dpram_512x32"/>
+    <!-- END physical pb_type binding in complex block memory -->
+  </pb_type_annotations>
+</openfpga_architecture>
+<openfpga_simulation_setting>
+  <clock_setting>
+    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
+    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
+    <programming frequency="10e6"/>
+  </clock_setting>
+  <simulator_option>
+    <operating_condition temperature="25"/>
+    <output_log verbose="false" captab="false"/>
+    <accuracy type="abs" value="1e-13"/>
+    <runtime fast_simulation="true"/>
+  </simulator_option>
+  <monte_carlo num_simulation_points="2"/>
+  <measurement_setting>
+    <slew>
+      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
+      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
+    </slew>
+    <delay>
+      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
+      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
+    </delay>
+  </measurement_setting>
+  <stimulus>
+    <clock>
+      <rise slew_type="abs" slew_time="20e-12" />
+      <fall slew_type="abs" slew_time="20e-12" />
+    </clock>
+    <input>
+      <rise slew_type="abs" slew_time="25e-12" />
+      <fall slew_type="abs" slew_time="25e-12" />
+    </input>
+  </stimulus>
+</openfpga_simulation_setting>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml
new file mode 100644
index 000000000..2b432ce86
--- /dev/null
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml
@@ -0,0 +1,270 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
+      <design_technology type="cmos" topology="OR"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <!--mux2to1 subckt_name="mux2to1"/-->
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <!--mux2to1 subckt_name="mux2to1"/-->
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <!--mux2to1 subckt_name="mux2to1"/-->
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <pass_gate_logic circuit_model_name="TGATE"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
+      <design_technology type="cmos" fracturable_lut="true"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="6" tri_state_map="-----1" circuit_model_name="OR2"/>
+      <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
+      <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
+      <port type="sram" prefix="sram" size="64"/>
+      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <pass_gate_logic circuit_model_name="TGATE"/>
+       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="Qb" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="inout" prefix="pad" size="1"/>
+      <!-- A spypad for the direction port of the I/O pad, which can be visible in the fpga_top -->
+      <port type="input" prefix="din" size="1" is_global="true" io="true" default_value="0"/>
+      <port type="output" prefix="dout" size="1" is_global="true"/>
+      <port type="output" prefix="dir" size="1" is_global="true"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+      <port type="input" prefix="outpad" size="1"/>
+      <port type="output" prefix="inpad" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle" physical_mode_name="physical"/>
+    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="0"/>
+    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
+    <!-- Binding operating pb_type to physical pb_type -->
+    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="1" physical_pb_type_index_factor="0.5">
+      <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:4]"/>
+      <port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="0">
+      <!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:5]"/>
+      <port name="out" physical_mode_port="lut6_out"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>
+<openfpga_simulation_setting>
+  <clock_setting>
+    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
+    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
+    <programming frequency="10e6"/>
+  </clock_setting>
+  <simulator_option>
+    <operating_condition temperature="25"/>
+    <output_log verbose="false" captab="false"/>
+    <accuracy type="abs" value="1e-13"/>
+    <runtime fast_simulation="true"/>
+  </simulator_option>
+  <monte_carlo num_simulation_points="2"/>
+  <measurement_setting>
+    <slew>
+      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
+      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
+    </slew>
+    <delay>
+      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
+      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
+    </delay>
+  </measurement_setting>
+  <stimulus>
+    <clock>
+      <rise slew_type="abs" slew_time="20e-12" />
+      <fall slew_type="abs" slew_time="20e-12" />
+    </clock>
+    <input>
+      <rise slew_type="abs" slew_time="25e-12" />
+      <fall slew_type="abs" slew_time="25e-12" />
+    </input>
+  </stimulus>
+</openfpga_simulation_setting>

From 7f98ecc8a67820aca775b7af4b6553c2042a3721 Mon Sep 17 00:00:00 2001
From: ganeshgore <goreganesh007@gmail.com>
Date: Mon, 6 Apr 2020 00:32:43 -0600
Subject: [PATCH 378/645] OpenFPGA shell run test script template

---
 .../example_script.openfpga                   | 58 +++++++++++++++++++
 1 file changed, 58 insertions(+)
 create mode 100644 openfpga_flow/OpenFPGAShellScripts/example_script.openfpga

diff --git a/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
new file mode 100644
index 000000000..5a79a3910
--- /dev/null
+++ b/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
@@ -0,0 +1,58 @@
+# Run VPR for the 'and' design
+#--write_rr_graph example_rr_graph.xml
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
+
+# Annotate the OpenFPGA architecture to VPR data base
+# to debug use --verbose options
+link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to clustering nets based on routing results
+pb_pin_fixup --verbose
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup
+
+# Build the module graph
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules
+build_fabric --compress_routing --duplicate_grid_pin #--verbose
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --file fabric_indepenent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file ./VerilogNetlist/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_verilog_testbench --file ./VerilogNetlist/SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here
+write_pnr_sdc --file ./VerilogNetlist/SDC
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+write_analysis_sdc --file ./VerilogNetlist/SDC_analysis
+
+# Finish and exit OpenFPGA
+exit

From ea4122a8a426c00284740a782958e988f936b5bf Mon Sep 17 00:00:00 2001
From: ganeshgore <goreganesh007@gmail.com>
Date: Mon, 6 Apr 2020 00:34:36 -0600
Subject: [PATCH 379/645] Updated openfpga_flow and task file to support sheel
 run

---
 .../misc/fpgaflow_default_tool_path.conf      |   1 +
 openfpga_flow/scripts/run_fpga_flow.py        | 121 ++++++------------
 openfpga_flow/scripts/run_fpga_task.py        |   7 +
 3 files changed, 47 insertions(+), 82 deletions(-)

diff --git a/openfpga_flow/misc/fpgaflow_default_tool_path.conf b/openfpga_flow/misc/fpgaflow_default_tool_path.conf
index 88d4504ab..5b89052e3 100644
--- a/openfpga_flow/misc/fpgaflow_default_tool_path.conf
+++ b/openfpga_flow/misc/fpgaflow_default_tool_path.conf
@@ -1,5 +1,6 @@
 # Standard Configuration Example
 [CAD_TOOLS_PATH]
+openfpga_shell_path = ${PATH:OPENFPGA_PATH}/openfpga/openfpga
 yosys_path = ${PATH:OPENFPGA_PATH}/yosys/yosys
 misc_dir = ${PATH:OPENFPGA_PATH}/openfpga_flow/misc
 odin2_path = ${PATH:OPENFPGA_PATH}/openfpga_flow/not_used_atm/odin2.exe
diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py
index 1d67d3059..cd9a80f81 100644
--- a/openfpga_flow/scripts/run_fpga_flow.py
+++ b/openfpga_flow/scripts/run_fpga_flow.py
@@ -47,6 +47,7 @@ task_script_dir = os.path.dirname(os.path.abspath(__file__))
 script_env_vars = ({"PATH": {
     "OPENFPGA_FLOW_PATH": task_script_dir,
     "ARCH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "arch"),
+    "OPENFPGA_SHELLSCRIPT_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "OpenFPGAShellScripts"),
     "BENCH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "benchmarks"),
     "TECH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "tech"),
     "SPICENETLIST_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "SpiceNetlists"),
@@ -78,6 +79,13 @@ parser.add_argument('--flow_config', type=str,
 parser.add_argument('--run_dir', type=str,
                     default=os.path.join(openfpga_base_dir,  'tmp'),
                     help="Directory to store intermidiate file & final results")
+parser.add_argument('--openfpga_shell_template', type=str,
+                    default=os.path.join(openfpga_base_dir, 'openfpga_flow',
+                                         'OpenFPGAShellScripts',
+                                         'example_script.openfpga'),
+                    help="Sample openfpga shell script")
+parser.add_argument('--openfpga_arch_file', type=str,
+                    help="Openfpga architecture file for shell")
 parser.add_argument('--yosys_tmpl', type=str,
                     help="Alternate yosys template, generates top_module.blif")
 parser.add_argument('--disp', action="store_true",
@@ -249,7 +257,10 @@ def main():
     #     run_abc_vtr()
     # if (args.fpga_flow == "vtr_standard"):
     #     run_abc_for_standarad()
-    run_vpr()
+    if args.openfpga_shell_template:
+        run_openfpga_shell()
+    else:
+        run_vpr()
     if args.end_flow_with_test:
         run_netlists_verification()
 
@@ -323,10 +334,10 @@ def validate_command_line_arguments():
                     clean_up_and_exit("'%s' argument depends on (%s) argumets" %
                                       (eacharg, ", ".join(dependent).replace("|", " or ")))
 
-    # Filter provided architecrue files
+    # Filter provided architecture files
     args.arch_file = os.path.abspath(args.arch_file)
     if not os.path.isfile(args.arch_file):
-        clean_up_and_exit("Architecure file not found. -%s", args.arch_file)
+        clean_up_and_exit("Architecture file not found. -%s", args.arch_file)
 
     # Filter provided benchmark files
     for index, everyinput in enumerate(args.benchmark_files):
@@ -579,6 +590,15 @@ def collect_files_for_vpr():
         clean_up_and_exit("Provided base_verilog file not found")
     shutil.copy(args.base_verilog, args.top_module+"_output_verilog.v")
 
+    # Sanitize provided openshell template, if provided
+    if not os.path.isfile(args.openfpga_shell_template or ""):
+        logger.error("Openfpga shell file - %s" % args.openfpga_shell_template)
+        clean_up_and_exit("Provided openfpga_shell_template" +
+                          f" {args.openfpga_shell_template} file not found")
+    else:
+        shutil.copy(args.openfpga_shell_template,
+                    args.top_module+"_template.openfpga")
+
 
 def run_vpr():
     ExecTime["VPRStart"] = time.time()
@@ -646,86 +666,23 @@ def run_vpr():
     ExecTime["VPREnd"] = time.time()
 
 
-def run_openfpga_shell(bench_blif, fixed_chan_width, logfile, route_only=False):
-    runfile = open("run.openfpga", 'w+'):
-    command = ["vpr",
-               args.arch_file,
-               bench_blif,
-               "--net_file", args.top_module+"_vpr.net",
-               "--place_file", args.top_module+"_vpr.place",
-               "--route_file", args.top_module+"_vpr.route",
-               "--full_stats",
-               "--activity_file", args.top_module+"_ace_out.act"]
-    # Other VPR options
-    if args.vpr_place_clb_pin_remap:
-        command += ["--place_clb_pin_remap"]
-    if args.vpr_route_breadthfirst:
-        command += ["--router_algorithm", "breadth_first"]
-    if args.vpr_max_router_iteration:
-        command += ["--max_router_iterations", args.vpr_max_router_iteration]
-    runfile.write(" ".join(command)+os.linesep)
+def run_openfpga_shell():
+    # bench_blif, fixed_chan_width, logfile, route_only=False
+    tmpl = Template(open(args.top_module+"_template.openfpga",
+                         encoding='utf-8').read())
 
-    command = ["read_openfpga_arch", "-f", args.arch_file]
-    runfile.write(" ".join(command)+os.linesep)
-
-    command = ["link_openfpga_arch", "--activity_file",
-               args.top_module+"_ace_out.act"]
-    runfile.write(" ".join(command)+os.linesep)
-
-    command = ["check_netlist_naming_conflict",
-               "--fix", "--report",
-               (args.arch_file).replace(".xml", "_renaming.xml")]
-    runfile.write(" ".join(command)+os.linesep)
-
-    runfile.write(" ".join(["pb_pin_fixup", "--verbose"])+os.linesep)
-    runfile.write(" ".join(["lut_truth_table_fixup"])+os.linesep)
-
-    command = ["build_fabric", "--compress_routing", "--duplicate_grid_pin"]
-    runfile.write(" ".join(command)+os.linesep)
-
-    runfile.write(" ".join(["repack"])+os.linesep)
-
-    if args.vpr_fpga_verilog:
-        command += ["write_verilog_testbench", "--fpga_verilog"]
-        if args.vpr_fpga_verilog_dir:
-            command += ["--fpga_verilog_dir", args.vpr_fpga_verilog_dir]
-        if args.vpr_fpga_verilog_print_top_tb:
-            command += ["--fpga_verilog_print_top_testbench"]
-        if args.vpr_fpga_verilog_print_input_blif_tb:
-            command += ["--fpga_verilog_print_input_blif_testbench"]
-        if args.vpr_fpga_verilog_print_autocheck_top_testbench:
-            command += ["--fpga_verilog_print_autocheck_top_testbench",
-                        os.path.join(args.run_dir, args.top_module+"_output_verilog.v")]
-        if args.vpr_fpga_verilog_include_timing:
-            command += ["--fpga_verilog_include_timing"]
-        if args.vpr_fpga_verilog_explicit_mapping:
-            command += ["--fpga_verilog_explicit_mapping"]
-        if args.vpr_fpga_x2p_duplicate_grid_pin:
-            command += ["--fpga_x2p_duplicate_grid_pin"]
-        if args.vpr_fpga_verilog_include_signal_init:
-            command += ["--fpga_verilog_include_signal_init"]
-        if args.vpr_fpga_verilog_formal_verification_top_netlist:
-            command += ["--fpga_verilog_print_formal_verification_top_netlist"]
-        if args.vpr_fpga_verilog_print_simulation_ini:
-            command += ["--fpga_verilog_print_simulation_ini"]
-        if args.vpr_fpga_verilog_include_icarus_simulator:
-            command += ["--fpga_verilog_include_icarus_simulator"]
-        if args.vpr_fpga_verilog_print_report_timing_tcl:
-            command += ["--fpga_verilog_print_report_timing_tcl"]
-        if args.vpr_fpga_verilog_report_timing_rpt_path:
-            command += ["--fpga_verilog_report_timing_rpt_path",
-                        args.vpr_fpga_verilog_report_timing_rpt_path]
-        if args.vpr_fpga_verilog_print_sdc_pnr:
-            command += ["--fpga_verilog_print_sdc_pnr"]
-        if args.vpr_fpga_verilog_print_user_defined_template:
-            command += ["--fpga_verilog_print_user_defined_template"]
-        if args.vpr_fpga_verilog_print_sdc_analysis:
-            command += ["--fpga_verilog_print_sdc_analysis"]
-        runfile.write(" ".join(command)+os.linesep)
-
-        if args.vpr_fpga_verilog_print_sdc_analysis:
-            command = ["write_pnr_sdc", "--fpga_bitstream_generator"]
-            runfile.write(" ".join(command)+os.linesep)
+    path_variables = script_env_vars["PATH"]
+    path_variables["VPR_ARCH_FILE"] = args.arch_file
+    path_variables["OPENFPGA_ARCH_FILE"] = args.openfpga_arch_file
+    path_variables["VPR_TESTBENCH_BLIF"] = args.top_module+".blif"
+    path_variables["ACTIVITY_FILE"] = args.top_module+"_ace_out.act"
+    path_variables["REFERENCE_VERILOG_TESTBENCH"] = args.top_module + \
+        "_output_verilog.v"
+    with open(args.top_module+"_run.openfpga", 'w', encoding='utf-8') as archfile:
+        archfile.write(tmpl.substitute(path_variables))
+    command = [cad_tools["openfpga_shell_path"], "-f",
+               args.top_module+"_run.openfpga"]
+    run_command("OpenFPGA Shell Run", "openfpgashell.log", command)
 
 
 def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False):
diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py
index bcb4b6a44..9567c4fe5 100644
--- a/openfpga_flow/scripts/run_fpga_task.py
+++ b/openfpga_flow/scripts/run_fpga_task.py
@@ -71,6 +71,7 @@ task_script_dir = os.path.dirname(os.path.abspath(__file__))
 script_env_vars = ({"PATH": {
     "OPENFPGA_FLOW_PATH": task_script_dir,
     "ARCH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "arch"),
+    "OPENFPGA_SHELLSCRIPT_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "OpenFPGAShellScripts"),
     "BENCH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "benchmarks"),
     "TECH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "tech"),
     "SPICENETLIST_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "SpiceNetlists"),
@@ -349,6 +350,12 @@ def create_run_command(curr_job_dir, archfile, benchmark_obj, param, task_conf):
     if task_gc.get("fpga_flow"):
         command += ["--fpga_flow", task_gc.get("fpga_flow")]
 
+    if task_gc.get("run_engine") == "openfpga_shell":
+        command += ["--openfpga_shell_template",
+                    task_gc.get("openfpga_shell_template")]
+        command += ["--openfpga_arch_file",
+                    task_gc.get("openfpga_arch_file")]
+
     if benchmark_obj.get("activity_file"):
         command += ["--activity_file", benchmark_obj.get("activity_file")]
 

From e1db4df74438a5c0415e6506380549c387208c8f Mon Sep 17 00:00:00 2001
From: ganeshgore <goreganesh007@gmail.com>
Date: Mon, 6 Apr 2020 00:35:07 -0600
Subject: [PATCH 380/645] Created task for FPGA shell run

---
 .../OpenFPGAShell_Example/config/task.conf    | 33 +++++++++++++++++++
 1 file changed, 33 insertions(+)
 create mode 100644 openfpga_flow/tasks/OpenFPGAShell_Example/config/task.conf

diff --git a/openfpga_flow/tasks/OpenFPGAShell_Example/config/task.conf b/openfpga_flow/tasks/OpenFPGAShell_Example/config/task.conf
new file mode 100644
index 000000000..54d8e8a4a
--- /dev/null
+++ b/openfpga_flow/tasks/OpenFPGAShell_Example/config/task.conf
@@ -0,0 +1,33 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = top
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+min_route_chan_width=1.3
\ No newline at end of file

From 87c25a6084dd5505c477ee8407f317a7190277a2 Mon Sep 17 00:00:00 2001
From: ganeshgore <goreganesh007@gmail.com>
Date: Mon, 6 Apr 2020 00:35:28 -0600
Subject: [PATCH 381/645] Added GCC paths to source

---
 openfpga.sh | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/openfpga.sh b/openfpga.sh
index 02f2ba5fd..3ae8c992d 100755
--- a/openfpga.sh
+++ b/openfpga.sh
@@ -4,6 +4,12 @@
 #                  for several simple operations in OpenFPGA project
 #author          : Ganesh Gore <ganesh.gore@utah.edu>
 #==============================================================================
+# Enviroment variables
+export PATH=$PATH:/usr/local/stow/gcc/amd64_linux26/gcc-8.4.0/bin
+export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/usr/local/stow/gcc/amd64_linux26/gcc-8.4.0/lib64
+export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/usr/local/stow/boost/boost_1_67_0/lib/
+export CC=$(which gcc)
+export CXX=$(which g++)
 
 export OPENFPGA_PATH="$(pwd)"
 export OPENFPGA_SCRIPT_PATH="$(pwd)/openfpga_flow/scripts"
@@ -82,4 +88,5 @@ fi
 TaskList=$(ls -tdalh ${OPENFPGA_TASK_PATH}/* | awk '{system("basename " $9)}' |  awk '{printf("%s ",$1)}')
 complete -W "${TaskList}" goto-task
 complete -W "${TaskList}" run-task
+complete -W "${TaskList}" run-shell-task
 complete -W "${TaskList}" run-modelsim

From 6eb125ec2ae08d61bc55aae511960a4af6320c9e Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 6 Apr 2020 14:09:52 -0600
Subject: [PATCH 382/645] Now cross-column/row is optional to direct annotation
 in OpenFPGA architecture XML

---
 .../src/read_xml_routing_circuit.cpp          |   7 +-
 ...c_N10_adder_column_chain_40nm_openfpga.xml | 292 ++++++++++++++++++
 ..._frac_tileable_adder_column_chain.openfpga |  62 ++++
 3 files changed, 360 insertions(+), 1 deletion(-)
 create mode 100644 openfpga/test_openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml
 create mode 100644 openfpga/test_script/and_k6_frac_tileable_adder_column_chain.openfpga

diff --git a/libopenfpga/libarchopenfpga/src/read_xml_routing_circuit.cpp b/libopenfpga/libarchopenfpga/src/read_xml_routing_circuit.cpp
index 3114276ae..5daef1310 100644
--- a/libopenfpga/libarchopenfpga/src/read_xml_routing_circuit.cpp
+++ b/libopenfpga/libarchopenfpga/src/read_xml_routing_circuit.cpp
@@ -262,7 +262,12 @@ ArchDirect read_xml_direct_circuit(pugi::xml_node& Node,
     arch_direct.set_circuit_model(direct, direct_model);
 
     /* Add more information*/
-    std::string direct_type_name = get_attribute(xml_direct, "type", loc_data).as_string();
+    std::string direct_type_name = get_attribute(xml_direct, "type", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string("none");
+    /* If not defined, we go to the next */
+    if (std::string("none") == direct_type_name) {
+      continue;
+    }
+
     e_direct_type direct_type = string_to_direct_type(direct_type_name);
 
     if (NUM_DIRECT_TYPES == direct_type) {
diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml
new file mode 100644
index 000000000..34f44d153
--- /dev/null
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml
@@ -0,0 +1,292 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
+      <design_technology type="cmos" topology="OR"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <!--mux2to1 subckt_name="mux2to1"/-->
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <!--mux2to1 subckt_name="mux2to1"/-->
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <!--mux2to1 subckt_name="mux2to1"/-->
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <pass_gate_logic circuit_model_name="TGATE"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
+      <design_technology type="cmos" fracturable_lut="true"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="6" tri_state_map="----11" circuit_model_name="OR2"/>
+      <port type="output" prefix="lut4_out" size="4" lut_frac_level="4" lut_output_mask="0,1,2,3"/>
+      <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
+      <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
+      <port type="sram" prefix="sram" size="64"/>
+      <port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <pass_gate_logic circuit_model_name="TGATE"/>
+       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="Qb" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="inout" prefix="pad" size="1"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+      <port type="input" prefix="outpad" size="1"/>
+      <port type="output" prefix="inpad" size="1"/>
+    </circuit_model>
+    <circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="input" prefix="cin" size="1"/>
+      <port type="output" prefix="sumout" size="1"/>
+      <port type="output" prefix="cout" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <direct_connection>
+    <direct name="adder_carry" circuit_model_name="direct_interc"/>
+  </direct_connection>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle" physical_mode_name="physical"/>
+    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
+    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
+    <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="adder"/>
+    <!-- Binding operating pb_type to physical pb_type -->
+    <!-- Binding operating pb_types in mode 'n2_lut5' -->
+    <pb_type name="clb.fle[n2_lut5].ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5">
+      <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:4]"/>
+      <port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[n2_lut5].ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <!-- Binding operating pb_types in mode 'arithmetic' -->
+    <pb_type name="clb.fle[arithmetic].arithmetic.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="11" physical_pb_type_index_factor="0.25">
+      <!-- Binding the lut4 to the first 4 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:3]"/>
+      <port name="out" physical_mode_port="lut4_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[arithmetic].arithmetic.adder" physical_pb_type_name="clb.fle[physical].fabric.adder"/>
+    <pb_type name="clb.fle[arithmetic].arithmetic.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <!-- Binding operating pb_types in mode 'ble6' -->
+    <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="00">
+      <!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:5]"/>
+      <port name="out" physical_mode_port="lut6_out"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>
+<openfpga_simulation_setting>
+  <clock_setting>
+    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
+    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
+    <programming frequency="10e6"/>
+  </clock_setting>
+  <simulator_option>
+    <operating_condition temperature="25"/>
+    <output_log verbose="false" captab="false"/>
+    <accuracy type="abs" value="1e-13"/>
+    <runtime fast_simulation="true"/>
+  </simulator_option>
+  <monte_carlo num_simulation_points="2"/>
+  <measurement_setting>
+    <slew>
+      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
+      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
+    </slew>
+    <delay>
+      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
+      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
+    </delay>
+  </measurement_setting>
+  <stimulus>
+    <clock>
+      <rise slew_type="abs" slew_time="20e-12" />
+      <fall slew_type="abs" slew_time="20e-12" />
+    </clock>
+    <input>
+      <rise slew_type="abs" slew_time="25e-12" />
+      <fall slew_type="abs" slew_time="25e-12" />
+    </input>
+  </stimulus>
+</openfpga_simulation_setting>
diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_column_chain.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_column_chain.openfpga
new file mode 100644
index 000000000..fbcdda185
--- /dev/null
+++ b/openfpga/test_script/and_k6_frac_tileable_adder_column_chain.openfpga
@@ -0,0 +1,62 @@
+# Run VPR for the 'and' design
+vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml
+
+# Write out the architecture XML as a proof
+#write_openfpga_arch -f ./arch_echo.xml
+
+# Annotate the OpenFPGA architecture to VPR data base
+link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose
+
+# Write GSB to XML for debugging
+write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to clustering nets based on routing results
+pb_pin_fixup --verbose
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup #--verbose
+
+# Build the module graph 
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules 
+build_fabric --compress_routing --duplicate_grid_pin --verbose
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream 
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here 
+write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
+
+# Finish and exit OpenFPGA
+exit

From 13cd48c119b8f1198ad42de8c74aa34642df9f14 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 6 Apr 2020 16:07:49 -0600
Subject: [PATCH 383/645] add support on packable/unpackable modes in VPR
 architecture

---
 libs/libarchfpga/src/physical_types.h              |  3 +++
 libs/libarchfpga/src/read_xml_arch_file.cpp        | 14 ++++++++++++++
 openfpga/test_vpr_arch/k6_N10_40nm.xml             |  2 +-
 openfpga/test_vpr_arch/k6_N10_tileable_40nm.xml    |  2 +-
 openfpga/test_vpr_arch/k6_frac_N10_40nm.xml        |  4 ++--
 .../test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml |  4 ++--
 .../k6_frac_N10_adder_chain_mem16K_40nm.xml        |  4 ++--
 .../test_vpr_arch/k6_frac_N10_tileable_40nm.xml    |  4 ++--
 .../k6_frac_N10_tileable_adder_chain_40nm.xml      |  4 ++--
 ...6_frac_N10_tileable_adder_chain_mem16K_40nm.xml |  4 ++--
 ...ac_N10_tileable_adder_chain_mem16K_aib_40nm.xml |  4 ++--
 ...e_adder_chain_mem16K_multi_io_capacity_40nm.xml |  4 ++--
 ...tileable_adder_chain_mem16K_reduced_io_40nm.xml |  4 ++--
 ...c_N10_tileable_adder_chain_wide_mem16K_40nm.xml |  4 ++--
 vpr/src/pack/cluster.cpp                           |  5 +++++
 vpr/src/pack/cluster_router.cpp                    |  4 ++++
 vpr/src/pack/prepack.cpp                           | 14 +++++++++++++-
 17 files changed, 61 insertions(+), 23 deletions(-)

diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h
index f5f2c3c7e..c9b44cd92 100644
--- a/libs/libarchfpga/src/physical_types.h
+++ b/libs/libarchfpga/src/physical_types.h
@@ -822,6 +822,9 @@ struct t_mode {
     t_pb_type* parent_pb_type = nullptr;
     int index = 0;
 
+    /* Xifan Tang: Specify if the mode is packable or not */
+    bool packable = true;
+
     /* Power related members */
     t_mode_power* mode_power = nullptr;
 
diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp
index cabb17bbb..cf2dd72c3 100644
--- a/libs/libarchfpga/src/read_xml_arch_file.cpp
+++ b/libs/libarchfpga/src/read_xml_arch_file.cpp
@@ -1956,6 +1956,20 @@ static void ProcessMode(pugi::xml_node Parent, t_mode* mode, const bool timing_e
         mode->name = vtr::strdup(Prop);
     }
 
+    /* Xifan Tang: parse XML about if this mode is packable or not */
+    mode->packable = true;
+    /* If the parent mode is not packable, all the child mode should be unpackable as well */
+    if (nullptr != mode->parent_pb_type->parent_mode) {
+        mode->packable = mode->parent_pb_type->parent_mode->packable;
+    }
+    /* Override if user specify */
+    mode->packable = get_attribute(Parent, "packable", loc_data, ReqOpt::OPTIONAL).as_bool(mode->packable);
+    if (false == mode->packable) {
+        VTR_LOG("mode '%s[%s]' is defined by user to be not packable\n",
+                 mode->parent_pb_type->name,
+                 mode->name);
+    }
+
     mode->num_pb_type_children = count_children(Parent, "pb_type", loc_data, ReqOpt::OPTIONAL);
     if (mode->num_pb_type_children > 0) {
         mode->pb_type_children = new t_pb_type[mode->num_pb_type_children];
diff --git a/openfpga/test_vpr_arch/k6_N10_40nm.xml b/openfpga/test_vpr_arch/k6_N10_40nm.xml
index 630011e84..83b4948a8 100644
--- a/openfpga/test_vpr_arch/k6_N10_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_N10_40nm.xml
@@ -139,7 +139,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" disabled_in_pack="true">
+      <mode name="physical" packable="false">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
diff --git a/openfpga/test_vpr_arch/k6_N10_tileable_40nm.xml b/openfpga/test_vpr_arch/k6_N10_tileable_40nm.xml
index d86d7aa62..ceacbb3f2 100644
--- a/openfpga/test_vpr_arch/k6_N10_tileable_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_N10_tileable_40nm.xml
@@ -139,7 +139,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" disabled_in_pack="true">
+      <mode name="physical" packable="false">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml
index ef9268810..8476a5155 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml
@@ -158,7 +158,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" disabled_in_pack="true">
+      <mode name="physical" packable="false">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -230,7 +230,7 @@
         <output name="out" num_pins="2"/>
         <clock name="clk" num_pins="1"/>
         <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" disabled_in_pack="true">
+        <mode name="physical" packable="false">
           <pb_type name="fabric" num_pb="1">
             <input name="in" num_pins="6"/>
             <output name="out" num_pins="2"/>
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
index bbe041562..504431eb0 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
@@ -245,7 +245,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" disabled_in_pack="true">
+      <mode name="physical" packable="false">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -321,7 +321,7 @@
         <output name="cout" num_pins="1"/>
         <clock name="clk" num_pins="1"/>
         <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" disabled_in_pack="true">
+        <mode name="physical" packable="false">
           <pb_type name="fabric" num_pb="1">
             <input name="in" num_pins="6"/>
             <input name="cin" num_pins="1"/>
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml
index 850eb5450..3ecd20733 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml
@@ -282,7 +282,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" disabled_in_pack="true">
+      <mode name="physical" packable="false">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -358,7 +358,7 @@
         <output name="cout" num_pins="1"/>
         <clock name="clk" num_pins="1"/>
         <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" disabled_in_pack="true">
+        <mode name="physical" packable="false">
           <pb_type name="fabric" num_pb="1">
             <input name="in" num_pins="6"/>
             <input name="cin" num_pins="1"/>
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_40nm.xml
index 2c528c13c..146a170e5 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_tileable_40nm.xml
@@ -158,7 +158,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" disabled_in_pack="true">
+      <mode name="physical" packable="false">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -230,7 +230,7 @@
         <output name="out" num_pins="2"/>
         <clock name="clk" num_pins="1"/>
         <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" disabled_in_pack="true">
+        <mode name="physical" packable="false">
           <pb_type name="fabric" num_pb="1">
             <input name="in" num_pins="6"/>
             <output name="out" num_pins="2"/>
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml
index eea76837f..19b27b88b 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml
@@ -245,7 +245,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" disabled_in_pack="true">
+      <mode name="physical" packable="false">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -321,7 +321,7 @@
         <output name="cout" num_pins="1"/>
         <clock name="clk" num_pins="1"/>
         <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" disabled_in_pack="true">
+        <mode name="physical" packable="false">
           <pb_type name="fabric" num_pb="1">
             <input name="in" num_pins="6"/>
             <input name="cin" num_pins="1"/>
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml
index 9422c3a09..4c0751db4 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml
@@ -282,7 +282,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" disabled_in_pack="true">
+      <mode name="physical" packable="false">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -358,7 +358,7 @@
         <output name="cout" num_pins="1"/>
         <clock name="clk" num_pins="1"/>
         <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" disabled_in_pack="true">
+        <mode name="physical" packable="false">
           <pb_type name="fabric" num_pb="1">
             <input name="in" num_pins="6"/>
             <input name="cin" num_pins="1"/>
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml
index e196cb83c..37dbb2b93 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml
@@ -348,7 +348,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" disabled_in_pack="true">
+      <mode name="physical" packable="false">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -424,7 +424,7 @@
         <output name="cout" num_pins="1"/>
         <clock name="clk" num_pins="1"/>
         <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" disabled_in_pack="true">
+        <mode name="physical" packable="false">
           <pb_type name="fabric" num_pb="1">
             <input name="in" num_pins="6"/>
             <input name="cin" num_pins="1"/>
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml
index 8eb6f32bf..ff7c3278b 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml
@@ -316,7 +316,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" disabled_in_pack="true">
+      <mode name="physical" packable="false">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -392,7 +392,7 @@
         <output name="cout" num_pins="1"/>
         <clock name="clk" num_pins="1"/>
         <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" disabled_in_pack="true">
+        <mode name="physical" packable="false">
           <pb_type name="fabric" num_pb="1">
             <input name="in" num_pins="6"/>
             <input name="cin" num_pins="1"/>
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml
index 6f8c4cfae..d9adc9056 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml
@@ -285,7 +285,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" disabled_in_pack="true">
+      <mode name="physical" packable="false">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -361,7 +361,7 @@
         <output name="cout" num_pins="1"/>
         <clock name="clk" num_pins="1"/>
         <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" disabled_in_pack="true">
+        <mode name="physical" packable="false">
           <pb_type name="fabric" num_pb="1">
             <input name="in" num_pins="6"/>
             <input name="cin" num_pins="1"/>
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml
index f07f16c80..7eda2aa2f 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml
@@ -282,7 +282,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" disabled_in_pack="true">
+      <mode name="physical" packable="false">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -358,7 +358,7 @@
         <output name="cout" num_pins="1"/>
         <clock name="clk" num_pins="1"/>
         <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" disabled_in_pack="true">
+        <mode name="physical" packable="false">
           <pb_type name="fabric" num_pb="1">
             <input name="in" num_pins="6"/>
             <input name="cin" num_pins="1"/>
diff --git a/vpr/src/pack/cluster.cpp b/vpr/src/pack/cluster.cpp
index fa9d4d8f8..51de31f7e 100644
--- a/vpr/src/pack/cluster.cpp
+++ b/vpr/src/pack/cluster.cpp
@@ -1458,6 +1458,11 @@ static enum e_block_pack_status try_place_atom_block_rec(const t_pb_graph_node*
     }
     pb_type = pb_graph_node->pb_type;
 
+    /* Xifan Tang: bypass unpackable modes */
+    if (false == pb_type->parent_mode->packable) {
+        return BLK_FAILED_FEASIBLE;
+    }
+
     is_primitive = (pb_type->num_modes == 0);
 
     if (is_primitive) {
diff --git a/vpr/src/pack/cluster_router.cpp b/vpr/src/pack/cluster_router.cpp
index d94691053..7f2cd37d9 100644
--- a/vpr/src/pack/cluster_router.cpp
+++ b/vpr/src/pack/cluster_router.cpp
@@ -1173,6 +1173,10 @@ static void expand_node_all_modes(t_lb_router_data* router_data, t_expansion_nod
         if (cur_mode != -1 && mode != cur_mode) {
             continue;
         }
+        /* Xifan Tang: Do not expand in unpackable modes */
+        if (false == pin->parent_node->pb_type->parent_mode->packable) {
+            continue;
+        }
 
         /* Check whether a mode is illegal. If it is then the node will not be expanded */
         bool is_illegal = false;
diff --git a/vpr/src/pack/prepack.cpp b/vpr/src/pack/prepack.cpp
index 28e8c2bc5..cf9ccdd6d 100644
--- a/vpr/src/pack/prepack.cpp
+++ b/vpr/src/pack/prepack.cpp
@@ -791,6 +791,13 @@ t_pack_molecule* alloc_and_load_pack_molecules(t_pack_patterns* list_of_pack_pat
      * TODO: Need to investigate better mapping strategies than first-fit
      */
     for (i = 0; i < num_packing_patterns; i++) {
+
+        /* Xifan Tang: skip patterns that belong to unpackable modes */
+        if ( (nullptr != list_of_pack_patterns[i].root_block->pb_type->parent_mode)
+          && (false == list_of_pack_patterns[i].root_block->pb_type->parent_mode->packable) ) {
+            continue;
+        }
+
         best_pattern = 0;
         for (j = 1; j < num_packing_patterns; j++) {
             if (is_used[best_pattern]) {
@@ -799,7 +806,7 @@ t_pack_molecule* alloc_and_load_pack_molecules(t_pack_patterns* list_of_pack_pat
                 best_pattern = j;
             }
         }
-        VTR_ASSERT(is_used[best_pattern] == false);
+        VTR_ASSERT(is_used[best_pattern] == false); 
         is_used[best_pattern] = true;
 
         auto blocks = atom_ctx.nlist.blocks();
@@ -1213,6 +1220,11 @@ static t_pb_graph_node* get_expected_lowest_cost_primitive_for_atom_block_in_pb_
         }
     } else {
         for (i = 0; i < curr_pb_graph_node->pb_type->num_modes; i++) {
+            /* Xifan Tang: early fail if this primitive in a unpackable mode */
+            if (false == curr_pb_graph_node->pb_type->modes[i].packable) {
+                continue;
+            }
+
             for (j = 0; j < curr_pb_graph_node->pb_type->modes[i].num_pb_type_children; j++) {
                 *cost = UNDEFINED;
                 cur = get_expected_lowest_cost_primitive_for_atom_block_in_pb_graph_node(blk_id, &curr_pb_graph_node->child_pb_graph_nodes[i][j][0], cost);

From 7a4137fdcfb6c55710417d7e5790d3eea38d65f2 Mon Sep 17 00:00:00 2001
From: Xifan Tang <tangxifan@gmail.com>
Date: Mon, 6 Apr 2020 18:37:05 -0600
Subject: [PATCH 384/645] doc update for packable XML syntax in VPR

---
 docs/source/arch_lang/addon_vpr_syntax.rst | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/docs/source/arch_lang/addon_vpr_syntax.rst b/docs/source/arch_lang/addon_vpr_syntax.rst
index c6ac221a2..18f61703a 100644
--- a/docs/source/arch_lang/addon_vpr_syntax.rst
+++ b/docs/source/arch_lang/addon_vpr_syntax.rst
@@ -10,10 +10,18 @@ Models, Complex blocks and Physical Tiles
   
 Each ``<pb_type>`` should contain a ``<mode>`` that describe the physical implementation of the ``<pb_type>``. Note that this is fully compatible to the VPR architecture XML syntax.
   
-``<model>`` should include the models that describe the primitive ``<pb_type>`` in physical mode.
-  
+.. note:: ``<model>`` should include the models that describe the primitive ``<pb_type>`` in physical mode.
+
 .. note:: Currently, OpenFPGA only supports 1 ``<equivalent_sites>`` to be defined under each ``<tile>``
 
+.. option:: <mode packable="<bool">/>
+
+  OpenFPGA allows users to define it a mode is packable for VPR.
+  By default, the packable is set to ``true``. 
+  This is mainly used for the mode that describes the physical implementation, which is typically not packable. Disable it in the packing and signficantly accelerate the packing runtime.
+
+  .. note:: Once a mode is set to unpackable, its child modes will be unpackable as well.
+
 Layout
 ~~~~~~
 

From 92a3a444f93b0d4ae50071e6034b9cfec96919ef Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 6 Apr 2020 20:44:00 -0600
Subject: [PATCH 385/645] update VPR7 to support global I/O ports

---
 openfpga/src/fabric/build_grid_modules.cpp    |  2 +
 .../SRC/check_circuit_library.cpp             |  5 +-
 .../libarchfpgavpr7/SRC/circuit_library.cpp   | 16 ++++
 .../libarchfpgavpr7/SRC/circuit_library.h     |  4 +
 vpr7_x2p/libarchfpgavpr7/SRC/read_xml_spice.c |  6 ++
 vpr7_x2p/libarchfpgavpr7/SRC/spice_types.h    |  1 +
 .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp |  5 +-
 .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h   |  3 +-
 .../vpr/SRC/fpga_x2p/base/module_manager.cpp  |  2 +-
 .../vpr/SRC/fpga_x2p/base/module_manager.h    |  2 +
 .../fpga_x2p/base/module_manager_utils.cpp    | 84 ++++++++++++++++---
 .../module_builder/build_grid_modules.cpp     | 71 +++++++++++++---
 .../fpga_x2p/verilog/verilog_writer_utils.cpp |  6 ++
 13 files changed, 180 insertions(+), 27 deletions(-)

diff --git a/openfpga/src/fabric/build_grid_modules.cpp b/openfpga/src/fabric/build_grid_modules.cpp
index 741632d1c..95e435f6f 100644
--- a/openfpga/src/fabric/build_grid_modules.cpp
+++ b/openfpga/src/fabric/build_grid_modules.cpp
@@ -145,6 +145,8 @@ void add_grid_module_nets_connect_pb_type_ports(ModuleManager& module_manager,
 }
 
 /********************************************************************
+ * Add module nets between primitive module and its internal circuit module
+ * This is only applicable to the primitive module of a grid
  *******************************************************************/
 static 
 void add_primitive_module_fpga_global_io_port(ModuleManager& module_manager,
diff --git a/vpr7_x2p/libarchfpgavpr7/SRC/check_circuit_library.cpp b/vpr7_x2p/libarchfpgavpr7/SRC/check_circuit_library.cpp
index e6f49a1c0..f0ed79a1c 100644
--- a/vpr7_x2p/libarchfpgavpr7/SRC/check_circuit_library.cpp
+++ b/vpr7_x2p/libarchfpgavpr7/SRC/check_circuit_library.cpp
@@ -352,9 +352,10 @@ size_t check_circuit_library_ports(const CircuitLibrary& circuit_lib) {
   /* Check global ports: make sure all the global ports are input ports */
   for (const auto& port : circuit_lib.ports()) {
     if ( (circuit_lib.port_is_global(port)) 
-      && (!circuit_lib.is_input_port(port)) ) {
+      && (!circuit_lib.is_input_port(port)) 
+      && (!circuit_lib.is_output_port(port)) ) {
       vpr_printf(TIO_MESSAGE_ERROR,
-                 "Circuit port (type=%s) of model (name=%s) is defined as global but not an input port!\n",
+                 "Circuit port (type=%s) of model (name=%s) is defined as global but not an input/output port!\n",
                  CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(circuit_lib.port_type(port))],
                  circuit_lib.model_name(port).c_str());
       num_err++;
diff --git a/vpr7_x2p/libarchfpgavpr7/SRC/circuit_library.cpp b/vpr7_x2p/libarchfpgavpr7/SRC/circuit_library.cpp
index 5b7c7b62d..2a5154e44 100644
--- a/vpr7_x2p/libarchfpgavpr7/SRC/circuit_library.cpp
+++ b/vpr7_x2p/libarchfpgavpr7/SRC/circuit_library.cpp
@@ -767,6 +767,12 @@ size_t CircuitLibrary::port_default_value(const CircuitPortId& circuit_port_id)
   return port_default_values_[circuit_port_id];
 }
 
+/* Return a flag if the port is used in mode-selection purpuse of a circuit model */
+bool CircuitLibrary::port_is_io(const CircuitPortId& circuit_port_id) const {
+  /* validate the circuit_port_id */
+  VTR_ASSERT(valid_circuit_port_id(circuit_port_id));
+  return port_is_io_[circuit_port_id];
+}
 
 /* Return a flag if the port is used in mode-selection purpuse of a circuit model */
 bool CircuitLibrary::port_is_mode_select(const CircuitPortId& circuit_port_id) const {
@@ -1212,6 +1218,7 @@ CircuitPortId CircuitLibrary::add_model_port(const CircuitModelId& model_id,
   port_lib_names_.emplace_back();
   port_inv_prefix_.emplace_back();
   port_default_values_.push_back(-1);
+  port_is_io_.push_back(false);
   port_is_mode_select_.push_back(false);
   port_is_global_.push_back(false);
   port_is_reset_.push_back(false);
@@ -1282,6 +1289,15 @@ void CircuitLibrary::set_port_default_value(const CircuitPortId& circuit_port_id
   return;
 }
 
+/* Set the is_mode_select for a port of a circuit model */
+void CircuitLibrary::set_port_is_io(const CircuitPortId& circuit_port_id, 
+                                    const bool& is_io) {
+  /* validate the circuit_port_id */
+  VTR_ASSERT(valid_circuit_port_id(circuit_port_id));
+  port_is_io_[circuit_port_id] = is_io;
+  return;
+}
+
 /* Set the is_mode_select for a port of a circuit model */
 void CircuitLibrary::set_port_is_mode_select(const CircuitPortId& circuit_port_id, 
                                              const bool& is_mode_select) {
diff --git a/vpr7_x2p/libarchfpgavpr7/SRC/circuit_library.h b/vpr7_x2p/libarchfpgavpr7/SRC/circuit_library.h
index 8080d2ea3..b76e2be63 100644
--- a/vpr7_x2p/libarchfpgavpr7/SRC/circuit_library.h
+++ b/vpr7_x2p/libarchfpgavpr7/SRC/circuit_library.h
@@ -281,6 +281,7 @@ class CircuitLibrary {
     std::string port_lib_name(const CircuitPortId& circuit_port_id) const;
     std::string port_inv_prefix(const CircuitPortId& circuit_port_id) const;
     size_t port_default_value(const CircuitPortId& circuit_port_id) const;
+    bool port_is_io(const CircuitPortId& circuit_port_id) const;
     bool port_is_mode_select(const CircuitPortId& circuit_port_id) const;
     bool port_is_global(const CircuitPortId& circuit_port_id) const;
     bool port_is_reset(const CircuitPortId& circuit_port_id) const;
@@ -351,6 +352,8 @@ class CircuitLibrary {
                              const std::string& inv_prefix);
     void set_port_default_value(const CircuitPortId& circuit_port_id, 
                                 const size_t& default_val);
+    void set_port_is_io(const CircuitPortId& circuit_port_id, 
+                        const bool& is_io);
     void set_port_is_mode_select(const CircuitPortId& circuit_port_id, 
                                  const bool& is_mode_select);
     void set_port_is_global(const CircuitPortId& circuit_port_id, 
@@ -534,6 +537,7 @@ class CircuitLibrary {
     vtr::vector<CircuitPortId, std::string> port_lib_names_;
     vtr::vector<CircuitPortId, std::string> port_inv_prefix_;
     vtr::vector<CircuitPortId, size_t> port_default_values_;
+    vtr::vector<CircuitPortId, bool> port_is_io_;
     vtr::vector<CircuitPortId, bool> port_is_mode_select_;
     vtr::vector<CircuitPortId, bool> port_is_global_;
     vtr::vector<CircuitPortId, bool> port_is_reset_;
diff --git a/vpr7_x2p/libarchfpgavpr7/SRC/read_xml_spice.c b/vpr7_x2p/libarchfpgavpr7/SRC/read_xml_spice.c
index c630dc37f..4c613e076 100644
--- a/vpr7_x2p/libarchfpgavpr7/SRC/read_xml_spice.c
+++ b/vpr7_x2p/libarchfpgavpr7/SRC/read_xml_spice.c
@@ -783,6 +783,11 @@ static void ProcessSpiceModelPort(ezxml_t Node,
   /* Output mast of a fracturable LUT, which is to identify which intermediate LUT output will be connected to outputs */
   ProcessSpiceModelPortLutOutputMask(Node, port);
 
+  if (SPICE_MODEL_PORT_INPUT == port->type) {
+    port->is_io = GetBooleanProperty(Node, "io", FALSE, FALSE);
+    ezxml_set_attr(Node, "io", NULL);
+  }
+
   /* See if this is a global signal 
    * We assume that global signals are shared by all the SPICE Model/blocks.
    * We need to check if other SPICE model has the same port name
@@ -1748,6 +1753,7 @@ CircuitLibrary build_circuit_library(int num_spice_model, t_spice_model* spice_m
 
       circuit_lib.set_port_default_value(port_id, spice_models[imodel].ports[iport].default_val);
 
+      circuit_lib.set_port_is_io(port_id, TRUE == spice_models[imodel].ports[iport].is_io);
       circuit_lib.set_port_is_mode_select(port_id, TRUE == spice_models[imodel].ports[iport].mode_select);
       circuit_lib.set_port_is_global(port_id, TRUE == spice_models[imodel].ports[iport].is_global);
       circuit_lib.set_port_is_reset(port_id, TRUE == spice_models[imodel].ports[iport].is_reset);
diff --git a/vpr7_x2p/libarchfpgavpr7/SRC/spice_types.h b/vpr7_x2p/libarchfpgavpr7/SRC/spice_types.h
index 26f30b164..97e1b02dc 100644
--- a/vpr7_x2p/libarchfpgavpr7/SRC/spice_types.h
+++ b/vpr7_x2p/libarchfpgavpr7/SRC/spice_types.h
@@ -164,6 +164,7 @@ struct s_spice_model_port {
   boolean mode_select;
   int default_val;
   /* Global port properties */
+  boolean is_io;
   boolean is_global;
   boolean is_reset;
   boolean is_set;
diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp
index 4f1e21d80..7a61ae6c8 100644
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp
@@ -1343,10 +1343,13 @@ std::string generate_pb_type_port_name(t_port* pb_type_port) {
  ********************************************************************/
 std::string generate_fpga_global_io_port_name(const std::string& prefix, 
                                               const CircuitLibrary& circuit_lib,
-                                              const CircuitModelId& circuit_model) {
+                                              const CircuitModelId& circuit_model,
+                                              const CircuitPortId& circuit_port) {
   std::string port_name(prefix);
   
   port_name += circuit_lib.model_name(circuit_model);
+  port_name += std::string("_");
+  port_name += circuit_lib.port_prefix(circuit_port);
    
   return port_name;
 }
diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h
index ad0a5932e..a62523f59 100644
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h
@@ -232,7 +232,8 @@ std::string generate_pb_type_port_name(t_port* pb_type_port);
 
 std::string generate_fpga_global_io_port_name(const std::string& prefix, 
                                               const CircuitLibrary& circuit_lib,
-                                              const CircuitModelId& circuit_model);
+                                              const CircuitModelId& circuit_model,
+                                              const CircuitPortId& circuit_port);
 
 std::string generate_fpga_top_module_name();
 
diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp
index 0281a5a5a..2cce352a3 100644
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp
@@ -117,7 +117,7 @@ std::string ModuleManager::module_name(const ModuleId& module_id) const {
 
 /* Get the string of a module port type */
 std::string ModuleManager::module_port_type_str(const enum e_module_port_type& port_type) const {
-  std::array<const char*, NUM_MODULE_PORT_TYPES> MODULE_PORT_TYPE_STRING = {{"GLOBAL PORTS", "GPIO PORTS", "INOUT PORTS", "INPUT PORTS", "OUTPUT PORTS", "CLOCK PORTS"}};
+  std::array<const char*, NUM_MODULE_PORT_TYPES> MODULE_PORT_TYPE_STRING = {{"GLOBAL PORTS", "GPIN PORTS", "GPOUT PORTS", "GPIO PORTS", "INOUT PORTS", "INPUT PORTS", "OUTPUT PORTS", "CLOCK PORTS"}};
   return MODULE_PORT_TYPE_STRING[port_type];
 }
 
diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h
index 9097dd603..7aaf528f3 100644
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h
@@ -26,6 +26,8 @@ class ModuleManager {
   public: /* Private data structures */
     enum e_module_port_type {
       MODULE_GLOBAL_PORT, /* Global inputs */
+      MODULE_GPIN_PORT,   /* General-purpose input */
+      MODULE_GPOUT_PORT,  /* General-purpose outputs, could be used for spypads */
       MODULE_GPIO_PORT,   /* General-purpose IOs, which are data IOs of the fabric */
       MODULE_INOUT_PORT,  /* Normal (non-global) inout ports */
       MODULE_INPUT_PORT,  /* Normal (non-global) input ports */
diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp
index f8c79a238..927506096 100644
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp
@@ -37,7 +37,18 @@ ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager,
   /* Find global ports and add one by one */
   for (const auto& port : circuit_lib.model_global_ports(circuit_model, false)) {
     BasicPort port_info(circuit_lib.port_prefix(port), circuit_lib.port_size(port));
-    module_manager.add_port(module, port_info, ModuleManager::MODULE_GLOBAL_PORT);  
+    if ( (SPICE_MODEL_PORT_INPUT == circuit_lib.port_type(port))
+      && (false == circuit_lib.port_is_io(port)) ) {
+      module_manager.add_port(module, port_info, ModuleManager::MODULE_GLOBAL_PORT);  
+    } else if (SPICE_MODEL_PORT_CLOCK == circuit_lib.port_type(port)) {
+      module_manager.add_port(module, port_info, ModuleManager::MODULE_GLOBAL_PORT);  
+    } else if ( (SPICE_MODEL_PORT_INPUT == circuit_lib.port_type(port))
+             && (true == circuit_lib.port_is_io(port)) ) {
+      module_manager.add_port(module, port_info, ModuleManager::MODULE_GPIN_PORT);  
+    } else {
+      VTR_ASSERT(SPICE_MODEL_PORT_OUTPUT == circuit_lib.port_type(port));
+      module_manager.add_port(module, port_info, ModuleManager::MODULE_GPOUT_PORT);  
+    }
   }
 
   /* Find other ports and add one by one */
@@ -925,19 +936,35 @@ size_t find_module_num_config_bits(const ModuleManager& module_manager,
 }
 
 /********************************************************************
- * Add GPIO ports to the module:
+ * Add General purpose I/O ports to the module:
  * In this function, the following tasks are done: 
- * 1. find all the GPIO ports from the child modules and build a list of it,
- * 2. Merge all the GPIO ports with the same name
+ * 1. find all the I/O ports from the child modules and build a list of it,
+ * 2. Merge all the I/O ports with the same name
  * 3. add the ports to the pb_module
  * 4. add module nets to connect to the GPIO ports of each sub module 
+ *
+ *   Module
+ *   ----------------------+
+ *                         |
+ *   child[0]              |
+ *   -----------+          |
+ *              |----------+----> outputA[0]
+ *   -----------+          |
+ *                         |
+ *   child[1]              |
+ *   -----------+          |
+ *              |----------+----> outputA[1]
+ *   -----------+          |
+
  *
  * Note: This function should be call ONLY after all the sub modules (instances)
  * have been added to the pb_module!
  * Otherwise, some GPIO ports of the sub modules may be missed!
  *******************************************************************/
-void add_module_gpio_ports_from_child_modules(ModuleManager& module_manager, 
-                                              const ModuleId& module_id) {
+static 
+void add_module_io_ports_from_child_modules(ModuleManager& module_manager, 
+                                            const ModuleId& module_id,
+                                            const ModuleManager::e_module_port_type& module_port_type) {
   std::vector<BasicPort> gpio_ports_to_add;
 
   /* Iterate over the child modules */
@@ -945,7 +972,7 @@ void add_module_gpio_ports_from_child_modules(ModuleManager& module_manager,
     /* Iterate over the child instances */
     for (size_t i = 0; i < module_manager.num_instance(module_id, child); ++i) {
       /* Find all the global ports, whose port type is special */
-      for (BasicPort gpio_port : module_manager.module_ports_by_type(child, ModuleManager::MODULE_GPIO_PORT)) {
+      for (BasicPort gpio_port : module_manager.module_ports_by_type(child, module_port_type)) {
         /* If this port is not mergeable, we update the list */
         bool is_mergeable = false;
         for (BasicPort& gpio_port_to_add : gpio_ports_to_add) {
@@ -973,7 +1000,7 @@ void add_module_gpio_ports_from_child_modules(ModuleManager& module_manager,
   std::vector<ModulePortId> gpio_port_ids;
   /* Add the gpio ports for the module */
   for (const BasicPort& gpio_port_to_add : gpio_ports_to_add) {
-    ModulePortId port_id = module_manager.add_port(module_id, gpio_port_to_add, ModuleManager::MODULE_GPIO_PORT);
+    ModulePortId port_id = module_manager.add_port(module_id, gpio_port_to_add, module_port_type);
     gpio_port_ids.push_back(port_id);
   } 
 
@@ -984,7 +1011,7 @@ void add_module_gpio_ports_from_child_modules(ModuleManager& module_manager,
     /* Iterate over the child instances */
     for (const size_t& child_instance : module_manager.child_module_instances(module_id, child)) {
       /* Find all the global ports, whose port type is special */
-      for (ModulePortId child_gpio_port_id : module_manager.module_port_ids_by_type(child, ModuleManager::MODULE_GPIO_PORT)) {
+      for (ModulePortId child_gpio_port_id : module_manager.module_port_ids_by_type(child, module_port_type)) {
         BasicPort child_gpio_port = module_manager.module_port(child, child_gpio_port_id);
         /* Find the port with the same name! */
         for (size_t iport = 0; iport < gpio_ports_to_add.size(); ++iport) {
@@ -995,8 +1022,22 @@ void add_module_gpio_ports_from_child_modules(ModuleManager& module_manager,
           for (const size_t& pin_id : child_gpio_port.pins()) {
             /* Reach here, it means this is the port we want, create a net and configure its source and sink */
             ModuleNetId net = module_manager.create_module_net(module_id);
-            module_manager.add_module_net_source(module_id, net, module_id, 0, gpio_port_ids[iport], gpio_port_lsb[iport]); 
-            module_manager.add_module_net_sink(module_id, net, child, child_instance, child_gpio_port_id, pin_id); 
+            /* - For GPIO and GPIN ports
+             *   the source of the net is the current module 
+             *   the sink of the net is the child module
+             * - For GPOUT ports
+             *   the source of the net is the child module
+             *   the sink of the net is the current module 
+             */
+            if ( (ModuleManager::MODULE_GPIO_PORT == module_port_type)
+              || (ModuleManager::MODULE_GPIN_PORT == module_port_type) ) {
+              module_manager.add_module_net_source(module_id, net, module_id, 0, gpio_port_ids[iport], gpio_port_lsb[iport]); 
+              module_manager.add_module_net_sink(module_id, net, child, child_instance, child_gpio_port_id, pin_id); 
+            } else {
+              VTR_ASSERT(ModuleManager::MODULE_GPOUT_PORT == module_port_type);
+              module_manager.add_module_net_sink(module_id, net, module_id, 0, gpio_port_ids[iport], gpio_port_lsb[iport]); 
+              module_manager.add_module_net_source(module_id, net, child, child_instance, child_gpio_port_id, pin_id); 
+            }
             /* Update the LSB counter */
             gpio_port_lsb[iport]++;
           }
@@ -1014,6 +1055,27 @@ void add_module_gpio_ports_from_child_modules(ModuleManager& module_manager,
   }
 }
 
+/********************************************************************
+ * Add GPIO ports to the module:
+ * In this function, the following tasks are done: 
+ * 1. find all the GPIO ports from the child modules and build a list of it,
+ * 2. Merge all the GPIO ports with the same name
+ * 3. add the ports to the pb_module
+ * 4. add module nets to connect to the GPIO ports of each sub module 
+ *
+ * Note: This function should be call ONLY after all the sub modules (instances)
+ * have been added to the pb_module!
+ * Otherwise, some GPIO ports of the sub modules may be missed!
+ *******************************************************************/
+void add_module_gpio_ports_from_child_modules(ModuleManager& module_manager, 
+                                              const ModuleId& module_id) {
+  add_module_io_ports_from_child_modules(module_manager, module_id, ModuleManager::MODULE_GPIO_PORT);
+
+  add_module_io_ports_from_child_modules(module_manager, module_id, ModuleManager::MODULE_GPIN_PORT);
+
+  add_module_io_ports_from_child_modules(module_manager, module_id, ModuleManager::MODULE_GPOUT_PORT);
+}
+
 /********************************************************************
  * Add global ports to the module:
  * In this function, the following tasks are done: 
diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp
index a0ead11dd..c7578292a 100644
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp
@@ -140,6 +140,41 @@ void add_grid_module_nets_connect_pb_type_ports(ModuleManager& module_manager,
   }
 }
 
+/********************************************************************
+ * Add module nets between primitive module and its internal circuit module
+ * This is only applicable to the primitive module of a grid
+ *******************************************************************/
+static 
+void add_primitive_module_fpga_global_io_port(ModuleManager& module_manager,
+                                              const ModuleId& primitive_module,
+                                              const ModuleId& logic_module,
+                                              const size_t& logic_instance_id,
+                                              const ModuleManager::e_module_port_type& module_io_port_type,
+                                              const CircuitLibrary& circuit_lib,
+                                              const CircuitModelId& primitive_model,
+                                              const CircuitPortId& circuit_port) {
+  BasicPort module_port(generate_fpga_global_io_port_name(std::string(gio_inout_prefix), circuit_lib, primitive_model, circuit_port), circuit_lib.port_size(circuit_port));
+  ModulePortId primitive_io_port_id = module_manager.add_port(primitive_module, module_port, module_io_port_type);
+  ModulePortId logic_io_port_id = module_manager.find_module_port(logic_module, circuit_lib.port_prefix(circuit_port));
+  BasicPort logic_io_port = module_manager.module_port(logic_module, logic_io_port_id);
+  VTR_ASSERT(logic_io_port.get_width() == module_port.get_width());
+
+  /* Wire the GPIO port form primitive_module to the logic module!*/
+  for (size_t pin_id = 0; pin_id < module_port.pins().size(); ++pin_id) {      
+    ModuleNetId net = module_manager.create_module_net(primitive_module);
+    if ( (ModuleManager::MODULE_GPIO_PORT == module_io_port_type)
+      || (ModuleManager::MODULE_GPIN_PORT == module_io_port_type) ) {
+      module_manager.add_module_net_source(primitive_module, net, primitive_module, 0, primitive_io_port_id, module_port.pins()[pin_id]);
+      module_manager.add_module_net_sink(primitive_module, net, logic_module, logic_instance_id, logic_io_port_id, logic_io_port.pins()[pin_id]);
+    } else {
+      VTR_ASSERT(ModuleManager::MODULE_GPOUT_PORT == module_io_port_type);
+      module_manager.add_module_net_source(primitive_module, net, logic_module, logic_instance_id, logic_io_port_id, logic_io_port.pins()[pin_id]);
+      module_manager.add_module_net_sink(primitive_module, net, primitive_module, 0, primitive_io_port_id, module_port.pins()[pin_id]);
+    }
+  }
+}
+
+
 /********************************************************************
  * Print Verilog modules of a primitive node in the pb_graph_node graph
  * This generic function can support all the different types of primitive nodes
@@ -274,18 +309,32 @@ void build_primitive_block_module(ModuleManager& module_manager,
   if (SPICE_MODEL_IOPAD == circuit_lib.model_type(primitive_model)) {
     std::vector<CircuitPortId> primitive_model_inout_ports = circuit_lib.model_ports_by_type(primitive_model, SPICE_MODEL_PORT_INOUT);
     for (auto port : primitive_model_inout_ports) {
-      BasicPort module_port(generate_fpga_global_io_port_name(std::string(gio_inout_prefix), circuit_lib, primitive_model), circuit_lib.port_size(port));
-      ModulePortId primitive_gpio_port_id = module_manager.add_port(primitive_module, module_port, ModuleManager::MODULE_GPIO_PORT);
-      ModulePortId logic_gpio_port_id = module_manager.find_module_port(logic_module, circuit_lib.port_prefix(port));
-      BasicPort logic_gpio_port = module_manager.module_port(logic_module, logic_gpio_port_id);
-      VTR_ASSERT(logic_gpio_port.get_width() == module_port.get_width());
+      add_primitive_module_fpga_global_io_port(module_manager, primitive_module,
+                                               logic_module, logic_instance_id,
+                                               ModuleManager::MODULE_GPIO_PORT,
+                                               circuit_lib,
+                                               primitive_model,
+                                               port);
+    }
+  }
 
-      /* Wire the GPIO port form primitive_module to the logic module!*/
-      for (size_t pin_id = 0; pin_id < module_port.pins().size(); ++pin_id) {      
-        ModuleNetId net = module_manager.create_module_net(primitive_module);
-        module_manager.add_module_net_source(primitive_module, net, primitive_module, 0, primitive_gpio_port_id, module_port.pins()[pin_id]);
-        module_manager.add_module_net_sink(primitive_module, net, logic_module, logic_instance_id, logic_gpio_port_id, logic_gpio_port.pins()[pin_id]);
-      }
+  /* Find the other i/o ports required by the primitive node, and add them to the module */
+  for (const auto& port : circuit_lib.model_global_ports(primitive_model, false)) {
+    if ( (SPICE_MODEL_PORT_INPUT == circuit_lib.port_type(port))
+      && (true == circuit_lib.port_is_io(port)) ) {
+      add_primitive_module_fpga_global_io_port(module_manager, primitive_module,
+                                               logic_module, logic_instance_id,
+                                               ModuleManager::MODULE_GPIN_PORT,
+                                               circuit_lib,
+                                               primitive_model,
+                                               port);
+    } else if (SPICE_MODEL_PORT_OUTPUT == circuit_lib.port_type(port)) {
+      add_primitive_module_fpga_global_io_port(module_manager, primitive_module,
+                                               logic_module, logic_instance_id,
+                                               ModuleManager::MODULE_GPOUT_PORT,
+                                               circuit_lib,
+                                               primitive_model,
+                                               port);
     }
   }
 }
diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp
index 4d892f05f..19c7e59a4 100644
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp
@@ -125,6 +125,8 @@ void print_verilog_module_definition(std::fstream& fp,
   /* port type2type mapping */
   std::map<ModuleManager::e_module_port_type, enum e_dump_verilog_port_type> port_type2type_map;
   port_type2type_map[ModuleManager::MODULE_GLOBAL_PORT] = VERILOG_PORT_CONKT;
+  port_type2type_map[ModuleManager::MODULE_GPIN_PORT] = VERILOG_PORT_CONKT;
+  port_type2type_map[ModuleManager::MODULE_GPOUT_PORT] = VERILOG_PORT_CONKT;
   port_type2type_map[ModuleManager::MODULE_GPIO_PORT] = VERILOG_PORT_CONKT;
   port_type2type_map[ModuleManager::MODULE_INOUT_PORT] = VERILOG_PORT_CONKT;
   port_type2type_map[ModuleManager::MODULE_INPUT_PORT] = VERILOG_PORT_CONKT;
@@ -184,6 +186,8 @@ void print_verilog_module_ports(std::fstream& fp,
   /* port type2type mapping */
   std::map<ModuleManager::e_module_port_type, enum e_dump_verilog_port_type> port_type2type_map;
   port_type2type_map[ModuleManager::MODULE_GLOBAL_PORT] = VERILOG_PORT_INPUT;
+  port_type2type_map[ModuleManager::MODULE_GPIN_PORT] = VERILOG_PORT_INPUT;
+  port_type2type_map[ModuleManager::MODULE_GPOUT_PORT] = VERILOG_PORT_OUTPUT;
   port_type2type_map[ModuleManager::MODULE_GPIO_PORT] = VERILOG_PORT_INOUT;
   port_type2type_map[ModuleManager::MODULE_INOUT_PORT] = VERILOG_PORT_INOUT;
   port_type2type_map[ModuleManager::MODULE_INPUT_PORT] = VERILOG_PORT_INPUT;
@@ -340,6 +344,8 @@ void print_verilog_module_instance(std::fstream& fp,
   /* port type2type mapping */
   std::map<ModuleManager::e_module_port_type, enum e_dump_verilog_port_type> port_type2type_map;
   port_type2type_map[ModuleManager::MODULE_GLOBAL_PORT] = VERILOG_PORT_CONKT;
+  port_type2type_map[ModuleManager::MODULE_GPIN_PORT] = VERILOG_PORT_CONKT;
+  port_type2type_map[ModuleManager::MODULE_GPOUT_PORT] = VERILOG_PORT_CONKT;
   port_type2type_map[ModuleManager::MODULE_GPIO_PORT] = VERILOG_PORT_CONKT;
   port_type2type_map[ModuleManager::MODULE_INOUT_PORT] = VERILOG_PORT_CONKT;
   port_type2type_map[ModuleManager::MODULE_INPUT_PORT] = VERILOG_PORT_CONKT;

From d39d7a68cee9ae63af0034d170e56e9d564c9fe8 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 7 Apr 2020 10:46:49 -0600
Subject: [PATCH 386/645] add test cases for using tree-like multiplexer

---
 .../k6_frac_N10_tree_mux_40nm_openfpga.xml    | 256 ++++++++++++++++++
 .../and_k6_frac_tileable_tree_mux.openfpga    |  59 ++++
 2 files changed, 315 insertions(+)
 create mode 100644 openfpga/test_openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml
 create mode 100644 openfpga/test_script/and_k6_frac_tileable_tree_mux.openfpga

diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml
new file mode 100644
index 000000000..dc0fa4c27
--- /dev/null
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml
@@ -0,0 +1,256 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
+      <design_technology type="cmos" topology="OR"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_tree" prefix="mux_tree" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <!--mux2to1 subckt_name="mux2to1"/-->
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_tree_tapbuf" prefix="mux_tree_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <!--mux2to1 subckt_name="mux2to1"/-->
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <pass_gate_logic circuit_model_name="TGATE"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
+      <design_technology type="cmos" fracturable_lut="true"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="6" tri_state_map="-----1" circuit_model_name="OR2"/>
+      <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
+      <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
+      <port type="sram" prefix="sram" size="64"/>
+      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <pass_gate_logic circuit_model_name="TGATE"/>
+       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="Qb" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="inout" prefix="pad" size="1"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+      <port type="input" prefix="outpad" size="1"/>
+      <port type="output" prefix="inpad" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_tree_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_tree"/>
+    </pb_type>
+    <pb_type name="clb.fle" physical_mode_name="physical"/>
+    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="0"/>
+    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
+    <!-- Binding operating pb_type to physical pb_type -->
+    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="1" physical_pb_type_index_factor="0.5">
+      <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:4]"/>
+      <port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="0">
+      <!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:5]"/>
+      <port name="out" physical_mode_port="lut6_out"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>
+<openfpga_simulation_setting>
+  <clock_setting>
+    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
+    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
+    <programming frequency="10e6"/>
+  </clock_setting>
+  <simulator_option>
+    <operating_condition temperature="25"/>
+    <output_log verbose="false" captab="false"/>
+    <accuracy type="abs" value="1e-13"/>
+    <runtime fast_simulation="true"/>
+  </simulator_option>
+  <monte_carlo num_simulation_points="2"/>
+  <measurement_setting>
+    <slew>
+      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
+      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
+    </slew>
+    <delay>
+      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
+      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
+    </delay>
+  </measurement_setting>
+  <stimulus>
+    <clock>
+      <rise slew_type="abs" slew_time="20e-12" />
+      <fall slew_type="abs" slew_time="20e-12" />
+    </clock>
+    <input>
+      <rise slew_type="abs" slew_time="25e-12" />
+      <fall slew_type="abs" slew_time="25e-12" />
+    </input>
+  </stimulus>
+</openfpga_simulation_setting>
diff --git a/openfpga/test_script/and_k6_frac_tileable_tree_mux.openfpga b/openfpga/test_script/and_k6_frac_tileable_tree_mux.openfpga
new file mode 100644
index 000000000..95cd2a3c3
--- /dev/null
+++ b/openfpga/test_script/and_k6_frac_tileable_tree_mux.openfpga
@@ -0,0 +1,59 @@
+# Run VPR for the 'and' design
+vpr ./test_vpr_arch/k6_frac_N10_tileable_40nm.xml ./test_blif/and.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml
+
+# Write out the architecture XML as a proof
+#write_openfpga_arch -f ./arch_echo.xml
+
+# Annotate the OpenFPGA architecture to VPR data base
+link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to clustering nets based on routing results
+pb_pin_fixup --verbose
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup #--verbose
+
+# Build the module graph 
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules 
+build_fabric --compress_routing --duplicate_grid_pin #--verbose
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream 
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here 
+write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
+
+# Finish and exit OpenFPGA
+exit

From 6d6295ef93f93a50a151a32d1bff878a7ab2cbc1 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 7 Apr 2020 11:12:47 -0600
Subject: [PATCH 387/645] Add test cases about using standard cell mux2

---
 .../k6_frac_N10_stdcell_mux_40nm_openfpga.xml | 252 ++++++++++++++++++
 ...and_k6_frac_tileable_stdcell_mux2.openfpga |  59 ++++
 2 files changed, 311 insertions(+)
 create mode 100644 openfpga/test_openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml
 create mode 100644 openfpga/test_script/and_k6_frac_tileable_stdcell_mux2.openfpga

diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml
new file mode 100644
index 000000000..d3e3d1f6c
--- /dev/null
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml
@@ -0,0 +1,252 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
+      <design_technology type="cmos" topology="OR"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <!-- Define a circuit model for the standard cell MUX2 
+         OpenFPGA requires the following truth table for the MUX2
+         When the select signal sel is enabled, the first input, i.e., in0 
+         will be propagated to the output, i.e., out
+         If your standard cell provider does not offer the exact truth table,
+         you can simply swap the inputs as shown in the example below
+      -->
+    <circuit_model type="gate" name="stdcell_mux2" prefix="stdcell_mux2" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/sc_mux2.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/sc_mux2.v">
+      <design_technology type="cmos" topology="MUX2"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in0" lib_name="B" size="1"/>
+      <port type="input" prefix="in1" lib_name="A" size="1"/>
+      <port type="input" prefix="sel" lib_name="S" size="1"/>
+      <port type="output" prefix="out" lib_name="Y" size="1"/>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_tree" prefix="mux_tree" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="stdcell_mux2"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_tree_tapbuf" prefix="mux_tree_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="stdcell_mux2"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
+      <design_technology type="cmos" fracturable_lut="true"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
+      <pass_gate_logic circuit_model_name="stdcell_mux2"/>
+      <port type="input" prefix="in" size="6" tri_state_map="-----1" circuit_model_name="OR2"/>
+      <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
+      <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
+      <port type="sram" prefix="sram" size="64"/>
+      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="Qb" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="inout" prefix="pad" size="1"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+      <port type="input" prefix="outpad" size="1"/>
+      <port type="output" prefix="inpad" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_tree_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_tree"/>
+    </pb_type>
+    <pb_type name="clb.fle" physical_mode_name="physical"/>
+    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="0"/>
+    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
+    <!-- Binding operating pb_type to physical pb_type -->
+    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="1" physical_pb_type_index_factor="0.5">
+      <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:4]"/>
+      <port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="0">
+      <!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:5]"/>
+      <port name="out" physical_mode_port="lut6_out"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>
+<openfpga_simulation_setting>
+  <clock_setting>
+    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
+    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
+    <programming frequency="10e6"/>
+  </clock_setting>
+  <simulator_option>
+    <operating_condition temperature="25"/>
+    <output_log verbose="false" captab="false"/>
+    <accuracy type="abs" value="1e-13"/>
+    <runtime fast_simulation="true"/>
+  </simulator_option>
+  <monte_carlo num_simulation_points="2"/>
+  <measurement_setting>
+    <slew>
+      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
+      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
+    </slew>
+    <delay>
+      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
+      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
+    </delay>
+  </measurement_setting>
+  <stimulus>
+    <clock>
+      <rise slew_type="abs" slew_time="20e-12" />
+      <fall slew_type="abs" slew_time="20e-12" />
+    </clock>
+    <input>
+      <rise slew_type="abs" slew_time="25e-12" />
+      <fall slew_type="abs" slew_time="25e-12" />
+    </input>
+  </stimulus>
+</openfpga_simulation_setting>
diff --git a/openfpga/test_script/and_k6_frac_tileable_stdcell_mux2.openfpga b/openfpga/test_script/and_k6_frac_tileable_stdcell_mux2.openfpga
new file mode 100644
index 000000000..04ff99d8c
--- /dev/null
+++ b/openfpga/test_script/and_k6_frac_tileable_stdcell_mux2.openfpga
@@ -0,0 +1,59 @@
+# Run VPR for the 'and' design
+vpr ./test_vpr_arch/k6_frac_N10_tileable_40nm.xml ./test_blif/and.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml
+
+# Write out the architecture XML as a proof
+#write_openfpga_arch -f ./arch_echo.xml
+
+# Annotate the OpenFPGA architecture to VPR data base
+link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to clustering nets based on routing results
+pb_pin_fixup --verbose
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup #--verbose
+
+# Build the module graph 
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules 
+build_fabric --compress_routing --duplicate_grid_pin #--verbose
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream 
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here 
+write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
+
+# Finish and exit OpenFPGA
+exit

From 0eeb8e5317e1fb8eadce40560f4bae814ce8949f Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 7 Apr 2020 11:24:42 -0600
Subject: [PATCH 388/645] clean up example architecture XML by removing
 redundant syntax

---
 openfpga/test_openfpga_arch/k6_N10_40nm_openfpga.xml     | 6 ------
 .../test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml     | 6 ------
 .../k6_frac_N10_adder_chain_40nm_openfpga.xml            | 7 -------
 .../k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml     | 8 --------
 .../k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml | 9 ---------
 .../k6_frac_N10_adder_column_chain_40nm_openfpga.xml     | 7 -------
 .../k6_frac_N10_spyio_40nm_openfpga.xml                  | 6 ------
 .../k6_frac_N10_tree_mux_40nm_openfpga.xml               | 5 -----
 8 files changed, 54 deletions(-)

diff --git a/openfpga/test_openfpga_arch/k6_N10_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_N10_40nm_openfpga.xml
index d93495f6b..17eb8b550 100644
--- a/openfpga/test_openfpga_arch/k6_N10_40nm_openfpga.xml
+++ b/openfpga/test_openfpga_arch/k6_N10_40nm_openfpga.xml
@@ -96,7 +96,6 @@
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -106,7 +105,6 @@
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -116,7 +114,6 @@
       <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -127,7 +124,6 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <pass_gate_logic circuit_model_name="TGATE"/>
        <port type="input" prefix="D" size="1"/>
        <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
        <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
@@ -150,7 +146,6 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <pass_gate_logic circuit_model_name="TGATE"/>
        <port type="input" prefix="pReset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
        <port type="input" prefix="D" size="1"/>
        <port type="output" prefix="Q" size="1"/>
@@ -161,7 +156,6 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="inout" prefix="pad" size="1"/>
       <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
       <port type="input" prefix="outpad" size="1"/>
diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
index b750f9736..c43614ae8 100644
--- a/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
@@ -110,7 +110,6 @@
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -120,7 +119,6 @@
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -130,7 +128,6 @@
       <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -141,7 +138,6 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <pass_gate_logic circuit_model_name="TGATE"/>
        <port type="input" prefix="D" size="1"/>
        <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
        <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
@@ -167,7 +163,6 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <pass_gate_logic circuit_model_name="TGATE"/>
        <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
        <port type="input" prefix="D" size="1"/>
        <port type="output" prefix="Q" size="1"/>
@@ -178,7 +173,6 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="inout" prefix="pad" size="1"/>
       <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
       <port type="input" prefix="outpad" size="1"/>
diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
index 98823698f..cf619cd27 100644
--- a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
@@ -110,7 +110,6 @@
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -120,7 +119,6 @@
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -130,7 +128,6 @@
       <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -141,7 +138,6 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <pass_gate_logic circuit_model_name="TGATE"/>
        <port type="input" prefix="D" size="1"/>
        <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
        <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
@@ -168,7 +164,6 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <pass_gate_logic circuit_model_name="TGATE"/>
        <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
        <port type="input" prefix="D" size="1"/>
        <port type="output" prefix="Q" size="1"/>
@@ -179,7 +174,6 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="inout" prefix="pad" size="1"/>
       <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
       <port type="input" prefix="outpad" size="1"/>
@@ -189,7 +183,6 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="a" size="1"/>
       <port type="input" prefix="b" size="1"/>
       <port type="input" prefix="cin" size="1"/>
diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
index 9f37c1293..4ddf1dd0b 100644
--- a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
@@ -110,7 +110,6 @@
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -120,7 +119,6 @@
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -130,7 +128,6 @@
       <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -141,7 +138,6 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <pass_gate_logic circuit_model_name="TGATE"/>
        <port type="input" prefix="D" size="1"/>
        <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
        <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
@@ -168,7 +164,6 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <pass_gate_logic circuit_model_name="TGATE"/>
        <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
        <port type="input" prefix="D" size="1"/>
        <port type="output" prefix="Q" size="1"/>
@@ -179,7 +174,6 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="inout" prefix="pad" size="1"/>
       <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
       <port type="input" prefix="outpad" size="1"/>
@@ -189,7 +183,6 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="a" size="1"/>
       <port type="input" prefix="b" size="1"/>
       <port type="input" prefix="cin" size="1"/>
@@ -200,7 +193,6 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="waddr" size="10"/>
       <port type="input" prefix="raddr" size="10"/>
       <port type="input" prefix="d_in" size="32"/>
diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
index ea56fe036..f0e84e167 100644
--- a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
@@ -110,7 +110,6 @@
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -120,7 +119,6 @@
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -130,7 +128,6 @@
       <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -141,7 +138,6 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <pass_gate_logic circuit_model_name="TGATE"/>
        <port type="input" prefix="D" size="1"/>
        <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
        <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
@@ -168,7 +164,6 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <pass_gate_logic circuit_model_name="TGATE"/>
        <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
        <port type="input" prefix="D" size="1"/>
        <port type="output" prefix="Q" size="1"/>
@@ -179,7 +174,6 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="inout" prefix="pad" size="1"/>
       <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
       <port type="input" prefix="outpad" size="1"/>
@@ -189,7 +183,6 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="a" size="1"/>
       <port type="input" prefix="b" size="1"/>
       <port type="input" prefix="cin" size="1"/>
@@ -200,7 +193,6 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="waddr" size="10"/>
       <port type="input" prefix="raddr" size="10"/>
       <port type="input" prefix="d_in" size="32"/>
@@ -213,7 +205,6 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="tx_data" size="80"/>
       <port type="output" prefix="rx_data" size="80"/>
       <port type="clock" prefix="tx_clk" size="1" default_val="0"/>
diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml
index 34f44d153..d70ebcb2d 100644
--- a/openfpga/test_openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml
@@ -110,7 +110,6 @@
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -120,7 +119,6 @@
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -130,7 +128,6 @@
       <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -141,7 +138,6 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <pass_gate_logic circuit_model_name="TGATE"/>
        <port type="input" prefix="D" size="1"/>
        <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
        <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
@@ -168,7 +164,6 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <pass_gate_logic circuit_model_name="TGATE"/>
        <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
        <port type="input" prefix="D" size="1"/>
        <port type="output" prefix="Q" size="1"/>
@@ -179,7 +174,6 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="inout" prefix="pad" size="1"/>
       <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
       <port type="input" prefix="outpad" size="1"/>
@@ -189,7 +183,6 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="a" size="1"/>
       <port type="input" prefix="b" size="1"/>
       <port type="input" prefix="cin" size="1"/>
diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml
index 2b432ce86..547c742c8 100644
--- a/openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml
@@ -110,7 +110,6 @@
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -120,7 +119,6 @@
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -130,7 +128,6 @@
       <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -141,7 +138,6 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <pass_gate_logic circuit_model_name="TGATE"/>
        <port type="input" prefix="D" size="1"/>
        <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
        <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
@@ -167,7 +163,6 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <pass_gate_logic circuit_model_name="TGATE"/>
        <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
        <port type="input" prefix="D" size="1"/>
        <port type="output" prefix="Q" size="1"/>
@@ -178,7 +173,6 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="inout" prefix="pad" size="1"/>
       <!-- A spypad for the direction port of the I/O pad, which can be visible in the fpga_top -->
       <port type="input" prefix="din" size="1" is_global="true" io="true" default_value="0"/>
diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml
index dc0fa4c27..bcbcb7e00 100644
--- a/openfpga/test_openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml
@@ -110,7 +110,6 @@
       <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -120,7 +119,6 @@
       <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -131,7 +129,6 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <pass_gate_logic circuit_model_name="TGATE"/>
        <port type="input" prefix="D" size="1"/>
        <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
        <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
@@ -157,7 +154,6 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <pass_gate_logic circuit_model_name="TGATE"/>
        <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
        <port type="input" prefix="D" size="1"/>
        <port type="output" prefix="Q" size="1"/>
@@ -168,7 +164,6 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="inout" prefix="pad" size="1"/>
       <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
       <port type="input" prefix="outpad" size="1"/>

From e61e7167b3fab389b0d51a2269b7cbcd684e0d2f Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 7 Apr 2020 11:27:16 -0600
Subject: [PATCH 389/645] update circuit model names in the example tree-like
 MUX architecture

---
 .../k6_frac_N10_tree_mux_40nm_openfpga.xml                | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml
index bcbcb7e00..8052fb2dc 100644
--- a/openfpga/test_openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml
@@ -75,7 +75,7 @@
         10e-12 5e-12
       </delay_matrix>
     </circuit_model>
-    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+    <circuit_model type="pass_gate" name="MUX2" prefix="MUX2" is_default="true">
       <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
       <input_buffer exist="false"/>
       <output_buffer exist="false"/>
@@ -110,7 +110,7 @@
       <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
+      <pass_gate_logic circuit_model_name="MUX2"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
       <port type="sram" prefix="sram" size="1"/>
@@ -119,7 +119,7 @@
       <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
+      <pass_gate_logic circuit_model_name="MUX2"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
       <port type="sram" prefix="sram" size="1"/>
@@ -142,7 +142,7 @@
       <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
       <lut_input_buffer exist="true" circuit_model_name="buf4"/>
       <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
+      <pass_gate_logic circuit_model_name="MUX2"/>
       <port type="input" prefix="in" size="6" tri_state_map="-----1" circuit_model_name="OR2"/>
       <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
       <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>

From 55e68896d6de137b8deb3043e2a3c117db681675 Mon Sep 17 00:00:00 2001
From: Xifan Tang <tangxifan@gmail.com>
Date: Tue, 7 Apr 2020 12:01:13 -0600
Subject: [PATCH 390/645] doc update for the support on std cell MUX2 and
 examples

---
 .../arch_lang/circuit_model_examples.rst      | 46 ++++++++++++++++++-
 1 file changed, 45 insertions(+), 1 deletion(-)

diff --git a/docs/source/arch_lang/circuit_model_examples.rst b/docs/source/arch_lang/circuit_model_examples.rst
index 3a749e49d..9b689d2f7 100644
--- a/docs/source/arch_lang/circuit_model_examples.rst
+++ b/docs/source/arch_lang/circuit_model_examples.rst
@@ -260,7 +260,6 @@ Template
     <port type="output" prefix="<string>" lib_name="<string>" size="<int>"/>
   </circuit_model>
 
-
 .. option:: <design_technology type="cmos" topology="<string>"/>
   
   - ``topology="AND|OR|MUX2"`` Specify the logic functionality of a gate. As for standard cells, the size of each port is limited to 1. Currently, only 2-input and single-output logic gates are supported.
@@ -290,6 +289,29 @@ This example shows:
   - Propagation delay from input ``a`` to ``out`` is 10ps in rising edge and and 8ps in falling edge
   - Propagation delay from input ``b`` to ``out`` is 10ps in rising edge and 7ps in falling edge
 
+MUX2 Gate Example
+```````````````````````
+
+.. code-block:: xml
+
+    <circuit_model type="gate" name="MUX2" prefix="MUX2" is_default="true" verilog_netlist="sc_mux.v">
+      <design_technology type="cmos" topology="MUX2"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in0" lib_name="B" size="1"/>
+      <port type="input" prefix="in1" lib_name="A" size="1"/>
+      <port type="input" prefix="sel" lib_name="S" size="1"/>
+      <port type="output" prefix="out" lib_name="Y" size="1"/>
+    </circuit_model>
+
+This example shows:
+  - A 2-input MUX gate with two inputs ``in0`` and ``in1``, a select port ``sel`` and an output port ``out``
+  - The Verilog of MUX2 gate is provided by the user in the netlist ``sc_mux.v``
+  - The use of ``lib_name`` to bind to a Verilog module with different port names.
+  - When binding to the Verilog module, the inputs will be swapped. In other words, ``in0`` of the circuit model will be wired to the input ``B`` of the MUX2 cell, while ``in1`` of the circuit model will be wired to the input ``A`` of the MUX2 cell.
+
+.. note:: OpenFPGA requires a fixed truth table for the ``MUX2`` gate. When the select signal sel is enabled, the first input, i.e., ``in0``, will be propagated to the output, i.e., ``out``. If your standard cell provider does not offer the exact truth table, you can simply swap the inputs as shown in the example.
+
 Multiplexers
 ~~~~~~~~~~~~
 
@@ -330,6 +352,8 @@ Template
 
 .. note:: For tree-like multiplexers, they can be built with standard cell MUX2. To enable this, users should define a ``circuit_model``, which describes a 2-input multiplexer (See details and examples in how to define a logic gate using ``circuit_model``. In this case, the ``circuit_model_name`` in the ``pass_gate_logic`` should be the name of MUX2 ``circuit_model``.
 
+.. note:: When multiplexers are not provided by users, the size of ports do not have to be consistent with actual numbers in the architecture.
+
 One-level Mux Example
 `````````````````````
 
@@ -398,6 +422,26 @@ This example shows:
   - The multiplexer will be built by transmission gate using the circuit model ``tgate``
   - The multiplexer will have 4 inputs and 3 SRAMs to control which datapath to propagate
 
+Standard Cell Multiplexer Example
+`````````````````````````````````
+.. code-block:: xml
+
+  <circuit_model type="mux" name="mux_stdcell" prefix="mux_stdcell">
+    <design_technology type="cmos" structure="tree"/>
+    <input_buffer exist="on" circuit_model_name="inv1x"/>
+    <output_buffer exist="on" circuit_model_name="tapdrive4"/>
+    <pass_gate_logic circuit_model_name="MUX2"/>
+    <port type="input" prefix="in" size="4"/>
+    <port type="output" prefix="out" size="1"/>
+    <port type="sram" prefix="sram" size="3"/>
+  </circuit_model>
+
+This example shows:
+  - A tree-like 4-input CMOS multiplexer built by the standard cell ``MUX2``
+  - All the inputs will be buffered using the circuit model ``inv1x``
+  - All the outputs will be buffered using the circuit model ``tapbuf4``
+  - The multiplexer will have 4 inputs and 3 SRAMs to control which datapath to propagate
+
 Look-Up Tables
 ~~~~~~~~~~~~~~
 

From 307ef58c45ef00d3e5511b960d98c0f0156c636f Mon Sep 17 00:00:00 2001
From: Xifan Tang <tangxifan@gmail.com>
Date: Tue, 7 Apr 2020 12:30:23 -0600
Subject: [PATCH 391/645] update README to remove dead links

---
 README.md | 10 +++-------
 1 file changed, 3 insertions(+), 7 deletions(-)

diff --git a/README.md b/README.md
index efc0d0ad3..b6b67116c 100644
--- a/README.md
+++ b/README.md
@@ -3,10 +3,10 @@
 [![Documentation Status](https://readthedocs.org/projects/openfpga/badge/?version=master)](https://openfpga.readthedocs.io/en/master/?badge=master)
 
 ## Introduction
-The OpenFPGA framework is the **first open-source FPGA IP generator** supporting highly-customizable homogeneous FPGA architectures. OpenFPGA provides a full set of EDA support for customized FPGAs, including Verilog-to-bitstream generation and self-testing verification [testbenches/scripts](./testbenches/scripts) OpenFPGA opens the door to democratizing FPGA technology and EDA techniques, with agile prototyping approaches and constantly evolving EDA tools for chip designers and researchers.
+The OpenFPGA framework is the **first open-source FPGA IP generator** supporting highly-customizable homogeneous FPGA architectures. OpenFPGA provides a full set of EDA support for customized FPGAs, including Verilog-to-bitstream generation and self-testing verification. OpenFPGA opens the door to democratizing FPGA technology and EDA techniques, with agile prototyping approaches and constantly evolving EDA tools for chip designers and researchers.
 
 ## Compilation
-Dependencies and help using docker can be found [**here**](./docs/source/tutorials/building.rst).
+Dependencies and help using docker can be found [**here**](./docs/source/tutorials/compile.rst).
 
 **Compilation Steps:**
 ```bash
@@ -31,7 +31,6 @@ python3 openfpga_flow/scripts/run_fpga_task.py compilation_verification --debug
 We currently target OpenFPGA for:
  1. Ubuntu 18.04
  2. Red Hat 7.5
- 3. MacOS Mojave 10.14.4
 
 *The tool was tested with these operating systems. It might work with earlier versions and other distributions.*
 
@@ -39,7 +38,4 @@ We currently target OpenFPGA for:
 OpenFPGA's [full documentation](https://openfpga.readthedocs.io/en/master/) includes tutorials, descriptions of the design flow, and tool options.
 
 ## Tutorials
-You can find some tutorials in the [**./tutorials**](./tutorials) folder. This will help you get more familiar with the tool and use OpenFPGA under different configurations. 
-
-Through those tutorials, users can learn how to use the flow and install the different dependencies.
-The [tutorial index](./tutorials/tutorial_index.md) will guide you through training and explain the folder oraganization as well as introducing some tips and commonly used keywords.
+You can find some tutorials in the [**./tutorials**](./docs/source/tutorials/) folder. This will help you get more familiar with the tool and use OpenFPGA under different configurations. 

From 26d1261c1f726d456db130d9429a20c27f74fa30 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 7 Apr 2020 15:09:10 -0600
Subject: [PATCH 392/645] add test cases using shift registers

---
 openfpga/src/repack/check_lb_rr_graph.cpp     |   4 +-
 ...N10_adder_register_chain_40nm_openfpga.xml | 288 ++++++++
 ...N10_tileable_adder_register_chain_40nm.xml | 696 ++++++++++++++++++
 3 files changed, 986 insertions(+), 2 deletions(-)
 create mode 100644 openfpga/test_openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml
 create mode 100644 openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_chain_40nm.xml

diff --git a/openfpga/src/repack/check_lb_rr_graph.cpp b/openfpga/src/repack/check_lb_rr_graph.cpp
index 9b3adbf8f..64b286b62 100644
--- a/openfpga/src/repack/check_lb_rr_graph.cpp
+++ b/openfpga/src/repack/check_lb_rr_graph.cpp
@@ -79,8 +79,8 @@ static bool check_lb_rr_graph_dangling_nodes(const LbRRGraph& lb_rr_graph) {
     if ((0 == lb_rr_graph.node_in_edges(node).size())
       && (0 == lb_rr_graph.node_out_edges(node).size())) {
       /* Print a warning! */
-      VTR_LOG_WARN("Node %s is dangling (zero fan-in and zero fan-out)!\n",
-             node);
+      VTR_LOG_WARN("Node %lu is dangling (zero fan-in and zero fan-out)!\n",
+                   size_t(node));
       VTR_LOG_WARN("Node details for debugging:\n");
       print_lb_rr_node(lb_rr_graph, node);
       no_dangling = false;
diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml
new file mode 100644
index 000000000..81a9582dc
--- /dev/null
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml
@@ -0,0 +1,288 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
+      <design_technology type="cmos" topology="OR"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
+      <design_technology type="cmos" fracturable_lut="true"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="6" tri_state_map="----11" circuit_model_name="OR2"/>
+      <port type="output" prefix="lut4_out" size="4" lut_frac_level="4" lut_output_mask="0,1,2,3"/>
+      <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
+      <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
+      <port type="sram" prefix="sram" size="64"/>
+      <port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="Qb" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="inout" prefix="pad" size="1"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+      <port type="input" prefix="outpad" size="1"/>
+      <port type="output" prefix="inpad" size="1"/>
+    </circuit_model>
+    <circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="input" prefix="cin" size="1"/>
+      <port type="output" prefix="sumout" size="1"/>
+      <port type="output" prefix="cout" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <direct_connection>
+    <direct name="adder_carry" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
+    <direct name="shift_register" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
+  </direct_connection>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle" physical_mode_name="physical"/>
+    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
+    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
+    <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="adder"/>
+    <!-- Binding operating pb_type to physical pb_type -->
+    <!-- Binding operating pb_types in mode 'n2_lut5' -->
+    <pb_type name="clb.fle[n2_lut5].ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5">
+      <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:4]"/>
+      <port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[n2_lut5].ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <!-- Binding operating pb_types in mode 'arithmetic' -->
+    <pb_type name="clb.fle[arithmetic].arithmetic.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="11" physical_pb_type_index_factor="0.25">
+      <!-- Binding the lut4 to the first 4 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:3]"/>
+      <port name="out" physical_mode_port="lut4_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[arithmetic].arithmetic.adder" physical_pb_type_name="clb.fle[physical].fabric.adder"/>
+    <pb_type name="clb.fle[arithmetic].arithmetic.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <!-- Binding operating pb_types in mode 'ble6' -->
+    <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="00">
+      <!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:5]"/>
+      <port name="out" physical_mode_port="lut6_out"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
+    <!-- Binding operating pb_types in mode 'shift_register' -->
+    <pb_type name="clb.fle[shift_register].shift_reg.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>
+<openfpga_simulation_setting>
+  <clock_setting>
+    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
+    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
+    <programming frequency="10e6"/>
+  </clock_setting>
+  <simulator_option>
+    <operating_condition temperature="25"/>
+    <output_log verbose="false" captab="false"/>
+    <accuracy type="abs" value="1e-13"/>
+    <runtime fast_simulation="true"/>
+  </simulator_option>
+  <monte_carlo num_simulation_points="2"/>
+  <measurement_setting>
+    <slew>
+      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
+      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
+    </slew>
+    <delay>
+      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
+      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
+    </delay>
+  </measurement_setting>
+  <stimulus>
+    <clock>
+      <rise slew_type="abs" slew_time="20e-12" />
+      <fall slew_type="abs" slew_time="20e-12" />
+    </clock>
+    <input>
+      <rise slew_type="abs" slew_time="25e-12" />
+      <fall slew_type="abs" slew_time="25e-12" />
+    </input>
+  </stimulus>
+</openfpga_simulation_setting>
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_chain_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_chain_40nm.xml
new file mode 100644
index 000000000..77dedbcb0
--- /dev/null
+++ b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_chain_40nm.xml
@@ -0,0 +1,696 @@
+<!-- 
+  Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with 8 total FLE inputs (2 inputs of which are shared by the 5-LUTs) 
+    with optionally registered outputs
+    Each 5-LUT has an arithemtic mode that converts it to a single-bit adder with both inputs driven by 4-LUTs (both 4-LUTs share all 4 inputs)
+    Carry chain links to vertically adjacent logic blocks
+  - Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.  
+    Height = 6, found on every (8n+2)th column
+  - Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.  
+    Height = 4, found on every (8n+6)th column
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Details on Modelling:
+
+  The electrical design of the architecture described here is NOT from an 
+  optimized, SPICED architecture.  Instead, we attempt to create a reasonable 
+  architecture file by using an existing commercial FPGA to approximate the area, 
+  delay, and power of the underlying components. This is combined with a reasonable 40 nm 
+  model of wiring and circuit design for low-level routing components, where available.
+  The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also 
+  has wiring electrical parameters that allow the wire lengths and switch patterns to be 
+  modified and you will still get reasonable delay results for the new architecture.
+  The following describes, in detail, how we obtained the various electrical values for this 
+  architecture.
+
+  Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar 
+  architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture. 
+  (n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)      
+  This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to 
+  match the overall target (a 40 nm FPGA).
+
+  We obtain delay numbers by measuring delays of routing, soft logic blocks, 
+  memories, and multipliers from test circuits on a Stratix IV GX device 
+  (EP4SGX230DF29C2X, i.e. fastest speed grade). For routing, we took the average delay of H4 and V4 
+  wires.  Rmetal and Cmetal values for the routing wires were obtained from work done by Charles 
+  Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal stack 40 nm routing) and 
+  take the R and C data from the ITRS roadmap.  
+
+  For the general purpose logic block, we assume that the area and delays of the Stratix IV 
+  crossbar is close enough to the crossbar modelled here.  
+  Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to 
+  36:1 multiplexers.  We match these parameters in this architecture.
+
+  For LUTs, we include LUT 
+  delays measured from Stratix IV which is dependant on the input used (ie. some 
+  LUT inputs are faster than others).  The CAD tools at the time of VTR 7 does 
+  not consider differences in LUT input delays.
+
+  Adder delays obtained as approximate values from a Stratix IV EP4SE230F29C3 device.  
+  Delay obtained by compiling a 256 bit adder (registered inputs and outputs, 
+  all pins except clock virtual) then measuring the delays in chip-planner, 
+  sumout delay = 0.271ns to 0.348 ns, intra-block carry delay = 0.011 ns, 
+  inter-block carry delay = 0.327 ns.  Given this data, I will approximate 
+  sumout 0.3 ns, intra-block carry-delay = 0.01 ns, and 
+  inter-block carry-delay = 0.16 ns (since Altera inter-block carry delay has 
+  overhead that we don't have, I'll approximate the delay of a simpler chain at 
+  one half what they have.  This is very rough, anything from 0.01ns to 0.327ns 
+  can be justified).
+
+  Logic block area numbers obtained by scaling overall tile area of a 65nm 
+  Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out 
+  routing area at a channel width of 300. We use a channel width of 300 because it can route 
+  all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
+  total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
+  choosing a width that provides high routability. The architecture can be routed at different channel
+  widths, but we estimate the tile size and hence the physical length of routing wires assuming
+  a channel width of 300.
+
+  Sanity checks employed:
+    1.  We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches 
+        common electrical design.
+
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <model name="adder">
+      <input_ports>
+        <port name="a" combinational_sink_ports="sumout cout"/>
+        <port name="b" combinational_sink_ports="sumout cout"/>
+        <port name="cin" combinational_sink_ports="sumout cout"/>
+      </input_ports>
+      <output_ports>
+        <port name="cout"/>
+        <port name="sumout"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="frac_lut6">
+      <input_ports>
+        <port name="in"/>
+      </input_ports>
+      <output_ports>
+        <port name="lut4_out"/>
+        <port name="lut5_out"/>
+        <port name="lut6_out"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <tile name="io" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad</loc>
+        <loc side="top">io.outpad io.inpad</loc>
+        <loc side="right">io.outpad io.inpad</loc>
+        <loc side="bottom">io.outpad io.inpad</loc>
+      </pinlocations>
+    </tile>
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <input name="regin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <output name="regout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="regin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="regout" fc_type="frac" fc_val="0"/>
+      </fc>
+      <!--  Highly recommand to customize pin location when direct connection is used!!! -->
+      <!--pinlocations pattern="spread"/-->
+      <pinlocations pattern="custom">
+        <loc side="left">clb.clk</loc>
+        <loc side="top">clb.cin clb.regin</loc>
+        <loc side="right">clb.O[9:0] clb.I[19:0]</loc>
+        <loc side="bottom">clb.cout clb.regout clb.O[19:10] clb.I[39:20]</loc>
+      </pinlocations>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout tileable="true">
+    <!--auto_layout aspect_ratio="1.0"-->
+    <fixed_layout name="4x4" width="6" height="6">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </fixed_layout>
+    <!-- /auto_layout -->
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	    -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+           book area formula. This means the mux transistors are about 5x minimum drive strength.
+           We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+           mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+           the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+           by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+           buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+           I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+           (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+           The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+           2.5x when looking up in Jeff's tables.
+           Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+           This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+             With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+             reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <directlist>
+    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
+    <direct name="shift_register" from_pin="clb.regout" to_pin="clb.regin" x_offset="0" y_offset="-1" z_offset="0"/>
+  </directlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+
+      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+           If you need to register the I/O, define clocks in the circuit models
+           These clocks can be handled in back-end
+       -->
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" packable="false">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <input name="regin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <output name="regout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe fracturable logic element.  
+             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
+             The outputs of the fracturable logic element can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="10">
+        <input name="in" num_pins="6"/>
+        <input name="cin" num_pins="1"/>
+        <input name="regin" num_pins="1"/>
+        <output name="out" num_pins="2"/>
+        <output name="cout" num_pins="1"/>
+        <output name="regout" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- Physical mode definition begin (physical implementation of the fle) -->
+        <mode name="physical" packable="false">
+          <pb_type name="fabric" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <input name="cin" num_pins="1"/>
+            <input name="regin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <output name="regout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="frac_logic" num_pb="1">
+              <input name="in" num_pins="6"/>
+              <output name="lut4_out" num_pins="4"/>
+              <output name="out" num_pins="2"/>
+              <!-- Define LUT -->
+              <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
+                <input name="in" num_pins="6"/>
+                <output name="lut4_out" num_pins="4"/>
+                <output name="lut5_out" num_pins="2"/>
+                <output name="lut6_out" num_pins="1"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
+                <direct name="direct2" input="frac_lut6.lut4_out" output="frac_logic.lut4_out"/>
+                <direct name="direct3" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
+                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
+                <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
+              </interconnect>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>         
+            <!-- Define adders -->
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="2">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
+              <direct name="direct2" input="fabric.cin" output="adder[0:0].cin"/>
+              <direct name="direct3" input="adder[0:0].cout" output="adder[1:1].cin"/>
+              <direct name="direct4" input="adder[1:1].cout" output="fabric.cout"/>
+              <direct name="direct5" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
+              <direct name="direct6" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
+              <direct name="direct7" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
+              <direct name="direct8" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
+              <complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
+              <mux name="mux1" input="adder[0].sumout frac_logic.out[0] fabric.regin" output="ff[0].D">
+                <delay_constant max="25e-12" in_port="adder[0].sumout frac_logic.out[0] fabric.regin" out_port="ff[0].D"/>
+              </mux>
+              <mux name="mux2" input="adder[1].sumout frac_logic.out[1] ff[0].Q" output="ff[1].D">
+                <delay_constant max="25e-12" in_port="adder[1].sumout frac_logic.out[1] ff[0].Q" out_port="ff[1].D"/>
+              </mux>
+              <mux name="mux3" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
+                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
+              </mux>
+              <mux name="mux4" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
+                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="fabric.in"/>
+            <direct name="direct2" input="fle.cin" output="fabric.cin"/>
+            <direct name="direct3" input="fle.regin" output="fabric.regin"/>
+            <direct name="direct4" input="fabric.out" output="fle.out"/>
+            <direct name="direct5" input="fabric.cout" output="fle.cout"/>
+            <direct name="direct6" input="fabric.regout" output="fle.regout"/>
+            <direct name="direct7" input="fle.clk" output="fabric.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Physical mode definition end (physical implementation of the fle) -->
+        <!-- BEGIN fle mode of dual lut5 -->
+        <mode name="n2_lut5">
+          <pb_type name="ble5" num_pb="2">
+            <input name="in" num_pins="5"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Regular LUT mode -->
+            <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="5" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                  we instead take the average of these numbers to get more stable results
+                82e-12
+                173e-12
+                261e-12
+                263e-12
+                398e-12
+                -->
+              <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+              </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble5.in" output="lut5.in"/>
+              <direct name="direct2" input="lut5.out" output="ff.D">
+                <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble5.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut5.out" output="ble5.out">
+                <delay_constant max="25e-12" in_port="lut5.out" out_port="ble5.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble5.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[4:0]" output="ble5[0:0].in"/>
+            <direct name="direct2" input="fle.in[4:0]" output="ble5[1:1].in"/>
+            <complete name="direct3" input="fle.clk" output="ble5.clk"/>
+            <direct name="direct4" input="ble5.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- END fle mode of dual lut5 -->
+        <!-- BEGIN arithmetic mode of dual lut4 + adders -->
+        <mode name="arithmetic">
+          <pb_type name="arithmetic" num_pb="2">
+            <input name="in" num_pins="4"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="1"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Special dual-LUT mode that drives adder only -->
+            <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
+              <input name="in" num_pins="4" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  -->
+              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                  195e-12
+                  195e-12
+                  195e-12
+                  195e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
+              <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
+              <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
+              <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
+                </direct>
+              <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
+                </direct>
+              <direct name="add_to_ff" input="adder.sumout" output="ff.D">
+                <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
+              </direct>
+              <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
+                <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
+              </direct>
+              <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
+                <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
+              </direct>
+              <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
+                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[3:0]" output="arithmetic[0:0].in"/>
+            <direct name="direct2" input="fle.in[3:0]" output="arithmetic[1:1].in"/>
+            <direct name="carry_in" input="fle.cin" output="arithmetic[0:0].cin">
+              <pack_pattern name="chain" in_port="fle.cin" out_port="arithmetic[0:0].cin"/>
+            </direct>
+            <direct name="carry_inter" input="arithmetic[0:0].cout" output="arithmetic[1:1].cin">
+              <pack_pattern name="chain" in_port="arithmetic[0:0].cout" out_port="arithmetic[1:1].cin"/>
+            </direct>
+            <direct name="carry_out" input="arithmetic[1:1].cout" output="fle.cout">
+              <pack_pattern name="chain" in_port="arithmetic.cout" out_port="fle.cout"/>
+            </direct>
+            <complete name="direct3" input="fle.clk" output="arithmetic.clk"/>
+            <direct name="direct4" input="arithmetic.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- n2_lut5 -->
+        <mode name="n1_lut6">
+          <pb_type name="ble6" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="6" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->
+              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+              <direct name="direct2" input="lut6.out" output="ff.D">
+                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
+            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Define n1_lut6 end -->
+        <!-- Define shift register begin -->
+        <mode name="shift_register">
+          <pb_type name="shift_reg" num_pb="1">
+            <input name="regin" num_pins="1"/>
+            <output name="regout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="shift_reg.regin" output="ff[0].D"/>
+              <direct name="direct2" input="ff[0].Q" output="ff[1].D"/>
+              <direct name="direct3" input="ff[1].Q" output="shift_reg.regout"/>
+              <complete name="complete1" input="shift_reg.clk" output="ff.clk"/>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.regin" output="shift_reg.regin"/>
+            <direct name="direct2" input="shift_reg.regout" output="fle.regout"/>
+            <direct name="direct3" input="fle.clk" output="shift_reg.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Define shift register end --> 
+      </pb_type>
+      <interconnect>
+        <!-- We use a 50% depop crossbar built using small full xbars to get sets of logically equivalent pins at inputs of CLB 
+           The delays below come from Stratix IV. the delay through a connection block
+           input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+           delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+           delay within the crossbar is 95 ps. 
+           The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+           Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+           25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+           to get the part that should be marked on the crossbar.	 -->
+        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
+          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
+          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
+        </complete>
+
+        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+        </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+                 By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+                 then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+                 naive specification).
+          -->
+        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
+        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
+        <!-- Carry chain links -->
+        <direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
+          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
+        </direct>
+        <direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
+          <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
+        </direct>
+        <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
+          <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
+        </direct>
+        <!-- Shift register chain links -->
+        <direct name="shift_register_in" input="clb.regin" output="fle[0:0].regin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.16e-9" in_port="clb.regin" out_port="fle[0:0].regin"/>
+          <pack_pattern name="chain" in_port="clb.regin" out_port="fle[0:0].regin"/>
+        </direct>
+        <direct name="shift_register_out" input="fle[9:9].regout" output="clb.regout">
+          <pack_pattern name="chain" in_port="fle[9:9].regout" out_port="clb.regout"/>
+        </direct>
+        <direct name="shift_register_link" input="fle[8:0].regout" output="fle[9:1].regin">
+          <pack_pattern name="chain" in_port="fle[8:0].regout" out_port="fle[9:1].regin"/>
+        </direct>
+      </interconnect>
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+  </complexblocklist>
+</architecture>

From 628ea3b6546b08177b7444f5d59d18e53da0e8ca Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 7 Apr 2020 15:39:37 -0600
Subject: [PATCH 393/645] improve adder chain arch XML to support sequential
 output for sumout

---
 .../k6_frac_N10_adder_chain_40nm.xml          | 27 +++++++++++--------
 .../k6_frac_N10_adder_chain_mem16K_40nm.xml   | 27 +++++++++++--------
 .../k6_frac_N10_tileable_adder_chain_40nm.xml | 27 +++++++++++--------
 ...c_N10_tileable_adder_chain_mem16K_40nm.xml | 27 +++++++++++--------
 ...0_tileable_adder_chain_mem16K_aib_40nm.xml | 27 +++++++++++--------
 ...er_chain_mem16K_multi_io_capacity_40nm.xml | 27 +++++++++++--------
 ...ble_adder_chain_mem16K_reduced_io_40nm.xml | 26 ++++++++++--------
 ..._tileable_adder_chain_wide_mem16K_40nm.xml | 27 +++++++++++--------
 8 files changed, 127 insertions(+), 88 deletions(-)

diff --git a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
index 504431eb0..1fb82be72 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
@@ -371,21 +371,26 @@
             </pb_type>
             <interconnect>
               <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
-              <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
-              <direct name="direct3" input="fabric.cin" output="adder[0:0].cin"/>
-              <direct name="direct4" input="adder[0:0].cout" output="adder[1:1].cin"/>
-              <direct name="direct5" input="adder[1:1].cout" output="fabric.cout"/>
-              <direct name="direct6" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
-              <direct name="direct7" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
-              <direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
-              <direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
-              <complete name="direct10" input="fabric.clk" output="ff[1:0].clk"/>
-              <mux name="mux1" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+              <direct name="direct2" input="fabric.cin" output="adder[0:0].cin"/>
+              <direct name="direct3" input="adder[0:0].cout" output="adder[1:1].cin"/>
+              <direct name="direct4" input="adder[1:1].cout" output="fabric.cout"/>
+              <direct name="direct5" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
+              <direct name="direct6" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
+              <direct name="direct7" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
+              <direct name="direct8" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
+              <complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
+              <mux name="mux1" input="adder[0].sumout frac_logic.out[0]" output="ff[0].D">
+                <delay_constant max="25e-12" in_port="adder[0].sumout frac_logic.out[0]" out_port="ff[0].D"/>
+              </mux>
+              <mux name="mux2" input="adder[1].sumout frac_logic.out[1]" output="ff[1].D">
+                <delay_constant max="25e-12" in_port="adder[1].sumout frac_logic.out[1]" out_port="ff[1].D"/>
+              </mux>
+              <mux name="mux3" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
                 <!-- LUT to output is faster than FF to output on a Stratix IV -->
                 <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
                 <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
               </mux>
-              <mux name="mux2" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+              <mux name="mux4" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
                 <!-- LUT to output is faster than FF to output on a Stratix IV -->
                 <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
                 <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml
index 3ecd20733..e0d7ce812 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml
@@ -408,21 +408,26 @@
             </pb_type>
             <interconnect>
               <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
-              <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
-              <direct name="direct3" input="fabric.cin" output="adder[0:0].cin"/>
-              <direct name="direct4" input="adder[0:0].cout" output="adder[1:1].cin"/>
-              <direct name="direct5" input="adder[1:1].cout" output="fabric.cout"/>
-              <direct name="direct6" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
-              <direct name="direct7" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
-              <direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
-              <direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
-              <complete name="direct10" input="fabric.clk" output="ff[1:0].clk"/>
-              <mux name="mux1" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+              <direct name="direct2" input="fabric.cin" output="adder[0:0].cin"/>
+              <direct name="direct3" input="adder[0:0].cout" output="adder[1:1].cin"/>
+              <direct name="direct4" input="adder[1:1].cout" output="fabric.cout"/>
+              <direct name="direct5" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
+              <direct name="direct6" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
+              <direct name="direct7" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
+              <direct name="direct8" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
+              <complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
+              <mux name="mux1" input="adder[0].sumout frac_logic.out[0]" output="ff[0].D">
+                <delay_constant max="25e-12" in_port="adder[0].sumout frac_logic.out[0]" out_port="ff[0].D"/>
+              </mux>
+              <mux name="mux2" input="adder[1].sumout frac_logic.out[1]" output="ff[1].D">
+                <delay_constant max="25e-12" in_port="adder[1].sumout frac_logic.out[1]" out_port="ff[1].D"/>
+              </mux>
+              <mux name="mux3" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
                 <!-- LUT to output is faster than FF to output on a Stratix IV -->
                 <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
                 <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
               </mux>
-              <mux name="mux2" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+              <mux name="mux4" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
                 <!-- LUT to output is faster than FF to output on a Stratix IV -->
                 <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
                 <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml
index 19b27b88b..8f1dfd10e 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml
@@ -371,21 +371,26 @@
             </pb_type>
             <interconnect>
               <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
-              <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
-              <direct name="direct3" input="fabric.cin" output="adder[0:0].cin"/>
-              <direct name="direct4" input="adder[0:0].cout" output="adder[1:1].cin"/>
-              <direct name="direct5" input="adder[1:1].cout" output="fabric.cout"/>
-              <direct name="direct6" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
-              <direct name="direct7" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
-              <direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
-              <direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
-              <complete name="direct10" input="fabric.clk" output="ff[1:0].clk"/>
-              <mux name="mux1" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+              <direct name="direct2" input="fabric.cin" output="adder[0:0].cin"/>
+              <direct name="direct3" input="adder[0:0].cout" output="adder[1:1].cin"/>
+              <direct name="direct4" input="adder[1:1].cout" output="fabric.cout"/>
+              <direct name="direct5" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
+              <direct name="direct6" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
+              <direct name="direct7" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
+              <direct name="direct8" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
+              <complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
+              <mux name="mux1" input="adder[0].sumout frac_logic.out[0]" output="ff[0].D">
+                <delay_constant max="25e-12" in_port="adder[0].sumout frac_logic.out[0]" out_port="ff[0].D"/>
+              </mux>
+              <mux name="mux2" input="adder[1].sumout frac_logic.out[1]" output="ff[1].D">
+                <delay_constant max="25e-12" in_port="adder[1].sumout frac_logic.out[1]" out_port="ff[1].D"/>
+              </mux>
+              <mux name="mux3" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
                 <!-- LUT to output is faster than FF to output on a Stratix IV -->
                 <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
                 <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
               </mux>
-              <mux name="mux2" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+              <mux name="mux4" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
                 <!-- LUT to output is faster than FF to output on a Stratix IV -->
                 <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
                 <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml
index 4c0751db4..8254a0583 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml
@@ -408,21 +408,26 @@
             </pb_type>
             <interconnect>
               <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
-              <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
-              <direct name="direct3" input="fabric.cin" output="adder[0:0].cin"/>
-              <direct name="direct4" input="adder[0:0].cout" output="adder[1:1].cin"/>
-              <direct name="direct5" input="adder[1:1].cout" output="fabric.cout"/>
-              <direct name="direct6" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
-              <direct name="direct7" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
-              <direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
-              <direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
-              <complete name="direct10" input="fabric.clk" output="ff[1:0].clk"/>
-              <mux name="mux1" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+              <direct name="direct2" input="fabric.cin" output="adder[0:0].cin"/>
+              <direct name="direct3" input="adder[0:0].cout" output="adder[1:1].cin"/>
+              <direct name="direct4" input="adder[1:1].cout" output="fabric.cout"/>
+              <direct name="direct5" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
+              <direct name="direct6" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
+              <direct name="direct7" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
+              <direct name="direct8" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
+              <complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
+              <mux name="mux1" input="adder[0].sumout frac_logic.out[0]" output="ff[0].D">
+                <delay_constant max="25e-12" in_port="adder[0].sumout frac_logic.out[0]" out_port="ff[0].D"/>
+              </mux>
+              <mux name="mux2" input="adder[1].sumout frac_logic.out[1]" output="ff[1].D">
+                <delay_constant max="25e-12" in_port="adder[1].sumout frac_logic.out[1]" out_port="ff[1].D"/>
+              </mux>
+              <mux name="mux3" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
                 <!-- LUT to output is faster than FF to output on a Stratix IV -->
                 <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
                 <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
               </mux>
-              <mux name="mux2" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+              <mux name="mux4" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
                 <!-- LUT to output is faster than FF to output on a Stratix IV -->
                 <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
                 <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml
index 37dbb2b93..35eedb327 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml
@@ -474,21 +474,26 @@
             </pb_type>
             <interconnect>
               <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
-              <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
-              <direct name="direct3" input="fabric.cin" output="adder[0:0].cin"/>
-              <direct name="direct4" input="adder[0:0].cout" output="adder[1:1].cin"/>
-              <direct name="direct5" input="adder[1:1].cout" output="fabric.cout"/>
-              <direct name="direct6" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
-              <direct name="direct7" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
-              <direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
-              <direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
-              <complete name="direct10" input="fabric.clk" output="ff[1:0].clk"/>
-              <mux name="mux1" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+              <direct name="direct2" input="fabric.cin" output="adder[0:0].cin"/>
+              <direct name="direct3" input="adder[0:0].cout" output="adder[1:1].cin"/>
+              <direct name="direct4" input="adder[1:1].cout" output="fabric.cout"/>
+              <direct name="direct5" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
+              <direct name="direct6" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
+              <direct name="direct7" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
+              <direct name="direct8" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
+              <complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
+              <mux name="mux1" input="adder[0].sumout frac_logic.out[0]" output="ff[0].D">
+                <delay_constant max="25e-12" in_port="adder[0].sumout frac_logic.out[0]" out_port="ff[0].D"/>
+              </mux>
+              <mux name="mux2" input="adder[1].sumout frac_logic.out[1]" output="ff[1].D">
+                <delay_constant max="25e-12" in_port="adder[1].sumout frac_logic.out[1]" out_port="ff[1].D"/>
+              </mux>
+              <mux name="mux3" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
                 <!-- LUT to output is faster than FF to output on a Stratix IV -->
                 <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
                 <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
               </mux>
-              <mux name="mux2" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+              <mux name="mux4" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
                 <!-- LUT to output is faster than FF to output on a Stratix IV -->
                 <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
                 <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml
index ff7c3278b..d23c34960 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml
@@ -442,21 +442,26 @@
             </pb_type>
             <interconnect>
               <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
-              <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
-              <direct name="direct3" input="fabric.cin" output="adder[0:0].cin"/>
-              <direct name="direct4" input="adder[0:0].cout" output="adder[1:1].cin"/>
-              <direct name="direct5" input="adder[1:1].cout" output="fabric.cout"/>
-              <direct name="direct6" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
-              <direct name="direct7" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
-              <direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
-              <direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
-              <complete name="direct10" input="fabric.clk" output="ff[1:0].clk"/>
-              <mux name="mux1" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+              <direct name="direct2" input="fabric.cin" output="adder[0:0].cin"/>
+              <direct name="direct3" input="adder[0:0].cout" output="adder[1:1].cin"/>
+              <direct name="direct4" input="adder[1:1].cout" output="fabric.cout"/>
+              <direct name="direct5" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
+              <direct name="direct6" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
+              <direct name="direct7" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
+              <direct name="direct8" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
+              <complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
+              <mux name="mux1" input="adder[0].sumout frac_logic.out[0]" output="ff[0].D">
+                <delay_constant max="25e-12" in_port="adder[0].sumout frac_logic.out[0]" out_port="ff[0].D"/>
+              </mux>
+              <mux name="mux2" input="adder[1].sumout frac_logic.out[1]" output="ff[1].D">
+                <delay_constant max="25e-12" in_port="adder[1].sumout frac_logic.out[1]" out_port="ff[1].D"/>
+              </mux>
+              <mux name="mux3" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
                 <!-- LUT to output is faster than FF to output on a Stratix IV -->
                 <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
                 <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
               </mux>
-              <mux name="mux2" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+              <mux name="mux4" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
                 <!-- LUT to output is faster than FF to output on a Stratix IV -->
                 <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
                 <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml
index d9adc9056..66d0c9515 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml
@@ -411,21 +411,25 @@
             </pb_type>
             <interconnect>
               <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
-              <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
-              <direct name="direct3" input="fabric.cin" output="adder[0:0].cin"/>
-              <direct name="direct4" input="adder[0:0].cout" output="adder[1:1].cin"/>
-              <direct name="direct5" input="adder[1:1].cout" output="fabric.cout"/>
-              <direct name="direct6" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
-              <direct name="direct7" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
-              <direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
-              <direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
-              <complete name="direct10" input="fabric.clk" output="ff[1:0].clk"/>
-              <mux name="mux1" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+              <direct name="direct2" input="fabric.cin" output="adder[0:0].cin"/>
+              <direct name="direct3" input="adder[0:0].cout" output="adder[1:1].cin"/>
+              <direct name="direct4" input="adder[1:1].cout" output="fabric.cout"/>
+              <direct name="direct5" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
+              <direct name="direct6" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
+              <direct name="direct7" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
+              <direct name="direct8" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
+              <mux name="mux1" input="adder[0].sumout frac_logic.out[0]" output="ff[0].D">
+                <delay_constant max="25e-12" in_port="adder[0].sumout frac_logic.out[0]" out_port="ff[0].D"/>
+              </mux>
+              <mux name="mux2" input="adder[1].sumout frac_logic.out[1]" output="ff[1].D">
+                <delay_constant max="25e-12" in_port="adder[1].sumout frac_logic.out[1]" out_port="ff[1].D"/>
+              </mux>
+              <mux name="mux3" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
                 <!-- LUT to output is faster than FF to output on a Stratix IV -->
                 <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
                 <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
               </mux>
-              <mux name="mux2" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+              <mux name="mux4" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
                 <!-- LUT to output is faster than FF to output on a Stratix IV -->
                 <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
                 <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml
index 7eda2aa2f..1bb8ffe23 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml
@@ -408,21 +408,26 @@
             </pb_type>
             <interconnect>
               <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
-              <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
-              <direct name="direct3" input="fabric.cin" output="adder[0:0].cin"/>
-              <direct name="direct4" input="adder[0:0].cout" output="adder[1:1].cin"/>
-              <direct name="direct5" input="adder[1:1].cout" output="fabric.cout"/>
-              <direct name="direct6" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
-              <direct name="direct7" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
-              <direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
-              <direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
-              <complete name="direct10" input="fabric.clk" output="ff[1:0].clk"/>
-              <mux name="mux1" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+              <direct name="direct2" input="fabric.cin" output="adder[0:0].cin"/>
+              <direct name="direct3" input="adder[0:0].cout" output="adder[1:1].cin"/>
+              <direct name="direct4" input="adder[1:1].cout" output="fabric.cout"/>
+              <direct name="direct5" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
+              <direct name="direct6" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
+              <direct name="direct7" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
+              <direct name="direct8" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
+              <complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
+              <mux name="mux1" input="adder[0].sumout frac_logic.out[0]" output="ff[0].D">
+                <delay_constant max="25e-12" in_port="adder[0].sumout frac_logic.out[0]" out_port="ff[0].D"/>
+              </mux>
+              <mux name="mux2" input="adder[1].sumout frac_logic.out[1]" output="ff[1].D">
+                <delay_constant max="25e-12" in_port="adder[1].sumout frac_logic.out[1]" out_port="ff[1].D"/>
+              </mux>
+              <mux name="mux3" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
                 <!-- LUT to output is faster than FF to output on a Stratix IV -->
                 <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
                 <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
               </mux>
-              <mux name="mux2" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+              <mux name="mux4" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
                 <!-- LUT to output is faster than FF to output on a Stratix IV -->
                 <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
                 <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>

From 6daee8c2c84673382402063d191fe27ebcdc0cd9 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 7 Apr 2020 16:03:34 -0600
Subject: [PATCH 394/645] bug fixed in the example architecture

---
 .../k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml  | 1 +
 1 file changed, 1 insertion(+)

diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml
index 66d0c9515..bb06c5f39 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml
@@ -418,6 +418,7 @@
               <direct name="direct6" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
               <direct name="direct7" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
               <direct name="direct8" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
+              <complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
               <mux name="mux1" input="adder[0].sumout frac_logic.out[0]" output="ff[0].D">
                 <delay_constant max="25e-12" in_port="adder[0].sumout frac_logic.out[0]" out_port="ff[0].D"/>
               </mux>

From 5a04da2082563d2b1d3e7469dfce1d37831f6942 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 7 Apr 2020 16:14:41 -0600
Subject: [PATCH 395/645] fix memory leakage in openfpga title

---
 openfpga/src/base/openfpga_title.cpp | 4 ++--
 openfpga/src/base/openfpga_title.h   | 2 +-
 openfpga/src/main.cpp                | 2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/openfpga/src/base/openfpga_title.cpp b/openfpga/src/base/openfpga_title.cpp
index 41616c8bd..ca39fe2e6 100644
--- a/openfpga/src/base/openfpga_title.cpp
+++ b/openfpga/src/base/openfpga_title.cpp
@@ -8,7 +8,7 @@
  * Generate a string of openfpga title introduction
  * This is mainly used when launching OpenFPGA shell 
  *******************************************************************/
-const char* create_openfpga_title() {
+std::string create_openfpga_title() {
   std::string title;
 
   title += std::string("\n");
@@ -49,5 +49,5 @@ const char* create_openfpga_title() {
   title += std::string("THE SOFTWARE.\n");
   title += std::string("\n");
 
-  return title.c_str();
+  return title;
 }
diff --git a/openfpga/src/base/openfpga_title.h b/openfpga/src/base/openfpga_title.h
index b4826964a..8f4ab1e90 100644
--- a/openfpga/src/base/openfpga_title.h
+++ b/openfpga/src/base/openfpga_title.h
@@ -9,6 +9,6 @@
 /********************************************************************
  * Function declaration
  *******************************************************************/
-const char* create_openfpga_title();
+std::string create_openfpga_title();
 
 #endif
diff --git a/openfpga/src/main.cpp b/openfpga/src/main.cpp
index eb88c2c65..e1f813e9b 100644
--- a/openfpga/src/main.cpp
+++ b/openfpga/src/main.cpp
@@ -48,7 +48,7 @@ int main(int argc, char** argv) {
    */
   openfpga::Shell<OpenfpgaContext> shell("OpenFPGA");
 
-  shell.add_title(create_openfpga_title());
+  shell.add_title(create_openfpga_title().c_str());
 
   /* Add vpr commands */
   openfpga::add_vpr_commands(shell);

From cbcd1d20d465d0fd77a7032c6a4cafc621e1390b Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 7 Apr 2020 16:24:04 -0600
Subject: [PATCH 396/645] fixed memory leakage in pb_pin fixup

---
 openfpga/src/base/openfpga_pb_pin_fixup.cpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/openfpga/src/base/openfpga_pb_pin_fixup.cpp b/openfpga/src/base/openfpga_pb_pin_fixup.cpp
index 3e6fec2f7..cc91bdebe 100644
--- a/openfpga/src/base/openfpga_pb_pin_fixup.cpp
+++ b/openfpga/src/base/openfpga_pb_pin_fixup.cpp
@@ -121,7 +121,8 @@ void update_cluster_pin_with_post_routing_results(const DeviceContext& device_ct
     }
 
     /* Ignore used in local cluster only, reserved one CLB pin */
-    if (false == clustering_ctx.clb_nlist.net_sinks(cluster_net_id).size()) {
+    if ( (ClusterNetId::INVALID() != cluster_net_id)
+      && (0 == clustering_ctx.clb_nlist.net_sinks(cluster_net_id).size())) {
       continue;
     }
 

From 50bb04d49621154a1baebf0404dc63219629e94b Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 7 Apr 2020 16:50:41 -0600
Subject: [PATCH 397/645] add scan-chain test case. Debugging on the way

---
 ...dder_register_scan_chain_40nm_openfpga.xml | 294 +++++++
 ...ileable_adder_register_scan_chain.openfpga |  62 ++
 ...ileable_adder_register_scan_chain_40nm.xml | 735 ++++++++++++++++++
 3 files changed, 1091 insertions(+)
 create mode 100644 openfpga/test_openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml
 create mode 100644 openfpga/test_script/and_k6_frac_tileable_adder_register_scan_chain.openfpga
 create mode 100644 openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml

diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml
new file mode 100644
index 000000000..840a2e3bb
--- /dev/null
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml
@@ -0,0 +1,294 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
+      <design_technology type="cmos" topology="OR"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> 
+        This is flip-flop with scan-chain feature.
+        When the TESTEN is enabled, the data will be propagated form DI instead of D
+      -->
+    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="DI" size="1"/>
+       <port type="input" prefix="TESTEN" size="1" is_global="true" default_val="0"/>
+       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
+      <design_technology type="cmos" fracturable_lut="true"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="6" tri_state_map="----11" circuit_model_name="OR2"/>
+      <port type="output" prefix="lut4_out" size="4" lut_frac_level="4" lut_output_mask="0,1,2,3"/>
+      <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
+      <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
+      <port type="sram" prefix="sram" size="64"/>
+      <port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="Qb" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="inout" prefix="pad" size="1"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+      <port type="input" prefix="outpad" size="1"/>
+      <port type="output" prefix="inpad" size="1"/>
+    </circuit_model>
+    <circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="input" prefix="cin" size="1"/>
+      <port type="output" prefix="sumout" size="1"/>
+      <port type="output" prefix="cout" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <direct_connection>
+    <direct name="adder_carry" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
+    <direct name="shift_register" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
+    <direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
+  </direct_connection>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle" physical_mode_name="physical"/>
+    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
+    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
+    <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="adder"/>
+    <!-- Binding operating pb_type to physical pb_type -->
+    <!-- Binding operating pb_types in mode 'n2_lut5' -->
+    <pb_type name="clb.fle[n2_lut5].ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5">
+      <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:4]"/>
+      <port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[n2_lut5].ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <!-- Binding operating pb_types in mode 'arithmetic' -->
+    <pb_type name="clb.fle[arithmetic].arithmetic.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="11" physical_pb_type_index_factor="0.25">
+      <!-- Binding the lut4 to the first 4 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:3]"/>
+      <port name="out" physical_mode_port="lut4_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[arithmetic].arithmetic.adder" physical_pb_type_name="clb.fle[physical].fabric.adder"/>
+    <pb_type name="clb.fle[arithmetic].arithmetic.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <!-- Binding operating pb_types in mode 'ble6' -->
+    <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="00">
+      <!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:5]"/>
+      <port name="out" physical_mode_port="lut6_out"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
+    <!-- Binding operating pb_types in mode 'shift_register' -->
+    <pb_type name="clb.fle[shift_register].shift_reg.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>
+<openfpga_simulation_setting>
+  <clock_setting>
+    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
+    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
+    <programming frequency="10e6"/>
+  </clock_setting>
+  <simulator_option>
+    <operating_condition temperature="25"/>
+    <output_log verbose="false" captab="false"/>
+    <accuracy type="abs" value="1e-13"/>
+    <runtime fast_simulation="true"/>
+  </simulator_option>
+  <monte_carlo num_simulation_points="2"/>
+  <measurement_setting>
+    <slew>
+      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
+      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
+    </slew>
+    <delay>
+      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
+      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
+    </delay>
+  </measurement_setting>
+  <stimulus>
+    <clock>
+      <rise slew_type="abs" slew_time="20e-12" />
+      <fall slew_type="abs" slew_time="20e-12" />
+    </clock>
+    <input>
+      <rise slew_type="abs" slew_time="25e-12" />
+      <fall slew_type="abs" slew_time="25e-12" />
+    </input>
+  </stimulus>
+</openfpga_simulation_setting>
diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_register_scan_chain.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_register_scan_chain.openfpga
new file mode 100644
index 000000000..0ef91ab9d
--- /dev/null
+++ b/openfpga/test_script/and_k6_frac_tileable_adder_register_scan_chain.openfpga
@@ -0,0 +1,62 @@
+# Run VPR for the 'and' design
+vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml
+
+# Write out the architecture XML as a proof
+#write_openfpga_arch -f ./arch_echo.xml
+
+# Annotate the OpenFPGA architecture to VPR data base
+link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose
+
+# Write GSB to XML for debugging
+write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to clustering nets based on routing results
+pb_pin_fixup --verbose
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup #--verbose
+
+# Build the module graph 
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules 
+build_fabric --compress_routing --duplicate_grid_pin --verbose
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream 
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here 
+write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
+
+# Finish and exit OpenFPGA
+exit
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml
new file mode 100644
index 000000000..3b79b1df0
--- /dev/null
+++ b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml
@@ -0,0 +1,735 @@
+<!-- 
+  Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with 8 total FLE inputs (2 inputs of which are shared by the 5-LUTs) 
+    with optionally registered outputs
+    Each 5-LUT has an arithemtic mode that converts it to a single-bit adder with both inputs driven by 4-LUTs (both 4-LUTs share all 4 inputs)
+    Carry chain links to vertically adjacent logic blocks
+  - Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.  
+    Height = 6, found on every (8n+2)th column
+  - Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.  
+    Height = 4, found on every (8n+6)th column
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Details on Modelling:
+
+  The electrical design of the architecture described here is NOT from an 
+  optimized, SPICED architecture.  Instead, we attempt to create a reasonable 
+  architecture file by using an existing commercial FPGA to approximate the area, 
+  delay, and power of the underlying components. This is combined with a reasonable 40 nm 
+  model of wiring and circuit design for low-level routing components, where available.
+  The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also 
+  has wiring electrical parameters that allow the wire lengths and switch patterns to be 
+  modified and you will still get reasonable delay results for the new architecture.
+  The following describes, in detail, how we obtained the various electrical values for this 
+  architecture.
+
+  Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar 
+  architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture. 
+  (n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)      
+  This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to 
+  match the overall target (a 40 nm FPGA).
+
+  We obtain delay numbers by measuring delays of routing, soft logic blocks, 
+  memories, and multipliers from test circuits on a Stratix IV GX device 
+  (EP4SGX230DF29C2X, i.e. fastest speed grade). For routing, we took the average delay of H4 and V4 
+  wires.  Rmetal and Cmetal values for the routing wires were obtained from work done by Charles 
+  Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal stack 40 nm routing) and 
+  take the R and C data from the ITRS roadmap.  
+
+  For the general purpose logic block, we assume that the area and delays of the Stratix IV 
+  crossbar is close enough to the crossbar modelled here.  
+  Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to 
+  36:1 multiplexers.  We match these parameters in this architecture.
+
+  For LUTs, we include LUT 
+  delays measured from Stratix IV which is dependant on the input used (ie. some 
+  LUT inputs are faster than others).  The CAD tools at the time of VTR 7 does 
+  not consider differences in LUT input delays.
+
+  Adder delays obtained as approximate values from a Stratix IV EP4SE230F29C3 device.  
+  Delay obtained by compiling a 256 bit adder (registered inputs and outputs, 
+  all pins except clock virtual) then measuring the delays in chip-planner, 
+  sumout delay = 0.271ns to 0.348 ns, intra-block carry delay = 0.011 ns, 
+  inter-block carry delay = 0.327 ns.  Given this data, I will approximate 
+  sumout 0.3 ns, intra-block carry-delay = 0.01 ns, and 
+  inter-block carry-delay = 0.16 ns (since Altera inter-block carry delay has 
+  overhead that we don't have, I'll approximate the delay of a simpler chain at 
+  one half what they have.  This is very rough, anything from 0.01ns to 0.327ns 
+  can be justified).
+
+  Logic block area numbers obtained by scaling overall tile area of a 65nm 
+  Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out 
+  routing area at a channel width of 300. We use a channel width of 300 because it can route 
+  all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
+  total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
+  choosing a width that provides high routability. The architecture can be routed at different channel
+  widths, but we estimate the tile size and hence the physical length of routing wires assuming
+  a channel width of 300.
+
+  Sanity checks employed:
+    1.  We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches 
+        common electrical design.
+
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <model name="adder">
+      <input_ports>
+        <port name="a" combinational_sink_ports="sumout cout"/>
+        <port name="b" combinational_sink_ports="sumout cout"/>
+        <port name="cin" combinational_sink_ports="sumout cout"/>
+      </input_ports>
+      <output_ports>
+        <port name="cout"/>
+        <port name="sumout"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for fractruable LUT to be used in the physical mode of LUT -->
+    <model name="frac_lut6">
+      <input_ports>
+        <port name="in"/>
+      </input_ports>
+      <output_ports>
+        <port name="lut4_out"/>
+        <port name="lut5_out"/>
+        <port name="lut6_out"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for scan-chain flip-flop to be used in the physical mode of FF -->
+    <model name="scff">
+      <input_ports>
+        <port name="D" clock="clk"/>
+        <port name="DI" clock="clk"/>
+        <port name="clk" is_clock="1"/>
+      </input_ports>
+      <output_ports>
+        <port name="Q" clock="clk"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <tile name="io" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad</loc>
+        <loc side="top">io.outpad io.inpad</loc>
+        <loc side="right">io.outpad io.inpad</loc>
+        <loc side="bottom">io.outpad io.inpad</loc>
+      </pinlocations>
+    </tile>
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <input name="regin" num_pins="1"/>
+      <input name="scin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <output name="regout" num_pins="1"/>
+      <output name="scout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="regin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="regout" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="scin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="scout" fc_type="frac" fc_val="0"/>
+      </fc>
+      <!--  Highly recommand to customize pin location when direct connection is used!!! -->
+      <!--pinlocations pattern="spread"/-->
+      <pinlocations pattern="custom">
+        <loc side="left">clb.clk</loc>
+        <loc side="top">clb.cin clb.regin clb.scin</loc>
+        <loc side="right">clb.O[9:0] clb.I[19:0]</loc>
+        <loc side="bottom">clb.cout clb.regout clb.scout clb.O[19:10] clb.I[39:20]</loc>
+      </pinlocations>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout tileable="true">
+    <!--auto_layout aspect_ratio="1.0"-->
+    <fixed_layout name="4x4" width="6" height="6">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </fixed_layout>
+    <!-- /auto_layout -->
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	    -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+           book area formula. This means the mux transistors are about 5x minimum drive strength.
+           We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+           mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+           the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+           by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+           buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+           I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+           (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+           The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+           2.5x when looking up in Jeff's tables.
+           Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+           This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+             With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+             reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <directlist>
+    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
+    <direct name="shift_register" from_pin="clb.regout" to_pin="clb.regin" x_offset="0" y_offset="-1" z_offset="0"/>
+    <direct name="scan_chain" from_pin="clb.scout" to_pin="clb.scin" x_offset="0" y_offset="-1" z_offset="0"/>
+  </directlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+
+      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+           If you need to register the I/O, define clocks in the circuit models
+           These clocks can be handled in back-end
+       -->
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" packable="false">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <input name="regin" num_pins="1"/>
+      <input name="scin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <output name="regout" num_pins="1"/>
+      <output name="scout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe fracturable logic element.  
+             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
+             The outputs of the fracturable logic element can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="10">
+        <input name="in" num_pins="6"/>
+        <input name="cin" num_pins="1"/>
+        <input name="regin" num_pins="1"/>
+        <input name="scin" num_pins="1"/>
+        <output name="out" num_pins="2"/>
+        <output name="cout" num_pins="1"/>
+        <output name="regout" num_pins="1"/>
+        <output name="scout" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- Physical mode definition begin (physical implementation of the fle) -->
+        <mode name="physical" packable="false">
+          <pb_type name="fabric" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <input name="cin" num_pins="1"/>
+            <input name="regin" num_pins="1"/>
+            <input name="scin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <output name="regout" num_pins="1"/>
+            <output name="scout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="frac_logic" num_pb="1">
+              <input name="in" num_pins="6"/>
+              <output name="lut4_out" num_pins="4"/>
+              <output name="out" num_pins="2"/>
+              <!-- Define LUT -->
+              <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
+                <input name="in" num_pins="6"/>
+                <output name="lut4_out" num_pins="4"/>
+                <output name="lut5_out" num_pins="2"/>
+                <output name="lut6_out" num_pins="1"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
+                <direct name="direct2" input="frac_lut6.lut4_out" output="frac_logic.lut4_out"/>
+                <direct name="direct3" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
+                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
+                <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
+              </interconnect>
+            </pb_type>
+            <!-- Define flip-flop with scan-chain capability, DI is the scan-chain data input -->
+            <pb_type name="ff" blif_model=".subckt scff" num_pb="2">
+              <input name="D" num_pins="1"/>
+              <input name="DI" num_pins="1"/>
+              <output name="Q" num_pins="1"/>
+              <clock name="clk" num_pins="1"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_setup value="66e-12" port="ff.DI" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>         
+            <!-- Define adders -->
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="2">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
+              <direct name="direct2" input="fabric.cin" output="adder[0:0].cin"/>
+              <direct name="direct3" input="adder[0:0].cout" output="adder[1:1].cin"/>
+              <direct name="direct4" input="adder[1:1].cout" output="fabric.cout"/>
+              <direct name="direct5" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
+              <direct name="direct6" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
+              <direct name="direct7" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
+              <direct name="direct8" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
+              <direct name="direct9" input="fabric.scin" output="ff[0].DI"/>
+              <direct name="direct10" input="ff[0].Q" output="ff[1].DI"/>
+              <direct name="direct11" input="ff[1].Q" output="fabric.scout"/>
+              <complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
+              <mux name="mux1" input="adder[0].sumout frac_logic.out[0] fabric.regin" output="ff[0].D">
+                <delay_constant max="25e-12" in_port="adder[0].sumout frac_logic.out[0] fabric.regin" out_port="ff[0].D"/>
+              </mux>
+              <mux name="mux2" input="adder[1].sumout frac_logic.out[1] ff[0].Q" output="ff[1].D">
+                <delay_constant max="25e-12" in_port="adder[1].sumout frac_logic.out[1] ff[0].Q" out_port="ff[1].D"/>
+              </mux>
+              <mux name="mux3" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
+                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
+              </mux>
+              <mux name="mux4" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
+                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="fabric.in"/>
+            <direct name="direct2" input="fle.cin" output="fabric.cin"/>
+            <direct name="direct3" input="fle.regin" output="fabric.regin"/>
+            <direct name="direct4" input="fabric.out" output="fle.out"/>
+            <direct name="direct5" input="fabric.cout" output="fle.cout"/>
+            <direct name="direct6" input="fabric.regout" output="fle.regout"/>
+            <direct name="direct7" input="fle.clk" output="fabric.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Physical mode definition end (physical implementation of the fle) -->
+        <!-- BEGIN fle mode of dual lut5 -->
+        <mode name="n2_lut5">
+          <pb_type name="ble5" num_pb="2">
+            <input name="in" num_pins="5"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Regular LUT mode -->
+            <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="5" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                  we instead take the average of these numbers to get more stable results
+                82e-12
+                173e-12
+                261e-12
+                263e-12
+                398e-12
+                -->
+              <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+              </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble5.in" output="lut5.in"/>
+              <direct name="direct2" input="lut5.out" output="ff.D">
+                <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble5.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut5.out" output="ble5.out">
+                <delay_constant max="25e-12" in_port="lut5.out" out_port="ble5.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble5.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[4:0]" output="ble5[0:0].in"/>
+            <direct name="direct2" input="fle.in[4:0]" output="ble5[1:1].in"/>
+            <complete name="direct3" input="fle.clk" output="ble5.clk"/>
+            <direct name="direct4" input="ble5.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- END fle mode of dual lut5 -->
+        <!-- BEGIN arithmetic mode of dual lut4 + adders -->
+        <mode name="arithmetic">
+          <pb_type name="arithmetic" num_pb="2">
+            <input name="in" num_pins="4"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="1"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Special dual-LUT mode that drives adder only -->
+            <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
+              <input name="in" num_pins="4" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  -->
+              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                  195e-12
+                  195e-12
+                  195e-12
+                  195e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
+              <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
+              <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
+              <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
+                </direct>
+              <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
+                </direct>
+              <direct name="add_to_ff" input="adder.sumout" output="ff.D">
+                <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
+              </direct>
+              <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
+                <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
+              </direct>
+              <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
+                <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
+              </direct>
+              <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
+                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[3:0]" output="arithmetic[0:0].in"/>
+            <direct name="direct2" input="fle.in[3:0]" output="arithmetic[1:1].in"/>
+            <direct name="carry_in" input="fle.cin" output="arithmetic[0:0].cin">
+              <pack_pattern name="chain" in_port="fle.cin" out_port="arithmetic[0:0].cin"/>
+            </direct>
+            <direct name="carry_inter" input="arithmetic[0:0].cout" output="arithmetic[1:1].cin">
+              <pack_pattern name="chain" in_port="arithmetic[0:0].cout" out_port="arithmetic[1:1].cin"/>
+            </direct>
+            <direct name="carry_out" input="arithmetic[1:1].cout" output="fle.cout">
+              <pack_pattern name="chain" in_port="arithmetic.cout" out_port="fle.cout"/>
+            </direct>
+            <complete name="direct3" input="fle.clk" output="arithmetic.clk"/>
+            <direct name="direct4" input="arithmetic.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- n2_lut5 -->
+        <mode name="n1_lut6">
+          <pb_type name="ble6" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="6" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->
+              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+              <direct name="direct2" input="lut6.out" output="ff.D">
+                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
+            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Define n1_lut6 end -->
+        <!-- Define shift register begin -->
+        <mode name="shift_register">
+          <pb_type name="shift_reg" num_pb="1">
+            <input name="regin" num_pins="1"/>
+            <output name="regout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="shift_reg.regin" output="ff[0].D"/>
+              <direct name="direct2" input="ff[0].Q" output="ff[1].D"/>
+              <direct name="direct3" input="ff[1].Q" output="shift_reg.regout"/>
+              <complete name="complete1" input="shift_reg.clk" output="ff.clk"/>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.regin" output="shift_reg.regin"/>
+            <direct name="direct2" input="shift_reg.regout" output="fle.regout"/>
+            <direct name="direct3" input="fle.clk" output="shift_reg.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Define shift register end --> 
+      </pb_type>
+      <interconnect>
+        <!-- We use a 50% depop crossbar built using small full xbars to get sets of logically equivalent pins at inputs of CLB 
+           The delays below come from Stratix IV. the delay through a connection block
+           input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+           delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+           delay within the crossbar is 95 ps. 
+           The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+           Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+           25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+           to get the part that should be marked on the crossbar.	 -->
+        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
+          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
+          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
+        </complete>
+
+        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+        </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+                 By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+                 then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+                 naive specification).
+          -->
+        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
+        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
+        <!-- Carry chain links -->
+        <direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
+          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
+        </direct>
+        <direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
+          <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
+        </direct>
+        <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
+          <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
+        </direct>
+        <!-- Shift register chain links -->
+        <direct name="shift_register_in" input="clb.regin" output="fle[0:0].regin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.16e-9" in_port="clb.regin" out_port="fle[0:0].regin"/>
+          <pack_pattern name="chain" in_port="clb.regin" out_port="fle[0:0].regin"/>
+        </direct>
+        <direct name="shift_register_out" input="fle[9:9].regout" output="clb.regout">
+          <pack_pattern name="chain" in_port="fle[9:9].regout" out_port="clb.regout"/>
+        </direct>
+        <direct name="shift_register_link" input="fle[8:0].regout" output="fle[9:1].regin">
+          <pack_pattern name="chain" in_port="fle[8:0].regout" out_port="fle[9:1].regin"/>
+        </direct>
+        <!-- Scan chain links -->
+        <direct name="scan_chain_in" input="clb.scin" output="fle[0:0].scin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.16e-9" in_port="clb.scin" out_port="fle[0:0].scin"/>
+          <pack_pattern name="chain" in_port="clb.scin" out_port="fle[0:0].scin"/>
+        </direct>
+        <direct name="scan_chain_out" input="fle[9:9].scout" output="clb.scout">
+          <pack_pattern name="chain" in_port="fle[9:9].scout" out_port="clb.scout"/>
+        </direct>
+        <direct name="scan_chain_link" input="fle[8:0].scout" output="fle[9:1].scin">
+          <pack_pattern name="chain" in_port="fle[8:0].scout" out_port="fle[9:1].scin"/>
+        </direct>
+      </interconnect>
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+  </complexblocklist>
+</architecture>

From 2342d7cdc6c54f9cdeccc59315640e8392f041fa Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 7 Apr 2020 17:03:44 -0600
Subject: [PATCH 398/645] minor tweak on the scan-chain support in VPR8 as well
 as architecture file Do NOT use pack patterns for the scan-chain. It will
 cause searching root chain in VPR8 to fail Actually, we do not use scan-chain
 in mapping designs. Disable the pack pattern has no impact

---
 ...k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml | 3 ---
 vpr/src/pack/prepack.cpp                                   | 7 +++++++
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml
index 3b79b1df0..0bce05d74 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml
@@ -720,13 +720,10 @@
         <direct name="scan_chain_in" input="clb.scin" output="fle[0:0].scin">
           <!-- Put all inter-block carry chain delay on this one edge -->
           <delay_constant max="0.16e-9" in_port="clb.scin" out_port="fle[0:0].scin"/>
-          <pack_pattern name="chain" in_port="clb.scin" out_port="fle[0:0].scin"/>
         </direct>
         <direct name="scan_chain_out" input="fle[9:9].scout" output="clb.scout">
-          <pack_pattern name="chain" in_port="fle[9:9].scout" out_port="clb.scout"/>
         </direct>
         <direct name="scan_chain_link" input="fle[8:0].scout" output="fle[9:1].scin">
-          <pack_pattern name="chain" in_port="fle[8:0].scout" out_port="fle[9:1].scin"/>
         </direct>
       </interconnect>
     </pb_type>
diff --git a/vpr/src/pack/prepack.cpp b/vpr/src/pack/prepack.cpp
index cf9ccdd6d..dd9d1da3f 100644
--- a/vpr/src/pack/prepack.cpp
+++ b/vpr/src/pack/prepack.cpp
@@ -1557,6 +1557,13 @@ static t_pb_graph_pin* get_connected_primitive_pin(const t_pb_graph_pin* cluster
  *  will be only one pin connected to the very first adder in the cluster.
  */
 static void get_all_connected_primitive_pins(const t_pb_graph_pin* cluster_input_pin, std::vector<t_pb_graph_pin*>& connected_primitive_pins) {
+
+    /* Xifan Tang: Skip pins belong to unpackable modes */
+    if ( (nullptr != cluster_input_pin->parent_node->pb_type->parent_mode)
+       && (false == cluster_input_pin->parent_node->pb_type->parent_mode->packable) ) {
+        return;
+    }
+
     for (int iedge = 0; iedge < cluster_input_pin->num_output_edges; iedge++) {
         const auto& output_edge = cluster_input_pin->output_edges[iedge];
         for (int ipin = 0; ipin < output_edge->num_output_pins; ipin++) {

From ff7ea9938154a939c617ad92c65d9be18c727842 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 7 Apr 2020 17:06:16 -0600
Subject: [PATCH 399/645] bug fixed in register scan-chain architecture

---
 ...rac_N10_tileable_adder_register_scan_chain_40nm.xml | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml
index 0bce05d74..f83919c7c 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml
@@ -439,10 +439,12 @@
             <direct name="direct1" input="fle.in" output="fabric.in"/>
             <direct name="direct2" input="fle.cin" output="fabric.cin"/>
             <direct name="direct3" input="fle.regin" output="fabric.regin"/>
-            <direct name="direct4" input="fabric.out" output="fle.out"/>
-            <direct name="direct5" input="fabric.cout" output="fle.cout"/>
-            <direct name="direct6" input="fabric.regout" output="fle.regout"/>
-            <direct name="direct7" input="fle.clk" output="fabric.clk"/>
+            <direct name="direct4" input="fle.scin" output="fabric.scin"/>
+            <direct name="direct5" input="fabric.out" output="fle.out"/>
+            <direct name="direct6" input="fabric.cout" output="fle.cout"/>
+            <direct name="direct7" input="fabric.regout" output="fle.regout"/>
+            <direct name="direct8" input="fabric.scout" output="fle.scout"/>
+            <direct name="direct9" input="fle.clk" output="fabric.clk"/>
           </interconnect>
         </mode>
         <!-- Physical mode definition end (physical implementation of the fle) -->

From dd4f83a374b0b2ef91832abe9d0b2b7bbdc854a6 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 7 Apr 2020 18:28:19 -0600
Subject: [PATCH 400/645] bug fixing to constant string to display interconnect
 names

---
 libs/libarchfpga/src/physical_types.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h
index c9b44cd92..3d97fee47 100644
--- a/libs/libarchfpga/src/physical_types.h
+++ b/libs/libarchfpga/src/physical_types.h
@@ -166,7 +166,7 @@ enum e_interconnect {
     NUM_INTERC_TYPES /* Xifan Tang - Invalid types for interconnect */
 };
 /* Xifan Tang - String versions of interconnection type */
-constexpr std::array<const char*, NUM_INTERC_TYPES> INTERCONNECT_TYPE_STRING = {{"complete", "direct", "mux"}}; 
+constexpr std::array<const char*, NUM_INTERC_TYPES> INTERCONNECT_TYPE_STRING = {{"unknown", "complete", "direct", "mux"}}; 
 
 /* Orientations. */
 enum e_side : unsigned char {

From 62276f9e2865a915b211a7a17333dd013c35b15d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 7 Apr 2020 18:43:11 -0600
Subject: [PATCH 401/645] minor code format

---
 openfpga/src/annotation/annotate_pb_graph.cpp | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/openfpga/src/annotation/annotate_pb_graph.cpp b/openfpga/src/annotation/annotate_pb_graph.cpp
index 2b78f2f0e..c930a20b6 100644
--- a/openfpga/src/annotation/annotate_pb_graph.cpp
+++ b/openfpga/src/annotation/annotate_pb_graph.cpp
@@ -89,7 +89,9 @@ void rec_build_vpr_pb_graph_interconnect_physical_type_annotation(t_pb_graph_nod
       }
       VTR_LOGV(verbose_output,
                "Infer physical type '%s' of interconnect '%s' (was '%s')\n",
-               INTERCONNECT_TYPE_STRING[interc_physical_type], interc->name, INTERCONNECT_TYPE_STRING[interc->type]);
+               INTERCONNECT_TYPE_STRING[interc_physical_type],
+               interc->name,
+               INTERCONNECT_TYPE_STRING[interc->type]);
       vpr_device_annotation.add_interconnect_physical_type(interc, interc_physical_type);
     }
   }

From 0b1c8ac139ea2ba29d366e5492bb1c349055b52b Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 7 Apr 2020 19:46:42 -0600
Subject: [PATCH 402/645] bug fixed in identifying the physical interconnect
 for pb_graph nodes

---
 openfpga/src/annotation/annotate_pb_graph.cpp | 130 ++++++++++++++++--
 openfpga/test_script/and_k6_frac.openfpga     |   2 +-
 2 files changed, 119 insertions(+), 13 deletions(-)

diff --git a/openfpga/src/annotation/annotate_pb_graph.cpp b/openfpga/src/annotation/annotate_pb_graph.cpp
index c930a20b6..081acf900 100644
--- a/openfpga/src/annotation/annotate_pb_graph.cpp
+++ b/openfpga/src/annotation/annotate_pb_graph.cpp
@@ -49,17 +49,48 @@ void rec_build_vpr_pb_graph_interconnect_physical_type_annotation(t_pb_graph_nod
     VTR_ASSERT(nullptr != child_physical_mode);
 
     std::map<t_interconnect*, size_t> interc_num_inputs;
-    /* Initialize the counter */
-    for (t_interconnect* interc : pb_mode_interconnects(child_physical_mode)) {
-      interc_num_inputs[interc] = 0;
+
+    /* Find all the interconnects sourced from the input and clock pins */
+    for (int iport = 0; iport < pb_graph_node->num_input_ports; ++iport) {
+      for (int ipin = 0; ipin < pb_graph_node->num_input_pins[iport]; ++ipin) {
+        for (int iedge = 0; iedge < pb_graph_node->input_pins[iport][ipin].num_input_edges; ++iedge) {
+          t_interconnect* interc = pb_graph_node->input_pins[iport][ipin].input_edges[iedge]->interconnect;
+          /* Ensure that the interconnect is unique in the list */
+          if (0 < interc_num_inputs.count(interc)) {
+            continue;
+          }
+          /* Unique interconnect, initialize the counter to be zero */ 
+          interc_num_inputs[interc] = 0;
+        }
+      }
+    }
+
+    for (int iport = 0; iport < pb_graph_node->num_clock_ports; ++iport) {
+      for (int ipin = 0; ipin < pb_graph_node->num_clock_pins[iport]; ++ipin) {
+        for (int iedge = 0; iedge < pb_graph_node->clock_pins[iport][ipin].num_input_edges; ++iedge) {
+          t_interconnect* interc = pb_graph_node->clock_pins[iport][ipin].input_edges[iedge]->interconnect;
+          /* Ensure that the interconnect is unique in the list */
+          if (0 < interc_num_inputs.count(interc)) {
+            continue;
+          }
+          /* Unique interconnect, initialize the counter to be zero */ 
+          interc_num_inputs[interc] = 0;
+        }
+      }
+    }
+
+    /* Check: all the element should be initialized to 0 */
+    for (const auto& pair : interc_num_inputs) {
+      VTR_ASSERT(nullptr != pair.first);
+      VTR_ASSERT(0 == pair.second);
     }
 
     /* We only care input and clock pins */
     for (int iport = 0; iport < pb_graph_node->num_input_ports; ++iport) {
       for (int ipin = 0; ipin < pb_graph_node->num_input_pins[iport]; ++ipin) {
         /* For each interconnect, we count the total number of inputs */
-        for (t_interconnect* interc : pb_mode_interconnects(child_physical_mode)) {
-          interc_num_inputs[interc] += pb_graph_pin_inputs(&(pb_graph_node->input_pins[iport][ipin]), interc).size(); 
+        for (const auto& pair : interc_num_inputs) {
+          interc_num_inputs[pair.first] += pb_graph_pin_inputs(&(pb_graph_node->input_pins[iport][ipin]), pair.first).size(); 
         }
       }
     }
@@ -67,22 +98,24 @@ void rec_build_vpr_pb_graph_interconnect_physical_type_annotation(t_pb_graph_nod
     for (int iport = 0; iport < pb_graph_node->num_clock_ports; ++iport) {
       for (int ipin = 0; ipin < pb_graph_node->num_clock_pins[iport]; ++ipin) {
         /* For each interconnect, we count the total number of inputs */
-        for (t_interconnect* interc : pb_mode_interconnects(child_physical_mode)) {
-          interc_num_inputs[interc] += pb_graph_pin_inputs(&(pb_graph_node->clock_pins[iport][ipin]), interc).size(); 
+        for (const auto& pair : interc_num_inputs) {
+          interc_num_inputs[pair.first] += pb_graph_pin_inputs(&(pb_graph_node->clock_pins[iport][ipin]), pair.first).size(); 
         }
       }
     }
 
     /* For each interconnect that has more than 1 input, we can infer the physical type */
-    for (t_interconnect* interc : pb_mode_interconnects(child_physical_mode)) {
+    for (const auto& pair : interc_num_inputs) {
+      t_interconnect* interc = pair.first;
+      size_t actual_interc_num_inputs = pair.second;
       /* If the number inputs for an interconnect is zero, this is a 0-driver pin
        * we just set 1 to use direct wires
        */
-      if (0 == interc_num_inputs[interc]) {
-        interc_num_inputs[interc] = 1;
+      if (0 == actual_interc_num_inputs) {
+        actual_interc_num_inputs = 1;
       }
       
-      e_interconnect interc_physical_type = pb_interconnect_physical_type(interc, interc_num_inputs[interc]);
+      e_interconnect interc_physical_type = pb_interconnect_physical_type(interc, actual_interc_num_inputs);
       if (interc_physical_type == vpr_device_annotation.interconnect_physical_type(interc)) {
         /* Skip annotation if we have already done! */
         continue;
@@ -101,9 +134,82 @@ void rec_build_vpr_pb_graph_interconnect_physical_type_annotation(t_pb_graph_nod
     return;
   }
 
-  /* Recursively visit all the child pb_graph_nodes */
+  /* Find the physical mode of current pb_graph node  */
   t_mode* physical_mode = vpr_device_annotation.physical_mode(pb_graph_node->pb_type);
   VTR_ASSERT(nullptr != physical_mode);
+
+  /* Before going recursive, we should check the interconnect between output pins
+   * Note that this is NOT applicable to primitive pb_graph nodes!!!
+   *
+   *    pb_graph_node
+   *    -------------------------------+
+   *                                   |
+   *    child_pb_graph_node            |
+   *    -------------------+           |
+   *                       |           |
+   *            output_pin +<----------+ output_pin
+   *                       |           |
+   *    -------------------+           |
+   *
+   */
+  { /* Use a code block to use local variables freely */
+    std::map<t_interconnect*, size_t> interc_num_inputs;
+    /* Find all the interconnects sourced from the output pins */
+    for (int iport = 0; iport < pb_graph_node->num_output_ports; ++iport) {
+      for (int ipin = 0; ipin < pb_graph_node->num_output_pins[iport]; ++ipin) {
+        for (int iedge = 0; iedge < pb_graph_node->output_pins[iport][ipin].num_input_edges; ++iedge) {
+          t_interconnect* interc = pb_graph_node->output_pins[iport][ipin].input_edges[iedge]->interconnect;
+          /* Ensure that the interconnect is unique in the list */
+          if (0 < interc_num_inputs.count(interc)) {
+            continue;
+          }
+          /* Unique interconnect, initialize the counter to be zero */ 
+          interc_num_inputs[interc] = 0;
+        }
+      }
+    }
+
+    /* Check: all the element should be initialized to 0 */
+    for (const auto& pair : interc_num_inputs) {
+      VTR_ASSERT(nullptr != pair.first);
+      VTR_ASSERT(0 == pair.second);
+    }
+
+    /* We only care input and clock pins */
+    for (int iport = 0; iport < pb_graph_node->num_output_ports; ++iport) {
+      for (int ipin = 0; ipin < pb_graph_node->num_output_pins[iport]; ++ipin) {
+        /* For each interconnect, we count the total number of inputs */
+        for (const auto& pair : interc_num_inputs) {
+          interc_num_inputs[pair.first] += pb_graph_pin_inputs(&(pb_graph_node->output_pins[iport][ipin]), pair.first).size(); 
+        }
+      }
+    }
+    /* For each interconnect that has more than 1 input, we can infer the physical type */
+    for (const auto& pair : interc_num_inputs) {
+      t_interconnect* interc = pair.first;
+      size_t actual_interc_num_inputs = pair.second;
+      /* If the number inputs for an interconnect is zero, this is a 0-driver pin
+       * we just set 1 to use direct wires
+       */
+      if (0 == actual_interc_num_inputs) {
+        actual_interc_num_inputs = 1;
+      }
+      
+      e_interconnect interc_physical_type = pb_interconnect_physical_type(interc, actual_interc_num_inputs);
+      if (interc_physical_type == vpr_device_annotation.interconnect_physical_type(interc)) {
+        /* Skip annotation if we have already done! */
+        continue;
+      }
+      VTR_LOGV(verbose_output,
+               "Infer physical type '%s' of interconnect '%s' (was '%s')\n",
+               INTERCONNECT_TYPE_STRING[interc_physical_type],
+               interc->name,
+               INTERCONNECT_TYPE_STRING[interc->type]);
+      vpr_device_annotation.add_interconnect_physical_type(interc, interc_physical_type);
+    }
+  }
+
+  /* Recursively visit all the child pb_graph_nodes */
   for (int ipb = 0; ipb < physical_mode->num_pb_type_children; ++ipb) {
     /* Each child may exist multiple times in the hierarchy*/
     for (int jpb = 0; jpb < physical_mode->pb_type_children[ipb].num_pb; ++jpb) {
diff --git a/openfpga/test_script/and_k6_frac.openfpga b/openfpga/test_script/and_k6_frac.openfpga
index 63746cd71..e14811f49 100644
--- a/openfpga/test_script/and_k6_frac.openfpga
+++ b/openfpga/test_script/and_k6_frac.openfpga
@@ -8,7 +8,7 @@ read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
 #write_openfpga_arch -f ./arch_echo.xml
 
 # Annotate the OpenFPGA architecture to VPR data base
-link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose
+link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges --verbose
 
 # Check and correct any naming conflicts in the BLIF netlist
 check_netlist_naming_conflict --fix --report ./netlist_renaming.xml

From 33315f0521a0d6b4054f3b66291525ee8febbf93 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 7 Apr 2020 20:46:45 -0600
Subject: [PATCH 403/645] now openfpga shell allow empty space at beginning and
 end of each line in script mode

---
 libopenfpga/libopenfpgashell/src/shell.tpp                | 8 ++++++++
 ...nd_k6_frac_tileable_adder_register_scan_chain.openfpga | 4 ++--
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/libopenfpga/libopenfpgashell/src/shell.tpp b/libopenfpga/libopenfpgashell/src/shell.tpp
index 24ef13dea..2bc4a503a 100644
--- a/libopenfpga/libopenfpgashell/src/shell.tpp
+++ b/libopenfpga/libopenfpgashell/src/shell.tpp
@@ -302,6 +302,14 @@ void Shell<T>::run_script_mode(const char* script_file_name, T& context) {
     if (cmd_end_pos != std::string::npos) {
       cmd_part = line.substr(0, cmd_end_pos);
     }
+    /* Remove the space at the beginning of the line */
+    cmd_part.erase(cmd_part.begin(), std::find_if(cmd_part.begin(), cmd_part.end(), [](int ch) {
+      return !std::isspace(ch);
+    }));
+    /* Remove the space at the end of the line */
+    cmd_part.erase(std::find_if(cmd_part.rbegin(), cmd_part.rend(), [](int ch) {
+      return !std::isspace(ch);
+    }).base(), cmd_part.end());
     /* Process the command only when the line is not empty */
     if (!cmd_part.empty()) {
       execute_command(cmd_part.c_str(), context);
diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_register_scan_chain.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_register_scan_chain.openfpga
index 0ef91ab9d..ae10ebb34 100644
--- a/openfpga/test_script/and_k6_frac_tileable_adder_register_scan_chain.openfpga
+++ b/openfpga/test_script/and_k6_frac_tileable_adder_register_scan_chain.openfpga
@@ -28,8 +28,8 @@ lut_truth_table_fixup #--verbose
 build_fabric --compress_routing --duplicate_grid_pin --verbose
 
 # Repack the netlist to physical pbs
-# This must be done before bitstream generator and testbench generation
-# Strongly recommend it is done after all the fix-up have been applied
+  # This must be done before bitstream generator and testbench generation
+  # Strongly recommend it is done after all the fix-up have been applied
 repack #--verbose
 
 # Build the bitstream 

From e31dc1f2f21f76eac7b49e991cf0ed87c525e636 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 7 Apr 2020 21:27:51 -0600
Subject: [PATCH 404/645] openfpga shell now support continued line charactor
 '\'

---
 libopenfpga/libopenfpgashell/src/shell.tpp    | 47 +++++++++++++++----
 ...ileable_adder_register_scan_chain.openfpga |  7 +--
 2 files changed, 43 insertions(+), 11 deletions(-)

diff --git a/libopenfpga/libopenfpgashell/src/shell.tpp b/libopenfpga/libopenfpgashell/src/shell.tpp
index 2bc4a503a..5fe043f8e 100644
--- a/libopenfpga/libopenfpgashell/src/shell.tpp
+++ b/libopenfpga/libopenfpgashell/src/shell.tpp
@@ -289,6 +289,11 @@ void Shell<T>::run_script_mode(const char* script_file_name, T& context) {
     return; 
   }
 
+  /* Consider that each line may not end due to the continued line charactor 
+   * Use cmd_line to conjunct multiple lines 
+   */
+  std::string cmd_line;
+
   /* Read line by line */
   while (getline(fp, line)) {
     /* If the line that starts with '#', it is commented, we can skip */ 
@@ -302,17 +307,43 @@ void Shell<T>::run_script_mode(const char* script_file_name, T& context) {
     if (cmd_end_pos != std::string::npos) {
       cmd_part = line.substr(0, cmd_end_pos);
     }
-    /* Remove the space at the beginning of the line */
-    cmd_part.erase(cmd_part.begin(), std::find_if(cmd_part.begin(), cmd_part.end(), [](int ch) {
-      return !std::isspace(ch);
-    }));
-    /* Remove the space at the end of the line */
+
+    /* Remove the space at the end of the line
+     * So that we can check easily if there is a continued line in the end  
+     */
     cmd_part.erase(std::find_if(cmd_part.rbegin(), cmd_part.rend(), [](int ch) {
       return !std::isspace(ch);
     }).base(), cmd_part.end());
-    /* Process the command only when the line is not empty */
-    if (!cmd_part.empty()) {
-      execute_command(cmd_part.c_str(), context);
+
+    /* If the line ends with '\', this is a continued line, parse the next until it ends */
+    if ('\\' == cmd_part.back()) {
+      /* Pop up the last charactor and conjunct to cmd_line */
+      cmd_part.pop_back();
+ 
+      if (!cmd_part.empty()) {
+        cmd_line += cmd_part; 
+      }
+      /* Not finished yet. Parse the next line */
+      continue;
+    } else {
+      /* End of this line, if cmd_line is empty, 
+       * there is no previous lines, cache the part we have
+       * and then execute the command 
+       */
+      cmd_line += cmd_part;
+    }
+
+    /* Remove the space at the beginning of the line */
+    cmd_line.erase(cmd_line.begin(), std::find_if(cmd_line.begin(), cmd_line.end(), [](int ch) {
+      return !std::isspace(ch);
+    }));
+
+    /* Process the command only when the full command line in ended */
+    if (!cmd_line.empty()) {
+      VTR_LOG("\nCommand line to execute: %s\n", cmd_line.c_str());
+      execute_command(cmd_line.c_str(), context);
+      /* Empty the line ready to start a new line */
+      cmd_line.clear();
     }
   }
   fp.close();
diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_register_scan_chain.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_register_scan_chain.openfpga
index ae10ebb34..864fea78d 100644
--- a/openfpga/test_script/and_k6_frac_tileable_adder_register_scan_chain.openfpga
+++ b/openfpga/test_script/and_k6_frac_tileable_adder_register_scan_chain.openfpga
@@ -28,8 +28,8 @@ lut_truth_table_fixup #--verbose
 build_fabric --compress_routing --duplicate_grid_pin --verbose
 
 # Repack the netlist to physical pbs
-  # This must be done before bitstream generator and testbench generation
-  # Strongly recommend it is done after all the fix-up have been applied
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
 repack #--verbose
 
 # Build the bitstream 
@@ -56,7 +56,8 @@ write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_
 write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
 
 # Write the SDC to run timing analysis for a mapped FPGA fabric
-write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
+write_analysis_sdc \
+ --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
 
 # Finish and exit OpenFPGA
 exit

From 583a4d87671de2f93dbe58afa458a7c3d62664c9 Mon Sep 17 00:00:00 2001
From: ganeshgore <goreganesh007@gmail.com>
Date: Wed, 8 Apr 2020 12:04:08 -0600
Subject: [PATCH 405/645] Fixed bug in openfpga_flow script

---
 openfpga_flow/scripts/run_fpga_flow.py | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py
index cd9a80f81..434163410 100644
--- a/openfpga_flow/scripts/run_fpga_flow.py
+++ b/openfpga_flow/scripts/run_fpga_flow.py
@@ -80,9 +80,6 @@ parser.add_argument('--run_dir', type=str,
                     default=os.path.join(openfpga_base_dir,  'tmp'),
                     help="Directory to store intermidiate file & final results")
 parser.add_argument('--openfpga_shell_template', type=str,
-                    default=os.path.join(openfpga_base_dir, 'openfpga_flow',
-                                         'OpenFPGAShellScripts',
-                                         'example_script.openfpga'),
                     help="Sample openfpga shell script")
 parser.add_argument('--openfpga_arch_file', type=str,
                     help="Openfpga architecture file for shell")
@@ -258,6 +255,7 @@ def main():
     # if (args.fpga_flow == "vtr_standard"):
     #     run_abc_for_standarad()
     if args.openfpga_shell_template:
+        logger.info("Runing OpenFPGA Shell Engine ")
         run_openfpga_shell()
     else:
         run_vpr()
@@ -591,13 +589,15 @@ def collect_files_for_vpr():
     shutil.copy(args.base_verilog, args.top_module+"_output_verilog.v")
 
     # Sanitize provided openshell template, if provided
-    if not os.path.isfile(args.openfpga_shell_template or ""):
-        logger.error("Openfpga shell file - %s" % args.openfpga_shell_template)
-        clean_up_and_exit("Provided openfpga_shell_template" +
-                          f" {args.openfpga_shell_template} file not found")
-    else:
-        shutil.copy(args.openfpga_shell_template,
-                    args.top_module+"_template.openfpga")
+    if (args.openfpga_shell_template):
+        if not os.path.isfile(args.openfpga_shell_template or ""):
+            logger.error("Openfpga shell file - %s" %
+                         args.openfpga_shell_template)
+            clean_up_and_exit("Provided openfpga_shell_template" +
+                              f" {args.openfpga_shell_template} file not found")
+        else:
+            shutil.copy(args.openfpga_shell_template,
+                        args.top_module+"_template.openfpga")
 
 
 def run_vpr():

From 1fb37f4c719a494af835feeda7911304471bc358 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 8 Apr 2020 12:55:09 -0600
Subject: [PATCH 406/645] improve directory creator to support same
 functionality as 'mkdir -p'

---
 .../libopenfpgautil/src/openfpga_digest.cpp   | 137 ++++++++++++++----
 .../libopenfpgautil/src/openfpga_digest.h     |   2 +-
 .../annotation/write_xml_device_rr_gsb.cpp    |   2 +-
 openfpga/src/base/openfpga_bitstream.cpp      |   2 +-
 openfpga/src/base/openfpga_sdc.cpp            |   4 +-
 openfpga/src/fpga_verilog/verilog_api.cpp     |  10 +-
 6 files changed, 121 insertions(+), 36 deletions(-)

diff --git a/libopenfpga/libopenfpgautil/src/openfpga_digest.cpp b/libopenfpga/libopenfpgautil/src/openfpga_digest.cpp
index 4714700e4..3ae2083df 100644
--- a/libopenfpga/libopenfpgautil/src/openfpga_digest.cpp
+++ b/libopenfpga/libopenfpgautil/src/openfpga_digest.cpp
@@ -3,6 +3,7 @@
  * in OpenFPGA framework
  *******************************************************************/
 #include <sys/stat.h>
+#include <vector>
 #include <algorithm>
 
 /* Headers from vtrutil library */
@@ -117,37 +118,121 @@ std::string find_path_dir_name(const std::string& file_name) {
 /******************************************************************** 
  * Create a directory with a given path
  ********************************************************************/
-bool create_dir_path(const char* dir_path) {
-   /* Give up if the path is empty */
-   if (nullptr == dir_path) {
-     VTR_LOG_ERROR("dir_path is empty and nothing is created.\n");
-     return false;
-   }
+static 
+bool create_dir_path(const std::string& dir_path,
+                     const bool& verbose) {
+  /* Give up if the path is empty */
+  if (true == dir_path.empty()) {
+    VTR_LOG_ERROR("Directory path is empty and nothing will be created.\n");
+    return false;
+  }
 
-   /* Try to create a directory */
-   int ret = mkdir(dir_path, S_IRWXU|S_IRWXG|S_IROTH|S_IXOTH);
+  /* Try to create a directory */
+  int ret = mkdir(dir_path.c_str(), S_IRWXU|S_IRWXG|S_IROTH|S_IXOTH);
 
-   /* Analyze the return flag and output status */
-   switch (ret) {
-   case 0:
-     VTR_LOG("Succeed to create directory '%s'\n",
-             dir_path);
-     return true;
-   case -1:
-     if (EEXIST == errno) {
-       VTR_LOG_WARN("Directory '%s' already exists. Will overwrite contents\n",
-                     dir_path);
-       return true;
-     }
-     break;
-   default:
-     VTR_LOG_ERROR("Create directory '%s'...Failed!\n",
-                 dir_path);
-     exit(1);
-     return false;
+  /* Analyze the return flag and output status */
+  switch (ret) {
+  case 0:
+    VTR_LOGV(verbose,
+             "Succeed to create directory '%s'\n",
+             dir_path.c_str());
+    return true;
+  case -1:
+    if (EEXIST == errno) {
+      VTR_LOGV_WARN(verbose,
+                    "Directory '%s' already exists. Will overwrite contents\n",
+                    dir_path.c_str());
+      return true;
+    }
+    VTR_LOG_ERROR("Create directory '%s'...Failed!\n",
+                  dir_path.c_str());
+    exit(1);
+    break;
+  default:
+    VTR_LOG_ERROR("Create directory '%s'...Failed!\n",
+                  dir_path.c_str());
+    exit(1);
+    return false;
   }
 
   return false;
 }
 
+/******************************************************************** 
+ * Recursively create a directory with a given path
+ * The create_dir_path() function will only try to create a directory
+ * in the last level. If any parent directory is not created, it will
+ * always fail.
+ * This function will try to create all the parent directory before 
+ * creating the last level. 
+ ********************************************************************/
+static 
+bool rec_create_dir_path(const std::string& dir_path) {
+  /* Give up if the path is empty */
+  if (true == dir_path.empty()) {
+    VTR_LOG_ERROR("Directory path is empty and nothing will be created.\n");
+    return false;
+  }
+
+  /* Try to find the positions of all the slashes
+   * which are the splitter between directories
+   */
+  char back_slash = '/';
+
+#ifdef _WIN32
+/* For windows OS, replace any '/' with '\' */
+  char back_slash = '\\';
+#endif 
+
+  std::vector<size_t> slash_pos; 
+ 
+  /* Keep searching until we reach the end of the string */
+  for (size_t pos = 0; pos < dir_path.size(); ++pos) {
+    /* Skip the pos = 0, we should avoid creating any root directory */
+    if ( (back_slash == dir_path.at(pos))
+      && (0 != pos))  {
+      slash_pos.push_back(pos);
+    }
+  }
+
+  /* Create directory by following the position of back slash
+   * For each back slash, create a sub string from the beginning 
+   * and try to create directory
+   */
+  for (const size_t& pos : slash_pos) {
+    std::string sub_dir = dir_path.substr(0, pos);
+
+    /* Turn on verbose output only for the last position: the leaf directory */
+    if (false == create_dir_path(sub_dir, &pos == &slash_pos.back())) {
+      return false;
+    } 
+  }
+
+  return true;
+}
+
+/******************************************************************** 
+ * Top function to create a directory with a given path
+ * Allow users to select if use the recursive way or not
+ *
+ * Strongly recommend to use the recursive way, as it can maximum
+ * guarantee the success in creation of directories
+ ********************************************************************/
+void create_directory(const std::string& dir_path, const bool& recursive) { 
+  std::string formatted_dir_path = format_dir_path(dir_path);
+  bool status = false;
+
+  if (true == recursive) {
+    status = rec_create_dir_path(formatted_dir_path); 
+  } else {
+    status = create_dir_path(formatted_dir_path, true);
+  }
+
+  if (false == status) {
+    VTR_LOG_ERROR("Fail to create directory '%s'\n",
+                  formatted_dir_path.c_str());
+    exit(1);
+  }
+}
+
 } /* namespace openfpga ends */
diff --git a/libopenfpga/libopenfpgautil/src/openfpga_digest.h b/libopenfpga/libopenfpgautil/src/openfpga_digest.h
index 90af3dc4e..0e1cd5d76 100644
--- a/libopenfpga/libopenfpgautil/src/openfpga_digest.h
+++ b/libopenfpga/libopenfpgautil/src/openfpga_digest.h
@@ -23,7 +23,7 @@ std::string find_path_file_name(const std::string& file_name);
 
 std::string find_path_dir_name(const std::string& file_name);
 
-bool create_dir_path(const char* dir_path);
+void create_directory(const std::string& dir_path, const bool& recursive = true); 
 
 } /* namespace openfpga ends */
 
diff --git a/openfpga/src/annotation/write_xml_device_rr_gsb.cpp b/openfpga/src/annotation/write_xml_device_rr_gsb.cpp
index 906c71d70..63c5454a7 100644
--- a/openfpga/src/annotation/write_xml_device_rr_gsb.cpp
+++ b/openfpga/src/annotation/write_xml_device_rr_gsb.cpp
@@ -182,7 +182,7 @@ void write_device_rr_gsb_to_xml(const char* sb_xml_dir,
   std::string xml_dir_name = format_dir_path(std::string(sb_xml_dir));
 
   /* Create directories */
-  create_dir_path(xml_dir_name.c_str());
+  create_directory(xml_dir_name);
 
   vtr::Point<size_t> sb_range = device_rr_gsb.get_gsb_range();
 
diff --git a/openfpga/src/base/openfpga_bitstream.cpp b/openfpga/src/base/openfpga_bitstream.cpp
index e732dee92..e472e7618 100644
--- a/openfpga/src/base/openfpga_bitstream.cpp
+++ b/openfpga/src/base/openfpga_bitstream.cpp
@@ -36,7 +36,7 @@ void fpga_bitstream(OpenfpgaContext& openfpga_ctx,
     std::string src_dir_path = find_path_dir_name(cmd_context.option_value(cmd, opt_file));
 
     /* Create directories */
-    create_dir_path(src_dir_path.c_str());
+    create_directory(src_dir_path);
 
     write_arch_independent_bitstream_to_xml_file(openfpga_ctx.bitstream_manager(),
                                                  cmd_context.option_value(cmd, opt_file));
diff --git a/openfpga/src/base/openfpga_sdc.cpp b/openfpga/src/base/openfpga_sdc.cpp
index cb2e1bf72..06b594e73 100644
--- a/openfpga/src/base/openfpga_sdc.cpp
+++ b/openfpga/src/base/openfpga_sdc.cpp
@@ -42,7 +42,7 @@ void write_pnr_sdc(OpenfpgaContext& openfpga_ctx,
   std::string sdc_dir_path = format_dir_path(cmd_context.option_value(cmd, opt_output_dir));
 
   /* Create directories */
-  create_dir_path(sdc_dir_path.c_str());
+  create_directory(sdc_dir_path);
 
   PnrSdcOption options(sdc_dir_path);
 
@@ -96,7 +96,7 @@ void write_analysis_sdc(OpenfpgaContext& openfpga_ctx,
   std::string sdc_dir_path = format_dir_path(cmd_context.option_value(cmd, opt_output_dir));
 
   /* Create directories */
-  create_dir_path(sdc_dir_path.c_str());
+  create_directory(sdc_dir_path);
 
   AnalysisSdcOption options(sdc_dir_path);
   options.set_generate_sdc_analysis(true);
diff --git a/openfpga/src/fpga_verilog/verilog_api.cpp b/openfpga/src/fpga_verilog/verilog_api.cpp
index dc332db58..c37b68888 100644
--- a/openfpga/src/fpga_verilog/verilog_api.cpp
+++ b/openfpga/src/fpga_verilog/verilog_api.cpp
@@ -63,19 +63,19 @@ void fpga_fabric_verilog(ModuleManager& module_manager,
   std::string src_dir_path = format_dir_path(options.output_directory());
 
   /* Create directories */
-  create_dir_path(src_dir_path.c_str());
+  create_directory(src_dir_path);
 
   /* Sub directory under SRC directory to contain all the primitive block netlists */
   std::string submodule_dir_path = src_dir_path + std::string(DEFAULT_SUBMODULE_DIR_NAME);
-  create_dir_path(submodule_dir_path.c_str());
+  create_directory(submodule_dir_path);
 
   /* Sub directory under SRC directory to contain all the logic block netlists */
   std::string lb_dir_path = src_dir_path + std::string(DEFAULT_LB_DIR_NAME);
-  create_dir_path(lb_dir_path.c_str());
+  create_directory(lb_dir_path);
 
   /* Sub directory under SRC directory to contain all the routing block netlists */
   std::string rr_dir_path = src_dir_path + std::string(DEFAULT_RR_DIR_NAME);
-  create_dir_path(rr_dir_path.c_str());
+  create_directory(rr_dir_path);
 
   /* Print Verilog files containing preprocessing flags */
   print_verilog_preprocessing_flags_netlist(std::string(src_dir_path),
@@ -153,7 +153,7 @@ void fpga_verilog_testbench(const ModuleManager& module_manager,
   std::string netlist_name = atom_ctx.nlist.netlist_name();
 
   /* Create directories */
-  create_dir_path(src_dir_path.c_str());
+  create_directory(src_dir_path);
 
   /* TODO: check if this works here. This function was in fabric generator */
   print_verilog_simulation_preprocessing_flags(std::string(src_dir_path),

From b9ade3fcb6d4421afc4aca80d4b7ebc4e27ff811 Mon Sep 17 00:00:00 2001
From: Xifan Tang <tangxifan@gmail.com>
Date: Wed, 8 Apr 2020 14:13:28 -0600
Subject: [PATCH 407/645] documentation update to introduce new features in
 script mode of OpenFPGA shell

---
 .../openfpga_shell/launch_openfpga_shell.rst  |  2 +
 .../openfpga_shell/openfpga_commands.rst      |  2 +-
 .../source/openfpga_shell/openfpga_script.rst | 39 +++++++++++++++----
 3 files changed, 35 insertions(+), 8 deletions(-)

diff --git a/docs/source/openfpga_shell/launch_openfpga_shell.rst b/docs/source/openfpga_shell/launch_openfpga_shell.rst
index 3ef6e9fb5..8ef7e3858 100644
--- a/docs/source/openfpga_shell/launch_openfpga_shell.rst
+++ b/docs/source/openfpga_shell/launch_openfpga_shell.rst
@@ -11,6 +11,8 @@ To launch OpenFPGA shell, users can choose two modes.
 
   Launch OpenFPGA in interactive mode where users type-in command by command and get runtime results
 
+  .. warning:: Currently OpenFPGA does not support continued lines and comments
+
 .. option::	--file or -f
 
   Launch OpenFPGA in script mode where users write commands in scripts and FPGA will execute them
diff --git a/docs/source/openfpga_shell/openfpga_commands.rst b/docs/source/openfpga_shell/openfpga_commands.rst
index 8f71cdb54..3712cea0d 100644
--- a/docs/source/openfpga_shell/openfpga_commands.rst
+++ b/docs/source/openfpga_shell/openfpga_commands.rst
@@ -194,7 +194,7 @@ FPGA-SDC
 
   - ``--constrain_zero_delay_paths`` Constrain all the zero-delay paths in FPGA fabric
 
-  .. note:: Zero-delay path may cause errors in some PnR tools as it is considered illegal
+    .. note:: Zero-delay path may cause errors in some PnR tools as it is considered illegal
   
   - ``--verbose`` Enable verbose output
 
diff --git a/docs/source/openfpga_shell/openfpga_script.rst b/docs/source/openfpga_shell/openfpga_script.rst
index dde33a044..7c9bd5548 100644
--- a/docs/source/openfpga_shell/openfpga_script.rst
+++ b/docs/source/openfpga_shell/openfpga_script.rst
@@ -4,8 +4,20 @@ OpenFPGA Script Format
 ----------------------
 
 OpenFPGA accepts a simplified tcl-like script format.
-Commented lines are started with `#`.
-Note that comments can be added inline or as a new line.
+
+.. option:: Comments
+   
+   Any content after a ``#`` will be treated as comments.
+   Comments will not be executed.
+
+  .. note:: comments can be added inline or as a new line. See the example below
+
+.. option:: Continued line
+  
+   Lines to be continued should be finished with ``\``.
+   Continued lines will be conjuncted and executed as one line
+ 
+  .. note:: please ensure necessary spaces. Otherwise it may cause command parser fail.
 
 The following is an example.
 
@@ -21,7 +33,8 @@ The following is an example.
   #write_openfpga_arch -f ./arch_echo.xml
   
   # Annotate the OpenFPGA architecture to VPR data base
-  link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose
+  link_openfpga_arch --activity_file ./test_blif/and.act \
+                     --sort_gsb_chan_node_in_edges #--verbose
   
   # Check and correct any naming conflicts in the BLIF netlist
   check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
@@ -35,7 +48,8 @@ The following is an example.
   # Build the module graph 
   #  - Enabled compression on routing architecture modules
   #  - Enable pin duplication on grid modules 
-  build_fabric --compress_routing --duplicate_grid_pin #--verbose
+  build_fabric --compress_routing \
+               --duplicate_grid_pin #--verbose
   
   # Repack the netlist to physical pbs
   # This must be done before bitstream generator and testbench generation
@@ -44,14 +58,21 @@ The following is an example.
   
   # Build the bitstream 
   #  - Output the fabric-independent bitstream to a file
-  build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
+  build_architecture_bitstream --verbose \
+                               --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
   
   # Build fabric-dependent bitstream
   build_fabric_bitstream --verbose
   
   # Write the Verilog netlist for FPGA fabric
   #  - Enable the use of explicit port mapping in Verilog netlist
-  write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
+  write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC \
+                       --explicit_port_mapping \
+                       --include_timing \
+                       --include_signal_init \
+                       --support_icarus_simulator \
+                       --print_user_defined_template \
+                       --verbose
   
   # Write the Verilog testbench for FPGA fabric
   #  - We suggest the use of same output directory as fabric Verilog netlists
@@ -59,7 +80,11 @@ The following is an example.
   #  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
   #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
   #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-  write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
+  write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC \
+                          --reference_benchmark_file_path /var/tmp/xtang/and.v \
+                          --print_top_testbench \
+                          --print_preconfig_top_testbench \
+                          --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
   
   # Write the SDC files for PnR backend
   #  - Turn on every options here 

From b9dab2baaf760d7ba5bb440e8467758349f4b2b1 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 8 Apr 2020 16:18:05 -0600
Subject: [PATCH 408/645] add exit codes to command execution in shell context

---
 .../libopenfpgashell/src/command_exit_codes.h | 27 +++++
 libopenfpga/libopenfpgashell/src/shell.h      | 55 ++++++++---
 libopenfpga/libopenfpgashell/src/shell.tpp    | 98 ++++++++++++++-----
 .../libopenfpgashell/test/test_shell.cpp      | 10 +-
 .../check_netlist_naming_conflict.cpp         | 20 +++-
 .../check_netlist_naming_conflict.h           |  4 +-
 openfpga/src/base/openfpga_bitstream.cpp      | 17 +++-
 openfpga/src/base/openfpga_bitstream.h        |  8 +-
 openfpga/src/base/openfpga_build_fabric.cpp   | 10 +-
 openfpga/src/base/openfpga_build_fabric.h     |  4 +-
 openfpga/src/base/openfpga_link_arch.cpp      | 12 ++-
 openfpga/src/base/openfpga_link_arch.h        |  4 +-
 .../base/openfpga_lut_truth_table_fixup.cpp   | 11 ++-
 .../src/base/openfpga_lut_truth_table_fixup.h |  4 +-
 openfpga/src/base/openfpga_pb_pin_fixup.cpp   | 10 +-
 openfpga/src/base/openfpga_pb_pin_fixup.h     |  4 +-
 openfpga/src/base/openfpga_read_arch.cpp      | 17 +++-
 openfpga/src/base/openfpga_read_arch.h        |  8 +-
 openfpga/src/base/openfpga_repack.cpp         | 10 +-
 openfpga/src/base/openfpga_repack.h           |  4 +-
 openfpga/src/base/openfpga_sdc.cpp            | 17 +++-
 openfpga/src/base/openfpga_sdc.h              |  8 +-
 openfpga/src/base/openfpga_verilog.cpp        | 17 +++-
 openfpga/src/base/openfpga_verilog.h          |  8 +-
 openfpga/src/base/openfpga_write_gsb.cpp      | 10 +-
 openfpga/src/base/openfpga_write_gsb.h        |  4 +-
 26 files changed, 293 insertions(+), 108 deletions(-)
 create mode 100644 libopenfpga/libopenfpgashell/src/command_exit_codes.h

diff --git a/libopenfpga/libopenfpgashell/src/command_exit_codes.h b/libopenfpga/libopenfpgashell/src/command_exit_codes.h
new file mode 100644
index 000000000..f1490e533
--- /dev/null
+++ b/libopenfpga/libopenfpgashell/src/command_exit_codes.h
@@ -0,0 +1,27 @@
+#ifndef COMMAND_EXIT_CODES_H
+#define COMMAND_EXIT_CODES_H
+
+/* Begin namespace openfpga */
+namespace openfpga {
+
+/*********************************************************************
+ * Exit codes to signal success/failure status of command execution
+ * Depend on the exit code, OpenFPGA shell will decide to continue or abort
+ ********************************************************************/
+
+/* Never been executed */
+constexpr int CMD_EXEC_NONE = -1;
+
+/* Everything OK */
+constexpr int CMD_EXEC_SUCCESS = 0;
+
+/* Fatal error occurred, we have to abort and do not execute the rest of commands */
+constexpr int CMD_EXEC_FATAL_ERROR = 1;
+
+/* See minor errors but it will not impact the downsteam. We can continue to execute the rest of commands */
+constexpr int CMD_EXEC_MINOR_ERROR = 2;
+
+
+} /* End namespace openfpga */
+
+#endif
diff --git a/libopenfpga/libopenfpgashell/src/shell.h b/libopenfpga/libopenfpgashell/src/shell.h
index 427580010..1a49b313c 100644
--- a/libopenfpga/libopenfpgashell/src/shell.h
+++ b/libopenfpga/libopenfpgashell/src/shell.h
@@ -10,6 +10,7 @@
 #include "vtr_range.h"
 #include "command.h"
 #include "command_context.h"
+#include "command_exit_codes.h"
 #include "shell_fwd.h"
 
 /* Begin namespace openfpga */
@@ -88,25 +89,49 @@ class Shell {
     ShellCommandId add_command(const Command& cmd, const char* descr);
     void set_command_class(const ShellCommandId& cmd_id, const ShellCommandClassId& cmd_class_id);
     /* Link the execute function to a command
-     * We support here three types of functions to be executed in the shell
-     * 1. Standard function, including the data exchange <T> and commands
-     * 2. Short function, including only the data exchange <T>
-     * 3. Built-in function, including only the shell envoriment variables
-     * 4. Marco function, which directly call a macro function without command parsing
+     * We support here different types of functions to be executed in the shell
      * Users just need to specify the function object and its type will be automatically inferred
+     *
+     * Note that all the function should return exit codes complying to the shell_exit_code.h
+     * execept the internal functions
+     */
+
+    /* Standard function, including the data exchange <T> and commands 
+     * This function requires the data exchange <T> to be constant
+     * This is designed for outputting functions requiring external data than the <T>
      */
     void set_command_const_execute_function(const ShellCommandId& cmd_id,
-                                      std::function<void(const T&, const Command&, const CommandContext&)> exec_func);
+                                      std::function<int(const T&, const Command&, const CommandContext&)> exec_func);
+
+    /* Standard function, including the data exchange <T> and commands 
+     * This function allows modification to the data exchange <T>
+     * This is designed for implementing functions requiring external data than the <T>
+     */
     void set_command_execute_function(const ShellCommandId& cmd_id,
-                                      std::function<void(T&, const Command&, const CommandContext&)> exec_func);
+                                      std::function<int(T&, const Command&, const CommandContext&)> exec_func);
+
+    /* Short function, including only the data exchange <T> 
+     * This function requires the data exchange <T> to be constant
+     * This is designed for outputting functions without external data than the <T>
+     */
     void set_command_const_execute_function(const ShellCommandId& cmd_id,
-                                            std::function<void(const T&)> exec_func);
+                                            std::function<int(const T&)> exec_func);
+
+    /* Short function, including only the data exchange <T> 
+     * This function allows modification to the data exchange <T>
+     * This is designed for internal implementing functions without external data than the <T>
+     */
     void set_command_execute_function(const ShellCommandId& cmd_id,
-                                      std::function<void(T&)> exec_func);
+                                      std::function<int(T&)> exec_func);
+
+    /* Built-in function, including only the shell envoriment variables */
     void set_command_execute_function(const ShellCommandId& cmd_id,
                                       std::function<void()> exec_func);
+
+    /* Marco function, which directly call a macro function without command parsing */
     void set_command_execute_function(const ShellCommandId& cmd_id,
                                       std::function<int(int, char**)> exec_func);
+
     void set_command_dependency(const ShellCommandId& cmd_id,
                                 const std::vector<ShellCommandId>& cmd_dependency);
     ShellCommandClassId add_command_class(const char* name);
@@ -126,7 +151,7 @@ class Shell {
     /* Execute a command, the command line is the user's input to launch a command
      * The common_context is the data structure to exchange data between commands
      */
-    void execute_command(const char* cmd_line, T& common_context);
+    int execute_command(const char* cmd_line, T& common_context);
   private: /* Internal data */ 
     /* Name of the shell, this will appear in the interactive mode */
     std::string name_;
@@ -162,10 +187,10 @@ class Shell {
      * 3. Built-in function, including only the shell envoriment variables
      * 4. Marco function, which directly call a macro function without command parsing
      */
-    vtr::vector<ShellCommandId, std::function<void(const T&, const Command&, const CommandContext&)>> command_const_execute_functions_;  
-    vtr::vector<ShellCommandId, std::function<void(T&, const Command&, const CommandContext&)>> command_standard_execute_functions_;  
-    vtr::vector<ShellCommandId, std::function<void(const T&)>> command_short_const_execute_functions_; 
-    vtr::vector<ShellCommandId, std::function<void(T&)>> command_short_execute_functions_; 
+    vtr::vector<ShellCommandId, std::function<int(const T&, const Command&, const CommandContext&)>> command_const_execute_functions_;  
+    vtr::vector<ShellCommandId, std::function<int(T&, const Command&, const CommandContext&)>> command_standard_execute_functions_;  
+    vtr::vector<ShellCommandId, std::function<int(const T&)>> command_short_const_execute_functions_; 
+    vtr::vector<ShellCommandId, std::function<int(T&)>> command_short_execute_functions_; 
     vtr::vector<ShellCommandId, std::function<void()>> command_builtin_execute_functions_;  
     vtr::vector<ShellCommandId, std::function<int(int, char**)>> command_macro_execute_functions_;  
 
@@ -175,7 +200,7 @@ class Shell {
     vtr::vector<ShellCommandId, e_exec_func_type> command_execute_function_types_;  
 
     /* A flag to indicate if the command has been executed */  
-    vtr::vector<ShellCommandId, bool> command_status_;  
+    vtr::vector<ShellCommandId, int> command_status_;  
 
     /* Dependency graph for different commands,
      * This helps the shell interface to check if a command need other commands to be run before its execution  
diff --git a/libopenfpga/libopenfpgashell/src/shell.tpp b/libopenfpga/libopenfpgashell/src/shell.tpp
index 5fe043f8e..69ec89ab9 100644
--- a/libopenfpga/libopenfpgashell/src/shell.tpp
+++ b/libopenfpga/libopenfpgashell/src/shell.tpp
@@ -131,7 +131,7 @@ ShellCommandId Shell<T>::add_command(const Command& cmd, const char* descr) {
   command_short_execute_functions_.emplace_back();
   command_builtin_execute_functions_.emplace_back();
   command_macro_execute_functions_.emplace_back();
-  command_status_.push_back(false); /* By default, the command should be marked as never executed */
+  command_status_.push_back(CMD_EXEC_NONE); /* By default, the command should be marked as fatal error as it has been never executed */
   command_dependencies_.emplace_back();
 
   /* Register the name in the name2id map */
@@ -155,7 +155,7 @@ void Shell<T>::set_command_class(const ShellCommandId& cmd_id, const ShellComman
 
 template<class T>
 void Shell<T>::set_command_const_execute_function(const ShellCommandId& cmd_id, 
-                                                  std::function<void(const T&, const Command&, const CommandContext&)> exec_func) {
+                                                  std::function<int(const T&, const Command&, const CommandContext&)> exec_func) {
   VTR_ASSERT(true == valid_command_id(cmd_id));
   command_execute_function_types_[cmd_id] = CONST_STANDARD;
   command_const_execute_functions_[cmd_id] = exec_func;
@@ -163,7 +163,7 @@ void Shell<T>::set_command_const_execute_function(const ShellCommandId& cmd_id,
 
 template<class T>
 void Shell<T>::set_command_execute_function(const ShellCommandId& cmd_id, 
-                                            std::function<void(T&, const Command&, const CommandContext&)> exec_func) {
+                                            std::function<int(T&, const Command&, const CommandContext&)> exec_func) {
   VTR_ASSERT(true == valid_command_id(cmd_id));
   command_execute_function_types_[cmd_id] = STANDARD;
   command_standard_execute_functions_[cmd_id] = exec_func;
@@ -171,7 +171,7 @@ void Shell<T>::set_command_execute_function(const ShellCommandId& cmd_id,
 
 template<class T>
 void Shell<T>::set_command_const_execute_function(const ShellCommandId& cmd_id, 
-                                                  std::function<void(const T&)> exec_func) {
+                                                  std::function<int(const T&)> exec_func) {
   VTR_ASSERT(true == valid_command_id(cmd_id));
   command_execute_function_types_[cmd_id] = CONST_SHORT;
   command_short_const_execute_functions_[cmd_id] = exec_func;
@@ -179,7 +179,7 @@ void Shell<T>::set_command_const_execute_function(const ShellCommandId& cmd_id,
 
 template<class T>
 void Shell<T>::set_command_execute_function(const ShellCommandId& cmd_id, 
-                                            std::function<void(T&)> exec_func) {
+                                            std::function<int(T&)> exec_func) {
   VTR_ASSERT(true == valid_command_id(cmd_id));
   command_execute_function_types_[cmd_id] = SHORT;
   command_short_execute_functions_[cmd_id] = exec_func;
@@ -341,9 +341,15 @@ void Shell<T>::run_script_mode(const char* script_file_name, T& context) {
     /* Process the command only when the full command line in ended */
     if (!cmd_line.empty()) {
       VTR_LOG("\nCommand line to execute: %s\n", cmd_line.c_str());
-      execute_command(cmd_line.c_str(), context);
+      int status = execute_command(cmd_line.c_str(), context);
       /* Empty the line ready to start a new line */
       cmd_line.clear();
+
+      /* Check the execution status of the command, if fatal error happened, we should abort immediately */
+      if (CMD_EXEC_FATAL_ERROR == status) {
+        VTR_LOG("Fatal error occurred!\nAbort and enter interactive mode\n");
+        break;
+      }
     }
   }
   fp.close();
@@ -376,16 +382,49 @@ void Shell<T>::print_commands() const {
 
 template <class T>
 void Shell<T>::exit() const {
+  /* Check all the command status, if we see fatal errors or minor errors, we drop an error code */
+  int exit_code = 0;
+  for (const int& status : command_status_) {
+    if ( (status == CMD_EXEC_FATAL_ERROR)
+      || (status == CMD_EXEC_MINOR_ERROR) ) {
+      exit_code = 1;
+      break;
+    }
+  } 
+
+  /* Show error message if we detect any errors */
+  int num_err = 0;
+  if (0 != exit_code) {
+    VTR_LOG("\n");
+    for (const ShellCommandId& cmd : commands()) {
+      if (command_status_[cmd] == CMD_EXEC_FATAL_ERROR) {
+        VTR_LOG_ERROR("Command '%s' execution has fatal errors\n",
+                      commands_[cmd].name().c_str());
+        num_err++;
+      }
+        
+      if (command_status_[cmd] == CMD_EXEC_MINOR_ERROR) {
+        VTR_LOG_ERROR("Command '%s' execution has minor errors\n",
+                      commands_[cmd].name().c_str());
+        num_err++;
+      }
+    }
+  }
+
+  VTR_LOG("\nFinish execution with %d errors\n",
+            num_err);
+
   VTR_LOG("\nThank you for using %s!\n",
           name().c_str());
-  std::exit(0);
+
+  std::exit(exit_code);
 }
 
 /************************************************************************
  * Private executors
  ***********************************************************************/
 template <class T>
-void Shell<T>::execute_command(const char* cmd_line,
+int Shell<T>::execute_command(const char* cmd_line,
                                T& common_context) {
   /* Tokenize the line */
   openfpga::StringToken tokenizer(cmd_line);  
@@ -396,17 +435,18 @@ void Shell<T>::execute_command(const char* cmd_line,
   if (ShellCommandId::INVALID() == cmd_id) {
     VTR_LOG("Try to call a command '%s' which is not defined!\n",
             tokens[0].c_str());
-    return;
+    return CMD_EXEC_FATAL_ERROR;
   }
 
   /* Check the dependency graph to see if all the prequistics have been met */
   for (const ShellCommandId& dep_cmd : command_dependencies_[cmd_id]) {
-    if (false == command_status_[dep_cmd]) {
+    if ( (CMD_EXEC_NONE == command_status_[dep_cmd])
+      || (CMD_EXEC_FATAL_ERROR == command_status_[dep_cmd]) ) {
       VTR_LOG("Command '%s' is required to be executed before command '%s'!\n",
               commands_[dep_cmd].name().c_str(), commands_[cmd_id].name().c_str());
       /* Echo the command help desk */
       print_command_options(commands_[cmd_id]);
-      return;
+      return CMD_EXEC_FATAL_ERROR;
     } 
   }
 
@@ -421,25 +461,22 @@ void Shell<T>::execute_command(const char* cmd_line,
       argv[itok] = (char*)malloc((tokens[itok].length() + 1) * sizeof(char));
       strcpy(argv[itok], tokens[itok].c_str());
     }
-    /* Execute the marco function */
-    command_macro_execute_functions_[cmd_id](tokens.size(), argv);
+    /* Execute the marco function and record the execution status */
+    command_status_[cmd_id] = command_macro_execute_functions_[cmd_id](tokens.size(), argv);
     /* Free the argv */
     for (size_t itok = 0; itok < tokens.size(); ++itok) {
       free(argv[itok]);
     }
     free(argv);
 
-    /* Change the status of the command */
-    command_status_[cmd_id] = true;
-
     /* Finish for macro command, return */
-    return;
+    return command_status_[cmd_id];
   }
  
   if (false == parse_command(tokens, commands_[cmd_id], command_contexts_[cmd_id])) {
     /* Echo the command */
     print_command_options(commands_[cmd_id]);
-    return;
+    return CMD_EXEC_FATAL_ERROR;
   }
  
   /* Parse succeed. Let user to confirm selected options */ 
@@ -448,31 +485,38 @@ void Shell<T>::execute_command(const char* cmd_line,
   /* Execute the command depending on the type of function ! */ 
   switch (command_execute_function_types_[cmd_id]) {
   case CONST_STANDARD:
-    command_const_execute_functions_[cmd_id](common_context, commands_[cmd_id], command_contexts_[cmd_id]);
+    command_status_[cmd_id] = command_const_execute_functions_[cmd_id](common_context, commands_[cmd_id], command_contexts_[cmd_id]);
     break;
   case STANDARD:
-    command_standard_execute_functions_[cmd_id](common_context, commands_[cmd_id], command_contexts_[cmd_id]);
+    command_status_[cmd_id] = command_standard_execute_functions_[cmd_id](common_context, commands_[cmd_id], command_contexts_[cmd_id]);
     break;
   case CONST_SHORT:
-    command_short_const_execute_functions_[cmd_id](common_context);
+    command_status_[cmd_id] = command_short_const_execute_functions_[cmd_id](common_context);
     break;
   case SHORT:
-    command_short_execute_functions_[cmd_id](common_context);
+    command_status_[cmd_id] = command_short_execute_functions_[cmd_id](common_context);
     break;
   case BUILTIN:
     command_builtin_execute_functions_[cmd_id]();
+    /* Built-in execution is always correct */
+    command_status_[cmd_id] = CMD_EXEC_SUCCESS; 
     break;
   /* MACRO should be executed eariler in this function. It should not appear here */
   default:
     /* This is not allowed! Error out */
-    VTR_LOG("Invalid type of execute function for command '%s'!\n",
-            commands_[cmd_id].name().c_str());
+    VTR_LOG_ERROR("Invalid type of execute function for command '%s'!\n",
+                  commands_[cmd_id].name().c_str());
     /* Exit the shell using the exit() function inside this class! */
-    exit();
+    return CMD_EXEC_FATAL_ERROR;
   }
 
-  /* Change the status of the command */
-  command_status_[cmd_id] = true;
+  /* Forbid users to return the status CMD_EXEC_NONE */
+  if (CMD_EXEC_NONE == command_status_[cmd_id]) {
+    VTR_LOG_ERROR("It is illegal to return never-executed status for an executed command!\n");
+    return CMD_EXEC_FATAL_ERROR;
+  }
+
+  return command_status_[cmd_id];
 }
 
 /************************************************************************
diff --git a/libopenfpga/libopenfpgashell/test/test_shell.cpp b/libopenfpga/libopenfpgashell/test/test_shell.cpp
index 649859d85..0edc257dd 100644
--- a/libopenfpga/libopenfpgashell/test/test_shell.cpp
+++ b/libopenfpga/libopenfpgashell/test/test_shell.cpp
@@ -15,16 +15,20 @@ class ShellContext {
 };
 
 static
-void shell_execute_set(ShellContext& context, 
+int shell_execute_set(ShellContext& context, 
                        const Command& cmd, const CommandContext& cmd_context) {
   CommandOptionId opt_id = cmd.option("value");
   /* Get the value of a in the command context */
   context.a = std::atoi(cmd_context.option_value(cmd, opt_id).c_str());
+
+  return CMD_EXEC_SUCCESS; 
 }
 
 static
-void shell_execute_print(ShellContext& context) {
+int shell_execute_print(ShellContext& context) {
   VTR_LOG("a=%d\n", context.a);
+
+  return CMD_EXEC_SUCCESS; 
 }
 
 static
@@ -35,7 +39,7 @@ int shell_execute_print_macro(int argc, char** argv) {
     VTR_LOG("\t[%d]: %s\n", iarg, argv[iarg]);
   }
 
-  return 0;
+  return CMD_EXEC_SUCCESS; 
 }
 
 int main(int argc, char** argv) {
diff --git a/openfpga/src/annotation/check_netlist_naming_conflict.cpp b/openfpga/src/annotation/check_netlist_naming_conflict.cpp
index 3470c9f0a..a8ab94384 100644
--- a/openfpga/src/annotation/check_netlist_naming_conflict.cpp
+++ b/openfpga/src/annotation/check_netlist_naming_conflict.cpp
@@ -11,6 +11,9 @@
 #include "vtr_assert.h"
 #include "vtr_log.h"
 
+/* Headers from openfpgashell library */
+#include "command_exit_codes.h"
+
 /* Headers from archopenfpga library */
 #include "write_xml_utils.h" 
 
@@ -213,8 +216,8 @@ void print_netlist_naming_fix_report(const std::string& fname,
  * in the users' BLIF netlist that violates the syntax of OpenFPGA
  * fabric generator, i.e., Verilog generator and SPICE generator
  *******************************************************************/
-void check_netlist_naming_conflict(OpenfpgaContext& openfpga_context,
-                                   const Command& cmd, const CommandContext& cmd_context) {
+int check_netlist_naming_conflict(OpenfpgaContext& openfpga_context,
+                                  const Command& cmd, const CommandContext& cmd_context) {
   vtr::ScopedStartFinishTimer timer("Check naming violations of netlist blocks and nets");
 
   /* By default, we replace all the illegal characters with '_' */
@@ -231,7 +234,15 @@ void check_netlist_naming_conflict(OpenfpgaContext& openfpga_context,
                   num_conflicts);
     VTR_LOGV(0 == num_conflicts, 
              "Check naming conflicts in the netlist passed.\n");
-    return;
+
+    /* If we see conflicts, report minor error */
+    if (0 < num_conflicts) {
+      return CMD_EXEC_MINOR_ERROR;
+    }
+
+    /* Otherwise, we should see zero conflicts */
+    VTR_ASSERT(0 == num_conflicts);
+    return CMD_EXEC_SUCCESS;
   }
 
   /* If the auto correction is enabled, we apply a fix */
@@ -248,6 +259,9 @@ void check_netlist_naming_conflict(OpenfpgaContext& openfpga_context,
               cmd_context.option_value(cmd, opt_report).c_str());
     }
   } 
+
+  /* TODO: should identify the error code from internal function execution */
+  return CMD_EXEC_SUCCESS;
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/annotation/check_netlist_naming_conflict.h b/openfpga/src/annotation/check_netlist_naming_conflict.h
index 54d86bca4..cad6c3963 100644
--- a/openfpga/src/annotation/check_netlist_naming_conflict.h
+++ b/openfpga/src/annotation/check_netlist_naming_conflict.h
@@ -15,8 +15,8 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-void check_netlist_naming_conflict(OpenfpgaContext& openfpga_context,
-                                   const Command& cmd, const CommandContext& cmd_context); 
+int check_netlist_naming_conflict(OpenfpgaContext& openfpga_context,
+                                  const Command& cmd, const CommandContext& cmd_context); 
 
 } /* end namespace openfpga */
 
diff --git a/openfpga/src/base/openfpga_bitstream.cpp b/openfpga/src/base/openfpga_bitstream.cpp
index e472e7618..7e2a19fc4 100644
--- a/openfpga/src/base/openfpga_bitstream.cpp
+++ b/openfpga/src/base/openfpga_bitstream.cpp
@@ -5,6 +5,9 @@
 #include "vtr_time.h"
 #include "vtr_log.h"
 
+/* Headers from openfpgashell library */
+#include "command_exit_codes.h"
+
 /* Headers from openfpgautil library */
 #include "openfpga_digest.h"
 
@@ -22,8 +25,8 @@ namespace openfpga {
 /********************************************************************
  * A wrapper function to call the build_device_bitstream() in FPGA bitstream
  *******************************************************************/
-void fpga_bitstream(OpenfpgaContext& openfpga_ctx,
-                    const Command& cmd, const CommandContext& cmd_context) {
+int fpga_bitstream(OpenfpgaContext& openfpga_ctx,
+                   const Command& cmd, const CommandContext& cmd_context) {
 
   CommandOptionId opt_verbose = cmd.option("verbose");
   CommandOptionId opt_file = cmd.option("file");
@@ -41,19 +44,25 @@ void fpga_bitstream(OpenfpgaContext& openfpga_ctx,
     write_arch_independent_bitstream_to_xml_file(openfpga_ctx.bitstream_manager(),
                                                  cmd_context.option_value(cmd, opt_file));
   }
+
+  /* TODO: should identify the error code from internal function execution */
+  return CMD_EXEC_SUCCESS;
 }
 
 /********************************************************************
  * A wrapper function to call the build_fabric_bitstream() in FPGA bitstream
  *******************************************************************/
-void build_fabric_bitstream(OpenfpgaContext& openfpga_ctx,
-                            const Command& cmd, const CommandContext& cmd_context) {
+int build_fabric_bitstream(OpenfpgaContext& openfpga_ctx,
+                           const Command& cmd, const CommandContext& cmd_context) {
 
   CommandOptionId opt_verbose = cmd.option("verbose");
 
   openfpga_ctx.mutable_fabric_bitstream() = build_fabric_dependent_bitstream(openfpga_ctx.bitstream_manager(),
                                                                              openfpga_ctx.module_graph(),
                                                                              cmd_context.option_enable(cmd, opt_verbose));
+  
+  /* TODO: should identify the error code from internal function execution */
+  return CMD_EXEC_SUCCESS;
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_bitstream.h b/openfpga/src/base/openfpga_bitstream.h
index 9dc2ad471..58f1c7e86 100644
--- a/openfpga/src/base/openfpga_bitstream.h
+++ b/openfpga/src/base/openfpga_bitstream.h
@@ -15,11 +15,11 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-void fpga_bitstream(OpenfpgaContext& openfpga_ctx,
-                    const Command& cmd, const CommandContext& cmd_context); 
+int fpga_bitstream(OpenfpgaContext& openfpga_ctx,
+                   const Command& cmd, const CommandContext& cmd_context); 
 
-void build_fabric_bitstream(OpenfpgaContext& openfpga_ctx,
-                            const Command& cmd, const CommandContext& cmd_context);
+int build_fabric_bitstream(OpenfpgaContext& openfpga_ctx,
+                           const Command& cmd, const CommandContext& cmd_context);
 
 } /* end namespace openfpga */
 
diff --git a/openfpga/src/base/openfpga_build_fabric.cpp b/openfpga/src/base/openfpga_build_fabric.cpp
index 4e8b44916..67203216a 100644
--- a/openfpga/src/base/openfpga_build_fabric.cpp
+++ b/openfpga/src/base/openfpga_build_fabric.cpp
@@ -5,6 +5,9 @@
 #include "vtr_time.h"
 #include "vtr_log.h"
 
+/* Headers from openfpgashell library */
+#include "command_exit_codes.h"
+
 #include "device_rr_gsb.h"
 #include "device_rr_gsb_utils.h"
 #include "build_device_module.h"
@@ -56,8 +59,8 @@ void compress_routing_hierarchy(OpenfpgaContext& openfpga_ctx,
 /********************************************************************
  * Build the module graph for FPGA device
  *******************************************************************/
-void build_fabric(OpenfpgaContext& openfpga_ctx,
-                  const Command& cmd, const CommandContext& cmd_context) { 
+int build_fabric(OpenfpgaContext& openfpga_ctx,
+                 const Command& cmd, const CommandContext& cmd_context) { 
 
   CommandOptionId opt_compress_routing = cmd.option("compress_routing");
   CommandOptionId opt_duplicate_grid_pin = cmd.option("duplicate_grid_pin");
@@ -77,6 +80,9 @@ void build_fabric(OpenfpgaContext& openfpga_ctx,
                                                                   cmd_context.option_enable(cmd, opt_compress_routing),
                                                                   cmd_context.option_enable(cmd, opt_duplicate_grid_pin),
                                                                   cmd_context.option_enable(cmd, opt_verbose));
+
+  /* TODO: should identify the error code from internal function execution */
+  return CMD_EXEC_SUCCESS;
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_build_fabric.h b/openfpga/src/base/openfpga_build_fabric.h
index 824ed63a1..3b63c7ab2 100644
--- a/openfpga/src/base/openfpga_build_fabric.h
+++ b/openfpga/src/base/openfpga_build_fabric.h
@@ -15,8 +15,8 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-void build_fabric(OpenfpgaContext& openfpga_ctx,
-                  const Command& cmd, const CommandContext& cmd_context); 
+int build_fabric(OpenfpgaContext& openfpga_ctx,
+                 const Command& cmd, const CommandContext& cmd_context); 
 
 } /* end namespace openfpga */
 
diff --git a/openfpga/src/base/openfpga_link_arch.cpp b/openfpga/src/base/openfpga_link_arch.cpp
index 34c98ee8d..65aef7cf8 100644
--- a/openfpga/src/base/openfpga_link_arch.cpp
+++ b/openfpga/src/base/openfpga_link_arch.cpp
@@ -8,6 +8,9 @@
 #include "vtr_assert.h"
 #include "vtr_log.h"
 
+/* Headers from openfpgashell library */
+#include "command_exit_codes.h"
+
 /* Headers from vpr library */
 #include "read_activity.h"
 
@@ -59,8 +62,8 @@ bool is_vpr_rr_graph_supported(const RRGraph& rr_graph) {
  * - physical pb_graph nodes and pb_graph pins
  * - circuit models for global routing architecture
  *******************************************************************/
-void link_arch(OpenfpgaContext& openfpga_ctx,
-               const Command& cmd, const CommandContext& cmd_context) { 
+int link_arch(OpenfpgaContext& openfpga_ctx,
+              const Command& cmd, const CommandContext& cmd_context) { 
 
   vtr::ScopedStartFinishTimer timer("Link OpenFPGA architecture to VPR architecture");
 
@@ -105,7 +108,7 @@ void link_arch(OpenfpgaContext& openfpga_ctx,
    * - DeviceRRGSB 
    */
   if (false == is_vpr_rr_graph_supported(g_vpr_ctx.device().rr_graph)) {
-    return;
+    return CMD_EXEC_FATAL_ERROR;
   }
 
   annotate_device_rr_gsb(g_vpr_ctx.device(),
@@ -147,6 +150,9 @@ void link_arch(OpenfpgaContext& openfpga_ctx,
   annotate_simulation_setting(g_vpr_ctx.atom(),
                               openfpga_ctx.net_activity(),
                               openfpga_ctx.mutable_arch().sim_setting);
+
+  /* TODO: should identify the error code from internal function execution */
+  return CMD_EXEC_SUCCESS;
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_link_arch.h b/openfpga/src/base/openfpga_link_arch.h
index 742c29541..8eba64386 100644
--- a/openfpga/src/base/openfpga_link_arch.h
+++ b/openfpga/src/base/openfpga_link_arch.h
@@ -15,8 +15,8 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-void link_arch(OpenfpgaContext& openfpga_context, 
-               const Command& cmd, const CommandContext& cmd_context); 
+int link_arch(OpenfpgaContext& openfpga_context, 
+              const Command& cmd, const CommandContext& cmd_context); 
 
 } /* end namespace openfpga */
 
diff --git a/openfpga/src/base/openfpga_lut_truth_table_fixup.cpp b/openfpga/src/base/openfpga_lut_truth_table_fixup.cpp
index 45ecbca31..396842dcd 100644
--- a/openfpga/src/base/openfpga_lut_truth_table_fixup.cpp
+++ b/openfpga/src/base/openfpga_lut_truth_table_fixup.cpp
@@ -7,6 +7,9 @@
 #include "vtr_assert.h"
 #include "vtr_log.h"
 
+/* Headers from openfpgashell library */
+#include "command_exit_codes.h"
+
 /* Headers from vpr library */
 #include "vpr_utils.h"
 
@@ -182,7 +185,6 @@ void update_lut_tt_with_post_packing_results(const AtomContext& atom_ctx,
   }
 }
 
-
 /********************************************************************
  * Top-level function to fix up the lut truth table results after packing is done
  * The problem comes from a mismatch between the packing results and 
@@ -194,8 +196,8 @@ void update_lut_tt_with_post_packing_results(const AtomContext& atom_ctx,
  * This function aims to fix the mess after packing so that the truth table
  * can be synchronized
  *******************************************************************/
-void lut_truth_table_fixup(OpenfpgaContext& openfpga_context,
-                           const Command& cmd, const CommandContext& cmd_context) { 
+int lut_truth_table_fixup(OpenfpgaContext& openfpga_context,
+                          const Command& cmd, const CommandContext& cmd_context) { 
 
   vtr::ScopedStartFinishTimer timer("Fix up LUT truth tables after packing optimization");
 
@@ -206,6 +208,9 @@ void lut_truth_table_fixup(OpenfpgaContext& openfpga_context,
                                           g_vpr_ctx.clustering(),
                                           openfpga_context.mutable_vpr_clustering_annotation(),
                                           cmd_context.option_enable(cmd, opt_verbose));
+
+  /* TODO: should identify the error code from internal function execution */
+  return CMD_EXEC_SUCCESS;
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_lut_truth_table_fixup.h b/openfpga/src/base/openfpga_lut_truth_table_fixup.h
index f11abc7fb..d685a4b44 100644
--- a/openfpga/src/base/openfpga_lut_truth_table_fixup.h
+++ b/openfpga/src/base/openfpga_lut_truth_table_fixup.h
@@ -15,8 +15,8 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-void lut_truth_table_fixup(OpenfpgaContext& openfpga_context, 
-                           const Command& cmd, const CommandContext& cmd_context); 
+int lut_truth_table_fixup(OpenfpgaContext& openfpga_context, 
+                          const Command& cmd, const CommandContext& cmd_context); 
 
 } /* end namespace openfpga */
 
diff --git a/openfpga/src/base/openfpga_pb_pin_fixup.cpp b/openfpga/src/base/openfpga_pb_pin_fixup.cpp
index cc91bdebe..2a8686190 100644
--- a/openfpga/src/base/openfpga_pb_pin_fixup.cpp
+++ b/openfpga/src/base/openfpga_pb_pin_fixup.cpp
@@ -7,6 +7,9 @@
 #include "vtr_assert.h"
 #include "vtr_log.h"
 
+/* Headers from openfpgashell library */
+#include "command_exit_codes.h"
+
 /* Headers from vpr library */
 #include "vpr_utils.h"
 
@@ -254,8 +257,8 @@ void update_pb_pin_with_post_routing_results(const DeviceContext& device_ctx,
  * This function aims to fix the mess after routing so that the net mapping
  * can be synchronized
  *******************************************************************/
-void pb_pin_fixup(OpenfpgaContext& openfpga_context,
-                  const Command& cmd, const CommandContext& cmd_context) { 
+int pb_pin_fixup(OpenfpgaContext& openfpga_context,
+                 const Command& cmd, const CommandContext& cmd_context) { 
 
   vtr::ScopedStartFinishTimer timer("Fix up pb pin mapping results after routing optimization");
 
@@ -268,6 +271,9 @@ void pb_pin_fixup(OpenfpgaContext& openfpga_context,
                                           openfpga_context.vpr_routing_annotation(),
                                           openfpga_context.mutable_vpr_clustering_annotation(),
                                           cmd_context.option_enable(cmd, opt_verbose));
+
+  /* TODO: should identify the error code from internal function execution */
+  return CMD_EXEC_SUCCESS;
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_pb_pin_fixup.h b/openfpga/src/base/openfpga_pb_pin_fixup.h
index e924c6067..bab4e9565 100644
--- a/openfpga/src/base/openfpga_pb_pin_fixup.h
+++ b/openfpga/src/base/openfpga_pb_pin_fixup.h
@@ -15,8 +15,8 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-void pb_pin_fixup(OpenfpgaContext& openfpga_context, 
-                  const Command& cmd, const CommandContext& cmd_context); 
+int pb_pin_fixup(OpenfpgaContext& openfpga_context, 
+                 const Command& cmd, const CommandContext& cmd_context); 
 
 } /* end namespace openfpga */
 
diff --git a/openfpga/src/base/openfpga_read_arch.cpp b/openfpga/src/base/openfpga_read_arch.cpp
index 1a36e85a3..214af1612 100644
--- a/openfpga/src/base/openfpga_read_arch.cpp
+++ b/openfpga/src/base/openfpga_read_arch.cpp
@@ -5,6 +5,9 @@
 /* Headers from vtrutil library */
 #include "vtr_log.h"
 
+/* Headers from openfpgashell library */
+#include "command_exit_codes.h"
+
 /* Headers from archopenfpga library */
 #include "read_xml_openfpga_arch.h"
 #include "check_circuit_library.h"
@@ -22,8 +25,8 @@ namespace openfpga {
  * The command will accept an option '--file' which is the architecture
  * file provided by users  
  *******************************************************************/
-void read_arch(OpenfpgaContext& openfpga_context,
-               const Command& cmd, const CommandContext& cmd_context) {
+int read_arch(OpenfpgaContext& openfpga_context,
+              const Command& cmd, const CommandContext& cmd_context) {
   /* Check the option '--file' is enabled or not 
    * Actually, it must be enabled as the shell interface will check 
    * before reaching this fuction
@@ -44,6 +47,9 @@ void read_arch(OpenfpgaContext& openfpga_context,
    * 3. Simulation settings (TODO)
    */
   check_circuit_library(openfpga_context.arch().circuit_lib);
+
+  /* TODO: should identify the error code from internal function execution */
+  return CMD_EXEC_SUCCESS;
 } 
 
 /********************************************************************
@@ -53,8 +59,8 @@ void read_arch(OpenfpgaContext& openfpga_context,
  * The command will accept an option '--file' which is the architecture
  * file provided by users  
  *******************************************************************/
-void write_arch(const OpenfpgaContext& openfpga_context,
-                const Command& cmd, const CommandContext& cmd_context) {
+int write_arch(const OpenfpgaContext& openfpga_context,
+               const Command& cmd, const CommandContext& cmd_context) {
   /* Check the option '--file' is enabled or not 
    * Actually, it must be enabled as the shell interface will check 
    * before reaching this fuction
@@ -68,6 +74,9 @@ void write_arch(const OpenfpgaContext& openfpga_context,
   VTR_LOG("Writing XML architecture to '%s'...\n",
           arch_file_name.c_str());
   write_xml_openfpga_arch(arch_file_name.c_str(), openfpga_context.arch());
+
+  /* TODO: should identify the error code from internal function execution */
+  return CMD_EXEC_SUCCESS;
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_read_arch.h b/openfpga/src/base/openfpga_read_arch.h
index dcc04d77a..b664a7b3e 100644
--- a/openfpga/src/base/openfpga_read_arch.h
+++ b/openfpga/src/base/openfpga_read_arch.h
@@ -15,11 +15,11 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-void read_arch(OpenfpgaContext& openfpga_context,
-               const Command& cmd, const CommandContext& cmd_context); 
+int read_arch(OpenfpgaContext& openfpga_context,
+              const Command& cmd, const CommandContext& cmd_context); 
 
-void write_arch(const OpenfpgaContext& openfpga_context,
-                const Command& cmd, const CommandContext& cmd_context);
+int write_arch(const OpenfpgaContext& openfpga_context,
+               const Command& cmd, const CommandContext& cmd_context);
 
 } /* end namespace openfpga */
 
diff --git a/openfpga/src/base/openfpga_repack.cpp b/openfpga/src/base/openfpga_repack.cpp
index 91c6b4798..fe0529d04 100644
--- a/openfpga/src/base/openfpga_repack.cpp
+++ b/openfpga/src/base/openfpga_repack.cpp
@@ -5,6 +5,9 @@
 #include "vtr_time.h"
 #include "vtr_log.h"
 
+/* Headers from openfpgashell library */
+#include "command_exit_codes.h"
+
 #include "build_physical_truth_table.h"
 #include "repack.h"
 #include "openfpga_repack.h"
@@ -18,8 +21,8 @@ namespace openfpga {
 /********************************************************************
  * A wrapper function to call the fabric_verilog function of FPGA-Verilog 
  *******************************************************************/
-void repack(OpenfpgaContext& openfpga_ctx,
-            const Command& cmd, const CommandContext& cmd_context) {
+int repack(OpenfpgaContext& openfpga_ctx,
+           const Command& cmd, const CommandContext& cmd_context) {
 
   CommandOptionId opt_verbose = cmd.option("verbose");
 
@@ -35,6 +38,9 @@ void repack(OpenfpgaContext& openfpga_ctx,
                                   g_vpr_ctx.clustering(),
                                   openfpga_ctx.vpr_device_annotation(),
                                   openfpga_ctx.arch().circuit_lib); 
+
+  /* TODO: should identify the error code from internal function execution */
+  return CMD_EXEC_SUCCESS;
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_repack.h b/openfpga/src/base/openfpga_repack.h
index 0fce62f78..83e4bce63 100644
--- a/openfpga/src/base/openfpga_repack.h
+++ b/openfpga/src/base/openfpga_repack.h
@@ -15,8 +15,8 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-void repack(OpenfpgaContext& openfpga_ctx,
-            const Command& cmd, const CommandContext& cmd_context); 
+int repack(OpenfpgaContext& openfpga_ctx,
+           const Command& cmd, const CommandContext& cmd_context); 
 
 } /* end namespace openfpga */
 
diff --git a/openfpga/src/base/openfpga_sdc.cpp b/openfpga/src/base/openfpga_sdc.cpp
index 06b594e73..21a3ab8fb 100644
--- a/openfpga/src/base/openfpga_sdc.cpp
+++ b/openfpga/src/base/openfpga_sdc.cpp
@@ -5,6 +5,9 @@
 #include "vtr_time.h"
 #include "vtr_log.h"
 
+/* Headers from openfpgashell library */
+#include "command_exit_codes.h"
+
 /* Headers from openfpgautil library */
 #include "openfpga_digest.h"
 
@@ -22,8 +25,8 @@ namespace openfpga {
 /********************************************************************
  * A wrapper function to call the PnR SDC generator of FPGA-SDC
  *******************************************************************/
-void write_pnr_sdc(OpenfpgaContext& openfpga_ctx,
-                   const Command& cmd, const CommandContext& cmd_context) {
+int write_pnr_sdc(OpenfpgaContext& openfpga_ctx,
+                  const Command& cmd, const CommandContext& cmd_context) {
 
   CommandOptionId opt_output_dir = cmd.option("file");
   CommandOptionId opt_constrain_global_port = cmd.option("constrain_global_port");
@@ -80,13 +83,16 @@ void write_pnr_sdc(OpenfpgaContext& openfpga_ctx,
                   global_ports,
                   openfpga_ctx.flow_manager().compress_routing());
   }
+
+  /* TODO: should identify the error code from internal function execution */
+  return CMD_EXEC_SUCCESS;
 } 
 
 /********************************************************************
  * A wrapper function to call the analysis SDC generator of FPGA-SDC
  *******************************************************************/
-void write_analysis_sdc(OpenfpgaContext& openfpga_ctx,
-                        const Command& cmd, const CommandContext& cmd_context) {
+int write_analysis_sdc(OpenfpgaContext& openfpga_ctx,
+                       const Command& cmd, const CommandContext& cmd_context) {
 
   CommandOptionId opt_output_dir = cmd.option("file");
 
@@ -114,6 +120,9 @@ void write_analysis_sdc(OpenfpgaContext& openfpga_ctx,
                        global_ports,
                        openfpga_ctx.flow_manager().compress_routing());
   }
+
+  /* TODO: should identify the error code from internal function execution */
+  return CMD_EXEC_SUCCESS;
 }
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_sdc.h b/openfpga/src/base/openfpga_sdc.h
index 110a8cd72..99a87f899 100644
--- a/openfpga/src/base/openfpga_sdc.h
+++ b/openfpga/src/base/openfpga_sdc.h
@@ -15,11 +15,11 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-void write_pnr_sdc(OpenfpgaContext& openfpga_ctx,
-                   const Command& cmd, const CommandContext& cmd_context); 
+int write_pnr_sdc(OpenfpgaContext& openfpga_ctx,
+                  const Command& cmd, const CommandContext& cmd_context); 
 
-void write_analysis_sdc(OpenfpgaContext& openfpga_ctx,
-                        const Command& cmd, const CommandContext& cmd_context);
+int write_analysis_sdc(OpenfpgaContext& openfpga_ctx,
+                       const Command& cmd, const CommandContext& cmd_context);
 
 } /* end namespace openfpga */
 
diff --git a/openfpga/src/base/openfpga_verilog.cpp b/openfpga/src/base/openfpga_verilog.cpp
index 1ce23a1d4..c79b68fc2 100644
--- a/openfpga/src/base/openfpga_verilog.cpp
+++ b/openfpga/src/base/openfpga_verilog.cpp
@@ -5,6 +5,9 @@
 #include "vtr_time.h"
 #include "vtr_log.h"
 
+/* Headers from openfpgashell library */
+#include "command_exit_codes.h"
+
 #include "verilog_api.h"
 #include "openfpga_verilog.h"
 
@@ -17,8 +20,8 @@ namespace openfpga {
 /********************************************************************
  * A wrapper function to call the fabric Verilog generator of FPGA-Verilog 
  *******************************************************************/
-void write_fabric_verilog(OpenfpgaContext& openfpga_ctx,
-                          const Command& cmd, const CommandContext& cmd_context) {
+int write_fabric_verilog(OpenfpgaContext& openfpga_ctx,
+                         const Command& cmd, const CommandContext& cmd_context) {
 
   CommandOptionId opt_output_dir = cmd.option("file");
   CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping");
@@ -48,13 +51,16 @@ void write_fabric_verilog(OpenfpgaContext& openfpga_ctx,
                       openfpga_ctx.vpr_device_annotation(),
                       openfpga_ctx.device_rr_gsb(),
                       options);
+
+  /* TODO: should identify the error code from internal function execution */
+  return CMD_EXEC_SUCCESS;
 } 
 
 /********************************************************************
  * A wrapper function to call the Verilog testbench generator of FPGA-Verilog 
  *******************************************************************/
-void write_verilog_testbench(OpenfpgaContext& openfpga_ctx,
-                             const Command& cmd, const CommandContext& cmd_context) {
+int write_verilog_testbench(OpenfpgaContext& openfpga_ctx,
+                            const Command& cmd, const CommandContext& cmd_context) {
 
   CommandOptionId opt_output_dir = cmd.option("file");
   CommandOptionId opt_reference_benchmark = cmd.option("reference_benchmark_file_path");
@@ -87,6 +93,9 @@ void write_verilog_testbench(OpenfpgaContext& openfpga_ctx,
                          openfpga_ctx.arch().sim_setting,
                          openfpga_ctx.arch().config_protocol.type(),
                          options);
+
+  /* TODO: should identify the error code from internal function execution */
+  return CMD_EXEC_SUCCESS;
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_verilog.h b/openfpga/src/base/openfpga_verilog.h
index faf8cf6b0..096039aab 100644
--- a/openfpga/src/base/openfpga_verilog.h
+++ b/openfpga/src/base/openfpga_verilog.h
@@ -15,11 +15,11 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-void write_fabric_verilog(OpenfpgaContext& openfpga_ctx,
-                          const Command& cmd, const CommandContext& cmd_context); 
+int write_fabric_verilog(OpenfpgaContext& openfpga_ctx,
+                         const Command& cmd, const CommandContext& cmd_context); 
 
-void write_verilog_testbench(OpenfpgaContext& openfpga_ctx,
-                             const Command& cmd, const CommandContext& cmd_context); 
+int write_verilog_testbench(OpenfpgaContext& openfpga_ctx,
+                            const Command& cmd, const CommandContext& cmd_context); 
 
 } /* end namespace openfpga */
 
diff --git a/openfpga/src/base/openfpga_write_gsb.cpp b/openfpga/src/base/openfpga_write_gsb.cpp
index 9c367ebfb..cdb833c75 100644
--- a/openfpga/src/base/openfpga_write_gsb.cpp
+++ b/openfpga/src/base/openfpga_write_gsb.cpp
@@ -5,6 +5,9 @@
 #include "vtr_time.h"
 #include "vtr_log.h"
 
+/* Headers from openfpgashell library */
+#include "command_exit_codes.h"
+
 #include "write_xml_device_rr_gsb.h"
 
 #include "openfpga_write_gsb.h"
@@ -19,8 +22,8 @@ namespace openfpga {
  * Write internal structrure of all the General Switch Blocks (GSBs)
  * to an XML file 
  *******************************************************************/
-void write_gsb(const OpenfpgaContext& openfpga_ctx,
-               const Command& cmd, const CommandContext& cmd_context) { 
+int write_gsb(const OpenfpgaContext& openfpga_ctx,
+              const Command& cmd, const CommandContext& cmd_context) { 
 
   /* Check the option '--file' is enabled or not 
    * Actually, it must be enabled as the shell interface will check 
@@ -38,6 +41,9 @@ void write_gsb(const OpenfpgaContext& openfpga_ctx,
                              g_vpr_ctx.device().rr_graph,
                              openfpga_ctx.device_rr_gsb(),
                              cmd_context.option_enable(cmd, opt_verbose));
+
+  /* TODO: should identify the error code from internal function execution */
+  return CMD_EXEC_SUCCESS;
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_write_gsb.h b/openfpga/src/base/openfpga_write_gsb.h
index 4f7110717..206e6cd5a 100644
--- a/openfpga/src/base/openfpga_write_gsb.h
+++ b/openfpga/src/base/openfpga_write_gsb.h
@@ -15,8 +15,8 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-void write_gsb(const OpenfpgaContext& openfpga_ctx,
-               const Command& cmd, const CommandContext& cmd_context); 
+int write_gsb(const OpenfpgaContext& openfpga_ctx,
+              const Command& cmd, const CommandContext& cmd_context); 
 
 } /* end namespace openfpga */
 

From e6c896d58312d1b7f2bcf9c518681d1e46b41a78 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 8 Apr 2020 16:54:08 -0600
Subject: [PATCH 409/645] now inout must be global port and I/O port so that it
 will appear in the top-level module

---
 .../libarchopenfpga/src/check_circuit_library.cpp | 12 ++++++++++++
 .../src/read_xml_circuit_library.cpp              |  4 +---
 openfpga/src/fabric/build_grid_modules.cpp        | 15 +++++----------
 openfpga/src/fpga_sdc/analysis_sdc_writer.cpp     |  6 ++++++
 openfpga/src/utils/module_manager_utils.cpp       | 12 ++++++++----
 .../test_openfpga_arch/k6_N10_40nm_openfpga.xml   |  2 +-
 .../k6_frac_N10_40nm_openfpga.xml                 |  2 +-
 .../k6_frac_N10_adder_chain_40nm_openfpga.xml     |  2 +-
 ..._frac_N10_adder_chain_mem16K_40nm_openfpga.xml |  2 +-
 ...c_N10_adder_chain_mem16K_aib_40nm_openfpga.xml |  4 ++--
 ..._frac_N10_adder_column_chain_40nm_openfpga.xml |  2 +-
 ...rac_N10_adder_register_chain_40nm_openfpga.xml |  2 +-
 ...10_adder_register_scan_chain_40nm_openfpga.xml |  2 +-
 .../k6_frac_N10_spyio_40nm_openfpga.xml           |  8 ++++----
 .../k6_frac_N10_stdcell_mux_40nm_openfpga.xml     |  2 +-
 .../k6_frac_N10_tree_mux_40nm_openfpga.xml        |  2 +-
 16 files changed, 47 insertions(+), 32 deletions(-)

diff --git a/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp b/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp
index 2e8c1a214..0abc16a0e 100644
--- a/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp
+++ b/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp
@@ -317,6 +317,18 @@ size_t check_circuit_library_ports(const CircuitLibrary& circuit_lib) {
     }
   }
 
+  /* Check global output ports: make sure they are all I/Os */
+  for (const auto& port : circuit_lib.ports()) {
+    if ( (circuit_lib.port_is_global(port)) 
+      && (CIRCUIT_MODEL_PORT_OUTPUT == circuit_lib.port_type(port))
+      && (false == circuit_lib.port_is_io(port)) ) {
+      VTR_LOG_ERROR("Circuit port (type=%s) of model (name=%s) is defined as global output port but not an I/O!\n",
+                    CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(circuit_lib.port_type(port))],
+                    circuit_lib.model_name(port).c_str());
+      num_err++;
+    }
+  }
+
   /* Check set/reset/config_enable ports: make sure they are all global ports */
   for (const auto& port : circuit_lib.ports()) {
     if ( ( (circuit_lib.port_is_set(port)) 
diff --git a/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp b/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp
index cd8ffd1c5..ba6e6af7f 100644
--- a/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp
+++ b/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp
@@ -489,9 +489,7 @@ void read_xml_circuit_port(pugi::xml_node& xml_port,
   /* Identify if the port is for io, this is only applicable to INPUT ports.
    * By default, it will NOT be a mode selection port
    */
-  if (CIRCUIT_MODEL_PORT_INPUT == circuit_lib.port_type(port)) {
-    circuit_lib.set_port_is_io(port, get_attribute(xml_port, "io", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false));
-  } 
+  circuit_lib.set_port_is_io(port, get_attribute(xml_port, "is_io", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false));
 
   /* Identify if the port is for mode selection, this is only applicable to SRAM ports.
    * By default, it will NOT be a mode selection port
diff --git a/openfpga/src/fabric/build_grid_modules.cpp b/openfpga/src/fabric/build_grid_modules.cpp
index 95e435f6f..0b693fcec 100644
--- a/openfpga/src/fabric/build_grid_modules.cpp
+++ b/openfpga/src/fabric/build_grid_modules.cpp
@@ -306,22 +306,17 @@ void build_primitive_block_module(ModuleManager& module_manager,
   /* Find the inout ports required by the primitive node, and add them to the module
    * This is mainly due to the I/O blocks, which have inout ports for the top-level fabric
    */
-  if (CIRCUIT_MODEL_IOPAD == circuit_lib.model_type(primitive_model)) {
-    std::vector<CircuitPortId> primitive_model_inout_ports = circuit_lib.model_ports_by_type(primitive_model, CIRCUIT_MODEL_PORT_INOUT);
-    for (auto port : primitive_model_inout_ports) {
+  for (const auto& port : circuit_lib.model_global_ports(primitive_model, false)) {
+    if ( (CIRCUIT_MODEL_PORT_INOUT == circuit_lib.port_type(port))
+      && (true == circuit_lib.port_is_io(port)) ) {
       add_primitive_module_fpga_global_io_port(module_manager, primitive_module,
                                                logic_module, logic_instance_id,
                                                ModuleManager::MODULE_GPIO_PORT,
                                                circuit_lib,
                                                primitive_model,
                                                port);
-    }
-  }
-
-  /* Find the other i/o ports required by the primitive node, and add them to the module */
-  for (const auto& port : circuit_lib.model_global_ports(primitive_model, false)) {
-    if ( (CIRCUIT_MODEL_PORT_INPUT == circuit_lib.port_type(port))
-      && (true == circuit_lib.port_is_io(port)) ) {
+    } else if ( (CIRCUIT_MODEL_PORT_INPUT == circuit_lib.port_type(port))
+             && (true == circuit_lib.port_is_io(port)) ) {
       add_primitive_module_fpga_global_io_port(module_manager, primitive_module,
                                                logic_module, logic_instance_id,
                                                ModuleManager::MODULE_GPIN_PORT,
diff --git a/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp b/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp
index c188dedd8..584f6e63f 100644
--- a/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp
+++ b/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp
@@ -203,6 +203,12 @@ void print_analysis_sdc_disable_global_ports(std::fstream& fp,
       continue;
     }
 
+    /* Skip any gpio port here! */
+    if ( (CIRCUIT_MODEL_PORT_INOUT == circuit_lib.port_type(global_port)) 
+      && (true == circuit_lib.port_is_io(global_port)) ) {
+      continue;
+    }
+
     ModulePortId module_port = module_manager.find_module_port(top_module, circuit_lib.port_prefix(global_port)); 
     BasicPort port_to_disable = module_manager.module_port(top_module, module_port);
 
diff --git a/openfpga/src/utils/module_manager_utils.cpp b/openfpga/src/utils/module_manager_utils.cpp
index 64bef2e88..a57e97261 100644
--- a/openfpga/src/utils/module_manager_utils.cpp
+++ b/openfpga/src/utils/module_manager_utils.cpp
@@ -37,8 +37,9 @@ ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager,
 
   /* Add ports */
   /* Find global ports and add one by one 
-   * Global input ports will be considered as global port in the context of module manager
-   * Global output ports will be considered as spy port in the context of module manager
+   * Non-I/O Global input ports will be considered as global port to be shorted wired in the context of module manager
+   * I/O Global output ports will be considered as general purpose output port in the context of module manager
+   * I/O Global inout ports will be considered as general purpose i/o port in the context of module manager
    */
   for (const auto& port : circuit_lib.model_global_ports(circuit_model, false)) {
     BasicPort port_info(circuit_lib.port_prefix(port), circuit_lib.port_size(port));
@@ -50,9 +51,12 @@ ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager,
     } else if ( (CIRCUIT_MODEL_PORT_INPUT == circuit_lib.port_type(port))
              && (true == circuit_lib.port_is_io(port)) ) {
       module_manager.add_port(module, port_info, ModuleManager::MODULE_GPIN_PORT);  
-    } else {
-      VTR_ASSERT(CIRCUIT_MODEL_PORT_OUTPUT == circuit_lib.port_type(port));
+    } else if (CIRCUIT_MODEL_PORT_OUTPUT == circuit_lib.port_type(port)) {
+      VTR_ASSERT(true == circuit_lib.port_is_io(port));
       module_manager.add_port(module, port_info, ModuleManager::MODULE_GPOUT_PORT);  
+    } else if ( (CIRCUIT_MODEL_PORT_INOUT == circuit_lib.port_type(port)) 
+             && (true == circuit_lib.port_is_io(port)) ) {
+      module_manager.add_port(module, port_info, ModuleManager::MODULE_GPIO_PORT);  
     }
   }
 
diff --git a/openfpga/test_openfpga_arch/k6_N10_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_N10_40nm_openfpga.xml
index 17eb8b550..de0602e1e 100644
--- a/openfpga/test_openfpga_arch/k6_N10_40nm_openfpga.xml
+++ b/openfpga/test_openfpga_arch/k6_N10_40nm_openfpga.xml
@@ -156,7 +156,7 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="inout" prefix="pad" size="1"/>
+      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
       <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
       <port type="input" prefix="outpad" size="1"/>
       <port type="output" prefix="inpad" size="1"/>
diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
index c43614ae8..51e250a8a 100644
--- a/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
@@ -173,7 +173,7 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="inout" prefix="pad" size="1"/>
+      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
       <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
       <port type="input" prefix="outpad" size="1"/>
       <port type="output" prefix="inpad" size="1"/>
diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
index cf619cd27..ae08c8250 100644
--- a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
@@ -174,7 +174,7 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="inout" prefix="pad" size="1"/>
+      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
       <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
       <port type="input" prefix="outpad" size="1"/>
       <port type="output" prefix="inpad" size="1"/>
diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
index 4ddf1dd0b..cb145e06d 100644
--- a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
@@ -174,7 +174,7 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="inout" prefix="pad" size="1"/>
+      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
       <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
       <port type="input" prefix="outpad" size="1"/>
       <port type="output" prefix="inpad" size="1"/>
diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
index f0e84e167..e65851291 100644
--- a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
@@ -174,7 +174,7 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="inout" prefix="pad" size="1"/>
+      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
       <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
       <port type="input" prefix="outpad" size="1"/>
       <port type="output" prefix="inpad" size="1"/>
@@ -209,7 +209,7 @@
       <port type="output" prefix="rx_data" size="80"/>
       <port type="clock" prefix="tx_clk" size="1" default_val="0"/>
       <port type="clock" prefix="rx_clk" size="1" default_val="0"/>
-      <port type="inout" prefix="pad" size="80"/>
+      <port type="inout" prefix="pad" size="80" is_global="true" is_io="true"/>
     </circuit_model>
   </circuit_library>
   <configuration_protocol>
diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml
index d70ebcb2d..65117d199 100644
--- a/openfpga/test_openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml
@@ -174,7 +174,7 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="inout" prefix="pad" size="1"/>
+      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
       <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
       <port type="input" prefix="outpad" size="1"/>
       <port type="output" prefix="inpad" size="1"/>
diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml
index 81a9582dc..779880dea 100644
--- a/openfpga/test_openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml
@@ -174,7 +174,7 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="inout" prefix="pad" size="1"/>
+      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
       <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
       <port type="input" prefix="outpad" size="1"/>
       <port type="output" prefix="inpad" size="1"/>
diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml
index 840a2e3bb..621847439 100644
--- a/openfpga/test_openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml
@@ -179,7 +179,7 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="inout" prefix="pad" size="1"/>
+      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
       <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
       <port type="input" prefix="outpad" size="1"/>
       <port type="output" prefix="inpad" size="1"/>
diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml
index 547c742c8..159214507 100644
--- a/openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml
@@ -173,11 +173,11 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="inout" prefix="pad" size="1"/>
+      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true" />
       <!-- A spypad for the direction port of the I/O pad, which can be visible in the fpga_top -->
-      <port type="input" prefix="din" size="1" is_global="true" io="true" default_value="0"/>
-      <port type="output" prefix="dout" size="1" is_global="true"/>
-      <port type="output" prefix="dir" size="1" is_global="true"/>
+      <port type="input" prefix="din" size="1" is_global="true" is_io="true" default_value="0"/>
+      <port type="output" prefix="dout" size="1" is_global="true" is_io="true"/>
+      <port type="output" prefix="dir" size="1" is_global="true" is_io="true"/>
       <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
       <port type="input" prefix="outpad" size="1"/>
       <port type="output" prefix="inpad" size="1"/>
diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml
index d3e3d1f6c..59f493a13 100644
--- a/openfpga/test_openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml
@@ -165,7 +165,7 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="inout" prefix="pad" size="1"/>
+      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
       <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
       <port type="input" prefix="outpad" size="1"/>
       <port type="output" prefix="inpad" size="1"/>
diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml
index 8052fb2dc..d04318510 100644
--- a/openfpga/test_openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml
@@ -164,7 +164,7 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="inout" prefix="pad" size="1"/>
+      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
       <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
       <port type="input" prefix="outpad" size="1"/>
       <port type="output" prefix="inpad" size="1"/>

From d99776b260ea94880573814d6279d8e4dd7436a0 Mon Sep 17 00:00:00 2001
From: Xifan Tang <tangxifan@gmail.com>
Date: Wed, 8 Apr 2020 18:18:53 -0600
Subject: [PATCH 410/645] update documentation on the global I/O ports

---
 docs/source/arch_lang/circuit_library.rst     | 112 +++++++++++++++++-
 .../arch_lang/figures/global_inout_ports.png  | Bin 0 -> 24210 bytes
 .../arch_lang/figures/global_input_ports.png  | Bin 0 -> 24062 bytes
 docs/source/arch_lang/figures/gpin_ports.png  | Bin 0 -> 24052 bytes
 docs/source/arch_lang/figures/gpio_ports.png  | Bin 0 -> 24674 bytes
 docs/source/arch_lang/figures/gpout_ports.png | Bin 0 -> 23998 bytes
 6 files changed, 111 insertions(+), 1 deletion(-)
 create mode 100644 docs/source/arch_lang/figures/global_inout_ports.png
 create mode 100644 docs/source/arch_lang/figures/global_input_ports.png
 create mode 100644 docs/source/arch_lang/figures/gpin_ports.png
 create mode 100644 docs/source/arch_lang/figures/gpio_ports.png
 create mode 100644 docs/source/arch_lang/figures/gpout_ports.png

diff --git a/docs/source/arch_lang/circuit_library.rst b/docs/source/arch_lang/circuit_library.rst
index 2cab83abd..bf32fc113 100644
--- a/docs/source/arch_lang/circuit_library.rst
+++ b/docs/source/arch_lang/circuit_library.rst
@@ -272,7 +272,7 @@ A circuit model may consist of a number of ports. The port list is mandatory in
 
   - ``io="true|false"`` Specify if this port should be treated as an I/O port of an FPGA fabric. When this is enabled, this port of each circuit model instanciated in FPGA will be added as an I/O of an FPGA.
 
-    .. note:: ``io`` is only valid for ``input`` ports
+    .. note:: global ``output`` ports must be ``io`` ports
 
   - ``mode_select="true|false"`` Specify if this port controls the mode switching in a configurable logic block. This is due to that a configurable logic block can operate in different modes, which is controlled by SRAM bits.
 
@@ -296,3 +296,113 @@ A circuit model may consist of a number of ports. The port list is mandatory in
 .. note::  Different types of ``circuit_model`` have different XML syntax, with which users can highly customize their circuit topologies. See refer to examples of :ref:``circuit_model_example`` for more details.
 
 .. note:: Note that we have a list of reserved port names, which indicate the usage of these ports when building FPGA fabrics. Please do not use ``mem_out``, ``mem_inv``, ``bl``, ``wl``, ``blb``, ``wlb``, ``ccff_head`` and ``ccff_tail``.
+
+FPGA I/O Port 
+^^^^^^^^^^^^^
+
+The ``circuit_model`` support not only highly customizable circuit-level modeling but also flexible I/O connection in the FPGA fabric.
+Typically, circuit ports appear in the primitive modules of a FPGA fabric.
+However, it is also very common that some circuit ports should be I/O of a FPGA fabric.
+Using syntax ``is_global`` and ``is_io``, users can freely define how these ports are connected as FPGA I/Os.
+
+In principle, when ``is_global`` is set ``true``, the port will appear as an FPGA I/O.
+The syntax ``is_io`` is applicable when ``is_global`` is ``true``.
+When ``is_io`` is ``true``, the port from different instances will be treated as independent I/Os.
+When ``is_io`` is ``false``, the port from different instances will be treated as the same I/Os, which are short-wired.
+
+To beef up, the following examples will explain how to use ``is_global`` and ``is_io`` to achieve different types of connections to FPGA I/Os.
+
+.. option:: Global short-wired inputs
+
+.. code-block:: xml
+
+  <port type="input" is_global="true" is_io="false"/>
+
+The global inputs are short wired across different instances. 
+These inputs are widely seen in FPGAs, such as clock ports, which are shared between sequential elements. 
+
+:numref:`fig_global_input_ports` shows an example on how the global inputs are wired inside FPGA fabric.
+
+.. _fig_global_input_ports:
+
+.. figure:: ./figures/global_input_ports.png
+   :scale: 100%
+   :alt: classical inverter 1x symbol
+
+   Short-wired global inputs as an FPGA I/O
+
+.. option:: Global short-wired inouts
+
+.. code-block:: xml
+
+  <port type="inout" is_global="true" is_io="false"/>
+
+The global inouts are short wired across different instances. 
+
+:numref:`fig_global_ioput_ports` shows an example on how the global inouts are wired inside FPGA fabric.
+
+.. _fig_global_inout_ports:
+
+.. figure:: ./figures/global_inout_ports.png
+   :scale: 100%
+   :alt: classical inverter 1x symbol
+
+   Short-wired global inouts as an FPGA I/O
+
+.. option:: General-purpose inputs
+
+.. code-block:: xml
+
+  <port type="input" is_global="true" is_io="true"/>
+
+The general-purpose inputs are independent wired from different instances to separated FPGA I/Os.
+For example, power-gating signals can be applied to each tile of a FPGA.
+
+:numref:`fig_gpin_ports` shows an example on how the general-purpose inputs are wired inside FPGA fabric.
+
+.. _fig_gpin_ports:
+
+.. figure:: ./figures/gpin_ports.png
+   :scale: 100%
+   :alt: classical inverter 1x symbol
+
+   General-purpose inputs as separated FPGA I/Os
+
+.. option:: General-purpose I/O
+
+.. code-block:: xml
+
+  <port type="inout" is_global="true" is_io="true"/>
+
+The general-purpose I/O are independent wired from different instances to separated FPGA I/Os.
+In practice, inout of GPIO cell is typically wired like this.
+
+:numref:`fig_gpin_ports` shows an example on how the general-purpose inouts are wired inside FPGA fabric.
+
+.. _fig_gpio_ports:
+
+.. figure:: ./figures/gpio_ports.png
+   :scale: 100%
+   :alt: classical inverter 1x symbol
+
+   General-purpose inouts as separated FPGA I/Os
+
+.. option:: General-purpose outputs
+
+.. code-block:: xml
+
+  <port type="output" is_global="true" is_io="true"/>
+
+The general-purpose outputs are independent wired from different instances to separated FPGA outputs.
+In practice, these outputs are typically spypads to probe internal signals of a FPGA.
+
+:numref:`fig_gpout_ports` shows an example on how the general-purpose outputs are wired inside FPGA fabric.
+
+.. _fig_gpout_ports:
+
+.. figure:: ./figures/gpout_ports.png
+   :scale: 100%
+   :alt: classical inverter 1x symbol
+
+   General-purpose outputs as separated FPGA I/Os
+
diff --git a/docs/source/arch_lang/figures/global_inout_ports.png b/docs/source/arch_lang/figures/global_inout_ports.png
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diff --git a/docs/source/arch_lang/figures/gpio_ports.png b/docs/source/arch_lang/figures/gpio_ports.png
new file mode 100644
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HcmV?d00001


From 8ea272dc2c51466772f52873fa6111a71af2002c Mon Sep 17 00:00:00 2001
From: ganeshgore <goreganesh007@gmail.com>
Date: Wed, 8 Apr 2020 21:28:14 -0600
Subject: [PATCH 411/645] Patched the OpenFPGA shell execution bug

---
 openfpga_flow/scripts/run_fpga_flow.py | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py
index 434163410..d0bbd6dd0 100644
--- a/openfpga_flow/scripts/run_fpga_flow.py
+++ b/openfpga_flow/scripts/run_fpga_flow.py
@@ -667,6 +667,7 @@ def run_vpr():
 
 
 def run_openfpga_shell():
+    ExecTime["VPRStart"] = time.time()
     # bench_blif, fixed_chan_width, logfile, route_only=False
     tmpl = Template(open(args.top_module+"_template.openfpga",
                          encoding='utf-8').read())
@@ -683,6 +684,8 @@ def run_openfpga_shell():
     command = [cad_tools["openfpga_shell_path"], "-f",
                args.top_module+"_run.openfpga"]
     run_command("OpenFPGA Shell Run", "openfpgashell.log", command)
+    ExecTime["VPREnd"] = time.time()
+    extract_vpr_stats("vpr_stdout.log")
 
 
 def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False):

From b4542ea34b0b09338ca15bd368f023583ac4030c Mon Sep 17 00:00:00 2001
From: Xifan Tang <tangxifan@gmail.com>
Date: Thu, 9 Apr 2020 17:10:04 -0600
Subject: [PATCH 412/645] minor fix on doc about the global and general purpose
 port

---
 docs/source/arch_lang/circuit_library.rst     |   4 ++++
 .../arch_lang/figures/global_inout_ports.png  | Bin 24210 -> 16240 bytes
 .../arch_lang/figures/global_input_ports.png  | Bin 24062 -> 16035 bytes
 docs/source/arch_lang/figures/gpin_ports.png  | Bin 24052 -> 16129 bytes
 docs/source/arch_lang/figures/gpio_ports.png  | Bin 24674 -> 16474 bytes
 docs/source/arch_lang/figures/gpout_ports.png | Bin 23998 -> 16042 bytes
 6 files changed, 4 insertions(+)

diff --git a/docs/source/arch_lang/circuit_library.rst b/docs/source/arch_lang/circuit_library.rst
index bf32fc113..cde9b5fbc 100644
--- a/docs/source/arch_lang/circuit_library.rst
+++ b/docs/source/arch_lang/circuit_library.rst
@@ -406,3 +406,7 @@ In practice, these outputs are typically spypads to probe internal signals of a
 
    General-purpose outputs as separated FPGA I/Os
 
+
+.. warning:: The general-purpose inputs/inouts/outputs are not applicable to routing multiplexer outputs
+
+
diff --git a/docs/source/arch_lang/figures/global_inout_ports.png b/docs/source/arch_lang/figures/global_inout_ports.png
index 9dd7d2b8966d9de5291c8fcd93fa2e81f4506ba8..090952714e04eefdb211fbc1b63ddb3d460dff4b 100644
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diff --git a/docs/source/arch_lang/figures/gpio_ports.png b/docs/source/arch_lang/figures/gpio_ports.png
index 4b0362c7b786e282cedf14344864ebad72b37635..d42d2741585b0cb8a78a8cbb0540b879a7485979 100644
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From f6b3c5854ac6bbce93014cb84cd0f29c6f990d1b Mon Sep 17 00:00:00 2001
From: ganeshgore <goreganesh007@gmail.com>
Date: Sat, 11 Apr 2020 16:45:22 -0600
Subject: [PATCH 413/645] Bugfix : + OpenFPGA template variables update +
 Default path for the verilog netlist

---
 .../OpenFPGAShellScripts/example_script.openfpga     | 11 +++++++----
 openfpga_flow/scripts/run_fpga_flow.py               | 12 ++++++++++--
 .../tasks/OpenFPGAShell_Example/config/task.conf     |  2 +-
 3 files changed, 18 insertions(+), 7 deletions(-)

diff --git a/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
index 5a79a3910..f584f39d8 100644
--- a/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
@@ -37,7 +37,7 @@ build_fabric_bitstream --verbose
 
 # Write the Verilog netlist for FPGA fabric
 #  - Enable the use of explicit port mapping in Verilog netlist
-write_fabric_verilog --file ./VerilogNetlist/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
+write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
 
 # Write the Verilog testbench for FPGA fabric
 #  - We suggest the use of same output directory as fabric Verilog netlists
@@ -45,14 +45,17 @@ write_fabric_verilog --file ./VerilogNetlist/SRC --explicit_port_mapping --inclu
 #  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_verilog_testbench --file ./VerilogNetlist/SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini
+write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini
 
 # Write the SDC files for PnR backend
 #  - Turn on every options here
-write_pnr_sdc --file ./VerilogNetlist/SDC
+write_pnr_sdc --file ./SDC
 
 # Write the SDC to run timing analysis for a mapped FPGA fabric
-write_analysis_sdc --file ./VerilogNetlist/SDC_analysis
+write_analysis_sdc --file ./SDC_analysis
 
 # Finish and exit OpenFPGA
 exit
+
+# Note :
+# To run verification at the end of the flow maintain source in ./SRC directory
\ No newline at end of file
diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py
index d0bbd6dd0..4c90f6f7c 100644
--- a/openfpga_flow/scripts/run_fpga_flow.py
+++ b/openfpga_flow/scripts/run_fpga_flow.py
@@ -398,7 +398,7 @@ def prepare_run_directory(run_dir):
     # Clean run_dir is created change working directory
     os.chdir(run_dir)
 
-    # Create arch dir in run_dir and copy flattern architecrture file
+    # Create arch dir in run_dir and copy flattened architecture file
     os.mkdir("arch")
     tmpl = Template(
         open(args.arch_file, encoding='utf-8').read())
@@ -407,7 +407,15 @@ def prepare_run_directory(run_dir):
     with open(args.arch_file, 'w', encoding='utf-8') as archfile:
         archfile.write(tmpl.substitute(script_env_vars["PATH"]))
 
-    # Create benchmark dir in run_dir and copy flattern architecrture file
+    if (args.openfpga_arch_file):
+        tmpl = Template(
+            open(args.openfpga_arch_file, encoding='utf-8').read())
+        arch_filename = os.path.basename(args.openfpga_arch_file)
+        args.openfpga_arch_file = os.path.join(run_dir, "arch", arch_filename)
+        with open(args.openfpga_arch_file, 'w', encoding='utf-8') as archfile:
+            archfile.write(tmpl.substitute(script_env_vars["PATH"]))
+
+    # Create benchmark dir in run_dir and copy flattern architecture file
     os.mkdir("benchmark")
     try:
         for index, eachfile in enumerate(args.benchmark_files):
diff --git a/openfpga_flow/tasks/OpenFPGAShell_Example/config/task.conf b/openfpga_flow/tasks/OpenFPGAShell_Example/config/task.conf
index 54d8e8a4a..9247493e1 100644
--- a/openfpga_flow/tasks/OpenFPGAShell_Example/config/task.conf
+++ b/openfpga_flow/tasks/OpenFPGAShell_Example/config/task.conf
@@ -30,4 +30,4 @@ bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
-min_route_chan_width=1.3
\ No newline at end of file
+end_flow_with_test=
\ No newline at end of file

From 130b78ca74f305db727b6c43ffd9533e355b93bc Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 11 Apr 2020 18:00:37 -0600
Subject: [PATCH 414/645] update arch in openfpga_flow

---
 .../openfpga_arch/k6_N10_40nm_openfpga.xml    |  8 +--
 .../k6_frac_N10_40nm_openfpga.xml             | 54 ++++++++-----------
 .../k6_frac_N10_adder_chain_40nm_openfpga.xml |  9 +---
 ...c_N10_adder_chain_mem16K_40nm_openfpga.xml | 10 +---
 ...0_adder_chain_mem16K_aib_40nm_openfpga.xml | 13 +----
 .../k6_frac_N10_spyio_40nm_openfpga.xml       | 14 ++---
 .../OpenFPGAShell_Example/config/task.conf    |  2 +-
 7 files changed, 33 insertions(+), 77 deletions(-)

diff --git a/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml
index d93495f6b..de0602e1e 100644
--- a/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml
@@ -96,7 +96,6 @@
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -106,7 +105,6 @@
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -116,7 +114,6 @@
       <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -127,7 +124,6 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <pass_gate_logic circuit_model_name="TGATE"/>
        <port type="input" prefix="D" size="1"/>
        <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
        <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
@@ -150,7 +146,6 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <pass_gate_logic circuit_model_name="TGATE"/>
        <port type="input" prefix="pReset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
        <port type="input" prefix="D" size="1"/>
        <port type="output" prefix="Q" size="1"/>
@@ -161,8 +156,7 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
-      <port type="inout" prefix="pad" size="1"/>
+      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
       <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
       <port type="input" prefix="outpad" size="1"/>
       <port type="output" prefix="inpad" size="1"/>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
index afb45dc1f..51e250a8a 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
@@ -1,5 +1,5 @@
 <!-- Architecture annotation for OpenFPGA framework
-     This annotation supports the k6_N10_40nm.xml
+     This annotation supports the k6_N10_40nm.xml 
      - General purpose logic block
        - K = 6, N = 10, I = 40
        - Single mode
@@ -96,8 +96,7 @@
       <output_buffer exist="false"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
-      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
-      <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
     </circuit_model>
     <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
       <design_technology type="cmos"/>
@@ -105,14 +104,12 @@
       <output_buffer exist="false"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
-      <wire_param model_type="pi" R="0" C="0" num_level="1"/>
-      <!-- model_type could be T, res_val cap_val should be defined -->
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
     </circuit_model>
     <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -122,7 +119,6 @@
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -132,7 +128,6 @@
       <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -140,15 +135,14 @@
     </circuit_model>
     <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
     <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
-      <design_technology type="cmos"/>
-      <input_buffer exist="true" circuit_model_name="INVTX1"/>
-      <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
-      <port type="input" prefix="D" size="1"/>
-      <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
-      <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
-      <port type="output" prefix="Q" size="1"/>
-      <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
     </circuit_model>
     <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
       <design_technology type="cmos" fracturable_lut="true"/>
@@ -166,22 +160,20 @@
     </circuit_model>
     <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
     <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
-      <design_technology type="cmos"/>
-      <input_buffer exist="true" circuit_model_name="INVTX1"/>
-      <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
-      <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
-      <port type="input" prefix="D" size="1"/>
-      <port type="output" prefix="Q" size="1"/>
-      <port type="output" prefix="Qb" size="1"/>
-      <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="Qb" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
     </circuit_model>
     <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
-      <port type="inout" prefix="pad" size="1"/>
+      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
       <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
       <port type="input" prefix="outpad" size="1"/>
       <port type="output" prefix="inpad" size="1"/>
@@ -202,9 +194,9 @@
   <pb_type_annotations>
     <!-- physical pb_type binding in complex block IO -->
     <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
-    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/>
-    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
-    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
     <!-- End physical pb_type binding in complex block IO -->
 
     <!-- physical pb_type binding in complex block CLB -->
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
index 98823698f..ae08c8250 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
@@ -110,7 +110,6 @@
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -120,7 +119,6 @@
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -130,7 +128,6 @@
       <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -141,7 +138,6 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <pass_gate_logic circuit_model_name="TGATE"/>
        <port type="input" prefix="D" size="1"/>
        <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
        <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
@@ -168,7 +164,6 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <pass_gate_logic circuit_model_name="TGATE"/>
        <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
        <port type="input" prefix="D" size="1"/>
        <port type="output" prefix="Q" size="1"/>
@@ -179,8 +174,7 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
-      <port type="inout" prefix="pad" size="1"/>
+      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
       <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
       <port type="input" prefix="outpad" size="1"/>
       <port type="output" prefix="inpad" size="1"/>
@@ -189,7 +183,6 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="a" size="1"/>
       <port type="input" prefix="b" size="1"/>
       <port type="input" prefix="cin" size="1"/>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
index 9f37c1293..cb145e06d 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
@@ -110,7 +110,6 @@
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -120,7 +119,6 @@
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -130,7 +128,6 @@
       <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -141,7 +138,6 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <pass_gate_logic circuit_model_name="TGATE"/>
        <port type="input" prefix="D" size="1"/>
        <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
        <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
@@ -168,7 +164,6 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <pass_gate_logic circuit_model_name="TGATE"/>
        <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
        <port type="input" prefix="D" size="1"/>
        <port type="output" prefix="Q" size="1"/>
@@ -179,8 +174,7 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
-      <port type="inout" prefix="pad" size="1"/>
+      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
       <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
       <port type="input" prefix="outpad" size="1"/>
       <port type="output" prefix="inpad" size="1"/>
@@ -189,7 +183,6 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="a" size="1"/>
       <port type="input" prefix="b" size="1"/>
       <port type="input" prefix="cin" size="1"/>
@@ -200,7 +193,6 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="waddr" size="10"/>
       <port type="input" prefix="raddr" size="10"/>
       <port type="input" prefix="d_in" size="32"/>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
index ea56fe036..e65851291 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
@@ -110,7 +110,6 @@
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -120,7 +119,6 @@
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -130,7 +128,6 @@
       <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -141,7 +138,6 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <pass_gate_logic circuit_model_name="TGATE"/>
        <port type="input" prefix="D" size="1"/>
        <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
        <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
@@ -168,7 +164,6 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <pass_gate_logic circuit_model_name="TGATE"/>
        <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
        <port type="input" prefix="D" size="1"/>
        <port type="output" prefix="Q" size="1"/>
@@ -179,8 +174,7 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
-      <port type="inout" prefix="pad" size="1"/>
+      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
       <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
       <port type="input" prefix="outpad" size="1"/>
       <port type="output" prefix="inpad" size="1"/>
@@ -189,7 +183,6 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="a" size="1"/>
       <port type="input" prefix="b" size="1"/>
       <port type="input" prefix="cin" size="1"/>
@@ -200,7 +193,6 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="waddr" size="10"/>
       <port type="input" prefix="raddr" size="10"/>
       <port type="input" prefix="d_in" size="32"/>
@@ -213,12 +205,11 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="tx_data" size="80"/>
       <port type="output" prefix="rx_data" size="80"/>
       <port type="clock" prefix="tx_clk" size="1" default_val="0"/>
       <port type="clock" prefix="rx_clk" size="1" default_val="0"/>
-      <port type="inout" prefix="pad" size="80"/>
+      <port type="inout" prefix="pad" size="80" is_global="true" is_io="true"/>
     </circuit_model>
   </circuit_library>
   <configuration_protocol>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml
index 2b432ce86..159214507 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml
@@ -110,7 +110,6 @@
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -120,7 +119,6 @@
       <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -130,7 +128,6 @@
       <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <!--mux2to1 subckt_name="mux2to1"/-->
       <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -141,7 +138,6 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <pass_gate_logic circuit_model_name="TGATE"/>
        <port type="input" prefix="D" size="1"/>
        <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
        <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
@@ -167,7 +163,6 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <pass_gate_logic circuit_model_name="TGATE"/>
        <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
        <port type="input" prefix="D" size="1"/>
        <port type="output" prefix="Q" size="1"/>
@@ -178,12 +173,11 @@
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
-      <port type="inout" prefix="pad" size="1"/>
+      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true" />
       <!-- A spypad for the direction port of the I/O pad, which can be visible in the fpga_top -->
-      <port type="input" prefix="din" size="1" is_global="true" io="true" default_value="0"/>
-      <port type="output" prefix="dout" size="1" is_global="true"/>
-      <port type="output" prefix="dir" size="1" is_global="true"/>
+      <port type="input" prefix="din" size="1" is_global="true" is_io="true" default_value="0"/>
+      <port type="output" prefix="dout" size="1" is_global="true" is_io="true"/>
+      <port type="output" prefix="dir" size="1" is_global="true" is_io="true"/>
       <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
       <port type="input" prefix="outpad" size="1"/>
       <port type="output" prefix="inpad" size="1"/>
diff --git a/openfpga_flow/tasks/OpenFPGAShell_Example/config/task.conf b/openfpga_flow/tasks/OpenFPGAShell_Example/config/task.conf
index 9247493e1..f06ae2589 100644
--- a/openfpga_flow/tasks/OpenFPGAShell_Example/config/task.conf
+++ b/openfpga_flow/tasks/OpenFPGAShell_Example/config/task.conf
@@ -30,4 +30,4 @@ bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
-end_flow_with_test=
\ No newline at end of file
+end_flow_with_test=

From 49ddbf98c355d4327ac4b2a61c24ddc963ee213e Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 11 Apr 2020 18:01:09 -0600
Subject: [PATCH 415/645] add more testing architecture to openfpga_flow

---
 ...c_N10_adder_column_chain_40nm_openfpga.xml | 285 +++++++++++++++++
 ...N10_adder_register_chain_40nm_openfpga.xml | 288 +++++++++++++++++
 ...dder_register_scan_chain_40nm_openfpga.xml | 294 ++++++++++++++++++
 .../k6_frac_N10_stdcell_mux_40nm_openfpga.xml | 252 +++++++++++++++
 .../k6_frac_N10_tree_mux_40nm_openfpga.xml    | 251 +++++++++++++++
 5 files changed, 1370 insertions(+)
 create mode 100644 openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml
 create mode 100644 openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml
 create mode 100644 openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml
 create mode 100644 openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml
 create mode 100644 openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml

diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml
new file mode 100644
index 000000000..65117d199
--- /dev/null
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml
@@ -0,0 +1,285 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
+      <design_technology type="cmos" topology="OR"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
+      <design_technology type="cmos" fracturable_lut="true"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="6" tri_state_map="----11" circuit_model_name="OR2"/>
+      <port type="output" prefix="lut4_out" size="4" lut_frac_level="4" lut_output_mask="0,1,2,3"/>
+      <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
+      <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
+      <port type="sram" prefix="sram" size="64"/>
+      <port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="Qb" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+      <port type="input" prefix="outpad" size="1"/>
+      <port type="output" prefix="inpad" size="1"/>
+    </circuit_model>
+    <circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="input" prefix="cin" size="1"/>
+      <port type="output" prefix="sumout" size="1"/>
+      <port type="output" prefix="cout" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <direct_connection>
+    <direct name="adder_carry" circuit_model_name="direct_interc"/>
+  </direct_connection>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle" physical_mode_name="physical"/>
+    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
+    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
+    <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="adder"/>
+    <!-- Binding operating pb_type to physical pb_type -->
+    <!-- Binding operating pb_types in mode 'n2_lut5' -->
+    <pb_type name="clb.fle[n2_lut5].ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5">
+      <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:4]"/>
+      <port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[n2_lut5].ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <!-- Binding operating pb_types in mode 'arithmetic' -->
+    <pb_type name="clb.fle[arithmetic].arithmetic.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="11" physical_pb_type_index_factor="0.25">
+      <!-- Binding the lut4 to the first 4 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:3]"/>
+      <port name="out" physical_mode_port="lut4_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[arithmetic].arithmetic.adder" physical_pb_type_name="clb.fle[physical].fabric.adder"/>
+    <pb_type name="clb.fle[arithmetic].arithmetic.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <!-- Binding operating pb_types in mode 'ble6' -->
+    <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="00">
+      <!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:5]"/>
+      <port name="out" physical_mode_port="lut6_out"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>
+<openfpga_simulation_setting>
+  <clock_setting>
+    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
+    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
+    <programming frequency="10e6"/>
+  </clock_setting>
+  <simulator_option>
+    <operating_condition temperature="25"/>
+    <output_log verbose="false" captab="false"/>
+    <accuracy type="abs" value="1e-13"/>
+    <runtime fast_simulation="true"/>
+  </simulator_option>
+  <monte_carlo num_simulation_points="2"/>
+  <measurement_setting>
+    <slew>
+      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
+      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
+    </slew>
+    <delay>
+      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
+      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
+    </delay>
+  </measurement_setting>
+  <stimulus>
+    <clock>
+      <rise slew_type="abs" slew_time="20e-12" />
+      <fall slew_type="abs" slew_time="20e-12" />
+    </clock>
+    <input>
+      <rise slew_type="abs" slew_time="25e-12" />
+      <fall slew_type="abs" slew_time="25e-12" />
+    </input>
+  </stimulus>
+</openfpga_simulation_setting>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml
new file mode 100644
index 000000000..779880dea
--- /dev/null
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml
@@ -0,0 +1,288 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
+      <design_technology type="cmos" topology="OR"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
+      <design_technology type="cmos" fracturable_lut="true"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="6" tri_state_map="----11" circuit_model_name="OR2"/>
+      <port type="output" prefix="lut4_out" size="4" lut_frac_level="4" lut_output_mask="0,1,2,3"/>
+      <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
+      <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
+      <port type="sram" prefix="sram" size="64"/>
+      <port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="Qb" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+      <port type="input" prefix="outpad" size="1"/>
+      <port type="output" prefix="inpad" size="1"/>
+    </circuit_model>
+    <circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="input" prefix="cin" size="1"/>
+      <port type="output" prefix="sumout" size="1"/>
+      <port type="output" prefix="cout" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <direct_connection>
+    <direct name="adder_carry" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
+    <direct name="shift_register" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
+  </direct_connection>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle" physical_mode_name="physical"/>
+    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
+    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
+    <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="adder"/>
+    <!-- Binding operating pb_type to physical pb_type -->
+    <!-- Binding operating pb_types in mode 'n2_lut5' -->
+    <pb_type name="clb.fle[n2_lut5].ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5">
+      <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:4]"/>
+      <port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[n2_lut5].ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <!-- Binding operating pb_types in mode 'arithmetic' -->
+    <pb_type name="clb.fle[arithmetic].arithmetic.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="11" physical_pb_type_index_factor="0.25">
+      <!-- Binding the lut4 to the first 4 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:3]"/>
+      <port name="out" physical_mode_port="lut4_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[arithmetic].arithmetic.adder" physical_pb_type_name="clb.fle[physical].fabric.adder"/>
+    <pb_type name="clb.fle[arithmetic].arithmetic.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <!-- Binding operating pb_types in mode 'ble6' -->
+    <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="00">
+      <!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:5]"/>
+      <port name="out" physical_mode_port="lut6_out"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
+    <!-- Binding operating pb_types in mode 'shift_register' -->
+    <pb_type name="clb.fle[shift_register].shift_reg.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>
+<openfpga_simulation_setting>
+  <clock_setting>
+    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
+    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
+    <programming frequency="10e6"/>
+  </clock_setting>
+  <simulator_option>
+    <operating_condition temperature="25"/>
+    <output_log verbose="false" captab="false"/>
+    <accuracy type="abs" value="1e-13"/>
+    <runtime fast_simulation="true"/>
+  </simulator_option>
+  <monte_carlo num_simulation_points="2"/>
+  <measurement_setting>
+    <slew>
+      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
+      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
+    </slew>
+    <delay>
+      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
+      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
+    </delay>
+  </measurement_setting>
+  <stimulus>
+    <clock>
+      <rise slew_type="abs" slew_time="20e-12" />
+      <fall slew_type="abs" slew_time="20e-12" />
+    </clock>
+    <input>
+      <rise slew_type="abs" slew_time="25e-12" />
+      <fall slew_type="abs" slew_time="25e-12" />
+    </input>
+  </stimulus>
+</openfpga_simulation_setting>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml
new file mode 100644
index 000000000..621847439
--- /dev/null
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml
@@ -0,0 +1,294 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
+      <design_technology type="cmos" topology="OR"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> 
+        This is flip-flop with scan-chain feature.
+        When the TESTEN is enabled, the data will be propagated form DI instead of D
+      -->
+    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="DI" size="1"/>
+       <port type="input" prefix="TESTEN" size="1" is_global="true" default_val="0"/>
+       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
+      <design_technology type="cmos" fracturable_lut="true"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="6" tri_state_map="----11" circuit_model_name="OR2"/>
+      <port type="output" prefix="lut4_out" size="4" lut_frac_level="4" lut_output_mask="0,1,2,3"/>
+      <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
+      <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
+      <port type="sram" prefix="sram" size="64"/>
+      <port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="Qb" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+      <port type="input" prefix="outpad" size="1"/>
+      <port type="output" prefix="inpad" size="1"/>
+    </circuit_model>
+    <circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="input" prefix="cin" size="1"/>
+      <port type="output" prefix="sumout" size="1"/>
+      <port type="output" prefix="cout" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <direct_connection>
+    <direct name="adder_carry" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
+    <direct name="shift_register" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
+    <direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
+  </direct_connection>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle" physical_mode_name="physical"/>
+    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
+    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
+    <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="adder"/>
+    <!-- Binding operating pb_type to physical pb_type -->
+    <!-- Binding operating pb_types in mode 'n2_lut5' -->
+    <pb_type name="clb.fle[n2_lut5].ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5">
+      <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:4]"/>
+      <port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[n2_lut5].ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <!-- Binding operating pb_types in mode 'arithmetic' -->
+    <pb_type name="clb.fle[arithmetic].arithmetic.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="11" physical_pb_type_index_factor="0.25">
+      <!-- Binding the lut4 to the first 4 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:3]"/>
+      <port name="out" physical_mode_port="lut4_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[arithmetic].arithmetic.adder" physical_pb_type_name="clb.fle[physical].fabric.adder"/>
+    <pb_type name="clb.fle[arithmetic].arithmetic.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <!-- Binding operating pb_types in mode 'ble6' -->
+    <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="00">
+      <!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:5]"/>
+      <port name="out" physical_mode_port="lut6_out"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
+    <!-- Binding operating pb_types in mode 'shift_register' -->
+    <pb_type name="clb.fle[shift_register].shift_reg.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>
+<openfpga_simulation_setting>
+  <clock_setting>
+    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
+    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
+    <programming frequency="10e6"/>
+  </clock_setting>
+  <simulator_option>
+    <operating_condition temperature="25"/>
+    <output_log verbose="false" captab="false"/>
+    <accuracy type="abs" value="1e-13"/>
+    <runtime fast_simulation="true"/>
+  </simulator_option>
+  <monte_carlo num_simulation_points="2"/>
+  <measurement_setting>
+    <slew>
+      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
+      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
+    </slew>
+    <delay>
+      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
+      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
+    </delay>
+  </measurement_setting>
+  <stimulus>
+    <clock>
+      <rise slew_type="abs" slew_time="20e-12" />
+      <fall slew_type="abs" slew_time="20e-12" />
+    </clock>
+    <input>
+      <rise slew_type="abs" slew_time="25e-12" />
+      <fall slew_type="abs" slew_time="25e-12" />
+    </input>
+  </stimulus>
+</openfpga_simulation_setting>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml
new file mode 100644
index 000000000..59f493a13
--- /dev/null
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml
@@ -0,0 +1,252 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
+      <design_technology type="cmos" topology="OR"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <!-- Define a circuit model for the standard cell MUX2 
+         OpenFPGA requires the following truth table for the MUX2
+         When the select signal sel is enabled, the first input, i.e., in0 
+         will be propagated to the output, i.e., out
+         If your standard cell provider does not offer the exact truth table,
+         you can simply swap the inputs as shown in the example below
+      -->
+    <circuit_model type="gate" name="stdcell_mux2" prefix="stdcell_mux2" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/sc_mux2.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/sc_mux2.v">
+      <design_technology type="cmos" topology="MUX2"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in0" lib_name="B" size="1"/>
+      <port type="input" prefix="in1" lib_name="A" size="1"/>
+      <port type="input" prefix="sel" lib_name="S" size="1"/>
+      <port type="output" prefix="out" lib_name="Y" size="1"/>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_tree" prefix="mux_tree" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="stdcell_mux2"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_tree_tapbuf" prefix="mux_tree_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="stdcell_mux2"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
+      <design_technology type="cmos" fracturable_lut="true"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
+      <pass_gate_logic circuit_model_name="stdcell_mux2"/>
+      <port type="input" prefix="in" size="6" tri_state_map="-----1" circuit_model_name="OR2"/>
+      <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
+      <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
+      <port type="sram" prefix="sram" size="64"/>
+      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="Qb" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+      <port type="input" prefix="outpad" size="1"/>
+      <port type="output" prefix="inpad" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_tree_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_tree"/>
+    </pb_type>
+    <pb_type name="clb.fle" physical_mode_name="physical"/>
+    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="0"/>
+    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
+    <!-- Binding operating pb_type to physical pb_type -->
+    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="1" physical_pb_type_index_factor="0.5">
+      <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:4]"/>
+      <port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="0">
+      <!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:5]"/>
+      <port name="out" physical_mode_port="lut6_out"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>
+<openfpga_simulation_setting>
+  <clock_setting>
+    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
+    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
+    <programming frequency="10e6"/>
+  </clock_setting>
+  <simulator_option>
+    <operating_condition temperature="25"/>
+    <output_log verbose="false" captab="false"/>
+    <accuracy type="abs" value="1e-13"/>
+    <runtime fast_simulation="true"/>
+  </simulator_option>
+  <monte_carlo num_simulation_points="2"/>
+  <measurement_setting>
+    <slew>
+      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
+      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
+    </slew>
+    <delay>
+      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
+      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
+    </delay>
+  </measurement_setting>
+  <stimulus>
+    <clock>
+      <rise slew_type="abs" slew_time="20e-12" />
+      <fall slew_type="abs" slew_time="20e-12" />
+    </clock>
+    <input>
+      <rise slew_type="abs" slew_time="25e-12" />
+      <fall slew_type="abs" slew_time="25e-12" />
+    </input>
+  </stimulus>
+</openfpga_simulation_setting>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml
new file mode 100644
index 000000000..d04318510
--- /dev/null
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml
@@ -0,0 +1,251 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
+      <design_technology type="cmos" topology="OR"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="MUX2" prefix="MUX2" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_tree" prefix="mux_tree" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="MUX2"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_tree_tapbuf" prefix="mux_tree_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="MUX2"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
+      <design_technology type="cmos" fracturable_lut="true"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
+      <pass_gate_logic circuit_model_name="MUX2"/>
+      <port type="input" prefix="in" size="6" tri_state_map="-----1" circuit_model_name="OR2"/>
+      <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
+      <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
+      <port type="sram" prefix="sram" size="64"/>
+      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="Qb" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+      <port type="input" prefix="outpad" size="1"/>
+      <port type="output" prefix="inpad" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_tree_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_tree"/>
+    </pb_type>
+    <pb_type name="clb.fle" physical_mode_name="physical"/>
+    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="0"/>
+    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
+    <!-- Binding operating pb_type to physical pb_type -->
+    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="1" physical_pb_type_index_factor="0.5">
+      <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:4]"/>
+      <port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="0">
+      <!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:5]"/>
+      <port name="out" physical_mode_port="lut6_out"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>
+<openfpga_simulation_setting>
+  <clock_setting>
+    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
+    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
+    <programming frequency="10e6"/>
+  </clock_setting>
+  <simulator_option>
+    <operating_condition temperature="25"/>
+    <output_log verbose="false" captab="false"/>
+    <accuracy type="abs" value="1e-13"/>
+    <runtime fast_simulation="true"/>
+  </simulator_option>
+  <monte_carlo num_simulation_points="2"/>
+  <measurement_setting>
+    <slew>
+      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
+      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
+    </slew>
+    <delay>
+      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
+      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
+    </delay>
+  </measurement_setting>
+  <stimulus>
+    <clock>
+      <rise slew_type="abs" slew_time="20e-12" />
+      <fall slew_type="abs" slew_time="20e-12" />
+    </clock>
+    <input>
+      <rise slew_type="abs" slew_time="25e-12" />
+      <fall slew_type="abs" slew_time="25e-12" />
+    </input>
+  </stimulus>
+</openfpga_simulation_setting>

From 80bdb41df61a58a7165371999b7239b153a561cf Mon Sep 17 00:00:00 2001
From: ganeshgore <goreganesh007@gmail.com>
Date: Sat, 11 Apr 2020 18:30:21 -0600
Subject: [PATCH 416/645] Updated task file to run formal verification

---
 openfpga_flow/tasks/OpenFPGAShell_Example/config/task.conf | 1 +
 1 file changed, 1 insertion(+)

diff --git a/openfpga_flow/tasks/OpenFPGAShell_Example/config/task.conf b/openfpga_flow/tasks/OpenFPGAShell_Example/config/task.conf
index f06ae2589..4ea65822f 100644
--- a/openfpga_flow/tasks/OpenFPGAShell_Example/config/task.conf
+++ b/openfpga_flow/tasks/OpenFPGAShell_Example/config/task.conf
@@ -31,3 +31,4 @@ bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
 end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

From 68fd296e14ebb9b40f0c37762884f400816da35f Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 12 Apr 2020 12:49:16 -0600
Subject: [PATCH 417/645] add more test vpr architecture to regression tests

---
 ...N10_tileable_adder_register_chain_40nm.xml | 696 +++++++++++++++++
 ...ileable_adder_register_scan_chain_40nm.xml | 734 ++++++++++++++++++
 2 files changed, 1430 insertions(+)
 create mode 100644 openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_chain_40nm.xml
 create mode 100644 openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml

diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_chain_40nm.xml b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_chain_40nm.xml
new file mode 100644
index 000000000..77dedbcb0
--- /dev/null
+++ b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_chain_40nm.xml
@@ -0,0 +1,696 @@
+<!-- 
+  Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with 8 total FLE inputs (2 inputs of which are shared by the 5-LUTs) 
+    with optionally registered outputs
+    Each 5-LUT has an arithemtic mode that converts it to a single-bit adder with both inputs driven by 4-LUTs (both 4-LUTs share all 4 inputs)
+    Carry chain links to vertically adjacent logic blocks
+  - Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.  
+    Height = 6, found on every (8n+2)th column
+  - Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.  
+    Height = 4, found on every (8n+6)th column
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Details on Modelling:
+
+  The electrical design of the architecture described here is NOT from an 
+  optimized, SPICED architecture.  Instead, we attempt to create a reasonable 
+  architecture file by using an existing commercial FPGA to approximate the area, 
+  delay, and power of the underlying components. This is combined with a reasonable 40 nm 
+  model of wiring and circuit design for low-level routing components, where available.
+  The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also 
+  has wiring electrical parameters that allow the wire lengths and switch patterns to be 
+  modified and you will still get reasonable delay results for the new architecture.
+  The following describes, in detail, how we obtained the various electrical values for this 
+  architecture.
+
+  Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar 
+  architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture. 
+  (n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)      
+  This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to 
+  match the overall target (a 40 nm FPGA).
+
+  We obtain delay numbers by measuring delays of routing, soft logic blocks, 
+  memories, and multipliers from test circuits on a Stratix IV GX device 
+  (EP4SGX230DF29C2X, i.e. fastest speed grade). For routing, we took the average delay of H4 and V4 
+  wires.  Rmetal and Cmetal values for the routing wires were obtained from work done by Charles 
+  Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal stack 40 nm routing) and 
+  take the R and C data from the ITRS roadmap.  
+
+  For the general purpose logic block, we assume that the area and delays of the Stratix IV 
+  crossbar is close enough to the crossbar modelled here.  
+  Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to 
+  36:1 multiplexers.  We match these parameters in this architecture.
+
+  For LUTs, we include LUT 
+  delays measured from Stratix IV which is dependant on the input used (ie. some 
+  LUT inputs are faster than others).  The CAD tools at the time of VTR 7 does 
+  not consider differences in LUT input delays.
+
+  Adder delays obtained as approximate values from a Stratix IV EP4SE230F29C3 device.  
+  Delay obtained by compiling a 256 bit adder (registered inputs and outputs, 
+  all pins except clock virtual) then measuring the delays in chip-planner, 
+  sumout delay = 0.271ns to 0.348 ns, intra-block carry delay = 0.011 ns, 
+  inter-block carry delay = 0.327 ns.  Given this data, I will approximate 
+  sumout 0.3 ns, intra-block carry-delay = 0.01 ns, and 
+  inter-block carry-delay = 0.16 ns (since Altera inter-block carry delay has 
+  overhead that we don't have, I'll approximate the delay of a simpler chain at 
+  one half what they have.  This is very rough, anything from 0.01ns to 0.327ns 
+  can be justified).
+
+  Logic block area numbers obtained by scaling overall tile area of a 65nm 
+  Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out 
+  routing area at a channel width of 300. We use a channel width of 300 because it can route 
+  all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
+  total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
+  choosing a width that provides high routability. The architecture can be routed at different channel
+  widths, but we estimate the tile size and hence the physical length of routing wires assuming
+  a channel width of 300.
+
+  Sanity checks employed:
+    1.  We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches 
+        common electrical design.
+
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <model name="adder">
+      <input_ports>
+        <port name="a" combinational_sink_ports="sumout cout"/>
+        <port name="b" combinational_sink_ports="sumout cout"/>
+        <port name="cin" combinational_sink_ports="sumout cout"/>
+      </input_ports>
+      <output_ports>
+        <port name="cout"/>
+        <port name="sumout"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="frac_lut6">
+      <input_ports>
+        <port name="in"/>
+      </input_ports>
+      <output_ports>
+        <port name="lut4_out"/>
+        <port name="lut5_out"/>
+        <port name="lut6_out"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <tile name="io" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad</loc>
+        <loc side="top">io.outpad io.inpad</loc>
+        <loc side="right">io.outpad io.inpad</loc>
+        <loc side="bottom">io.outpad io.inpad</loc>
+      </pinlocations>
+    </tile>
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <input name="regin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <output name="regout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="regin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="regout" fc_type="frac" fc_val="0"/>
+      </fc>
+      <!--  Highly recommand to customize pin location when direct connection is used!!! -->
+      <!--pinlocations pattern="spread"/-->
+      <pinlocations pattern="custom">
+        <loc side="left">clb.clk</loc>
+        <loc side="top">clb.cin clb.regin</loc>
+        <loc side="right">clb.O[9:0] clb.I[19:0]</loc>
+        <loc side="bottom">clb.cout clb.regout clb.O[19:10] clb.I[39:20]</loc>
+      </pinlocations>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout tileable="true">
+    <!--auto_layout aspect_ratio="1.0"-->
+    <fixed_layout name="4x4" width="6" height="6">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </fixed_layout>
+    <!-- /auto_layout -->
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	    -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+           book area formula. This means the mux transistors are about 5x minimum drive strength.
+           We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+           mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+           the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+           by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+           buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+           I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+           (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+           The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+           2.5x when looking up in Jeff's tables.
+           Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+           This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+             With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+             reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <directlist>
+    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
+    <direct name="shift_register" from_pin="clb.regout" to_pin="clb.regin" x_offset="0" y_offset="-1" z_offset="0"/>
+  </directlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+
+      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+           If you need to register the I/O, define clocks in the circuit models
+           These clocks can be handled in back-end
+       -->
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" packable="false">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <input name="regin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <output name="regout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe fracturable logic element.  
+             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
+             The outputs of the fracturable logic element can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="10">
+        <input name="in" num_pins="6"/>
+        <input name="cin" num_pins="1"/>
+        <input name="regin" num_pins="1"/>
+        <output name="out" num_pins="2"/>
+        <output name="cout" num_pins="1"/>
+        <output name="regout" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- Physical mode definition begin (physical implementation of the fle) -->
+        <mode name="physical" packable="false">
+          <pb_type name="fabric" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <input name="cin" num_pins="1"/>
+            <input name="regin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <output name="regout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="frac_logic" num_pb="1">
+              <input name="in" num_pins="6"/>
+              <output name="lut4_out" num_pins="4"/>
+              <output name="out" num_pins="2"/>
+              <!-- Define LUT -->
+              <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
+                <input name="in" num_pins="6"/>
+                <output name="lut4_out" num_pins="4"/>
+                <output name="lut5_out" num_pins="2"/>
+                <output name="lut6_out" num_pins="1"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
+                <direct name="direct2" input="frac_lut6.lut4_out" output="frac_logic.lut4_out"/>
+                <direct name="direct3" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
+                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
+                <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
+              </interconnect>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>         
+            <!-- Define adders -->
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="2">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
+              <direct name="direct2" input="fabric.cin" output="adder[0:0].cin"/>
+              <direct name="direct3" input="adder[0:0].cout" output="adder[1:1].cin"/>
+              <direct name="direct4" input="adder[1:1].cout" output="fabric.cout"/>
+              <direct name="direct5" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
+              <direct name="direct6" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
+              <direct name="direct7" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
+              <direct name="direct8" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
+              <complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
+              <mux name="mux1" input="adder[0].sumout frac_logic.out[0] fabric.regin" output="ff[0].D">
+                <delay_constant max="25e-12" in_port="adder[0].sumout frac_logic.out[0] fabric.regin" out_port="ff[0].D"/>
+              </mux>
+              <mux name="mux2" input="adder[1].sumout frac_logic.out[1] ff[0].Q" output="ff[1].D">
+                <delay_constant max="25e-12" in_port="adder[1].sumout frac_logic.out[1] ff[0].Q" out_port="ff[1].D"/>
+              </mux>
+              <mux name="mux3" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
+                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
+              </mux>
+              <mux name="mux4" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
+                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="fabric.in"/>
+            <direct name="direct2" input="fle.cin" output="fabric.cin"/>
+            <direct name="direct3" input="fle.regin" output="fabric.regin"/>
+            <direct name="direct4" input="fabric.out" output="fle.out"/>
+            <direct name="direct5" input="fabric.cout" output="fle.cout"/>
+            <direct name="direct6" input="fabric.regout" output="fle.regout"/>
+            <direct name="direct7" input="fle.clk" output="fabric.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Physical mode definition end (physical implementation of the fle) -->
+        <!-- BEGIN fle mode of dual lut5 -->
+        <mode name="n2_lut5">
+          <pb_type name="ble5" num_pb="2">
+            <input name="in" num_pins="5"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Regular LUT mode -->
+            <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="5" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                  we instead take the average of these numbers to get more stable results
+                82e-12
+                173e-12
+                261e-12
+                263e-12
+                398e-12
+                -->
+              <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+              </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble5.in" output="lut5.in"/>
+              <direct name="direct2" input="lut5.out" output="ff.D">
+                <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble5.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut5.out" output="ble5.out">
+                <delay_constant max="25e-12" in_port="lut5.out" out_port="ble5.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble5.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[4:0]" output="ble5[0:0].in"/>
+            <direct name="direct2" input="fle.in[4:0]" output="ble5[1:1].in"/>
+            <complete name="direct3" input="fle.clk" output="ble5.clk"/>
+            <direct name="direct4" input="ble5.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- END fle mode of dual lut5 -->
+        <!-- BEGIN arithmetic mode of dual lut4 + adders -->
+        <mode name="arithmetic">
+          <pb_type name="arithmetic" num_pb="2">
+            <input name="in" num_pins="4"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="1"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Special dual-LUT mode that drives adder only -->
+            <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
+              <input name="in" num_pins="4" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  -->
+              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                  195e-12
+                  195e-12
+                  195e-12
+                  195e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
+              <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
+              <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
+              <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
+                </direct>
+              <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
+                </direct>
+              <direct name="add_to_ff" input="adder.sumout" output="ff.D">
+                <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
+              </direct>
+              <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
+                <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
+              </direct>
+              <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
+                <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
+              </direct>
+              <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
+                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[3:0]" output="arithmetic[0:0].in"/>
+            <direct name="direct2" input="fle.in[3:0]" output="arithmetic[1:1].in"/>
+            <direct name="carry_in" input="fle.cin" output="arithmetic[0:0].cin">
+              <pack_pattern name="chain" in_port="fle.cin" out_port="arithmetic[0:0].cin"/>
+            </direct>
+            <direct name="carry_inter" input="arithmetic[0:0].cout" output="arithmetic[1:1].cin">
+              <pack_pattern name="chain" in_port="arithmetic[0:0].cout" out_port="arithmetic[1:1].cin"/>
+            </direct>
+            <direct name="carry_out" input="arithmetic[1:1].cout" output="fle.cout">
+              <pack_pattern name="chain" in_port="arithmetic.cout" out_port="fle.cout"/>
+            </direct>
+            <complete name="direct3" input="fle.clk" output="arithmetic.clk"/>
+            <direct name="direct4" input="arithmetic.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- n2_lut5 -->
+        <mode name="n1_lut6">
+          <pb_type name="ble6" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="6" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->
+              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+              <direct name="direct2" input="lut6.out" output="ff.D">
+                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
+            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Define n1_lut6 end -->
+        <!-- Define shift register begin -->
+        <mode name="shift_register">
+          <pb_type name="shift_reg" num_pb="1">
+            <input name="regin" num_pins="1"/>
+            <output name="regout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="shift_reg.regin" output="ff[0].D"/>
+              <direct name="direct2" input="ff[0].Q" output="ff[1].D"/>
+              <direct name="direct3" input="ff[1].Q" output="shift_reg.regout"/>
+              <complete name="complete1" input="shift_reg.clk" output="ff.clk"/>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.regin" output="shift_reg.regin"/>
+            <direct name="direct2" input="shift_reg.regout" output="fle.regout"/>
+            <direct name="direct3" input="fle.clk" output="shift_reg.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Define shift register end --> 
+      </pb_type>
+      <interconnect>
+        <!-- We use a 50% depop crossbar built using small full xbars to get sets of logically equivalent pins at inputs of CLB 
+           The delays below come from Stratix IV. the delay through a connection block
+           input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+           delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+           delay within the crossbar is 95 ps. 
+           The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+           Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+           25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+           to get the part that should be marked on the crossbar.	 -->
+        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
+          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
+          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
+        </complete>
+
+        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+        </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+                 By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+                 then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+                 naive specification).
+          -->
+        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
+        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
+        <!-- Carry chain links -->
+        <direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
+          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
+        </direct>
+        <direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
+          <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
+        </direct>
+        <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
+          <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
+        </direct>
+        <!-- Shift register chain links -->
+        <direct name="shift_register_in" input="clb.regin" output="fle[0:0].regin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.16e-9" in_port="clb.regin" out_port="fle[0:0].regin"/>
+          <pack_pattern name="chain" in_port="clb.regin" out_port="fle[0:0].regin"/>
+        </direct>
+        <direct name="shift_register_out" input="fle[9:9].regout" output="clb.regout">
+          <pack_pattern name="chain" in_port="fle[9:9].regout" out_port="clb.regout"/>
+        </direct>
+        <direct name="shift_register_link" input="fle[8:0].regout" output="fle[9:1].regin">
+          <pack_pattern name="chain" in_port="fle[8:0].regout" out_port="fle[9:1].regin"/>
+        </direct>
+      </interconnect>
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+  </complexblocklist>
+</architecture>
diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml
new file mode 100644
index 000000000..f83919c7c
--- /dev/null
+++ b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml
@@ -0,0 +1,734 @@
+<!-- 
+  Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with 8 total FLE inputs (2 inputs of which are shared by the 5-LUTs) 
+    with optionally registered outputs
+    Each 5-LUT has an arithemtic mode that converts it to a single-bit adder with both inputs driven by 4-LUTs (both 4-LUTs share all 4 inputs)
+    Carry chain links to vertically adjacent logic blocks
+  - Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.  
+    Height = 6, found on every (8n+2)th column
+  - Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.  
+    Height = 4, found on every (8n+6)th column
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Details on Modelling:
+
+  The electrical design of the architecture described here is NOT from an 
+  optimized, SPICED architecture.  Instead, we attempt to create a reasonable 
+  architecture file by using an existing commercial FPGA to approximate the area, 
+  delay, and power of the underlying components. This is combined with a reasonable 40 nm 
+  model of wiring and circuit design for low-level routing components, where available.
+  The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also 
+  has wiring electrical parameters that allow the wire lengths and switch patterns to be 
+  modified and you will still get reasonable delay results for the new architecture.
+  The following describes, in detail, how we obtained the various electrical values for this 
+  architecture.
+
+  Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar 
+  architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture. 
+  (n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)      
+  This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to 
+  match the overall target (a 40 nm FPGA).
+
+  We obtain delay numbers by measuring delays of routing, soft logic blocks, 
+  memories, and multipliers from test circuits on a Stratix IV GX device 
+  (EP4SGX230DF29C2X, i.e. fastest speed grade). For routing, we took the average delay of H4 and V4 
+  wires.  Rmetal and Cmetal values for the routing wires were obtained from work done by Charles 
+  Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal stack 40 nm routing) and 
+  take the R and C data from the ITRS roadmap.  
+
+  For the general purpose logic block, we assume that the area and delays of the Stratix IV 
+  crossbar is close enough to the crossbar modelled here.  
+  Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to 
+  36:1 multiplexers.  We match these parameters in this architecture.
+
+  For LUTs, we include LUT 
+  delays measured from Stratix IV which is dependant on the input used (ie. some 
+  LUT inputs are faster than others).  The CAD tools at the time of VTR 7 does 
+  not consider differences in LUT input delays.
+
+  Adder delays obtained as approximate values from a Stratix IV EP4SE230F29C3 device.  
+  Delay obtained by compiling a 256 bit adder (registered inputs and outputs, 
+  all pins except clock virtual) then measuring the delays in chip-planner, 
+  sumout delay = 0.271ns to 0.348 ns, intra-block carry delay = 0.011 ns, 
+  inter-block carry delay = 0.327 ns.  Given this data, I will approximate 
+  sumout 0.3 ns, intra-block carry-delay = 0.01 ns, and 
+  inter-block carry-delay = 0.16 ns (since Altera inter-block carry delay has 
+  overhead that we don't have, I'll approximate the delay of a simpler chain at 
+  one half what they have.  This is very rough, anything from 0.01ns to 0.327ns 
+  can be justified).
+
+  Logic block area numbers obtained by scaling overall tile area of a 65nm 
+  Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out 
+  routing area at a channel width of 300. We use a channel width of 300 because it can route 
+  all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
+  total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
+  choosing a width that provides high routability. The architecture can be routed at different channel
+  widths, but we estimate the tile size and hence the physical length of routing wires assuming
+  a channel width of 300.
+
+  Sanity checks employed:
+    1.  We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches 
+        common electrical design.
+
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <model name="adder">
+      <input_ports>
+        <port name="a" combinational_sink_ports="sumout cout"/>
+        <port name="b" combinational_sink_ports="sumout cout"/>
+        <port name="cin" combinational_sink_ports="sumout cout"/>
+      </input_ports>
+      <output_ports>
+        <port name="cout"/>
+        <port name="sumout"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for fractruable LUT to be used in the physical mode of LUT -->
+    <model name="frac_lut6">
+      <input_ports>
+        <port name="in"/>
+      </input_ports>
+      <output_ports>
+        <port name="lut4_out"/>
+        <port name="lut5_out"/>
+        <port name="lut6_out"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for scan-chain flip-flop to be used in the physical mode of FF -->
+    <model name="scff">
+      <input_ports>
+        <port name="D" clock="clk"/>
+        <port name="DI" clock="clk"/>
+        <port name="clk" is_clock="1"/>
+      </input_ports>
+      <output_ports>
+        <port name="Q" clock="clk"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <tile name="io" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad</loc>
+        <loc side="top">io.outpad io.inpad</loc>
+        <loc side="right">io.outpad io.inpad</loc>
+        <loc side="bottom">io.outpad io.inpad</loc>
+      </pinlocations>
+    </tile>
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <input name="regin" num_pins="1"/>
+      <input name="scin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <output name="regout" num_pins="1"/>
+      <output name="scout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="regin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="regout" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="scin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="scout" fc_type="frac" fc_val="0"/>
+      </fc>
+      <!--  Highly recommand to customize pin location when direct connection is used!!! -->
+      <!--pinlocations pattern="spread"/-->
+      <pinlocations pattern="custom">
+        <loc side="left">clb.clk</loc>
+        <loc side="top">clb.cin clb.regin clb.scin</loc>
+        <loc side="right">clb.O[9:0] clb.I[19:0]</loc>
+        <loc side="bottom">clb.cout clb.regout clb.scout clb.O[19:10] clb.I[39:20]</loc>
+      </pinlocations>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout tileable="true">
+    <!--auto_layout aspect_ratio="1.0"-->
+    <fixed_layout name="4x4" width="6" height="6">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </fixed_layout>
+    <!-- /auto_layout -->
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	    -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+           book area formula. This means the mux transistors are about 5x minimum drive strength.
+           We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+           mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+           the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+           by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+           buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+           I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+           (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+           The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+           2.5x when looking up in Jeff's tables.
+           Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+           This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+             With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+             reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <directlist>
+    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
+    <direct name="shift_register" from_pin="clb.regout" to_pin="clb.regin" x_offset="0" y_offset="-1" z_offset="0"/>
+    <direct name="scan_chain" from_pin="clb.scout" to_pin="clb.scin" x_offset="0" y_offset="-1" z_offset="0"/>
+  </directlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+
+      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+           If you need to register the I/O, define clocks in the circuit models
+           These clocks can be handled in back-end
+       -->
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" packable="false">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <input name="regin" num_pins="1"/>
+      <input name="scin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <output name="regout" num_pins="1"/>
+      <output name="scout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe fracturable logic element.  
+             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
+             The outputs of the fracturable logic element can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="10">
+        <input name="in" num_pins="6"/>
+        <input name="cin" num_pins="1"/>
+        <input name="regin" num_pins="1"/>
+        <input name="scin" num_pins="1"/>
+        <output name="out" num_pins="2"/>
+        <output name="cout" num_pins="1"/>
+        <output name="regout" num_pins="1"/>
+        <output name="scout" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- Physical mode definition begin (physical implementation of the fle) -->
+        <mode name="physical" packable="false">
+          <pb_type name="fabric" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <input name="cin" num_pins="1"/>
+            <input name="regin" num_pins="1"/>
+            <input name="scin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <output name="regout" num_pins="1"/>
+            <output name="scout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="frac_logic" num_pb="1">
+              <input name="in" num_pins="6"/>
+              <output name="lut4_out" num_pins="4"/>
+              <output name="out" num_pins="2"/>
+              <!-- Define LUT -->
+              <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
+                <input name="in" num_pins="6"/>
+                <output name="lut4_out" num_pins="4"/>
+                <output name="lut5_out" num_pins="2"/>
+                <output name="lut6_out" num_pins="1"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
+                <direct name="direct2" input="frac_lut6.lut4_out" output="frac_logic.lut4_out"/>
+                <direct name="direct3" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
+                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
+                <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
+              </interconnect>
+            </pb_type>
+            <!-- Define flip-flop with scan-chain capability, DI is the scan-chain data input -->
+            <pb_type name="ff" blif_model=".subckt scff" num_pb="2">
+              <input name="D" num_pins="1"/>
+              <input name="DI" num_pins="1"/>
+              <output name="Q" num_pins="1"/>
+              <clock name="clk" num_pins="1"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_setup value="66e-12" port="ff.DI" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>         
+            <!-- Define adders -->
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="2">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
+              <direct name="direct2" input="fabric.cin" output="adder[0:0].cin"/>
+              <direct name="direct3" input="adder[0:0].cout" output="adder[1:1].cin"/>
+              <direct name="direct4" input="adder[1:1].cout" output="fabric.cout"/>
+              <direct name="direct5" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
+              <direct name="direct6" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
+              <direct name="direct7" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
+              <direct name="direct8" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
+              <direct name="direct9" input="fabric.scin" output="ff[0].DI"/>
+              <direct name="direct10" input="ff[0].Q" output="ff[1].DI"/>
+              <direct name="direct11" input="ff[1].Q" output="fabric.scout"/>
+              <complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
+              <mux name="mux1" input="adder[0].sumout frac_logic.out[0] fabric.regin" output="ff[0].D">
+                <delay_constant max="25e-12" in_port="adder[0].sumout frac_logic.out[0] fabric.regin" out_port="ff[0].D"/>
+              </mux>
+              <mux name="mux2" input="adder[1].sumout frac_logic.out[1] ff[0].Q" output="ff[1].D">
+                <delay_constant max="25e-12" in_port="adder[1].sumout frac_logic.out[1] ff[0].Q" out_port="ff[1].D"/>
+              </mux>
+              <mux name="mux3" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
+                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
+              </mux>
+              <mux name="mux4" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
+                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="fabric.in"/>
+            <direct name="direct2" input="fle.cin" output="fabric.cin"/>
+            <direct name="direct3" input="fle.regin" output="fabric.regin"/>
+            <direct name="direct4" input="fle.scin" output="fabric.scin"/>
+            <direct name="direct5" input="fabric.out" output="fle.out"/>
+            <direct name="direct6" input="fabric.cout" output="fle.cout"/>
+            <direct name="direct7" input="fabric.regout" output="fle.regout"/>
+            <direct name="direct8" input="fabric.scout" output="fle.scout"/>
+            <direct name="direct9" input="fle.clk" output="fabric.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Physical mode definition end (physical implementation of the fle) -->
+        <!-- BEGIN fle mode of dual lut5 -->
+        <mode name="n2_lut5">
+          <pb_type name="ble5" num_pb="2">
+            <input name="in" num_pins="5"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Regular LUT mode -->
+            <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="5" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                  we instead take the average of these numbers to get more stable results
+                82e-12
+                173e-12
+                261e-12
+                263e-12
+                398e-12
+                -->
+              <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+              </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble5.in" output="lut5.in"/>
+              <direct name="direct2" input="lut5.out" output="ff.D">
+                <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble5.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut5.out" output="ble5.out">
+                <delay_constant max="25e-12" in_port="lut5.out" out_port="ble5.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble5.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[4:0]" output="ble5[0:0].in"/>
+            <direct name="direct2" input="fle.in[4:0]" output="ble5[1:1].in"/>
+            <complete name="direct3" input="fle.clk" output="ble5.clk"/>
+            <direct name="direct4" input="ble5.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- END fle mode of dual lut5 -->
+        <!-- BEGIN arithmetic mode of dual lut4 + adders -->
+        <mode name="arithmetic">
+          <pb_type name="arithmetic" num_pb="2">
+            <input name="in" num_pins="4"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="1"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Special dual-LUT mode that drives adder only -->
+            <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
+              <input name="in" num_pins="4" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  -->
+              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                  195e-12
+                  195e-12
+                  195e-12
+                  195e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
+              <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
+              <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
+              <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
+                </direct>
+              <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
+                </direct>
+              <direct name="add_to_ff" input="adder.sumout" output="ff.D">
+                <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
+              </direct>
+              <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
+                <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
+              </direct>
+              <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
+                <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
+              </direct>
+              <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
+                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[3:0]" output="arithmetic[0:0].in"/>
+            <direct name="direct2" input="fle.in[3:0]" output="arithmetic[1:1].in"/>
+            <direct name="carry_in" input="fle.cin" output="arithmetic[0:0].cin">
+              <pack_pattern name="chain" in_port="fle.cin" out_port="arithmetic[0:0].cin"/>
+            </direct>
+            <direct name="carry_inter" input="arithmetic[0:0].cout" output="arithmetic[1:1].cin">
+              <pack_pattern name="chain" in_port="arithmetic[0:0].cout" out_port="arithmetic[1:1].cin"/>
+            </direct>
+            <direct name="carry_out" input="arithmetic[1:1].cout" output="fle.cout">
+              <pack_pattern name="chain" in_port="arithmetic.cout" out_port="fle.cout"/>
+            </direct>
+            <complete name="direct3" input="fle.clk" output="arithmetic.clk"/>
+            <direct name="direct4" input="arithmetic.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- n2_lut5 -->
+        <mode name="n1_lut6">
+          <pb_type name="ble6" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="6" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->
+              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+              <direct name="direct2" input="lut6.out" output="ff.D">
+                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
+            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Define n1_lut6 end -->
+        <!-- Define shift register begin -->
+        <mode name="shift_register">
+          <pb_type name="shift_reg" num_pb="1">
+            <input name="regin" num_pins="1"/>
+            <output name="regout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="shift_reg.regin" output="ff[0].D"/>
+              <direct name="direct2" input="ff[0].Q" output="ff[1].D"/>
+              <direct name="direct3" input="ff[1].Q" output="shift_reg.regout"/>
+              <complete name="complete1" input="shift_reg.clk" output="ff.clk"/>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.regin" output="shift_reg.regin"/>
+            <direct name="direct2" input="shift_reg.regout" output="fle.regout"/>
+            <direct name="direct3" input="fle.clk" output="shift_reg.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Define shift register end --> 
+      </pb_type>
+      <interconnect>
+        <!-- We use a 50% depop crossbar built using small full xbars to get sets of logically equivalent pins at inputs of CLB 
+           The delays below come from Stratix IV. the delay through a connection block
+           input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+           delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+           delay within the crossbar is 95 ps. 
+           The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+           Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+           25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+           to get the part that should be marked on the crossbar.	 -->
+        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
+          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
+          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
+        </complete>
+
+        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+        </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+                 By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+                 then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+                 naive specification).
+          -->
+        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
+        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
+        <!-- Carry chain links -->
+        <direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
+          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
+        </direct>
+        <direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
+          <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
+        </direct>
+        <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
+          <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
+        </direct>
+        <!-- Shift register chain links -->
+        <direct name="shift_register_in" input="clb.regin" output="fle[0:0].regin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.16e-9" in_port="clb.regin" out_port="fle[0:0].regin"/>
+          <pack_pattern name="chain" in_port="clb.regin" out_port="fle[0:0].regin"/>
+        </direct>
+        <direct name="shift_register_out" input="fle[9:9].regout" output="clb.regout">
+          <pack_pattern name="chain" in_port="fle[9:9].regout" out_port="clb.regout"/>
+        </direct>
+        <direct name="shift_register_link" input="fle[8:0].regout" output="fle[9:1].regin">
+          <pack_pattern name="chain" in_port="fle[8:0].regout" out_port="fle[9:1].regin"/>
+        </direct>
+        <!-- Scan chain links -->
+        <direct name="scan_chain_in" input="clb.scin" output="fle[0:0].scin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.16e-9" in_port="clb.scin" out_port="fle[0:0].scin"/>
+        </direct>
+        <direct name="scan_chain_out" input="fle[9:9].scout" output="clb.scout">
+        </direct>
+        <direct name="scan_chain_link" input="fle[8:0].scout" output="fle[9:1].scin">
+        </direct>
+      </interconnect>
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+  </complexblocklist>
+</architecture>

From d806ad314819139edbfbff4a9268b7ee5173a14c Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 12 Apr 2020 12:54:21 -0600
Subject: [PATCH 418/645] add testcases using openfpga_shell in openfpga_flow

---
 .../openfpga_shell/frac_lut/config/task.conf  | 34 +++++++++++++++++++
 1 file changed, 34 insertions(+)
 create mode 100644 openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf

diff --git a/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf b/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf
new file mode 100644
index 000000000..4ea65822f
--- /dev/null
+++ b/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf
@@ -0,0 +1,34 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = top
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

From cc7adae91e121e0203789d68b90a7f8555a38d79 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 12 Apr 2020 12:57:13 -0600
Subject: [PATCH 419/645] deploy openfpga shell in Travis CI

---
 .travis/script.sh | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/.travis/script.sh b/.travis/script.sh
index f49bb68ea..754289e9f 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -18,6 +18,11 @@ end_section "OpenFPGA.build"
 
 start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
 cd -
+
+###############################################
+# OpenFPGA with VPR7
+# TO BE DEPRECATED
+##############################################
 echo -e "Testing single-mode architectures";
 python3 openfpga_flow/scripts/run_fpga_task.py single_mode --debug --show_thread_logs
 #python3 openfpga_flow/scripts/run_fpga_task.py s298 
@@ -37,4 +42,13 @@ python3 openfpga_flow/scripts/run_fpga_task.py explicit_verilog --debug --show_t
 echo -e "Testing Verilog generation with grid pin duplication ";
 python3 openfpga_flow/scripts/run_fpga_task.py duplicate_grid_pin --debug --show_thread_logs
 
+###############################################
+# OpenFPGA Shell with VPR8
+# (Will replace all the old tests)
+##############################################
+echo -e "Testing OpenFPGA Shell";
+
+echo -e "Testing Verilog generation with simple fracturable LUT6 ";
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/frac_lut --debug --show_thread_logs
+
 end_section "OpenFPGA.TaskTun"

From 2444752de89c13a27c8e68a22b099fdf79823c06 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 12 Apr 2020 14:08:24 -0600
Subject: [PATCH 420/645] add untileable test case to Travis CI

---
 .travis/script.sh                             |  3 ++
 .../openfpga_shell/frac_lut/config/task.conf  |  2 +-
 .../untileable/config/task.conf               | 34 +++++++++++++++++++
 3 files changed, 38 insertions(+), 1 deletion(-)
 create mode 100644 openfpga_flow/tasks/openfpga_shell/untileable/config/task.conf

diff --git a/.travis/script.sh b/.travis/script.sh
index 754289e9f..e36520d1e 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -51,4 +51,7 @@ echo -e "Testing OpenFPGA Shell";
 echo -e "Testing Verilog generation with simple fracturable LUT6 ";
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/frac_lut --debug --show_thread_logs
 
+echo -e "Testing Verilog generation with VPR's untileable routing architecture ";
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/untileable --debug --show_thread_logs
+
 end_section "OpenFPGA.TaskTun"
diff --git a/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf b/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf
index 4ea65822f..a52d2f515 100644
--- a/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf
@@ -18,7 +18,7 @@ fpga_flow=vpr_blif
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
 
 [ARCHITECTURES]
-arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_40nm.xml
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
 
 [BENCHMARKS]
 bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
diff --git a/openfpga_flow/tasks/openfpga_shell/untileable/config/task.conf b/openfpga_flow/tasks/openfpga_shell/untileable/config/task.conf
new file mode 100644
index 000000000..4ea65822f
--- /dev/null
+++ b/openfpga_flow/tasks/openfpga_shell/untileable/config/task.conf
@@ -0,0 +1,34 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = top
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

From 600a48edc7716ec8833b7591352c15913a750e06 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 12 Apr 2020 14:27:05 -0600
Subject: [PATCH 421/645] add test case of BRAM to Travis CI

---
 .travis/script.sh                             |  6 ++
 openfpga_flow/VerilogNetlists/dpram16k.v      | 56 +++++++++++++++++++
 .../k6_frac_N10_tileable_adder_chain_40nm.xml |  2 +-
 ...c_N10_tileable_adder_chain_mem16K_40nm.xml |  2 +-
 ...c_N10_adder_chain_mem16K_40nm_openfpga.xml |  2 +-
 .../openfpga_shell/bram/config/task.conf      | 34 +++++++++++
 .../hard_adder/config/task.conf               | 34 +++++++++++
 7 files changed, 133 insertions(+), 3 deletions(-)
 create mode 100644 openfpga_flow/VerilogNetlists/dpram16k.v
 create mode 100644 openfpga_flow/tasks/openfpga_shell/bram/config/task.conf
 create mode 100644 openfpga_flow/tasks/openfpga_shell/hard_adder/config/task.conf

diff --git a/.travis/script.sh b/.travis/script.sh
index e36520d1e..81358c90f 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -54,4 +54,10 @@ python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/frac_lut --debug -
 echo -e "Testing Verilog generation with VPR's untileable routing architecture ";
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/untileable --debug --show_thread_logs
 
+echo -e "Testing Verilog generation with hard adder chain in CLBs ";
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/hard_adder --debug --show_thread_logs
+
+echo -e "Testing Verilog generation with 16k block RAMs ";
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/bram --debug --show_thread_logs
+
 end_section "OpenFPGA.TaskTun"
diff --git a/openfpga_flow/VerilogNetlists/dpram16k.v b/openfpga_flow/VerilogNetlists/dpram16k.v
new file mode 100644
index 000000000..665884cb5
--- /dev/null
+++ b/openfpga_flow/VerilogNetlists/dpram16k.v
@@ -0,0 +1,56 @@
+//-----------------------------------------------------
+// Design Name : dual_port_ram
+// File Name   : dpram.v
+// Function    : Dual port RAM 32x1024 
+// Coder       : Aurelien
+//-----------------------------------------------------
+
+module dpram_512x32 (
+	input clk,
+	input wen,
+	input ren,
+	input[0:9] waddr,
+	input[0:9] raddr,
+	input[0:31] d_in,
+	output[0:31] d_out );
+
+		dual_port_sram memory_0 (
+			.wclk		(clk),
+			.wen		(wen),
+			.waddr		(waddr),
+			.data_in	(d_in),
+			.rclk		(clk),
+			.ren		(ren),
+			.raddr		(raddr),
+			.d_out		(d_out) );
+
+endmodule
+
+module dual_port_sram (
+	input wclk,
+	input wen,
+	input[0:9] waddr,
+	input[0:31] data_in,
+	input rclk,
+	input ren,
+	input[0:9] raddr,
+	output[0:31] d_out );
+
+	reg[0:31] ram[0:1023];
+	reg[0:31] internal;
+
+	assign d_out = internal;
+
+	always @(posedge wclk) begin
+		if(wen) begin
+			ram[waddr] <= data_in;
+		end
+	end
+
+	always @(posedge rclk) begin
+		if(ren) begin
+			internal <= ram[raddr];
+		end
+	end
+
+endmodule
diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_40nm.xml b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_40nm.xml
index eea76837f..c3598bd2b 100644
--- a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_40nm.xml
+++ b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_40nm.xml
@@ -161,7 +161,7 @@
   <!-- Physical descriptions begin -->
   <layout tileable="true">
     <!--auto_layout aspect_ratio="1.0"-->
-    <fixed_layout name="4x4" width="6" height="6">
+    <fixed_layout name="2x2" width="4" height="4">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
       <corners type="EMPTY" priority="101"/>
diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml
index 9422c3a09..49656c706 100644
--- a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml
+++ b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml
@@ -195,7 +195,7 @@
   <!-- Physical descriptions begin -->
   <layout tileable="true" through_channel="false">
     <!--auto_layout aspect_ratio="1.0"-->
-    <fixed_layout name="4x4" width="5" height="4">
+    <fixed_layout name="3x2" width="5" height="4">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
       <corners type="EMPTY" priority="101"/>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
index cb145e06d..eaacadd17 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
@@ -189,7 +189,7 @@
       <port type="output" prefix="sumout" size="1"/>
       <port type="output" prefix="cout" size="1"/>
     </circuit_model>
-    <circuit_model type="hard_logic" name="dpram_512x32" prefix="dpram_512x32" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dpram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dpsram.v">
+    <circuit_model type="hard_logic" name="dpram_512x32" prefix="dpram_512x32" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dpram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dpram16k.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
diff --git a/openfpga_flow/tasks/openfpga_shell/bram/config/task.conf b/openfpga_flow/tasks/openfpga_shell/bram/config/task.conf
new file mode 100644
index 000000000..aeffa9a86
--- /dev/null
+++ b/openfpga_flow/tasks/openfpga_shell/bram/config/task.conf
@@ -0,0 +1,34 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = top
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=
diff --git a/openfpga_flow/tasks/openfpga_shell/hard_adder/config/task.conf b/openfpga_flow/tasks/openfpga_shell/hard_adder/config/task.conf
new file mode 100644
index 000000000..f9fbc97f2
--- /dev/null
+++ b/openfpga_flow/tasks/openfpga_shell/hard_adder/config/task.conf
@@ -0,0 +1,34 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = top
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

From 5d665aa04bd36dd12ca38d8d6220ff8321aa66a9 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 12 Apr 2020 14:32:09 -0600
Subject: [PATCH 422/645] reshape bram test case

---
 .travis/script.sh                                               | 2 +-
 .../tasks/openfpga_shell/bram/{ => dpram16k}/config/task.conf   | 0
 2 files changed, 1 insertion(+), 1 deletion(-)
 rename openfpga_flow/tasks/openfpga_shell/bram/{ => dpram16k}/config/task.conf (100%)

diff --git a/.travis/script.sh b/.travis/script.sh
index 81358c90f..f647a445a 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -58,6 +58,6 @@ echo -e "Testing Verilog generation with hard adder chain in CLBs ";
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/hard_adder --debug --show_thread_logs
 
 echo -e "Testing Verilog generation with 16k block RAMs ";
-python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/bram --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/bram/dpram16k --debug --show_thread_logs
 
 end_section "OpenFPGA.TaskTun"
diff --git a/openfpga_flow/tasks/openfpga_shell/bram/config/task.conf b/openfpga_flow/tasks/openfpga_shell/bram/dpram16k/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/openfpga_shell/bram/config/task.conf
rename to openfpga_flow/tasks/openfpga_shell/bram/dpram16k/config/task.conf

From 28cb41235906626a8d61db6110d79b47b817abb0 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 12 Apr 2020 14:37:08 -0600
Subject: [PATCH 423/645] add test case of wide BRAM 16k to Travis CI

---
 .travis/script.sh                             |  3 ++
 .../bram/wide_dpram16k/config/task.conf       | 35 +++++++++++++++++++
 2 files changed, 38 insertions(+)
 create mode 100644 openfpga_flow/tasks/openfpga_shell/bram/wide_dpram16k/config/task.conf

diff --git a/.travis/script.sh b/.travis/script.sh
index f647a445a..4c82f8128 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -60,4 +60,7 @@ python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/hard_adder --debug
 echo -e "Testing Verilog generation with 16k block RAMs ";
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/bram/dpram16k --debug --show_thread_logs
 
+echo -e "Testing Verilog generation with 16k block RAMs spanning two columns ";
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/bram/wide_dpram16k --debug --show_thread_logs
+
 end_section "OpenFPGA.TaskTun"
diff --git a/openfpga_flow/tasks/openfpga_shell/bram/wide_dpram16k/config/task.conf b/openfpga_flow/tasks/openfpga_shell/bram/wide_dpram16k/config/task.conf
new file mode 100644
index 000000000..53cc5407c
--- /dev/null
+++ b/openfpga_flow/tasks/openfpga_shell/bram/wide_dpram16k/config/task.conf
@@ -0,0 +1,35 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
+
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = top
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

From da5af8f0e0951079a8a301c921b3ab5905470c87 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 12 Apr 2020 14:54:45 -0600
Subject: [PATCH 424/645] try to add aib test case. bug found

---
 openfpga_flow/VerilogNetlists/aib.v           | 19 +++++++++++
 ...0_tileable_adder_chain_mem16K_aib_40nm.xml |  4 +--
 ...0_adder_chain_mem16K_aib_40nm_openfpga.xml |  2 +-
 .../openfpga_shell/io/aib/config/task.conf    | 34 +++++++++++++++++++
 4 files changed, 56 insertions(+), 3 deletions(-)
 create mode 100644 openfpga_flow/VerilogNetlists/aib.v
 create mode 100644 openfpga_flow/tasks/openfpga_shell/io/aib/config/task.conf

diff --git a/openfpga_flow/VerilogNetlists/aib.v b/openfpga_flow/VerilogNetlists/aib.v
new file mode 100644
index 000000000..2ebfd5cea
--- /dev/null
+++ b/openfpga_flow/VerilogNetlists/aib.v
@@ -0,0 +1,19 @@
+//-----------------------------------------------------
+// Design Name : AIB interface
+// File Name   : aib.v
+// Function    : A wrapper for AIB interface
+// Coder       : Xifan Tang
+//-----------------------------------------------------
+
+module aib (
+	input tx_clk,
+	input rx_clk,
+	inout[0:79] pad,
+	input[0:79] tx_data,
+	output[0:79] rx_data);
+
+// May add the logic function of a real AIB
+// Refer to the offical AIB github
+//   https://github.com/intel/aib-phy-hardware
+
+endmodule
diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml
index e196cb83c..2147d392d 100644
--- a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml
+++ b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml
@@ -225,7 +225,7 @@
   <!-- Physical descriptions begin -->
   <layout tileable="true" through_channel="false">
     <!--auto_layout aspect_ratio="1.0"-->
-    <fixed_layout name="4x4" width="7" height="6">
+    <fixed_layout name="3x4" width="5" height="6">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="10"/>
       <corners type="EMPTY" priority="101"/>
@@ -235,7 +235,7 @@
       <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
       <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
       <!-- Single instance of an AIB interface -->
-      <single type="aib" x="6" y="1" priority="20"/>
+      <single type="aib" x="4" y="1" priority="20"/>
     </fixed_layout>
     <!-- /auto_layout -->
   </layout>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
index e65851291..441f10ee4 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
@@ -189,7 +189,7 @@
       <port type="output" prefix="sumout" size="1"/>
       <port type="output" prefix="cout" size="1"/>
     </circuit_model>
-    <circuit_model type="hard_logic" name="dpram_512x32" prefix="dpram_512x32" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dpram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dpsram.v">
+    <circuit_model type="hard_logic" name="dpram_512x32" prefix="dpram_512x32" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dpram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dpram16k.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
diff --git a/openfpga_flow/tasks/openfpga_shell/io/aib/config/task.conf b/openfpga_flow/tasks/openfpga_shell/io/aib/config/task.conf
new file mode 100644
index 000000000..abb9c625f
--- /dev/null
+++ b/openfpga_flow/tasks/openfpga_shell/io/aib/config/task.conf
@@ -0,0 +1,34 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = top
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

From 148cc74d6a79335ae0a6a609e3162e3a989ab0cc Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 12 Apr 2020 15:01:47 -0600
Subject: [PATCH 425/645] add io test cases to Travis CI

---
 .travis/script.sh                             |  6 ++++
 ...er_chain_mem16K_multi_io_capacity_40nm.xml |  2 +-
 ...ble_adder_chain_mem16K_reduced_io_40nm.xml |  2 +-
 .../io/multi_io_capacity/config/task.conf     | 34 +++++++++++++++++++
 .../io/reduced_io/config/task.conf            | 34 +++++++++++++++++++
 5 files changed, 76 insertions(+), 2 deletions(-)
 create mode 100644 openfpga_flow/tasks/openfpga_shell/io/multi_io_capacity/config/task.conf
 create mode 100644 openfpga_flow/tasks/openfpga_shell/io/reduced_io/config/task.conf

diff --git a/.travis/script.sh b/.travis/script.sh
index 4c82f8128..59390a124 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -63,4 +63,10 @@ python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/bram/dpram16k --de
 echo -e "Testing Verilog generation with 16k block RAMs spanning two columns ";
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/bram/wide_dpram16k --debug --show_thread_logs
 
+echo -e "Testing Verilog generation with different I/O capacities on each side of an FPGA ";
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/io/multi_io_capacity --debug --show_thread_logs
+
+echo -e "Testing Verilog generation with I/Os only on left and right sides of an FPGA ";
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/io/reduced_io --debug --show_thread_logs
+
 end_section "OpenFPGA.TaskTun"
diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml
index 8eb6f32bf..a3233edb3 100644
--- a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml
+++ b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml
@@ -226,7 +226,7 @@
   <!-- Physical descriptions begin -->
   <layout tileable="true" through_channel="false">
     <!--auto_layout aspect_ratio="1.0"-->
-    <fixed_layout name="4x4" width="5" height="4">
+    <fixed_layout name="3x2" width="5" height="4">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <row type="io_top" starty="H-1" priority="100"/>
       <row type="io_bottom" starty="0" priority="100"/>
diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml
index 6f8c4cfae..2ed58d2f7 100644
--- a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml
+++ b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml
@@ -195,7 +195,7 @@
   <!-- Physical descriptions begin -->
   <layout tileable="true" through_channel="false">
     <!--auto_layout aspect_ratio="1.0"-->
-    <fixed_layout name="4x4" width="7" height="6">
+    <fixed_layout name="3x2" width="5" height="4">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="10"/>
       <corners type="EMPTY" priority="101"/>
diff --git a/openfpga_flow/tasks/openfpga_shell/io/multi_io_capacity/config/task.conf b/openfpga_flow/tasks/openfpga_shell/io/multi_io_capacity/config/task.conf
new file mode 100644
index 000000000..a3f9081d9
--- /dev/null
+++ b/openfpga_flow/tasks/openfpga_shell/io/multi_io_capacity/config/task.conf
@@ -0,0 +1,34 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = top
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=
diff --git a/openfpga_flow/tasks/openfpga_shell/io/reduced_io/config/task.conf b/openfpga_flow/tasks/openfpga_shell/io/reduced_io/config/task.conf
new file mode 100644
index 000000000..8ed4998db
--- /dev/null
+++ b/openfpga_flow/tasks/openfpga_shell/io/reduced_io/config/task.conf
@@ -0,0 +1,34 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = top
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

From 214d98fbcd8d05bd342229132d84a41b00b087e4 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 12 Apr 2020 15:28:22 -0600
Subject: [PATCH 426/645] add register chain and scan chain to Travis CI

---
 .travis/script.sh                             |  6 ++++
 openfpga_flow/VerilogNetlists/ff.v            | 32 +++++++++++++++++
 ...N10_tileable_adder_register_chain_40nm.xml |  2 +-
 ...ileable_adder_register_scan_chain_40nm.xml |  2 +-
 ...dder_register_scan_chain_40nm_openfpga.xml |  4 +--
 .../register_chain/config/task.conf           | 34 +++++++++++++++++++
 .../fabric_chain/scan_chain/config/task.conf  | 34 +++++++++++++++++++
 7 files changed, 110 insertions(+), 4 deletions(-)
 create mode 100644 openfpga_flow/tasks/openfpga_shell/fabric_chain/register_chain/config/task.conf
 create mode 100644 openfpga_flow/tasks/openfpga_shell/fabric_chain/scan_chain/config/task.conf

diff --git a/.travis/script.sh b/.travis/script.sh
index 59390a124..d6060b13f 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -69,4 +69,10 @@ python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/io/multi_io_capaci
 echo -e "Testing Verilog generation with I/Os only on left and right sides of an FPGA ";
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/io/reduced_io --debug --show_thread_logs
 
+echo -e "Testing Verilog generation with shift register chain across an FPGA";
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/fabric_chain/register_chain --debug --show_thread_logs
+
+echo -e "Testing Verilog generation with scan chain across an FPGA";
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/fabric_chain/scan_chain --debug --show_thread_logs
+
 end_section "OpenFPGA.TaskTun"
diff --git a/openfpga_flow/VerilogNetlists/ff.v b/openfpga_flow/VerilogNetlists/ff.v
index f0097019e..2f2477f24 100644
--- a/openfpga_flow/VerilogNetlists/ff.v
+++ b/openfpga_flow/VerilogNetlists/ff.v
@@ -33,6 +33,38 @@ assign Q = q_reg;
 
 endmodule //End Of Module static_dff
 
+module scan_chain_ff (
+/* Global ports go first */
+input set,     // set input
+input reset, // Reset input
+input clk, // Clock Input
+input TESTEN, // Clock Input
+/* Local ports follow */
+input D, // Data Input
+input DI, // Scan Chain Data Input
+output Q // Q output
+);
+//------------Internal Variables--------
+reg q_reg;
+
+//-------------Code Starts Here---------
+always @ ( posedge clk or posedge reset or posedge set)
+if (reset) begin
+  q_reg <= 1'b0;
+end else if (set) begin
+  q_reg <= 1'b1;
+end else if (TESTEN) begin
+  q_reg <= DI;
+end else begin
+  q_reg <= D;
+end
+
+// Wire q_reg to Q
+assign Q = q_reg;
+
+endmodule //End Of Module static_dff
+
+
 //-----------------------------------------------------
 // Design Name : scan_chain_dff
 // File Name   : ff.v
diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_chain_40nm.xml b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_chain_40nm.xml
index 77dedbcb0..9d2f8aee9 100644
--- a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_chain_40nm.xml
+++ b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_chain_40nm.xml
@@ -165,7 +165,7 @@
   <!-- Physical descriptions begin -->
   <layout tileable="true">
     <!--auto_layout aspect_ratio="1.0"-->
-    <fixed_layout name="4x4" width="6" height="6">
+    <fixed_layout name="2x2" width="4" height="4">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
       <corners type="EMPTY" priority="101"/>
diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml
index f83919c7c..ea1144264 100644
--- a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml
+++ b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml
@@ -180,7 +180,7 @@
   <!-- Physical descriptions begin -->
   <layout tileable="true">
     <!--auto_layout aspect_ratio="1.0"-->
-    <fixed_layout name="4x4" width="6" height="6">
+    <fixed_layout name="2x2" width="4" height="4">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
       <corners type="EMPTY" priority="101"/>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml
index 621847439..e6f6bdb6c 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml
@@ -137,7 +137,7 @@
         This is flip-flop with scan-chain feature.
         When the TESTEN is enabled, the data will be propagated form DI instead of D
       -->
-    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+    <circuit_model type="ff" name="scan_chain_ff" prefix="scan_chain_ff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
@@ -228,7 +228,7 @@
     </pb_type>
     <pb_type name="clb.fle" physical_mode_name="physical"/>
     <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
-    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
+    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="scan_chain_ff"/>
     <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="adder"/>
     <!-- Binding operating pb_type to physical pb_type -->
     <!-- Binding operating pb_types in mode 'n2_lut5' -->
diff --git a/openfpga_flow/tasks/openfpga_shell/fabric_chain/register_chain/config/task.conf b/openfpga_flow/tasks/openfpga_shell/fabric_chain/register_chain/config/task.conf
new file mode 100644
index 000000000..29f1ac4b0
--- /dev/null
+++ b/openfpga_flow/tasks/openfpga_shell/fabric_chain/register_chain/config/task.conf
@@ -0,0 +1,34 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_chain_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = top
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=
diff --git a/openfpga_flow/tasks/openfpga_shell/fabric_chain/scan_chain/config/task.conf b/openfpga_flow/tasks/openfpga_shell/fabric_chain/scan_chain/config/task.conf
new file mode 100644
index 000000000..e1e85366b
--- /dev/null
+++ b/openfpga_flow/tasks/openfpga_shell/fabric_chain/scan_chain/config/task.conf
@@ -0,0 +1,34 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = top
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

From f71a85a1d4027823386d5c13c5bbc05d30165131 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 12 Apr 2020 15:39:45 -0600
Subject: [PATCH 427/645] add test cases on different routing multiplexer
 circuit designs to Travis CI

---
 .travis/script.sh                             |  6 ++++
 .../k6_frac_N10_stdcell_mux_40nm_openfpga.xml | 10 +++---
 .../mux_design/stdcell_mux2/config/task.conf  | 34 +++++++++++++++++++
 .../tree_structure/config/task.conf           | 34 +++++++++++++++++++
 4 files changed, 79 insertions(+), 5 deletions(-)
 create mode 100644 openfpga_flow/tasks/openfpga_shell/mux_design/stdcell_mux2/config/task.conf
 create mode 100644 openfpga_flow/tasks/openfpga_shell/mux_design/tree_structure/config/task.conf

diff --git a/.travis/script.sh b/.travis/script.sh
index d6060b13f..6a852a8b4 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -75,4 +75,10 @@ python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/fabric_chain/regis
 echo -e "Testing Verilog generation with scan chain across an FPGA";
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/fabric_chain/scan_chain --debug --show_thread_logs
 
+echo -e "Testing Verilog generation with routing mutliplexers implemented by tree structure";
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/mux_design/tree_structure --debug --show_thread_logs
+
+echo -e "Testing Verilog generation with routing mutliplexers implemented by standard cell MUX2";
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/mux_design/stdcell_mux2 --debug --show_thread_logs
+
 end_section "OpenFPGA.TaskTun"
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml
index 59f493a13..660e9f003 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml
@@ -82,13 +82,13 @@
          If your standard cell provider does not offer the exact truth table,
          you can simply swap the inputs as shown in the example below
       -->
-    <circuit_model type="gate" name="stdcell_mux2" prefix="stdcell_mux2" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/sc_mux2.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/sc_mux2.v">
+    <circuit_model type="gate" name="MUX2" prefix="MUX2" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/mux2.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/mux2.v">
       <design_technology type="cmos" topology="MUX2"/>
       <input_buffer exist="false"/>
       <output_buffer exist="false"/>
       <port type="input" prefix="in0" lib_name="B" size="1"/>
       <port type="input" prefix="in1" lib_name="A" size="1"/>
-      <port type="input" prefix="sel" lib_name="S" size="1"/>
+      <port type="input" prefix="sel" lib_name="S0" size="1"/>
       <port type="output" prefix="out" lib_name="Y" size="1"/>
     </circuit_model>
     <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
@@ -111,7 +111,7 @@
       <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="stdcell_mux2"/>
+      <pass_gate_logic circuit_model_name="MUX2"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
       <port type="sram" prefix="sram" size="1"/>
@@ -120,7 +120,7 @@
       <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <pass_gate_logic circuit_model_name="stdcell_mux2"/>
+      <pass_gate_logic circuit_model_name="MUX2"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
       <port type="sram" prefix="sram" size="1"/>
@@ -143,7 +143,7 @@
       <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
       <lut_input_buffer exist="true" circuit_model_name="buf4"/>
       <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
-      <pass_gate_logic circuit_model_name="stdcell_mux2"/>
+      <pass_gate_logic circuit_model_name="MUX2"/>
       <port type="input" prefix="in" size="6" tri_state_map="-----1" circuit_model_name="OR2"/>
       <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
       <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
diff --git a/openfpga_flow/tasks/openfpga_shell/mux_design/stdcell_mux2/config/task.conf b/openfpga_flow/tasks/openfpga_shell/mux_design/stdcell_mux2/config/task.conf
new file mode 100644
index 000000000..6ad9d0db0
--- /dev/null
+++ b/openfpga_flow/tasks/openfpga_shell/mux_design/stdcell_mux2/config/task.conf
@@ -0,0 +1,34 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = top
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=
diff --git a/openfpga_flow/tasks/openfpga_shell/mux_design/tree_structure/config/task.conf b/openfpga_flow/tasks/openfpga_shell/mux_design/tree_structure/config/task.conf
new file mode 100644
index 000000000..658e328c0
--- /dev/null
+++ b/openfpga_flow/tasks/openfpga_shell/mux_design/tree_structure/config/task.conf
@@ -0,0 +1,34 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = top
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

From a614e5aad9240a20bc99e40802d985fa5d6384aa Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 12 Apr 2020 15:43:19 -0600
Subject: [PATCH 428/645] add long adder chain to Travis CI

---
 .travis/script.sh                             |  3 ++
 .../fabric_chain/adder_chain/config/task.conf | 34 +++++++++++++++++++
 2 files changed, 37 insertions(+)
 create mode 100644 openfpga_flow/tasks/openfpga_shell/fabric_chain/adder_chain/config/task.conf

diff --git a/.travis/script.sh b/.travis/script.sh
index 6a852a8b4..dc19e3582 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -69,6 +69,9 @@ python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/io/multi_io_capaci
 echo -e "Testing Verilog generation with I/Os only on left and right sides of an FPGA ";
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/io/reduced_io --debug --show_thread_logs
 
+echo -e "Testing Verilog generation with adder chain across an FPGA";
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/fabric_chain/adder_chain --debug --show_thread_logs
+
 echo -e "Testing Verilog generation with shift register chain across an FPGA";
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/fabric_chain/register_chain --debug --show_thread_logs
 
diff --git a/openfpga_flow/tasks/openfpga_shell/fabric_chain/adder_chain/config/task.conf b/openfpga_flow/tasks/openfpga_shell/fabric_chain/adder_chain/config/task.conf
new file mode 100644
index 000000000..348d11cde
--- /dev/null
+++ b/openfpga_flow/tasks/openfpga_shell/fabric_chain/adder_chain/config/task.conf
@@ -0,0 +1,34 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = top
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

From 11e90145427f72ae4cd98bc19a2bcd1c13669824 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 12 Apr 2020 19:07:53 -0600
Subject: [PATCH 429/645] add notes about debugging the aib FPGA

---
 .../tasks/openfpga_shell/io/aib/config/task.conf      | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/openfpga_flow/tasks/openfpga_shell/io/aib/config/task.conf b/openfpga_flow/tasks/openfpga_shell/io/aib/config/task.conf
index abb9c625f..2d08de621 100644
--- a/openfpga_flow/tasks/openfpga_shell/io/aib/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/io/aib/config/task.conf
@@ -17,6 +17,17 @@ timeout_each_job = 20*60
 fpga_flow=vpr_blif
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
 
+#####################################
+# Debugging status 
+# Fail in the following cases
+# - tileable routing is used
+# - vpr routing is used
+# - compressed routing is enabled/disabled
+# - duplicated pin is enabled/disabled
+#
+# Therefore, this could be a bug in the VPR
+####################################
+
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml
 

From 23aef96d3ae5c47a697ad757bcaa5cad2364761f Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 12 Apr 2020 19:55:47 -0600
Subject: [PATCH 430/645] add behavioral verilog test case to Travis CI

---
 .travis/script.sh                             |   3 +
 .../k6_frac_N10_behavioral_40nm_openfpga.xml  | 260 ++++++++++++++++++
 .../behavioral_verilog/config/task.conf       |  34 +++
 3 files changed, 297 insertions(+)
 create mode 100644 openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml
 create mode 100644 openfpga_flow/tasks/openfpga_shell/behavioral_verilog/config/task.conf

diff --git a/.travis/script.sh b/.travis/script.sh
index dc19e3582..3cc2a64b7 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -84,4 +84,7 @@ python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/mux_design/tree_st
 echo -e "Testing Verilog generation with routing mutliplexers implemented by standard cell MUX2";
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/mux_design/stdcell_mux2 --debug --show_thread_logs
 
+echo -e "Testing Verilog generation with behavioral description";
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/behavioral_verilog --debug --show_thread_logs
+
 end_section "OpenFPGA.TaskTun"
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml
new file mode 100644
index 000000000..e305bbc08
--- /dev/null
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml
@@ -0,0 +1,260 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
+      <design_technology type="cmos" topology="OR"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6">
+      <design_technology type="cmos" fracturable_lut="true"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="6" tri_state_map="-----1" circuit_model_name="OR2"/>
+      <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
+      <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
+      <port type="sram" prefix="sram" size="64"/>
+      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="Qb" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+      <port type="input" prefix="outpad" size="1"/>
+      <port type="output" prefix="inpad" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle" physical_mode_name="physical"/>
+    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="0"/>
+    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
+    <!-- Binding operating pb_type to physical pb_type -->
+    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="1" physical_pb_type_index_factor="0.5">
+      <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:4]"/>
+      <port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="0">
+      <!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:5]"/>
+      <port name="out" physical_mode_port="lut6_out"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>
+<openfpga_simulation_setting>
+  <clock_setting>
+    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
+    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
+    <programming frequency="10e6"/>
+  </clock_setting>
+  <simulator_option>
+    <operating_condition temperature="25"/>
+    <output_log verbose="false" captab="false"/>
+    <accuracy type="abs" value="1e-13"/>
+    <runtime fast_simulation="true"/>
+  </simulator_option>
+  <monte_carlo num_simulation_points="2"/>
+  <measurement_setting>
+    <slew>
+      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
+      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
+    </slew>
+    <delay>
+      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
+      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
+    </delay>
+  </measurement_setting>
+  <stimulus>
+    <clock>
+      <rise slew_type="abs" slew_time="20e-12" />
+      <fall slew_type="abs" slew_time="20e-12" />
+    </clock>
+    <input>
+      <rise slew_type="abs" slew_time="25e-12" />
+      <fall slew_type="abs" slew_time="25e-12" />
+    </input>
+  </stimulus>
+</openfpga_simulation_setting>
diff --git a/openfpga_flow/tasks/openfpga_shell/behavioral_verilog/config/task.conf b/openfpga_flow/tasks/openfpga_shell/behavioral_verilog/config/task.conf
new file mode 100644
index 000000000..4d5f90d67
--- /dev/null
+++ b/openfpga_flow/tasks/openfpga_shell/behavioral_verilog/config/task.conf
@@ -0,0 +1,34 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = top
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

From 59ea0a6ad58167867ebbf7728ba479b445145e8d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 12 Apr 2020 20:00:20 -0600
Subject: [PATCH 431/645] add implicit verilog test case to Travis CI

---
 .travis/script.sh                             |  3 +
 .../implicit_verilog_example_script.openfpga  | 61 +++++++++++++++++++
 .../implicit_verilog/config/task.conf         | 34 +++++++++++
 3 files changed, 98 insertions(+)
 create mode 100644 openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga
 create mode 100644 openfpga_flow/tasks/openfpga_shell/implicit_verilog/config/task.conf

diff --git a/.travis/script.sh b/.travis/script.sh
index 3cc2a64b7..402720e8e 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -87,4 +87,7 @@ python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/mux_design/stdcell
 echo -e "Testing Verilog generation with behavioral description";
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/behavioral_verilog --debug --show_thread_logs
 
+echo -e "Testing implicit Verilog generation";
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/implicit_verilog --debug --show_thread_logs
+
 end_section "OpenFPGA.TaskTun"
diff --git a/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga
new file mode 100644
index 000000000..d23534cbe
--- /dev/null
+++ b/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga
@@ -0,0 +1,61 @@
+# Run VPR for the 'and' design
+#--write_rr_graph example_rr_graph.xml
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
+
+# Annotate the OpenFPGA architecture to VPR data base
+# to debug use --verbose options
+link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to clustering nets based on routing results
+pb_pin_fixup --verbose
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup
+
+# Build the module graph
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules
+build_fabric --compress_routing --duplicate_grid_pin #--verbose
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --file fabric_indepenent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file ./SRC --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here
+write_pnr_sdc --file ./SDC
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+write_analysis_sdc --file ./SDC_analysis
+
+# Finish and exit OpenFPGA
+exit
+
+# Note :
+# To run verification at the end of the flow maintain source in ./SRC directory
diff --git a/openfpga_flow/tasks/openfpga_shell/implicit_verilog/config/task.conf b/openfpga_flow/tasks/openfpga_shell/implicit_verilog/config/task.conf
new file mode 100644
index 000000000..9c10e2783
--- /dev/null
+++ b/openfpga_flow/tasks/openfpga_shell/implicit_verilog/config/task.conf
@@ -0,0 +1,34 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = top
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

From e78643f1083a2992f5a7475fb43d39eb01f4bbb1 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 12 Apr 2020 20:06:40 -0600
Subject: [PATCH 432/645] add flatten routing test case to Travis CI

---
 .travis/script.sh                             |  3 +
 .../flatten_routing_example_script.openfpga   | 61 +++++++++++++++++++
 .../flatten_routing/config/task.conf          | 34 +++++++++++
 3 files changed, 98 insertions(+)
 create mode 100644 openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga
 create mode 100644 openfpga_flow/tasks/openfpga_shell/flatten_routing/config/task.conf

diff --git a/.travis/script.sh b/.travis/script.sh
index 402720e8e..9a4f8189d 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -90,4 +90,7 @@ python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/behavioral_verilog
 echo -e "Testing implicit Verilog generation";
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/implicit_verilog --debug --show_thread_logs
 
+echo -e "Testing Verilog generation with flatten routing modules";
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/flatten_routing --debug --show_thread_logs
+
 end_section "OpenFPGA.TaskTun"
diff --git a/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga
new file mode 100644
index 000000000..06a89a4f5
--- /dev/null
+++ b/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga
@@ -0,0 +1,61 @@
+# Run VPR for the 'and' design
+#--write_rr_graph example_rr_graph.xml
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
+
+# Annotate the OpenFPGA architecture to VPR data base
+# to debug use --verbose options
+link_openfpga_arch --activity_file ${ACTIVITY_FILE}
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to clustering nets based on routing results
+pb_pin_fixup --verbose
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup
+
+# Build the module graph
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules
+build_fabric #--verbose
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --file fabric_indepenent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here
+write_pnr_sdc --file ./SDC
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+write_analysis_sdc --file ./SDC_analysis
+
+# Finish and exit OpenFPGA
+exit
+
+# Note :
+# To run verification at the end of the flow maintain source in ./SRC directory
diff --git a/openfpga_flow/tasks/openfpga_shell/flatten_routing/config/task.conf b/openfpga_flow/tasks/openfpga_shell/flatten_routing/config/task.conf
new file mode 100644
index 000000000..bb15c4c43
--- /dev/null
+++ b/openfpga_flow/tasks/openfpga_shell/flatten_routing/config/task.conf
@@ -0,0 +1,34 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = top
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

From 7ba3e2737139ca006819c7e94d8d6deea8157961 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 12 Apr 2020 20:10:51 -0600
Subject: [PATCH 433/645] add duplicated_grid_pin test case to Travis CI

---
 .travis/script.sh                             |  3 +
 ...uplicated_grid_pin_example_script.openfpga | 61 +++++++++++++++++++
 .../example_script.openfpga                   |  4 +-
 .../duplicated_grid_pin/config/task.conf      | 34 +++++++++++
 4 files changed, 100 insertions(+), 2 deletions(-)
 create mode 100644 openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga
 create mode 100644 openfpga_flow/tasks/openfpga_shell/duplicated_grid_pin/config/task.conf

diff --git a/.travis/script.sh b/.travis/script.sh
index 9a4f8189d..126f633d1 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -93,4 +93,7 @@ python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/implicit_verilog -
 echo -e "Testing Verilog generation with flatten routing modules";
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/flatten_routing --debug --show_thread_logs
 
+echo -e "Testing Verilog generation with duplicated grid output pins";
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/duplicated_grid_pin --debug --show_thread_logs
+
 end_section "OpenFPGA.TaskTun"
diff --git a/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga
new file mode 100644
index 000000000..ac808a9a6
--- /dev/null
+++ b/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga
@@ -0,0 +1,61 @@
+# Run VPR for the 'and' design
+#--write_rr_graph example_rr_graph.xml
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
+
+# Annotate the OpenFPGA architecture to VPR data base
+# to debug use --verbose options
+link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to clustering nets based on routing results
+pb_pin_fixup --verbose
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup
+
+# Build the module graph
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules
+build_fabric --compress_routing #--verbose
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --file fabric_indepenent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here
+write_pnr_sdc --file ./SDC
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+write_analysis_sdc --file ./SDC_analysis
+
+# Finish and exit OpenFPGA
+exit
+
+# Note :
+# To run verification at the end of the flow maintain source in ./SRC directory
diff --git a/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
index f584f39d8..ac808a9a6 100644
--- a/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
@@ -21,7 +21,7 @@ lut_truth_table_fixup
 # Build the module graph
 #  - Enabled compression on routing architecture modules
 #  - Enable pin duplication on grid modules
-build_fabric --compress_routing --duplicate_grid_pin #--verbose
+build_fabric --compress_routing #--verbose
 
 # Repack the netlist to physical pbs
 # This must be done before bitstream generator and testbench generation
@@ -58,4 +58,4 @@ write_analysis_sdc --file ./SDC_analysis
 exit
 
 # Note :
-# To run verification at the end of the flow maintain source in ./SRC directory
\ No newline at end of file
+# To run verification at the end of the flow maintain source in ./SRC directory
diff --git a/openfpga_flow/tasks/openfpga_shell/duplicated_grid_pin/config/task.conf b/openfpga_flow/tasks/openfpga_shell/duplicated_grid_pin/config/task.conf
new file mode 100644
index 000000000..7f1f370c6
--- /dev/null
+++ b/openfpga_flow/tasks/openfpga_shell/duplicated_grid_pin/config/task.conf
@@ -0,0 +1,34 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = top
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

From 07a384e440d17f74dfe86486fa0519474d271620 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 13 Apr 2020 11:08:31 -0600
Subject: [PATCH 434/645] now use openfpga tokenizer to trim command line
 string in openfpga shell

---
 libopenfpga/libopenfpgashell/src/shell.tpp           | 12 ++++++------
 .../and_k6_frac_tileable_adder_chain.openfpga        |  4 +++-
 2 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/libopenfpga/libopenfpgashell/src/shell.tpp b/libopenfpga/libopenfpgashell/src/shell.tpp
index 69ec89ab9..05f760e59 100644
--- a/libopenfpga/libopenfpgashell/src/shell.tpp
+++ b/libopenfpga/libopenfpgashell/src/shell.tpp
@@ -311,9 +311,9 @@ void Shell<T>::run_script_mode(const char* script_file_name, T& context) {
     /* Remove the space at the end of the line
      * So that we can check easily if there is a continued line in the end  
      */
-    cmd_part.erase(std::find_if(cmd_part.rbegin(), cmd_part.rend(), [](int ch) {
-      return !std::isspace(ch);
-    }).base(), cmd_part.end());
+    StringToken cmd_part_tokenizer(cmd_part);
+    cmd_part_tokenizer.rtrim(std::string(" "));
+    cmd_part = cmd_part_tokenizer.data();
 
     /* If the line ends with '\', this is a continued line, parse the next until it ends */
     if ('\\' == cmd_part.back()) {
@@ -334,9 +334,9 @@ void Shell<T>::run_script_mode(const char* script_file_name, T& context) {
     }
 
     /* Remove the space at the beginning of the line */
-    cmd_line.erase(cmd_line.begin(), std::find_if(cmd_line.begin(), cmd_line.end(), [](int ch) {
-      return !std::isspace(ch);
-    }));
+    StringToken cmd_line_tokenizer(cmd_line);
+    cmd_line_tokenizer.ltrim(std::string(" "));
+    cmd_line = cmd_line_tokenizer.data();
 
     /* Process the command only when the full command line in ended */
     if (!cmd_line.empty()) {
diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_chain.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_chain.openfpga
index 77fa29aa1..05ea64bce 100644
--- a/openfpga/test_script/and_k6_frac_tileable_adder_chain.openfpga
+++ b/openfpga/test_script/and_k6_frac_tileable_adder_chain.openfpga
@@ -41,7 +41,9 @@ build_fabric_bitstream --verbose
 
 # Write the Verilog netlist for FPGA fabric
 #  - Enable the use of explicit port mapping in Verilog netlist
-write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
+ write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC \
+  --explicit_port_mapping --include_timing --include_signal_init \
+  --support_icarus_simulator --print_user_defined_template --verbose
 
 # Write the Verilog testbench for FPGA fabric
 #  - We suggest the use of same output directory as fabric Verilog netlists

From 56e0d2a918dd9ccf58f61570143b3f820e32d792 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 13 Apr 2020 12:58:44 -0600
Subject: [PATCH 435/645] critical patch on the ccff head and tail connection
 in grid modules for VPR7+OpenFPGA

---
 openfpga/src/fabric/build_grid_modules.cpp                      | 1 +
 vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/openfpga/src/fabric/build_grid_modules.cpp b/openfpga/src/fabric/build_grid_modules.cpp
index 0b693fcec..0d88bdc81 100644
--- a/openfpga/src/fabric/build_grid_modules.cpp
+++ b/openfpga/src/fabric/build_grid_modules.cpp
@@ -289,6 +289,7 @@ void build_primitive_block_module(ModuleManager& module_manager,
     /* Record memory-related information */
     module_manager.add_configurable_child(primitive_module, memory_module, memory_instance_id);
   }
+
   /* Add all the nets to connect configuration ports from memory module to primitive modules
    * This is a one-shot addition that covers all the memory modules in this primitive module!
    */
diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp
index c7578292a..6a98d89c5 100644
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp
@@ -292,7 +292,7 @@ void build_primitive_block_module(ModuleManager& module_manager,
   /* Add all the nets to connect configuration ports from memory module to primitive modules
    * This is a one-shot addition that covers all the memory modules in this primitive module!
    */
-  if (false == memory_modules.empty()) {
+  if (0 < module_manager.configurable_children(primitive_module).size()) {
     add_module_nets_memory_config_bus(module_manager, primitive_module, 
                                       sram_orgz_type, circuit_lib.design_tech_type(sram_model));
   }

From 7f37bf14416b20ce9b5d3beeb89716a8b3b16c78 Mon Sep 17 00:00:00 2001
From: ganeshgore <goreganesh007@gmail.com>
Date: Wed, 15 Apr 2020 12:24:51 -0600
Subject: [PATCH 436/645] Added formal verification support to fpga_flow script

---
 openfpga_flow/scripts/run_fpga_flow.py | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py
index 4c90f6f7c..0d64f864d 100644
--- a/openfpga_flow/scripts/run_fpga_flow.py
+++ b/openfpga_flow/scripts/run_fpga_flow.py
@@ -911,13 +911,23 @@ def run_netlists_verification(exit_if_fail=True):
 
     command = [cad_tools["iverilog_path"]]
     command += ["-o", compiled_file]
-    command += ["./SRC/%s_include_netlists.v" %
-                args.top_module]
+    fpga_define_file = "./SRC/fpga_defines.v"
+    fpga_define_file_bk = "./SRC/fpga_defines.v.bak"
+    shutil.copy(fpga_define_file, fpga_define_file_bk)
+    with open(fpga_define_file, "r") as fp:
+        fpga_defines = fp.readlines()
+
+    command += ["./SRC/%s_include_netlists.v" % args.top_module]
     command += ["-s"]
     if args.vpr_fpga_verilog_formal_verification_top_netlist:
         command += [tb_top_formal]
     else:
         command += [tb_top_autochecked]
+        with open(fpga_define_file, "w") as fp:
+            for eachLine in fpga_defines:
+                if not (("ENABLE_FORMAL_VERIFICATION" in eachLine) or
+                        "FORMAL_SIMULATION" in eachLine):
+                    fp.write(eachLine)
     run_command("iverilog_verification", "iverilog_output.txt", command)
 
     vvp_command = ["vvp", compiled_file]

From 689c4a3e19beb7f0ac4c3dd9f1dedc7d11e691bd Mon Sep 17 00:00:00 2001
From: ganeshgore <goreganesh007@gmail.com>
Date: Wed, 15 Apr 2020 12:44:22 -0600
Subject: [PATCH 437/645] BugFix: The filename in the previous commit

---
 openfpga_flow/scripts/run_fpga_flow.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py
index 0d64f864d..cee4ec2ce 100644
--- a/openfpga_flow/scripts/run_fpga_flow.py
+++ b/openfpga_flow/scripts/run_fpga_flow.py
@@ -911,8 +911,8 @@ def run_netlists_verification(exit_if_fail=True):
 
     command = [cad_tools["iverilog_path"]]
     command += ["-o", compiled_file]
-    fpga_define_file = "./SRC/fpga_defines.v"
-    fpga_define_file_bk = "./SRC/fpga_defines.v.bak"
+    fpga_define_file = "./SRC/define_simulation.v"
+    fpga_define_file_bk = "./SRC/define_simulation.v.bak"
     shutil.copy(fpga_define_file, fpga_define_file_bk)
     with open(fpga_define_file, "r") as fp:
         fpga_defines = fp.readlines()

From 1e742a367689ef34db454de250e2f15196bd208e Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 15 Apr 2020 12:52:52 -0600
Subject: [PATCH 438/645] add test case on auto-check test benches

---
 .../configuration_chain/config/task.conf      | 34 +++++++++++++++++++
 1 file changed, 34 insertions(+)
 create mode 100644 openfpga_flow/tasks/openfpga_shell/configuration_chain/config/task.conf

diff --git a/openfpga_flow/tasks/openfpga_shell/configuration_chain/config/task.conf b/openfpga_flow/tasks/openfpga_shell/configuration_chain/config/task.conf
new file mode 100644
index 000000000..481faab3a
--- /dev/null
+++ b/openfpga_flow/tasks/openfpga_shell/configuration_chain/config/task.conf
@@ -0,0 +1,34 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = top
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+#vpr_fpga_verilog_formal_verification_top_netlist=

From 2ffd174e6a63c224be707bee70eb7225cc8674c8 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 15 Apr 2020 15:48:33 -0600
Subject: [PATCH 439/645] fixed a bug in single mode FPGA; add arch to
 regression test; deploy full testbench verification on Travis CI

---
 .travis/script.sh                             |   3 +
 .../fpga_sdc/analysis_sdc_writer_utils.cpp    |   1 +
 .../fpga_verilog/verilog_top_testbench.cpp    |   4 +-
 .../src/repack/build_physical_truth_table.cpp |  19 +-
 .../k4_N4_tileable_40nm.xml                   | 288 ++++++++++++++++++
 .../arch/vpr_only_templates/k6_N10_40nm.xml   |  10 +-
 .../k6_N10_tileable_40nm.xml                  |  10 +-
 .../openfpga_arch/k4_N4_40nm_openfpga.xml     | 228 ++++++++++++++
 .../configuration_chain/config/task.conf      |   4 +-
 9 files changed, 550 insertions(+), 17 deletions(-)
 create mode 100644 openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml
 create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_openfpga.xml

diff --git a/.travis/script.sh b/.travis/script.sh
index 126f633d1..b577ee48c 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -48,6 +48,9 @@ python3 openfpga_flow/scripts/run_fpga_task.py duplicate_grid_pin --debug --show
 ##############################################
 echo -e "Testing OpenFPGA Shell";
 
+echo -e "Testing configuration chain of a K4N4 FPGA";
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/configuration_chain --debug --show_thread_logs
+
 echo -e "Testing Verilog generation with simple fracturable LUT6 ";
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/frac_lut --debug --show_thread_logs
 
diff --git a/openfpga/src/fpga_sdc/analysis_sdc_writer_utils.cpp b/openfpga/src/fpga_sdc/analysis_sdc_writer_utils.cpp
index f761cafea..1491d161d 100644
--- a/openfpga/src/fpga_sdc/analysis_sdc_writer_utils.cpp
+++ b/openfpga/src/fpga_sdc/analysis_sdc_writer_utils.cpp
@@ -60,6 +60,7 @@ void disable_analysis_module_input_pin_net_sinks(std::fstream& fp,
 
   /* Find the module net which sources from this port! */
   ModuleNetId module_net = module_manager.module_instance_port_net(parent_module, parent_module, 0, module_input_port, module_input_pin); 
+  if (true != module_manager.valid_module_net_id(parent_module, module_net))
   VTR_ASSERT(true == module_manager.valid_module_net_id(parent_module, module_net));
 
   /* Touch each sink of the net! */
diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
index 98d69c337..25017d741 100644
--- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
@@ -273,8 +273,8 @@ void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp,
       continue;
     }
 
-    /* Bypass gp output signals, they do not need any drivers */
-    if (CIRCUIT_MODEL_PORT_OUTPUT == circuit_lib.port_type(model_global_port)) {
+    /* Bypass io signals, they do not need any drivers */
+    if (true == circuit_lib.port_is_io(model_global_port)) {
       continue;
     }
 
diff --git a/openfpga/src/repack/build_physical_truth_table.cpp b/openfpga/src/repack/build_physical_truth_table.cpp
index 5e291d88b..51fc93f93 100644
--- a/openfpga/src/repack/build_physical_truth_table.cpp
+++ b/openfpga/src/repack/build_physical_truth_table.cpp
@@ -17,6 +17,9 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
+/* Mode 1 is the lut mode while mode 0 is the wire mode */
+constexpr int VPR_PB_TYPE_LUT_MODE = 1;
+
 /***************************************************************************************
  * Identify if LUT is used as wiring 
  * In this case, LUT functions as a buffer
@@ -56,9 +59,23 @@ std::vector<int> generate_lut_rotated_input_pin_map(const std::vector<AtomNetId>
   std::vector<int> rotated_pin_map(input_nets.size(), -1);
 
   VTR_ASSERT(1 == pb_graph_node->num_input_ports);
+
   for (int ipin = 0; ipin < pb_graph_node->num_input_pins[0]; ++ipin) {
+    /* The lut pb_graph_node may not be the primitive node 
+     * because VPR adds two default modes to its LUT pb_type
+     * If so, we will use the LUT mode of the pb_graph node
+     */
+    t_port* lut_pb_type_in_port = pb_graph_node->input_pins[0][ipin].port; 
+    if (0 != pb_graph_node->pb_type->num_modes) {
+      VTR_ASSERT(2 == pb_graph_node->pb_type->num_modes);
+      VTR_ASSERT(1 == pb_graph_node->pb_type->modes[VPR_PB_TYPE_LUT_MODE].num_pb_type_children);
+      lut_pb_type_in_port = &(pb_graph_node->pb_type->modes[VPR_PB_TYPE_LUT_MODE].pb_type_children[0].ports[0]);
+      VTR_ASSERT(std::string(lut_pb_type_in_port->name) == std::string(pb_graph_node->input_pins[0][ipin].port->name));
+      VTR_ASSERT(lut_pb_type_in_port->num_pins == pb_graph_node->input_pins[0][ipin].port->num_pins);
+    }
+
     /* Port exists (some LUTs may have no input and hence no port in the atom netlist) */
-    AtomPortId atom_port = atom_ctx.nlist.find_atom_port(atom_blk, pb_graph_node->input_pins[0][ipin].port->model_port);
+    AtomPortId atom_port = atom_ctx.nlist.find_atom_port(atom_blk, lut_pb_type_in_port->model_port);
     if (!atom_port) { 
       continue;
     }
diff --git a/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml b/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml
new file mode 100644
index 000000000..533704db8
--- /dev/null
+++ b/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml
@@ -0,0 +1,288 @@
+<!-- 
+  Architecture with no fracturable LUTs
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 4, N = 4
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Details on Modelling:
+
+  Based on flagship k6_frac_N10_mem32K_40nm.xml architecture.  This architecture has no fracturable LUTs nor any heterogeneous blocks.
+
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <tile name="io" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad</loc>
+        <loc side="top">io.outpad io.inpad</loc>
+        <loc side="right">io.outpad io.inpad</loc>
+        <loc side="bottom">io.outpad io.inpad</loc>
+      </pinlocations>
+    </tile>
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I" num_pins="10" equivalent="full"/>
+      <output name="O" num_pins="4" equivalent="none"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="spread"/>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout tileable="true">
+    <!--auto_layout aspect_ratio="1.0"-->
+    <fixed_layout name="2x2" width="4" height="4">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </fixed_layout>
+    <!--/auto_layout-->
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	  -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+	       book area formula. This means the mux transistors are about 5x minimum drive strength.
+	       We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+	       mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+	       the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+	       by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+	       buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+	       I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+	       (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+	       The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+	       2.5x when looking up in Jeff's tables.
+	       Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+	       This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+			     With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+			     reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" packable="false">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I" num_pins="10" equivalent="full"/>
+      <output name="O" num_pins="4" equivalent="none"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe basic logic element.  
+             Each basic logic element has a 4-LUT that can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="4">
+        <input name="in" num_pins="4"/>
+        <output name="out" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- 4-LUT mode definition begin -->
+        <mode name="n1_lut4">
+          <!-- Define 4-LUT mode -->
+          <pb_type name="ble4" num_pb="1">
+            <input name="in" num_pins="4"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Define LUT -->
+            <pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="4" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                261e-12
+                261e-12
+                261e-12
+                261e-12
+              </delay_matrix>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
+              <direct name="direct2" input="lut4.out" output="ff.D">
+                <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
+                <pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble4.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="ble4.in"/>
+            <direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble4.clk"/>
+          </interconnect>
+        </mode>
+        <!-- 6-LUT mode definition end -->
+      </pb_type>
+      <interconnect>
+        <!-- We use a full crossbar to get logical equivalence at inputs of CLB 
+		     The delays below come from Stratix IV. the delay through a connection block
+		     input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+		     delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+		     delay within the crossbar is 95 ps. 
+		     The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+		     Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+		     25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+		     to get the part that should be marked on the crossbar.	 -->
+        <complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in">
+          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/>
+          <delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
+        </complete>
+        <complete name="clks" input="clb.clk" output="fle[3:0].clk">
+        </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+               By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+               then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+               naive specification).
+          -->
+        <direct name="clbouts1" input="fle[3:0].out" output="clb.O"/>
+      </interconnect>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- Place this general purpose logic block in any unspecified column -->
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+  </complexblocklist>
+</architecture>
diff --git a/openfpga_flow/arch/vpr_only_templates/k6_N10_40nm.xml b/openfpga_flow/arch/vpr_only_templates/k6_N10_40nm.xml
index 630011e84..e94f339c1 100644
--- a/openfpga_flow/arch/vpr_only_templates/k6_N10_40nm.xml
+++ b/openfpga_flow/arch/vpr_only_templates/k6_N10_40nm.xml
@@ -41,13 +41,12 @@
       </equivalent_sites>
       <input name="outpad" num_pins="1"/>
       <output name="inpad" num_pins="1"/>
-      <clock name="clock" num_pins="1"/>
       <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
       <pinlocations pattern="custom">
-        <loc side="left">io.outpad io.inpad io.clock</loc>
-        <loc side="top">io.outpad io.inpad io.clock</loc>
-        <loc side="right">io.outpad io.inpad io.clock</loc>
-        <loc side="bottom">io.outpad io.inpad io.clock</loc>
+        <loc side="left">io.outpad io.inpad</loc>
+        <loc side="top">io.outpad io.inpad</loc>
+        <loc side="right">io.outpad io.inpad</loc>
+        <loc side="bottom">io.outpad io.inpad</loc>
       </pinlocations>
     </tile>
     <tile name="clb" area="53894">
@@ -135,7 +134,6 @@
     <pb_type name="io">
       <input name="outpad" num_pins="1"/>
       <output name="inpad" num_pins="1"/>
-      <clock name="clock" num_pins="1"/>
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
diff --git a/openfpga_flow/arch/vpr_only_templates/k6_N10_tileable_40nm.xml b/openfpga_flow/arch/vpr_only_templates/k6_N10_tileable_40nm.xml
index d86d7aa62..f9065d437 100644
--- a/openfpga_flow/arch/vpr_only_templates/k6_N10_tileable_40nm.xml
+++ b/openfpga_flow/arch/vpr_only_templates/k6_N10_tileable_40nm.xml
@@ -41,13 +41,12 @@
       </equivalent_sites>
       <input name="outpad" num_pins="1"/>
       <output name="inpad" num_pins="1"/>
-      <clock name="clock" num_pins="1"/>
       <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
       <pinlocations pattern="custom">
-        <loc side="left">io.outpad io.inpad io.clock</loc>
-        <loc side="top">io.outpad io.inpad io.clock</loc>
-        <loc side="right">io.outpad io.inpad io.clock</loc>
-        <loc side="bottom">io.outpad io.inpad io.clock</loc>
+        <loc side="left">io.outpad io.inpad</loc>
+        <loc side="top">io.outpad io.inpad</loc>
+        <loc side="right">io.outpad io.inpad</loc>
+        <loc side="bottom">io.outpad io.inpad</loc>
       </pinlocations>
     </tile>
     <tile name="clb" area="53894">
@@ -135,7 +134,6 @@
     <pb_type name="io">
       <input name="outpad" num_pins="1"/>
       <output name="inpad" num_pins="1"/>
-      <clock name="clock" num_pins="1"/>
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_openfpga.xml
new file mode 100644
index 000000000..1d48387ed
--- /dev/null
+++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_openfpga.xml
@@ -0,0 +1,228 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="4"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="16"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="Qb" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+      <port type="input" prefix="outpad" size="1"/>
+      <port type="output" prefix="inpad" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="static_dff"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>
+<openfpga_simulation_setting>
+  <clock_setting>
+    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
+    <programming frequency="10e6"/>
+  </clock_setting>
+  <simulator_option>
+    <operating_condition temperature="25"/>
+    <output_log verbose="false" captab="false"/>
+    <accuracy type="abs" value="1e-13"/>
+    <runtime fast_simulation="true"/>
+  </simulator_option>
+  <monte_carlo num_simulation_points="2"/>
+  <measurement_setting>
+    <slew>
+      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
+      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
+    </slew>
+    <delay>
+      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
+      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
+    </delay>
+  </measurement_setting>
+  <stimulus>
+    <clock>
+      <rise slew_type="abs" slew_time="20e-12" />
+      <fall slew_type="abs" slew_time="20e-12" />
+    </clock>
+    <input>
+      <rise slew_type="abs" slew_time="25e-12" />
+      <fall slew_type="abs" slew_time="25e-12" />
+    </input>
+  </stimulus>
+</openfpga_simulation_setting>
diff --git a/openfpga_flow/tasks/openfpga_shell/configuration_chain/config/task.conf b/openfpga_flow/tasks/openfpga_shell/configuration_chain/config/task.conf
index 481faab3a..7415b96ab 100644
--- a/openfpga_flow/tasks/openfpga_shell/configuration_chain/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/configuration_chain/config/task.conf
@@ -15,10 +15,10 @@ spice_output=false
 verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
-openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_openfpga.xml
 
 [ARCHITECTURES]
-arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_40nm.xml
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml
 
 [BENCHMARKS]
 bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif

From 72e8824a874a80d02ab860df01423372f1b594fa Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 15 Apr 2020 20:41:15 -0600
Subject: [PATCH 440/645] bug fixed on removing undriven pins (direct
 connection between clbs) from cb

---
 openfpga/src/annotation/annotate_rr_graph.cpp | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/openfpga/src/annotation/annotate_rr_graph.cpp b/openfpga/src/annotation/annotate_rr_graph.cpp
index eba72933f..644f4541c 100644
--- a/openfpga/src/annotation/annotate_rr_graph.cpp
+++ b/openfpga/src/annotation/annotate_rr_graph.cpp
@@ -373,6 +373,14 @@ RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx,
                                                   ix, iy, IPIN, ipin_rr_node_grid_side);
     /* Fill the ipin nodes of RRGSB */ 
     for (const RRNodeId& inode : temp_ipin_rr_nodes) {
+      /* Skip those has no configurable outgoing, they should NOT appear in the GSB connection
+       * This is for those grid output pins used by direct connections
+       */
+      if (0 == std::distance(vpr_device_ctx.rr_graph.node_configurable_in_edges(inode).begin(),
+                             vpr_device_ctx.rr_graph.node_configurable_in_edges(inode).end())) {
+        continue;
+      }
+
       /* Do not consider IPINs that are directly connected by an OPIN
        * they are supposed to be handled by direct connection
        */

From a7d900088b6bd36ab1d720eea55664a0cc21df3a Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 15 Apr 2020 20:53:37 -0600
Subject: [PATCH 441/645] now generating simulation ini file will try to create
 directory first

---
 openfpga/src/fpga_verilog/simulation_info_writer.cpp | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/openfpga/src/fpga_verilog/simulation_info_writer.cpp b/openfpga/src/fpga_verilog/simulation_info_writer.cpp
index fbbb7e83c..7c0bf0e3e 100644
--- a/openfpga/src/fpga_verilog/simulation_info_writer.cpp
+++ b/openfpga/src/fpga_verilog/simulation_info_writer.cpp
@@ -12,6 +12,9 @@
 #include "vtr_assert.h"
 #include "vtr_time.h"
 
+/* Headers from openfpgautil library */
+#include "openfpga_digest.h"
+
 #include "simulation_utils.h"
 
 #include "verilog_constants.h"
@@ -34,6 +37,11 @@ void print_verilog_simulation_info(const std::string& ini_fname,
 
   std::string timer_message = std::string("Write exchangeable file containing simulation information '") + ini_fname + std::string("'");
 
+  std::string ini_dir_path = format_dir_path(find_path_dir_name(ini_fname));
+
+  /* Create directories */
+  create_directory(ini_dir_path);
+
   /* Start time count */
   vtr::ScopedStartFinishTimer timer(timer_message);
 

From 2ea4b8a2a24f999d91c8f46778ec95c99cf89136 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 17 Apr 2020 19:12:27 -0600
Subject: [PATCH 442/645] add more flagship architectures

---
 ...adder_register_scan_chain_depop50_40nm.xml | 680 +++++++++++++++
 ...egister_scan_chain_mem16K_depop50_40nm.xml | 781 ++++++++++++++++++
 2 files changed, 1461 insertions(+)
 create mode 100755 openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml
 create mode 100755 openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_40nm.xml

diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml
new file mode 100755
index 000000000..ce1cc258c
--- /dev/null
+++ b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml
@@ -0,0 +1,680 @@
+<!-- Homogeneous FPGA Architecture with Carry Chain for VPR8
+
+  - The chip layout is organized with a 2x2 array of Configurable Logic Blocks (CLBs)
+    surrounded by a ring of I/Os
+  - [TODO] Delay numbers are extracted from a 12 nm technology
+  Author: Xifan Tang, Aurelien Alacchi and Ganesh Gore
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <model name="adder">
+      <input_ports>
+        <port name="a" combinational_sink_ports="sumout cout"/>
+        <port name="b" combinational_sink_ports="sumout cout"/>
+        <port name="cin" combinational_sink_ports="sumout cout"/>
+      </input_ports>
+      <output_ports>
+        <port name="cout"/>
+        <port name="sumout"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="frac_lut6">
+      <input_ports>
+        <port name="in"/>
+      </input_ports>
+      <output_ports>
+        <port name="lut4_out"/>
+        <port name="lut5_out"/>
+        <port name="lut6_out"/>
+      </output_ports>
+    </model>
+    <model name="shift">
+      <input_ports>
+        <port name="D" clock="clk"/>
+        <port name="clk" is_clock="1"/>
+      </input_ports>
+      <output_ports>
+        <port name="Q" clock="clk"/>
+      </output_ports>
+    </model>
+    <model name="scff">
+      <input_ports>
+        <port name="D" clock="clk"/>
+        <port name="D_chain" clock="clk"/>
+        <port name="clk" is_clock="1"/>
+      </input_ports>
+      <output_ports>
+        <port name="Q" clock="clk"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <!-- Each I/O tile includes a GPIO --> 
+    <!-- IOs go on the periphery of the FPGA, for consistency, 
+         make it physically equivalent on all sides so that only one definition of I/Os is needed.
+         If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+      -->
+    <tile name="io" capacity="1" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <!-- Each input of the tile can be driven by 15% of routing tracks
+           Each output of the tile can drive 10% of routing tracks
+        -->
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad</loc>
+        <loc side="top">io.outpad io.inpad</loc>
+        <loc side="right">io.outpad io.inpad</loc>
+        <loc side="bottom">io.outpad io.inpad</loc>
+      </pinlocations>
+    </tile>
+    <!-- Each CLB tile includes a Configurable Logic Block (CLB)
+         Each input of the tile can be driven by 15% of routing tracks
+         Each output of the tile can drive 10% of routing tracks
+      -->
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I0" num_pins="10" equivalent="full"/>
+      <input name="I1" num_pins="10" equivalent="full"/>
+      <input name="I2" num_pins="10" equivalent="full"/>
+      <input name="I3" num_pins="10" equivalent="full"/>
+      <input name="sc_in" num_pins="1"/>
+      <input name="cin" num_pins="1"/>
+      <input name="cin_trick" num_pins="1"/>
+      <input name="regin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="sc_out" num_pins="1"/>
+      <output name="cout" num_pins="1"/>
+      <output name="cout_copy" num_pins="1"/>
+      <output name="regout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Each input of the tile can be driven by 15% of routing tracks
+           Each output of the tile can drive 10% of routing tracks
+           There are four pins (cin, cout, sc_in, sc_out) has not connection 
+           to routing tracks. There are directed wired from/to adjacent CLBs
+        -->
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="sc_in" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="sc_out" fc_type="frac" fc_val="0"/>
+      </fc>
+      <!-- Highly recommand to customize pin location when direct connection is used!!! -->
+      <!-- To ensure best tileable routing architecture (minimize the number of unique SBs
+           We keep all the pins that touch routing architecture on the right and bottom sides of the tile
+           Top side pins are mainly for direct connections
+        -->
+      <pinlocations pattern="custom">
+        <loc side="left"></loc>
+        <loc side="top">clb.sc_in clb.cin clb.cin_trick clb.regin clb.clk</loc>
+        <loc side="right">clb.I0[9:0] clb.I1[9:0] clb.O[9:0]</loc>
+        <loc side="bottom">clb.cout clb.cout_copy clb.sc_out clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10]</loc>
+      </pinlocations>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <!-- Apply tileable routing architecture.
+       This is strongly recommended if you want to PnR large FPGA fabric
+    -->
+  <layout tileable="true">
+    <!--auto_layout aspect_ratio="1.0"-->
+    <!-- Apply a fixed layout of 2x2 core array.
+         VPR8 considers the I/O ring in the array size
+         Therefore the height and width are both 4
+      -->
+    <fixed_layout name="32x32" width="34" height="34">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </fixed_layout>
+    <!-- /auto_layout -->
+  </layout>
+  <device>
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+         area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+      -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <!-- Use Wilton-style connecting pattern in switch block 
+         Each routing track has access to only three other routing tracks
+         (one per each side of the switch block except the side where the routing track locates)
+      -->
+    <switch_block type="wilton" fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
+    <!-- Uni-directional routing architecture using only length-4 wires in routing channels -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <directlist>
+    <!-- Hard adder chain inside CLB is directly connected between adjacent CLBs -->
+    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
+    <!-- Scan chain inside CLB is directly connected between adjacent CLBs -->
+    <direct name="scff_chain" from_pin="clb.sc_out" to_pin="clb.sc_in" x_offset="0" y_offset="-1" z_offset="0"/>
+  </directlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+
+      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+           If you need to register the I/O, define clocks in the circuit models
+           These clocks can be handled in back-end
+       -->
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" packable="false">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+
+      <!-- IOs can operate as either inputs or outputs.
+       Delays below come from Ian Kuon. They are small, so they should be interpreted as
+       the delays to and from registers in the I/O (and generally I/Os are registered 
+       today and that is when you timing analyze them.
+       -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define multi-mode Configurable Logic Block (CLB) begin -->
+    <!-- Technical highlight:
+         K6_frac_N10_I40_chain_shiftreg_depop50
+         - K6_frac: Each Logic Element (LE) contains a fracturable 6 LUT,
+                    which can operate as one 6-LUT or two 5-LUTs or four 4-LUTs 
+                    In addition to 6-LUT, each LE also includes two Flip-Flops
+         - N10: every CLB consists of 10 LEs and a local routing architecture
+         - I40: every CLB has 40 inputs
+         - chain: a hard adder chain across all the LEs in a CLB
+                  The inputs of adder are driven by 4-LUTs.
+                  The sumout of adder can optional drive an LE output or a Flip-Flop
+                  The carry-out of adder will drive the carry-in of the next adder in the chain
+         - shiftreg: Flip-flops inside CLB can be configured as shift registers.
+                     The organization is similar the hard adder chain except it is programmable
+         - depop50: every local routing multiplexer accesses to 50% of the CLB inputs
+      -->
+    <pb_type name="clb">
+      <input name="I0" num_pins="10" equivalent="full"/>
+      <input name="I1" num_pins="10" equivalent="full"/>
+      <input name="I2" num_pins="10" equivalent="full"/>
+      <input name="I3" num_pins="10" equivalent="full"/>
+      <input name="sc_in" num_pins="1"/>
+      <input name="cin" num_pins="1"/>
+      <input name="cin_trick" num_pins="1"/>
+      <input name="regin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="sc_out" num_pins="1"/>
+      <output name="cout" num_pins="1"/>
+      <output name="cout_copy" num_pins="1"/>
+      <output name="regout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+
+      <!-- Describe fracturable logic element -->
+      <pb_type name="fle" num_pb="10">
+        <input name="in" num_pins="6"/>
+        <input name="cin" num_pins="1"/>
+        <input name="sc_in" num_pins="1"/>
+        <input name="regin" num_pins="1"/>
+        <output name="out" num_pins="2"/>
+        <output name="cout" num_pins="1"/>
+        <output name="sc_out" num_pins="1"/>
+        <output name="regout" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+
+        <!-- Describe physical mode begins -->
+        <mode name="physical" packable="false">
+          <pb_type name="frac_logic" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <input name="cin" num_pins="1"/>
+            <input name="regin" num_pins="1"/>
+            <input name="regchain" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
+              <input name="in" num_pins="6"/>
+              <output name="lut4_out" num_pins="4"/>
+              <output name="lut5_out" num_pins="2"/>
+              <output name="lut6_out" num_pins="1"/>
+            </pb_type>
+            <pb_type name="adder_phy" blif_model=".subckt adder" num_pb="2">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder_phy.a" out_port="adder_phy.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder_phy.b" out_port="adder_phy.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder_phy.cin" out_port="adder_phy.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder_phy.a" out_port="adder_phy.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder_phy.b" out_port="adder_phy.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder_phy.cin" out_port="adder_phy.cout"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct_fraclut_in" input="frac_logic.in[5:0]" output="frac_lut6.in[5:0]"/>
+              <direct name="direct_cin" input="frac_logic.cin" output="adder_phy[0].cin"/>
+              <direct name="direct_carry" input="adder_phy[0].cout" output="adder_phy[1].cin"/>
+              <direct name="direct_cout" input="adder_phy[1].cout" output="frac_logic.cout"/>
+              <direct name="direct_lut4carry0" input="frac_lut6.lut4_out[0]" output="adder_phy[0].a"/>
+              <direct name="direct_lut4carry1" input="frac_lut6.lut4_out[1]" output="adder_phy[0].b"/>
+              <direct name="direct_lut4carry2" input="frac_lut6.lut4_out[2]" output="adder_phy[1].a"/>
+              <direct name="direct_lut4carry3" input="frac_lut6.lut4_out[3]" output="adder_phy[1].b"/>
+              <mux name="mux1" input="adder_phy[0].sumout frac_lut6.lut5_out[0] frac_logic.regin" output="frac_logic.out[0]">
+              </mux>
+              <mux name="mux2" input="adder_phy[1].sumout frac_lut6.lut5_out[1] frac_lut6.lut6_out[0] frac_logic.regchain[0]" output="frac_logic.out[1]">
+              </mux>
+            </interconnect>
+          </pb_type>
+          <pb_type name="ff_phy" blif_model=".subckt scff" num_pb="2">
+            <input name="D" num_pins="1"/>
+            <input name="D_chain" num_pins="1"/>
+            <output name="Q" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <T_setup value="66e-12" port="ff_phy.D" clock="clk"/>
+            <T_setup value="66e-12" port="ff_phy.D_chain" clock="clk"/>
+            <T_clock_to_Q max="124e-12" port="ff_phy.Q" clock="clk"/>
+          </pb_type>
+          <interconnect>
+            <complete name="direct_clk" input="fle.clk" output="ff_phy[1:0].clk"/>
+            <direct name="direct_in" input="fle.in[5:0]" output="frac_logic.in[5:0]"/>
+            <direct name="direct_regin" input="fle.regin" output="frac_logic.regin"/>
+            <direct name="direct_regchain" input="ff_phy[0].Q" output="frac_logic.regchain"/>
+            <direct name="direct_regout" input="ff_phy[1].Q" output="fle.regout"/>
+            <direct name="direct_cin" input="fle.cin" output="frac_logic.cin"/>
+            <direct name="direct_cout" input="frac_logic.cout" output="fle.cout"/>
+            <direct name="direct_frac_out1" input="frac_logic.out[0]" output="ff_phy[0].D"/>
+            <direct name="direct_frac_out2" input="frac_logic.out[1]" output="ff_phy[1].D"/>
+            <direct name="direct_fle_scin" input="fle.sc_in" output="ff_phy[0].D_chain"/>
+            <direct name="direct_fle_sc_chain" input="ff_phy[0].Q" output="ff_phy[1].D_chain"/>
+            <direct name="direct_fle_scout" input="ff_phy[1].Q" output="fle.sc_out"/>
+            <mux name="mux1" input="ff_phy[0].Q frac_logic.out[0]" output="fle.out[0]">
+            </mux>
+            <mux name="mux2" input="ff_phy[1].Q frac_logic.out[1]" output="fle.out[1]">
+            </mux>
+          </interconnect>
+        </mode>
+        <!-- Define physical mode begins -->
+        <!-- Define n2_lut5 mode begins -->
+        <mode name="n2_lut5" packable="true">
+          <pb_type name="lut5inter" num_pb="1">
+            <input name="in" num_pins="5"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="ble5" num_pb="2">
+              <input name="in" num_pins="5"/>
+              <input name="cin" num_pins="1"/>
+              <output name="out" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <clock name="clk" num_pins="1"/>
+              <mode name="blut5">
+                <pb_type name="flut5" num_pb="1">
+                  <input name="in" num_pins="5"/>
+                  <output name="out" num_pins="1"/>
+                  <clock name="clk" num_pins="1"/>
+                  <!-- Regular LUT mode -->
+                  <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
+                    <input name="in" num_pins="5" port_class="lut_in"/>
+                    <output name="out" num_pins="1" port_class="lut_out"/>
+                    <!-- LUT timing using delay matrix -->
+                    <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
+                        202e-12
+                        202e-12
+                        202e-12
+                        202e-12
+                        202e-12
+                    </delay_matrix>
+                  </pb_type>
+
+                  <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+                    <input name="D" num_pins="1" port_class="D"/>
+                    <output name="Q" num_pins="1" port_class="Q"/>
+                    <clock name="clk" num_pins="1" port_class="clock"/>
+                    <T_setup value="66e-12" port="ff.D" clock="clk"/>
+                    <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+                  </pb_type>
+                  <interconnect>
+                    <direct name="direct1" input="flut5.in" output="lut5.in"/>
+                    <direct name="direct2" input="lut5.out" output="ff.D">
+                      <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
+                    </direct>
+                    <direct name="direct3" input="flut5.clk" output="ff.clk"/>
+                    <mux name="mux1" input="ff.Q lut5.out" output="flut5.out">
+                      <delay_constant max="25e-12" in_port="lut5.out" out_port="flut5.out" />
+                      <delay_constant max="45e-12" in_port="ff.Q" out_port="flut5.out" />
+                    </mux>
+                  </interconnect>
+                </pb_type>
+                <interconnect>
+                  <direct name="direct1" input="ble5.in" output="flut5.in"/>
+                  <direct name="direct2" input="ble5.clk" output="flut5.clk"/>
+                  <direct name="direct3" input="flut5.out" output="ble5.out"/>
+                </interconnect>
+              </mode>
+              <mode name="arithmetic">
+                <pb_type name="arithmetic" num_pb="1">
+                  <input name="in" num_pins="4"/>
+                  <input name="cin" num_pins="1"/>
+                  <output name="out" num_pins="1"/>
+                  <output name="cout" num_pins="1"/>
+                  <clock name="clk" num_pins="1"/>
+                  <!-- Special dual-LUT mode that drives adder only -->
+                  <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
+                    <input name="in" num_pins="4" port_class="lut_in"/>
+                    <output name="out" num_pins="1" port_class="lut_out"/>
+                    <!-- LUT timing using delay matrix -->
+                    <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                        180e-12
+                        180e-12
+                        180e-12
+                        180e-12
+                    </delay_matrix>
+                  </pb_type>
+                  <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
+                    <input name="a" num_pins="1"/>
+                    <input name="b" num_pins="1"/>
+                    <input name="cin" num_pins="1"/>
+                    <output name="cout" num_pins="1"/>
+                    <output name="sumout" num_pins="1"/>
+                    <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+                    <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+                    <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+                    <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+                    <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+                    <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.cout"/>
+                  </pb_type>
+                  <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+                    <input name="D" num_pins="1" port_class="D"/>
+                    <output name="Q" num_pins="1" port_class="Q"/>
+                    <clock name="clk" num_pins="1" port_class="clock"/>
+                    <T_setup value="66e-12" port="ff.D" clock="clk"/>
+                    <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+                  </pb_type>
+                  <interconnect>
+                    <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
+                    <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
+                    <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
+                    <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
+                    </direct>
+                    <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
+                    </direct>
+                    <direct name="add_to_ff" input="adder.sumout" output="ff.D">
+                      <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
+                    </direct>
+                    <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
+                      <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
+                    </direct>
+                    <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
+                      <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
+                    </direct>
+                    <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
+                      <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
+                      <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out" />
+                    </mux>
+                  </interconnect>
+                </pb_type>
+
+                <interconnect>
+                  <direct name="direct1" input="ble5.in[3:0]" output="arithmetic.in"/>
+                  <direct name="carry_in" input="ble5.cin" output="arithmetic.cin">
+                    <!--pack_pattern name="chain" in_port="ble5.cin" out_port="arithmetic.cin"/-->
+                  </direct>
+                  <direct name="carry_out" input="arithmetic.cout" output="ble5.cout">
+                    <!--pack_pattern name="chain" in_port="arithmetic.cout" out_port="ble5.cout"/-->
+                  </direct>
+                  <direct name="direct2" input="ble5.clk" output="arithmetic.clk"/>
+                  <direct name="direct3" input="arithmetic.out" output="ble5.out"/>
+                </interconnect>
+              </mode>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="lut5inter.in" output="ble5[0:0].in"/>
+              <direct name="direct2" input="lut5inter.in" output="ble5[1:1].in"/>
+              <direct name="direct3" input="ble5[1:0].out" output="lut5inter.out"/>
+              <direct name="carry_in" input="lut5inter.cin" output="ble5[0:0].cin">
+                <!--pack_pattern name="chain" in_port="lut5inter.cin" out_port="ble5[0:0].cin"/-->
+              </direct>
+              <direct name="carry_out" input="ble5[1:1].cout" output="lut5inter.cout">
+                <!--pack_pattern name="chain" in_port="ble5[1:1].cout" out_port="lut5inter.cout"/-->
+              </direct>
+              <direct name="carry_link" input="ble5[0:0].cout" output="ble5[1:1].cin">
+                <!--pack_pattern name="chain" in_port="ble5[0:0].cout" out_port="ble5[1:1].cout"/-->
+              </direct>
+              <complete name="complete1" input="lut5inter.clk" output="ble5[1:0].clk"/>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[4:0]" output="lut5inter.in"/>
+            <direct name="direct2" input="lut5inter.out" output="fle.out"/>
+            <direct name="direct3" input="fle.clk" output="lut5inter.clk"/>
+            <direct name="carry_in" input="fle.cin" output="lut5inter.cin">
+              <!--pack_pattern name="chain" in_port="fle.cin" out_port="lut5inter.cin"/-->
+            </direct>
+            <direct name="carry_out" input="lut5inter.cout" output="fle.cout">
+              <!--pack_pattern name="chain" in_port="lut5inter.cout" out_port="fle.cout"/-->
+            </direct>
+          </interconnect>
+        </mode>
+        <!-- Define n2_lut5 mode ends -->
+        <mode name="n1_lut6">
+          <pb_type name="ble6" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="6" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                  229e-12
+                  229e-12
+                  229e-12
+                  229e-12
+                  229e-12
+                  229e-12
+              </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+
+            <interconnect>
+              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+              <direct name="direct2" input="lut6.out" output="ff.D">
+                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out" />
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out" />
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="ble6.in"/>
+            <direct name="direct2" input="ble6.out" output="fle.out[1:1]"/>
+            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Define n1_lut6 mode ends -->
+        <!-- Define shift register mode begins -->
+        <mode name="shift_register">
+          <pb_type name="ble_shift" num_pb="1">
+            <input name="in" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="regout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="ff" blif_model=".subckt shift" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble_shift.in" output="ff[0].D"/>
+              <direct name="direct2" input="ff[0].Q" output="ff[1].D">
+                <!--pack_pattern name="ble_shift" in_port="ff[0].Q" out_port="ff[1].D"/-->
+              </direct>
+              <direct name="out1" input="ff[0].Q" output="ble_shift.out[0]"/>
+              <direct name="out2" input="ff[1].Q" output="ble_shift.out[1]"/>
+              <direct name="direct_regout" input="ff[1].Q" output="ble_shift.regout"/>
+              <complete name="direct3" input="ble_shift.clk" output="ff[1:0].clk"/>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.regin" output="ble_shift.in"/>
+            <direct name="direct2" input="ble_shift.out" output="fle.out"/>
+            <direct name="direct3" input="fle.clk" output="ble_shift.clk"/>
+            <direct name="direct4" input="ble_shift.regout" output="fle.regout"/>
+          </interconnect>
+        </mode>
+       <!-- Define shift_register mode end -->
+      </pb_type>
+      <interconnect>
+        <complete name="crossbar0" input="clb.I2 clb.I3 fle[9:0].out" output="fle[9:0].in[0]">
+          <delay_constant max="190e-12" in_port="clb.I2 clb.I3" out_port="fle[9:0].in[0]" />
+          <delay_constant max="190e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[0]" />
+        </complete>
+        <complete name="crossbar1" input="clb.I1 clb.I2 fle[9:0].out" output="fle[9:0].in[1]">
+          <delay_constant max="190e-12" in_port="clb.I1 clb.I2" out_port="fle[9:0].in[1]" />
+          <delay_constant max="190e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[1]" />
+        </complete>
+        <complete name="crossbar2" input="clb.I0 clb.I1 fle[9:0].out" output="fle[9:0].in[2]">
+          <delay_constant max="190e-12" in_port="clb.I0 clb.I1" out_port="fle[9:0].in[2]" />
+          <delay_constant max="190e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[2]" />
+        </complete>
+        <complete name="crossbar3" input="clb.I1 clb.I3 fle[9:0].out" output="fle[9:0].in[3]">
+          <delay_constant max="190e-12" in_port="clb.I1 clb.I3" out_port="fle[9:0].in[3]" />
+          <delay_constant max="190e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[3]" />
+        </complete>
+        <complete name="crossbar4" input="clb.I0 clb.I2 fle[9:0].out" output="fle[9:0].in[4]">
+          <delay_constant max="190e-12" in_port="clb.I0 clb.I2" out_port="fle[9:0].in[4]" />
+          <delay_constant max="190e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[4]" />
+        </complete>
+        <complete name="crossbar5" input="clb.I0 clb.I3 fle[9:0].out" output="fle[9:0].in[5]">
+        </complete>
+        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+        </complete>
+        <complete name="carry_in" input="clb.cin clb.cin_trick fle[9:0].out" output="fle[0:0].cin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <!--delay_constant max="0.15e-9" in_port="clb.cin clb.cin_trick" out_port="fle[0:0].cin"/-->
+          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
+          <!--pack_pattern name="chain" in_port="clb.cin_trick" out_port="fle[0:0].cin"/-->
+        </complete>
+
+        <!--direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
+          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
+        </direct-->
+        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
+        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
+        <direct name="cout_copy" input="fle[9:9].cout" output="clb.cout_copy"/>
+
+        <!-- Shift register links -->
+        <direct name="regin" input="clb.regin" output="fle[0:0].regin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.15e-9" in_port="clb.regin" out_port="fle[0:0].regin"/>
+          <pack_pattern name="chain" in_port="clb.regin" out_port="fle[0:0].regin"/>
+        </direct>
+        <direct name="regout" input="fle[9:9].regout" output="clb.regout">
+          <pack_pattern name="chain" in_port="fle[9:9].regout" out_port="clb.regout"/>
+        </direct>
+        <direct name="reg_link" input="fle[8:0].regout" output="fle[9:1].regin">
+          <pack_pattern name="chain" in_port="fle[8:0].regout" out_port="fle[9:1].regin"/>
+        </direct>
+        <!-- Carry chain links -->
+        <direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
+          <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
+        </direct>
+        <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
+          <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
+        </direct>
+        <!-- Scan chain links -->
+        <direct name="sc_in" input="clb.sc_in" output="fle[0:0].sc_in">
+        </direct>
+        <direct name="sc_out" input="fle[9:9].sc_out" output="clb.sc_out">
+        </direct>
+        <direct name="sc_link" input="fle[8:0].sc_out" output="fle[9:1].sc_in">
+        </direct>
+      </interconnect>
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+  </complexblocklist>
+</architecture>
diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_40nm.xml b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_40nm.xml
new file mode 100755
index 000000000..37b5e17d9
--- /dev/null
+++ b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_40nm.xml
@@ -0,0 +1,781 @@
+<!-- Homogeneous FPGA Architecture with Carry Chain for VPR8
+
+  - The chip layout is organized with a 2x2 array of Configurable Logic Blocks (CLBs)
+    surrounded by a ring of I/Os
+  - [TODO] Delay numbers are extracted from a 12 nm technology
+  Author: Xifan Tang, Aurelien Alacchi and Ganesh Gore
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <model name="adder">
+      <input_ports>
+        <port name="a" combinational_sink_ports="sumout cout"/>
+        <port name="b" combinational_sink_ports="sumout cout"/>
+        <port name="cin" combinational_sink_ports="sumout cout"/>
+      </input_ports>
+      <output_ports>
+        <port name="cout"/>
+        <port name="sumout"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="frac_lut6">
+      <input_ports>
+        <port name="in"/>
+      </input_ports>
+      <output_ports>
+        <port name="lut4_out"/>
+        <port name="lut5_out"/>
+        <port name="lut6_out"/>
+      </output_ports>
+    </model>
+    <model name="shift">
+      <input_ports>
+        <port name="D" clock="clk"/>
+        <port name="clk" is_clock="1"/>
+      </input_ports>
+      <output_ports>
+        <port name="Q" clock="clk"/>
+      </output_ports>
+    </model>
+    <model name="scff">
+      <input_ports>
+        <port name="D" clock="clk"/>
+        <port name="D_chain" clock="clk"/>
+        <port name="clk" is_clock="1"/>
+      </input_ports>
+      <output_ports>
+        <port name="Q" clock="clk"/>
+      </output_ports>
+    </model>
+    <model name="dual_port_ram">
+      <input_ports>
+        <!-- write address lines -->
+        <port name="waddr" clock="clk"/>
+        <!-- read address lines -->
+        <port name="raddr" clock="clk"/>
+        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
+        <port name="d_in" clock="clk"/>
+        <!-- write enable -->
+        <port name="wen" clock="clk"/>
+        <!-- read enable -->
+        <port name="ren" clock="clk"/>
+        <!-- memories are often clocked -->
+        <port name="clk" is_clock="1"/>
+      </input_ports>
+      <output_ports>
+        <!-- output can be broken down into smaller bit widths minimum size 1 -->
+        <port name="d_out" clock="clk"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <!-- Each I/O tile includes a GPIO --> 
+    <!-- IOs go on the periphery of the FPGA, for consistency, 
+         make it physically equivalent on all sides so that only one definition of I/Os is needed.
+         If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+      -->
+    <tile name="io" capacity="1" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <!-- Each input of the tile can be driven by 15% of routing tracks
+           Each output of the tile can drive 10% of routing tracks
+        -->
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad</loc>
+        <loc side="top">io.outpad io.inpad</loc>
+        <loc side="right">io.outpad io.inpad</loc>
+        <loc side="bottom">io.outpad io.inpad</loc>
+      </pinlocations>
+    </tile>
+    <!-- Each CLB tile includes a Configurable Logic Block (CLB)
+         Each input of the tile can be driven by 15% of routing tracks
+         Each output of the tile can drive 10% of routing tracks
+      -->
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I0" num_pins="10" equivalent="full"/>
+      <input name="I1" num_pins="10" equivalent="full"/>
+      <input name="I2" num_pins="10" equivalent="full"/>
+      <input name="I3" num_pins="10" equivalent="full"/>
+      <input name="sc_in" num_pins="1"/>
+      <input name="cin" num_pins="1"/>
+      <input name="cin_trick" num_pins="1"/>
+      <input name="regin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="sc_out" num_pins="1"/>
+      <output name="cout" num_pins="1"/>
+      <output name="cout_copy" num_pins="1"/>
+      <output name="regout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Each input of the tile can be driven by 15% of routing tracks
+           Each output of the tile can drive 10% of routing tracks
+           There are four pins (cin, cout, sc_in, sc_out) has not connection 
+           to routing tracks. There are directed wired from/to adjacent CLBs
+        -->
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="sc_in" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="sc_out" fc_type="frac" fc_val="0"/>
+      </fc>
+      <!-- Highly recommand to customize pin location when direct connection is used!!! -->
+      <!-- To ensure best tileable routing architecture (minimize the number of unique SBs
+           We keep all the pins that touch routing architecture on the right and bottom sides of the tile
+           Top side pins are mainly for direct connections
+        -->
+      <pinlocations pattern="custom">
+        <loc side="left"></loc>
+        <loc side="top">clb.sc_in clb.cin clb.cin_trick clb.regin clb.clk</loc>
+        <loc side="right">clb.I0[9:0] clb.I1[9:0] clb.O[9:0]</loc>
+        <loc side="bottom">clb.cout clb.cout_copy clb.sc_out clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10]</loc>
+      </pinlocations>
+    </tile>
+    <tile name="memory" height="2" area="548000">
+      <equivalent_sites>
+        <site pb_type="memory"/>
+      </equivalent_sites>
+      <input name="waddr" num_pins="10"/>
+      <input name="raddr" num_pins="10"/>
+      <input name="d_in" num_pins="32"/>
+      <input name="wen" num_pins="1"/>
+      <input name="ren" num_pins="1"/>
+      <output name="d_out" num_pins="32"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left"></loc>
+        <loc side="top">memory.clk</loc>
+        <loc side="right">memory.waddr memory.d_in[15:0] memory.wen memory.d_out[15:0]</loc>
+        <loc side="bottom">memory.raddr memory.d_in[31:16] memory.ren memory.d_out[31:16]</loc>
+      </pinlocations>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <!-- Apply tileable routing architecture.
+       This is strongly recommended if you want to PnR large FPGA fabric
+    -->
+  <layout tileable="true">
+    <!--auto_layout aspect_ratio="1.0"-->
+    <!-- Apply a fixed layout of 2x2 core array.
+         VPR8 considers the I/O ring in the array size
+         Therefore the height and width are both 4
+      -->
+    <fixed_layout name="32x32" width="34" height="34">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="memory" startx="16" starty="1" repeatx="16" priority="20"/>
+      <col type="EMPTY" startx="16" repeatx="16" starty="1" priority="19"/>
+    </fixed_layout>
+    <!-- /auto_layout -->
+  </layout>
+  <device>
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+         area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+      -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <!-- Use Wilton-style connecting pattern in switch block 
+         Each routing track has access to only three other routing tracks
+         (one per each side of the switch block except the side where the routing track locates)
+      -->
+    <switch_block type="wilton" fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
+    <!-- Uni-directional routing architecture using only length-4 wires in routing channels -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <directlist>
+    <!-- Hard adder chain inside CLB is directly connected between adjacent CLBs -->
+    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
+    <!-- Scan chain inside CLB is directly connected between adjacent CLBs -->
+    <direct name="scff_chain" from_pin="clb.sc_out" to_pin="clb.sc_in" x_offset="0" y_offset="-1" z_offset="0"/>
+  </directlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+
+      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+           If you need to register the I/O, define clocks in the circuit models
+           These clocks can be handled in back-end
+       -->
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" packable="false">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+
+      <!-- IOs can operate as either inputs or outputs.
+       Delays below come from Ian Kuon. They are small, so they should be interpreted as
+       the delays to and from registers in the I/O (and generally I/Os are registered 
+       today and that is when you timing analyze them.
+       -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define multi-mode Configurable Logic Block (CLB) begin -->
+    <!-- Technical highlight:
+         K6_frac_N10_I40_chain_shiftreg_depop50
+         - K6_frac: Each Logic Element (LE) contains a fracturable 6 LUT,
+                    which can operate as one 6-LUT or two 5-LUTs or four 4-LUTs 
+                    In addition to 6-LUT, each LE also includes two Flip-Flops
+         - N10: every CLB consists of 10 LEs and a local routing architecture
+         - I40: every CLB has 40 inputs
+         - chain: a hard adder chain across all the LEs in a CLB
+                  The inputs of adder are driven by 4-LUTs.
+                  The sumout of adder can optional drive an LE output or a Flip-Flop
+                  The carry-out of adder will drive the carry-in of the next adder in the chain
+         - shiftreg: Flip-flops inside CLB can be configured as shift registers.
+                     The organization is similar the hard adder chain except it is programmable
+         - depop50: every local routing multiplexer accesses to 50% of the CLB inputs
+      -->
+    <pb_type name="clb">
+      <input name="I0" num_pins="10" equivalent="full"/>
+      <input name="I1" num_pins="10" equivalent="full"/>
+      <input name="I2" num_pins="10" equivalent="full"/>
+      <input name="I3" num_pins="10" equivalent="full"/>
+      <input name="sc_in" num_pins="1"/>
+      <input name="cin" num_pins="1"/>
+      <input name="cin_trick" num_pins="1"/>
+      <input name="regin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="sc_out" num_pins="1"/>
+      <output name="cout" num_pins="1"/>
+      <output name="cout_copy" num_pins="1"/>
+      <output name="regout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+
+      <!-- Describe fracturable logic element -->
+      <pb_type name="fle" num_pb="10">
+        <input name="in" num_pins="6"/>
+        <input name="cin" num_pins="1"/>
+        <input name="sc_in" num_pins="1"/>
+        <input name="regin" num_pins="1"/>
+        <output name="out" num_pins="2"/>
+        <output name="cout" num_pins="1"/>
+        <output name="sc_out" num_pins="1"/>
+        <output name="regout" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+
+        <!-- Describe physical mode begins -->
+        <mode name="physical" packable="false">
+          <pb_type name="frac_logic" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <input name="cin" num_pins="1"/>
+            <input name="regin" num_pins="1"/>
+            <input name="regchain" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
+              <input name="in" num_pins="6"/>
+              <output name="lut4_out" num_pins="4"/>
+              <output name="lut5_out" num_pins="2"/>
+              <output name="lut6_out" num_pins="1"/>
+            </pb_type>
+            <pb_type name="adder_phy" blif_model=".subckt adder" num_pb="2">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder_phy.a" out_port="adder_phy.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder_phy.b" out_port="adder_phy.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder_phy.cin" out_port="adder_phy.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder_phy.a" out_port="adder_phy.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder_phy.b" out_port="adder_phy.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder_phy.cin" out_port="adder_phy.cout"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct_fraclut_in" input="frac_logic.in[5:0]" output="frac_lut6.in[5:0]"/>
+              <direct name="direct_cin" input="frac_logic.cin" output="adder_phy[0].cin"/>
+              <direct name="direct_carry" input="adder_phy[0].cout" output="adder_phy[1].cin"/>
+              <direct name="direct_cout" input="adder_phy[1].cout" output="frac_logic.cout"/>
+              <direct name="direct_lut4carry0" input="frac_lut6.lut4_out[0]" output="adder_phy[0].a"/>
+              <direct name="direct_lut4carry1" input="frac_lut6.lut4_out[1]" output="adder_phy[0].b"/>
+              <direct name="direct_lut4carry2" input="frac_lut6.lut4_out[2]" output="adder_phy[1].a"/>
+              <direct name="direct_lut4carry3" input="frac_lut6.lut4_out[3]" output="adder_phy[1].b"/>
+              <mux name="mux1" input="adder_phy[0].sumout frac_lut6.lut5_out[0] frac_logic.regin" output="frac_logic.out[0]">
+              </mux>
+              <mux name="mux2" input="adder_phy[1].sumout frac_lut6.lut5_out[1] frac_lut6.lut6_out[0] frac_logic.regchain[0]" output="frac_logic.out[1]">
+              </mux>
+            </interconnect>
+          </pb_type>
+          <pb_type name="ff_phy" blif_model=".subckt scff" num_pb="2">
+            <input name="D" num_pins="1"/>
+            <input name="D_chain" num_pins="1"/>
+            <output name="Q" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <T_setup value="66e-12" port="ff_phy.D" clock="clk"/>
+            <T_setup value="66e-12" port="ff_phy.D_chain" clock="clk"/>
+            <T_clock_to_Q max="124e-12" port="ff_phy.Q" clock="clk"/>
+          </pb_type>
+          <interconnect>
+            <complete name="direct_clk" input="fle.clk" output="ff_phy[1:0].clk"/>
+            <direct name="direct_in" input="fle.in[5:0]" output="frac_logic.in[5:0]"/>
+            <direct name="direct_regin" input="fle.regin" output="frac_logic.regin"/>
+            <direct name="direct_regchain" input="ff_phy[0].Q" output="frac_logic.regchain"/>
+            <direct name="direct_regout" input="ff_phy[1].Q" output="fle.regout"/>
+            <direct name="direct_cin" input="fle.cin" output="frac_logic.cin"/>
+            <direct name="direct_cout" input="frac_logic.cout" output="fle.cout"/>
+            <direct name="direct_frac_out1" input="frac_logic.out[0]" output="ff_phy[0].D"/>
+            <direct name="direct_frac_out2" input="frac_logic.out[1]" output="ff_phy[1].D"/>
+            <direct name="direct_fle_scin" input="fle.sc_in" output="ff_phy[0].D_chain"/>
+            <direct name="direct_fle_sc_chain" input="ff_phy[0].Q" output="ff_phy[1].D_chain"/>
+            <direct name="direct_fle_scout" input="ff_phy[1].Q" output="fle.sc_out"/>
+            <mux name="mux1" input="ff_phy[0].Q frac_logic.out[0]" output="fle.out[0]">
+            </mux>
+            <mux name="mux2" input="ff_phy[1].Q frac_logic.out[1]" output="fle.out[1]">
+            </mux>
+          </interconnect>
+        </mode>
+        <!-- Define physical mode begins -->
+        <!-- Define n2_lut5 mode begins -->
+        <mode name="n2_lut5" packable="true">
+          <pb_type name="lut5inter" num_pb="1">
+            <input name="in" num_pins="5"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="ble5" num_pb="2">
+              <input name="in" num_pins="5"/>
+              <input name="cin" num_pins="1"/>
+              <output name="out" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <clock name="clk" num_pins="1"/>
+              <mode name="blut5">
+                <pb_type name="flut5" num_pb="1">
+                  <input name="in" num_pins="5"/>
+                  <output name="out" num_pins="1"/>
+                  <clock name="clk" num_pins="1"/>
+                  <!-- Regular LUT mode -->
+                  <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
+                    <input name="in" num_pins="5" port_class="lut_in"/>
+                    <output name="out" num_pins="1" port_class="lut_out"/>
+                    <!-- LUT timing using delay matrix -->
+                    <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
+                        202e-12
+                        202e-12
+                        202e-12
+                        202e-12
+                        202e-12
+                    </delay_matrix>
+                  </pb_type>
+
+                  <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+                    <input name="D" num_pins="1" port_class="D"/>
+                    <output name="Q" num_pins="1" port_class="Q"/>
+                    <clock name="clk" num_pins="1" port_class="clock"/>
+                    <T_setup value="66e-12" port="ff.D" clock="clk"/>
+                    <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+                  </pb_type>
+                  <interconnect>
+                    <direct name="direct1" input="flut5.in" output="lut5.in"/>
+                    <direct name="direct2" input="lut5.out" output="ff.D">
+                      <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
+                    </direct>
+                    <direct name="direct3" input="flut5.clk" output="ff.clk"/>
+                    <mux name="mux1" input="ff.Q lut5.out" output="flut5.out">
+                      <delay_constant max="25e-12" in_port="lut5.out" out_port="flut5.out" />
+                      <delay_constant max="45e-12" in_port="ff.Q" out_port="flut5.out" />
+                    </mux>
+                  </interconnect>
+                </pb_type>
+                <interconnect>
+                  <direct name="direct1" input="ble5.in" output="flut5.in"/>
+                  <direct name="direct2" input="ble5.clk" output="flut5.clk"/>
+                  <direct name="direct3" input="flut5.out" output="ble5.out"/>
+                </interconnect>
+              </mode>
+              <mode name="arithmetic">
+                <pb_type name="arithmetic" num_pb="1">
+                  <input name="in" num_pins="4"/>
+                  <input name="cin" num_pins="1"/>
+                  <output name="out" num_pins="1"/>
+                  <output name="cout" num_pins="1"/>
+                  <clock name="clk" num_pins="1"/>
+                  <!-- Special dual-LUT mode that drives adder only -->
+                  <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
+                    <input name="in" num_pins="4" port_class="lut_in"/>
+                    <output name="out" num_pins="1" port_class="lut_out"/>
+                    <!-- LUT timing using delay matrix -->
+                    <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                        180e-12
+                        180e-12
+                        180e-12
+                        180e-12
+                    </delay_matrix>
+                  </pb_type>
+                  <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
+                    <input name="a" num_pins="1"/>
+                    <input name="b" num_pins="1"/>
+                    <input name="cin" num_pins="1"/>
+                    <output name="cout" num_pins="1"/>
+                    <output name="sumout" num_pins="1"/>
+                    <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+                    <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+                    <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+                    <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+                    <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+                    <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.cout"/>
+                  </pb_type>
+                  <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+                    <input name="D" num_pins="1" port_class="D"/>
+                    <output name="Q" num_pins="1" port_class="Q"/>
+                    <clock name="clk" num_pins="1" port_class="clock"/>
+                    <T_setup value="66e-12" port="ff.D" clock="clk"/>
+                    <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+                  </pb_type>
+                  <interconnect>
+                    <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
+                    <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
+                    <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
+                    <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
+                    </direct>
+                    <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
+                    </direct>
+                    <direct name="add_to_ff" input="adder.sumout" output="ff.D">
+                      <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
+                    </direct>
+                    <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
+                      <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
+                    </direct>
+                    <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
+                      <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
+                    </direct>
+                    <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
+                      <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
+                      <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out" />
+                    </mux>
+                  </interconnect>
+                </pb_type>
+
+                <interconnect>
+                  <direct name="direct1" input="ble5.in[3:0]" output="arithmetic.in"/>
+                  <direct name="carry_in" input="ble5.cin" output="arithmetic.cin">
+                    <!--pack_pattern name="chain" in_port="ble5.cin" out_port="arithmetic.cin"/-->
+                  </direct>
+                  <direct name="carry_out" input="arithmetic.cout" output="ble5.cout">
+                    <!--pack_pattern name="chain" in_port="arithmetic.cout" out_port="ble5.cout"/-->
+                  </direct>
+                  <direct name="direct2" input="ble5.clk" output="arithmetic.clk"/>
+                  <direct name="direct3" input="arithmetic.out" output="ble5.out"/>
+                </interconnect>
+              </mode>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="lut5inter.in" output="ble5[0:0].in"/>
+              <direct name="direct2" input="lut5inter.in" output="ble5[1:1].in"/>
+              <direct name="direct3" input="ble5[1:0].out" output="lut5inter.out"/>
+              <direct name="carry_in" input="lut5inter.cin" output="ble5[0:0].cin">
+                <!--pack_pattern name="chain" in_port="lut5inter.cin" out_port="ble5[0:0].cin"/-->
+              </direct>
+              <direct name="carry_out" input="ble5[1:1].cout" output="lut5inter.cout">
+                <!--pack_pattern name="chain" in_port="ble5[1:1].cout" out_port="lut5inter.cout"/-->
+              </direct>
+              <direct name="carry_link" input="ble5[0:0].cout" output="ble5[1:1].cin">
+                <!--pack_pattern name="chain" in_port="ble5[0:0].cout" out_port="ble5[1:1].cout"/-->
+              </direct>
+              <complete name="complete1" input="lut5inter.clk" output="ble5[1:0].clk"/>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[4:0]" output="lut5inter.in"/>
+            <direct name="direct2" input="lut5inter.out" output="fle.out"/>
+            <direct name="direct3" input="fle.clk" output="lut5inter.clk"/>
+            <direct name="carry_in" input="fle.cin" output="lut5inter.cin">
+              <!--pack_pattern name="chain" in_port="fle.cin" out_port="lut5inter.cin"/-->
+            </direct>
+            <direct name="carry_out" input="lut5inter.cout" output="fle.cout">
+              <!--pack_pattern name="chain" in_port="lut5inter.cout" out_port="fle.cout"/-->
+            </direct>
+          </interconnect>
+        </mode>
+        <!-- Define n2_lut5 mode ends -->
+        <mode name="n1_lut6">
+          <pb_type name="ble6" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="6" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                  229e-12
+                  229e-12
+                  229e-12
+                  229e-12
+                  229e-12
+                  229e-12
+              </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+
+            <interconnect>
+              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+              <direct name="direct2" input="lut6.out" output="ff.D">
+                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out" />
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out" />
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="ble6.in"/>
+            <direct name="direct2" input="ble6.out" output="fle.out[1:1]"/>
+            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Define n1_lut6 mode ends -->
+        <!-- Define shift register mode begins -->
+        <mode name="shift_register">
+          <pb_type name="ble_shift" num_pb="1">
+            <input name="in" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="regout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="ff" blif_model=".subckt shift" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble_shift.in" output="ff[0].D"/>
+              <direct name="direct2" input="ff[0].Q" output="ff[1].D">
+                <!--pack_pattern name="ble_shift" in_port="ff[0].Q" out_port="ff[1].D"/-->
+              </direct>
+              <direct name="out1" input="ff[0].Q" output="ble_shift.out[0]"/>
+              <direct name="out2" input="ff[1].Q" output="ble_shift.out[1]"/>
+              <direct name="direct_regout" input="ff[1].Q" output="ble_shift.regout"/>
+              <complete name="direct3" input="ble_shift.clk" output="ff[1:0].clk"/>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.regin" output="ble_shift.in"/>
+            <direct name="direct2" input="ble_shift.out" output="fle.out"/>
+            <direct name="direct3" input="fle.clk" output="ble_shift.clk"/>
+            <direct name="direct4" input="ble_shift.regout" output="fle.regout"/>
+          </interconnect>
+        </mode>
+       <!-- Define shift_register mode end -->
+      </pb_type>
+      <interconnect>
+        <complete name="crossbar0" input="clb.I2 clb.I3 fle[9:0].out" output="fle[9:0].in[0]">
+          <delay_constant max="190e-12" in_port="clb.I2 clb.I3" out_port="fle[9:0].in[0]" />
+          <delay_constant max="190e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[0]" />
+        </complete>
+        <complete name="crossbar1" input="clb.I1 clb.I2 fle[9:0].out" output="fle[9:0].in[1]">
+          <delay_constant max="190e-12" in_port="clb.I1 clb.I2" out_port="fle[9:0].in[1]" />
+          <delay_constant max="190e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[1]" />
+        </complete>
+        <complete name="crossbar2" input="clb.I0 clb.I1 fle[9:0].out" output="fle[9:0].in[2]">
+          <delay_constant max="190e-12" in_port="clb.I0 clb.I1" out_port="fle[9:0].in[2]" />
+          <delay_constant max="190e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[2]" />
+        </complete>
+        <complete name="crossbar3" input="clb.I1 clb.I3 fle[9:0].out" output="fle[9:0].in[3]">
+          <delay_constant max="190e-12" in_port="clb.I1 clb.I3" out_port="fle[9:0].in[3]" />
+          <delay_constant max="190e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[3]" />
+        </complete>
+        <complete name="crossbar4" input="clb.I0 clb.I2 fle[9:0].out" output="fle[9:0].in[4]">
+          <delay_constant max="190e-12" in_port="clb.I0 clb.I2" out_port="fle[9:0].in[4]" />
+          <delay_constant max="190e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[4]" />
+        </complete>
+        <complete name="crossbar5" input="clb.I0 clb.I3 fle[9:0].out" output="fle[9:0].in[5]">
+        </complete>
+        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+        </complete>
+        <complete name="carry_in" input="clb.cin clb.cin_trick fle[9:0].out" output="fle[0:0].cin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <!--delay_constant max="0.15e-9" in_port="clb.cin clb.cin_trick" out_port="fle[0:0].cin"/-->
+          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
+          <!--pack_pattern name="chain" in_port="clb.cin_trick" out_port="fle[0:0].cin"/-->
+        </complete>
+
+        <!--direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
+          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
+        </direct-->
+        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
+        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
+        <direct name="cout_copy" input="fle[9:9].cout" output="clb.cout_copy"/>
+
+        <!-- Shift register links -->
+        <direct name="regin" input="clb.regin" output="fle[0:0].regin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.15e-9" in_port="clb.regin" out_port="fle[0:0].regin"/>
+          <pack_pattern name="chain" in_port="clb.regin" out_port="fle[0:0].regin"/>
+        </direct>
+        <direct name="regout" input="fle[9:9].regout" output="clb.regout">
+          <pack_pattern name="chain" in_port="fle[9:9].regout" out_port="clb.regout"/>
+        </direct>
+        <direct name="reg_link" input="fle[8:0].regout" output="fle[9:1].regin">
+          <pack_pattern name="chain" in_port="fle[8:0].regout" out_port="fle[9:1].regin"/>
+        </direct>
+        <!-- Carry chain links -->
+        <direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
+          <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
+        </direct>
+        <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
+          <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
+        </direct>
+        <!-- Scan chain links -->
+        <direct name="sc_in" input="clb.sc_in" output="fle[0:0].sc_in">
+        </direct>
+        <direct name="sc_out" input="fle[9:9].sc_out" output="clb.sc_out">
+        </direct>
+        <direct name="sc_link" input="fle[8:0].sc_out" output="fle[9:1].sc_in">
+        </direct>
+      </interconnect>
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+    <!-- Define single-mode dual-port memory begin -->
+    <pb_type name="memory">
+      <input name="waddr" num_pins="10"/>
+      <input name="raddr" num_pins="10"/>
+      <input name="d_in" num_pins="32"/>
+      <input name="wen" num_pins="1"/>
+      <input name="ren" num_pins="1"/>
+      <output name="d_out" num_pins="32"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Specify the 512x32=16Kbit memory block
+           Note: the delay numbers are extracted from VPR flagship XML without modification
+                 Should align to the process technology we using to create the 16K dual-port RAM
+        -->
+      <mode name="mem_512x32_dp">
+        <pb_type name="mem_512x32_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
+          <input name="waddr" num_pins="10" port_class="address"/>
+          <input name="raddr" num_pins="10" port_class="address"/>
+          <input name="d_in" num_pins="32" port_class="data_in"/>
+          <input name="wen" num_pins="1" port_class="write_en"/>
+          <input name="ren" num_pins="1" port_class="write_en"/>
+          <output name="d_out" num_pins="32" port_class="data_out"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.waddr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.raddr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.d_in" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.wen" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.ren" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_512x32_dp.d_out" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="17.9e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="waddress" input="memory.waddr" output="mem_512x32_dp.waddr">
+            <delay_constant max="132e-12" in_port="memory.waddr" out_port="mem_512x32_dp.waddr"/>
+          </direct>
+          <direct name="raddress" input="memory.raddr" output="mem_512x32_dp.raddr">
+            <delay_constant max="132e-12" in_port="memory.raddr" out_port="mem_512x32_dp.raddr"/>
+          </direct>
+          <direct name="data_input" input="memory.d_in" output="mem_512x32_dp.d_in">
+            <delay_constant max="132e-12" in_port="memory.d_in" out_port="mem_512x32_dp.d_in"/>
+          </direct>
+          <direct name="writeen" input="memory.wen" output="mem_512x32_dp.wen">
+            <delay_constant max="132e-12" in_port="memory.wen" out_port="mem_512x32_dp.wen"/>
+          </direct>
+          <direct name="readen" input="memory.ren" output="mem_512x32_dp.ren">
+            <delay_constant max="132e-12" in_port="memory.ren" out_port="mem_512x32_dp.ren"/>
+          </direct>
+          <direct name="dataout" input="mem_512x32_dp.d_out" output="memory.d_out">
+            <delay_constant max="40e-12" in_port="mem_512x32_dp.d_out" out_port="memory.d_out"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_512x32_dp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+    </pb_type>
+    <!-- Define single-mode dual-port memory end -->
+
+  </complexblocklist>
+</architecture>

From 7ce34be175fabde71de28b176b0212de34e189c3 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 17 Apr 2020 22:06:06 -0600
Subject: [PATCH 443/645] update sample architecture timing

---
 ...egister_scan_chain_mem16K_depop50_40nm.xml | 120 +++++++++---------
 1 file changed, 63 insertions(+), 57 deletions(-)

diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_40nm.xml b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_40nm.xml
index 37b5e17d9..1e2808f66 100755
--- a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_40nm.xml
+++ b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_40nm.xml
@@ -181,7 +181,7 @@
        This is strongly recommended if you want to PnR large FPGA fabric
     -->
   <layout tileable="true">
-    <!--auto_layout aspect_ratio="1.0"-->
+    <!-- auto_layout aspect_ratio="1.0" -->
     <!-- Apply a fixed layout of 2x2 core array.
          VPR8 considers the I/O ring in the array size
          Therefore the height and width are both 4
@@ -196,7 +196,7 @@
       <col type="memory" startx="16" starty="1" repeatx="16" priority="20"/>
       <col type="EMPTY" startx="16" repeatx="16" starty="1" priority="19"/>
     </fixed_layout>
-    <!-- /auto_layout -->
+    <!--/auto_layout-->
   </layout>
   <device>
     <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
@@ -216,13 +216,13 @@
     <connection_block input_switch_name="ipin_cblock"/>
   </device>
   <switchlist>
-    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
-    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+    <switch type="mux" name="0" R="0" Cin="0" Cout="0" Tdel="160e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <switch type="mux" name="ipin_cblock" R="0." Cout="0." Cin="0" Tdel="207e-12" mux_trans_size="1.222260" buf_size="auto"/>
   </switchlist>
   <segmentlist>
     <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
     <!-- Uni-directional routing architecture using only length-4 wires in routing channels -->
-    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="0" Cmetal="0">
       <mux name="0"/>
       <sb type="pattern">1 1 1 1 1</sb>
       <cb type="pattern">1 1 1 1</cb>
@@ -256,10 +256,10 @@
         </pb_type>
         <interconnect>
           <direct name="outpad" input="io.outpad" output="iopad.outpad">
-            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+            <delay_constant max="0" in_port="io.outpad" out_port="iopad.outpad"/>
           </direct>
           <direct name="inpad" input="iopad.inpad" output="io.inpad">
-            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+            <delay_constant max="0" in_port="iopad.inpad" out_port="io.inpad"/>
           </direct>
         </interconnect>
       </mode>
@@ -275,7 +275,7 @@
         </pb_type>
         <interconnect>
           <direct name="inpad" input="inpad.inpad" output="io.inpad">
-            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+            <delay_constant max="0" in_port="inpad.inpad" out_port="io.inpad"/>
           </direct>
         </interconnect>
       </mode>
@@ -285,7 +285,7 @@
         </pb_type>
         <interconnect>
           <direct name="outpad" input="io.outpad" output="outpad.outpad">
-            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+            <delay_constant max="0" in_port="io.outpad" out_port="outpad.outpad"/>
           </direct>
         </interconnect>
       </mode>
@@ -433,11 +433,11 @@
                     <output name="out" num_pins="1" port_class="lut_out"/>
                     <!-- LUT timing using delay matrix -->
                     <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
-                        202e-12
-                        202e-12
-                        202e-12
-                        202e-12
-                        202e-12
+                        193e-12
+                        193e-12
+                        193e-12
+                        193e-12
+                        193e-12
                     </delay_matrix>
                   </pb_type>
 
@@ -445,8 +445,8 @@
                     <input name="D" num_pins="1" port_class="D"/>
                     <output name="Q" num_pins="1" port_class="Q"/>
                     <clock name="clk" num_pins="1" port_class="clock"/>
-                    <T_setup value="66e-12" port="ff.D" clock="clk"/>
-                    <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+                    <T_setup value="26e-12" port="ff.D" clock="clk"/>
+                    <T_clock_to_Q max="46e-12" port="ff.Q" clock="clk"/>
                   </pb_type>
                   <interconnect>
                     <direct name="direct1" input="flut5.in" output="lut5.in"/>
@@ -455,8 +455,8 @@
                     </direct>
                     <direct name="direct3" input="flut5.clk" output="ff.clk"/>
                     <mux name="mux1" input="ff.Q lut5.out" output="flut5.out">
-                      <delay_constant max="25e-12" in_port="lut5.out" out_port="flut5.out" />
-                      <delay_constant max="45e-12" in_port="ff.Q" out_port="flut5.out" />
+                      <delay_constant max="112e-12" in_port="lut5.out" out_port="flut5.out" />
+                      <delay_constant max="48e-12" in_port="ff.Q" out_port="flut5.out" />
                     </mux>
                   </interconnect>
                 </pb_type>
@@ -479,10 +479,10 @@
                     <output name="out" num_pins="1" port_class="lut_out"/>
                     <!-- LUT timing using delay matrix -->
                     <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
-                        180e-12
-                        180e-12
-                        180e-12
-                        180e-12
+                        161e-12
+                        161e-12
+                        161e-12
+                        161e-12
                     </delay_matrix>
                   </pb_type>
                   <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
@@ -491,19 +491,19 @@
                     <input name="cin" num_pins="1"/>
                     <output name="cout" num_pins="1"/>
                     <output name="sumout" num_pins="1"/>
-                    <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
-                    <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
-                    <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
-                    <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
-                    <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
-                    <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.cout"/>
+                    <delay_constant max="26e-12" in_port="adder.a" out_port="adder.sumout"/>
+                    <delay_constant max="26e-12" in_port="adder.b" out_port="adder.sumout"/>
+                    <delay_constant max="26e-12" in_port="adder.cin" out_port="adder.sumout"/>
+                    <delay_constant max="26e-12" in_port="adder.a" out_port="adder.cout"/>
+                    <delay_constant max="26e-12" in_port="adder.b" out_port="adder.cout"/>
+                    <delay_constant max="26e-12" in_port="adder.cin" out_port="adder.cout"/>
                   </pb_type>
                   <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
                     <input name="D" num_pins="1" port_class="D"/>
                     <output name="Q" num_pins="1" port_class="Q"/>
                     <clock name="clk" num_pins="1" port_class="clock"/>
-                    <T_setup value="66e-12" port="ff.D" clock="clk"/>
-                    <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+                    <T_setup value="26e-12" port="ff.D" clock="clk"/>
+                    <T_clock_to_Q max="46e-12" port="ff.Q" clock="clk"/>
                   </pb_type>
                   <interconnect>
                     <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
@@ -523,8 +523,8 @@
                       <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
                     </direct>
                     <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
-                      <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
-                      <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out" />
+                      <delay_constant max="112e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
+                      <delay_constant max="48e-12" in_port="ff.Q" out_port="arithmetic.out" />
                     </mux>
                   </interconnect>
                 </pb_type>
@@ -581,20 +581,20 @@
               <output name="out" num_pins="1" port_class="lut_out"/>
               <!-- LUT timing using delay matrix -->
               <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
-                  229e-12
-                  229e-12
-                  229e-12
-                  229e-12
-                  229e-12
-                  229e-12
+                  230e-12
+                  230e-12
+                  230e-12
+                  230e-12
+                  230e-12
+                  230e-12
               </delay_matrix>
             </pb_type>
             <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
               <input name="D" num_pins="1" port_class="D"/>
               <output name="Q" num_pins="1" port_class="Q"/>
               <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+              <T_setup value="26e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="46e-12" port="ff.Q" clock="clk"/>
             </pb_type>
 
             <interconnect>
@@ -604,8 +604,8 @@
               </direct>
               <direct name="direct3" input="ble6.clk" output="ff.clk"/>
               <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
-                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out" />
-                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out" />
+                <delay_constant max="112e-12" in_port="lut6.out" out_port="ble6.out" />
+                <delay_constant max="48e-12" in_port="ff.Q" out_port="ble6.out" />
               </mux>
             </interconnect>
           </pb_type>
@@ -627,8 +627,8 @@
               <input name="D" num_pins="1" port_class="D"/>
               <output name="Q" num_pins="1" port_class="Q"/>
               <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+              <T_setup value="26e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="46e-12" port="ff.Q" clock="clk"/>
             </pb_type>
             <interconnect>
               <direct name="direct1" input="ble_shift.in" output="ff[0].D"/>
@@ -652,26 +652,28 @@
       </pb_type>
       <interconnect>
         <complete name="crossbar0" input="clb.I2 clb.I3 fle[9:0].out" output="fle[9:0].in[0]">
-          <delay_constant max="190e-12" in_port="clb.I2 clb.I3" out_port="fle[9:0].in[0]" />
-          <delay_constant max="190e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[0]" />
+          <delay_constant max="230e-12" in_port="clb.I2 clb.I3" out_port="fle[9:0].in[0]" />
+          <delay_constant max="230e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[0]" />
         </complete>
         <complete name="crossbar1" input="clb.I1 clb.I2 fle[9:0].out" output="fle[9:0].in[1]">
-          <delay_constant max="190e-12" in_port="clb.I1 clb.I2" out_port="fle[9:0].in[1]" />
-          <delay_constant max="190e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[1]" />
+          <delay_constant max="230e-12" in_port="clb.I1 clb.I2" out_port="fle[9:0].in[1]" />
+          <delay_constant max="230e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[1]" />
         </complete>
         <complete name="crossbar2" input="clb.I0 clb.I1 fle[9:0].out" output="fle[9:0].in[2]">
-          <delay_constant max="190e-12" in_port="clb.I0 clb.I1" out_port="fle[9:0].in[2]" />
-          <delay_constant max="190e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[2]" />
+          <delay_constant max="230e-12" in_port="clb.I0 clb.I1" out_port="fle[9:0].in[2]" />
+          <delay_constant max="230e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[2]" />
         </complete>
         <complete name="crossbar3" input="clb.I1 clb.I3 fle[9:0].out" output="fle[9:0].in[3]">
-          <delay_constant max="190e-12" in_port="clb.I1 clb.I3" out_port="fle[9:0].in[3]" />
-          <delay_constant max="190e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[3]" />
+          <delay_constant max="230e-12" in_port="clb.I1 clb.I3" out_port="fle[9:0].in[3]" />
+          <delay_constant max="230e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[3]" />
         </complete>
         <complete name="crossbar4" input="clb.I0 clb.I2 fle[9:0].out" output="fle[9:0].in[4]">
-          <delay_constant max="190e-12" in_port="clb.I0 clb.I2" out_port="fle[9:0].in[4]" />
-          <delay_constant max="190e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[4]" />
+          <delay_constant max="230e-12" in_port="clb.I0 clb.I2" out_port="fle[9:0].in[4]" />
+          <delay_constant max="230e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[4]" />
         </complete>
         <complete name="crossbar5" input="clb.I0 clb.I3 fle[9:0].out" output="fle[9:0].in[5]">
+          <delay_constant max="230e-12" in_port="clb.I0 clb.I3" out_port="fle[9:0].in[5]" />
+          <delay_constant max="230e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[5]" />
         </complete>
         <complete name="clks" input="clb.clk" output="fle[9:0].clk">
         </complete>
@@ -685,14 +687,18 @@
         <!--direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
           <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
         </direct-->
-        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
-        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
+        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]">
+          <delay_constant max="172e-12" in_port="fle[9:0].out[0:0]" out_port="clb.O[9:0]"/>
+        </direct>
+        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]">
+          <delay_constant max="172e-12" in_port="fle[9:0].out[1:1]" out_port="clb.O[19:10]"/>
+        </direct>
         <direct name="cout_copy" input="fle[9:9].cout" output="clb.cout_copy"/>
 
         <!-- Shift register links -->
         <direct name="regin" input="clb.regin" output="fle[0:0].regin">
           <!-- Put all inter-block carry chain delay on this one edge -->
-          <delay_constant max="0.15e-9" in_port="clb.regin" out_port="fle[0:0].regin"/>
+          <delay_constant max="0e-9" in_port="clb.regin" out_port="fle[0:0].regin"/>
           <pack_pattern name="chain" in_port="clb.regin" out_port="fle[0:0].regin"/>
         </direct>
         <direct name="regout" input="fle[9:9].regout" output="clb.regout">

From 2f3a36ee81d80a090f3127e7de4b914590895a6c Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 18 Apr 2020 18:39:47 -0600
Subject: [PATCH 444/645] update timing and rename the arch file

---
 ...gister_scan_chain_mem16K_depop50_12nm.xml} | 39 +++++++++++++------
 1 file changed, 27 insertions(+), 12 deletions(-)
 rename openfpga_flow/arch/vpr_only_templates/{k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_40nm.xml => k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_12nm.xml} (96%)

diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_40nm.xml b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_12nm.xml
similarity index 96%
rename from openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_40nm.xml
rename to openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_12nm.xml
index 1e2808f66..15281812f 100755
--- a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_40nm.xml
+++ b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_12nm.xml
@@ -1,8 +1,11 @@
-<!-- Homogeneous FPGA Architecture with Carry Chain for VPR8
+<!-- Heterogeneous FPGA Architecture with Carry Chain for VPR8
 
-  - The chip layout is organized with a 2x2 array of Configurable Logic Blocks (CLBs)
+  - The chip layout is organized with a 32x32 array of Configurable Logic Blocks (CLBs)
     surrounded by a ring of I/Os
-  - [TODO] Delay numbers are extracted from a 12 nm technology
+  - A column of BRAM locates at the 16th column of the 32x32 array
+  - Delay numbers are extracted from a 12 nm technology
+    Process corner: TT 0.8V
+  
   Author: Xifan Tang, Aurelien Alacchi and Ganesh Gore
 -->
 <architecture>
@@ -216,8 +219,8 @@
     <connection_block input_switch_name="ipin_cblock"/>
   </device>
   <switchlist>
-    <switch type="mux" name="0" R="0" Cin="0" Cout="0" Tdel="160e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
-    <switch type="mux" name="ipin_cblock" R="0." Cout="0." Cin="0" Tdel="207e-12" mux_trans_size="1.222260" buf_size="auto"/>
+    <switch type="mux" name="0" R="0" Cin="0" Cout="0" Tdel="200e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <switch type="mux" name="ipin_cblock" R="0." Cout="0." Cin="0" Tdel="210e-12" mux_trans_size="1.222260" buf_size="auto"/>
   </switchlist>
   <segmentlist>
     <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
@@ -337,6 +340,9 @@
         <clock name="clk" num_pins="1"/>
 
         <!-- Describe physical mode begins -->
+        <!-- Timing annotation is not require for unpackable mode
+             It will not be used by timing analyzer
+          -->
         <mode name="physical" packable="false">
           <pb_type name="frac_logic" num_pb="1">
             <input name="in" num_pins="6"/>
@@ -485,6 +491,9 @@
                         161e-12
                     </delay_matrix>
                   </pb_type>
+                  <!-- Delay extracted from standard cell lib file
+                       Consider the minimum slew and minimum load
+                   -->
                   <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
                     <input name="a" num_pins="1"/>
                     <input name="b" num_pins="1"/>
@@ -498,6 +507,9 @@
                     <delay_constant max="26e-12" in_port="adder.b" out_port="adder.cout"/>
                     <delay_constant max="26e-12" in_port="adder.cin" out_port="adder.cout"/>
                   </pb_type>
+                  <!-- Delay extracted from standard cell lib file
+                       Consider the minimum slew and minimum load
+                   -->
                   <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
                     <input name="D" num_pins="1" port_class="D"/>
                     <output name="Q" num_pins="1" port_class="Q"/>
@@ -522,6 +534,12 @@
                     <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
                       <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
                     </direct>
+                    <!-- Timing is extracted from the physical implementation 
+                         The path from ff.Q to arithmetic.out consists of a routing multiplexer
+                         The path from adder.sumout to arithmetic.out consists of two routing multiplexers
+                         One multiplexer connects from adder to ff.D 
+                         Another connects from the ff.D to arithmetic.out
+                      -->
                     <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
                       <delay_constant max="112e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
                       <delay_constant max="48e-12" in_port="ff.Q" out_port="arithmetic.out" />
@@ -532,10 +550,8 @@
                 <interconnect>
                   <direct name="direct1" input="ble5.in[3:0]" output="arithmetic.in"/>
                   <direct name="carry_in" input="ble5.cin" output="arithmetic.cin">
-                    <!--pack_pattern name="chain" in_port="ble5.cin" out_port="arithmetic.cin"/-->
                   </direct>
                   <direct name="carry_out" input="arithmetic.cout" output="ble5.cout">
-                    <!--pack_pattern name="chain" in_port="arithmetic.cout" out_port="ble5.cout"/-->
                   </direct>
                   <direct name="direct2" input="ble5.clk" output="arithmetic.clk"/>
                   <direct name="direct3" input="arithmetic.out" output="ble5.out"/>
@@ -547,13 +563,10 @@
               <direct name="direct2" input="lut5inter.in" output="ble5[1:1].in"/>
               <direct name="direct3" input="ble5[1:0].out" output="lut5inter.out"/>
               <direct name="carry_in" input="lut5inter.cin" output="ble5[0:0].cin">
-                <!--pack_pattern name="chain" in_port="lut5inter.cin" out_port="ble5[0:0].cin"/-->
               </direct>
               <direct name="carry_out" input="ble5[1:1].cout" output="lut5inter.cout">
-                <!--pack_pattern name="chain" in_port="ble5[1:1].cout" out_port="lut5inter.cout"/-->
               </direct>
               <direct name="carry_link" input="ble5[0:0].cout" output="ble5[1:1].cin">
-                <!--pack_pattern name="chain" in_port="ble5[0:0].cout" out_port="ble5[1:1].cout"/-->
               </direct>
               <complete name="complete1" input="lut5inter.clk" output="ble5[1:0].clk"/>
             </interconnect>
@@ -563,10 +576,8 @@
             <direct name="direct2" input="lut5inter.out" output="fle.out"/>
             <direct name="direct3" input="fle.clk" output="lut5inter.clk"/>
             <direct name="carry_in" input="fle.cin" output="lut5inter.cin">
-              <!--pack_pattern name="chain" in_port="fle.cin" out_port="lut5inter.cin"/-->
             </direct>
             <direct name="carry_out" input="lut5inter.cout" output="fle.cout">
-              <!--pack_pattern name="chain" in_port="lut5inter.cout" out_port="fle.cout"/-->
             </direct>
           </interconnect>
         </mode>
@@ -589,6 +600,9 @@
                   230e-12
               </delay_matrix>
             </pb_type>
+            <!-- Delay extracted from standard cell lib file
+                 Consider the minimum slew and minimum load
+             -->
             <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
               <input name="D" num_pins="1" port_class="D"/>
               <output name="Q" num_pins="1" port_class="Q"/>
@@ -746,6 +760,7 @@
           <input name="ren" num_pins="1" port_class="write_en"/>
           <output name="d_out" num_pins="32" port_class="data_out"/>
           <clock name="clk" num_pins="1" port_class="clock"/>
+          <!-- TODO the setup time and clk2Q delay should be extracted from BRAM LIB -->
           <T_setup value="509e-12" port="mem_512x32_dp.waddr" clock="clk"/>
           <T_setup value="509e-12" port="mem_512x32_dp.raddr" clock="clk"/>
           <T_setup value="509e-12" port="mem_512x32_dp.d_in" clock="clk"/>

From 95863e996a12e5ad20e931871716ded8a170fe7c Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 18 Apr 2020 18:43:56 -0600
Subject: [PATCH 445/645] minor update on arch to use auto layout sizing

---
 ...10_tileable_adder_register_scan_chain_depop50_40nm.xml | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml
index ce1cc258c..1b51c45af 100755
--- a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml
+++ b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml
@@ -142,19 +142,19 @@
        This is strongly recommended if you want to PnR large FPGA fabric
     -->
   <layout tileable="true">
-    <!--auto_layout aspect_ratio="1.0"-->
+    <auto_layout aspect_ratio="1.0">
     <!-- Apply a fixed layout of 2x2 core array.
          VPR8 considers the I/O ring in the array size
          Therefore the height and width are both 4
       -->
-    <fixed_layout name="32x32" width="34" height="34">
+    <!-- fixed_layout name="32x32" width="34" height="34" -->
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
       <corners type="EMPTY" priority="101"/>
       <!--Fill with 'clb'-->
       <fill type="clb" priority="10"/>
-    </fixed_layout>
-    <!-- /auto_layout -->
+    <!-- /fixed_layout -->
+    </auto_layout>
   </layout>
   <device>
     <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>

From f76a3090c4bb9a814dd1d118a6c7a99e26261c6c Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 18 Apr 2020 19:25:16 -0600
Subject: [PATCH 446/645] add mcnc big20 test cases and start debugging

---
 ...ister_scan_chain_depop50_40nm_openfpga.xml | 289 ++++++++++++++++++
 .../mcnc_big20/config/task.conf               | 134 ++++++++
 2 files changed, 423 insertions(+)
 create mode 100644 openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml
 create mode 100644 openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf

diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml
new file mode 100644
index 000000000..8d2aadaeb
--- /dev/null
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml
@@ -0,0 +1,289 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
+      <design_technology type="cmos" topology="OR"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> 
+        This is flip-flop with scan-chain feature.
+        When the TESTEN is enabled, the data will be propagated form DI instead of D
+      -->
+    <circuit_model type="ff" name="scan_chain_ff" prefix="scan_chain_ff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="D_chain" lib_name="DI" size="1"/>
+       <port type="input" prefix="TESTEN" size="1" is_global="true" default_val="0"/>
+       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
+      <design_technology type="cmos" fracturable_lut="true"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="6" tri_state_map="----11" circuit_model_name="OR2"/>
+      <port type="output" prefix="lut4_out" size="4" lut_frac_level="4" lut_output_mask="0,1,2,3"/>
+      <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
+      <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
+      <port type="sram" prefix="sram" size="64"/>
+      <port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="Qb" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+      <port type="input" prefix="outpad" size="1"/>
+      <port type="output" prefix="inpad" size="1"/>
+    </circuit_model>
+    <circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="input" prefix="cin" size="1"/>
+      <port type="output" prefix="sumout" size="1"/>
+      <port type="output" prefix="cout" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <direct_connection>
+    <direct name="adder_carry" circuit_model_name="direct_interc"/>
+    <direct name="scff_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
+  </direct_connection>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/>
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb.fle" physical_mode_name="physical"/>
+    <pb_type name="clb.fle[physical].frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
+    <pb_type name="clb.fle[physical].ff_phy" circuit_model_name="scan_chain_ff"/>
+    <pb_type name="clb.fle[physical].frac_logic.adder_phy" circuit_model_name="adder"/>
+    <!-- Binding operating pb_type to physical pb_type -->
+    <!-- Binding operating pb_types in mode 'n2_lut5' -->
+    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5[blut5].flut5.lut5" physical_pb_type_name="clb.fle[physical].frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5">
+      <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:4]"/>
+      <port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5[blut5].flut5.ff" physical_pb_type_name="clb.fle[physical].ff_phy"/>
+    <!-- Binding operating pb_types in mode 'arithmetic' -->
+    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5[arithmetic].arithmetic.lut4" physical_pb_type_name="clb.fle[physical].frac_logic.frac_lut6" mode_bits="11" physical_pb_type_index_factor="0.25">
+      <!-- Binding the lut4 to the first 4 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:3]"/>
+      <port name="out" physical_mode_port="lut4_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5[arithmetic].arithmetic.adder" physical_pb_type_name="clb.fle[physical].frac_logic.adder_phy"/>
+    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5[arithmetic].arithmetic.ff" physical_pb_type_name="clb.fle[physical].ff_phy"/>
+    <!-- Binding operating pb_types in mode 'ble6' -->
+    <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].frac_logic.frac_lut6" mode_bits="00">
+      <!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:5]"/>
+      <port name="out" physical_mode_port="lut6_out"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].ff_phy" physical_pb_type_index_factor="2" physical_pb_type_index_offset="1"/>
+    <!-- Binding operating pb_types in mode 'shift_register' -->
+    <pb_type name="clb.fle[shift_register].ble_shift.ff" physical_pb_type_name="clb.fle[physical].ff_phy"/>
+    <!-- End physical pb_type binding in complex block CLB -->
+  </pb_type_annotations>
+</openfpga_architecture>
+<openfpga_simulation_setting>
+  <clock_setting>
+    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
+    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
+    <programming frequency="10e6"/>
+  </clock_setting>
+  <simulator_option>
+    <operating_condition temperature="25"/>
+    <output_log verbose="false" captab="false"/>
+    <accuracy type="abs" value="1e-13"/>
+    <runtime fast_simulation="true"/>
+  </simulator_option>
+  <monte_carlo num_simulation_points="2"/>
+  <measurement_setting>
+    <slew>
+      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
+      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
+    </slew>
+    <delay>
+      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
+      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
+    </delay>
+  </measurement_setting>
+  <stimulus>
+    <clock>
+      <rise slew_type="abs" slew_time="20e-12" />
+      <fall slew_type="abs" slew_time="20e-12" />
+    </clock>
+    <input>
+      <rise slew_type="abs" slew_time="25e-12" />
+      <fall slew_type="abs" slew_time="25e-12" />
+    </input>
+  </stimulus>
+</openfpga_simulation_setting>
diff --git a/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf b/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf
new file mode 100644
index 000000000..9ecb77896
--- /dev/null
+++ b/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf
@@ -0,0 +1,134 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml
+
+[BENCHMARKS]
+# Pass
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif 
+# Pass, but port does not match, i_15_ is dangling
+bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif
+# Pass
+bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.blif
+bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.blif
+# To be tested
+bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.blif
+bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.blif
+bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.blif
+bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.blif
+bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.blif
+bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.blif
+bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.blif
+bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.blif
+bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.blif
+bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.blif
+# Pass
+bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.blif 
+bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.blif 
+bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.blif
+bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.blif
+bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.blif
+bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.blif
+
+[SYNTHESIS_PARAM]
+# Benchmark alu4 
+bench0_top = alu4
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.v
+# Benchmark apex2 
+bench1_top = apex2
+bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.act
+bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.v
+# Benchmark apex4 
+bench2_top = apex4
+bench2_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.act
+bench2_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.v
+# Benchmark bigkey 
+bench3_top = bigkey
+bench3_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.act
+bench3_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.v
+# Benchmark clma 
+bench4_top = clma
+bench4_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.act
+bench4_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.v
+# Benchmark des 
+bench5_top = des
+bench5_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.act
+bench5_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.v
+# Benchmark diffeq 
+bench6_top = diffeq
+bench6_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.act
+bench6_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.v
+# Benchmark dsip 
+bench7_top = dsip
+bench7_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.act
+bench7_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.v
+# Benchmark elliptic 
+bench8_top = elliptic
+bench8_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.act
+bench8_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.v
+# Benchmark ex1010 
+bench9_top = ex1010
+bench9_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.act
+bench9_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.v
+# Benchmark ex5p 
+bench10_top = ex5p
+bench10_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.act
+bench10_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.v
+# Benchmark frisc 
+bench11_top = frisc
+bench11_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.act
+bench11_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.v
+# Benchmark misex3 
+bench12_top = misex3
+bench12_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.act
+bench12_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.v
+# Benchmark pdc 
+bench13_top = pdc
+bench13_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.act
+bench13_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.v
+# Benchmark s298 
+bench14_top = s298
+bench14_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.act
+bench14_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.v
+# Benchmark s38417 
+bench15_top = s38417
+bench15_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.act
+bench15_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.v
+# Benchmark s38584 
+bench16_top = s38584
+bench16_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.act
+bench16_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.v
+# Benchmark seq 
+bench17_top = seq
+bench17_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.act
+bench17_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.v
+# Benchmark spla 
+bench18_top = spla
+bench18_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.act
+bench18_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.v
+# Benchmark tseng 
+bench19_top = tseng
+bench19_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.act
+bench19_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.v
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+#end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

From 2e3a811f4fd39692ca5007636f2490bf99b7827c Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 18 Apr 2020 21:04:46 -0600
Subject: [PATCH 447/645] critical bug fixed in repacking. This is due to
 depop50% local routing where the same net may be mapped to two different pins
 in the same pb_graph_pin. Now we restrict the pin searching. But in long
 term, we should sync the pb_route results to post routing results

---
 .../src/annotation/vpr_routing_annotation.cpp |  7 +--
 openfpga/src/repack/repack.cpp                | 14 ++++--
 .../mcnc_big20/config/task.conf               | 43 ++++++++-----------
 3 files changed, 33 insertions(+), 31 deletions(-)

diff --git a/openfpga/src/annotation/vpr_routing_annotation.cpp b/openfpga/src/annotation/vpr_routing_annotation.cpp
index 1c17450ed..b51f4be94 100644
--- a/openfpga/src/annotation/vpr_routing_annotation.cpp
+++ b/openfpga/src/annotation/vpr_routing_annotation.cpp
@@ -36,9 +36,10 @@ void VprRoutingAnnotation::set_rr_node_net(const RRNodeId& rr_node,
   /* Ensure that the node_id is in the list */
   VTR_ASSERT(size_t(rr_node) < rr_node_nets_.size());
   /* Warn any override attempt */
-  if (ClusterNetId::INVALID() != rr_node_nets_[rr_node]) {
-    VTR_LOG_WARN("Override the net '%ld' for node '%ld' with in routing context annotation!\n",
-                 size_t(net_id), size_t(rr_node));
+  if ( (ClusterNetId::INVALID() != rr_node_nets_[rr_node])
+    && (net_id != rr_node_nets_[rr_node])) {
+    VTR_LOG_WARN("Override the net '%ld' by net '%ld' for node '%ld' with in routing context annotation!\n",
+                 size_t(rr_node_nets_[rr_node]), size_t(net_id), size_t(rr_node));
   }
 
   rr_node_nets_[rr_node] = net_id;
diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp
index 2d0b2c3e8..a32366be0 100644
--- a/openfpga/src/repack/repack.cpp
+++ b/openfpga/src/repack/repack.cpp
@@ -117,15 +117,21 @@ int find_pb_route_remapped_source_pb_pin(const t_pb* pb,
 
   for (int pin = 0; pin < pb->pb_graph_node->total_pb_pins; ++pin) {
     /* Bypass unused pins */
-    if ((0 == pb->pb_route.count(pin)) || (AtomNetId::INVALID() == pb->pb_route[pin].atom_net_id)) {
+    if ((0 == pb->pb_route.count(pin)) || (AtomNetId::INVALID() == pb->pb_route.at(pin).atom_net_id)) {
       continue;
     }
     /* Get the driver pb pin id, it must be valid */
-    if (atom_net_id != pb->pb_route[pin].atom_net_id) {
+    if (atom_net_id != pb->pb_route.at(pin).atom_net_id) {
       continue;
     }
-    /* Only care the pin that shares the same parent_node as source_pb_pin */
-    if (source_pb_pin->parent_node == pb->pb_route[pin].pb_graph_pin->parent_node) {
+    /* Only care the pin has the same parent port as source_pb_pin 
+     * Due to that the source_pb_pin may be swapped during routing
+     * the pb_route is out-of-date
+     * TODO: should update pb_route by post routing results
+     * On the other side, the swapping can only happen between equivalent pins
+     * in a port. So the port must match here!
+     */
+    if (source_pb_pin->port == pb->pb_route.at(pin).pb_graph_pin->port) {
       pb_route_indices.push_back(pin);
     } 
   }
diff --git a/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf b/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf
index 9ecb77896..0734df61d 100644
--- a/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf
@@ -21,31 +21,26 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml
 
 [BENCHMARKS]
-# Pass
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif 
-# Pass, but port does not match, i_15_ is dangling
-bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif
-# Pass
-bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.blif
-bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.blif
-# To be tested
-bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.blif
-bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.blif
-bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.blif
-bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.blif
-bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.blif
-bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.blif
-bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.blif
-bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.blif
-bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.blif
-bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.blif
-# Pass
+#bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif 
+#bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif
+#bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.blif
+#bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.blif
+#bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.blif
+#bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.blif
+#bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.blif
+#bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.blif
+#bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.blif
+#bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.blif
+#bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.blif
+#bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.blif
+#bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.blif
+#bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.blif
 bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.blif 
-bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.blif 
-bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.blif
-bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.blif
-bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.blif
-bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.blif
+#bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.blif 
+#bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.blif
+#bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.blif
+#bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.blif
+#bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.blif
 
 [SYNTHESIS_PARAM]
 # Benchmark alu4 

From cc163081f5f34881a5d1eb40d36206d6b38dcdfb Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 18 Apr 2020 21:06:43 -0600
Subject: [PATCH 448/645] recover mcnc big20 test configuration

---
 .../mcnc_big20/config/task.conf               | 38 +++++++++----------
 1 file changed, 19 insertions(+), 19 deletions(-)

diff --git a/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf b/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf
index 0734df61d..7a64bfcde 100644
--- a/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf
@@ -21,26 +21,26 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml
 
 [BENCHMARKS]
-#bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif 
-#bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif
-#bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.blif
-#bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.blif
-#bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.blif
-#bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.blif
-#bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.blif
-#bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.blif
-#bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.blif
-#bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.blif
-#bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.blif
-#bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.blif
-#bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.blif
-#bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif 
+bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif
+bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.blif
+bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.blif
+bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.blif
+bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.blif
+bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.blif
+bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.blif
+bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.blif
+bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.blif
+bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.blif
+bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.blif
+bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.blif
+bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.blif
 bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.blif 
-#bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.blif 
-#bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.blif
-#bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.blif
-#bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.blif
-#bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.blif
+bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.blif 
+bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.blif
+bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.blif
+bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.blif
+bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.blif
 
 [SYNTHESIS_PARAM]
 # Benchmark alu4 

From 98878f474b04270527d88356bc285bf8f91c616d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 19 Apr 2020 12:03:31 -0600
Subject: [PATCH 449/645] light change on arch file to accelerate mcnc big20
 run

---
 ...frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml
index 1b51c45af..174649d93 100755
--- a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml
+++ b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml
@@ -73,7 +73,7 @@
          make it physically equivalent on all sides so that only one definition of I/Os is needed.
          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
       -->
-    <tile name="io" capacity="1" area="0">
+    <tile name="io" capacity="8" area="0">
       <equivalent_sites>
         <site pb_type="io"/>
       </equivalent_sites>

From 32ed6092388066b421a1374016c907c0e52ef0d3 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 19 Apr 2020 12:49:07 -0600
Subject: [PATCH 450/645] update micro benchmark set and regression tests using
 them

---
 .../benchmarks/micro_benchmark/{ => and}/and.act     |  0
 .../benchmarks/micro_benchmark/{ => and}/and.blif    |  0
 .../benchmarks/micro_benchmark/{ => and}/and.v       |  0
 .../micro_benchmark/{ => and_latch}/and_latch.act    |  0
 .../micro_benchmark/{ => and_latch}/and_latch.blif   |  0
 .../micro_benchmark/{ => and_latch}/and_latch.v      |  0
 .../behavioral_verilog/config/task.conf              |  6 +++---
 .../openfpga_shell/bram/dpram16k/config/task.conf    |  6 +++---
 .../bram/wide_dpram16k/config/task.conf              |  6 +++---
 .../configuration_chain/config/task.conf             |  6 +++---
 .../duplicated_grid_pin/config/task.conf             |  6 +++---
 .../fabric_chain/adder_chain/config/task.conf        |  6 +++---
 .../fabric_chain/register_chain/config/task.conf     |  6 +++---
 .../fabric_chain/scan_chain/config/task.conf         |  6 +++---
 .../openfpga_shell/flatten_routing/config/task.conf  |  6 +++---
 .../tasks/openfpga_shell/frac_lut/config/task.conf   | 12 ++++++++----
 .../tasks/openfpga_shell/hard_adder/config/task.conf |  6 +++---
 .../openfpga_shell/implicit_verilog/config/task.conf |  6 +++---
 .../tasks/openfpga_shell/io/aib/config/task.conf     |  6 +++---
 .../io/multi_io_capacity/config/task.conf            |  6 +++---
 .../openfpga_shell/io/reduced_io/config/task.conf    |  6 +++---
 .../tasks/openfpga_shell/mcnc_big20/config/task.conf |  3 ++-
 .../mux_design/stdcell_mux2/config/task.conf         |  6 +++---
 .../mux_design/tree_structure/config/task.conf       |  6 +++---
 .../tasks/openfpga_shell/untileable/config/task.conf |  6 +++---
 25 files changed, 61 insertions(+), 56 deletions(-)
 rename openfpga_flow/benchmarks/micro_benchmark/{ => and}/and.act (100%)
 rename openfpga_flow/benchmarks/micro_benchmark/{ => and}/and.blif (100%)
 rename openfpga_flow/benchmarks/micro_benchmark/{ => and}/and.v (100%)
 rename openfpga_flow/benchmarks/micro_benchmark/{ => and_latch}/and_latch.act (100%)
 rename openfpga_flow/benchmarks/micro_benchmark/{ => and_latch}/and_latch.blif (100%)
 rename openfpga_flow/benchmarks/micro_benchmark/{ => and_latch}/and_latch.v (100%)

diff --git a/openfpga_flow/benchmarks/micro_benchmark/and.act b/openfpga_flow/benchmarks/micro_benchmark/and/and.act
similarity index 100%
rename from openfpga_flow/benchmarks/micro_benchmark/and.act
rename to openfpga_flow/benchmarks/micro_benchmark/and/and.act
diff --git a/openfpga_flow/benchmarks/micro_benchmark/and.blif b/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
similarity index 100%
rename from openfpga_flow/benchmarks/micro_benchmark/and.blif
rename to openfpga_flow/benchmarks/micro_benchmark/and/and.blif
diff --git a/openfpga_flow/benchmarks/micro_benchmark/and.v b/openfpga_flow/benchmarks/micro_benchmark/and/and.v
similarity index 100%
rename from openfpga_flow/benchmarks/micro_benchmark/and.v
rename to openfpga_flow/benchmarks/micro_benchmark/and/and.v
diff --git a/openfpga_flow/benchmarks/micro_benchmark/and_latch.act b/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.act
similarity index 100%
rename from openfpga_flow/benchmarks/micro_benchmark/and_latch.act
rename to openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.act
diff --git a/openfpga_flow/benchmarks/micro_benchmark/and_latch.blif b/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.blif
similarity index 100%
rename from openfpga_flow/benchmarks/micro_benchmark/and_latch.blif
rename to openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.blif
diff --git a/openfpga_flow/benchmarks/micro_benchmark/and_latch.v b/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.v
similarity index 100%
rename from openfpga_flow/benchmarks/micro_benchmark/and_latch.v
rename to openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.v
diff --git a/openfpga_flow/tasks/openfpga_shell/behavioral_verilog/config/task.conf b/openfpga_flow/tasks/openfpga_shell/behavioral_verilog/config/task.conf
index 4d5f90d67..c7c111313 100644
--- a/openfpga_flow/tasks/openfpga_shell/behavioral_verilog/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/behavioral_verilog/config/task.conf
@@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
 
 [SYNTHESIS_PARAM]
 bench0_top = top
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
diff --git a/openfpga_flow/tasks/openfpga_shell/bram/dpram16k/config/task.conf b/openfpga_flow/tasks/openfpga_shell/bram/dpram16k/config/task.conf
index aeffa9a86..cb3632359 100644
--- a/openfpga_flow/tasks/openfpga_shell/bram/dpram16k/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/bram/dpram16k/config/task.conf
@@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
 
 [SYNTHESIS_PARAM]
 bench0_top = top
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
diff --git a/openfpga_flow/tasks/openfpga_shell/bram/wide_dpram16k/config/task.conf b/openfpga_flow/tasks/openfpga_shell/bram/wide_dpram16k/config/task.conf
index 53cc5407c..756b2980e 100644
--- a/openfpga_flow/tasks/openfpga_shell/bram/wide_dpram16k/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/bram/wide_dpram16k/config/task.conf
@@ -22,12 +22,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
 
 [SYNTHESIS_PARAM]
 bench0_top = top
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
diff --git a/openfpga_flow/tasks/openfpga_shell/configuration_chain/config/task.conf b/openfpga_flow/tasks/openfpga_shell/configuration_chain/config/task.conf
index 7415b96ab..5dca0428c 100644
--- a/openfpga_flow/tasks/openfpga_shell/configuration_chain/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/configuration_chain/config/task.conf
@@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
 
 [SYNTHESIS_PARAM]
 bench0_top = top
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
diff --git a/openfpga_flow/tasks/openfpga_shell/duplicated_grid_pin/config/task.conf b/openfpga_flow/tasks/openfpga_shell/duplicated_grid_pin/config/task.conf
index 7f1f370c6..03c54d43f 100644
--- a/openfpga_flow/tasks/openfpga_shell/duplicated_grid_pin/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/duplicated_grid_pin/config/task.conf
@@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
 
 [SYNTHESIS_PARAM]
 bench0_top = top
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
diff --git a/openfpga_flow/tasks/openfpga_shell/fabric_chain/adder_chain/config/task.conf b/openfpga_flow/tasks/openfpga_shell/fabric_chain/adder_chain/config/task.conf
index 348d11cde..82afc9a11 100644
--- a/openfpga_flow/tasks/openfpga_shell/fabric_chain/adder_chain/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/fabric_chain/adder_chain/config/task.conf
@@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
 
 [SYNTHESIS_PARAM]
 bench0_top = top
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
diff --git a/openfpga_flow/tasks/openfpga_shell/fabric_chain/register_chain/config/task.conf b/openfpga_flow/tasks/openfpga_shell/fabric_chain/register_chain/config/task.conf
index 29f1ac4b0..5c1ec8fb9 100644
--- a/openfpga_flow/tasks/openfpga_shell/fabric_chain/register_chain/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/fabric_chain/register_chain/config/task.conf
@@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_chain_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
 
 [SYNTHESIS_PARAM]
 bench0_top = top
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
diff --git a/openfpga_flow/tasks/openfpga_shell/fabric_chain/scan_chain/config/task.conf b/openfpga_flow/tasks/openfpga_shell/fabric_chain/scan_chain/config/task.conf
index e1e85366b..7a98b0731 100644
--- a/openfpga_flow/tasks/openfpga_shell/fabric_chain/scan_chain/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/fabric_chain/scan_chain/config/task.conf
@@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
 
 [SYNTHESIS_PARAM]
 bench0_top = top
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
diff --git a/openfpga_flow/tasks/openfpga_shell/flatten_routing/config/task.conf b/openfpga_flow/tasks/openfpga_shell/flatten_routing/config/task.conf
index bb15c4c43..7823bee48 100644
--- a/openfpga_flow/tasks/openfpga_shell/flatten_routing/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/flatten_routing/config/task.conf
@@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
 
 [SYNTHESIS_PARAM]
 bench0_top = top
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
diff --git a/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf b/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf
index a52d2f515..f9276b42b 100644
--- a/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf
@@ -21,13 +21,17 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
+#bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.blif
 
 [SYNTHESIS_PARAM]
 bench0_top = top
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v
-bench0_chan_width = 300
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
+
+bench1_top = top
+bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and_latch.act
+bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and_latch.v
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
 end_flow_with_test=
diff --git a/openfpga_flow/tasks/openfpga_shell/hard_adder/config/task.conf b/openfpga_flow/tasks/openfpga_shell/hard_adder/config/task.conf
index f9fbc97f2..cd63c7064 100644
--- a/openfpga_flow/tasks/openfpga_shell/hard_adder/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/hard_adder/config/task.conf
@@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
 
 [SYNTHESIS_PARAM]
 bench0_top = top
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
diff --git a/openfpga_flow/tasks/openfpga_shell/implicit_verilog/config/task.conf b/openfpga_flow/tasks/openfpga_shell/implicit_verilog/config/task.conf
index 9c10e2783..24e443381 100644
--- a/openfpga_flow/tasks/openfpga_shell/implicit_verilog/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/implicit_verilog/config/task.conf
@@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
 
 [SYNTHESIS_PARAM]
 bench0_top = top
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
diff --git a/openfpga_flow/tasks/openfpga_shell/io/aib/config/task.conf b/openfpga_flow/tasks/openfpga_shell/io/aib/config/task.conf
index 2d08de621..d71cc949f 100644
--- a/openfpga_flow/tasks/openfpga_shell/io/aib/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/io/aib/config/task.conf
@@ -32,12 +32,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
 
 [SYNTHESIS_PARAM]
 bench0_top = top
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
diff --git a/openfpga_flow/tasks/openfpga_shell/io/multi_io_capacity/config/task.conf b/openfpga_flow/tasks/openfpga_shell/io/multi_io_capacity/config/task.conf
index a3f9081d9..ee003aa84 100644
--- a/openfpga_flow/tasks/openfpga_shell/io/multi_io_capacity/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/io/multi_io_capacity/config/task.conf
@@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
 
 [SYNTHESIS_PARAM]
 bench0_top = top
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
diff --git a/openfpga_flow/tasks/openfpga_shell/io/reduced_io/config/task.conf b/openfpga_flow/tasks/openfpga_shell/io/reduced_io/config/task.conf
index 8ed4998db..7d2be5aa5 100644
--- a/openfpga_flow/tasks/openfpga_shell/io/reduced_io/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/io/reduced_io/config/task.conf
@@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
 
 [SYNTHESIS_PARAM]
 bench0_top = top
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
diff --git a/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf b/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf
index 7a64bfcde..f28150126 100644
--- a/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf
@@ -24,7 +24,8 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_ti
 bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif 
 bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif
 bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.blif
-bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.blif
+# VPR remove dangling PIs and POs which are in act file. Then VPR errors out by saying these PI/PO should not exist in act file
+#bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.blif
 bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.blif
 bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.blif
 bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.blif
diff --git a/openfpga_flow/tasks/openfpga_shell/mux_design/stdcell_mux2/config/task.conf b/openfpga_flow/tasks/openfpga_shell/mux_design/stdcell_mux2/config/task.conf
index 6ad9d0db0..3aa07c229 100644
--- a/openfpga_flow/tasks/openfpga_shell/mux_design/stdcell_mux2/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/mux_design/stdcell_mux2/config/task.conf
@@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
 
 [SYNTHESIS_PARAM]
 bench0_top = top
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
diff --git a/openfpga_flow/tasks/openfpga_shell/mux_design/tree_structure/config/task.conf b/openfpga_flow/tasks/openfpga_shell/mux_design/tree_structure/config/task.conf
index 658e328c0..2b164ecf5 100644
--- a/openfpga_flow/tasks/openfpga_shell/mux_design/tree_structure/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/mux_design/tree_structure/config/task.conf
@@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
 
 [SYNTHESIS_PARAM]
 bench0_top = top
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
diff --git a/openfpga_flow/tasks/openfpga_shell/untileable/config/task.conf b/openfpga_flow/tasks/openfpga_shell/untileable/config/task.conf
index 4ea65822f..c67f71c55 100644
--- a/openfpga_flow/tasks/openfpga_shell/untileable/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/untileable/config/task.conf
@@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
 
 [SYNTHESIS_PARAM]
 bench0_top = top
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and.v
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]

From e10cafe0a575365b3c3b92a2a1ba719f733f9c3f Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 19 Apr 2020 16:42:31 -0600
Subject: [PATCH 451/645] Critical patch on repacking about wire LUT support.
 Previously, the wire LUT identification is too naive and does not consider
 all the cases

---
 openfpga/src/base/openfpga_repack.cpp         |  3 +-
 .../src/repack/build_physical_truth_table.cpp | 60 ++++++++----
 .../src/repack/build_physical_truth_table.h   |  3 +-
 openfpga/src/repack/lb_router_utils.cpp       | 10 ++
 openfpga/src/repack/physical_pb.cpp           | 24 +++++
 openfpga/src/repack/physical_pb.h             |  6 ++
 openfpga/src/repack/repack.cpp                | 49 ++++++----
 openfpga/src/utils/lut_utils.cpp              | 23 +++++
 openfpga/src/utils/pb_type_utils.h            |  9 ++
 openfpga/src/utils/physical_pb_utils.cpp      | 98 ++++++++++++++++++-
 openfpga/src/utils/physical_pb_utils.h        |  3 +-
 .../openfpga_shell/frac_lut/config/task.conf  |  8 +-
 12 files changed, 248 insertions(+), 48 deletions(-)

diff --git a/openfpga/src/base/openfpga_repack.cpp b/openfpga/src/base/openfpga_repack.cpp
index fe0529d04..a0fd143f4 100644
--- a/openfpga/src/base/openfpga_repack.cpp
+++ b/openfpga/src/base/openfpga_repack.cpp
@@ -37,7 +37,8 @@ int repack(OpenfpgaContext& openfpga_ctx,
                                   g_vpr_ctx.atom(),
                                   g_vpr_ctx.clustering(),
                                   openfpga_ctx.vpr_device_annotation(),
-                                  openfpga_ctx.arch().circuit_lib); 
+                                  openfpga_ctx.arch().circuit_lib,
+                                  cmd_context.option_enable(cmd, opt_verbose));
 
   /* TODO: should identify the error code from internal function execution */
   return CMD_EXEC_SUCCESS;
diff --git a/openfpga/src/repack/build_physical_truth_table.cpp b/openfpga/src/repack/build_physical_truth_table.cpp
index 51fc93f93..404911a2d 100644
--- a/openfpga/src/repack/build_physical_truth_table.cpp
+++ b/openfpga/src/repack/build_physical_truth_table.cpp
@@ -11,15 +11,13 @@
 #include "openfpga_naming.h"
 
 #include "lut_utils.h"
+#include "pb_type_utils.h"
 #include "physical_pb.h"
 #include "build_physical_truth_table.h"
 
 /* begin namespace openfpga */
 namespace openfpga {
 
-/* Mode 1 is the lut mode while mode 0 is the wire mode */
-constexpr int VPR_PB_TYPE_LUT_MODE = 1;
-
 /***************************************************************************************
  * Identify if LUT is used as wiring 
  * In this case, LUT functions as a buffer
@@ -102,7 +100,8 @@ void build_physical_pb_lut_truth_tables(PhysicalPb& physical_pb,
                                         const PhysicalPbId& lut_pb_id,
                                         const AtomContext& atom_ctx,
                                         const VprDeviceAnnotation& device_annotation,
-                                        const CircuitLibrary& circuit_lib) {
+                                        const CircuitLibrary& circuit_lib,
+                                        const bool& verbose) {
   const t_pb_graph_node* pb_graph_node = physical_pb.pb_graph_node(lut_pb_id);
 
   CircuitModelId lut_model = device_annotation.pb_type_circuit_model(physical_pb.pb_graph_node(lut_pb_id)->pb_type);
@@ -125,20 +124,21 @@ void build_physical_pb_lut_truth_tables(PhysicalPb& physical_pb,
         continue;
       }
       /* Check if this is a LUT used as wiring */
-      if (true == is_wired_lut(input_nets, output_net)) {
-        AtomNetlist::TruthTable wire_tt = build_wired_lut_truth_table(input_nets.size(), std::find(input_nets.begin(), input_nets.end(), output_net) - input_nets.begin()); 
-        physical_pb.set_truth_table(lut_pb_id, output_pin, wire_tt);
-        continue;
+      AtomNetlist::TruthTable adapt_tt;
+      if (true == physical_pb.is_wire_lut_output(lut_pb_id, output_pin)) {
+        /* Double check: ensure that the output nets appear in the input net !!! */
+        VTR_ASSERT(true == is_wired_lut(input_nets, output_net));
+        adapt_tt = build_wired_lut_truth_table(input_nets.size(), std::find(input_nets.begin(), input_nets.end(), output_net) - input_nets.begin()); 
+      } else {
+        /* Find the truth table from atom block which drives the atom net */
+        const AtomBlockId& atom_blk = atom_ctx.nlist.net_driver_block(output_net); 
+        VTR_ASSERT(true == atom_ctx.nlist.valid_block_id(atom_blk));
+        const AtomNetlist::TruthTable& orig_tt = atom_ctx.nlist.block_truth_table(atom_blk);
+
+        std::vector<int> rotated_pin_map = generate_lut_rotated_input_pin_map(input_nets, atom_ctx, atom_blk, pb_graph_node);
+        adapt_tt = lut_truth_table_adaption(orig_tt, rotated_pin_map);
       }
 
-      /* Find the truth table from atom block which drives the atom net */
-      const AtomBlockId& atom_blk = atom_ctx.nlist.net_driver_block(output_net); 
-      VTR_ASSERT(true == atom_ctx.nlist.valid_block_id(atom_blk));
-      const AtomNetlist::TruthTable& orig_tt = atom_ctx.nlist.block_truth_table(atom_blk);
-
-      std::vector<int> rotated_pin_map = generate_lut_rotated_input_pin_map(input_nets, atom_ctx, atom_blk, pb_graph_node);
-      const AtomNetlist::TruthTable& adapt_tt = lut_truth_table_adaption(orig_tt, rotated_pin_map);
-
       /* Adapt the truth table for fracturable lut implementation and add to physical pb */
       CircuitPortId lut_model_output_port = device_annotation.pb_circuit_port(output_pin->port);
       size_t lut_frac_level = circuit_lib.port_lut_frac_level(lut_model_output_port);
@@ -148,6 +148,29 @@ void build_physical_pb_lut_truth_tables(PhysicalPb& physical_pb,
       size_t lut_output_mask = circuit_lib.port_lut_output_mask(lut_model_output_port)[output_pin->pin_number];
       const AtomNetlist::TruthTable& frac_lut_tt = adapt_truth_table_for_frac_lut(lut_frac_level, lut_output_mask, adapt_tt);
       physical_pb.set_truth_table(lut_pb_id, output_pin, frac_lut_tt);
+
+      /* Print debug information */
+      VTR_LOGV(verbose, "Input nets: ");
+      for (const AtomNetId& net : input_nets) {
+        if (AtomNetId::INVALID() == net) {
+          VTR_LOGV(verbose, "unconn  ");
+        } else {
+          VTR_ASSERT(AtomNetId::INVALID() != net);
+          VTR_LOGV(verbose, "%s  ", atom_ctx.nlist.net_name(net).c_str());
+        }
+      }
+      VTR_LOGV(verbose, "\n");
+
+      VTR_ASSERT(AtomNetId::INVALID() != output_net);
+      VTR_LOGV(verbose, "Output net: %s\n", atom_ctx.nlist.net_name(output_net).c_str());
+
+      VTR_LOGV(verbose,
+               "Add following truth table to pb_graph_pin '%s[%d]'\n", 
+               output_pin->port->name, output_pin->pin_number);
+      for (const std::string& tt_line : truth_table_to_string(frac_lut_tt)) {
+        VTR_LOGV(verbose, "\t%s\n", tt_line.c_str());
+      }
+      VTR_LOGV(verbose, "\n");
     }
   }
 }
@@ -164,7 +187,8 @@ void build_physical_lut_truth_tables(VprClusteringAnnotation& cluster_annotation
                                      const AtomContext& atom_ctx,
                                      const ClusteringContext& cluster_ctx,
                                      const VprDeviceAnnotation& device_annotation,
-                                     const CircuitLibrary& circuit_lib) {
+                                     const CircuitLibrary& circuit_lib,
+                                     const bool& verbose) {
   vtr::ScopedStartFinishTimer timer("Build truth tables for physical LUTs");
 
   for (auto blk_id : cluster_ctx.clb_nlist.blocks()) {
@@ -178,7 +202,7 @@ void build_physical_lut_truth_tables(VprClusteringAnnotation& cluster_annotation
       }
     
       /* Reach here, we have a LUT to deal with. Find the truth tables that mapped to the LUT */
-      build_physical_pb_lut_truth_tables(physical_pb, primitive_pb, atom_ctx, device_annotation, circuit_lib);
+      build_physical_pb_lut_truth_tables(physical_pb, primitive_pb, atom_ctx, device_annotation, circuit_lib, verbose);
     }
   }
 }
diff --git a/openfpga/src/repack/build_physical_truth_table.h b/openfpga/src/repack/build_physical_truth_table.h
index c5d14059f..3c0c8ebf3 100644
--- a/openfpga/src/repack/build_physical_truth_table.h
+++ b/openfpga/src/repack/build_physical_truth_table.h
@@ -20,7 +20,8 @@ void build_physical_lut_truth_tables(VprClusteringAnnotation& cluster_annotation
                                      const AtomContext& atom_ctx,
                                      const ClusteringContext& cluster_ctx,
                                      const VprDeviceAnnotation& device_annotation,
-                                     const CircuitLibrary& circuit_lib);
+                                     const CircuitLibrary& circuit_lib,
+                                     const bool& verbose);
 
 } /* end namespace openfpga */
 
diff --git a/openfpga/src/repack/lb_router_utils.cpp b/openfpga/src/repack/lb_router_utils.cpp
index 362ce4a76..1dea1750d 100644
--- a/openfpga/src/repack/lb_router_utils.cpp
+++ b/openfpga/src/repack/lb_router_utils.cpp
@@ -86,6 +86,16 @@ void save_lb_router_results_to_physical_pb(PhysicalPb& phy_pb,
       VTR_ASSERT(true == phy_pb.valid_pb_id(pb_id));
 
       const AtomNetId& atom_net = lb_router.net_atom_net_id(net);
+
+      /* Print info to help debug 
+      bool verbose = true;
+      VTR_LOGV(verbose,
+               "\nSave net '%lu' to physical pb_graph_pin '%s.%s[%d]'\n",
+               size_t(atom_net),
+               pb_graph_pin->parent_node->pb_type->name,
+               pb_graph_pin->port->name,
+               pb_graph_pin->pin_number);
+       */
       
       if (AtomNetId::INVALID() == phy_pb.pb_graph_pin_atom_net(pb_id, pb_graph_pin)) {
         phy_pb.set_pb_graph_pin_atom_net(pb_id, pb_graph_pin, atom_net);
diff --git a/openfpga/src/repack/physical_pb.cpp b/openfpga/src/repack/physical_pb.cpp
index 74894293a..4650d7d0d 100644
--- a/openfpga/src/repack/physical_pb.cpp
+++ b/openfpga/src/repack/physical_pb.cpp
@@ -81,6 +81,17 @@ AtomNetId PhysicalPb::pb_graph_pin_atom_net(const PhysicalPbId& pb,
   return AtomNetId::INVALID();
 }
 
+bool PhysicalPb::is_wire_lut_output(const PhysicalPbId& pb,
+                                    const t_pb_graph_pin* pb_graph_pin) const {
+  VTR_ASSERT(true == valid_pb_id(pb));
+  if (wire_lut_outputs_[pb].find(pb_graph_pin) != wire_lut_outputs_[pb].end()) {
+    /* Find it, return the status */
+    return wire_lut_outputs_[pb].at(pb_graph_pin); 
+  }
+  /* Not found, return false */
+  return false;
+}
+
 std::map<const t_pb_graph_pin*, AtomNetlist::TruthTable> PhysicalPb::truth_tables(const PhysicalPbId& pb) const {
   VTR_ASSERT(true == valid_pb_id(pb));
   return truth_tables_[pb];
@@ -110,6 +121,7 @@ PhysicalPbId PhysicalPb::create_pb(const t_pb_graph_node* pb_graph_node) {
   pb_graph_nodes_.push_back(pb_graph_node);
   atom_blocks_.emplace_back();
   pin_atom_nets_.emplace_back();
+  wire_lut_outputs_.emplace_back();
 
   child_pbs_.emplace_back();
   parent_pbs_.emplace_back();
@@ -182,6 +194,18 @@ void PhysicalPb::set_pb_graph_pin_atom_net(const PhysicalPbId& pb,
   pin_atom_nets_[pb][pb_graph_pin] = atom_net;
 }
 
+void PhysicalPb::set_wire_lut_output(const PhysicalPbId& pb,
+                                     const t_pb_graph_pin* pb_graph_pin,
+                                     const bool& wire_lut_output) {
+  VTR_ASSERT(true == valid_pb_id(pb)); 
+  if (wire_lut_outputs_[pb].end() != wire_lut_outputs_[pb].find(pb_graph_pin)) {
+    VTR_LOG_WARN("Overwrite pb_graph_pin '%s[%d]' status on wire LUT output\n",
+                 pb_graph_pin->port->name, pb_graph_pin->pin_number);
+  }
+
+  wire_lut_outputs_[pb][pb_graph_pin] = wire_lut_output;
+}
+
 /******************************************************************************
  * Private validators/invalidators
  ******************************************************************************/
diff --git a/openfpga/src/repack/physical_pb.h b/openfpga/src/repack/physical_pb.h
index 11559da6b..6d8d2ba3b 100644
--- a/openfpga/src/repack/physical_pb.h
+++ b/openfpga/src/repack/physical_pb.h
@@ -50,6 +50,8 @@ class PhysicalPb {
     std::vector<AtomBlockId> atom_blocks(const PhysicalPbId& pb) const;
     AtomNetId pb_graph_pin_atom_net(const PhysicalPbId& pb,
                                     const t_pb_graph_pin* pb_graph_pin) const;
+    bool is_wire_lut_output(const PhysicalPbId& pb,
+                            const t_pb_graph_pin* pb_graph_pin) const;
     std::map<const t_pb_graph_pin*, AtomNetlist::TruthTable> truth_tables(const PhysicalPbId& pb) const;
     std::vector<size_t> mode_bits(const PhysicalPbId& pb) const;
   public: /* Public mutators */
@@ -67,6 +69,9 @@ class PhysicalPb {
     void set_pb_graph_pin_atom_net(const PhysicalPbId& pb,
                                    const t_pb_graph_pin* pb_graph_pin,
                                    const AtomNetId& atom_net);
+    void set_wire_lut_output(const PhysicalPbId& pb,
+                             const t_pb_graph_pin* pb_graph_pin,
+                             const bool& wire_lut_output);
   public: /* Public validators/invalidators */
     bool valid_pb_id(const PhysicalPbId& pb_id) const;
     bool empty() const;
@@ -76,6 +81,7 @@ class PhysicalPb {
     vtr::vector<PhysicalPbId, std::string> names_;
     vtr::vector<PhysicalPbId, std::vector<AtomBlockId>> atom_blocks_;
     vtr::vector<PhysicalPbId, std::map<const t_pb_graph_pin*, AtomNetId>> pin_atom_nets_;
+    vtr::vector<PhysicalPbId, std::map<const t_pb_graph_pin*, bool>> wire_lut_outputs_;
 
     /* Child pbs are organized as [0..num_child_pb_types-1][0..child_pb_type->num_pb-1] */
     vtr::vector<PhysicalPbId, std::map<const t_pb_type*, std::vector<PhysicalPbId>>> child_pbs_;
diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp
index a32366be0..39697f100 100644
--- a/openfpga/src/repack/repack.cpp
+++ b/openfpga/src/repack/repack.cpp
@@ -278,17 +278,20 @@ void add_lb_router_nets(LbRouter& lb_router,
     VTR_ASSERT(sink_lb_rr_nodes.size() == sink_pb_graph_pins.size());
 
     /* Printf for debugging only, may be enabled if verbose is enabled
-    VTR_LOG("Pb route for Net %s:\n", 
-            atom_ctx.nlist.net_name(atom_net_id).c_str());
-    VTR_LOG("Source node:\n\t%s -> %s\n",
-            source_pb_pin->to_string().c_str(),
-            source_pb_pin->to_string().c_str());
-    VTR_LOG("Sink nodes:\n");
-    for (t_pb_graph_pin* sink_pb_pin : sink_pb_graph_pins) {
-      VTR_LOG("\t%s\n",
-              sink_pb_pin->to_string().c_str());
-    }
      */
+    VTR_LOGV(verbose,
+             "Pb route for Net %s:\n", 
+             atom_ctx.nlist.net_name(atom_net_id).c_str());
+    VTR_LOGV(verbose,
+             "Source node:\n\t%s -> %s\n",
+             source_pb_pin->to_string().c_str(),
+             source_pb_pin->to_string().c_str());
+    VTR_LOGV(verbose, "Sink nodes:\n");
+    for (t_pb_graph_pin* sink_pb_pin : sink_pb_graph_pins) {
+      VTR_LOGV(verbose,
+               "\t%s\n",
+               sink_pb_pin->to_string().c_str());
+    }
 
     /* Add the net */
     add_lb_router_net_to_route(lb_router, lb_rr_graph,
@@ -341,17 +344,20 @@ void add_lb_router_nets(LbRouter& lb_router,
     VTR_ASSERT(sink_lb_rr_nodes.size() == sink_pb_graph_pins.size());
 
     /* Printf for debugging only, may be enabled if verbose is enabled
-    VTR_LOG("Pb route for Net %s:\n", 
-            atom_ctx.nlist.net_name(atom_net_id).c_str());
-    VTR_LOG("Source node:\n\t%s -> %s\n",
-            source_pb_pin->to_string().c_str(),
-            physical_source_pb_pin->to_string().c_str());
-    VTR_LOG("Sink nodes:\n");
-    for (t_pb_graph_pin* sink_pb_pin : sink_pb_graph_pins) {
-      VTR_LOG("\t%s\n",
-              sink_pb_pin->to_string().c_str());
-    }
      */
+    VTR_LOGV(verbose,
+             "Pb route for Net %s:\n", 
+             atom_ctx.nlist.net_name(atom_net_id).c_str());
+    VTR_LOGV(verbose,
+             "Source node:\n\t%s -> %s\n",
+             source_pb_pin->to_string().c_str(),
+             physical_source_pb_pin->to_string().c_str());
+    VTR_LOGV(verbose, "Sink nodes:\n");
+    for (t_pb_graph_pin* sink_pb_pin : sink_pb_graph_pins) {
+      VTR_LOGV(verbose,
+               "\t%s\n",
+               sink_pb_pin->to_string().c_str());
+    }
 
     /* Add the net */
     add_lb_router_net_to_route(lb_router, lb_rr_graph,
@@ -429,7 +435,8 @@ void repack_cluster(const AtomContext& atom_ctx,
                                            clustering_ctx.clb_nlist.block_pb(block_id),
                                            clustering_ctx.clb_nlist.block_pb(block_id)->pb_route,
                                            atom_ctx,
-                                           device_annotation);
+                                           device_annotation,
+                                           verbose);
   /* Save routing results */
   save_lb_router_results_to_physical_pb(phy_pb, lb_router, lb_rr_graph);
   VTR_LOGV(verbose, "Saved results in physical pb\n");
diff --git a/openfpga/src/utils/lut_utils.cpp b/openfpga/src/utils/lut_utils.cpp
index ca3ac343e..35f613c73 100644
--- a/openfpga/src/utils/lut_utils.cpp
+++ b/openfpga/src/utils/lut_utils.cpp
@@ -473,6 +473,29 @@ std::vector<bool> build_frac_lut_bitstream(const CircuitLibrary& circuit_lib,
     VTR_ASSERT(bitstream_offset < lut_bitstream.size());
     VTR_ASSERT(bitstream_offset + length_of_temp_bitstream_to_copy <= lut_bitstream.size());
 
+    /* Print debug information 
+    bool verbose = true;
+    VTR_LOGV(verbose, "Full truth table\n");
+    for (const std::string& tt_line : truth_table_to_string(element.second)) {
+      VTR_LOGV(verbose, "\t%s\n", tt_line.c_str());
+    }
+    VTR_LOGV(verbose, "\n");
+
+    VTR_LOGV(verbose, "Bitstream (size = %ld)\n", temp_bitstream.size());
+    for (const bool& bit : temp_bitstream) {
+      if (true == bit) {
+        VTR_LOGV(verbose, "1");
+      } else {
+        VTR_ASSERT(false == bit);
+        VTR_LOGV(verbose, "0");
+      }
+    }
+    VTR_LOGV(verbose, "\n");
+
+    VTR_LOGV(verbose, "Bitstream offset = %d\n", bitstream_offset);
+    VTR_LOGV(verbose, "Bitstream length to be used = %d\n", length_of_temp_bitstream_to_copy);
+     */
+
     /* Copy to the segment of bitstream */
     for (size_t bit = bitstream_offset; bit < bitstream_offset + length_of_temp_bitstream_to_copy; ++bit) {
       lut_bitstream[bit] = temp_bitstream[bit];
diff --git a/openfpga/src/utils/pb_type_utils.h b/openfpga/src/utils/pb_type_utils.h
index 6a4dd91be..5d23f23bc 100644
--- a/openfpga/src/utils/pb_type_utils.h
+++ b/openfpga/src/utils/pb_type_utils.h
@@ -17,6 +17,15 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
+/* Constants */
+
+/* Mode index of a LUT pb_type
+ * Mode 0 is the wire mode
+ * Mode 1 is the lut mode
+ */
+constexpr int VPR_PB_TYPE_WIRE_MODE = 0;
+constexpr int VPR_PB_TYPE_LUT_MODE = 1;
+
 bool is_primitive_pb_type(t_pb_type* pb_type); 
 
 bool is_root_pb_type(t_pb_type* pb_type);
diff --git a/openfpga/src/utils/physical_pb_utils.cpp b/openfpga/src/utils/physical_pb_utils.cpp
index 93fbba992..cd1b13a4b 100644
--- a/openfpga/src/utils/physical_pb_utils.cpp
+++ b/openfpga/src/utils/physical_pb_utils.cpp
@@ -132,6 +132,16 @@ void update_primitive_physical_pb_pin_atom_net(PhysicalPb& phy_pb,
     t_pb_graph_pin* physical_pb_graph_pin = device_annotation.physical_pb_graph_pin(pb_graph_pin);
     VTR_ASSERT(nullptr != physical_pb_graph_pin);
 
+    /* Print info to help debug 
+    bool verbose = true;
+    VTR_LOGV(verbose,
+             "\nSynchronize net '%lu' to physical pb_graph_pin '%s.%s[%d]'\n",
+             size_t(atom_net),
+             pb_graph_pin->parent_node->pb_type->name,
+             pb_graph_pin->port->name,
+             pb_graph_pin->pin_number);
+     */
+
     /* Check if the pin has been mapped to a net.
      * If yes, the atom net must be the same 
      */
@@ -155,6 +165,7 @@ void synchronize_primitive_physical_pb_atom_nets(PhysicalPb& phy_pb,
                                                  const AtomBlockId& atom_blk,
                                                  const VprDeviceAnnotation& device_annotation) {
   /* Iterate over all the ports: input, output and clock */
+
   for (int iport = 0; iport < pb_graph_node->num_input_ports; ++iport) {
     for (int ipin = 0; ipin < pb_graph_node->num_input_pins[iport]; ++ipin) {
       /* Port exists (some LUTs may have no input and hence no port in the atom netlist) */
@@ -219,6 +230,46 @@ void synchronize_primitive_physical_pb_atom_nets(PhysicalPb& phy_pb,
   }
 }
 
+/************************************************************************
+ * Reach this function, the primitive pb should be 
+ * - linked to a LUT pb_type
+ * - operating in the wire mode of a LUT
+ *
+ * Note: this function will not check the prequistics here
+ *       Users must be responsible for this!!!
+ *
+ * This function will find the physical pb_graph_pin for each output 
+ * of the pb_graph node and mark in the physical_pb database
+ * as driven by an wired LUT
+ ***********************************************************************/
+static 
+void mark_physical_pb_wired_lut_outputs(PhysicalPb& phy_pb, 
+                                        const PhysicalPbId& primitive_pb,
+                                        const t_pb_graph_node* pb_graph_node,
+                                        const VprDeviceAnnotation& device_annotation,
+                                        const bool& verbose) {
+
+  for (int iport = 0; iport < pb_graph_node->num_output_ports; ++iport) {
+    for (int ipin = 0; ipin < pb_graph_node->num_output_pins[iport]; ++ipin) {
+      t_pb_graph_pin* pb_graph_pin = &(pb_graph_node->output_pins[iport][ipin]);
+
+      /* Find the physical pb_graph_pin */
+      t_pb_graph_pin* physical_pb_graph_pin = device_annotation.physical_pb_graph_pin(pb_graph_pin);
+      VTR_ASSERT(nullptr != physical_pb_graph_pin);
+
+      /* Print debug info */
+      VTR_LOGV(verbose,
+               "Mark physical pb_graph pin '%s.%s[%d]' as wire LUT output\n",
+               physical_pb_graph_pin->parent_node->pb_type->name,
+               physical_pb_graph_pin->port->name,
+               physical_pb_graph_pin->pin_number);
+
+      /* Label the pins in physical_pb as driven by wired LUT*/
+      phy_pb.set_wire_lut_output(primitive_pb, physical_pb_graph_pin, true);
+    }
+  }
+}
+
 /************************************************************************
  * Synchronize mapping results from an operating pb to a physical pb
  ***********************************************************************/
@@ -226,7 +277,8 @@ void rec_update_physical_pb_from_operating_pb(PhysicalPb& phy_pb,
                                               const t_pb* op_pb,
                                               const t_pb_routes& pb_route,
                                               const AtomContext& atom_ctx,
-                                              const VprDeviceAnnotation& device_annotation) {
+                                              const VprDeviceAnnotation& device_annotation,
+                                              const bool& verbose) {
   t_pb_graph_node* pb_graph_node = op_pb->pb_graph_node;
   t_pb_type* pb_type = pb_graph_node->pb_type;
 
@@ -265,7 +317,49 @@ void rec_update_physical_pb_from_operating_pb(PhysicalPb& phy_pb,
                                                  &(op_pb->child_pbs[ipb][jpb]),
                                                  pb_route,
                                                  atom_ctx,
-                                                 device_annotation);
+                                                 device_annotation,
+                                                 verbose);
+      } else {
+        /* Some pb may be used just in routing purpose, find out the output nets  */
+        /* The following code is inspired by output_cluster.cpp */
+        bool is_used = false;
+        t_pb_type* child_pb_type = &(mapped_mode->pb_type_children[ipb]);
+        int port_index = 0;
+        t_pb_graph_node* child_pb_graph_node = &(pb_graph_node->child_pb_graph_nodes[op_pb->mode][ipb][jpb]);
+
+        for (int k = 0; k < child_pb_type->num_ports && !is_used; k++) {
+          if (OUT_PORT == child_pb_type->ports[k].type) {
+            for (int m = 0; m < child_pb_type->ports[k].num_pins; m++) {
+              int node_index = child_pb_graph_node->output_pins[port_index][m].pin_count_in_cluster;
+              if (pb_route.count(node_index) && pb_route[node_index].atom_net_id) {
+                is_used = true;
+                break;
+              }
+            }
+            port_index++;
+          }
+        }
+        /* Identify output pb_graph_pin that is driven by a wired LUT
+         * Without this function, physical Look-Up Table build-up will cause errors
+         * and bitstream will be incorrect!!!
+         */
+        if (true == is_used) {
+          VTR_ASSERT(LUT_CLASS == child_pb_type->class_type);
+
+          t_pb_graph_node* physical_pb_graph_node = device_annotation.physical_pb_graph_node(child_pb_graph_node);
+          VTR_ASSERT(nullptr != physical_pb_graph_node);
+          /* Find the physical pb */
+          const PhysicalPbId& physical_pb = phy_pb.find_pb(physical_pb_graph_node);
+          VTR_ASSERT(true == phy_pb.valid_pb_id(physical_pb));
+
+          /* Set the mode bits */
+          phy_pb.set_mode_bits(physical_pb, device_annotation.pb_type_mode_bits(child_pb_type));
+
+          mark_physical_pb_wired_lut_outputs(phy_pb, physical_pb,
+                                             child_pb_graph_node,
+                                             device_annotation,
+                                             verbose);
+        }
       }
     }
   }
diff --git a/openfpga/src/utils/physical_pb_utils.h b/openfpga/src/utils/physical_pb_utils.h
index 0e8bb71df..227feec6c 100644
--- a/openfpga/src/utils/physical_pb_utils.h
+++ b/openfpga/src/utils/physical_pb_utils.h
@@ -28,7 +28,8 @@ void rec_update_physical_pb_from_operating_pb(PhysicalPb& phy_pb,
                                               const t_pb* op_pb,
                                               const t_pb_routes& pb_route,
                                               const AtomContext& atom_ctx,
-                                              const VprDeviceAnnotation& device_annotation);
+                                              const VprDeviceAnnotation& device_annotation,
+                                              const bool& verbose);
 
 } /* end namespace openfpga */
 
diff --git a/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf b/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf
index f9276b42b..cd002c9d4 100644
--- a/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf
@@ -21,8 +21,8 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
-#bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.blif
+#bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
+bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.blif
 
 [SYNTHESIS_PARAM]
 bench0_top = top
@@ -30,8 +30,8 @@ bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/
 bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
 
 bench1_top = top
-bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and_latch.act
-bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and_latch.v
+bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.act
+bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.v
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
 end_flow_with_test=

From 8b03ec900ff23dfc7461dfc414ebdd461174e51c Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 19 Apr 2020 17:05:12 -0600
Subject: [PATCH 452/645] fine-tune micro benchmark to fit port mapping in
 testbenches

---
 .../benchmarks/micro_benchmark/and_latch/and_latch.v         | 2 +-
 openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf | 5 +++--
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.v b/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.v
index 893cdf7a4..a8f147f5b 100644
--- a/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.v
+++ b/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.v
@@ -1,9 +1,9 @@
 `timescale 1ns / 1ps
 
 module top(
-  clk,
   a,
   b,
+  clk,
   c,
   d);
 
diff --git a/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf b/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf
index cd002c9d4..76c70bb6c 100644
--- a/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf
@@ -21,8 +21,9 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
 
 [BENCHMARKS]
-#bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
-bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
+# Modelsim is ok with this but icarus fails due to poor support on timing and looping
+#bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.blif
 
 [SYNTHESIS_PARAM]
 bench0_top = top

From f6b7583a2aef52031b206957876b6538d7316f1c Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 20 Apr 2020 12:55:40 -0600
Subject: [PATCH 453/645] add tasks for single mode

---
 .../k6_N10_tileable_40nm.xml                  |  6 +--
 .../openfpga_arch/k6_N10_40nm_openfpga.xml    |  4 +-
 .../mcnc_big20/config/task.conf               | 40 +++++++++----------
 .../single_mode/config/task.conf              | 38 ++++++++++++++++++
 4 files changed, 63 insertions(+), 25 deletions(-)
 create mode 100644 openfpga_flow/tasks/openfpga_shell/single_mode/config/task.conf

diff --git a/openfpga_flow/arch/vpr_only_templates/k6_N10_tileable_40nm.xml b/openfpga_flow/arch/vpr_only_templates/k6_N10_tileable_40nm.xml
index f9065d437..fcbc20437 100644
--- a/openfpga_flow/arch/vpr_only_templates/k6_N10_tileable_40nm.xml
+++ b/openfpga_flow/arch/vpr_only_templates/k6_N10_tileable_40nm.xml
@@ -54,7 +54,7 @@
         <site pb_type="clb"/>
       </equivalent_sites>
       <input name="I" num_pins="40" equivalent="full"/>
-      <output name="O" num_pins="10" equivalent="instance"/>
+      <output name="O" num_pins="10" equivalent="none"/>
       <clock name="clk" num_pins="1"/>
       <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
       <pinlocations pattern="spread"/>
@@ -137,7 +137,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" disabled_in_pack="true">
+      <mode name="physical" packable="false">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -197,7 +197,7 @@
 	   -->
     <pb_type name="clb">
       <input name="I" num_pins="40" equivalent="full"/>
-      <output name="O" num_pins="10" equivalent="instance"/>
+      <output name="O" num_pins="10" equivalent="none"/>
       <clock name="clk" num_pins="1"/>
       <!-- Describe basic logic element.  
              Each basic logic element has a 6-LUT that can be optionally registered
diff --git a/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml
index de0602e1e..c3385e96c 100644
--- a/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml
@@ -146,11 +146,11 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <port type="input" prefix="pReset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
        <port type="input" prefix="D" size="1"/>
        <port type="output" prefix="Q" size="1"/>
        <port type="output" prefix="Qb" size="1"/>
-       <port type="clock" prefix="prog_clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
     </circuit_model>
     <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
       <design_technology type="cmos"/>
diff --git a/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf b/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf
index f28150126..bab48c1fd 100644
--- a/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf
@@ -21,27 +21,27 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif 
-bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif
-bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.blif
-# VPR remove dangling PIs and POs which are in act file. Then VPR errors out by saying these PI/PO should not exist in act file
-#bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.blif
-bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.blif
-bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.blif
-bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.blif
-bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.blif
-bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.blif
-bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.blif
-bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.blif
-bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.blif
-bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.blif
-bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.blif
+#bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif 
+#bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif
+#bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.blif
+## VPR remove dangling PIs and POs which are in act file. Then VPR errors out by saying these PI/PO should not exist in act file
+##bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.blif
+#bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.blif
+#bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.blif
+#bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.blif
+#bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.blif
+#bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.blif
+#bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.blif
+#bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.blif
+#bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.blif
+#bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.blif
+#bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.blif
 bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.blif 
-bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.blif 
-bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.blif
-bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.blif
-bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.blif
-bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.blif
+#bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.blif 
+#bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.blif
+#bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.blif
+#bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.blif
+#bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.blif
 
 [SYNTHESIS_PARAM]
 # Benchmark alu4 
diff --git a/openfpga_flow/tasks/openfpga_shell/single_mode/config/task.conf b/openfpga_flow/tasks/openfpga_shell/single_mode/config/task.conf
new file mode 100644
index 000000000..566b7e353
--- /dev/null
+++ b/openfpga_flow/tasks/openfpga_shell/single_mode/config/task.conf
@@ -0,0 +1,38 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_N10_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
+bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = top
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
+
+bench1_top = top
+bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.act
+bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.v
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

From 489ca752300526ffa2b512cf227027dbbca1e0f6 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 20 Apr 2020 13:15:05 -0600
Subject: [PATCH 454/645] adapt benchmark and_latch module name to be different
 than benchmark and

---
 .../benchmarks/micro_benchmark/and_latch/and_latch.blif       | 4 ++--
 .../benchmarks/micro_benchmark/and_latch/and_latch.v          | 2 +-
 openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf  | 2 +-
 .../tasks/openfpga_shell/single_mode/config/task.conf         | 2 +-
 4 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.blif b/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.blif
index dbd863d9c..0a064691b 100644
--- a/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.blif
+++ b/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.blif
@@ -1,5 +1,5 @@
-# Benchmark "top" written by ABC on Wed Mar 11 10:36:28 2020
-.model top
+# Benchmark "and_latch" written by ABC on Wed Mar 11 10:36:28 2020
+.model and_latch
 .inputs a b clk
 .outputs c d
 
diff --git a/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.v b/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.v
index a8f147f5b..b874d558c 100644
--- a/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.v
+++ b/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.v
@@ -1,6 +1,6 @@
 `timescale 1ns / 1ps
 
-module top(
+module and_latch(
   a,
   b,
   clk,
diff --git a/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf b/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf
index 76c70bb6c..d1d9ba17e 100644
--- a/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf
@@ -30,7 +30,7 @@ bench0_top = top
 bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
 bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
 
-bench1_top = top
+bench1_top = and_latch
 bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.act
 bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.v
 
diff --git a/openfpga_flow/tasks/openfpga_shell/single_mode/config/task.conf b/openfpga_flow/tasks/openfpga_shell/single_mode/config/task.conf
index 566b7e353..714874d13 100644
--- a/openfpga_flow/tasks/openfpga_shell/single_mode/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/single_mode/config/task.conf
@@ -29,7 +29,7 @@ bench0_top = top
 bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
 bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
 
-bench1_top = top
+bench1_top = and_latch
 bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.act
 bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.v
 

From f06f2d72be705963c9dc3f9a42fed660bdc88c56 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 20 Apr 2020 13:16:52 -0600
Subject: [PATCH 455/645] deploy single mode in regression tests

---
 .travis/script.sh | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/.travis/script.sh b/.travis/script.sh
index b577ee48c..fd9b8616e 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -51,6 +51,9 @@ echo -e "Testing OpenFPGA Shell";
 echo -e "Testing configuration chain of a K4N4 FPGA";
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/configuration_chain --debug --show_thread_logs
 
+echo -e "Testing Verilog generation for a single mode LUT6 FPGA using micro benchmarks";
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/single_mode --debug --show_thread_logs
+
 echo -e "Testing Verilog generation with simple fracturable LUT6 ";
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/frac_lut --debug --show_thread_logs
 

From 9761d13eefc1b83565aa5e85807e452037fdaae9 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 20 Apr 2020 13:37:39 -0600
Subject: [PATCH 456/645] update microbenchmark and2 module name

---
 .../benchmarks/micro_benchmark/and/and.v      | 14 ---------
 .../{and/and.act => and2/and2.act}            |  0
 .../{and/and.blif => and2/and2.blif}          |  2 +-
 .../benchmarks/micro_benchmark/and2/and2.v    | 18 ++++++++++++
 .../and2_latch.act}                           |  0
 .../and2_latch.blif}                          |  4 +--
 .../micro_benchmark/and2_latch/and2_latch.v   | 29 +++++++++++++++++++
 .../micro_benchmark/and_latch/and_latch.v     | 23 ---------------
 .../behavioral_verilog/config/task.conf       |  8 ++---
 .../bram/dpram16k/config/task.conf            |  8 ++---
 .../bram/wide_dpram16k/config/task.conf       |  8 ++---
 .../configuration_chain/config/task.conf      |  8 ++---
 .../duplicated_grid_pin/config/task.conf      |  8 ++---
 .../fabric_chain/adder_chain/config/task.conf |  8 ++---
 .../register_chain/config/task.conf           |  8 ++---
 .../fabric_chain/scan_chain/config/task.conf  |  8 ++---
 .../flatten_routing/config/task.conf          |  8 ++---
 .../openfpga_shell/frac_lut/config/task.conf  | 16 +++++-----
 .../hard_adder/config/task.conf               |  8 ++---
 .../implicit_verilog/config/task.conf         |  8 ++---
 .../openfpga_shell/io/aib/config/task.conf    |  8 ++---
 .../io/multi_io_capacity/config/task.conf     |  8 ++---
 .../io/reduced_io/config/task.conf            |  8 ++---
 .../mux_design/stdcell_mux2/config/task.conf  |  8 ++---
 .../tree_structure/config/task.conf           |  8 ++---
 .../single_mode/config/task.conf              | 16 +++++-----
 .../untileable/config/task.conf               |  8 ++---
 27 files changed, 134 insertions(+), 124 deletions(-)
 delete mode 100644 openfpga_flow/benchmarks/micro_benchmark/and/and.v
 rename openfpga_flow/benchmarks/micro_benchmark/{and/and.act => and2/and2.act} (100%)
 rename openfpga_flow/benchmarks/micro_benchmark/{and/and.blif => and2/and2.blif} (80%)
 create mode 100644 openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
 rename openfpga_flow/benchmarks/micro_benchmark/{and_latch/and_latch.act => and2_latch/and2_latch.act} (100%)
 rename openfpga_flow/benchmarks/micro_benchmark/{and_latch/and_latch.blif => and2_latch/and2_latch.blif} (52%)
 create mode 100644 openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
 delete mode 100644 openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.v

diff --git a/openfpga_flow/benchmarks/micro_benchmark/and/and.v b/openfpga_flow/benchmarks/micro_benchmark/and/and.v
deleted file mode 100644
index 876f1c6fe..000000000
--- a/openfpga_flow/benchmarks/micro_benchmark/and/and.v
+++ /dev/null
@@ -1,14 +0,0 @@
-`timescale 1ns / 1ps
-
-module top(
-  a,
-  b,
-  c);
-
-input wire a;
-input wire b;
-output wire c;
-
-assign c = a & b;
-
-endmodule
diff --git a/openfpga_flow/benchmarks/micro_benchmark/and/and.act b/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
similarity index 100%
rename from openfpga_flow/benchmarks/micro_benchmark/and/and.act
rename to openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
diff --git a/openfpga_flow/benchmarks/micro_benchmark/and/and.blif b/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
similarity index 80%
rename from openfpga_flow/benchmarks/micro_benchmark/and/and.blif
rename to openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
index 67d978741..d13bdc564 100644
--- a/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
+++ b/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
@@ -1,4 +1,4 @@
-.model top
+.model and2
 .inputs a b
 .outputs c
 
diff --git a/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v b/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
new file mode 100644
index 000000000..a23293c58
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
@@ -0,0 +1,18 @@
+/////////////////////////////////////////
+//  Functionality: 2-input AND 
+//  Author:        Xifan Tang
+////////////////////////////////////////
+`timescale 1ns / 1ps
+
+module and2(
+  a,
+  b,
+  c);
+
+input wire a;
+input wire b;
+output wire c;
+
+assign c = a & b;
+
+endmodule
diff --git a/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.act b/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.act
similarity index 100%
rename from openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.act
rename to openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.act
diff --git a/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.blif b/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.blif
similarity index 52%
rename from openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.blif
rename to openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.blif
index 0a064691b..96450e30a 100644
--- a/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.blif
+++ b/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.blif
@@ -1,5 +1,5 @@
-# Benchmark "and_latch" written by ABC on Wed Mar 11 10:36:28 2020
-.model and_latch
+# Benchmark "and2_latch" written by ABC on Wed Mar 11 10:36:28 2020
+.model and2_latch
 .inputs a b clk
 .outputs c d
 
diff --git a/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v b/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
new file mode 100644
index 000000000..135454daa
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
@@ -0,0 +1,29 @@
+/////////////////////////////////////////
+//  Functionality: 2-input AND with clocked 
+//                 and combinational outputs 
+//  Author:        Xifan Tang
+////////////////////////////////////////
+
+`timescale 1ns / 1ps
+
+module and2_latch(
+  a,
+  b,
+  clk,
+  c,
+  d);
+
+input wire clk;
+
+input wire a;
+input wire b;
+output wire c;
+output reg d;
+
+assign c = a & b;
+
+always @(posedge clk) begin
+  d <= c;
+end
+
+endmodule
diff --git a/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.v b/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.v
deleted file mode 100644
index b874d558c..000000000
--- a/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.v
+++ /dev/null
@@ -1,23 +0,0 @@
-`timescale 1ns / 1ps
-
-module and_latch(
-  a,
-  b,
-  clk,
-  c,
-  d);
-
-input wire clk;
-
-input wire a;
-input wire b;
-output wire c;
-output reg d;
-
-assign c = a & b;
-
-always @(posedge clk) begin
-  d <= c;
-end
-
-endmodule
diff --git a/openfpga_flow/tasks/openfpga_shell/behavioral_verilog/config/task.conf b/openfpga_flow/tasks/openfpga_shell/behavioral_verilog/config/task.conf
index c7c111313..e11da844f 100644
--- a/openfpga_flow/tasks/openfpga_shell/behavioral_verilog/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/behavioral_verilog/config/task.conf
@@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
 
 [SYNTHESIS_PARAM]
-bench0_top = top
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
diff --git a/openfpga_flow/tasks/openfpga_shell/bram/dpram16k/config/task.conf b/openfpga_flow/tasks/openfpga_shell/bram/dpram16k/config/task.conf
index cb3632359..4996f42e2 100644
--- a/openfpga_flow/tasks/openfpga_shell/bram/dpram16k/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/bram/dpram16k/config/task.conf
@@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
 
 [SYNTHESIS_PARAM]
-bench0_top = top
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
diff --git a/openfpga_flow/tasks/openfpga_shell/bram/wide_dpram16k/config/task.conf b/openfpga_flow/tasks/openfpga_shell/bram/wide_dpram16k/config/task.conf
index 756b2980e..5cfc3ce57 100644
--- a/openfpga_flow/tasks/openfpga_shell/bram/wide_dpram16k/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/bram/wide_dpram16k/config/task.conf
@@ -22,12 +22,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
 
 [SYNTHESIS_PARAM]
-bench0_top = top
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
diff --git a/openfpga_flow/tasks/openfpga_shell/configuration_chain/config/task.conf b/openfpga_flow/tasks/openfpga_shell/configuration_chain/config/task.conf
index 5dca0428c..79781a758 100644
--- a/openfpga_flow/tasks/openfpga_shell/configuration_chain/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/configuration_chain/config/task.conf
@@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
 
 [SYNTHESIS_PARAM]
-bench0_top = top
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
diff --git a/openfpga_flow/tasks/openfpga_shell/duplicated_grid_pin/config/task.conf b/openfpga_flow/tasks/openfpga_shell/duplicated_grid_pin/config/task.conf
index 03c54d43f..f2777f7ee 100644
--- a/openfpga_flow/tasks/openfpga_shell/duplicated_grid_pin/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/duplicated_grid_pin/config/task.conf
@@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
 
 [SYNTHESIS_PARAM]
-bench0_top = top
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
diff --git a/openfpga_flow/tasks/openfpga_shell/fabric_chain/adder_chain/config/task.conf b/openfpga_flow/tasks/openfpga_shell/fabric_chain/adder_chain/config/task.conf
index 82afc9a11..5e9533e36 100644
--- a/openfpga_flow/tasks/openfpga_shell/fabric_chain/adder_chain/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/fabric_chain/adder_chain/config/task.conf
@@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
 
 [SYNTHESIS_PARAM]
-bench0_top = top
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
diff --git a/openfpga_flow/tasks/openfpga_shell/fabric_chain/register_chain/config/task.conf b/openfpga_flow/tasks/openfpga_shell/fabric_chain/register_chain/config/task.conf
index 5c1ec8fb9..1b76cb3e9 100644
--- a/openfpga_flow/tasks/openfpga_shell/fabric_chain/register_chain/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/fabric_chain/register_chain/config/task.conf
@@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_chain_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
 
 [SYNTHESIS_PARAM]
-bench0_top = top
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
diff --git a/openfpga_flow/tasks/openfpga_shell/fabric_chain/scan_chain/config/task.conf b/openfpga_flow/tasks/openfpga_shell/fabric_chain/scan_chain/config/task.conf
index 7a98b0731..ac398aa4c 100644
--- a/openfpga_flow/tasks/openfpga_shell/fabric_chain/scan_chain/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/fabric_chain/scan_chain/config/task.conf
@@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
 
 [SYNTHESIS_PARAM]
-bench0_top = top
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
diff --git a/openfpga_flow/tasks/openfpga_shell/flatten_routing/config/task.conf b/openfpga_flow/tasks/openfpga_shell/flatten_routing/config/task.conf
index 7823bee48..2879e95ed 100644
--- a/openfpga_flow/tasks/openfpga_shell/flatten_routing/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/flatten_routing/config/task.conf
@@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
 
 [SYNTHESIS_PARAM]
-bench0_top = top
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
diff --git a/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf b/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf
index d1d9ba17e..a69c1107e 100644
--- a/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf
@@ -21,18 +21,18 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
 # Modelsim is ok with this but icarus fails due to poor support on timing and looping
-#bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.blif
+#bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.blif
 
 [SYNTHESIS_PARAM]
-bench0_top = top
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
 
-bench1_top = and_latch
-bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.act
-bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.v
+bench1_top = and2_latch
+bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.act
+bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
 end_flow_with_test=
diff --git a/openfpga_flow/tasks/openfpga_shell/hard_adder/config/task.conf b/openfpga_flow/tasks/openfpga_shell/hard_adder/config/task.conf
index cd63c7064..c0198598e 100644
--- a/openfpga_flow/tasks/openfpga_shell/hard_adder/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/hard_adder/config/task.conf
@@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
 
 [SYNTHESIS_PARAM]
-bench0_top = top
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
diff --git a/openfpga_flow/tasks/openfpga_shell/implicit_verilog/config/task.conf b/openfpga_flow/tasks/openfpga_shell/implicit_verilog/config/task.conf
index 24e443381..21751cc7f 100644
--- a/openfpga_flow/tasks/openfpga_shell/implicit_verilog/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/implicit_verilog/config/task.conf
@@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
 
 [SYNTHESIS_PARAM]
-bench0_top = top
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
diff --git a/openfpga_flow/tasks/openfpga_shell/io/aib/config/task.conf b/openfpga_flow/tasks/openfpga_shell/io/aib/config/task.conf
index d71cc949f..0f4727657 100644
--- a/openfpga_flow/tasks/openfpga_shell/io/aib/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/io/aib/config/task.conf
@@ -32,12 +32,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
 
 [SYNTHESIS_PARAM]
-bench0_top = top
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
diff --git a/openfpga_flow/tasks/openfpga_shell/io/multi_io_capacity/config/task.conf b/openfpga_flow/tasks/openfpga_shell/io/multi_io_capacity/config/task.conf
index ee003aa84..8ae3286c5 100644
--- a/openfpga_flow/tasks/openfpga_shell/io/multi_io_capacity/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/io/multi_io_capacity/config/task.conf
@@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
 
 [SYNTHESIS_PARAM]
-bench0_top = top
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
diff --git a/openfpga_flow/tasks/openfpga_shell/io/reduced_io/config/task.conf b/openfpga_flow/tasks/openfpga_shell/io/reduced_io/config/task.conf
index 7d2be5aa5..190acfda7 100644
--- a/openfpga_flow/tasks/openfpga_shell/io/reduced_io/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/io/reduced_io/config/task.conf
@@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
 
 [SYNTHESIS_PARAM]
-bench0_top = top
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
diff --git a/openfpga_flow/tasks/openfpga_shell/mux_design/stdcell_mux2/config/task.conf b/openfpga_flow/tasks/openfpga_shell/mux_design/stdcell_mux2/config/task.conf
index 3aa07c229..60df151e7 100644
--- a/openfpga_flow/tasks/openfpga_shell/mux_design/stdcell_mux2/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/mux_design/stdcell_mux2/config/task.conf
@@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
 
 [SYNTHESIS_PARAM]
-bench0_top = top
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
diff --git a/openfpga_flow/tasks/openfpga_shell/mux_design/tree_structure/config/task.conf b/openfpga_flow/tasks/openfpga_shell/mux_design/tree_structure/config/task.conf
index 2b164ecf5..3f8b56582 100644
--- a/openfpga_flow/tasks/openfpga_shell/mux_design/tree_structure/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/mux_design/tree_structure/config/task.conf
@@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
 
 [SYNTHESIS_PARAM]
-bench0_top = top
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
diff --git a/openfpga_flow/tasks/openfpga_shell/single_mode/config/task.conf b/openfpga_flow/tasks/openfpga_shell/single_mode/config/task.conf
index 714874d13..4216a7482 100644
--- a/openfpga_flow/tasks/openfpga_shell/single_mode/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/single_mode/config/task.conf
@@ -21,17 +21,17 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_N10_40nm
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_N10_tileable_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
-bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
+bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.blif
 
 [SYNTHESIS_PARAM]
-bench0_top = top
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
 
-bench1_top = and_latch
-bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.act
-bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and_latch/and_latch.v
+bench1_top = and2_latch
+bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.act
+bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
 end_flow_with_test=
diff --git a/openfpga_flow/tasks/openfpga_shell/untileable/config/task.conf b/openfpga_flow/tasks/openfpga_shell/untileable/config/task.conf
index c67f71c55..7dcf88915 100644
--- a/openfpga_flow/tasks/openfpga_shell/untileable/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/untileable/config/task.conf
@@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
 
 [SYNTHESIS_PARAM]
-bench0_top = top
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]

From 1a8968cb3778d59459c3a8d80ba450f305123b9b Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 20 Apr 2020 21:12:51 -0600
Subject: [PATCH 457/645] now FPGA-SDC will constrain timing for routing tracks
 using the VPR Rmetal parameter in ARCH XML

---
 .../src/fpga_sdc/pnr_sdc_routing_writer.cpp   | 39 +++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp
index d4f1ce522..a73ad8d30 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp
+++ b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp
@@ -334,6 +334,45 @@ void print_pnr_sdc_constrain_cb_timing(const std::string& sdc_dir,
   /* Generate the descriptions*/
   print_sdc_file_header(fp, std::string("Constrain timing of Connection Block " + cb_module_name + " for PnR"));
 
+  /* Contrain each routing track inside the connection block */
+  for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) {
+    /* Create a port description for the input */
+    std::string input_port_name = generate_cb_module_track_port_name(cb_type,
+                                                                     itrack,  
+                                                                     IN_PORT);
+    ModulePortId input_port_id = module_manager.find_module_port(cb_module, input_port_name);
+    BasicPort input_port = module_manager.module_port(cb_module, input_port_id);
+
+    /* Create a port description for the output */
+    std::string output_port_name = generate_cb_module_track_port_name(cb_type,
+                                                                      itrack,  
+                                                                      OUT_PORT);
+    ModulePortId output_port_id = module_manager.find_module_port(cb_module, output_port_name);
+    BasicPort output_port = module_manager.module_port(cb_module, output_port_id);
+
+    /* Ensure port size matching */
+    VTR_ASSERT(1 == input_port.get_width());
+    VTR_ASSERT(input_port.get_width() == output_port.get_width());
+
+    /* Connection block routing segment ids for each track */
+    RRSegmentId segment_id = rr_gsb.get_chan_node_segment(rr_gsb.get_cb_chan_side(cb_type), itrack);
+    float routing_segment_delay = rr_graph.get_segment(segment_id).Rmetal;
+
+    /* If we have a zero-delay path to contrain, we will skip unless users want so */
+    if ( (false == constrain_zero_delay_paths) 
+      && (0. == routing_segment_delay) ) {
+      continue;
+    }
+
+    /* Constrain a path with routing segment delay */
+    print_pnr_sdc_constrain_port2port_timing(fp,
+                                             module_manager, 
+                                             cb_module, input_port_id, 
+                                             cb_module, output_port_id,
+                                             routing_segment_delay);
+  }
+
+  /* Contrain each multiplexers inside the connection block */
   std::vector<enum e_side> cb_sides = rr_gsb.get_cb_ipin_sides(cb_type);
 
   for (size_t side = 0; side < cb_sides.size(); ++side) {

From c2804a4c1f04810f315f0a630781a09b44dcc9fd Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 20 Apr 2020 22:20:00 -0600
Subject: [PATCH 458/645] bug fix for RC delay computing in SDC generation

---
 openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp
index a73ad8d30..4bed8f16a 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp
+++ b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp
@@ -356,7 +356,14 @@ void print_pnr_sdc_constrain_cb_timing(const std::string& sdc_dir,
 
     /* Connection block routing segment ids for each track */
     RRSegmentId segment_id = rr_gsb.get_chan_node_segment(rr_gsb.get_cb_chan_side(cb_type), itrack);
-    float routing_segment_delay = rr_graph.get_segment(segment_id).Rmetal;
+
+    /* Computing the delay of the routing segment
+     * Here we just assume a simple 1-level RC delay model 
+     * TODO: Should consider multi-level RC delay models
+     *       where the number of levels are defined by users
+     */
+    float routing_segment_delay = rr_graph.get_segment(segment_id).Rmetal
+                                * rr_graph.get_segment(segment_id).Cmetal;
 
     /* If we have a zero-delay path to contrain, we will skip unless users want so */
     if ( (false == constrain_zero_delay_paths) 

From 3f1fb70d16d60f2eb3d016022d32af211b2e5506 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 21 Apr 2020 11:00:28 -0600
Subject: [PATCH 459/645] FPGA SDC now constrain max and min delay for
 primitive modules in grids

---
 openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp | 113 +++++++++++++++++-
 openfpga/src/fpga_sdc/sdc_writer_utils.cpp    |  32 +++++
 openfpga/src/fpga_sdc/sdc_writer_utils.h      |   7 ++
 3 files changed, 151 insertions(+), 1 deletion(-)

diff --git a/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp
index c6b50d797..f47ed3068 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp
+++ b/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp
@@ -281,6 +281,114 @@ void print_pnr_sdc_constrain_pb_graph_node_timing(const std::string& sdc_dir,
   fp.close();
 }
 
+/********************************************************************
+ * Print SDC timing constraints for a primitive pb_type
+ * This function will generate SDC to constrain pin-to-pin timing
+ * if it is defined in XML
+ *
+ * This is designed for LUT, adder or other hard IPs
+ * When PnR the modules, we want to minimize the interconnect delay
+ *******************************************************************/
+static 
+void print_pnr_sdc_constrain_primitive_pb_graph_node(const std::string& sdc_dir,
+                                                     const ModuleManager& module_manager,
+                                                     t_pb_graph_node* primitive_pb_graph_node,
+                                                     const bool& constrain_zero_delay_paths) {
+  /* Validate pb_graph node */
+  if (nullptr == primitive_pb_graph_node) {
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid primitive_pb_graph_node.\n");
+    exit(1);
+  }
+
+  /* Get the pb_type */
+  t_pb_type* primitive_pb_type = primitive_pb_graph_node->pb_type;
+
+  /* We can directly return if there is no timing annotation defined */
+  if (0 == primitive_pb_type->num_annotations) {
+    return;
+  } 
+
+  /* Get the pb_type definition related to the node */
+  t_pb_type* physical_pb_type = primitive_pb_graph_node->pb_type; 
+  std::string pb_module_name = generate_physical_block_module_name(physical_pb_type);
+
+  /* Find the pb module in module manager */
+  ModuleId pb_module = module_manager.find_module(pb_module_name);
+  VTR_ASSERT(true == module_manager.valid_module_id(pb_module));
+
+  /* Create the file name for SDC */
+  std::string sdc_fname(sdc_dir + pb_module_name + std::string(SDC_FILE_NAME_POSTFIX));
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(sdc_fname, std::fstream::out | std::fstream::trunc);
+
+  check_file_stream(sdc_fname.c_str(), fp);
+
+  /* Generate the descriptions*/
+  print_sdc_file_header(fp, std::string("Timing constraints for Grid " + pb_module_name + " in PnR"));
+
+  /* We traverse the pb_graph pins where we can find pin-to-pin timing annotation
+   * We walk through output pins here, build timing constraints by pair each output to input
+   * Clock pins are not walked through because they will be handled by clock tree synthesis
+   */
+  for (int iport = 0; iport < primitive_pb_graph_node->num_output_ports; ++iport) {
+    for (int ipin = 0; ipin < primitive_pb_graph_node->num_output_pins[iport]; ++ipin) {
+       t_pb_graph_pin* sink_pin = &(primitive_pb_graph_node->output_pins[iport][ipin]);
+
+       /* Port must exist in the module graph */
+       ModulePortId sink_module_port_id = module_manager.find_module_port(pb_module, generate_pb_type_port_name(sink_pin->port));
+       VTR_ASSERT(true == module_manager.valid_module_port_id(pb_module, sink_module_port_id));
+       BasicPort sink_port = module_manager.module_port(pb_module, sink_module_port_id);
+       /* Set the correct pin number of the port */
+       sink_port.set_width(sink_pin->pin_number, sink_pin->pin_number);
+
+       /* Find all the sink pin from this source pb_graph_pin */
+       for (int iedge = 0; iedge < sink_pin->num_input_edges; ++iedge) {
+         VTR_ASSERT(1 == sink_pin->input_edges[iedge]->num_input_pins);
+         t_pb_graph_pin* src_pin = sink_pin->input_edges[iedge]->input_pins[0];
+
+         /* Port must exist in the module graph */
+         ModulePortId src_module_port_id = module_manager.find_module_port(pb_module, generate_pb_type_port_name(src_pin->port));
+         VTR_ASSERT(true == module_manager.valid_module_port_id(pb_module, src_module_port_id));
+         BasicPort src_port = module_manager.module_port(pb_module, src_module_port_id);
+         /* Set the correct pin number of the port */
+         src_port.set_width(src_pin->pin_number, src_pin->pin_number);
+
+         /* Find max delay between src and sink pin */
+         float tmax = sink_pin->input_edges[iedge]->delay_max;
+         /* If the delay is zero, constrain only when user wants it */
+         if ( (true == constrain_zero_delay_paths)
+           || (0. == tmax) ) {
+           print_pnr_sdc_constrain_max_delay(fp, 
+                                             pb_module_name, 
+                                             generate_sdc_port(src_port),
+                                             pb_module_name, 
+                                             generate_sdc_port(sink_port),
+                                             tmax);
+         }
+
+         /* Find min delay between src and sink pin */
+         float tmin = sink_pin->input_edges[iedge]->delay_min;
+         /* If the delay is zero, constrain only when user wants it */
+         if ( (true == constrain_zero_delay_paths)
+           || (0. == tmin) ) {
+           print_pnr_sdc_constrain_min_delay(fp, 
+                                             pb_module_name, 
+                                             generate_sdc_port(src_port),
+                                             pb_module_name, 
+                                             generate_sdc_port(sink_port),
+                                             tmin);
+        } 
+      }
+    }
+  }
+
+  /* Close file handler */
+  fp.close();
+}
+
 /********************************************************************
  * Recursively print SDC timing constraints for a pb_type
  * This function will generate a SDC file for each pb_type,
@@ -302,8 +410,11 @@ void rec_print_pnr_sdc_constrain_pb_graph_timing(const std::string& sdc_dir,
   /* Get the pb_type */
   t_pb_type* parent_pb_type = parent_pb_graph_node->pb_type;
 
-  /* No need to constrain the primitive node */
+  /* Constrain the primitive node if a timing matrix is defined */
   if (true == is_primitive_pb_type(parent_pb_type)) {
+    print_pnr_sdc_constrain_primitive_pb_graph_node(sdc_dir, module_manager,
+                                                    parent_pb_graph_node,
+                                                    constrain_zero_delay_paths);
     return;
   }
 
diff --git a/openfpga/src/fpga_sdc/sdc_writer_utils.cpp b/openfpga/src/fpga_sdc/sdc_writer_utils.cpp
index 328f87ce6..363d97e1c 100644
--- a/openfpga/src/fpga_sdc/sdc_writer_utils.cpp
+++ b/openfpga/src/fpga_sdc/sdc_writer_utils.cpp
@@ -87,6 +87,38 @@ void print_pnr_sdc_constrain_max_delay(std::fstream& fp,
   fp << std::endl;
 }
 
+/********************************************************************
+ * Constrain a path between two ports of a module with a given minimum timing value
+ *******************************************************************/
+void print_pnr_sdc_constrain_min_delay(std::fstream& fp,
+                                       const std::string& src_instance_name,
+                                       const std::string& src_port_name,
+                                       const std::string& des_instance_name,
+                                       const std::string& des_port_name,
+                                       const float& delay) {
+  /* Validate file stream */
+  valid_file_stream(fp);
+
+  fp << "set_min_delay";
+
+  fp << " -from ";
+  if (!src_instance_name.empty()) {
+    fp << src_instance_name << "/";
+  }
+  fp << src_port_name;
+
+  fp << " -to ";
+ 
+  if (!des_instance_name.empty()) {
+    fp << des_instance_name << "/";
+  }
+  fp << des_port_name;
+
+  fp << " " << std::setprecision(10) << delay;
+
+  fp << std::endl;
+}
+
 /********************************************************************
  * Constrain a path between two ports of a module with a given timing value
  * Note: this function uses set_max_delay !!!
diff --git a/openfpga/src/fpga_sdc/sdc_writer_utils.h b/openfpga/src/fpga_sdc/sdc_writer_utils.h
index 4e0d86839..80f6e97e9 100644
--- a/openfpga/src/fpga_sdc/sdc_writer_utils.h
+++ b/openfpga/src/fpga_sdc/sdc_writer_utils.h
@@ -28,6 +28,13 @@ void print_pnr_sdc_constrain_max_delay(std::fstream& fp,
                                        const std::string& des_port_name,
                                        const float& delay);
 
+void print_pnr_sdc_constrain_min_delay(std::fstream& fp,
+                                       const std::string& src_instance_name,
+                                       const std::string& src_port_name,
+                                       const std::string& des_instance_name,
+                                       const std::string& des_port_name,
+                                       const float& delay);
+
 void print_pnr_sdc_constrain_module_port2port_timing(std::fstream& fp,
                                                      const ModuleManager& module_manager,
                                                      const ModuleId& input_parent_module_id, 

From d325bede6816bee63dba32d60ff8318e5d50074d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 21 Apr 2020 12:02:10 -0600
Subject: [PATCH 460/645] add fabric bitstream writer

---
 openfpga/src/base/openfpga_bitstream.cpp      | 17 +++++-
 .../src/base/openfpga_bitstream_command.cpp   |  5 ++
 ...m_writer.cpp => arch_bitstream_writer.cpp} |  2 +-
 ...tream_writer.h => arch_bitstream_writer.h} |  4 +-
 .../fabric_bitstream_writer.cpp               | 61 +++++++++++++++++++
 .../fpga_bitstream/fabric_bitstream_writer.h  | 24 ++++++++
 openfpga/test_script/and_k6_frac.openfpga     |  2 +-
 7 files changed, 110 insertions(+), 5 deletions(-)
 rename openfpga/src/fpga_bitstream/{bitstream_writer.cpp => arch_bitstream_writer.cpp} (99%)
 rename openfpga/src/fpga_bitstream/{bitstream_writer.h => arch_bitstream_writer.h} (91%)
 create mode 100644 openfpga/src/fpga_bitstream/fabric_bitstream_writer.cpp
 create mode 100644 openfpga/src/fpga_bitstream/fabric_bitstream_writer.h

diff --git a/openfpga/src/base/openfpga_bitstream.cpp b/openfpga/src/base/openfpga_bitstream.cpp
index 7e2a19fc4..e131a2bfc 100644
--- a/openfpga/src/base/openfpga_bitstream.cpp
+++ b/openfpga/src/base/openfpga_bitstream.cpp
@@ -12,7 +12,8 @@
 #include "openfpga_digest.h"
 
 #include "build_device_bitstream.h"
-#include "bitstream_writer.h"
+#include "arch_bitstream_writer.h"
+#include "fabric_bitstream_writer.h"
 #include "build_fabric_bitstream.h"
 #include "openfpga_bitstream.h"
 
@@ -56,10 +57,24 @@ int build_fabric_bitstream(OpenfpgaContext& openfpga_ctx,
                            const Command& cmd, const CommandContext& cmd_context) {
 
   CommandOptionId opt_verbose = cmd.option("verbose");
+  CommandOptionId opt_file = cmd.option("file");
 
+  /* Build fabric bitstream here */
   openfpga_ctx.mutable_fabric_bitstream() = build_fabric_dependent_bitstream(openfpga_ctx.bitstream_manager(),
                                                                              openfpga_ctx.module_graph(),
                                                                              cmd_context.option_enable(cmd, opt_verbose));
+
+  /* Write fabric bitstream if required */
+  if (true == cmd_context.option_enable(cmd, opt_file)) {
+    std::string src_dir_path = find_path_dir_name(cmd_context.option_value(cmd, opt_file));
+
+    /* Create directories */
+    create_directory(src_dir_path);
+
+    write_fabric_bitstream_to_text_file(openfpga_ctx.bitstream_manager(),
+                                        openfpga_ctx.fabric_bitstream(),
+                                        cmd_context.option_value(cmd, opt_file));
+  }
   
   /* TODO: should identify the error code from internal function execution */
   return CMD_EXEC_SUCCESS;
diff --git a/openfpga/src/base/openfpga_bitstream_command.cpp b/openfpga/src/base/openfpga_bitstream_command.cpp
index b64696d79..70149dd43 100644
--- a/openfpga/src/base/openfpga_bitstream_command.cpp
+++ b/openfpga/src/base/openfpga_bitstream_command.cpp
@@ -76,6 +76,11 @@ ShellCommandId add_openfpga_fabric_bitstream_command(openfpga::Shell<OpenfpgaCon
                                                      const std::vector<ShellCommandId>& dependent_cmds) {
   Command shell_cmd("build_fabric_bitstream");
 
+  /* Add an option '--file' in short '-f'*/
+  CommandOptionId opt_file = shell_cmd.add_option("file", false, "file path to output the fabric bitstream to plain text file");
+  shell_cmd.set_option_short_name(opt_file, "f");
+  shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING);
+
   /* Add an option '--verbose' */
   shell_cmd.add_option("verbose", false, "Enable verbose output");
 
diff --git a/openfpga/src/fpga_bitstream/bitstream_writer.cpp b/openfpga/src/fpga_bitstream/arch_bitstream_writer.cpp
similarity index 99%
rename from openfpga/src/fpga_bitstream/bitstream_writer.cpp
rename to openfpga/src/fpga_bitstream/arch_bitstream_writer.cpp
index 6f8539d3f..6a87a6768 100644
--- a/openfpga/src/fpga_bitstream/bitstream_writer.cpp
+++ b/openfpga/src/fpga_bitstream/arch_bitstream_writer.cpp
@@ -17,7 +17,7 @@
 #include "openfpga_naming.h"
 
 #include "bitstream_manager_utils.h"
-#include "bitstream_writer.h"
+#include "arch_bitstream_writer.h"
 
 /* begin namespace openfpga */
 namespace openfpga {
diff --git a/openfpga/src/fpga_bitstream/bitstream_writer.h b/openfpga/src/fpga_bitstream/arch_bitstream_writer.h
similarity index 91%
rename from openfpga/src/fpga_bitstream/bitstream_writer.h
rename to openfpga/src/fpga_bitstream/arch_bitstream_writer.h
index 338bfde35..a66880735 100644
--- a/openfpga/src/fpga_bitstream/bitstream_writer.h
+++ b/openfpga/src/fpga_bitstream/arch_bitstream_writer.h
@@ -1,5 +1,5 @@
-#ifndef BITSTREAM_WRITER_H
-#define BITSTREAM_WRITER_H
+#ifndef ARCH_BITSTREAM_WRITER_H
+#define ARCH_BITSTREAM_WRITER_H
 
 /********************************************************************
  * Include header files that are required by function declaration
diff --git a/openfpga/src/fpga_bitstream/fabric_bitstream_writer.cpp b/openfpga/src/fpga_bitstream/fabric_bitstream_writer.cpp
new file mode 100644
index 000000000..069a99345
--- /dev/null
+++ b/openfpga/src/fpga_bitstream/fabric_bitstream_writer.cpp
@@ -0,0 +1,61 @@
+/********************************************************************
+ * This file includes functions that output a fabric-dependent 
+ * bitstream database to files in different formats
+ *******************************************************************/
+#include <chrono>
+#include <ctime>
+#include <fstream>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+#include "vtr_time.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_digest.h"
+
+#include "openfpga_naming.h"
+
+#include "bitstream_manager_utils.h"
+#include "fabric_bitstream_writer.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Write the fabric bitstream to a plain text file 
+ * Notes: 
+ *   - This is the final bitstream which is loadable to the FPGA fabric
+ *     (Verilog netlists etc.)
+ *   - Do NOT include any comments or other characters that the 0|1 bitstream content
+ *     in this file
+ *******************************************************************/
+void write_fabric_bitstream_to_text_file(const BitstreamManager& bitstream_manager,
+                                         const std::vector<ConfigBitId>& fabric_bitstream,
+                                         const std::string& fname) {
+  /* Ensure that we have a valid file name */
+  if (true == fname.empty()) {
+    VTR_LOG_ERROR("Received empty file name to output bitstream!\n\tPlease specify a valid file name.\n");
+  }
+
+  std::string timer_message = std::string("Write ") + std::to_string(fabric_bitstream.size()) + std::string(" fabric bitstream into plain text file '") + fname + std::string("'");
+  vtr::ScopedStartFinishTimer timer(timer_message);
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(fname, std::fstream::out | std::fstream::trunc);
+
+  check_file_stream(fname.c_str(), fp);
+
+  /* Put down pure 0|1 bitstream here */
+  for (const ConfigBitId& fabric_bit : fabric_bitstream) {
+    fp << bitstream_manager.bit_value(fabric_bit);
+  }
+  /* Print an end to the file here */
+  fp << std::endl;
+
+  /* Close file handler */
+  fp.close();
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_bitstream/fabric_bitstream_writer.h b/openfpga/src/fpga_bitstream/fabric_bitstream_writer.h
new file mode 100644
index 000000000..6b2c0e771
--- /dev/null
+++ b/openfpga/src/fpga_bitstream/fabric_bitstream_writer.h
@@ -0,0 +1,24 @@
+#ifndef FABRIC_BITSTREAM_WRITER_H
+#define FABRIC_BITSTREAM_WRITER_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <string>
+#include <vector>
+#include "bitstream_manager.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void write_fabric_bitstream_to_text_file(const BitstreamManager& bitstream_manager,
+                                         const std::vector<ConfigBitId>& fabric_bitstream,
+                                         const std::string& fname);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/test_script/and_k6_frac.openfpga b/openfpga/test_script/and_k6_frac.openfpga
index e14811f49..20a75a661 100644
--- a/openfpga/test_script/and_k6_frac.openfpga
+++ b/openfpga/test_script/and_k6_frac.openfpga
@@ -34,7 +34,7 @@ repack #--verbose
 build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
 
 # Build fabric-dependent bitstream
-build_fabric_bitstream --verbose
+build_fabric_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/and.bitstream
 
 # Write the Verilog netlist for FPGA fabric
 #  - Enable the use of explicit port mapping in Verilog netlist

From 68b7991a465954d5b946c6805294103519d95b8a Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 21 Apr 2020 13:37:56 -0600
Subject: [PATCH 461/645] bug fixed for sdc on memory blocks

---
 openfpga/src/base/openfpga_naming.cpp         | 18 +++++++++--
 openfpga/src/base/openfpga_naming.h           |  3 ++
 openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp | 30 +++++++++++++++----
 3 files changed, 43 insertions(+), 8 deletions(-)

diff --git a/openfpga/src/base/openfpga_naming.cpp b/openfpga/src/base/openfpga_naming.cpp
index 99d59afdb..0796d4df1 100644
--- a/openfpga/src/base/openfpga_naming.cpp
+++ b/openfpga/src/base/openfpga_naming.cpp
@@ -1325,14 +1325,28 @@ bool is_core_grid_on_given_border_side(const vtr::Point<size_t>& device_size,
  * The name convention is 
  * <pb_type_name>_<port_name>
  ********************************************************************/
-std::string generate_pb_type_port_name(t_port* pb_type_port) {
+std::string generate_pb_type_port_name(t_pb_type* pb_type,
+                                       t_port* pb_type_port) {
   std::string port_name;
   
-  port_name = std::string(pb_type_port->parent_pb_type->name) + std::string("_") + std::string(pb_type_port->name);
+  port_name = std::string(pb_type->name) + std::string("_") + std::string(pb_type_port->name);
    
   return port_name;
 }
 
+/*********************************************************************
+ * Generate the port name of a Verilog module describing a pb_type
+ * The name convention is 
+ * <pb_type_name>_<port_name>
+ *  
+ * This is a wrapper on the generate_pb_type_port_name() function
+ * which can infer the parent_pb_type
+ ********************************************************************/
+std::string generate_pb_type_port_name(t_port* pb_type_port) {
+  return generate_pb_type_port_name(pb_type_port->parent_pb_type, pb_type_port);
+}
+
+
 /*********************************************************************
  * Generate the global I/O port name of a Verilog module
  * This is mainly used by I/O circuit models
diff --git a/openfpga/src/base/openfpga_naming.h b/openfpga/src/base/openfpga_naming.h
index 40d7f05e9..d3307fe3c 100644
--- a/openfpga/src/base/openfpga_naming.h
+++ b/openfpga/src/base/openfpga_naming.h
@@ -238,6 +238,9 @@ bool is_core_grid_on_given_border_side(const vtr::Point<size_t>& device_size,
                                        const vtr::Point<size_t>& grid_coordinate,
                                        const e_side& border_side);
 
+std::string generate_pb_type_port_name(t_pb_type* pb_type,
+                                       t_port* pb_type_port);
+
 std::string generate_pb_type_port_name(t_port* pb_type_port);
 
 std::string generate_fpga_global_io_port_name(const std::string& prefix, 
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp
index f47ed3068..5c206838d 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp
+++ b/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp
@@ -301,8 +301,26 @@ void print_pnr_sdc_constrain_primitive_pb_graph_node(const std::string& sdc_dir,
     exit(1);
   }
 
-  /* Get the pb_type */
+  t_pb_graph_node* logical_primitive_pb_graph_node = primitive_pb_graph_node;
+
+  /* Get the pb_type where the timing annotations are stored
+   * Note that some primitive pb_type has child modes
+   *   - Look-Up Table
+   *   - Memory
+   * For those pb_type, timing annotations are stored in the child pb_type
+   */
   t_pb_type* primitive_pb_type = primitive_pb_graph_node->pb_type;
+  if (LUT_CLASS == primitive_pb_type->class_type) {
+    primitive_pb_type = find_mode_child_pb_type(&(primitive_pb_type->modes[VPR_PB_TYPE_LUT_MODE]),
+                                                primitive_pb_type->name);
+    VTR_ASSERT(nullptr != primitive_pb_type);
+    logical_primitive_pb_graph_node = primitive_pb_graph_node->child_pb_graph_nodes[VPR_PB_TYPE_LUT_MODE][0];
+  } else if (MEMORY_CLASS == primitive_pb_type->class_type) {
+    VTR_ASSERT(1 == primitive_pb_type->num_modes);
+    VTR_ASSERT(1 == primitive_pb_type->modes[0].num_pb_type_children);
+    primitive_pb_type = &(primitive_pb_type->modes[0].pb_type_children[0]);
+    logical_primitive_pb_graph_node = primitive_pb_graph_node->child_pb_graph_nodes[0][0];
+  }
 
   /* We can directly return if there is no timing annotation defined */
   if (0 == primitive_pb_type->num_annotations) {
@@ -333,12 +351,12 @@ void print_pnr_sdc_constrain_primitive_pb_graph_node(const std::string& sdc_dir,
    * We walk through output pins here, build timing constraints by pair each output to input
    * Clock pins are not walked through because they will be handled by clock tree synthesis
    */
-  for (int iport = 0; iport < primitive_pb_graph_node->num_output_ports; ++iport) {
-    for (int ipin = 0; ipin < primitive_pb_graph_node->num_output_pins[iport]; ++ipin) {
-       t_pb_graph_pin* sink_pin = &(primitive_pb_graph_node->output_pins[iport][ipin]);
+  for (int iport = 0; iport < logical_primitive_pb_graph_node->num_output_ports; ++iport) {
+    for (int ipin = 0; ipin < logical_primitive_pb_graph_node->num_output_pins[iport]; ++ipin) {
+       t_pb_graph_pin* sink_pin = &(logical_primitive_pb_graph_node->output_pins[iport][ipin]);
 
        /* Port must exist in the module graph */
-       ModulePortId sink_module_port_id = module_manager.find_module_port(pb_module, generate_pb_type_port_name(sink_pin->port));
+       ModulePortId sink_module_port_id = module_manager.find_module_port(pb_module, generate_pb_type_port_name(physical_pb_type, sink_pin->port));
        VTR_ASSERT(true == module_manager.valid_module_port_id(pb_module, sink_module_port_id));
        BasicPort sink_port = module_manager.module_port(pb_module, sink_module_port_id);
        /* Set the correct pin number of the port */
@@ -350,7 +368,7 @@ void print_pnr_sdc_constrain_primitive_pb_graph_node(const std::string& sdc_dir,
          t_pb_graph_pin* src_pin = sink_pin->input_edges[iedge]->input_pins[0];
 
          /* Port must exist in the module graph */
-         ModulePortId src_module_port_id = module_manager.find_module_port(pb_module, generate_pb_type_port_name(src_pin->port));
+         ModulePortId src_module_port_id = module_manager.find_module_port(pb_module, generate_pb_type_port_name(physical_pb_type, src_pin->port));
          VTR_ASSERT(true == module_manager.valid_module_port_id(pb_module, src_module_port_id));
          BasicPort src_port = module_manager.module_port(pb_module, src_module_port_id);
          /* Set the correct pin number of the port */

From 2e3054f79a87f023aa1525626a94bf93c528f318 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 21 Apr 2020 14:34:51 -0600
Subject: [PATCH 462/645] bug fixed for SDC generation for LUTs

---
 openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp
index 5c206838d..4f748f9ad 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp
+++ b/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp
@@ -311,16 +311,19 @@ void print_pnr_sdc_constrain_primitive_pb_graph_node(const std::string& sdc_dir,
    */
   t_pb_type* primitive_pb_type = primitive_pb_graph_node->pb_type;
   if (LUT_CLASS == primitive_pb_type->class_type) {
-    primitive_pb_type = find_mode_child_pb_type(&(primitive_pb_type->modes[VPR_PB_TYPE_LUT_MODE]),
-                                                primitive_pb_type->name);
-    VTR_ASSERT(nullptr != primitive_pb_type);
+    VTR_ASSERT(VPR_PB_TYPE_LUT_MODE < primitive_pb_type->num_modes);
+    VTR_ASSERT(1 == primitive_pb_type->modes[VPR_PB_TYPE_LUT_MODE].num_pb_type_children);
+    primitive_pb_type = &(primitive_pb_type->modes[VPR_PB_TYPE_LUT_MODE].pb_type_children[0]);
     logical_primitive_pb_graph_node = primitive_pb_graph_node->child_pb_graph_nodes[VPR_PB_TYPE_LUT_MODE][0];
+    VTR_ASSERT(nullptr != logical_primitive_pb_graph_node);
   } else if (MEMORY_CLASS == primitive_pb_type->class_type) {
     VTR_ASSERT(1 == primitive_pb_type->num_modes);
     VTR_ASSERT(1 == primitive_pb_type->modes[0].num_pb_type_children);
     primitive_pb_type = &(primitive_pb_type->modes[0].pb_type_children[0]);
     logical_primitive_pb_graph_node = primitive_pb_graph_node->child_pb_graph_nodes[0][0];
   }
+  VTR_ASSERT(nullptr != primitive_pb_type);
+  VTR_ASSERT(nullptr != logical_primitive_pb_graph_node);
 
   /* We can directly return if there is no timing annotation defined */
   if (0 == primitive_pb_type->num_annotations) {

From 52adebacfb5072683e3efe0e58f83505e8f14674 Mon Sep 17 00:00:00 2001
From: Xifan Tang <tangxifan@gmail.com>
Date: Tue, 21 Apr 2020 14:40:53 -0600
Subject: [PATCH 463/645] update doc for file options in openfpga bitstream

---
 docs/source/openfpga_shell/openfpga_commands.rst | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/docs/source/openfpga_shell/openfpga_commands.rst b/docs/source/openfpga_shell/openfpga_commands.rst
index 3712cea0d..543b87397 100644
--- a/docs/source/openfpga_shell/openfpga_commands.rst
+++ b/docs/source/openfpga_shell/openfpga_commands.rst
@@ -124,7 +124,9 @@ FPGA-Bitstream
 
 .. option:: build_fabric_bitstream
 
-  Reorganize the bitstream database for a specific FPGA fabric
+  Build a sequence for every configuration bits in the bitstream database for a specific FPGA fabric
+
+  - ``--file`` or ``-f`` Output the fabric bitstream to an plain text file (only 0 or 1)
 
   - ``--verbose`` Show verbose log
   

From 9960625b01f3cee7696b47bba2de81f90aea3305 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 22 Apr 2020 11:10:59 -0600
Subject: [PATCH 464/645] add example spypad architecture

---
 ...egister_scan_chain_depop50_spypad_40nm.xml | 680 ++++++++++++++++++
 1 file changed, 680 insertions(+)
 create mode 100755 openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml

diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml
new file mode 100755
index 000000000..70bc907f8
--- /dev/null
+++ b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml
@@ -0,0 +1,680 @@
+<!-- Homogeneous FPGA Architecture with Carry Chain for VPR8
+
+  - The chip layout is organized with a 2x2 array of Configurable Logic Blocks (CLBs)
+    surrounded by a ring of I/Os
+  - [TODO] Delay numbers are extracted from a 12 nm technology
+  Author: Xifan Tang, Aurelien Alacchi and Ganesh Gore
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <model name="adder">
+      <input_ports>
+        <port name="a" combinational_sink_ports="sumout cout"/>
+        <port name="b" combinational_sink_ports="sumout cout"/>
+        <port name="cin" combinational_sink_ports="sumout cout"/>
+      </input_ports>
+      <output_ports>
+        <port name="cout"/>
+        <port name="sumout"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="frac_lut6">
+      <input_ports>
+        <port name="in"/>
+      </input_ports>
+      <output_ports>
+        <port name="lut4_out"/>
+        <port name="lut5_out"/>
+        <port name="lut6_out"/>
+      </output_ports>
+    </model>
+    <model name="shift">
+      <input_ports>
+        <port name="D" clock="clk"/>
+        <port name="clk" is_clock="1"/>
+      </input_ports>
+      <output_ports>
+        <port name="Q" clock="clk"/>
+      </output_ports>
+    </model>
+    <model name="scff">
+      <input_ports>
+        <port name="D" clock="clk"/>
+        <port name="D_chain" clock="clk"/>
+        <port name="clk" is_clock="1"/>
+      </input_ports>
+      <output_ports>
+        <port name="Q" clock="clk"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <!-- Each I/O tile includes a GPIO --> 
+    <!-- IOs go on the periphery of the FPGA, for consistency, 
+         make it physically equivalent on all sides so that only one definition of I/Os is needed.
+         If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+      -->
+    <tile name="io" capacity="1" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <!-- Each input of the tile can be driven by 15% of routing tracks
+           Each output of the tile can drive 10% of routing tracks
+        -->
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad</loc>
+        <loc side="top">io.outpad io.inpad</loc>
+        <loc side="right">io.outpad io.inpad</loc>
+        <loc side="bottom">io.outpad io.inpad</loc>
+      </pinlocations>
+    </tile>
+    <!-- Each CLB tile includes a Configurable Logic Block (CLB)
+         Each input of the tile can be driven by 15% of routing tracks
+         Each output of the tile can drive 10% of routing tracks
+      -->
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I0" num_pins="10" equivalent="full"/>
+      <input name="I1" num_pins="10" equivalent="full"/>
+      <input name="I2" num_pins="10" equivalent="full"/>
+      <input name="I3" num_pins="10" equivalent="full"/>
+      <input name="sc_in" num_pins="1"/>
+      <input name="cin" num_pins="1"/>
+      <input name="cin_trick" num_pins="1"/>
+      <input name="regin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="sc_out" num_pins="1"/>
+      <output name="cout" num_pins="1"/>
+      <output name="cout_copy" num_pins="1"/>
+      <output name="regout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Each input of the tile can be driven by 15% of routing tracks
+           Each output of the tile can drive 10% of routing tracks
+           There are four pins (cin, cout, sc_in, sc_out) has not connection 
+           to routing tracks. There are directed wired from/to adjacent CLBs
+        -->
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="sc_in" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="sc_out" fc_type="frac" fc_val="0"/>
+      </fc>
+      <!-- Highly recommand to customize pin location when direct connection is used!!! -->
+      <!-- To ensure best tileable routing architecture (minimize the number of unique SBs
+           We keep all the pins that touch routing architecture on the right and bottom sides of the tile
+           Top side pins are mainly for direct connections
+        -->
+      <pinlocations pattern="custom">
+        <loc side="left"></loc>
+        <loc side="top">clb.sc_in clb.cin clb.cin_trick clb.regin clb.clk</loc>
+        <loc side="right">clb.I0[9:0] clb.I1[9:0] clb.O[9:0]</loc>
+        <loc side="bottom">clb.cout clb.cout_copy clb.sc_out clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10]</loc>
+      </pinlocations>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <!-- Apply tileable routing architecture.
+       This is strongly recommended if you want to PnR large FPGA fabric
+    -->
+  <layout tileable="true">
+    <!--auto_layout aspect_ratio="1.0"-->
+    <!-- Apply a fixed layout of 2x2 core array.
+         VPR8 considers the I/O ring in the array size
+         Therefore the height and width are both 4
+      -->
+    <fixed_layout name="2x2" width="4" height="4">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </fixed_layout>
+    <!-- /auto_layout -->
+  </layout>
+  <device>
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+         area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+      -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <!-- Use Wilton-style connecting pattern in switch block 
+         Each routing track has access to only three other routing tracks
+         (one per each side of the switch block except the side where the routing track locates)
+      -->
+    <switch_block type="wilton" fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
+    <!-- Uni-directional routing architecture using only length-4 wires in routing channels -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <directlist>
+    <!-- Hard adder chain inside CLB is directly connected between adjacent CLBs -->
+    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
+    <!-- Scan chain inside CLB is directly connected between adjacent CLBs -->
+    <direct name="scff_chain" from_pin="clb.sc_out" to_pin="clb.sc_in" x_offset="0" y_offset="-1" z_offset="0"/>
+  </directlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+
+      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+           If you need to register the I/O, define clocks in the circuit models
+           These clocks can be handled in back-end
+       -->
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" packable="false">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+
+      <!-- IOs can operate as either inputs or outputs.
+       Delays below come from Ian Kuon. They are small, so they should be interpreted as
+       the delays to and from registers in the I/O (and generally I/Os are registered 
+       today and that is when you timing analyze them.
+       -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define multi-mode Configurable Logic Block (CLB) begin -->
+    <!-- Technical highlight:
+         K6_frac_N10_I40_chain_shiftreg_depop50
+         - K6_frac: Each Logic Element (LE) contains a fracturable 6 LUT,
+                    which can operate as one 6-LUT or two 5-LUTs or four 4-LUTs 
+                    In addition to 6-LUT, each LE also includes two Flip-Flops
+         - N10: every CLB consists of 10 LEs and a local routing architecture
+         - I40: every CLB has 40 inputs
+         - chain: a hard adder chain across all the LEs in a CLB
+                  The inputs of adder are driven by 4-LUTs.
+                  The sumout of adder can optional drive an LE output or a Flip-Flop
+                  The carry-out of adder will drive the carry-in of the next adder in the chain
+         - shiftreg: Flip-flops inside CLB can be configured as shift registers.
+                     The organization is similar the hard adder chain except it is programmable
+         - depop50: every local routing multiplexer accesses to 50% of the CLB inputs
+      -->
+    <pb_type name="clb">
+      <input name="I0" num_pins="10" equivalent="full"/>
+      <input name="I1" num_pins="10" equivalent="full"/>
+      <input name="I2" num_pins="10" equivalent="full"/>
+      <input name="I3" num_pins="10" equivalent="full"/>
+      <input name="sc_in" num_pins="1"/>
+      <input name="cin" num_pins="1"/>
+      <input name="cin_trick" num_pins="1"/>
+      <input name="regin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="sc_out" num_pins="1"/>
+      <output name="cout" num_pins="1"/>
+      <output name="cout_copy" num_pins="1"/>
+      <output name="regout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+
+      <!-- Describe fracturable logic element -->
+      <pb_type name="fle" num_pb="10">
+        <input name="in" num_pins="6"/>
+        <input name="cin" num_pins="1"/>
+        <input name="sc_in" num_pins="1"/>
+        <input name="regin" num_pins="1"/>
+        <output name="out" num_pins="2"/>
+        <output name="cout" num_pins="1"/>
+        <output name="sc_out" num_pins="1"/>
+        <output name="regout" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+
+        <!-- Describe physical mode begins -->
+        <mode name="physical" packable="false">
+          <pb_type name="frac_logic" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <input name="cin" num_pins="1"/>
+            <input name="regin" num_pins="1"/>
+            <input name="regchain" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
+              <input name="in" num_pins="6"/>
+              <output name="lut4_out" num_pins="4"/>
+              <output name="lut5_out" num_pins="2"/>
+              <output name="lut6_out" num_pins="1"/>
+            </pb_type>
+            <pb_type name="adder_phy" blif_model=".subckt adder" num_pb="2">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder_phy.a" out_port="adder_phy.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder_phy.b" out_port="adder_phy.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder_phy.cin" out_port="adder_phy.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder_phy.a" out_port="adder_phy.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder_phy.b" out_port="adder_phy.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder_phy.cin" out_port="adder_phy.cout"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct_fraclut_in" input="frac_logic.in[5:0]" output="frac_lut6.in[5:0]"/>
+              <direct name="direct_cin" input="frac_logic.cin" output="adder_phy[0].cin"/>
+              <direct name="direct_carry" input="adder_phy[0].cout" output="adder_phy[1].cin"/>
+              <direct name="direct_cout" input="adder_phy[1].cout" output="frac_logic.cout"/>
+              <direct name="direct_lut4carry0" input="frac_lut6.lut4_out[0]" output="adder_phy[0].a"/>
+              <direct name="direct_lut4carry1" input="frac_lut6.lut4_out[1]" output="adder_phy[0].b"/>
+              <direct name="direct_lut4carry2" input="frac_lut6.lut4_out[2]" output="adder_phy[1].a"/>
+              <direct name="direct_lut4carry3" input="frac_lut6.lut4_out[3]" output="adder_phy[1].b"/>
+              <mux name="mux1" input="adder_phy[0].sumout frac_lut6.lut5_out[0] frac_logic.regin" output="frac_logic.out[0]">
+              </mux>
+              <mux name="mux2" input="adder_phy[1].sumout frac_lut6.lut5_out[1] frac_lut6.lut6_out[0] frac_logic.regchain[0]" output="frac_logic.out[1]">
+              </mux>
+            </interconnect>
+          </pb_type>
+          <pb_type name="ff_phy" blif_model=".subckt scff" num_pb="2">
+            <input name="D" num_pins="1"/>
+            <input name="D_chain" num_pins="1"/>
+            <output name="Q" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <T_setup value="66e-12" port="ff_phy.D" clock="clk"/>
+            <T_setup value="66e-12" port="ff_phy.D_chain" clock="clk"/>
+            <T_clock_to_Q max="124e-12" port="ff_phy.Q" clock="clk"/>
+          </pb_type>
+          <interconnect>
+            <complete name="direct_clk" input="fle.clk" output="ff_phy[1:0].clk"/>
+            <direct name="direct_in" input="fle.in[5:0]" output="frac_logic.in[5:0]"/>
+            <direct name="direct_regin" input="fle.regin" output="frac_logic.regin"/>
+            <direct name="direct_regchain" input="ff_phy[0].Q" output="frac_logic.regchain"/>
+            <direct name="direct_regout" input="ff_phy[1].Q" output="fle.regout"/>
+            <direct name="direct_cin" input="fle.cin" output="frac_logic.cin"/>
+            <direct name="direct_cout" input="frac_logic.cout" output="fle.cout"/>
+            <direct name="direct_frac_out1" input="frac_logic.out[0]" output="ff_phy[0].D"/>
+            <direct name="direct_frac_out2" input="frac_logic.out[1]" output="ff_phy[1].D"/>
+            <direct name="direct_fle_scin" input="fle.sc_in" output="ff_phy[0].D_chain"/>
+            <direct name="direct_fle_sc_chain" input="ff_phy[0].Q" output="ff_phy[1].D_chain"/>
+            <direct name="direct_fle_scout" input="ff_phy[1].Q" output="fle.sc_out"/>
+            <mux name="mux1" input="ff_phy[0].Q frac_logic.out[0]" output="fle.out[0]">
+            </mux>
+            <mux name="mux2" input="ff_phy[1].Q frac_logic.out[1]" output="fle.out[1]">
+            </mux>
+          </interconnect>
+        </mode>
+        <!-- Define physical mode begins -->
+        <!-- Define n2_lut5 mode begins -->
+        <mode name="n2_lut5" packable="true">
+          <pb_type name="lut5inter" num_pb="1">
+            <input name="in" num_pins="5"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="ble5" num_pb="2">
+              <input name="in" num_pins="5"/>
+              <input name="cin" num_pins="1"/>
+              <output name="out" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <clock name="clk" num_pins="1"/>
+              <mode name="blut5">
+                <pb_type name="flut5" num_pb="1">
+                  <input name="in" num_pins="5"/>
+                  <output name="out" num_pins="1"/>
+                  <clock name="clk" num_pins="1"/>
+                  <!-- Regular LUT mode -->
+                  <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
+                    <input name="in" num_pins="5" port_class="lut_in"/>
+                    <output name="out" num_pins="1" port_class="lut_out"/>
+                    <!-- LUT timing using delay matrix -->
+                    <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
+                        202e-12
+                        202e-12
+                        202e-12
+                        202e-12
+                        202e-12
+                    </delay_matrix>
+                  </pb_type>
+
+                  <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+                    <input name="D" num_pins="1" port_class="D"/>
+                    <output name="Q" num_pins="1" port_class="Q"/>
+                    <clock name="clk" num_pins="1" port_class="clock"/>
+                    <T_setup value="66e-12" port="ff.D" clock="clk"/>
+                    <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+                  </pb_type>
+                  <interconnect>
+                    <direct name="direct1" input="flut5.in" output="lut5.in"/>
+                    <direct name="direct2" input="lut5.out" output="ff.D">
+                      <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
+                    </direct>
+                    <direct name="direct3" input="flut5.clk" output="ff.clk"/>
+                    <mux name="mux1" input="ff.Q lut5.out" output="flut5.out">
+                      <delay_constant max="25e-12" in_port="lut5.out" out_port="flut5.out" />
+                      <delay_constant max="45e-12" in_port="ff.Q" out_port="flut5.out" />
+                    </mux>
+                  </interconnect>
+                </pb_type>
+                <interconnect>
+                  <direct name="direct1" input="ble5.in" output="flut5.in"/>
+                  <direct name="direct2" input="ble5.clk" output="flut5.clk"/>
+                  <direct name="direct3" input="flut5.out" output="ble5.out"/>
+                </interconnect>
+              </mode>
+              <mode name="arithmetic">
+                <pb_type name="arithmetic" num_pb="1">
+                  <input name="in" num_pins="4"/>
+                  <input name="cin" num_pins="1"/>
+                  <output name="out" num_pins="1"/>
+                  <output name="cout" num_pins="1"/>
+                  <clock name="clk" num_pins="1"/>
+                  <!-- Special dual-LUT mode that drives adder only -->
+                  <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
+                    <input name="in" num_pins="4" port_class="lut_in"/>
+                    <output name="out" num_pins="1" port_class="lut_out"/>
+                    <!-- LUT timing using delay matrix -->
+                    <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                        180e-12
+                        180e-12
+                        180e-12
+                        180e-12
+                    </delay_matrix>
+                  </pb_type>
+                  <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
+                    <input name="a" num_pins="1"/>
+                    <input name="b" num_pins="1"/>
+                    <input name="cin" num_pins="1"/>
+                    <output name="cout" num_pins="1"/>
+                    <output name="sumout" num_pins="1"/>
+                    <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+                    <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+                    <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+                    <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+                    <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+                    <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.cout"/>
+                  </pb_type>
+                  <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+                    <input name="D" num_pins="1" port_class="D"/>
+                    <output name="Q" num_pins="1" port_class="Q"/>
+                    <clock name="clk" num_pins="1" port_class="clock"/>
+                    <T_setup value="66e-12" port="ff.D" clock="clk"/>
+                    <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+                  </pb_type>
+                  <interconnect>
+                    <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
+                    <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
+                    <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
+                    <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
+                    </direct>
+                    <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
+                    </direct>
+                    <direct name="add_to_ff" input="adder.sumout" output="ff.D">
+                      <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
+                    </direct>
+                    <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
+                      <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
+                    </direct>
+                    <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
+                      <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
+                    </direct>
+                    <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
+                      <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
+                      <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out" />
+                    </mux>
+                  </interconnect>
+                </pb_type>
+
+                <interconnect>
+                  <direct name="direct1" input="ble5.in[3:0]" output="arithmetic.in"/>
+                  <direct name="carry_in" input="ble5.cin" output="arithmetic.cin">
+                    <!--pack_pattern name="chain" in_port="ble5.cin" out_port="arithmetic.cin"/-->
+                  </direct>
+                  <direct name="carry_out" input="arithmetic.cout" output="ble5.cout">
+                    <!--pack_pattern name="chain" in_port="arithmetic.cout" out_port="ble5.cout"/-->
+                  </direct>
+                  <direct name="direct2" input="ble5.clk" output="arithmetic.clk"/>
+                  <direct name="direct3" input="arithmetic.out" output="ble5.out"/>
+                </interconnect>
+              </mode>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="lut5inter.in" output="ble5[0:0].in"/>
+              <direct name="direct2" input="lut5inter.in" output="ble5[1:1].in"/>
+              <direct name="direct3" input="ble5[1:0].out" output="lut5inter.out"/>
+              <direct name="carry_in" input="lut5inter.cin" output="ble5[0:0].cin">
+                <!--pack_pattern name="chain" in_port="lut5inter.cin" out_port="ble5[0:0].cin"/-->
+              </direct>
+              <direct name="carry_out" input="ble5[1:1].cout" output="lut5inter.cout">
+                <!--pack_pattern name="chain" in_port="ble5[1:1].cout" out_port="lut5inter.cout"/-->
+              </direct>
+              <direct name="carry_link" input="ble5[0:0].cout" output="ble5[1:1].cin">
+                <!--pack_pattern name="chain" in_port="ble5[0:0].cout" out_port="ble5[1:1].cout"/-->
+              </direct>
+              <complete name="complete1" input="lut5inter.clk" output="ble5[1:0].clk"/>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[4:0]" output="lut5inter.in"/>
+            <direct name="direct2" input="lut5inter.out" output="fle.out"/>
+            <direct name="direct3" input="fle.clk" output="lut5inter.clk"/>
+            <direct name="carry_in" input="fle.cin" output="lut5inter.cin">
+              <!--pack_pattern name="chain" in_port="fle.cin" out_port="lut5inter.cin"/-->
+            </direct>
+            <direct name="carry_out" input="lut5inter.cout" output="fle.cout">
+              <!--pack_pattern name="chain" in_port="lut5inter.cout" out_port="fle.cout"/-->
+            </direct>
+          </interconnect>
+        </mode>
+        <!-- Define n2_lut5 mode ends -->
+        <mode name="n1_lut6">
+          <pb_type name="ble6" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="6" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                  229e-12
+                  229e-12
+                  229e-12
+                  229e-12
+                  229e-12
+                  229e-12
+              </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+
+            <interconnect>
+              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+              <direct name="direct2" input="lut6.out" output="ff.D">
+                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out" />
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out" />
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="ble6.in"/>
+            <direct name="direct2" input="ble6.out" output="fle.out[1:1]"/>
+            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Define n1_lut6 mode ends -->
+        <!-- Define shift register mode begins -->
+        <mode name="shift_register">
+          <pb_type name="ble_shift" num_pb="1">
+            <input name="in" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="regout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="ff" blif_model=".subckt shift" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble_shift.in" output="ff[0].D"/>
+              <direct name="direct2" input="ff[0].Q" output="ff[1].D">
+                <!--pack_pattern name="ble_shift" in_port="ff[0].Q" out_port="ff[1].D"/-->
+              </direct>
+              <direct name="out1" input="ff[0].Q" output="ble_shift.out[0]"/>
+              <direct name="out2" input="ff[1].Q" output="ble_shift.out[1]"/>
+              <direct name="direct_regout" input="ff[1].Q" output="ble_shift.regout"/>
+              <complete name="direct3" input="ble_shift.clk" output="ff[1:0].clk"/>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.regin" output="ble_shift.in"/>
+            <direct name="direct2" input="ble_shift.out" output="fle.out"/>
+            <direct name="direct3" input="fle.clk" output="ble_shift.clk"/>
+            <direct name="direct4" input="ble_shift.regout" output="fle.regout"/>
+          </interconnect>
+        </mode>
+       <!-- Define shift_register mode end -->
+      </pb_type>
+      <interconnect>
+        <complete name="crossbar0" input="clb.I2 clb.I3 fle[9:0].out" output="fle[9:0].in[0]">
+          <delay_constant max="190e-12" in_port="clb.I2 clb.I3" out_port="fle[9:0].in[0]" />
+          <delay_constant max="190e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[0]" />
+        </complete>
+        <complete name="crossbar1" input="clb.I1 clb.I2 fle[9:0].out" output="fle[9:0].in[1]">
+          <delay_constant max="190e-12" in_port="clb.I1 clb.I2" out_port="fle[9:0].in[1]" />
+          <delay_constant max="190e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[1]" />
+        </complete>
+        <complete name="crossbar2" input="clb.I0 clb.I1 fle[9:0].out" output="fle[9:0].in[2]">
+          <delay_constant max="190e-12" in_port="clb.I0 clb.I1" out_port="fle[9:0].in[2]" />
+          <delay_constant max="190e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[2]" />
+        </complete>
+        <complete name="crossbar3" input="clb.I1 clb.I3 fle[9:0].out" output="fle[9:0].in[3]">
+          <delay_constant max="190e-12" in_port="clb.I1 clb.I3" out_port="fle[9:0].in[3]" />
+          <delay_constant max="190e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[3]" />
+        </complete>
+        <complete name="crossbar4" input="clb.I0 clb.I2 fle[9:0].out" output="fle[9:0].in[4]">
+          <delay_constant max="190e-12" in_port="clb.I0 clb.I2" out_port="fle[9:0].in[4]" />
+          <delay_constant max="190e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[4]" />
+        </complete>
+        <complete name="crossbar5" input="clb.I0 clb.I3 fle[9:0].out" output="fle[9:0].in[5]">
+        </complete>
+        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+        </complete>
+        <complete name="carry_in" input="clb.cin clb.cin_trick fle[9:0].out" output="fle[0:0].cin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <!--delay_constant max="0.15e-9" in_port="clb.cin clb.cin_trick" out_port="fle[0:0].cin"/-->
+          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
+          <!--pack_pattern name="chain" in_port="clb.cin_trick" out_port="fle[0:0].cin"/-->
+        </complete>
+
+        <!--direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
+          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
+        </direct-->
+        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
+        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
+        <direct name="cout_copy" input="fle[9:9].cout" output="clb.cout_copy"/>
+
+        <!-- Shift register links -->
+        <direct name="regin" input="clb.regin" output="fle[0:0].regin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.15e-9" in_port="clb.regin" out_port="fle[0:0].regin"/>
+          <pack_pattern name="chain" in_port="clb.regin" out_port="fle[0:0].regin"/>
+        </direct>
+        <direct name="regout" input="fle[9:9].regout" output="clb.regout">
+          <pack_pattern name="chain" in_port="fle[9:9].regout" out_port="clb.regout"/>
+        </direct>
+        <direct name="reg_link" input="fle[8:0].regout" output="fle[9:1].regin">
+          <pack_pattern name="chain" in_port="fle[8:0].regout" out_port="fle[9:1].regin"/>
+        </direct>
+        <!-- Carry chain links -->
+        <direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
+          <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
+        </direct>
+        <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
+          <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
+        </direct>
+        <!-- Scan chain links -->
+        <direct name="sc_in" input="clb.sc_in" output="fle[0:0].sc_in">
+        </direct>
+        <direct name="sc_out" input="fle[9:9].sc_out" output="clb.sc_out">
+        </direct>
+        <direct name="sc_link" input="fle[8:0].sc_out" output="fle[9:1].sc_in">
+        </direct>
+      </interconnect>
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+  </complexblocklist>
+</architecture>

From 9fb8971281064c24c810d9c533beea5fd8bf3634 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 22 Apr 2020 11:12:28 -0600
Subject: [PATCH 465/645] add FPGA arch with spypads to portofilo

---
 ...egister_scan_chain_depop50_spypad_40nm.xml | 680 ++++++++++++++++++
 1 file changed, 680 insertions(+)
 create mode 100755 openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml

diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml
new file mode 100755
index 000000000..70bc907f8
--- /dev/null
+++ b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml
@@ -0,0 +1,680 @@
+<!-- Homogeneous FPGA Architecture with Carry Chain for VPR8
+
+  - The chip layout is organized with a 2x2 array of Configurable Logic Blocks (CLBs)
+    surrounded by a ring of I/Os
+  - [TODO] Delay numbers are extracted from a 12 nm technology
+  Author: Xifan Tang, Aurelien Alacchi and Ganesh Gore
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <model name="adder">
+      <input_ports>
+        <port name="a" combinational_sink_ports="sumout cout"/>
+        <port name="b" combinational_sink_ports="sumout cout"/>
+        <port name="cin" combinational_sink_ports="sumout cout"/>
+      </input_ports>
+      <output_ports>
+        <port name="cout"/>
+        <port name="sumout"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="frac_lut6">
+      <input_ports>
+        <port name="in"/>
+      </input_ports>
+      <output_ports>
+        <port name="lut4_out"/>
+        <port name="lut5_out"/>
+        <port name="lut6_out"/>
+      </output_ports>
+    </model>
+    <model name="shift">
+      <input_ports>
+        <port name="D" clock="clk"/>
+        <port name="clk" is_clock="1"/>
+      </input_ports>
+      <output_ports>
+        <port name="Q" clock="clk"/>
+      </output_ports>
+    </model>
+    <model name="scff">
+      <input_ports>
+        <port name="D" clock="clk"/>
+        <port name="D_chain" clock="clk"/>
+        <port name="clk" is_clock="1"/>
+      </input_ports>
+      <output_ports>
+        <port name="Q" clock="clk"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <!-- Each I/O tile includes a GPIO --> 
+    <!-- IOs go on the periphery of the FPGA, for consistency, 
+         make it physically equivalent on all sides so that only one definition of I/Os is needed.
+         If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+      -->
+    <tile name="io" capacity="1" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <!-- Each input of the tile can be driven by 15% of routing tracks
+           Each output of the tile can drive 10% of routing tracks
+        -->
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad</loc>
+        <loc side="top">io.outpad io.inpad</loc>
+        <loc side="right">io.outpad io.inpad</loc>
+        <loc side="bottom">io.outpad io.inpad</loc>
+      </pinlocations>
+    </tile>
+    <!-- Each CLB tile includes a Configurable Logic Block (CLB)
+         Each input of the tile can be driven by 15% of routing tracks
+         Each output of the tile can drive 10% of routing tracks
+      -->
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I0" num_pins="10" equivalent="full"/>
+      <input name="I1" num_pins="10" equivalent="full"/>
+      <input name="I2" num_pins="10" equivalent="full"/>
+      <input name="I3" num_pins="10" equivalent="full"/>
+      <input name="sc_in" num_pins="1"/>
+      <input name="cin" num_pins="1"/>
+      <input name="cin_trick" num_pins="1"/>
+      <input name="regin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="sc_out" num_pins="1"/>
+      <output name="cout" num_pins="1"/>
+      <output name="cout_copy" num_pins="1"/>
+      <output name="regout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Each input of the tile can be driven by 15% of routing tracks
+           Each output of the tile can drive 10% of routing tracks
+           There are four pins (cin, cout, sc_in, sc_out) has not connection 
+           to routing tracks. There are directed wired from/to adjacent CLBs
+        -->
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="sc_in" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="sc_out" fc_type="frac" fc_val="0"/>
+      </fc>
+      <!-- Highly recommand to customize pin location when direct connection is used!!! -->
+      <!-- To ensure best tileable routing architecture (minimize the number of unique SBs
+           We keep all the pins that touch routing architecture on the right and bottom sides of the tile
+           Top side pins are mainly for direct connections
+        -->
+      <pinlocations pattern="custom">
+        <loc side="left"></loc>
+        <loc side="top">clb.sc_in clb.cin clb.cin_trick clb.regin clb.clk</loc>
+        <loc side="right">clb.I0[9:0] clb.I1[9:0] clb.O[9:0]</loc>
+        <loc side="bottom">clb.cout clb.cout_copy clb.sc_out clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10]</loc>
+      </pinlocations>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <!-- Apply tileable routing architecture.
+       This is strongly recommended if you want to PnR large FPGA fabric
+    -->
+  <layout tileable="true">
+    <!--auto_layout aspect_ratio="1.0"-->
+    <!-- Apply a fixed layout of 2x2 core array.
+         VPR8 considers the I/O ring in the array size
+         Therefore the height and width are both 4
+      -->
+    <fixed_layout name="2x2" width="4" height="4">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </fixed_layout>
+    <!-- /auto_layout -->
+  </layout>
+  <device>
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+         area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+      -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <!-- Use Wilton-style connecting pattern in switch block 
+         Each routing track has access to only three other routing tracks
+         (one per each side of the switch block except the side where the routing track locates)
+      -->
+    <switch_block type="wilton" fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
+    <!-- Uni-directional routing architecture using only length-4 wires in routing channels -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <directlist>
+    <!-- Hard adder chain inside CLB is directly connected between adjacent CLBs -->
+    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
+    <!-- Scan chain inside CLB is directly connected between adjacent CLBs -->
+    <direct name="scff_chain" from_pin="clb.sc_out" to_pin="clb.sc_in" x_offset="0" y_offset="-1" z_offset="0"/>
+  </directlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+
+      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+           If you need to register the I/O, define clocks in the circuit models
+           These clocks can be handled in back-end
+       -->
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" packable="false">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+
+      <!-- IOs can operate as either inputs or outputs.
+       Delays below come from Ian Kuon. They are small, so they should be interpreted as
+       the delays to and from registers in the I/O (and generally I/Os are registered 
+       today and that is when you timing analyze them.
+       -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define multi-mode Configurable Logic Block (CLB) begin -->
+    <!-- Technical highlight:
+         K6_frac_N10_I40_chain_shiftreg_depop50
+         - K6_frac: Each Logic Element (LE) contains a fracturable 6 LUT,
+                    which can operate as one 6-LUT or two 5-LUTs or four 4-LUTs 
+                    In addition to 6-LUT, each LE also includes two Flip-Flops
+         - N10: every CLB consists of 10 LEs and a local routing architecture
+         - I40: every CLB has 40 inputs
+         - chain: a hard adder chain across all the LEs in a CLB
+                  The inputs of adder are driven by 4-LUTs.
+                  The sumout of adder can optional drive an LE output or a Flip-Flop
+                  The carry-out of adder will drive the carry-in of the next adder in the chain
+         - shiftreg: Flip-flops inside CLB can be configured as shift registers.
+                     The organization is similar the hard adder chain except it is programmable
+         - depop50: every local routing multiplexer accesses to 50% of the CLB inputs
+      -->
+    <pb_type name="clb">
+      <input name="I0" num_pins="10" equivalent="full"/>
+      <input name="I1" num_pins="10" equivalent="full"/>
+      <input name="I2" num_pins="10" equivalent="full"/>
+      <input name="I3" num_pins="10" equivalent="full"/>
+      <input name="sc_in" num_pins="1"/>
+      <input name="cin" num_pins="1"/>
+      <input name="cin_trick" num_pins="1"/>
+      <input name="regin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="sc_out" num_pins="1"/>
+      <output name="cout" num_pins="1"/>
+      <output name="cout_copy" num_pins="1"/>
+      <output name="regout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+
+      <!-- Describe fracturable logic element -->
+      <pb_type name="fle" num_pb="10">
+        <input name="in" num_pins="6"/>
+        <input name="cin" num_pins="1"/>
+        <input name="sc_in" num_pins="1"/>
+        <input name="regin" num_pins="1"/>
+        <output name="out" num_pins="2"/>
+        <output name="cout" num_pins="1"/>
+        <output name="sc_out" num_pins="1"/>
+        <output name="regout" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+
+        <!-- Describe physical mode begins -->
+        <mode name="physical" packable="false">
+          <pb_type name="frac_logic" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <input name="cin" num_pins="1"/>
+            <input name="regin" num_pins="1"/>
+            <input name="regchain" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
+              <input name="in" num_pins="6"/>
+              <output name="lut4_out" num_pins="4"/>
+              <output name="lut5_out" num_pins="2"/>
+              <output name="lut6_out" num_pins="1"/>
+            </pb_type>
+            <pb_type name="adder_phy" blif_model=".subckt adder" num_pb="2">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder_phy.a" out_port="adder_phy.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder_phy.b" out_port="adder_phy.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder_phy.cin" out_port="adder_phy.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder_phy.a" out_port="adder_phy.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder_phy.b" out_port="adder_phy.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder_phy.cin" out_port="adder_phy.cout"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct_fraclut_in" input="frac_logic.in[5:0]" output="frac_lut6.in[5:0]"/>
+              <direct name="direct_cin" input="frac_logic.cin" output="adder_phy[0].cin"/>
+              <direct name="direct_carry" input="adder_phy[0].cout" output="adder_phy[1].cin"/>
+              <direct name="direct_cout" input="adder_phy[1].cout" output="frac_logic.cout"/>
+              <direct name="direct_lut4carry0" input="frac_lut6.lut4_out[0]" output="adder_phy[0].a"/>
+              <direct name="direct_lut4carry1" input="frac_lut6.lut4_out[1]" output="adder_phy[0].b"/>
+              <direct name="direct_lut4carry2" input="frac_lut6.lut4_out[2]" output="adder_phy[1].a"/>
+              <direct name="direct_lut4carry3" input="frac_lut6.lut4_out[3]" output="adder_phy[1].b"/>
+              <mux name="mux1" input="adder_phy[0].sumout frac_lut6.lut5_out[0] frac_logic.regin" output="frac_logic.out[0]">
+              </mux>
+              <mux name="mux2" input="adder_phy[1].sumout frac_lut6.lut5_out[1] frac_lut6.lut6_out[0] frac_logic.regchain[0]" output="frac_logic.out[1]">
+              </mux>
+            </interconnect>
+          </pb_type>
+          <pb_type name="ff_phy" blif_model=".subckt scff" num_pb="2">
+            <input name="D" num_pins="1"/>
+            <input name="D_chain" num_pins="1"/>
+            <output name="Q" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <T_setup value="66e-12" port="ff_phy.D" clock="clk"/>
+            <T_setup value="66e-12" port="ff_phy.D_chain" clock="clk"/>
+            <T_clock_to_Q max="124e-12" port="ff_phy.Q" clock="clk"/>
+          </pb_type>
+          <interconnect>
+            <complete name="direct_clk" input="fle.clk" output="ff_phy[1:0].clk"/>
+            <direct name="direct_in" input="fle.in[5:0]" output="frac_logic.in[5:0]"/>
+            <direct name="direct_regin" input="fle.regin" output="frac_logic.regin"/>
+            <direct name="direct_regchain" input="ff_phy[0].Q" output="frac_logic.regchain"/>
+            <direct name="direct_regout" input="ff_phy[1].Q" output="fle.regout"/>
+            <direct name="direct_cin" input="fle.cin" output="frac_logic.cin"/>
+            <direct name="direct_cout" input="frac_logic.cout" output="fle.cout"/>
+            <direct name="direct_frac_out1" input="frac_logic.out[0]" output="ff_phy[0].D"/>
+            <direct name="direct_frac_out2" input="frac_logic.out[1]" output="ff_phy[1].D"/>
+            <direct name="direct_fle_scin" input="fle.sc_in" output="ff_phy[0].D_chain"/>
+            <direct name="direct_fle_sc_chain" input="ff_phy[0].Q" output="ff_phy[1].D_chain"/>
+            <direct name="direct_fle_scout" input="ff_phy[1].Q" output="fle.sc_out"/>
+            <mux name="mux1" input="ff_phy[0].Q frac_logic.out[0]" output="fle.out[0]">
+            </mux>
+            <mux name="mux2" input="ff_phy[1].Q frac_logic.out[1]" output="fle.out[1]">
+            </mux>
+          </interconnect>
+        </mode>
+        <!-- Define physical mode begins -->
+        <!-- Define n2_lut5 mode begins -->
+        <mode name="n2_lut5" packable="true">
+          <pb_type name="lut5inter" num_pb="1">
+            <input name="in" num_pins="5"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="ble5" num_pb="2">
+              <input name="in" num_pins="5"/>
+              <input name="cin" num_pins="1"/>
+              <output name="out" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <clock name="clk" num_pins="1"/>
+              <mode name="blut5">
+                <pb_type name="flut5" num_pb="1">
+                  <input name="in" num_pins="5"/>
+                  <output name="out" num_pins="1"/>
+                  <clock name="clk" num_pins="1"/>
+                  <!-- Regular LUT mode -->
+                  <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
+                    <input name="in" num_pins="5" port_class="lut_in"/>
+                    <output name="out" num_pins="1" port_class="lut_out"/>
+                    <!-- LUT timing using delay matrix -->
+                    <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
+                        202e-12
+                        202e-12
+                        202e-12
+                        202e-12
+                        202e-12
+                    </delay_matrix>
+                  </pb_type>
+
+                  <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+                    <input name="D" num_pins="1" port_class="D"/>
+                    <output name="Q" num_pins="1" port_class="Q"/>
+                    <clock name="clk" num_pins="1" port_class="clock"/>
+                    <T_setup value="66e-12" port="ff.D" clock="clk"/>
+                    <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+                  </pb_type>
+                  <interconnect>
+                    <direct name="direct1" input="flut5.in" output="lut5.in"/>
+                    <direct name="direct2" input="lut5.out" output="ff.D">
+                      <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
+                    </direct>
+                    <direct name="direct3" input="flut5.clk" output="ff.clk"/>
+                    <mux name="mux1" input="ff.Q lut5.out" output="flut5.out">
+                      <delay_constant max="25e-12" in_port="lut5.out" out_port="flut5.out" />
+                      <delay_constant max="45e-12" in_port="ff.Q" out_port="flut5.out" />
+                    </mux>
+                  </interconnect>
+                </pb_type>
+                <interconnect>
+                  <direct name="direct1" input="ble5.in" output="flut5.in"/>
+                  <direct name="direct2" input="ble5.clk" output="flut5.clk"/>
+                  <direct name="direct3" input="flut5.out" output="ble5.out"/>
+                </interconnect>
+              </mode>
+              <mode name="arithmetic">
+                <pb_type name="arithmetic" num_pb="1">
+                  <input name="in" num_pins="4"/>
+                  <input name="cin" num_pins="1"/>
+                  <output name="out" num_pins="1"/>
+                  <output name="cout" num_pins="1"/>
+                  <clock name="clk" num_pins="1"/>
+                  <!-- Special dual-LUT mode that drives adder only -->
+                  <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
+                    <input name="in" num_pins="4" port_class="lut_in"/>
+                    <output name="out" num_pins="1" port_class="lut_out"/>
+                    <!-- LUT timing using delay matrix -->
+                    <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                        180e-12
+                        180e-12
+                        180e-12
+                        180e-12
+                    </delay_matrix>
+                  </pb_type>
+                  <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
+                    <input name="a" num_pins="1"/>
+                    <input name="b" num_pins="1"/>
+                    <input name="cin" num_pins="1"/>
+                    <output name="cout" num_pins="1"/>
+                    <output name="sumout" num_pins="1"/>
+                    <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+                    <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+                    <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+                    <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+                    <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+                    <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.cout"/>
+                  </pb_type>
+                  <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+                    <input name="D" num_pins="1" port_class="D"/>
+                    <output name="Q" num_pins="1" port_class="Q"/>
+                    <clock name="clk" num_pins="1" port_class="clock"/>
+                    <T_setup value="66e-12" port="ff.D" clock="clk"/>
+                    <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+                  </pb_type>
+                  <interconnect>
+                    <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
+                    <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
+                    <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
+                    <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
+                    </direct>
+                    <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
+                    </direct>
+                    <direct name="add_to_ff" input="adder.sumout" output="ff.D">
+                      <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
+                    </direct>
+                    <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
+                      <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
+                    </direct>
+                    <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
+                      <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
+                    </direct>
+                    <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
+                      <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
+                      <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out" />
+                    </mux>
+                  </interconnect>
+                </pb_type>
+
+                <interconnect>
+                  <direct name="direct1" input="ble5.in[3:0]" output="arithmetic.in"/>
+                  <direct name="carry_in" input="ble5.cin" output="arithmetic.cin">
+                    <!--pack_pattern name="chain" in_port="ble5.cin" out_port="arithmetic.cin"/-->
+                  </direct>
+                  <direct name="carry_out" input="arithmetic.cout" output="ble5.cout">
+                    <!--pack_pattern name="chain" in_port="arithmetic.cout" out_port="ble5.cout"/-->
+                  </direct>
+                  <direct name="direct2" input="ble5.clk" output="arithmetic.clk"/>
+                  <direct name="direct3" input="arithmetic.out" output="ble5.out"/>
+                </interconnect>
+              </mode>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="lut5inter.in" output="ble5[0:0].in"/>
+              <direct name="direct2" input="lut5inter.in" output="ble5[1:1].in"/>
+              <direct name="direct3" input="ble5[1:0].out" output="lut5inter.out"/>
+              <direct name="carry_in" input="lut5inter.cin" output="ble5[0:0].cin">
+                <!--pack_pattern name="chain" in_port="lut5inter.cin" out_port="ble5[0:0].cin"/-->
+              </direct>
+              <direct name="carry_out" input="ble5[1:1].cout" output="lut5inter.cout">
+                <!--pack_pattern name="chain" in_port="ble5[1:1].cout" out_port="lut5inter.cout"/-->
+              </direct>
+              <direct name="carry_link" input="ble5[0:0].cout" output="ble5[1:1].cin">
+                <!--pack_pattern name="chain" in_port="ble5[0:0].cout" out_port="ble5[1:1].cout"/-->
+              </direct>
+              <complete name="complete1" input="lut5inter.clk" output="ble5[1:0].clk"/>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[4:0]" output="lut5inter.in"/>
+            <direct name="direct2" input="lut5inter.out" output="fle.out"/>
+            <direct name="direct3" input="fle.clk" output="lut5inter.clk"/>
+            <direct name="carry_in" input="fle.cin" output="lut5inter.cin">
+              <!--pack_pattern name="chain" in_port="fle.cin" out_port="lut5inter.cin"/-->
+            </direct>
+            <direct name="carry_out" input="lut5inter.cout" output="fle.cout">
+              <!--pack_pattern name="chain" in_port="lut5inter.cout" out_port="fle.cout"/-->
+            </direct>
+          </interconnect>
+        </mode>
+        <!-- Define n2_lut5 mode ends -->
+        <mode name="n1_lut6">
+          <pb_type name="ble6" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="6" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                  229e-12
+                  229e-12
+                  229e-12
+                  229e-12
+                  229e-12
+                  229e-12
+              </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+
+            <interconnect>
+              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+              <direct name="direct2" input="lut6.out" output="ff.D">
+                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out" />
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out" />
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="ble6.in"/>
+            <direct name="direct2" input="ble6.out" output="fle.out[1:1]"/>
+            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Define n1_lut6 mode ends -->
+        <!-- Define shift register mode begins -->
+        <mode name="shift_register">
+          <pb_type name="ble_shift" num_pb="1">
+            <input name="in" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="regout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="ff" blif_model=".subckt shift" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble_shift.in" output="ff[0].D"/>
+              <direct name="direct2" input="ff[0].Q" output="ff[1].D">
+                <!--pack_pattern name="ble_shift" in_port="ff[0].Q" out_port="ff[1].D"/-->
+              </direct>
+              <direct name="out1" input="ff[0].Q" output="ble_shift.out[0]"/>
+              <direct name="out2" input="ff[1].Q" output="ble_shift.out[1]"/>
+              <direct name="direct_regout" input="ff[1].Q" output="ble_shift.regout"/>
+              <complete name="direct3" input="ble_shift.clk" output="ff[1:0].clk"/>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.regin" output="ble_shift.in"/>
+            <direct name="direct2" input="ble_shift.out" output="fle.out"/>
+            <direct name="direct3" input="fle.clk" output="ble_shift.clk"/>
+            <direct name="direct4" input="ble_shift.regout" output="fle.regout"/>
+          </interconnect>
+        </mode>
+       <!-- Define shift_register mode end -->
+      </pb_type>
+      <interconnect>
+        <complete name="crossbar0" input="clb.I2 clb.I3 fle[9:0].out" output="fle[9:0].in[0]">
+          <delay_constant max="190e-12" in_port="clb.I2 clb.I3" out_port="fle[9:0].in[0]" />
+          <delay_constant max="190e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[0]" />
+        </complete>
+        <complete name="crossbar1" input="clb.I1 clb.I2 fle[9:0].out" output="fle[9:0].in[1]">
+          <delay_constant max="190e-12" in_port="clb.I1 clb.I2" out_port="fle[9:0].in[1]" />
+          <delay_constant max="190e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[1]" />
+        </complete>
+        <complete name="crossbar2" input="clb.I0 clb.I1 fle[9:0].out" output="fle[9:0].in[2]">
+          <delay_constant max="190e-12" in_port="clb.I0 clb.I1" out_port="fle[9:0].in[2]" />
+          <delay_constant max="190e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[2]" />
+        </complete>
+        <complete name="crossbar3" input="clb.I1 clb.I3 fle[9:0].out" output="fle[9:0].in[3]">
+          <delay_constant max="190e-12" in_port="clb.I1 clb.I3" out_port="fle[9:0].in[3]" />
+          <delay_constant max="190e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[3]" />
+        </complete>
+        <complete name="crossbar4" input="clb.I0 clb.I2 fle[9:0].out" output="fle[9:0].in[4]">
+          <delay_constant max="190e-12" in_port="clb.I0 clb.I2" out_port="fle[9:0].in[4]" />
+          <delay_constant max="190e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[4]" />
+        </complete>
+        <complete name="crossbar5" input="clb.I0 clb.I3 fle[9:0].out" output="fle[9:0].in[5]">
+        </complete>
+        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+        </complete>
+        <complete name="carry_in" input="clb.cin clb.cin_trick fle[9:0].out" output="fle[0:0].cin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <!--delay_constant max="0.15e-9" in_port="clb.cin clb.cin_trick" out_port="fle[0:0].cin"/-->
+          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
+          <!--pack_pattern name="chain" in_port="clb.cin_trick" out_port="fle[0:0].cin"/-->
+        </complete>
+
+        <!--direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
+          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
+        </direct-->
+        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
+        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
+        <direct name="cout_copy" input="fle[9:9].cout" output="clb.cout_copy"/>
+
+        <!-- Shift register links -->
+        <direct name="regin" input="clb.regin" output="fle[0:0].regin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.15e-9" in_port="clb.regin" out_port="fle[0:0].regin"/>
+          <pack_pattern name="chain" in_port="clb.regin" out_port="fle[0:0].regin"/>
+        </direct>
+        <direct name="regout" input="fle[9:9].regout" output="clb.regout">
+          <pack_pattern name="chain" in_port="fle[9:9].regout" out_port="clb.regout"/>
+        </direct>
+        <direct name="reg_link" input="fle[8:0].regout" output="fle[9:1].regin">
+          <pack_pattern name="chain" in_port="fle[8:0].regout" out_port="fle[9:1].regin"/>
+        </direct>
+        <!-- Carry chain links -->
+        <direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
+          <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
+        </direct>
+        <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
+          <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
+        </direct>
+        <!-- Scan chain links -->
+        <direct name="sc_in" input="clb.sc_in" output="fle[0:0].sc_in">
+        </direct>
+        <direct name="sc_out" input="fle[9:9].sc_out" output="clb.sc_out">
+        </direct>
+        <direct name="sc_link" input="fle[8:0].sc_out" output="fle[9:1].sc_in">
+        </direct>
+      </interconnect>
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+  </complexblocklist>
+</architecture>

From 73e90063728e037f45c4d8a6ac5e8a379bf3e5d3 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 22 Apr 2020 12:56:09 -0600
Subject: [PATCH 466/645] add arch file with spy pads

---
 ...egister_scan_chain_depop50_spypad_40nm.xml | 680 --------------
 ...egister_scan_chain_depop50_spypad_40nm.xml | 862 ++++++++++++++++++
 ...can_chain_depop50_spypad_40nm_openfpga.xml | 373 ++++++++
 3 files changed, 1235 insertions(+), 680 deletions(-)
 delete mode 100755 openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml
 create mode 100644 openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml

diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml
deleted file mode 100755
index 70bc907f8..000000000
--- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml
+++ /dev/null
@@ -1,680 +0,0 @@
-<!-- Homogeneous FPGA Architecture with Carry Chain for VPR8
-
-  - The chip layout is organized with a 2x2 array of Configurable Logic Blocks (CLBs)
-    surrounded by a ring of I/Os
-  - [TODO] Delay numbers are extracted from a 12 nm technology
-  Author: Xifan Tang, Aurelien Alacchi and Ganesh Gore
--->
-<architecture>
-  <!-- 
-       ODIN II specific config begins 
-       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
-       ".model [type_of_block]") that this architecture supports.
-
-       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
-       already special structures in blif (.names, .input, .output, and .latch) 
-       that describe them.
-  -->
-  <models>
-    <model name="adder">
-      <input_ports>
-        <port name="a" combinational_sink_ports="sumout cout"/>
-        <port name="b" combinational_sink_ports="sumout cout"/>
-        <port name="cin" combinational_sink_ports="sumout cout"/>
-      </input_ports>
-      <output_ports>
-        <port name="cout"/>
-        <port name="sumout"/>
-      </output_ports>
-    </model>
-    <!-- A virtual model for I/O to be used in the physical mode of io block -->
-    <model name="io">
-      <input_ports>
-        <port name="outpad"/>
-      </input_ports>
-      <output_ports>
-        <port name="inpad"/>
-      </output_ports>
-    </model>
-    <!-- A virtual model for I/O to be used in the physical mode of io block -->
-    <model name="frac_lut6">
-      <input_ports>
-        <port name="in"/>
-      </input_ports>
-      <output_ports>
-        <port name="lut4_out"/>
-        <port name="lut5_out"/>
-        <port name="lut6_out"/>
-      </output_ports>
-    </model>
-    <model name="shift">
-      <input_ports>
-        <port name="D" clock="clk"/>
-        <port name="clk" is_clock="1"/>
-      </input_ports>
-      <output_ports>
-        <port name="Q" clock="clk"/>
-      </output_ports>
-    </model>
-    <model name="scff">
-      <input_ports>
-        <port name="D" clock="clk"/>
-        <port name="D_chain" clock="clk"/>
-        <port name="clk" is_clock="1"/>
-      </input_ports>
-      <output_ports>
-        <port name="Q" clock="clk"/>
-      </output_ports>
-    </model>
-  </models>
-  <tiles>
-    <!-- Each I/O tile includes a GPIO --> 
-    <!-- IOs go on the periphery of the FPGA, for consistency, 
-         make it physically equivalent on all sides so that only one definition of I/Os is needed.
-         If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
-      -->
-    <tile name="io" capacity="1" area="0">
-      <equivalent_sites>
-        <site pb_type="io"/>
-      </equivalent_sites>
-      <input name="outpad" num_pins="1"/>
-      <output name="inpad" num_pins="1"/>
-      <!-- Each input of the tile can be driven by 15% of routing tracks
-           Each output of the tile can drive 10% of routing tracks
-        -->
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
-      <pinlocations pattern="custom">
-        <loc side="left">io.outpad io.inpad</loc>
-        <loc side="top">io.outpad io.inpad</loc>
-        <loc side="right">io.outpad io.inpad</loc>
-        <loc side="bottom">io.outpad io.inpad</loc>
-      </pinlocations>
-    </tile>
-    <!-- Each CLB tile includes a Configurable Logic Block (CLB)
-         Each input of the tile can be driven by 15% of routing tracks
-         Each output of the tile can drive 10% of routing tracks
-      -->
-    <tile name="clb" area="53894">
-      <equivalent_sites>
-        <site pb_type="clb"/>
-      </equivalent_sites>
-      <input name="I0" num_pins="10" equivalent="full"/>
-      <input name="I1" num_pins="10" equivalent="full"/>
-      <input name="I2" num_pins="10" equivalent="full"/>
-      <input name="I3" num_pins="10" equivalent="full"/>
-      <input name="sc_in" num_pins="1"/>
-      <input name="cin" num_pins="1"/>
-      <input name="cin_trick" num_pins="1"/>
-      <input name="regin" num_pins="1"/>
-      <output name="O" num_pins="20" equivalent="none"/>
-      <output name="sc_out" num_pins="1"/>
-      <output name="cout" num_pins="1"/>
-      <output name="cout_copy" num_pins="1"/>
-      <output name="regout" num_pins="1"/>
-      <clock name="clk" num_pins="1"/>
-      <!-- Each input of the tile can be driven by 15% of routing tracks
-           Each output of the tile can drive 10% of routing tracks
-           There are four pins (cin, cout, sc_in, sc_out) has not connection 
-           to routing tracks. There are directed wired from/to adjacent CLBs
-        -->
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
-        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
-        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
-        <fc_override port_name="sc_in" fc_type="frac" fc_val="0"/>
-        <fc_override port_name="sc_out" fc_type="frac" fc_val="0"/>
-      </fc>
-      <!-- Highly recommand to customize pin location when direct connection is used!!! -->
-      <!-- To ensure best tileable routing architecture (minimize the number of unique SBs
-           We keep all the pins that touch routing architecture on the right and bottom sides of the tile
-           Top side pins are mainly for direct connections
-        -->
-      <pinlocations pattern="custom">
-        <loc side="left"></loc>
-        <loc side="top">clb.sc_in clb.cin clb.cin_trick clb.regin clb.clk</loc>
-        <loc side="right">clb.I0[9:0] clb.I1[9:0] clb.O[9:0]</loc>
-        <loc side="bottom">clb.cout clb.cout_copy clb.sc_out clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10]</loc>
-      </pinlocations>
-    </tile>
-  </tiles>
-  <!-- ODIN II specific config ends -->
-  <!-- Physical descriptions begin -->
-  <!-- Apply tileable routing architecture.
-       This is strongly recommended if you want to PnR large FPGA fabric
-    -->
-  <layout tileable="true">
-    <!--auto_layout aspect_ratio="1.0"-->
-    <!-- Apply a fixed layout of 2x2 core array.
-         VPR8 considers the I/O ring in the array size
-         Therefore the height and width are both 4
-      -->
-    <fixed_layout name="2x2" width="4" height="4">
-      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
-      <perimeter type="io" priority="100"/>
-      <corners type="EMPTY" priority="101"/>
-      <!--Fill with 'clb'-->
-      <fill type="clb" priority="10"/>
-    </fixed_layout>
-    <!-- /auto_layout -->
-  </layout>
-  <device>
-    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
-    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
-         area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
-      -->
-    <area grid_logic_tile_area="0"/>
-    <chan_width_distr>
-      <x distr="uniform" peak="1.000000"/>
-      <y distr="uniform" peak="1.000000"/>
-    </chan_width_distr>
-    <!-- Use Wilton-style connecting pattern in switch block 
-         Each routing track has access to only three other routing tracks
-         (one per each side of the switch block except the side where the routing track locates)
-      -->
-    <switch_block type="wilton" fs="3"/>
-    <connection_block input_switch_name="ipin_cblock"/>
-  </device>
-  <switchlist>
-    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
-    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
-  </switchlist>
-  <segmentlist>
-    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
-    <!-- Uni-directional routing architecture using only length-4 wires in routing channels -->
-    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
-      <mux name="0"/>
-      <sb type="pattern">1 1 1 1 1</sb>
-      <cb type="pattern">1 1 1 1</cb>
-    </segment>
-  </segmentlist>
-  <directlist>
-    <!-- Hard adder chain inside CLB is directly connected between adjacent CLBs -->
-    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
-    <!-- Scan chain inside CLB is directly connected between adjacent CLBs -->
-    <direct name="scff_chain" from_pin="clb.sc_out" to_pin="clb.sc_in" x_offset="0" y_offset="-1" z_offset="0"/>
-  </directlist>
-  <complexblocklist>
-    <!-- Define I/O pads begin -->
-    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
-    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
-    <pb_type name="io">
-      <input name="outpad" num_pins="1"/>
-      <output name="inpad" num_pins="1"/>
-
-      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
-           If you need to register the I/O, define clocks in the circuit models
-           These clocks can be handled in back-end
-       -->
-      <!-- A mode denotes the physical implementation of an I/O 
-           This mode will be not packable but is mainly used for fabric verilog generation   
-        -->
-      <mode name="physical" packable="false">
-        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
-          <input name="outpad" num_pins="1"/>
-          <output name="inpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="outpad" input="io.outpad" output="iopad.outpad">
-            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
-          </direct>
-          <direct name="inpad" input="iopad.inpad" output="io.inpad">
-            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-
-      <!-- IOs can operate as either inputs or outputs.
-       Delays below come from Ian Kuon. They are small, so they should be interpreted as
-       the delays to and from registers in the I/O (and generally I/Os are registered 
-       today and that is when you timing analyze them.
-       -->
-      <mode name="inpad">
-        <pb_type name="inpad" blif_model=".input" num_pb="1">
-          <output name="inpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="inpad" input="inpad.inpad" output="io.inpad">
-            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-      <mode name="outpad">
-        <pb_type name="outpad" blif_model=".output" num_pb="1">
-          <input name="outpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="outpad" input="io.outpad" output="outpad.outpad">
-            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-      <power method="ignore"/>
-    </pb_type>
-    <!-- Define I/O pads ends -->
-    <!-- Define multi-mode Configurable Logic Block (CLB) begin -->
-    <!-- Technical highlight:
-         K6_frac_N10_I40_chain_shiftreg_depop50
-         - K6_frac: Each Logic Element (LE) contains a fracturable 6 LUT,
-                    which can operate as one 6-LUT or two 5-LUTs or four 4-LUTs 
-                    In addition to 6-LUT, each LE also includes two Flip-Flops
-         - N10: every CLB consists of 10 LEs and a local routing architecture
-         - I40: every CLB has 40 inputs
-         - chain: a hard adder chain across all the LEs in a CLB
-                  The inputs of adder are driven by 4-LUTs.
-                  The sumout of adder can optional drive an LE output or a Flip-Flop
-                  The carry-out of adder will drive the carry-in of the next adder in the chain
-         - shiftreg: Flip-flops inside CLB can be configured as shift registers.
-                     The organization is similar the hard adder chain except it is programmable
-         - depop50: every local routing multiplexer accesses to 50% of the CLB inputs
-      -->
-    <pb_type name="clb">
-      <input name="I0" num_pins="10" equivalent="full"/>
-      <input name="I1" num_pins="10" equivalent="full"/>
-      <input name="I2" num_pins="10" equivalent="full"/>
-      <input name="I3" num_pins="10" equivalent="full"/>
-      <input name="sc_in" num_pins="1"/>
-      <input name="cin" num_pins="1"/>
-      <input name="cin_trick" num_pins="1"/>
-      <input name="regin" num_pins="1"/>
-      <output name="O" num_pins="20" equivalent="none"/>
-      <output name="sc_out" num_pins="1"/>
-      <output name="cout" num_pins="1"/>
-      <output name="cout_copy" num_pins="1"/>
-      <output name="regout" num_pins="1"/>
-      <clock name="clk" num_pins="1"/>
-
-      <!-- Describe fracturable logic element -->
-      <pb_type name="fle" num_pb="10">
-        <input name="in" num_pins="6"/>
-        <input name="cin" num_pins="1"/>
-        <input name="sc_in" num_pins="1"/>
-        <input name="regin" num_pins="1"/>
-        <output name="out" num_pins="2"/>
-        <output name="cout" num_pins="1"/>
-        <output name="sc_out" num_pins="1"/>
-        <output name="regout" num_pins="1"/>
-        <clock name="clk" num_pins="1"/>
-
-        <!-- Describe physical mode begins -->
-        <mode name="physical" packable="false">
-          <pb_type name="frac_logic" num_pb="1">
-            <input name="in" num_pins="6"/>
-            <input name="cin" num_pins="1"/>
-            <input name="regin" num_pins="1"/>
-            <input name="regchain" num_pins="1"/>
-            <output name="out" num_pins="2"/>
-            <output name="cout" num_pins="1"/>
-            <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
-              <input name="in" num_pins="6"/>
-              <output name="lut4_out" num_pins="4"/>
-              <output name="lut5_out" num_pins="2"/>
-              <output name="lut6_out" num_pins="1"/>
-            </pb_type>
-            <pb_type name="adder_phy" blif_model=".subckt adder" num_pb="2">
-              <input name="a" num_pins="1"/>
-              <input name="b" num_pins="1"/>
-              <input name="cin" num_pins="1"/>
-              <output name="cout" num_pins="1"/>
-              <output name="sumout" num_pins="1"/>
-              <delay_constant max="0.3e-9" in_port="adder_phy.a" out_port="adder_phy.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder_phy.b" out_port="adder_phy.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder_phy.cin" out_port="adder_phy.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder_phy.a" out_port="adder_phy.cout"/>
-              <delay_constant max="0.3e-9" in_port="adder_phy.b" out_port="adder_phy.cout"/>
-              <delay_constant max="0.3e-9" in_port="adder_phy.cin" out_port="adder_phy.cout"/>
-            </pb_type>
-            <interconnect>
-              <direct name="direct_fraclut_in" input="frac_logic.in[5:0]" output="frac_lut6.in[5:0]"/>
-              <direct name="direct_cin" input="frac_logic.cin" output="adder_phy[0].cin"/>
-              <direct name="direct_carry" input="adder_phy[0].cout" output="adder_phy[1].cin"/>
-              <direct name="direct_cout" input="adder_phy[1].cout" output="frac_logic.cout"/>
-              <direct name="direct_lut4carry0" input="frac_lut6.lut4_out[0]" output="adder_phy[0].a"/>
-              <direct name="direct_lut4carry1" input="frac_lut6.lut4_out[1]" output="adder_phy[0].b"/>
-              <direct name="direct_lut4carry2" input="frac_lut6.lut4_out[2]" output="adder_phy[1].a"/>
-              <direct name="direct_lut4carry3" input="frac_lut6.lut4_out[3]" output="adder_phy[1].b"/>
-              <mux name="mux1" input="adder_phy[0].sumout frac_lut6.lut5_out[0] frac_logic.regin" output="frac_logic.out[0]">
-              </mux>
-              <mux name="mux2" input="adder_phy[1].sumout frac_lut6.lut5_out[1] frac_lut6.lut6_out[0] frac_logic.regchain[0]" output="frac_logic.out[1]">
-              </mux>
-            </interconnect>
-          </pb_type>
-          <pb_type name="ff_phy" blif_model=".subckt scff" num_pb="2">
-            <input name="D" num_pins="1"/>
-            <input name="D_chain" num_pins="1"/>
-            <output name="Q" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <T_setup value="66e-12" port="ff_phy.D" clock="clk"/>
-            <T_setup value="66e-12" port="ff_phy.D_chain" clock="clk"/>
-            <T_clock_to_Q max="124e-12" port="ff_phy.Q" clock="clk"/>
-          </pb_type>
-          <interconnect>
-            <complete name="direct_clk" input="fle.clk" output="ff_phy[1:0].clk"/>
-            <direct name="direct_in" input="fle.in[5:0]" output="frac_logic.in[5:0]"/>
-            <direct name="direct_regin" input="fle.regin" output="frac_logic.regin"/>
-            <direct name="direct_regchain" input="ff_phy[0].Q" output="frac_logic.regchain"/>
-            <direct name="direct_regout" input="ff_phy[1].Q" output="fle.regout"/>
-            <direct name="direct_cin" input="fle.cin" output="frac_logic.cin"/>
-            <direct name="direct_cout" input="frac_logic.cout" output="fle.cout"/>
-            <direct name="direct_frac_out1" input="frac_logic.out[0]" output="ff_phy[0].D"/>
-            <direct name="direct_frac_out2" input="frac_logic.out[1]" output="ff_phy[1].D"/>
-            <direct name="direct_fle_scin" input="fle.sc_in" output="ff_phy[0].D_chain"/>
-            <direct name="direct_fle_sc_chain" input="ff_phy[0].Q" output="ff_phy[1].D_chain"/>
-            <direct name="direct_fle_scout" input="ff_phy[1].Q" output="fle.sc_out"/>
-            <mux name="mux1" input="ff_phy[0].Q frac_logic.out[0]" output="fle.out[0]">
-            </mux>
-            <mux name="mux2" input="ff_phy[1].Q frac_logic.out[1]" output="fle.out[1]">
-            </mux>
-          </interconnect>
-        </mode>
-        <!-- Define physical mode begins -->
-        <!-- Define n2_lut5 mode begins -->
-        <mode name="n2_lut5" packable="true">
-          <pb_type name="lut5inter" num_pb="1">
-            <input name="in" num_pins="5"/>
-            <input name="cin" num_pins="1"/>
-            <output name="out" num_pins="2"/>
-            <output name="cout" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <pb_type name="ble5" num_pb="2">
-              <input name="in" num_pins="5"/>
-              <input name="cin" num_pins="1"/>
-              <output name="out" num_pins="1"/>
-              <output name="cout" num_pins="1"/>
-              <clock name="clk" num_pins="1"/>
-              <mode name="blut5">
-                <pb_type name="flut5" num_pb="1">
-                  <input name="in" num_pins="5"/>
-                  <output name="out" num_pins="1"/>
-                  <clock name="clk" num_pins="1"/>
-                  <!-- Regular LUT mode -->
-                  <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
-                    <input name="in" num_pins="5" port_class="lut_in"/>
-                    <output name="out" num_pins="1" port_class="lut_out"/>
-                    <!-- LUT timing using delay matrix -->
-                    <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
-                        202e-12
-                        202e-12
-                        202e-12
-                        202e-12
-                        202e-12
-                    </delay_matrix>
-                  </pb_type>
-
-                  <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-                    <input name="D" num_pins="1" port_class="D"/>
-                    <output name="Q" num_pins="1" port_class="Q"/>
-                    <clock name="clk" num_pins="1" port_class="clock"/>
-                    <T_setup value="66e-12" port="ff.D" clock="clk"/>
-                    <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-                  </pb_type>
-                  <interconnect>
-                    <direct name="direct1" input="flut5.in" output="lut5.in"/>
-                    <direct name="direct2" input="lut5.out" output="ff.D">
-                      <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
-                    </direct>
-                    <direct name="direct3" input="flut5.clk" output="ff.clk"/>
-                    <mux name="mux1" input="ff.Q lut5.out" output="flut5.out">
-                      <delay_constant max="25e-12" in_port="lut5.out" out_port="flut5.out" />
-                      <delay_constant max="45e-12" in_port="ff.Q" out_port="flut5.out" />
-                    </mux>
-                  </interconnect>
-                </pb_type>
-                <interconnect>
-                  <direct name="direct1" input="ble5.in" output="flut5.in"/>
-                  <direct name="direct2" input="ble5.clk" output="flut5.clk"/>
-                  <direct name="direct3" input="flut5.out" output="ble5.out"/>
-                </interconnect>
-              </mode>
-              <mode name="arithmetic">
-                <pb_type name="arithmetic" num_pb="1">
-                  <input name="in" num_pins="4"/>
-                  <input name="cin" num_pins="1"/>
-                  <output name="out" num_pins="1"/>
-                  <output name="cout" num_pins="1"/>
-                  <clock name="clk" num_pins="1"/>
-                  <!-- Special dual-LUT mode that drives adder only -->
-                  <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
-                    <input name="in" num_pins="4" port_class="lut_in"/>
-                    <output name="out" num_pins="1" port_class="lut_out"/>
-                    <!-- LUT timing using delay matrix -->
-                    <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
-                        180e-12
-                        180e-12
-                        180e-12
-                        180e-12
-                    </delay_matrix>
-                  </pb_type>
-                  <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
-                    <input name="a" num_pins="1"/>
-                    <input name="b" num_pins="1"/>
-                    <input name="cin" num_pins="1"/>
-                    <output name="cout" num_pins="1"/>
-                    <output name="sumout" num_pins="1"/>
-                    <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
-                    <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
-                    <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
-                    <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
-                    <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
-                    <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.cout"/>
-                  </pb_type>
-                  <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-                    <input name="D" num_pins="1" port_class="D"/>
-                    <output name="Q" num_pins="1" port_class="Q"/>
-                    <clock name="clk" num_pins="1" port_class="clock"/>
-                    <T_setup value="66e-12" port="ff.D" clock="clk"/>
-                    <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-                  </pb_type>
-                  <interconnect>
-                    <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
-                    <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
-                    <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
-                    <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
-                    </direct>
-                    <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
-                    </direct>
-                    <direct name="add_to_ff" input="adder.sumout" output="ff.D">
-                      <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
-                    </direct>
-                    <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
-                      <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
-                    </direct>
-                    <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
-                      <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
-                    </direct>
-                    <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
-                      <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
-                      <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out" />
-                    </mux>
-                  </interconnect>
-                </pb_type>
-
-                <interconnect>
-                  <direct name="direct1" input="ble5.in[3:0]" output="arithmetic.in"/>
-                  <direct name="carry_in" input="ble5.cin" output="arithmetic.cin">
-                    <!--pack_pattern name="chain" in_port="ble5.cin" out_port="arithmetic.cin"/-->
-                  </direct>
-                  <direct name="carry_out" input="arithmetic.cout" output="ble5.cout">
-                    <!--pack_pattern name="chain" in_port="arithmetic.cout" out_port="ble5.cout"/-->
-                  </direct>
-                  <direct name="direct2" input="ble5.clk" output="arithmetic.clk"/>
-                  <direct name="direct3" input="arithmetic.out" output="ble5.out"/>
-                </interconnect>
-              </mode>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="lut5inter.in" output="ble5[0:0].in"/>
-              <direct name="direct2" input="lut5inter.in" output="ble5[1:1].in"/>
-              <direct name="direct3" input="ble5[1:0].out" output="lut5inter.out"/>
-              <direct name="carry_in" input="lut5inter.cin" output="ble5[0:0].cin">
-                <!--pack_pattern name="chain" in_port="lut5inter.cin" out_port="ble5[0:0].cin"/-->
-              </direct>
-              <direct name="carry_out" input="ble5[1:1].cout" output="lut5inter.cout">
-                <!--pack_pattern name="chain" in_port="ble5[1:1].cout" out_port="lut5inter.cout"/-->
-              </direct>
-              <direct name="carry_link" input="ble5[0:0].cout" output="ble5[1:1].cin">
-                <!--pack_pattern name="chain" in_port="ble5[0:0].cout" out_port="ble5[1:1].cout"/-->
-              </direct>
-              <complete name="complete1" input="lut5inter.clk" output="ble5[1:0].clk"/>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in[4:0]" output="lut5inter.in"/>
-            <direct name="direct2" input="lut5inter.out" output="fle.out"/>
-            <direct name="direct3" input="fle.clk" output="lut5inter.clk"/>
-            <direct name="carry_in" input="fle.cin" output="lut5inter.cin">
-              <!--pack_pattern name="chain" in_port="fle.cin" out_port="lut5inter.cin"/-->
-            </direct>
-            <direct name="carry_out" input="lut5inter.cout" output="fle.cout">
-              <!--pack_pattern name="chain" in_port="lut5inter.cout" out_port="fle.cout"/-->
-            </direct>
-          </interconnect>
-        </mode>
-        <!-- Define n2_lut5 mode ends -->
-        <mode name="n1_lut6">
-          <pb_type name="ble6" num_pb="1">
-            <input name="in" num_pins="6"/>
-            <output name="out" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
-              <input name="in" num_pins="6" port_class="lut_in"/>
-              <output name="out" num_pins="1" port_class="lut_out"/>
-              <!-- LUT timing using delay matrix -->
-              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
-                  229e-12
-                  229e-12
-                  229e-12
-                  229e-12
-                  229e-12
-                  229e-12
-              </delay_matrix>
-            </pb_type>
-            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>
-
-            <interconnect>
-              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
-              <direct name="direct2" input="lut6.out" output="ff.D">
-                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
-              </direct>
-              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
-              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
-                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out" />
-                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out" />
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in" output="ble6.in"/>
-            <direct name="direct2" input="ble6.out" output="fle.out[1:1]"/>
-            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
-          </interconnect>
-        </mode>
-        <!-- Define n1_lut6 mode ends -->
-        <!-- Define shift register mode begins -->
-        <mode name="shift_register">
-          <pb_type name="ble_shift" num_pb="1">
-            <input name="in" num_pins="1"/>
-            <output name="out" num_pins="2"/>
-            <output name="regout" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <pb_type name="ff" blif_model=".subckt shift" num_pb="2" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="ble_shift.in" output="ff[0].D"/>
-              <direct name="direct2" input="ff[0].Q" output="ff[1].D">
-                <!--pack_pattern name="ble_shift" in_port="ff[0].Q" out_port="ff[1].D"/-->
-              </direct>
-              <direct name="out1" input="ff[0].Q" output="ble_shift.out[0]"/>
-              <direct name="out2" input="ff[1].Q" output="ble_shift.out[1]"/>
-              <direct name="direct_regout" input="ff[1].Q" output="ble_shift.regout"/>
-              <complete name="direct3" input="ble_shift.clk" output="ff[1:0].clk"/>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.regin" output="ble_shift.in"/>
-            <direct name="direct2" input="ble_shift.out" output="fle.out"/>
-            <direct name="direct3" input="fle.clk" output="ble_shift.clk"/>
-            <direct name="direct4" input="ble_shift.regout" output="fle.regout"/>
-          </interconnect>
-        </mode>
-       <!-- Define shift_register mode end -->
-      </pb_type>
-      <interconnect>
-        <complete name="crossbar0" input="clb.I2 clb.I3 fle[9:0].out" output="fle[9:0].in[0]">
-          <delay_constant max="190e-12" in_port="clb.I2 clb.I3" out_port="fle[9:0].in[0]" />
-          <delay_constant max="190e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[0]" />
-        </complete>
-        <complete name="crossbar1" input="clb.I1 clb.I2 fle[9:0].out" output="fle[9:0].in[1]">
-          <delay_constant max="190e-12" in_port="clb.I1 clb.I2" out_port="fle[9:0].in[1]" />
-          <delay_constant max="190e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[1]" />
-        </complete>
-        <complete name="crossbar2" input="clb.I0 clb.I1 fle[9:0].out" output="fle[9:0].in[2]">
-          <delay_constant max="190e-12" in_port="clb.I0 clb.I1" out_port="fle[9:0].in[2]" />
-          <delay_constant max="190e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[2]" />
-        </complete>
-        <complete name="crossbar3" input="clb.I1 clb.I3 fle[9:0].out" output="fle[9:0].in[3]">
-          <delay_constant max="190e-12" in_port="clb.I1 clb.I3" out_port="fle[9:0].in[3]" />
-          <delay_constant max="190e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[3]" />
-        </complete>
-        <complete name="crossbar4" input="clb.I0 clb.I2 fle[9:0].out" output="fle[9:0].in[4]">
-          <delay_constant max="190e-12" in_port="clb.I0 clb.I2" out_port="fle[9:0].in[4]" />
-          <delay_constant max="190e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[4]" />
-        </complete>
-        <complete name="crossbar5" input="clb.I0 clb.I3 fle[9:0].out" output="fle[9:0].in[5]">
-        </complete>
-        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
-        </complete>
-        <complete name="carry_in" input="clb.cin clb.cin_trick fle[9:0].out" output="fle[0:0].cin">
-          <!-- Put all inter-block carry chain delay on this one edge -->
-          <!--delay_constant max="0.15e-9" in_port="clb.cin clb.cin_trick" out_port="fle[0:0].cin"/-->
-          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
-          <!--pack_pattern name="chain" in_port="clb.cin_trick" out_port="fle[0:0].cin"/-->
-        </complete>
-
-        <!--direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
-          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
-        </direct-->
-        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
-        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
-        <direct name="cout_copy" input="fle[9:9].cout" output="clb.cout_copy"/>
-
-        <!-- Shift register links -->
-        <direct name="regin" input="clb.regin" output="fle[0:0].regin">
-          <!-- Put all inter-block carry chain delay on this one edge -->
-          <delay_constant max="0.15e-9" in_port="clb.regin" out_port="fle[0:0].regin"/>
-          <pack_pattern name="chain" in_port="clb.regin" out_port="fle[0:0].regin"/>
-        </direct>
-        <direct name="regout" input="fle[9:9].regout" output="clb.regout">
-          <pack_pattern name="chain" in_port="fle[9:9].regout" out_port="clb.regout"/>
-        </direct>
-        <direct name="reg_link" input="fle[8:0].regout" output="fle[9:1].regin">
-          <pack_pattern name="chain" in_port="fle[8:0].regout" out_port="fle[9:1].regin"/>
-        </direct>
-        <!-- Carry chain links -->
-        <direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
-          <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
-        </direct>
-        <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
-          <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
-        </direct>
-        <!-- Scan chain links -->
-        <direct name="sc_in" input="clb.sc_in" output="fle[0:0].sc_in">
-        </direct>
-        <direct name="sc_out" input="fle[9:9].sc_out" output="clb.sc_out">
-        </direct>
-        <direct name="sc_link" input="fle[8:0].sc_out" output="fle[9:1].sc_in">
-        </direct>
-      </interconnect>
-    </pb_type>
-    <!-- Define general purpose logic block (CLB) ends -->
-  </complexblocklist>
-</architecture>
diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml
index 70bc907f8..d4a4104af 100755
--- a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml
+++ b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml
@@ -135,6 +135,51 @@
         <loc side="bottom">clb.cout clb.cout_copy clb.sc_out clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10]</loc>
       </pinlocations>
     </tile>
+    <!-- Each CLB tile with spypads includes a Configurable Logic Block (CLB) with spypads
+         Each input of the tile can be driven by 15% of routing tracks
+         Each output of the tile can drive 10% of routing tracks
+      -->
+    <tile name="clb_spypad" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb_spypad"/>
+      </equivalent_sites>
+      <input name="I0" num_pins="10" equivalent="full"/>
+      <input name="I1" num_pins="10" equivalent="full"/>
+      <input name="I2" num_pins="10" equivalent="full"/>
+      <input name="I3" num_pins="10" equivalent="full"/>
+      <input name="sc_in" num_pins="1"/>
+      <input name="cin" num_pins="1"/>
+      <input name="cin_trick" num_pins="1"/>
+      <input name="regin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="sc_out" num_pins="1"/>
+      <output name="cout" num_pins="1"/>
+      <output name="cout_copy" num_pins="1"/>
+      <output name="regout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Each input of the tile can be driven by 15% of routing tracks
+           Each output of the tile can drive 10% of routing tracks
+           There are four pins (cin, cout, sc_in, sc_out) has not connection 
+           to routing tracks. There are directed wired from/to adjacent CLBs
+        -->
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="sc_in" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="sc_out" fc_type="frac" fc_val="0"/>
+      </fc>
+      <!-- Highly recommand to customize pin location when direct connection is used!!! -->
+      <!-- To ensure best tileable routing architecture (minimize the number of unique SBs
+           We keep all the pins that touch routing architecture on the right and bottom sides of the tile
+           Top side pins are mainly for direct connections
+        -->
+      <pinlocations pattern="custom">
+        <loc side="left"></loc>
+        <loc side="top">clb_spypad.sc_in clb_spypad.cin clb_spypad.cin_trick clb_spypad.regin clb_spypad.clk</loc>
+        <loc side="right">clb_spypad.I0[9:0] clb_spypad.I1[9:0] clb_spypad.O[9:0]</loc>
+        <loc side="bottom">clb_spypad.cout clb_spypad.cout_copy clb_spypad.sc_out clb_spypad.regout clb_spypad.I2[9:0] clb_spypad.I3[9:0] clb_spypad.O[19:10]</loc>
+      </pinlocations>
+    </tile>
   </tiles>
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
@@ -153,6 +198,8 @@
       <corners type="EMPTY" priority="101"/>
       <!--Fill with 'clb'-->
       <fill type="clb" priority="10"/>
+      <!-- Use the clb with spypad at [1,1] by setting a higher priority -->
+      <single type="clb_spypad" x="1" y="1" priority="11"/>
     </fixed_layout>
     <!-- /auto_layout -->
   </layout>
@@ -676,5 +723,820 @@
       </interconnect>
     </pb_type>
     <!-- Define general purpose logic block (CLB) ends -->
+    <!-- Define multi-mode Configurable Logic Block (CLB) with spypads begin -->
+    <!-- Technical highlight:
+         K6_frac_N10_I40_chain_shiftreg_depop50
+         - K6_frac: Each Logic Element (LE) contains a fracturable 6 LUT,
+                    which can operate as one 6-LUT or two 5-LUTs or four 4-LUTs 
+                    In addition to 6-LUT, each LE also includes two Flip-Flops
+         - N10: every CLB consists of 10 LEs and a local routing architecture
+         - I40: every CLB has 40 inputs
+         - chain: a hard adder chain across all the LEs in a CLB
+                  The inputs of adder are driven by 4-LUTs.
+                  The sumout of adder can optional drive an LE output or a Flip-Flop
+                  The carry-out of adder will drive the carry-in of the next adder in the chain
+         - shiftreg: Flip-flops inside CLB can be configured as shift registers.
+                     The organization is similar the hard adder chain except it is programmable
+         - depop50: every local routing multiplexer accesses to 50% of the CLB inputs
+         - spypads: spypads are added to LUT outputs in the first fle (fle[0]) 
+      -->
+    <pb_type name="clb_spypad">
+      <input name="I0" num_pins="10" equivalent="full"/>
+      <input name="I1" num_pins="10" equivalent="full"/>
+      <input name="I2" num_pins="10" equivalent="full"/>
+      <input name="I3" num_pins="10" equivalent="full"/>
+      <input name="sc_in" num_pins="1"/>
+      <input name="cin" num_pins="1"/>
+      <input name="cin_trick" num_pins="1"/>
+      <input name="regin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="sc_out" num_pins="1"/>
+      <output name="cout" num_pins="1"/>
+      <output name="cout_copy" num_pins="1"/>
+      <output name="regout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+
+      <!-- Describe fracturable logic element -->
+      <pb_type name="fle" num_pb="9">
+        <input name="in" num_pins="6"/>
+        <input name="cin" num_pins="1"/>
+        <input name="sc_in" num_pins="1"/>
+        <input name="regin" num_pins="1"/>
+        <output name="out" num_pins="2"/>
+        <output name="cout" num_pins="1"/>
+        <output name="sc_out" num_pins="1"/>
+        <output name="regout" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+
+        <!-- Describe physical mode begins -->
+        <mode name="physical" packable="false">
+          <pb_type name="frac_logic" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <input name="cin" num_pins="1"/>
+            <input name="regin" num_pins="1"/>
+            <input name="regchain" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
+              <input name="in" num_pins="6"/>
+              <output name="lut4_out" num_pins="4"/>
+              <output name="lut5_out" num_pins="2"/>
+              <output name="lut6_out" num_pins="1"/>
+            </pb_type>
+            <pb_type name="adder_phy" blif_model=".subckt adder" num_pb="2">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder_phy.a" out_port="adder_phy.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder_phy.b" out_port="adder_phy.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder_phy.cin" out_port="adder_phy.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder_phy.a" out_port="adder_phy.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder_phy.b" out_port="adder_phy.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder_phy.cin" out_port="adder_phy.cout"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct_fraclut_in" input="frac_logic.in[5:0]" output="frac_lut6.in[5:0]"/>
+              <direct name="direct_cin" input="frac_logic.cin" output="adder_phy[0].cin"/>
+              <direct name="direct_carry" input="adder_phy[0].cout" output="adder_phy[1].cin"/>
+              <direct name="direct_cout" input="adder_phy[1].cout" output="frac_logic.cout"/>
+              <direct name="direct_lut4carry0" input="frac_lut6.lut4_out[0]" output="adder_phy[0].a"/>
+              <direct name="direct_lut4carry1" input="frac_lut6.lut4_out[1]" output="adder_phy[0].b"/>
+              <direct name="direct_lut4carry2" input="frac_lut6.lut4_out[2]" output="adder_phy[1].a"/>
+              <direct name="direct_lut4carry3" input="frac_lut6.lut4_out[3]" output="adder_phy[1].b"/>
+              <mux name="mux1" input="adder_phy[0].sumout frac_lut6.lut5_out[0] frac_logic.regin" output="frac_logic.out[0]">
+              </mux>
+              <mux name="mux2" input="adder_phy[1].sumout frac_lut6.lut5_out[1] frac_lut6.lut6_out[0] frac_logic.regchain[0]" output="frac_logic.out[1]">
+              </mux>
+            </interconnect>
+          </pb_type>
+          <pb_type name="ff_phy" blif_model=".subckt scff" num_pb="2">
+            <input name="D" num_pins="1"/>
+            <input name="D_chain" num_pins="1"/>
+            <output name="Q" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <T_setup value="66e-12" port="ff_phy.D" clock="clk"/>
+            <T_setup value="66e-12" port="ff_phy.D_chain" clock="clk"/>
+            <T_clock_to_Q max="124e-12" port="ff_phy.Q" clock="clk"/>
+          </pb_type>
+          <interconnect>
+            <complete name="direct_clk" input="fle.clk" output="ff_phy[1:0].clk"/>
+            <direct name="direct_in" input="fle.in[5:0]" output="frac_logic.in[5:0]"/>
+            <direct name="direct_regin" input="fle.regin" output="frac_logic.regin"/>
+            <direct name="direct_regchain" input="ff_phy[0].Q" output="frac_logic.regchain"/>
+            <direct name="direct_regout" input="ff_phy[1].Q" output="fle.regout"/>
+            <direct name="direct_cin" input="fle.cin" output="frac_logic.cin"/>
+            <direct name="direct_cout" input="frac_logic.cout" output="fle.cout"/>
+            <direct name="direct_frac_out1" input="frac_logic.out[0]" output="ff_phy[0].D"/>
+            <direct name="direct_frac_out2" input="frac_logic.out[1]" output="ff_phy[1].D"/>
+            <direct name="direct_fle_scin" input="fle.sc_in" output="ff_phy[0].D_chain"/>
+            <direct name="direct_fle_sc_chain" input="ff_phy[0].Q" output="ff_phy[1].D_chain"/>
+            <direct name="direct_fle_scout" input="ff_phy[1].Q" output="fle.sc_out"/>
+            <mux name="mux1" input="ff_phy[0].Q frac_logic.out[0]" output="fle.out[0]">
+            </mux>
+            <mux name="mux2" input="ff_phy[1].Q frac_logic.out[1]" output="fle.out[1]">
+            </mux>
+          </interconnect>
+        </mode>
+        <!-- Define physical mode begins -->
+        <!-- Define n2_lut5 mode begins -->
+        <mode name="n2_lut5" packable="true">
+          <pb_type name="lut5inter" num_pb="1">
+            <input name="in" num_pins="5"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="ble5" num_pb="2">
+              <input name="in" num_pins="5"/>
+              <input name="cin" num_pins="1"/>
+              <output name="out" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <clock name="clk" num_pins="1"/>
+              <mode name="blut5">
+                <pb_type name="flut5" num_pb="1">
+                  <input name="in" num_pins="5"/>
+                  <output name="out" num_pins="1"/>
+                  <clock name="clk" num_pins="1"/>
+                  <!-- Regular LUT mode -->
+                  <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
+                    <input name="in" num_pins="5" port_class="lut_in"/>
+                    <output name="out" num_pins="1" port_class="lut_out"/>
+                    <!-- LUT timing using delay matrix -->
+                    <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
+                        202e-12
+                        202e-12
+                        202e-12
+                        202e-12
+                        202e-12
+                    </delay_matrix>
+                  </pb_type>
+
+                  <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+                    <input name="D" num_pins="1" port_class="D"/>
+                    <output name="Q" num_pins="1" port_class="Q"/>
+                    <clock name="clk" num_pins="1" port_class="clock"/>
+                    <T_setup value="66e-12" port="ff.D" clock="clk"/>
+                    <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+                  </pb_type>
+                  <interconnect>
+                    <direct name="direct1" input="flut5.in" output="lut5.in"/>
+                    <direct name="direct2" input="lut5.out" output="ff.D">
+                      <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
+                    </direct>
+                    <direct name="direct3" input="flut5.clk" output="ff.clk"/>
+                    <mux name="mux1" input="ff.Q lut5.out" output="flut5.out">
+                      <delay_constant max="25e-12" in_port="lut5.out" out_port="flut5.out" />
+                      <delay_constant max="45e-12" in_port="ff.Q" out_port="flut5.out" />
+                    </mux>
+                  </interconnect>
+                </pb_type>
+                <interconnect>
+                  <direct name="direct1" input="ble5.in" output="flut5.in"/>
+                  <direct name="direct2" input="ble5.clk" output="flut5.clk"/>
+                  <direct name="direct3" input="flut5.out" output="ble5.out"/>
+                </interconnect>
+              </mode>
+              <mode name="arithmetic">
+                <pb_type name="arithmetic" num_pb="1">
+                  <input name="in" num_pins="4"/>
+                  <input name="cin" num_pins="1"/>
+                  <output name="out" num_pins="1"/>
+                  <output name="cout" num_pins="1"/>
+                  <clock name="clk" num_pins="1"/>
+                  <!-- Special dual-LUT mode that drives adder only -->
+                  <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
+                    <input name="in" num_pins="4" port_class="lut_in"/>
+                    <output name="out" num_pins="1" port_class="lut_out"/>
+                    <!-- LUT timing using delay matrix -->
+                    <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                        180e-12
+                        180e-12
+                        180e-12
+                        180e-12
+                    </delay_matrix>
+                  </pb_type>
+                  <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
+                    <input name="a" num_pins="1"/>
+                    <input name="b" num_pins="1"/>
+                    <input name="cin" num_pins="1"/>
+                    <output name="cout" num_pins="1"/>
+                    <output name="sumout" num_pins="1"/>
+                    <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+                    <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+                    <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+                    <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+                    <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+                    <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.cout"/>
+                  </pb_type>
+                  <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+                    <input name="D" num_pins="1" port_class="D"/>
+                    <output name="Q" num_pins="1" port_class="Q"/>
+                    <clock name="clk" num_pins="1" port_class="clock"/>
+                    <T_setup value="66e-12" port="ff.D" clock="clk"/>
+                    <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+                  </pb_type>
+                  <interconnect>
+                    <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
+                    <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
+                    <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
+                    <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
+                    </direct>
+                    <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
+                    </direct>
+                    <direct name="add_to_ff" input="adder.sumout" output="ff.D">
+                      <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
+                    </direct>
+                    <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
+                      <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
+                    </direct>
+                    <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
+                      <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
+                    </direct>
+                    <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
+                      <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
+                      <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out" />
+                    </mux>
+                  </interconnect>
+                </pb_type>
+
+                <interconnect>
+                  <direct name="direct1" input="ble5.in[3:0]" output="arithmetic.in"/>
+                  <direct name="carry_in" input="ble5.cin" output="arithmetic.cin">
+                    <!--pack_pattern name="chain" in_port="ble5.cin" out_port="arithmetic.cin"/-->
+                  </direct>
+                  <direct name="carry_out" input="arithmetic.cout" output="ble5.cout">
+                    <!--pack_pattern name="chain" in_port="arithmetic.cout" out_port="ble5.cout"/-->
+                  </direct>
+                  <direct name="direct2" input="ble5.clk" output="arithmetic.clk"/>
+                  <direct name="direct3" input="arithmetic.out" output="ble5.out"/>
+                </interconnect>
+              </mode>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="lut5inter.in" output="ble5[0:0].in"/>
+              <direct name="direct2" input="lut5inter.in" output="ble5[1:1].in"/>
+              <direct name="direct3" input="ble5[1:0].out" output="lut5inter.out"/>
+              <direct name="carry_in" input="lut5inter.cin" output="ble5[0:0].cin">
+                <!--pack_pattern name="chain" in_port="lut5inter.cin" out_port="ble5[0:0].cin"/-->
+              </direct>
+              <direct name="carry_out" input="ble5[1:1].cout" output="lut5inter.cout">
+                <!--pack_pattern name="chain" in_port="ble5[1:1].cout" out_port="lut5inter.cout"/-->
+              </direct>
+              <direct name="carry_link" input="ble5[0:0].cout" output="ble5[1:1].cin">
+                <!--pack_pattern name="chain" in_port="ble5[0:0].cout" out_port="ble5[1:1].cout"/-->
+              </direct>
+              <complete name="complete1" input="lut5inter.clk" output="ble5[1:0].clk"/>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[4:0]" output="lut5inter.in"/>
+            <direct name="direct2" input="lut5inter.out" output="fle.out"/>
+            <direct name="direct3" input="fle.clk" output="lut5inter.clk"/>
+            <direct name="carry_in" input="fle.cin" output="lut5inter.cin">
+              <!--pack_pattern name="chain" in_port="fle.cin" out_port="lut5inter.cin"/-->
+            </direct>
+            <direct name="carry_out" input="lut5inter.cout" output="fle.cout">
+              <!--pack_pattern name="chain" in_port="lut5inter.cout" out_port="fle.cout"/-->
+            </direct>
+          </interconnect>
+        </mode>
+        <!-- Define n2_lut5 mode ends -->
+        <mode name="n1_lut6">
+          <pb_type name="ble6" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="6" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                  229e-12
+                  229e-12
+                  229e-12
+                  229e-12
+                  229e-12
+                  229e-12
+              </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+
+            <interconnect>
+              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+              <direct name="direct2" input="lut6.out" output="ff.D">
+                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out" />
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out" />
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="ble6.in"/>
+            <direct name="direct2" input="ble6.out" output="fle.out[1:1]"/>
+            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Define n1_lut6 mode ends -->
+        <!-- Define shift register mode begins -->
+        <mode name="shift_register">
+          <pb_type name="ble_shift" num_pb="1">
+            <input name="in" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="regout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="ff" blif_model=".subckt shift" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble_shift.in" output="ff[0].D"/>
+              <direct name="direct2" input="ff[0].Q" output="ff[1].D">
+                <!--pack_pattern name="ble_shift" in_port="ff[0].Q" out_port="ff[1].D"/-->
+              </direct>
+              <direct name="out1" input="ff[0].Q" output="ble_shift.out[0]"/>
+              <direct name="out2" input="ff[1].Q" output="ble_shift.out[1]"/>
+              <direct name="direct_regout" input="ff[1].Q" output="ble_shift.regout"/>
+              <complete name="direct3" input="ble_shift.clk" output="ff[1:0].clk"/>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.regin" output="ble_shift.in"/>
+            <direct name="direct2" input="ble_shift.out" output="fle.out"/>
+            <direct name="direct3" input="fle.clk" output="ble_shift.clk"/>
+            <direct name="direct4" input="ble_shift.regout" output="fle.regout"/>
+          </interconnect>
+        </mode>
+       <!-- Define shift_register mode end -->
+      </pb_type>
+
+      <!-- Describe fracturable logic element with spy outputs -->
+      <pb_type name="fle_spypad" num_pb="1">
+        <input name="in" num_pins="6"/>
+        <input name="cin" num_pins="1"/>
+        <input name="sc_in" num_pins="1"/>
+        <input name="regin" num_pins="1"/>
+        <output name="out" num_pins="2"/>
+        <output name="cout" num_pins="1"/>
+        <output name="sc_out" num_pins="1"/>
+        <output name="regout" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+
+        <!-- Describe physical mode begins -->
+        <mode name="physical" packable="false">
+          <pb_type name="frac_logic" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <input name="cin" num_pins="1"/>
+            <input name="regin" num_pins="1"/>
+            <input name="regchain" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
+              <input name="in" num_pins="6"/>
+              <output name="lut4_out" num_pins="4"/>
+              <output name="lut5_out" num_pins="2"/>
+              <output name="lut6_out" num_pins="1"/>
+            </pb_type>
+            <pb_type name="adder_phy" blif_model=".subckt adder" num_pb="2">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder_phy.a" out_port="adder_phy.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder_phy.b" out_port="adder_phy.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder_phy.cin" out_port="adder_phy.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder_phy.a" out_port="adder_phy.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder_phy.b" out_port="adder_phy.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder_phy.cin" out_port="adder_phy.cout"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct_fraclut_in" input="frac_logic.in[5:0]" output="frac_lut6.in[5:0]"/>
+              <direct name="direct_cin" input="frac_logic.cin" output="adder_phy[0].cin"/>
+              <direct name="direct_carry" input="adder_phy[0].cout" output="adder_phy[1].cin"/>
+              <direct name="direct_cout" input="adder_phy[1].cout" output="frac_logic.cout"/>
+              <direct name="direct_lut4carry0" input="frac_lut6.lut4_out[0]" output="adder_phy[0].a"/>
+              <direct name="direct_lut4carry1" input="frac_lut6.lut4_out[1]" output="adder_phy[0].b"/>
+              <direct name="direct_lut4carry2" input="frac_lut6.lut4_out[2]" output="adder_phy[1].a"/>
+              <direct name="direct_lut4carry3" input="frac_lut6.lut4_out[3]" output="adder_phy[1].b"/>
+              <mux name="mux1" input="adder_phy[0].sumout frac_lut6.lut5_out[0] frac_logic.regin" output="frac_logic.out[0]">
+              </mux>
+              <mux name="mux2" input="adder_phy[1].sumout frac_lut6.lut5_out[1] frac_lut6.lut6_out[0] frac_logic.regchain[0]" output="frac_logic.out[1]">
+              </mux>
+            </interconnect>
+          </pb_type>
+          <pb_type name="ff_phy" blif_model=".subckt scff" num_pb="2">
+            <input name="D" num_pins="1"/>
+            <input name="D_chain" num_pins="1"/>
+            <output name="Q" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <T_setup value="66e-12" port="ff_phy.D" clock="clk"/>
+            <T_setup value="66e-12" port="ff_phy.D_chain" clock="clk"/>
+            <T_clock_to_Q max="124e-12" port="ff_phy.Q" clock="clk"/>
+          </pb_type>
+          <interconnect>
+            <complete name="direct_clk" input="fle_spypad.clk" output="ff_phy[1:0].clk"/>
+            <direct name="direct_in" input="fle_spypad.in[5:0]" output="frac_logic.in[5:0]"/>
+            <direct name="direct_regin" input="fle_spypad.regin" output="frac_logic.regin"/>
+            <direct name="direct_regchain" input="ff_phy[0].Q" output="frac_logic.regchain"/>
+            <direct name="direct_regout" input="ff_phy[1].Q" output="fle_spypad.regout"/>
+            <direct name="direct_cin" input="fle_spypad.cin" output="frac_logic.cin"/>
+            <direct name="direct_cout" input="frac_logic.cout" output="fle_spypad.cout"/>
+            <direct name="direct_frac_out1" input="frac_logic.out[0]" output="ff_phy[0].D"/>
+            <direct name="direct_frac_out2" input="frac_logic.out[1]" output="ff_phy[1].D"/>
+            <direct name="direct_fle_scin" input="fle_spypad.sc_in" output="ff_phy[0].D_chain"/>
+            <direct name="direct_fle_sc_chain" input="ff_phy[0].Q" output="ff_phy[1].D_chain"/>
+            <direct name="direct_fle_scout" input="ff_phy[1].Q" output="fle_spypad.sc_out"/>
+            <mux name="mux1" input="ff_phy[0].Q frac_logic.out[0]" output="fle_spypad.out[0]">
+            </mux>
+            <mux name="mux2" input="ff_phy[1].Q frac_logic.out[1]" output="fle_spypad.out[1]">
+            </mux>
+          </interconnect>
+        </mode>
+        <!-- Define physical mode begins -->
+        <!-- Define n2_lut5 mode begins -->
+        <mode name="n2_lut5" packable="true">
+          <pb_type name="lut5inter" num_pb="1">
+            <input name="in" num_pins="5"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="ble5" num_pb="2">
+              <input name="in" num_pins="5"/>
+              <input name="cin" num_pins="1"/>
+              <output name="out" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <clock name="clk" num_pins="1"/>
+              <mode name="blut5">
+                <pb_type name="flut5" num_pb="1">
+                  <input name="in" num_pins="5"/>
+                  <output name="out" num_pins="1"/>
+                  <clock name="clk" num_pins="1"/>
+                  <!-- Regular LUT mode -->
+                  <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
+                    <input name="in" num_pins="5" port_class="lut_in"/>
+                    <output name="out" num_pins="1" port_class="lut_out"/>
+                    <!-- LUT timing using delay matrix -->
+                    <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
+                        202e-12
+                        202e-12
+                        202e-12
+                        202e-12
+                        202e-12
+                    </delay_matrix>
+                  </pb_type>
+
+                  <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+                    <input name="D" num_pins="1" port_class="D"/>
+                    <output name="Q" num_pins="1" port_class="Q"/>
+                    <clock name="clk" num_pins="1" port_class="clock"/>
+                    <T_setup value="66e-12" port="ff.D" clock="clk"/>
+                    <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+                  </pb_type>
+                  <interconnect>
+                    <direct name="direct1" input="flut5.in" output="lut5.in"/>
+                    <direct name="direct2" input="lut5.out" output="ff.D">
+                      <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
+                    </direct>
+                    <direct name="direct3" input="flut5.clk" output="ff.clk"/>
+                    <mux name="mux1" input="ff.Q lut5.out" output="flut5.out">
+                      <delay_constant max="25e-12" in_port="lut5.out" out_port="flut5.out" />
+                      <delay_constant max="45e-12" in_port="ff.Q" out_port="flut5.out" />
+                    </mux>
+                  </interconnect>
+                </pb_type>
+                <interconnect>
+                  <direct name="direct1" input="ble5.in" output="flut5.in"/>
+                  <direct name="direct2" input="ble5.clk" output="flut5.clk"/>
+                  <direct name="direct3" input="flut5.out" output="ble5.out"/>
+                </interconnect>
+              </mode>
+              <mode name="arithmetic">
+                <pb_type name="arithmetic" num_pb="1">
+                  <input name="in" num_pins="4"/>
+                  <input name="cin" num_pins="1"/>
+                  <output name="out" num_pins="1"/>
+                  <output name="cout" num_pins="1"/>
+                  <clock name="clk" num_pins="1"/>
+                  <!-- Special dual-LUT mode that drives adder only -->
+                  <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
+                    <input name="in" num_pins="4" port_class="lut_in"/>
+                    <output name="out" num_pins="1" port_class="lut_out"/>
+                    <!-- LUT timing using delay matrix -->
+                    <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                        180e-12
+                        180e-12
+                        180e-12
+                        180e-12
+                    </delay_matrix>
+                  </pb_type>
+                  <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
+                    <input name="a" num_pins="1"/>
+                    <input name="b" num_pins="1"/>
+                    <input name="cin" num_pins="1"/>
+                    <output name="cout" num_pins="1"/>
+                    <output name="sumout" num_pins="1"/>
+                    <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+                    <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+                    <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+                    <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+                    <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+                    <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.cout"/>
+                  </pb_type>
+                  <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+                    <input name="D" num_pins="1" port_class="D"/>
+                    <output name="Q" num_pins="1" port_class="Q"/>
+                    <clock name="clk" num_pins="1" port_class="clock"/>
+                    <T_setup value="66e-12" port="ff.D" clock="clk"/>
+                    <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+                  </pb_type>
+                  <interconnect>
+                    <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
+                    <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
+                    <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
+                    <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
+                    </direct>
+                    <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
+                    </direct>
+                    <direct name="add_to_ff" input="adder.sumout" output="ff.D">
+                      <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
+                    </direct>
+                    <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
+                      <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
+                    </direct>
+                    <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
+                      <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
+                    </direct>
+                    <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
+                      <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
+                      <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out" />
+                    </mux>
+                  </interconnect>
+                </pb_type>
+
+                <interconnect>
+                  <direct name="direct1" input="ble5.in[3:0]" output="arithmetic.in"/>
+                  <direct name="carry_in" input="ble5.cin" output="arithmetic.cin">
+                    <!--pack_pattern name="chain" in_port="ble5.cin" out_port="arithmetic.cin"/-->
+                  </direct>
+                  <direct name="carry_out" input="arithmetic.cout" output="ble5.cout">
+                    <!--pack_pattern name="chain" in_port="arithmetic.cout" out_port="ble5.cout"/-->
+                  </direct>
+                  <direct name="direct2" input="ble5.clk" output="arithmetic.clk"/>
+                  <direct name="direct3" input="arithmetic.out" output="ble5.out"/>
+                </interconnect>
+              </mode>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="lut5inter.in" output="ble5[0:0].in"/>
+              <direct name="direct2" input="lut5inter.in" output="ble5[1:1].in"/>
+              <direct name="direct3" input="ble5[1:0].out" output="lut5inter.out"/>
+              <direct name="carry_in" input="lut5inter.cin" output="ble5[0:0].cin">
+                <!--pack_pattern name="chain" in_port="lut5inter.cin" out_port="ble5[0:0].cin"/-->
+              </direct>
+              <direct name="carry_out" input="ble5[1:1].cout" output="lut5inter.cout">
+                <!--pack_pattern name="chain" in_port="ble5[1:1].cout" out_port="lut5inter.cout"/-->
+              </direct>
+              <direct name="carry_link" input="ble5[0:0].cout" output="ble5[1:1].cin">
+                <!--pack_pattern name="chain" in_port="ble5[0:0].cout" out_port="ble5[1:1].cout"/-->
+              </direct>
+              <complete name="complete1" input="lut5inter.clk" output="ble5[1:0].clk"/>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle_spypad.in[4:0]" output="lut5inter.in"/>
+            <direct name="direct2" input="lut5inter.out" output="fle_spypad.out"/>
+            <direct name="direct3" input="fle_spypad.clk" output="lut5inter.clk"/>
+            <direct name="carry_in" input="fle_spypad.cin" output="lut5inter.cin">
+              <!--pack_pattern name="chain" in_port="fle.cin" out_port="lut5inter.cin"/-->
+            </direct>
+            <direct name="carry_out" input="lut5inter.cout" output="fle_spypad.cout">
+              <!--pack_pattern name="chain" in_port="lut5inter.cout" out_port="fle.cout"/-->
+            </direct>
+          </interconnect>
+        </mode>
+        <!-- Define n2_lut5 mode ends -->
+        <mode name="n1_lut6">
+          <pb_type name="ble6" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="6" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                  229e-12
+                  229e-12
+                  229e-12
+                  229e-12
+                  229e-12
+                  229e-12
+              </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+
+            <interconnect>
+              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+              <direct name="direct2" input="lut6.out" output="ff.D">
+                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out" />
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out" />
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle_spypad.in" output="ble6.in"/>
+            <direct name="direct2" input="ble6.out" output="fle_spypad.out[1:1]"/>
+            <direct name="direct3" input="fle_spypad.clk" output="ble6.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Define n1_lut6 mode ends -->
+        <!-- Define shift register mode begins -->
+        <mode name="shift_register">
+          <pb_type name="ble_shift" num_pb="1">
+            <input name="in" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="regout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="ff" blif_model=".subckt shift" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble_shift.in" output="ff[0].D"/>
+              <direct name="direct2" input="ff[0].Q" output="ff[1].D">
+                <!--pack_pattern name="ble_shift" in_port="ff[0].Q" out_port="ff[1].D"/-->
+              </direct>
+              <direct name="out1" input="ff[0].Q" output="ble_shift.out[0]"/>
+              <direct name="out2" input="ff[1].Q" output="ble_shift.out[1]"/>
+              <direct name="direct_regout" input="ff[1].Q" output="ble_shift.regout"/>
+              <complete name="direct3" input="ble_shift.clk" output="ff[1:0].clk"/>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle_spypad.regin" output="ble_shift.in"/>
+            <direct name="direct2" input="ble_shift.out" output="fle_spypad.out"/>
+            <direct name="direct3" input="fle_spypad.clk" output="ble_shift.clk"/>
+            <direct name="direct4" input="ble_shift.regout" output="fle_spypad.regout"/>
+          </interconnect>
+        </mode>
+       <!-- Define shift_register mode end -->
+      </pb_type>
+
+      <interconnect>
+        <complete name="crossbar0" input="clb_spypad.I2 clb_spypad.I3 fle[8:0].out fle_spypad.out" output="fle[8:0].in[0]">
+          <delay_constant max="190e-12" in_port="clb_spypad.I2 clb_spypad.I3" out_port="fle[8:0].in[0]" />
+          <delay_constant max="190e-12" in_port="fle[8:0].out" out_port="fle[8:0].in[0]" />
+          <delay_constant max="190e-12" in_port="fle_spypad.out" out_port="fle[8:0].in[0]" />
+        </complete>
+        <complete name="crossbar0_spyfle" input="clb_spypad.I2 clb_spypad.I3 fle[8:0].out fle_spypad.out" output="fle_spypad.in[0]">
+          <delay_constant max="190e-12" in_port="clb_spypad.I2 clb_spypad.I3" out_port="fle_spypad.in[0]" />
+          <delay_constant max="190e-12" in_port="fle[8:0].out" out_port="fle_spypad.in[0]" />
+          <delay_constant max="190e-12" in_port="fle_spypad.out" out_port="fle_spypad.in[0]" />
+        </complete>
+
+        <complete name="crossbar1" input="clb_spypad.I1 clb_spypad.I2 fle[8:0].out fle_spypad.out" output="fle[8:0].in[1]">
+          <delay_constant max="190e-12" in_port="clb_spypad.I1 clb_spypad.I2" out_port="fle[8:0].in[1]" />
+          <delay_constant max="190e-12" in_port="fle[8:0].out" out_port="fle[8:0].in[1]" />
+          <delay_constant max="190e-12" in_port="fle_spypad.out" out_port="fle[8:0].in[1]" />
+        </complete>
+        <complete name="crossbar1_spyfle" input="clb_spypad.I1 clb_spypad.I2 fle[8:0].out fle_spypad.out" output="fle_spypad.in[1]">
+          <delay_constant max="190e-12" in_port="clb_spypad.I1 clb_spypad.I2" out_port="fle_spypad.in[1]" />
+          <delay_constant max="190e-12" in_port="fle[8:0].out" out_port="fle_spypad.in[1]" />
+          <delay_constant max="190e-12" in_port="fle_spypad.out" out_port="fle_spypad.in[1]" />
+        </complete>
+
+        <complete name="crossbar2" input="clb_spypad.I0 clb_spypad.I1 fle[8:0].out fle_spypad.out" output="fle[8:0].in[2]">
+          <delay_constant max="190e-12" in_port="clb_spypad.I0 clb_spypad.I1" out_port="fle[8:0].in[2]" />
+          <delay_constant max="190e-12" in_port="fle[8:0].out" out_port="fle[8:0].in[2]" />
+          <delay_constant max="190e-12" in_port="fle_spypad.out" out_port="fle[8:0].in[2]" />
+        </complete>
+        <complete name="crossbar2_spyfle" input="clb_spypad.I0 clb_spypad.I1 fle[8:0].out fle_spypad.out" output="fle_spypad.in[2]">
+          <delay_constant max="190e-12" in_port="clb_spypad.I0 clb_spypad.I1" out_port="fle_spypad.in[2]" />
+          <delay_constant max="190e-12" in_port="fle[8:0].out" out_port="fle_spypad.in[2]" />
+          <delay_constant max="190e-12" in_port="fle_spypad.out" out_port="fle_spypad.in[2]" />
+        </complete>
+
+        <complete name="crossbar3" input="clb_spypad.I1 clb_spypad.I3 fle[8:0].out fle_spypad.out" output="fle[8:0].in[3]">
+          <delay_constant max="190e-12" in_port="clb_spypad.I1 clb_spypad.I3" out_port="fle[8:0].in[3]" />
+          <delay_constant max="190e-12" in_port="fle[8:0].out" out_port="fle[8:0].in[3]" />
+          <delay_constant max="190e-12" in_port="fle_spypad.out" out_port="fle[8:0].in[3]" />
+        </complete>
+        <complete name="crossbar3_spyfle" input="clb_spypad.I1 clb_spypad.I3 fle[8:0].out fle_spypad.out" output="fle_spypad.in[3]">
+          <delay_constant max="190e-12" in_port="clb_spypad.I1 clb_spypad.I3" out_port="fle_spypad.in[3]" />
+          <delay_constant max="190e-12" in_port="fle[8:0].out" out_port="fle_spypad.in[3]" />
+          <delay_constant max="190e-12" in_port="fle_spypad.out" out_port="fle_spypad.in[3]" />
+        </complete>
+
+        <complete name="crossbar4" input="clb_spypad.I0 clb_spypad.I2 fle[8:0].out fle_spypad.out" output="fle[8:0].in[4]">
+          <delay_constant max="190e-12" in_port="clb_spypad.I0 clb_spypad.I2" out_port="fle[8:0].in[4]" />
+          <delay_constant max="190e-12" in_port="fle[8:0].out" out_port="fle[8:0].in[4]" />
+          <delay_constant max="190e-12" in_port="fle_spypad.out" out_port="fle[8:0].in[4]" />
+        </complete>
+        <complete name="crossbar4_spyfle" input="clb_spypad.I0 clb_spypad.I2 fle[8:0].out fle_spypad.out" output="fle_spypad.in[4]">
+          <delay_constant max="190e-12" in_port="clb_spypad.I0 clb_spypad.I2" out_port="fle_spypad.in[4]" />
+          <delay_constant max="190e-12" in_port="fle[8:0].out" out_port="fle_spypad.in[4]" />
+          <delay_constant max="190e-12" in_port="fle_spypad.out" out_port="fle_spypad.in[4]" />
+        </complete>
+
+        <complete name="crossbar5" input="clb_spypad.I0 clb_spypad.I3 fle[8:0].out fle_spypad.out" output="fle[8:0].in[5]">
+          <delay_constant max="190e-12" in_port="clb_spypad.I0 clb_spypad.I3" out_port="fle[8:0].in[5]" />
+          <delay_constant max="190e-12" in_port="fle[8:0].out" out_port="fle[8:0].in[5]" />
+          <delay_constant max="190e-12" in_port="fle_spypad.out" out_port="fle[8:0].in[5]" />
+        </complete>
+        <complete name="crossbar5_spyfle" input="clb_spypad.I0 clb_spypad.I3 fle[8:0].out fle_spypad.out" output="fle_spypad.in[5]">
+          <delay_constant max="190e-12" in_port="clb_spypad.I0 clb_spypad.I3" out_port="fle_spypad.in[5]" />
+          <delay_constant max="190e-12" in_port="fle[8:0].out" out_port="fle_spypad.in[5]" />
+          <delay_constant max="190e-12" in_port="fle_spypad.out" out_port="fle_spypad.in[5]" />
+        </complete>
+
+        <complete name="clks" input="clb_spypad.clk" output="fle[8:0].clk">
+        </complete>
+        <complete name="clks_spyfle" input="clb_spypad.clk" output="fle_spypad.clk">
+        </complete>
+        <complete name="carry_in" input="clb_spypad.cin clb_spypad.cin_trick fle[8:0].out fle_spypad.out" output="fle_spypad.cin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <!--delay_constant max="0.15e-9" in_port="clb.cin clb.cin_trick" out_port="fle[0:0].cin"/-->
+          <pack_pattern name="chain" in_port="clb_spypad.cin" out_port="fle_spypad.cin"/>
+          <!--pack_pattern name="chain" in_port="clb.cin_trick" out_port="fle[0:0].cin"/-->
+        </complete>
+
+        <!--direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
+          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
+        </direct-->
+        <direct name="clbouts1_spyfle" input="fle_spypad.out[0:0]" output="clb_spypad.O[0:0]"/>
+        <direct name="clbouts2_spyfle" input="fle_spypad.out[1:1]" output="clb_spypad.O[10:10]"/>
+        <direct name="clbouts1" input="fle[8:0].out[0:0]" output="clb_spypad.O[9:1]"/>
+        <direct name="clbouts2" input="fle[8:0].out[1:1]" output="clb_spypad.O[19:11]"/>
+        <direct name="cout_copy" input="fle[8:8].cout" output="clb_spypad.cout_copy"/>
+
+        <!-- Shift register links -->
+        <direct name="regin" input="clb_spypad.regin" output="fle_spypad.regin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.15e-9" in_port="clb_spypad.regin" out_port="fle_spypad.regin"/>
+          <pack_pattern name="chain" in_port="clb_spypad.regin" out_port="fle_spypad.regin"/>
+        </direct>
+        <direct name="regout" input="fle[8:8].regout" output="clb_spypad.regout">
+          <pack_pattern name="chain" in_port="fle[8:8].regout" out_port="clb_spypad.regout"/>
+        </direct>
+        <direct name="reg_link_spyfle" input="fle_spypad.regout" output="fle[0:0].regin">
+          <pack_pattern name="chain" in_port="fle_spypad.regout" out_port="fle[0:0].regin"/>
+        </direct>
+        <direct name="reg_link" input="fle[7:0].regout" output="fle[8:1].regin">
+          <pack_pattern name="chain" in_port="fle[7:0].regout" out_port="fle[8:1].regin"/>
+        </direct>
+
+        <!-- Carry chain links -->
+        <direct name="carry_out" input="fle[8:8].cout" output="clb_spypad.cout">
+          <pack_pattern name="chain" in_port="fle[8:8].cout" out_port="clb_spypad.cout"/>
+        </direct>
+        <direct name="carry_link_spyfle" input="fle_spypad.cout" output="fle[0:0].cin">
+          <pack_pattern name="chain" in_port="fle_spypad.cout" out_port="fle[0:0].cin"/>
+        </direct>
+        <direct name="carry_link" input="fle[7:0].cout" output="fle[8:1].cin">
+          <pack_pattern name="chain" in_port="fle[7:0].cout" out_port="fle[8:1].cin"/>
+        </direct>
+
+        <!-- Scan chain links: Do NOT use pack patterns here.
+                               They are testing elements and are NOT dealed by packers -->
+        <direct name="sc_in" input="clb_spypad.sc_in" output="fle_spypad.sc_in">
+        </direct>
+        <direct name="sc_out" input="fle[8:8].sc_out" output="clb_spypad.sc_out">
+        </direct>
+        <direct name="sc_link_spyfle" input="fle_spypad.sc_out" output="fle[0:0].sc_in">
+        </direct>
+        <direct name="sc_link" input="fle[7:0].sc_out" output="fle[8:1].sc_in">
+        </direct>
+      </interconnect>
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+
   </complexblocklist>
 </architecture>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml
new file mode 100644
index 000000000..4939b2dc0
--- /dev/null
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml
@@ -0,0 +1,373 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
+      <design_technology type="cmos" topology="OR"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> 
+        This is flip-flop with scan-chain feature.
+        When the TESTEN is enabled, the data will be propagated form DI instead of D
+      -->
+    <circuit_model type="ff" name="scan_chain_ff" prefix="scan_chain_ff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="D_chain" lib_name="DI" size="1"/>
+       <port type="input" prefix="TESTEN" size="1" is_global="true" default_val="0"/>
+       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
+      <design_technology type="cmos" fracturable_lut="true"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="6" tri_state_map="----11" circuit_model_name="OR2"/>
+      <port type="output" prefix="lut4_out" size="4" lut_frac_level="4" lut_output_mask="0,1,2,3"/>
+      <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
+      <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
+      <port type="sram" prefix="sram" size="64"/>
+      <port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+    </circuit_model>
+    <circuit_model type="lut" name="frac_lut6_spypad" prefix="frac_lut6_spypad" dump_structural_verilog="true">
+      <design_technology type="cmos" fracturable_lut="true"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="6" tri_state_map="----11" circuit_model_name="OR2"/>
+      <port type="output" prefix="lut4_out" size="4" lut_frac_level="4" lut_output_mask="0,1,2,3" is_global="true" is_io="true"/>
+      <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1" is_global="true" is_io="true"/>
+      <port type="output" prefix="lut6_out" size="1" lut_output_mask="0" is_global="true" is_io="true"/>
+      <port type="sram" prefix="sram" size="64"/>
+      <port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="Qb" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+      <port type="input" prefix="outpad" size="1"/>
+      <port type="output" prefix="inpad" size="1"/>
+    </circuit_model>
+    <circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="input" prefix="cin" size="1"/>
+      <port type="output" prefix="sumout" size="1"/>
+      <port type="output" prefix="cout" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <direct_connection>
+    <direct name="adder_carry" circuit_model_name="direct_interc"/>
+    <direct name="scff_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
+  </direct_connection>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/>
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb.fle" physical_mode_name="physical"/>
+    <pb_type name="clb.fle[physical].frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
+    <pb_type name="clb.fle[physical].ff_phy" circuit_model_name="scan_chain_ff"/>
+    <pb_type name="clb.fle[physical].frac_logic.adder_phy" circuit_model_name="adder"/>
+    <!-- Binding operating pb_type to physical pb_type -->
+    <!-- Binding operating pb_types in mode 'n2_lut5' -->
+    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5[blut5].flut5.lut5" physical_pb_type_name="clb.fle[physical].frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5">
+      <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:4]"/>
+      <port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5[blut5].flut5.ff" physical_pb_type_name="clb.fle[physical].ff_phy"/>
+    <!-- Binding operating pb_types in mode 'arithmetic' -->
+    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5[arithmetic].arithmetic.lut4" physical_pb_type_name="clb.fle[physical].frac_logic.frac_lut6" mode_bits="11" physical_pb_type_index_factor="0.25">
+      <!-- Binding the lut4 to the first 4 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:3]"/>
+      <port name="out" physical_mode_port="lut4_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5[arithmetic].arithmetic.adder" physical_pb_type_name="clb.fle[physical].frac_logic.adder_phy"/>
+    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5[arithmetic].arithmetic.ff" physical_pb_type_name="clb.fle[physical].ff_phy"/>
+    <!-- Binding operating pb_types in mode 'ble6' -->
+    <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].frac_logic.frac_lut6" mode_bits="00">
+      <!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:5]"/>
+      <port name="out" physical_mode_port="lut6_out"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].ff_phy" physical_pb_type_index_factor="2" physical_pb_type_index_offset="1"/>
+    <!-- Binding operating pb_types in mode 'shift_register' -->
+    <pb_type name="clb.fle[shift_register].ble_shift.ff" physical_pb_type_name="clb.fle[physical].ff_phy"/>
+    <!-- End physical pb_type binding in complex block CLB -->
+
+    <!-- physical pb_type binding in complex block CLB with spypads-->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb_spypad.fle" physical_mode_name="physical"/>
+
+    <!-- Binding regular FLEs -->
+    <pb_type name="clb_spypad.fle[physical].frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
+    <pb_type name="clb_spypad.fle[physical].ff_phy" circuit_model_name="scan_chain_ff"/>
+    <pb_type name="clb_spypad.fle[physical].frac_logic.adder_phy" circuit_model_name="adder"/>
+    <!-- Binding operating pb_type to physical pb_type -->
+    <!-- Binding operating pb_types in mode 'n2_lut5' -->
+    <pb_type name="clb_spypad.fle[n2_lut5].lut5inter.ble5[blut5].flut5.lut5" physical_pb_type_name="clb_spypad.fle[physical].frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5">
+      <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:4]"/>
+      <port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb_spypad.fle[n2_lut5].lut5inter.ble5[blut5].flut5.ff" physical_pb_type_name="clb_spypad.fle[physical].ff_phy"/>
+    <!-- Binding operating pb_types in mode 'arithmetic' -->
+    <pb_type name="clb_spypad.fle[n2_lut5].lut5inter.ble5[arithmetic].arithmetic.lut4" physical_pb_type_name="clb_spypad.fle[physical].frac_logic.frac_lut6" mode_bits="11" physical_pb_type_index_factor="0.25">
+      <!-- Binding the lut4 to the first 4 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:3]"/>
+      <port name="out" physical_mode_port="lut4_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb_spypad.fle[n2_lut5].lut5inter.ble5[arithmetic].arithmetic.adder" physical_pb_type_name="clb_spypad.fle[physical].frac_logic.adder_phy"/>
+    <pb_type name="clb_spypad.fle[n2_lut5].lut5inter.ble5[arithmetic].arithmetic.ff" physical_pb_type_name="clb_spypad.fle[physical].ff_phy"/>
+    <!-- Binding operating pb_types in mode 'ble6' -->
+    <pb_type name="clb_spypad.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb_spypad.fle[physical].frac_logic.frac_lut6" mode_bits="00">
+      <!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:5]"/>
+      <port name="out" physical_mode_port="lut6_out"/>
+    </pb_type>
+    <pb_type name="clb_spypad.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb_spypad.fle[physical].ff_phy" physical_pb_type_index_factor="2" physical_pb_type_index_offset="1"/>
+    <!-- Binding operating pb_types in mode 'shift_register' -->
+    <pb_type name="clb_spypad.fle[shift_register].ble_shift.ff" physical_pb_type_name="clb_spypad.fle[physical].ff_phy"/>
+
+    <!-- Binding FLE with spy pads -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb_spypad.fle_spypad" physical_mode_name="physical"/>
+
+    <pb_type name="clb_spypad.fle_spypad[physical].frac_logic.frac_lut6" circuit_model_name="frac_lut6_spypad" mode_bits="11"/>
+    <pb_type name="clb_spypad.fle_spypad[physical].ff_phy" circuit_model_name="scan_chain_ff"/>
+    <pb_type name="clb_spypad.fle_spypad[physical].frac_logic.adder_phy" circuit_model_name="adder"/>
+    <!-- Binding operating pb_type to physical pb_type -->
+    <!-- Binding operating pb_types in mode 'n2_lut5' -->
+    <pb_type name="clb_spypad.fle_spypad[n2_lut5].lut5inter.ble5[blut5].flut5.lut5" physical_pb_type_name="clb_spypad.fle_spypad[physical].frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5">
+      <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:4]"/>
+      <port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb_spypad.fle_spypad[n2_lut5].lut5inter.ble5[blut5].flut5.ff" physical_pb_type_name="clb_spypad.fle_spypad[physical].ff_phy"/>
+    <!-- Binding operating pb_types in mode 'arithmetic' -->
+    <pb_type name="clb_spypad.fle_spypad[n2_lut5].lut5inter.ble5[arithmetic].arithmetic.lut4" physical_pb_type_name="clb_spypad.fle_spypad[physical].frac_logic.frac_lut6" mode_bits="11" physical_pb_type_index_factor="0.25">
+      <!-- Binding the lut4 to the first 4 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:3]"/>
+      <port name="out" physical_mode_port="lut4_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb_spypad.fle_spypad[n2_lut5].lut5inter.ble5[arithmetic].arithmetic.adder" physical_pb_type_name="clb_spypad.fle_spypad[physical].frac_logic.adder_phy"/>
+    <pb_type name="clb_spypad.fle_spypad[n2_lut5].lut5inter.ble5[arithmetic].arithmetic.ff" physical_pb_type_name="clb_spypad.fle_spypad[physical].ff_phy"/>
+    <!-- Binding operating pb_types in mode 'ble6' -->
+    <pb_type name="clb_spypad.fle_spypad[n1_lut6].ble6.lut6" physical_pb_type_name="clb_spypad.fle_spypad[physical].frac_logic.frac_lut6" mode_bits="00">
+      <!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:5]"/>
+      <port name="out" physical_mode_port="lut6_out"/>
+    </pb_type>
+    <pb_type name="clb_spypad.fle_spypad[n1_lut6].ble6.ff" physical_pb_type_name="clb_spypad.fle_spypad[physical].ff_phy" physical_pb_type_index_factor="2" physical_pb_type_index_offset="1"/>
+    <!-- Binding operating pb_types in mode 'shift_register' -->
+    <pb_type name="clb_spypad.fle_spypad[shift_register].ble_shift.ff" physical_pb_type_name="clb_spypad.fle_spypad[physical].ff_phy"/>
+    <!-- End physical pb_type binding in complex block CLB with spypads-->
+
+  </pb_type_annotations>
+</openfpga_architecture>
+<openfpga_simulation_setting>
+  <clock_setting>
+    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
+    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
+    <programming frequency="10e6"/>
+  </clock_setting>
+  <simulator_option>
+    <operating_condition temperature="25"/>
+    <output_log verbose="false" captab="false"/>
+    <accuracy type="abs" value="1e-13"/>
+    <runtime fast_simulation="true"/>
+  </simulator_option>
+  <monte_carlo num_simulation_points="2"/>
+  <measurement_setting>
+    <slew>
+      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
+      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
+    </slew>
+    <delay>
+      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
+      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
+    </delay>
+  </measurement_setting>
+  <stimulus>
+    <clock>
+      <rise slew_type="abs" slew_time="20e-12" />
+      <fall slew_type="abs" slew_time="20e-12" />
+    </clock>
+    <input>
+      <rise slew_type="abs" slew_time="25e-12" />
+      <fall slew_type="abs" slew_time="25e-12" />
+    </input>
+  </stimulus>
+</openfpga_simulation_setting>

From 726185cd5ee37eb28a1860091b8e5f50399b7411 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 22 Apr 2020 12:56:57 -0600
Subject: [PATCH 467/645] add test cases using spypad architecture

---
 .../openfpga_shell/spypad/config/task.conf    | 34 +++++++++++++++++++
 1 file changed, 34 insertions(+)
 create mode 100644 openfpga_flow/tasks/openfpga_shell/spypad/config/task.conf

diff --git a/openfpga_flow/tasks/openfpga_shell/spypad/config/task.conf b/openfpga_flow/tasks/openfpga_shell/spypad/config/task.conf
new file mode 100644
index 000000000..e093b2b53
--- /dev/null
+++ b/openfpga_flow/tasks/openfpga_shell/spypad/config/task.conf
@@ -0,0 +1,34 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

From 8ac6e107271f0d153a7c2d5a4fe14d0fe867a385 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 22 Apr 2020 14:41:16 -0600
Subject: [PATCH 468/645] bug fix in lut and mux module generation on
 supporting spypads

---
 .../libarchopenfpga/src/circuit_library.cpp   |  2 +-
 openfpga/src/fabric/build_grid_modules.cpp    | 28 ++++++++++++++++---
 openfpga/src/fabric/build_lut_modules.cpp     |  2 +-
 openfpga/src/fabric/build_mux_modules.cpp     |  4 +--
 openfpga/src/mux_lib/mux_graph.cpp            |  2 +-
 5 files changed, 29 insertions(+), 9 deletions(-)

diff --git a/libopenfpga/libarchopenfpga/src/circuit_library.cpp b/libopenfpga/libarchopenfpga/src/circuit_library.cpp
index cf8b8714f..a235e53af 100644
--- a/libopenfpga/libarchopenfpga/src/circuit_library.cpp
+++ b/libopenfpga/libarchopenfpga/src/circuit_library.cpp
@@ -777,7 +777,7 @@ std::vector<CircuitPortId> CircuitLibrary::model_ports_by_type(const CircuitMode
     if ( type != port_type(port_id) ) {
       continue; 
     }
-    /* We skip global ports if specified */
+    /* We skip global ports if specified. Note: I/O port should be kept */
     if ( (true == ignore_global_port)
       && (true == port_is_global(port_id)) ) {
       continue; 
diff --git a/openfpga/src/fabric/build_grid_modules.cpp b/openfpga/src/fabric/build_grid_modules.cpp
index 0d88bdc81..12090d43d 100644
--- a/openfpga/src/fabric/build_grid_modules.cpp
+++ b/openfpga/src/fabric/build_grid_modules.cpp
@@ -163,16 +163,36 @@ void add_primitive_module_fpga_global_io_port(ModuleManager& module_manager,
   BasicPort logic_io_port = module_manager.module_port(logic_module, logic_io_port_id);
   VTR_ASSERT(logic_io_port.get_width() == module_port.get_width());
 
-  /* Wire the GPIO port form primitive_module to the logic module!*/
+  /* Wire the GPIO port from primitive_module to the logic module!*/
   for (size_t pin_id = 0; pin_id < module_port.pins().size(); ++pin_id) {      
-    ModuleNetId net = module_manager.create_module_net(primitive_module);
     if ( (ModuleManager::MODULE_GPIO_PORT == module_io_port_type)
       || (ModuleManager::MODULE_GPIN_PORT == module_io_port_type) ) {
-      module_manager.add_module_net_source(primitive_module, net, primitive_module, 0, primitive_io_port_id, module_port.pins()[pin_id]);
+      bool net_exist = true;
+      /* If the source port has already a net to drive, we just update the net sinks */
+      ModuleNetId net = module_manager.module_instance_port_net(primitive_module, primitive_module, 0, primitive_io_port_id, module_port.pins()[pin_id]);
+      if (net == ModuleNetId::INVALID()) {
+        net_exist = false;
+        net = module_manager.create_module_net(primitive_module);
+      }
+
+      if (false == net_exist) {
+        module_manager.add_module_net_source(primitive_module, net, primitive_module, 0, primitive_io_port_id, module_port.pins()[pin_id]);
+      }
       module_manager.add_module_net_sink(primitive_module, net, logic_module, logic_instance_id, logic_io_port_id, logic_io_port.pins()[pin_id]);
     } else {
+      bool net_exist = true;
+      /* If the source port has already a net to drive, we just update the net sinks */
+      ModuleNetId net = module_manager.module_instance_port_net(primitive_module, logic_module, logic_instance_id, logic_io_port_id, logic_io_port.pins()[pin_id]);
+      if (net == ModuleNetId::INVALID()) {
+        net_exist = false;
+        net = module_manager.create_module_net(primitive_module);
+      }
+
       VTR_ASSERT(ModuleManager::MODULE_GPOUT_PORT == module_io_port_type);
-      module_manager.add_module_net_source(primitive_module, net, logic_module, logic_instance_id, logic_io_port_id, logic_io_port.pins()[pin_id]);
+
+      if (false == net_exist) {
+        module_manager.add_module_net_source(primitive_module, net, logic_module, logic_instance_id, logic_io_port_id, logic_io_port.pins()[pin_id]);
+      }
       module_manager.add_module_net_sink(primitive_module, net, primitive_module, 0, primitive_io_port_id, module_port.pins()[pin_id]);
     }
   }
diff --git a/openfpga/src/fabric/build_lut_modules.cpp b/openfpga/src/fabric/build_lut_modules.cpp
index 184de6698..2ba688e4d 100644
--- a/openfpga/src/fabric/build_lut_modules.cpp
+++ b/openfpga/src/fabric/build_lut_modules.cpp
@@ -45,7 +45,7 @@ void build_lut_module(ModuleManager& module_manager,
   /* Get the input ports from the mux */
   std::vector<CircuitPortId> lut_input_ports = circuit_lib.model_ports_by_type(lut_model, CIRCUIT_MODEL_PORT_INPUT, true);
   /* Get the output ports from the mux */
-  std::vector<CircuitPortId> lut_output_ports = circuit_lib.model_ports_by_type(lut_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
+  std::vector<CircuitPortId> lut_output_ports = circuit_lib.model_ports_by_type(lut_model, CIRCUIT_MODEL_PORT_OUTPUT, false);
 
   /* Classify SRAM ports into two categories: regular (not for mode select) and mode-select */
   std::vector<CircuitPortId> lut_regular_sram_ports = find_circuit_regular_sram_ports(circuit_lib, lut_model);
diff --git a/openfpga/src/fabric/build_mux_modules.cpp b/openfpga/src/fabric/build_mux_modules.cpp
index 41cb68118..a28eac264 100644
--- a/openfpga/src/fabric/build_mux_modules.cpp
+++ b/openfpga/src/fabric/build_mux_modules.cpp
@@ -849,7 +849,7 @@ vtr::vector<MuxOutputId, ModuleNetId> build_mux_module_output_buffers(ModuleMana
   vtr::vector<MuxOutputId, ModuleNetId> mux_output_nets(mux_graph.num_outputs(), ModuleNetId::INVALID());
 
   /* Get the output ports from the mux */
-  std::vector<CircuitPortId> mux_output_ports = circuit_lib.model_ports_by_type(mux_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
+  std::vector<CircuitPortId> mux_output_ports = circuit_lib.model_ports_by_type(mux_model, CIRCUIT_MODEL_PORT_OUTPUT, false);
 
   /* Iterate over all the outputs in the MUX module */
   for (const auto& output_port : mux_output_ports) {
@@ -1098,7 +1098,7 @@ void build_cmos_mux_module(ModuleManager& module_manager,
   /* Get the input ports from the mux */
   std::vector<CircuitPortId> mux_input_ports = circuit_lib.model_ports_by_type(mux_model, CIRCUIT_MODEL_PORT_INPUT, true);
   /* Get the output ports from the mux */
-  std::vector<CircuitPortId> mux_output_ports = circuit_lib.model_ports_by_type(mux_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
+  std::vector<CircuitPortId> mux_output_ports = circuit_lib.model_ports_by_type(mux_model, CIRCUIT_MODEL_PORT_OUTPUT, false);
   /* Get the sram ports from the mux 
    * Multiplexing structure does not mode_sram_ports, they are handled in LUT modules
    * Here we just bypass it.
diff --git a/openfpga/src/mux_lib/mux_graph.cpp b/openfpga/src/mux_lib/mux_graph.cpp
index 5b0f81828..d8066c055 100644
--- a/openfpga/src/mux_lib/mux_graph.cpp
+++ b/openfpga/src/mux_lib/mux_graph.cpp
@@ -1001,7 +1001,7 @@ void MuxGraph::build_onelevel_mux_graph(const size_t& mux_size,
 void MuxGraph::add_fracturable_outputs(const CircuitLibrary& circuit_lib, 
                                        const CircuitModelId& circuit_model) {
   /* Iterate over output ports */
-  for (const auto& port : circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true)) {
+  for (const auto& port : circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, false)) {
     /* Get the fracturable_level */
     size_t frac_level = circuit_lib.port_lut_frac_level(port);
     /* Bypass invalid frac_level */

From 341f38025ee12c86fec5f1557444f72db25ece8d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 22 Apr 2020 14:42:30 -0600
Subject: [PATCH 469/645] add spypad to regression test

---
 .travis/script.sh | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/.travis/script.sh b/.travis/script.sh
index fd9b8616e..231437e28 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -102,4 +102,7 @@ python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/flatten_routing --
 echo -e "Testing Verilog generation with duplicated grid output pins";
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/duplicated_grid_pin --debug --show_thread_logs
 
+echo -e "Testing Verilog generation with spy output pads";
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/spypad --debug --show_thread_logs
+
 end_section "OpenFPGA.TaskTun"

From bf841b9a8e2b4711685709d251943a1b235db87d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 22 Apr 2020 17:28:16 -0600
Subject: [PATCH 470/645] bug fixed in identifying wired LUT

---
 openfpga/src/utils/physical_pb_utils.cpp | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/openfpga/src/utils/physical_pb_utils.cpp b/openfpga/src/utils/physical_pb_utils.cpp
index cd1b13a4b..129784575 100644
--- a/openfpga/src/utils/physical_pb_utils.cpp
+++ b/openfpga/src/utils/physical_pb_utils.cpp
@@ -324,6 +324,12 @@ void rec_update_physical_pb_from_operating_pb(PhysicalPb& phy_pb,
         /* The following code is inspired by output_cluster.cpp */
         bool is_used = false;
         t_pb_type* child_pb_type = &(mapped_mode->pb_type_children[ipb]);
+           
+        /* Bypass non-primitive pb_type, we care only the LUT pb_type */
+        if (false == is_primitive_pb_type(child_pb_type)) {
+          continue;
+        }
+
         int port_index = 0;
         t_pb_graph_node* child_pb_graph_node = &(pb_graph_node->child_pb_graph_nodes[op_pb->mode][ipb][jpb]);
 

From 0c4904065f13b93d0d0959f5af510df7e494ea3c Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 22 Apr 2020 17:36:02 -0600
Subject: [PATCH 471/645] reduce activity error to warning.

---
 vpr/src/base/read_activity.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/vpr/src/base/read_activity.cpp b/vpr/src/base/read_activity.cpp
index 41cc86a21..821fc4672 100644
--- a/vpr/src/base/read_activity.cpp
+++ b/vpr/src/base/read_activity.cpp
@@ -19,8 +19,8 @@ static bool add_activity_to_net(const AtomNetlist& netlist, std::unordered_map<A
         return false;
     }
 
-    VTR_LOG(
-        "Error: net %s found in activity file, but it does not exist in the .blif file.\n",
+    VTR_LOG_WARN(
+        "net %s found in activity file, but it does not exist in the .blif file.\n",
         net_name);
     return true;
 }

From f9fcc6b471e44e11951ee15692ff333a8f8d81fc Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 22 Apr 2020 18:24:09 -0600
Subject: [PATCH 472/645] tweak mcnc scripts by stop VRP to remove buffers. Now
 passed mcnc big20 in Verilog/Bitstream generation

---
 .../mcnc_example_script.openfpga              | 61 +++++++++++++++++++
 .../mcnc_big20/config/task.conf               | 47 +++++++-------
 2 files changed, 86 insertions(+), 22 deletions(-)
 create mode 100644 openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga

diff --git a/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga
new file mode 100644
index 000000000..cfe061298
--- /dev/null
+++ b/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga
@@ -0,0 +1,61 @@
+# Run VPR for the 'and' design
+#--write_rr_graph example_rr_graph.xml
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --absorb_buffer_luts off
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
+
+# Annotate the OpenFPGA architecture to VPR data base
+# to debug use --verbose options
+link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to clustering nets based on routing results
+pb_pin_fixup --verbose
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup
+
+# Build the module graph
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules
+build_fabric --compress_routing #--verbose
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --file fabric_indepenent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here
+write_pnr_sdc --file ./SDC
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+write_analysis_sdc --file ./SDC_analysis
+
+# Finish and exit OpenFPGA
+exit
+
+# Note :
+# To run verification at the end of the flow maintain source in ./SRC directory
diff --git a/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf b/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf
index bab48c1fd..f2a92e6b9 100644
--- a/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf
@@ -8,7 +8,7 @@
 
 [GENERAL]
 run_engine=openfpga_shell
-openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga
 power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
 power_analysis = true
 spice_output=false
@@ -21,27 +21,30 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml
 
 [BENCHMARKS]
-#bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif 
-#bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif
-#bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.blif
-## VPR remove dangling PIs and POs which are in act file. Then VPR errors out by saying these PI/PO should not exist in act file
-##bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.blif
-#bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.blif
-#bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.blif
-#bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.blif
-#bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.blif
-#bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.blif
-#bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.blif
-#bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.blif
-#bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.blif
-#bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.blif
-#bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.blif
-bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.blif 
-#bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.blif 
-#bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.blif
-#bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.blif
-#bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.blif
-#bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif 
+bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif
+bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.blif
+# VPR remove buffers which are in act file and create a new net. Then VPR errors out by saying the new net does not exist in act file
+bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.blif
+# VPR remove buffers which are in act file and create a new net. Then VPR errors out by saying the new net does not exist in act file
+bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.blif
+bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.blif
+bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.blif
+# VPR remove buffers which are in act file and create a new net. Then VPR errors out by saying the new net does not exist in act file
+bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.blif
+bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.blif
+bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.blif
+bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.blif
+bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.blif
+bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.blif
+bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.blif
+# Passed
+#bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.blif 
+bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.blif 
+bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.blif
+bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.blif
+bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.blif
+bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.blif
 
 [SYNTHESIS_PARAM]
 # Benchmark alu4 

From df85175765159dc0f09def946bb7243e0de2e08a Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 22 Apr 2020 21:44:52 -0600
Subject: [PATCH 473/645] fine tuning on mcnc example script so that we can run
 run_modelsim.py --runsim

---
 openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga
index cfe061298..66b4c12fa 100644
--- a/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga
@@ -45,7 +45,7 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --inc
 #  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini
+write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./simulation_deck_info.ini
 
 # Write the SDC files for PnR backend
 #  - Turn on every options here

From 417d534121197ca93b05d21a421062bf88855aac Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 23 Apr 2020 16:15:45 -0600
Subject: [PATCH 474/645] fine tune mcnc example script to run Modelsim
 simulations easily

---
 .../OpenFPGAShellScripts/mcnc_example_script.openfpga       | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga
index 66b4c12fa..9a4f577f8 100644
--- a/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga
@@ -37,7 +37,11 @@ build_fabric_bitstream --verbose
 
 # Write the Verilog netlist for FPGA fabric
 #  - Enable the use of explicit port mapping in Verilog netlist
-write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
+write_fabric_verilog --file ./SRC \
+  --explicit_port_mapping \
+  --include_timing \
+  --include_signal_init 
+  #--support_icarus_simulator 
 
 # Write the Verilog testbench for FPGA fabric
 #  - We suggest the use of same output directory as fabric Verilog netlists

From 90f608baeaac8420bc091aba9d1e763ea255e357 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 23 Apr 2020 18:58:39 -0600
Subject: [PATCH 475/645] changing task mcnc file for debugging (temporarily
 now) Will be corrected later

---
 .../mcnc_big20/config/task.conf               | 48 +++++++++----------
 1 file changed, 24 insertions(+), 24 deletions(-)

diff --git a/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf b/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf
index f2a92e6b9..5028283fb 100644
--- a/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf
@@ -21,30 +21,30 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif 
-bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif
-bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.blif
-# VPR remove buffers which are in act file and create a new net. Then VPR errors out by saying the new net does not exist in act file
-bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.blif
-# VPR remove buffers which are in act file and create a new net. Then VPR errors out by saying the new net does not exist in act file
-bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.blif
-bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.blif
-bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.blif
-# VPR remove buffers which are in act file and create a new net. Then VPR errors out by saying the new net does not exist in act file
-bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.blif
-bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.blif
-bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.blif
-bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.blif
-bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.blif
-bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.blif
-bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.blif
-# Passed
-#bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.blif 
-bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.blif 
-bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.blif
-bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.blif
-bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.blif
-bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.blif
+#bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif 
+#bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif
+#bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.blif
+## VPR remove buffers which are in act file and create a new net. Then VPR errors out by saying the new net does not exist in act file
+#bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.blif
+## VPR remove buffers which are in act file and create a new net. Then VPR errors out by saying the new net does not exist in act file
+#bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.blif
+#bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.blif
+#bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.blif
+## VPR remove buffers which are in act file and create a new net. Then VPR errors out by saying the new net does not exist in act file
+#bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.blif
+#bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.blif
+#bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.blif
+#bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.blif
+#bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.blif
+#bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.blif
+#bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.blif
+## Passed
+bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.blif 
+#bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.blif 
+#bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.blif
+#bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.blif
+#bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.blif
+#bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.blif
 
 [SYNTHESIS_PARAM]
 # Benchmark alu4 

From 87b17fc25f2944012d85e1d0da18cfd54488e056 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 23 Apr 2020 18:59:09 -0600
Subject: [PATCH 476/645] add netlist manager data structure

---
 openfpga/src/base/netlist_manager.cpp   | 201 ++++++++++++++++++++++++
 openfpga/src/base/netlist_manager.h     | 107 +++++++++++++
 openfpga/src/base/netlist_manager_fwd.h |  25 +++
 3 files changed, 333 insertions(+)
 create mode 100644 openfpga/src/base/netlist_manager.cpp
 create mode 100644 openfpga/src/base/netlist_manager.h
 create mode 100644 openfpga/src/base/netlist_manager_fwd.h

diff --git a/openfpga/src/base/netlist_manager.cpp b/openfpga/src/base/netlist_manager.cpp
new file mode 100644
index 000000000..b7860d14f
--- /dev/null
+++ b/openfpga/src/base/netlist_manager.cpp
@@ -0,0 +1,201 @@
+/******************************************************************************
+ * This files includes memeber functions for data structure NetlistManager
+ ******************************************************************************/
+#include <algorithm>
+
+#include "vtr_assert.h"
+#include "netlist_manager.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/******************************************************************************
+ * Public aggregators
+ ******************************************************************************/
+/* Find all the netlists */
+NetlistManager::netlist_range NetlistManager::netlists() const {
+  return vtr::make_range(netlist_ids_.begin(), netlist_ids_.end());
+}
+
+/* Find all the modules that are included in a netlist */
+std::vector<ModuleId> NetlistManager::netlist_modules(const NetlistId& netlist) const {
+  VTR_ASSERT(true == valid_netlist_id(netlist));
+  return included_module_ids_[netlist];
+}
+
+
+/******************************************************************************
+ * Public accessors
+ ******************************************************************************/
+/* Find the name of a netlist */
+std::string NetlistManager::netlist_name(const NetlistId& netlist) const {
+  VTR_ASSERT(true == valid_netlist_id(netlist));
+  return netlist_names_[netlist];
+}
+
+/* Find a netlist by its name */
+NetlistId NetlistManager::find_netlist(const std::string& netlist_name) const {
+  if (name_id_map_.find(netlist_name) != name_id_map_.end()) {
+    /* Found, return the id */
+    return name_id_map_.at(netlist_name);
+  } 
+  /* Not found, return an invalid id */
+  return NetlistId::INVALID();
+}
+
+NetlistManager::e_netlist_type NetlistManager::netlist_type(const NetlistId& netlist) const {
+  VTR_ASSERT(true == valid_netlist_id(netlist));
+  return netlist_types_[netlist];
+}
+
+/* Find if a module belongs to a netlist */
+bool NetlistManager::is_module_in_netlist(const NetlistId& netlist, const ModuleId& module) const {
+  VTR_ASSERT(true == valid_netlist_id(netlist));
+
+  for (const ModuleId& included_module : included_module_ids_[netlist]) {
+    /* Already in the netlist, return true */
+    if (module == included_module) {
+      return true;  
+    }
+  }
+ 
+  /* Not in the netlist, return false */
+  return false;
+}
+
+/* Find the netlist that a module belongs to */
+NetlistId NetlistManager::find_module_netlist(const ModuleId& module) const {
+  /* Find if the module has been added to a netlist. If used, return false! */
+  /* Not found, return an invalid value */
+  if ( module_netlist_map_.end()
+    != module_netlist_map_.find(module)) {
+    return NetlistId::INVALID();
+  }
+  return module_netlist_map_.at(module);
+}
+
+
+/* Find all the preprocessing flags that are included in a netlist */
+std::vector<std::string> NetlistManager::netlist_preprocessing_flags(const NetlistId& netlist) const {
+  VTR_ASSERT(true == valid_netlist_id(netlist));
+
+  std::vector<std::string> flags; 
+
+  for (const PreprocessingFlagId& flag_id : included_preprocessing_flag_ids_[netlist]) {
+    VTR_ASSERT(true == valid_preprocessing_flag_id(flag_id));
+    flags.push_back(preprocessing_flag_names_[flag_id]);
+  }
+
+  return flags;
+}
+
+/******************************************************************************
+ * Public mutators
+ ******************************************************************************/
+/* Add a netlist to the library */
+NetlistId NetlistManager::add_netlist(const std::string& name) {
+  /* Find if the name has been used. If used, return an invalid Id! */
+  std::map<std::string, NetlistId>::iterator it = name_id_map_.find(name);
+  if (it !=  name_id_map_.end()) {
+    return NetlistId::INVALID();
+  }
+
+  /* Create a new id */
+  NetlistId netlist = NetlistId(netlist_ids_.size());
+  netlist_ids_.push_back(netlist);
+
+  /* Allocate related attributes */
+  netlist_names_.push_back(name);
+  netlist_types_.push_back(NUM_NETLIST_TYPES);
+  included_module_ids_.emplace_back();
+  included_preprocessing_flag_ids_.emplace_back();
+
+  /* Register in the name-to-id map */
+  name_id_map_[name] = netlist;  
+
+  return netlist;
+} 
+
+void NetlistManager::set_netlist_type(const NetlistId& netlist,
+                                      const e_netlist_type& type) {
+  VTR_ASSERT(true == valid_netlist_id(netlist));
+  netlist_types_[netlist] = type;
+}
+
+/* Add a module to a netlist in the library */
+bool NetlistManager::add_netlist_module(const NetlistId& netlist, const ModuleId& module) {
+  VTR_ASSERT(true == valid_netlist_id(netlist));
+
+  /* Find if the module already in the netlist */
+  std::vector<ModuleId>::iterator module_it = std::find(included_module_ids_[netlist].begin(), included_module_ids_[netlist].end(), module);
+  if (module_it != included_module_ids_[netlist].end()) {
+    /* Already in the netlist, nothing to do */
+    return true;
+  }
+  /* Try to register it in module-to-netlist map */
+  /* Find if the module has been added to a netlist. If used, return false! */
+  std::map<ModuleId, NetlistId>::iterator map_it = module_netlist_map_.find(module);
+  if (map_it != module_netlist_map_.end()) {
+    return false;
+  }
+
+  /* Does not exist! Should add it to the list */
+  included_module_ids_[netlist].push_back(module);
+  /* Register it in module-to-netlist map */
+  module_netlist_map_[module] = netlist;
+  return true;
+}
+
+/* Add a pre-processing flag to a netlist */
+void NetlistManager::add_netlist_preprocessing_flag(const NetlistId& netlist, const std::string& preprocessing_flag) {
+  VTR_ASSERT(true == valid_netlist_id(netlist));
+
+  PreprocessingFlagId flag = PreprocessingFlagId(preprocessing_flag_ids_.size());
+ 
+  /* Find if the module already in the netlist */
+  for (const PreprocessingFlagId& id : preprocessing_flag_ids_) {
+    if (0 != preprocessing_flag.compare(preprocessing_flag_names_[id])) {
+      continue;
+    }
+    /* Already in the list of pre-processing flags, push it ot the  */
+    flag = id;
+    break;
+  }
+
+  /* Update the list if we need */
+  if (flag == PreprocessingFlagId(preprocessing_flag_ids_.size())) {
+    preprocessing_flag_ids_.push_back(flag);
+    preprocessing_flag_names_.push_back(preprocessing_flag);
+  }
+
+  /* Check if the flag is already in the netlist */
+  std::vector<PreprocessingFlagId>::iterator it = std::find(included_preprocessing_flag_ids_[netlist].begin(), included_preprocessing_flag_ids_[netlist].end(), flag);
+  if (it == included_preprocessing_flag_ids_[netlist].end()) {
+    /* Not in the list, we add it */
+    included_preprocessing_flag_ids_[netlist].push_back(flag);
+  }
+}
+
+/******************************************************************************
+ * Public validators/invalidators
+ ******************************************************************************/
+bool NetlistManager::valid_netlist_id(const NetlistId& netlist) const {
+  return (size_t(netlist) < netlist_ids_.size()) && (netlist == netlist_ids_[netlist]);
+}
+
+/******************************************************************************
+ * Private validators/invalidators
+ ******************************************************************************/
+bool NetlistManager::valid_preprocessing_flag_id(const PreprocessingFlagId& flag) const {
+  return (size_t(flag) < preprocessing_flag_ids_.size()) && (flag == preprocessing_flag_ids_[flag]);
+}
+
+void NetlistManager::invalidate_name2id_map() {
+  name_id_map_.clear();
+}
+
+void NetlistManager::invalidate_module2netlist_map() {
+  module_netlist_map_.clear();
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/base/netlist_manager.h b/openfpga/src/base/netlist_manager.h
new file mode 100644
index 000000000..fad76d25a
--- /dev/null
+++ b/openfpga/src/base/netlist_manager.h
@@ -0,0 +1,107 @@
+/******************************************************************************
+ * This files includes data structures for netlist management.
+ * It keeps a list of netlists that have been created
+ * Each netlist includes a list of ids of modules that are stored in ModuleManager
+ *
+ * When we want to dump out a netlist in Verilog/SPICE format,
+ * the netlist manager can generate the dependency on other netlists 
+ * This can help us tracking the dependency and generate `include` files easily
+ *
+ * Cross-reference:
+ *
+ *   +---------+               +---------+      
+ *   |         |   ModuleId    |         |
+ *   | Netlist |-------------->| Module  |
+ *   | Manager |               | Manager |
+ *   |         |               |         |
+ *   +---------+               +---------+
+ *   
+ ******************************************************************************/
+#ifndef NETLIST_MANAGER_H
+#define NETLIST_MANAGER_H
+
+#include <string>
+#include <vector>
+#include <map>
+#include "vtr_vector.h"
+#include "netlist_manager_fwd.h"
+#include "module_manager.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+class NetlistManager {
+  public: /* Internal Types */
+    /* Type of netlists */ 
+    enum e_netlist_type {
+      SUBMODULE_NETLIST,
+      LOGIC_BLOCK_NETLIST,
+      ROUTING_MODULE_NETLIST,
+      TOP_MODULE_NETLIST,
+      TESTBENCH_NETLIST,
+      NUM_NETLIST_TYPES
+    };
+  public: /* Types and ranges */
+    typedef vtr::vector<NetlistId, NetlistId>::const_iterator netlist_iterator;
+    typedef vtr::Range<netlist_iterator> netlist_range;
+
+  public: /* Public aggregators */
+    /* Find all the netlists */
+    netlist_range netlists() const;
+    /* Find all the modules that are included in a netlist */
+    std::vector<ModuleId> netlist_modules(const NetlistId& netlist) const;
+    /* Find all the preprocessing flags that are included in a netlist */
+    std::vector<std::string> netlist_preprocessing_flags(const NetlistId& netlist) const;
+
+  public: /* Public accessors */
+    /* Find the name of a netlist */
+    std::string netlist_name(const NetlistId& netlist) const;
+    /* Find a netlist by its name */
+    NetlistId find_netlist(const std::string& netlist_name) const;
+    /* Get the type of a netlist */
+    e_netlist_type netlist_type(const NetlistId& netlist) const;
+    /* Find if a module belongs to a netlist */
+    bool is_module_in_netlist(const NetlistId& netlist, const ModuleId& module) const;
+    /* Find the netlist that a module belongs to */
+    NetlistId find_module_netlist(const ModuleId& module) const;
+
+  public: /* Public mutators */
+    /* Add a netlist to the library */
+    NetlistId add_netlist(const std::string& name);
+    /* Set a netlist type */
+    void set_netlist_type(const NetlistId& netlist,
+                          const e_netlist_type& type);
+    /* Add a module to a netlist in the library */
+    bool add_netlist_module(const NetlistId& netlist, const ModuleId& module);
+    /* Add a pre-processing flag to a netlist */
+    void add_netlist_preprocessing_flag(const NetlistId& netlist, const std::string& preprocessing_flag);
+
+  public: /* Public validators/invalidators */
+    bool valid_netlist_id(const NetlistId& netlist) const;
+
+  private: /* Private validators/invalidators */
+    bool valid_preprocessing_flag_id(const PreprocessingFlagId& flag) const;
+    void invalidate_name2id_map();
+    void invalidate_module2netlist_map();
+
+  private: /* Internal data */
+    vtr::vector<NetlistId, NetlistId> netlist_ids_;
+    vtr::vector<NetlistId, std::string> netlist_names_;
+    vtr::vector<NetlistId, e_netlist_type> netlist_types_;
+
+    vtr::vector<NetlistId, std::vector<ModuleId>> included_module_ids_;
+    vtr::vector<NetlistId, std::vector<PreprocessingFlagId>> included_preprocessing_flag_ids_;
+
+    vtr::vector<PreprocessingFlagId, PreprocessingFlagId> preprocessing_flag_ids_;
+    vtr::vector<PreprocessingFlagId, std::string> preprocessing_flag_names_;
+
+    /* fast look-up for netlist */
+    std::map<std::string, NetlistId> name_id_map_;
+    /* fast look-up for modules in netlists */
+    std::map<ModuleId, NetlistId> module_netlist_map_;
+};
+
+} /* end namespace openfpga */
+
+#endif
+
diff --git a/openfpga/src/base/netlist_manager_fwd.h b/openfpga/src/base/netlist_manager_fwd.h
new file mode 100644
index 000000000..186e1792c
--- /dev/null
+++ b/openfpga/src/base/netlist_manager_fwd.h
@@ -0,0 +1,25 @@
+/**************************************************
+ * This file includes only declarations for 
+ * the data structures for netlist managers
+ * Please refer to netlist_manager.h for more details
+ *************************************************/
+#ifndef NETLIST_MANAGER_FWD_H
+#define NETLIST_MANAGER_FWD_H
+
+#include "vtr_strong_id.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/* Strong Ids for ModuleManager */
+struct netlist_id_tag;
+struct preprocessing_flag_id_tag;
+
+typedef vtr::StrongId<netlist_id_tag> NetlistId;
+typedef vtr::StrongId<preprocessing_flag_id_tag> PreprocessingFlagId;
+
+class NetlistManager;
+
+} /* end namespace openfpga */
+
+#endif 

From e811f8bb211c9d7c7420b411df1120942738a6db Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 23 Apr 2020 20:42:11 -0600
Subject: [PATCH 477/645] plug in netlist manager and now the include_netlist
 appears in one unique file

---
 openfpga/src/base/netlist_manager.cpp         | 11 +++++
 openfpga/src/base/netlist_manager.h           |  2 +
 openfpga/src/base/openfpga_context.h          |  8 +++
 openfpga/src/base/openfpga_verilog.cpp        |  4 +-
 openfpga/src/fpga_verilog/verilog_api.cpp     | 22 ++++++---
 openfpga/src/fpga_verilog/verilog_api.h       |  5 +-
 .../verilog_auxiliary_netlists.cpp            | 24 +++++++--
 .../fpga_verilog/verilog_auxiliary_netlists.h |  4 +-
 .../src/fpga_verilog/verilog_decoders.cpp     |  6 ++-
 openfpga/src/fpga_verilog/verilog_decoders.h  |  3 +-
 .../fpga_verilog/verilog_essential_gates.cpp  |  6 ++-
 .../fpga_verilog/verilog_essential_gates.h    |  4 +-
 openfpga/src/fpga_verilog/verilog_grid.cpp    | 30 ++++++++----
 openfpga/src/fpga_verilog/verilog_grid.h      |  4 +-
 openfpga/src/fpga_verilog/verilog_lut.cpp     |  6 ++-
 openfpga/src/fpga_verilog/verilog_lut.h       |  3 +-
 openfpga/src/fpga_verilog/verilog_memory.cpp  |  6 ++-
 openfpga/src/fpga_verilog/verilog_memory.h    |  3 +-
 openfpga/src/fpga_verilog/verilog_mux.cpp     |  6 ++-
 openfpga/src/fpga_verilog/verilog_mux.h       |  3 +-
 openfpga/src/fpga_verilog/verilog_routing.cpp | 49 ++++++++++++-------
 openfpga/src/fpga_verilog/verilog_routing.h   |  7 ++-
 .../src/fpga_verilog/verilog_submodule.cpp    | 21 ++++----
 openfpga/src/fpga_verilog/verilog_submodule.h |  2 +
 .../src/fpga_verilog/verilog_top_module.cpp   |  8 ++-
 .../src/fpga_verilog/verilog_top_module.h     |  4 +-
 openfpga/src/fpga_verilog/verilog_wire.cpp    |  6 ++-
 openfpga/src/fpga_verilog/verilog_wire.h      |  3 +-
 28 files changed, 184 insertions(+), 76 deletions(-)

diff --git a/openfpga/src/base/netlist_manager.cpp b/openfpga/src/base/netlist_manager.cpp
index b7860d14f..0b2e6ec45 100644
--- a/openfpga/src/base/netlist_manager.cpp
+++ b/openfpga/src/base/netlist_manager.cpp
@@ -74,6 +74,17 @@ NetlistId NetlistManager::find_module_netlist(const ModuleId& module) const {
   return module_netlist_map_.at(module);
 }
 
+std::vector<NetlistId> NetlistManager::netlists_by_type(const NetlistManager::e_netlist_type& netlist_type) const {
+  std::vector<NetlistId> nlists;
+
+  for (const NetlistId& nlist_id : netlist_ids_) {
+    if (netlist_type == netlist_types_[nlist_id]) {
+      nlists.push_back(nlist_id);
+    }
+  }
+
+  return nlists;
+}
 
 /* Find all the preprocessing flags that are included in a netlist */
 std::vector<std::string> NetlistManager::netlist_preprocessing_flags(const NetlistId& netlist) const {
diff --git a/openfpga/src/base/netlist_manager.h b/openfpga/src/base/netlist_manager.h
index fad76d25a..df2283e77 100644
--- a/openfpga/src/base/netlist_manager.h
+++ b/openfpga/src/base/netlist_manager.h
@@ -58,6 +58,8 @@ class NetlistManager {
     std::string netlist_name(const NetlistId& netlist) const;
     /* Find a netlist by its name */
     NetlistId find_netlist(const std::string& netlist_name) const;
+    /* Find all the netlist in a given type */
+    std::vector<NetlistId> netlists_by_type(const e_netlist_type& netlist_type) const;
     /* Get the type of a netlist */
     e_netlist_type netlist_type(const NetlistId& netlist) const;
     /* Find if a module belongs to a netlist */
diff --git a/openfpga/src/base/openfpga_context.h b/openfpga/src/base/openfpga_context.h
index d4320915f..2ea114410 100644
--- a/openfpga/src/base/openfpga_context.h
+++ b/openfpga/src/base/openfpga_context.h
@@ -12,6 +12,7 @@
 #include "mux_library.h"
 #include "tile_direct.h"
 #include "module_manager.h"
+#include "netlist_manager.h"
 #include "openfpga_flow_manager.h"
 #include "bitstream_manager.h"
 #include "device_rr_gsb.h"
@@ -61,6 +62,7 @@ class OpenfpgaContext : public Context  {
     const std::vector<openfpga::ConfigBitId>& fabric_bitstream() const { return fabric_bitstream_; }
     const openfpga::IoLocationMap& io_location_map() const { return io_location_map_; }
     const std::unordered_map<AtomNetId, t_net_power>& net_activity() const { return net_activity_; }
+    const openfpga::NetlistManager& verilog_netlists() const { return verilog_netlists_; }
   public:  /* Public mutators */
     openfpga::Arch& mutable_arch() { return arch_; }
     openfpga::VprDeviceAnnotation& mutable_vpr_device_annotation() { return vpr_device_annotation_; }
@@ -77,6 +79,7 @@ class OpenfpgaContext : public Context  {
     std::vector<openfpga::ConfigBitId>& mutable_fabric_bitstream() { return fabric_bitstream_; }
     openfpga::IoLocationMap& mutable_io_location_map() { return io_location_map_; }
     std::unordered_map<AtomNetId, t_net_power>& mutable_net_activity() { return net_activity_; }
+    openfpga::NetlistManager& mutable_verilog_netlists() { return verilog_netlists_; }
   private: /* Internal data */
     /* Data structure to store information from read_openfpga_arch library */
     openfpga::Arch arch_;
@@ -113,6 +116,11 @@ class OpenfpgaContext : public Context  {
     openfpga::BitstreamManager bitstream_manager_;
     std::vector<openfpga::ConfigBitId> fabric_bitstream_;
 
+    /* Netlist database 
+     * TODO: Each format should have an independent entry
+     */
+    openfpga::NetlistManager verilog_netlists_;
+
     /* Net activities of users' implementation */
     std::unordered_map<AtomNetId, t_net_power> net_activity_; 
  
diff --git a/openfpga/src/base/openfpga_verilog.cpp b/openfpga/src/base/openfpga_verilog.cpp
index c79b68fc2..9a877c9f2 100644
--- a/openfpga/src/base/openfpga_verilog.cpp
+++ b/openfpga/src/base/openfpga_verilog.cpp
@@ -45,6 +45,7 @@ int write_fabric_verilog(OpenfpgaContext& openfpga_ctx,
   options.set_compress_routing(openfpga_ctx.flow_manager().compress_routing());
   
   fpga_fabric_verilog(openfpga_ctx.mutable_module_graph(),
+                      openfpga_ctx.mutable_verilog_netlists(),
                       openfpga_ctx.arch().circuit_lib,
                       openfpga_ctx.mux_lib(),
                       g_vpr_ctx.device(),
@@ -82,7 +83,8 @@ int write_verilog_testbench(OpenfpgaContext& openfpga_ctx,
   options.set_print_simulation_ini(cmd_context.option_value(cmd, opt_print_simulation_ini));
   options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
   
-  fpga_verilog_testbench(openfpga_ctx.module_graph(),
+  fpga_verilog_testbench(openfpga_ctx.verilog_netlists(),
+                         openfpga_ctx.module_graph(),
                          openfpga_ctx.bitstream_manager(),
                          openfpga_ctx.fabric_bitstream(),
                          g_vpr_ctx.atom(),
diff --git a/openfpga/src/fpga_verilog/verilog_api.cpp b/openfpga/src/fpga_verilog/verilog_api.cpp
index c37b68888..d2823df48 100644
--- a/openfpga/src/fpga_verilog/verilog_api.cpp
+++ b/openfpga/src/fpga_verilog/verilog_api.cpp
@@ -51,6 +51,7 @@ namespace openfpga {
  * We should think clearly about how to handle them for both Verilog and SPICE generators!
  ********************************************************************/
 void fpga_fabric_verilog(ModuleManager& module_manager,
+                         NetlistManager& netlist_manager,
                          const CircuitLibrary& circuit_lib,
                          const MuxLibrary& mux_lib,
                          const DeviceContext& device_ctx, 
@@ -88,33 +89,38 @@ void fpga_fabric_verilog(ModuleManager& module_manager,
    * the module manager.
    * Without the modules in the module manager, core logic generation is not possible!!!
    */
-  print_verilog_submodule(module_manager, mux_lib, circuit_lib,
+  print_verilog_submodule(module_manager, netlist_manager,
+                          mux_lib, circuit_lib,
                           src_dir_path, submodule_dir_path, 
                           options);
 
   /* Generate routing blocks */
   if (true == options.compress_routing()) {
-    print_verilog_unique_routing_modules(const_cast<const ModuleManager&>(module_manager),
+    print_verilog_unique_routing_modules(netlist_manager,
+                                         const_cast<const ModuleManager&>(module_manager),
                                          device_rr_gsb,  
                                          src_dir_path, rr_dir_path,
                                          options.explicit_port_mapping());
   } else {
     VTR_ASSERT(false == options.compress_routing());
-    print_verilog_flatten_routing_modules(const_cast<const ModuleManager&>(module_manager),
+    print_verilog_flatten_routing_modules(netlist_manager,
+                                          const_cast<const ModuleManager&>(module_manager),
                                           device_rr_gsb, 
                                           src_dir_path, rr_dir_path,
                                           options.explicit_port_mapping());
   }
 
   /* Generate grids */
-  print_verilog_grids(const_cast<const ModuleManager&>(module_manager),
+  print_verilog_grids(netlist_manager,
+                      const_cast<const ModuleManager&>(module_manager),
                       device_ctx, device_annotation, 
                       src_dir_path, lb_dir_path,
                       options.explicit_port_mapping(),
                       options.verbose_output());
 
   /* Generate FPGA fabric */
-  print_verilog_top_module(const_cast<const ModuleManager&>(module_manager), 
+  print_verilog_top_module(netlist_manager,
+                           const_cast<const ModuleManager&>(module_manager), 
                            src_dir_path,
                            options.explicit_port_mapping());
 
@@ -134,7 +140,8 @@ void fpga_fabric_verilog(ModuleManager& module_manager,
  *    This testbench is created for quick verification and formal verification purpose.
  *  - Verilog netlist including preprocessing flags and all the Verilog netlists that have been generated
  ********************************************************************/
-void fpga_verilog_testbench(const ModuleManager& module_manager,
+void fpga_verilog_testbench(const NetlistManager& netlist_manager,
+                            const ModuleManager& module_manager,
                             const BitstreamManager& bitstream_manager, 
                             const std::vector<ConfigBitId>& fabric_bitstream, 
                             const AtomContext& atom_ctx, 
@@ -219,7 +226,8 @@ void fpga_verilog_testbench(const ModuleManager& module_manager,
   }
 
   /* Generate a Verilog file including all the netlists that have been generated */
-  print_include_netlists(src_dir_path,
+  print_include_netlists(netlist_manager,
+                         src_dir_path,
                          netlist_name,
                          options.reference_benchmark_file_path(),
                          circuit_lib);
diff --git a/openfpga/src/fpga_verilog/verilog_api.h b/openfpga/src/fpga_verilog/verilog_api.h
index 66eb069ba..c9d194dff 100644
--- a/openfpga/src/fpga_verilog/verilog_api.h
+++ b/openfpga/src/fpga_verilog/verilog_api.h
@@ -12,6 +12,7 @@
 #include "vpr_context.h"
 #include "vpr_device_annotation.h"
 #include "device_rr_gsb.h"
+#include "netlist_manager.h"
 #include "module_manager.h"
 #include "bitstream_manager.h"
 #include "simulation_setting.h"
@@ -28,6 +29,7 @@
 namespace openfpga {
 
 void fpga_fabric_verilog(ModuleManager& module_manager,
+                         NetlistManager& netlist_manager,
                          const CircuitLibrary& circuit_lib,
                          const MuxLibrary& mux_lib,
                          const DeviceContext& device_ctx, 
@@ -35,7 +37,8 @@ void fpga_fabric_verilog(ModuleManager& module_manager,
                          const DeviceRRGSB& device_rr_gsb,
                          const FabricVerilogOption& options);
 
-void fpga_verilog_testbench(const ModuleManager& module_manager,
+void fpga_verilog_testbench(const NetlistManager& netlist_manager,
+                            const ModuleManager& module_manager,
                             const BitstreamManager& bitstream_manager, 
                             const std::vector<ConfigBitId>& fabric_bitstream, 
                             const AtomContext& atom_ctx, 
diff --git a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
index fd01a462f..ba2483ca7 100644
--- a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
+++ b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
@@ -29,7 +29,8 @@ namespace openfpga {
  * and user-defined.
  * Some netlists are open to compile under specific preprocessing flags
  *******************************************************************/
-void print_include_netlists(const std::string& src_dir,
+void print_include_netlists(const NetlistManager& netlist_manager,
+                            const std::string& src_dir,
                             const std::string& circuit_name,
                             const std::string& reference_benchmark_file,
                             const CircuitLibrary& circuit_lib) {
@@ -55,24 +56,37 @@ void print_include_netlists(const std::string& src_dir,
   fp << std::endl;
 
   /* Include all the user-defined netlists */
+  print_verilog_comment(fp, std::string("------ Include user-defined netlists -----"));
   for (const std::string& user_defined_netlist : find_circuit_library_unique_verilog_netlists(circuit_lib)) {
     print_verilog_include_netlist(fp, user_defined_netlist);
   }
 
   /* Include all the primitive modules */
-  print_verilog_include_netlist(fp, src_dir + std::string(DEFAULT_SUBMODULE_DIR_NAME) + std::string(SUBMODULE_VERILOG_FILE_NAME));
+  print_verilog_comment(fp, std::string("------ Include primitive module netlists -----"));
+  for (const NetlistId& nlist_id : netlist_manager.netlists_by_type(NetlistManager::SUBMODULE_NETLIST)) {
+    print_verilog_include_netlist(fp, netlist_manager.netlist_name(nlist_id));
+  }
   fp << std::endl;
 
   /* Include all the CLB, heterogeneous block modules */
-  print_verilog_include_netlist(fp, src_dir  + std::string(DEFAULT_LB_DIR_NAME) + std::string(LOGIC_BLOCK_VERILOG_FILE_NAME));
+  print_verilog_comment(fp, std::string("------ Include logic block netlists -----"));
+  for (const NetlistId& nlist_id : netlist_manager.netlists_by_type(NetlistManager::LOGIC_BLOCK_NETLIST)) {
+    print_verilog_include_netlist(fp, netlist_manager.netlist_name(nlist_id));
+  }
   fp << std::endl;
 
   /* Include all the routing architecture modules */
-  print_verilog_include_netlist(fp, src_dir + std::string(DEFAULT_RR_DIR_NAME) + std::string(ROUTING_VERILOG_FILE_NAME));
+  print_verilog_comment(fp, std::string("------ Include routing module netlists -----"));
+  for (const NetlistId& nlist_id : netlist_manager.netlists_by_type(NetlistManager::ROUTING_MODULE_NETLIST)) {
+    print_verilog_include_netlist(fp, netlist_manager.netlist_name(nlist_id));
+  }
   fp << std::endl;
 
   /* Include FPGA top module */
-  print_verilog_include_netlist(fp, src_dir + generate_fpga_top_netlist_name(std::string(VERILOG_NETLIST_FILE_POSTFIX)));
+  print_verilog_comment(fp, std::string("------ Include fabric top-level netlists -----"));
+  for (const NetlistId& nlist_id : netlist_manager.netlists_by_type(NetlistManager::TOP_MODULE_NETLIST)) {
+    print_verilog_include_netlist(fp, netlist_manager.netlist_name(nlist_id));
+  }
   fp << std::endl;
 
   /* Include reference benchmark netlist only when auto-check flag is enabled */
diff --git a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h
index 291ca8915..ed1317862 100644
--- a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h
+++ b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h
@@ -7,6 +7,7 @@
 #include <string>
 #include "circuit_library.h"
 #include "fabric_verilog_options.h"
+#include "netlist_manager.h"
 #include "verilog_testbench_options.h"
 
 /********************************************************************
@@ -16,7 +17,8 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-void print_include_netlists(const std::string& src_dir,
+void print_include_netlists(const NetlistManager& netlist_manager,
+                            const std::string& src_dir,
                             const std::string& circuit_name,
                             const std::string& reference_benchmark_file,
                             const CircuitLibrary& circuit_lib);
diff --git a/openfpga/src/fpga_verilog/verilog_decoders.cpp b/openfpga/src/fpga_verilog/verilog_decoders.cpp
index e9b9f6d02..0e993a3d3 100644
--- a/openfpga/src/fpga_verilog/verilog_decoders.cpp
+++ b/openfpga/src/fpga_verilog/verilog_decoders.cpp
@@ -162,7 +162,7 @@ void print_verilog_mux_local_decoder_module(std::fstream& fp,
  *    See more details in the function print_verilog_mux_local_decoder() for more details
  ***************************************************************************************/
 void print_verilog_submodule_mux_local_decoders(const ModuleManager& module_manager,
-                                                std::vector<std::string>& netlist_names,
+                                                NetlistManager& netlist_manager,
                                                 const MuxLibrary& mux_lib,
                                                 const CircuitLibrary& circuit_lib,
                                                 const std::string& verilog_dir,
@@ -223,7 +223,9 @@ void print_verilog_submodule_mux_local_decoders(const ModuleManager& module_mana
   fp.close();
 
   /* Add fname to the netlist name list */
-  netlist_names.push_back(verilog_fname);
+  NetlistId nlist_id = netlist_manager.add_netlist(verilog_fname);
+  VTR_ASSERT(NetlistId::INVALID() != nlist_id);
+  netlist_manager.set_netlist_type(nlist_id, NetlistManager::SUBMODULE_NETLIST);
 
   VTR_LOG("Done\n");
 }
diff --git a/openfpga/src/fpga_verilog/verilog_decoders.h b/openfpga/src/fpga_verilog/verilog_decoders.h
index 271e7aa5c..f8d559f4d 100644
--- a/openfpga/src/fpga_verilog/verilog_decoders.h
+++ b/openfpga/src/fpga_verilog/verilog_decoders.h
@@ -12,6 +12,7 @@
 #include "mux_graph.h"
 #include "mux_library.h"
 #include "module_manager.h"
+#include "netlist_manager.h"
 
 /********************************************************************
  * Function declaration
@@ -21,7 +22,7 @@
 namespace openfpga {
 
 void print_verilog_submodule_mux_local_decoders(const ModuleManager& module_manager,
-                                                std::vector<std::string>& netlist_names,
+                                                NetlistManager& netlist_manager,
                                                 const MuxLibrary& mux_lib,
                                                 const CircuitLibrary& circuit_lib,
                                                 const std::string& verilog_dir,
diff --git a/openfpga/src/fpga_verilog/verilog_essential_gates.cpp b/openfpga/src/fpga_verilog/verilog_essential_gates.cpp
index a84d02bdf..20be3e7e4 100644
--- a/openfpga/src/fpga_verilog/verilog_essential_gates.cpp
+++ b/openfpga/src/fpga_verilog/verilog_essential_gates.cpp
@@ -526,7 +526,7 @@ void print_verilog_constant_generator_module(const ModuleManager& module_manager
  * etc.
  ***********************************************/
 void print_verilog_submodule_essentials(const ModuleManager& module_manager, 
-                                        std::vector<std::string>& netlist_names,
+                                        NetlistManager& netlist_manager,
                                         const std::string& verilog_dir, 
                                         const std::string& submodule_dir,
                                         const CircuitLibrary& circuit_lib) {
@@ -577,7 +577,9 @@ void print_verilog_submodule_essentials(const ModuleManager& module_manager,
   fp.close();
 
   /* Add fname to the netlist name list */
-  netlist_names.push_back(verilog_fname);
+  NetlistId nlist_id = netlist_manager.add_netlist(verilog_fname);
+  VTR_ASSERT(NetlistId::INVALID() != nlist_id);
+  netlist_manager.set_netlist_type(nlist_id, NetlistManager::SUBMODULE_NETLIST);
 
   VTR_LOG("Done\n");
 }
diff --git a/openfpga/src/fpga_verilog/verilog_essential_gates.h b/openfpga/src/fpga_verilog/verilog_essential_gates.h
index b7f9b519a..b267d0e6e 100644
--- a/openfpga/src/fpga_verilog/verilog_essential_gates.h
+++ b/openfpga/src/fpga_verilog/verilog_essential_gates.h
@@ -6,6 +6,8 @@
  *******************************************************************/
 #include <string>
 #include "circuit_library.h"
+#include "module_manager.h"
+#include "netlist_manager.h"
 
 /********************************************************************
  * Function declaration
@@ -15,7 +17,7 @@
 namespace openfpga {
 
 void print_verilog_submodule_essentials(const ModuleManager& module_manager, 
-                                        std::vector<std::string>& netlist_names,
+                                        NetlistManager& netlist_manager,
                                         const std::string& verilog_dir, 
                                         const std::string& submodule_dir,
                                         const CircuitLibrary& circuit_lib);
diff --git a/openfpga/src/fpga_verilog/verilog_grid.cpp b/openfpga/src/fpga_verilog/verilog_grid.cpp
index 20cdd02f4..0cf509bde 100644
--- a/openfpga/src/fpga_verilog/verilog_grid.cpp
+++ b/openfpga/src/fpga_verilog/verilog_grid.cpp
@@ -194,8 +194,8 @@ void rec_print_verilog_logical_tile(std::fstream& fp,
  * for the logical tile (pb_graph/pb_type) 
  *****************************************************************************/
 static 
-void print_verilog_logical_tile_netlist(const ModuleManager& module_manager,
-                                        std::vector<std::string>& netlist_names,
+void print_verilog_logical_tile_netlist(NetlistManager& netlist_manager,
+                                        const ModuleManager& module_manager,
                                         const VprDeviceAnnotation& device_annotation,
                                         const std::string& verilog_dir,
                                         const std::string& subckt_dir,
@@ -243,7 +243,9 @@ void print_verilog_logical_tile_netlist(const ModuleManager& module_manager,
   fp.close();
 
   /* Add fname to the netlist name list */
-  netlist_names.push_back(verilog_fname);
+  NetlistId nlist_id = netlist_manager.add_netlist(verilog_fname);
+  VTR_ASSERT(NetlistId::INVALID() != nlist_id);
+  netlist_manager.set_netlist_type(nlist_id, NetlistManager::LOGIC_BLOCK_NETLIST);
 
   VTR_LOG("Done\n");
   VTR_LOG("\n");
@@ -258,8 +260,8 @@ void print_verilog_logical_tile_netlist(const ModuleManager& module_manager,
  * the I/O block locates at.
  *****************************************************************************/
 static 
-void print_verilog_physical_tile_netlist(const ModuleManager& module_manager,
-                                         std::vector<std::string>& netlist_names,
+void print_verilog_physical_tile_netlist(NetlistManager& netlist_manager,
+                                         const ModuleManager& module_manager,
                                          const std::string& verilog_dir,
                                          const std::string& subckt_dir,
                                          t_physical_tile_type_ptr phy_block_type,
@@ -319,7 +321,9 @@ void print_verilog_physical_tile_netlist(const ModuleManager& module_manager,
   fp.close();
 
   /* Add fname to the netlist name list */
-  netlist_names.push_back(verilog_fname);
+  NetlistId nlist_id = netlist_manager.add_netlist(verilog_fname);
+  VTR_ASSERT(NetlistId::INVALID() != nlist_id);
+  netlist_manager.set_netlist_type(nlist_id, NetlistManager::LOGIC_BLOCK_NETLIST);
 
   VTR_LOG("Done\n");
 }
@@ -330,7 +334,8 @@ void print_verilog_physical_tile_netlist(const ModuleManager& module_manager,
  * 2. Only one module for each CLB (FILL_TYPE)
  * 3. Only one module for each heterogeneous block
  ****************************************************************************/
-void print_verilog_grids(const ModuleManager& module_manager,
+void print_verilog_grids(NetlistManager& netlist_manager,
+                         const ModuleManager& module_manager,
                          const DeviceContext& device_ctx,
                          const VprDeviceAnnotation& device_annotation,
                          const std::string& verilog_dir,
@@ -354,7 +359,8 @@ void print_verilog_grids(const ModuleManager& module_manager,
     if (nullptr == logical_tile.pb_graph_head) {
       continue;
     }
-    print_verilog_logical_tile_netlist(module_manager, netlist_names,
+    print_verilog_logical_tile_netlist(netlist_manager,
+                                       module_manager,
                                        device_annotation,
                                        verilog_dir, subckt_dir,
                                        logical_tile.pb_graph_head,
@@ -387,7 +393,8 @@ void print_verilog_grids(const ModuleManager& module_manager,
       std::set<e_side> io_type_sides = find_physical_io_tile_located_sides(device_ctx.grid,
                                                                            &physical_tile);
       for (const e_side& io_type_side : io_type_sides) {
-        print_verilog_physical_tile_netlist(module_manager, netlist_names,
+        print_verilog_physical_tile_netlist(netlist_manager,
+                                            module_manager,
                                             verilog_dir, subckt_dir, 
                                             &physical_tile,
                                             io_type_side,
@@ -396,7 +403,8 @@ void print_verilog_grids(const ModuleManager& module_manager,
       continue;
     } else {
       /* For CLB and heterogenenous blocks */
-      print_verilog_physical_tile_netlist(module_manager, netlist_names,
+      print_verilog_physical_tile_netlist(netlist_manager,
+                                          module_manager,
                                           verilog_dir, subckt_dir, 
                                           &physical_tile,
                                           NUM_SIDES,
@@ -408,6 +416,7 @@ void print_verilog_grids(const ModuleManager& module_manager,
   VTR_LOG("\n");
 
   /* Output a header file for all the logic blocks */
+  /*
   std::string grid_verilog_fname(LOGIC_BLOCK_VERILOG_FILE_NAME);
   VTR_LOG("Writing header file for grid Verilog modules '%s' ...",
           grid_verilog_fname.c_str());
@@ -415,6 +424,7 @@ void print_verilog_grids(const ModuleManager& module_manager,
                                             subckt_dir.c_str(),
                                             grid_verilog_fname.c_str());
   VTR_LOG("Done\n");
+   */
 }
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/fpga_verilog/verilog_grid.h b/openfpga/src/fpga_verilog/verilog_grid.h
index da8ea09fa..6d2843628 100644
--- a/openfpga/src/fpga_verilog/verilog_grid.h
+++ b/openfpga/src/fpga_verilog/verilog_grid.h
@@ -7,6 +7,7 @@
 #include <string>
 #include "vpr_context.h"
 #include "module_manager.h"
+#include "netlist_manager.h"
 #include "vpr_device_annotation.h"
 
 /********************************************************************
@@ -16,7 +17,8 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-void print_verilog_grids(const ModuleManager& module_manager,
+void print_verilog_grids(NetlistManager& netlist_manager,
+                         const ModuleManager& module_manager,
                          const DeviceContext& device_ctx,
                          const VprDeviceAnnotation& device_annotation,
                          const std::string& verilog_dir,
diff --git a/openfpga/src/fpga_verilog/verilog_lut.cpp b/openfpga/src/fpga_verilog/verilog_lut.cpp
index a849c5827..fabe9340e 100644
--- a/openfpga/src/fpga_verilog/verilog_lut.cpp
+++ b/openfpga/src/fpga_verilog/verilog_lut.cpp
@@ -30,7 +30,7 @@ namespace openfpga {
  * in the circuit library
  ********************************************************************/
 void print_verilog_submodule_luts(const ModuleManager& module_manager,
-                                  std::vector<std::string>& netlist_names,
+                                  NetlistManager& netlist_manager,
                                   const CircuitLibrary& circuit_lib,
                                   const std::string& verilog_dir,
                                   const std::string& submodule_dir,
@@ -70,7 +70,9 @@ void print_verilog_submodule_luts(const ModuleManager& module_manager,
   fp.close();
 
   /* Add fname to the netlist name list */
-  netlist_names.push_back(verilog_fname);
+  NetlistId nlist_id = netlist_manager.add_netlist(verilog_fname);
+  VTR_ASSERT(NetlistId::INVALID() != nlist_id);
+  netlist_manager.set_netlist_type(nlist_id, NetlistManager::SUBMODULE_NETLIST);
 
   VTR_LOG("Done\n");
 }
diff --git a/openfpga/src/fpga_verilog/verilog_lut.h b/openfpga/src/fpga_verilog/verilog_lut.h
index 7c8b85b79..e9ba3465a 100644
--- a/openfpga/src/fpga_verilog/verilog_lut.h
+++ b/openfpga/src/fpga_verilog/verilog_lut.h
@@ -9,6 +9,7 @@
 
 #include "circuit_library.h"
 #include "module_manager.h"
+#include "netlist_manager.h"
 
 /********************************************************************
  * Function declaration
@@ -18,7 +19,7 @@
 namespace openfpga {
 
 void print_verilog_submodule_luts(const ModuleManager& module_manager,
-                                  std::vector<std::string>& netlist_names,
+                                  NetlistManager& netlist_manager,
                                   const CircuitLibrary& circuit_lib,
                                   const std::string& verilog_dir,
                                   const std::string& submodule_dir,
diff --git a/openfpga/src/fpga_verilog/verilog_memory.cpp b/openfpga/src/fpga_verilog/verilog_memory.cpp
index de0418481..53420a794 100644
--- a/openfpga/src/fpga_verilog/verilog_memory.cpp
+++ b/openfpga/src/fpga_verilog/verilog_memory.cpp
@@ -97,7 +97,7 @@ void print_verilog_mux_memory_module(const ModuleManager& module_manager,
  * memory-bank organization for the memories.
  ********************************************************************/
 void print_verilog_submodule_memories(const ModuleManager& module_manager,
-                                      std::vector<std::string>& netlist_names,
+                                      NetlistManager& netlist_manager,
                                       const MuxLibrary& mux_lib,
                                       const CircuitLibrary& circuit_lib,
                                       const std::string& verilog_dir,
@@ -187,7 +187,9 @@ void print_verilog_submodule_memories(const ModuleManager& module_manager,
   fp.close();
 
   /* Add fname to the netlist name list */
-  netlist_names.push_back(verilog_fname);
+  NetlistId nlist_id = netlist_manager.add_netlist(verilog_fname);
+  VTR_ASSERT(NetlistId::INVALID() != nlist_id);
+  netlist_manager.set_netlist_type(nlist_id, NetlistManager::SUBMODULE_NETLIST);
 
   VTR_LOG("Done\n");
 }
diff --git a/openfpga/src/fpga_verilog/verilog_memory.h b/openfpga/src/fpga_verilog/verilog_memory.h
index 9d29eb15f..a331e5687 100644
--- a/openfpga/src/fpga_verilog/verilog_memory.h
+++ b/openfpga/src/fpga_verilog/verilog_memory.h
@@ -10,6 +10,7 @@
 #include "mux_graph.h"
 #include "mux_library.h"
 #include "module_manager.h"
+#include "netlist_manager.h"
 
 /********************************************************************
  * Function declaration
@@ -19,7 +20,7 @@
 namespace openfpga {
 
 void print_verilog_submodule_memories(const ModuleManager& module_manager,
-                                      std::vector<std::string>& netlist_names,
+                                      NetlistManager& netlist_manager,
                                       const MuxLibrary& mux_lib,
                                       const CircuitLibrary& circuit_lib,
                                       const std::string& verilog_dir,
diff --git a/openfpga/src/fpga_verilog/verilog_mux.cpp b/openfpga/src/fpga_verilog/verilog_mux.cpp
index 1e58e3fc8..c85978722 100644
--- a/openfpga/src/fpga_verilog/verilog_mux.cpp
+++ b/openfpga/src/fpga_verilog/verilog_mux.cpp
@@ -1224,7 +1224,7 @@ void generate_verilog_mux_module(ModuleManager& module_manager,
  * multiplexers in the FPGA device
  **********************************************/
 void print_verilog_submodule_muxes(ModuleManager& module_manager,
-                                   std::vector<std::string>& netlist_names,
+                                   NetlistManager& netlist_manager,
                                    const MuxLibrary& mux_lib,
                                    const CircuitLibrary& circuit_lib,
                                    const std::string& verilog_dir,
@@ -1273,7 +1273,9 @@ void print_verilog_submodule_muxes(ModuleManager& module_manager,
   fp.close();
 
   /* Add fname to the netlist name list */
-  netlist_names.push_back(verilog_fname);
+  NetlistId nlist_id = netlist_manager.add_netlist(verilog_fname);
+  VTR_ASSERT(NetlistId::INVALID() != nlist_id);
+  netlist_manager.set_netlist_type(nlist_id, NetlistManager::SUBMODULE_NETLIST);
 
   VTR_LOG("Done\n");
 }
diff --git a/openfpga/src/fpga_verilog/verilog_mux.h b/openfpga/src/fpga_verilog/verilog_mux.h
index 16e6c2f2a..c98fa77d0 100644
--- a/openfpga/src/fpga_verilog/verilog_mux.h
+++ b/openfpga/src/fpga_verilog/verilog_mux.h
@@ -11,6 +11,7 @@
 #include "mux_graph.h"
 #include "mux_library.h"
 #include "module_manager.h"
+#include "netlist_manager.h"
 
 /********************************************************************
  * Function declaration
@@ -20,7 +21,7 @@
 namespace openfpga {
 
 void print_verilog_submodule_muxes(ModuleManager& module_manager,
-                                   std::vector<std::string>& netlist_names,
+                                   NetlistManager& netlist_manager,
                                    const MuxLibrary& mux_lib,
                                    const CircuitLibrary& circuit_lib,
                                    const std::string& verilog_dir,
diff --git a/openfpga/src/fpga_verilog/verilog_routing.cpp b/openfpga/src/fpga_verilog/verilog_routing.cpp
index a3361fd06..8f74c0074 100644
--- a/openfpga/src/fpga_verilog/verilog_routing.cpp
+++ b/openfpga/src/fpga_verilog/verilog_routing.cpp
@@ -75,8 +75,8 @@ namespace openfpga {
  *              
  ********************************************************************/
 static 
-void print_verilog_routing_connection_box_unique_module(const ModuleManager& module_manager, 
-                                                        std::vector<std::string>& netlist_names,
+void print_verilog_routing_connection_box_unique_module(NetlistManager& netlist_manager,
+                                                        const ModuleManager& module_manager, 
                                                         const std::string& verilog_dir, 
                                                         const std::string& subckt_dir, 
                                                         const RRGSB& rr_gsb,
@@ -111,7 +111,9 @@ void print_verilog_routing_connection_box_unique_module(const ModuleManager& mod
   fp.close();
 
   /* Add fname to the netlist name list */
-  netlist_names.push_back(verilog_fname);
+  NetlistId nlist_id = netlist_manager.add_netlist(verilog_fname);
+  VTR_ASSERT(NetlistId::INVALID() != nlist_id);
+  netlist_manager.set_netlist_type(nlist_id, NetlistManager::ROUTING_MODULE_NETLIST);
 }
 
 /*********************************************************************
@@ -178,8 +180,8 @@ void print_verilog_routing_connection_box_unique_module(const ModuleManager& mod
  *
  ********************************************************************/
 static 
-void print_verilog_routing_switch_box_unique_module(const ModuleManager& module_manager, 
-                                                    std::vector<std::string>& netlist_names,
+void print_verilog_routing_switch_box_unique_module(NetlistManager& netlist_manager,
+                                                    const ModuleManager& module_manager, 
                                                     const std::string& verilog_dir, 
                                                     const std::string& subckt_dir, 
                                                     const RRGSB& rr_gsb,
@@ -210,7 +212,9 @@ void print_verilog_routing_switch_box_unique_module(const ModuleManager& module_
   fp.close();
 
   /* Add fname to the netlist name list */
-  netlist_names.push_back(verilog_fname);
+  NetlistId nlist_id = netlist_manager.add_netlist(verilog_fname);
+  VTR_ASSERT(NetlistId::INVALID() != nlist_id);
+  netlist_manager.set_netlist_type(nlist_id, NetlistManager::ROUTING_MODULE_NETLIST);
 }
 
 /********************************************************************
@@ -218,8 +222,8 @@ void print_verilog_routing_switch_box_unique_module(const ModuleManager& module_
  * and build a module for each of them 
  *******************************************************************/
 static 
-void print_verilog_flatten_connection_block_modules(const ModuleManager& module_manager, 
-                                                    std::vector<std::string>& netlist_names,
+void print_verilog_flatten_connection_block_modules(NetlistManager& netlist_manager,
+                                                    const ModuleManager& module_manager, 
                                                     const DeviceRRGSB& device_rr_gsb,
                                                     const std::string& verilog_dir,
                                                     const std::string& subckt_dir,
@@ -238,7 +242,8 @@ void print_verilog_flatten_connection_block_modules(const ModuleManager& module_
       if (true != rr_gsb.is_cb_exist(cb_type)) {
         continue;
       }
-      print_verilog_routing_connection_box_unique_module(module_manager, netlist_names, 
+      print_verilog_routing_connection_box_unique_module(netlist_manager, 
+                                                         module_manager,
                                                          verilog_dir,
                                                          subckt_dir, 
                                                          rr_gsb, cb_type,  
@@ -256,7 +261,8 @@ void print_verilog_flatten_connection_block_modules(const ModuleManager& module_
  * 1. Connection blocks
  * 2. Switch blocks
  *******************************************************************/
-void print_verilog_flatten_routing_modules(const ModuleManager& module_manager,
+void print_verilog_flatten_routing_modules(NetlistManager& netlist_manager,
+                                           const ModuleManager& module_manager,
                                            const DeviceRRGSB& device_rr_gsb,
                                            const std::string& verilog_dir,
                                            const std::string& subckt_dir,
@@ -273,7 +279,8 @@ void print_verilog_flatten_routing_modules(const ModuleManager& module_manager,
       if (true != rr_gsb.is_sb_exist()) {
         continue;
       }
-      print_verilog_routing_switch_box_unique_module(module_manager, netlist_names, 
+      print_verilog_routing_switch_box_unique_module(netlist_manager,
+                                                     module_manager, 
                                                      verilog_dir,
                                                      subckt_dir, 
                                                      rr_gsb, 
@@ -281,10 +288,11 @@ void print_verilog_flatten_routing_modules(const ModuleManager& module_manager,
     }
   }
 
-  print_verilog_flatten_connection_block_modules(module_manager, netlist_names, device_rr_gsb, verilog_dir, subckt_dir, CHANX, use_explicit_port_map);
+  print_verilog_flatten_connection_block_modules(netlist_manager, module_manager, device_rr_gsb, verilog_dir, subckt_dir, CHANX, use_explicit_port_map);
 
-  print_verilog_flatten_connection_block_modules(module_manager, netlist_names, device_rr_gsb, verilog_dir, subckt_dir, CHANY, use_explicit_port_map);
+  print_verilog_flatten_connection_block_modules(netlist_manager, module_manager, device_rr_gsb, verilog_dir, subckt_dir, CHANY, use_explicit_port_map);
 
+  /*
   VTR_LOG("Writing header file for routing submodules '%s'...",
           ROUTING_VERILOG_FILE_NAME);
   print_verilog_netlist_include_header_file(netlist_names,
@@ -292,6 +300,7 @@ void print_verilog_flatten_routing_modules(const ModuleManager& module_manager,
                                             ROUTING_VERILOG_FILE_NAME);
   VTR_LOG("Done\n");
   VTR_LOG("\n");
+   */
 }
 
 
@@ -305,7 +314,8 @@ void print_verilog_flatten_routing_modules(const ModuleManager& module_manager,
  * Note: this function SHOULD be called only when 
  * the option compact_routing_hierarchy is turned on!!!
  *******************************************************************/
-void print_verilog_unique_routing_modules(const ModuleManager& module_manager,
+void print_verilog_unique_routing_modules(NetlistManager& netlist_manager,
+                                          const ModuleManager& module_manager,
                                           const DeviceRRGSB& device_rr_gsb,
                                           const std::string& verilog_dir,
                                           const std::string& subckt_dir,
@@ -316,7 +326,8 @@ void print_verilog_unique_routing_modules(const ModuleManager& module_manager,
   /* Build unique switch block modules */
   for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_module(); ++isb) {
     const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(isb);
-    print_verilog_routing_switch_box_unique_module(module_manager, netlist_names,
+    print_verilog_routing_switch_box_unique_module(netlist_manager,
+                                                   module_manager,
                                                    verilog_dir,
                                                    subckt_dir, 
                                                    unique_mirror, 
@@ -327,7 +338,8 @@ void print_verilog_unique_routing_modules(const ModuleManager& module_manager,
   for (size_t icb = 0; icb < device_rr_gsb.get_num_cb_unique_module(CHANX); ++icb) {
     const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANX, icb);
 
-    print_verilog_routing_connection_box_unique_module(module_manager, netlist_names,
+    print_verilog_routing_connection_box_unique_module(netlist_manager,
+                                                       module_manager,
                                                        verilog_dir,
                                                        subckt_dir, 
                                                        unique_mirror, CHANX,  
@@ -338,19 +350,22 @@ void print_verilog_unique_routing_modules(const ModuleManager& module_manager,
   for (size_t icb = 0; icb < device_rr_gsb.get_num_cb_unique_module(CHANY); ++icb) {
     const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANY, icb);
 
-    print_verilog_routing_connection_box_unique_module(module_manager, netlist_names, 
+    print_verilog_routing_connection_box_unique_module(netlist_manager, 
+                                                       module_manager,
                                                        verilog_dir,
                                                        subckt_dir, 
                                                        unique_mirror, CHANY,  
                                                        use_explicit_port_map);
   }
 
+  /*
   VTR_LOG("Writing header file for routing submodules '%s'...",
           ROUTING_VERILOG_FILE_NAME);
   print_verilog_netlist_include_header_file(netlist_names,
                                             subckt_dir.c_str(),
                                             ROUTING_VERILOG_FILE_NAME);
   VTR_LOG("Done\n");
+   */
   VTR_LOG("\n");
 }
 
diff --git a/openfpga/src/fpga_verilog/verilog_routing.h b/openfpga/src/fpga_verilog/verilog_routing.h
index 2a1a58a66..a9f8fd6a1 100644
--- a/openfpga/src/fpga_verilog/verilog_routing.h
+++ b/openfpga/src/fpga_verilog/verilog_routing.h
@@ -7,6 +7,7 @@
 
 #include "mux_library.h"
 #include "module_manager.h"
+#include "netlist_manager.h"
 #include "device_rr_gsb.h"
 
 /********************************************************************
@@ -16,13 +17,15 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-void print_verilog_flatten_routing_modules(const ModuleManager& module_manager,
+void print_verilog_flatten_routing_modules(NetlistManager& netlist_manager,
+                                           const ModuleManager& module_manager,
                                            const DeviceRRGSB& device_rr_gsb,
                                            const std::string& verilog_dir,
                                            const std::string& subckt_dir,
                                            const bool& use_explicit_port_map);
 
-void print_verilog_unique_routing_modules(const ModuleManager& module_manager,
+void print_verilog_unique_routing_modules(NetlistManager& netlist_manager,
+                                          const ModuleManager& module_manager,
                                           const DeviceRRGSB& device_rr_gsb,
                                           const std::string& verilog_dir,
                                           const std::string& subckt_dir,
diff --git a/openfpga/src/fpga_verilog/verilog_submodule.cpp b/openfpga/src/fpga_verilog/verilog_submodule.cpp
index 099118e5f..b38750ab9 100644
--- a/openfpga/src/fpga_verilog/verilog_submodule.cpp
+++ b/openfpga/src/fpga_verilog/verilog_submodule.cpp
@@ -32,6 +32,7 @@ namespace openfpga {
  * 6. Verilog template
  ********************************************************************/
 void print_verilog_submodule(ModuleManager& module_manager, 
+                             NetlistManager& netlist_manager,
                              const MuxLibrary& mux_lib,
                              const CircuitLibrary& circuit_lib, 
                              const std::string& verilog_dir, 
@@ -44,12 +45,8 @@ void print_verilog_submodule(ModuleManager& module_manager,
    */
   //add_user_defined_verilog_modules(module_manager, circuit_lib);
 
-  /* Create a vector to contain all the Verilog netlist names that have been generated in this function */
-  std::vector<std::string> netlist_names;
-
-
   print_verilog_submodule_essentials(const_cast<const ModuleManager&>(module_manager), 
-                                     netlist_names,
+                                     netlist_manager,
                                      verilog_dir, 
                                      submodule_dir,
                                      circuit_lib);
@@ -59,28 +56,28 @@ void print_verilog_submodule(ModuleManager& module_manager,
    *       because local decoders modules will be instanciated in the MUX modules 
    */
   print_verilog_submodule_mux_local_decoders(const_cast<const ModuleManager&>(module_manager),
-                                             netlist_names, 
+                                             netlist_manager, 
                                              mux_lib, circuit_lib, 
                                              verilog_dir, submodule_dir);
-  print_verilog_submodule_muxes(module_manager, netlist_names, mux_lib, circuit_lib,
+  print_verilog_submodule_muxes(module_manager, netlist_manager, mux_lib, circuit_lib,
                                 verilog_dir, submodule_dir,
                                 fpga_verilog_opts.explicit_port_mapping());
 
  
   /* LUTes */
   print_verilog_submodule_luts(const_cast<const ModuleManager&>(module_manager),
-                               netlist_names, circuit_lib,
+                               netlist_manager, circuit_lib,
                                verilog_dir, submodule_dir,
                                fpga_verilog_opts.explicit_port_mapping());
 
   /* Hard wires */
   print_verilog_submodule_wires(const_cast<const ModuleManager&>(module_manager),
-                                netlist_names, circuit_lib,
+                                netlist_manager, circuit_lib,
                                 verilog_dir, submodule_dir);
 
   /* 4. Memories */
   print_verilog_submodule_memories(const_cast<const ModuleManager&>(module_manager),
-                                   netlist_names,
+                                   netlist_manager,
                                    mux_lib, circuit_lib, 
                                    verilog_dir, submodule_dir,
                                    fpga_verilog_opts.explicit_port_mapping());
@@ -93,9 +90,11 @@ void print_verilog_submodule(ModuleManager& module_manager,
   }
 
   /* Create a header file to include all the subckts */
-  print_verilog_netlist_include_header_file(netlist_names,
+  /*
+  print_verilog_netlist_include_header_file(netlist_manager,
                                             submodule_dir.c_str(),
                                             SUBMODULE_VERILOG_FILE_NAME);
+   */
 }
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/fpga_verilog/verilog_submodule.h b/openfpga/src/fpga_verilog/verilog_submodule.h
index 88e1ce965..d3de8b9d7 100644
--- a/openfpga/src/fpga_verilog/verilog_submodule.h
+++ b/openfpga/src/fpga_verilog/verilog_submodule.h
@@ -5,6 +5,7 @@
  * Include header files that are required by function declaration
  *******************************************************************/
 #include "module_manager.h"
+#include "netlist_manager.h"
 #include "mux_library.h"
 #include "fabric_verilog_options.h"
 
@@ -16,6 +17,7 @@
 namespace openfpga {
 
 void print_verilog_submodule(ModuleManager& module_manager, 
+                             NetlistManager& netlist_manager,
                              const MuxLibrary& mux_lib,
                              const CircuitLibrary& circuit_lib, 
                              const std::string& verilog_dir, 
diff --git a/openfpga/src/fpga_verilog/verilog_top_module.cpp b/openfpga/src/fpga_verilog/verilog_top_module.cpp
index 9bcfadc68..9596f20a3 100644
--- a/openfpga/src/fpga_verilog/verilog_top_module.cpp
+++ b/openfpga/src/fpga_verilog/verilog_top_module.cpp
@@ -34,7 +34,8 @@ namespace openfpga {
  * 4. Add module nets to connect datapath ports
  * 5. Add module nets/submodules to connect configuration ports
  *******************************************************************/
-void print_verilog_top_module(const ModuleManager& module_manager,
+void print_verilog_top_module(NetlistManager& netlist_manager,
+                              const ModuleManager& module_manager,
                               const std::string& verilog_dir,
                               const bool& use_explicit_mapping) {
   /* Create a module as the top-level fabric, and add it to the module manager */
@@ -69,6 +70,11 @@ void print_verilog_top_module(const ModuleManager& module_manager,
   /* Close file handler */
   fp.close();
 
+  /* Add fname to the netlist name list */
+  NetlistId nlist_id = netlist_manager.add_netlist(verilog_fname);
+  VTR_ASSERT(NetlistId::INVALID() != nlist_id);
+  netlist_manager.set_netlist_type(nlist_id, NetlistManager::TOP_MODULE_NETLIST);
+
   VTR_LOG("Done\n");
 }
 
diff --git a/openfpga/src/fpga_verilog/verilog_top_module.h b/openfpga/src/fpga_verilog/verilog_top_module.h
index 2fb451e16..95f73e815 100644
--- a/openfpga/src/fpga_verilog/verilog_top_module.h
+++ b/openfpga/src/fpga_verilog/verilog_top_module.h
@@ -6,6 +6,7 @@
  *******************************************************************/
 #include <string>
 #include "module_manager.h"
+#include "netlist_manager.h"
 
 /********************************************************************
  * Function declaration
@@ -14,7 +15,8 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-void print_verilog_top_module(const ModuleManager& module_manager,
+void print_verilog_top_module(NetlistManager& netlist_manager,
+                              const ModuleManager& module_manager,
                               const std::string& verilog_dir,
                               const bool& use_explicit_mapping);
 
diff --git a/openfpga/src/fpga_verilog/verilog_wire.cpp b/openfpga/src/fpga_verilog/verilog_wire.cpp
index 4f084fad9..d28b26f81 100644
--- a/openfpga/src/fpga_verilog/verilog_wire.cpp
+++ b/openfpga/src/fpga_verilog/verilog_wire.cpp
@@ -93,7 +93,7 @@ void print_verilog_wire_module(const ModuleManager& module_manager,
  * Top-level function to print wire modules
  *******************************************************************/
 void print_verilog_submodule_wires(const ModuleManager& module_manager,
-                                   std::vector<std::string>& netlist_names,
+                                   NetlistManager& netlist_manager,
                                    const CircuitLibrary& circuit_lib,
                                    const std::string& verilog_dir,
                                    const std::string& submodule_dir) {
@@ -128,7 +128,9 @@ void print_verilog_submodule_wires(const ModuleManager& module_manager,
   fp.close();
 
   /* Add fname to the netlist name list */
-  netlist_names.push_back(verilog_fname);
+  NetlistId nlist_id = netlist_manager.add_netlist(verilog_fname);
+  VTR_ASSERT(NetlistId::INVALID() != nlist_id);
+  netlist_manager.set_netlist_type(nlist_id, NetlistManager::SUBMODULE_NETLIST);
 
   VTR_LOG("Done\n");
 }
diff --git a/openfpga/src/fpga_verilog/verilog_wire.h b/openfpga/src/fpga_verilog/verilog_wire.h
index 55c39fb30..62331d8b9 100644
--- a/openfpga/src/fpga_verilog/verilog_wire.h
+++ b/openfpga/src/fpga_verilog/verilog_wire.h
@@ -9,6 +9,7 @@
 
 #include "circuit_library.h"
 #include "module_manager.h"
+#include "netlist_manager.h"
 
 /********************************************************************
  * Function declaration
@@ -18,7 +19,7 @@
 namespace openfpga {
 
 void print_verilog_submodule_wires(const ModuleManager& module_manager,
-                                   std::vector<std::string>& netlist_names,
+                                   NetlistManager& netlist_manager,
                                    const CircuitLibrary& circuit_lib,
                                    const std::string& verilog_dir,
                                    const std::string& submodule_dir);

From 8f5a684b102afdb3d81518d75fef4487f4eca89f Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 24 Apr 2020 20:21:32 -0600
Subject: [PATCH 478/645] removed redundant include files in all the verilog
 netlists except the top one

---
 openfpga/src/fpga_verilog/verilog_api.cpp     | 13 +++++-------
 .../src/fpga_verilog/verilog_decoders.cpp     |  3 ---
 openfpga/src/fpga_verilog/verilog_decoders.h  |  1 -
 .../fpga_verilog/verilog_essential_gates.cpp  |  3 ---
 .../fpga_verilog/verilog_essential_gates.h    |  1 -
 .../verilog_formal_random_top_testbench.cpp   |  6 ------
 .../verilog_formal_random_top_testbench.h     |  1 -
 openfpga/src/fpga_verilog/verilog_grid.cpp    | 15 +++-----------
 openfpga/src/fpga_verilog/verilog_grid.h      |  1 -
 openfpga/src/fpga_verilog/verilog_lut.cpp     |  3 ---
 openfpga/src/fpga_verilog/verilog_lut.h       |  1 -
 openfpga/src/fpga_verilog/verilog_memory.cpp  |  3 ---
 openfpga/src/fpga_verilog/verilog_memory.h    |  1 -
 openfpga/src/fpga_verilog/verilog_mux.cpp     |  3 ---
 openfpga/src/fpga_verilog/verilog_mux.h       |  1 -
 .../verilog_preconfig_top_module.cpp          |  8 +-------
 .../verilog_preconfig_top_module.h            |  3 +--
 openfpga/src/fpga_verilog/verilog_routing.cpp | 20 ++-----------------
 openfpga/src/fpga_verilog/verilog_routing.h   |  2 --
 .../src/fpga_verilog/verilog_submodule.cpp    | 14 ++++++-------
 openfpga/src/fpga_verilog/verilog_submodule.h |  1 -
 .../fpga_verilog/verilog_submodule_utils.cpp  |  3 ---
 .../fpga_verilog/verilog_submodule_utils.h    |  1 -
 .../src/fpga_verilog/verilog_top_module.cpp   |  3 ---
 .../fpga_verilog/verilog_top_testbench.cpp    |  4 ----
 .../src/fpga_verilog/verilog_top_testbench.h  |  1 -
 openfpga/src/fpga_verilog/verilog_wire.cpp    |  3 ---
 openfpga/src/fpga_verilog/verilog_wire.h      |  1 -
 28 files changed, 18 insertions(+), 102 deletions(-)

diff --git a/openfpga/src/fpga_verilog/verilog_api.cpp b/openfpga/src/fpga_verilog/verilog_api.cpp
index d2823df48..c8c7343ad 100644
--- a/openfpga/src/fpga_verilog/verilog_api.cpp
+++ b/openfpga/src/fpga_verilog/verilog_api.cpp
@@ -91,7 +91,7 @@ void fpga_fabric_verilog(ModuleManager& module_manager,
    */
   print_verilog_submodule(module_manager, netlist_manager,
                           mux_lib, circuit_lib,
-                          src_dir_path, submodule_dir_path, 
+                          submodule_dir_path, 
                           options);
 
   /* Generate routing blocks */
@@ -99,14 +99,14 @@ void fpga_fabric_verilog(ModuleManager& module_manager,
     print_verilog_unique_routing_modules(netlist_manager,
                                          const_cast<const ModuleManager&>(module_manager),
                                          device_rr_gsb,  
-                                         src_dir_path, rr_dir_path,
+                                         rr_dir_path,
                                          options.explicit_port_mapping());
   } else {
     VTR_ASSERT(false == options.compress_routing());
     print_verilog_flatten_routing_modules(netlist_manager,
                                           const_cast<const ModuleManager&>(module_manager),
                                           device_rr_gsb, 
-                                          src_dir_path, rr_dir_path,
+                                          rr_dir_path,
                                           options.explicit_port_mapping());
   }
 
@@ -114,7 +114,7 @@ void fpga_fabric_verilog(ModuleManager& module_manager,
   print_verilog_grids(netlist_manager,
                       const_cast<const ModuleManager&>(module_manager),
                       device_ctx, device_annotation, 
-                      src_dir_path, lb_dir_path,
+                      lb_dir_path,
                       options.explicit_port_mapping(),
                       options.verbose_output());
 
@@ -180,8 +180,7 @@ void fpga_verilog_testbench(const NetlistManager& netlist_manager,
                                        atom_ctx, place_ctx, io_location_map,
                                        netlist_annotation,
                                        netlist_name,
-                                       formal_verification_top_netlist_file_path,
-                                       src_dir_path);
+                                       formal_verification_top_netlist_file_path);
   }
 
   if (true == options.print_preconfig_top_testbench()) {
@@ -190,7 +189,6 @@ void fpga_verilog_testbench(const NetlistManager& netlist_manager,
                                                + std::string(RANDOM_TOP_TESTBENCH_VERILOG_FILE_POSTFIX);
     print_verilog_random_top_testbench(netlist_name,
                                        random_top_testbench_file_path, 
-                                       src_dir_path,
                                        atom_ctx,  
                                        netlist_annotation,
                                        simulation_setting);
@@ -208,7 +206,6 @@ void fpga_verilog_testbench(const NetlistManager& netlist_manager,
                                 netlist_annotation,
                                 netlist_name,
                                 top_testbench_file_path,
-                                src_dir_path,
                                 simulation_setting);
   }
  
diff --git a/openfpga/src/fpga_verilog/verilog_decoders.cpp b/openfpga/src/fpga_verilog/verilog_decoders.cpp
index 0e993a3d3..30789e36f 100644
--- a/openfpga/src/fpga_verilog/verilog_decoders.cpp
+++ b/openfpga/src/fpga_verilog/verilog_decoders.cpp
@@ -165,7 +165,6 @@ void print_verilog_submodule_mux_local_decoders(const ModuleManager& module_mana
                                                 NetlistManager& netlist_manager,
                                                 const MuxLibrary& mux_lib,
                                                 const CircuitLibrary& circuit_lib,
-                                                const std::string& verilog_dir,
                                                 const std::string& submodule_dir) {
   std::string verilog_fname(submodule_dir + std::string(LOCAL_ENCODER_VERILOG_FILE_NAME));
 
@@ -181,8 +180,6 @@ void print_verilog_submodule_mux_local_decoders(const ModuleManager& module_mana
 
   print_verilog_file_header(fp, "Local Decoders for Multiplexers"); 
 
-  print_verilog_include_defines_preproc_file(fp, verilog_dir);
-
   /* Create a library for local encoders with different sizes */
   DecoderLibrary decoder_lib;
   
diff --git a/openfpga/src/fpga_verilog/verilog_decoders.h b/openfpga/src/fpga_verilog/verilog_decoders.h
index f8d559f4d..9b2bbb6b1 100644
--- a/openfpga/src/fpga_verilog/verilog_decoders.h
+++ b/openfpga/src/fpga_verilog/verilog_decoders.h
@@ -25,7 +25,6 @@ void print_verilog_submodule_mux_local_decoders(const ModuleManager& module_mana
                                                 NetlistManager& netlist_manager,
                                                 const MuxLibrary& mux_lib,
                                                 const CircuitLibrary& circuit_lib,
-                                                const std::string& verilog_dir,
                                                 const std::string& submodule_dir);
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/fpga_verilog/verilog_essential_gates.cpp b/openfpga/src/fpga_verilog/verilog_essential_gates.cpp
index 20be3e7e4..cb8eb9504 100644
--- a/openfpga/src/fpga_verilog/verilog_essential_gates.cpp
+++ b/openfpga/src/fpga_verilog/verilog_essential_gates.cpp
@@ -527,7 +527,6 @@ void print_verilog_constant_generator_module(const ModuleManager& module_manager
  ***********************************************/
 void print_verilog_submodule_essentials(const ModuleManager& module_manager, 
                                         NetlistManager& netlist_manager,
-                                        const std::string& verilog_dir, 
                                         const std::string& submodule_dir,
                                         const CircuitLibrary& circuit_lib) {
   /* TODO: remove .bak when this part is completed and tested */
@@ -546,8 +545,6 @@ void print_verilog_submodule_essentials(const ModuleManager& module_manager,
 
   print_verilog_file_header(fp, "Essential gates"); 
 
-  print_verilog_include_defines_preproc_file(fp, verilog_dir);
-
   /* Print constant generators */
   /* VDD */
   print_verilog_constant_generator_module(module_manager, fp, 0);
diff --git a/openfpga/src/fpga_verilog/verilog_essential_gates.h b/openfpga/src/fpga_verilog/verilog_essential_gates.h
index b267d0e6e..2510e6d3d 100644
--- a/openfpga/src/fpga_verilog/verilog_essential_gates.h
+++ b/openfpga/src/fpga_verilog/verilog_essential_gates.h
@@ -18,7 +18,6 @@ namespace openfpga {
 
 void print_verilog_submodule_essentials(const ModuleManager& module_manager, 
                                         NetlistManager& netlist_manager,
-                                        const std::string& verilog_dir, 
                                         const std::string& submodule_dir,
                                         const CircuitLibrary& circuit_lib);
 
diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
index fa4f68938..8d4dab5c9 100644
--- a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
@@ -183,7 +183,6 @@ void print_verilog_random_testbench_fpga_instance(std::fstream& fp,
  ********************************************************************/
 void print_verilog_random_top_testbench(const std::string& circuit_name,
                                         const std::string& verilog_fname,
-                                        const std::string& verilog_dir,
                                         const AtomContext& atom_ctx,
                                         const VprNetlistAnnotation& netlist_annotation,
                                         const SimulationSetting& simulation_parameters) {
@@ -203,11 +202,6 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
   std::string title = std::string("FPGA Verilog Testbench for Formal Top-level netlist of Design: ") + circuit_name;
   print_verilog_file_header(fp, title); 
 
-  /* Print preprocessing flags and external netlists */
-  print_verilog_include_defines_preproc_file(fp, verilog_dir);
-
-  print_verilog_include_netlist(fp, std::string(verilog_dir + std::string(DEFINES_VERILOG_SIMULATION_FILE_NAME)));  
-
   /* Preparation: find all the clock ports */
   std::vector<std::string> clock_port_names = find_atom_netlist_clock_port_names(atom_ctx.nlist, netlist_annotation);
 
diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.h b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.h
index 88692ae4f..b12072b70 100644
--- a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.h
+++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.h
@@ -17,7 +17,6 @@ namespace openfpga {
 
 void print_verilog_random_top_testbench(const std::string& circuit_name,
                                         const std::string& verilog_fname,
-                                        const std::string& verilog_dir,
                                         const AtomContext& atom_ctx,
                                         const VprNetlistAnnotation& netlist_annotation,
                                         const SimulationSetting& simulation_parameters);
diff --git a/openfpga/src/fpga_verilog/verilog_grid.cpp b/openfpga/src/fpga_verilog/verilog_grid.cpp
index 0cf509bde..d2917836b 100644
--- a/openfpga/src/fpga_verilog/verilog_grid.cpp
+++ b/openfpga/src/fpga_verilog/verilog_grid.cpp
@@ -197,7 +197,6 @@ static
 void print_verilog_logical_tile_netlist(NetlistManager& netlist_manager,
                                         const ModuleManager& module_manager,
                                         const VprDeviceAnnotation& device_annotation,
-                                        const std::string& verilog_dir,
                                         const std::string& subckt_dir,
                                         t_pb_graph_node* pb_graph_head,
                                         const bool& use_explicit_mapping,
@@ -220,9 +219,6 @@ void print_verilog_logical_tile_netlist(NetlistManager& netlist_manager,
 
   print_verilog_file_header(fp, std::string("Verilog modules for logical tile: " + std::string(pb_graph_head->pb_type->name) + "]")); 
 
-  /* Print preprocessing flags */
-  print_verilog_include_defines_preproc_file(fp, verilog_dir);
-
   /* Print Verilog modules for all the pb_types/pb_graph_nodes
    * use a Depth-First Search Algorithm to print the sub-modules 
    * Note: DFS is the right way. Do NOT use BFS.
@@ -262,7 +258,6 @@ void print_verilog_logical_tile_netlist(NetlistManager& netlist_manager,
 static 
 void print_verilog_physical_tile_netlist(NetlistManager& netlist_manager,
                                          const ModuleManager& module_manager,
-                                         const std::string& verilog_dir,
                                          const std::string& subckt_dir,
                                          t_physical_tile_type_ptr phy_block_type,
                                          const e_side& border_side,
@@ -300,9 +295,6 @@ void print_verilog_physical_tile_netlist(NetlistManager& netlist_manager,
 
   print_verilog_file_header(fp, std::string("Verilog modules for physical tile: " + std::string(phy_block_type->name) + "]")); 
 
-  /* Print preprocessing flags */
-  print_verilog_include_defines_preproc_file(fp, verilog_dir);
-
   /* Create a Verilog Module for the top-level physical block, and add to module manager */
   std::string grid_module_name = generate_grid_block_module_name(std::string(GRID_VERILOG_FILE_NAME_PREFIX), std::string(phy_block_type->name), is_io_type(phy_block_type), border_side);
   ModuleId grid_module = module_manager.find_module(grid_module_name); 
@@ -338,7 +330,6 @@ void print_verilog_grids(NetlistManager& netlist_manager,
                          const ModuleManager& module_manager,
                          const DeviceContext& device_ctx,
                          const VprDeviceAnnotation& device_annotation,
-                         const std::string& verilog_dir,
                          const std::string& subckt_dir,
                          const bool& use_explicit_mapping,
                          const bool& verbose) {
@@ -362,7 +353,7 @@ void print_verilog_grids(NetlistManager& netlist_manager,
     print_verilog_logical_tile_netlist(netlist_manager,
                                        module_manager,
                                        device_annotation,
-                                       verilog_dir, subckt_dir,
+                                       subckt_dir,
                                        logical_tile.pb_graph_head,
                                        use_explicit_mapping,
                                        verbose);
@@ -395,7 +386,7 @@ void print_verilog_grids(NetlistManager& netlist_manager,
       for (const e_side& io_type_side : io_type_sides) {
         print_verilog_physical_tile_netlist(netlist_manager,
                                             module_manager,
-                                            verilog_dir, subckt_dir, 
+                                            subckt_dir, 
                                             &physical_tile,
                                             io_type_side,
                                             use_explicit_mapping);
@@ -405,7 +396,7 @@ void print_verilog_grids(NetlistManager& netlist_manager,
       /* For CLB and heterogenenous blocks */
       print_verilog_physical_tile_netlist(netlist_manager,
                                           module_manager,
-                                          verilog_dir, subckt_dir, 
+                                          subckt_dir, 
                                           &physical_tile,
                                           NUM_SIDES,
                                           use_explicit_mapping);
diff --git a/openfpga/src/fpga_verilog/verilog_grid.h b/openfpga/src/fpga_verilog/verilog_grid.h
index 6d2843628..7603bd298 100644
--- a/openfpga/src/fpga_verilog/verilog_grid.h
+++ b/openfpga/src/fpga_verilog/verilog_grid.h
@@ -21,7 +21,6 @@ void print_verilog_grids(NetlistManager& netlist_manager,
                          const ModuleManager& module_manager,
                          const DeviceContext& device_ctx,
                          const VprDeviceAnnotation& device_annotation,
-                         const std::string& verilog_dir,
                          const std::string& subckt_dir,
                          const bool& use_explicit_mapping,
                          const bool& verbose);
diff --git a/openfpga/src/fpga_verilog/verilog_lut.cpp b/openfpga/src/fpga_verilog/verilog_lut.cpp
index fabe9340e..34767aff7 100644
--- a/openfpga/src/fpga_verilog/verilog_lut.cpp
+++ b/openfpga/src/fpga_verilog/verilog_lut.cpp
@@ -32,7 +32,6 @@ namespace openfpga {
 void print_verilog_submodule_luts(const ModuleManager& module_manager,
                                   NetlistManager& netlist_manager,
                                   const CircuitLibrary& circuit_lib,
-                                  const std::string& verilog_dir,
                                   const std::string& submodule_dir,
                                   const bool& use_explicit_port_map) {
   std::string verilog_fname = submodule_dir + std::string(LUTS_VERILOG_FILE_NAME);
@@ -50,8 +49,6 @@ void print_verilog_submodule_luts(const ModuleManager& module_manager,
 
   print_verilog_file_header(fp, "Look-Up Tables"); 
 
-  print_verilog_include_defines_preproc_file(fp, verilog_dir);
-
   /* Search for each LUT circuit model */
   for (const auto& lut_model : circuit_lib.models()) {
     /* Bypass user-defined and non-LUT modules */
diff --git a/openfpga/src/fpga_verilog/verilog_lut.h b/openfpga/src/fpga_verilog/verilog_lut.h
index e9ba3465a..a102e6df0 100644
--- a/openfpga/src/fpga_verilog/verilog_lut.h
+++ b/openfpga/src/fpga_verilog/verilog_lut.h
@@ -21,7 +21,6 @@ namespace openfpga {
 void print_verilog_submodule_luts(const ModuleManager& module_manager,
                                   NetlistManager& netlist_manager,
                                   const CircuitLibrary& circuit_lib,
-                                  const std::string& verilog_dir,
                                   const std::string& submodule_dir,
                                   const bool& use_explicit_port_map);
 
diff --git a/openfpga/src/fpga_verilog/verilog_memory.cpp b/openfpga/src/fpga_verilog/verilog_memory.cpp
index 53420a794..ad30eb337 100644
--- a/openfpga/src/fpga_verilog/verilog_memory.cpp
+++ b/openfpga/src/fpga_verilog/verilog_memory.cpp
@@ -100,7 +100,6 @@ void print_verilog_submodule_memories(const ModuleManager& module_manager,
                                       NetlistManager& netlist_manager,
                                       const MuxLibrary& mux_lib,
                                       const CircuitLibrary& circuit_lib,
-                                      const std::string& verilog_dir,
                                       const std::string& submodule_dir,
                                       const bool& use_explicit_port_map) {
   /* Plug in with the mux subckt */
@@ -118,8 +117,6 @@ void print_verilog_submodule_memories(const ModuleManager& module_manager,
 
   print_verilog_file_header(fp, "Memories used in FPGA"); 
 
-  print_verilog_include_defines_preproc_file(fp, verilog_dir);
-  
   /* Create the memory circuits for the multiplexer */
   for (auto mux : mux_lib.muxes()) {
     const MuxGraph& mux_graph = mux_lib.mux_graph(mux);
diff --git a/openfpga/src/fpga_verilog/verilog_memory.h b/openfpga/src/fpga_verilog/verilog_memory.h
index a331e5687..f489df2ad 100644
--- a/openfpga/src/fpga_verilog/verilog_memory.h
+++ b/openfpga/src/fpga_verilog/verilog_memory.h
@@ -23,7 +23,6 @@ void print_verilog_submodule_memories(const ModuleManager& module_manager,
                                       NetlistManager& netlist_manager,
                                       const MuxLibrary& mux_lib,
                                       const CircuitLibrary& circuit_lib,
-                                      const std::string& verilog_dir,
                                       const std::string& submodule_dir,
                                       const bool& use_explicit_port_map);
 
diff --git a/openfpga/src/fpga_verilog/verilog_mux.cpp b/openfpga/src/fpga_verilog/verilog_mux.cpp
index c85978722..3b7d3300b 100644
--- a/openfpga/src/fpga_verilog/verilog_mux.cpp
+++ b/openfpga/src/fpga_verilog/verilog_mux.cpp
@@ -1227,7 +1227,6 @@ void print_verilog_submodule_muxes(ModuleManager& module_manager,
                                    NetlistManager& netlist_manager,
                                    const MuxLibrary& mux_lib,
                                    const CircuitLibrary& circuit_lib,
-                                   const std::string& verilog_dir,
                                    const std::string& submodule_dir,
                                    const bool& use_explicit_port_map) {
 
@@ -1245,8 +1244,6 @@ void print_verilog_submodule_muxes(ModuleManager& module_manager,
 
   print_verilog_file_header(fp, "Multiplexers"); 
 
-  print_verilog_include_defines_preproc_file(fp, verilog_dir);
-  
   /* Generate basis sub-circuit for unique branches shared by the multiplexers */
   for (auto mux : mux_lib.muxes()) {
     const MuxGraph& mux_graph = mux_lib.mux_graph(mux);
diff --git a/openfpga/src/fpga_verilog/verilog_mux.h b/openfpga/src/fpga_verilog/verilog_mux.h
index c98fa77d0..361c394dc 100644
--- a/openfpga/src/fpga_verilog/verilog_mux.h
+++ b/openfpga/src/fpga_verilog/verilog_mux.h
@@ -24,7 +24,6 @@ void print_verilog_submodule_muxes(ModuleManager& module_manager,
                                    NetlistManager& netlist_manager,
                                    const MuxLibrary& mux_lib,
                                    const CircuitLibrary& circuit_lib,
-                                   const std::string& verilog_dir,
                                    const std::string& submodule_dir,
                                    const bool& use_explicit_port_map);
 
diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
index 695d9275f..8e1de5cfc 100644
--- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
+++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
@@ -385,8 +385,7 @@ void print_verilog_preconfig_top_module(const ModuleManager& module_manager,
                                         const IoLocationMap& io_location_map,
                                         const VprNetlistAnnotation& netlist_annotation, 
                                         const std::string& circuit_name,
-                                        const std::string& verilog_fname,
-                                        const std::string& verilog_dir) {
+                                        const std::string& verilog_fname) {
   std::string timer_message = std::string("Write pre-configured FPGA top-level Verilog netlist for design '") + circuit_name + std::string("'");
 
   /* Start time count */
@@ -403,11 +402,6 @@ void print_verilog_preconfig_top_module(const ModuleManager& module_manager,
   std::string title = std::string("Verilog netlist for pre-configured FPGA fabric by design: ") + circuit_name;
   print_verilog_file_header(fp, title); 
 
-  /* Print preprocessing flags and external netlists */
-  print_verilog_include_defines_preproc_file(fp, verilog_dir);
-
-  print_verilog_include_netlist(fp, std::string(verilog_dir + std::string(DEFINES_VERILOG_SIMULATION_FILE_NAME)));  
-
   /* Print module declaration and ports */
   print_verilog_preconfig_top_module_ports(fp, circuit_name, atom_ctx, netlist_annotation);
 
diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.h b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.h
index 499cafea9..e8efe5f29 100644
--- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.h
+++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.h
@@ -29,8 +29,7 @@ void print_verilog_preconfig_top_module(const ModuleManager& module_manager,
                                         const IoLocationMap& io_location_map,
                                         const VprNetlistAnnotation& netlist_annotation, 
                                         const std::string& circuit_name,
-                                        const std::string& verilog_fname,
-                                        const std::string& verilog_dir);
+                                        const std::string& verilog_fname);
 
 } /* end namespace openfpga */
 
diff --git a/openfpga/src/fpga_verilog/verilog_routing.cpp b/openfpga/src/fpga_verilog/verilog_routing.cpp
index 8f74c0074..e6df8e858 100644
--- a/openfpga/src/fpga_verilog/verilog_routing.cpp
+++ b/openfpga/src/fpga_verilog/verilog_routing.cpp
@@ -77,7 +77,6 @@ namespace openfpga {
 static 
 void print_verilog_routing_connection_box_unique_module(NetlistManager& netlist_manager,
                                                         const ModuleManager& module_manager, 
-                                                        const std::string& verilog_dir, 
                                                         const std::string& subckt_dir, 
                                                         const RRGSB& rr_gsb,
                                                         const t_rr_type& cb_type,
@@ -94,9 +93,6 @@ void print_verilog_routing_connection_box_unique_module(NetlistManager& netlist_
 
   print_verilog_file_header(fp, std::string("Verilog modules for Unique Connection Blocks[" + std::to_string(rr_gsb.get_cb_x(cb_type)) + "]["+ std::to_string(rr_gsb.get_cb_y(cb_type)) + "]")); 
 
-  /* Print preprocessing flags */
-  print_verilog_include_defines_preproc_file(fp, verilog_dir);
-
   /* Create a Verilog Module based on the circuit model, and add to module manager */
   ModuleId cb_module = module_manager.find_module(generate_connection_block_module_name(cb_type, gsb_coordinate)); 
   VTR_ASSERT(true == module_manager.valid_module_id(cb_module));
@@ -182,7 +178,6 @@ void print_verilog_routing_connection_box_unique_module(NetlistManager& netlist_
 static 
 void print_verilog_routing_switch_box_unique_module(NetlistManager& netlist_manager,
                                                     const ModuleManager& module_manager, 
-                                                    const std::string& verilog_dir, 
                                                     const std::string& subckt_dir, 
                                                     const RRGSB& rr_gsb,
                                                     const bool& use_explicit_port_map) {
@@ -198,9 +193,6 @@ void print_verilog_routing_switch_box_unique_module(NetlistManager& netlist_mana
 
   print_verilog_file_header(fp, std::string("Verilog modules for Unique Switch Blocks[" + std::to_string(rr_gsb.get_sb_x()) + "]["+ std::to_string(rr_gsb.get_sb_y()) + "]")); 
 
-  /* Print preprocessing flags */
-  print_verilog_include_defines_preproc_file(fp, verilog_dir);
-
   /* Create a Verilog Module based on the circuit model, and add to module manager */
   ModuleId sb_module = module_manager.find_module(generate_switch_block_module_name(gsb_coordinate)); 
   VTR_ASSERT(true == module_manager.valid_module_id(sb_module));
@@ -225,7 +217,6 @@ static
 void print_verilog_flatten_connection_block_modules(NetlistManager& netlist_manager,
                                                     const ModuleManager& module_manager, 
                                                     const DeviceRRGSB& device_rr_gsb,
-                                                    const std::string& verilog_dir,
                                                     const std::string& subckt_dir,
                                                     const t_rr_type& cb_type,
                                                     const bool& use_explicit_port_map) {
@@ -244,7 +235,6 @@ void print_verilog_flatten_connection_block_modules(NetlistManager& netlist_mana
       }
       print_verilog_routing_connection_box_unique_module(netlist_manager, 
                                                          module_manager,
-                                                         verilog_dir,
                                                          subckt_dir, 
                                                          rr_gsb, cb_type,  
                                                          use_explicit_port_map);
@@ -264,7 +254,6 @@ void print_verilog_flatten_connection_block_modules(NetlistManager& netlist_mana
 void print_verilog_flatten_routing_modules(NetlistManager& netlist_manager,
                                            const ModuleManager& module_manager,
                                            const DeviceRRGSB& device_rr_gsb,
-                                           const std::string& verilog_dir,
                                            const std::string& subckt_dir,
                                            const bool& use_explicit_port_map) {
   /* Create a vector to contain all the Verilog netlist names that have been generated in this function */
@@ -281,16 +270,15 @@ void print_verilog_flatten_routing_modules(NetlistManager& netlist_manager,
       }
       print_verilog_routing_switch_box_unique_module(netlist_manager,
                                                      module_manager, 
-                                                     verilog_dir,
                                                      subckt_dir, 
                                                      rr_gsb, 
                                                      use_explicit_port_map);
     }
   }
 
-  print_verilog_flatten_connection_block_modules(netlist_manager, module_manager, device_rr_gsb, verilog_dir, subckt_dir, CHANX, use_explicit_port_map);
+  print_verilog_flatten_connection_block_modules(netlist_manager, module_manager, device_rr_gsb, subckt_dir, CHANX, use_explicit_port_map);
 
-  print_verilog_flatten_connection_block_modules(netlist_manager, module_manager, device_rr_gsb, verilog_dir, subckt_dir, CHANY, use_explicit_port_map);
+  print_verilog_flatten_connection_block_modules(netlist_manager, module_manager, device_rr_gsb, subckt_dir, CHANY, use_explicit_port_map);
 
   /*
   VTR_LOG("Writing header file for routing submodules '%s'...",
@@ -317,7 +305,6 @@ void print_verilog_flatten_routing_modules(NetlistManager& netlist_manager,
 void print_verilog_unique_routing_modules(NetlistManager& netlist_manager,
                                           const ModuleManager& module_manager,
                                           const DeviceRRGSB& device_rr_gsb,
-                                          const std::string& verilog_dir,
                                           const std::string& subckt_dir,
                                           const bool& use_explicit_port_map) {
   /* Create a vector to contain all the Verilog netlist names that have been generated in this function */
@@ -328,7 +315,6 @@ void print_verilog_unique_routing_modules(NetlistManager& netlist_manager,
     const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(isb);
     print_verilog_routing_switch_box_unique_module(netlist_manager,
                                                    module_manager,
-                                                   verilog_dir,
                                                    subckt_dir, 
                                                    unique_mirror, 
                                                    use_explicit_port_map);
@@ -340,7 +326,6 @@ void print_verilog_unique_routing_modules(NetlistManager& netlist_manager,
 
     print_verilog_routing_connection_box_unique_module(netlist_manager,
                                                        module_manager,
-                                                       verilog_dir,
                                                        subckt_dir, 
                                                        unique_mirror, CHANX,  
                                                        use_explicit_port_map);
@@ -352,7 +337,6 @@ void print_verilog_unique_routing_modules(NetlistManager& netlist_manager,
 
     print_verilog_routing_connection_box_unique_module(netlist_manager, 
                                                        module_manager,
-                                                       verilog_dir,
                                                        subckt_dir, 
                                                        unique_mirror, CHANY,  
                                                        use_explicit_port_map);
diff --git a/openfpga/src/fpga_verilog/verilog_routing.h b/openfpga/src/fpga_verilog/verilog_routing.h
index a9f8fd6a1..9d439053a 100644
--- a/openfpga/src/fpga_verilog/verilog_routing.h
+++ b/openfpga/src/fpga_verilog/verilog_routing.h
@@ -20,14 +20,12 @@ namespace openfpga {
 void print_verilog_flatten_routing_modules(NetlistManager& netlist_manager,
                                            const ModuleManager& module_manager,
                                            const DeviceRRGSB& device_rr_gsb,
-                                           const std::string& verilog_dir,
                                            const std::string& subckt_dir,
                                            const bool& use_explicit_port_map);
 
 void print_verilog_unique_routing_modules(NetlistManager& netlist_manager,
                                           const ModuleManager& module_manager,
                                           const DeviceRRGSB& device_rr_gsb,
-                                          const std::string& verilog_dir,
                                           const std::string& subckt_dir,
                                           const bool& use_explicit_port_map);
 
diff --git a/openfpga/src/fpga_verilog/verilog_submodule.cpp b/openfpga/src/fpga_verilog/verilog_submodule.cpp
index b38750ab9..37df77c60 100644
--- a/openfpga/src/fpga_verilog/verilog_submodule.cpp
+++ b/openfpga/src/fpga_verilog/verilog_submodule.cpp
@@ -35,7 +35,6 @@ void print_verilog_submodule(ModuleManager& module_manager,
                              NetlistManager& netlist_manager,
                              const MuxLibrary& mux_lib,
                              const CircuitLibrary& circuit_lib, 
-                             const std::string& verilog_dir, 
                              const std::string& submodule_dir, 
                              const FabricVerilogOption& fpga_verilog_opts) {
 
@@ -47,7 +46,6 @@ void print_verilog_submodule(ModuleManager& module_manager,
 
   print_verilog_submodule_essentials(const_cast<const ModuleManager&>(module_manager), 
                                      netlist_manager,
-                                     verilog_dir, 
                                      submodule_dir,
                                      circuit_lib);
 
@@ -58,35 +56,35 @@ void print_verilog_submodule(ModuleManager& module_manager,
   print_verilog_submodule_mux_local_decoders(const_cast<const ModuleManager&>(module_manager),
                                              netlist_manager, 
                                              mux_lib, circuit_lib, 
-                                             verilog_dir, submodule_dir);
+                                             submodule_dir);
   print_verilog_submodule_muxes(module_manager, netlist_manager, mux_lib, circuit_lib,
-                                verilog_dir, submodule_dir,
+                                submodule_dir,
                                 fpga_verilog_opts.explicit_port_mapping());
 
  
   /* LUTes */
   print_verilog_submodule_luts(const_cast<const ModuleManager&>(module_manager),
                                netlist_manager, circuit_lib,
-                               verilog_dir, submodule_dir,
+                               submodule_dir,
                                fpga_verilog_opts.explicit_port_mapping());
 
   /* Hard wires */
   print_verilog_submodule_wires(const_cast<const ModuleManager&>(module_manager),
                                 netlist_manager, circuit_lib,
-                                verilog_dir, submodule_dir);
+                                submodule_dir);
 
   /* 4. Memories */
   print_verilog_submodule_memories(const_cast<const ModuleManager&>(module_manager),
                                    netlist_manager,
                                    mux_lib, circuit_lib, 
-                                   verilog_dir, submodule_dir,
+                                   submodule_dir,
                                    fpga_verilog_opts.explicit_port_mapping());
 
   /* 5. Dump template for all the modules */
   if (true == fpga_verilog_opts.print_user_defined_template()) { 
     print_verilog_submodule_templates(const_cast<const ModuleManager&>(module_manager),
                                       circuit_lib,
-                                      verilog_dir, submodule_dir);
+                                      submodule_dir);
   }
 
   /* Create a header file to include all the subckts */
diff --git a/openfpga/src/fpga_verilog/verilog_submodule.h b/openfpga/src/fpga_verilog/verilog_submodule.h
index d3de8b9d7..06bb7aeef 100644
--- a/openfpga/src/fpga_verilog/verilog_submodule.h
+++ b/openfpga/src/fpga_verilog/verilog_submodule.h
@@ -20,7 +20,6 @@ void print_verilog_submodule(ModuleManager& module_manager,
                              NetlistManager& netlist_manager,
                              const MuxLibrary& mux_lib,
                              const CircuitLibrary& circuit_lib, 
-                             const std::string& verilog_dir, 
                              const std::string& submodule_dir, 
                              const FabricVerilogOption& fpga_verilog_opts);
 
diff --git a/openfpga/src/fpga_verilog/verilog_submodule_utils.cpp b/openfpga/src/fpga_verilog/verilog_submodule_utils.cpp
index b4255b3e9..faf965068 100644
--- a/openfpga/src/fpga_verilog/verilog_submodule_utils.cpp
+++ b/openfpga/src/fpga_verilog/verilog_submodule_utils.cpp
@@ -207,7 +207,6 @@ void print_one_verilog_template_module(const ModuleManager& module_manager,
  ********************************************************************/
 void print_verilog_submodule_templates(const ModuleManager& module_manager,
                                        const CircuitLibrary& circuit_lib,
-                                       const std::string& verilog_dir,
                                        const std::string& submodule_dir) {
   std::string verilog_fname(submodule_dir + USER_DEFINED_TEMPLATE_VERILOG_FILE_NAME);
 
@@ -223,8 +222,6 @@ void print_verilog_submodule_templates(const ModuleManager& module_manager,
 
   print_verilog_file_header(fp, "Template for user-defined Verilog modules"); 
 
-  print_verilog_include_defines_preproc_file(fp, verilog_dir);
-
   /* Output essential models*/
   for (const auto& model : circuit_lib.models()) {
     /* Focus on user-defined modules, which must have a Verilog netlist defined */
diff --git a/openfpga/src/fpga_verilog/verilog_submodule_utils.h b/openfpga/src/fpga_verilog/verilog_submodule_utils.h
index fedcb63a8..3f0e1dadd 100644
--- a/openfpga/src/fpga_verilog/verilog_submodule_utils.h
+++ b/openfpga/src/fpga_verilog/verilog_submodule_utils.h
@@ -29,7 +29,6 @@ void add_user_defined_verilog_modules(ModuleManager& module_manager,
 
 void print_verilog_submodule_templates(const ModuleManager& module_manager,
                                        const CircuitLibrary& circuit_lib,
-                                       const std::string& verilog_dir,
                                        const std::string& submodule_dir);
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/fpga_verilog/verilog_top_module.cpp b/openfpga/src/fpga_verilog/verilog_top_module.cpp
index 9596f20a3..79c6ebebe 100644
--- a/openfpga/src/fpga_verilog/verilog_top_module.cpp
+++ b/openfpga/src/fpga_verilog/verilog_top_module.cpp
@@ -58,9 +58,6 @@ void print_verilog_top_module(NetlistManager& netlist_manager,
 
   print_verilog_file_header(fp, std::string("Top-level Verilog module for FPGA")); 
 
-  /* Print preprocessing flags */
-  print_verilog_include_defines_preproc_file(fp, verilog_dir);
-
   /* Write the module content in Verilog format */
   write_verilog_module_to_file(fp, module_manager, top_module, use_explicit_mapping);
 
diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
index 25017d741..a477fa99e 100644
--- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
@@ -799,7 +799,6 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
                                  const VprNetlistAnnotation& netlist_annotation,
                                  const std::string& circuit_name,
                                  const std::string& verilog_fname,
-                                 const std::string& verilog_dir,
                                  const SimulationSetting& simulation_parameters) {
 
   std::string timer_message = std::string("Write autocheck testbench for FPGA top-level Verilog netlist for '") + circuit_name + std::string("'");
@@ -818,9 +817,6 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
   std::string title = std::string("FPGA Verilog Testbench for Top-level netlist of Design: ") + circuit_name;
   print_verilog_file_header(fp, title); 
 
-  /* Print preprocessing flags and external netlists */
-  print_verilog_include_defines_preproc_file(fp, verilog_dir);
-
   /* Find the top_module */
   ModuleId top_module = module_manager.find_module(generate_fpga_top_module_name());
   VTR_ASSERT(true == module_manager.valid_module_id(top_module));
diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.h b/openfpga/src/fpga_verilog/verilog_top_testbench.h
index 5684b37e2..c0ad77c51 100644
--- a/openfpga/src/fpga_verilog/verilog_top_testbench.h
+++ b/openfpga/src/fpga_verilog/verilog_top_testbench.h
@@ -33,7 +33,6 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
                                  const VprNetlistAnnotation& netlist_annotation, 
                                  const std::string& circuit_name,
                                  const std::string& verilog_fname,
-                                 const std::string& verilog_dir,
                                  const SimulationSetting& simulation_parameters);
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/fpga_verilog/verilog_wire.cpp b/openfpga/src/fpga_verilog/verilog_wire.cpp
index d28b26f81..bb8419edd 100644
--- a/openfpga/src/fpga_verilog/verilog_wire.cpp
+++ b/openfpga/src/fpga_verilog/verilog_wire.cpp
@@ -95,7 +95,6 @@ void print_verilog_wire_module(const ModuleManager& module_manager,
 void print_verilog_submodule_wires(const ModuleManager& module_manager,
                                    NetlistManager& netlist_manager,
                                    const CircuitLibrary& circuit_lib,
-                                   const std::string& verilog_dir,
                                    const std::string& submodule_dir) {
   std::string verilog_fname(submodule_dir + std::string(WIRES_VERILOG_FILE_NAME));
 
@@ -111,8 +110,6 @@ void print_verilog_submodule_wires(const ModuleManager& module_manager,
 
   print_verilog_file_header(fp, "Wires"); 
 
-  print_verilog_include_defines_preproc_file(fp, verilog_dir);
-
   /* Print Verilog models for regular wires*/
   print_verilog_comment(fp, std::string("----- BEGIN Verilog modules for regular wires -----"));
   for (const auto& model : circuit_lib.models_by_type(CIRCUIT_MODEL_WIRE)) { 
diff --git a/openfpga/src/fpga_verilog/verilog_wire.h b/openfpga/src/fpga_verilog/verilog_wire.h
index 62331d8b9..d9996fbcf 100644
--- a/openfpga/src/fpga_verilog/verilog_wire.h
+++ b/openfpga/src/fpga_verilog/verilog_wire.h
@@ -21,7 +21,6 @@ namespace openfpga {
 void print_verilog_submodule_wires(const ModuleManager& module_manager,
                                    NetlistManager& netlist_manager,
                                    const CircuitLibrary& circuit_lib,
-                                   const std::string& verilog_dir,
                                    const std::string& submodule_dir);
 
 } /* end namespace openfpga */

From 890ead91b95ef1f6caea64157a5b38be3be07d8c Mon Sep 17 00:00:00 2001
From: ganeshgore <goreganesh007@gmail.com>
Date: Fri, 24 Apr 2020 21:53:57 -0600
Subject: [PATCH 479/645] Fixed modelsim include references

---
 openfpga_flow/misc/modelsim_runsim.tcl | 12 +------
 openfpga_flow/scripts/run_modelsim.py  | 43 +++++++++++++++++++-------
 2 files changed, 32 insertions(+), 23 deletions(-)

diff --git a/openfpga_flow/misc/modelsim_runsim.tcl b/openfpga_flow/misc/modelsim_runsim.tcl
index 64578d883..a7734bae0 100644
--- a/openfpga_flow/misc/modelsim_runsim.tcl
+++ b/openfpga_flow/misc/modelsim_runsim.tcl
@@ -11,27 +11,17 @@ set simtime ${SIMTIME}
 set unit ${UNIT}
 
 #Path were both tcl script are located
-set verilog_path ${VERILOG_PATH}
 set project_path "${MODELSIM_PROJ_DIR}/msim_projects/"
 
 #Path were the verilog files are located
-set verilog_path ${VERILOG_PATH}
-
-set verilog_files [list \
-  ${VERILOG_PATH}${VERILOG_FILE1} \
-  ${VERILOG_PATH}${VERILOG_FILE2} \
-  ${VERILOG_PATH}fpga_defines.v
-  ]
+set verilog_files ${VERILOG_PATH}/*_include_netlists_resolved.v
 
 #Source the tcl script
 source ${MODELSIM_PROJ_DIR}/${BENCHMARK}_autocheck_proc.tcl
 
 #Execute the top level procedure
-
 try {
   top_create_new_project $$projectname $$verilog_files $$project_path $$simtime $$unit $$top_tb
 } finally {
    quit
 }
-
-#Relaunch simulation
diff --git a/openfpga_flow/scripts/run_modelsim.py b/openfpga_flow/scripts/run_modelsim.py
index 077b84e61..564ca504d 100644
--- a/openfpga_flow/scripts/run_modelsim.py
+++ b/openfpga_flow/scripts/run_modelsim.py
@@ -104,7 +104,7 @@ def main():
         logfile_path = os.path.join(gc["task_dir"],
                                     taskname, task_run, "modelsim_run.log")
         resultfile_path = os.path.join(gc["task_dir"],
-                                    taskname, task_run, "modelsim_result.csv")
+                                       taskname, task_run, "modelsim_result.csv")
         logfilefh = logging.FileHandler(logfile_path, "w")
         logfilefh.setFormatter(logging.Formatter(FILE_LOG_FORMAT))
         logger.addHandler(logfilefh)
@@ -129,7 +129,8 @@ def main():
                         task_ini_files.append(INIfile)
         logger.info(f"Found {len(task_ini_files)} INI files")
         results = create_tcl_script(task_ini_files)
-        collect_result(resultfile_path, results)
+        if args.run_sim:
+            collect_result(resultfile_path, results)
 
 
 def clean_up_and_exit(msg):
@@ -168,7 +169,21 @@ def create_tcl_script(files):
 
         config["MODELSIM_PROJ_NAME"] = args.modelsim_proj_name
         config["MODELSIM_INI"] = args.modelsim_ini
-
+        config["VERILOG_PATH"] = os.path.join(
+            os.getcwd(), config["VERILOG_PATH"])
+        IncludeFile = os.path.join(
+            os.getcwd(),
+            config["VERILOG_PATH"],
+            config["VERILOG_FILE2"])
+        IncludeFileResolved = os.path.join(
+            os.getcwd(),
+            config["VERILOG_PATH"],
+            config["VERILOG_FILE2"].replace(".v", "_resolved.v"))
+        with open(IncludeFileResolved, "w") as fpw:
+            with open(IncludeFile, "r") as fp:
+                for eachline in fp.readlines():
+                    eachline = eachline.replace("./SRC", "../../../SRC/")
+                    fpw.write(eachline)
         # Modify the variables in config file here
         config["TOP_TB"] = os.path.splitext(config["TOP_TB"])[0]
 
@@ -193,13 +208,13 @@ def create_tcl_script(files):
             "ini_file": eachFile,
             "modelsim_run_dir": args.modelsim_run_dir,
             "runsim_filename": runsim_filename,
-            "run_complete" :False,
+            "run_complete": False,
             "status": False,
-            "finished" : True,
-            "starttime" : 0,
-            "endtime" : 0,
+            "finished": True,
+            "starttime": 0,
+            "endtime": 0,
             "Errors": 0,
-            "Warnings" : 0
+            "Warnings": 0
         })
     # Execute modelsim
     if args.run_sim:
@@ -229,7 +244,7 @@ def run_modelsim_thread(s, eachJob, job_list):
         thread_name = threading.currentThread().getName()
         eachJob["starttime"] = time.time()
         eachJob["Errors"] = 0
-        eachJob["Warnings"]= 0
+        eachJob["Warnings"] = 0
         try:
             logfile = "%s_modelsim.log" % thread_name
             eachJob["logfile"] = "<task_dir>" + \
@@ -248,7 +263,8 @@ def run_modelsim_thread(s, eachJob, job_list):
                 for line in process.stdout:
                     if "Errors" in line:
                         logger.info(line.strip())
-                        e,w = re.match("# .*: ([0-9].*), .*: ([0-9].*)", line).groups()
+                        e, w = re.match(
+                            "# .*: ([0-9].*), .*: ([0-9].*)", line).groups()
                         eachJob["Errors"] += int(e)
                         eachJob["Warnings"] += int(w)
                     sys.stdout.buffer.flush()
@@ -275,8 +291,10 @@ def run_modelsim_thread(s, eachJob, job_list):
         no_of_finished_job = sum([not eachJ["finished"] for eachJ in job_list])
         logger.info("***** %d runs pending *****" % (no_of_finished_job))
 
+
 def collect_result(result_file, result_obj):
-    colnames = ["status", "Errors", "Warnings", "run_complete", "exectime", "finished", "logfile"]
+    colnames = ["status", "Errors", "Warnings",
+                "run_complete", "exectime", "finished", "logfile"]
     if len(result_obj):
         with open(result_file, 'w', newline='') as csvfile:
             writer = csv.DictWriter(
@@ -285,11 +303,12 @@ def collect_result(result_file, result_obj):
             for eachResult in result_obj:
                 writer.writerow(eachResult)
     logger.info("= = = ="*10)
-    passed_jobs = [ each["status"] for each in result_obj ]
+    passed_jobs = [each["status"] for each in result_obj]
     logger.info(f"Passed Jobs %d/%d", len(passed_jobs), len(result_obj))
     logger.info(f"Result file stored at {result_file}")
     logger.info("= = = ="*10)
 
+
 if __name__ == "__main__":
     if args.debug:
         logger.info("Setting loggger in debug mode")

From 49edeb119c380e07c41bf19ea74089f92a579d58 Mon Sep 17 00:00:00 2001
From: ganeshgore <goreganesh007@gmail.com>
Date: Sat, 25 Apr 2020 20:16:17 -0600
Subject: [PATCH 480/645] BugFix : Relative path for refrence benchmark fixed

---
 .../OpenFPGAShellScripts/mcnc_example_script.openfpga       | 6 +++---
 openfpga_flow/scripts/run_modelsim.py                       | 2 +-
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga
index 9a4f577f8..ba086855e 100644
--- a/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga
@@ -40,8 +40,8 @@ build_fabric_bitstream --verbose
 write_fabric_verilog --file ./SRC \
   --explicit_port_mapping \
   --include_timing \
-  --include_signal_init 
-  #--support_icarus_simulator 
+  --include_signal_init
+  #--support_icarus_simulator
 
 # Write the Verilog testbench for FPGA fabric
 #  - We suggest the use of same output directory as fabric Verilog netlists
@@ -49,7 +49,7 @@ write_fabric_verilog --file ./SRC \
 #  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./simulation_deck_info.ini
+write_verilog_testbench --file ./SRC --reference_benchmark_file_path ./${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./simulation_deck_info.ini
 
 # Write the SDC files for PnR backend
 #  - Turn on every options here
diff --git a/openfpga_flow/scripts/run_modelsim.py b/openfpga_flow/scripts/run_modelsim.py
index 564ca504d..4151ebd4b 100644
--- a/openfpga_flow/scripts/run_modelsim.py
+++ b/openfpga_flow/scripts/run_modelsim.py
@@ -182,7 +182,7 @@ def create_tcl_script(files):
         with open(IncludeFileResolved, "w") as fpw:
             with open(IncludeFile, "r") as fp:
                 for eachline in fp.readlines():
-                    eachline = eachline.replace("./SRC", "../../../SRC/")
+                    eachline = eachline.replace("\"./", "\"../../../")
                     fpw.write(eachline)
         # Modify the variables in config file here
         config["TOP_TB"] = os.path.splitext(config["TOP_TB"])[0]

From c31b20dc91cee0a333f4b5a6a3eea01ee1ff55e6 Mon Sep 17 00:00:00 2001
From: ganeshgore <goreganesh007@gmail.com>
Date: Wed, 10 Jun 2020 23:12:30 -0600
Subject: [PATCH 481/645] Added support for simulation setting file in the task
 flow

---
 openfpga_flow/scripts/run_fpga_flow.py        |  3 ++
 openfpga_flow/scripts/run_fpga_task.py        |  2 +
 .../mcnc_big20/config/task.conf               | 47 ++++++++++---------
 3 files changed, 29 insertions(+), 23 deletions(-)

diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py
index cee4ec2ce..fcf47ee44 100644
--- a/openfpga_flow/scripts/run_fpga_flow.py
+++ b/openfpga_flow/scripts/run_fpga_flow.py
@@ -83,6 +83,8 @@ parser.add_argument('--openfpga_shell_template', type=str,
                     help="Sample openfpga shell script")
 parser.add_argument('--openfpga_arch_file', type=str,
                     help="Openfpga architecture file for shell")
+parser.add_argument('--openfpga_sim_setting_file', type=str,
+                    help="Openfpga simulation file for shell")
 parser.add_argument('--yosys_tmpl', type=str,
                     help="Alternate yosys template, generates top_module.blif")
 parser.add_argument('--disp', action="store_true",
@@ -683,6 +685,7 @@ def run_openfpga_shell():
     path_variables = script_env_vars["PATH"]
     path_variables["VPR_ARCH_FILE"] = args.arch_file
     path_variables["OPENFPGA_ARCH_FILE"] = args.openfpga_arch_file
+    path_variables["OPENFPGA_SIM_SETTING_FILE"] = args.openfpga_sim_setting_file
     path_variables["VPR_TESTBENCH_BLIF"] = args.top_module+".blif"
     path_variables["ACTIVITY_FILE"] = args.top_module+"_ace_out.act"
     path_variables["REFERENCE_VERILOG_TESTBENCH"] = args.top_module + \
diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py
index 9567c4fe5..3361a3082 100644
--- a/openfpga_flow/scripts/run_fpga_task.py
+++ b/openfpga_flow/scripts/run_fpga_task.py
@@ -355,6 +355,8 @@ def create_run_command(curr_job_dir, archfile, benchmark_obj, param, task_conf):
                     task_gc.get("openfpga_shell_template")]
         command += ["--openfpga_arch_file",
                     task_gc.get("openfpga_arch_file")]
+        command += ["--openfpga_sim_setting_file",
+                    task_gc.get("openfpga_sim_setting_file")]
 
     if benchmark_obj.get("activity_file"):
         command += ["--activity_file", benchmark_obj.get("activity_file")]
diff --git a/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf b/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf
index 5028283fb..149c0695b 100644
--- a/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf
@@ -16,12 +16,13 @@ verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml
 
 [BENCHMARKS]
-#bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif 
+#bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif
 #bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif
 #bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.blif
 ## VPR remove buffers which are in act file and create a new net. Then VPR errors out by saying the new net does not exist in act file
@@ -39,91 +40,91 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_ti
 #bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.blif
 #bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.blif
 ## Passed
-bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.blif 
-#bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.blif 
+bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.blif
+# bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.blif
 #bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.blif
 #bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.blif
 #bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.blif
 #bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.blif
 
 [SYNTHESIS_PARAM]
-# Benchmark alu4 
+# Benchmark alu4
 bench0_top = alu4
 bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.act
 bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.v
-# Benchmark apex2 
+# Benchmark apex2
 bench1_top = apex2
 bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.act
 bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.v
-# Benchmark apex4 
+# Benchmark apex4
 bench2_top = apex4
 bench2_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.act
 bench2_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.v
-# Benchmark bigkey 
+# Benchmark bigkey
 bench3_top = bigkey
 bench3_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.act
 bench3_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.v
-# Benchmark clma 
+# Benchmark clma
 bench4_top = clma
 bench4_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.act
 bench4_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.v
-# Benchmark des 
+# Benchmark des
 bench5_top = des
 bench5_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.act
 bench5_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.v
-# Benchmark diffeq 
+# Benchmark diffeq
 bench6_top = diffeq
 bench6_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.act
 bench6_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.v
-# Benchmark dsip 
+# Benchmark dsip
 bench7_top = dsip
 bench7_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.act
 bench7_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.v
-# Benchmark elliptic 
+# Benchmark elliptic
 bench8_top = elliptic
 bench8_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.act
 bench8_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.v
-# Benchmark ex1010 
+# Benchmark ex1010
 bench9_top = ex1010
 bench9_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.act
 bench9_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.v
-# Benchmark ex5p 
+# Benchmark ex5p
 bench10_top = ex5p
 bench10_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.act
 bench10_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.v
-# Benchmark frisc 
+# Benchmark frisc
 bench11_top = frisc
 bench11_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.act
 bench11_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.v
-# Benchmark misex3 
+# Benchmark misex3
 bench12_top = misex3
 bench12_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.act
 bench12_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.v
-# Benchmark pdc 
+# Benchmark pdc
 bench13_top = pdc
 bench13_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.act
 bench13_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.v
-# Benchmark s298 
+# Benchmark s298
 bench14_top = s298
 bench14_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.act
 bench14_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.v
-# Benchmark s38417 
+# Benchmark s38417
 bench15_top = s38417
 bench15_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.act
 bench15_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.v
-# Benchmark s38584 
+# Benchmark s38584
 bench16_top = s38584
 bench16_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.act
 bench16_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.v
-# Benchmark seq 
+# Benchmark seq
 bench17_top = seq
 bench17_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.act
 bench17_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.v
-# Benchmark spla 
+# Benchmark spla
 bench18_top = spla
 bench18_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.act
 bench18_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.v
-# Benchmark tseng 
+# Benchmark tseng
 bench19_top = tseng
 bench19_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.act
 bench19_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.v

From 9bf91bd92a78b10823f0038653bf58c0a5c5f141 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 25 Apr 2020 20:18:10 -0600
Subject: [PATCH 482/645] start testing mcnc_big20 using OpenFPGA tasks

---
 .../mcnc_big20/config/task.conf               | 48 +++++++++----------
 1 file changed, 24 insertions(+), 24 deletions(-)

diff --git a/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf b/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf
index 149c0695b..5532a0888 100644
--- a/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf
@@ -22,30 +22,30 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml
 
 [BENCHMARKS]
-#bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif
-#bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif
-#bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.blif
-## VPR remove buffers which are in act file and create a new net. Then VPR errors out by saying the new net does not exist in act file
-#bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.blif
-## VPR remove buffers which are in act file and create a new net. Then VPR errors out by saying the new net does not exist in act file
-#bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.blif
-#bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.blif
-#bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.blif
-## VPR remove buffers which are in act file and create a new net. Then VPR errors out by saying the new net does not exist in act file
-#bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.blif
-#bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.blif
-#bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.blif
-#bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.blif
-#bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.blif
-#bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.blif
-#bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.blif
-## Passed
-bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.blif
-# bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.blif
-#bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.blif
-#bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.blif
-#bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.blif
-#bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif 
+bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif
+bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.blif
+# VPR remove buffers which are in act file and create a new net. Then VPR errors out by saying the new net does not exist in act file
+bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.blif
+# VPR remove buffers which are in act file and create a new net. Then VPR errors out by saying the new net does not exist in act file
+bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.blif
+bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.blif
+bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.blif
+# VPR remove buffers which are in act file and create a new net. Then VPR errors out by saying the new net does not exist in act file
+bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.blif
+bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.blif
+bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.blif
+bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.blif
+bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.blif
+bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.blif
+bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.blif
+# Passed
+bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.blif 
+bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.blif 
+bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.blif
+bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.blif
+bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.blif
+bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.blif
 
 [SYNTHESIS_PARAM]
 # Benchmark alu4

From a3fe6a9fcbfc5560ad8ffebde27c17d14bbd5db8 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 28 Apr 2020 18:16:52 -0600
Subject: [PATCH 483/645] update travis script with example run on MCNC big20

---
 .travis/script.sh | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/.travis/script.sh b/.travis/script.sh
index 231437e28..60c3d0715 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -105,4 +105,10 @@ python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/duplicated_grid_pi
 echo -e "Testing Verilog generation with spy output pads";
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/spypad --debug --show_thread_logs
 
+# Verify MCNC big20 benchmark suite with ModelSim 
+# Please make sure you have ModelSim installed in the environment
+# Otherwise, it will fail
+#python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/mcnc_big20 --debug --show_thread_logs --maxthreads 20
+#python3 openfpga_flow/scripts/run_modelsim.py openfpga_shell/mcnc_big20 --run_sim 
+
 end_section "OpenFPGA.TaskTun"

From 42cede37fa4d3c432092d36ce4073ce99b9a8477 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 28 Apr 2020 18:22:41 -0600
Subject: [PATCH 484/645] add testcases on generate fabric/testbench only

---
 .../generate_fabric_example_script.openfpga   | 32 +++++++++++
 ...generate_testbench_example_script.openfpga | 53 +++++++++++++++++++
 .../generate_fabric/config/task.conf          | 31 +++++++++++
 .../generate_testbench/config/task.conf       | 31 +++++++++++
 4 files changed, 147 insertions(+)
 create mode 100644 openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga
 create mode 100644 openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga
 create mode 100644 openfpga_flow/tasks/openfpga_shell/generate_fabric/config/task.conf
 create mode 100644 openfpga_flow/tasks/openfpga_shell/generate_testbench/config/task.conf

diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga
new file mode 100644
index 000000000..23ed17f59
--- /dev/null
+++ b/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga
@@ -0,0 +1,32 @@
+# Run VPR for the 'and' design
+#--write_rr_graph example_rr_graph.xml
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
+
+# Annotate the OpenFPGA architecture to VPR data base
+# to debug use --verbose options
+link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Build the module graph
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules
+build_fabric --compress_routing #--verbose
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here
+write_pnr_sdc --file ./SDC
+
+# Finish and exit OpenFPGA
+exit
+
+# Note :
+# To run verification at the end of the flow maintain source in ./SRC directory
diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga
new file mode 100644
index 000000000..0926935e9
--- /dev/null
+++ b/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga
@@ -0,0 +1,53 @@
+# Run VPR for the 'and' design
+#--write_rr_graph example_rr_graph.xml
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
+
+# Annotate the OpenFPGA architecture to VPR data base
+# to debug use --verbose options
+link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to clustering nets based on routing results
+pb_pin_fixup --verbose
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup
+
+# Build the module graph
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules
+build_fabric --compress_routing #--verbose
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --file fabric_indepenent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_verilog_testbench --file ./TESTBENCH --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+write_analysis_sdc --file ./SDC_analysis
+
+# Finish and exit OpenFPGA
+exit
+
+# Note :
+# To run verification at the end of the flow maintain source in ./SRC directory
diff --git a/openfpga_flow/tasks/openfpga_shell/generate_fabric/config/task.conf b/openfpga_flow/tasks/openfpga_shell/generate_fabric/config/task.conf
new file mode 100644
index 000000000..75bc6c703
--- /dev/null
+++ b/openfpga_flow/tasks/openfpga_shell/generate_fabric/config/task.conf
@@ -0,0 +1,31 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
diff --git a/openfpga_flow/tasks/openfpga_shell/generate_testbench/config/task.conf b/openfpga_flow/tasks/openfpga_shell/generate_testbench/config/task.conf
new file mode 100644
index 000000000..9540b767f
--- /dev/null
+++ b/openfpga_flow/tasks/openfpga_shell/generate_testbench/config/task.conf
@@ -0,0 +1,31 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]

From 5c851a84675b55549b2ee6db04ec4164a75127d1 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 28 Apr 2020 18:24:20 -0600
Subject: [PATCH 485/645] deploy the fabric/testbench generation only cases to
 travis

---
 .travis/script.sh | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/.travis/script.sh b/.travis/script.sh
index 60c3d0715..ac801729c 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -105,6 +105,12 @@ python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/duplicated_grid_pi
 echo -e "Testing Verilog generation with spy output pads";
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/spypad --debug --show_thread_logs
 
+echo -e "Testing fabric Verilog generation only";
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/generate_fabric --debug --show_thread_logs
+
+echo -e "Testing Verilog testbench generation only";
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/generate_testbench --debug --show_thread_logs
+
 # Verify MCNC big20 benchmark suite with ModelSim 
 # Please make sure you have ModelSim installed in the environment
 # Otherwise, it will fail

From 69306faf22d3ea79bcf35439caa089193d00449d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 28 Apr 2020 23:21:14 -0600
Subject: [PATCH 486/645] add a new include netlist for all the fabric-related
 netlists

---
 openfpga/src/fpga_verilog/verilog_api.cpp     |  6 +-
 .../verilog_auxiliary_netlists.cpp            | 69 ++++++++++++++++++-
 .../fpga_verilog/verilog_auxiliary_netlists.h |  4 ++
 openfpga/src/fpga_verilog/verilog_constants.h |  1 +
 4 files changed, 77 insertions(+), 3 deletions(-)

diff --git a/openfpga/src/fpga_verilog/verilog_api.cpp b/openfpga/src/fpga_verilog/verilog_api.cpp
index c8c7343ad..2c2ea4e93 100644
--- a/openfpga/src/fpga_verilog/verilog_api.cpp
+++ b/openfpga/src/fpga_verilog/verilog_api.cpp
@@ -124,13 +124,17 @@ void fpga_fabric_verilog(ModuleManager& module_manager,
                            src_dir_path,
                            options.explicit_port_mapping());
 
+  /* Generate an netlist including all the fabric-related netlists */
+  print_fabric_include_netlist(const_cast<const NetlistManager&>(netlist_manager),
+                               src_dir_path,
+                               circuit_lib);
+
   /* Given a brief stats on how many Verilog modules have been written to files */
   VTR_LOGV(options.verbose_output(), 
            "Written %lu Verilog modules in total\n", 
            module_manager.num_modules());  
 }
 
-
 /********************************************************************
  * A top-level function of FPGA-Verilog which focuses on fabric Verilog generation
  * This function will generate
diff --git a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
index ba2483ca7..b69868d17 100644
--- a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
+++ b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
@@ -25,8 +25,73 @@ namespace openfpga {
  *******************************************************************/
 
 /********************************************************************
- * Print a file that includes all the netlists that have been generated
- * and user-defined.
+ * Print a file that includes all the fabric netlists 
+ * that have been generated  and user-defined.
+ * This does NOT include any testbenches!
+ * Some netlists are open to compile under specific preprocessing flags
+ *******************************************************************/
+void print_fabric_include_netlist(const NetlistManager& netlist_manager,
+                                  const std::string& src_dir,
+                                  const CircuitLibrary& circuit_lib) {
+  std::string verilog_fname = src_dir + std::string(FABRIC_INCLUDE_NETLIST_FILE_NAME);
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
+
+  /* Validate the file stream */
+  check_file_stream(verilog_fname.c_str(), fp);
+
+  /* Print the title */
+  print_verilog_file_header(fp, std::string("Fabric Netlist Summary")); 
+
+  /* Print preprocessing flags */
+  print_verilog_comment(fp, std::string("------ Include defines: preproc flags -----"));
+  print_verilog_include_netlist(fp, std::string(src_dir + std::string(DEFINES_VERILOG_FILE_NAME)));
+  fp << std::endl;
+
+  /* Include all the user-defined netlists */
+  print_verilog_comment(fp, std::string("------ Include user-defined netlists -----"));
+  for (const std::string& user_defined_netlist : find_circuit_library_unique_verilog_netlists(circuit_lib)) {
+    print_verilog_include_netlist(fp, user_defined_netlist);
+  }
+
+  /* Include all the primitive modules */
+  print_verilog_comment(fp, std::string("------ Include primitive module netlists -----"));
+  for (const NetlistId& nlist_id : netlist_manager.netlists_by_type(NetlistManager::SUBMODULE_NETLIST)) {
+    print_verilog_include_netlist(fp, netlist_manager.netlist_name(nlist_id));
+  }
+  fp << std::endl;
+
+  /* Include all the CLB, heterogeneous block modules */
+  print_verilog_comment(fp, std::string("------ Include logic block netlists -----"));
+  for (const NetlistId& nlist_id : netlist_manager.netlists_by_type(NetlistManager::LOGIC_BLOCK_NETLIST)) {
+    print_verilog_include_netlist(fp, netlist_manager.netlist_name(nlist_id));
+  }
+  fp << std::endl;
+
+  /* Include all the routing architecture modules */
+  print_verilog_comment(fp, std::string("------ Include routing module netlists -----"));
+  for (const NetlistId& nlist_id : netlist_manager.netlists_by_type(NetlistManager::ROUTING_MODULE_NETLIST)) {
+    print_verilog_include_netlist(fp, netlist_manager.netlist_name(nlist_id));
+  }
+  fp << std::endl;
+
+  /* Include FPGA top module */
+  print_verilog_comment(fp, std::string("------ Include fabric top-level netlists -----"));
+  for (const NetlistId& nlist_id : netlist_manager.netlists_by_type(NetlistManager::TOP_MODULE_NETLIST)) {
+    print_verilog_include_netlist(fp, netlist_manager.netlist_name(nlist_id));
+  }
+  fp << std::endl;
+
+  /* Close the file stream */
+  fp.close();
+}
+
+/********************************************************************
+ * Print a file that includes all the netlists 
+ * including the fabric netlists and testbenches
+ * that have been generated and user-defined.
  * Some netlists are open to compile under specific preprocessing flags
  *******************************************************************/
 void print_include_netlists(const NetlistManager& netlist_manager,
diff --git a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h
index ed1317862..52292881a 100644
--- a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h
+++ b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h
@@ -17,6 +17,10 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
+void print_fabric_include_netlist(const NetlistManager& netlist_manager,
+                                  const std::string& src_dir,
+                                  const CircuitLibrary& circuit_lib);
+
 void print_include_netlists(const NetlistManager& netlist_manager,
                             const std::string& src_dir,
                             const std::string& circuit_name,
diff --git a/openfpga/src/fpga_verilog/verilog_constants.h b/openfpga/src/fpga_verilog/verilog_constants.h
index 797a00574..4456a1048 100644
--- a/openfpga/src/fpga_verilog/verilog_constants.h
+++ b/openfpga/src/fpga_verilog/verilog_constants.h
@@ -22,6 +22,7 @@ constexpr char* MODELSIM_SIMULATION_TIME_UNIT = "ms";
 constexpr char* ICARUS_SIMULATOR_FLAG = "ICARUS_SIMULATOR"; // the flag to enable specific Verilog code in testbenches
 // End of Icarus variables and flag
 
+constexpr char* FABRIC_INCLUDE_NETLIST_FILE_NAME = "fabric_netlists.v";
 constexpr char* TOP_INCLUDE_NETLIST_FILE_NAME_POSTFIX = "_include_netlists.v";
 constexpr char* VERILOG_TOP_POSTFIX = "_top.v";
 constexpr char* FORMAL_VERIFICATION_VERILOG_FILE_POSTFIX = "_top_formal_verification.v"; 

From 3c781b18d3b49e449be3e470fbb1b9f7930ff094 Mon Sep 17 00:00:00 2001
From: CHARAS SAMY <u6030277@lnissrv4.eng.utah.edu>
Date: Fri, 1 May 2020 09:55:38 -0600
Subject: [PATCH 487/645] Added routing benchmark

---
 .../routing_test/routing_test.act             | 10 ++++++++++
 .../routing_test/routing_test.blif            | 16 ++++++++++++++++
 .../routing_test/routing_test.v               | 19 +++++++++++++++++++
 3 files changed, 45 insertions(+)
 create mode 100755 openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.act
 create mode 100755 openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.blif
 create mode 100644 openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.v

diff --git a/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.act b/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.act
new file mode 100755
index 000000000..19f52fdd9
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.act
@@ -0,0 +1,10 @@
+IN0 0.505000 0.204400
+IN1 0.491000 0.206000
+IN2 0.472000 0.204400
+clk 0.500000 2.000000
+OUT1 0.491000 0.206000
+OUT0 0.505000 0.204400
+OUT2 0.472000 0.204400
+n15 0.491000 0.101146
+n18 0.505000 0.103222
+n21 0.472000 0.096477
diff --git a/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.blif b/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.blif
new file mode 100755
index 000000000..bf85b04b3
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.blif
@@ -0,0 +1,16 @@
+# Benchmark "routing_test" written by ABC on Tue Apr 21 18:25:21 2020 
+.model routing_test 
+.inputs IN0 IN1 IN2 clk  
+.outputs OUT0 OUT1 OUT2  
+ 
+.latch n15 OUT1 re clk 2 
+.latch n18 OUT0 re clk 2 
+.latch n21 OUT2 re clk 2 
+ 
+.names IN1 n15 
+1 1 
+.names IN0 n18 
+1 1 
+.names IN2 n21 
+1 1 
+.end 
diff --git a/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.v b/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.v
new file mode 100644
index 000000000..1cacf4857
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.v
@@ -0,0 +1,19 @@
+
+module routing_test(IN0,IN1,IN2,OUT0,OUT1,OUT2,clk);
+
+input wire IN0,IN1,IN2,clk;
+
+output reg OUT0, OUT1, OUT2;
+
+always @(posedge clk)
+	begin
+
+		OUT0  <=  IN0;
+		OUT1  <=  IN1;
+		OUT2  <=  IN2;
+
+	end
+
+
+
+endmodule

From f6cea1e17c7b364e5c61908c993b947e5ad4713f Mon Sep 17 00:00:00 2001
From: CHARAS SAMY <u6030277@lnissrv4.eng.utah.edu>
Date: Fri, 1 May 2020 10:55:23 -0600
Subject: [PATCH 488/645] Added test_mode_low benchmark

---
 .../test_mode_low/test_mode_low.act           | 23 ++++++++
 .../test_mode_low/test_mode_low.blif          | 35 +++++++++++++
 .../test_mode_low/test_mode_low.v             | 52 +++++++++++++++++++
 3 files changed, 110 insertions(+)
 create mode 100644 openfpga_flow/benchmarks/micro_benchmark/test_mode_low/test_mode_low.act
 create mode 100644 openfpga_flow/benchmarks/micro_benchmark/test_mode_low/test_mode_low.blif
 create mode 100644 openfpga_flow/benchmarks/micro_benchmark/test_mode_low/test_mode_low.v

diff --git a/openfpga_flow/benchmarks/micro_benchmark/test_mode_low/test_mode_low.act b/openfpga_flow/benchmarks/micro_benchmark/test_mode_low/test_mode_low.act
new file mode 100644
index 000000000..44920c540
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/test_mode_low/test_mode_low.act
@@ -0,0 +1,23 @@
+a 0.5 0.2
+b 0.5 0.2
+clk 0.5 0.2
+out_0 0.5 0.2
+out_1 0.5 0.2
+out_2 0.5 0.2
+out_3 0.5 0.2
+sum_0 0.5 0.2
+sum_1 0.5 0.2
+sum_2 0.5 0.2
+sum_3 0.5 0.2
+sum_4 0.5 0.2
+sum_5 0.5 0.2
+sum_6 0.5 0.2
+sum_7 0.5 0.2
+pipe_a_0 0.5 0.2
+pipe_a_1 0.5 0.2
+pipe_b_0 0.5 0.2
+pipe_b_1 0.5 0.2
+pipe_sum_0 0.5 0.2
+pipe_sum_1 0.5 0.2
+pipe_sum_2 0.5 0.2
+pipe_sum_3 0.5 0.2
diff --git a/openfpga_flow/benchmarks/micro_benchmark/test_mode_low/test_mode_low.blif b/openfpga_flow/benchmarks/micro_benchmark/test_mode_low/test_mode_low.blif
new file mode 100644
index 000000000..fd6a62c17
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/test_mode_low/test_mode_low.blif
@@ -0,0 +1,35 @@
+.model test_mode_low
+.inputs a b clk
+.outputs out_0 out_1 out_2 out_3
+
+#.subckt shift D=a clk=clk Q=pipe_a_0
+#.subckt shift D=pipe_a_0 clk=clk Q=pipe_a_1
+#.subckt shift D=b clk=clk Q=pipe_b_0
+#.subckt shift D=pipe_b_0 clk=clk Q=pipe_b_1
+
+
+.latch a pipe_a_0 re clk 0
+.latch pipe_a_0 pipe_a_1 re clk 0
+.latch b pipe_b_0 re clk 0
+.latch pipe_b_0 pipe_b_1 re clk 0
+
+.latch sum_0 pipe_sum_0 re clk 0
+.latch sum_2 pipe_sum_1 re clk 0
+.latch sum_4 pipe_sum_2 re clk 0
+.latch sum_6 pipe_sum_3 re clk 0
+
+.subckt adder a=pipe_a_1 b=pipe_b_1 cin=pipe_sum_3 cout=sum_1 sumout=sum_0
+.subckt adder a=pipe_sum_0 b=pipe_sum_2 cin=sum_1 cout=sum_3 sumout=sum_2
+.subckt adder a=pipe_sum_1 b=pipe_sum_3 cin=sum_3 cout=sum_5 sumout=sum_4
+.subckt adder a=pipe_sum_2 b=pipe_sum_0 cin=sum_5 cout=sum_7 sumout=sum_6
+
+.names pipe_sum_0 out_0
+1 1
+.names pipe_sum_1 out_1
+1 1
+.names pipe_sum_2 out_2
+1 1
+.names pipe_sum_3 out_3
+1 1
+
+.end
diff --git a/openfpga_flow/benchmarks/micro_benchmark/test_mode_low/test_mode_low.v b/openfpga_flow/benchmarks/micro_benchmark/test_mode_low/test_mode_low.v
new file mode 100644
index 000000000..ac34e62f3
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/test_mode_low/test_mode_low.v
@@ -0,0 +1,52 @@
+//////////////////////////////////////
+//                                  //
+//    2x2 Test-modes Low density    //
+//                                  //
+//////////////////////////////////////
+
+
+module test_mode_low (
+	a,
+	b,
+	clk,
+	reset,
+	out );
+
+	input wire a;
+	input wire b;
+	input wire clk;
+	input wire reset;
+	output wire[3:0] out;
+
+	reg[1:0] pipe_a;
+	reg[1:0] pipe_b;
+	reg[3:0] pipe_sum;
+	wire[7:0] sum;
+
+	assign sum[1:0] = pipe_a[1] + pipe_b[1] + pipe_sum[3];
+	assign sum[3:2] = pipe_sum[0] + sum[1] + pipe_sum[2];
+	assign sum[5:4] = pipe_sum[1] + sum[3] + pipe_sum[3];
+	assign sum[7:6] = pipe_sum[2] + sum[5] + pipe_sum[0];
+	assign out = pipe_sum;
+
+	initial begin
+		pipe_a <= 2'b00;
+		pipe_b <= 2'b00;
+		pipe_sum <= 4'b0000;
+	end
+
+	always @(posedge clk or posedge reset) begin
+		if(reset) begin
+			pipe_a <= 2'b00;
+			pipe_b <= 2'b00;
+			pipe_sum <= 4'b0000;
+		end else begin
+			pipe_a[0] <= a;
+			pipe_a[1] <= pipe_a[0];
+			pipe_b[0] <= b;
+			pipe_b[1] <= pipe_b[0];
+			pipe_sum <= {sum[6], sum[4], sum[2], sum[0]};
+		end	
+	end
+
+endmodule

From 6dd8d347e140d9aad6c8c72c02786240fc291166 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 1 May 2020 14:39:04 -0600
Subject: [PATCH 489/645] try to deploy microbenchmark test_mode_low but fail
 due to .v port mismatch with .blif

---
 openfpga_flow/tasks/openfpga_shell/spypad/config/task.conf | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/openfpga_flow/tasks/openfpga_shell/spypad/config/task.conf b/openfpga_flow/tasks/openfpga_shell/spypad/config/task.conf
index e093b2b53..b42e17287 100644
--- a/openfpga_flow/tasks/openfpga_shell/spypad/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/spypad/config/task.conf
@@ -22,11 +22,18 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_ti
 
 [BENCHMARKS]
 bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
+# Cannot pass automatically. Need change in .v file to match ports
+# When passed, we can replace the and2 benchmark
+#bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/test_mode_low/test_mode_low.blif
 
 [SYNTHESIS_PARAM]
 bench0_top = and2
 bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
 bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+
+#bench0_top = test_mode_low
+#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/test_mode_low/test_mode_low.act
+#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/test_mode_low/test_mode_low.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]

From 98a658a01349f246f7f4118f348ed441719830b6 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 1 May 2020 14:47:08 -0600
Subject: [PATCH 490/645] bug fixed in routing_test.v. Deployed to regression
 tests

---
 .../micro_benchmark/routing_test/routing_test.v    |  2 +-
 .../tasks/openfpga_shell/frac_lut/config/task.conf | 14 ++++++++++----
 2 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.v b/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.v
index 1cacf4857..d9729c1c8 100644
--- a/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.v
+++ b/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.v
@@ -1,5 +1,5 @@
 
-module routing_test(IN0,IN1,IN2,OUT0,OUT1,OUT2,clk);
+module routing_test(IN0,IN1,IN2, clk, OUT0,OUT1,OUT2);
 
 input wire IN0,IN1,IN2,clk;
 
diff --git a/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf b/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf
index a69c1107e..030c0d41e 100644
--- a/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf
@@ -21,18 +21,24 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
 
 [BENCHMARKS]
+#
 bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
+bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.blif
 # Modelsim is ok with this but icarus fails due to poor support on timing and looping
-#bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.blif
+#bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.blif
 
 [SYNTHESIS_PARAM]
 bench0_top = and2
 bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
 bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
 
-bench1_top = and2_latch
-bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.act
-bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
+bench1_top = routing_test
+bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.act
+bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.v
+
+bench2_top = and2_latch
+bench2_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.act
+bench2_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
 end_flow_with_test=

From 889f179ce779c7c5de4e8b9337f2c54b62eccf96 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 1 May 2020 14:54:57 -0600
Subject: [PATCH 491/645] add local encoder test case

---
 ...6_frac_N10_local_encoder_40nm_openfpga.xml | 260 ++++++++++++++++++
 .../mux_design/local_encoder/config/task.conf |  34 +++
 2 files changed, 294 insertions(+)
 create mode 100644 openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml
 create mode 100644 openfpga_flow/tasks/openfpga_shell/mux_design/local_encoder/config/task.conf

diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml
new file mode 100644
index 000000000..201a4be58
--- /dev/null
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml
@@ -0,0 +1,260 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
+      <design_technology type="cmos" topology="OR"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1" local_encoder="true"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1" local_encoder="true"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true" local_encoder="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
+      <design_technology type="cmos" fracturable_lut="true"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="6" tri_state_map="-----1" circuit_model_name="OR2"/>
+      <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
+      <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
+      <port type="sram" prefix="sram" size="64"/>
+      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="Qb" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+      <port type="input" prefix="outpad" size="1"/>
+      <port type="output" prefix="inpad" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle" physical_mode_name="physical"/>
+    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="0"/>
+    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
+    <!-- Binding operating pb_type to physical pb_type -->
+    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="1" physical_pb_type_index_factor="0.5">
+      <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:4]"/>
+      <port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="0">
+      <!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:5]"/>
+      <port name="out" physical_mode_port="lut6_out"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>
+<openfpga_simulation_setting>
+  <clock_setting>
+    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
+    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
+    <programming frequency="10e6"/>
+  </clock_setting>
+  <simulator_option>
+    <operating_condition temperature="25"/>
+    <output_log verbose="false" captab="false"/>
+    <accuracy type="abs" value="1e-13"/>
+    <runtime fast_simulation="true"/>
+  </simulator_option>
+  <monte_carlo num_simulation_points="2"/>
+  <measurement_setting>
+    <slew>
+      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
+      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
+    </slew>
+    <delay>
+      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
+      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
+    </delay>
+  </measurement_setting>
+  <stimulus>
+    <clock>
+      <rise slew_type="abs" slew_time="20e-12" />
+      <fall slew_type="abs" slew_time="20e-12" />
+    </clock>
+    <input>
+      <rise slew_type="abs" slew_time="25e-12" />
+      <fall slew_type="abs" slew_time="25e-12" />
+    </input>
+  </stimulus>
+</openfpga_simulation_setting>
diff --git a/openfpga_flow/tasks/openfpga_shell/mux_design/local_encoder/config/task.conf b/openfpga_flow/tasks/openfpga_shell/mux_design/local_encoder/config/task.conf
new file mode 100644
index 000000000..76cf4b589
--- /dev/null
+++ b/openfpga_flow/tasks/openfpga_shell/mux_design/local_encoder/config/task.conf
@@ -0,0 +1,34 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

From 1d35ac8086f541acdeefe01ffe8d0fd071a69d85 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 1 May 2020 14:56:07 -0600
Subject: [PATCH 492/645] deploy local encoder to CI

---
 .travis/script.sh | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/.travis/script.sh b/.travis/script.sh
index ac801729c..cb9601683 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -90,6 +90,9 @@ python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/mux_design/tree_st
 echo -e "Testing Verilog generation with routing mutliplexers implemented by standard cell MUX2";
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/mux_design/stdcell_mux2 --debug --show_thread_logs
 
+echo -e "Testing Verilog generation with routing mutliplexers implemented by local encoders";
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/mux_design/local_encoder --debug --show_thread_logs
+
 echo -e "Testing Verilog generation with behavioral description";
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/behavioral_verilog --debug --show_thread_logs
 

From 889bc8dbe82999372ce41dda188b7d55c1ceaa94 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 1 May 2020 15:05:59 -0600
Subject: [PATCH 493/645] add more test cases about LUT design and deploy to CI

---
 .travis/script.sh                             |  11 +-
 ..._N10_intermediate_buffer_40nm_openfpga.xml | 229 ++++++++++++++++++
 .../frac_lut/config/task.conf                 |   0
 .../intermediate_buffer/config/task.conf      |  45 ++++
 .../single_mode/config/task.conf              |   0
 5 files changed, 281 insertions(+), 4 deletions(-)
 create mode 100644 openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml
 rename openfpga_flow/tasks/openfpga_shell/{ => lut_design}/frac_lut/config/task.conf (100%)
 create mode 100644 openfpga_flow/tasks/openfpga_shell/lut_design/intermediate_buffer/config/task.conf
 rename openfpga_flow/tasks/openfpga_shell/{ => lut_design}/single_mode/config/task.conf (100%)

diff --git a/.travis/script.sh b/.travis/script.sh
index cb9601683..19da16b8b 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -51,11 +51,14 @@ echo -e "Testing OpenFPGA Shell";
 echo -e "Testing configuration chain of a K4N4 FPGA";
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/configuration_chain --debug --show_thread_logs
 
-echo -e "Testing Verilog generation for a single mode LUT6 FPGA using micro benchmarks";
-python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/single_mode --debug --show_thread_logs
+echo -e "Testing Verilog generation for LUTs: a single mode LUT6 FPGA using micro benchmarks";
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/lut_design/single_mode --debug --show_thread_logs
 
-echo -e "Testing Verilog generation with simple fracturable LUT6 ";
-python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/frac_lut --debug --show_thread_logs
+echo -e "Testing Verilog generation for LUTs: simple fracturable LUT6 ";
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/lut_design/frac_lut --debug --show_thread_logs
+
+echo -e "Testing Verilog generation for LUTs: LUT6 with intermediate buffers";
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/lut_design/intermediate_buffer --debug --show_thread_logs
 
 echo -e "Testing Verilog generation with VPR's untileable routing architecture ";
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/untileable --debug --show_thread_logs
diff --git a/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml
new file mode 100644
index 000000000..ef1c60a80
--- /dev/null
+++ b/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml
@@ -0,0 +1,229 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="lut6" prefix="lut6" dump_structural_verilog="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="--1--"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="6"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="64"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="Qb" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+      <port type="input" prefix="outpad" size="1"/>
+      <port type="output" prefix="inpad" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut6].ble6.lut6" circuit_model_name="lut6"/>
+    <pb_type name="clb.fle[n1_lut6].ble6.ff" circuit_model_name="static_dff"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>
+<openfpga_simulation_setting>
+  <clock_setting>
+    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
+    <programming frequency="10e6"/>
+  </clock_setting>
+  <simulator_option>
+    <operating_condition temperature="25"/>
+    <output_log verbose="false" captab="false"/>
+    <accuracy type="abs" value="1e-13"/>
+    <runtime fast_simulation="true"/>
+  </simulator_option>
+  <monte_carlo num_simulation_points="2"/>
+  <measurement_setting>
+    <slew>
+      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
+      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
+    </slew>
+    <delay>
+      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
+      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
+    </delay>
+  </measurement_setting>
+  <stimulus>
+    <clock>
+      <rise slew_type="abs" slew_time="20e-12" />
+      <fall slew_type="abs" slew_time="20e-12" />
+    </clock>
+    <input>
+      <rise slew_type="abs" slew_time="25e-12" />
+      <fall slew_type="abs" slew_time="25e-12" />
+    </input>
+  </stimulus>
+</openfpga_simulation_setting>
diff --git a/openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf b/openfpga_flow/tasks/openfpga_shell/lut_design/frac_lut/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/openfpga_shell/frac_lut/config/task.conf
rename to openfpga_flow/tasks/openfpga_shell/lut_design/frac_lut/config/task.conf
diff --git a/openfpga_flow/tasks/openfpga_shell/lut_design/intermediate_buffer/config/task.conf b/openfpga_flow/tasks/openfpga_shell/lut_design/intermediate_buffer/config/task.conf
new file mode 100644
index 000000000..b2535bd7c
--- /dev/null
+++ b/openfpga_flow/tasks/openfpga_shell/lut_design/intermediate_buffer/config/task.conf
@@ -0,0 +1,45 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_N10_tileable_40nm.xml
+
+[BENCHMARKS]
+#
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
+bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.blif
+# Modelsim is ok with this but icarus fails due to poor support on timing and looping
+#bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+
+bench1_top = routing_test
+bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.act
+bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.v
+
+bench2_top = and2_latch
+bench2_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.act
+bench2_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=
diff --git a/openfpga_flow/tasks/openfpga_shell/single_mode/config/task.conf b/openfpga_flow/tasks/openfpga_shell/lut_design/single_mode/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/openfpga_shell/single_mode/config/task.conf
rename to openfpga_flow/tasks/openfpga_shell/lut_design/single_mode/config/task.conf

From 1e2226e1c3038e0c9a757800c69b6c793da87a10 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 1 May 2020 21:18:14 -0600
Subject: [PATCH 494/645] now use explicit port mapping in the verilog
 testbenches for reference benchmarks

---
 .../verilog_formal_random_top_testbench.cpp      |  7 ++++++-
 .../src/fpga_verilog/verilog_testbench_utils.cpp | 16 +++++++++++++++-
 .../src/fpga_verilog/verilog_testbench_utils.h   |  4 ++++
 .../src/fpga_verilog/verilog_top_testbench.cpp   |  6 +++++-
 4 files changed, 30 insertions(+), 3 deletions(-)

diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
index 8d4dab5c9..a06f58188 100644
--- a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
@@ -108,13 +108,17 @@ void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp,
   /* Do NOT use explicit port mapping here: 
    * VPR added a prefix of "out_" to the output ports of input benchmark
    */
+  std::vector<std::string> prefix_to_remove;
+  prefix_to_remove.push_back(std::string(VPR_BENCHMARK_OUT_PORT_PREFIX));
+  prefix_to_remove.push_back(std::string(OPENFPGA_BENCHMARK_OUT_PORT_PREFIX));
   print_verilog_testbench_benchmark_instance(fp, reference_verilog_top_name,
                                              std::string(BENCHMARK_INSTANCE_NAME),
                                              std::string(),
                                              std::string(),
+                                             prefix_to_remove,
                                              std::string(BENCHMARK_PORT_POSTFIX),
                                              atom_ctx, netlist_annotation,
-                                             false);
+                                             true);
 
   print_verilog_comment(fp, std::string("----- End reference Benchmark Instanication -------"));
 
@@ -146,6 +150,7 @@ void print_verilog_random_testbench_fpga_instance(std::fstream& fp,
                                              std::string(FPGA_INSTANCE_NAME),
                                              std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX),
                                              std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX),
+                                             std::vector<std::string>(),
                                              std::string(FPGA_PORT_POSTFIX),
                                              atom_ctx, netlist_annotation,
                                              true);
diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
index dae42f042..8b5c741f1 100644
--- a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
+++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
@@ -57,6 +57,7 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp,
                                                 const std::string& instance_name,
                                                 const std::string& module_input_port_postfix,
                                                 const std::string& module_output_port_postfix,
+                                                const std::vector<std::string>& output_port_prefix_to_remove,
                                                 const std::string& output_port_postfix,
                                                 const AtomContext& atom_ctx,
                                                 const VprNetlistAnnotation& netlist_annotation,
@@ -97,8 +98,21 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp,
     } else {
       VTR_ASSERT_SAFE(AtomBlockType::OUTPAD == atom_ctx.nlist.block_type(atom_blk));
       fp << "\t\t";
+      /* Note that VPR added a prefix "out_" or "out:" to the name of output blocks
+       * We can remove this when specified through input argument 
+       */
+      std::string output_block_name = block_name;
+      for (const std::string& prefix_to_remove : output_port_prefix_to_remove) {
+        if (!prefix_to_remove.empty()) {
+          if (0 == output_block_name.find(prefix_to_remove)) {
+            output_block_name.erase(0, prefix_to_remove.length());
+            break;
+          }
+        }
+      }
+
       if (true == use_explicit_port_map) {
-        fp << "." << block_name << module_output_port_postfix << "(";
+        fp << "." << output_block_name << module_output_port_postfix << "(";
       }
       fp << block_name << output_port_postfix;
       if (true == use_explicit_port_map) {
diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.h b/openfpga/src/fpga_verilog/verilog_testbench_utils.h
index 5e0bd69f9..d51f3b7e8 100644
--- a/openfpga/src/fpga_verilog/verilog_testbench_utils.h
+++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.h
@@ -20,6 +20,9 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
+constexpr char* VPR_BENCHMARK_OUT_PORT_PREFIX = "out:";
+constexpr char* OPENFPGA_BENCHMARK_OUT_PORT_PREFIX = "out_";
+
 void print_verilog_testbench_fpga_instance(std::fstream& fp,
                                            const ModuleManager& module_manager,
                                            const ModuleId& top_module,
@@ -30,6 +33,7 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp,
                                                 const std::string& instance_name,
                                                 const std::string& module_input_port_postfix,
                                                 const std::string& module_output_port_postfix,
+                                                const std::vector<std::string>& output_port_prefix_to_remove,
                                                 const std::string& output_port_postfix,
                                                 const AtomContext& atom_ctx,
                                                 const VprNetlistAnnotation& netlist_annotation,
diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
index a477fa99e..6a647de35 100644
--- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
@@ -458,13 +458,17 @@ void print_verilog_top_testbench_benchmark_instance(std::fstream& fp,
   /* Do NOT use explicit port mapping here: 
    * VPR added a prefix of "out_" to the output ports of input benchmark
    */
+  std::vector<std::string> prefix_to_remove;
+  prefix_to_remove.push_back(std::string(VPR_BENCHMARK_OUT_PORT_PREFIX));
+  prefix_to_remove.push_back(std::string(OPENFPGA_BENCHMARK_OUT_PORT_PREFIX));
   print_verilog_testbench_benchmark_instance(fp, reference_verilog_top_name,
                                              std::string(TOP_TESTBENCH_REFERENCE_INSTANCE_NAME),
                                              std::string(),
                                              std::string(),
+                                             prefix_to_remove,
                                              std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX),
                                              atom_ctx, netlist_annotation,
-                                             false);
+                                             true);
 
   print_verilog_comment(fp, std::string("----- End reference Benchmark Instanication -------"));
 

From facd87dafe5eec9bd0734836ddb1f80c5333bdce Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 1 May 2020 21:39:43 -0600
Subject: [PATCH 495/645] use wildcard in SDC generation for
 multiple-instanced-blocks

---
 openfpga/src/fpga_sdc/sdc_memory_utils.cpp | 18 +++++++++++++++++-
 openfpga/src/fpga_sdc/sdc_writer_utils.cpp | 20 +++++++++++++++++---
 2 files changed, 34 insertions(+), 4 deletions(-)

diff --git a/openfpga/src/fpga_sdc/sdc_memory_utils.cpp b/openfpga/src/fpga_sdc/sdc_memory_utils.cpp
index 1910b4197..61457b467 100644
--- a/openfpga/src/fpga_sdc/sdc_memory_utils.cpp
+++ b/openfpga/src/fpga_sdc/sdc_memory_utils.cpp
@@ -3,6 +3,9 @@
  * fabric using SDC commands
  *******************************************************************/
 
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+
 /* Headers from openfpgautil library */
 #include "openfpga_digest.h"
 
@@ -26,17 +29,30 @@ void rec_print_pnr_sdc_disable_configurable_memory_module_output(std::fstream& f
                                                                  const ModuleId& parent_module,
                                                                  const std::string& parent_module_path) {
 
+  /* Keep tracking multiple-instanced-blocks (MIB) 
+   * if they should be skipped as the unique module has been visited already
+   */
+  std::map<ModuleId, bool> skip_mib;
   /* For each configurable child, we will go one level down in priority */
   for (size_t child_index = 0; child_index < module_manager.configurable_children(parent_module).size(); ++child_index) {
     std::string child_module_path = parent_module_path;
     ModuleId child_module_id = module_manager.configurable_children(parent_module)[child_index];
     size_t child_instance_id = module_manager.configurable_child_instances(parent_module)[child_index];
     if (true == module_manager.instance_name(parent_module, child_module_id, child_instance_id).empty()) {
+      if (0 < skip_mib.count(child_module_id)) {
+        VTR_ASSERT(skip_mib.at(child_module_id) = true);
+        continue;
+      }
       /* Give a default name <module_name>_<instance_id>_ */
       child_module_path += module_manager.module_name(child_module_id); 
       child_module_path += "_";
-      child_module_path += std::to_string(child_instance_id);
+      child_module_path += "*";
+      //child_module_path += std::to_string(child_instance_id);
       child_module_path += "_";
+      /* If we use wild card to disable all the other instance
+       * So we can skip later if there is no specific instance name 
+       */
+      skip_mib[child_module_id] = true;
     } else {
       child_module_path += module_manager.instance_name(parent_module, child_module_id, child_instance_id);
     }
diff --git a/openfpga/src/fpga_sdc/sdc_writer_utils.cpp b/openfpga/src/fpga_sdc/sdc_writer_utils.cpp
index 363d97e1c..4f021034c 100644
--- a/openfpga/src/fpga_sdc/sdc_writer_utils.cpp
+++ b/openfpga/src/fpga_sdc/sdc_writer_utils.cpp
@@ -5,6 +5,9 @@
 #include <ctime>
 #include <iomanip>
 
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+
 /* Headers from openfpgautil library */
 #include "openfpga_digest.h"
 
@@ -46,10 +49,21 @@ std::string generate_sdc_port(const BasicPort& port) {
   /* Only connection require a format of <port_name>[<lsb>:<msb>]
    * others require a format of <port_type> [<lsb>:<msb>] <port_name> 
    */
-  /* When LSB == MSB, we can use a simplified format <port_type>[<lsb>]*/
-  if ( 1 == port.get_width()) {
-    size_str = "[" + std::to_string(port.get_lsb()) + "]";
+  /* When LSB == MSB, we can use a simplified format 
+   * If LSB != 0, we need to give explicit pin number
+   *   <port_type>[<lsb>]
+   * Otherwise, we can keep a compact format
+   *   <port_type>
+   */
+  if (1 == port.get_width()) {
+    if (0 != port.get_lsb()) {
+      size_str = "[" + std::to_string(port.get_lsb()) + "]";
+    } else {
+      VTR_ASSERT(0 == port.get_lsb());
+      size_str.clear();
+    }
   }
+
   sdc_line = port.get_name() + size_str;
 
   return sdc_line;

From 8695c5ee78cb1b55e2e41aeac3021b6f6cf4b99a Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 2 May 2020 14:17:07 -0600
Subject: [PATCH 496/645] add options to use general-purpose wildcards in SDC
 generator

---
 .../src/openfpga_wildcard_string.cpp          | 105 ++++++++++++++++++
 .../src/openfpga_wildcard_string.h            |  57 ++++++++++
 openfpga/src/base/openfpga_naming.cpp         |  14 +++
 openfpga/src/base/openfpga_naming.h           |   3 +
 openfpga/src/base/openfpga_sdc.cpp            |   4 +
 openfpga/src/base/openfpga_sdc_command.cpp    |   6 +
 openfpga/src/fpga_sdc/analysis_sdc_option.cpp |   9 ++
 openfpga/src/fpga_sdc/analysis_sdc_option.h   |   3 +
 openfpga/src/fpga_sdc/analysis_sdc_writer.cpp |   2 +-
 openfpga/src/fpga_sdc/pnr_sdc_option.cpp      |   9 ++
 openfpga/src/fpga_sdc/pnr_sdc_option.h        |   3 +
 openfpga/src/fpga_sdc/pnr_sdc_writer.cpp      |   6 +-
 openfpga/src/fpga_sdc/sdc_memory_utils.cpp    |  61 +++++++---
 openfpga/src/fpga_sdc/sdc_memory_utils.h      |   1 +
 14 files changed, 263 insertions(+), 20 deletions(-)
 create mode 100644 libopenfpga/libopenfpgautil/src/openfpga_wildcard_string.cpp
 create mode 100644 libopenfpga/libopenfpgautil/src/openfpga_wildcard_string.h

diff --git a/libopenfpga/libopenfpgautil/src/openfpga_wildcard_string.cpp b/libopenfpga/libopenfpgautil/src/openfpga_wildcard_string.cpp
new file mode 100644
index 000000000..67031a2a5
--- /dev/null
+++ b/libopenfpga/libopenfpgautil/src/openfpga_wildcard_string.cpp
@@ -0,0 +1,105 @@
+/************************************************************************
+ * Member functions for WildCardString class 
+ ***********************************************************************/
+#include <cstring>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+#include "openfpga_wildcard_string.h"
+
+/* namespace openfpga begins */
+namespace openfpga {
+
+/************************************************************************
+ * Constructors
+ ***********************************************************************/
+WildCardString::WildCardString(const std::string& data) {
+  set_data(data);
+}
+
+/************************************************************************
+ * Public Accessors
+ ***********************************************************************/
+std::string WildCardString::data() const {
+  return data_;
+}
+
+/************************************************************************
+ * Public Mutators
+ ***********************************************************************/
+void WildCardString::set_data(const std::string& data) {
+  data_ = data;
+
+  set_default_wildcard_char(); 
+  set_default_sensitive_chars(); 
+  apply_wildcard_char(); 
+  compress();
+}
+
+/************************************************************************
+ * Internal Mutators
+ ***********************************************************************/
+void WildCardString::set_default_wildcard_char() {
+  wildcard_char_ = '*';
+}
+
+void WildCardString::set_default_sensitive_chars() {
+  sensitive_chars_.clear();
+  sensitive_chars_.reserve(10);
+  sensitive_chars_.push_back('0');
+  sensitive_chars_.push_back('1');
+  sensitive_chars_.push_back('2');
+  sensitive_chars_.push_back('3');
+  sensitive_chars_.push_back('4');
+  sensitive_chars_.push_back('5');
+  sensitive_chars_.push_back('6');
+  sensitive_chars_.push_back('7');
+  sensitive_chars_.push_back('8');
+  sensitive_chars_.push_back('9');
+}
+
+void WildCardString::apply_wildcard_char() {
+  /* Step by step:
+   * For each sensitive character,
+   * replace all of its occurance in the string data_ with wildcard character
+   */
+  for (const char& char_to_replace : sensitive_chars_) {
+    size_t cur_pos = 0;
+    std::string::size_type found;
+    while (std::string::npos != (found = data_.find_first_of(char_to_replace, cur_pos))) {
+      data_.replace(found, 1, 1, wildcard_char_);
+      cur_pos = found + 1;
+    }
+  }
+}
+
+void WildCardString::compress() {
+  for (std::string::size_type i = 0; i < data_.size(); ++i) {
+    /* Care only wildcard character */
+    if (wildcard_char_ != data_[i]) {
+      continue;
+    }
+
+    /* Finish if this is the end of string */
+    if (data_.size() - 1 == i) {
+      break;
+    }
+
+    /* Try to find the next element and see if the same as wild card 
+     * Keep erase the next element until we have a non-wildcard character
+     */
+    while (data_[i] == data_[i + 1]) {
+      /* Erase the next element */
+      data_.erase(i + 1, 1);
+
+      /* Finish if this is the end of string */
+      if (data_.size() - 1 == i) {
+        break;
+      }
+    }
+  }
+}
+
+} /* namespace openfpga ends */
diff --git a/libopenfpga/libopenfpgautil/src/openfpga_wildcard_string.h b/libopenfpga/libopenfpgautil/src/openfpga_wildcard_string.h
new file mode 100644
index 000000000..874641cf4
--- /dev/null
+++ b/libopenfpga/libopenfpgautil/src/openfpga_wildcard_string.h
@@ -0,0 +1,57 @@
+#ifndef OPENFPGA_WILDCARD_STRING_H
+#define OPENFPGA_WILDCARD_STRING_H
+
+/********************************************************************
+ * Include header files that are required by data structure declaration
+ *******************************************************************/
+#include <string>
+#include <vector>
+
+/* namespace openfpga begins */
+namespace openfpga {
+
+/************************************************************************
+ * This file includes a object that can apply wildcard characters 
+ * By default it will replace any digital numbers with a '*' character 
+ * Users can set the wildcard character on their needs
+ *
+ * Example:
+ *   std::string orig_str;
+ *   WildCardString wc_str(orig_str);
+ *   std::string output = wc_str.data();
+ *
+ ***********************************************************************/
+
+class WildCardString {
+  public : /* Constructors*/
+    WildCardString (const std::string& data);
+
+  public : /* Public Accessors */ 
+    std::string data() const;
+
+  public : /* Public Mutators */ 
+    /* Give a string to apply wildcards */
+    void set_data(const std::string& data);
+
+  private : /* Private Mutators */ 
+    /* Use default wildcard character '*' */
+    void set_default_wildcard_char();
+
+    /* Use default sensitive words which are numbers */
+    void set_default_sensitive_chars();
+
+    /* Replace sensitive words with wildcard characters */
+    void apply_wildcard_char();
+
+    /* Remove redundant wildcard chars (which are next to each other) */
+    void compress();
+
+  private : /* Internal data */
+    std::string data_; /* Lines to be splited */
+    std::vector<char> sensitive_chars_;
+    char wildcard_char_;
+};
+
+} /* namespace openfpga ends */
+
+#endif
diff --git a/openfpga/src/base/openfpga_naming.cpp b/openfpga/src/base/openfpga_naming.cpp
index 0796d4df1..74750fca5 100644
--- a/openfpga/src/base/openfpga_naming.cpp
+++ b/openfpga/src/base/openfpga_naming.cpp
@@ -30,6 +30,20 @@ std::string generate_instance_name(const std::string& instance_name,
   return instance_name + std::string("_") + std::to_string(instance_id) + std::string("_");
 }
 
+/************************************************
+ * A generic function to generate the instance name
+ * in the following format:
+ * <instance_name>_<id>_
+ * This is mainly used by module manager to give a default
+ * name for each instance when outputting the module
+ * in Verilog/SPICE format
+ ***********************************************/
+std::string generate_instance_wildcard_name(const std::string& instance_name,
+                                            const std::string& wildcard_str) {
+  return instance_name + std::string("_") + wildcard_str + std::string("_");
+}
+
+
 /************************************************
  * Generate the node name for a multiplexing structure 
  * Case 1 : If there is an intermediate buffer followed by,
diff --git a/openfpga/src/base/openfpga_naming.h b/openfpga/src/base/openfpga_naming.h
index d3307fe3c..9896dddd4 100644
--- a/openfpga/src/base/openfpga_naming.h
+++ b/openfpga/src/base/openfpga_naming.h
@@ -26,6 +26,9 @@ namespace openfpga {
 std::string generate_instance_name(const std::string& instance_name,
                                    const size_t& instance_id);
 
+std::string generate_instance_wildcard_name(const std::string& instance_name,
+                                            const std::string& wildcard_str);
+
 std::string generate_mux_node_name(const size_t& node_level, 
                                    const bool& add_buffer_postfix);
 
diff --git a/openfpga/src/base/openfpga_sdc.cpp b/openfpga/src/base/openfpga_sdc.cpp
index 21a3ab8fb..c0c5b3f22 100644
--- a/openfpga/src/base/openfpga_sdc.cpp
+++ b/openfpga/src/base/openfpga_sdc.cpp
@@ -29,6 +29,7 @@ int write_pnr_sdc(OpenfpgaContext& openfpga_ctx,
                   const Command& cmd, const CommandContext& cmd_context) {
 
   CommandOptionId opt_output_dir = cmd.option("file");
+  CommandOptionId opt_flatten_names = cmd.option("flatten_names");
   CommandOptionId opt_constrain_global_port = cmd.option("constrain_global_port");
   CommandOptionId opt_constrain_non_clock_global_port = cmd.option("constrain_non_clock_global_port");
   CommandOptionId opt_constrain_grid = cmd.option("constrain_grid");
@@ -49,6 +50,7 @@ int write_pnr_sdc(OpenfpgaContext& openfpga_ctx,
 
   PnrSdcOption options(sdc_dir_path);
 
+  options.set_flatten_names(cmd_context.option_enable(cmd, opt_flatten_names));
   options.set_constrain_global_port(cmd_context.option_enable(cmd, opt_constrain_global_port));
   options.set_constrain_non_clock_global_port(cmd_context.option_enable(cmd, opt_constrain_non_clock_global_port));
   options.set_constrain_grid(cmd_context.option_enable(cmd, opt_constrain_grid));
@@ -95,6 +97,7 @@ int write_analysis_sdc(OpenfpgaContext& openfpga_ctx,
                        const Command& cmd, const CommandContext& cmd_context) {
 
   CommandOptionId opt_output_dir = cmd.option("file");
+  CommandOptionId opt_flatten_names = cmd.option("flatten_names");
 
   /* This is an intermediate data structure which is designed to modularize the FPGA-SDC
    * Keep it independent from any other outside data structures
@@ -106,6 +109,7 @@ int write_analysis_sdc(OpenfpgaContext& openfpga_ctx,
 
   AnalysisSdcOption options(sdc_dir_path);
   options.set_generate_sdc_analysis(true);
+  options.set_flatten_names(cmd_context.option_enable(cmd, opt_flatten_names));
 
   /* Collect global ports from the circuit library:
    * TODO: should we place this in the OpenFPGA context?
diff --git a/openfpga/src/base/openfpga_sdc_command.cpp b/openfpga/src/base/openfpga_sdc_command.cpp
index 551b37d2b..02595a10c 100644
--- a/openfpga/src/base/openfpga_sdc_command.cpp
+++ b/openfpga/src/base/openfpga_sdc_command.cpp
@@ -26,6 +26,9 @@ ShellCommandId add_openfpga_write_pnr_sdc_command(openfpga::Shell<OpenfpgaContex
   shell_cmd.set_option_short_name(output_opt, "f");
   shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING);
 
+  /* Add an option '--flatten_name' */
+  shell_cmd.add_option("flatten_names", false, "Use flatten names to compress SDC file size");
+
   /* Add an option '--constrain_global_port' */
   shell_cmd.add_option("constrain_global_port", false, "Constrain all the global ports of FPGA fabric");
 
@@ -85,6 +88,9 @@ ShellCommandId add_openfpga_write_analysis_sdc_command(openfpga::Shell<OpenfpgaC
 
   /* Add an option '--verbose' */
   shell_cmd.add_option("verbose", false, "Enable verbose output");
+
+  /* Add an option '--flatten_name' */
+  shell_cmd.add_option("flatten_names", false, "Use flatten names to compress SDC file size");
   
   /* Add command 'write_fabric_verilog' to the Shell */
   ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "generate SDC files for timing analysis a PnRed FPGA fabric mapped by a benchmark");
diff --git a/openfpga/src/fpga_sdc/analysis_sdc_option.cpp b/openfpga/src/fpga_sdc/analysis_sdc_option.cpp
index 444e73fb4..80d6d0084 100644
--- a/openfpga/src/fpga_sdc/analysis_sdc_option.cpp
+++ b/openfpga/src/fpga_sdc/analysis_sdc_option.cpp
@@ -11,6 +11,7 @@ namespace openfpga {
  ********************************************************************/
 AnalysisSdcOption::AnalysisSdcOption(const std::string& sdc_dir) {
   sdc_dir_ = sdc_dir;
+  flatten_names_ = false;
   generate_sdc_analysis_ = false;
 }
 
@@ -21,6 +22,10 @@ std::string AnalysisSdcOption::sdc_dir() const {
   return sdc_dir_;
 }
 
+bool AnalysisSdcOption::flatten_names() const {
+  return flatten_names_;
+}
+
 bool AnalysisSdcOption::generate_sdc_analysis() const {
   return generate_sdc_analysis_;
 }
@@ -32,6 +37,10 @@ void AnalysisSdcOption::set_sdc_dir(const std::string& sdc_dir) {
   sdc_dir_ = sdc_dir;
 }
 
+void AnalysisSdcOption::set_flatten_names(const bool& flatten_names) {
+  flatten_names_ = flatten_names;
+}
+
 void AnalysisSdcOption::set_generate_sdc_analysis(const bool& generate_sdc_analysis) {
   generate_sdc_analysis_ = generate_sdc_analysis;
 }
diff --git a/openfpga/src/fpga_sdc/analysis_sdc_option.h b/openfpga/src/fpga_sdc/analysis_sdc_option.h
index 514e5e81c..8154de9c9 100644
--- a/openfpga/src/fpga_sdc/analysis_sdc_option.h
+++ b/openfpga/src/fpga_sdc/analysis_sdc_option.h
@@ -16,13 +16,16 @@ class AnalysisSdcOption {
     AnalysisSdcOption(const std::string& sdc_dir);
   public: /* Public accessors */
     std::string sdc_dir() const;
+    bool flatten_names() const;
     bool generate_sdc_analysis() const;
   public: /* Public mutators */
     void set_sdc_dir(const std::string& sdc_dir);
+    void set_flatten_names(const bool& flatten_names);
     void set_generate_sdc_analysis(const bool& generate_sdc_analysis);
   private: /* Internal data */
     std::string sdc_dir_;
     bool generate_sdc_analysis_; 
+    bool flatten_names_; 
 };
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp b/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp
index 584f6e63f..8efdb4e9e 100644
--- a/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp
+++ b/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp
@@ -264,7 +264,7 @@ void print_analysis_sdc(const AnalysisSdcOption& option,
                                           openfpga_ctx.arch().circuit_lib, global_ports);
 
   /* Disable the timing for configuration cells */ 
-  rec_print_pnr_sdc_disable_configurable_memory_module_output(fp, 
+  rec_print_pnr_sdc_disable_configurable_memory_module_output(fp, option.flatten_names(), 
                                                               openfpga_ctx.module_graph(), top_module, 
                                                               format_dir_path(openfpga_ctx.module_graph().module_name(top_module)));
 
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_option.cpp b/openfpga/src/fpga_sdc/pnr_sdc_option.cpp
index 153ac4fac..bf87cac8e 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_option.cpp
+++ b/openfpga/src/fpga_sdc/pnr_sdc_option.cpp
@@ -11,6 +11,7 @@ namespace openfpga {
  ********************************************************************/
 PnrSdcOption::PnrSdcOption(const std::string& sdc_dir) {
   sdc_dir_ = sdc_dir;
+  flatten_names_ = false;
   constrain_global_port_ = false;
   constrain_non_clock_global_port_ = false;
   constrain_grid_ = false;
@@ -29,6 +30,10 @@ std::string PnrSdcOption::sdc_dir() const {
   return sdc_dir_;
 }
 
+bool PnrSdcOption::flatten_names() const {
+  return flatten_names_;
+}
+
 bool PnrSdcOption::generate_sdc_pnr() const {
   return constrain_global_port_ 
       || constrain_grid_
@@ -82,6 +87,10 @@ void PnrSdcOption::set_sdc_dir(const std::string& sdc_dir) {
   sdc_dir_ = sdc_dir;
 }
 
+void PnrSdcOption::set_flatten_names(const bool& flatten_names) {
+  flatten_names_ = flatten_names;
+}
+
 void PnrSdcOption::set_generate_sdc_pnr(const bool& generate_sdc_pnr) {
   constrain_global_port_ = generate_sdc_pnr;
   constrain_grid_ = generate_sdc_pnr;
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_option.h b/openfpga/src/fpga_sdc/pnr_sdc_option.h
index 71dc1a806..49a1f18ed 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_option.h
+++ b/openfpga/src/fpga_sdc/pnr_sdc_option.h
@@ -16,6 +16,7 @@ class PnrSdcOption {
     PnrSdcOption(const std::string& sdc_dir);
   public: /* Public accessors */
     std::string sdc_dir() const;
+    bool flatten_names() const;
     bool generate_sdc_pnr() const;
     bool constrain_global_port() const;
     bool constrain_non_clock_global_port() const;
@@ -28,6 +29,7 @@ class PnrSdcOption {
     bool constrain_zero_delay_paths() const;
   public: /* Public mutators */
     void set_sdc_dir(const std::string& sdc_dir);
+    void set_flatten_names(const bool& flatten_names);
     void set_generate_sdc_pnr(const bool& generate_sdc_pnr);
     void set_constrain_global_port(const bool& constrain_global_port);
     void set_constrain_non_clock_global_port(const bool& constrain_non_clock_global_port);
@@ -40,6 +42,7 @@ class PnrSdcOption {
     void set_constrain_zero_delay_paths(const bool& constrain_zero_delay_paths);
   private: /* Internal data */
     std::string sdc_dir_;
+    bool flatten_names_;
     bool constrain_global_port_; 
     bool constrain_non_clock_global_port_; 
     bool constrain_grid_; 
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
index b7ac5bb43..3678530fc 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
+++ b/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
@@ -43,6 +43,7 @@ namespace openfpga {
  *******************************************************************/
 static 
 void print_pnr_sdc_constrain_configurable_memory_outputs(const std::string& sdc_dir,
+                                                         const bool& flatten_names,
                                                          const ModuleManager& module_manager,
                                                          const ModuleId& top_module) {
 
@@ -63,7 +64,8 @@ void print_pnr_sdc_constrain_configurable_memory_outputs(const std::string& sdc_
   print_sdc_file_header(fp, std::string("Disable configurable memory outputs for PnR"));
 
   /* Go recursively in the module manager, starting from the top-level module: instance id of the top-level module is 0 by default */
-  rec_print_pnr_sdc_disable_configurable_memory_module_output(fp, module_manager, top_module, 
+  rec_print_pnr_sdc_disable_configurable_memory_module_output(fp, flatten_names,
+                                                              module_manager, top_module, 
                                                               format_dir_path(module_manager.module_name(top_module)));
 
   /* Close file handler */
@@ -266,7 +268,7 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options,
 
   /* Output Design Constraints to disable outputs of memory cells */
   if (true == sdc_options.constrain_configurable_memory_outputs()) {
-    print_pnr_sdc_constrain_configurable_memory_outputs(sdc_options.sdc_dir(), module_manager, top_module); 
+    print_pnr_sdc_constrain_configurable_memory_outputs(sdc_options.sdc_dir(), sdc_options.flatten_names(), module_manager, top_module); 
   } 
 
   /* Break loops from Multiplexer Output */
diff --git a/openfpga/src/fpga_sdc/sdc_memory_utils.cpp b/openfpga/src/fpga_sdc/sdc_memory_utils.cpp
index 61457b467..07b7d0804 100644
--- a/openfpga/src/fpga_sdc/sdc_memory_utils.cpp
+++ b/openfpga/src/fpga_sdc/sdc_memory_utils.cpp
@@ -5,10 +5,14 @@
 
 /* Headers from vtrutil library */
 #include "vtr_assert.h"
+#include "vtr_log.h"
 
 /* Headers from openfpgautil library */
+#include "openfpga_wildcard_string.h"
 #include "openfpga_digest.h"
 
+#include "openfpga_naming.h"
+
 #include "sdc_writer_utils.h"
 
 #include "sdc_memory_utils.h"
@@ -23,42 +27,65 @@ namespace openfpga {
  * using a Depth-First Search (DFS) strategy
  * It will iterate over all the configurable children under each module
  * and print a SDC command to disable its outputs
+ *
+ * Note:
+ *   - When flatten_names is true
+ *     this function will not apply any wildcard to names
+ *   - When flatten_names is false
+ *     It will straightforwardly output the instance name and port name
+ *     This function will try to apply wildcard to names
+ *     so that SDC file size can be minimal 
  *******************************************************************/
 void rec_print_pnr_sdc_disable_configurable_memory_module_output(std::fstream& fp, 
+                                                                 const bool& flatten_names,
                                                                  const ModuleManager& module_manager, 
                                                                  const ModuleId& parent_module,
                                                                  const std::string& parent_module_path) {
 
-  /* Keep tracking multiple-instanced-blocks (MIB) 
-   * if they should be skipped as the unique module has been visited already
+  /* Build wildcard names for the instance names of multiple-instanced-blocks (MIB) 
+   * We will find all the instance names and see there are common prefix 
+   * If so, we can use wildcards
    */
-  std::map<ModuleId, bool> skip_mib;
+  std::map<ModuleId, std::vector<std::string>> wildcard_names;
+
   /* For each configurable child, we will go one level down in priority */
   for (size_t child_index = 0; child_index < module_manager.configurable_children(parent_module).size(); ++child_index) {
     std::string child_module_path = parent_module_path;
     ModuleId child_module_id = module_manager.configurable_children(parent_module)[child_index];
     size_t child_instance_id = module_manager.configurable_child_instances(parent_module)[child_index];
+    std::string child_instance_name;
     if (true == module_manager.instance_name(parent_module, child_module_id, child_instance_id).empty()) {
-      if (0 < skip_mib.count(child_module_id)) {
-        VTR_ASSERT(skip_mib.at(child_module_id) = true);
+      child_instance_name = generate_instance_name(module_manager.module_name(child_module_id), child_instance_id);
+    } else {
+      child_instance_name = module_manager.instance_name(parent_module, child_module_id, child_instance_id);
+    }
+
+    if (false == flatten_names) { 
+      /* Try to adapt to a wildcard name: replace all the numbers with a wildcard character '*' */
+      WildCardString wildcard_str(child_instance_name); 
+      /* If the wildcard name is already in the list, we can skip this
+       * Otherwise, we have to 
+       *   - output this instance 
+       *   - record the wildcard name in the map 
+       */
+      if ( (0 < wildcard_names.count(child_module_id)) 
+        && (wildcard_names.at(child_module_id).end() != std::find(wildcard_names.at(child_module_id).begin(),
+                                                                  wildcard_names.at(child_module_id).end(),
+                                                                  wildcard_str.data())) ) {
         continue;
       }
-      /* Give a default name <module_name>_<instance_id>_ */
-      child_module_path += module_manager.module_name(child_module_id); 
-      child_module_path += "_";
-      child_module_path += "*";
-      //child_module_path += std::to_string(child_instance_id);
-      child_module_path += "_";
-      /* If we use wild card to disable all the other instance
-       * So we can skip later if there is no specific instance name 
-       */
-      skip_mib[child_module_id] = true;
+
+      child_module_path += wildcard_str.data();
+ 
+      wildcard_names[child_module_id].push_back(wildcard_str.data());
     } else {
-      child_module_path += module_manager.instance_name(parent_module, child_module_id, child_instance_id);
+      child_module_path += child_instance_name;
     }
+    
     child_module_path = format_dir_path(child_module_path);
 
-    rec_print_pnr_sdc_disable_configurable_memory_module_output(fp, module_manager, 
+    rec_print_pnr_sdc_disable_configurable_memory_module_output(fp, flatten_names,
+                                                                module_manager, 
                                                                 child_module_id, 
                                                                 child_module_path);
   }
diff --git a/openfpga/src/fpga_sdc/sdc_memory_utils.h b/openfpga/src/fpga_sdc/sdc_memory_utils.h
index 7fbf92294..576b3a36e 100644
--- a/openfpga/src/fpga_sdc/sdc_memory_utils.h
+++ b/openfpga/src/fpga_sdc/sdc_memory_utils.h
@@ -16,6 +16,7 @@
 namespace openfpga {
 
 void rec_print_pnr_sdc_disable_configurable_memory_module_output(std::fstream& fp, 
+                                                                 const bool& flatten_names,
                                                                  const ModuleManager& module_manager, 
                                                                  const ModuleId& parent_module,
                                                                  const std::string& parent_module_path);

From ecdbdcb59254ba3a79032ababe2f4bc29de74f4e Mon Sep 17 00:00:00 2001
From: Xifan Tang <tangxifan@gmail.com>
Date: Sat, 2 May 2020 14:23:20 -0600
Subject: [PATCH 497/645] update documentation on new SDC options

---
 docs/source/openfpga_shell/openfpga_commands.rst | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/docs/source/openfpga_shell/openfpga_commands.rst b/docs/source/openfpga_shell/openfpga_commands.rst
index 543b87397..12a1d89c7 100644
--- a/docs/source/openfpga_shell/openfpga_commands.rst
+++ b/docs/source/openfpga_shell/openfpga_commands.rst
@@ -176,6 +176,8 @@ FPGA-SDC
   
   - ``--file`` or ``-f`` Specify the output directory for SDC files
 
+  - ``--flatten_names`` Use flatten names (no wildcards) in SDC files
+
   - ``--constrain_global_port`` Constrain all the global ports of FPGA fabric.
 
   - ``--constrain_non_clock_global_port`` Constrain all the non-clock global ports as clocks ports of FPGA fabric
@@ -205,3 +207,5 @@ FPGA-SDC
   Write the SDC to run timing analysis for a mapped FPGA fabric
 
   - ``--file`` or ``-f`` Specify the output directory for SDC files
+  
+  - ``--flatten_names`` Use flatten names (no wildcards) in SDC files

From d0793d90298e8edb70a5b8a4ef7bda9116d3f77d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 2 May 2020 15:52:17 -0600
Subject: [PATCH 498/645] now disable_sb_output support wildcard

---
 openfpga/src/base/openfpga_sdc_command.cpp |   4 +-
 openfpga/src/fpga_sdc/pnr_sdc_writer.cpp   | 241 ++++++++++++++++-----
 2 files changed, 186 insertions(+), 59 deletions(-)

diff --git a/openfpga/src/base/openfpga_sdc_command.cpp b/openfpga/src/base/openfpga_sdc_command.cpp
index 02595a10c..77c581da2 100644
--- a/openfpga/src/base/openfpga_sdc_command.cpp
+++ b/openfpga/src/base/openfpga_sdc_command.cpp
@@ -27,7 +27,7 @@ ShellCommandId add_openfpga_write_pnr_sdc_command(openfpga::Shell<OpenfpgaContex
   shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING);
 
   /* Add an option '--flatten_name' */
-  shell_cmd.add_option("flatten_names", false, "Use flatten names to compress SDC file size");
+  shell_cmd.add_option("flatten_names", false, "Use flatten names (no wildcards) in SDC files");
 
   /* Add an option '--constrain_global_port' */
   shell_cmd.add_option("constrain_global_port", false, "Constrain all the global ports of FPGA fabric");
@@ -90,7 +90,7 @@ ShellCommandId add_openfpga_write_analysis_sdc_command(openfpga::Shell<OpenfpgaC
   shell_cmd.add_option("verbose", false, "Enable verbose output");
 
   /* Add an option '--flatten_name' */
-  shell_cmd.add_option("flatten_names", false, "Use flatten names to compress SDC file size");
+  shell_cmd.add_option("flatten_names", false, "Use flatten names (no wildcards) in SDC files");
   
   /* Add command 'write_fabric_verilog' to the Shell */
   ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "generate SDC files for timing analysis a PnRed FPGA fabric mapped by a benchmark");
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
index 3678530fc..e3c5625ef 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
+++ b/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
@@ -19,6 +19,7 @@
 
 /* Headers from openfpgautil library */
 #include "openfpga_port.h"
+#include "openfpga_wildcard_string.h"
 #include "openfpga_digest.h"
 
 #include "mux_utils.h"
@@ -135,61 +136,7 @@ void print_sdc_disable_routing_multiplexer_outputs(const std::string& sdc_dir,
  *******************************************************************/
 static 
 void print_pnr_sdc_flatten_routing_disable_switch_block_outputs(const std::string& sdc_dir,
-                                                                const ModuleManager& module_manager,
-                                                                const DeviceRRGSB& device_rr_gsb) {
-  /* Create the file name for Verilog netlist */
-  std::string sdc_fname(sdc_dir + std::string(SDC_DISABLE_SB_OUTPUTS_FILE_NAME));
-
-  /* Start time count */
-  std::string timer_message = std::string("Write SDC to disable switch block outputs for P&R flow '") + sdc_fname + std::string("'");
-  vtr::ScopedStartFinishTimer timer(timer_message);
-
-  /* Create the file stream */
-  std::fstream fp;
-  fp.open(sdc_fname, std::fstream::out | std::fstream::trunc);
-
-  check_file_stream(sdc_fname.c_str(), fp);
-
-  /* Generate the descriptions*/
-  print_sdc_file_header(fp, std::string("Disable Switch Block outputs for PnR"));
-
-  /* Get the range of SB array */
-  vtr::Point<size_t> sb_range = device_rr_gsb.get_gsb_range();
-  /* Go for each SB */
-  for (size_t ix = 0; ix < sb_range.x(); ++ix) {
-    for (size_t iy = 0; iy < sb_range.y(); ++iy) {
-      const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
-
-      if (false == rr_gsb.is_sb_exist()) {
-        continue;
-      }
-
-      vtr::Point<size_t> gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
-      std::string sb_instance_name = generate_switch_block_module_name(gsb_coordinate); 
-
-      ModuleId sb_module = module_manager.find_module(sb_instance_name);
-      VTR_ASSERT(true == module_manager.valid_module_id(sb_module));
-
-      /* Disable the outputs of the module */
-      for (const BasicPort& output_port : module_manager.module_ports_by_type(sb_module, ModuleManager::MODULE_OUTPUT_PORT)) {
-        fp << "set_disable_timing " << sb_instance_name << "/" << output_port.get_name() << std::endl;
-        fp << std::endl;
-      }
-    }
-  }
-  
-  /* Close file handler */
-  fp.close();
-}
-
-/********************************************************************
- * Break combinational loops in FPGA fabric, which mainly come from 
- * loops of multiplexers.
- * To handle this, we disable the timing at outputs of Switch blocks
- * This function is designed for compact routing hierarchy
- *******************************************************************/
-static 
-void print_pnr_sdc_compact_routing_disable_switch_block_outputs(const std::string& sdc_dir,
+                                                                const bool& flatten_names,
                                                                 const ModuleManager& module_manager,
                                                                 const ModuleId& top_module,
                                                                 const DeviceRRGSB& device_rr_gsb) {
@@ -209,6 +156,131 @@ void print_pnr_sdc_compact_routing_disable_switch_block_outputs(const std::strin
   /* Generate the descriptions*/
   print_sdc_file_header(fp, std::string("Disable Switch Block outputs for PnR"));
 
+  std::string root_path = format_dir_path(module_manager.module_name(top_module));
+
+  /* Build wildcard names for the instance names of multiple-instanced-blocks (MIB) 
+   * We will find all the instance names and see there are common prefix 
+   * If so, we can use wildcards
+   */
+  std::map<ModuleId, std::vector<std::string>> wildcard_names;
+
+  /* Get the range of SB array */
+  vtr::Point<size_t> sb_range = device_rr_gsb.get_gsb_range();
+  /* Go for each SB */
+  for (size_t ix = 0; ix < sb_range.x(); ++ix) {
+    for (size_t iy = 0; iy < sb_range.y(); ++iy) {
+      const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
+
+      if (false == rr_gsb.is_sb_exist()) {
+        continue;
+      }
+
+      std::string module_path = root_path;
+
+      vtr::Point<size_t> gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
+      std::string sb_instance_name = generate_switch_block_module_name(gsb_coordinate); 
+
+      ModuleId sb_module = module_manager.find_module(sb_instance_name);
+      VTR_ASSERT(true == module_manager.valid_module_id(sb_module));
+
+      if (false == flatten_names) { 
+        /* Try to adapt to a wildcard name: replace all the numbers with a wildcard character '*' */
+        WildCardString wildcard_str(sb_instance_name); 
+        /* If the wildcard name is already in the list, we can skip this
+         * Otherwise, we have to 
+         *   - output this instance 
+         *   - record the wildcard name in the map 
+         */
+        if ( (0 < wildcard_names.count(sb_module)) 
+          && (wildcard_names.at(sb_module).end() != std::find(wildcard_names.at(sb_module).begin(),
+                                                              wildcard_names.at(sb_module).end(),
+                                                              wildcard_str.data())) ) {
+          continue;
+        }
+
+        module_path += wildcard_str.data();
+ 
+        wildcard_names[sb_module].push_back(wildcard_str.data());
+      } else {
+        module_path += sb_instance_name;
+      }
+
+      module_path = format_dir_path(module_path);
+
+      std::vector<std::string> port_wildcard_names;
+
+      /* Disable the outputs of the module */
+      for (const BasicPort& output_port : module_manager.module_ports_by_type(sb_module, ModuleManager::MODULE_OUTPUT_PORT)) {
+        std::string port_name = output_port.get_name();        
+
+        if (false == flatten_names) { 
+          /* Try to adapt to a wildcard name: replace all the numbers with a wildcard character '*' */
+          WildCardString port_wildcard_str(output_port.get_name()); 
+          /* If the wildcard name is already in the list, we can skip this
+           * Otherwise, we have to 
+           *   - output this port 
+           *   - record the wildcard name in the vector
+           */
+          if (port_wildcard_names.end() != std::find(port_wildcard_names.begin(),
+                                                     port_wildcard_names.end(),
+                                                     port_wildcard_str.data())) {
+            continue;
+          }
+
+          port_name = port_wildcard_str.data();
+ 
+          port_wildcard_names.push_back(port_wildcard_str.data());
+        }
+
+        fp << "set_disable_timing ";
+        fp << module_path;
+        fp << port_name << std::endl;
+
+        fp << std::endl;
+      }
+    }
+  }
+  
+  /* Close file handler */
+  fp.close();
+}
+
+/********************************************************************
+ * Break combinational loops in FPGA fabric, which mainly come from 
+ * loops of multiplexers.
+ * To handle this, we disable the timing at outputs of Switch blocks
+ * This function is designed for compact routing hierarchy
+ *******************************************************************/
+static 
+void print_pnr_sdc_compact_routing_disable_switch_block_outputs(const std::string& sdc_dir,
+                                                                const bool& flatten_names,
+                                                                const ModuleManager& module_manager,
+                                                                const ModuleId& top_module,
+                                                                const DeviceRRGSB& device_rr_gsb) {
+  /* Create the file name for Verilog netlist */
+  std::string sdc_fname(sdc_dir + std::string(SDC_DISABLE_SB_OUTPUTS_FILE_NAME));
+
+  /* Start time count */
+  std::string timer_message = std::string("Write SDC to disable switch block outputs for P&R flow '") + sdc_fname + std::string("'");
+  vtr::ScopedStartFinishTimer timer(timer_message);
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(sdc_fname, std::fstream::out | std::fstream::trunc);
+
+  check_file_stream(sdc_fname.c_str(), fp);
+
+  /* Generate the descriptions*/
+  print_sdc_file_header(fp, std::string("Disable Switch Block outputs for PnR"));
+
+  std::string root_path = format_dir_path(module_manager.module_name(top_module));
+
+  /* Build wildcard names for the instance names of multiple-instanced-blocks (MIB) 
+   * We will find all the instance names and see there are common prefix 
+   * If so, we can use wildcards
+   */
+  std::map<ModuleId, std::vector<std::string>> wildcard_names;
+
   /* Build unique switch block modules */
   for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_module(); ++isb) {
     const RRGSB& rr_gsb = device_rr_gsb.get_sb_unique_module(isb);
@@ -217,13 +289,66 @@ void print_pnr_sdc_compact_routing_disable_switch_block_outputs(const std::strin
 
     ModuleId sb_module = module_manager.find_module(sb_module_name);
     VTR_ASSERT(true == module_manager.valid_module_id(sb_module));
+    
+    std::string module_path = root_path;
 
     /* Find all the instances in the top-level module */
     for (const size_t& instance_id : module_manager.child_module_instances(top_module, sb_module)) {
       std::string sb_instance_name = module_manager.instance_name(top_module, sb_module, instance_id);
+
+      if (false == flatten_names) { 
+        /* Try to adapt to a wildcard name: replace all the numbers with a wildcard character '*' */
+        WildCardString wildcard_str(sb_instance_name); 
+        /* If the wildcard name is already in the list, we can skip this
+         * Otherwise, we have to 
+         *   - output this instance 
+         *   - record the wildcard name in the map 
+         */
+        if ( (0 < wildcard_names.count(sb_module)) 
+          && (wildcard_names.at(sb_module).end() != std::find(wildcard_names.at(sb_module).begin(),
+                                                              wildcard_names.at(sb_module).end(),
+                                                              wildcard_str.data())) ) {
+          continue;
+        }
+
+        module_path += wildcard_str.data();
+ 
+        wildcard_names[sb_module].push_back(wildcard_str.data());
+      } else {
+        module_path += sb_instance_name;
+      }
+
+      module_path = format_dir_path(module_path);
+
+      std::vector<std::string> port_wildcard_names;
+
       /* Disable the outputs of the module */
       for (const BasicPort& output_port : module_manager.module_ports_by_type(sb_module, ModuleManager::MODULE_OUTPUT_PORT)) {
-        fp << "set_disable_timing " << sb_instance_name << "/" << output_port.get_name() << std::endl;
+        std::string port_name = output_port.get_name();        
+
+        if (false == flatten_names) { 
+          /* Try to adapt to a wildcard name: replace all the numbers with a wildcard character '*' */
+          WildCardString port_wildcard_str(output_port.get_name()); 
+          /* If the wildcard name is already in the list, we can skip this
+           * Otherwise, we have to 
+           *   - output this port 
+           *   - record the wildcard name in the vector
+           */
+          if (port_wildcard_names.end() != std::find(port_wildcard_names.begin(),
+                                                     port_wildcard_names.end(),
+                                                     port_wildcard_str.data())) {
+            continue;
+          }
+
+          port_name = port_wildcard_str.data();
+ 
+          port_wildcard_names.push_back(port_wildcard_str.data());
+        }
+
+        fp << "set_disable_timing ";
+        fp << module_path;
+        fp << port_name << std::endl;
+
         fp << std::endl;
       }
     }
@@ -282,12 +407,14 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options,
   if (true == sdc_options.constrain_switch_block_outputs()) {
     if (true == compact_routing_hierarchy) {
       print_pnr_sdc_compact_routing_disable_switch_block_outputs(sdc_options.sdc_dir(),
+                                                                 sdc_options.flatten_names(),
                                                                  module_manager, top_module,
                                                                  device_rr_gsb);
     } else {
       VTR_ASSERT_SAFE (false == compact_routing_hierarchy);
       print_pnr_sdc_flatten_routing_disable_switch_block_outputs(sdc_options.sdc_dir(),
-                                                                 module_manager,
+                                                                 sdc_options.flatten_names(),
+                                                                 module_manager, top_module,
                                                                  device_rr_gsb);
     }
   }

From 7503c58fb277c0a798bcd8f9f675d67f6d4f9e39 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 2 May 2020 16:33:43 -0600
Subject: [PATCH 499/645] small fix on SDC generator for SB which do not exist
 in FPGA

---
 openfpga/src/fpga_sdc/pnr_sdc_writer.cpp | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
index e3c5625ef..a26b67a71 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
+++ b/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
@@ -284,6 +284,11 @@ void print_pnr_sdc_compact_routing_disable_switch_block_outputs(const std::strin
   /* Build unique switch block modules */
   for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_module(); ++isb) {
     const RRGSB& rr_gsb = device_rr_gsb.get_sb_unique_module(isb);
+
+    if (false == rr_gsb.is_sb_exist()) {
+      continue;
+    }
+
     vtr::Point<size_t> gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
     std::string sb_module_name = generate_switch_block_module_name(gsb_coordinate); 
 

From 7e82c23f52af2d351e8387ffbb451fc93a5c6d85 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 2 May 2020 18:31:37 -0600
Subject: [PATCH 500/645] now add SDC generator supports both hierarchical and
 flatten in writing timing constraints

---
 openfpga/src/base/openfpga_sdc.cpp            |  2 +
 openfpga/src/base/openfpga_sdc_command.cpp    |  5 +-
 openfpga/src/fpga_sdc/pnr_sdc_option.cpp      |  9 +++
 openfpga/src/fpga_sdc/pnr_sdc_option.h        |  3 +
 .../src/fpga_sdc/pnr_sdc_routing_writer.cpp   | 81 +++++++++++++++++--
 .../src/fpga_sdc/pnr_sdc_routing_writer.h     |  4 +
 openfpga/src/fpga_sdc/pnr_sdc_writer.cpp      |  4 +
 openfpga/src/fpga_sdc/sdc_writer_utils.cpp    | 40 +++++++++
 openfpga/src/fpga_sdc/sdc_writer_utils.h      |  7 ++
 9 files changed, 149 insertions(+), 6 deletions(-)

diff --git a/openfpga/src/base/openfpga_sdc.cpp b/openfpga/src/base/openfpga_sdc.cpp
index c0c5b3f22..9fa360cff 100644
--- a/openfpga/src/base/openfpga_sdc.cpp
+++ b/openfpga/src/base/openfpga_sdc.cpp
@@ -30,6 +30,7 @@ int write_pnr_sdc(OpenfpgaContext& openfpga_ctx,
 
   CommandOptionId opt_output_dir = cmd.option("file");
   CommandOptionId opt_flatten_names = cmd.option("flatten_names");
+  CommandOptionId opt_hierarchical = cmd.option("hierarchical");
   CommandOptionId opt_constrain_global_port = cmd.option("constrain_global_port");
   CommandOptionId opt_constrain_non_clock_global_port = cmd.option("constrain_non_clock_global_port");
   CommandOptionId opt_constrain_grid = cmd.option("constrain_grid");
@@ -51,6 +52,7 @@ int write_pnr_sdc(OpenfpgaContext& openfpga_ctx,
   PnrSdcOption options(sdc_dir_path);
 
   options.set_flatten_names(cmd_context.option_enable(cmd, opt_flatten_names));
+  options.set_hierarchical(cmd_context.option_enable(cmd, opt_hierarchical));
   options.set_constrain_global_port(cmd_context.option_enable(cmd, opt_constrain_global_port));
   options.set_constrain_non_clock_global_port(cmd_context.option_enable(cmd, opt_constrain_non_clock_global_port));
   options.set_constrain_grid(cmd_context.option_enable(cmd, opt_constrain_grid));
diff --git a/openfpga/src/base/openfpga_sdc_command.cpp b/openfpga/src/base/openfpga_sdc_command.cpp
index 77c581da2..479cb8de9 100644
--- a/openfpga/src/base/openfpga_sdc_command.cpp
+++ b/openfpga/src/base/openfpga_sdc_command.cpp
@@ -29,6 +29,9 @@ ShellCommandId add_openfpga_write_pnr_sdc_command(openfpga::Shell<OpenfpgaContex
   /* Add an option '--flatten_name' */
   shell_cmd.add_option("flatten_names", false, "Use flatten names (no wildcards) in SDC files");
 
+  /* Add an option '--hierarchical' */
+  shell_cmd.add_option("hierarchical", false, "Output SDC files hierachically (without full path in hierarchy)");
+
   /* Add an option '--constrain_global_port' */
   shell_cmd.add_option("constrain_global_port", false, "Constrain all the global ports of FPGA fabric");
 
@@ -91,7 +94,7 @@ ShellCommandId add_openfpga_write_analysis_sdc_command(openfpga::Shell<OpenfpgaC
 
   /* Add an option '--flatten_name' */
   shell_cmd.add_option("flatten_names", false, "Use flatten names (no wildcards) in SDC files");
-  
+
   /* Add command 'write_fabric_verilog' to the Shell */
   ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "generate SDC files for timing analysis a PnRed FPGA fabric mapped by a benchmark");
   shell.set_command_class(shell_cmd_id, cmd_class_id);
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_option.cpp b/openfpga/src/fpga_sdc/pnr_sdc_option.cpp
index bf87cac8e..3b7c417e0 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_option.cpp
+++ b/openfpga/src/fpga_sdc/pnr_sdc_option.cpp
@@ -11,6 +11,7 @@ namespace openfpga {
  ********************************************************************/
 PnrSdcOption::PnrSdcOption(const std::string& sdc_dir) {
   sdc_dir_ = sdc_dir;
+  hierarchical_ = false;
   flatten_names_ = false;
   constrain_global_port_ = false;
   constrain_non_clock_global_port_ = false;
@@ -34,6 +35,10 @@ bool PnrSdcOption::flatten_names() const {
   return flatten_names_;
 }
 
+bool PnrSdcOption::hierarchical() const {
+  return hierarchical_;
+}
+
 bool PnrSdcOption::generate_sdc_pnr() const {
   return constrain_global_port_ 
       || constrain_grid_
@@ -91,6 +96,10 @@ void PnrSdcOption::set_flatten_names(const bool& flatten_names) {
   flatten_names_ = flatten_names;
 }
 
+void PnrSdcOption::set_hierarchical(const bool& hierarchical) {
+  hierarchical_ = hierarchical;
+}
+
 void PnrSdcOption::set_generate_sdc_pnr(const bool& generate_sdc_pnr) {
   constrain_global_port_ = generate_sdc_pnr;
   constrain_grid_ = generate_sdc_pnr;
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_option.h b/openfpga/src/fpga_sdc/pnr_sdc_option.h
index 49a1f18ed..ff52a75fd 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_option.h
+++ b/openfpga/src/fpga_sdc/pnr_sdc_option.h
@@ -17,6 +17,7 @@ class PnrSdcOption {
   public: /* Public accessors */
     std::string sdc_dir() const;
     bool flatten_names() const;
+    bool hierarchical() const;
     bool generate_sdc_pnr() const;
     bool constrain_global_port() const;
     bool constrain_non_clock_global_port() const;
@@ -30,6 +31,7 @@ class PnrSdcOption {
   public: /* Public mutators */
     void set_sdc_dir(const std::string& sdc_dir);
     void set_flatten_names(const bool& flatten_names);
+    void set_hierarchical(const bool& hierarchical);
     void set_generate_sdc_pnr(const bool& generate_sdc_pnr);
     void set_constrain_global_port(const bool& constrain_global_port);
     void set_constrain_non_clock_global_port(const bool& constrain_non_clock_global_port);
@@ -43,6 +45,7 @@ class PnrSdcOption {
   private: /* Internal data */
     std::string sdc_dir_;
     bool flatten_names_;
+    bool hierarchical_;
     bool constrain_global_port_; 
     bool constrain_non_clock_global_port_; 
     bool constrain_grid_; 
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp
index 4bed8f16a..6f7d77c69 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp
+++ b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp
@@ -49,6 +49,8 @@ float find_pnr_sdc_switch_tmax(const t_rr_switch_inf& switch_inf) {
  *******************************************************************/
 static 
 void print_pnr_sdc_constrain_sb_mux_timing(std::fstream& fp,
+                                           const bool& hierarchical,
+                                           const std::string& module_path,
                                            const ModuleManager& module_manager,
                                            const ModuleId& sb_module, 
                                            const RRGraph& rr_graph,
@@ -96,11 +98,22 @@ void print_pnr_sdc_constrain_sb_mux_timing(std::fstream& fp,
       continue;
     }
     /* Constrain a path */
-    print_pnr_sdc_constrain_port2port_timing(fp,
-                                             module_manager, 
-                                             sb_module, module_input_port, 
-                                             sb_module, module_output_port,
-                                             switch_delays[module_input_port]);
+    if (false == hierarchical) {
+      print_pnr_sdc_regexp_constrain_max_delay(fp,
+                                               module_path,
+                                               generate_sdc_port(module_manager.module_port(sb_module, module_input_port)),
+                                               module_path,
+                                               generate_sdc_port(module_manager.module_port(sb_module, module_output_port)),
+                                               switch_delays[module_input_port]);
+
+    } else {
+      VTR_ASSERT_SAFE(true == hierarchical);
+      print_pnr_sdc_constrain_port2port_timing(fp,
+                                               module_manager, 
+                                               sb_module, module_input_port, 
+                                               sb_module, module_output_port,
+                                               switch_delays[module_input_port]);
+    }
   }
 }
 
@@ -114,6 +127,8 @@ void print_pnr_sdc_constrain_sb_mux_timing(std::fstream& fp,
  *******************************************************************/
 static 
 void print_pnr_sdc_constrain_sb_timing(const std::string& sdc_dir,
+                                       const bool& hierarchical,
+                                       const std::string& module_path,
                                        const ModuleManager& module_manager,
                                        const RRGraph& rr_graph,
                                        const RRGSB& rr_gsb,
@@ -151,6 +166,8 @@ void print_pnr_sdc_constrain_sb_timing(const std::string& sdc_dir,
       } 
       /* This is a MUX, constrain all the paths from an input to an output */
       print_pnr_sdc_constrain_sb_mux_timing(fp,
+                                            hierarchical,
+                                            module_path,
                                             module_manager, sb_module, 
                                             rr_graph,
                                             rr_gsb,
@@ -169,7 +186,9 @@ void print_pnr_sdc_constrain_sb_timing(const std::string& sdc_dir,
  * This function is designed for flatten routing hierarchy
  *******************************************************************/
 void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_dir,
+                                                       const bool& hierarchical,
                                                        const ModuleManager& module_manager,
+                                                       const ModuleId& top_module,
                                                        const RRGraph& rr_graph,
                                                        const DeviceRRGSB& device_rr_gsb,
                                                        const bool& constrain_zero_delay_paths) {
@@ -177,6 +196,8 @@ void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_di
   /* Start time count */
   vtr::ScopedStartFinishTimer timer("Write SDC for constrain Switch Block timing for P&R flow");
 
+  std::string root_path = module_manager.module_name(top_module);
+
   /* Get the range of SB array */
   vtr::Point<size_t> sb_range = device_rr_gsb.get_gsb_range();
   /* Go for each SB */
@@ -186,7 +207,24 @@ void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_di
       if (false == rr_gsb.is_sb_exist()) {
         continue;
       }
+
+      vtr::Point<size_t> gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
+      std::string sb_instance_name = generate_switch_block_module_name(gsb_coordinate); 
+
+      ModuleId sb_module = module_manager.find_module(sb_instance_name);
+      VTR_ASSERT(true == module_manager.valid_module_id(sb_module));
+
+      std::string module_path = root_path
+                              + std::string("\\/")
+                              + std::string("(");
+
+      /* Find all the instances in the top-level module */
+      module_path += sb_instance_name;
+      module_path += std::string(")") + std::string("\\");
+
       print_pnr_sdc_constrain_sb_timing(sdc_dir,
+                                        hierarchical,
+                                        module_path,
                                         module_manager,
                                         rr_graph,
                                         rr_gsb,
@@ -200,7 +238,9 @@ void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_di
  * This function is designed for compact routing hierarchy
  *******************************************************************/
 void print_pnr_sdc_compact_routing_constrain_sb_timing(const std::string& sdc_dir,
+                                                       const bool& hierarchical,
                                                        const ModuleManager& module_manager,
+                                                       const ModuleId& top_module,
                                                        const RRGraph& rr_graph,
                                                        const DeviceRRGSB& device_rr_gsb,
                                                        const bool& constrain_zero_delay_paths) {
@@ -208,12 +248,43 @@ void print_pnr_sdc_compact_routing_constrain_sb_timing(const std::string& sdc_di
   /* Start time count */
   vtr::ScopedStartFinishTimer timer("Write SDC for constrain Switch Block timing for P&R flow");
 
+  std::string root_path = module_manager.module_name(top_module);
+
   for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_module(); ++isb) {
     const RRGSB& rr_gsb = device_rr_gsb.get_sb_unique_module(isb);
     if (false == rr_gsb.is_sb_exist()) {
       continue;
     }
+
+    /* Find all the sb instance under this module
+     * Create a regular expression to include these instance names 
+     */
+    vtr::Point<size_t> gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
+    std::string sb_module_name = generate_switch_block_module_name(gsb_coordinate); 
+
+    ModuleId sb_module = module_manager.find_module(sb_module_name);
+    VTR_ASSERT(true == module_manager.valid_module_id(sb_module));
+    
+    std::string module_path = root_path
+                            + std::string("\\/")
+                            + std::string("(");
+
+    /* Find all the instances in the top-level module */
+    bool first_element = true;
+    for (const size_t& instance_id : module_manager.child_module_instances(top_module, sb_module)) {
+      std::string sb_instance_name = module_manager.instance_name(top_module, sb_module, instance_id);
+      if (false == first_element) {
+        module_path += std::string("|");
+      }
+      module_path += sb_instance_name;
+      first_element = false;
+    }
+
+    module_path += std::string(")") + std::string("\\");
+
     print_pnr_sdc_constrain_sb_timing(sdc_dir,
+                                      hierarchical,
+                                      module_path,
                                       module_manager,
                                       rr_graph,
                                       rr_gsb,
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.h b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.h
index 0ced07938..aa0d04cbc 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.h
+++ b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.h
@@ -18,13 +18,17 @@
 namespace openfpga {
 
 void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_dir,
+                                                       const bool& hierarchical,
                                                        const ModuleManager& module_manager,
+                                                       const ModuleId& top_module,
                                                        const RRGraph& rr_graph,
                                                        const DeviceRRGSB& device_rr_gsb,
                                                        const bool& constrain_zero_delay_paths);
 
 void print_pnr_sdc_compact_routing_constrain_sb_timing(const std::string& sdc_dir,
+                                                       const bool& hierarchical,
                                                        const ModuleManager& module_manager,
+                                                       const ModuleId& top_module,
                                                        const RRGraph& rr_graph,
                                                        const DeviceRRGSB& device_rr_gsb,
                                                        const bool& constrain_zero_delay_paths);
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
index a26b67a71..4b363d7d7 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
+++ b/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
@@ -428,14 +428,18 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options,
   if (true == sdc_options.constrain_sb()) {
     if (true == compact_routing_hierarchy) {
       print_pnr_sdc_compact_routing_constrain_sb_timing(sdc_options.sdc_dir(),
+                                                        sdc_options.hierarchical(),
                                                         module_manager,
+                                                        top_module,
                                                         device_ctx.rr_graph,
                                                         device_rr_gsb,
                                                         sdc_options.constrain_zero_delay_paths());
     } else {
 	  VTR_ASSERT_SAFE (false == compact_routing_hierarchy);
       print_pnr_sdc_flatten_routing_constrain_sb_timing(sdc_options.sdc_dir(),
+                                                        sdc_options.hierarchical(),
                                                         module_manager,
+                                                        top_module,
                                                         device_ctx.rr_graph,
                                                         device_rr_gsb,
                                                         sdc_options.constrain_zero_delay_paths());
diff --git a/openfpga/src/fpga_sdc/sdc_writer_utils.cpp b/openfpga/src/fpga_sdc/sdc_writer_utils.cpp
index 4f021034c..13b70fec4 100644
--- a/openfpga/src/fpga_sdc/sdc_writer_utils.cpp
+++ b/openfpga/src/fpga_sdc/sdc_writer_utils.cpp
@@ -101,6 +101,46 @@ void print_pnr_sdc_constrain_max_delay(std::fstream& fp,
   fp << std::endl;
 }
 
+/********************************************************************
+ * Constrain a path between two ports of a module with a given maximum timing value
+ * This function use regular expression and get_pins which are 
+ * from open-source SDC 2.1 format
+ *******************************************************************/
+void print_pnr_sdc_regexp_constrain_max_delay(std::fstream& fp,
+                                              const std::string& src_instance_name,
+                                              const std::string& src_port_name,
+                                              const std::string& des_instance_name,
+                                              const std::string& des_port_name,
+                                              const float& delay) {
+  /* Validate file stream */
+  valid_file_stream(fp);
+
+  fp << "set_max_delay";
+
+  fp << " -from ";
+  fp << "[get_pins -regexp \"";
+  if (!src_instance_name.empty()) {
+    fp << src_instance_name << "/";
+  }
+  fp << src_port_name;
+
+  fp << "\"]";
+
+  fp << " -to ";
+  fp << "[get_pins -regexp \"";
+ 
+  if (!des_instance_name.empty()) {
+    fp << des_instance_name << "/";
+  }
+  fp << des_port_name;
+
+  fp << "\"]";
+
+  fp << " " << std::setprecision(10) << delay;
+
+  fp << std::endl;
+}
+
 /********************************************************************
  * Constrain a path between two ports of a module with a given minimum timing value
  *******************************************************************/
diff --git a/openfpga/src/fpga_sdc/sdc_writer_utils.h b/openfpga/src/fpga_sdc/sdc_writer_utils.h
index 80f6e97e9..c7a7cd3a1 100644
--- a/openfpga/src/fpga_sdc/sdc_writer_utils.h
+++ b/openfpga/src/fpga_sdc/sdc_writer_utils.h
@@ -28,6 +28,13 @@ void print_pnr_sdc_constrain_max_delay(std::fstream& fp,
                                        const std::string& des_port_name,
                                        const float& delay);
 
+void print_pnr_sdc_regexp_constrain_max_delay(std::fstream& fp,
+                                              const std::string& src_instance_name,
+                                              const std::string& src_port_name,
+                                              const std::string& des_instance_name,
+                                              const std::string& des_port_name,
+                                              const float& delay);
+
 void print_pnr_sdc_constrain_min_delay(std::fstream& fp,
                                        const std::string& src_instance_name,
                                        const std::string& src_port_name,

From d18e924a899e16eab1c279d1c9fd2e07b80d234c Mon Sep 17 00:00:00 2001
From: Xifan Tang <tangxifan@gmail.com>
Date: Sat, 2 May 2020 18:38:00 -0600
Subject: [PATCH 501/645] Update documentation on new fpga_sdc option

---
 docs/source/openfpga_shell/openfpga_commands.rst | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/docs/source/openfpga_shell/openfpga_commands.rst b/docs/source/openfpga_shell/openfpga_commands.rst
index 12a1d89c7..d3020e9c1 100644
--- a/docs/source/openfpga_shell/openfpga_commands.rst
+++ b/docs/source/openfpga_shell/openfpga_commands.rst
@@ -176,6 +176,8 @@ FPGA-SDC
   
   - ``--file`` or ``-f`` Specify the output directory for SDC files
 
+  - ``--hierarchical`` Output SDC files without full path in hierarchy
+
   - ``--flatten_names`` Use flatten names (no wildcards) in SDC files
 
   - ``--constrain_global_port`` Constrain all the global ports of FPGA fabric.

From 609115e51f635c86eab258edad976250fa3baede Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 2 May 2020 19:02:35 -0600
Subject: [PATCH 502/645] now hierarchical SDC generation is applicable to CB
 timing constraints

---
 .../src/fpga_sdc/pnr_sdc_routing_writer.cpp   | 137 ++++++++++++++++--
 .../src/fpga_sdc/pnr_sdc_routing_writer.h     |   4 +
 openfpga/src/fpga_sdc/pnr_sdc_writer.cpp      |   4 +
 3 files changed, 133 insertions(+), 12 deletions(-)

diff --git a/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp
index 6f7d77c69..60e756839 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp
+++ b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp
@@ -298,6 +298,8 @@ void print_pnr_sdc_compact_routing_constrain_sb_timing(const std::string& sdc_di
  *******************************************************************/
 static 
 void print_pnr_sdc_constrain_cb_mux_timing(std::fstream& fp,
+                                           const bool& hierarchical,
+                                           const std::string& module_path,
                                            const ModuleManager& module_manager,
                                            const ModuleId& cb_module, 
                                            const RRGraph& rr_graph,
@@ -366,11 +368,22 @@ void print_pnr_sdc_constrain_cb_mux_timing(std::fstream& fp,
     }
 
     /* Constrain a path */
-    print_pnr_sdc_constrain_port2port_timing(fp,
-                                             module_manager, 
-                                             cb_module, module_input_port, 
-                                             cb_module, module_output_port,
-                                             switch_delays[module_input_port]);
+    if (true == hierarchical) {
+      print_pnr_sdc_constrain_port2port_timing(fp,
+                                               module_manager, 
+                                               cb_module, module_input_port, 
+                                               cb_module, module_output_port,
+                                               switch_delays[module_input_port]);
+    } else {
+      VTR_ASSERT_SAFE(false == hierarchical);
+      print_pnr_sdc_regexp_constrain_max_delay(fp,
+                                               std::string(module_path),
+                                               generate_sdc_port(module_manager.module_port(cb_module, module_input_port)),
+                                               std::string(module_path),
+                                               generate_sdc_port(module_manager.module_port(cb_module, module_output_port)),
+                                               switch_delays[module_input_port]);
+
+    }
   }
 }
 
@@ -380,6 +393,8 @@ void print_pnr_sdc_constrain_cb_mux_timing(std::fstream& fp,
  *******************************************************************/
 static 
 void print_pnr_sdc_constrain_cb_timing(const std::string& sdc_dir,
+                                       const bool& hierarchical,
+                                       const std::string& module_path,
                                        const ModuleManager& module_manager,
                                        const RRGraph& rr_graph,
                                        const RRGSB& rr_gsb, 
@@ -443,11 +458,21 @@ void print_pnr_sdc_constrain_cb_timing(const std::string& sdc_dir,
     }
 
     /* Constrain a path with routing segment delay */
-    print_pnr_sdc_constrain_port2port_timing(fp,
-                                             module_manager, 
-                                             cb_module, input_port_id, 
-                                             cb_module, output_port_id,
-                                             routing_segment_delay);
+    if (true == hierarchical) {
+      print_pnr_sdc_constrain_port2port_timing(fp,
+                                               module_manager, 
+                                               cb_module, input_port_id, 
+                                               cb_module, output_port_id,
+                                               routing_segment_delay);
+    } else {
+      VTR_ASSERT_SAFE(false == hierarchical);
+      print_pnr_sdc_regexp_constrain_max_delay(fp,
+                                               std::string(module_path),
+                                               generate_sdc_port(module_manager.module_port(cb_module, input_port_id)),
+                                               std::string(module_path),
+                                               generate_sdc_port(module_manager.module_port(cb_module, output_port_id)),
+                                               routing_segment_delay);
+    }
   }
 
   /* Contrain each multiplexers inside the connection block */
@@ -459,6 +484,7 @@ void print_pnr_sdc_constrain_cb_timing(const std::string& sdc_dir,
     for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) {
       const RRNodeId& ipin_rr_node = rr_gsb.get_ipin_node(cb_ipin_side, inode);
       print_pnr_sdc_constrain_cb_mux_timing(fp,
+                                            hierarchical, module_path,
                                             module_manager, cb_module, 
                                             rr_graph, rr_gsb, cb_type,
                                             ipin_rr_node,
@@ -476,7 +502,9 @@ void print_pnr_sdc_constrain_cb_timing(const std::string& sdc_dir,
  *******************************************************************/
 static 
 void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_dir,
+                                                       const bool& hierarchical,
                                                        const ModuleManager& module_manager, 
+                                                       const ModuleId& top_module,
                                                        const RRGraph& rr_graph,
                                                        const DeviceRRGSB& device_rr_gsb,
                                                        const t_rr_type& cb_type,
@@ -484,6 +512,8 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_di
   /* Build unique X-direction connection block modules */
   vtr::Point<size_t> cb_range = device_rr_gsb.get_gsb_range();
 
+  std::string root_path = module_manager.module_name(top_module);
+
   for (size_t ix = 0; ix < cb_range.x(); ++ix) {
     for (size_t iy = 0; iy < cb_range.y(); ++iy) {
       /* Check if the connection block exists in the device!
@@ -494,7 +524,26 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_di
       if (false == rr_gsb.is_cb_exist(cb_type)) {
         continue;
       }
+
+      /* Find all the cb instance under this module
+       * Create a regular expression to include these instance names 
+       */
+      vtr::Point<size_t> gsb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type));
+      std::string cb_instance_name = generate_connection_block_module_name(cb_type, gsb_coordinate); 
+      ModuleId cb_module = module_manager.find_module(cb_instance_name);
+      VTR_ASSERT(true == module_manager.valid_module_id(cb_module));
+
+      std::string module_path = root_path
+                              + std::string("\\/")
+                              + std::string("(");
+
+      /* Find all the instances in the top-level module */
+      module_path += cb_instance_name;
+      module_path += std::string(")") + std::string("\\");
+
       print_pnr_sdc_constrain_cb_timing(sdc_dir,
+                                        hierarchical,
+                                        module_path,
                                         module_manager,
                                         rr_graph, 
                                         rr_gsb, 
@@ -510,7 +559,9 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_di
  * and print SDC file for each of them 
  *******************************************************************/
 void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_dir,
+                                                       const bool& hierarchical,
                                                        const ModuleManager& module_manager, 
+                                                       const ModuleId& top_module,
                                                        const RRGraph& rr_graph,
                                                        const DeviceRRGSB& device_rr_gsb,
                                                        const bool& constrain_zero_delay_paths) {
@@ -518,13 +569,15 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_di
   /* Start time count */
   vtr::ScopedStartFinishTimer timer("Write SDC for constrain Connection Block timing for P&R flow");
 
-  print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_dir, module_manager, 
+  print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_dir, hierarchical,
+                                                    module_manager, top_module,
                                                     rr_graph,
                                                     device_rr_gsb,
                                                     CHANX,
                                                     constrain_zero_delay_paths);
 
-  print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_dir, module_manager, 
+  print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_dir, hierarchical, 
+                                                    module_manager, top_module,
                                                     rr_graph,
                                                     device_rr_gsb,
                                                     CHANY,
@@ -536,7 +589,9 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_di
  * This function is designed for compact routing hierarchy
  *******************************************************************/
 void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_dir,
+                                                       const bool& hierarchical,
                                                        const ModuleManager& module_manager,
+                                                       const ModuleId& top_module,
                                                        const RRGraph& rr_graph,
                                                        const DeviceRRGSB& device_rr_gsb,
                                                        const bool& constrain_zero_delay_paths) {
@@ -544,10 +599,40 @@ void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_di
   /* Start time count */
   vtr::ScopedStartFinishTimer timer("Write SDC for constrain Connection Block timing for P&R flow");
 
+  std::string root_path = module_manager.module_name(top_module);
+
   /* Print SDC for unique X-direction connection block modules */
   for (size_t icb = 0; icb < device_rr_gsb.get_num_cb_unique_module(CHANX); ++icb) {
     const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANX, icb);
+
+    /* Find all the cb instance under this module
+     * Create a regular expression to include these instance names 
+     */
+    vtr::Point<size_t> gsb_coordinate(unique_mirror.get_cb_x(CHANX), unique_mirror.get_cb_y(CHANX));
+    std::string cb_module_name = generate_connection_block_module_name(CHANX, gsb_coordinate); 
+    ModuleId cb_module = module_manager.find_module(cb_module_name);
+    VTR_ASSERT(true == module_manager.valid_module_id(cb_module));
+
+    std::string module_path = root_path
+                            + std::string("\\/")
+                            + std::string("(");
+
+    /* Find all the instances in the top-level module */
+    bool first_element = true;
+    for (const size_t& instance_id : module_manager.child_module_instances(top_module, cb_module)) {
+      std::string cb_instance_name = module_manager.instance_name(top_module, cb_module, instance_id);
+      if (false == first_element) {
+        module_path += std::string("|");
+      }
+      module_path += cb_instance_name;
+      first_element = false;
+    }
+
+    module_path += std::string(")") + std::string("\\");
+
     print_pnr_sdc_constrain_cb_timing(sdc_dir,
+                                      hierarchical,
+                                      module_path,
                                       module_manager,
                                       rr_graph, 
                                       unique_mirror, 
@@ -558,7 +643,35 @@ void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_di
   /* Print SDC for unique Y-direction connection block modules */
   for (size_t icb = 0; icb < device_rr_gsb.get_num_cb_unique_module(CHANY); ++icb) {
     const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANY, icb);
+
+    /* Find all the cb instance under this module
+     * Create a regular expression to include these instance names 
+     */
+    vtr::Point<size_t> gsb_coordinate(unique_mirror.get_cb_x(CHANY), unique_mirror.get_cb_y(CHANY));
+    std::string cb_module_name = generate_connection_block_module_name(CHANY, gsb_coordinate); 
+    ModuleId cb_module = module_manager.find_module(cb_module_name);
+    VTR_ASSERT(true == module_manager.valid_module_id(cb_module));
+
+    std::string module_path = root_path
+                            + std::string("\\/")
+                            + std::string("(");
+
+    /* Find all the instances in the top-level module */
+    bool first_element = true;
+    for (const size_t& instance_id : module_manager.child_module_instances(top_module, cb_module)) {
+      std::string cb_instance_name = module_manager.instance_name(top_module, cb_module, instance_id);
+      if (false == first_element) {
+        module_path += std::string("|");
+      }
+      module_path += cb_instance_name;
+      first_element = false;
+    }
+
+    module_path += std::string(")") + std::string("\\");
+
     print_pnr_sdc_constrain_cb_timing(sdc_dir,
+                                      hierarchical,
+                                      module_path,
                                       module_manager,
                                       rr_graph, 
                                       unique_mirror, 
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.h b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.h
index aa0d04cbc..a29a7ac56 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.h
+++ b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.h
@@ -34,13 +34,17 @@ void print_pnr_sdc_compact_routing_constrain_sb_timing(const std::string& sdc_di
                                                        const bool& constrain_zero_delay_paths);
 
 void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_dir,
+                                                       const bool& hierarchical,
                                                        const ModuleManager& module_manager, 
+                                                       const ModuleId& top_module,
                                                        const RRGraph& rr_graph,
                                                        const DeviceRRGSB& device_rr_gsb,
                                                        const bool& constrain_zero_delay_paths);
 
 void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_dir,
+                                                       const bool& hierarchical,
                                                        const ModuleManager& module_manager,
+                                                       const ModuleId& top_module,
                                                        const RRGraph& rr_graph,
                                                        const DeviceRRGSB& device_rr_gsb,
                                                        const bool& constrain_zero_delay_paths);
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
index 4b363d7d7..167ec497b 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
+++ b/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
@@ -450,14 +450,18 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options,
   if (true == sdc_options.constrain_cb()) {
     if (true == compact_routing_hierarchy) {
       print_pnr_sdc_compact_routing_constrain_cb_timing(sdc_options.sdc_dir(),
+                                                        sdc_options.hierarchical(),
                                                         module_manager,
+                                                        top_module,
                                                         device_ctx.rr_graph,
                                                         device_rr_gsb,
                                                         sdc_options.constrain_zero_delay_paths());
     } else {
 	  VTR_ASSERT_SAFE (false == compact_routing_hierarchy);
       print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_options.sdc_dir(),
+                                                        sdc_options.hierarchical(),
                                                         module_manager, 
+                                                        top_module,
                                                         device_ctx.rr_graph,
                                                         device_rr_gsb,
                                                         sdc_options.constrain_zero_delay_paths());

From 0e44cf3ea353b78c6d7108c1c867dbb0f26395bf Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 2 May 2020 21:09:00 -0600
Subject: [PATCH 503/645] now SDC to disable routing multiplexer outputs can
 use wildcards

---
 openfpga/src/fpga_sdc/pnr_sdc_writer.cpp |  34 +++++--
 openfpga/src/fpga_sdc/sdc_mux_utils.cpp  | 113 +++++++++++++++++++++++
 openfpga/src/fpga_sdc/sdc_mux_utils.h    |  28 ++++++
 3 files changed, 165 insertions(+), 10 deletions(-)
 create mode 100644 openfpga/src/fpga_sdc/sdc_mux_utils.cpp
 create mode 100644 openfpga/src/fpga_sdc/sdc_mux_utils.h

diff --git a/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
index 167ec497b..c88e3e2ef 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
+++ b/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
@@ -29,6 +29,7 @@
 #include "sdc_writer_naming.h"
 #include "sdc_writer_utils.h"
 #include "sdc_memory_utils.h"
+#include "sdc_mux_utils.h"
 #include "pnr_sdc_global_port.h"
 #include "pnr_sdc_routing_writer.h"
 #include "pnr_sdc_grid_writer.h"
@@ -80,9 +81,11 @@ void print_pnr_sdc_constrain_configurable_memory_outputs(const std::string& sdc_
  *******************************************************************/
 static 
 void print_sdc_disable_routing_multiplexer_outputs(const std::string& sdc_dir,
+                                                   const bool& flatten_names,
                                                    const MuxLibrary& mux_lib,
                                                    const CircuitLibrary& circuit_lib,
-                                                   const ModuleManager& module_manager) {
+                                                   const ModuleManager& module_manager,
+                                                   const ModuleId& top_module) {
   /* Create the file name for Verilog netlist */
   std::string sdc_fname(sdc_dir + std::string(SDC_DISABLE_MUX_OUTPUTS_FILE_NAME));
 
@@ -112,16 +115,22 @@ void print_sdc_disable_routing_multiplexer_outputs(const std::string& sdc_dir,
     std::string mux_module_name = generate_mux_subckt_name(circuit_lib, mux_model, 
                                                            find_mux_num_datapath_inputs(circuit_lib, mux_model, mux_graph.num_inputs()), 
                                                            std::string(""));
+
     /* Find the module name in module manager */
     ModuleId mux_module = module_manager.find_module(mux_module_name);
     VTR_ASSERT(true == module_manager.valid_module_id(mux_module));
-     
-    /* Disable the timing for the output ports */ 
-    for (const BasicPort& output_port : module_manager.module_ports_by_type(mux_module, ModuleManager::MODULE_OUTPUT_PORT)) {
-      fp << "set_disable_timing [get_pins -filter \"name =~ " << output_port.get_name() << "*\" ";
-      fp << "-of [get_cells -hier -filter \"ref_lib_cell_name == " << mux_module_name << "\"]]" << std::endl;
-      fp << std::endl;
-    }
+
+    /* Go recursively in the module manager, 
+     * starting from the top-level module: instance id of the top-level module is 0 by default 
+     * Disable all the outputs of child modules that matches the mux_module id
+     */
+    rec_print_pnr_sdc_disable_routing_multiplexer_outputs(fp,
+                                                          flatten_names,
+                                                          module_manager,
+                                                          top_module,
+                                                          mux_module,
+                                                          format_dir_path(module_manager.module_name(top_module)));
+
   }
 
   /* Close file handler */
@@ -398,14 +407,19 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options,
 
   /* Output Design Constraints to disable outputs of memory cells */
   if (true == sdc_options.constrain_configurable_memory_outputs()) {
-    print_pnr_sdc_constrain_configurable_memory_outputs(sdc_options.sdc_dir(), sdc_options.flatten_names(), module_manager, top_module); 
+    print_pnr_sdc_constrain_configurable_memory_outputs(sdc_options.sdc_dir(),
+                                                        sdc_options.flatten_names(),
+                                                        module_manager,
+                                                        top_module); 
   } 
 
   /* Break loops from Multiplexer Output */
   if (true == sdc_options.constrain_routing_multiplexer_outputs()) {
     print_sdc_disable_routing_multiplexer_outputs(sdc_options.sdc_dir(),
+                                                  sdc_options.flatten_names(),
                                                   mux_lib, circuit_lib,
-                                                  module_manager);
+                                                  module_manager,
+                                                  top_module);
   }
 
   /* Break loops from any SB output */
diff --git a/openfpga/src/fpga_sdc/sdc_mux_utils.cpp b/openfpga/src/fpga_sdc/sdc_mux_utils.cpp
new file mode 100644
index 000000000..ee30eae9b
--- /dev/null
+++ b/openfpga/src/fpga_sdc/sdc_mux_utils.cpp
@@ -0,0 +1,113 @@
+/********************************************************************
+ * Most utilized function used to constrain routing multiplexers in FPGA
+ * fabric using SDC commands
+ *******************************************************************/
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_wildcard_string.h"
+#include "openfpga_digest.h"
+
+#include "openfpga_naming.h"
+
+#include "sdc_writer_utils.h"
+
+#include "sdc_mux_utils.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Print SDC commands to disable outputs of routing multiplexer modules
+ * in a given module id 
+ * This function will be executed in a recursive way, 
+ * using a Depth-First Search (DFS) strategy
+ * It will iterate over all the configurable children under each module
+ * and print a SDC command to disable its outputs
+ *
+ * Note:
+ *   - When flatten_names is true
+ *     this function will not apply any wildcard to names
+ *   - When flatten_names is false
+ *     It will straightforwardly output the instance name and port name
+ *     This function will try to apply wildcard to names
+ *     so that SDC file size can be minimal 
+ *******************************************************************/
+void rec_print_pnr_sdc_disable_routing_multiplexer_outputs(std::fstream& fp, 
+                                                           const bool& flatten_names,
+                                                           const ModuleManager& module_manager, 
+                                                           const ModuleId& parent_module,
+                                                           const ModuleId& mux_module,
+                                                           const std::string& parent_module_path) {
+
+  /* Build wildcard names for the instance names of multiple-instanced-blocks (MIB) 
+   * We will find all the instance names and see there are common prefix 
+   * If so, we can use wildcards
+   */
+  std::map<ModuleId, std::vector<std::string>> wildcard_names;
+
+  /* For each child, we will go one level down in priority */
+  for (const ModuleId& child_module : module_manager.child_modules(parent_module)) {
+
+    std::string child_module_path = parent_module_path;
+
+    /* Iterate over the child instances*/
+    for (const size_t& child_instance : module_manager.child_module_instances(parent_module, child_module)) {
+      std::string child_instance_name;
+      if (true == module_manager.instance_name(parent_module, child_module, child_instance).empty()) {
+        child_instance_name = generate_instance_name(module_manager.module_name(child_module), child_instance);
+      } else {
+        child_instance_name = module_manager.instance_name(parent_module, child_module, child_instance);
+      }
+
+      if (false == flatten_names) { 
+        /* Try to adapt to a wildcard name: replace all the numbers with a wildcard character '*' */
+        WildCardString wildcard_str(child_instance_name); 
+        /* If the wildcard name is already in the list, we can skip this
+         * Otherwise, we have to 
+         *   - output this instance 
+         *   - record the wildcard name in the map 
+         */
+        if ( (0 < wildcard_names.count(child_module)) 
+          && (wildcard_names.at(child_module).end() != std::find(wildcard_names.at(child_module).begin(),
+                                                                 wildcard_names.at(child_module).end(),
+                                                                 wildcard_str.data())) ) {
+          continue;
+        }
+
+        child_module_path += wildcard_str.data();
+ 
+        wildcard_names[child_module].push_back(wildcard_str.data());
+      } else {
+        child_module_path += child_instance_name;
+      }
+      
+      child_module_path = format_dir_path(child_module_path);
+
+      /* If this is NOT the MUX module we want, we go recursively */
+      if (mux_module != child_module) {
+        rec_print_pnr_sdc_disable_routing_multiplexer_outputs(fp, flatten_names,
+                                                              module_manager, 
+                                                              child_module, 
+                                                              mux_module,
+                                                              child_module_path);
+        continue;
+      }
+
+      /* Validate file stream */
+      valid_file_stream(fp);
+
+      /* Reach here, this is the MUX module we want, disable the outputs */
+      for (const BasicPort& output_port : module_manager.module_ports_by_type(mux_module, ModuleManager::MODULE_OUTPUT_PORT)) {
+        fp << "set_disable_timing ";
+        fp << child_module_path << output_port.get_name();
+        fp << std::endl;
+      }
+    }
+  }
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_sdc/sdc_mux_utils.h b/openfpga/src/fpga_sdc/sdc_mux_utils.h
new file mode 100644
index 000000000..70089aa93
--- /dev/null
+++ b/openfpga/src/fpga_sdc/sdc_mux_utils.h
@@ -0,0 +1,28 @@
+#ifndef SDC_MUX_UTILS_H
+#define SDC_MUX_UTILS_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <fstream>
+#include <string>
+#include "module_manager.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void rec_print_pnr_sdc_disable_routing_multiplexer_outputs(std::fstream& fp, 
+                                                           const bool& flatten_names,
+                                                           const ModuleManager& module_manager, 
+                                                           const ModuleId& parent_module,
+                                                           const ModuleId& mux_module,
+                                                           const std::string& parent_module_path);
+
+
+} /* end namespace openfpga */
+
+#endif

From 2fbf9c2cfc0c053f8c484470c1a4f265036981a4 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 4 May 2020 12:28:47 -0600
Subject: [PATCH 504/645] change to a higher simulation clock speed to
 accelerate CI verification. Later, we should place simulation information in
 another XML so that we can reuse that easily

---
 openfpga_flow/openfpga_arch/k4_N4_40nm_openfpga.xml         | 4 ++--
 openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml        | 4 ++--
 .../k6_N10_intermediate_buffer_40nm_openfpga.xml            | 4 ++--
 openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml   | 4 ++--
 .../openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml | 6 +++---
 .../k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml        | 6 +++---
 .../k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml    | 6 +++---
 .../k6_frac_N10_adder_column_chain_40nm_openfpga.xml        | 6 +++---
 .../k6_frac_N10_adder_register_chain_40nm_openfpga.xml      | 6 +++---
 .../k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml | 6 +++---
 ..._N10_adder_register_scan_chain_depop50_40nm_openfpga.xml | 6 +++---
 ...der_register_scan_chain_depop50_spypad_40nm_openfpga.xml | 6 +++---
 .../openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml  | 6 +++---
 .../k6_frac_N10_local_encoder_40nm_openfpga.xml             | 6 +++---
 .../openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml       | 6 +++---
 .../openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml | 6 +++---
 .../openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml    | 6 +++---
 17 files changed, 47 insertions(+), 47 deletions(-)

diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_openfpga.xml
index 1d48387ed..298e0c0c0 100644
--- a/openfpga_flow/openfpga_arch/k4_N4_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_openfpga.xml
@@ -195,8 +195,8 @@
 </openfpga_architecture>
 <openfpga_simulation_setting>
   <clock_setting>
-    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
-    <programming frequency="10e6"/>
+    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
+    <programming frequency="100e6"/>
   </clock_setting>
   <simulator_option>
     <operating_condition temperature="25"/>
diff --git a/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml
index c3385e96c..e6e53d9f6 100644
--- a/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml
@@ -195,8 +195,8 @@
 </openfpga_architecture>
 <openfpga_simulation_setting>
   <clock_setting>
-    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
-    <programming frequency="10e6"/>
+    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
+    <programming frequency="100e6"/>
   </clock_setting>
   <simulator_option>
     <operating_condition temperature="25"/>
diff --git a/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml
index ef1c60a80..b211bd040 100644
--- a/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml
@@ -196,8 +196,8 @@
 </openfpga_architecture>
 <openfpga_simulation_setting>
   <clock_setting>
-    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
-    <programming frequency="10e6"/>
+    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
+    <programming frequency="100e6"/>
   </clock_setting>
   <simulator_option>
     <operating_condition temperature="25"/>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
index 51e250a8a..9b20ab2a2 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
@@ -227,8 +227,8 @@
 <openfpga_simulation_setting>
   <clock_setting>
     <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
-    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
-    <programming frequency="10e6"/>
+    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
+    <programming frequency="100e6"/>
   </clock_setting>
   <simulator_option>
     <operating_condition temperature="25"/>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
index ae08c8250..10051a9ca 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
@@ -251,9 +251,9 @@
 </openfpga_architecture>
 <openfpga_simulation_setting>
   <clock_setting>
-    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
-    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
-    <programming frequency="10e6"/>
+    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
+    <!--operating frequency="200e6" num_cycles="auto" slack="0.2"/-->
+    <programming frequency="100e6"/>
   </clock_setting>
   <simulator_option>
     <operating_condition temperature="25"/>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
index eaacadd17..40a451b55 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
@@ -268,9 +268,9 @@
 </openfpga_architecture>
 <openfpga_simulation_setting>
   <clock_setting>
-    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
-    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
-    <programming frequency="10e6"/>
+    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
+    <!--operating frequency="200e6" num_cycles="auto" slack="0.2"/-->
+    <programming frequency="100e6"/>
   </clock_setting>
   <simulator_option>
     <operating_condition temperature="25"/>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
index 441f10ee4..9e608ead9 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
@@ -280,9 +280,9 @@
 </openfpga_architecture>
 <openfpga_simulation_setting>
   <clock_setting>
-    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
-    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
-    <programming frequency="10e6"/>
+    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
+    <!--operating frequency="200e6" num_cycles="auto" slack="0.2"/-->
+    <programming frequency="100e6"/>
   </clock_setting>
   <simulator_option>
     <operating_condition temperature="25"/>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml
index 65117d199..79b82375f 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml
@@ -251,9 +251,9 @@
 </openfpga_architecture>
 <openfpga_simulation_setting>
   <clock_setting>
-    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
-    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
-    <programming frequency="10e6"/>
+    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
+    <!--operating frequency="200e6" num_cycles="auto" slack="0.2"/-->
+    <programming frequency="100e6"/>
   </clock_setting>
   <simulator_option>
     <operating_condition temperature="25"/>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml
index 779880dea..33cfa9e61 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml
@@ -254,9 +254,9 @@
 </openfpga_architecture>
 <openfpga_simulation_setting>
   <clock_setting>
-    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
-    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
-    <programming frequency="10e6"/>
+    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
+    <!--operating frequency="200e6" num_cycles="auto" slack="0.2"/-->
+    <programming frequency="100e6"/>
   </clock_setting>
   <simulator_option>
     <operating_condition temperature="25"/>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml
index e6f6bdb6c..460c8743e 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml
@@ -260,9 +260,9 @@
 </openfpga_architecture>
 <openfpga_simulation_setting>
   <clock_setting>
-    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
-    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
-    <programming frequency="10e6"/>
+    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
+    <!--operating frequency="200e6" num_cycles="auto" slack="0.2"/-->
+    <programming frequency="100e6"/>
   </clock_setting>
   <simulator_option>
     <operating_condition temperature="25"/>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml
index 8d2aadaeb..4bb4a24a2 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml
@@ -255,9 +255,9 @@
 </openfpga_architecture>
 <openfpga_simulation_setting>
   <clock_setting>
-    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
-    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
-    <programming frequency="10e6"/>
+    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
+    <!--operating frequency="200e6" num_cycles="auto" slack="0.2"/-->
+    <programming frequency="100e6"/>
   </clock_setting>
   <simulator_option>
     <operating_condition temperature="25"/>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml
index 4939b2dc0..e1dde16b6 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml
@@ -339,9 +339,9 @@
 </openfpga_architecture>
 <openfpga_simulation_setting>
   <clock_setting>
-    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
-    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
-    <programming frequency="10e6"/>
+    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
+    <!--operating frequency="200e6" num_cycles="auto" slack="0.2"/-->
+    <programming frequency="100e6"/>
   </clock_setting>
   <simulator_option>
     <operating_condition temperature="25"/>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml
index e305bbc08..ebad2d203 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml
@@ -226,9 +226,9 @@
 </openfpga_architecture>
 <openfpga_simulation_setting>
   <clock_setting>
-    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
-    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
-    <programming frequency="10e6"/>
+    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
+    <!--operating frequency="200e6" num_cycles="auto" slack="0.2"/-->
+    <programming frequency="100e6"/>
   </clock_setting>
   <simulator_option>
     <operating_condition temperature="25"/>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml
index 201a4be58..b32deb8a9 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml
@@ -226,9 +226,9 @@
 </openfpga_architecture>
 <openfpga_simulation_setting>
   <clock_setting>
-    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
-    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
-    <programming frequency="10e6"/>
+    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
+    <!--operating frequency="200e6" num_cycles="auto" slack="0.2"/-->
+    <programming frequency="100e6"/>
   </clock_setting>
   <simulator_option>
     <operating_condition temperature="25"/>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml
index 159214507..c980065bb 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml
@@ -230,9 +230,9 @@
 </openfpga_architecture>
 <openfpga_simulation_setting>
   <clock_setting>
-    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
-    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
-    <programming frequency="10e6"/>
+    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
+    <!--operating frequency="200e6" num_cycles="auto" slack="0.2"/-->
+    <programming frequency="100e6"/>
   </clock_setting>
   <simulator_option>
     <operating_condition temperature="25"/>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml
index 660e9f003..2b42cdced 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml
@@ -218,9 +218,9 @@
 </openfpga_architecture>
 <openfpga_simulation_setting>
   <clock_setting>
-    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
-    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
-    <programming frequency="10e6"/>
+    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
+    <!--operating frequency="200e6" num_cycles="auto" slack="0.2"/-->
+    <programming frequency="100e6"/>
   </clock_setting>
   <simulator_option>
     <operating_condition temperature="25"/>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml
index d04318510..c26c30f31 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml
@@ -217,9 +217,9 @@
 </openfpga_architecture>
 <openfpga_simulation_setting>
   <clock_setting>
-    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
-    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
-    <programming frequency="10e6"/>
+    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
+    <!--operating frequency="200e6" num_cycles="auto" slack="0.2"/-->
+    <programming frequency="100e6"/>
   </clock_setting>
   <simulator_option>
     <operating_condition temperature="25"/>

From 4083fae41ac24d03d11c76dab940e95b90c8bb05 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 4 May 2020 12:34:54 -0600
Subject: [PATCH 505/645] add new test cases about user-defined simulation
 settings

---
 .../k4_N4_40nm_fixed_sim_openfpga.xml         | 228 ++++++++++++++++++
 .../config/task.conf                          |  34 +++
 2 files changed, 262 insertions(+)
 create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml
 create mode 100644 openfpga_flow/tasks/openfpga_shell/fixed_simulation_settings/config/task.conf

diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml
new file mode 100644
index 000000000..677061785
--- /dev/null
+++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml
@@ -0,0 +1,228 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="4"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="16"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="Qb" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+      <port type="input" prefix="outpad" size="1"/>
+      <port type="output" prefix="inpad" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="static_dff"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>
+<openfpga_simulation_setting>
+  <clock_setting>
+    <operating frequency="500e6" num_cycles="10" slack="0.2"/>
+    <programming frequency="300e6"/>
+  </clock_setting>
+  <simulator_option>
+    <operating_condition temperature="25"/>
+    <output_log verbose="false" captab="false"/>
+    <accuracy type="abs" value="1e-13"/>
+    <runtime fast_simulation="true"/>
+  </simulator_option>
+  <monte_carlo num_simulation_points="2"/>
+  <measurement_setting>
+    <slew>
+      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
+      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
+    </slew>
+    <delay>
+      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
+      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
+    </delay>
+  </measurement_setting>
+  <stimulus>
+    <clock>
+      <rise slew_type="abs" slew_time="20e-12" />
+      <fall slew_type="abs" slew_time="20e-12" />
+    </clock>
+    <input>
+      <rise slew_type="abs" slew_time="25e-12" />
+      <fall slew_type="abs" slew_time="25e-12" />
+    </input>
+  </stimulus>
+</openfpga_simulation_setting>
diff --git a/openfpga_flow/tasks/openfpga_shell/fixed_simulation_settings/config/task.conf b/openfpga_flow/tasks/openfpga_shell/fixed_simulation_settings/config/task.conf
new file mode 100644
index 000000000..4875931e3
--- /dev/null
+++ b/openfpga_flow/tasks/openfpga_shell/fixed_simulation_settings/config/task.conf
@@ -0,0 +1,34 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+#vpr_fpga_verilog_formal_verification_top_netlist=

From 47f040822fee04dcc4e2d93639cac53215660014 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 4 May 2020 12:36:06 -0600
Subject: [PATCH 506/645] deploy the tests to CI

---
 .travis/script.sh | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/.travis/script.sh b/.travis/script.sh
index 19da16b8b..675ab4996 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -51,6 +51,9 @@ echo -e "Testing OpenFPGA Shell";
 echo -e "Testing configuration chain of a K4N4 FPGA";
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/configuration_chain --debug --show_thread_logs
 
+echo -e "Testing user-defined simulation settings: clock frequency and number of cycles";
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/fixed_simulation_settings --debug --show_thread_logs
+
 echo -e "Testing Verilog generation for LUTs: a single mode LUT6 FPGA using micro benchmarks";
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/lut_design/single_mode --debug --show_thread_logs
 

From 8726c618eb73cefb41bad3743ce1119ccf4a2115 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 5 May 2020 12:31:11 -0600
Subject: [PATCH 507/645] add time unit support on SDC generator. Now users can
 define time_unit thru cmd-line options

---
 .../libopenfpgautil/src/openfpga_scale.cpp    | 183 ++++++++++++++++++
 .../libopenfpgautil/src/openfpga_scale.h      |  29 +++
 openfpga/src/base/openfpga_sdc.cpp            |  12 ++
 openfpga/src/base/openfpga_sdc_command.cpp    |   8 +
 openfpga/src/fpga_sdc/analysis_sdc_option.cpp |   9 +
 openfpga/src/fpga_sdc/analysis_sdc_option.h   |   3 +
 openfpga/src/fpga_sdc/analysis_sdc_writer.cpp |  11 +-
 openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp |  37 +++-
 openfpga/src/fpga_sdc/pnr_sdc_grid_writer.h   |   1 +
 openfpga/src/fpga_sdc/pnr_sdc_option.cpp      |   9 +
 openfpga/src/fpga_sdc/pnr_sdc_option.h        |   3 +
 .../src/fpga_sdc/pnr_sdc_routing_writer.cpp   |  41 +++-
 .../src/fpga_sdc/pnr_sdc_routing_writer.h     |   4 +
 openfpga/src/fpga_sdc/pnr_sdc_writer.cpp      |   5 +
 openfpga/src/fpga_sdc/sdc_writer_utils.cpp    |  15 ++
 openfpga/src/fpga_sdc/sdc_writer_utils.h      |   3 +
 16 files changed, 353 insertions(+), 20 deletions(-)
 create mode 100644 libopenfpga/libopenfpgautil/src/openfpga_scale.cpp
 create mode 100644 libopenfpga/libopenfpgautil/src/openfpga_scale.h

diff --git a/libopenfpga/libopenfpgautil/src/openfpga_scale.cpp b/libopenfpga/libopenfpgautil/src/openfpga_scale.cpp
new file mode 100644
index 000000000..9baa753d1
--- /dev/null
+++ b/libopenfpga/libopenfpgautil/src/openfpga_scale.cpp
@@ -0,0 +1,183 @@
+/********************************************************************
+ * This file includes functions that convert time/resistance/capacitance
+ * units to string or vice versa
+ *******************************************************************/
+#include <cmath>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_scale.h" 
+
+namespace openfpga {
+
+/* A small ratio for float number comparison 
+ * If the float number B is in the range of the referance A +/- epsilon 
+ * we regard A == B
+ *   A - A * EPSILON <= B <= A + A * EPSILON 
+ */
+#define EPSILON_RATIO 1e-3
+
+bool same_float_number(const float& a,
+                       const float& b,
+                       const float& epsilon) {
+  /* Always use a positive epsilon */
+  if ( (a - a * std::abs(epsilon) <= b) 
+    && (b <= a + a * std::abs(epsilon)) ) {
+    return true;
+  }
+ 
+  return false;
+}
+
+/********************************************************************
+ * Convert numeric unit to string:
+ *   - 1e12  -> T
+ *   - 1e9   -> B
+ *   - 1e6   -> M
+ *   - 1e3   -> k
+ *   - 1.    ->  
+ *   - 1e-3  -> m
+ *   - 1e-6  -> u 
+ *   - 1e-9  -> n
+ *   - 1e-12 -> p
+ *   - 1e-15 -> f 
+ *   - 1e-18 -> a 
+ *******************************************************************/
+std::string unit_to_string(const float& unit) {
+  if (true == same_float_number(unit, 1., EPSILON_RATIO)) {
+    return std::string();
+  /* Larger than 1 unit */
+  } else if (true == same_float_number(unit, 1e3, EPSILON_RATIO)) {
+    return std::string("k");
+  } else if (true == same_float_number(unit, 1e6, EPSILON_RATIO)) {
+    return std::string("M");
+  } else if (true == same_float_number(unit, 1e9, EPSILON_RATIO)) {
+    return std::string("B");
+  } else if (true == same_float_number(unit, 1e12, EPSILON_RATIO)) {
+    return std::string("T");
+  /* Less than 1 unit */
+  } else if (true == same_float_number(unit, 1e-3, EPSILON_RATIO)) {
+    return std::string("m");
+  } else if (true == same_float_number(unit, 1e-6, EPSILON_RATIO)) {
+    return std::string("u");
+  } else if (true == same_float_number(unit, 1e-9, EPSILON_RATIO)) {
+    return std::string("n");
+  } else if (true == same_float_number(unit, 1e-12, EPSILON_RATIO)) {
+    return std::string("p");
+  } else if (true == same_float_number(unit, 1e-15, EPSILON_RATIO)) {
+    return std::string("f");
+  } else if (true == same_float_number(unit, 1e-18, EPSILON_RATIO)) {
+    return std::string("a");
+  }
+
+  /* Invalid unit report error */
+  VTR_LOGF_ERROR(__FILE__, __LINE__,
+                 "Invalid unit %g!\nAcceptable units are [1e12|1e9|1e6|1e3|1|1e-3|1e-6|1e-9|1e-12|1e-15|1e-18]\n",
+                 unit); 
+  exit(1);
+}
+
+/********************************************************************
+ * Convert numeric time unit to string
+ * e.g. 1e-12 -> ps
+ *******************************************************************/
+std::string time_unit_to_string(const float& unit) {
+  /* For larger than 1 unit, we do not accept */
+  if (1e6 < unit) {
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid time unit %g!\nAcceptable units are [1e6|1e3|1|1e-3|1e-6|1e-9|1e-12|1e-15|1e-18]\n",
+                   unit); 
+    exit(1);
+  }
+
+  return unit_to_string(unit) + std::string("s");
+}
+
+/********************************************************************
+ * Convert string unit to numeric:
+ *   - T  -> 1e12
+ *   - B  -> 1e9 
+ *   - M  -> 1e6
+ *   - k  -> 1e3
+ *   - "" -> 1.  
+ *   - m  -> 1e-3
+ *   - u  -> 1e-6 
+ *   - n  -> 1e-9
+ *   - p  -> 1e-12
+ *   - f  -> 1e-15
+ *   - a  -> 1e-18
+ *******************************************************************/
+float string_to_unit(const std::string& scale) {
+  if (true == scale.empty()) {
+    return 1.;
+  /* Larger than 1 unit */
+  } else if (std::string("T") == scale) {
+    return 1e12;
+  } else if (std::string("B") == scale) {
+    return 1e9;
+  } else if (std::string("M") == scale) {
+    return 1e6;
+  } else if (std::string("k") == scale) {
+    return 1e3;
+  /* Less than 1 unit */
+  } else if (std::string("m") == scale) {
+    return 1e-3;
+  } else if (std::string("u") == scale) {
+    return 1e-6;
+  } else if (std::string("n") == scale) {
+    return 1e-9;
+  } else if (std::string("p") == scale) {
+    return 1e-12;
+  } else if (std::string("f") == scale) {
+    return 1e-15;
+  } else if (std::string("a") == scale) {
+    return 1e-18;
+  }
+
+  /* Invalid unit report error */
+  VTR_LOGF_ERROR(__FILE__, __LINE__,
+                 "Invalid unit %s!\nAcceptable units are [a|f|p|n|u|k|M|B|T] or empty\n",
+                 scale); 
+  exit(1);
+}
+
+/********************************************************************
+ * Convert string time unit to numeric
+ * e.g. ps -> 1e-12
+ *******************************************************************/
+float string_to_time_unit(const std::string& scale) {
+  if ( (1 != scale.length())
+    && (2 != scale.length()) ) {
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Time unit (='%s') must contain only one or two characters!\n",
+                   scale);
+  } 
+  /* The last character must be 's' */
+  if ('s' != scale.back()) {
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Time unit (='%s') must end with 's'!\n",
+                   scale);
+  }
+
+  float unit = 1.;
+  VTR_ASSERT ( (1 == scale.length())
+            || (2 == scale.length()) );
+  if (2 == scale.length()) {
+    unit = string_to_unit(scale.substr(0, 1));
+  }
+
+  /* For larger than 1 unit, we do not accept */
+  if (1e6 < unit) {
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid time unit %g!\nAcceptable units are [1e6|1e3|1|1e-3|1e-6|1e-9|1e-12|1e-15|1e-18]\n",
+                   unit); 
+    exit(1);
+  }
+
+  return unit;
+}
+
+} /* namespace openfpga ends */
diff --git a/libopenfpga/libopenfpgautil/src/openfpga_scale.h b/libopenfpga/libopenfpgautil/src/openfpga_scale.h
new file mode 100644
index 000000000..197923548
--- /dev/null
+++ b/libopenfpga/libopenfpgautil/src/openfpga_scale.h
@@ -0,0 +1,29 @@
+#ifndef OPENFPGA_SCALE_H
+#define OPENFPGA_SCALE_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <string>
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+/* namespace openfpga begins */
+namespace openfpga {
+
+bool same_float_number(const float& a,
+                       const float& b,
+                       const float& epsilon);
+
+std::string unit_to_string(const float& unit);
+
+std::string time_unit_to_string(const float& unit);
+
+float string_to_unit(const std::string& scale);
+
+float string_to_time_unit(const std::string& scale); 
+
+} /* namespace openfpga ends */
+
+#endif
diff --git a/openfpga/src/base/openfpga_sdc.cpp b/openfpga/src/base/openfpga_sdc.cpp
index 9fa360cff..d90376839 100644
--- a/openfpga/src/base/openfpga_sdc.cpp
+++ b/openfpga/src/base/openfpga_sdc.cpp
@@ -9,6 +9,7 @@
 #include "command_exit_codes.h"
 
 /* Headers from openfpgautil library */
+#include "openfpga_scale.h"
 #include "openfpga_digest.h"
 
 #include "circuit_library_utils.h"
@@ -31,6 +32,7 @@ int write_pnr_sdc(OpenfpgaContext& openfpga_ctx,
   CommandOptionId opt_output_dir = cmd.option("file");
   CommandOptionId opt_flatten_names = cmd.option("flatten_names");
   CommandOptionId opt_hierarchical = cmd.option("hierarchical");
+  CommandOptionId opt_time_unit = cmd.option("time_unit");
   CommandOptionId opt_constrain_global_port = cmd.option("constrain_global_port");
   CommandOptionId opt_constrain_non_clock_global_port = cmd.option("constrain_non_clock_global_port");
   CommandOptionId opt_constrain_grid = cmd.option("constrain_grid");
@@ -53,6 +55,11 @@ int write_pnr_sdc(OpenfpgaContext& openfpga_ctx,
 
   options.set_flatten_names(cmd_context.option_enable(cmd, opt_flatten_names));
   options.set_hierarchical(cmd_context.option_enable(cmd, opt_hierarchical));
+  
+  if (true == cmd_context.option_enable(cmd, opt_time_unit)) {
+    options.set_time_unit(string_to_time_unit(cmd_context.option_value(cmd, opt_time_unit)));
+  }
+
   options.set_constrain_global_port(cmd_context.option_enable(cmd, opt_constrain_global_port));
   options.set_constrain_non_clock_global_port(cmd_context.option_enable(cmd, opt_constrain_non_clock_global_port));
   options.set_constrain_grid(cmd_context.option_enable(cmd, opt_constrain_grid));
@@ -100,6 +107,7 @@ int write_analysis_sdc(OpenfpgaContext& openfpga_ctx,
 
   CommandOptionId opt_output_dir = cmd.option("file");
   CommandOptionId opt_flatten_names = cmd.option("flatten_names");
+  CommandOptionId opt_time_unit = cmd.option("time_unit");
 
   /* This is an intermediate data structure which is designed to modularize the FPGA-SDC
    * Keep it independent from any other outside data structures
@@ -113,6 +121,10 @@ int write_analysis_sdc(OpenfpgaContext& openfpga_ctx,
   options.set_generate_sdc_analysis(true);
   options.set_flatten_names(cmd_context.option_enable(cmd, opt_flatten_names));
 
+  if (true == cmd_context.option_enable(cmd, opt_time_unit)) {
+    options.set_time_unit(string_to_time_unit(cmd_context.option_value(cmd, opt_time_unit)));
+  }
+
   /* Collect global ports from the circuit library:
    * TODO: should we place this in the OpenFPGA context?
    */
diff --git a/openfpga/src/base/openfpga_sdc_command.cpp b/openfpga/src/base/openfpga_sdc_command.cpp
index 479cb8de9..bdf123e8b 100644
--- a/openfpga/src/base/openfpga_sdc_command.cpp
+++ b/openfpga/src/base/openfpga_sdc_command.cpp
@@ -32,6 +32,10 @@ ShellCommandId add_openfpga_write_pnr_sdc_command(openfpga::Shell<OpenfpgaContex
   /* Add an option '--hierarchical' */
   shell_cmd.add_option("hierarchical", false, "Output SDC files hierachically (without full path in hierarchy)");
 
+  /* Add an option '--time_unit' */
+  CommandOptionId time_unit_opt = shell_cmd.add_option("time_unit", false, "Specify the time unit in SDC files. Acceptable is [a|f|p|n|u|m|kM]s");
+  shell_cmd.set_option_require_value(time_unit_opt, openfpga::OPT_STRING);
+
   /* Add an option '--constrain_global_port' */
   shell_cmd.add_option("constrain_global_port", false, "Constrain all the global ports of FPGA fabric");
 
@@ -95,6 +99,10 @@ ShellCommandId add_openfpga_write_analysis_sdc_command(openfpga::Shell<OpenfpgaC
   /* Add an option '--flatten_name' */
   shell_cmd.add_option("flatten_names", false, "Use flatten names (no wildcards) in SDC files");
 
+  /* Add an option '--time_unit' */
+  CommandOptionId time_unit_opt = shell_cmd.add_option("time_unit", false, "Specify the time unit in SDC files. Acceptable is [a|f|p|n|u|m|kM]s");
+  shell_cmd.set_option_require_value(time_unit_opt, openfpga::OPT_STRING);
+
   /* Add command 'write_fabric_verilog' to the Shell */
   ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "generate SDC files for timing analysis a PnRed FPGA fabric mapped by a benchmark");
   shell.set_command_class(shell_cmd_id, cmd_class_id);
diff --git a/openfpga/src/fpga_sdc/analysis_sdc_option.cpp b/openfpga/src/fpga_sdc/analysis_sdc_option.cpp
index 80d6d0084..b6c55e864 100644
--- a/openfpga/src/fpga_sdc/analysis_sdc_option.cpp
+++ b/openfpga/src/fpga_sdc/analysis_sdc_option.cpp
@@ -12,6 +12,7 @@ namespace openfpga {
 AnalysisSdcOption::AnalysisSdcOption(const std::string& sdc_dir) {
   sdc_dir_ = sdc_dir;
   flatten_names_ = false;
+  time_unit_ = 1.;
   generate_sdc_analysis_ = false;
 }
 
@@ -26,6 +27,10 @@ bool AnalysisSdcOption::flatten_names() const {
   return flatten_names_;
 }
 
+float AnalysisSdcOption::time_unit() const {
+  return time_unit_;
+}
+
 bool AnalysisSdcOption::generate_sdc_analysis() const {
   return generate_sdc_analysis_;
 }
@@ -41,6 +46,10 @@ void AnalysisSdcOption::set_flatten_names(const bool& flatten_names) {
   flatten_names_ = flatten_names;
 }
 
+void AnalysisSdcOption::set_time_unit(const float& time_unit) {
+  time_unit_ = time_unit;
+}
+
 void AnalysisSdcOption::set_generate_sdc_analysis(const bool& generate_sdc_analysis) {
   generate_sdc_analysis_ = generate_sdc_analysis;
 }
diff --git a/openfpga/src/fpga_sdc/analysis_sdc_option.h b/openfpga/src/fpga_sdc/analysis_sdc_option.h
index 8154de9c9..17ff10f4f 100644
--- a/openfpga/src/fpga_sdc/analysis_sdc_option.h
+++ b/openfpga/src/fpga_sdc/analysis_sdc_option.h
@@ -17,15 +17,18 @@ class AnalysisSdcOption {
   public: /* Public accessors */
     std::string sdc_dir() const;
     bool flatten_names() const;
+    float time_unit() const;
     bool generate_sdc_analysis() const;
   public: /* Public mutators */
     void set_sdc_dir(const std::string& sdc_dir);
     void set_flatten_names(const bool& flatten_names);
+    void set_time_unit(const float& time_unit);
     void set_generate_sdc_analysis(const bool& generate_sdc_analysis);
   private: /* Internal data */
     std::string sdc_dir_;
     bool generate_sdc_analysis_; 
     bool flatten_names_; 
+    float time_unit_;
 };
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp b/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp
index 8efdb4e9e..a4730cae6 100644
--- a/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp
+++ b/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp
@@ -37,6 +37,7 @@ namespace openfpga {
  *******************************************************************/
 static 
 void print_analysis_sdc_io_delays(std::fstream& fp,
+                                  const float& time_unit,
                                   const AtomContext& atom_ctx,
                                   const PlacementContext& place_ctx,
                                   const VprNetlistAnnotation& netlist_annotation,
@@ -74,8 +75,8 @@ void print_analysis_sdc_io_delays(std::fstream& fp,
     /* Reach here, it means a clock port and we need print constraints */
     fp << "create_clock ";
     fp << generate_sdc_port(operating_clock_port);
-    fp << " -period " << std::setprecision(10) << critical_path_delay;
-    fp << " -waveform {0 " << std::setprecision(10) << critical_path_delay / 2 << "}";
+    fp << " -period " << std::setprecision(10) << critical_path_delay / time_unit;
+    fp << " -waveform {0 " << std::setprecision(10) << critical_path_delay / (2 * time_unit) << "}";
     fp << std::endl;
 
     /* Add an empty line as a splitter */
@@ -130,11 +131,11 @@ void print_analysis_sdc_io_delays(std::fstream& fp,
        */
       if (AtomBlockType::INPAD == atom_ctx.nlist.block_type(atom_blk)) {
         print_sdc_set_port_input_delay(fp, module_mapped_io_port,
-                                       operating_clock_ports[0], critical_path_delay);
+                                       operating_clock_ports[0], critical_path_delay / time_unit);
       } else {
         VTR_ASSERT(AtomBlockType::OUTPAD == atom_ctx.nlist.block_type(atom_blk));
         print_sdc_set_port_output_delay(fp, module_mapped_io_port,
-                                        operating_clock_ports[0], critical_path_delay);
+                                        operating_clock_ports[0], critical_path_delay / time_unit);
       }
 
       /* Mark this I/O has been used/wired */
@@ -251,7 +252,7 @@ void print_analysis_sdc(const AnalysisSdcOption& option,
   VTR_ASSERT(true == openfpga_ctx.module_graph().valid_module_id(top_module));
 
   /* Create clock and set I/O ports with input/output delays */
-  print_analysis_sdc_io_delays(fp,
+  print_analysis_sdc_io_delays(fp, option.time_unit(),
                                vpr_ctx.atom(), vpr_ctx.placement(),
                                openfpga_ctx.vpr_netlist_annotation(), openfpga_ctx.io_location_map(),
                                openfpga_ctx.module_graph(), top_module, 
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp
index 4f748f9ad..f0708cc61 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp
+++ b/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp
@@ -16,6 +16,7 @@
 #include "vtr_time.h"
 
 /* Headers from openfpgautil library */
+#include "openfpga_scale.h"
 #include "openfpga_port.h"
 #include "openfpga_digest.h"
 #include "openfpga_side_manager.h"
@@ -43,6 +44,7 @@ namespace openfpga {
  *******************************************************************/
 static 
 void print_pnr_sdc_constrain_pb_pin_interc_timing(std::fstream& fp,
+                                                  const float& time_unit,
                                                   const ModuleManager& module_manager,
                                                   const ModuleId& parent_module,
                                                   t_pb_graph_pin* des_pb_graph_pin,
@@ -151,7 +153,7 @@ void print_pnr_sdc_constrain_pb_pin_interc_timing(std::fstream& fp,
                                       generate_sdc_port(src_port),
                                       des_instance_name, 
                                       generate_sdc_port(des_port),
-                                      des_pb_graph_pin->input_edges[iedge]->delay_max);
+                                      des_pb_graph_pin->input_edges[iedge]->delay_max / time_unit);
   }
 }
 
@@ -161,6 +163,7 @@ void print_pnr_sdc_constrain_pb_pin_interc_timing(std::fstream& fp,
  *******************************************************************/
 static 
 void print_pnr_sdc_constrain_pb_interc_timing(std::fstream& fp,
+                                              const float& time_unit,
                                               const ModuleManager& module_manager,
                                               const ModuleId& parent_module,
                                               t_pb_graph_node* des_pb_graph_node,
@@ -176,7 +179,8 @@ void print_pnr_sdc_constrain_pb_interc_timing(std::fstream& fp,
       for (int ipin = 0; ipin < des_pb_graph_node->num_input_pins[iport]; ++ipin) {
         /* If this is a idle block, we set 0 to the selected edge*/
         /* Get the selected edge of current pin*/
-        print_pnr_sdc_constrain_pb_pin_interc_timing(fp, 
+        print_pnr_sdc_constrain_pb_pin_interc_timing(fp,
+                                                     time_unit, 
                                                      module_manager, parent_module, 
                                                      &(des_pb_graph_node->input_pins[iport][ipin]),
                                                      physical_mode,
@@ -189,6 +193,7 @@ void print_pnr_sdc_constrain_pb_interc_timing(std::fstream& fp,
     for (int iport = 0; iport < des_pb_graph_node->num_output_ports; ++iport) {
       for (int ipin = 0; ipin < des_pb_graph_node->num_output_pins[iport]; ++ipin) {
         print_pnr_sdc_constrain_pb_pin_interc_timing(fp,
+                                                     time_unit, 
                                                      module_manager, parent_module, 
                                                      &(des_pb_graph_node->output_pins[iport][ipin]),
                                                      physical_mode,
@@ -217,6 +222,7 @@ void print_pnr_sdc_constrain_pb_interc_timing(std::fstream& fp,
  *******************************************************************/
 static 
 void print_pnr_sdc_constrain_pb_graph_node_timing(const std::string& sdc_dir,
+                                                  const float& time_unit,
                                                   const ModuleManager& module_manager,
                                                   t_pb_graph_node* parent_pb_graph_node,
                                                   t_mode* physical_mode,
@@ -242,6 +248,9 @@ void print_pnr_sdc_constrain_pb_graph_node_timing(const std::string& sdc_dir,
   /* Generate the descriptions*/
   print_sdc_file_header(fp, std::string("Timing constraints for Grid " + pb_module_name + " in PnR"));
 
+  /* Print time unit for the SDC file */
+  print_sdc_timescale(fp, time_unit_to_string(time_unit));
+
   /* We check output_pins of cur_pb_graph_node and its the input_edges
    * Built the interconnections between outputs of cur_pb_graph_node and outputs of child_pb_graph_node
    *   child_pb_graph_node.output_pins -----------------> cur_pb_graph_node.outpins
@@ -250,6 +259,7 @@ void print_pnr_sdc_constrain_pb_graph_node_timing(const std::string& sdc_dir,
    *                         input_pins,   edges,       output_pins
    */ 
   print_pnr_sdc_constrain_pb_interc_timing(fp,
+                                           time_unit,
                                            module_manager, pb_module,
                                            parent_pb_graph_node, 
                                            CIRCUIT_PB_PORT_OUTPUT,
@@ -268,6 +278,7 @@ void print_pnr_sdc_constrain_pb_graph_node_timing(const std::string& sdc_dir,
       t_pb_graph_node* child_pb_graph_node = &(parent_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb][jpb]);
       /* For each child_pb_graph_node input pins*/
       print_pnr_sdc_constrain_pb_interc_timing(fp,
+                                               time_unit,
                                                module_manager, pb_module,
                                                child_pb_graph_node, 
                                                CIRCUIT_PB_PORT_INPUT,
@@ -291,6 +302,7 @@ void print_pnr_sdc_constrain_pb_graph_node_timing(const std::string& sdc_dir,
  *******************************************************************/
 static 
 void print_pnr_sdc_constrain_primitive_pb_graph_node(const std::string& sdc_dir,
+                                                     const float& time_unit,
                                                      const ModuleManager& module_manager,
                                                      t_pb_graph_node* primitive_pb_graph_node,
                                                      const bool& constrain_zero_delay_paths) {
@@ -350,6 +362,9 @@ void print_pnr_sdc_constrain_primitive_pb_graph_node(const std::string& sdc_dir,
   /* Generate the descriptions*/
   print_sdc_file_header(fp, std::string("Timing constraints for Grid " + pb_module_name + " in PnR"));
 
+  /* Print time unit for the SDC file */
+  print_sdc_timescale(fp, time_unit_to_string(time_unit));
+
   /* We traverse the pb_graph pins where we can find pin-to-pin timing annotation
    * We walk through output pins here, build timing constraints by pair each output to input
    * Clock pins are not walked through because they will be handled by clock tree synthesis
@@ -387,7 +402,7 @@ void print_pnr_sdc_constrain_primitive_pb_graph_node(const std::string& sdc_dir,
                                              generate_sdc_port(src_port),
                                              pb_module_name, 
                                              generate_sdc_port(sink_port),
-                                             tmax);
+                                             tmax / time_unit);
          }
 
          /* Find min delay between src and sink pin */
@@ -400,7 +415,7 @@ void print_pnr_sdc_constrain_primitive_pb_graph_node(const std::string& sdc_dir,
                                              generate_sdc_port(src_port),
                                              pb_module_name, 
                                              generate_sdc_port(sink_port),
-                                             tmin);
+                                             tmin / time_unit);
         } 
       }
     }
@@ -417,6 +432,7 @@ void print_pnr_sdc_constrain_primitive_pb_graph_node(const std::string& sdc_dir,
  *******************************************************************/
 static 
 void rec_print_pnr_sdc_constrain_pb_graph_timing(const std::string& sdc_dir,
+                                                 const float& time_unit,
                                                  const ModuleManager& module_manager,
                                                  const VprDeviceAnnotation& device_annotation,
                                                  t_pb_graph_node* parent_pb_graph_node,
@@ -433,7 +449,9 @@ void rec_print_pnr_sdc_constrain_pb_graph_timing(const std::string& sdc_dir,
 
   /* Constrain the primitive node if a timing matrix is defined */
   if (true == is_primitive_pb_type(parent_pb_type)) {
-    print_pnr_sdc_constrain_primitive_pb_graph_node(sdc_dir, module_manager,
+    print_pnr_sdc_constrain_primitive_pb_graph_node(sdc_dir,
+                                                    time_unit,
+                                                    module_manager,
                                                     parent_pb_graph_node,
                                                     constrain_zero_delay_paths);
     return;
@@ -446,6 +464,7 @@ void rec_print_pnr_sdc_constrain_pb_graph_timing(const std::string& sdc_dir,
 
   /* Write a SDC file for this pb_type */
   print_pnr_sdc_constrain_pb_graph_node_timing(sdc_dir,
+                                               time_unit,
                                                module_manager,
                                                parent_pb_graph_node,
                                                physical_mode,
@@ -455,7 +474,9 @@ void rec_print_pnr_sdc_constrain_pb_graph_timing(const std::string& sdc_dir,
    * Note that we assume a full hierarchical P&R, we will only visit pb_graph_node of unique pb_type 
    */
   for (int ipb = 0; ipb < physical_mode->num_pb_type_children; ++ipb) {
-    rec_print_pnr_sdc_constrain_pb_graph_timing(sdc_dir, module_manager, 
+    rec_print_pnr_sdc_constrain_pb_graph_timing(sdc_dir,
+                                                time_unit, 
+                                                module_manager, 
                                                 device_annotation,
                                                 &(parent_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb][0]),
                                                 constrain_zero_delay_paths);
@@ -466,6 +487,7 @@ void rec_print_pnr_sdc_constrain_pb_graph_timing(const std::string& sdc_dir,
  * Top-level function to print timing constraints for pb_types
  *******************************************************************/
 void print_pnr_sdc_constrain_grid_timing(const std::string& sdc_dir,
+                                         const float& time_unit,
                                          const DeviceContext& device_ctx,
                                          const VprDeviceAnnotation& device_annotation,
                                          const ModuleManager& module_manager,
@@ -485,7 +507,8 @@ void print_pnr_sdc_constrain_grid_timing(const std::string& sdc_dir,
         continue;
       }
       /* Special for I/O block, generate one module for each border side */
-      rec_print_pnr_sdc_constrain_pb_graph_timing(sdc_dir, module_manager, 
+      rec_print_pnr_sdc_constrain_pb_graph_timing(sdc_dir, time_unit,
+                                                  module_manager, 
                                                   device_annotation,
                                                   pb_graph_head,
                                                   constrain_zero_delay_paths);
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.h b/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.h
index 400ca1616..909caff2a 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.h
+++ b/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.h
@@ -18,6 +18,7 @@
 namespace openfpga {
 
 void print_pnr_sdc_constrain_grid_timing(const std::string& sdc_dir,
+                                         const float& time_unit,
                                          const DeviceContext& device_ctx,
                                          const VprDeviceAnnotation& device_annotation,
                                          const ModuleManager& module_manager,
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_option.cpp b/openfpga/src/fpga_sdc/pnr_sdc_option.cpp
index 3b7c417e0..f8ee429f3 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_option.cpp
+++ b/openfpga/src/fpga_sdc/pnr_sdc_option.cpp
@@ -13,6 +13,7 @@ PnrSdcOption::PnrSdcOption(const std::string& sdc_dir) {
   sdc_dir_ = sdc_dir;
   hierarchical_ = false;
   flatten_names_ = false;
+  time_unit_ = 1.;
   constrain_global_port_ = false;
   constrain_non_clock_global_port_ = false;
   constrain_grid_ = false;
@@ -39,6 +40,10 @@ bool PnrSdcOption::hierarchical() const {
   return hierarchical_;
 }
 
+float PnrSdcOption::time_unit() const {
+  return time_unit_;
+}
+
 bool PnrSdcOption::generate_sdc_pnr() const {
   return constrain_global_port_ 
       || constrain_grid_
@@ -100,6 +105,10 @@ void PnrSdcOption::set_hierarchical(const bool& hierarchical) {
   hierarchical_ = hierarchical;
 }
 
+void PnrSdcOption::set_time_unit(const float& time_unit) {
+  time_unit_ = time_unit;
+}
+
 void PnrSdcOption::set_generate_sdc_pnr(const bool& generate_sdc_pnr) {
   constrain_global_port_ = generate_sdc_pnr;
   constrain_grid_ = generate_sdc_pnr;
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_option.h b/openfpga/src/fpga_sdc/pnr_sdc_option.h
index ff52a75fd..4fe997321 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_option.h
+++ b/openfpga/src/fpga_sdc/pnr_sdc_option.h
@@ -18,6 +18,7 @@ class PnrSdcOption {
     std::string sdc_dir() const;
     bool flatten_names() const;
     bool hierarchical() const;
+    float time_unit() const;
     bool generate_sdc_pnr() const;
     bool constrain_global_port() const;
     bool constrain_non_clock_global_port() const;
@@ -32,6 +33,7 @@ class PnrSdcOption {
     void set_sdc_dir(const std::string& sdc_dir);
     void set_flatten_names(const bool& flatten_names);
     void set_hierarchical(const bool& hierarchical);
+    void set_time_unit(const float& time_unit);
     void set_generate_sdc_pnr(const bool& generate_sdc_pnr);
     void set_constrain_global_port(const bool& constrain_global_port);
     void set_constrain_non_clock_global_port(const bool& constrain_non_clock_global_port);
@@ -46,6 +48,7 @@ class PnrSdcOption {
     std::string sdc_dir_;
     bool flatten_names_;
     bool hierarchical_;
+    float time_unit_;
     bool constrain_global_port_; 
     bool constrain_non_clock_global_port_; 
     bool constrain_grid_; 
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp
index 60e756839..e530e7903 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp
+++ b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp
@@ -16,6 +16,7 @@
 #include "vtr_time.h"
 
 /* Headers from openfpgautil library */
+#include "openfpga_scale.h"
 #include "openfpga_port.h"
 #include "openfpga_side_manager.h"
 #include "openfpga_digest.h"
@@ -49,6 +50,7 @@ float find_pnr_sdc_switch_tmax(const t_rr_switch_inf& switch_inf) {
  *******************************************************************/
 static 
 void print_pnr_sdc_constrain_sb_mux_timing(std::fstream& fp,
+                                           const float& time_unit,
                                            const bool& hierarchical,
                                            const std::string& module_path,
                                            const ModuleManager& module_manager,
@@ -104,7 +106,7 @@ void print_pnr_sdc_constrain_sb_mux_timing(std::fstream& fp,
                                                generate_sdc_port(module_manager.module_port(sb_module, module_input_port)),
                                                module_path,
                                                generate_sdc_port(module_manager.module_port(sb_module, module_output_port)),
-                                               switch_delays[module_input_port]);
+                                               switch_delays[module_input_port] / time_unit);
 
     } else {
       VTR_ASSERT_SAFE(true == hierarchical);
@@ -112,7 +114,7 @@ void print_pnr_sdc_constrain_sb_mux_timing(std::fstream& fp,
                                                module_manager, 
                                                sb_module, module_input_port, 
                                                sb_module, module_output_port,
-                                               switch_delays[module_input_port]);
+                                               switch_delays[module_input_port] / time_unit);
     }
   }
 }
@@ -127,6 +129,7 @@ void print_pnr_sdc_constrain_sb_mux_timing(std::fstream& fp,
  *******************************************************************/
 static 
 void print_pnr_sdc_constrain_sb_timing(const std::string& sdc_dir,
+                                       const float& time_unit,
                                        const bool& hierarchical,
                                        const std::string& module_path,
                                        const ModuleManager& module_manager,
@@ -152,6 +155,9 @@ void print_pnr_sdc_constrain_sb_timing(const std::string& sdc_dir,
   /* Generate the descriptions*/
   print_sdc_file_header(fp, std::string("Constrain timing of Switch Block " + sb_module_name + " for PnR"));
 
+  /* Print time unit for the SDC file */
+  print_sdc_timescale(fp, time_unit_to_string(time_unit));
+
   for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
     SideManager side_manager(side);
     for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) {
@@ -166,6 +172,7 @@ void print_pnr_sdc_constrain_sb_timing(const std::string& sdc_dir,
       } 
       /* This is a MUX, constrain all the paths from an input to an output */
       print_pnr_sdc_constrain_sb_mux_timing(fp,
+                                            time_unit,
                                             hierarchical,
                                             module_path,
                                             module_manager, sb_module, 
@@ -186,6 +193,7 @@ void print_pnr_sdc_constrain_sb_timing(const std::string& sdc_dir,
  * This function is designed for flatten routing hierarchy
  *******************************************************************/
 void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_dir,
+                                                       const float& time_unit,
                                                        const bool& hierarchical,
                                                        const ModuleManager& module_manager,
                                                        const ModuleId& top_module,
@@ -223,6 +231,7 @@ void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_di
       module_path += std::string(")") + std::string("\\");
 
       print_pnr_sdc_constrain_sb_timing(sdc_dir,
+                                        time_unit,
                                         hierarchical,
                                         module_path,
                                         module_manager,
@@ -238,6 +247,7 @@ void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_di
  * This function is designed for compact routing hierarchy
  *******************************************************************/
 void print_pnr_sdc_compact_routing_constrain_sb_timing(const std::string& sdc_dir,
+                                                       const float& time_unit,
                                                        const bool& hierarchical,
                                                        const ModuleManager& module_manager,
                                                        const ModuleId& top_module,
@@ -283,6 +293,7 @@ void print_pnr_sdc_compact_routing_constrain_sb_timing(const std::string& sdc_di
     module_path += std::string(")") + std::string("\\");
 
     print_pnr_sdc_constrain_sb_timing(sdc_dir,
+                                      time_unit,
                                       hierarchical,
                                       module_path,
                                       module_manager,
@@ -298,6 +309,7 @@ void print_pnr_sdc_compact_routing_constrain_sb_timing(const std::string& sdc_di
  *******************************************************************/
 static 
 void print_pnr_sdc_constrain_cb_mux_timing(std::fstream& fp,
+                                           const float& time_unit,
                                            const bool& hierarchical,
                                            const std::string& module_path,
                                            const ModuleManager& module_manager,
@@ -373,7 +385,7 @@ void print_pnr_sdc_constrain_cb_mux_timing(std::fstream& fp,
                                                module_manager, 
                                                cb_module, module_input_port, 
                                                cb_module, module_output_port,
-                                               switch_delays[module_input_port]);
+                                               switch_delays[module_input_port] / time_unit);
     } else {
       VTR_ASSERT_SAFE(false == hierarchical);
       print_pnr_sdc_regexp_constrain_max_delay(fp,
@@ -381,7 +393,7 @@ void print_pnr_sdc_constrain_cb_mux_timing(std::fstream& fp,
                                                generate_sdc_port(module_manager.module_port(cb_module, module_input_port)),
                                                std::string(module_path),
                                                generate_sdc_port(module_manager.module_port(cb_module, module_output_port)),
-                                               switch_delays[module_input_port]);
+                                               switch_delays[module_input_port] / time_unit);
 
     }
   }
@@ -393,6 +405,7 @@ void print_pnr_sdc_constrain_cb_mux_timing(std::fstream& fp,
  *******************************************************************/
 static 
 void print_pnr_sdc_constrain_cb_timing(const std::string& sdc_dir,
+                                       const float& time_unit,
                                        const bool& hierarchical,
                                        const std::string& module_path,
                                        const ModuleManager& module_manager,
@@ -420,6 +433,9 @@ void print_pnr_sdc_constrain_cb_timing(const std::string& sdc_dir,
   /* Generate the descriptions*/
   print_sdc_file_header(fp, std::string("Constrain timing of Connection Block " + cb_module_name + " for PnR"));
 
+  /* Print time unit for the SDC file */
+  print_sdc_timescale(fp, time_unit_to_string(time_unit));
+
   /* Contrain each routing track inside the connection block */
   for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) {
     /* Create a port description for the input */
@@ -463,7 +479,7 @@ void print_pnr_sdc_constrain_cb_timing(const std::string& sdc_dir,
                                                module_manager, 
                                                cb_module, input_port_id, 
                                                cb_module, output_port_id,
-                                               routing_segment_delay);
+                                               routing_segment_delay / time_unit);
     } else {
       VTR_ASSERT_SAFE(false == hierarchical);
       print_pnr_sdc_regexp_constrain_max_delay(fp,
@@ -471,7 +487,7 @@ void print_pnr_sdc_constrain_cb_timing(const std::string& sdc_dir,
                                                generate_sdc_port(module_manager.module_port(cb_module, input_port_id)),
                                                std::string(module_path),
                                                generate_sdc_port(module_manager.module_port(cb_module, output_port_id)),
-                                               routing_segment_delay);
+                                               routing_segment_delay / time_unit);
     }
   }
 
@@ -484,6 +500,7 @@ void print_pnr_sdc_constrain_cb_timing(const std::string& sdc_dir,
     for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) {
       const RRNodeId& ipin_rr_node = rr_gsb.get_ipin_node(cb_ipin_side, inode);
       print_pnr_sdc_constrain_cb_mux_timing(fp,
+                                            time_unit,
                                             hierarchical, module_path,
                                             module_manager, cb_module, 
                                             rr_graph, rr_gsb, cb_type,
@@ -502,6 +519,7 @@ void print_pnr_sdc_constrain_cb_timing(const std::string& sdc_dir,
  *******************************************************************/
 static 
 void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_dir,
+                                                       const float& time_unit,
                                                        const bool& hierarchical,
                                                        const ModuleManager& module_manager, 
                                                        const ModuleId& top_module,
@@ -542,6 +560,7 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_di
       module_path += std::string(")") + std::string("\\");
 
       print_pnr_sdc_constrain_cb_timing(sdc_dir,
+                                        time_unit,
                                         hierarchical,
                                         module_path,
                                         module_manager,
@@ -559,6 +578,7 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_di
  * and print SDC file for each of them 
  *******************************************************************/
 void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_dir,
+                                                       const float& time_unit,
                                                        const bool& hierarchical,
                                                        const ModuleManager& module_manager, 
                                                        const ModuleId& top_module,
@@ -569,14 +589,16 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_di
   /* Start time count */
   vtr::ScopedStartFinishTimer timer("Write SDC for constrain Connection Block timing for P&R flow");
 
-  print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_dir, hierarchical,
+  print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_dir, time_unit,
+                                                    hierarchical,
                                                     module_manager, top_module,
                                                     rr_graph,
                                                     device_rr_gsb,
                                                     CHANX,
                                                     constrain_zero_delay_paths);
 
-  print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_dir, hierarchical, 
+  print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_dir, time_unit,
+                                                    hierarchical, 
                                                     module_manager, top_module,
                                                     rr_graph,
                                                     device_rr_gsb,
@@ -589,6 +611,7 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_di
  * This function is designed for compact routing hierarchy
  *******************************************************************/
 void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_dir,
+                                                       const float& time_unit,
                                                        const bool& hierarchical,
                                                        const ModuleManager& module_manager,
                                                        const ModuleId& top_module,
@@ -631,6 +654,7 @@ void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_di
     module_path += std::string(")") + std::string("\\");
 
     print_pnr_sdc_constrain_cb_timing(sdc_dir,
+                                      time_unit,
                                       hierarchical,
                                       module_path,
                                       module_manager,
@@ -670,6 +694,7 @@ void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_di
     module_path += std::string(")") + std::string("\\");
 
     print_pnr_sdc_constrain_cb_timing(sdc_dir,
+                                      time_unit,
                                       hierarchical,
                                       module_path,
                                       module_manager,
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.h b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.h
index a29a7ac56..d95c03a00 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.h
+++ b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.h
@@ -18,6 +18,7 @@
 namespace openfpga {
 
 void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_dir,
+                                                       const float& time_unit,
                                                        const bool& hierarchical,
                                                        const ModuleManager& module_manager,
                                                        const ModuleId& top_module,
@@ -26,6 +27,7 @@ void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_di
                                                        const bool& constrain_zero_delay_paths);
 
 void print_pnr_sdc_compact_routing_constrain_sb_timing(const std::string& sdc_dir,
+                                                       const float& time_unit,
                                                        const bool& hierarchical,
                                                        const ModuleManager& module_manager,
                                                        const ModuleId& top_module,
@@ -34,6 +36,7 @@ void print_pnr_sdc_compact_routing_constrain_sb_timing(const std::string& sdc_di
                                                        const bool& constrain_zero_delay_paths);
 
 void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_dir,
+                                                       const float& time_unit,
                                                        const bool& hierarchical,
                                                        const ModuleManager& module_manager, 
                                                        const ModuleId& top_module,
@@ -42,6 +45,7 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_di
                                                        const bool& constrain_zero_delay_paths);
 
 void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_dir,
+                                                       const float& time_unit,
                                                        const bool& hierarchical,
                                                        const ModuleManager& module_manager,
                                                        const ModuleId& top_module,
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
index c88e3e2ef..ae6d3a4b8 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
+++ b/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
@@ -442,6 +442,7 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options,
   if (true == sdc_options.constrain_sb()) {
     if (true == compact_routing_hierarchy) {
       print_pnr_sdc_compact_routing_constrain_sb_timing(sdc_options.sdc_dir(),
+                                                        sdc_options.time_unit(),
                                                         sdc_options.hierarchical(),
                                                         module_manager,
                                                         top_module,
@@ -451,6 +452,7 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options,
     } else {
 	  VTR_ASSERT_SAFE (false == compact_routing_hierarchy);
       print_pnr_sdc_flatten_routing_constrain_sb_timing(sdc_options.sdc_dir(),
+                                                        sdc_options.time_unit(),
                                                         sdc_options.hierarchical(),
                                                         module_manager,
                                                         top_module,
@@ -464,6 +466,7 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options,
   if (true == sdc_options.constrain_cb()) {
     if (true == compact_routing_hierarchy) {
       print_pnr_sdc_compact_routing_constrain_cb_timing(sdc_options.sdc_dir(),
+                                                        sdc_options.time_unit(),
                                                         sdc_options.hierarchical(),
                                                         module_manager,
                                                         top_module,
@@ -473,6 +476,7 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options,
     } else {
 	  VTR_ASSERT_SAFE (false == compact_routing_hierarchy);
       print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_options.sdc_dir(),
+                                                        sdc_options.time_unit(),
                                                         sdc_options.hierarchical(),
                                                         module_manager, 
                                                         top_module,
@@ -485,6 +489,7 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options,
   /* Output Timing constraints for Programmable blocks */
   if (true == sdc_options.constrain_grid()) {
     print_pnr_sdc_constrain_grid_timing(sdc_options.sdc_dir(),
+                                        sdc_options.time_unit(),
                                         device_ctx,
                                         device_annotation,
                                         module_manager,
diff --git a/openfpga/src/fpga_sdc/sdc_writer_utils.cpp b/openfpga/src/fpga_sdc/sdc_writer_utils.cpp
index 13b70fec4..0fcf450ad 100644
--- a/openfpga/src/fpga_sdc/sdc_writer_utils.cpp
+++ b/openfpga/src/fpga_sdc/sdc_writer_utils.cpp
@@ -38,6 +38,21 @@ void print_sdc_file_header(std::fstream& fp,
   fp << std::endl;
 }
 
+/********************************************************************
+ * Write a timescale definition in SDC file 
+ *******************************************************************/
+void print_sdc_timescale(std::fstream& fp,
+                         const std::string& timescale) {
+
+  valid_file_stream(fp);
+
+  fp << "#############################################" << std::endl;
+  fp << "#\tDefine time unit " << std::endl;
+  fp << "#############################################" << std::endl;
+  fp << "set_units -time " << timescale << std::endl;
+  fp << std::endl;
+}
+
 /********************************************************************
  * Write a port in SDC format
  *******************************************************************/
diff --git a/openfpga/src/fpga_sdc/sdc_writer_utils.h b/openfpga/src/fpga_sdc/sdc_writer_utils.h
index c7a7cd3a1..4b353045b 100644
--- a/openfpga/src/fpga_sdc/sdc_writer_utils.h
+++ b/openfpga/src/fpga_sdc/sdc_writer_utils.h
@@ -19,6 +19,9 @@ namespace openfpga {
 void print_sdc_file_header(std::fstream& fp,
                            const std::string& usage);
 
+void print_sdc_timescale(std::fstream& fp,
+                         const std::string& timescale);
+
 std::string generate_sdc_port(const BasicPort& port);
 
 void print_pnr_sdc_constrain_max_delay(std::fstream& fp,

From ac378febef3c582782db8e307caf091b54c44b25 Mon Sep 17 00:00:00 2001
From: Xifan Tang <tangxifan@gmail.com>
Date: Tue, 5 May 2020 12:36:01 -0600
Subject: [PATCH 508/645] update doc about time units in SDC generator

---
 docs/source/openfpga_shell/openfpga_commands.rst | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/docs/source/openfpga_shell/openfpga_commands.rst b/docs/source/openfpga_shell/openfpga_commands.rst
index d3020e9c1..987e8b981 100644
--- a/docs/source/openfpga_shell/openfpga_commands.rst
+++ b/docs/source/openfpga_shell/openfpga_commands.rst
@@ -180,6 +180,8 @@ FPGA-SDC
 
   - ``--flatten_names`` Use flatten names (no wildcards) in SDC files
 
+  - ``--time_unit`` Specify a time unit to be used in SDC files. Acceptable values are string: ``as`` | ``fs`` | ``ps`` | ``ns`` | ``us`` | ``ms`` | ``ks`` | ``Ms``. By default, we will consider second (``s``).
+
   - ``--constrain_global_port`` Constrain all the global ports of FPGA fabric.
 
   - ``--constrain_non_clock_global_port`` Constrain all the non-clock global ports as clocks ports of FPGA fabric
@@ -211,3 +213,5 @@ FPGA-SDC
   - ``--file`` or ``-f`` Specify the output directory for SDC files
   
   - ``--flatten_names`` Use flatten names (no wildcards) in SDC files
+
+  - ``--time_unit`` Specify a time unit to be used in SDC files. Acceptable values are string: ``as`` | ``fs`` | ``ps`` | ``ns`` | ``us`` | ``ms`` | ``ks`` | ``Ms``. By default, we will consider second (``s``).

From 98fbcb5410c8c8ccc9d7f60e714c770254d364c5 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 5 May 2020 12:43:49 -0600
Subject: [PATCH 509/645] add time unit test for SDC generation to CI

---
 .travis/script.sh                             |  3 +
 .../sdc_time_unit_example_script.openfpga     | 61 +++++++++++++++++++
 .../sdc_time_unit/config/task.conf            | 34 +++++++++++
 3 files changed, 98 insertions(+)
 create mode 100644 openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga
 create mode 100644 openfpga_flow/tasks/openfpga_shell/sdc_time_unit/config/task.conf

diff --git a/.travis/script.sh b/.travis/script.sh
index 675ab4996..ba4c209a1 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -120,6 +120,9 @@ python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/generate_fabric --
 echo -e "Testing Verilog testbench generation only";
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/generate_testbench --debug --show_thread_logs
 
+echo -e "Testing SDC generation with time units";
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/sdc_time_unit --debug --show_thread_logs
+
 # Verify MCNC big20 benchmark suite with ModelSim 
 # Please make sure you have ModelSim installed in the environment
 # Otherwise, it will fail
diff --git a/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga
new file mode 100644
index 000000000..1d153a4e9
--- /dev/null
+++ b/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga
@@ -0,0 +1,61 @@
+# Run VPR for the 'and' design
+#--write_rr_graph example_rr_graph.xml
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
+
+# Annotate the OpenFPGA architecture to VPR data base
+# to debug use --verbose options
+link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to clustering nets based on routing results
+pb_pin_fixup --verbose
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup
+
+# Build the module graph
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules
+build_fabric --compress_routing #--verbose
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --file fabric_indepenent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here
+write_pnr_sdc --time_unit ps --file ./SDC
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+write_analysis_sdc --time_unit ps --file ./SDC_analysis
+
+# Finish and exit OpenFPGA
+exit
+
+# Note :
+# To run verification at the end of the flow maintain source in ./SRC directory
diff --git a/openfpga_flow/tasks/openfpga_shell/sdc_time_unit/config/task.conf b/openfpga_flow/tasks/openfpga_shell/sdc_time_unit/config/task.conf
new file mode 100644
index 000000000..1aeaa036f
--- /dev/null
+++ b/openfpga_flow/tasks/openfpga_shell/sdc_time_unit/config/task.conf
@@ -0,0 +1,34 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+#end_flow_with_test=
+#vpr_fpga_verilog_formal_verification_top_netlist=

From 0985c720e92381c9456060a6eabc8d2d4aba8b7b Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 5 May 2020 13:40:18 -0600
Subject: [PATCH 510/645] remove regexp in SDC generation.

---
 .../src/fpga_sdc/pnr_sdc_routing_writer.cpp   | 103 ++++--------------
 1 file changed, 23 insertions(+), 80 deletions(-)

diff --git a/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp
index e530e7903..de43b7803 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp
+++ b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp
@@ -101,12 +101,12 @@ void print_pnr_sdc_constrain_sb_mux_timing(std::fstream& fp,
     }
     /* Constrain a path */
     if (false == hierarchical) {
-      print_pnr_sdc_regexp_constrain_max_delay(fp,
-                                               module_path,
-                                               generate_sdc_port(module_manager.module_port(sb_module, module_input_port)),
-                                               module_path,
-                                               generate_sdc_port(module_manager.module_port(sb_module, module_output_port)),
-                                               switch_delays[module_input_port] / time_unit);
+      print_pnr_sdc_constrain_max_delay(fp,
+                                        module_path,
+                                        generate_sdc_port(module_manager.module_port(sb_module, module_input_port)),
+                                        module_path,
+                                        generate_sdc_port(module_manager.module_port(sb_module, module_output_port)),
+                                        switch_delays[module_input_port] / time_unit);
 
     } else {
       VTR_ASSERT_SAFE(true == hierarchical);
@@ -222,13 +222,7 @@ void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_di
       ModuleId sb_module = module_manager.find_module(sb_instance_name);
       VTR_ASSERT(true == module_manager.valid_module_id(sb_module));
 
-      std::string module_path = root_path
-                              + std::string("\\/")
-                              + std::string("(");
-
-      /* Find all the instances in the top-level module */
-      module_path += sb_instance_name;
-      module_path += std::string(")") + std::string("\\");
+      std::string module_path = format_dir_path(root_path) + sb_instance_name;
 
       print_pnr_sdc_constrain_sb_timing(sdc_dir,
                                         time_unit,
@@ -275,22 +269,7 @@ void print_pnr_sdc_compact_routing_constrain_sb_timing(const std::string& sdc_di
     ModuleId sb_module = module_manager.find_module(sb_module_name);
     VTR_ASSERT(true == module_manager.valid_module_id(sb_module));
     
-    std::string module_path = root_path
-                            + std::string("\\/")
-                            + std::string("(");
-
-    /* Find all the instances in the top-level module */
-    bool first_element = true;
-    for (const size_t& instance_id : module_manager.child_module_instances(top_module, sb_module)) {
-      std::string sb_instance_name = module_manager.instance_name(top_module, sb_module, instance_id);
-      if (false == first_element) {
-        module_path += std::string("|");
-      }
-      module_path += sb_instance_name;
-      first_element = false;
-    }
-
-    module_path += std::string(")") + std::string("\\");
+    std::string module_path = format_dir_path(root_path) + sb_module_name;
 
     print_pnr_sdc_constrain_sb_timing(sdc_dir,
                                       time_unit,
@@ -388,12 +367,12 @@ void print_pnr_sdc_constrain_cb_mux_timing(std::fstream& fp,
                                                switch_delays[module_input_port] / time_unit);
     } else {
       VTR_ASSERT_SAFE(false == hierarchical);
-      print_pnr_sdc_regexp_constrain_max_delay(fp,
-                                               std::string(module_path),
-                                               generate_sdc_port(module_manager.module_port(cb_module, module_input_port)),
-                                               std::string(module_path),
-                                               generate_sdc_port(module_manager.module_port(cb_module, module_output_port)),
-                                               switch_delays[module_input_port] / time_unit);
+      print_pnr_sdc_constrain_max_delay(fp,
+                                        std::string(module_path),
+                                        generate_sdc_port(module_manager.module_port(cb_module, module_input_port)),
+                                        std::string(module_path),
+                                        generate_sdc_port(module_manager.module_port(cb_module, module_output_port)),
+                                        switch_delays[module_input_port] / time_unit);
 
     }
   }
@@ -482,12 +461,12 @@ void print_pnr_sdc_constrain_cb_timing(const std::string& sdc_dir,
                                                routing_segment_delay / time_unit);
     } else {
       VTR_ASSERT_SAFE(false == hierarchical);
-      print_pnr_sdc_regexp_constrain_max_delay(fp,
-                                               std::string(module_path),
-                                               generate_sdc_port(module_manager.module_port(cb_module, input_port_id)),
-                                               std::string(module_path),
-                                               generate_sdc_port(module_manager.module_port(cb_module, output_port_id)),
-                                               routing_segment_delay / time_unit);
+      print_pnr_sdc_constrain_max_delay(fp,
+                                        std::string(module_path),
+                                        generate_sdc_port(module_manager.module_port(cb_module, input_port_id)),
+                                        std::string(module_path),
+                                        generate_sdc_port(module_manager.module_port(cb_module, output_port_id)),
+                                        routing_segment_delay / time_unit);
     }
   }
 
@@ -551,13 +530,7 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_di
       ModuleId cb_module = module_manager.find_module(cb_instance_name);
       VTR_ASSERT(true == module_manager.valid_module_id(cb_module));
 
-      std::string module_path = root_path
-                              + std::string("\\/")
-                              + std::string("(");
-
-      /* Find all the instances in the top-level module */
-      module_path += cb_instance_name;
-      module_path += std::string(")") + std::string("\\");
+      std::string module_path = format_dir_path(root_path) + cb_instance_name;
 
       print_pnr_sdc_constrain_cb_timing(sdc_dir,
                                         time_unit,
@@ -636,22 +609,7 @@ void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_di
     ModuleId cb_module = module_manager.find_module(cb_module_name);
     VTR_ASSERT(true == module_manager.valid_module_id(cb_module));
 
-    std::string module_path = root_path
-                            + std::string("\\/")
-                            + std::string("(");
-
-    /* Find all the instances in the top-level module */
-    bool first_element = true;
-    for (const size_t& instance_id : module_manager.child_module_instances(top_module, cb_module)) {
-      std::string cb_instance_name = module_manager.instance_name(top_module, cb_module, instance_id);
-      if (false == first_element) {
-        module_path += std::string("|");
-      }
-      module_path += cb_instance_name;
-      first_element = false;
-    }
-
-    module_path += std::string(")") + std::string("\\");
+    std::string module_path = format_dir_path(root_path) + cb_module_name;
 
     print_pnr_sdc_constrain_cb_timing(sdc_dir,
                                       time_unit,
@@ -676,22 +634,7 @@ void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_di
     ModuleId cb_module = module_manager.find_module(cb_module_name);
     VTR_ASSERT(true == module_manager.valid_module_id(cb_module));
 
-    std::string module_path = root_path
-                            + std::string("\\/")
-                            + std::string("(");
-
-    /* Find all the instances in the top-level module */
-    bool first_element = true;
-    for (const size_t& instance_id : module_manager.child_module_instances(top_module, cb_module)) {
-      std::string cb_instance_name = module_manager.instance_name(top_module, cb_module, instance_id);
-      if (false == first_element) {
-        module_path += std::string("|");
-      }
-      module_path += cb_instance_name;
-      first_element = false;
-    }
-
-    module_path += std::string(")") + std::string("\\");
+    std::string module_path = format_dir_path(root_path) + cb_module_name;
 
     print_pnr_sdc_constrain_cb_timing(sdc_dir,
                                       time_unit,

From 6aff33dd35ecc23d258ddfc043c1cac2f8df1a05 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 5 May 2020 14:36:27 -0600
Subject: [PATCH 511/645] add fabric hierarchy writer

---
 .../libopenfpgautil/src/openfpga_digest.cpp   |  16 +++
 .../libopenfpgautil/src/openfpga_digest.h     |   3 +
 openfpga/src/base/openfpga_build_fabric.cpp   |  25 ++++
 openfpga/src/base/openfpga_build_fabric.h     |   3 +
 openfpga/src/base/openfpga_setup_command.cpp  |  47 ++++++-
 .../src/fabric/fabric_hierarchy_writer.cpp    | 129 ++++++++++++++++++
 openfpga/src/fabric/fabric_hierarchy_writer.h |  23 ++++
 openfpga/test_script/and_k6_frac.openfpga     |   2 +
 8 files changed, 245 insertions(+), 3 deletions(-)
 create mode 100644 openfpga/src/fabric/fabric_hierarchy_writer.cpp
 create mode 100644 openfpga/src/fabric/fabric_hierarchy_writer.h

diff --git a/libopenfpga/libopenfpgautil/src/openfpga_digest.cpp b/libopenfpga/libopenfpgautil/src/openfpga_digest.cpp
index 3ae2083df..00cbbe1e3 100644
--- a/libopenfpga/libopenfpgautil/src/openfpga_digest.cpp
+++ b/libopenfpga/libopenfpgautil/src/openfpga_digest.cpp
@@ -235,4 +235,20 @@ void create_directory(const std::string& dir_path, const bool& recursive) {
   }
 }
 
+/******************************************************************** 
+ * Write a number of space to a file 
+ ********************************************************************/
+bool write_space_to_file(std::fstream& fp,
+                         const size_t& num_space) {
+  if (false == valid_file_stream(fp)) {
+    return false;
+  }
+
+  for (size_t i = 0; i < num_space; ++i) {
+    fp << " ";
+  }
+
+  return true;
+}
+
 } /* namespace openfpga ends */
diff --git a/libopenfpga/libopenfpgautil/src/openfpga_digest.h b/libopenfpga/libopenfpgautil/src/openfpga_digest.h
index 0e1cd5d76..a28b2c4d0 100644
--- a/libopenfpga/libopenfpgautil/src/openfpga_digest.h
+++ b/libopenfpga/libopenfpgautil/src/openfpga_digest.h
@@ -25,6 +25,9 @@ std::string find_path_dir_name(const std::string& file_name);
 
 void create_directory(const std::string& dir_path, const bool& recursive = true); 
 
+bool write_space_to_file(std::fstream& fp,
+                         const size_t& num_space);
+
 } /* namespace openfpga ends */
 
 #endif
diff --git a/openfpga/src/base/openfpga_build_fabric.cpp b/openfpga/src/base/openfpga_build_fabric.cpp
index 67203216a..e013ab267 100644
--- a/openfpga/src/base/openfpga_build_fabric.cpp
+++ b/openfpga/src/base/openfpga_build_fabric.cpp
@@ -11,6 +11,7 @@
 #include "device_rr_gsb.h"
 #include "device_rr_gsb_utils.h"
 #include "build_device_module.h"
+#include "fabric_hierarchy_writer.h"
 #include "openfpga_build_fabric.h"
 
 /* Include global variables of VPR */
@@ -85,4 +86,28 @@ int build_fabric(OpenfpgaContext& openfpga_ctx,
   return CMD_EXEC_SUCCESS;
 } 
 
+/********************************************************************
+ * Build the module graph for FPGA device
+ *******************************************************************/
+int write_fabric_hierarchy(const OpenfpgaContext& openfpga_ctx,
+                           const Command& cmd, const CommandContext& cmd_context) { 
+
+  CommandOptionId opt_verbose = cmd.option("verbose");
+
+  /* Check the option '--file' is enabled or not 
+   * Actually, it must be enabled as the shell interface will check 
+   * before reaching this fuction
+   */
+  CommandOptionId opt_file = cmd.option("file");
+  VTR_ASSERT(true == cmd_context.option_enable(cmd, opt_file));
+  VTR_ASSERT(false == cmd_context.option_value(cmd, opt_file).empty());
+
+  std::string hie_file_name = cmd_context.option_value(cmd, opt_file);
+
+  /* Write hierarchy to a file */
+  return write_fabric_hierarchy_to_text_file(openfpga_ctx.module_graph(),
+                                             hie_file_name,
+                                             cmd_context.option_enable(cmd, opt_verbose));
+}
+
 } /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_build_fabric.h b/openfpga/src/base/openfpga_build_fabric.h
index 3b63c7ab2..6a090397d 100644
--- a/openfpga/src/base/openfpga_build_fabric.h
+++ b/openfpga/src/base/openfpga_build_fabric.h
@@ -18,6 +18,9 @@ namespace openfpga {
 int build_fabric(OpenfpgaContext& openfpga_ctx,
                  const Command& cmd, const CommandContext& cmd_context); 
 
+int write_fabric_hierarchy(const OpenfpgaContext& openfpga_ctx,
+                           const Command& cmd, const CommandContext& cmd_context); 
+
 } /* end namespace openfpga */
 
 #endif
diff --git a/openfpga/src/base/openfpga_setup_command.cpp b/openfpga/src/base/openfpga_setup_command.cpp
index 8f4b0cec3..2a3b11227 100644
--- a/openfpga/src/base/openfpga_setup_command.cpp
+++ b/openfpga/src/base/openfpga_setup_command.cpp
@@ -238,6 +238,37 @@ ShellCommandId add_openfpga_build_fabric_command(openfpga::Shell<OpenfpgaContext
   return shell_cmd_id;
 }
 
+/********************************************************************
+ * - Add a command to Shell environment: write_fabric_hierarchy
+ * - Add associated options 
+ * - Add command dependency
+ *******************************************************************/
+static 
+ShellCommandId add_openfpga_write_fabric_hierarchy_command(openfpga::Shell<OpenfpgaContext>& shell,
+                                                           const ShellCommandClassId& cmd_class_id,
+                                                           const std::vector<ShellCommandId>& dependent_cmds) {
+
+  Command shell_cmd("write_fabric_hierarchy");
+
+  /* Add an option '--file' */
+  CommandOptionId opt_file = shell_cmd.add_option("file", true, "Specify the file name to write the hierarchy to");
+  shell_cmd.set_option_short_name(opt_file, "f");
+  shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING);
+
+  /* Add an option '--verbose' */
+  shell_cmd.add_option("verbose", false, "Show verbose outputs");
+
+  /* Add command 'write_fabric_hierarchy' to the Shell */
+  ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "Write the hierarchy of FPGA fabric graph to a plain-text file");
+  shell.set_command_class(shell_cmd_id, cmd_class_id);
+  shell.set_command_const_execute_function(shell_cmd_id, write_fabric_hierarchy);
+
+  /* Add command dependency to the Shell */
+  shell.set_command_dependency(shell_cmd_id, dependent_cmds);
+
+  return shell_cmd_id;
+}
+
 void add_openfpga_setup_commands(openfpga::Shell<OpenfpgaContext>& shell) {
   /* Get the unique id of 'vpr' command which is to be used in creating the dependency graph */
   const ShellCommandId& vpr_cmd_id = shell.command(std::string("vpr"));
@@ -317,9 +348,19 @@ void add_openfpga_setup_commands(openfpga::Shell<OpenfpgaContext>& shell) {
   /* The 'build_fabric' command should NOT be executed before 'link_openfpga_arch' */
   std::vector<ShellCommandId> build_fabric_dependent_cmds;
   build_fabric_dependent_cmds.push_back(link_arch_cmd_id);
-  add_openfpga_build_fabric_command(shell,
-                                    openfpga_setup_cmd_class,
-                                    build_fabric_dependent_cmds);
+  ShellCommandId build_fabric_cmd_id = add_openfpga_build_fabric_command(shell,
+                                                                         openfpga_setup_cmd_class,
+                                                                         build_fabric_dependent_cmds);
+
+  /******************************** 
+   * Command 'write_fabric_hierarchy' 
+   */
+  /* The 'write_fabric_hierarchy' command should NOT be executed before 'build_fabric' */
+  std::vector<ShellCommandId> write_fabric_hie_dependent_cmds;
+  write_fabric_hie_dependent_cmds.push_back(build_fabric_cmd_id);
+  add_openfpga_write_fabric_hierarchy_command(shell,
+                                              openfpga_setup_cmd_class,
+                                              write_fabric_hie_dependent_cmds);
 } 
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/fabric/fabric_hierarchy_writer.cpp b/openfpga/src/fabric/fabric_hierarchy_writer.cpp
new file mode 100644
index 000000000..7b752f015
--- /dev/null
+++ b/openfpga/src/fabric/fabric_hierarchy_writer.cpp
@@ -0,0 +1,129 @@
+/***************************************************************************************
+ * Output internal structure of Module Graph hierarchy to file formats
+ ***************************************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_log.h"
+#include "vtr_assert.h"
+#include "vtr_time.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_digest.h"
+
+#include "openfpga_naming.h"
+
+#include "fabric_hierarchy_writer.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/***************************************************************************************
+ * Recursively output child module of the parent_module to a text file
+ * We use Depth-First Search (DFS) here so that we can output a tree down to leaf first
+ * Add space (indent) based on the depth in hierarchy
+ * e.g. depth = 1 means a space as indent
+ ***************************************************************************************/
+static 
+int rec_output_module_hierarchy_to_text_file(std::fstream& fp,
+                                             const size_t& hie_depth,
+                                             const ModuleManager& module_manager,  
+                                             const ModuleId& parent_module,
+                                             const bool& verbose) {
+  if (false == valid_file_stream(fp)) {
+    return 2;
+  }
+
+  /* Iterate over all the child module */
+  for (const ModuleId& child_module : module_manager.child_modules(parent_module)) {
+    if (false == write_space_to_file(fp, hie_depth)) {
+      return 2;
+    }
+
+    if (true != module_manager.valid_module_id(child_module)) {
+      VTR_LOGV_ERROR(verbose,
+                     "Unable to find the child module '%u'!\n",
+                     size_t(child_module));
+      return 1;
+    }
+
+    fp << module_manager.module_name(child_module);
+    fp << "\n";
+
+    /* Go to next level */
+    int status = rec_output_module_hierarchy_to_text_file(fp,
+                                                          hie_depth + 1, /* Increment the depth for the next level */
+                                                          module_manager,
+                                                          child_module,
+                                                          verbose);
+    if (0 != status) {
+      return status;
+    }
+  }
+
+  return 0;
+}
+
+/***************************************************************************************
+ * Write the hierarchy of modules to a plain text file
+ * e.g.,
+ *    <module_name>
+ *      <child_module_name>
+ *        ...
+ * This file is mainly used by hierarchical P&R flow 
+ *
+ * Return 0 if successful
+ * Return 1 if there are more serious bugs in the architecture 
+ * Return 2 if fail when creating files
+ ***************************************************************************************/
+int write_fabric_hierarchy_to_text_file(const ModuleManager& module_manager,
+                                        const std::string& fname,
+                                        const bool& verbose) {
+  std::string timer_message = std::string("Write fabric hierarchy to plain-text file '") + fname + std::string("'");
+
+  std::string dir_path = format_dir_path(find_path_dir_name(fname));
+
+  /* Create directories */
+  create_directory(dir_path);
+
+  /* Start time count */
+  vtr::ScopedStartFinishTimer timer(timer_message);
+
+  /* Use default name if user does not provide one */
+  VTR_ASSERT(true != fname.empty());
+
+  /* Create a file handler*/
+  std::fstream fp;
+  /* Open a file */
+  fp.open(fname, std::fstream::out | std::fstream::trunc);
+
+  /* Validate the file stream */
+  check_file_stream(fname.c_str(), fp);
+
+  /* Find top-level module */
+  std::string top_module_name = generate_fpga_top_module_name();
+  ModuleId top_module = module_manager.find_module(top_module_name);
+  if (true != module_manager.valid_module_id(top_module)) {
+    VTR_LOGV_ERROR(verbose,
+                   "Unable to find the top-level module '%s'!\n",
+                   top_module_name.c_str());
+    return 1;
+  }
+  
+  /* Record current depth of module: top module is the root with 0 depth */
+  size_t hie_depth = 0;
+
+  fp << top_module_name << "\n";
+
+  /* Visit child module recursively and output the hierarchy */
+  int err_code = rec_output_module_hierarchy_to_text_file(fp,
+                                                          hie_depth + 1, /* Start with level 1 */
+                                                          module_manager,  
+                                                          top_module,
+                                                          verbose);
+
+  /* close a file */
+  fp.close();
+
+  return err_code;
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fabric/fabric_hierarchy_writer.h b/openfpga/src/fabric/fabric_hierarchy_writer.h
new file mode 100644
index 000000000..48e112c76
--- /dev/null
+++ b/openfpga/src/fabric/fabric_hierarchy_writer.h
@@ -0,0 +1,23 @@
+#ifndef FABRIC_HIERARCHY_WRITER_H
+#define FABRIC_HIERARCHY_WRITER_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "vpr_context.h"
+#include "openfpga_context.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+int write_fabric_hierarchy_to_text_file(const ModuleManager& module_manager,
+                                        const std::string& fname,
+                                        const bool& verbose);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/test_script/and_k6_frac.openfpga b/openfpga/test_script/and_k6_frac.openfpga
index 20a75a661..014142fb1 100644
--- a/openfpga/test_script/and_k6_frac.openfpga
+++ b/openfpga/test_script/and_k6_frac.openfpga
@@ -24,6 +24,8 @@ lut_truth_table_fixup #--verbose
 #  - Enable pin duplication on grid modules 
 build_fabric --compress_routing --duplicate_grid_pin #--verbose
 
+write_fabric_hierarchy --file ./fabric_hierarchy.txt
+
 # Repack the netlist to physical pbs
 # This must be done before bitstream generator and testbench generation
 # Strongly recommend it is done after all the fix-up have been applied

From 1943929353ad5a70355f62a131f705e5c11ff29b Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 5 May 2020 14:38:46 -0600
Subject: [PATCH 512/645] add write_fabric_hierarchy to regression tests

---
 .../duplicated_grid_pin_example_script.openfpga               | 4 ++++
 openfpga_flow/OpenFPGAShellScripts/example_script.openfpga    | 4 ++++
 .../flatten_routing_example_script.openfpga                   | 4 ++++
 .../generate_fabric_example_script.openfpga                   | 4 ++++
 .../generate_testbench_example_script.openfpga                | 4 ++++
 .../implicit_verilog_example_script.openfpga                  | 4 ++++
 .../OpenFPGAShellScripts/mcnc_example_script.openfpga         | 4 ++++
 .../sdc_time_unit_example_script.openfpga                     | 4 ++++
 8 files changed, 32 insertions(+)

diff --git a/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga
index ac808a9a6..1ccd8418d 100644
--- a/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga
@@ -23,6 +23,10 @@ lut_truth_table_fixup
 #  - Enable pin duplication on grid modules
 build_fabric --compress_routing #--verbose
 
+# Write the fabric hierarchy of module graph to a file
+# This is used by hierarchical PnR flows
+write_fabric_hierarchy --file ./fabric_hierarchy.txt
+
 # Repack the netlist to physical pbs
 # This must be done before bitstream generator and testbench generation
 # Strongly recommend it is done after all the fix-up have been applied
diff --git a/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
index ac808a9a6..1ccd8418d 100644
--- a/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
@@ -23,6 +23,10 @@ lut_truth_table_fixup
 #  - Enable pin duplication on grid modules
 build_fabric --compress_routing #--verbose
 
+# Write the fabric hierarchy of module graph to a file
+# This is used by hierarchical PnR flows
+write_fabric_hierarchy --file ./fabric_hierarchy.txt
+
 # Repack the netlist to physical pbs
 # This must be done before bitstream generator and testbench generation
 # Strongly recommend it is done after all the fix-up have been applied
diff --git a/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga
index 06a89a4f5..529fc19ae 100644
--- a/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga
@@ -23,6 +23,10 @@ lut_truth_table_fixup
 #  - Enable pin duplication on grid modules
 build_fabric #--verbose
 
+# Write the fabric hierarchy of module graph to a file
+# This is used by hierarchical PnR flows
+write_fabric_hierarchy --file ./fabric_hierarchy.txt
+
 # Repack the netlist to physical pbs
 # This must be done before bitstream generator and testbench generation
 # Strongly recommend it is done after all the fix-up have been applied
diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga
index 23ed17f59..6514f36b4 100644
--- a/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga
@@ -17,6 +17,10 @@ check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
 #  - Enable pin duplication on grid modules
 build_fabric --compress_routing #--verbose
 
+# Write the fabric hierarchy of module graph to a file
+# This is used by hierarchical PnR flows
+write_fabric_hierarchy --file ./fabric_hierarchy.txt
+
 # Write the Verilog netlist for FPGA fabric
 #  - Enable the use of explicit port mapping in Verilog netlist
 write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga
index 0926935e9..5f7be9ffa 100644
--- a/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga
@@ -23,6 +23,10 @@ lut_truth_table_fixup
 #  - Enable pin duplication on grid modules
 build_fabric --compress_routing #--verbose
 
+# Write the fabric hierarchy of module graph to a file
+# This is used by hierarchical PnR flows
+write_fabric_hierarchy --file ./fabric_hierarchy.txt
+
 # Repack the netlist to physical pbs
 # This must be done before bitstream generator and testbench generation
 # Strongly recommend it is done after all the fix-up have been applied
diff --git a/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga
index d23534cbe..aa4ea30ad 100644
--- a/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga
@@ -23,6 +23,10 @@ lut_truth_table_fixup
 #  - Enable pin duplication on grid modules
 build_fabric --compress_routing --duplicate_grid_pin #--verbose
 
+# Write the fabric hierarchy of module graph to a file
+# This is used by hierarchical PnR flows
+write_fabric_hierarchy --file ./fabric_hierarchy.txt
+
 # Repack the netlist to physical pbs
 # This must be done before bitstream generator and testbench generation
 # Strongly recommend it is done after all the fix-up have been applied
diff --git a/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga
index ba086855e..71d3ee294 100644
--- a/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga
@@ -23,6 +23,10 @@ lut_truth_table_fixup
 #  - Enable pin duplication on grid modules
 build_fabric --compress_routing #--verbose
 
+# Write the fabric hierarchy of module graph to a file
+# This is used by hierarchical PnR flows
+write_fabric_hierarchy --file ./fabric_hierarchy.txt
+
 # Repack the netlist to physical pbs
 # This must be done before bitstream generator and testbench generation
 # Strongly recommend it is done after all the fix-up have been applied
diff --git a/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga
index 1d153a4e9..39c4d1c70 100644
--- a/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga
@@ -23,6 +23,10 @@ lut_truth_table_fixup
 #  - Enable pin duplication on grid modules
 build_fabric --compress_routing #--verbose
 
+# Write the fabric hierarchy of module graph to a file
+# This is used by hierarchical PnR flows
+write_fabric_hierarchy --file ./fabric_hierarchy.txt
+
 # Repack the netlist to physical pbs
 # This must be done before bitstream generator and testbench generation
 # Strongly recommend it is done after all the fix-up have been applied

From c651df64218961058d03213dcbca9451bd926672 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 5 May 2020 15:35:41 -0600
Subject: [PATCH 513/645] add hierarchy writer to SDC generator

---
 openfpga/src/base/openfpga_sdc.cpp            |   3 +
 openfpga/src/base/openfpga_sdc_command.cpp    |   3 +
 openfpga/src/fpga_sdc/pnr_sdc_option.cpp      |   8 +
 openfpga/src/fpga_sdc/pnr_sdc_option.h        |   3 +
 openfpga/src/fpga_sdc/pnr_sdc_writer.cpp      |  26 +++
 .../src/fpga_sdc/sdc_hierarchy_writer.cpp     | 173 ++++++++++++++++++
 6 files changed, 216 insertions(+)
 create mode 100644 openfpga/src/fpga_sdc/sdc_hierarchy_writer.cpp

diff --git a/openfpga/src/base/openfpga_sdc.cpp b/openfpga/src/base/openfpga_sdc.cpp
index d90376839..d492e653a 100644
--- a/openfpga/src/base/openfpga_sdc.cpp
+++ b/openfpga/src/base/openfpga_sdc.cpp
@@ -33,6 +33,7 @@ int write_pnr_sdc(OpenfpgaContext& openfpga_ctx,
   CommandOptionId opt_flatten_names = cmd.option("flatten_names");
   CommandOptionId opt_hierarchical = cmd.option("hierarchical");
   CommandOptionId opt_time_unit = cmd.option("time_unit");
+  CommandOptionId opt_output_hierarchy = cmd.option("output_hierarchy");
   CommandOptionId opt_constrain_global_port = cmd.option("constrain_global_port");
   CommandOptionId opt_constrain_non_clock_global_port = cmd.option("constrain_non_clock_global_port");
   CommandOptionId opt_constrain_grid = cmd.option("constrain_grid");
@@ -60,6 +61,8 @@ int write_pnr_sdc(OpenfpgaContext& openfpga_ctx,
     options.set_time_unit(string_to_time_unit(cmd_context.option_value(cmd, opt_time_unit)));
   }
 
+  options.set_output_hierarchy(cmd_context.option_enable(cmd, opt_output_hierarchy));
+
   options.set_constrain_global_port(cmd_context.option_enable(cmd, opt_constrain_global_port));
   options.set_constrain_non_clock_global_port(cmd_context.option_enable(cmd, opt_constrain_non_clock_global_port));
   options.set_constrain_grid(cmd_context.option_enable(cmd, opt_constrain_grid));
diff --git a/openfpga/src/base/openfpga_sdc_command.cpp b/openfpga/src/base/openfpga_sdc_command.cpp
index bdf123e8b..6d58d4ac1 100644
--- a/openfpga/src/base/openfpga_sdc_command.cpp
+++ b/openfpga/src/base/openfpga_sdc_command.cpp
@@ -32,6 +32,9 @@ ShellCommandId add_openfpga_write_pnr_sdc_command(openfpga::Shell<OpenfpgaContex
   /* Add an option '--hierarchical' */
   shell_cmd.add_option("hierarchical", false, "Output SDC files hierachically (without full path in hierarchy)");
 
+  /* Add an option '--output_hierarchy' */
+  shell_cmd.add_option("output_hierarchy", false, "Output hierachy of Multiple-Instance-Blocks (MIBs) to plain text file. This is applied to constrain timing for grid, SBs and CBs");
+
   /* Add an option '--time_unit' */
   CommandOptionId time_unit_opt = shell_cmd.add_option("time_unit", false, "Specify the time unit in SDC files. Acceptable is [a|f|p|n|u|m|kM]s");
   shell_cmd.set_option_require_value(time_unit_opt, openfpga::OPT_STRING);
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_option.cpp b/openfpga/src/fpga_sdc/pnr_sdc_option.cpp
index f8ee429f3..321cc2ca4 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_option.cpp
+++ b/openfpga/src/fpga_sdc/pnr_sdc_option.cpp
@@ -44,6 +44,10 @@ float PnrSdcOption::time_unit() const {
   return time_unit_;
 }
 
+bool PnrSdcOption::output_hierarchy() const {
+  return output_hierarchy_;
+}
+
 bool PnrSdcOption::generate_sdc_pnr() const {
   return constrain_global_port_ 
       || constrain_grid_
@@ -109,6 +113,10 @@ void PnrSdcOption::set_time_unit(const float& time_unit) {
   time_unit_ = time_unit;
 }
 
+void PnrSdcOption::set_output_hierarchy(const bool& output_hierarchy) {
+  output_hierarchy_ = output_hierarchy;
+}
+
 void PnrSdcOption::set_generate_sdc_pnr(const bool& generate_sdc_pnr) {
   constrain_global_port_ = generate_sdc_pnr;
   constrain_grid_ = generate_sdc_pnr;
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_option.h b/openfpga/src/fpga_sdc/pnr_sdc_option.h
index 4fe997321..9cc1e6d24 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_option.h
+++ b/openfpga/src/fpga_sdc/pnr_sdc_option.h
@@ -19,6 +19,7 @@ class PnrSdcOption {
     bool flatten_names() const;
     bool hierarchical() const;
     float time_unit() const;
+    bool output_hierarchy() const;
     bool generate_sdc_pnr() const;
     bool constrain_global_port() const;
     bool constrain_non_clock_global_port() const;
@@ -34,6 +35,7 @@ class PnrSdcOption {
     void set_flatten_names(const bool& flatten_names);
     void set_hierarchical(const bool& hierarchical);
     void set_time_unit(const float& time_unit);
+    void set_output_hierarchy(const bool& output_hierarchy);
     void set_generate_sdc_pnr(const bool& generate_sdc_pnr);
     void set_constrain_global_port(const bool& constrain_global_port);
     void set_constrain_non_clock_global_port(const bool& constrain_non_clock_global_port);
@@ -49,6 +51,7 @@ class PnrSdcOption {
     bool flatten_names_;
     bool hierarchical_;
     float time_unit_;
+    bool output_hierarchy_;
     bool constrain_global_port_; 
     bool constrain_non_clock_global_port_; 
     bool constrain_grid_; 
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
index ae6d3a4b8..0d1b71e5f 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
+++ b/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
@@ -30,6 +30,7 @@
 #include "sdc_writer_utils.h"
 #include "sdc_memory_utils.h"
 #include "sdc_mux_utils.h"
+#include "sdc_hierarchy_writer.h"
 #include "pnr_sdc_global_port.h"
 #include "pnr_sdc_routing_writer.h"
 #include "pnr_sdc_grid_writer.h"
@@ -462,6 +463,15 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options,
     }
   }
 
+  /* Output hierachy to plain text file */
+  if ( (true == sdc_options.output_hierarchy())
+    && (true == compact_routing_hierarchy) ) {
+    print_pnr_sdc_routing_sb_hierarchy(sdc_options.sdc_dir(),
+                                       module_manager,
+                                       top_module,
+                                       device_rr_gsb);
+  }
+
   /* Output routing constraints for Connection Blocks */
   if (true == sdc_options.constrain_cb()) {
     if (true == compact_routing_hierarchy) {
@@ -486,6 +496,22 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options,
     }
   }
 
+  /* Output hierachy to plain text file */
+  if ( (true == sdc_options.output_hierarchy())
+    && (true == compact_routing_hierarchy) ) {
+    print_pnr_sdc_routing_cb_hierarchy(sdc_options.sdc_dir(),
+                                       module_manager,
+                                       top_module,
+                                       CHANX,
+                                       device_rr_gsb);
+
+    print_pnr_sdc_routing_cb_hierarchy(sdc_options.sdc_dir(),
+                                       module_manager,
+                                       top_module,
+                                       CHANY,
+                                       device_rr_gsb);
+  }
+
   /* Output Timing constraints for Programmable blocks */
   if (true == sdc_options.constrain_grid()) {
     print_pnr_sdc_constrain_grid_timing(sdc_options.sdc_dir(),
diff --git a/openfpga/src/fpga_sdc/sdc_hierarchy_writer.cpp b/openfpga/src/fpga_sdc/sdc_hierarchy_writer.cpp
new file mode 100644
index 000000000..05101ab15
--- /dev/null
+++ b/openfpga/src/fpga_sdc/sdc_hierarchy_writer.cpp
@@ -0,0 +1,173 @@
+/***************************************************************************************
+ * Output instance hierarchy in SDC to file formats
+ ***************************************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_log.h"
+#include "vtr_assert.h"
+#include "vtr_time.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_digest.h"
+
+#include "openfpga_naming.h"
+
+#include "sdc_writer_naming.h"
+#include "sdc_hierarchy_writer.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/***************************************************************************************
+ * Write the hierarchy of Switch Block module and its instances to a plain text file
+ * e.g.,
+ *    <sdc_file_for_the_module>
+ *      <module_name>/<instance_name>
+ *        ...
+ * This file is mainly used by hierarchical P&R flow 
+ *
+ * Return 0 if successful
+ * Return 1 if there are more serious bugs in the architecture 
+ * Return 2 if fail when creating files
+ ***************************************************************************************/
+void print_pnr_sdc_routing_sb_hierarchy(const std::string& sdc_dir,
+                                        const ModuleManager& module_manager,
+                                        const ModuleId& top_module,
+                                        const DeviceRRGSB& device_rr_gsb) {
+
+  std::string fname(sdc_dir + std::string("sb_hierarchy.txt"));
+
+  std::string timer_message = std::string("Write Switch Block hierarchy to plain-text file '") + fname + std::string("'");
+
+  std::string dir_path = format_dir_path(find_path_dir_name(fname));
+
+  /* Create directories */
+  create_directory(dir_path);
+
+  /* Start time count */
+  vtr::ScopedStartFinishTimer timer(timer_message);
+
+  /* Use default name if user does not provide one */
+  VTR_ASSERT(true != fname.empty());
+
+  /* Create a file handler*/
+  std::fstream fp;
+  /* Open a file */
+  fp.open(fname, std::fstream::out | std::fstream::trunc);
+
+  /* Validate the file stream */
+  check_file_stream(fname.c_str(), fp);
+
+  for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_module(); ++isb) {
+    const RRGSB& rr_gsb = device_rr_gsb.get_sb_unique_module(isb);
+    if (false == rr_gsb.is_sb_exist()) {
+      continue;
+    }
+
+    /* Find all the sb instance under this module
+     * Create a regular expression to include these instance names 
+     */
+    vtr::Point<size_t> gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
+    std::string sb_module_name = generate_switch_block_module_name(gsb_coordinate); 
+
+    ModuleId sb_module = module_manager.find_module(sb_module_name);
+    VTR_ASSERT(true == module_manager.valid_module_id(sb_module));
+
+    /* Create the file name for SDC */
+    std::string sdc_fname(sdc_dir + generate_switch_block_module_name(gsb_coordinate) + std::string(SDC_FILE_NAME_POSTFIX));
+
+    fp << sdc_fname << "\n";
+
+    /* Go through all the instance */
+    for (const size_t& instance_id : module_manager.child_module_instances(top_module, sb_module)) {
+      std::string sb_instance_name = module_manager.instance_name(top_module, sb_module, instance_id);
+      fp << " - ";
+      fp << sb_module_name << "/" << sb_instance_name << "\n";  
+    } 
+
+    fp << "\n";
+  }
+
+  /* close a file */
+  fp.close();
+}
+
+/***************************************************************************************
+ * Write the hierarchy of Switch Block module and its instances to a plain text file
+ * e.g.,
+ *    <sdc_file_for_the_module>
+ *      <module_name>/<instance_name>
+ *        ...
+ * This file is mainly used by hierarchical P&R flow 
+ *
+ * Return 0 if successful
+ * Return 1 if there are more serious bugs in the architecture 
+ * Return 2 if fail when creating files
+ ***************************************************************************************/
+void print_pnr_sdc_routing_cb_hierarchy(const std::string& sdc_dir,
+                                        const ModuleManager& module_manager,
+                                        const ModuleId& top_module,
+                                        const t_rr_type& cb_type,
+                                        const DeviceRRGSB& device_rr_gsb) {
+
+  /* TODO: This is dirty, should use constant to handle this */
+  std::string fname(sdc_dir);
+  if (CHANX == cb_type) {
+    fname += std::string("cbx_hierarchy.txt");
+  } else {
+    VTR_ASSERT(CHANY == cb_type);
+    fname += std::string("cby_hierarchy.txt");
+  }
+
+  std::string timer_message = std::string("Write Connection Block hierarchy to plain-text file '") + fname + std::string("'");
+
+  std::string dir_path = format_dir_path(find_path_dir_name(fname));
+
+  /* Create directories */
+  create_directory(dir_path);
+
+  /* Start time count */
+  vtr::ScopedStartFinishTimer timer(timer_message);
+
+  /* Use default name if user does not provide one */
+  VTR_ASSERT(true != fname.empty());
+
+  /* Create a file handler*/
+  std::fstream fp;
+  /* Open a file */
+  fp.open(fname, std::fstream::out | std::fstream::trunc);
+
+  /* Validate the file stream */
+  check_file_stream(fname.c_str(), fp);
+
+  /* Print SDC for unique X-direction connection block modules */
+  for (size_t icb = 0; icb < device_rr_gsb.get_num_cb_unique_module(cb_type); ++icb) {
+    const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(cb_type, icb);
+
+    /* Find all the cb instance under this module
+     * Create a regular expression to include these instance names 
+     */
+    vtr::Point<size_t> gsb_coordinate(unique_mirror.get_cb_x(cb_type), unique_mirror.get_cb_y(cb_type));
+    std::string cb_module_name = generate_connection_block_module_name(cb_type, gsb_coordinate); 
+    ModuleId cb_module = module_manager.find_module(cb_module_name);
+    VTR_ASSERT(true == module_manager.valid_module_id(cb_module));
+
+    /* Create the file name for SDC */
+    std::string sdc_fname(sdc_dir + generate_connection_block_module_name(cb_type, gsb_coordinate) + std::string(SDC_FILE_NAME_POSTFIX));
+
+    fp << sdc_fname << "\n";
+
+    /* Go through all the instance */
+    for (const size_t& instance_id : module_manager.child_module_instances(top_module, cb_module)) {
+      std::string cb_instance_name = module_manager.instance_name(top_module, cb_module, instance_id);
+      fp << " - ";
+      fp << cb_module_name << "/" << cb_instance_name << "\n";  
+    } 
+
+    fp << "\n";
+  }
+
+  /* close a file */
+  fp.close();
+}
+
+} /* end namespace openfpga */

From 17c254a3706323626008da0433f42679052edb38 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 5 May 2020 15:36:07 -0600
Subject: [PATCH 514/645] add missing file to follow up the previous commit

---
 openfpga/src/fpga_sdc/sdc_hierarchy_writer.h | 30 ++++++++++++++++++++
 1 file changed, 30 insertions(+)
 create mode 100644 openfpga/src/fpga_sdc/sdc_hierarchy_writer.h

diff --git a/openfpga/src/fpga_sdc/sdc_hierarchy_writer.h b/openfpga/src/fpga_sdc/sdc_hierarchy_writer.h
new file mode 100644
index 000000000..3e7cae5a7
--- /dev/null
+++ b/openfpga/src/fpga_sdc/sdc_hierarchy_writer.h
@@ -0,0 +1,30 @@
+#ifndef SDC_HIERARCHY_WRITER_H
+#define SDC_HIERARCHY_WRITER_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "vpr_context.h"
+#include "openfpga_context.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void print_pnr_sdc_routing_sb_hierarchy(const std::string& sdc_dir,
+                                        const ModuleManager& module_manager,
+                                        const ModuleId& top_module,
+                                        const DeviceRRGSB& device_rr_gsb);
+
+void print_pnr_sdc_routing_cb_hierarchy(const std::string& sdc_dir,
+                                        const ModuleManager& module_manager,
+                                        const ModuleId& top_module,
+                                        const t_rr_type& cb_type,
+                                        const DeviceRRGSB& device_rr_gsb);
+
+} /* end namespace openfpga */
+
+#endif

From 752470c2da734d2c69753f883bf6682761575e49 Mon Sep 17 00:00:00 2001
From: Xifan Tang <tangxifan@gmail.com>
Date: Tue, 5 May 2020 15:50:55 -0600
Subject: [PATCH 515/645] update documentation on write hierarchy command and
 options

---
 docs/source/openfpga_shell/openfpga_commands.rst | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/docs/source/openfpga_shell/openfpga_commands.rst b/docs/source/openfpga_shell/openfpga_commands.rst
index 987e8b981..296a24a25 100644
--- a/docs/source/openfpga_shell/openfpga_commands.rst
+++ b/docs/source/openfpga_shell/openfpga_commands.rst
@@ -102,6 +102,15 @@ Setup OpenFPGA
 
   .. note:: This is a must-run command before launching FPGA-Verilog, FPGA-Bitstream, FPGA-SDC and FPGA-SPICE
 
+.. option:: write_fabric_hierarchy
+
+  Write the hierarchy of FPGA fabric graph to a plain-text file
+  
+  - ``--file`` or ``-f`` Specify the file name to write the hierarchy. 
+
+  - ``--verbose`` Show verbose log
+
+  .. note:: This file is designed for hierarchical PnR flow, which requires the tree of Multiple-Instanced-Blocks (MIBs).
   
 FPGA-Bitstream
 ~~~~~~~~~~~~~~
@@ -182,6 +191,10 @@ FPGA-SDC
 
   - ``--time_unit`` Specify a time unit to be used in SDC files. Acceptable values are string: ``as`` | ``fs`` | ``ps`` | ``ns`` | ``us`` | ``ms`` | ``ks`` | ``Ms``. By default, we will consider second (``s``).
 
+  - ``--output_hierarchy`` Output hierarchy of Multiple-Instance-Blocks(MIBs) to plain text file. This is applied to constrain timing for grids, Switch Blocks and Connection Blocks. 
+
+    .. note:: Valid only when ``compress_routing`` is enabled in ``build_fabric``
+
   - ``--constrain_global_port`` Constrain all the global ports of FPGA fabric.
 
   - ``--constrain_non_clock_global_port`` Constrain all the non-clock global ports as clocks ports of FPGA fabric

From d9dc7160a7f98efcb3be1a593f01860cf299e853 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 5 May 2020 16:14:08 -0600
Subject: [PATCH 516/645] minor fix on the hierarchy writer in SDC generator

---
 openfpga/src/base/openfpga_sdc_command.cpp     |  2 +-
 openfpga/src/fpga_sdc/sdc_hierarchy_writer.cpp | 12 ++++++------
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/openfpga/src/base/openfpga_sdc_command.cpp b/openfpga/src/base/openfpga_sdc_command.cpp
index 6d58d4ac1..a0f578786 100644
--- a/openfpga/src/base/openfpga_sdc_command.cpp
+++ b/openfpga/src/base/openfpga_sdc_command.cpp
@@ -36,7 +36,7 @@ ShellCommandId add_openfpga_write_pnr_sdc_command(openfpga::Shell<OpenfpgaContex
   shell_cmd.add_option("output_hierarchy", false, "Output hierachy of Multiple-Instance-Blocks (MIBs) to plain text file. This is applied to constrain timing for grid, SBs and CBs");
 
   /* Add an option '--time_unit' */
-  CommandOptionId time_unit_opt = shell_cmd.add_option("time_unit", false, "Specify the time unit in SDC files. Acceptable is [a|f|p|n|u|m|kM]s");
+  CommandOptionId time_unit_opt = shell_cmd.add_option("time_unit", false, "Specify the time unit in SDC files. Acceptable is [a|f|p|n|u|m|k|M]s");
   shell_cmd.set_option_require_value(time_unit_opt, openfpga::OPT_STRING);
 
   /* Add an option '--constrain_global_port' */
diff --git a/openfpga/src/fpga_sdc/sdc_hierarchy_writer.cpp b/openfpga/src/fpga_sdc/sdc_hierarchy_writer.cpp
index 05101ab15..aff95ec5b 100644
--- a/openfpga/src/fpga_sdc/sdc_hierarchy_writer.cpp
+++ b/openfpga/src/fpga_sdc/sdc_hierarchy_writer.cpp
@@ -75,13 +75,13 @@ void print_pnr_sdc_routing_sb_hierarchy(const std::string& sdc_dir,
     /* Create the file name for SDC */
     std::string sdc_fname(sdc_dir + generate_switch_block_module_name(gsb_coordinate) + std::string(SDC_FILE_NAME_POSTFIX));
 
-    fp << sdc_fname << "\n";
+    fp << "- " << sb_module_name << "\n";
 
     /* Go through all the instance */
     for (const size_t& instance_id : module_manager.child_module_instances(top_module, sb_module)) {
       std::string sb_instance_name = module_manager.instance_name(top_module, sb_module, instance_id);
-      fp << " - ";
-      fp << sb_module_name << "/" << sb_instance_name << "\n";  
+      fp << "  ";
+      fp << "- " << sb_instance_name << "\n";  
     } 
 
     fp << "\n";
@@ -154,13 +154,13 @@ void print_pnr_sdc_routing_cb_hierarchy(const std::string& sdc_dir,
     /* Create the file name for SDC */
     std::string sdc_fname(sdc_dir + generate_connection_block_module_name(cb_type, gsb_coordinate) + std::string(SDC_FILE_NAME_POSTFIX));
 
-    fp << sdc_fname << "\n";
+    fp << "- " << cb_module_name << "\n";
 
     /* Go through all the instance */
     for (const size_t& instance_id : module_manager.child_module_instances(top_module, cb_module)) {
       std::string cb_instance_name = module_manager.instance_name(top_module, cb_module, instance_id);
-      fp << " - ";
-      fp << cb_module_name << "/" << cb_instance_name << "\n";  
+      fp << "  ";
+      fp << "- " << cb_instance_name << "\n";  
     } 
 
     fp << "\n";

From 5a8c05378e300970b300f985708de0bbc0c6ecbf Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 5 May 2020 16:40:41 -0600
Subject: [PATCH 517/645] add --depth option to fabric hierarchy writer

---
 openfpga/src/base/openfpga_build_fabric.cpp   | 14 ++++++++++++++
 openfpga/src/base/openfpga_setup_command.cpp  |  4 ++++
 .../src/fabric/fabric_hierarchy_writer.cpp    | 19 ++++++++++++++++---
 openfpga/src/fabric/fabric_hierarchy_writer.h |  1 +
 4 files changed, 35 insertions(+), 3 deletions(-)

diff --git a/openfpga/src/base/openfpga_build_fabric.cpp b/openfpga/src/base/openfpga_build_fabric.cpp
index e013ab267..708bef124 100644
--- a/openfpga/src/base/openfpga_build_fabric.cpp
+++ b/openfpga/src/base/openfpga_build_fabric.cpp
@@ -102,11 +102,25 @@ int write_fabric_hierarchy(const OpenfpgaContext& openfpga_ctx,
   VTR_ASSERT(true == cmd_context.option_enable(cmd, opt_file));
   VTR_ASSERT(false == cmd_context.option_value(cmd, opt_file).empty());
 
+  /* Default depth requirement, will not stop until the leaf */
+  int depth = -1;
+  CommandOptionId opt_depth = cmd.option("depth");
+  if (true == cmd_context.option_enable(cmd, opt_depth)) {
+    depth = std::atoi(cmd_context.option_value(cmd, opt_depth).c_str());
+    /* Error out if we have negative depth */
+    if (0 > depth) {
+      VTR_LOG_ERROR("Invalid depth '%d' which should be 0 or a positive number!\n",
+                    depth);
+      return CMD_EXEC_FATAL_ERROR; 
+    }
+  }
+
   std::string hie_file_name = cmd_context.option_value(cmd, opt_file);
 
   /* Write hierarchy to a file */
   return write_fabric_hierarchy_to_text_file(openfpga_ctx.module_graph(),
                                              hie_file_name,
+                                             size_t(depth),
                                              cmd_context.option_enable(cmd, opt_verbose));
 }
 
diff --git a/openfpga/src/base/openfpga_setup_command.cpp b/openfpga/src/base/openfpga_setup_command.cpp
index 2a3b11227..8af22e7da 100644
--- a/openfpga/src/base/openfpga_setup_command.cpp
+++ b/openfpga/src/base/openfpga_setup_command.cpp
@@ -255,6 +255,10 @@ ShellCommandId add_openfpga_write_fabric_hierarchy_command(openfpga::Shell<Openf
   shell_cmd.set_option_short_name(opt_file, "f");
   shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING);
 
+  /* Add an option '--depth' */
+  CommandOptionId opt_depth = shell_cmd.add_option("depth", false, "Specify the depth of hierarchy to which the writer should stop");
+  shell_cmd.set_option_require_value(opt_depth, openfpga::OPT_INT);
+
   /* Add an option '--verbose' */
   shell_cmd.add_option("verbose", false, "Show verbose outputs");
 
diff --git a/openfpga/src/fabric/fabric_hierarchy_writer.cpp b/openfpga/src/fabric/fabric_hierarchy_writer.cpp
index 7b752f015..959c1fa5f 100644
--- a/openfpga/src/fabric/fabric_hierarchy_writer.cpp
+++ b/openfpga/src/fabric/fabric_hierarchy_writer.cpp
@@ -24,17 +24,23 @@ namespace openfpga {
  ***************************************************************************************/
 static 
 int rec_output_module_hierarchy_to_text_file(std::fstream& fp,
-                                             const size_t& hie_depth,
+                                             const size_t& hie_depth_to_stop,
+                                             const size_t& current_hie_depth,
                                              const ModuleManager& module_manager,  
                                              const ModuleId& parent_module,
                                              const bool& verbose) {
+  /* Stop if hierarchy depth is beyond the stop line */
+  if (hie_depth_to_stop < current_hie_depth) {
+    return 0;
+  }
+
   if (false == valid_file_stream(fp)) {
     return 2;
   }
 
   /* Iterate over all the child module */
   for (const ModuleId& child_module : module_manager.child_modules(parent_module)) {
-    if (false == write_space_to_file(fp, hie_depth)) {
+    if (false == write_space_to_file(fp, current_hie_depth)) {
       return 2;
     }
 
@@ -50,7 +56,8 @@ int rec_output_module_hierarchy_to_text_file(std::fstream& fp,
 
     /* Go to next level */
     int status = rec_output_module_hierarchy_to_text_file(fp,
-                                                          hie_depth + 1, /* Increment the depth for the next level */
+                                                          hie_depth_to_stop,
+                                                          current_hie_depth + 1, /* Increment the depth for the next level */
                                                           module_manager,
                                                           child_module,
                                                           verbose);
@@ -76,6 +83,7 @@ int rec_output_module_hierarchy_to_text_file(std::fstream& fp,
  ***************************************************************************************/
 int write_fabric_hierarchy_to_text_file(const ModuleManager& module_manager,
                                         const std::string& fname,
+                                        const size_t& hie_depth_to_stop,
                                         const bool& verbose) {
   std::string timer_message = std::string("Write fabric hierarchy to plain-text file '") + fname + std::string("'");
 
@@ -111,10 +119,15 @@ int write_fabric_hierarchy_to_text_file(const ModuleManager& module_manager,
   /* Record current depth of module: top module is the root with 0 depth */
   size_t hie_depth = 0;
 
+  if (hie_depth_to_stop < hie_depth) {
+    return 0;
+  }
+
   fp << top_module_name << "\n";
 
   /* Visit child module recursively and output the hierarchy */
   int err_code = rec_output_module_hierarchy_to_text_file(fp,
+                                                          hie_depth_to_stop,
                                                           hie_depth + 1, /* Start with level 1 */
                                                           module_manager,  
                                                           top_module,
diff --git a/openfpga/src/fabric/fabric_hierarchy_writer.h b/openfpga/src/fabric/fabric_hierarchy_writer.h
index 48e112c76..86ed3a263 100644
--- a/openfpga/src/fabric/fabric_hierarchy_writer.h
+++ b/openfpga/src/fabric/fabric_hierarchy_writer.h
@@ -16,6 +16,7 @@ namespace openfpga {
 
 int write_fabric_hierarchy_to_text_file(const ModuleManager& module_manager,
                                         const std::string& fname,
+                                        const size_t& hie_depth_to_stop,
                                         const bool& verbose);
 
 } /* end namespace openfpga */

From 24934aff863cd739de47013454b710c1cf2b0967 Mon Sep 17 00:00:00 2001
From: Xifan Tang <tangxifan@gmail.com>
Date: Tue, 5 May 2020 16:44:07 -0600
Subject: [PATCH 518/645] update documentation on the depth option for fabric
 hierarchy writer

---
 docs/source/openfpga_shell/openfpga_commands.rst | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/docs/source/openfpga_shell/openfpga_commands.rst b/docs/source/openfpga_shell/openfpga_commands.rst
index 296a24a25..5cd5a8c33 100644
--- a/docs/source/openfpga_shell/openfpga_commands.rst
+++ b/docs/source/openfpga_shell/openfpga_commands.rst
@@ -108,6 +108,8 @@ Setup OpenFPGA
   
   - ``--file`` or ``-f`` Specify the file name to write the hierarchy. 
 
+  - ``--depth`` Specify at which depth of the fabric module graph should the writer stop outputting. The root module start from depth 0. For example, if you want a two-level hierarchy, you should specify depth as 1. 
+
   - ``--verbose`` Show verbose log
 
   .. note:: This file is designed for hierarchical PnR flow, which requires the tree of Multiple-Instanced-Blocks (MIBs).

From b57a90a6ca98bd5080ff321e840ec70d2b57d4d3 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 5 May 2020 20:12:13 -0600
Subject: [PATCH 519/645] add SDC hierarchy writer for grids and now support
 flatten hierarchy in grid timing constraints

---
 openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp | 124 +++++++++--
 openfpga/src/fpga_sdc/pnr_sdc_grid_writer.h   |   2 +
 openfpga/src/fpga_sdc/pnr_sdc_writer.cpp      |  18 +-
 .../src/fpga_sdc/sdc_hierarchy_writer.cpp     | 206 +++++++++++++++++-
 openfpga/src/fpga_sdc/sdc_hierarchy_writer.h  |   7 +
 openfpga/src/fpga_sdc/sdc_writer_naming.h     |   5 +
 6 files changed, 342 insertions(+), 20 deletions(-)

diff --git a/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp
index f0708cc61..740ba097b 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp
+++ b/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp
@@ -21,7 +21,6 @@
 #include "openfpga_digest.h"
 #include "openfpga_side_manager.h"
 
-
 #include "openfpga_interconnect_types.h"
 #include "vpr_utils.h"
 #include "mux_utils.h"
@@ -30,6 +29,7 @@
 #include "openfpga_naming.h"
 #include "pb_type_utils.h"
 #include "pb_graph_utils.h"
+#include "openfpga_physical_tile_utils.h"
 
 #include "sdc_writer_naming.h"
 #include "sdc_writer_utils.h"
@@ -45,6 +45,8 @@ namespace openfpga {
 static 
 void print_pnr_sdc_constrain_pb_pin_interc_timing(std::fstream& fp,
                                                   const float& time_unit,
+                                                  const bool& hierarchical,
+                                                  const std::string& module_path,
                                                   const ModuleManager& module_manager,
                                                   const ModuleId& parent_module,
                                                   t_pb_graph_pin* des_pb_graph_pin,
@@ -147,11 +149,22 @@ void print_pnr_sdc_constrain_pb_pin_interc_timing(std::fstream& fp,
       continue;
     }
 
+    /* Give full path if hierarchical is not enabled */
+    std::string src_module_path = src_instance_name;
+    if (false == hierarchical) {
+      src_module_path = module_path + src_instance_name;
+    }
+
+    std::string des_module_path = des_instance_name;
+    if (false == hierarchical) {
+      src_module_path = module_path + des_instance_name;
+    }
+
     /* Print a SDC timing constraint */
     print_pnr_sdc_constrain_max_delay(fp, 
-                                      src_instance_name, 
+                                      src_module_path, 
                                       generate_sdc_port(src_port),
-                                      des_instance_name, 
+                                      des_module_path, 
                                       generate_sdc_port(des_port),
                                       des_pb_graph_pin->input_edges[iedge]->delay_max / time_unit);
   }
@@ -164,6 +177,8 @@ void print_pnr_sdc_constrain_pb_pin_interc_timing(std::fstream& fp,
 static 
 void print_pnr_sdc_constrain_pb_interc_timing(std::fstream& fp,
                                               const float& time_unit,
+                                              const bool& hierarchical,
+                                              const std::string& module_path,
                                               const ModuleManager& module_manager,
                                               const ModuleId& parent_module,
                                               t_pb_graph_node* des_pb_graph_node,
@@ -181,6 +196,8 @@ void print_pnr_sdc_constrain_pb_interc_timing(std::fstream& fp,
         /* Get the selected edge of current pin*/
         print_pnr_sdc_constrain_pb_pin_interc_timing(fp,
                                                      time_unit, 
+                                                     hierarchical, 
+                                                     module_path, 
                                                      module_manager, parent_module, 
                                                      &(des_pb_graph_node->input_pins[iport][ipin]),
                                                      physical_mode,
@@ -194,6 +211,8 @@ void print_pnr_sdc_constrain_pb_interc_timing(std::fstream& fp,
       for (int ipin = 0; ipin < des_pb_graph_node->num_output_pins[iport]; ++ipin) {
         print_pnr_sdc_constrain_pb_pin_interc_timing(fp,
                                                      time_unit, 
+                                                     hierarchical, 
+                                                     module_path, 
                                                      module_manager, parent_module, 
                                                      &(des_pb_graph_node->output_pins[iport][ipin]),
                                                      physical_mode,
@@ -223,6 +242,8 @@ void print_pnr_sdc_constrain_pb_interc_timing(std::fstream& fp,
 static 
 void print_pnr_sdc_constrain_pb_graph_node_timing(const std::string& sdc_dir,
                                                   const float& time_unit,
+                                                  const bool& hierarchical,
+                                                  const std::string& module_path,
                                                   const ModuleManager& module_manager,
                                                   t_pb_graph_node* parent_pb_graph_node,
                                                   t_mode* physical_mode,
@@ -260,6 +281,8 @@ void print_pnr_sdc_constrain_pb_graph_node_timing(const std::string& sdc_dir,
    */ 
   print_pnr_sdc_constrain_pb_interc_timing(fp,
                                            time_unit,
+                                           hierarchical,
+                                           module_path,
                                            module_manager, pb_module,
                                            parent_pb_graph_node, 
                                            CIRCUIT_PB_PORT_OUTPUT,
@@ -279,6 +302,8 @@ void print_pnr_sdc_constrain_pb_graph_node_timing(const std::string& sdc_dir,
       /* For each child_pb_graph_node input pins*/
       print_pnr_sdc_constrain_pb_interc_timing(fp,
                                                time_unit,
+                                               hierarchical,
+                                               module_path,
                                                module_manager, pb_module,
                                                child_pb_graph_node, 
                                                CIRCUIT_PB_PORT_INPUT,
@@ -303,6 +328,8 @@ void print_pnr_sdc_constrain_pb_graph_node_timing(const std::string& sdc_dir,
 static 
 void print_pnr_sdc_constrain_primitive_pb_graph_node(const std::string& sdc_dir,
                                                      const float& time_unit,
+                                                     const bool& hierarchical,
+                                                     const std::string& module_path,
                                                      const ModuleManager& module_manager,
                                                      t_pb_graph_node* primitive_pb_graph_node,
                                                      const bool& constrain_zero_delay_paths) {
@@ -394,13 +421,20 @@ void print_pnr_sdc_constrain_primitive_pb_graph_node(const std::string& sdc_dir,
 
          /* Find max delay between src and sink pin */
          float tmax = sink_pin->input_edges[iedge]->delay_max;
+
+         /* Generate module path in hierarchy depending if the hierarchical is enabled */
+         std::string module_hie_path = pb_module_name;
+         if (false == hierarchical) {
+           module_hie_path = module_path + pb_module_name;
+         }
+
          /* If the delay is zero, constrain only when user wants it */
          if ( (true == constrain_zero_delay_paths)
            || (0. == tmax) ) {
            print_pnr_sdc_constrain_max_delay(fp, 
-                                             pb_module_name, 
+                                             module_hie_path, 
                                              generate_sdc_port(src_port),
-                                             pb_module_name, 
+                                             module_hie_path, 
                                              generate_sdc_port(sink_port),
                                              tmax / time_unit);
          }
@@ -411,9 +445,9 @@ void print_pnr_sdc_constrain_primitive_pb_graph_node(const std::string& sdc_dir,
          if ( (true == constrain_zero_delay_paths)
            || (0. == tmin) ) {
            print_pnr_sdc_constrain_min_delay(fp, 
-                                             pb_module_name, 
+                                             module_hie_path, 
                                              generate_sdc_port(src_port),
-                                             pb_module_name, 
+                                             module_hie_path, 
                                              generate_sdc_port(sink_port),
                                              tmin / time_unit);
         } 
@@ -433,6 +467,8 @@ void print_pnr_sdc_constrain_primitive_pb_graph_node(const std::string& sdc_dir,
 static 
 void rec_print_pnr_sdc_constrain_pb_graph_timing(const std::string& sdc_dir,
                                                  const float& time_unit,
+                                                 const bool& hierarchical,
+                                                 const std::string& module_path,
                                                  const ModuleManager& module_manager,
                                                  const VprDeviceAnnotation& device_annotation,
                                                  t_pb_graph_node* parent_pb_graph_node,
@@ -451,6 +487,8 @@ void rec_print_pnr_sdc_constrain_pb_graph_timing(const std::string& sdc_dir,
   if (true == is_primitive_pb_type(parent_pb_type)) {
     print_pnr_sdc_constrain_primitive_pb_graph_node(sdc_dir,
                                                     time_unit,
+                                                    hierarchical,
+                                                    module_path,
                                                     module_manager,
                                                     parent_pb_graph_node,
                                                     constrain_zero_delay_paths);
@@ -465,6 +503,8 @@ void rec_print_pnr_sdc_constrain_pb_graph_timing(const std::string& sdc_dir,
   /* Write a SDC file for this pb_type */
   print_pnr_sdc_constrain_pb_graph_node_timing(sdc_dir,
                                                time_unit,
+                                               hierarchical,
+                                               module_path,
                                                module_manager,
                                                parent_pb_graph_node,
                                                physical_mode,
@@ -476,6 +516,8 @@ void rec_print_pnr_sdc_constrain_pb_graph_timing(const std::string& sdc_dir,
   for (int ipb = 0; ipb < physical_mode->num_pb_type_children; ++ipb) {
     rec_print_pnr_sdc_constrain_pb_graph_timing(sdc_dir,
                                                 time_unit, 
+                                                hierarchical,
+                                                format_dir_path(module_path + std::string(physical_mode->pb_type_children[ipb].name)),
                                                 module_manager, 
                                                 device_annotation,
                                                 &(parent_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb][0]),
@@ -488,26 +530,80 @@ void rec_print_pnr_sdc_constrain_pb_graph_timing(const std::string& sdc_dir,
  *******************************************************************/
 void print_pnr_sdc_constrain_grid_timing(const std::string& sdc_dir,
                                          const float& time_unit,
+                                         const bool& hierarchical,
                                          const DeviceContext& device_ctx,
                                          const VprDeviceAnnotation& device_annotation,
                                          const ModuleManager& module_manager,
+                                         const ModuleId& top_module,
                                          const bool& constrain_zero_delay_paths) {
 
   /* Start time count */
   vtr::ScopedStartFinishTimer timer("Write SDC for constraining grid timing for P&R flow");
 
+  std::string root_path = format_dir_path(module_manager.module_name(top_module));
+
   for (const t_physical_tile_type& physical_tile : device_ctx.physical_tile_types) {
     /* Bypass empty type or nullptr */
     if (true == is_empty_type(&physical_tile)) {
       continue;
-    } else {
-      VTR_ASSERT(1 == physical_tile.equivalent_sites.size());
-      t_pb_graph_node* pb_graph_head = physical_tile.equivalent_sites[0]->pb_graph_head;
-      if (nullptr == pb_graph_head) {
-        continue;
+    }
+
+    VTR_ASSERT(1 == physical_tile.equivalent_sites.size());
+    t_pb_graph_node* pb_graph_head = physical_tile.equivalent_sites[0]->pb_graph_head;
+    if (nullptr == pb_graph_head) {
+      continue;
+    }
+
+    if (true == is_io_type(&physical_tile)) {
+      /* Special for I/O block:
+       * We will search the grids and see where the I/O blocks are located:
+       * - If a I/O block locates on border sides of FPGA fabric:
+       *   i.e., one or more from {TOP, RIGHT, BOTTOM, LEFT},
+       *   we will generate one module for each border side 
+       * - If a I/O block locates in the center of FPGA fabric:
+       *   we will generate one module with NUM_SIDES (same treatment as regular grids) 
+       */
+      std::set<e_side> io_type_sides = find_physical_io_tile_located_sides(device_ctx.grid,
+                                                                           &physical_tile);
+
+
+      /* Generate the grid module name */
+      for (const e_side& io_type_side : io_type_sides) {
+        std::string grid_module_name = generate_grid_block_module_name(std::string(GRID_MODULE_NAME_PREFIX), 
+                                                                       std::string(physical_tile.name),
+                                                                       is_io_type(&physical_tile),
+                                                                       io_type_side);
+        /* Find the module Id */
+        ModuleId grid_module = module_manager.find_module(grid_module_name);
+        VTR_ASSERT(true == module_manager.valid_module_id(grid_module));
+
+        std::string module_path = format_dir_path(root_path + grid_module_name);
+
+        rec_print_pnr_sdc_constrain_pb_graph_timing(sdc_dir,
+                                                    time_unit,
+                                                    hierarchical,
+                                                    module_path, 
+                                                    module_manager, 
+                                                    device_annotation,
+                                                    pb_graph_head,
+                                                    constrain_zero_delay_paths);
       }
-      /* Special for I/O block, generate one module for each border side */
-      rec_print_pnr_sdc_constrain_pb_graph_timing(sdc_dir, time_unit,
+    } else {
+      /* For CLB and heterogenenous blocks */
+      std::string grid_module_name = generate_grid_block_module_name(std::string(GRID_MODULE_NAME_PREFIX), 
+                                                                     std::string(physical_tile.name),
+                                                                     is_io_type(&physical_tile),
+                                                                     NUM_SIDES);
+      /* Find the module Id */
+      ModuleId grid_module = module_manager.find_module(grid_module_name);
+      VTR_ASSERT(true == module_manager.valid_module_id(grid_module));
+
+      std::string module_path = format_dir_path(root_path + grid_module_name);
+
+      rec_print_pnr_sdc_constrain_pb_graph_timing(sdc_dir,
+                                                  time_unit,
+                                                  hierarchical,
+                                                  module_path, 
                                                   module_manager, 
                                                   device_annotation,
                                                   pb_graph_head,
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.h b/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.h
index 909caff2a..761bcf94c 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.h
+++ b/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.h
@@ -19,9 +19,11 @@ namespace openfpga {
 
 void print_pnr_sdc_constrain_grid_timing(const std::string& sdc_dir,
                                          const float& time_unit,
+                                         const bool& hierarchical,
                                          const DeviceContext& device_ctx,
                                          const VprDeviceAnnotation& device_annotation,
                                          const ModuleManager& module_manager,
+                                         const ModuleId& top_module,
                                          const bool& constrain_zero_delay_paths);
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
index 0d1b71e5f..3ef29330d 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
+++ b/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
@@ -464,7 +464,8 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options,
   }
 
   /* Output hierachy to plain text file */
-  if ( (true == sdc_options.output_hierarchy())
+  if ( (true == sdc_options.constrain_sb())
+    && (true == sdc_options.output_hierarchy())
     && (true == compact_routing_hierarchy) ) {
     print_pnr_sdc_routing_sb_hierarchy(sdc_options.sdc_dir(),
                                        module_manager,
@@ -497,7 +498,8 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options,
   }
 
   /* Output hierachy to plain text file */
-  if ( (true == sdc_options.output_hierarchy())
+  if ( (true == sdc_options.constrain_cb())
+    && (true == sdc_options.output_hierarchy())
     && (true == compact_routing_hierarchy) ) {
     print_pnr_sdc_routing_cb_hierarchy(sdc_options.sdc_dir(),
                                        module_manager,
@@ -516,11 +518,23 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options,
   if (true == sdc_options.constrain_grid()) {
     print_pnr_sdc_constrain_grid_timing(sdc_options.sdc_dir(),
                                         sdc_options.time_unit(),
+                                        sdc_options.hierarchical(),
                                         device_ctx,
                                         device_annotation,
                                         module_manager,
+                                        top_module,
                                         sdc_options.constrain_zero_delay_paths());
   }
+
+  if ( (true == sdc_options.constrain_grid())
+    && (true == sdc_options.output_hierarchy()) ) {
+    print_pnr_sdc_grid_hierarchy(sdc_options.sdc_dir(),
+                                 device_ctx,
+                                 device_annotation,
+                                 module_manager,
+                                 top_module);
+
+  }
 }
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/fpga_sdc/sdc_hierarchy_writer.cpp b/openfpga/src/fpga_sdc/sdc_hierarchy_writer.cpp
index aff95ec5b..68cbed4b6 100644
--- a/openfpga/src/fpga_sdc/sdc_hierarchy_writer.cpp
+++ b/openfpga/src/fpga_sdc/sdc_hierarchy_writer.cpp
@@ -9,8 +9,12 @@
 /* Headers from openfpgautil library */
 #include "openfpga_digest.h"
 
+#include "openfpga_reserved_words.h"
 #include "openfpga_naming.h"
 
+#include "pb_type_utils.h"
+#include "openfpga_physical_tile_utils.h"
+
 #include "sdc_writer_naming.h"
 #include "sdc_hierarchy_writer.h"
 
@@ -34,7 +38,7 @@ void print_pnr_sdc_routing_sb_hierarchy(const std::string& sdc_dir,
                                         const ModuleId& top_module,
                                         const DeviceRRGSB& device_rr_gsb) {
 
-  std::string fname(sdc_dir + std::string("sb_hierarchy.txt"));
+  std::string fname(sdc_dir + std::string(SDC_SB_HIERARCHY_FILE_NAME));
 
   std::string timer_message = std::string("Write Switch Block hierarchy to plain-text file '") + fname + std::string("'");
 
@@ -109,13 +113,12 @@ void print_pnr_sdc_routing_cb_hierarchy(const std::string& sdc_dir,
                                         const t_rr_type& cb_type,
                                         const DeviceRRGSB& device_rr_gsb) {
 
-  /* TODO: This is dirty, should use constant to handle this */
   std::string fname(sdc_dir);
   if (CHANX == cb_type) {
-    fname += std::string("cbx_hierarchy.txt");
+    fname += std::string(SDC_CBX_HIERARCHY_FILE_NAME);
   } else {
     VTR_ASSERT(CHANY == cb_type);
-    fname += std::string("cby_hierarchy.txt");
+    fname += std::string(SDC_CBY_HIERARCHY_FILE_NAME);
   }
 
   std::string timer_message = std::string("Write Connection Block hierarchy to plain-text file '") + fname + std::string("'");
@@ -170,4 +173,199 @@ void print_pnr_sdc_routing_cb_hierarchy(const std::string& sdc_dir,
   fp.close();
 }
 
+/********************************************************************
+ * Recursively write the hierarchy of pb_type and its instances to a plain text file
+ * e.g.,
+ *    <sdc_file_for_the_module>
+ *      <module_name>/<instance_name>
+ *        ...
+ * This file is mainly used by hierarchical P&R flow 
+ *******************************************************************/
+static 
+void rec_print_pnr_sdc_grid_pb_graph_hierarchy(std::fstream& fp,
+                                               const ModuleManager& module_manager,
+                                               const ModuleId& parent_pb_module,
+                                               const VprDeviceAnnotation& device_annotation,
+                                               t_pb_graph_node* parent_pb_graph_node) {
+  /* Validate the file stream */
+  VTR_ASSERT(true == valid_file_stream(fp));
+
+  /* Validate pb_graph node */
+  if (nullptr == parent_pb_graph_node) {
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid parent_pb_graph_node.\n");
+    exit(1);
+  }
+
+  /* Get the pb_type */
+  t_pb_type* parent_pb_type = parent_pb_graph_node->pb_type;
+
+  if (true == is_primitive_pb_type(parent_pb_type)) {
+    return;
+  }
+
+  std::string pb_module_name = generate_physical_block_module_name(parent_pb_type);
+
+  /* Find the pb module in module manager */
+  ModuleId pb_module = module_manager.find_module(pb_module_name);
+  VTR_ASSERT(true == module_manager.valid_module_id(pb_module));
+
+  fp << "- " << pb_module_name << "\n";
+
+  /* Go through all the instance */
+  for (const size_t& instance_id : module_manager.child_module_instances(parent_pb_module, pb_module)) {
+    std::string child_instance_name = module_manager.instance_name(parent_pb_module, pb_module, instance_id);
+    fp << "  ";
+    fp << "- " << child_instance_name << "\n";  
+  } 
+
+  fp << "\n";
+
+  /* Note we only go through the graph through the physical modes. 
+   * which we build the modules 
+   */
+  t_mode* physical_mode = device_annotation.physical_mode(parent_pb_type);  
+
+  /* Go recursively to the lower level in the pb_graph
+   * Note that we assume a full hierarchical P&R, we will only visit pb_graph_node of unique pb_type 
+   */
+  for (int ipb = 0; ipb < physical_mode->num_pb_type_children; ++ipb) {
+    rec_print_pnr_sdc_grid_pb_graph_hierarchy(fp,
+                                              module_manager, 
+                                              pb_module,
+                                              device_annotation,
+                                              &(parent_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb][0]));
+  }
+}
+
+
+/***************************************************************************************
+ * Write the hierarchy of grid module and its instances to a plain text file
+ * e.g.,
+ *    <sdc_file_for_the_module>
+ *      <module_name>/<instance_name>
+ *        ...
+ * This file is mainly used by hierarchical P&R flow 
+ *
+ * Return 0 if successful
+ * Return 1 if there are more serious bugs in the architecture 
+ * Return 2 if fail when creating files
+ ***************************************************************************************/
+void print_pnr_sdc_grid_hierarchy(const std::string& sdc_dir,
+                                  const DeviceContext& device_ctx,
+                                  const VprDeviceAnnotation& device_annotation,
+                                  const ModuleManager& module_manager,
+                                  const ModuleId& top_module) {
+
+  std::string fname(sdc_dir + std::string(SDC_GRID_HIERARCHY_FILE_NAME));
+
+  std::string timer_message = std::string("Write Grid hierarchy to plain-text file '") + fname + std::string("'");
+
+  std::string dir_path = format_dir_path(find_path_dir_name(fname));
+
+  /* Create directories */
+  create_directory(dir_path);
+
+  /* Start time count */
+  vtr::ScopedStartFinishTimer timer(timer_message);
+
+  /* Use default name if user does not provide one */
+  VTR_ASSERT(true != fname.empty());
+
+  /* Create a file handler*/
+  std::fstream fp;
+  /* Open a file */
+  fp.open(fname, std::fstream::out | std::fstream::trunc);
+
+  /* Validate the file stream */
+  check_file_stream(fname.c_str(), fp);
+
+  std::string root_path = format_dir_path(module_manager.module_name(top_module));
+
+  for (const t_physical_tile_type& physical_tile : device_ctx.physical_tile_types) {
+    /* Bypass empty type or nullptr */
+    if (true == is_empty_type(&physical_tile)) {
+      continue;
+    }
+
+    VTR_ASSERT(1 == physical_tile.equivalent_sites.size());
+    t_pb_graph_node* pb_graph_head = physical_tile.equivalent_sites[0]->pb_graph_head;
+    if (nullptr == pb_graph_head) {
+      continue;
+    }
+
+    if (true == is_io_type(&physical_tile)) {
+      /* Special for I/O block:
+       * We will search the grids and see where the I/O blocks are located:
+       * - If a I/O block locates on border sides of FPGA fabric:
+       *   i.e., one or more from {TOP, RIGHT, BOTTOM, LEFT},
+       *   we will generate one module for each border side 
+       * - If a I/O block locates in the center of FPGA fabric:
+       *   we will generate one module with NUM_SIDES (same treatment as regular grids) 
+       */
+      std::set<e_side> io_type_sides = find_physical_io_tile_located_sides(device_ctx.grid,
+                                                                           &physical_tile);
+
+
+      /* Generate the grid module name */
+      for (const e_side& io_type_side : io_type_sides) {
+        std::string grid_module_name = generate_grid_block_module_name(std::string(GRID_MODULE_NAME_PREFIX), 
+                                                                       std::string(physical_tile.name),
+                                                                       is_io_type(&physical_tile),
+                                                                       io_type_side);
+        /* Find the module Id */
+        ModuleId grid_module = module_manager.find_module(grid_module_name);
+        VTR_ASSERT(true == module_manager.valid_module_id(grid_module));
+
+        fp << "- " << grid_module_name << "\n";
+
+        /* Go through all the instance */
+        for (const size_t& instance_id : module_manager.child_module_instances(top_module, grid_module)) {
+          std::string grid_instance_name = module_manager.instance_name(top_module, grid_module, instance_id);
+          fp << "  ";
+          fp << "- " << grid_instance_name << "\n";  
+        } 
+
+        fp << "\n";
+
+        rec_print_pnr_sdc_grid_pb_graph_hierarchy(fp,
+                                                  module_manager, 
+                                                  grid_module, 
+                                                  device_annotation,
+                                                  pb_graph_head);
+      }
+    } else {
+      /* For CLB and heterogenenous blocks */
+      std::string grid_module_name = generate_grid_block_module_name(std::string(GRID_MODULE_NAME_PREFIX), 
+                                                                     std::string(physical_tile.name),
+                                                                     is_io_type(&physical_tile),
+                                                                     NUM_SIDES);
+      /* Find the module Id */
+      ModuleId grid_module = module_manager.find_module(grid_module_name);
+      VTR_ASSERT(true == module_manager.valid_module_id(grid_module));
+
+      fp << "- " << grid_module_name << "\n";
+
+      /* Go through all the instance */
+      for (const size_t& instance_id : module_manager.child_module_instances(top_module, grid_module)) {
+        std::string grid_instance_name = module_manager.instance_name(top_module, grid_module, instance_id);
+        fp << "  ";
+        fp << "- " << grid_instance_name << "\n";  
+      } 
+
+      fp << "\n";
+
+      rec_print_pnr_sdc_grid_pb_graph_hierarchy(fp,
+                                                module_manager, 
+                                                grid_module, 
+                                                device_annotation,
+                                                pb_graph_head);
+    }
+  }
+
+  /* close a file */
+  fp.close();
+}
+
+
 } /* end namespace openfpga */
diff --git a/openfpga/src/fpga_sdc/sdc_hierarchy_writer.h b/openfpga/src/fpga_sdc/sdc_hierarchy_writer.h
index 3e7cae5a7..eb4aaf9c0 100644
--- a/openfpga/src/fpga_sdc/sdc_hierarchy_writer.h
+++ b/openfpga/src/fpga_sdc/sdc_hierarchy_writer.h
@@ -25,6 +25,13 @@ void print_pnr_sdc_routing_cb_hierarchy(const std::string& sdc_dir,
                                         const t_rr_type& cb_type,
                                         const DeviceRRGSB& device_rr_gsb);
 
+void print_pnr_sdc_grid_hierarchy(const std::string& sdc_dir,
+                                  const DeviceContext& device_ctx,
+                                  const VprDeviceAnnotation& device_annotation,
+                                  const ModuleManager& module_manager,
+                                  const ModuleId& top_module);
+
+
 } /* end namespace openfpga */
 
 #endif
diff --git a/openfpga/src/fpga_sdc/sdc_writer_naming.h b/openfpga/src/fpga_sdc/sdc_writer_naming.h
index 9783e29f2..17126f98b 100644
--- a/openfpga/src/fpga_sdc/sdc_writer_naming.h
+++ b/openfpga/src/fpga_sdc/sdc_writer_naming.h
@@ -13,6 +13,11 @@ constexpr char* SDC_DISABLE_MUX_OUTPUTS_FILE_NAME = "disable_routing_multiplexer
 constexpr char* SDC_DISABLE_SB_OUTPUTS_FILE_NAME = "disable_sb_outputs.sdc";
 constexpr char* SDC_CB_FILE_NAME = "cb.sdc";
 
+constexpr char* SDC_GRID_HIERARCHY_FILE_NAME = "grid_hierarchy.txt";
+constexpr char* SDC_SB_HIERARCHY_FILE_NAME = "sb_hierarchy.txt";
+constexpr char* SDC_CBX_HIERARCHY_FILE_NAME = "cbx_hierarchy.txt";
+constexpr char* SDC_CBY_HIERARCHY_FILE_NAME = "cby_hierarchy.txt";
+
 constexpr char* SDC_ANALYSIS_FILE_NAME = "fpga_top_analysis.sdc";
 
 } /* end namespace openfpga */

From 55518f4cec765cfab0ed688cfd337f0a2e2efdd1 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 5 May 2020 22:31:11 -0600
Subject: [PATCH 520/645] minor fix in the sdc hierarchy writer for grids

---
 .../src/fpga_sdc/sdc_hierarchy_writer.cpp     | 49 +++++++++++--------
 1 file changed, 28 insertions(+), 21 deletions(-)

diff --git a/openfpga/src/fpga_sdc/sdc_hierarchy_writer.cpp b/openfpga/src/fpga_sdc/sdc_hierarchy_writer.cpp
index 68cbed4b6..3e6b7e8a3 100644
--- a/openfpga/src/fpga_sdc/sdc_hierarchy_writer.cpp
+++ b/openfpga/src/fpga_sdc/sdc_hierarchy_writer.cpp
@@ -183,6 +183,7 @@ void print_pnr_sdc_routing_cb_hierarchy(const std::string& sdc_dir,
  *******************************************************************/
 static 
 void rec_print_pnr_sdc_grid_pb_graph_hierarchy(std::fstream& fp,
+                                               const size_t& depth,
                                                const ModuleManager& module_manager,
                                                const ModuleId& parent_pb_module,
                                                const VprDeviceAnnotation& device_annotation,
@@ -200,26 +201,26 @@ void rec_print_pnr_sdc_grid_pb_graph_hierarchy(std::fstream& fp,
   /* Get the pb_type */
   t_pb_type* parent_pb_type = parent_pb_graph_node->pb_type;
 
-  if (true == is_primitive_pb_type(parent_pb_type)) {
-    return;
-  }
-
   std::string pb_module_name = generate_physical_block_module_name(parent_pb_type);
 
   /* Find the pb module in module manager */
   ModuleId pb_module = module_manager.find_module(pb_module_name);
   VTR_ASSERT(true == module_manager.valid_module_id(pb_module));
 
+  write_space_to_file(fp, depth * 2);
   fp << "- " << pb_module_name << "\n";
 
   /* Go through all the instance */
   for (const size_t& instance_id : module_manager.child_module_instances(parent_pb_module, pb_module)) {
     std::string child_instance_name = module_manager.instance_name(parent_pb_module, pb_module, instance_id);
+    write_space_to_file(fp, depth * 2);
     fp << "  ";
     fp << "- " << child_instance_name << "\n";  
   } 
 
-  fp << "\n";
+  if (true == is_primitive_pb_type(parent_pb_type)) {
+    return;
+  }
 
   /* Note we only go through the graph through the physical modes. 
    * which we build the modules 
@@ -230,11 +231,14 @@ void rec_print_pnr_sdc_grid_pb_graph_hierarchy(std::fstream& fp,
    * Note that we assume a full hierarchical P&R, we will only visit pb_graph_node of unique pb_type 
    */
   for (int ipb = 0; ipb < physical_mode->num_pb_type_children; ++ipb) {
-    rec_print_pnr_sdc_grid_pb_graph_hierarchy(fp,
-                                              module_manager, 
-                                              pb_module,
-                                              device_annotation,
-                                              &(parent_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb][0]));
+    for (int jpb = 0; jpb < physical_mode->pb_type_children[ipb].num_pb; ++jpb) {
+      rec_print_pnr_sdc_grid_pb_graph_hierarchy(fp,
+                                                depth + 2,
+                                                module_manager, 
+                                                pb_module,
+                                                device_annotation,
+                                                &(parent_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb][jpb]));
+    }
   }
 }
 
@@ -324,15 +328,16 @@ void print_pnr_sdc_grid_hierarchy(const std::string& sdc_dir,
           std::string grid_instance_name = module_manager.instance_name(top_module, grid_module, instance_id);
           fp << "  ";
           fp << "- " << grid_instance_name << "\n";  
-        } 
 
+          rec_print_pnr_sdc_grid_pb_graph_hierarchy(fp,
+                                                    2,
+                                                    module_manager, 
+                                                    grid_module, 
+                                                    device_annotation,
+                                                    pb_graph_head);
+        } 
         fp << "\n";
 
-        rec_print_pnr_sdc_grid_pb_graph_hierarchy(fp,
-                                                  module_manager, 
-                                                  grid_module, 
-                                                  device_annotation,
-                                                  pb_graph_head);
       }
     } else {
       /* For CLB and heterogenenous blocks */
@@ -351,15 +356,17 @@ void print_pnr_sdc_grid_hierarchy(const std::string& sdc_dir,
         std::string grid_instance_name = module_manager.instance_name(top_module, grid_module, instance_id);
         fp << "  ";
         fp << "- " << grid_instance_name << "\n";  
+
+        rec_print_pnr_sdc_grid_pb_graph_hierarchy(fp,
+                                                  2,
+                                                  module_manager, 
+                                                  grid_module, 
+                                                  device_annotation,
+                                                  pb_graph_head);
       } 
 
       fp << "\n";
 
-      rec_print_pnr_sdc_grid_pb_graph_hierarchy(fp,
-                                                module_manager, 
-                                                grid_module, 
-                                                device_annotation,
-                                                pb_graph_head);
     }
   }
 

From b167c859801c468634f9a1399026de120a2e3919 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 6 May 2020 11:01:49 -0600
Subject: [PATCH 521/645] fully expand grid hierarchy in SDC writer

---
 .../src/fpga_sdc/sdc_hierarchy_writer.cpp     | 44 +++++++++----------
 1 file changed, 22 insertions(+), 22 deletions(-)

diff --git a/openfpga/src/fpga_sdc/sdc_hierarchy_writer.cpp b/openfpga/src/fpga_sdc/sdc_hierarchy_writer.cpp
index 3e6b7e8a3..f4730b350 100644
--- a/openfpga/src/fpga_sdc/sdc_hierarchy_writer.cpp
+++ b/openfpga/src/fpga_sdc/sdc_hierarchy_writer.cpp
@@ -216,30 +216,30 @@ void rec_print_pnr_sdc_grid_pb_graph_hierarchy(std::fstream& fp,
     write_space_to_file(fp, depth * 2);
     fp << "  ";
     fp << "- " << child_instance_name << "\n";  
-  } 
 
-  if (true == is_primitive_pb_type(parent_pb_type)) {
-    return;
-  }
-
-  /* Note we only go through the graph through the physical modes. 
-   * which we build the modules 
-   */
-  t_mode* physical_mode = device_annotation.physical_mode(parent_pb_type);  
-
-  /* Go recursively to the lower level in the pb_graph
-   * Note that we assume a full hierarchical P&R, we will only visit pb_graph_node of unique pb_type 
-   */
-  for (int ipb = 0; ipb < physical_mode->num_pb_type_children; ++ipb) {
-    for (int jpb = 0; jpb < physical_mode->pb_type_children[ipb].num_pb; ++jpb) {
-      rec_print_pnr_sdc_grid_pb_graph_hierarchy(fp,
-                                                depth + 2,
-                                                module_manager, 
-                                                pb_module,
-                                                device_annotation,
-                                                &(parent_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb][jpb]));
+    if (true == is_primitive_pb_type(parent_pb_type)) {
+      return;
     }
-  }
+
+    /* Note we only go through the graph through the physical modes. 
+     * which we build the modules 
+     */
+    t_mode* physical_mode = device_annotation.physical_mode(parent_pb_type);  
+
+    /* Go recursively to the lower level in the pb_graph
+     * Note that we assume a full hierarchical P&R, we will only visit pb_graph_node of unique pb_type 
+     */
+    for (int ipb = 0; ipb < physical_mode->num_pb_type_children; ++ipb) {
+      for (int jpb = 0; jpb < physical_mode->pb_type_children[ipb].num_pb; ++jpb) {
+        rec_print_pnr_sdc_grid_pb_graph_hierarchy(fp,
+                                                  depth + 2,
+                                                  module_manager, 
+                                                  pb_module,
+                                                  device_annotation,
+                                                  &(parent_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb][jpb]));
+      }
+    }
+  } 
 }
 
 

From cc6d98887281636fdd3cacfb95bb1590632eccc1 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 6 May 2020 14:31:56 -0600
Subject: [PATCH 522/645] bug fix in grid SDC generator

---
 openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp
index 740ba097b..009b834fe 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp
+++ b/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp
@@ -94,7 +94,7 @@ void print_pnr_sdc_constrain_pb_pin_interc_timing(std::fstream& fp,
      * If des module is not the parent module, it is a child module.
      * We should find the instance id 
      */
-    std::string src_instance_name = src_module_name; 
+    std::string src_instance_name; 
     if (parent_module != src_module) {
       src_instance_name = module_manager.module_name(parent_module) + std::string("/"); 
       /* Instance id is actually the placement index */
@@ -124,7 +124,7 @@ void print_pnr_sdc_constrain_pb_pin_interc_timing(std::fstream& fp,
      * If des module is not the parent module, it is a child module.
      * We should find the instance id 
      */
-    std::string des_instance_name = des_module_name; 
+    std::string des_instance_name; 
     if (parent_module != des_module) {
       des_instance_name = module_manager.module_name(parent_module) + std::string("/"); 
       /* Instance id is actually the placement index */
@@ -152,12 +152,18 @@ void print_pnr_sdc_constrain_pb_pin_interc_timing(std::fstream& fp,
     /* Give full path if hierarchical is not enabled */
     std::string src_module_path = src_instance_name;
     if (false == hierarchical) {
+      if (true == src_instance_name.empty()) {
+        src_instance_name = generate_instance_name(src_module_name, 0);
+      }
       src_module_path = module_path + src_instance_name;
     }
 
     std::string des_module_path = des_instance_name;
     if (false == hierarchical) {
-      src_module_path = module_path + des_instance_name;
+      if (true == des_instance_name.empty()) {
+        des_instance_name = generate_instance_name(des_module_name, 0);
+      }
+      des_module_path = module_path + des_instance_name;
     }
 
     /* Print a SDC timing constraint */

From 10e1a4b2fea6a6829c1863fb6843b93721b8f510 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 6 May 2020 14:51:51 -0600
Subject: [PATCH 523/645] format fix in the fabric hierarchy and grid SDC
 hierarchy to be complaint to YAML format

---
 .../src/fabric/fabric_hierarchy_writer.cpp    | 13 +++++++++++--
 .../src/fpga_sdc/sdc_hierarchy_writer.cpp     | 19 +++++++++++--------
 2 files changed, 22 insertions(+), 10 deletions(-)

diff --git a/openfpga/src/fabric/fabric_hierarchy_writer.cpp b/openfpga/src/fabric/fabric_hierarchy_writer.cpp
index 959c1fa5f..a40bfee39 100644
--- a/openfpga/src/fabric/fabric_hierarchy_writer.cpp
+++ b/openfpga/src/fabric/fabric_hierarchy_writer.cpp
@@ -40,7 +40,7 @@ int rec_output_module_hierarchy_to_text_file(std::fstream& fp,
 
   /* Iterate over all the child module */
   for (const ModuleId& child_module : module_manager.child_modules(parent_module)) {
-    if (false == write_space_to_file(fp, current_hie_depth)) {
+    if (false == write_space_to_file(fp, current_hie_depth * 2)) {
       return 2;
     }
 
@@ -51,7 +51,16 @@ int rec_output_module_hierarchy_to_text_file(std::fstream& fp,
       return 1;
     }
 
+    fp << "- ";
     fp << module_manager.module_name(child_module);
+
+    /* If this is the leaf node, we leave a new line 
+     * Otherwise, we will leave a ':' to be compatible to YAML file format 
+     */
+    if ( (0 != module_manager.child_modules(child_module).size())
+      && (hie_depth_to_stop >= current_hie_depth + 1) ) {
+      fp << ":";
+    }
     fp << "\n";
 
     /* Go to next level */
@@ -123,7 +132,7 @@ int write_fabric_hierarchy_to_text_file(const ModuleManager& module_manager,
     return 0;
   }
 
-  fp << top_module_name << "\n";
+  fp << top_module_name << ":" << "\n";
 
   /* Visit child module recursively and output the hierarchy */
   int err_code = rec_output_module_hierarchy_to_text_file(fp,
diff --git a/openfpga/src/fpga_sdc/sdc_hierarchy_writer.cpp b/openfpga/src/fpga_sdc/sdc_hierarchy_writer.cpp
index f4730b350..2c47aec2f 100644
--- a/openfpga/src/fpga_sdc/sdc_hierarchy_writer.cpp
+++ b/openfpga/src/fpga_sdc/sdc_hierarchy_writer.cpp
@@ -79,7 +79,7 @@ void print_pnr_sdc_routing_sb_hierarchy(const std::string& sdc_dir,
     /* Create the file name for SDC */
     std::string sdc_fname(sdc_dir + generate_switch_block_module_name(gsb_coordinate) + std::string(SDC_FILE_NAME_POSTFIX));
 
-    fp << "- " << sb_module_name << "\n";
+    fp << "- " << sb_module_name << ":" << "\n";
 
     /* Go through all the instance */
     for (const size_t& instance_id : module_manager.child_module_instances(top_module, sb_module)) {
@@ -163,7 +163,7 @@ void print_pnr_sdc_routing_cb_hierarchy(const std::string& sdc_dir,
     for (const size_t& instance_id : module_manager.child_module_instances(top_module, cb_module)) {
       std::string cb_instance_name = module_manager.instance_name(top_module, cb_module, instance_id);
       fp << "  ";
-      fp << "- " << cb_instance_name << "\n";  
+      fp << "- " << cb_instance_name << ":" << "\n";  
     } 
 
     fp << "\n";
@@ -208,18 +208,21 @@ void rec_print_pnr_sdc_grid_pb_graph_hierarchy(std::fstream& fp,
   VTR_ASSERT(true == module_manager.valid_module_id(pb_module));
 
   write_space_to_file(fp, depth * 2);
-  fp << "- " << pb_module_name << "\n";
+  fp << "- " << pb_module_name << ":" << "\n";
 
   /* Go through all the instance */
   for (const size_t& instance_id : module_manager.child_module_instances(parent_pb_module, pb_module)) {
     std::string child_instance_name = module_manager.instance_name(parent_pb_module, pb_module, instance_id);
     write_space_to_file(fp, depth * 2);
     fp << "  ";
-    fp << "- " << child_instance_name << "\n";  
+    fp << "- " << child_instance_name;  
 
     if (true == is_primitive_pb_type(parent_pb_type)) {
+      fp << "\n";
       return;
     }
+     
+    fp << ":" << "\n";
 
     /* Note we only go through the graph through the physical modes. 
      * which we build the modules 
@@ -321,13 +324,13 @@ void print_pnr_sdc_grid_hierarchy(const std::string& sdc_dir,
         ModuleId grid_module = module_manager.find_module(grid_module_name);
         VTR_ASSERT(true == module_manager.valid_module_id(grid_module));
 
-        fp << "- " << grid_module_name << "\n";
+        fp << "- " << grid_module_name << ":" << "\n";
 
         /* Go through all the instance */
         for (const size_t& instance_id : module_manager.child_module_instances(top_module, grid_module)) {
           std::string grid_instance_name = module_manager.instance_name(top_module, grid_module, instance_id);
           fp << "  ";
-          fp << "- " << grid_instance_name << "\n";  
+          fp << "- " << grid_instance_name << ":" << "\n";  
 
           rec_print_pnr_sdc_grid_pb_graph_hierarchy(fp,
                                                     2,
@@ -349,13 +352,13 @@ void print_pnr_sdc_grid_hierarchy(const std::string& sdc_dir,
       ModuleId grid_module = module_manager.find_module(grid_module_name);
       VTR_ASSERT(true == module_manager.valid_module_id(grid_module));
 
-      fp << "- " << grid_module_name << "\n";
+      fp << "- " << grid_module_name << ":" << "\n";
 
       /* Go through all the instance */
       for (const size_t& instance_id : module_manager.child_module_instances(top_module, grid_module)) {
         std::string grid_instance_name = module_manager.instance_name(top_module, grid_module, instance_id);
         fp << "  ";
-        fp << "- " << grid_instance_name << "\n";  
+        fp << "- " << grid_instance_name << ":" << "\n";  
 
         rec_print_pnr_sdc_grid_pb_graph_hierarchy(fp,
                                                   2,

From 99fa51cb49d9a7089fd62b3f7018c3a1c187afc5 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 6 May 2020 14:56:04 -0600
Subject: [PATCH 524/645] bug fixed in the SDC CB hierarchy writer

---
 openfpga/src/fpga_sdc/sdc_hierarchy_writer.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/openfpga/src/fpga_sdc/sdc_hierarchy_writer.cpp b/openfpga/src/fpga_sdc/sdc_hierarchy_writer.cpp
index 2c47aec2f..49214aaa3 100644
--- a/openfpga/src/fpga_sdc/sdc_hierarchy_writer.cpp
+++ b/openfpga/src/fpga_sdc/sdc_hierarchy_writer.cpp
@@ -157,13 +157,13 @@ void print_pnr_sdc_routing_cb_hierarchy(const std::string& sdc_dir,
     /* Create the file name for SDC */
     std::string sdc_fname(sdc_dir + generate_connection_block_module_name(cb_type, gsb_coordinate) + std::string(SDC_FILE_NAME_POSTFIX));
 
-    fp << "- " << cb_module_name << "\n";
+    fp << "- " << cb_module_name << ":" << "\n";
 
     /* Go through all the instance */
     for (const size_t& instance_id : module_manager.child_module_instances(top_module, cb_module)) {
       std::string cb_instance_name = module_manager.instance_name(top_module, cb_module, instance_id);
       fp << "  ";
-      fp << "- " << cb_instance_name << ":" << "\n";  
+      fp << "- " << cb_instance_name << "\n";  
     } 
 
     fp << "\n";

From 84d24ad075c9dd0e29e14f025250d4061aead299 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 6 May 2020 15:05:41 -0600
Subject: [PATCH 525/645] bug fix in pnr sdc grid writer for module paths in
 hierarchical view

---
 openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp | 2 --
 openfpga/test_script/and_k6_frac.openfpga     | 1 +
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp
index 009b834fe..26949ec29 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp
+++ b/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp
@@ -96,7 +96,6 @@ void print_pnr_sdc_constrain_pb_pin_interc_timing(std::fstream& fp,
      */
     std::string src_instance_name; 
     if (parent_module != src_module) {
-      src_instance_name = module_manager.module_name(parent_module) + std::string("/"); 
       /* Instance id is actually the placement index */
       size_t instance_id = src_pb_graph_node->placement_index;
       if (true == module_manager.instance_name(parent_module, src_module, instance_id).empty()) {  
@@ -126,7 +125,6 @@ void print_pnr_sdc_constrain_pb_pin_interc_timing(std::fstream& fp,
      */
     std::string des_instance_name; 
     if (parent_module != des_module) {
-      des_instance_name = module_manager.module_name(parent_module) + std::string("/"); 
       /* Instance id is actually the placement index */
       size_t instance_id = des_pb_graph_node->placement_index;
       if (true == module_manager.instance_name(parent_module, des_module, instance_id).empty()) {  
diff --git a/openfpga/test_script/and_k6_frac.openfpga b/openfpga/test_script/and_k6_frac.openfpga
index 014142fb1..90f20b2b7 100644
--- a/openfpga/test_script/and_k6_frac.openfpga
+++ b/openfpga/test_script/and_k6_frac.openfpga
@@ -52,6 +52,7 @@ write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_
 
 # Write the SDC files for PnR backend
 #  - Turn on every options here 
+write_pnr_sdc --hierarchical --file /var/tmp/xtang/openfpga_test_src/SDC_hie
 write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
 
 # Write the SDC to run timing analysis for a mapped FPGA fabric

From b8a79c563d70927b622018cfc6c3788b91db386d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 6 May 2020 16:08:40 -0600
Subject: [PATCH 526/645] bug fix in the SDC port generation

---
 openfpga/src/fpga_sdc/sdc_memory_utils.cpp | 9 +++------
 openfpga/src/fpga_sdc/sdc_writer_utils.cpp | 7 +------
 2 files changed, 4 insertions(+), 12 deletions(-)

diff --git a/openfpga/src/fpga_sdc/sdc_memory_utils.cpp b/openfpga/src/fpga_sdc/sdc_memory_utils.cpp
index 07b7d0804..c9459ebaf 100644
--- a/openfpga/src/fpga_sdc/sdc_memory_utils.cpp
+++ b/openfpga/src/fpga_sdc/sdc_memory_utils.cpp
@@ -100,12 +100,9 @@ void rec_print_pnr_sdc_disable_configurable_memory_module_output(std::fstream& f
 
   /* Disable timing for each output port of this module */
   for (const BasicPort& output_port : module_manager.module_ports_by_type(parent_module, ModuleManager::MODULE_OUTPUT_PORT)) {
-    for (const size_t& pin : output_port.pins()) {
-      BasicPort output_pin(output_port.get_name(), pin, pin);
-      fp << "set_disable_timing ";
-      fp << parent_module_path << generate_sdc_port(output_pin);
-      fp << std::endl;
-    }
+    fp << "set_disable_timing ";
+    fp << parent_module_path << output_port.get_name();
+    fp << std::endl;
   }
 }
 
diff --git a/openfpga/src/fpga_sdc/sdc_writer_utils.cpp b/openfpga/src/fpga_sdc/sdc_writer_utils.cpp
index 0fcf450ad..85ff6edcb 100644
--- a/openfpga/src/fpga_sdc/sdc_writer_utils.cpp
+++ b/openfpga/src/fpga_sdc/sdc_writer_utils.cpp
@@ -71,12 +71,7 @@ std::string generate_sdc_port(const BasicPort& port) {
    *   <port_type>
    */
   if (1 == port.get_width()) {
-    if (0 != port.get_lsb()) {
-      size_str = "[" + std::to_string(port.get_lsb()) + "]";
-    } else {
-      VTR_ASSERT(0 == port.get_lsb());
-      size_str.clear();
-    }
+    size_str = "[" + std::to_string(port.get_lsb()) + "]";
   }
 
   sdc_line = port.get_name() + size_str;

From 05d276097e71d04483fab47c75740ce874067e14 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 6 May 2020 16:20:04 -0600
Subject: [PATCH 527/645] critical bug fixed in openfpga shell so that our
 command parse results should be reset each time before parsing a line

---
 libopenfpga/libopenfpgashell/src/command_context.cpp | 5 +++++
 libopenfpga/libopenfpgashell/src/command_context.h   | 2 ++
 libopenfpga/libopenfpgashell/src/shell.tpp           | 4 ++++
 3 files changed, 11 insertions(+)

diff --git a/libopenfpga/libopenfpgashell/src/command_context.cpp b/libopenfpga/libopenfpgashell/src/command_context.cpp
index ee7c684d6..24593a77b 100644
--- a/libopenfpga/libopenfpgashell/src/command_context.cpp
+++ b/libopenfpga/libopenfpgashell/src/command_context.cpp
@@ -66,4 +66,9 @@ void CommandContext::set_option_value(const Command& command,
   option_values_[option_id] = value;
 }
 
+void CommandContext::reset() {
+  std::fill(option_enabled_.begin(), option_enabled_.end(), false);
+  std::fill(option_values_.begin(), option_values_.end(), std::string());
+}
+
 } /* End namespace openfpga */
diff --git a/libopenfpga/libopenfpgashell/src/command_context.h b/libopenfpga/libopenfpgashell/src/command_context.h
index 2300888cf..5f3fb8856 100644
--- a/libopenfpga/libopenfpgashell/src/command_context.h
+++ b/libopenfpga/libopenfpgashell/src/command_context.h
@@ -43,6 +43,8 @@ class CommandContext {
                     const CommandOptionId& option_id, const bool& status);
     void set_option_value(const Command& command,
                           const CommandOptionId& option_id, const std::string& value);
+    /* Reset the command context to initial state */
+    void reset();
   private: /* Internal data */  
     /* Identify if the option is enabled or not */
     vtr::vector<CommandOptionId, bool> option_enabled_;  
diff --git a/libopenfpga/libopenfpgashell/src/shell.tpp b/libopenfpga/libopenfpgashell/src/shell.tpp
index 05f760e59..b5c506d42 100644
--- a/libopenfpga/libopenfpgashell/src/shell.tpp
+++ b/libopenfpga/libopenfpgashell/src/shell.tpp
@@ -473,6 +473,10 @@ int Shell<T>::execute_command(const char* cmd_line,
     return command_status_[cmd_id];
   }
  
+  /* Reset the command parse results to initial status 
+   * Avoid conflict when calling the same command in the second time 
+   */
+  command_contexts_[cmd_id].reset();
   if (false == parse_command(tokens, commands_[cmd_id], command_contexts_[cmd_id])) {
     /* Echo the command */
     print_command_options(commands_[cmd_id]);

From 8d2360a7101588fc1a923468a7a31746cfa1f21f Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 9 May 2020 19:01:41 -0600
Subject: [PATCH 528/645] simplify include_netlist.v

---
 openfpga/src/base/openfpga_verilog.cpp        |  3 +-
 openfpga/src/fpga_verilog/verilog_api.cpp     |  9 ++--
 openfpga/src/fpga_verilog/verilog_api.h       |  3 +-
 .../verilog_auxiliary_netlists.cpp            | 41 ++-----------------
 .../fpga_verilog/verilog_auxiliary_netlists.h |  6 +--
 5 files changed, 10 insertions(+), 52 deletions(-)

diff --git a/openfpga/src/base/openfpga_verilog.cpp b/openfpga/src/base/openfpga_verilog.cpp
index 9a877c9f2..1d47055df 100644
--- a/openfpga/src/base/openfpga_verilog.cpp
+++ b/openfpga/src/base/openfpga_verilog.cpp
@@ -83,8 +83,7 @@ int write_verilog_testbench(OpenfpgaContext& openfpga_ctx,
   options.set_print_simulation_ini(cmd_context.option_value(cmd, opt_print_simulation_ini));
   options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
   
-  fpga_verilog_testbench(openfpga_ctx.verilog_netlists(),
-                         openfpga_ctx.module_graph(),
+  fpga_verilog_testbench(openfpga_ctx.module_graph(),
                          openfpga_ctx.bitstream_manager(),
                          openfpga_ctx.fabric_bitstream(),
                          g_vpr_ctx.atom(),
diff --git a/openfpga/src/fpga_verilog/verilog_api.cpp b/openfpga/src/fpga_verilog/verilog_api.cpp
index 2c2ea4e93..7f82507f5 100644
--- a/openfpga/src/fpga_verilog/verilog_api.cpp
+++ b/openfpga/src/fpga_verilog/verilog_api.cpp
@@ -144,8 +144,7 @@ void fpga_fabric_verilog(ModuleManager& module_manager,
  *    This testbench is created for quick verification and formal verification purpose.
  *  - Verilog netlist including preprocessing flags and all the Verilog netlists that have been generated
  ********************************************************************/
-void fpga_verilog_testbench(const NetlistManager& netlist_manager,
-                            const ModuleManager& module_manager,
+void fpga_verilog_testbench(const ModuleManager& module_manager,
                             const BitstreamManager& bitstream_manager, 
                             const std::vector<ConfigBitId>& fabric_bitstream, 
                             const AtomContext& atom_ctx, 
@@ -227,11 +226,9 @@ void fpga_verilog_testbench(const NetlistManager& netlist_manager,
   }
 
   /* Generate a Verilog file including all the netlists that have been generated */
-  print_include_netlists(netlist_manager,
-                         src_dir_path,
+  print_include_netlists(src_dir_path,
                          netlist_name,
-                         options.reference_benchmark_file_path(),
-                         circuit_lib);
+                         options.reference_benchmark_file_path());
 
 }
 
diff --git a/openfpga/src/fpga_verilog/verilog_api.h b/openfpga/src/fpga_verilog/verilog_api.h
index c9d194dff..301e68b3e 100644
--- a/openfpga/src/fpga_verilog/verilog_api.h
+++ b/openfpga/src/fpga_verilog/verilog_api.h
@@ -37,8 +37,7 @@ void fpga_fabric_verilog(ModuleManager& module_manager,
                          const DeviceRRGSB& device_rr_gsb,
                          const FabricVerilogOption& options);
 
-void fpga_verilog_testbench(const NetlistManager& netlist_manager,
-                            const ModuleManager& module_manager,
+void fpga_verilog_testbench(const ModuleManager& module_manager,
                             const BitstreamManager& bitstream_manager, 
                             const std::vector<ConfigBitId>& fabric_bitstream, 
                             const AtomContext& atom_ctx, 
diff --git a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
index b69868d17..65e0d1ca2 100644
--- a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
+++ b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
@@ -94,11 +94,9 @@ void print_fabric_include_netlist(const NetlistManager& netlist_manager,
  * that have been generated and user-defined.
  * Some netlists are open to compile under specific preprocessing flags
  *******************************************************************/
-void print_include_netlists(const NetlistManager& netlist_manager,
-                            const std::string& src_dir,
+void print_include_netlists(const std::string& src_dir,
                             const std::string& circuit_name,
-                            const std::string& reference_benchmark_file,
-                            const CircuitLibrary& circuit_lib) {
+                            const std::string& reference_benchmark_file) {
   std::string verilog_fname = src_dir + circuit_name + std::string(TOP_INCLUDE_NETLIST_FILE_NAME_POSTFIX);
 
   /* Create the file stream */
@@ -112,46 +110,13 @@ void print_include_netlists(const NetlistManager& netlist_manager,
   print_verilog_file_header(fp, std::string("Netlist Summary")); 
 
   /* Print preprocessing flags */
-  print_verilog_comment(fp, std::string("------ Include defines: preproc flags -----"));
-  print_verilog_include_netlist(fp, std::string(src_dir + std::string(DEFINES_VERILOG_FILE_NAME)));
-  fp << std::endl;
-
   print_verilog_comment(fp, std::string("------ Include simulation defines -----"));
   print_verilog_include_netlist(fp, src_dir + std::string(DEFINES_VERILOG_SIMULATION_FILE_NAME));
   fp << std::endl;
 
-  /* Include all the user-defined netlists */
-  print_verilog_comment(fp, std::string("------ Include user-defined netlists -----"));
-  for (const std::string& user_defined_netlist : find_circuit_library_unique_verilog_netlists(circuit_lib)) {
-    print_verilog_include_netlist(fp, user_defined_netlist);
-  }
-
-  /* Include all the primitive modules */
-  print_verilog_comment(fp, std::string("------ Include primitive module netlists -----"));
-  for (const NetlistId& nlist_id : netlist_manager.netlists_by_type(NetlistManager::SUBMODULE_NETLIST)) {
-    print_verilog_include_netlist(fp, netlist_manager.netlist_name(nlist_id));
-  }
-  fp << std::endl;
-
-  /* Include all the CLB, heterogeneous block modules */
-  print_verilog_comment(fp, std::string("------ Include logic block netlists -----"));
-  for (const NetlistId& nlist_id : netlist_manager.netlists_by_type(NetlistManager::LOGIC_BLOCK_NETLIST)) {
-    print_verilog_include_netlist(fp, netlist_manager.netlist_name(nlist_id));
-  }
-  fp << std::endl;
-
-  /* Include all the routing architecture modules */
-  print_verilog_comment(fp, std::string("------ Include routing module netlists -----"));
-  for (const NetlistId& nlist_id : netlist_manager.netlists_by_type(NetlistManager::ROUTING_MODULE_NETLIST)) {
-    print_verilog_include_netlist(fp, netlist_manager.netlist_name(nlist_id));
-  }
-  fp << std::endl;
-
   /* Include FPGA top module */
   print_verilog_comment(fp, std::string("------ Include fabric top-level netlists -----"));
-  for (const NetlistId& nlist_id : netlist_manager.netlists_by_type(NetlistManager::TOP_MODULE_NETLIST)) {
-    print_verilog_include_netlist(fp, netlist_manager.netlist_name(nlist_id));
-  }
+  print_verilog_include_netlist(fp, src_dir + std::string(FABRIC_INCLUDE_NETLIST_FILE_NAME));
   fp << std::endl;
 
   /* Include reference benchmark netlist only when auto-check flag is enabled */
diff --git a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h
index 52292881a..57f04032f 100644
--- a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h
+++ b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h
@@ -21,11 +21,9 @@ void print_fabric_include_netlist(const NetlistManager& netlist_manager,
                                   const std::string& src_dir,
                                   const CircuitLibrary& circuit_lib);
 
-void print_include_netlists(const NetlistManager& netlist_manager,
-                            const std::string& src_dir,
+void print_include_netlists(const std::string& src_dir,
                             const std::string& circuit_name,
-                            const std::string& reference_benchmark_file,
-                            const CircuitLibrary& circuit_lib);
+                            const std::string& reference_benchmark_file);
 
 void print_verilog_preprocessing_flags_netlist(const std::string& src_dir,
                                                const FabricVerilogOption& fabric_verilog_opts);

From dad99d13a20a64eb660cf2609d0bda85339d96d1 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 11 May 2020 14:52:55 -0600
Subject: [PATCH 529/645] bug fixed in SDC timing writer for primitive pb_type

---
 openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp | 38 +++++++++----------
 1 file changed, 19 insertions(+), 19 deletions(-)

diff --git a/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp
index 26949ec29..b56f8acf0 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp
+++ b/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp
@@ -397,34 +397,34 @@ void print_pnr_sdc_constrain_primitive_pb_graph_node(const std::string& sdc_dir,
   print_sdc_timescale(fp, time_unit_to_string(time_unit));
 
   /* We traverse the pb_graph pins where we can find pin-to-pin timing annotation
-   * We walk through output pins here, build timing constraints by pair each output to input
+   * We walk through input pins here, build timing constraints by pair each input to output
+   * Because VPR keeps all the timing values in pin_timing data structure instead of pb_graph_pin edges
    * Clock pins are not walked through because they will be handled by clock tree synthesis
    */
-  for (int iport = 0; iport < logical_primitive_pb_graph_node->num_output_ports; ++iport) {
-    for (int ipin = 0; ipin < logical_primitive_pb_graph_node->num_output_pins[iport]; ++ipin) {
-       t_pb_graph_pin* sink_pin = &(logical_primitive_pb_graph_node->output_pins[iport][ipin]);
+  for (int iport = 0; iport < logical_primitive_pb_graph_node->num_input_ports; ++iport) {
+    for (int ipin = 0; ipin < logical_primitive_pb_graph_node->num_input_pins[iport]; ++ipin) {
+       t_pb_graph_pin* src_pin = &(logical_primitive_pb_graph_node->input_pins[iport][ipin]);
 
        /* Port must exist in the module graph */
-       ModulePortId sink_module_port_id = module_manager.find_module_port(pb_module, generate_pb_type_port_name(physical_pb_type, sink_pin->port));
-       VTR_ASSERT(true == module_manager.valid_module_port_id(pb_module, sink_module_port_id));
-       BasicPort sink_port = module_manager.module_port(pb_module, sink_module_port_id);
+       ModulePortId src_module_port_id = module_manager.find_module_port(pb_module, generate_pb_type_port_name(physical_pb_type, src_pin->port));
+       VTR_ASSERT(true == module_manager.valid_module_port_id(pb_module, src_module_port_id));
+       BasicPort src_port = module_manager.module_port(pb_module, src_module_port_id);
        /* Set the correct pin number of the port */
-       sink_port.set_width(sink_pin->pin_number, sink_pin->pin_number);
+       src_port.set_width(src_pin->pin_number, src_pin->pin_number);
 
        /* Find all the sink pin from this source pb_graph_pin */
-       for (int iedge = 0; iedge < sink_pin->num_input_edges; ++iedge) {
-         VTR_ASSERT(1 == sink_pin->input_edges[iedge]->num_input_pins);
-         t_pb_graph_pin* src_pin = sink_pin->input_edges[iedge]->input_pins[0];
+       for (int itiming = 0; itiming < src_pin->num_pin_timing; ++itiming) { 
+         t_pb_graph_pin* sink_pin = src_pin->pin_timing[itiming];
 
          /* Port must exist in the module graph */
-         ModulePortId src_module_port_id = module_manager.find_module_port(pb_module, generate_pb_type_port_name(physical_pb_type, src_pin->port));
-         VTR_ASSERT(true == module_manager.valid_module_port_id(pb_module, src_module_port_id));
-         BasicPort src_port = module_manager.module_port(pb_module, src_module_port_id);
+         ModulePortId sink_module_port_id = module_manager.find_module_port(pb_module, generate_pb_type_port_name(physical_pb_type, sink_pin->port));
+         VTR_ASSERT(true == module_manager.valid_module_port_id(pb_module, sink_module_port_id));
+         BasicPort sink_port = module_manager.module_port(pb_module, sink_module_port_id);
          /* Set the correct pin number of the port */
-         src_port.set_width(src_pin->pin_number, src_pin->pin_number);
+         sink_port.set_width(sink_pin->pin_number, sink_pin->pin_number);
 
          /* Find max delay between src and sink pin */
-         float tmax = sink_pin->input_edges[iedge]->delay_max;
+         float tmax = src_pin->pin_timing_del_max[itiming];
 
          /* Generate module path in hierarchy depending if the hierarchical is enabled */
          std::string module_hie_path = pb_module_name;
@@ -434,7 +434,7 @@ void print_pnr_sdc_constrain_primitive_pb_graph_node(const std::string& sdc_dir,
 
          /* If the delay is zero, constrain only when user wants it */
          if ( (true == constrain_zero_delay_paths)
-           || (0. == tmax) ) {
+           || (0. != tmax) ) {
            print_pnr_sdc_constrain_max_delay(fp, 
                                              module_hie_path, 
                                              generate_sdc_port(src_port),
@@ -444,10 +444,10 @@ void print_pnr_sdc_constrain_primitive_pb_graph_node(const std::string& sdc_dir,
          }
 
          /* Find min delay between src and sink pin */
-         float tmin = sink_pin->input_edges[iedge]->delay_min;
+         float tmin = src_pin->pin_timing_del_min[itiming];
          /* If the delay is zero, constrain only when user wants it */
          if ( (true == constrain_zero_delay_paths)
-           || (0. == tmin) ) {
+           || (0. != tmin) ) {
            print_pnr_sdc_constrain_min_delay(fp, 
                                              module_hie_path, 
                                              generate_sdc_port(src_port),

From 4c0953415b87984e969a9a1d4161fc89b3721dc7 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 12 May 2020 20:44:53 -0600
Subject: [PATCH 530/645] add configuration chain sdc writer

---
 openfpga/src/base/openfpga_sdc.cpp            |  36 ++++
 openfpga/src/base/openfpga_sdc.h              |   3 +
 openfpga/src/base/openfpga_sdc_command.cpp    |  49 +++++
 .../configuration_chain_sdc_writer.cpp        | 175 ++++++++++++++++++
 .../fpga_sdc/configuration_chain_sdc_writer.h |  26 +++
 openfpga/src/fpga_sdc/sdc_writer_utils.cpp    |  12 +-
 6 files changed, 295 insertions(+), 6 deletions(-)
 create mode 100644 openfpga/src/fpga_sdc/configuration_chain_sdc_writer.cpp
 create mode 100644 openfpga/src/fpga_sdc/configuration_chain_sdc_writer.h

diff --git a/openfpga/src/base/openfpga_sdc.cpp b/openfpga/src/base/openfpga_sdc.cpp
index d492e653a..93bd46959 100644
--- a/openfpga/src/base/openfpga_sdc.cpp
+++ b/openfpga/src/base/openfpga_sdc.cpp
@@ -15,6 +15,7 @@
 #include "circuit_library_utils.h"
 #include "pnr_sdc_writer.h"
 #include "analysis_sdc_writer.h"
+#include "configuration_chain_sdc_writer.h"
 #include "openfpga_sdc.h"
 
 /* Include global variables of VPR */
@@ -102,6 +103,41 @@ int write_pnr_sdc(OpenfpgaContext& openfpga_ctx,
   return CMD_EXEC_SUCCESS;
 } 
 
+/********************************************************************
+ * A wrapper function to call the PnR SDC generator on configuration chain 
+ * of FPGA-SDC
+ *******************************************************************/
+int write_configuration_chain_sdc(const OpenfpgaContext& openfpga_ctx,
+                                  const Command& cmd, const CommandContext& cmd_context) {
+  /* If the configuration protocol is not a configuration chain, we will not write anything */
+  if (CONFIG_MEM_SCAN_CHAIN != openfpga_ctx.arch().config_protocol.type()) {
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Configuration protocol is %s. Expected %s to write SDC!\n",
+                   CONFIG_PROTOCOL_TYPE_STRING[openfpga_ctx.arch().config_protocol.type()],
+                   CONFIG_PROTOCOL_TYPE_STRING[CONFIG_MEM_SCAN_CHAIN]);
+    return CMD_EXEC_FATAL_ERROR;
+  }
+
+  /* Get command options */
+  CommandOptionId opt_output_dir = cmd.option("file");
+  CommandOptionId opt_time_unit = cmd.option("time_unit");
+  CommandOptionId opt_min_delay = cmd.option("min_delay");
+  CommandOptionId opt_max_delay = cmd.option("max_delay");
+
+  std::string sdc_dir_path = format_dir_path(cmd_context.option_value(cmd, opt_output_dir));
+
+  float time_unit = string_to_time_unit(cmd_context.option_value(cmd, opt_time_unit));
+
+  /* Write the SDC for configuration chain */
+  print_pnr_sdc_constrain_configurable_chain(cmd_context.option_value(cmd, opt_output_dir),
+                                             time_unit,
+                                             std::stof(cmd_context.option_value(cmd, opt_max_delay)),
+                                             std::stof(cmd_context.option_value(cmd, opt_min_delay)),
+                                             openfpga_ctx.module_graph());
+
+  return CMD_EXEC_SUCCESS;
+}
+
 /********************************************************************
  * A wrapper function to call the analysis SDC generator of FPGA-SDC
  *******************************************************************/
diff --git a/openfpga/src/base/openfpga_sdc.h b/openfpga/src/base/openfpga_sdc.h
index 99a87f899..060c304bc 100644
--- a/openfpga/src/base/openfpga_sdc.h
+++ b/openfpga/src/base/openfpga_sdc.h
@@ -18,6 +18,9 @@ namespace openfpga {
 int write_pnr_sdc(OpenfpgaContext& openfpga_ctx,
                   const Command& cmd, const CommandContext& cmd_context); 
 
+int write_configuration_chain_sdc(const OpenfpgaContext& openfpga_ctx,
+                                  const Command& cmd, const CommandContext& cmd_context);
+
 int write_analysis_sdc(OpenfpgaContext& openfpga_ctx,
                        const Command& cmd, const CommandContext& cmd_context);
 
diff --git a/openfpga/src/base/openfpga_sdc_command.cpp b/openfpga/src/base/openfpga_sdc_command.cpp
index a0f578786..faa488931 100644
--- a/openfpga/src/base/openfpga_sdc_command.cpp
+++ b/openfpga/src/base/openfpga_sdc_command.cpp
@@ -80,6 +80,45 @@ ShellCommandId add_openfpga_write_pnr_sdc_command(openfpga::Shell<OpenfpgaContex
   return shell_cmd_id;
 }
 
+/********************************************************************
+ * - Add a command to Shell environment: generate PnR SDC for configuration chain 
+ * - Add associated options 
+ * - Add command dependency
+ *******************************************************************/
+static 
+ShellCommandId add_openfpga_write_configuration_chain_sdc_command(openfpga::Shell<OpenfpgaContext>& shell,
+                                                                  const ShellCommandClassId& cmd_class_id,
+                                                                  const std::vector<ShellCommandId>& dependent_cmds) {
+  Command shell_cmd("write_configuration_chain_sdc");
+
+  /* Add an option '--file' in short '-f'*/
+  CommandOptionId output_opt = shell_cmd.add_option("file", true, "Specify the SDC file to constrain configuration chain");
+  shell_cmd.set_option_short_name(output_opt, "f");
+  shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING);
+
+  /* Add an option '--time_unit' */
+  CommandOptionId time_unit_opt = shell_cmd.add_option("time_unit", false, "Specify the time unit in SDC files. Acceptable is [a|f|p|n|u|m|k|M]s");
+  shell_cmd.set_option_require_value(time_unit_opt, openfpga::OPT_STRING);
+
+  /* Add an option '--min_delay' */
+  CommandOptionId min_dly_opt = shell_cmd.add_option("min_delay", false, "Specify the minimum delay to be used.");
+  shell_cmd.set_option_require_value(min_dly_opt, openfpga::OPT_STRING);
+
+  /* Add an option '--max_delay' */
+  CommandOptionId max_dly_opt = shell_cmd.add_option("max_delay", false, "Specify the maximum delay to be used.");
+  shell_cmd.set_option_require_value(max_dly_opt, openfpga::OPT_STRING);
+
+  /* Add command 'write_configuration_chain_sdc' to the Shell */
+  ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "generate SDC files to constrain the configuration chain for FPGA fabric");
+  shell.set_command_class(shell_cmd_id, cmd_class_id);
+  shell.set_command_const_execute_function(shell_cmd_id, write_configuration_chain_sdc);
+
+  /* Add command dependency to the Shell */
+  shell.set_command_dependency(shell_cmd_id, dependent_cmds);
+
+  return shell_cmd_id;
+}
+
 /********************************************************************
  * - Add a command to Shell environment: generate PnR SDC 
  * - Add associated options 
@@ -134,6 +173,16 @@ void add_openfpga_sdc_commands(openfpga::Shell<OpenfpgaContext>& shell) {
                                      openfpga_sdc_cmd_class,
                                      pnr_sdc_cmd_dependency);
 
+  /******************************** 
+   * Command 'write_configuration_chain_sdc' 
+   */
+  /* The 'write_configuration_chain_sdc' command should NOT be executed before 'build_fabric' */
+  std::vector<ShellCommandId> cc_sdc_cmd_dependency;
+  cc_sdc_cmd_dependency.push_back(build_fabric_id);
+  add_openfpga_write_configuration_chain_sdc_command(shell,
+                                                     openfpga_sdc_cmd_class,
+                                                     cc_sdc_cmd_dependency);
+
   /******************************** 
    * Command 'write_analysis_sdc' 
    */
diff --git a/openfpga/src/fpga_sdc/configuration_chain_sdc_writer.cpp b/openfpga/src/fpga_sdc/configuration_chain_sdc_writer.cpp
new file mode 100644
index 000000000..ce41e6851
--- /dev/null
+++ b/openfpga/src/fpga_sdc/configuration_chain_sdc_writer.cpp
@@ -0,0 +1,175 @@
+/********************************************************************
+ * This file includes functions that print SDC (Synopsys Design Constraint) 
+ * files in physical design tools, i.e., Place & Route (PnR) tools
+ * The SDC files are used to constrain the timing of configuration chain 
+ *
+ * Note that this is different from the SDC to constrain VPR Place&Route
+ * engine! These SDCs are designed for PnR to generate FPGA layouts!!!
+ *******************************************************************/
+#include <ctime>
+#include <fstream>
+#include <iomanip>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_time.h"
+#include "vtr_log.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_scale.h"
+#include "openfpga_port.h"
+#include "openfpga_digest.h"
+
+#include "openfpga_naming.h"
+
+#include "sdc_writer_utils.h"
+#include "configuration_chain_sdc_writer.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Print SDC commands to constrain the timing between outputs and inputs
+ * of all the configurable memory modules
+ *   
+ *           |<------Max/Min delay-->|
+ *           |                       | 
+ *    +------+ out               in  +------+
+ *    | CCFF |---------------------->| CCFF |
+ *    +------+                       +------+
+ *
+ * This function will be executed in a recursive way, 
+ * using a Depth-First Search (DFS) strategy
+ * It will iterate over all the configurable children under each module
+ * and print a SDC command
+ *
+ *******************************************************************/
+static 
+void rec_print_pnr_sdc_constrain_configurable_chain(std::fstream& fp, 
+                                                    const float& tmax,
+                                                    const float& tmin,
+                                                    const ModuleManager& module_manager, 
+                                                    const ModuleId& parent_module,
+                                                    const std::string& parent_module_path,
+                                                    std::string& previous_module_path,
+                                                    ModuleId& previous_module) {
+
+  /* For each configurable child, we will go one level down in priority */
+  for (size_t child_index = 0; child_index < module_manager.configurable_children(parent_module).size(); ++child_index) {
+    std::string child_module_path = parent_module_path;
+    ModuleId child_module_id = module_manager.configurable_children(parent_module)[child_index];
+    size_t child_instance_id = module_manager.configurable_child_instances(parent_module)[child_index];
+    std::string child_instance_name;
+    if (true == module_manager.instance_name(parent_module, child_module_id, child_instance_id).empty()) {
+      child_instance_name = generate_instance_name(module_manager.module_name(child_module_id), child_instance_id);
+    } else {
+      child_instance_name = module_manager.instance_name(parent_module, child_module_id, child_instance_id);
+    }
+
+    child_module_path += child_instance_name;
+    
+    child_module_path = format_dir_path(child_module_path);
+
+    rec_print_pnr_sdc_constrain_configurable_chain(fp,
+                                                   tmax, tmin,
+                                                   module_manager, 
+                                                   child_module_id, 
+                                                   child_module_path,
+                                                   previous_module_path,
+                                                   previous_module);
+  }
+
+  /* If there is no configurable children any more, this is a leaf module, print a SDC command for disable timing */
+  if (0 < module_manager.configurable_children(parent_module).size()) {
+    return;
+  }
+
+  /* Validate file stream */
+  valid_file_stream(fp);
+
+  /* Disable timing for each output port of this module */
+  if (!previous_module_path.empty()) {
+    bool first_port = true;
+    for (const BasicPort& output_port : module_manager.module_ports_by_type(previous_module, ModuleManager::MODULE_OUTPUT_PORT)) {
+      /* Only the first output port will be considered,
+       * being consistent with build_memory_module.cpp:395
+       */
+      if (false == first_port) {
+        continue;
+      }
+
+      for (const BasicPort& input_port : module_manager.module_ports_by_type(parent_module, ModuleManager::MODULE_INPUT_PORT)) {
+        print_pnr_sdc_constrain_max_delay(fp, 
+                                          previous_module_path, 
+                                          generate_sdc_port(output_port),
+                                          parent_module_path, 
+                                          generate_sdc_port(input_port),
+                                          tmax);
+
+        print_pnr_sdc_constrain_min_delay(fp, 
+                                          previous_module_path, 
+                                          generate_sdc_port(output_port),
+                                          parent_module_path, 
+                                          generate_sdc_port(input_port),
+                                          tmin);
+      }
+      
+      first_port = false;
+    }
+  }
+
+  /* Update previous module */
+  previous_module_path = parent_module_path;
+  previous_module = parent_module;
+}
+
+
+/********************************************************************
+ * Break combinational loops in FPGA fabric, which mainly come from
+ * configurable memory cells. 
+ * To handle this, we disable the outputs of memory cells
+ *******************************************************************/
+void print_pnr_sdc_constrain_configurable_chain(const std::string& sdc_fname,
+                                                const float& time_unit,
+                                                const float& max_delay,
+                                                const float& min_delay,
+                                                const ModuleManager& module_manager) {
+
+  /* Create the directory */
+  create_directory(find_path_dir_name(sdc_fname));
+
+  /* Start time count */
+  std::string timer_message = std::string("Write SDC to constrain configurable chain for P&R flow '") + sdc_fname + std::string("'");
+  vtr::ScopedStartFinishTimer timer(timer_message);
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(sdc_fname, std::fstream::out | std::fstream::trunc);
+
+  check_file_stream(sdc_fname.c_str(), fp);
+
+  /* Generate the descriptions*/
+  print_sdc_file_header(fp, std::string("Timing constraints for configurable chains used in PnR"));
+
+  /* Print time unit for the SDC file */
+  print_sdc_timescale(fp, time_unit_to_string(time_unit));
+
+  std::string top_module_name = generate_fpga_top_module_name();
+  ModuleId top_module = module_manager.find_module(top_module_name);
+  VTR_ASSERT(true == module_manager.valid_module_id(top_module));
+
+  /* Go recursively in the module manager, starting from the top-level module: instance id of the top-level module is 0 by default */
+  std::string previous_module_path;
+  ModuleId previous_module = ModuleId::INVALID();
+  rec_print_pnr_sdc_constrain_configurable_chain(fp,
+                                                 max_delay/time_unit, min_delay/time_unit, 
+                                                 module_manager, top_module, 
+                                                 format_dir_path(module_manager.module_name(top_module)),
+                                                 previous_module_path,
+                                                 previous_module);
+
+  /* Close file handler */
+  fp.close();
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_sdc/configuration_chain_sdc_writer.h b/openfpga/src/fpga_sdc/configuration_chain_sdc_writer.h
new file mode 100644
index 000000000..1e636c8a9
--- /dev/null
+++ b/openfpga/src/fpga_sdc/configuration_chain_sdc_writer.h
@@ -0,0 +1,26 @@
+#ifndef CONFIGURATION_CHAIN_SDC_WRITER_H
+#define CONFIGURATION_CHAIN_SDC_WRITER_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <string>
+#include <vector>
+#include "module_manager.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void print_pnr_sdc_constrain_configurable_chain(const std::string& sdc_fname,
+                                                const float& time_unit,
+                                                const float& max_delay,
+                                                const float& min_delay,
+                                                const ModuleManager& module_manager);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/fpga_sdc/sdc_writer_utils.cpp b/openfpga/src/fpga_sdc/sdc_writer_utils.cpp
index 85ff6edcb..93a3a94aa 100644
--- a/openfpga/src/fpga_sdc/sdc_writer_utils.cpp
+++ b/openfpga/src/fpga_sdc/sdc_writer_utils.cpp
@@ -95,14 +95,14 @@ void print_pnr_sdc_constrain_max_delay(std::fstream& fp,
 
   fp << " -from ";
   if (!src_instance_name.empty()) {
-    fp << src_instance_name << "/";
+    fp << format_dir_path(src_instance_name);
   }
   fp << src_port_name;
 
   fp << " -to ";
  
   if (!des_instance_name.empty()) {
-    fp << des_instance_name << "/";
+    fp << format_dir_path(des_instance_name);
   }
   fp << des_port_name;
 
@@ -130,7 +130,7 @@ void print_pnr_sdc_regexp_constrain_max_delay(std::fstream& fp,
   fp << " -from ";
   fp << "[get_pins -regexp \"";
   if (!src_instance_name.empty()) {
-    fp << src_instance_name << "/";
+    fp << format_dir_path(src_instance_name);
   }
   fp << src_port_name;
 
@@ -140,7 +140,7 @@ void print_pnr_sdc_regexp_constrain_max_delay(std::fstream& fp,
   fp << "[get_pins -regexp \"";
  
   if (!des_instance_name.empty()) {
-    fp << des_instance_name << "/";
+    fp << format_dir_path(des_instance_name);
   }
   fp << des_port_name;
 
@@ -167,14 +167,14 @@ void print_pnr_sdc_constrain_min_delay(std::fstream& fp,
 
   fp << " -from ";
   if (!src_instance_name.empty()) {
-    fp << src_instance_name << "/";
+    fp << format_dir_path(src_instance_name);
   }
   fp << src_port_name;
 
   fp << " -to ";
  
   if (!des_instance_name.empty()) {
-    fp << des_instance_name << "/";
+    fp << format_dir_path(des_instance_name);
   }
   fp << des_port_name;
 

From fc2b09514eb8a6546419b6e0905892de90111abd Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 12 May 2020 20:51:16 -0600
Subject: [PATCH 531/645] add configuration chain write to regression tests

---
 ...onfiguration_chain_example_script.openfpga | 68 +++++++++++++++++++
 .../configuration_chain/config/task.conf      |  2 +-
 2 files changed, 69 insertions(+), 1 deletion(-)
 create mode 100644 openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga

diff --git a/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga
new file mode 100644
index 000000000..326bdba6a
--- /dev/null
+++ b/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga
@@ -0,0 +1,68 @@
+# Run VPR for the 'and' design
+#--write_rr_graph example_rr_graph.xml
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
+
+# Annotate the OpenFPGA architecture to VPR data base
+# to debug use --verbose options
+link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to clustering nets based on routing results
+pb_pin_fixup --verbose
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup
+
+# Build the module graph
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules
+build_fabric --compress_routing #--verbose
+
+# Write the fabric hierarchy of module graph to a file
+# This is used by hierarchical PnR flows
+write_fabric_hierarchy --file ./fabric_hierarchy.txt
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --file fabric_indepenent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here
+write_pnr_sdc --file ./SDC
+
+# Write SDC to constrain timing of configuration chain
+write_configuration_chain_sdc --file ./SDC/ccff_timing.sdc --time_unit ns --max_delay 5 --min_delay 2.5
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+write_analysis_sdc --file ./SDC_analysis
+
+# Finish and exit OpenFPGA
+exit
+
+# Note :
+# To run verification at the end of the flow maintain source in ./SRC directory
diff --git a/openfpga_flow/tasks/openfpga_shell/configuration_chain/config/task.conf b/openfpga_flow/tasks/openfpga_shell/configuration_chain/config/task.conf
index 79781a758..9e18efc65 100644
--- a/openfpga_flow/tasks/openfpga_shell/configuration_chain/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/configuration_chain/config/task.conf
@@ -8,7 +8,7 @@
 
 [GENERAL]
 run_engine=openfpga_shell
-openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga
 power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
 power_analysis = true
 spice_output=false

From 02e86c565ac0051b47db452e78f9d09cfbf83247 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 12 May 2020 20:53:17 -0600
Subject: [PATCH 532/645] bug fix in configuration chain SDC writer

---
 openfpga/src/fpga_sdc/configuration_chain_sdc_writer.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/openfpga/src/fpga_sdc/configuration_chain_sdc_writer.cpp b/openfpga/src/fpga_sdc/configuration_chain_sdc_writer.cpp
index ce41e6851..5372741bb 100644
--- a/openfpga/src/fpga_sdc/configuration_chain_sdc_writer.cpp
+++ b/openfpga/src/fpga_sdc/configuration_chain_sdc_writer.cpp
@@ -162,7 +162,7 @@ void print_pnr_sdc_constrain_configurable_chain(const std::string& sdc_fname,
   std::string previous_module_path;
   ModuleId previous_module = ModuleId::INVALID();
   rec_print_pnr_sdc_constrain_configurable_chain(fp,
-                                                 max_delay/time_unit, min_delay/time_unit, 
+                                                 max_delay, min_delay, 
                                                  module_manager, top_module, 
                                                  format_dir_path(module_manager.module_name(top_module)),
                                                  previous_module_path,

From a41c8dbcb3eff7497cb388a5f87c9098e8d6c11d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 12 May 2020 20:54:11 -0600
Subject: [PATCH 533/645] change to use default sphinx build version

---
 docs/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/Makefile b/docs/Makefile
index 6f26ca799..1f299ec6b 100644
--- a/docs/Makefile
+++ b/docs/Makefile
@@ -3,7 +3,7 @@
 
 # You can set these variables from the command line.
 SPHINXOPTS    =
-SPHINXBUILD   = sphinx-build-3.6
+SPHINXBUILD   = sphinx-build
 SOURCEDIR     = source
 BUILDDIR      = build
 

From df9cf32b4969a1b3eb918b041e5144a95b583512 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 12 May 2020 20:59:55 -0600
Subject: [PATCH 534/645] update documenation for configuration chain writer

---
 .../source/openfpga_shell/openfpga_commands.rst | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/docs/source/openfpga_shell/openfpga_commands.rst b/docs/source/openfpga_shell/openfpga_commands.rst
index 5cd5a8c33..c07b7a71c 100644
--- a/docs/source/openfpga_shell/openfpga_commands.rst
+++ b/docs/source/openfpga_shell/openfpga_commands.rst
@@ -221,6 +221,23 @@ FPGA-SDC
   
   - ``--verbose`` Enable verbose output
 
+.. option:: write_configuration_chain_sdc
+ 
+  Write the SDC file to constrain the timing for configuration chain. The timing constraints will always start from the first output (Q) of a Configuration Chain Flip-flop (CCFF) and ends at the inputs of the next CCFF in the chain. Note that Qb of CCFF will not be constrained!
+
+  - ``--file`` or ``-f`` Specify the output SDC file
+
+  - ``--time_unit`` Specify a time unit to be used in SDC files. Acceptable values are string: ``as`` | ``fs`` | ``ps`` | ``ns`` | ``us`` | ``ms`` | ``ks`` | ``Ms``. By default, we will consider second (``s``).
+
+  
+  - ``--max_delay`` Specify the maximum delay to be used. The timing value should follow the time unit defined in this command.
+
+  - ``--min_delay`` Specify the minimum delay to be used. The timing value should follow the time unit defined in this command.
+
+  .. note::
+     Only applicable when configuration chain is used as configuration protocol
+
+
 .. option:: write_analysis_sdc
 
   Write the SDC to run timing analysis for a mapped FPGA fabric

From 99751b84f5814743acd93a13c9fef1bc7aa6de7b Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 12 May 2020 22:49:41 -0600
Subject: [PATCH 535/645] bug fix in configuration chain sdc writer

---
 openfpga/src/fpga_sdc/configuration_chain_sdc_writer.cpp | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/openfpga/src/fpga_sdc/configuration_chain_sdc_writer.cpp b/openfpga/src/fpga_sdc/configuration_chain_sdc_writer.cpp
index 5372741bb..ea74ea579 100644
--- a/openfpga/src/fpga_sdc/configuration_chain_sdc_writer.cpp
+++ b/openfpga/src/fpga_sdc/configuration_chain_sdc_writer.cpp
@@ -101,16 +101,16 @@ void rec_print_pnr_sdc_constrain_configurable_chain(std::fstream& fp,
       for (const BasicPort& input_port : module_manager.module_ports_by_type(parent_module, ModuleManager::MODULE_INPUT_PORT)) {
         print_pnr_sdc_constrain_max_delay(fp, 
                                           previous_module_path, 
-                                          generate_sdc_port(output_port),
+                                          output_port.get_name(),
                                           parent_module_path, 
-                                          generate_sdc_port(input_port),
+                                          input_port.get_name(),
                                           tmax);
 
         print_pnr_sdc_constrain_min_delay(fp, 
                                           previous_module_path, 
-                                          generate_sdc_port(output_port),
+                                          output_port.get_name(),
                                           parent_module_path, 
-                                          generate_sdc_port(input_port),
+                                          input_port.get_name(),
                                           tmin);
       }
       

From ae9f1fbd908f3724ad54c630bcf088cd1d7cc2d9 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 13 May 2020 23:37:07 -0600
Subject: [PATCH 536/645] critical bug fixed in the disable MUX output

---
 openfpga/src/fpga_sdc/sdc_mux_utils.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/openfpga/src/fpga_sdc/sdc_mux_utils.cpp b/openfpga/src/fpga_sdc/sdc_mux_utils.cpp
index ee30eae9b..7f7acc41f 100644
--- a/openfpga/src/fpga_sdc/sdc_mux_utils.cpp
+++ b/openfpga/src/fpga_sdc/sdc_mux_utils.cpp
@@ -52,10 +52,10 @@ void rec_print_pnr_sdc_disable_routing_multiplexer_outputs(std::fstream& fp,
   /* For each child, we will go one level down in priority */
   for (const ModuleId& child_module : module_manager.child_modules(parent_module)) {
 
-    std::string child_module_path = parent_module_path;
-
     /* Iterate over the child instances*/
     for (const size_t& child_instance : module_manager.child_module_instances(parent_module, child_module)) {
+      std::string child_module_path = parent_module_path;
+
       std::string child_instance_name;
       if (true == module_manager.instance_name(parent_module, child_module, child_instance).empty()) {
         child_instance_name = generate_instance_name(module_manager.module_name(child_module), child_instance);

From 13f591cacfa451e9d0d8f97d6cb92fbb934ce820 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 14 May 2020 16:53:15 -0600
Subject: [PATCH 537/645] add new command to disable timing for configure ports
 of programmable modules

---
 openfpga/src/base/openfpga_sdc.cpp            |  27 +++
 openfpga/src/base/openfpga_sdc.h              |   3 +
 openfpga/src/base/openfpga_sdc_command.cpp    |  40 ++++
 .../fpga_sdc/configure_port_sdc_writer.cpp    | 160 ++++++++++++++
 .../src/fpga_sdc/configure_port_sdc_writer.h  |  26 +++
 openfpga/src/fpga_sdc/pnr_sdc_writer.cpp      |  63 ------
 openfpga/src/fpga_sdc/sdc_mux_utils.cpp       | 204 +++++++++++-------
 openfpga/src/fpga_sdc/sdc_mux_utils.h         |  21 +-
 openfpga/src/fpga_sdc/sdc_writer_utils.cpp    | 111 ++++++++++
 openfpga/src/fpga_sdc/sdc_writer_utils.h      |   8 +
 ...onfiguration_chain_example_script.openfpga |   3 +
 .../example_script.openfpga                   |   3 +
 12 files changed, 523 insertions(+), 146 deletions(-)
 create mode 100644 openfpga/src/fpga_sdc/configure_port_sdc_writer.cpp
 create mode 100644 openfpga/src/fpga_sdc/configure_port_sdc_writer.h

diff --git a/openfpga/src/base/openfpga_sdc.cpp b/openfpga/src/base/openfpga_sdc.cpp
index 93bd46959..bba115d3c 100644
--- a/openfpga/src/base/openfpga_sdc.cpp
+++ b/openfpga/src/base/openfpga_sdc.cpp
@@ -16,6 +16,7 @@
 #include "pnr_sdc_writer.h"
 #include "analysis_sdc_writer.h"
 #include "configuration_chain_sdc_writer.h"
+#include "configure_port_sdc_writer.h"
 #include "openfpga_sdc.h"
 
 /* Include global variables of VPR */
@@ -138,6 +139,32 @@ int write_configuration_chain_sdc(const OpenfpgaContext& openfpga_ctx,
   return CMD_EXEC_SUCCESS;
 }
 
+/********************************************************************
+ * A wrapper function to call the PnR SDC generator on routing multiplexers
+ * of FPGA-SDC
+ *******************************************************************/
+int write_sdc_disable_timing_configure_ports(const OpenfpgaContext& openfpga_ctx,
+                                             const Command& cmd, const CommandContext& cmd_context) {
+
+  /* Get command options */
+  CommandOptionId opt_output_dir = cmd.option("file");
+  CommandOptionId opt_flatten_names = cmd.option("flatten_names");
+
+  std::string sdc_dir_path = format_dir_path(cmd_context.option_value(cmd, opt_output_dir));
+
+  /* Write the SDC for configuration chain */
+  if (CMD_EXEC_FATAL_ERROR == 
+        print_sdc_disable_timing_configure_ports(cmd_context.option_value(cmd, opt_output_dir),
+                                                 cmd_context.option_enable(cmd, opt_flatten_names),
+                                                 openfpga_ctx.mux_lib(),
+                                                 openfpga_ctx.arch().circuit_lib,
+                                                 openfpga_ctx.module_graph())) {
+    return CMD_EXEC_FATAL_ERROR;
+  }
+
+  return CMD_EXEC_SUCCESS;
+}
+
 /********************************************************************
  * A wrapper function to call the analysis SDC generator of FPGA-SDC
  *******************************************************************/
diff --git a/openfpga/src/base/openfpga_sdc.h b/openfpga/src/base/openfpga_sdc.h
index 060c304bc..03f4af03f 100644
--- a/openfpga/src/base/openfpga_sdc.h
+++ b/openfpga/src/base/openfpga_sdc.h
@@ -21,6 +21,9 @@ int write_pnr_sdc(OpenfpgaContext& openfpga_ctx,
 int write_configuration_chain_sdc(const OpenfpgaContext& openfpga_ctx,
                                   const Command& cmd, const CommandContext& cmd_context);
 
+int write_sdc_disable_timing_configure_ports(const OpenfpgaContext& openfpga_ctx,
+                                             const Command& cmd, const CommandContext& cmd_context);
+
 int write_analysis_sdc(OpenfpgaContext& openfpga_ctx,
                        const Command& cmd, const CommandContext& cmd_context);
 
diff --git a/openfpga/src/base/openfpga_sdc_command.cpp b/openfpga/src/base/openfpga_sdc_command.cpp
index faa488931..17910a711 100644
--- a/openfpga/src/base/openfpga_sdc_command.cpp
+++ b/openfpga/src/base/openfpga_sdc_command.cpp
@@ -119,6 +119,36 @@ ShellCommandId add_openfpga_write_configuration_chain_sdc_command(openfpga::Shel
   return shell_cmd_id;
 }
 
+/********************************************************************
+ * - Add a command to Shell environment: generate PnR SDC for configure ports
+ * - Add associated options 
+ * - Add command dependency
+ *******************************************************************/
+static 
+ShellCommandId add_openfpga_write_sdc_disable_timing_configure_ports_command(openfpga::Shell<OpenfpgaContext>& shell,
+                                                                             const ShellCommandClassId& cmd_class_id,
+                                                                             const std::vector<ShellCommandId>& dependent_cmds) {
+  Command shell_cmd("write_sdc_disable_timing_configure_ports");
+
+  /* Add an option '--file' in short '-f'*/
+  CommandOptionId output_opt = shell_cmd.add_option("file", true, "Specify the output directory");
+  shell_cmd.set_option_short_name(output_opt, "f");
+  shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING);
+
+  /* Add an option '--flatten_name' */
+  shell_cmd.add_option("flatten_names", false, "Use flatten names (no wildcards) in SDC files");
+
+  /* Add command 'write_configuration_chain_sdc' to the Shell */
+  ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "generate SDC files to disable timing for configure ports across FPGA fabric");
+  shell.set_command_class(shell_cmd_id, cmd_class_id);
+  shell.set_command_const_execute_function(shell_cmd_id, write_sdc_disable_timing_configure_ports);
+
+  /* Add command dependency to the Shell */
+  shell.set_command_dependency(shell_cmd_id, dependent_cmds);
+
+  return shell_cmd_id;
+}
+
 /********************************************************************
  * - Add a command to Shell environment: generate PnR SDC 
  * - Add associated options 
@@ -183,6 +213,16 @@ void add_openfpga_sdc_commands(openfpga::Shell<OpenfpgaContext>& shell) {
                                                      openfpga_sdc_cmd_class,
                                                      cc_sdc_cmd_dependency);
 
+  /******************************** 
+   * Command 'write_sdc_disable_timing_configure_ports' 
+   */
+  /* The 'write_sdc_disable_timing_configure_ports' command should NOT be executed before 'build_fabric' */
+  std::vector<ShellCommandId> config_port_sdc_cmd_dependency;
+  config_port_sdc_cmd_dependency.push_back(build_fabric_id);
+  add_openfpga_write_sdc_disable_timing_configure_ports_command(shell,
+                                                                openfpga_sdc_cmd_class,
+                                                                config_port_sdc_cmd_dependency);
+
   /******************************** 
    * Command 'write_analysis_sdc' 
    */
diff --git a/openfpga/src/fpga_sdc/configure_port_sdc_writer.cpp b/openfpga/src/fpga_sdc/configure_port_sdc_writer.cpp
new file mode 100644
index 000000000..c38a2d725
--- /dev/null
+++ b/openfpga/src/fpga_sdc/configure_port_sdc_writer.cpp
@@ -0,0 +1,160 @@
+/********************************************************************
+ * This file includes functions that print SDC (Synopsys Design Constraint) 
+ * files in physical design tools, i.e., Place & Route (PnR) tools
+ * The SDC files are used to constrain the timing of configuration chain 
+ *
+ * Note that this is different from the SDC to constrain VPR Place&Route
+ * engine! These SDCs are designed for PnR to generate FPGA layouts!!!
+ *******************************************************************/
+#include <ctime>
+#include <fstream>
+#include <iomanip>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_time.h"
+#include "vtr_log.h"
+
+/* Headers from openfpgashell library */
+#include "command_exit_codes.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_scale.h"
+#include "openfpga_port.h"
+#include "openfpga_digest.h"
+
+#include "openfpga_naming.h"
+
+#include "sdc_writer_naming.h"
+#include "sdc_writer_utils.h"
+#include "sdc_mux_utils.h"
+#include "configure_port_sdc_writer.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Break combinational loops in FPGA fabric, which mainly come from 
+ * non-MUX programmable modules
+ * To handle this, we disable the timing at configuration ports
+ *
+ * Return code:
+ *   0: success
+ *   1: fatal error occurred
+ *******************************************************************/
+static 
+int print_sdc_disable_non_mux_circuit_configure_ports(std::fstream& fp,
+                                                      const bool& flatten_names,
+                                                      const CircuitLibrary& circuit_lib,
+                                                      const ModuleManager& module_manager,
+                                                      const ModuleId& top_module) {
+
+  if (false == valid_file_stream(fp)) {
+    return CMD_EXEC_FATAL_ERROR;
+  }
+
+  /* Iterate over the MUX modules */
+  for (const CircuitModelId& model : circuit_lib.models()) {
+    
+    /* Skip MUXes, they are handled in another function */
+    if (CIRCUIT_MODEL_MUX == circuit_lib.model_type(model)) {
+      continue;
+    }
+
+    /* We care programmable circuit models only */
+    if (0 == circuit_lib.model_ports_by_type(model, CIRCUIT_MODEL_PORT_SRAM).size()) {
+      continue;
+    }
+
+    std::string programmable_module_name = circuit_lib.model_name(model);
+
+    /* Find the module name in module manager */
+    ModuleId programmable_module = module_manager.find_module(programmable_module_name);
+    VTR_ASSERT(true == module_manager.valid_module_id(programmable_module));
+
+    /* Go recursively in the module manager, 
+     * starting from the top-level module: instance id of the top-level module is 0 by default 
+     * Disable all the outputs of child modules that matches the mux_module id
+     */
+    for (const CircuitPortId& sram_port : circuit_lib.model_ports_by_type(model, CIRCUIT_MODEL_PORT_SRAM)) {
+      const std::string& sram_port_name = circuit_lib.port_lib_name(sram_port);
+      if (CMD_EXEC_FATAL_ERROR == 
+            rec_print_sdc_disable_timing_for_module_ports(fp,
+                                                          flatten_names,
+                                                          module_manager,
+                                                          top_module,
+                                                          programmable_module,
+                                                          format_dir_path(module_manager.module_name(top_module)),
+                                                          sram_port_name)) {
+        return CMD_EXEC_FATAL_ERROR;
+      }
+    }
+  }
+
+  return CMD_EXEC_SUCCESS;
+}
+
+/********************************************************************
+ * Break combinational loops in FPGA fabric, which mainly come from
+ * the configure ports of each programmable module. 
+ * To handle this, we disable the configure ports of 
+ *   - routing multiplexers
+ *   - other circuit model that has SRAM ports
+ *******************************************************************/
+int print_sdc_disable_timing_configure_ports(const std::string& sdc_fname,
+                                             const bool& flatten_names,
+                                             const MuxLibrary& mux_lib,
+                                             const CircuitLibrary& circuit_lib,
+                                             const ModuleManager& module_manager) {
+  /* Create the directory */
+  create_directory(find_path_dir_name(sdc_fname));
+
+  /* Start time count */
+  std::string timer_message = std::string("Write SDC to disable timing on configuration outputs of programmable cells for P&R flow '") + sdc_fname + std::string("'");
+  vtr::ScopedStartFinishTimer timer(timer_message);
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(sdc_fname, std::fstream::out | std::fstream::trunc);
+
+  check_file_stream(sdc_fname.c_str(), fp);
+
+  /* Generate the descriptions*/
+  print_sdc_file_header(fp, std::string("Disable configuration outputs of all the programmable cells for PnR"));
+
+  std::string top_module_name = generate_fpga_top_module_name();
+  ModuleId top_module = module_manager.find_module(top_module_name);
+  VTR_ASSERT(true == module_manager.valid_module_id(top_module));
+ 
+  /* Disable timing for the configure ports of all the routing multiplexer */
+  VTR_LOG("Write disable timing for routing multiplexers...");
+  if (CMD_EXEC_FATAL_ERROR == print_sdc_disable_routing_multiplexer_configure_ports(fp,
+                                                                                    flatten_names,
+                                                                                    mux_lib,
+                                                                                    circuit_lib,
+                                                                                    module_manager,
+                                                                                    top_module)) {
+    VTR_LOG("Fatal errors occurred\n");
+    return CMD_EXEC_FATAL_ERROR;
+  }
+  VTR_LOG("Done\n");
+
+  /* Disable timing for the other programmable circuit models */
+  VTR_LOG("Write disable timing for other programmable modules...");
+  if (CMD_EXEC_FATAL_ERROR == print_sdc_disable_non_mux_circuit_configure_ports(fp,
+                                                                                flatten_names,
+                                                                                circuit_lib,
+                                                                                module_manager,
+                                                                                top_module)) {
+    VTR_LOG("Fatal errors occurred\n");
+    return CMD_EXEC_FATAL_ERROR;
+  }
+  VTR_LOG("Done\n");
+
+  /* Close file handler */
+  fp.close();
+
+  return CMD_EXEC_SUCCESS;
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_sdc/configure_port_sdc_writer.h b/openfpga/src/fpga_sdc/configure_port_sdc_writer.h
new file mode 100644
index 000000000..ef66af749
--- /dev/null
+++ b/openfpga/src/fpga_sdc/configure_port_sdc_writer.h
@@ -0,0 +1,26 @@
+#ifndef CONFIGURE_PORT_SDC_WRITER_H
+#define CONFIGURE_PORT_SDC_WRITER_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <string>
+#include <vector>
+#include "module_manager.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+int print_sdc_disable_timing_configure_ports(const std::string& sdc_fname,
+                                             const bool& flatten_names,
+                                             const MuxLibrary& mux_lib,
+                                             const CircuitLibrary& circuit_lib,
+                                             const ModuleManager& module_manager);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
index 3ef29330d..c02988462 100644
--- a/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
+++ b/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
@@ -75,69 +75,6 @@ void print_pnr_sdc_constrain_configurable_memory_outputs(const std::string& sdc_
   fp.close();
 }
 
-/********************************************************************
- * Break combinational loops in FPGA fabric, which mainly come from 
- * loops of multiplexers.
- * To handle this, we disable the timing at outputs of routing multiplexers
- *******************************************************************/
-static 
-void print_sdc_disable_routing_multiplexer_outputs(const std::string& sdc_dir,
-                                                   const bool& flatten_names,
-                                                   const MuxLibrary& mux_lib,
-                                                   const CircuitLibrary& circuit_lib,
-                                                   const ModuleManager& module_manager,
-                                                   const ModuleId& top_module) {
-  /* Create the file name for Verilog netlist */
-  std::string sdc_fname(sdc_dir + std::string(SDC_DISABLE_MUX_OUTPUTS_FILE_NAME));
-
-  /* Start time count */
-  std::string timer_message = std::string("Write SDC to disable routing multiplexer outputs for P&R flow '") + sdc_fname + std::string("'");
-  vtr::ScopedStartFinishTimer timer(timer_message);
-
-  /* Create the file stream */
-  std::fstream fp;
-  fp.open(sdc_fname, std::fstream::out | std::fstream::trunc);
-
-  check_file_stream(sdc_fname.c_str(), fp);
-
-  /* Generate the descriptions*/
-  print_sdc_file_header(fp, std::string("Disable routing multiplexer outputs for PnR"));
-
-  /* Iterate over the MUX modules */
-  for (const MuxId& mux_id : mux_lib.muxes()) {
-    const CircuitModelId& mux_model = mux_lib.mux_circuit_model(mux_id);
-    
-    /* Skip LUTs, we only care about multiplexers here */
-    if (CIRCUIT_MODEL_MUX != circuit_lib.model_type(mux_model)) {
-      continue;
-    }
-
-    const MuxGraph& mux_graph = mux_lib.mux_graph(mux_id);
-    std::string mux_module_name = generate_mux_subckt_name(circuit_lib, mux_model, 
-                                                           find_mux_num_datapath_inputs(circuit_lib, mux_model, mux_graph.num_inputs()), 
-                                                           std::string(""));
-
-    /* Find the module name in module manager */
-    ModuleId mux_module = module_manager.find_module(mux_module_name);
-    VTR_ASSERT(true == module_manager.valid_module_id(mux_module));
-
-    /* Go recursively in the module manager, 
-     * starting from the top-level module: instance id of the top-level module is 0 by default 
-     * Disable all the outputs of child modules that matches the mux_module id
-     */
-    rec_print_pnr_sdc_disable_routing_multiplexer_outputs(fp,
-                                                          flatten_names,
-                                                          module_manager,
-                                                          top_module,
-                                                          mux_module,
-                                                          format_dir_path(module_manager.module_name(top_module)));
-
-  }
-
-  /* Close file handler */
-  fp.close();
-}
-
 /********************************************************************
  * Break combinational loops in FPGA fabric, which mainly come from 
  * loops of multiplexers.
diff --git a/openfpga/src/fpga_sdc/sdc_mux_utils.cpp b/openfpga/src/fpga_sdc/sdc_mux_utils.cpp
index 7f7acc41f..0d2770566 100644
--- a/openfpga/src/fpga_sdc/sdc_mux_utils.cpp
+++ b/openfpga/src/fpga_sdc/sdc_mux_utils.cpp
@@ -6,13 +6,19 @@
 /* Headers from vtrutil library */
 #include "vtr_assert.h"
 #include "vtr_log.h"
+#include "vtr_time.h"
+
+/* Headers from openfpgashell library */
+#include "command_exit_codes.h"
 
 /* Headers from openfpgautil library */
-#include "openfpga_wildcard_string.h"
 #include "openfpga_digest.h"
 
 #include "openfpga_naming.h"
 
+#include "mux_utils.h"
+
+#include "sdc_writer_naming.h"
 #include "sdc_writer_utils.h"
 
 #include "sdc_mux_utils.h"
@@ -21,93 +27,137 @@
 namespace openfpga {
 
 /********************************************************************
- * Print SDC commands to disable outputs of routing multiplexer modules
- * in a given module id 
- * This function will be executed in a recursive way, 
- * using a Depth-First Search (DFS) strategy
- * It will iterate over all the configurable children under each module
- * and print a SDC command to disable its outputs
- *
- * Note:
- *   - When flatten_names is true
- *     this function will not apply any wildcard to names
- *   - When flatten_names is false
- *     It will straightforwardly output the instance name and port name
- *     This function will try to apply wildcard to names
- *     so that SDC file size can be minimal 
+ * Break combinational loops in FPGA fabric, which mainly come from 
+ * loops of multiplexers.
+ * To handle this, we disable the timing at outputs of routing multiplexers
  *******************************************************************/
-void rec_print_pnr_sdc_disable_routing_multiplexer_outputs(std::fstream& fp, 
-                                                           const bool& flatten_names,
-                                                           const ModuleManager& module_manager, 
-                                                           const ModuleId& parent_module,
-                                                           const ModuleId& mux_module,
-                                                           const std::string& parent_module_path) {
+void print_sdc_disable_routing_multiplexer_outputs(const std::string& sdc_dir,
+                                                   const bool& flatten_names,
+                                                   const MuxLibrary& mux_lib,
+                                                   const CircuitLibrary& circuit_lib,
+                                                   const ModuleManager& module_manager,
+                                                   const ModuleId& top_module) {
+  /* Create the file name for Verilog netlist */
+  std::string sdc_fname(sdc_dir + std::string(SDC_DISABLE_MUX_OUTPUTS_FILE_NAME));
 
-  /* Build wildcard names for the instance names of multiple-instanced-blocks (MIB) 
-   * We will find all the instance names and see there are common prefix 
-   * If so, we can use wildcards
-   */
-  std::map<ModuleId, std::vector<std::string>> wildcard_names;
+  /* Start time count */
+  std::string timer_message = std::string("Write SDC to disable routing multiplexer outputs for P&R flow '") + sdc_fname + std::string("'");
+  vtr::ScopedStartFinishTimer timer(timer_message);
 
-  /* For each child, we will go one level down in priority */
-  for (const ModuleId& child_module : module_manager.child_modules(parent_module)) {
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(sdc_fname, std::fstream::out | std::fstream::trunc);
 
-    /* Iterate over the child instances*/
-    for (const size_t& child_instance : module_manager.child_module_instances(parent_module, child_module)) {
-      std::string child_module_path = parent_module_path;
+  check_file_stream(sdc_fname.c_str(), fp);
 
-      std::string child_instance_name;
-      if (true == module_manager.instance_name(parent_module, child_module, child_instance).empty()) {
-        child_instance_name = generate_instance_name(module_manager.module_name(child_module), child_instance);
-      } else {
-        child_instance_name = module_manager.instance_name(parent_module, child_module, child_instance);
-      }
+  /* Generate the descriptions*/
+  print_sdc_file_header(fp, std::string("Disable routing multiplexer outputs for PnR"));
 
-      if (false == flatten_names) { 
-        /* Try to adapt to a wildcard name: replace all the numbers with a wildcard character '*' */
-        WildCardString wildcard_str(child_instance_name); 
-        /* If the wildcard name is already in the list, we can skip this
-         * Otherwise, we have to 
-         *   - output this instance 
-         *   - record the wildcard name in the map 
-         */
-        if ( (0 < wildcard_names.count(child_module)) 
-          && (wildcard_names.at(child_module).end() != std::find(wildcard_names.at(child_module).begin(),
-                                                                 wildcard_names.at(child_module).end(),
-                                                                 wildcard_str.data())) ) {
-          continue;
-        }
+  /* Iterate over the MUX modules */
+  for (const MuxId& mux_id : mux_lib.muxes()) {
+    const CircuitModelId& mux_model = mux_lib.mux_circuit_model(mux_id);
+    
+    /* Skip LUTs, we only care about multiplexers here */
+    if (CIRCUIT_MODEL_MUX != circuit_lib.model_type(mux_model)) {
+      continue;
+    }
 
-        child_module_path += wildcard_str.data();
- 
-        wildcard_names[child_module].push_back(wildcard_str.data());
-      } else {
-        child_module_path += child_instance_name;
-      }
-      
-      child_module_path = format_dir_path(child_module_path);
+    const MuxGraph& mux_graph = mux_lib.mux_graph(mux_id);
+    std::string mux_module_name = generate_mux_subckt_name(circuit_lib, mux_model, 
+                                                           find_mux_num_datapath_inputs(circuit_lib, mux_model, mux_graph.num_inputs()), 
+                                                           std::string(""));
 
-      /* If this is NOT the MUX module we want, we go recursively */
-      if (mux_module != child_module) {
-        rec_print_pnr_sdc_disable_routing_multiplexer_outputs(fp, flatten_names,
-                                                              module_manager, 
-                                                              child_module, 
-                                                              mux_module,
-                                                              child_module_path);
-        continue;
-      }
+    /* Find the module name in module manager */
+    ModuleId mux_module = module_manager.find_module(mux_module_name);
+    VTR_ASSERT(true == module_manager.valid_module_id(mux_module));
 
-      /* Validate file stream */
-      valid_file_stream(fp);
-
-      /* Reach here, this is the MUX module we want, disable the outputs */
-      for (const BasicPort& output_port : module_manager.module_ports_by_type(mux_module, ModuleManager::MODULE_OUTPUT_PORT)) {
-        fp << "set_disable_timing ";
-        fp << child_module_path << output_port.get_name();
-        fp << std::endl;
-      }
+    /* Go recursively in the module manager, 
+     * starting from the top-level module: instance id of the top-level module is 0 by default 
+     * Disable all the outputs of child modules that matches the mux_module id
+     */
+    for (const BasicPort& output_port : module_manager.module_ports_by_type(mux_module, ModuleManager::MODULE_OUTPUT_PORT)) {
+      rec_print_sdc_disable_timing_for_module_ports(fp,
+                                                    flatten_names,
+                                                    module_manager,
+                                                    top_module,
+                                                    mux_module,
+                                                    format_dir_path(module_manager.module_name(top_module)),
+                                                    output_port.get_name());
     }
   }
+
+  /* Close file handler */
+  fp.close();
+}
+
+/********************************************************************
+ * Break combinational loops in FPGA fabric, which mainly come from 
+ * loops of multiplexers.
+ * To handle this, we disable the timing at configuration ports of routing multiplexers
+ *
+ * Return code:
+ *   0: success
+ *   1: fatal error occurred
+ *******************************************************************/
+int print_sdc_disable_routing_multiplexer_configure_ports(std::fstream& fp,
+                                                          const bool& flatten_names,
+                                                          const MuxLibrary& mux_lib,
+                                                          const CircuitLibrary& circuit_lib,
+                                                          const ModuleManager& module_manager,
+                                                          const ModuleId& top_module) {
+
+  if (false == valid_file_stream(fp)) {
+    return CMD_EXEC_FATAL_ERROR;
+  }
+
+  /* Iterate over the MUX modules */
+  for (const MuxId& mux_id : mux_lib.muxes()) {
+    const CircuitModelId& mux_model = mux_lib.mux_circuit_model(mux_id);
+    
+    const MuxGraph& mux_graph = mux_lib.mux_graph(mux_id);
+    std::string mux_module_name = generate_mux_subckt_name(circuit_lib, mux_model, 
+                                                           find_mux_num_datapath_inputs(circuit_lib, mux_model, mux_graph.num_inputs()), 
+                                                           std::string(""));
+
+    /* Find the module name in module manager */
+    ModuleId mux_module = module_manager.find_module(mux_module_name);
+    VTR_ASSERT(true == module_manager.valid_module_id(mux_module));
+
+    /* Go recursively in the module manager, 
+     * starting from the top-level module: instance id of the top-level module is 0 by default 
+     * Disable all the outputs of child modules that matches the mux_module id
+     */
+    for (const CircuitPortId& mux_sram_port : circuit_lib.model_ports_by_type(mux_model, CIRCUIT_MODEL_PORT_SRAM)) {
+      const std::string& mux_sram_port_name = circuit_lib.port_prefix(mux_sram_port);
+      VTR_ASSERT(true == module_manager.valid_module_port_id(mux_module, module_manager.find_module_port(mux_module, mux_sram_port_name)));
+      if (CMD_EXEC_FATAL_ERROR == 
+            rec_print_sdc_disable_timing_for_module_ports(fp,
+                                                          flatten_names,
+                                                          module_manager,
+                                                          top_module,
+                                                          mux_module,
+                                                          format_dir_path(module_manager.module_name(top_module)),
+                                                          mux_sram_port_name)) {
+        return CMD_EXEC_FATAL_ERROR;
+      }
+
+      const std::string& mux_sram_inv_port_name = circuit_lib.port_prefix(mux_sram_port) + "_inv";
+      VTR_ASSERT(true == module_manager.valid_module_port_id(mux_module, module_manager.find_module_port(mux_module, mux_sram_inv_port_name)));
+      if (CMD_EXEC_FATAL_ERROR == 
+            rec_print_sdc_disable_timing_for_module_ports(fp,
+                                                          flatten_names,
+                                                          module_manager,
+                                                          top_module,
+                                                          mux_module,
+                                                          format_dir_path(module_manager.module_name(top_module)),
+                                                          mux_sram_inv_port_name)) {
+        return CMD_EXEC_FATAL_ERROR;
+      }
+    }
+
+  }
+
+  return CMD_EXEC_SUCCESS;
 }
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/fpga_sdc/sdc_mux_utils.h b/openfpga/src/fpga_sdc/sdc_mux_utils.h
index 70089aa93..a63a42bb3 100644
--- a/openfpga/src/fpga_sdc/sdc_mux_utils.h
+++ b/openfpga/src/fpga_sdc/sdc_mux_utils.h
@@ -6,6 +6,8 @@
  *******************************************************************/
 #include <fstream>
 #include <string>
+#include "mux_library.h"
+#include "circuit_library.h"
 #include "module_manager.h"
 
 /********************************************************************
@@ -15,12 +17,19 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-void rec_print_pnr_sdc_disable_routing_multiplexer_outputs(std::fstream& fp, 
-                                                           const bool& flatten_names,
-                                                           const ModuleManager& module_manager, 
-                                                           const ModuleId& parent_module,
-                                                           const ModuleId& mux_module,
-                                                           const std::string& parent_module_path);
+void print_sdc_disable_routing_multiplexer_outputs(const std::string& sdc_dir,
+                                                   const bool& flatten_names,
+                                                   const MuxLibrary& mux_lib,
+                                                   const CircuitLibrary& circuit_lib,
+                                                   const ModuleManager& module_manager,
+                                                   const ModuleId& top_module);
+
+int print_sdc_disable_routing_multiplexer_configure_ports(std::fstream& fp,
+                                                          const bool& flatten_names,
+                                                          const MuxLibrary& mux_lib,
+                                                          const CircuitLibrary& circuit_lib,
+                                                          const ModuleManager& module_manager,
+                                                          const ModuleId& top_module);
 
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/fpga_sdc/sdc_writer_utils.cpp b/openfpga/src/fpga_sdc/sdc_writer_utils.cpp
index 93a3a94aa..e448d806e 100644
--- a/openfpga/src/fpga_sdc/sdc_writer_utils.cpp
+++ b/openfpga/src/fpga_sdc/sdc_writer_utils.cpp
@@ -4,12 +4,16 @@
 #include <chrono>
 #include <ctime>
 #include <iomanip>
+#include <map>
 
 /* Headers from vtrutil library */
 #include "vtr_assert.h"
 
 /* Headers from openfpgautil library */
 #include "openfpga_digest.h"
+#include "openfpga_wildcard_string.h"
+
+#include "openfpga_naming.h"
 
 #include "sdc_writer_utils.h"
 
@@ -295,4 +299,111 @@ void print_sdc_set_port_output_delay(std::fstream& fp,
   fp << std::endl;
 }
 
+/********************************************************************
+ * Print SDC commands to disable a given port of modules
+ * in a given module id 
+ * This function will be executed in a recursive way, 
+ * using a Depth-First Search (DFS) strategy
+ * It will iterate over all the configurable children under each module
+ * and print a SDC command to disable its outputs
+ *
+ * Return code:
+ *   0: success
+ *   1: fatal error occurred
+ *
+ * Note:
+ *   - When flatten_names is true
+ *     this function will not apply any wildcard to names
+ *   - When flatten_names is false
+ *     It will straightforwardly output the instance name and port name
+ *     This function will try to apply wildcard to names
+ *     so that SDC file size can be minimal 
+ *******************************************************************/
+int rec_print_sdc_disable_timing_for_module_ports(std::fstream& fp, 
+                                                  const bool& flatten_names,
+                                                  const ModuleManager& module_manager, 
+                                                  const ModuleId& parent_module,
+                                                  const ModuleId& module_to_disable,
+                                                  const std::string& parent_module_path,
+                                                  const std::string& disable_port_name) {
+
+  if (false == valid_file_stream(fp)) {
+    return 1;
+  }
+
+  /* Build wildcard names for the instance names of multiple-instanced-blocks (MIB) 
+   * We will find all the instance names and see there are common prefix 
+   * If so, we can use wildcards
+   */
+  std::map<ModuleId, std::vector<std::string>> wildcard_names;
+
+  /* For each child, we will go one level down in priority */
+  for (const ModuleId& child_module : module_manager.child_modules(parent_module)) {
+
+    /* Iterate over the child instances*/
+    for (const size_t& child_instance : module_manager.child_module_instances(parent_module, child_module)) {
+      std::string child_module_path = parent_module_path;
+
+      std::string child_instance_name;
+      if (true == module_manager.instance_name(parent_module, child_module, child_instance).empty()) {
+        child_instance_name = generate_instance_name(module_manager.module_name(child_module), child_instance);
+      } else {
+        child_instance_name = module_manager.instance_name(parent_module, child_module, child_instance);
+      }
+
+      if (false == flatten_names) { 
+        /* Try to adapt to a wildcard name: replace all the numbers with a wildcard character '*' */
+        WildCardString wildcard_str(child_instance_name); 
+        /* If the wildcard name is already in the list, we can skip this
+         * Otherwise, we have to 
+         *   - output this instance 
+         *   - record the wildcard name in the map 
+         */
+        if ( (0 < wildcard_names.count(child_module)) 
+          && (wildcard_names.at(child_module).end() != std::find(wildcard_names.at(child_module).begin(),
+                                                                 wildcard_names.at(child_module).end(),
+                                                                 wildcard_str.data())) ) {
+          continue;
+        }
+
+        child_module_path += wildcard_str.data();
+ 
+        wildcard_names[child_module].push_back(wildcard_str.data());
+      } else {
+        child_module_path += child_instance_name;
+      }
+      
+      child_module_path = format_dir_path(child_module_path);
+
+      /* If this is NOT the MUX module we want, we go recursively */
+      if (module_to_disable != child_module) {
+        int status = rec_print_sdc_disable_timing_for_module_ports(fp, flatten_names,
+                                                                   module_manager, 
+                                                                   child_module, 
+                                                                   module_to_disable,
+                                                                   child_module_path,
+                                                                   disable_port_name);
+        if (1 == status) {
+          return 1; /* FATAL ERRORS */
+        }
+        continue;
+      }
+
+      /* Validate file stream */
+      valid_file_stream(fp);
+
+      /* Reach here, this is the MUX module we want, disable the outputs */
+      ModulePortId port_to_disable = module_manager.find_module_port(module_to_disable, disable_port_name);
+      if (ModulePortId::INVALID() == port_to_disable) {
+        return 1; /* FATAL ERRORS */
+      }
+      fp << "set_disable_timing ";
+      fp << child_module_path << module_manager.module_port(module_to_disable, port_to_disable).get_name();
+      fp << std::endl;
+    }
+  }
+
+  return 0; /* Success */
+}
+
 } /* end namespace openfpga */
diff --git a/openfpga/src/fpga_sdc/sdc_writer_utils.h b/openfpga/src/fpga_sdc/sdc_writer_utils.h
index 4b353045b..7a3861737 100644
--- a/openfpga/src/fpga_sdc/sdc_writer_utils.h
+++ b/openfpga/src/fpga_sdc/sdc_writer_utils.h
@@ -74,6 +74,14 @@ void print_sdc_set_port_output_delay(std::fstream& fp,
                                      const BasicPort& clock_port,
                                      const float& delay);
 
+int rec_print_sdc_disable_timing_for_module_ports(std::fstream& fp, 
+                                                  const bool& flatten_names,
+                                                  const ModuleManager& module_manager, 
+                                                  const ModuleId& parent_module,
+                                                  const ModuleId& module_to_disable,
+                                                  const std::string& parent_module_path,
+                                                  const std::string& disable_port_name);
+
 } /* end namespace openfpga */
 
 #endif
diff --git a/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga
index 326bdba6a..8b523f4ae 100644
--- a/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga
@@ -58,6 +58,9 @@ write_pnr_sdc --file ./SDC
 # Write SDC to constrain timing of configuration chain
 write_configuration_chain_sdc --file ./SDC/ccff_timing.sdc --time_unit ns --max_delay 5 --min_delay 2.5
 
+# Write SDC to disable timing for configure ports
+write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
+
 # Write the SDC to run timing analysis for a mapped FPGA fabric
 write_analysis_sdc --file ./SDC_analysis
 
diff --git a/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
index 1ccd8418d..f1dc80820 100644
--- a/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
@@ -55,6 +55,9 @@ write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE
 #  - Turn on every options here
 write_pnr_sdc --file ./SDC
 
+# Write SDC to disable timing for configure ports
+write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
+
 # Write the SDC to run timing analysis for a mapped FPGA fabric
 write_analysis_sdc --file ./SDC_analysis
 

From f4dd882f0f974b12f98348ddeedd2b65df84a585 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 14 May 2020 16:57:07 -0600
Subject: [PATCH 538/645] documentation updated for new command

---
 docs/source/openfpga_shell/openfpga_commands.rst | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/docs/source/openfpga_shell/openfpga_commands.rst b/docs/source/openfpga_shell/openfpga_commands.rst
index c07b7a71c..4e5770ebd 100644
--- a/docs/source/openfpga_shell/openfpga_commands.rst
+++ b/docs/source/openfpga_shell/openfpga_commands.rst
@@ -237,6 +237,13 @@ FPGA-SDC
   .. note::
      Only applicable when configuration chain is used as configuration protocol
 
+.. option:: write_sdc_disable_timing_configure_ports
+
+  Write the SDC file to disable timing for configure ports of programmable modules. The SDC aims to break the combinational loops across FPGAs and avoid false path timing to be visible to timing analyzers
+
+  - ``--file`` or ``-f`` Specify the output SDC file
+
+  - ``--flatten_names`` Use flatten names (no wildcards) in SDC files
 
 .. option:: write_analysis_sdc
 

From 067d09f9542bccef2765a92a295ab3e9b37590f0 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 14 May 2020 17:13:05 -0600
Subject: [PATCH 539/645] bug fix for configure port disable_timing writer

---
 openfpga/src/fpga_sdc/configure_port_sdc_writer.cpp | 5 ++++-
 openfpga/src/fpga_sdc/sdc_mux_utils.cpp             | 7 ++++---
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/openfpga/src/fpga_sdc/configure_port_sdc_writer.cpp b/openfpga/src/fpga_sdc/configure_port_sdc_writer.cpp
index c38a2d725..ee9c83667 100644
--- a/openfpga/src/fpga_sdc/configure_port_sdc_writer.cpp
+++ b/openfpga/src/fpga_sdc/configure_port_sdc_writer.cpp
@@ -25,6 +25,8 @@
 
 #include "openfpga_naming.h"
 
+#include "circuit_library_utils.h"
+
 #include "sdc_writer_naming.h"
 #include "sdc_writer_utils.h"
 #include "sdc_mux_utils.h"
@@ -76,8 +78,9 @@ int print_sdc_disable_non_mux_circuit_configure_ports(std::fstream& fp,
      * starting from the top-level module: instance id of the top-level module is 0 by default 
      * Disable all the outputs of child modules that matches the mux_module id
      */
-    for (const CircuitPortId& sram_port : circuit_lib.model_ports_by_type(model, CIRCUIT_MODEL_PORT_SRAM)) {
+    for (const CircuitPortId& sram_port : find_circuit_mode_select_sram_ports(circuit_lib, model)) {
       const std::string& sram_port_name = circuit_lib.port_lib_name(sram_port);
+      VTR_ASSERT(true == module_manager.valid_module_port_id(programmable_module, module_manager.find_module_port(programmable_module, sram_port_name)));
       if (CMD_EXEC_FATAL_ERROR == 
             rec_print_sdc_disable_timing_for_module_ports(fp,
                                                           flatten_names,
diff --git a/openfpga/src/fpga_sdc/sdc_mux_utils.cpp b/openfpga/src/fpga_sdc/sdc_mux_utils.cpp
index 0d2770566..b72d17fdf 100644
--- a/openfpga/src/fpga_sdc/sdc_mux_utils.cpp
+++ b/openfpga/src/fpga_sdc/sdc_mux_utils.cpp
@@ -17,6 +17,7 @@
 #include "openfpga_naming.h"
 
 #include "mux_utils.h"
+#include "circuit_library_utils.h"
 
 #include "sdc_writer_naming.h"
 #include "sdc_writer_utils.h"
@@ -127,8 +128,8 @@ int print_sdc_disable_routing_multiplexer_configure_ports(std::fstream& fp,
      * starting from the top-level module: instance id of the top-level module is 0 by default 
      * Disable all the outputs of child modules that matches the mux_module id
      */
-    for (const CircuitPortId& mux_sram_port : circuit_lib.model_ports_by_type(mux_model, CIRCUIT_MODEL_PORT_SRAM)) {
-      const std::string& mux_sram_port_name = circuit_lib.port_prefix(mux_sram_port);
+    for (const CircuitPortId& mux_sram_port : find_circuit_regular_sram_ports(circuit_lib, mux_model)) {
+      const std::string& mux_sram_port_name = circuit_lib.port_lib_name(mux_sram_port);
       VTR_ASSERT(true == module_manager.valid_module_port_id(mux_module, module_manager.find_module_port(mux_module, mux_sram_port_name)));
       if (CMD_EXEC_FATAL_ERROR == 
             rec_print_sdc_disable_timing_for_module_ports(fp,
@@ -141,7 +142,7 @@ int print_sdc_disable_routing_multiplexer_configure_ports(std::fstream& fp,
         return CMD_EXEC_FATAL_ERROR;
       }
 
-      const std::string& mux_sram_inv_port_name = circuit_lib.port_prefix(mux_sram_port) + "_inv";
+      const std::string& mux_sram_inv_port_name = circuit_lib.port_lib_name(mux_sram_port) + "_inv";
       VTR_ASSERT(true == module_manager.valid_module_port_id(mux_module, module_manager.find_module_port(mux_module, mux_sram_inv_port_name)));
       if (CMD_EXEC_FATAL_ERROR == 
             rec_print_sdc_disable_timing_for_module_ports(fp,

From 910be3cadb0197d9254d1c1b0bfc6b0210ae6fb9 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 14 May 2020 17:23:58 -0600
Subject: [PATCH 540/645] massively deploy disable_timing for configure ports
 in CI

---
 .../duplicated_grid_pin_example_script.openfpga                | 3 +++
 .../flatten_routing_example_script.openfpga                    | 3 +++
 .../generate_fabric_example_script.openfpga                    | 3 +++
 .../implicit_verilog_example_script.openfpga                   | 3 +++
 .../OpenFPGAShellScripts/mcnc_example_script.openfpga          | 3 +++
 .../OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga | 3 +++
 6 files changed, 18 insertions(+)

diff --git a/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga
index 1ccd8418d..f1dc80820 100644
--- a/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga
@@ -55,6 +55,9 @@ write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE
 #  - Turn on every options here
 write_pnr_sdc --file ./SDC
 
+# Write SDC to disable timing for configure ports
+write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
+
 # Write the SDC to run timing analysis for a mapped FPGA fabric
 write_analysis_sdc --file ./SDC_analysis
 
diff --git a/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga
index 529fc19ae..88be8a878 100644
--- a/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga
@@ -55,6 +55,9 @@ write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE
 #  - Turn on every options here
 write_pnr_sdc --file ./SDC
 
+# Write SDC to disable timing for configure ports
+write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
+
 # Write the SDC to run timing analysis for a mapped FPGA fabric
 write_analysis_sdc --file ./SDC_analysis
 
diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga
index 6514f36b4..ff40f4c76 100644
--- a/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga
@@ -29,6 +29,9 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --inc
 #  - Turn on every options here
 write_pnr_sdc --file ./SDC
 
+# Write SDC to disable timing for configure ports
+write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
+
 # Finish and exit OpenFPGA
 exit
 
diff --git a/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga
index aa4ea30ad..579e113a9 100644
--- a/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga
@@ -55,6 +55,9 @@ write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE
 #  - Turn on every options here
 write_pnr_sdc --file ./SDC
 
+# Write SDC to disable timing for configure ports
+write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
+
 # Write the SDC to run timing analysis for a mapped FPGA fabric
 write_analysis_sdc --file ./SDC_analysis
 
diff --git a/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga
index 71d3ee294..3293979ea 100644
--- a/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga
@@ -59,6 +59,9 @@ write_verilog_testbench --file ./SRC --reference_benchmark_file_path ./${REFEREN
 #  - Turn on every options here
 write_pnr_sdc --file ./SDC
 
+# Write SDC to disable timing for configure ports
+write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
+
 # Write the SDC to run timing analysis for a mapped FPGA fabric
 write_analysis_sdc --file ./SDC_analysis
 
diff --git a/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga
index 39c4d1c70..b4b6ff5ef 100644
--- a/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga
@@ -55,6 +55,9 @@ write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE
 #  - Turn on every options here
 write_pnr_sdc --time_unit ps --file ./SDC
 
+# Write SDC to disable timing for configure ports
+write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
+
 # Write the SDC to run timing analysis for a mapped FPGA fabric
 write_analysis_sdc --time_unit ps --file ./SDC_analysis
 

From e9ceedb01ba1bcaade45c24520196f45314620ba Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 14 May 2020 19:59:39 -0600
Subject: [PATCH 541/645] use constant openfpga context in SDC generator

---
 openfpga/src/base/openfpga_sdc.cpp         | 4 ++--
 openfpga/src/base/openfpga_sdc.h           | 4 ++--
 openfpga/src/base/openfpga_sdc_command.cpp | 4 ++--
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/openfpga/src/base/openfpga_sdc.cpp b/openfpga/src/base/openfpga_sdc.cpp
index bba115d3c..148f5414b 100644
--- a/openfpga/src/base/openfpga_sdc.cpp
+++ b/openfpga/src/base/openfpga_sdc.cpp
@@ -28,7 +28,7 @@ namespace openfpga {
 /********************************************************************
  * A wrapper function to call the PnR SDC generator of FPGA-SDC
  *******************************************************************/
-int write_pnr_sdc(OpenfpgaContext& openfpga_ctx,
+int write_pnr_sdc(const OpenfpgaContext& openfpga_ctx,
                   const Command& cmd, const CommandContext& cmd_context) {
 
   CommandOptionId opt_output_dir = cmd.option("file");
@@ -168,7 +168,7 @@ int write_sdc_disable_timing_configure_ports(const OpenfpgaContext& openfpga_ctx
 /********************************************************************
  * A wrapper function to call the analysis SDC generator of FPGA-SDC
  *******************************************************************/
-int write_analysis_sdc(OpenfpgaContext& openfpga_ctx,
+int write_analysis_sdc(const OpenfpgaContext& openfpga_ctx,
                        const Command& cmd, const CommandContext& cmd_context) {
 
   CommandOptionId opt_output_dir = cmd.option("file");
diff --git a/openfpga/src/base/openfpga_sdc.h b/openfpga/src/base/openfpga_sdc.h
index 03f4af03f..2dd97b72a 100644
--- a/openfpga/src/base/openfpga_sdc.h
+++ b/openfpga/src/base/openfpga_sdc.h
@@ -15,7 +15,7 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-int write_pnr_sdc(OpenfpgaContext& openfpga_ctx,
+int write_pnr_sdc(const OpenfpgaContext& openfpga_ctx,
                   const Command& cmd, const CommandContext& cmd_context); 
 
 int write_configuration_chain_sdc(const OpenfpgaContext& openfpga_ctx,
@@ -24,7 +24,7 @@ int write_configuration_chain_sdc(const OpenfpgaContext& openfpga_ctx,
 int write_sdc_disable_timing_configure_ports(const OpenfpgaContext& openfpga_ctx,
                                              const Command& cmd, const CommandContext& cmd_context);
 
-int write_analysis_sdc(OpenfpgaContext& openfpga_ctx,
+int write_analysis_sdc(const OpenfpgaContext& openfpga_ctx,
                        const Command& cmd, const CommandContext& cmd_context);
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_sdc_command.cpp b/openfpga/src/base/openfpga_sdc_command.cpp
index 17910a711..bf207c33f 100644
--- a/openfpga/src/base/openfpga_sdc_command.cpp
+++ b/openfpga/src/base/openfpga_sdc_command.cpp
@@ -72,7 +72,7 @@ ShellCommandId add_openfpga_write_pnr_sdc_command(openfpga::Shell<OpenfpgaContex
   /* Add command 'write_fabric_verilog' to the Shell */
   ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "generate SDC files to constrain the backend flow for FPGA fabric");
   shell.set_command_class(shell_cmd_id, cmd_class_id);
-  shell.set_command_execute_function(shell_cmd_id, write_pnr_sdc);
+  shell.set_command_const_execute_function(shell_cmd_id, write_pnr_sdc);
 
   /* Add command dependency to the Shell */
   shell.set_command_dependency(shell_cmd_id, dependent_cmds);
@@ -178,7 +178,7 @@ ShellCommandId add_openfpga_write_analysis_sdc_command(openfpga::Shell<OpenfpgaC
   /* Add command 'write_fabric_verilog' to the Shell */
   ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "generate SDC files for timing analysis a PnRed FPGA fabric mapped by a benchmark");
   shell.set_command_class(shell_cmd_id, cmd_class_id);
-  shell.set_command_execute_function(shell_cmd_id, write_analysis_sdc);
+  shell.set_command_const_execute_function(shell_cmd_id, write_analysis_sdc);
 
   /* Add command dependency to the Shell */
   shell.set_command_dependency(shell_cmd_id, dependent_cmds);

From f52b5d5b4ce49957970110e2926a768afb4ad904 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 14 May 2020 20:02:42 -0600
Subject: [PATCH 542/645] use error code in read_arch command

---
 libopenfpga/libarchopenfpga/src/check_circuit_library.cpp | 6 +++---
 libopenfpga/libarchopenfpga/src/check_circuit_library.h   | 2 +-
 openfpga/src/base/openfpga_read_arch.cpp                  | 5 +++--
 3 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp b/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp
index 0abc16a0e..f5392a2e4 100644
--- a/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp
+++ b/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp
@@ -447,7 +447,7 @@ size_t check_circuit_library_ports(const CircuitLibrary& circuit_lib) {
  * 9. LUT must have at least an input, an output and a SRAM ports
  * 10. We must have default circuit models for these types: MUX, channel wires and wires
  ***********************************************************************/
-void check_circuit_library(const CircuitLibrary& circuit_lib) {
+bool check_circuit_library(const CircuitLibrary& circuit_lib) {
   size_t num_err = 0;
 
   vtr::ScopedStartFinishTimer timer("Check circuit library");
@@ -545,10 +545,10 @@ void check_circuit_library(const CircuitLibrary& circuit_lib) {
   if (0 < num_err) {
     VTR_LOG("Finished checking circuit library with %d errors!\n",
             num_err);
-    exit(1);
+    return false;
   }
 
   VTR_LOG("Checking circuit library passed.\n");
 
-  return;
+  return true;
 }
diff --git a/libopenfpga/libarchopenfpga/src/check_circuit_library.h b/libopenfpga/libarchopenfpga/src/check_circuit_library.h
index 7a056d796..a6690f60c 100644
--- a/libopenfpga/libarchopenfpga/src/check_circuit_library.h
+++ b/libopenfpga/libarchopenfpga/src/check_circuit_library.h
@@ -43,6 +43,6 @@ size_t check_sram_circuit_model_ports(const CircuitLibrary& circuit_lib,
                                       const CircuitModelId& circuit_model,
                                       const bool& check_blwl);
 
-void check_circuit_library(const CircuitLibrary& circuit_lib);
+bool check_circuit_library(const CircuitLibrary& circuit_lib);
 
 #endif
diff --git a/openfpga/src/base/openfpga_read_arch.cpp b/openfpga/src/base/openfpga_read_arch.cpp
index 214af1612..ee0670268 100644
--- a/openfpga/src/base/openfpga_read_arch.cpp
+++ b/openfpga/src/base/openfpga_read_arch.cpp
@@ -46,9 +46,10 @@ int read_arch(OpenfpgaContext& openfpga_context,
    * 2. Technology library (TODO)
    * 3. Simulation settings (TODO)
    */
-  check_circuit_library(openfpga_context.arch().circuit_lib);
+  if (false == check_circuit_library(openfpga_context.arch().circuit_lib)) {
+    return CMD_EXEC_FATAL_ERROR;
+  }
 
-  /* TODO: should identify the error code from internal function execution */
   return CMD_EXEC_SUCCESS;
 } 
 

From 6177921d4c1264c1033451f8b670e75c2fbbd924 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 17 May 2020 19:31:46 -0600
Subject: [PATCH 543/645] bug fixed in configure port disable timing. Now we
 disable the right ports of LUTs

---
 .../fpga_sdc/configure_port_sdc_writer.cpp    | 87 +++++++++++++++++++
 openfpga/src/fpga_sdc/sdc_mux_utils.cpp       |  5 ++
 2 files changed, 92 insertions(+)

diff --git a/openfpga/src/fpga_sdc/configure_port_sdc_writer.cpp b/openfpga/src/fpga_sdc/configure_port_sdc_writer.cpp
index ee9c83667..a2a04f003 100644
--- a/openfpga/src/fpga_sdc/configure_port_sdc_writer.cpp
+++ b/openfpga/src/fpga_sdc/configure_port_sdc_writer.cpp
@@ -35,6 +35,76 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
+/********************************************************************
+ * Break combinational loops in FPGA fabric, which mainly come from 
+ * Look-Up Table programmable modules
+ * To handle this, we disable the timing at configuration ports
+ *
+ * Return code:
+ *   0: success
+ *   1: fatal error occurred
+ *******************************************************************/
+static 
+int print_sdc_disable_lut_configure_ports(std::fstream& fp,
+                                          const bool& flatten_names,
+                                          const CircuitLibrary& circuit_lib,
+                                          const ModuleManager& module_manager,
+                                          const ModuleId& top_module) {
+
+  if (false == valid_file_stream(fp)) {
+    return CMD_EXEC_FATAL_ERROR;
+  }
+
+  /* Iterate over the MUX modules */
+  for (const CircuitModelId& model : circuit_lib.models()) {
+    
+    /* Only care LUTs */
+    if (CIRCUIT_MODEL_LUT != circuit_lib.model_type(model)) {
+      continue;
+    }
+
+    std::string programmable_module_name = circuit_lib.model_name(model);
+
+    /* Find the module name in module manager */
+    ModuleId programmable_module = module_manager.find_module(programmable_module_name);
+    VTR_ASSERT(true == module_manager.valid_module_id(programmable_module));
+
+    /* Go recursively in the module manager, 
+     * starting from the top-level module: instance id of the top-level module is 0 by default 
+     * Disable all the outputs of child modules that matches the mux_module id
+     */
+    for (const CircuitPortId& sram_port : circuit_lib.model_ports_by_type(model, CIRCUIT_MODEL_PORT_SRAM)) {
+      const std::string& sram_port_name = circuit_lib.port_lib_name(sram_port);
+      VTR_ASSERT(true == module_manager.valid_module_port_id(programmable_module, module_manager.find_module_port(programmable_module, sram_port_name)));
+      if (CMD_EXEC_FATAL_ERROR == 
+            rec_print_sdc_disable_timing_for_module_ports(fp,
+                                                          flatten_names,
+                                                          module_manager,
+                                                          top_module,
+                                                          programmable_module,
+                                                          format_dir_path(module_manager.module_name(top_module)),
+                                                          sram_port_name)) {
+        return CMD_EXEC_FATAL_ERROR;
+      }
+
+      const std::string& sram_inv_port_name = circuit_lib.port_lib_name(sram_port) + "_inv";
+      VTR_ASSERT(true == module_manager.valid_module_port_id(programmable_module, module_manager.find_module_port(programmable_module, sram_inv_port_name)));
+      if (CMD_EXEC_FATAL_ERROR == 
+            rec_print_sdc_disable_timing_for_module_ports(fp,
+                                                          flatten_names,
+                                                          module_manager,
+                                                          top_module,
+                                                          programmable_module,
+                                                          format_dir_path(module_manager.module_name(top_module)),
+                                                          sram_inv_port_name)) {
+        return CMD_EXEC_FATAL_ERROR;
+      }
+    }
+  }
+
+  return CMD_EXEC_SUCCESS;
+}
+
 /********************************************************************
  * Break combinational loops in FPGA fabric, which mainly come from 
  * non-MUX programmable modules
@@ -63,6 +133,11 @@ int print_sdc_disable_non_mux_circuit_configure_ports(std::fstream& fp,
       continue;
     }
 
+    /* Skip LUTs, they are handled in another function */
+    if (CIRCUIT_MODEL_LUT == circuit_lib.model_type(model)) {
+      continue;
+    }
+
     /* We care programmable circuit models only */
     if (0 == circuit_lib.model_ports_by_type(model, CIRCUIT_MODEL_PORT_SRAM).size()) {
       continue;
@@ -128,6 +203,18 @@ int print_sdc_disable_timing_configure_ports(const std::string& sdc_fname,
   std::string top_module_name = generate_fpga_top_module_name();
   ModuleId top_module = module_manager.find_module(top_module_name);
   VTR_ASSERT(true == module_manager.valid_module_id(top_module));
+
+  /* Disable timing for the configure ports of all the Look-Up Tables */
+  VTR_LOG("Write disable timing for Look-Up Tables...");
+  if (CMD_EXEC_FATAL_ERROR == print_sdc_disable_lut_configure_ports(fp,
+                                                                    flatten_names,
+                                                                    circuit_lib,
+                                                                    module_manager,
+                                                                    top_module)) {
+    VTR_LOG("Fatal errors occurred\n");
+    return CMD_EXEC_FATAL_ERROR;
+  }
+  VTR_LOG("Done\n");
  
   /* Disable timing for the configure ports of all the routing multiplexer */
   VTR_LOG("Write disable timing for routing multiplexers...");
diff --git a/openfpga/src/fpga_sdc/sdc_mux_utils.cpp b/openfpga/src/fpga_sdc/sdc_mux_utils.cpp
index b72d17fdf..c0fd21fca 100644
--- a/openfpga/src/fpga_sdc/sdc_mux_utils.cpp
+++ b/openfpga/src/fpga_sdc/sdc_mux_utils.cpp
@@ -114,6 +114,11 @@ int print_sdc_disable_routing_multiplexer_configure_ports(std::fstream& fp,
   /* Iterate over the MUX modules */
   for (const MuxId& mux_id : mux_lib.muxes()) {
     const CircuitModelId& mux_model = mux_lib.mux_circuit_model(mux_id);
+
+    /* Skip LUTs, we only care about multiplexers here */
+    if (CIRCUIT_MODEL_MUX != circuit_lib.model_type(mux_model)) {
+      continue;
+    }
     
     const MuxGraph& mux_graph = mux_lib.mux_graph(mux_id);
     std::string mux_module_name = generate_mux_subckt_name(circuit_lib, mux_model, 

From 8915d10d2790e296525f9c9c16c11b3a606978a6 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 17 May 2020 19:36:57 -0600
Subject: [PATCH 544/645] add verbose output option to configure port disable
 timing writer

---
 openfpga/src/base/openfpga_sdc.cpp            |  4 +++-
 openfpga/src/base/openfpga_sdc_command.cpp    |  3 +++
 .../fpga_sdc/configure_port_sdc_writer.cpp    | 24 +++++++++++--------
 .../src/fpga_sdc/configure_port_sdc_writer.h  |  3 ++-
 4 files changed, 22 insertions(+), 12 deletions(-)

diff --git a/openfpga/src/base/openfpga_sdc.cpp b/openfpga/src/base/openfpga_sdc.cpp
index 148f5414b..2d44520db 100644
--- a/openfpga/src/base/openfpga_sdc.cpp
+++ b/openfpga/src/base/openfpga_sdc.cpp
@@ -149,6 +149,7 @@ int write_sdc_disable_timing_configure_ports(const OpenfpgaContext& openfpga_ctx
   /* Get command options */
   CommandOptionId opt_output_dir = cmd.option("file");
   CommandOptionId opt_flatten_names = cmd.option("flatten_names");
+  CommandOptionId opt_verbose = cmd.option("verbose");
 
   std::string sdc_dir_path = format_dir_path(cmd_context.option_value(cmd, opt_output_dir));
 
@@ -158,7 +159,8 @@ int write_sdc_disable_timing_configure_ports(const OpenfpgaContext& openfpga_ctx
                                                  cmd_context.option_enable(cmd, opt_flatten_names),
                                                  openfpga_ctx.mux_lib(),
                                                  openfpga_ctx.arch().circuit_lib,
-                                                 openfpga_ctx.module_graph())) {
+                                                 openfpga_ctx.module_graph(),
+                                                 cmd_context.option_enable(cmd, opt_verbose))) {
     return CMD_EXEC_FATAL_ERROR;
   }
 
diff --git a/openfpga/src/base/openfpga_sdc_command.cpp b/openfpga/src/base/openfpga_sdc_command.cpp
index bf207c33f..5459b7fec 100644
--- a/openfpga/src/base/openfpga_sdc_command.cpp
+++ b/openfpga/src/base/openfpga_sdc_command.cpp
@@ -138,6 +138,9 @@ ShellCommandId add_openfpga_write_sdc_disable_timing_configure_ports_command(ope
   /* Add an option '--flatten_name' */
   shell_cmd.add_option("flatten_names", false, "Use flatten names (no wildcards) in SDC files");
 
+  /* Add an option '--verbose' */
+  shell_cmd.add_option("verbose", false, "Enable verbose outputs");
+
   /* Add command 'write_configuration_chain_sdc' to the Shell */
   ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "generate SDC files to disable timing for configure ports across FPGA fabric");
   shell.set_command_class(shell_cmd_id, cmd_class_id);
diff --git a/openfpga/src/fpga_sdc/configure_port_sdc_writer.cpp b/openfpga/src/fpga_sdc/configure_port_sdc_writer.cpp
index a2a04f003..e0508d3f4 100644
--- a/openfpga/src/fpga_sdc/configure_port_sdc_writer.cpp
+++ b/openfpga/src/fpga_sdc/configure_port_sdc_writer.cpp
@@ -183,7 +183,8 @@ int print_sdc_disable_timing_configure_ports(const std::string& sdc_fname,
                                              const bool& flatten_names,
                                              const MuxLibrary& mux_lib,
                                              const CircuitLibrary& circuit_lib,
-                                             const ModuleManager& module_manager) {
+                                             const ModuleManager& module_manager,
+                                             const bool& verbose) {
   /* Create the directory */
   create_directory(find_path_dir_name(sdc_fname));
 
@@ -205,41 +206,44 @@ int print_sdc_disable_timing_configure_ports(const std::string& sdc_fname,
   VTR_ASSERT(true == module_manager.valid_module_id(top_module));
 
   /* Disable timing for the configure ports of all the Look-Up Tables */
-  VTR_LOG("Write disable timing for Look-Up Tables...");
+  VTR_LOGV(verbose, "Write disable timing for Look-Up Tables...");
   if (CMD_EXEC_FATAL_ERROR == print_sdc_disable_lut_configure_ports(fp,
                                                                     flatten_names,
                                                                     circuit_lib,
                                                                     module_manager,
                                                                     top_module)) {
-    VTR_LOG("Fatal errors occurred\n");
+    VTR_LOGF_ERROR(__FILE__, __LINE__, 
+                   "Fatal errors occurred\n");
     return CMD_EXEC_FATAL_ERROR;
   }
-  VTR_LOG("Done\n");
+  VTR_LOGV(verbose, "Done\n");
  
   /* Disable timing for the configure ports of all the routing multiplexer */
-  VTR_LOG("Write disable timing for routing multiplexers...");
+  VTR_LOGV(verbose, "Write disable timing for routing multiplexers...");
   if (CMD_EXEC_FATAL_ERROR == print_sdc_disable_routing_multiplexer_configure_ports(fp,
                                                                                     flatten_names,
                                                                                     mux_lib,
                                                                                     circuit_lib,
                                                                                     module_manager,
                                                                                     top_module)) {
-    VTR_LOG("Fatal errors occurred\n");
+    VTR_LOGF_ERROR(__FILE__, __LINE__, 
+                   "Fatal errors occurred\n");
     return CMD_EXEC_FATAL_ERROR;
   }
-  VTR_LOG("Done\n");
+  VTR_LOGV(verbose, "Done\n");
 
   /* Disable timing for the other programmable circuit models */
-  VTR_LOG("Write disable timing for other programmable modules...");
+  VTR_LOGV(verbose, "Write disable timing for other programmable modules...");
   if (CMD_EXEC_FATAL_ERROR == print_sdc_disable_non_mux_circuit_configure_ports(fp,
                                                                                 flatten_names,
                                                                                 circuit_lib,
                                                                                 module_manager,
                                                                                 top_module)) {
-    VTR_LOG("Fatal errors occurred\n");
+    VTR_LOGF_ERROR(__FILE__, __LINE__, 
+                   "Fatal errors occurred\n");
     return CMD_EXEC_FATAL_ERROR;
   }
-  VTR_LOG("Done\n");
+  VTR_LOGV(verbose, "Done\n");
 
   /* Close file handler */
   fp.close();
diff --git a/openfpga/src/fpga_sdc/configure_port_sdc_writer.h b/openfpga/src/fpga_sdc/configure_port_sdc_writer.h
index ef66af749..b8b4791d6 100644
--- a/openfpga/src/fpga_sdc/configure_port_sdc_writer.h
+++ b/openfpga/src/fpga_sdc/configure_port_sdc_writer.h
@@ -19,7 +19,8 @@ int print_sdc_disable_timing_configure_ports(const std::string& sdc_fname,
                                              const bool& flatten_names,
                                              const MuxLibrary& mux_lib,
                                              const CircuitLibrary& circuit_lib,
-                                             const ModuleManager& module_manager);
+                                             const ModuleManager& module_manager,
+                                             const bool& verbose);
 
 } /* end namespace openfpga */
 

From c2a81c76e1a1ba50d06a21d21db2b2e16db6e68f Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 17 May 2020 19:38:13 -0600
Subject: [PATCH 545/645] update doc for new options

---
 docs/source/openfpga_shell/openfpga_commands.rst | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/docs/source/openfpga_shell/openfpga_commands.rst b/docs/source/openfpga_shell/openfpga_commands.rst
index 4e5770ebd..909a6416f 100644
--- a/docs/source/openfpga_shell/openfpga_commands.rst
+++ b/docs/source/openfpga_shell/openfpga_commands.rst
@@ -245,6 +245,8 @@ FPGA-SDC
 
   - ``--flatten_names`` Use flatten names (no wildcards) in SDC files
 
+  - ``--verbose`` Show verbose log
+
 .. option:: write_analysis_sdc
 
   Write the SDC to run timing analysis for a mapped FPGA fabric

From e089b0ef22412d13eed645519369eb471aacb1f3 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 17 May 2020 19:45:27 -0600
Subject: [PATCH 546/645] use constant string for inverted port naming

---
 openfpga/src/base/openfpga_reserved_words.h         | 3 +++
 openfpga/src/fabric/build_lut_modules.cpp           | 7 ++++---
 openfpga/src/fabric/build_mux_modules.cpp           | 6 +++---
 openfpga/src/fpga_sdc/configure_port_sdc_writer.cpp | 3 ++-
 openfpga/src/fpga_sdc/sdc_mux_utils.cpp             | 3 ++-
 openfpga/src/utils/module_manager_utils.cpp         | 5 +++--
 6 files changed, 17 insertions(+), 10 deletions(-)

diff --git a/openfpga/src/base/openfpga_reserved_words.h b/openfpga/src/base/openfpga_reserved_words.h
index f04490c0d..be47315ba 100644
--- a/openfpga/src/base/openfpga_reserved_words.h
+++ b/openfpga/src/base/openfpga_reserved_words.h
@@ -30,6 +30,9 @@ constexpr char* GRID_MUX_INSTANCE_PREFIX = "mux_";
 constexpr char* SWITCH_BLOCK_MUX_INSTANCE_PREFIX = "mux_"; 
 constexpr char* CONNECTION_BLOCK_MUX_INSTANCE_PREFIX = "mux_"; 
 
+/* Inverted port naming */
+constexpr char* INV_PORT_POSTFIX = "_inv";
+
 /* Bitstream file strings */
 constexpr char* BITSTREAM_XML_FILE_NAME_POSTFIX = "_bitstream.xml";
 
diff --git a/openfpga/src/fabric/build_lut_modules.cpp b/openfpga/src/fabric/build_lut_modules.cpp
index 2ba688e4d..477308e08 100644
--- a/openfpga/src/fabric/build_lut_modules.cpp
+++ b/openfpga/src/fabric/build_lut_modules.cpp
@@ -10,6 +10,7 @@
 #include "vtr_log.h"
 #include "vtr_time.h"
 
+#include "openfpga_reserved_words.h"
 #include "openfpga_naming.h"
 #include "circuit_library_utils.h"
 #include "module_manager.h"
@@ -106,7 +107,7 @@ void build_lut_module(ModuleManager& module_manager,
   for (const auto& port : lut_regular_sram_ports) {
     BasicPort mem_port(circuit_lib.port_prefix(port), circuit_lib.port_size(port));
     module_manager.add_port(lut_module, mem_port, ModuleManager::MODULE_INPUT_PORT);
-    BasicPort mem_inv_port(std::string(circuit_lib.port_prefix(port) + "_inv"), circuit_lib.port_size(port));
+    BasicPort mem_inv_port(std::string(circuit_lib.port_prefix(port) + INV_PORT_POSTFIX), circuit_lib.port_size(port));
     module_manager.add_port(lut_module, mem_inv_port, ModuleManager::MODULE_INPUT_PORT);
   }
 
@@ -114,7 +115,7 @@ void build_lut_module(ModuleManager& module_manager,
   for (const auto& port : lut_mode_select_sram_ports) {
     BasicPort mem_port(circuit_lib.port_prefix(port), circuit_lib.port_size(port));
     module_manager.add_port(lut_module, mem_port, ModuleManager::MODULE_INPUT_PORT);
-    BasicPort mem_inv_port(std::string(circuit_lib.port_prefix(port) + "_inv"), circuit_lib.port_size(port));
+    BasicPort mem_inv_port(std::string(circuit_lib.port_prefix(port) + INV_PORT_POSTFIX), circuit_lib.port_size(port));
     module_manager.add_port(lut_module, mem_inv_port, ModuleManager::MODULE_INPUT_PORT);
   }
 
@@ -336,7 +337,7 @@ void build_lut_module(ModuleManager& module_manager,
     module_manager.add_module_net_sink(lut_module, lut_mux_sram_nets[pin], lut_mux_module, lut_mux_instance, lut_mux_sram_port_id, pin);
   } 
 
-  ModulePortId lut_mux_sram_inv_port_id = module_manager.find_module_port(lut_mux_module, std::string(circuit_lib.port_prefix(lut_regular_sram_ports[0]) + "_inv"));
+  ModulePortId lut_mux_sram_inv_port_id = module_manager.find_module_port(lut_mux_module, std::string(circuit_lib.port_prefix(lut_regular_sram_ports[0]) + INV_PORT_POSTFIX));
   BasicPort lut_mux_sram_inv_port = module_manager.module_port(lut_mux_module, lut_mux_sram_inv_port_id);
   VTR_ASSERT(lut_mux_sram_inv_port.get_width() == lut_mux_sram_inv_nets.size());
   /* Wire the port to lut_mux_sram_net */
diff --git a/openfpga/src/fabric/build_mux_modules.cpp b/openfpga/src/fabric/build_mux_modules.cpp
index a28eac264..6bc2a55d5 100644
--- a/openfpga/src/fabric/build_mux_modules.cpp
+++ b/openfpga/src/fabric/build_mux_modules.cpp
@@ -977,7 +977,7 @@ void build_mux_module_local_encoders_and_memory_nets(ModuleManager& module_manag
     /* Add mem and mem_inv nets here */
     size_t mem_inv_net_cnt = 0;
     for (const auto& port : mux_sram_ports) {
-      ModulePortId mem_inv_port_id = module_manager.find_module_port(mux_module, std::string(circuit_lib.port_prefix(port) + "_inv"));
+      ModulePortId mem_inv_port_id = module_manager.find_module_port(mux_module, std::string(circuit_lib.port_prefix(port) + INV_PORT_POSTFIX));
       BasicPort mem_inv_port = module_manager.module_port(mux_module, mem_inv_port_id);
       for (const size_t& pin : mem_inv_port.pins()) {
         MuxMemId mem_id = MuxMemId(mem_inv_net_cnt);
@@ -998,7 +998,7 @@ void build_mux_module_local_encoders_and_memory_nets(ModuleManager& module_manag
 
   /* Local port to record the LSB and MSB of each level, here, we deposite (0, 0) */
   ModulePortId mux_module_sram_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_prefix(mux_sram_ports[0]));
-  ModulePortId mux_module_sram_inv_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_prefix(mux_sram_ports[0]) + "_inv");
+  ModulePortId mux_module_sram_inv_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_prefix(mux_sram_ports[0]) + INV_PORT_POSTFIX);
   BasicPort lvl_addr_port(circuit_lib.port_prefix(mux_sram_ports[0]), 0);
   BasicPort lvl_data_port(decoder_data_port.get_name(), 0);
   BasicPort lvl_data_inv_port(decoder_data_inv_port.get_name(), 0);
@@ -1181,7 +1181,7 @@ void build_cmos_mux_module(ModuleManager& module_manager,
   for (const auto& port : mux_sram_ports) {
     BasicPort mem_port(circuit_lib.port_prefix(port), num_mems);
     module_manager.add_port(mux_module, mem_port, ModuleManager::MODULE_INPUT_PORT);
-    BasicPort mem_inv_port(std::string(circuit_lib.port_prefix(port) + "_inv"), num_mems);
+    BasicPort mem_inv_port(std::string(circuit_lib.port_prefix(port) + INV_PORT_POSTFIX), num_mems);
     module_manager.add_port(mux_module, mem_inv_port, ModuleManager::MODULE_INPUT_PORT);
     /* Update counter */
     sram_port_cnt++;
diff --git a/openfpga/src/fpga_sdc/configure_port_sdc_writer.cpp b/openfpga/src/fpga_sdc/configure_port_sdc_writer.cpp
index e0508d3f4..42d5c030c 100644
--- a/openfpga/src/fpga_sdc/configure_port_sdc_writer.cpp
+++ b/openfpga/src/fpga_sdc/configure_port_sdc_writer.cpp
@@ -23,6 +23,7 @@
 #include "openfpga_port.h"
 #include "openfpga_digest.h"
 
+#include "openfpga_reserved_words.h"
 #include "openfpga_naming.h"
 
 #include "circuit_library_utils.h"
@@ -87,7 +88,7 @@ int print_sdc_disable_lut_configure_ports(std::fstream& fp,
         return CMD_EXEC_FATAL_ERROR;
       }
 
-      const std::string& sram_inv_port_name = circuit_lib.port_lib_name(sram_port) + "_inv";
+      const std::string& sram_inv_port_name = circuit_lib.port_lib_name(sram_port) + INV_PORT_POSTFIX;
       VTR_ASSERT(true == module_manager.valid_module_port_id(programmable_module, module_manager.find_module_port(programmable_module, sram_inv_port_name)));
       if (CMD_EXEC_FATAL_ERROR == 
             rec_print_sdc_disable_timing_for_module_ports(fp,
diff --git a/openfpga/src/fpga_sdc/sdc_mux_utils.cpp b/openfpga/src/fpga_sdc/sdc_mux_utils.cpp
index c0fd21fca..57fd8f8a1 100644
--- a/openfpga/src/fpga_sdc/sdc_mux_utils.cpp
+++ b/openfpga/src/fpga_sdc/sdc_mux_utils.cpp
@@ -14,6 +14,7 @@
 /* Headers from openfpgautil library */
 #include "openfpga_digest.h"
 
+#include "openfpga_reserved_words.h"
 #include "openfpga_naming.h"
 
 #include "mux_utils.h"
@@ -147,7 +148,7 @@ int print_sdc_disable_routing_multiplexer_configure_ports(std::fstream& fp,
         return CMD_EXEC_FATAL_ERROR;
       }
 
-      const std::string& mux_sram_inv_port_name = circuit_lib.port_lib_name(mux_sram_port) + "_inv";
+      const std::string& mux_sram_inv_port_name = circuit_lib.port_lib_name(mux_sram_port) + INV_PORT_POSTFIX;
       VTR_ASSERT(true == module_manager.valid_module_port_id(mux_module, module_manager.find_module_port(mux_module, mux_sram_inv_port_name)));
       if (CMD_EXEC_FATAL_ERROR == 
             rec_print_sdc_disable_timing_for_module_ports(fp,
diff --git a/openfpga/src/utils/module_manager_utils.cpp b/openfpga/src/utils/module_manager_utils.cpp
index a57e97261..b1408dcad 100644
--- a/openfpga/src/utils/module_manager_utils.cpp
+++ b/openfpga/src/utils/module_manager_utils.cpp
@@ -13,6 +13,7 @@
 /* Headers from openfpgautil library */
 #include "openfpga_port.h"
 
+#include "openfpga_reserved_words.h"
 #include "openfpga_naming.h"
 #include "memory_utils.h"
 #include "pb_type_utils.h"
@@ -612,11 +613,11 @@ void add_module_nets_between_logic_and_memory_sram_bus(ModuleManager& module_man
   std::vector<std::string> logic_model_sramb_port_names;
   /* Regular sram port goes first */
   for (CircuitPortId regular_sram_port : find_circuit_regular_sram_ports(circuit_lib, logic_model)) {
-    logic_model_sramb_port_names.push_back(circuit_lib.port_prefix(regular_sram_port) + std::string("_inv"));
+    logic_model_sramb_port_names.push_back(circuit_lib.port_prefix(regular_sram_port) + std::string(INV_PORT_POSTFIX));
   }
   /* Mode-select sram port goes first */
   for (CircuitPortId mode_select_sram_port : find_circuit_mode_select_sram_ports(circuit_lib, logic_model)) {
-    logic_model_sramb_port_names.push_back(circuit_lib.port_prefix(mode_select_sram_port) + std::string("_inv"));
+    logic_model_sramb_port_names.push_back(circuit_lib.port_prefix(mode_select_sram_port) + std::string(INV_PORT_POSTFIX));
   }
   /* Find the port ids in the memory */
   std::vector<ModulePortId> logic_module_sramb_port_ids;

From 6f133bd009b2afa204e5f005ad4177b87ff79316 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 20 May 2020 18:49:21 -0600
Subject: [PATCH 547/645] bug fix in packable mode support

---
 vpr/src/pack/cluster_router.cpp | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/vpr/src/pack/cluster_router.cpp b/vpr/src/pack/cluster_router.cpp
index 7f2cd37d9..49a60a805 100644
--- a/vpr/src/pack/cluster_router.cpp
+++ b/vpr/src/pack/cluster_router.cpp
@@ -208,6 +208,15 @@ static bool check_edge_for_route_conflicts(std::unordered_map<const t_pb_graph_n
     auto* mode = &pb_graph_node->pb_type->modes[mode_of_edge];
 
     auto result = mode_map->insert(std::make_pair(pb_graph_node, mode));
+
+    /* Xifan Tang: Insert unpackable mode to the illegal mode list */
+    if (false == mode->packable) {
+        if (std::find(pb_graph_node->illegal_modes.begin(), pb_graph_node->illegal_modes.end(), mode->index) == pb_graph_node->illegal_modes.end()) {
+            pb_graph_node->illegal_modes.push_back(mode->index);
+        }
+        return true;
+    }
+
     if (!result.second) {
         if (result.first->second != mode) {
             std::cout << vtr::string_fmt("Differing modes for block.  Got %s mode, while previously was %s for interconnect %s.",
@@ -1173,10 +1182,6 @@ static void expand_node_all_modes(t_lb_router_data* router_data, t_expansion_nod
         if (cur_mode != -1 && mode != cur_mode) {
             continue;
         }
-        /* Xifan Tang: Do not expand in unpackable modes */
-        if (false == pin->parent_node->pb_type->parent_mode->packable) {
-            continue;
-        }
 
         /* Check whether a mode is illegal. If it is then the node will not be expanded */
         bool is_illegal = false;

From bba476fef499e50801c65ecf190e7e6c95f2a089 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 22 May 2020 14:40:05 -0600
Subject: [PATCH 548/645] add explicit port mapping support to Verilog
 testbench generator

---
 openfpga/src/base/openfpga_verilog.cpp        |  2 ++
 .../src/base/openfpga_verilog_command.cpp     |  3 +++
 openfpga/src/fpga_verilog/verilog_api.cpp     |  9 +++++---
 .../verilog_formal_random_top_testbench.cpp   | 21 ++++++++++++-------
 .../verilog_formal_random_top_testbench.h     |  3 ++-
 .../verilog_preconfig_top_module.cpp          |  6 ++++--
 .../verilog_preconfig_top_module.h            |  3 ++-
 .../verilog_testbench_options.cpp             |  9 ++++++++
 .../fpga_verilog/verilog_testbench_options.h  |  3 +++
 .../fpga_verilog/verilog_testbench_utils.cpp  |  6 ++++--
 .../fpga_verilog/verilog_testbench_utils.h    |  3 ++-
 .../fpga_verilog/verilog_top_testbench.cpp    | 14 ++++++++-----
 .../src/fpga_verilog/verilog_top_testbench.h  |  3 ++-
 ...onfiguration_chain_example_script.openfpga |  2 +-
 ...uplicated_grid_pin_example_script.openfpga |  2 +-
 .../example_script.openfpga                   |  2 +-
 .../flatten_routing_example_script.openfpga   |  2 +-
 ...generate_testbench_example_script.openfpga |  2 +-
 .../sdc_time_unit_example_script.openfpga     |  2 +-
 19 files changed, 68 insertions(+), 29 deletions(-)

diff --git a/openfpga/src/base/openfpga_verilog.cpp b/openfpga/src/base/openfpga_verilog.cpp
index 1d47055df..481bd2866 100644
--- a/openfpga/src/base/openfpga_verilog.cpp
+++ b/openfpga/src/base/openfpga_verilog.cpp
@@ -69,6 +69,7 @@ int write_verilog_testbench(OpenfpgaContext& openfpga_ctx,
   CommandOptionId opt_print_formal_verification_top_netlist = cmd.option("print_formal_verification_top_netlist");
   CommandOptionId opt_print_preconfig_top_testbench = cmd.option("print_preconfig_top_testbench");
   CommandOptionId opt_print_simulation_ini = cmd.option("print_simulation_ini");
+  CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping");
   CommandOptionId opt_verbose = cmd.option("verbose");
 
   /* This is an intermediate data structure which is designed to modularize the FPGA-Verilog
@@ -81,6 +82,7 @@ int write_verilog_testbench(OpenfpgaContext& openfpga_ctx,
   options.set_print_preconfig_top_testbench(cmd_context.option_enable(cmd, opt_print_preconfig_top_testbench));
   options.set_print_top_testbench(cmd_context.option_enable(cmd, opt_print_top_testbench));
   options.set_print_simulation_ini(cmd_context.option_value(cmd, opt_print_simulation_ini));
+  options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping));
   options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
   
   fpga_verilog_testbench(openfpga_ctx.module_graph(),
diff --git a/openfpga/src/base/openfpga_verilog_command.cpp b/openfpga/src/base/openfpga_verilog_command.cpp
index 71fad80f0..99ee7a319 100644
--- a/openfpga/src/base/openfpga_verilog_command.cpp
+++ b/openfpga/src/base/openfpga_verilog_command.cpp
@@ -89,6 +89,9 @@ ShellCommandId add_openfpga_write_verilog_testbench_command(openfpga::Shell<Open
   CommandOptionId sim_ini_opt = shell_cmd.add_option("print_simulation_ini", false, "Generate a .ini file as an exchangeable file to enable HDL simulations");
   shell_cmd.set_option_require_value(sim_ini_opt, openfpga::OPT_STRING);
 
+  /* Add an option '--explicit_port_mapping' */
+  shell_cmd.add_option("explicit_port_mapping", false, "Use explicit port mapping in Verilog netlists");
+
   /* Add an option '--verbose' */
   shell_cmd.add_option("verbose", false, "Enable verbose output");
   
diff --git a/openfpga/src/fpga_verilog/verilog_api.cpp b/openfpga/src/fpga_verilog/verilog_api.cpp
index 7f82507f5..06ef0e58e 100644
--- a/openfpga/src/fpga_verilog/verilog_api.cpp
+++ b/openfpga/src/fpga_verilog/verilog_api.cpp
@@ -183,7 +183,8 @@ void fpga_verilog_testbench(const ModuleManager& module_manager,
                                        atom_ctx, place_ctx, io_location_map,
                                        netlist_annotation,
                                        netlist_name,
-                                       formal_verification_top_netlist_file_path);
+                                       formal_verification_top_netlist_file_path,
+                                       options.explicit_port_mapping());
   }
 
   if (true == options.print_preconfig_top_testbench()) {
@@ -194,7 +195,8 @@ void fpga_verilog_testbench(const ModuleManager& module_manager,
                                        random_top_testbench_file_path, 
                                        atom_ctx,  
                                        netlist_annotation,
-                                       simulation_setting);
+                                       simulation_setting,
+                                       options.explicit_port_mapping());
   }
 
   /* Generate full testbench for verification, including configuration phase and operating phase */
@@ -209,7 +211,8 @@ void fpga_verilog_testbench(const ModuleManager& module_manager,
                                 netlist_annotation,
                                 netlist_name,
                                 top_testbench_file_path,
-                                simulation_setting);
+                                simulation_setting,
+                                options.explicit_port_mapping());
   }
  
   /* Generate exchangeable files which contains simulation settings */
diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
index a06f58188..741502dfe 100644
--- a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
@@ -96,7 +96,8 @@ static
 void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp, 
                                                            const std::string& reference_verilog_top_name,
                                                            const AtomContext& atom_ctx,
-                                                           const VprNetlistAnnotation& netlist_annotation) {
+                                                           const VprNetlistAnnotation& netlist_annotation,
+                                                           const bool& explicit_port_mapping) {
   /* Validate the file stream */
   valid_file_stream(fp);
 
@@ -118,7 +119,7 @@ void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp,
                                              prefix_to_remove,
                                              std::string(BENCHMARK_PORT_POSTFIX),
                                              atom_ctx, netlist_annotation,
-                                             true);
+                                             explicit_port_mapping);
 
   print_verilog_comment(fp, std::string("----- End reference Benchmark Instanication -------"));
 
@@ -139,7 +140,8 @@ static
 void print_verilog_random_testbench_fpga_instance(std::fstream& fp,
                                                   const std::string& circuit_name,
                                                   const AtomContext& atom_ctx,
-                                                  const VprNetlistAnnotation& netlist_annotation) {
+                                                  const VprNetlistAnnotation& netlist_annotation,
+                                                  const bool& explicit_port_mapping) {
   /* Validate the file stream */
   valid_file_stream(fp);
 
@@ -153,7 +155,7 @@ void print_verilog_random_testbench_fpga_instance(std::fstream& fp,
                                              std::vector<std::string>(),
                                              std::string(FPGA_PORT_POSTFIX),
                                              atom_ctx, netlist_annotation,
-                                             true);
+                                             explicit_port_mapping);
 
   print_verilog_comment(fp, std::string("----- End FPGA Fabric Instanication -------"));
 
@@ -190,7 +192,8 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
                                         const std::string& verilog_fname,
                                         const AtomContext& atom_ctx,
                                         const VprNetlistAnnotation& netlist_annotation,
-                                        const SimulationSetting& simulation_parameters) {
+                                        const SimulationSetting& simulation_parameters,
+                                        const bool& explicit_port_mapping) {
   std::string timer_message = std::string("Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by '") + circuit_name.c_str() + std::string("'");
 
   /* Start time count */
@@ -214,10 +217,14 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
   print_verilog_top_random_testbench_ports(fp, circuit_name, clock_port_names, atom_ctx, netlist_annotation);
 
   /* Call defined top-level module */
-  print_verilog_random_testbench_fpga_instance(fp, circuit_name, atom_ctx, netlist_annotation);
+  print_verilog_random_testbench_fpga_instance(fp, circuit_name,
+                                               atom_ctx, netlist_annotation,
+                                               explicit_port_mapping);
 
   /* Call defined benchmark */
-  print_verilog_top_random_testbench_benchmark_instance(fp, circuit_name, atom_ctx, netlist_annotation);
+  print_verilog_top_random_testbench_benchmark_instance(fp, circuit_name,
+                                                        atom_ctx, netlist_annotation,
+                                                        explicit_port_mapping);
 
   /* Find clock port to be used */
   BasicPort clock_port = generate_verilog_testbench_clock_port(clock_port_names, std::string(DEFAULT_CLOCK_NAME));
diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.h b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.h
index b12072b70..775bc14d4 100644
--- a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.h
+++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.h
@@ -19,7 +19,8 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
                                         const std::string& verilog_fname,
                                         const AtomContext& atom_ctx,
                                         const VprNetlistAnnotation& netlist_annotation,
-                                        const SimulationSetting& simulation_parameters);
+                                        const SimulationSetting& simulation_parameters,
+                                        const bool& explicit_port_mapping);
 
 } /* end namespace openfpga */
 
diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
index 8e1de5cfc..8e577dfb4 100644
--- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
+++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
@@ -385,7 +385,8 @@ void print_verilog_preconfig_top_module(const ModuleManager& module_manager,
                                         const IoLocationMap& io_location_map,
                                         const VprNetlistAnnotation& netlist_annotation, 
                                         const std::string& circuit_name,
-                                        const std::string& verilog_fname) {
+                                        const std::string& verilog_fname,
+                                        const bool& explicit_port_mapping) {
   std::string timer_message = std::string("Write pre-configured FPGA top-level Verilog netlist for design '") + circuit_name + std::string("'");
 
   /* Start time count */
@@ -414,7 +415,8 @@ void print_verilog_preconfig_top_module(const ModuleManager& module_manager,
 
   /* Instanciate FPGA top-level module */
   print_verilog_testbench_fpga_instance(fp, module_manager, top_module, 
-                                        std::string(FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME)); 
+                                        std::string(FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME),
+                                        explicit_port_mapping); 
 
   /* Find clock ports in benchmark */
   std::vector<std::string> benchmark_clock_port_names = find_atom_netlist_clock_port_names(atom_ctx.nlist, netlist_annotation);
diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.h b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.h
index e8efe5f29..9177676fa 100644
--- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.h
+++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.h
@@ -29,7 +29,8 @@ void print_verilog_preconfig_top_module(const ModuleManager& module_manager,
                                         const IoLocationMap& io_location_map,
                                         const VprNetlistAnnotation& netlist_annotation, 
                                         const std::string& circuit_name,
-                                        const std::string& verilog_fname);
+                                        const std::string& verilog_fname,
+                                        const bool& explicit_port_mapping);
 
 } /* end namespace openfpga */
 
diff --git a/openfpga/src/fpga_verilog/verilog_testbench_options.cpp b/openfpga/src/fpga_verilog/verilog_testbench_options.cpp
index 8cd2969f2..9fc6bfd33 100644
--- a/openfpga/src/fpga_verilog/verilog_testbench_options.cpp
+++ b/openfpga/src/fpga_verilog/verilog_testbench_options.cpp
@@ -19,6 +19,7 @@ VerilogTestbenchOption::VerilogTestbenchOption() {
   print_formal_verification_top_netlist_ = false;
   print_top_testbench_ = false;
   simulation_ini_path_.clear();
+  explicit_port_mapping_ = false;
   verbose_output_ = false;
 }
 
@@ -53,6 +54,10 @@ std::string VerilogTestbenchOption::simulation_ini_path() const {
   return simulation_ini_path_;
 }
 
+bool VerilogTestbenchOption::explicit_port_mapping() const {
+  return explicit_port_mapping_;
+}
+
 bool VerilogTestbenchOption::verbose_output() const {
   return verbose_output_;
 }
@@ -97,6 +102,10 @@ void VerilogTestbenchOption::set_print_simulation_ini(const std::string& simulat
   simulation_ini_path_ = simulation_ini_path;
 }
 
+void VerilogTestbenchOption::set_explicit_port_mapping(const bool& enabled) {
+  explicit_port_mapping_ = enabled;
+}
+
 void VerilogTestbenchOption::set_verbose_output(const bool& enabled) {
   verbose_output_ = enabled;
 }
diff --git a/openfpga/src/fpga_verilog/verilog_testbench_options.h b/openfpga/src/fpga_verilog/verilog_testbench_options.h
index d18bfa224..2572e3dee 100644
--- a/openfpga/src/fpga_verilog/verilog_testbench_options.h
+++ b/openfpga/src/fpga_verilog/verilog_testbench_options.h
@@ -29,6 +29,7 @@ class VerilogTestbenchOption {
     bool print_top_testbench() const;
     bool print_simulation_ini() const;
     std::string simulation_ini_path() const;
+    bool explicit_port_mapping() const;
     bool verbose_output() const;
   public: /* Public validator */
     bool validate() const;
@@ -45,6 +46,7 @@ class VerilogTestbenchOption {
     void set_print_preconfig_top_testbench(const bool& enabled);
     void set_print_top_testbench(const bool& enabled);
     void set_print_simulation_ini(const std::string& simulation_ini_path);
+    void set_explicit_port_mapping(const bool& enabled);
     void set_verbose_output(const bool& enabled);
   private: /* Internal Data */
     std::string output_directory_;
@@ -54,6 +56,7 @@ class VerilogTestbenchOption {
     bool print_top_testbench_;
     /* Print simulation ini is enabled only when the path is not empty */
     std::string simulation_ini_path_;
+    bool explicit_port_mapping_;
     bool verbose_output_;
 };
 
diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
index 8b5c741f1..b733c8ddd 100644
--- a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
+++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
@@ -30,7 +30,8 @@ namespace openfpga {
 void print_verilog_testbench_fpga_instance(std::fstream& fp,
                                            const ModuleManager& module_manager,
                                            const ModuleId& top_module,
-                                           const std::string& top_instance_name) {
+                                           const std::string& top_instance_name,
+                                           const bool& explicit_port_mapping) {
   /* Validate the file stream */
   valid_file_stream(fp);
 
@@ -43,7 +44,8 @@ void print_verilog_testbench_fpga_instance(std::fstream& fp,
   /* Use explicit port mapping for a clean instanciation */
   print_verilog_module_instance(fp, module_manager, top_module, 
                                 top_instance_name, 
-                                port2port_name_map, true); 
+                                port2port_name_map,
+                                explicit_port_mapping); 
 
   /* Add an empty line as a splitter */
   fp << std::endl;
diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.h b/openfpga/src/fpga_verilog/verilog_testbench_utils.h
index d51f3b7e8..9ba67f298 100644
--- a/openfpga/src/fpga_verilog/verilog_testbench_utils.h
+++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.h
@@ -26,7 +26,8 @@ constexpr char* OPENFPGA_BENCHMARK_OUT_PORT_PREFIX = "out_";
 void print_verilog_testbench_fpga_instance(std::fstream& fp,
                                            const ModuleManager& module_manager,
                                            const ModuleId& top_module,
-                                           const std::string& top_instance_name);
+                                           const std::string& top_instance_name,
+                                           const bool& explicit_port_mapping);
 
 void print_verilog_testbench_benchmark_instance(std::fstream& fp,
                                                 const std::string& module_name,
diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
index 6a647de35..dc4856cb3 100644
--- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
@@ -446,7 +446,8 @@ static
 void print_verilog_top_testbench_benchmark_instance(std::fstream& fp, 
                                                     const std::string& reference_verilog_top_name,
                                                     const AtomContext& atom_ctx,
-                                                    const VprNetlistAnnotation& netlist_annotation) {
+                                                    const VprNetlistAnnotation& netlist_annotation,
+                                                    const bool& explicit_port_mapping) {
   /* Validate the file stream */
   valid_file_stream(fp);
 
@@ -468,7 +469,7 @@ void print_verilog_top_testbench_benchmark_instance(std::fstream& fp,
                                              prefix_to_remove,
                                              std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX),
                                              atom_ctx, netlist_annotation,
-                                             true);
+                                             explicit_port_mapping);
 
   print_verilog_comment(fp, std::string("----- End reference Benchmark Instanication -------"));
 
@@ -803,7 +804,8 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
                                  const VprNetlistAnnotation& netlist_annotation,
                                  const std::string& circuit_name,
                                  const std::string& verilog_fname,
-                                 const SimulationSetting& simulation_parameters) {
+                                 const SimulationSetting& simulation_parameters,
+                                 const bool& explicit_port_mapping) {
 
   std::string timer_message = std::string("Write autocheck testbench for FPGA top-level Verilog netlist for '") + circuit_name + std::string("'");
 
@@ -856,7 +858,8 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
 
   /* Instanciate FPGA top-level module */
   print_verilog_testbench_fpga_instance(fp, module_manager, top_module, 
-                                        std::string(TOP_TESTBENCH_FPGA_INSTANCE_NAME)); 
+                                        std::string(TOP_TESTBENCH_FPGA_INSTANCE_NAME),
+                                        explicit_port_mapping); 
   
   /* Connect I/Os to benchmark I/Os or constant driver */
   print_verilog_testbench_connect_fpga_ios(fp, module_manager, top_module,
@@ -870,7 +873,8 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
   print_verilog_top_testbench_benchmark_instance(fp, 
                                                  circuit_name,
                                                  atom_ctx,
-                                                 netlist_annotation);
+                                                 netlist_annotation,
+                                                 explicit_port_mapping); 
 
   /* Print tasks used for loading bitstreams */
   print_verilog_top_testbench_load_bitstream_task(fp, sram_orgz_type);
diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.h b/openfpga/src/fpga_verilog/verilog_top_testbench.h
index c0ad77c51..39a2024d1 100644
--- a/openfpga/src/fpga_verilog/verilog_top_testbench.h
+++ b/openfpga/src/fpga_verilog/verilog_top_testbench.h
@@ -33,7 +33,8 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
                                  const VprNetlistAnnotation& netlist_annotation, 
                                  const std::string& circuit_name,
                                  const std::string& verilog_fname,
-                                 const SimulationSetting& simulation_parameters);
+                                 const SimulationSetting& simulation_parameters,
+                                 const bool& explicit_port_mapping);
 
 } /* end namespace openfpga */
 
diff --git a/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga
index 8b523f4ae..11f3ed295 100644
--- a/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga
@@ -49,7 +49,7 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --inc
 #  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini
+write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
 
 # Write the SDC files for PnR backend
 #  - Turn on every options here
diff --git a/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga
index f1dc80820..bcc8d36e3 100644
--- a/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga
@@ -49,7 +49,7 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --inc
 #  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini
+write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
 
 # Write the SDC files for PnR backend
 #  - Turn on every options here
diff --git a/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
index f1dc80820..bcc8d36e3 100644
--- a/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
@@ -49,7 +49,7 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --inc
 #  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini
+write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
 
 # Write the SDC files for PnR backend
 #  - Turn on every options here
diff --git a/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga
index 88be8a878..3210b411f 100644
--- a/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga
@@ -49,7 +49,7 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --inc
 #  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini
+write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
 
 # Write the SDC files for PnR backend
 #  - Turn on every options here
diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga
index 5f7be9ffa..a426a7833 100644
--- a/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga
@@ -45,7 +45,7 @@ build_fabric_bitstream --verbose
 #  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_verilog_testbench --file ./TESTBENCH --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini
+write_verilog_testbench --file ./TESTBENCH --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
 
 # Write the SDC to run timing analysis for a mapped FPGA fabric
 write_analysis_sdc --file ./SDC_analysis
diff --git a/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga
index b4b6ff5ef..6841eb935 100644
--- a/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga
@@ -49,7 +49,7 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --inc
 #  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini
+write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
 
 # Write the SDC files for PnR backend
 #  - Turn on every options here

From f6895fcc148efcd3a708d7d82aaa8fb1017f3d59 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 22 May 2020 14:41:21 -0600
Subject: [PATCH 549/645] update documentation for new options of Verilog
 testbench writer

---
 docs/source/openfpga_shell/openfpga_commands.rst | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/docs/source/openfpga_shell/openfpga_commands.rst b/docs/source/openfpga_shell/openfpga_commands.rst
index 909a6416f..7f72414d0 100644
--- a/docs/source/openfpga_shell/openfpga_commands.rst
+++ b/docs/source/openfpga_shell/openfpga_commands.rst
@@ -150,7 +150,7 @@ FPGA-Verilog
 
   - ``--file`` or ``-f`` Specify the output directory for the Verilog netlists
 
-  - ``--explict_port_mapping`` Use explict port mapping when writing the Verilog netlists
+  - ``--explicit_port_mapping`` Use explicit port mapping when writing the Verilog netlists
 
   - ``--include_timing`` Output timing information to Verilog netlists for primitive modules
  
@@ -178,6 +178,8 @@ FPGA-Verilog
 
   - ``--print_simulation_ini`` Output an exchangeable simulation ini file, which is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
 
+  - ``--explicit_port_mapping`` Use explicit port mapping when writing the Verilog netlists
+
 FPGA-SDC
 ~~~~~~~~
 

From c27d77a418169c24a26042508c293f87ad2d32f0 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 23 May 2020 21:07:44 -0600
Subject: [PATCH 550/645] clean-up documentation for a shallow hierarchy

---
 docs/source/arch_lang/figures/.DS_Store       | Bin 6148 -> 0 bytes
 docs/source/index.rst                         |  18 +++---------------
 .../arch_lang/addon_vpr_syntax.rst            |   0
 .../arch_lang/annotate_vpr_arch.rst           |   0
 .../arch_lang/circuit_library.rst             |   0
 .../arch_lang/circuit_model_examples.rst      |   0
 .../arch_lang/direct_interconnect.rst         |   0
 .../{ => manual}/arch_lang/figures/Buffer.png | Bin
 .../{ => manual}/arch_lang/figures/FF.png     | Bin
 .../arch_lang/figures/Inverter_1.png          | Bin
 .../arch_lang/figures/Tapered_inverter.png    | Bin
 .../arch_lang/figures/ccff_fpga.png           | Bin
 .../arch_lang/figures/global_inout_ports.png  | Bin
 .../arch_lang/figures/global_input_ports.png  | Bin
 .../arch_lang/figures/gpin_ports.png          | Bin
 .../arch_lang/figures/gpio_ports.png          | Bin
 .../arch_lang/figures/gpout_ports.png         | Bin
 .../{ => manual}/arch_lang/figures/iopad.png  | Bin
 .../{ => manual}/arch_lang/figures/lut.png    | Bin
 .../arch_lang/figures/meas_edge.png           | Bin
 .../{ => manual}/arch_lang/figures/mux.png    | Bin
 .../arch_lang/figures/mux1lvl.png             | Bin
 .../arch_lang/figures/pass-gate.png           | Bin
 .../arch_lang/figures/pass_transistor.png     | Bin
 .../arch_lang/figures/point2point_example.png | Bin
 .../figures/point2point_truthtable.png        | Bin
 .../{ => manual}/arch_lang/figures/scff.png   | Bin
 .../{ => manual}/arch_lang/figures/sram.png   | Bin
 .../arch_lang/figures/thru_channel.png        | Bin
 .../{ => manual}/arch_lang/figures/wire.png   | Bin
 .../{ => manual}/arch_lang/generality.rst     |   0
 docs/source/{ => manual}/arch_lang/index.rst  |   5 ++++-
 .../arch_lang/simulation_setting.rst          |   0
 .../arch_lang/technology_library.rst          |   0
 .../fabric_dependent_bitstream.rst            |   0
 .../fpga_bitstream/generic_bitstream.rst      |   0
 .../{ => manual}/fpga_bitstream/index.rst     |   0
 .../fpga_spice/command_line_usage.rst         |   0
 .../fpga_spice/customize_subckt.rst           |   0
 .../fpga_spice/file_organization.rst          |   0
 docs/source/{ => manual}/fpga_spice/index.rst |   0
 .../fpga_spice/spice_simulation.rst           |   0
 .../fpga_verilog/figures/Layout_Diagram.png   | Bin
 .../figures/Verification_step.pdf             |   0
 .../figures/fpga_asap_10x10_final.png         | Bin
 .../figures/fpga_asap_10x10_floorplan.png     | Bin
 .../figures/verification_step.png             | Bin
 .../fpga_verilog/file_organization.rst        |   0
 .../{ => manual}/fpga_verilog/func_verify.rst |   0
 .../{ => manual}/fpga_verilog/index.rst       |   0
 .../{ => manual}/fpga_verilog/sc_flow.rst     |   0
 docs/source/manual/index.rst                  |  18 ++++++++++++++++++
 docs/source/manual/openfpga_flow/index.rst    |  12 ++++++++++++
 .../openfpga_flow}/run_fpga_flow.rst          |   0
 .../openfpga_flow}/run_fpga_task.rst          |   0
 .../{ => manual}/openfpga_shell/index.rst     |   0
 .../openfpga_shell/launch_openfpga_shell.rst  |   0
 .../openfpga_shell/openfpga_commands.rst      |   0
 .../openfpga_shell/openfpga_script.rst        |   0
 docs/source/tutorials/index.rst               |  11 +----------
 60 files changed, 38 insertions(+), 26 deletions(-)
 delete mode 100644 docs/source/arch_lang/figures/.DS_Store
 rename docs/source/{ => manual}/arch_lang/addon_vpr_syntax.rst (100%)
 rename docs/source/{ => manual}/arch_lang/annotate_vpr_arch.rst (100%)
 rename docs/source/{ => manual}/arch_lang/circuit_library.rst (100%)
 rename docs/source/{ => manual}/arch_lang/circuit_model_examples.rst (100%)
 rename docs/source/{ => manual}/arch_lang/direct_interconnect.rst (100%)
 rename docs/source/{ => manual}/arch_lang/figures/Buffer.png (100%)
 rename docs/source/{ => manual}/arch_lang/figures/FF.png (100%)
 rename docs/source/{ => manual}/arch_lang/figures/Inverter_1.png (100%)
 rename docs/source/{ => manual}/arch_lang/figures/Tapered_inverter.png (100%)
 rename docs/source/{ => manual}/arch_lang/figures/ccff_fpga.png (100%)
 rename docs/source/{ => manual}/arch_lang/figures/global_inout_ports.png (100%)
 rename docs/source/{ => manual}/arch_lang/figures/global_input_ports.png (100%)
 rename docs/source/{ => manual}/arch_lang/figures/gpin_ports.png (100%)
 rename docs/source/{ => manual}/arch_lang/figures/gpio_ports.png (100%)
 rename docs/source/{ => manual}/arch_lang/figures/gpout_ports.png (100%)
 rename docs/source/{ => manual}/arch_lang/figures/iopad.png (100%)
 rename docs/source/{ => manual}/arch_lang/figures/lut.png (100%)
 rename docs/source/{ => manual}/arch_lang/figures/meas_edge.png (100%)
 rename docs/source/{ => manual}/arch_lang/figures/mux.png (100%)
 rename docs/source/{ => manual}/arch_lang/figures/mux1lvl.png (100%)
 rename docs/source/{ => manual}/arch_lang/figures/pass-gate.png (100%)
 rename docs/source/{ => manual}/arch_lang/figures/pass_transistor.png (100%)
 rename docs/source/{ => manual}/arch_lang/figures/point2point_example.png (100%)
 rename docs/source/{ => manual}/arch_lang/figures/point2point_truthtable.png (100%)
 rename docs/source/{ => manual}/arch_lang/figures/scff.png (100%)
 rename docs/source/{ => manual}/arch_lang/figures/sram.png (100%)
 rename docs/source/{ => manual}/arch_lang/figures/thru_channel.png (100%)
 rename docs/source/{ => manual}/arch_lang/figures/wire.png (100%)
 rename docs/source/{ => manual}/arch_lang/generality.rst (100%)
 rename docs/source/{ => manual}/arch_lang/index.rst (69%)
 rename docs/source/{ => manual}/arch_lang/simulation_setting.rst (100%)
 rename docs/source/{ => manual}/arch_lang/technology_library.rst (100%)
 rename docs/source/{ => manual}/fpga_bitstream/fabric_dependent_bitstream.rst (100%)
 rename docs/source/{ => manual}/fpga_bitstream/generic_bitstream.rst (100%)
 rename docs/source/{ => manual}/fpga_bitstream/index.rst (100%)
 rename docs/source/{ => manual}/fpga_spice/command_line_usage.rst (100%)
 rename docs/source/{ => manual}/fpga_spice/customize_subckt.rst (100%)
 rename docs/source/{ => manual}/fpga_spice/file_organization.rst (100%)
 rename docs/source/{ => manual}/fpga_spice/index.rst (100%)
 rename docs/source/{ => manual}/fpga_spice/spice_simulation.rst (100%)
 rename docs/source/{ => manual}/fpga_verilog/figures/Layout_Diagram.png (100%)
 rename docs/source/{ => manual}/fpga_verilog/figures/Verification_step.pdf (100%)
 rename docs/source/{ => manual}/fpga_verilog/figures/fpga_asap_10x10_final.png (100%)
 rename docs/source/{ => manual}/fpga_verilog/figures/fpga_asap_10x10_floorplan.png (100%)
 rename docs/source/{ => manual}/fpga_verilog/figures/verification_step.png (100%)
 rename docs/source/{ => manual}/fpga_verilog/file_organization.rst (100%)
 rename docs/source/{ => manual}/fpga_verilog/func_verify.rst (100%)
 rename docs/source/{ => manual}/fpga_verilog/index.rst (100%)
 rename docs/source/{ => manual}/fpga_verilog/sc_flow.rst (100%)
 create mode 100644 docs/source/manual/index.rst
 create mode 100644 docs/source/manual/openfpga_flow/index.rst
 rename docs/source/{tutorials => manual/openfpga_flow}/run_fpga_flow.rst (100%)
 rename docs/source/{tutorials => manual/openfpga_flow}/run_fpga_task.rst (100%)
 rename docs/source/{ => manual}/openfpga_shell/index.rst (100%)
 rename docs/source/{ => manual}/openfpga_shell/launch_openfpga_shell.rst (100%)
 rename docs/source/{ => manual}/openfpga_shell/openfpga_commands.rst (100%)
 rename docs/source/{ => manual}/openfpga_shell/openfpga_script.rst (100%)

diff --git a/docs/source/arch_lang/figures/.DS_Store b/docs/source/arch_lang/figures/.DS_Store
deleted file mode 100644
index 5008ddfcf53c02e82d7eee2e57c38e5672ef89f6..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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z0ynLxE!0092;Krf2c+FF_Fe*7ECH>lEfg7;MkzE(HCqgga^y>{tEnwC%0;vJ&^%eQ
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diff --git a/docs/source/index.rst b/docs/source/index.rst
index d3452b771..9a317c924 100644
--- a/docs/source/index.rst
+++ b/docs/source/index.rst
@@ -13,27 +13,15 @@ Welcome to OpenFPGA's documentation!
 
 .. toctree::
    :maxdepth: 2
-   :caption: Getting Started
+   :caption: Tutorials
 
    tutorials/index
 
 .. toctree::
    :maxdepth: 2
-   :caption: Architecture Description Language
+   :caption: User Manual
 
-   arch_lang/index
-
-.. toctree::
-   :maxdepth: 2
-   :caption: OpenFPGA Tools
-
-   openfpga_shell/index
-
-   fpga_spice/index
-
-   fpga_verilog/index
-
-   fpga_bitstream/index
+   manual/index
 
 .. toctree::
    :maxdepth: 2
diff --git a/docs/source/arch_lang/addon_vpr_syntax.rst b/docs/source/manual/arch_lang/addon_vpr_syntax.rst
similarity index 100%
rename from docs/source/arch_lang/addon_vpr_syntax.rst
rename to docs/source/manual/arch_lang/addon_vpr_syntax.rst
diff --git a/docs/source/arch_lang/annotate_vpr_arch.rst b/docs/source/manual/arch_lang/annotate_vpr_arch.rst
similarity index 100%
rename from docs/source/arch_lang/annotate_vpr_arch.rst
rename to docs/source/manual/arch_lang/annotate_vpr_arch.rst
diff --git a/docs/source/arch_lang/circuit_library.rst b/docs/source/manual/arch_lang/circuit_library.rst
similarity index 100%
rename from docs/source/arch_lang/circuit_library.rst
rename to docs/source/manual/arch_lang/circuit_library.rst
diff --git a/docs/source/arch_lang/circuit_model_examples.rst b/docs/source/manual/arch_lang/circuit_model_examples.rst
similarity index 100%
rename from docs/source/arch_lang/circuit_model_examples.rst
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diff --git a/docs/source/arch_lang/direct_interconnect.rst b/docs/source/manual/arch_lang/direct_interconnect.rst
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diff --git a/docs/source/arch_lang/figures/Buffer.png b/docs/source/manual/arch_lang/figures/Buffer.png
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rename from docs/source/arch_lang/figures/Inverter_1.png
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diff --git a/docs/source/arch_lang/figures/ccff_fpga.png b/docs/source/manual/arch_lang/figures/ccff_fpga.png
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diff --git a/docs/source/arch_lang/figures/gpio_ports.png b/docs/source/manual/arch_lang/figures/gpio_ports.png
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rename from docs/source/arch_lang/figures/gpio_ports.png
rename to docs/source/manual/arch_lang/figures/gpio_ports.png
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rename from docs/source/arch_lang/figures/gpout_ports.png
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diff --git a/docs/source/arch_lang/figures/iopad.png b/docs/source/manual/arch_lang/figures/iopad.png
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diff --git a/docs/source/arch_lang/figures/lut.png b/docs/source/manual/arch_lang/figures/lut.png
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rename to docs/source/manual/arch_lang/figures/lut.png
diff --git a/docs/source/arch_lang/figures/meas_edge.png b/docs/source/manual/arch_lang/figures/meas_edge.png
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diff --git a/docs/source/arch_lang/figures/mux.png b/docs/source/manual/arch_lang/figures/mux.png
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rename from docs/source/arch_lang/figures/mux.png
rename to docs/source/manual/arch_lang/figures/mux.png
diff --git a/docs/source/arch_lang/figures/mux1lvl.png b/docs/source/manual/arch_lang/figures/mux1lvl.png
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rename from docs/source/arch_lang/figures/mux1lvl.png
rename to docs/source/manual/arch_lang/figures/mux1lvl.png
diff --git a/docs/source/arch_lang/figures/pass-gate.png b/docs/source/manual/arch_lang/figures/pass-gate.png
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rename from docs/source/arch_lang/figures/pass-gate.png
rename to docs/source/manual/arch_lang/figures/pass-gate.png
diff --git a/docs/source/arch_lang/figures/pass_transistor.png b/docs/source/manual/arch_lang/figures/pass_transistor.png
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rename from docs/source/arch_lang/figures/pass_transistor.png
rename to docs/source/manual/arch_lang/figures/pass_transistor.png
diff --git a/docs/source/arch_lang/figures/point2point_example.png b/docs/source/manual/arch_lang/figures/point2point_example.png
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rename from docs/source/arch_lang/figures/point2point_example.png
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diff --git a/docs/source/arch_lang/figures/point2point_truthtable.png b/docs/source/manual/arch_lang/figures/point2point_truthtable.png
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rename from docs/source/arch_lang/figures/point2point_truthtable.png
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diff --git a/docs/source/arch_lang/figures/scff.png b/docs/source/manual/arch_lang/figures/scff.png
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rename from docs/source/arch_lang/figures/scff.png
rename to docs/source/manual/arch_lang/figures/scff.png
diff --git a/docs/source/arch_lang/figures/sram.png b/docs/source/manual/arch_lang/figures/sram.png
similarity index 100%
rename from docs/source/arch_lang/figures/sram.png
rename to docs/source/manual/arch_lang/figures/sram.png
diff --git a/docs/source/arch_lang/figures/thru_channel.png b/docs/source/manual/arch_lang/figures/thru_channel.png
similarity index 100%
rename from docs/source/arch_lang/figures/thru_channel.png
rename to docs/source/manual/arch_lang/figures/thru_channel.png
diff --git a/docs/source/arch_lang/figures/wire.png b/docs/source/manual/arch_lang/figures/wire.png
similarity index 100%
rename from docs/source/arch_lang/figures/wire.png
rename to docs/source/manual/arch_lang/figures/wire.png
diff --git a/docs/source/arch_lang/generality.rst b/docs/source/manual/arch_lang/generality.rst
similarity index 100%
rename from docs/source/arch_lang/generality.rst
rename to docs/source/manual/arch_lang/generality.rst
diff --git a/docs/source/arch_lang/index.rst b/docs/source/manual/arch_lang/index.rst
similarity index 69%
rename from docs/source/arch_lang/index.rst
rename to docs/source/manual/arch_lang/index.rst
index 52fd17caa..b7e33de15 100644
--- a/docs/source/arch_lang/index.rst
+++ b/docs/source/manual/arch_lang/index.rst
@@ -1,5 +1,8 @@
+OpenFPGA Architecture Description
+---------------------------------
+
 .. _arch_lang:
-   Extended FPGA Architecture Description Language
+   OpenFPGA Architecture Description
  
 .. toctree::
    :maxdepth: 2
diff --git a/docs/source/arch_lang/simulation_setting.rst b/docs/source/manual/arch_lang/simulation_setting.rst
similarity index 100%
rename from docs/source/arch_lang/simulation_setting.rst
rename to docs/source/manual/arch_lang/simulation_setting.rst
diff --git a/docs/source/arch_lang/technology_library.rst b/docs/source/manual/arch_lang/technology_library.rst
similarity index 100%
rename from docs/source/arch_lang/technology_library.rst
rename to docs/source/manual/arch_lang/technology_library.rst
diff --git a/docs/source/fpga_bitstream/fabric_dependent_bitstream.rst b/docs/source/manual/fpga_bitstream/fabric_dependent_bitstream.rst
similarity index 100%
rename from docs/source/fpga_bitstream/fabric_dependent_bitstream.rst
rename to docs/source/manual/fpga_bitstream/fabric_dependent_bitstream.rst
diff --git a/docs/source/fpga_bitstream/generic_bitstream.rst b/docs/source/manual/fpga_bitstream/generic_bitstream.rst
similarity index 100%
rename from docs/source/fpga_bitstream/generic_bitstream.rst
rename to docs/source/manual/fpga_bitstream/generic_bitstream.rst
diff --git a/docs/source/fpga_bitstream/index.rst b/docs/source/manual/fpga_bitstream/index.rst
similarity index 100%
rename from docs/source/fpga_bitstream/index.rst
rename to docs/source/manual/fpga_bitstream/index.rst
diff --git a/docs/source/fpga_spice/command_line_usage.rst b/docs/source/manual/fpga_spice/command_line_usage.rst
similarity index 100%
rename from docs/source/fpga_spice/command_line_usage.rst
rename to docs/source/manual/fpga_spice/command_line_usage.rst
diff --git a/docs/source/fpga_spice/customize_subckt.rst b/docs/source/manual/fpga_spice/customize_subckt.rst
similarity index 100%
rename from docs/source/fpga_spice/customize_subckt.rst
rename to docs/source/manual/fpga_spice/customize_subckt.rst
diff --git a/docs/source/fpga_spice/file_organization.rst b/docs/source/manual/fpga_spice/file_organization.rst
similarity index 100%
rename from docs/source/fpga_spice/file_organization.rst
rename to docs/source/manual/fpga_spice/file_organization.rst
diff --git a/docs/source/fpga_spice/index.rst b/docs/source/manual/fpga_spice/index.rst
similarity index 100%
rename from docs/source/fpga_spice/index.rst
rename to docs/source/manual/fpga_spice/index.rst
diff --git a/docs/source/fpga_spice/spice_simulation.rst b/docs/source/manual/fpga_spice/spice_simulation.rst
similarity index 100%
rename from docs/source/fpga_spice/spice_simulation.rst
rename to docs/source/manual/fpga_spice/spice_simulation.rst
diff --git a/docs/source/fpga_verilog/figures/Layout_Diagram.png b/docs/source/manual/fpga_verilog/figures/Layout_Diagram.png
similarity index 100%
rename from docs/source/fpga_verilog/figures/Layout_Diagram.png
rename to docs/source/manual/fpga_verilog/figures/Layout_Diagram.png
diff --git a/docs/source/fpga_verilog/figures/Verification_step.pdf b/docs/source/manual/fpga_verilog/figures/Verification_step.pdf
similarity index 100%
rename from docs/source/fpga_verilog/figures/Verification_step.pdf
rename to docs/source/manual/fpga_verilog/figures/Verification_step.pdf
diff --git a/docs/source/fpga_verilog/figures/fpga_asap_10x10_final.png b/docs/source/manual/fpga_verilog/figures/fpga_asap_10x10_final.png
similarity index 100%
rename from docs/source/fpga_verilog/figures/fpga_asap_10x10_final.png
rename to docs/source/manual/fpga_verilog/figures/fpga_asap_10x10_final.png
diff --git a/docs/source/fpga_verilog/figures/fpga_asap_10x10_floorplan.png b/docs/source/manual/fpga_verilog/figures/fpga_asap_10x10_floorplan.png
similarity index 100%
rename from docs/source/fpga_verilog/figures/fpga_asap_10x10_floorplan.png
rename to docs/source/manual/fpga_verilog/figures/fpga_asap_10x10_floorplan.png
diff --git a/docs/source/fpga_verilog/figures/verification_step.png b/docs/source/manual/fpga_verilog/figures/verification_step.png
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rename from docs/source/fpga_verilog/figures/verification_step.png
rename to docs/source/manual/fpga_verilog/figures/verification_step.png
diff --git a/docs/source/fpga_verilog/file_organization.rst b/docs/source/manual/fpga_verilog/file_organization.rst
similarity index 100%
rename from docs/source/fpga_verilog/file_organization.rst
rename to docs/source/manual/fpga_verilog/file_organization.rst
diff --git a/docs/source/fpga_verilog/func_verify.rst b/docs/source/manual/fpga_verilog/func_verify.rst
similarity index 100%
rename from docs/source/fpga_verilog/func_verify.rst
rename to docs/source/manual/fpga_verilog/func_verify.rst
diff --git a/docs/source/fpga_verilog/index.rst b/docs/source/manual/fpga_verilog/index.rst
similarity index 100%
rename from docs/source/fpga_verilog/index.rst
rename to docs/source/manual/fpga_verilog/index.rst
diff --git a/docs/source/fpga_verilog/sc_flow.rst b/docs/source/manual/fpga_verilog/sc_flow.rst
similarity index 100%
rename from docs/source/fpga_verilog/sc_flow.rst
rename to docs/source/manual/fpga_verilog/sc_flow.rst
diff --git a/docs/source/manual/index.rst b/docs/source/manual/index.rst
new file mode 100644
index 000000000..65e5b13bb
--- /dev/null
+++ b/docs/source/manual/index.rst
@@ -0,0 +1,18 @@
+.. _tools:
+   OpenFPGA tools
+ 
+.. toctree::
+   :maxdepth: 2
+
+   openfpga_flow/index
+
+   arch_lang/index
+
+   openfpga_shell/index
+
+   fpga_spice/index
+
+   fpga_verilog/index
+
+   fpga_bitstream/index
+
diff --git a/docs/source/manual/openfpga_flow/index.rst b/docs/source/manual/openfpga_flow/index.rst
new file mode 100644
index 000000000..ec691b7fc
--- /dev/null
+++ b/docs/source/manual/openfpga_flow/index.rst
@@ -0,0 +1,12 @@
+OpenFPGA Flow
+-------------
+
+.. _openfpga_flow:
+   OpenFPGA Flow
+ 
+.. toctree::
+   :maxdepth: 2
+
+   run_fpga_flow
+
+   run_fpga_task
diff --git a/docs/source/tutorials/run_fpga_flow.rst b/docs/source/manual/openfpga_flow/run_fpga_flow.rst
similarity index 100%
rename from docs/source/tutorials/run_fpga_flow.rst
rename to docs/source/manual/openfpga_flow/run_fpga_flow.rst
diff --git a/docs/source/tutorials/run_fpga_task.rst b/docs/source/manual/openfpga_flow/run_fpga_task.rst
similarity index 100%
rename from docs/source/tutorials/run_fpga_task.rst
rename to docs/source/manual/openfpga_flow/run_fpga_task.rst
diff --git a/docs/source/openfpga_shell/index.rst b/docs/source/manual/openfpga_shell/index.rst
similarity index 100%
rename from docs/source/openfpga_shell/index.rst
rename to docs/source/manual/openfpga_shell/index.rst
diff --git a/docs/source/openfpga_shell/launch_openfpga_shell.rst b/docs/source/manual/openfpga_shell/launch_openfpga_shell.rst
similarity index 100%
rename from docs/source/openfpga_shell/launch_openfpga_shell.rst
rename to docs/source/manual/openfpga_shell/launch_openfpga_shell.rst
diff --git a/docs/source/openfpga_shell/openfpga_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands.rst
similarity index 100%
rename from docs/source/openfpga_shell/openfpga_commands.rst
rename to docs/source/manual/openfpga_shell/openfpga_commands.rst
diff --git a/docs/source/openfpga_shell/openfpga_script.rst b/docs/source/manual/openfpga_shell/openfpga_script.rst
similarity index 100%
rename from docs/source/openfpga_shell/openfpga_script.rst
rename to docs/source/manual/openfpga_shell/openfpga_script.rst
diff --git a/docs/source/tutorials/index.rst b/docs/source/tutorials/index.rst
index e1cae21ac..ea844c11c 100644
--- a/docs/source/tutorials/index.rst
+++ b/docs/source/tutorials/index.rst
@@ -1,5 +1,5 @@
 .. _tutorials:
-   Getting Started
+   Tutorials
  
 .. toctree::
    :maxdepth: 2
@@ -7,12 +7,3 @@
    compile
 
    eda_flow
-
-   run_fpga_flow
-
-   run_fpga_task
-
-   
-  
-
-   

From cae7fe0fedd60c0495c0131e2e1b1ff1bf247efe Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 23 May 2020 21:14:32 -0600
Subject: [PATCH 551/645] minor fix on the manual subtree

---
 docs/source/manual/openfpga_shell/index.rst | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/docs/source/manual/openfpga_shell/index.rst b/docs/source/manual/openfpga_shell/index.rst
index 0aa515e23..24512f67d 100644
--- a/docs/source/manual/openfpga_shell/index.rst
+++ b/docs/source/manual/openfpga_shell/index.rst
@@ -1,5 +1,5 @@
-OpenFPGA Interface
-------------------
+OpenFPGA Shell
+--------------
 
 .. _openfpga_shell:
    OpenFPGA Shell

From c5a3e44e61ef0e3cdcef9e295c23a8d2bd46a7f0 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 24 May 2020 16:29:57 -0600
Subject: [PATCH 552/645] Update Verilog fabric netlist documentation

---
 .../manual/fpga_verilog/fabric_netlist.rst    | 132 ++++++++++++++++++
 .../figures/fabric_netlist_hierarchy.png      | Bin 0 -> 49128 bytes
 .../fpga_verilog/figures/generic_fabric.png   | Bin 0 -> 121309 bytes
 .../manual/fpga_verilog/file_organization.rst |  20 ---
 docs/source/manual/fpga_verilog/index.rst     |   2 +-
 .../openfpga_shell/openfpga_commands.rst      |   2 +
 6 files changed, 135 insertions(+), 21 deletions(-)
 create mode 100644 docs/source/manual/fpga_verilog/fabric_netlist.rst
 create mode 100644 docs/source/manual/fpga_verilog/figures/fabric_netlist_hierarchy.png
 create mode 100644 docs/source/manual/fpga_verilog/figures/generic_fabric.png
 delete mode 100644 docs/source/manual/fpga_verilog/file_organization.rst

diff --git a/docs/source/manual/fpga_verilog/fabric_netlist.rst b/docs/source/manual/fpga_verilog/fabric_netlist.rst
new file mode 100644
index 000000000..7ce403300
--- /dev/null
+++ b/docs/source/manual/fpga_verilog/fabric_netlist.rst
@@ -0,0 +1,132 @@
+.. _fabric_netlists:
+
+Fabric Netlists
+---------------
+
+In this paper, we will introduce the hierarchy, dependency and functionality of each Verilog netlist, which are generated to model the FPGA fabric.
+
+.. note:: These netlists are automatically generated by the OpenFPGA command ``write_fabric_verilog``. See :ref:`openfpga_verilog_commands` for its detailed usage. 
+
+All the generated Verilog netlists are located in the directory as you specify in the OpenFPGA command ``write_fabric_verilog``.
+Inside the directory, the Verilog netlists are organized as illustrated in :numref:`fig_fabric_netlist_hierarchy`.
+
+.. _fig_fabric_netlist_hierarchy:
+
+.. figure:: ./figures/fabric_netlist_hierarchy.png
+   :scale: 90%
+
+   Hierarchy of Verilog netlists modeling a FPGA fabric
+
+.. _fig_generic_fabric:
+
+.. figure:: ./figures/generic_fabric.png
+   :scale: 80%
+
+   An illustrative FPGA fabric modelled by the Verilog netlists
+
+Top-level Netlists
+~~~~~~~~~~~~~~~~~~
+
+.. option:: fabric_netlists.v
+
+   This file includes all the related Verilog netlists that are used by the ``fpga_top.v``.
+   This file is created to simplify the netlist addition for HDL simulator and backend tools.
+   This is the only file you need to add to a simulator or backend project.
+
+   .. note:: User-defined (external) Verilog netlists will be included in this file.
+
+.. option:: fpga_top.v
+
+   This netlist contains the top-level module of the fpga fabric, corresponding to the fabric shown in :numref:`fig_generic_fabric`.
+
+.. option:: fpga_defines.v
+
+   This file includes pre-processing flags required by the ``fpga_top.v``, to smooth HDL simulation.
+   It will include the folliwng pre-procesing flags:
+   
+   - ```define ENABLE_TIMING`` When enabled, all the delay values defined in primitive Verilog modules will be considered in compilation. This flag is added when ``--include_timing`` option is enabled when calling the ``write_fabric_verilog`` command. 
+
+   .. note:: We strongly recommend users to turn on this flag as it can help simulators to converge quickly.
+
+   - ```define ENABLE_SIGNAL_INITIALIZATION`` When enabled, all the outputs of primitive Verilog modules will be initialized with a random value. This flag is added when ``--include_signal_init`` option is enabled when calling the ``write_fabric_verilog`` command. 
+
+   .. note:: We strongly recommend users to turn on this flag as it can help simulators to converge quickly.
+   
+   - ```define ICARUS_SIMULATOR`` When enabled, Verilog netlists are generated to be compatible with the syntax required by `icarus iVerilog simulator`__. This flag is added when ``--support_icarus_simulator`` option is enabled when calling the ``write_fabric_verilog`` command. 
+
+   .. warning:: Please disable this flag if you are not using icarus iVerilog simulator.
+
+__ iverilog_website_
+
+.. _iverilog_website: http://iverilog.icarus.com/
+
+Logic Blocks
+~~~~~~~~~~~~
+This sub-directory contains all the Verilog modules modeling configurable logic blocks, heterogeneous blocks as well as I/O blocks.
+Take the example in :numref:`fig_generic_fabric`, the modules are CLBs, DSP blocks, I/Os and Block RAMs.
+
+.. option:: <physical_tile_name>.v
+
+   For each ``<physical_tile>`` defined in the VPR architecture description, a Verilog netlist will be generated to model its internal structure.
+
+   .. note:: For I/O blocks, separated ``<physical_tile_name>.v`` will be generated for each side of a FPGA fabric.
+
+.. option:: <logical_tile_name>.v
+
+   For each root ``pb_type`` defined in the ``<complexblock>`` of VPR architecture description, a Verilog netlist will be generated to model its internal structure.
+
+Routing Blocks
+~~~~~~~~~~~~~~
+This sub-directory contains all the Verilog modules modeling Switch Blocks (SBs) and Connection Blocks (CBs).
+Take the example in :numref:`fig_generic_fabric`, the modules are the Switch Blocks, X- and Y- Connection Blocks of a tile.
+
+.. option:: sb_<x>_<y>.v
+
+  For each unique Switch Block (SB) created by VPR routing resource graph generator, a Verilog netlist will be generated. The ``<x>`` and ``<y>`` denote the coordinate of the Switch Block in the FPGA fabric.
+
+.. option:: cbx_<x>_<y>.v
+
+  For each unique X-direction Connection Block (CBX) created by VPR routing resource graph generator, a Verilog netlist will be generated. The ``<x>`` and ``<y>`` denote the coordinate of the Connection Block in the FPGA fabric.
+
+.. option:: cby_<x>_<y>.v
+
+  For each unique Y-direction Connection Block (CBY) created by VPR routing resource graph generator, a Verilog netlist will be generated. The ``<x>`` and ``<y>`` denote the coordinate of the Connection Block in the FPGA fabric.
+
+Primitive Modules
+~~~~~~~~~~~~~~~~~
+This sub-directory contains all the primitive Verilog modules, which are used to build the logic blocks and routing blocks.
+
+.. option:: luts.v
+
+  Verilog modules for all the Look-Up Tables (LUTs), which are defined as ``<circuit_model name="lut">`` of OpenFPGA architecture description. See details in :ref:`circuit_library`.
+
+.. option:: wires.v
+
+  Verilog modules for all the routing wires, which are defined as ``<circuit_model name="wire|chan_wire">`` of OpenFPGA architecture description. See details in :ref:`circuit_library`.
+
+.. option:: memories.v
+
+  Verilog modules for all the configurable memories, which are defined as ``<circuit_model name="ccff|sram">`` of OpenFPGA architecture description. See details in :ref:`circuit_library`.
+
+.. option:: muxes.v
+
+  Verilog modules for all the routing multiplexers, which are defined as ``<circuit_model name="mux">`` of OpenFPGA architecture description. See details in :ref:`circuit_library`.
+
+  .. note:: multiplexers used in Look-Up Tables are also defined in this netlist.
+
+.. option:: inv_buf_passgate.v
+
+  Verilog modules for all the inverters, buffers and pass-gate logics, which are defined as ``<circuit_model name="inv_buf|pass_gate">`` of OpenFPGA architecture description. See details in :ref:`circuit_library`.
+
+.. option:: local_encoder.v
+
+  Verilog modules for all the encoders and decoders, which are created when routing multiplexers are defined to include local encoders. See details in :ref:`circuit_model_examples`.
+
+.. option:: user_defined_templates.v
+
+  This is a template netlist, which users can refer to when writing up their user-defined Verilog modules.
+  The user-defined Verilog modules are those ``<circuit_model>`` in the OpenFPGA architecture description with a specific ``verilog_netlist`` path.
+  It contains Verilog modules with ports declaration (compatible to other netlists that are auto-generated by OpenFPGA) but without any functionality.
+  This file is created only when the option ``--print_user_defined_template`` is enabled when calling the ``write_fabric_verilog`` command. 
+
+  .. warning:: Do not include this netlist in simulation without any modification to its content!
diff --git a/docs/source/manual/fpga_verilog/figures/fabric_netlist_hierarchy.png b/docs/source/manual/fpga_verilog/figures/fabric_netlist_hierarchy.png
new file mode 100644
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diff --git a/docs/source/manual/fpga_verilog/file_organization.rst b/docs/source/manual/fpga_verilog/file_organization.rst
deleted file mode 100644
index 181be2295..000000000
--- a/docs/source/manual/fpga_verilog/file_organization.rst
+++ /dev/null
@@ -1,20 +0,0 @@
-Hierarchy of Verilog Output Files
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-All the generated Verilog Netlists are located in the <verilog_dir>/SRC as you specify in the command-line options. Under the <verilog_dir>/SRC, FPGA-Verilog creates the top file name_top.v and some folders: lb (logic blocks), routing and sub_modules. 
-
-.. csv-table:: Folder hierarchy of FPGA-Verilog
-   :header: "File/Folder", "Content" 
-   :widths: 10, 20
-        
-   "name_top.v", "Contains the top module and calls all the other .v files"   
-   "name.bitstream", "Only if --fpga_verilog_print_top_testbench or --fpga_verilog_print_top_auto_testbench is chosen. Contains the bitstream programming the generated FPGA."
-   "name_top_tb.v", "Only if --fpga_verilog_print_top_testbench. Contains a testbench used for the simulation."
-   "name_autocheck_top_tb.v", "Only if --fpga_verilog_print_autocheck_top_testbench is chosen. Contains a testbench used for the simulation."
-   "name_formal_random_top_tb.v", "Only if --fpga_verilog_print_formal_verification_top_netlist is chosen. Contains a testbench used for the simulation."
-   "name_top_formal_verification.v", "Only if --fpga_verilog_print_formal_verification_top_netlist is chosen. Contains a top fil used for formal verification and by name_formal_random_top_tb.v."
-   "fpga_defines.v", "Contains all the defines set as 'include_timing'"
-   "name_include_netlists.v", "Contains all the netlists and defines paths used for the simulation."
-   "lb", "Logic Block. Contains all the CLBs. The logic_block.v includes all the CLB and is called by the top module afterward."
-   "routing", "Contains all the routing in the circuit. You can find in it the Switch Boxes, the Connection Blocks and the routing needed to connect the different blocks. The routing.v file packs them all and is called by the top module."
-   "sub_modules", "Contains the modules generated by the flow to build the CLBs."
diff --git a/docs/source/manual/fpga_verilog/index.rst b/docs/source/manual/fpga_verilog/index.rst
index 85d278ae6..2940943c4 100644
--- a/docs/source/manual/fpga_verilog/index.rst
+++ b/docs/source/manual/fpga_verilog/index.rst
@@ -7,7 +7,7 @@ FPGA-Verilog
 .. toctree::
    :maxdepth: 2
   
-   file_organization
+   fabric_netlist
  
    func_verify
 
diff --git a/docs/source/manual/openfpga_shell/openfpga_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands.rst
index 7f72414d0..1ac4ed69b 100644
--- a/docs/source/manual/openfpga_shell/openfpga_commands.rst
+++ b/docs/source/manual/openfpga_shell/openfpga_commands.rst
@@ -140,6 +140,8 @@ FPGA-Bitstream
   - ``--file`` or ``-f`` Output the fabric bitstream to an plain text file (only 0 or 1)
 
   - ``--verbose`` Show verbose log
+
+.. _openfpga_verilog_commands:
   
 FPGA-Verilog
 ~~~~~~~~~~~~

From dcce782a468358da21045792462c61955311c3da Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 24 May 2020 18:01:34 -0600
Subject: [PATCH 553/645] update documentation about Verilog testbenches

---
 .../manual/fpga_verilog/fabric_netlist.rst    |   4 +-
 .../fpga_verilog/figures/preconfig_module.png | Bin 0 -> 26664 bytes
 .../figures/verilog_testbench_hierarchy.png   | Bin 0 -> 32203 bytes
 .../verilog_testbench_organization.png        | Bin 0 -> 290654 bytes
 .../manual/fpga_verilog/func_verify.rst       |  12 ---
 docs/source/manual/fpga_verilog/index.rst     |   2 +-
 docs/source/manual/fpga_verilog/testbench.rst |  92 ++++++++++++++++++
 7 files changed, 95 insertions(+), 15 deletions(-)
 create mode 100644 docs/source/manual/fpga_verilog/figures/preconfig_module.png
 create mode 100644 docs/source/manual/fpga_verilog/figures/verilog_testbench_hierarchy.png
 create mode 100644 docs/source/manual/fpga_verilog/figures/verilog_testbench_organization.png
 delete mode 100644 docs/source/manual/fpga_verilog/func_verify.rst
 create mode 100644 docs/source/manual/fpga_verilog/testbench.rst

diff --git a/docs/source/manual/fpga_verilog/fabric_netlist.rst b/docs/source/manual/fpga_verilog/fabric_netlist.rst
index 7ce403300..46c8a934b 100644
--- a/docs/source/manual/fpga_verilog/fabric_netlist.rst
+++ b/docs/source/manual/fpga_verilog/fabric_netlist.rst
@@ -3,7 +3,7 @@
 Fabric Netlists
 ---------------
 
-In this paper, we will introduce the hierarchy, dependency and functionality of each Verilog netlist, which are generated to model the FPGA fabric.
+In this part, we will introduce the hierarchy, dependency and functionality of each Verilog netlist, which are generated to model the FPGA fabric.
 
 .. note:: These netlists are automatically generated by the OpenFPGA command ``write_fabric_verilog``. See :ref:`openfpga_verilog_commands` for its detailed usage. 
 
@@ -33,7 +33,7 @@ Top-level Netlists
    This file is created to simplify the netlist addition for HDL simulator and backend tools.
    This is the only file you need to add to a simulator or backend project.
 
-   .. note:: User-defined (external) Verilog netlists will be included in this file.
+   .. note:: User-defined (external) Verilog netlists are included in this file.
 
 .. option:: fpga_top.v
 
diff --git a/docs/source/manual/fpga_verilog/figures/preconfig_module.png b/docs/source/manual/fpga_verilog/figures/preconfig_module.png
new file mode 100644
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diff --git a/docs/source/manual/fpga_verilog/figures/verilog_testbench_hierarchy.png b/docs/source/manual/fpga_verilog/figures/verilog_testbench_hierarchy.png
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diff --git a/docs/source/manual/fpga_verilog/func_verify.rst b/docs/source/manual/fpga_verilog/func_verify.rst
deleted file mode 100644
index a21a01c1e..000000000
--- a/docs/source/manual/fpga_verilog/func_verify.rst
+++ /dev/null
@@ -1,12 +0,0 @@
-Perform Functionality Verification
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-If the --fpga_verilog_print_modelsim_autodeck option is selected, it is possible to directly generate scripts for Modelsim. Inside of the Verilog directory specified with --fpga_verilog_dir can be found name_runsim.tcl scripts which perform the functional verification onto the FPGA generated. 
-
-The point of the verification step is to check that the FPGA reproduces the right function. As illustrated in :numref:`fig_ModelSim`, inside of the red rectangle is the programming of the FPGA. Each prog clock cycle corresponds to one bit added to the scan-chain. Inside of the blue rectangle, we see that the prog clock is set to 0 and the operating clock is toggled. Two outputs are shown, benchmark and FPGA, and by checking the value on both of them, we know if the functionality is respected.
-
-.. _fig_ModelSim:
-
-.. figure:: figures/verification_step.png
-   :scale: 50%
-   :alt: Functional Verification using ModelSim
diff --git a/docs/source/manual/fpga_verilog/index.rst b/docs/source/manual/fpga_verilog/index.rst
index 2940943c4..9b3af3a12 100644
--- a/docs/source/manual/fpga_verilog/index.rst
+++ b/docs/source/manual/fpga_verilog/index.rst
@@ -9,7 +9,7 @@ FPGA-Verilog
   
    fabric_netlist
  
-   func_verify
+   testbench
 
    sc_flow
    
diff --git a/docs/source/manual/fpga_verilog/testbench.rst b/docs/source/manual/fpga_verilog/testbench.rst
new file mode 100644
index 000000000..e9be51fda
--- /dev/null
+++ b/docs/source/manual/fpga_verilog/testbench.rst
@@ -0,0 +1,92 @@
+Testbench
+---------
+
+In this part, we will introduce the hierarchy, dependency and functionality of each Verilog testbench, which are generated to verify a FPGA fabric implemented with an application.
+
+OpenFPGA can auto-generate two types of Verilog testbenches to validate the correctness of the fabric: full and formal-oriented.
+Both testbenches share the same organization, as depicted in :numref:`fig_verilog_testbench_organization` (a).
+To enable self-testing, the FPGA and user's RTL design (simulate using an HDL simulator) are driven by the same input stimuli, and any mismatch on their outputs will raise an error flag.
+
+.. _fig_verilog_testbench_organization:
+
+.. figure:: figures/verilog_testbench_organization.png
+   :scale: 50%
+   :alt: Functional Verification using ModelSim
+
+   Principles of Verilog testbenches organization: (a) block diagram and (b) waveforms. 
+
+Full Testbench
+~~~~~~~~~~~~~~
+Full testbench aims at simulating an entire FPGA operating period, consisting of two phases: 
+
+  - the **Configuration Phase**, where the synthesized design bitstream is loaded to the programmable fabric, as highlighted by the green rectangle of :numref:`fig_verilog_testbench_organization` (b);
+
+  - the **Operating Phase**, where random input vectors are auto-generated to drive both Devices Under Test (DUTs), as highlighted by the red rectangle of :numref:`fig_verilog_testbench_organization` (b). Using the full testbench, users can validate both the configuration circuits and programming fabric of an FPGA.
+
+Formal-oriented Testbench
+~~~~~~~~~~~~~~~~~~~~~~~~~
+The formal-oriented testbench aims to test a programmed FPGA is instantiated with the user's bitstream.
+The module of the programmed FPGA is encapsulated with the same port mapping as the user's RTL design and thus can be fed to a formal tool for a 100% coverage formal verification. Compared to the full testbench, this skips the time-consuming configuration phase, reducing the simulation time, potentially also significantly accelerating the functional verification, especially for large FPGAs.
+
+.. warning:: Formal-oriented testbenches do not validate the configuration protocol of FPGAs. It is used to  validate FPGA with a wide range of benchmarks.
+
+General Usage
+~~~~~~~~~~~~~
+
+All the generated Verilog testbenches are located in the directory as you specify in the OpenFPGA command ``write_fabric_verilog``.
+Inside the directory, the Verilog testbenches are organized as illustrated in :numref:`fig_verilog_testbench_hierarchy`.
+
+.. _fig_verilog_testbench_hierarchy:
+
+.. figure:: ./figures/verilog_testbench_hierarchy.png
+   :scale: 90%
+
+   Hierarchy of Verilog testbenches for a FPGA fabric implemented with an application
+
+.. note:: ``<bench_name>`` is the module name of users' RTL design. 
+
+.. option:: <bench_name>_include_netlist.v
+
+   This file includes all the related Verilog netlists that are used by the testbenches, including both full and formal oriented testbenches.
+   This file is created to simplify the netlist addition for HDL simulator.
+   This is the only file you need to add to a simulator.
+
+   .. note:: Fabric Verilog netlists are included in this file.
+
+.. option:: define_simulation.v
+
+   This file includes pre-processing flags required by the testbenches, to smooth HDL simulation.
+   It will include the folliwng pre-procesing flags:
+  
+   - ```define AUTOCHECK_SIMULATION`` When enabled, testbench will include self-testing features. The FPGA and user's RTL design (simulate using an HDL simulator) are driven by the same input stimuli, and any mismatch on their outputs will raise an error flag.
+
+   .. note:: OpenFPGA always enable the self-testing feature. Users can disable it by commenting out the associated line in the ``define_simulation.v``.
+
+   - ```define ENABLE_FORMAL_VERFICATION`` When enabled, the ``<bench_name>_include_netlist.v`` will include the pre-configured FPGA netlist for formal verification usage. This flag is added when ``--print_formal_verification_top_netlist`` option is enabled when calling the ``write_verilog_testbench`` command. 
+
+   - ```define ENABLE_FORMAL_SIMULATION`` When enabled, the ``<bench_name>_include_netlist.v`` will include the testbench netlist for formal-oriented simulation. This flag is added when ``--print_preconfig_top_testbench`` option is enabled when calling the ``write_verilog_testbench`` command. 
+
+   .. note:: To run full testbenches, both flags ``ENABLE_FORMAL_VERIFICATION`` and ``ENABLE_FORMAL_SIMULATION`` must be disabled!
+
+.. option:: <bench_name>_autocheck_top_tb.v
+
+  This is the netlist for full testbench.
+
+.. option:: <bench_name>_formal_random_top_tb.v
+
+  This is the netlist for formal-oriented testbench.
+
+.. option:: <bench_name>_top_formal_verification.v
+
+  This netlist includes a Verilog module of a pre-configured FPGA fabric, which is a wrapper on top of the ``fpga_top.v`` netlist.
+  The wrapper module has the same port map as the top-level module of user's RTL design, which be directly def to formal verification tools to validate FPGA's functional equivalence. 
+  :numref:`fig_preconfig_module` illustrates the organization of a pre-configured module, which consists of a FPGA fabric (see :ref:`fabric_netlists`) and a hard-coded bitstream.
+  Only used I/Os of FPGA fabric will appear in the port list of the pre-configured module. 
+
+.. _fig_preconfig_module:
+
+.. figure:: ./figures/preconfig_module.png
+   :scale: 100%
+
+   Internal structure of a pre-configured FPGA module
+

From f079c61bd3f7111d2870464643a320f31115ea20 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 24 May 2020 18:09:48 -0600
Subject: [PATCH 554/645] re organize tutorials

---
 .../manual/arch_lang/circuit_library.rst      |    2 +-
 .../figures/Verification_step.pdf             | 1300 -----------------
 .../figures/verification_step.png             |  Bin 183723 -> 0 bytes
 docs/source/manual/fpga_verilog/index.rst     |    4 -
 .../design_flow}/figures/Layout_Diagram.png   |  Bin
 .../figures/fpga_asap_10x10_final.png         |  Bin
 .../figures/fpga_asap_10x10_floorplan.png     |  Bin
 docs/source/tutorials/design_flow/index.rst   |   10 +
 .../design_flow}/sc_flow.rst                  |    0
 docs/source/tutorials/index.rst               |    2 +
 10 files changed, 13 insertions(+), 1305 deletions(-)
 delete mode 100644 docs/source/manual/fpga_verilog/figures/Verification_step.pdf
 delete mode 100644 docs/source/manual/fpga_verilog/figures/verification_step.png
 rename docs/source/{manual/fpga_verilog => tutorials/design_flow}/figures/Layout_Diagram.png (100%)
 rename docs/source/{manual/fpga_verilog => tutorials/design_flow}/figures/fpga_asap_10x10_final.png (100%)
 rename docs/source/{manual/fpga_verilog => tutorials/design_flow}/figures/fpga_asap_10x10_floorplan.png (100%)
 create mode 100644 docs/source/tutorials/design_flow/index.rst
 rename docs/source/{manual/fpga_verilog => tutorials/design_flow}/sc_flow.rst (100%)

diff --git a/docs/source/manual/arch_lang/circuit_library.rst b/docs/source/manual/arch_lang/circuit_library.rst
index cde9b5fbc..e483728ed 100644
--- a/docs/source/manual/arch_lang/circuit_library.rst
+++ b/docs/source/manual/arch_lang/circuit_library.rst
@@ -339,7 +339,7 @@ These inputs are widely seen in FPGAs, such as clock ports, which are shared bet
 
 The global inouts are short wired across different instances. 
 
-:numref:`fig_global_ioput_ports` shows an example on how the global inouts are wired inside FPGA fabric.
+:numref:`fig_global_inout_ports` shows an example on how the global inouts are wired inside FPGA fabric.
 
 .. _fig_global_inout_ports:
 
diff --git a/docs/source/manual/fpga_verilog/figures/Verification_step.pdf b/docs/source/manual/fpga_verilog/figures/Verification_step.pdf
deleted file mode 100644
index 3c3d3b655..000000000
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-               <rdf:li>Black</rdf:li>
-            </rdf:Seq>
-         </xmpTPg:PlateNames>
-         <xmpTPg:SwatchGroups>
-            <rdf:Seq>
-               <rdf:li rdf:parseType="Resource">
-                  <xmpG:groupName>Groupe de nuances par défaut</xmpG:groupName>
-                  <xmpG:groupType>0</xmpG:groupType>
-                  <xmpG:Colorants>
-                     <rdf:Seq>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>White</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>255</xmpG:red>
-                           <xmpG:green>255</xmpG:green>
-                           <xmpG:blue>255</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>Black</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>0</xmpG:red>
-                           <xmpG:green>0</xmpG:green>
-                           <xmpG:blue>0</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>RGB Red</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>255</xmpG:red>
-                           <xmpG:green>0</xmpG:green>
-                           <xmpG:blue>0</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>RGB Yellow</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>255</xmpG:red>
-                           <xmpG:green>255</xmpG:green>
-                           <xmpG:blue>0</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>RGB Green</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>0</xmpG:red>
-                           <xmpG:green>255</xmpG:green>
-                           <xmpG:blue>0</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>RGB Cyan</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>0</xmpG:red>
-                           <xmpG:green>255</xmpG:green>
-                           <xmpG:blue>255</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>RGB Blue</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>0</xmpG:red>
-                           <xmpG:green>0</xmpG:green>
-                           <xmpG:blue>255</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>RGB Magenta</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>255</xmpG:red>
-                           <xmpG:green>0</xmpG:green>
-                           <xmpG:blue>255</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>R=193 G=39 B=45</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>193</xmpG:red>
-                           <xmpG:green>39</xmpG:green>
-                           <xmpG:blue>45</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>R=237 G=28 B=36</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>237</xmpG:red>
-                           <xmpG:green>28</xmpG:green>
-                           <xmpG:blue>36</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>R=241 G=90 B=36</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>241</xmpG:red>
-                           <xmpG:green>90</xmpG:green>
-                           <xmpG:blue>36</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>R=247 G=147 B=30</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>247</xmpG:red>
-                           <xmpG:green>147</xmpG:green>
-                           <xmpG:blue>30</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>R=251 G=176 B=59</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>251</xmpG:red>
-                           <xmpG:green>176</xmpG:green>
-                           <xmpG:blue>59</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>R=252 G=238 B=33</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>252</xmpG:red>
-                           <xmpG:green>238</xmpG:green>
-                           <xmpG:blue>33</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>R=217 G=224 B=33</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>217</xmpG:red>
-                           <xmpG:green>224</xmpG:green>
-                           <xmpG:blue>33</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>R=140 G=198 B=63</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>140</xmpG:red>
-                           <xmpG:green>198</xmpG:green>
-                           <xmpG:blue>63</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>R=57 G=181 B=74</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>57</xmpG:red>
-                           <xmpG:green>181</xmpG:green>
-                           <xmpG:blue>74</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>R=0 G=146 B=69</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>0</xmpG:red>
-                           <xmpG:green>146</xmpG:green>
-                           <xmpG:blue>69</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>R=0 G=104 B=55</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>0</xmpG:red>
-                           <xmpG:green>104</xmpG:green>
-                           <xmpG:blue>55</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>R=34 G=181 B=115</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>34</xmpG:red>
-                           <xmpG:green>181</xmpG:green>
-                           <xmpG:blue>115</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>R=0 G=169 B=157</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>0</xmpG:red>
-                           <xmpG:green>169</xmpG:green>
-                           <xmpG:blue>157</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>R=41 G=171 B=226</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>41</xmpG:red>
-                           <xmpG:green>171</xmpG:green>
-                           <xmpG:blue>226</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>R=0 G=113 B=188</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>0</xmpG:red>
-                           <xmpG:green>113</xmpG:green>
-                           <xmpG:blue>188</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>R=46 G=49 B=146</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>46</xmpG:red>
-                           <xmpG:green>49</xmpG:green>
-                           <xmpG:blue>146</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>R=27 G=20 B=100</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>27</xmpG:red>
-                           <xmpG:green>20</xmpG:green>
-                           <xmpG:blue>100</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>R=102 G=45 B=145</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>102</xmpG:red>
-                           <xmpG:green>45</xmpG:green>
-                           <xmpG:blue>145</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>R=147 G=39 B=143</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>147</xmpG:red>
-                           <xmpG:green>39</xmpG:green>
-                           <xmpG:blue>143</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>R=158 G=0 B=93</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>158</xmpG:red>
-                           <xmpG:green>0</xmpG:green>
-                           <xmpG:blue>93</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>R=212 G=20 B=90</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>212</xmpG:red>
-                           <xmpG:green>20</xmpG:green>
-                           <xmpG:blue>90</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>R=237 G=30 B=121</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>237</xmpG:red>
-                           <xmpG:green>30</xmpG:green>
-                           <xmpG:blue>121</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>R=199 G=178 B=153</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>199</xmpG:red>
-                           <xmpG:green>178</xmpG:green>
-                           <xmpG:blue>153</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>R=153 G=134 B=117</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>153</xmpG:red>
-                           <xmpG:green>134</xmpG:green>
-                           <xmpG:blue>117</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>R=115 G=99 B=87</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>115</xmpG:red>
-                           <xmpG:green>99</xmpG:green>
-                           <xmpG:blue>87</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>R=83 G=71 B=65</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>83</xmpG:red>
-                           <xmpG:green>71</xmpG:green>
-                           <xmpG:blue>65</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>R=198 G=156 B=109</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>198</xmpG:red>
-                           <xmpG:green>156</xmpG:green>
-                           <xmpG:blue>109</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>R=166 G=124 B=82</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>166</xmpG:red>
-                           <xmpG:green>124</xmpG:green>
-                           <xmpG:blue>82</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>R=140 G=98 B=57</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>140</xmpG:red>
-                           <xmpG:green>98</xmpG:green>
-                           <xmpG:blue>57</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>R=117 G=76 B=36</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>117</xmpG:red>
-                           <xmpG:green>76</xmpG:green>
-                           <xmpG:blue>36</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>R=96 G=56 B=19</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>96</xmpG:red>
-                           <xmpG:green>56</xmpG:green>
-                           <xmpG:blue>19</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>R=66 G=33 B=11</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>66</xmpG:red>
-                           <xmpG:green>33</xmpG:green>
-                           <xmpG:blue>11</xmpG:blue>
-                        </rdf:li>
-                     </rdf:Seq>
-                  </xmpG:Colorants>
-               </rdf:li>
-               <rdf:li rdf:parseType="Resource">
-                  <xmpG:groupName>Cold</xmpG:groupName>
-                  <xmpG:groupType>1</xmpG:groupType>
-                  <xmpG:Colorants>
-                     <rdf:Seq>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>C=56 M=0 Y=20 K=0</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>101</xmpG:red>
-                           <xmpG:green>200</xmpG:green>
-                           <xmpG:blue>208</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>C=51 M=43 Y=0 K=0</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>131</xmpG:red>
-                           <xmpG:green>139</xmpG:green>
-                           <xmpG:blue>197</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>C=26 M=41 Y=0 K=0</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>186</xmpG:red>
-                           <xmpG:green>155</xmpG:green>
-                           <xmpG:blue>201</xmpG:blue>
-                        </rdf:li>
-                     </rdf:Seq>
-                  </xmpG:Colorants>
-               </rdf:li>
-               <rdf:li rdf:parseType="Resource">
-                  <xmpG:groupName>Grays</xmpG:groupName>
-                  <xmpG:groupType>1</xmpG:groupType>
-                  <xmpG:Colorants>
-                     <rdf:Seq>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>R=0 G=0 B=0</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>0</xmpG:red>
-                           <xmpG:green>0</xmpG:green>
-                           <xmpG:blue>0</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>R=26 G=26 B=26</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>26</xmpG:red>
-                           <xmpG:green>26</xmpG:green>
-                           <xmpG:blue>26</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>R=51 G=51 B=51</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>51</xmpG:red>
-                           <xmpG:green>51</xmpG:green>
-                           <xmpG:blue>51</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>R=77 G=77 B=77</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>77</xmpG:red>
-                           <xmpG:green>77</xmpG:green>
-                           <xmpG:blue>77</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>R=102 G=102 B=102</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
-                           <xmpG:red>102</xmpG:red>
-                           <xmpG:green>102</xmpG:green>
-                           <xmpG:blue>102</xmpG:blue>
-                        </rdf:li>
-                        <rdf:li rdf:parseType="Resource">
-                           <xmpG:swatchName>R=128 G=128 B=128</xmpG:swatchName>
-                           <xmpG:mode>RGB</xmpG:mode>
-                           <xmpG:type>PROCESS</xmpG:type>
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diff --git a/docs/source/manual/fpga_verilog/index.rst b/docs/source/manual/fpga_verilog/index.rst
index 9b3af3a12..f851e6ed9 100644
--- a/docs/source/manual/fpga_verilog/index.rst
+++ b/docs/source/manual/fpga_verilog/index.rst
@@ -10,7 +10,3 @@ FPGA-Verilog
    fabric_netlist
  
    testbench
-
-   sc_flow
-   
-   
diff --git a/docs/source/manual/fpga_verilog/figures/Layout_Diagram.png b/docs/source/tutorials/design_flow/figures/Layout_Diagram.png
similarity index 100%
rename from docs/source/manual/fpga_verilog/figures/Layout_Diagram.png
rename to docs/source/tutorials/design_flow/figures/Layout_Diagram.png
diff --git a/docs/source/manual/fpga_verilog/figures/fpga_asap_10x10_final.png b/docs/source/tutorials/design_flow/figures/fpga_asap_10x10_final.png
similarity index 100%
rename from docs/source/manual/fpga_verilog/figures/fpga_asap_10x10_final.png
rename to docs/source/tutorials/design_flow/figures/fpga_asap_10x10_final.png
diff --git a/docs/source/manual/fpga_verilog/figures/fpga_asap_10x10_floorplan.png b/docs/source/tutorials/design_flow/figures/fpga_asap_10x10_floorplan.png
similarity index 100%
rename from docs/source/manual/fpga_verilog/figures/fpga_asap_10x10_floorplan.png
rename to docs/source/tutorials/design_flow/figures/fpga_asap_10x10_floorplan.png
diff --git a/docs/source/tutorials/design_flow/index.rst b/docs/source/tutorials/design_flow/index.rst
new file mode 100644
index 000000000..e7e9937ae
--- /dev/null
+++ b/docs/source/tutorials/design_flow/index.rst
@@ -0,0 +1,10 @@
+.. _design_flow_tutorials:
+   Design Flows
+
+Design Flows
+------------
+ 
+.. toctree::
+   :maxdepth: 2
+
+   sc_flow
diff --git a/docs/source/manual/fpga_verilog/sc_flow.rst b/docs/source/tutorials/design_flow/sc_flow.rst
similarity index 100%
rename from docs/source/manual/fpga_verilog/sc_flow.rst
rename to docs/source/tutorials/design_flow/sc_flow.rst
diff --git a/docs/source/tutorials/index.rst b/docs/source/tutorials/index.rst
index ea844c11c..fbadf5193 100644
--- a/docs/source/tutorials/index.rst
+++ b/docs/source/tutorials/index.rst
@@ -7,3 +7,5 @@
    compile
 
    eda_flow
+
+   design_flow/index

From 011ce5cdf6de11ea6f7e29c7292304273246480c Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 24 May 2020 18:22:45 -0600
Subject: [PATCH 555/645] minor fix on the documentation

---
 docs/source/tutorials/compile.rst | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/docs/source/tutorials/compile.rst b/docs/source/tutorials/compile.rst
index 6844740d2..e7db5a059 100644
--- a/docs/source/tutorials/compile.rst
+++ b/docs/source/tutorials/compile.rst
@@ -23,7 +23,8 @@ In general, please follow the steps to compile
 
 .. note:: recommand to use ``make -j`` to accelerate the compilation
 
-Quick Compilation Verification
+**Quick Compilation Verification**
+
 To quickly verify the tool is well compiled, user can run the following command from OpenFPGA root repository
 
 ::

From 35536ee59428238a08764f430037b0a3b3405585 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 24 May 2020 23:03:54 -0600
Subject: [PATCH 556/645] renaming design flows in documentation

---
 docs/source/tutorials/design_flow/index.rst                     | 2 +-
 .../tutorials/design_flow/{sc_flow.rst => verilog_to_gds2.rst}  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)
 rename docs/source/tutorials/design_flow/{sc_flow.rst => verilog_to_gds2.rst} (98%)

diff --git a/docs/source/tutorials/design_flow/index.rst b/docs/source/tutorials/design_flow/index.rst
index e7e9937ae..610b09b35 100644
--- a/docs/source/tutorials/design_flow/index.rst
+++ b/docs/source/tutorials/design_flow/index.rst
@@ -7,4 +7,4 @@ Design Flows
 .. toctree::
    :maxdepth: 2
 
-   sc_flow
+   verilog_to_gds2
diff --git a/docs/source/tutorials/design_flow/sc_flow.rst b/docs/source/tutorials/design_flow/verilog_to_gds2.rst
similarity index 98%
rename from docs/source/tutorials/design_flow/sc_flow.rst
rename to docs/source/tutorials/design_flow/verilog_to_gds2.rst
index f89d71db2..6efb3041f 100644
--- a/docs/source/tutorials/design_flow/sc_flow.rst
+++ b/docs/source/tutorials/design_flow/verilog_to_gds2.rst
@@ -1,4 +1,4 @@
-From Verilog to Layout
+From Verilog to GDSII
 ~~~~~~~~~~~~~~~~~~~~~~
 
 The generated Verilog code can be used through a semi-custom design flow to generate the layout.

From aa77ee9af6d4fbd3631af8a8e924e4e1ed6e1668 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 25 May 2020 00:31:01 -0600
Subject: [PATCH 557/645] add tutorial for full testbench run

---
 docs/source/manual/fpga_verilog/testbench.rst | 2 ++
 docs/source/tutorials/compile.rst             | 8 ++++----
 docs/source/tutorials/design_flow/index.rst   | 2 ++
 3 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/docs/source/manual/fpga_verilog/testbench.rst b/docs/source/manual/fpga_verilog/testbench.rst
index e9be51fda..728adb1e0 100644
--- a/docs/source/manual/fpga_verilog/testbench.rst
+++ b/docs/source/manual/fpga_verilog/testbench.rst
@@ -1,3 +1,5 @@
+.. _fpga_verilog_testbench:
+
 Testbench
 ---------
 
diff --git a/docs/source/tutorials/compile.rst b/docs/source/tutorials/compile.rst
index e7db5a059..5183be503 100644
--- a/docs/source/tutorials/compile.rst
+++ b/docs/source/tutorials/compile.rst
@@ -8,7 +8,7 @@ General Guidelines
 OpenFPGA uses CMake to generate the Makefile scripts
 In general, please follow the steps to compile
 
-::
+.. code-block:: shell
 
   git clone https://github.com/LNIS-Projects/OpenFPGA.git
   cd OpenFPGA
@@ -27,7 +27,7 @@ In general, please follow the steps to compile
 
 To quickly verify the tool is well compiled, user can run the following command from OpenFPGA root repository
 
-::
+.. code-block:: shell
 
   python3 openfpga_flow/scripts/run_fpga_task.py compilation_verification --debug --show_thread_logs
 
@@ -49,7 +49,7 @@ Docker
 If some of these dependencies are not installed on your machine, you can choose to use a Docker (the Docker tool needs to be installed).
 For the ease of the customer first experience, a Dockerfile is provided in the OpenFPGA folder. A container ready to use can be created with the following command
 
-::
+.. code-block:: shell
 
   docker run lnis/open_fpga:release
 
@@ -57,7 +57,7 @@ For the ease of the customer first experience, a Dockerfile is provided in the O
 
 Otherwise, a container where you can build OpenFPGA yourself can be created with the following commands
 
-::
+.. code-block:: shell
 
   docker build . -t open_fpga
   docker run -it --rm -v $PWD:/localfile/OpenFPGA -w="/localfile/OpenFPGA" open_fpga bash
diff --git a/docs/source/tutorials/design_flow/index.rst b/docs/source/tutorials/design_flow/index.rst
index 610b09b35..e854a08c6 100644
--- a/docs/source/tutorials/design_flow/index.rst
+++ b/docs/source/tutorials/design_flow/index.rst
@@ -7,4 +7,6 @@ Design Flows
 .. toctree::
    :maxdepth: 2
 
+   blif_to_verification
+
    verilog_to_gds2

From 339bf87c430e98732ad4435b86c3e7d7d1408078 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 25 May 2020 00:31:27 -0600
Subject: [PATCH 558/645] add missing file

---
 .../design_flow/blif_to_verification.rst      | 157 ++++++++++++++++++
 1 file changed, 157 insertions(+)
 create mode 100644 docs/source/tutorials/design_flow/blif_to_verification.rst

diff --git a/docs/source/tutorials/design_flow/blif_to_verification.rst b/docs/source/tutorials/design_flow/blif_to_verification.rst
new file mode 100644
index 000000000..d3b27a43f
--- /dev/null
+++ b/docs/source/tutorials/design_flow/blif_to_verification.rst
@@ -0,0 +1,157 @@
+.. _from_blif_to_verification:
+
+From BLIF to Verification
+-------------------------
+
+This tutorial will show an example how to 
+  - generate Verilog netlists for a FPGA fabric
+  - generate Verilog testbenches for a RTL design
+  - run HDL simulation to verify the functional correctness of the implemented FPGA fabric
+
+Netlist Generation
+~~~~~~~~~~~~~~~~~~
+We will use the openfpga_flow scripts (see details in :ref:`run_fpga_task`) to generate the Verilog netlists and testbenches.
+Here, we consider a representative but fairly simple FPGA architecture, which is based on 4-input LUTs.
+We will map a 2-input AND gate to the FPGA fabric, and run a full testbench (see details in :ref:`fpga_verilog_testbench`)
+
+We will simply execute the following openfpga task-run by 
+
+.. code-block:: shell
+
+  python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/configuration_chain
+
+Detailed settings, such as architecture XML files and RTL designs, can be found at ``${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/configuration_chain/config/task.conf``.
+
+.. note:: ``${OPENFPGA_PATH}`` is the root directory of OpenFPGA 
+
+After this task-run, you can find all the generated netlists and testbenches at  
+
+.. code-block:: shell
+
+  ${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/
+   
+.. note:: See :ref:`fabric_netlists` and :ref:`fpga_verilog_testbench` for the netlist details. 
+
+Run icarus iVerilog Simulation
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Through OpenFPGA Scripts
+^^^^^^^^^^^^^^^^^^^^^^^^
+
+By default, the ``configuration_chain`` task-run will execute iVerilog simulation automatically.
+The simulation results are logged in 
+
+.. code-block:: shell
+
+  ${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/vvp_sim_output.txt
+
+If the verification passed, you should be able to see ``Simulation Succeed`` in the log file.
+
+All the waveforms are stored in the ``and2_formal.vcd`` file.
+To visualize the waveforms, you can use the `GTKWave
+<http://gtkwave.sourceforge.net/>`_.
+
+.. code-block:: shell
+
+  gtkwave ${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/and2_formal.vcd &
+
+Manual Method
+^^^^^^^^^^^^^
+
+If you want to run iVerilog simulation manually, you can follow these steps:
+
+.. code-block:: shell
+
+  cd ${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH
+
+  source iverilog_output.txt
+  
+  vvp compiled_and2
+
+Debugging Tips
+^^^^^^^^^^^^^^
+
+If you want to apply full visibility to the signals, you need to change the following line in 
+
+   .. code-block:: shell 
+
+     ${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/and2_autocheck_top_tb.v
+   
+from 
+
+.. code-block:: shell
+
+  $dumpvars (1, and2_autocheck_top_tb);
+
+to 
+
+.. code-block:: shell
+
+  $dumpvars (12, and2_autocheck_top_tb);
+   
+
+Run Modelsim Simulation
+~~~~~~~~~~~~~~~~~~~~~~~
+Alternatively, you can run Modelsim simulations through openfpga_flow scripts or manually.
+
+Through OpenFPGA Scripts
+^^^^^^^^^^^^^^^^^^^^^^^^
+You can simply call the python script in the following line:
+
+.. code-block:: shell
+
+  python3 openfpga_flow/scripts/run_modelsim.py openfpga_shell/configuration_chain --run_sim
+
+The script will automatically create a Modelsim project at  
+
+.. code-block:: shell
+
+  ${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/MSIM2/
+
+and run the simulation.
+
+You may open the project and visualize the simulation results.
+
+Manual Method
+^^^^^^^^^^^^^
+
+Modify the ``fpga_defines.v`` (see details in :ref:`fabric_netlists`) at 
+
+.. code-block:: shell
+
+  ${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/
+
+by **deleting** the line 
+
+.. code-block:: shell
+
+  `define ICARUS_SIMULATOR 1
+
+Create a folder ``MSIM`` under
+
+.. code-block:: shell
+
+  ${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/
+
+Under the ``MSIM`` folder, create symbolic links to ``SRC`` folder and reference benchmarks by
+
+.. code-block:: shell
+
+  ln -s ../SRC ./ 
+
+  ln -s ../and2_output_verilog.v ./
+
+.. note:: Depending on the operating system, you may use other ways to create the symbolic links
+
+Launch ModelSim under the ``MSIM`` folder and create a project by following Modelsim user manuals.
+
+Add the following file to your project:
+
+.. code-block:: shell
+
+  ${OPENFPGA_PATH}/openfpga_flow/tasks/openfpga_shell/configuration_chain/latest/k4_N4_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/and2_include_netlists.v
+
+Compile the netlists, create a simulation configuration and specify ``and2_autocheck_top_tb`` at the top unit.
+
+Execute simulation with ``run -all``
+You should see ``Simulation Succeed`` in the output log.

From 1150b903a5b88b258240e30649e77c462edc61b3 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 25 May 2020 14:43:55 -0600
Subject: [PATCH 559/645] add quick start tutorial for architecture modeling

---
 .../arch_modeling/figures/k4n4_arch.png       | Bin 0 -> 71307 bytes
 docs/source/tutorials/arch_modeling/index.rst |  10 +
 .../tutorials/arch_modeling/quick_start.rst   | 549 ++++++++++++++++++
 docs/source/tutorials/index.rst               |   2 +
 4 files changed, 561 insertions(+)
 create mode 100644 docs/source/tutorials/arch_modeling/figures/k4n4_arch.png
 create mode 100644 docs/source/tutorials/arch_modeling/index.rst
 create mode 100644 docs/source/tutorials/arch_modeling/quick_start.rst

diff --git a/docs/source/tutorials/arch_modeling/figures/k4n4_arch.png b/docs/source/tutorials/arch_modeling/figures/k4n4_arch.png
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diff --git a/docs/source/tutorials/arch_modeling/index.rst b/docs/source/tutorials/arch_modeling/index.rst
new file mode 100644
index 000000000..1b643641d
--- /dev/null
+++ b/docs/source/tutorials/arch_modeling/index.rst
@@ -0,0 +1,10 @@
+.. _design_flow_tutorials:
+   Design Flows
+
+Architecture Modeling
+---------------------
+ 
+.. toctree::
+   :maxdepth: 2
+
+   quick_start
diff --git a/docs/source/tutorials/arch_modeling/quick_start.rst b/docs/source/tutorials/arch_modeling/quick_start.rst
new file mode 100644
index 000000000..0efbddf0d
--- /dev/null
+++ b/docs/source/tutorials/arch_modeling/quick_start.rst
@@ -0,0 +1,549 @@
+.. _arch_quick_start:
+
+A Quick Start
+-------------
+
+In this tutorial, we will consider a simple but representative FPGA architecture to show you how to
+  - Adapt the VPR architecture XML file to OpenFPGA acceptable format
+  - Create the OpenFPGA architecture XMl file to customize the primitive circuits
+
+Through this quick example, we will introduce the key steps to build your own FPGA based on a VPR architecture template.
+
+.. note:: These tips are generic and fundamental to build any architecture file for OpenFPGA.
+
+Adapt VPR Architecture 
+~~~~~~~~~~~~~~~~~~~~~~
+We start with the VPR architecture `template
+<https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/arch/timing/k4_N4_90nm.xml>`_.
+This file models a homogeneous FPGA, as illustrated in :numref:`fig_k4n4_arch`.
+
+.. _fig_k4n4_arch:
+
+.. figure:: ./figures/k4n4_arch.png
+   :scale: 100%
+
+   K4N4 FPGA architecture 
+
+A summary of the architectural features is as follows:
+  - An array of tiles surrounded by a ring of I/O blocks
+  - K4N4 Configurable Logic Block (CLB), which consists of four Basic Logic Elements (BLEs) and a fully-connected crossbar. Each BLE contains a 4-input Look-Up Table (LUT), a Flip-Flop (FF) and a 2:1 routing multiplexer
+  - Length-1 routing wires interconnected by Wilton-Style Switch Block (SB)
+
+The VPR architecture description is designed for EDA needs mainly, which lacks the details physical modelingrequired by OpenFPGA.
+Here, we show a step-by-step adaption on the architecture template.
+
+Physical I/O Modeling
+^^^^^^^^^^^^^^^^^^^^^
+OpenFPGA requires a physical I/O block rather the abstract I/O modeling of VPR.
+The ``<pb_type name="io">`` under the ``<complexblocklist>`` should be adapted to the following:
+
+.. code-block:: xml
+
+   <!-- Define I/O pads begin -->
+   <pb_type name="io">
+     <input name="outpad" num_pins="1"/>
+     <output name="inpad" num_pins="1"/>
+
+     <!-- A mode denotes the physical implementation of an I/O 
+           This mode will not be used by packer but is mainly used for fabric verilog generation   
+       -->
+     <mode name="physical" packable="false">
+       <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+         <input name="outpad" num_pins="1"/>
+         <output name="inpad" num_pins="1"/>
+       </pb_type>
+       <interconnect>
+         <direct name="outpad" input="io.outpad" output="iopad.outpad">
+           <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+         </direct>
+         <direct name="inpad" input="iopad.inpad" output="io.inpad">
+           <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+         </direct>
+       </interconnect>
+     </mode>
+
+     <!-- Operating modes of I/O used by VPR
+          IOs can operate as either inputs or outputs. -->
+     <mode name="inpad">
+       <pb_type name="inpad" blif_model=".input" num_pb="1">
+         <output name="inpad" num_pins="1"/>
+       </pb_type>
+       <interconnect>
+         <direct name="inpad" input="inpad.inpad" output="io.inpad">
+           <delay_constant max="9.492000e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+         </direct>
+       </interconnect>
+     </mode>
+     <mode name="outpad">
+       <pb_type name="outpad" blif_model=".output" num_pb="1">
+         <input name="outpad" num_pins="1"/>
+       </pb_type>
+       <interconnect>
+         <direct name="outpad" input="io.outpad" output="outpad.outpad">
+           <delay_constant max="2.675000e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+         </direct>
+       </interconnect>
+     </mode>
+  </pb_type>
+
+Note that, there are several major changes in the above codes, when compared to the original code.
+  - We added a physical ``mode`` of I/O in addition to the original VPR I/O modeling, which is close to the physical implementation of an I/O cell. OpenFPGA will output fabric netlists base on the physical implementation rather than the operating modes.
+  - We remove the ``clock`` port of I/O is actually a dangling port.
+  - We specify that the phyical ``mode`` to be disabled for VPR packer by using ``packable=false``. This can help reduce packer's runtime.
+
+Since, we have added a new BLIF model ``subckt io`` to the architecture modeling, we should update the ``<models>`` XML node by adding a new I/O model. 
+  
+.. code-block:: xml
+   
+  <models>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+  </models>
+
+Tileable Architecture
+^^^^^^^^^^^^^^^^^^^^^
+OpenFPGA does support fine-grained tile-based architecture as shown in :numref:`fig_k4n4_arch`.
+The tileable architecture leads to fast netlist generation as well as enables highly optimized physical designs through backend flow.
+To turn on the tileable architecture, the ``tileable`` property should be added to ``<layout>`` node.
+
+.. code-block:: xml
+
+  <layout tileable="true">
+
+By enabling this, all the Switch Blocks and Connection Blocks will be generated as identical as possible.
+As a result, for any FPGA array size, there are only 9 unique tiles to be generated in netlists.
+See details in :cite:`XTang_FPT_2019`.
+
+Detailed guidelines can be found at :ref:`addon_vpr_syntax`.
+
+Craft OpenFPGA Architecture
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+OpenFPGA needs another XML file which contains detailed modeling on the physical design of FPGA architecture.
+This is designed to minimize the modification on the original VPR architecture file, so that it can be reused.
+
+Overview on the Structure
+^^^^^^^^^^^^^^^^^^^^^^^^^
+
+An OpenFPGA architecture including the following parts.
+  - Architecture modeling with a focus on circuit-level description
+  - Configuration protocol definition
+  - Annotation on the VPR architecture modules
+  - Simulation settings
+
+These parts are organized as follows in the XML file.
+
+.. code-block:: xml
+
+  <openfpga_architecture>
+    <!-- Technology-related (device/transistor-level) information
+    <technology_library>
+      ...
+    </technology_library>
+
+    <!-- Circuit-level description -->
+    <circuit_library>
+      ...
+    </circuit_library>
+
+    <!-- Configuration protocol definition --> 
+    <configuration_protocol>
+      ...
+    </configuration_protocol>
+
+    <!-- Annotation on VPR architecture modules -->
+    <connection_block>
+      ...
+    </connection_block>
+    <switch_block>
+      ...
+    </switch_block>
+    <routing_segment>
+      ...
+    </routing_segment>
+    <pb_type_annotations>
+      ...
+    </pb_type_annotations>
+  </openfpga_architecture>
+
+  <openfpga_simulation_setting>
+    ...
+  </openfpga_simulation_setting>
+
+Technology Library Definition
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+Technology information are all stored under the ``<technology_library>`` node, which contains transistor-level information to build the FPGA.
+Here, we bind to the open-source ASU Predictive Technology Modeling (PTM) 45nm process library.
+See details in :ref:`technology_library`.
+
+.. code-block:: xml
+
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+
+.. note:: These information are important for FPGA-SPICE to correctly generate netlists. If you are not using FPGA-SPICE, you may provide a dummy technology library.
+
+Circuit Library Definition
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Circuit library is the crucial component of the architecture description, which contains a list of ``<circuit_model>``, each of which describes how a circuit is implemented for a FPGA component.
+
+Typically, we will defined a few atom ``<circuit_model>`` which are used to build primitive ``<circuit_model>``.
+
+.. code-block:: xml
+
+  <circuit_library>
+    <!-- Atom circuit models begin-->
+    <circuit_model>
+      ...
+    </circuit_model>
+    <!-- Atom circuit models end-->
+
+    <!-- Primitive circuit models begin -->
+    <circuit_model>
+      ...
+    </circuit_model>
+    <!-- Primitive circuit models end -->
+  </circuit_library>
+
+.. note:: Primitive ``<circuit_model>`` are the circuits which are directly used to build a FPGA component, such as Look-Up Table (LUT). Atom ``<circuit_model>`` are the circuits which are only used inside primitive ``<circuit_model>``.
+
+In this tutorial, we need the following atom ``<circuit_model>``, which are inverters, buffers and pass-gate logics.
+
+.. code-block:: xml
+
+  <!-- Atom circuit models begin-->
+  <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+    <design_technology type="cmos" topology="inverter" size="1"/>
+    <port type="input" prefix="in" size="1"/>
+    <port type="output" prefix="out" size="1"/>
+    <delay_matrix type="rise" in_port="in" out_port="out">
+      10e-12
+    </delay_matrix>
+    <delay_matrix type="fall" in_port="in" out_port="out">
+      10e-12
+    </delay_matrix>
+  </circuit_model>
+  <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+    <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+    <port type="input" prefix="in" size="1"/>
+    <port type="output" prefix="out" size="1"/>
+    <delay_matrix type="rise" in_port="in" out_port="out">
+      10e-12
+    </delay_matrix>
+    <delay_matrix type="fall" in_port="in" out_port="out">
+      10e-12
+    </delay_matrix>
+  </circuit_model>
+  <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+    <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+    <port type="input" prefix="in" size="1"/>
+    <port type="output" prefix="out" size="1"/>
+    <delay_matrix type="rise" in_port="in" out_port="out">
+      10e-12
+    </delay_matrix>
+    <delay_matrix type="fall" in_port="in" out_port="out">
+      10e-12
+    </delay_matrix>
+  </circuit_model>
+  <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+    <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+    <input_buffer exist="false"/>
+    <output_buffer exist="false"/>
+    <port type="input" prefix="in" size="1"/>
+    <port type="input" prefix="sel" size="1"/>
+    <port type="input" prefix="selb" size="1"/>
+    <port type="output" prefix="out" size="1"/>
+    <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+      10e-12 5e-12 5e-12
+    </delay_matrix>
+    <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+      10e-12 5e-12 5e-12
+    </delay_matrix>
+  </circuit_model>
+  <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+    <design_technology type="cmos"/>
+    <input_buffer exist="false"/>
+    <output_buffer exist="false"/>
+    <port type="input" prefix="in" size="1"/>
+    <port type="output" prefix="out" size="1"/>
+    <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+  </circuit_model>
+  <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+    <design_technology type="cmos"/>
+    <input_buffer exist="false"/>
+    <output_buffer exist="false"/>
+    <port type="input" prefix="in" size="1"/>
+    <port type="output" prefix="out" size="1"/>
+    <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+  </circuit_model>
+  <!-- Atom circuit models end-->
+
+In this tutorial, we require the following primitive ``<circuit_model>``, which are routing multiplexers, Look-Up Tables, I/O cells in FPGA architecture (see :numref:`fig_k4n4_arch`).
+
+.. note:: We use different routing multiplexer circuits to maximum the performance by considering it fan-in and fan-out in the architecture context.
+
+.. note:: We specify that external Verilog netlists will be used for the circuits of Flip-Flops (FFs) ``static_dff`` and ``sc_dff_compact``, as well as the circuit of I/O cell ``iopad``. Other circuit models will be auto-generated by OpenFPGA.
+
+.. code-block:: xml
+
+  <!-- Primitive circuit models begin -->
+  <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+    <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+    <input_buffer exist="true" circuit_model_name="INVTX1"/>
+    <output_buffer exist="true" circuit_model_name="INVTX1"/>
+    <pass_gate_logic circuit_model_name="TGATE"/>
+    <port type="input" prefix="in" size="1"/>
+    <port type="output" prefix="out" size="1"/>
+    <port type="sram" prefix="sram" size="1"/>
+  </circuit_model>
+  <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+    <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+    <input_buffer exist="true" circuit_model_name="INVTX1"/>
+    <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+    <pass_gate_logic circuit_model_name="TGATE"/>
+    <port type="input" prefix="in" size="1"/>
+    <port type="output" prefix="out" size="1"/>
+    <port type="sram" prefix="sram" size="1"/>
+  </circuit_model>
+  <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+    <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+    <input_buffer exist="true" circuit_model_name="INVTX1"/>
+    <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+    <pass_gate_logic circuit_model_name="TGATE"/>
+    <port type="input" prefix="in" size="1"/>
+    <port type="output" prefix="out" size="1"/>
+    <port type="sram" prefix="sram" size="1"/>
+  </circuit_model>
+  <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+  <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+     <design_technology type="cmos"/>
+     <input_buffer exist="true" circuit_model_name="INVTX1"/>
+     <output_buffer exist="true" circuit_model_name="INVTX1"/>
+     <port type="input" prefix="D" size="1"/>
+     <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+     <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+     <port type="output" prefix="Q" size="1"/>
+     <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+  </circuit_model>
+  <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
+    <design_technology type="cmos"/>
+    <input_buffer exist="true" circuit_model_name="INVTX1"/>
+    <output_buffer exist="true" circuit_model_name="INVTX1"/>
+    <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+    <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+    <pass_gate_logic circuit_model_name="TGATE"/>
+    <port type="input" prefix="in" size="4"/>
+    <port type="output" prefix="out" size="1"/>
+    <port type="sram" prefix="sram" size="16"/>
+  </circuit_model>
+  <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+  <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+     <design_technology type="cmos"/>
+     <input_buffer exist="true" circuit_model_name="INVTX1"/>
+     <output_buffer exist="true" circuit_model_name="INVTX1"/>
+     <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+     <port type="input" prefix="D" size="1"/>
+     <port type="output" prefix="Q" size="1"/>
+     <port type="output" prefix="Qb" size="1"/>
+     <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+  </circuit_model>
+  <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+    <design_technology type="cmos"/>
+    <input_buffer exist="true" circuit_model_name="INVTX1"/>
+    <output_buffer exist="true" circuit_model_name="INVTX1"/>
+    <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
+    <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+    <port type="input" prefix="outpad" size="1"/>
+    <port type="output" prefix="inpad" size="1"/>
+  </circuit_model>
+  <!-- Primitive circuit models end -->
+
+See details in :ref:`circuit_library` and :ref:`circuit_model_examples`.
+
+Annotation on VPR Architecture
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+In this part, we bind the ``<circuit_model>`` defined in the circuit library to each FPGA component.
+
+We specify that the FPGA fabric will be configured through a chain of Flip-Flops (FFs), which is built with the ``<circuit_model name=sc_dff_compact>``.
+
+.. code-block:: xml
+
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+  </configuration_protocol>
+
+For the routing architecture, we specify the ``circuit_model`` to be used as routing multiplexers inside Connection Blocks (CBs), Switch Blocks (SBs), and also the routing wires.
+
+.. code-block:: xml
+
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+
+.. note:: For a correct binding, the name of connection block, switch block and routing segment should match the name definition in your VPR architecture description! 
+
+For each ``<pb_type>`` defined in the ``<complexblocklist>`` of VPR architecture, we need to specify
+
+- The physical mode for any ``<pb_type>`` that contains multiple ``<mode>``. The name of the physical mode  should match a mode name that is defined in the VPR architecture. For example:
+
+.. code-block:: xml
+
+  <pb_type name="io" physical_mode_name="physical"/>
+
+- The circuit model used to implement any primitive ``<pb_type>`` in physical modes. It is required to provide full hierarchy of the ``pb_type``. For example:
+
+.. code-block:: xml
+
+  <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+
+.. note:: Mode-selection bits should be provided as the default configuration for a configurable resource. In this example, an I/O cell has a configuration bit, as defined in the ``<circuit_model name="iopad">``. We specify that by default, the configuration memory will be set to logic ``1``.
+
+- The physical ``<pb_type>`` for any ``<pb_type>`` in the operating modes (mode other than the physical mode). This is required to translate mapping results from operating modes to their physical modes, in order to generate bitstreams. It is required to provide full hierarchy of the ``pb_type``. For example, 
+
+.. code-block:: xml
+
+  <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+
+.. note:: Mode-selection bits should be provided so as to configure the circuits to be functional as required by the operating mode. In this example, an I/O cell will be configured with a logic ``1`` when operating as an input pad.
+
+- The circuit model used to implement interconnecting modules. The interconnect name should match the definition in the VPR architecture file. For example, 
+
+.. code-block:: xml
+
+  <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+
+.. note:: If not specified, each interconnect will be binded to its default ``circuit_model``. For example, the crossbar will be binded to the default multiplexer ``<circuit_model name="mux_1level_tapbuf">``, if not specified here. 
+
+.. note:: OpenFPGA automatically infers the type of circuit model required by each interconnect.
+
+The complete annotation is shown as follows:
+
+.. code-block:: xml
+
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="static_dff"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+
+See details in :ref:`annotate_vpr_arch`.
+
+Simulation Settings
+^^^^^^^^^^^^^^^^^^^
+
+The simulation settings contain critical parameters to build testbenches for verify the FPGA fabric. 
+
+The complete annotation is shown as follows:
+
+.. code-block:: xml
+
+  <openfpga_simulation_setting>
+    <clock_setting>
+      <operating frequency="auto" num_cycles="auto" slack="0.2"/>
+      <programming frequency="100e6"/>
+    </clock_setting>
+    <simulator_option>
+      <operating_condition temperature="25"/>
+      <output_log verbose="false" captab="false"/>
+      <accuracy type="abs" value="1e-13"/>
+      <runtime fast_simulation="true"/>
+    </simulator_option>
+    <monte_carlo num_simulation_points="2"/>
+    <measurement_setting>
+      <slew>
+        <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
+        <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
+      </slew>
+      <delay>
+        <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
+        <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
+      </delay>
+    </measurement_setting>
+    <stimulus>
+      <clock>
+        <rise slew_type="abs" slew_time="20e-12" />
+        <fall slew_type="abs" slew_time="20e-12" />
+      </clock>
+      <input>
+        <rise slew_type="abs" slew_time="25e-12" />
+        <fall slew_type="abs" slew_time="25e-12" />
+      </input>
+    </stimulus>
+  </openfpga_simulation_setting>
+
+The ``<clock_setting>`` is crucial to create clock signals in testbenches.
+
+.. note:: FPGA has two types of clocks, one is the operating clock which controls applications that mapped to FPGA fabric, while the other is the programming clock which controls the configuration protocol.
+
+In this example, we specify 
+
+- the operating clock will follow the maximum frequency achieved by VPR routing results
+- the number of operating clock cycles to be used will follow the average signal activities of the RTL design that is mapped to the FPGA fabric.
+- the actual operating clock frequency will be relaxed (reduced) by 20% by considering the errors between VPR results and physical designs.
+- the programming clock frequency is fixed at 200MHz
+
+The ``<simulator_option>`` are the options for SPICE simulator.
+Here we specify
+
+- SPICE simulations will consider a 25 :math:`^\circ C` temperature.
+- SPICE simulation will output results in a compact way without details on node capacitances.
+- SPICE simulation will use ``0.1ps`` as the minimum time step.
+- SPICE simulation will consider fast algorithms to speed up runtime.
+
+The ``<monte_carlo num_simulation_points="2"/>`` are the options for SPICE simulator.
+Here we specify that for each testbench, we will consider two Monte-Carlo simulations to evaluate the impact of process variations.
+
+The ``<measurement_setting>`` specify how the output signals will be measured for delay and power evaluation.
+Here we specify that 
+
+- for slew calculation (used in power estimation), we consider from the 5% of the ``VDD`` to the 95% of the ``VDD`` for both rising and falling edges.
+- for delay calculation, we consider from the 50% of the ``VDD`` of input signal to the 50% of the ``VDD`` of output signals for both rising and falling edges.
+
+In the ``<stimulus>``, we specify that ``20ps`` slew time will be applied to built clock waverforms in SPICE simulations.
+
+See details in :ref:`simulation_setting`.
diff --git a/docs/source/tutorials/index.rst b/docs/source/tutorials/index.rst
index fbadf5193..9b1993d68 100644
--- a/docs/source/tutorials/index.rst
+++ b/docs/source/tutorials/index.rst
@@ -9,3 +9,5 @@
    eda_flow
 
    design_flow/index
+
+   arch_modeling/index

From 62c506182c53949822574e336017ed888c5a5a7b Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 25 May 2020 18:21:12 -0600
Subject: [PATCH 560/645] start developing frame-based configuration protocol

---
 libopenfpga/libarchopenfpga/src/circuit_types.h             | 6 +++---
 .../libarchopenfpga/src/read_xml_config_protocol.cpp        | 4 ++--
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/libopenfpga/libarchopenfpga/src/circuit_types.h b/libopenfpga/libarchopenfpga/src/circuit_types.h
index 448bf28d2..f13a8a5ee 100644
--- a/libopenfpga/libarchopenfpga/src/circuit_types.h
+++ b/libopenfpga/libarchopenfpga/src/circuit_types.h
@@ -119,16 +119,16 @@ constexpr std::array<const char*, NUM_CIRCUIT_MODEL_DELAY_TYPES> CIRCUIT_MODEL_D
  * 1. configurable memories are organized and accessed as standalone elements 
  * 2. configurable memories are organized and accessed by a scan-chain
  * 3. configurable memories are organized and accessed by memory bank 
- * 4. configurable memories are organized and accessed by a local encoder 
+ * 4. configurable memories are organized and accessed by frames 
  */
 enum e_config_protocol_type {
   CONFIG_MEM_STANDALONE,   
   CONFIG_MEM_SCAN_CHAIN,   
   CONFIG_MEM_MEMORY_BANK,  
-  CONFIG_MEM_LOCAL_ENCODER,  
+  CONFIG_MEM_FRAME_BASED,  
   NUM_CONFIG_PROTOCOL_TYPES
 };
 
-constexpr std::array<const char*, NUM_CONFIG_PROTOCOL_TYPES> CONFIG_PROTOCOL_TYPE_STRING = {{"standalone", "scan_chain", "memory_bank", "local_encoder"}};
+constexpr std::array<const char*, NUM_CONFIG_PROTOCOL_TYPES> CONFIG_PROTOCOL_TYPE_STRING = {{"standalone", "scan_chain", "memory_bank", "frame_based"}};
 
 #endif
diff --git a/libopenfpga/libarchopenfpga/src/read_xml_config_protocol.cpp b/libopenfpga/libarchopenfpga/src/read_xml_config_protocol.cpp
index e00600b1a..2daedbd39 100644
--- a/libopenfpga/libarchopenfpga/src/read_xml_config_protocol.cpp
+++ b/libopenfpga/libarchopenfpga/src/read_xml_config_protocol.cpp
@@ -35,8 +35,8 @@ e_config_protocol_type string_to_config_protocol_type(const std::string& type_st
     return CONFIG_MEM_MEMORY_BANK;
   }
 
-  if (std::string("local_encoder") == type_string) {
-    return CONFIG_MEM_LOCAL_ENCODER;
+  if (std::string("frame_based") == type_string) {
+    return CONFIG_MEM_FRAME_BASED;
   }
 
   return NUM_CONFIG_PROTOCOL_TYPES;

From 3a26bb5eefb7105c3c92c99c211b18360ec26a45 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 25 May 2020 19:02:14 -0600
Subject: [PATCH 561/645] add advanced check in configurable memories

---
 .../src/check_circuit_library.cpp             |  1 +
 openfpga/src/base/openfpga_read_arch.cpp      |  7 ++++
 openfpga/src/utils/circuit_library_utils.cpp  | 37 +++++++++++++++++++
 openfpga/src/utils/circuit_library_utils.h    |  4 ++
 4 files changed, 49 insertions(+)

diff --git a/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp b/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp
index f5392a2e4..f37742a5a 100644
--- a/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp
+++ b/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp
@@ -552,3 +552,4 @@ bool check_circuit_library(const CircuitLibrary& circuit_lib) {
 
   return true;
 }
+
diff --git a/openfpga/src/base/openfpga_read_arch.cpp b/openfpga/src/base/openfpga_read_arch.cpp
index ee0670268..db9b09b5b 100644
--- a/openfpga/src/base/openfpga_read_arch.cpp
+++ b/openfpga/src/base/openfpga_read_arch.cpp
@@ -11,6 +11,7 @@
 /* Headers from archopenfpga library */
 #include "read_xml_openfpga_arch.h"
 #include "check_circuit_library.h"
+#include "circuit_library_utils.h"
 #include "write_xml_openfpga_arch.h"
 
 #include "openfpga_read_arch.h"
@@ -50,6 +51,12 @@ int read_arch(OpenfpgaContext& openfpga_context,
     return CMD_EXEC_FATAL_ERROR;
   }
 
+  if (false == check_configurable_memory_circuit_model(openfpga_context.arch().config_protocol.type(),
+                                                       openfpga_context.arch().circuit_lib,
+                                                       openfpga_context.arch().config_protocol.memory_model())) {
+    return CMD_EXEC_FATAL_ERROR;
+  }
+
   return CMD_EXEC_SUCCESS;
 } 
 
diff --git a/openfpga/src/utils/circuit_library_utils.cpp b/openfpga/src/utils/circuit_library_utils.cpp
index cecbcafed..082349008 100644
--- a/openfpga/src/utils/circuit_library_utils.cpp
+++ b/openfpga/src/utils/circuit_library_utils.cpp
@@ -11,6 +11,7 @@
 #include "vtr_assert.h"
 #include "vtr_log.h"
 
+#include "check_circuit_library.h"
 #include "circuit_library_utils.h"
 
 /* begin namespace openfpga */
@@ -226,4 +227,40 @@ std::vector<std::string> find_circuit_library_unique_verilog_netlists(const Circ
  return netlists;
 }
 
+/************************************************************************
+ * Advanced check if the circuit model of configurable memory
+ * satisfy the needs of configuration protocol
+ * - Configuration chain -based: we check if we have a CCFF model
+ * - Frame -based: we check if we have a SRAM model which has BL and WL
+ * 
+ ***********************************************************************/
+bool check_configurable_memory_circuit_model(const e_config_protocol_type& config_protocol_type,
+                                             const CircuitLibrary& circuit_lib,
+                                             const CircuitModelId& config_mem_circuit_model) {
+  size_t num_err = 0;
+
+  switch (config_protocol_type) {
+  case CONFIG_MEM_SCAN_CHAIN:   
+    num_err = check_ccff_circuit_model_ports(circuit_lib,
+                                             config_mem_circuit_model);
+    break;
+  case CONFIG_MEM_STANDALONE: 
+  case CONFIG_MEM_MEMORY_BANK:  
+  case CONFIG_MEM_FRAME_BASED:  
+    num_err = check_sram_circuit_model_ports(circuit_lib,
+                                             config_mem_circuit_model,
+                                             true);
+    
+    break;
+  default:
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid type of configuration protocol!\n");
+    return false;
+  }
+  
+  VTR_LOG("Found %ld errors when checking configurable memory circuit models!\n",
+          num_err);
+  return (0 == num_err);
+}
+
 } /* end namespace openfpga */
diff --git a/openfpga/src/utils/circuit_library_utils.h b/openfpga/src/utils/circuit_library_utils.h
index 7c5552304..b03c03156 100644
--- a/openfpga/src/utils/circuit_library_utils.h
+++ b/openfpga/src/utils/circuit_library_utils.h
@@ -38,6 +38,10 @@ std::vector<CircuitPortId> find_circuit_library_global_ports(const CircuitLibrar
 
 std::vector<std::string> find_circuit_library_unique_verilog_netlists(const CircuitLibrary& circuit_lib);
 
+bool check_configurable_memory_circuit_model(const e_config_protocol_type& config_protocol_type,
+                                             const CircuitLibrary& circuit_lib,
+                                             const CircuitModelId& config_mem_circuit_model);
+
 } /* end namespace openfpga */
 
 #endif

From 8864920460aea5b60e52bf0754e064d6dc5e9e5c Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 25 May 2020 22:15:16 -0600
Subject: [PATCH 562/645] add frame-based memory module builder

---
 openfpga/src/base/openfpga_build_fabric.cpp   |   3 +-
 openfpga/src/base/openfpga_context.h          |   6 +
 openfpga/src/base/openfpga_naming.cpp         |  14 ++
 openfpga/src/base/openfpga_naming.h           |   3 +
 openfpga/src/base/openfpga_reserved_words.h   |   6 +
 openfpga/src/fabric/build_decoder_modules.cpp |  59 +++++-
 openfpga/src/fabric/build_decoder_modules.h   |   5 +
 openfpga/src/fabric/build_device_module.cpp   |   7 +-
 openfpga/src/fabric/build_device_module.h     |   3 +-
 openfpga/src/fabric/build_memory_modules.cpp  | 195 +++++++++++++++++-
 openfpga/src/fabric/build_memory_modules.h    |   2 +
 openfpga/src/utils/module_manager_utils.cpp   |  60 ++++++
 openfpga/src/utils/module_manager_utils.h     |   9 +
 13 files changed, 361 insertions(+), 11 deletions(-)

diff --git a/openfpga/src/base/openfpga_build_fabric.cpp b/openfpga/src/base/openfpga_build_fabric.cpp
index 708bef124..b1a1fe118 100644
--- a/openfpga/src/base/openfpga_build_fabric.cpp
+++ b/openfpga/src/base/openfpga_build_fabric.cpp
@@ -76,8 +76,9 @@ int build_fabric(OpenfpgaContext& openfpga_ctx,
   VTR_LOG("\n");
 
   openfpga_ctx.mutable_module_graph() = build_device_module_graph(openfpga_ctx.mutable_io_location_map(),
-                                                                  g_vpr_ctx.device(),
+                                                                  openfpga_ctx.mutable_decoder_lib(),
                                                                   const_cast<const OpenfpgaContext&>(openfpga_ctx),
+                                                                  g_vpr_ctx.device(),
                                                                   cmd_context.option_enable(cmd, opt_compress_routing),
                                                                   cmd_context.option_enable(cmd, opt_duplicate_grid_pin),
                                                                   cmd_context.option_enable(cmd, opt_verbose));
diff --git a/openfpga/src/base/openfpga_context.h b/openfpga/src/base/openfpga_context.h
index 2ea114410..8c025687f 100644
--- a/openfpga/src/base/openfpga_context.h
+++ b/openfpga/src/base/openfpga_context.h
@@ -10,6 +10,7 @@
 #include "vpr_placement_annotation.h"
 #include "vpr_routing_annotation.h"
 #include "mux_library.h"
+#include "decoder_library.h"
 #include "tile_direct.h"
 #include "module_manager.h"
 #include "netlist_manager.h"
@@ -55,6 +56,7 @@ class OpenfpgaContext : public Context  {
     const openfpga::VprRoutingAnnotation& vpr_routing_annotation() const { return vpr_routing_annotation_; }
     const openfpga::DeviceRRGSB& device_rr_gsb() const { return device_rr_gsb_; }
     const openfpga::MuxLibrary& mux_lib() const { return mux_lib_; }
+    const openfpga::DecoderLibrary& decoder_lib() const { return decoder_lib_; }
     const openfpga::TileDirect& tile_direct() const { return tile_direct_; }
     const openfpga::ModuleManager& module_graph() const { return module_graph_; }
     const openfpga::FlowManager& flow_manager() const { return flow_manager_; }
@@ -72,6 +74,7 @@ class OpenfpgaContext : public Context  {
     openfpga::VprRoutingAnnotation& mutable_vpr_routing_annotation() { return vpr_routing_annotation_; }
     openfpga::DeviceRRGSB& mutable_device_rr_gsb() { return device_rr_gsb_; }
     openfpga::MuxLibrary& mutable_mux_lib() { return mux_lib_; }
+    openfpga::DecoderLibrary& mutable_decoder_lib() { return decoder_lib_; }
     openfpga::TileDirect& mutable_tile_direct() { return tile_direct_; }
     openfpga::ModuleManager& mutable_module_graph() { return module_graph_; }
     openfpga::FlowManager& mutable_flow_manager() { return flow_manager_; }
@@ -105,6 +108,9 @@ class OpenfpgaContext : public Context  {
     /* Library of physical implmentation of routing multiplexers */
     openfpga::MuxLibrary mux_lib_;
 
+    /* Library of physical implmentation of decoders */
+    openfpga::DecoderLibrary decoder_lib_;
+
     /* Inner/inter-column/row tile direct connections */
     openfpga::TileDirect tile_direct_;
 
diff --git a/openfpga/src/base/openfpga_naming.cpp b/openfpga/src/base/openfpga_naming.cpp
index 74750fca5..bf82a1d7c 100644
--- a/openfpga/src/base/openfpga_naming.cpp
+++ b/openfpga/src/base/openfpga_naming.cpp
@@ -142,6 +142,20 @@ std::string generate_mux_local_decoder_subckt_name(const size_t& addr_size,
   return subckt_name;
 } 
 
+/************************************************
+ * Generate the module name of a decoder
+ * for frame-based memories
+ ***********************************************/
+std::string generate_frame_memory_decoder_subckt_name(const size_t& addr_size, 
+                                                      const size_t& data_size) {
+  std::string subckt_name = "frame_decoder";
+  subckt_name += std::to_string(addr_size);
+  subckt_name += "to";
+  subckt_name += std::to_string(data_size);
+
+  return subckt_name;
+} 
+
 /************************************************
  * Generate the module name of a routing track wire
  ***********************************************/
diff --git a/openfpga/src/base/openfpga_naming.h b/openfpga/src/base/openfpga_naming.h
index 9896dddd4..d3cfb04f0 100644
--- a/openfpga/src/base/openfpga_naming.h
+++ b/openfpga/src/base/openfpga_naming.h
@@ -50,6 +50,9 @@ std::string generate_mux_branch_subckt_name(const CircuitLibrary& circuit_lib,
 std::string generate_mux_local_decoder_subckt_name(const size_t& addr_size, 
                                                    const size_t& data_size); 
 
+std::string generate_frame_memory_decoder_subckt_name(const size_t& addr_size, 
+                                                      const size_t& data_size);
+
 std::string generate_segment_wire_subckt_name(const std::string& wire_model_name, 
                                               const size_t& segment_id); 
 
diff --git a/openfpga/src/base/openfpga_reserved_words.h b/openfpga/src/base/openfpga_reserved_words.h
index be47315ba..c556a19b1 100644
--- a/openfpga/src/base/openfpga_reserved_words.h
+++ b/openfpga/src/base/openfpga_reserved_words.h
@@ -30,6 +30,12 @@ constexpr char* GRID_MUX_INSTANCE_PREFIX = "mux_";
 constexpr char* SWITCH_BLOCK_MUX_INSTANCE_PREFIX = "mux_"; 
 constexpr char* CONNECTION_BLOCK_MUX_INSTANCE_PREFIX = "mux_"; 
 
+/* Decoder naming constant strings */
+constexpr char* DECODER_ENABLE_PORT_NAME = "enable";
+constexpr char* DECODER_ADDRESS_PORT_NAME = "address";
+constexpr char* DECODER_DATA_PORT_NAME = "data";
+constexpr char* DECODER_DATA_INV_PORT_NAME = "data_inv";
+
 /* Inverted port naming */
 constexpr char* INV_PORT_POSTFIX = "_inv";
 
diff --git a/openfpga/src/fabric/build_decoder_modules.cpp b/openfpga/src/fabric/build_decoder_modules.cpp
index 06defc007..a2accae89 100644
--- a/openfpga/src/fabric/build_decoder_modules.cpp
+++ b/openfpga/src/fabric/build_decoder_modules.cpp
@@ -9,6 +9,7 @@
 #include "vtr_assert.h"
 #include "vtr_time.h"
 
+#include "openfpga_reserved_words.h"
 #include "openfpga_naming.h"
 #include "decoder_library_utils.h"
 #include "module_manager_utils.h"
@@ -18,6 +19,61 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
+/***************************************************************************************
+ * Create a module for a decoder with a given output size
+ *
+ *                     Data input
+ *                   | | ... | 
+ *                   v v     v
+ *                 +-----------+
+ *                /             \
+ *      enable-->/    Decoder    \
+ *              +-----------------+
+ *                | | | ... | | |
+ *                v v v     v v v
+ *                  Data Outputs
+ *               
+ *  The outputs are assumes to be one-hot codes (at most only one '1' exist)
+ *  Considering this fact, there are only num_of_outputs conditions to be encoded.
+ *  Therefore, the number of inputs is ceil(log(num_of_outputs)/log(2))
+ ***************************************************************************************/
+ModuleId build_frame_memory_decoder_module(ModuleManager& module_manager,
+                                           const DecoderLibrary& decoder_lib,
+                                           const DecoderId& decoder) {
+  /* Get the number of inputs */
+  size_t addr_size = decoder_lib.addr_size(decoder);
+  size_t data_size = decoder_lib.data_size(decoder);
+
+  /* Create a name for the local encoder */
+  std::string module_name = generate_frame_memory_decoder_subckt_name(addr_size, data_size);
+
+  /* Create a Verilog Module based on the circuit model, and add to module manager */
+  ModuleId module_id = module_manager.add_module(module_name); 
+  VTR_ASSERT(true == module_manager.valid_module_id(module_id));
+
+  /* Add enable port */
+  BasicPort en_port(std::string(DECODER_ENABLE_PORT_NAME), 1);
+  module_manager.add_port(module_id, en_port, ModuleManager::MODULE_INPUT_PORT);
+  /* Add each input port */
+  BasicPort addr_port(std::string(DECODER_ADDRESS_PORT_NAME), addr_size);
+  module_manager.add_port(module_id, addr_port, ModuleManager::MODULE_INPUT_PORT);
+  /* Add each output port */
+  BasicPort data_port(std::string(DECODER_DATA_PORT_NAME), data_size);
+  module_manager.add_port(module_id, data_port, ModuleManager::MODULE_OUTPUT_PORT);
+
+  /* Data port is registered. It should be outputted as 
+   *   output reg [lsb:msb] data 
+   */
+  module_manager.set_port_is_register(module_id, data_port.get_name(), true);
+  /* Add data_in port */
+  if (true == decoder_lib.use_data_inv_port(decoder)) {
+    BasicPort data_inv_port(std::string(DECODER_DATA_INV_PORT_NAME), data_size);
+    module_manager.add_port(module_id, data_inv_port, ModuleManager::MODULE_OUTPUT_PORT);
+  }
+
+  return module_id;
+}
+
 /***************************************************************************************
  * Create a module for a decoder with a given output size
  *
@@ -44,7 +100,7 @@ void build_mux_local_decoder_module(ModuleManager& module_manager,
   size_t addr_size = decoder_lib.addr_size(decoder);
   size_t data_size = decoder_lib.data_size(decoder);
 
-  /* TODO: create a name for the local encoder */
+  /* Create a name for the local encoder */
   std::string module_name = generate_mux_local_decoder_subckt_name(addr_size, data_size);
 
   /* Create a Verilog Module based on the circuit model, and add to module manager */
@@ -67,7 +123,6 @@ void build_mux_local_decoder_module(ModuleManager& module_manager,
   module_manager.add_port(module_id, data_inv_port, ModuleManager::MODULE_OUTPUT_PORT);
 }
 
-
 /***************************************************************************************
  * This function will generate all the unique Verilog modules of local decoders for 
  * the multiplexers used in a FPGA fabric
diff --git a/openfpga/src/fabric/build_decoder_modules.h b/openfpga/src/fabric/build_decoder_modules.h
index 842aef8c4..bf18e47d4 100644
--- a/openfpga/src/fabric/build_decoder_modules.h
+++ b/openfpga/src/fabric/build_decoder_modules.h
@@ -5,6 +5,7 @@
  * Include header files that are required by function declaration
  *******************************************************************/
 #include "module_manager.h"
+#include "decoder_library.h"
 #include "mux_library.h"
 #include "circuit_library.h"
 
@@ -15,6 +16,10 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
+ModuleId build_frame_memory_decoder_module(ModuleManager& module_manager,
+                                           const DecoderLibrary& decoder_lib,
+                                           const DecoderId& decoder);
+
 void build_mux_local_decoder_modules(ModuleManager& module_manager,
                                      const MuxLibrary& mux_lib,
                                      const CircuitLibrary& circuit_lib);
diff --git a/openfpga/src/fabric/build_device_module.cpp b/openfpga/src/fabric/build_device_module.cpp
index 9680285fa..1d65fef7c 100644
--- a/openfpga/src/fabric/build_device_module.cpp
+++ b/openfpga/src/fabric/build_device_module.cpp
@@ -27,8 +27,9 @@ namespace openfpga {
  * for a FPGA fabric
  *******************************************************************/
 ModuleManager build_device_module_graph(IoLocationMap& io_location_map,
-                                        const DeviceContext& vpr_device_ctx,
+                                        DecoderLibrary& decoder_lib,
                                         const OpenfpgaContext& openfpga_ctx,
+                                        const DeviceContext& vpr_device_ctx,
                                         const bool& compress_routing,
                                         const bool& duplicate_grid_pin,
                                         const bool& verbose) {
@@ -66,7 +67,9 @@ ModuleManager build_device_module_graph(IoLocationMap& io_location_map,
   build_wire_modules(module_manager, openfpga_ctx.arch().circuit_lib);
 
   /* Build memory modules */
-  build_memory_modules(module_manager, openfpga_ctx.mux_lib(), 
+  build_memory_modules(module_manager,
+                       decoder_lib,
+                       openfpga_ctx.mux_lib(), 
                        openfpga_ctx.arch().circuit_lib,
                        openfpga_ctx.arch().config_protocol.type());
 
diff --git a/openfpga/src/fabric/build_device_module.h b/openfpga/src/fabric/build_device_module.h
index b8f8c0ac8..75a9f982c 100644
--- a/openfpga/src/fabric/build_device_module.h
+++ b/openfpga/src/fabric/build_device_module.h
@@ -15,8 +15,9 @@
 namespace openfpga {
 
 ModuleManager build_device_module_graph(IoLocationMap& io_location_map,
-                                        const DeviceContext& vpr_device_ctx,
+                                        DecoderLibrary& decoder_lib,
                                         const OpenfpgaContext& openfpga_ctx,
+                                        const DeviceContext& vpr_device_ctx,
                                         const bool& compress_routing,
                                         const bool& duplicate_grid_pin,
                                         const bool& verbose);
diff --git a/openfpga/src/fabric/build_memory_modules.cpp b/openfpga/src/fabric/build_memory_modules.cpp
index 299bf6d70..bbdb01fef 100644
--- a/openfpga/src/fabric/build_memory_modules.cpp
+++ b/openfpga/src/fabric/build_memory_modules.cpp
@@ -15,12 +15,14 @@
 #include "mux_graph.h"
 #include "module_manager.h"
 #include "circuit_library_utils.h"
+#include "decoder_library_utils.h"
 #include "module_manager_utils.h"
 #include "mux_utils.h"
 
 #include "openfpga_reserved_words.h"
 #include "openfpga_naming.h"
 
+#include "build_decoder_modules.h"
 #include "build_memory_modules.h"
 
 /* begin namespace openfpga */
@@ -553,6 +555,178 @@ void build_memory_bank_module(ModuleManager& module_manager,
   add_module_global_ports_from_child_modules(module_manager, mem_module);
 }
 
+/*********************************************************************
+ * Frame-based Memory organization
+ *
+ *              EN      Address    Data
+ *               |         |         |
+ *               v         v         v
+ *      +------------------------------------+
+ *      |           Address Decoder          |
+ *      +------------------------------------+
+ *          |            |               |
+ *          v            v               v
+ *      +-------+    +-------+       +-------+
+ *      | SRAM  |    | SRAM  |  ...  | SRAM  |
+ *      |  [0]  |    |  [1]  |       | [N-1] |
+ *      +-------+    +-------+       +-------+
+ *          |            |      ...      |
+ *          v            v               v
+ *      +------------------------------------+
+ *      |   Multiplexer Configuration port   |
+ *
+ ********************************************************************/
+static 
+void build_frame_memory_module(ModuleManager& module_manager,
+                               DecoderLibrary& frame_decoder_lib,
+                               const CircuitLibrary& circuit_lib,
+                               const std::string& module_name,
+                               const CircuitModelId& sram_model,
+                               const size_t& num_mems) {
+
+  /* Get the global ports required by the SRAM */
+  std::vector<enum e_circuit_model_port_type> global_port_types;
+  global_port_types.push_back(CIRCUIT_MODEL_PORT_CLOCK);
+  global_port_types.push_back(CIRCUIT_MODEL_PORT_INPUT);
+  std::vector<CircuitPortId> sram_global_ports = circuit_lib.model_global_ports_by_type(sram_model, global_port_types, true, false);
+  /* Get the input ports from the SRAM */
+  std::vector<CircuitPortId> sram_input_ports = circuit_lib.model_ports_by_type(sram_model, CIRCUIT_MODEL_PORT_INPUT, true);
+  /* A SRAM cell with BL/WL should not have any input */
+  VTR_ASSERT( 0 == sram_input_ports.size() );
+
+  /* Get the output ports from the SRAM */
+  std::vector<CircuitPortId> sram_output_ports = circuit_lib.model_ports_by_type(sram_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
+
+  /* Get the BL/WL ports from the SRAM 
+   * Here, we consider that the WL port will be EN signal of a SRAM
+   * and the BL port will be the data_in signal of a SRAM  
+   */
+  std::vector<CircuitPortId> sram_bl_ports  = circuit_lib.model_ports_by_type(sram_model, CIRCUIT_MODEL_PORT_BL, true);
+  std::vector<CircuitPortId> sram_blb_ports = circuit_lib.model_ports_by_type(sram_model, CIRCUIT_MODEL_PORT_BLB, true);
+  std::vector<CircuitPortId> sram_wl_ports  = circuit_lib.model_ports_by_type(sram_model, CIRCUIT_MODEL_PORT_WL, true);
+  std::vector<CircuitPortId> sram_wlb_ports = circuit_lib.model_ports_by_type(sram_model, CIRCUIT_MODEL_PORT_WLB, true);
+
+  /* We do NOT expect any BLB port here!!!
+   * TODO: to suppor this, we need an inverter circuit model to be specified by users !!!  
+   */
+  VTR_ASSERT(1 == sram_bl_ports.size());
+  VTR_ASSERT(1 == circuit_lib.port_size(sram_bl_ports[0]));
+  VTR_ASSERT(1 == sram_wl_ports.size());
+  VTR_ASSERT(1 == circuit_lib.port_size(sram_wl_ports[0]));
+  VTR_ASSERT(0 == sram_blb_ports.size());
+
+  /* Create a module and add to the module manager */
+  ModuleId mem_module = module_manager.add_module(module_name); 
+  VTR_ASSERT(true == module_manager.valid_module_id(mem_module));
+
+  /* Find the specification of the decoder:
+   * Size of address port and data input 
+   */
+  size_t addr_size = find_mux_local_decoder_addr_size(num_mems);
+  /* Data input should match the WL (data_in) of a SRAM */
+  size_t data_size = num_mems * circuit_lib.port_size(sram_bl_ports[0]); 
+  bool use_data_inv = (0 < sram_blb_ports.size()); 
+ 
+  /* Search the decoder library
+   * If we find one, we use the module.
+   * Otherwise, we create one and add it to the decoder library
+   */
+  DecoderId decoder_id = frame_decoder_lib.find_decoder(addr_size, data_size, true, true, use_data_inv);
+  if (DecoderId::INVALID() == decoder_id) {
+    decoder_id = frame_decoder_lib.add_decoder(addr_size, data_size, true, true, use_data_inv);
+  }
+  VTR_ASSERT(DecoderId::INVALID() != decoder_id);
+
+  /* Create a module if not existed yet */
+  std::string decoder_module_name = generate_frame_memory_decoder_subckt_name(addr_size, data_size);
+  ModuleId decoder_module = module_manager.find_module(decoder_module_name);
+  if (ModuleId::INVALID() == decoder_module) {
+    decoder_module = build_frame_memory_decoder_module(module_manager,
+                                                       frame_decoder_lib,
+                                                       decoder_id);
+  }
+  VTR_ASSERT(ModuleId::INVALID() != decoder_module);
+  
+  /* Add module ports */
+  /* Input: Enable port */
+  BasicPort en_port(std::string(DECODER_ENABLE_PORT_NAME), 1);
+  ModulePortId mem_en_port = module_manager.add_port(mem_module, en_port, ModuleManager::MODULE_INPUT_PORT);
+
+  /* Input: Address port */
+  BasicPort addr_port(std::string(DECODER_ADDRESS_PORT_NAME), addr_size);
+  ModulePortId mem_addr_port = module_manager.add_port(mem_module, addr_port, ModuleManager::MODULE_INPUT_PORT);
+
+  /* Input: Data port */
+  BasicPort data_port(std::string(DECODER_DATA_PORT_NAME), data_size);
+  ModulePortId mem_data_port = module_manager.add_port(mem_module, data_port, ModuleManager::MODULE_INPUT_PORT);
+
+  /* Add each output port: port width should match the number of memories */
+  for (const auto& port : sram_output_ports) {
+    BasicPort output_port(circuit_lib.port_prefix(port), num_mems * circuit_lib.port_size(port));
+    module_manager.add_port(mem_module, output_port, ModuleManager::MODULE_OUTPUT_PORT);
+  }
+
+  /* Instanciate the decoder module here */
+  VTR_ASSERT(0 == module_manager.num_instance(mem_module, decoder_module));
+  module_manager.add_child_module(mem_module, decoder_module);
+
+  /* Find the sram module in the module manager */
+  ModuleId sram_mem_module = module_manager.find_module(circuit_lib.model_name(sram_model));
+
+  /* Build module nets */
+  /* Wire enable port to decoder enable port */
+  ModulePortId decoder_en_port = module_manager.find_module_port(decoder_module, std::string(DECODER_ENABLE_PORT_NAME));
+  add_module_bus_nets(module_manager, mem_module,
+                      mem_module, 0, mem_en_port,
+                      decoder_module, 0, decoder_en_port);
+
+  /* Wire address port to decoder address port */
+  ModulePortId decoder_addr_port = module_manager.find_module_port(decoder_module, std::string(DECODER_ADDRESS_PORT_NAME));
+  add_module_bus_nets(module_manager, mem_module,
+                      mem_module, 0, mem_addr_port,
+                      decoder_module, 0, decoder_addr_port);
+
+  /* Instanciate each submodule */
+  for (size_t i = 0; i < num_mems; ++i) {
+    /* Memory seed module instanciation */
+    size_t sram_instance = module_manager.num_instance(mem_module, sram_mem_module);
+    module_manager.add_child_module(mem_module, sram_mem_module);
+
+    /* Wire data_in port to SRAM BL port */
+    ModulePortId sram_bl_port = module_manager.find_module_port(sram_mem_module, circuit_lib.port_lib_name(sram_bl_ports[0]));
+    add_module_bus_nets(module_manager, mem_module,
+                        mem_module, 0, mem_data_port,
+                        sram_mem_module, sram_instance, sram_bl_port);
+
+    /* Wire decoder data_out port to sram WL ports */
+    ModulePortId sram_wl_port = module_manager.find_module_port(sram_mem_module, circuit_lib.port_lib_name(sram_wl_ports[0]));
+    ModulePortId decoder_data_port = module_manager.find_module_port(decoder_module, std::string(DECODER_DATA_PORT_NAME));
+    ModuleNetId wl_net = module_manager.create_module_net(mem_module);
+    /* Source node of the input net is the input of memory module */
+    module_manager.add_module_net_source(mem_module, wl_net, decoder_module, 0, decoder_data_port, sram_instance);
+    module_manager.add_module_net_sink(mem_module, wl_net, sram_mem_module, sram_instance, sram_wl_port, 0);
+
+    /* Optional: Wire decoder data_out inverted port to sram WLB ports */
+    if (true == use_data_inv) {
+      ModulePortId sram_wlb_port = module_manager.find_module_port(sram_mem_module, circuit_lib.port_lib_name(sram_wlb_ports[0]));
+      ModulePortId decoder_data_inv_port = module_manager.find_module_port(decoder_module, std::string(DECODER_DATA_INV_PORT_NAME));
+      ModuleNetId wlb_net = module_manager.create_module_net(mem_module);
+      /* Source node of the input net is the input of memory module */
+      module_manager.add_module_net_source(mem_module, wlb_net, decoder_module, 0, decoder_data_inv_port, sram_instance);
+      module_manager.add_module_net_sink(mem_module, wlb_net, sram_mem_module, sram_instance, sram_wlb_port, 0);
+    }
+
+    /* Wire inputs of parent module to outputs of child modules */
+    add_module_output_nets_to_mem_modules(module_manager, mem_module, circuit_lib, sram_output_ports, sram_mem_module, i, sram_instance);
+  }
+
+  /* Add global ports to the pb_module:
+   * This is a much easier job after adding sub modules (instances), 
+   * we just need to find all the global ports from the child modules and build a list of it
+   */
+  add_module_global_ports_from_child_modules(module_manager, mem_module);
+}
+
 
 /*********************************************************************
  * Generate Verilog modules for the memories that are used
@@ -566,6 +740,7 @@ void build_memory_bank_module(ModuleManager& module_manager,
  ********************************************************************/
 static 
 void build_memory_module(ModuleManager& module_manager,
+                         DecoderLibrary& arch_decoder_lib,
                          const CircuitLibrary& circuit_lib,
                          const e_config_protocol_type& sram_orgz_type,
                          const std::string& module_name,
@@ -574,7 +749,7 @@ void build_memory_module(ModuleManager& module_manager,
   switch (sram_orgz_type) {
   case CONFIG_MEM_STANDALONE:
     build_memory_standalone_module(module_manager, circuit_lib, 
-                                           module_name, sram_model, num_mems);
+                                   module_name, sram_model, num_mems);
     break;
   case CONFIG_MEM_SCAN_CHAIN:
     build_memory_chain_module(module_manager, circuit_lib,  
@@ -584,8 +759,13 @@ void build_memory_module(ModuleManager& module_manager,
     build_memory_bank_module(module_manager, circuit_lib,
                              module_name, sram_model, num_mems);
     break;
+  case CONFIG_MEM_FRAME_BASED:
+    build_frame_memory_module(module_manager, arch_decoder_lib, circuit_lib,
+                              module_name, sram_model, num_mems);
+    break;
   default:
-    VTR_LOGF_ERROR(__FILE__, __LINE__, "Invalid SRAM organization!\n");
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid configurable memory organization!\n");
     exit(1);
   }
 }
@@ -606,6 +786,7 @@ void build_memory_module(ModuleManager& module_manager,
  ********************************************************************/
 static 
 void build_mux_memory_module(ModuleManager& module_manager,
+                             DecoderLibrary& arch_decoder_lib,
                              const CircuitLibrary& circuit_lib,
                              const e_config_protocol_type& sram_orgz_type,
                              const CircuitModelId& mux_model,
@@ -626,7 +807,8 @@ void build_mux_memory_module(ModuleManager& module_manager,
     std::vector<CircuitModelId> sram_models = find_circuit_sram_models(circuit_lib, mux_model);
     VTR_ASSERT( 1 == sram_models.size() );
 
-    build_memory_module(module_manager, circuit_lib, sram_orgz_type, module_name, sram_models[0], num_config_bits);
+    build_memory_module(module_manager, arch_decoder_lib,
+                        circuit_lib, sram_orgz_type, module_name, sram_models[0], num_config_bits);
     break;
   }
   case CIRCUIT_MODEL_DESIGN_RRAM:
@@ -659,6 +841,7 @@ void build_mux_memory_module(ModuleManager& module_manager,
  * memory-bank organization for the memories.
  ********************************************************************/
 void build_memory_modules(ModuleManager& module_manager,
+                          DecoderLibrary& arch_decoder_lib,
                           const MuxLibrary& mux_lib,
                           const CircuitLibrary& circuit_lib,
                           const e_config_protocol_type& sram_orgz_type) {
@@ -676,7 +859,8 @@ void build_memory_modules(ModuleManager& module_manager,
       continue;
     }
     /* Create a Verilog module for the memories used by the multiplexer */
-    build_mux_memory_module(module_manager, circuit_lib, sram_orgz_type, mux_model, mux_graph);
+    build_mux_memory_module(module_manager, arch_decoder_lib, 
+                            circuit_lib, sram_orgz_type, mux_model, mux_graph);
   }
 
   /* Create the memory circuits for non-MUX circuit models.
@@ -708,7 +892,8 @@ void build_memory_modules(ModuleManager& module_manager,
     std::string module_name = generate_memory_module_name(circuit_lib, model, sram_models[0], std::string(MEMORY_MODULE_POSTFIX));
 
     /* Create a Verilog module for the memories used by the circuit model */
-    build_memory_module(module_manager, circuit_lib, sram_orgz_type, module_name, sram_models[0], num_mems);
+    build_memory_module(module_manager, arch_decoder_lib, 
+                        circuit_lib, sram_orgz_type, module_name, sram_models[0], num_mems);
   }
 }
 
diff --git a/openfpga/src/fabric/build_memory_modules.h b/openfpga/src/fabric/build_memory_modules.h
index 2728d1d81..3551426a2 100644
--- a/openfpga/src/fabric/build_memory_modules.h
+++ b/openfpga/src/fabric/build_memory_modules.h
@@ -4,6 +4,7 @@
 /********************************************************************
  * Include header files that are required by function declaration
  *******************************************************************/
+#include "decoder_library.h"
 #include "circuit_library.h"
 #include "mux_library.h"
 #include "module_manager.h"
@@ -16,6 +17,7 @@
 namespace openfpga {
 
 void build_memory_modules(ModuleManager& module_manager,
+                          DecoderLibrary& arch_decoder_lib,
                           const MuxLibrary& mux_lib,
                           const CircuitLibrary& circuit_lib,
                           const e_config_protocol_type& sram_orgz_type);
diff --git a/openfpga/src/utils/module_manager_utils.cpp b/openfpga/src/utils/module_manager_utils.cpp
index b1408dcad..44e13c65a 100644
--- a/openfpga/src/utils/module_manager_utils.cpp
+++ b/openfpga/src/utils/module_manager_utils.cpp
@@ -1227,6 +1227,66 @@ size_t find_module_num_config_bits_from_child_modules(ModuleManager& module_mana
   return num_config_bits;
 }
 
+/********************************************************************
+ * Add a bus of nets to a module (cur_module_id)
+ * Note: 
+ * - both src and des module should exist in the module manager
+ * - src_module should be the cur_module or a child of it
+ * - des_module should be the cur_module or a child of it
+ * - src_instance should be valid and des_instance should be valid as well
+ * - src port size should match the des port size
+ *******************************************************************/
+void add_module_bus_nets(ModuleManager& module_manager,
+                         const ModuleId& cur_module_id,
+                         const ModuleId& src_module_id,
+                         const size_t& src_instance_id,
+                         const ModulePortId& src_module_port_id,
+                         const ModuleId& des_module_id,
+                         const size_t& des_instance_id,
+                         const ModulePortId& des_module_port_id) {
+
+  VTR_ASSERT(true == module_manager.valid_module_id(cur_module_id));
+  VTR_ASSERT(true == module_manager.valid_module_id(src_module_id));
+  VTR_ASSERT(true == module_manager.valid_module_id(des_module_id));
+
+  VTR_ASSERT(true == module_manager.valid_module_port_id(src_module_id, src_module_port_id));
+  VTR_ASSERT(true == module_manager.valid_module_port_id(des_module_id, des_module_port_id));
+
+  if (src_module_id == cur_module_id) {
+    VTR_ASSERT(0 == src_instance_id);
+  } else {
+    VTR_ASSERT(src_instance_id < module_manager.num_instance(cur_module_id, src_module_id));
+  }
+
+  if (des_module_id == cur_module_id) {
+    VTR_ASSERT(0 == des_instance_id);
+  } else {
+    VTR_ASSERT(des_instance_id < module_manager.num_instance(cur_module_id, des_module_id));
+  }
+
+  const BasicPort& src_port = module_manager.module_port(src_module_id, src_module_port_id);
+  const BasicPort& des_port = module_manager.module_port(des_module_id, des_module_port_id);
+
+  if (src_port.get_width() != des_port.get_width()) {
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Unmatched port size: src_port is %lu while des_port is %lu!\n");
+    exit(1);
+  }
+
+  /* Create a net for each pin */
+  for (size_t pin_id = 0; pin_id < src_port.pins().size(); ++pin_id) {
+    ModuleNetId net = module_manager.module_instance_port_net(cur_module_id,
+                                                              src_module_id, src_instance_id, 
+                                                              src_module_port_id, src_port.pins()[pin_id]);
+    if (ModuleNetId::INVALID() == net) { 
+      net = module_manager.create_module_net(cur_module_id);
+    }
+    /* Configure the net source */
+    module_manager.add_module_net_source(cur_module_id, net, src_module_id, src_instance_id, src_module_port_id, src_port.pins()[pin_id]);
+    /* Configure the net sink */
+    module_manager.add_module_net_sink(cur_module_id, net, des_module_id, des_instance_id, des_module_port_id, des_port.pins()[pin_id]);
+  }
+}
 
 /********************************************************************
  * TODO:
diff --git a/openfpga/src/utils/module_manager_utils.h b/openfpga/src/utils/module_manager_utils.h
index fcc95b8ba..0ecdfd282 100644
--- a/openfpga/src/utils/module_manager_utils.h
+++ b/openfpga/src/utils/module_manager_utils.h
@@ -129,6 +129,15 @@ size_t find_module_num_config_bits_from_child_modules(ModuleManager& module_mana
                                                       const CircuitModelId& sram_model,
                                                       const e_config_protocol_type& sram_orgz_type);
 
+void add_module_bus_nets(ModuleManager& module_manager,
+                         const ModuleId& cur_module_id,
+                         const ModuleId& src_module_id,
+                         const size_t& src_instance_id,
+                         const ModulePortId& src_module_port_id,
+                         const ModuleId& des_module_id,
+                         const size_t& des_instance_id,
+                         const ModulePortId& des_module_port_id);
+
 } /* end namespace openfpga */
 
 #endif

From 290dd1a8a68cfa893e77d57075a7c6c5023218ad Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 26 May 2020 18:55:55 -0600
Subject: [PATCH 563/645] add frame decoder builder to all the module graph
 builder except the top-level

---
 openfpga/src/base/openfpga_naming.cpp         |  17 +-
 openfpga/src/base/openfpga_reserved_words.h   |   5 +-
 openfpga/src/fabric/build_decoder_modules.cpp |   4 +-
 openfpga/src/fabric/build_device_module.cpp   |   6 +-
 openfpga/src/fabric/build_grid_modules.cpp    |  27 +-
 openfpga/src/fabric/build_grid_modules.h      |   2 +
 openfpga/src/fabric/build_memory_modules.cpp  |   6 +-
 openfpga/src/fabric/build_routing_modules.cpp |  18 +-
 openfpga/src/fabric/build_routing_modules.h   |   3 +
 openfpga/src/fabric/build_top_module.cpp      |  14 +-
 .../src/fabric/build_top_module_memory.cpp    |   3 +
 openfpga/src/utils/memory_utils.cpp           |   4 +
 openfpga/src/utils/module_manager_utils.cpp   | 256 +++++++++++++++++-
 openfpga/src/utils/module_manager_utils.h     |   6 +
 14 files changed, 337 insertions(+), 34 deletions(-)

diff --git a/openfpga/src/base/openfpga_naming.cpp b/openfpga/src/base/openfpga_naming.cpp
index bf82a1d7c..5c9c81eb3 100644
--- a/openfpga/src/base/openfpga_naming.cpp
+++ b/openfpga/src/base/openfpga_naming.cpp
@@ -798,8 +798,23 @@ std::string generate_sram_port_name(const e_config_protocol_type& sram_orgz_type
       port_name = std::string("wlb"); 
     }
     break;
+  case CONFIG_MEM_FRAME_BASED:
+    /* Only one input port is required, which is the address port
+     *
+     *        EN         ADDR      DATA_IN
+     *         |          |           |
+     *         v          v           v
+     *     +---------------------------------+
+     *     |       Frame decoder             |
+     *     +---------------------------------+
+     *
+     */
+    VTR_ASSERT(port_type == CIRCUIT_MODEL_PORT_INPUT);
+    port_name = std::string(DECODER_ADDRESS_PORT_NAME); 
+    break;
   default:
-    VTR_LOG_ERROR("Invalid type of SRAM organization !\n");
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid type of SRAM organization !\n");
     exit(1);
   }
 
diff --git a/openfpga/src/base/openfpga_reserved_words.h b/openfpga/src/base/openfpga_reserved_words.h
index c556a19b1..132858687 100644
--- a/openfpga/src/base/openfpga_reserved_words.h
+++ b/openfpga/src/base/openfpga_reserved_words.h
@@ -33,8 +33,9 @@ constexpr char* CONNECTION_BLOCK_MUX_INSTANCE_PREFIX = "mux_";
 /* Decoder naming constant strings */
 constexpr char* DECODER_ENABLE_PORT_NAME = "enable";
 constexpr char* DECODER_ADDRESS_PORT_NAME = "address";
-constexpr char* DECODER_DATA_PORT_NAME = "data";
-constexpr char* DECODER_DATA_INV_PORT_NAME = "data_inv";
+constexpr char* DECODER_DATA_IN_PORT_NAME = "data_in";
+constexpr char* DECODER_DATA_OUT_PORT_NAME = "data_out";
+constexpr char* DECODER_DATA_OUT_INV_PORT_NAME = "data_out_inv";
 
 /* Inverted port naming */
 constexpr char* INV_PORT_POSTFIX = "_inv";
diff --git a/openfpga/src/fabric/build_decoder_modules.cpp b/openfpga/src/fabric/build_decoder_modules.cpp
index a2accae89..ada36e3e7 100644
--- a/openfpga/src/fabric/build_decoder_modules.cpp
+++ b/openfpga/src/fabric/build_decoder_modules.cpp
@@ -58,7 +58,7 @@ ModuleId build_frame_memory_decoder_module(ModuleManager& module_manager,
   BasicPort addr_port(std::string(DECODER_ADDRESS_PORT_NAME), addr_size);
   module_manager.add_port(module_id, addr_port, ModuleManager::MODULE_INPUT_PORT);
   /* Add each output port */
-  BasicPort data_port(std::string(DECODER_DATA_PORT_NAME), data_size);
+  BasicPort data_port(std::string(DECODER_DATA_OUT_PORT_NAME), data_size);
   module_manager.add_port(module_id, data_port, ModuleManager::MODULE_OUTPUT_PORT);
 
   /* Data port is registered. It should be outputted as 
@@ -67,7 +67,7 @@ ModuleId build_frame_memory_decoder_module(ModuleManager& module_manager,
   module_manager.set_port_is_register(module_id, data_port.get_name(), true);
   /* Add data_in port */
   if (true == decoder_lib.use_data_inv_port(decoder)) {
-    BasicPort data_inv_port(std::string(DECODER_DATA_INV_PORT_NAME), data_size);
+    BasicPort data_inv_port(std::string(DECODER_DATA_OUT_INV_PORT_NAME), data_size);
     module_manager.add_port(module_id, data_inv_port, ModuleManager::MODULE_OUTPUT_PORT);
   }
 
diff --git a/openfpga/src/fabric/build_device_module.cpp b/openfpga/src/fabric/build_device_module.cpp
index 1d65fef7c..ee2547d7d 100644
--- a/openfpga/src/fabric/build_device_module.cpp
+++ b/openfpga/src/fabric/build_device_module.cpp
@@ -74,7 +74,9 @@ ModuleManager build_device_module_graph(IoLocationMap& io_location_map,
                        openfpga_ctx.arch().config_protocol.type());
 
   /* Build grid and programmable block modules */
-  build_grid_modules(module_manager, vpr_device_ctx,
+  build_grid_modules(module_manager,
+                     decoder_lib,
+                     vpr_device_ctx,
                      openfpga_ctx.vpr_device_annotation(),
                      openfpga_ctx.arch().circuit_lib,
                      openfpga_ctx.mux_lib(),
@@ -83,6 +85,7 @@ ModuleManager build_device_module_graph(IoLocationMap& io_location_map,
 
   if (true == compress_routing) {
     build_unique_routing_modules(module_manager,
+                                 decoder_lib,
                                  vpr_device_ctx,
                                  openfpga_ctx.vpr_device_annotation(),
                                  openfpga_ctx.device_rr_gsb(),
@@ -92,6 +95,7 @@ ModuleManager build_device_module_graph(IoLocationMap& io_location_map,
   } else {
     VTR_ASSERT_SAFE(false == compress_routing);
     build_flatten_routing_modules(module_manager,
+                                  decoder_lib,
                                   vpr_device_ctx,
                                   openfpga_ctx.vpr_device_annotation(),
                                   openfpga_ctx.device_rr_gsb(),
diff --git a/openfpga/src/fabric/build_grid_modules.cpp b/openfpga/src/fabric/build_grid_modules.cpp
index 12090d43d..b189a20fe 100644
--- a/openfpga/src/fabric/build_grid_modules.cpp
+++ b/openfpga/src/fabric/build_grid_modules.cpp
@@ -226,6 +226,7 @@ void add_primitive_module_fpga_global_io_port(ModuleManager& module_manager,
  *******************************************************************/
 static 
 void build_primitive_block_module(ModuleManager& module_manager,
+                                  DecoderLibrary& decoder_lib,
                                   const VprDeviceAnnotation& device_annotation,
                                   const CircuitLibrary& circuit_lib,
                                   const e_config_protocol_type& sram_orgz_type,
@@ -314,7 +315,7 @@ void build_primitive_block_module(ModuleManager& module_manager,
    * This is a one-shot addition that covers all the memory modules in this primitive module!
    */
   if (0 < module_manager.configurable_children(primitive_module).size()) {
-    add_module_nets_memory_config_bus(module_manager, primitive_module, 
+    add_module_nets_memory_config_bus(module_manager, decoder_lib, primitive_module, 
                                       sram_orgz_type, circuit_lib.design_tech_type(sram_model));
   }
 
@@ -799,6 +800,7 @@ void add_module_pb_graph_interc(ModuleManager& module_manager,
  *******************************************************************/
 static 
 void rec_build_logical_tile_modules(ModuleManager& module_manager,
+                                    DecoderLibrary& decoder_lib,
                                     const VprDeviceAnnotation& device_annotation,
                                     const CircuitLibrary& circuit_lib,
                                     const MuxLibrary& mux_lib,
@@ -821,7 +823,8 @@ void rec_build_logical_tile_modules(ModuleManager& module_manager,
   if (false == is_primitive_pb_type(physical_pb_type)) { 
     for (int ipb = 0; ipb < physical_mode->num_pb_type_children; ++ipb) {
       /* Go recursive to visit the children */
-      rec_build_logical_tile_modules(module_manager, device_annotation,
+      rec_build_logical_tile_modules(module_manager, decoder_lib,
+                                     device_annotation,
                                      circuit_lib, mux_lib, 
                                      sram_orgz_type, sram_model, 
                                      &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb][0]),
@@ -831,7 +834,8 @@ void rec_build_logical_tile_modules(ModuleManager& module_manager,
 
   /* For leaf node, a primitive Verilog module will be generated */
   if (true == is_primitive_pb_type(physical_pb_type)) { 
-    build_primitive_block_module(module_manager, device_annotation,
+    build_primitive_block_module(module_manager, decoder_lib,
+                                 device_annotation,
                                  circuit_lib,
                                  sram_orgz_type, sram_model, 
                                  physical_pb_graph_node,
@@ -938,7 +942,7 @@ void rec_build_logical_tile_modules(ModuleManager& module_manager,
    * This is a one-shot addition that covers all the memory modules in this pb module!
    */
   if (0 < module_manager.configurable_children(pb_module).size()) {
-    add_module_nets_memory_config_bus(module_manager, pb_module, 
+    add_module_nets_memory_config_bus(module_manager, decoder_lib, pb_module, 
                                       sram_orgz_type, circuit_lib.design_tech_type(sram_model));
   }
 
@@ -955,6 +959,7 @@ void rec_build_logical_tile_modules(ModuleManager& module_manager,
  *****************************************************************************/
 static 
 void build_physical_tile_module(ModuleManager& module_manager,
+                                DecoderLibrary& decoder_lib,
                                 const CircuitLibrary& circuit_lib,
                                 const e_config_protocol_type& sram_orgz_type,
                                 const CircuitModelId& sram_model,
@@ -1094,7 +1099,7 @@ void build_physical_tile_module(ModuleManager& module_manager,
    * This is a one-shot addition that covers all the memory modules in this pb module!
    */
   if (0 < module_manager.configurable_children(grid_module).size()) {
-    add_module_nets_memory_config_bus(module_manager, grid_module, 
+    add_module_nets_memory_config_bus(module_manager, decoder_lib, grid_module, 
                                       sram_orgz_type, circuit_lib.design_tech_type(sram_model));
   }
 
@@ -1114,6 +1119,7 @@ void build_physical_tile_module(ModuleManager& module_manager,
  *   - Only one module for each heterogeneous block
  ****************************************************************************/
 void build_grid_modules(ModuleManager& module_manager,
+                        DecoderLibrary& decoder_lib,
                         const DeviceContext& device_ctx,
                         const VprDeviceAnnotation& device_annotation,
                         const CircuitLibrary& circuit_lib,
@@ -1140,8 +1146,9 @@ void build_grid_modules(ModuleManager& module_manager,
     if (nullptr == logical_tile.pb_graph_head) {
       continue;
     }
-    rec_build_logical_tile_modules(module_manager, device_annotation,
-                                   circuit_lib, mux_lib, 
+    rec_build_logical_tile_modules(module_manager, decoder_lib,
+                                   device_annotation,
+                                   circuit_lib, mux_lib,
                                    sram_orgz_type, sram_model, 
                                    logical_tile.pb_graph_head,
                                    verbose);
@@ -1169,7 +1176,8 @@ void build_grid_modules(ModuleManager& module_manager,
       std::set<e_side> io_type_sides = find_physical_io_tile_located_sides(device_ctx.grid,
                                                                            &physical_tile);
       for (const e_side& io_type_side : io_type_sides) {
-        build_physical_tile_module(module_manager, circuit_lib,
+        build_physical_tile_module(module_manager, decoder_lib,
+                                   circuit_lib,
                                    sram_orgz_type, sram_model,
                                    &physical_tile,
                                    io_type_side,
@@ -1178,7 +1186,8 @@ void build_grid_modules(ModuleManager& module_manager,
       } 
     } else {
       /* For CLB and heterogenenous blocks */
-      build_physical_tile_module(module_manager, circuit_lib,
+      build_physical_tile_module(module_manager, decoder_lib,
+                                 circuit_lib, 
                                  sram_orgz_type, sram_model,
                                  &physical_tile,
                                  NUM_SIDES,
diff --git a/openfpga/src/fabric/build_grid_modules.h b/openfpga/src/fabric/build_grid_modules.h
index f2a8e967b..53e7f92cd 100644
--- a/openfpga/src/fabric/build_grid_modules.h
+++ b/openfpga/src/fabric/build_grid_modules.h
@@ -8,6 +8,7 @@
 #include "vpr_device_annotation.h"
 #include "module_manager.h"
 #include "mux_library.h"
+#include "decoder_library.h"
 
 /********************************************************************
  * Function declaration
@@ -17,6 +18,7 @@
 namespace openfpga {
 
 void build_grid_modules(ModuleManager& module_manager,
+                        DecoderLibrary& decoder_lib,
                         const DeviceContext& device_ctx,
                         const VprDeviceAnnotation& device_annotation,
                         const CircuitLibrary& circuit_lib,
diff --git a/openfpga/src/fabric/build_memory_modules.cpp b/openfpga/src/fabric/build_memory_modules.cpp
index bbdb01fef..f8db73d7a 100644
--- a/openfpga/src/fabric/build_memory_modules.cpp
+++ b/openfpga/src/fabric/build_memory_modules.cpp
@@ -657,7 +657,7 @@ void build_frame_memory_module(ModuleManager& module_manager,
   ModulePortId mem_addr_port = module_manager.add_port(mem_module, addr_port, ModuleManager::MODULE_INPUT_PORT);
 
   /* Input: Data port */
-  BasicPort data_port(std::string(DECODER_DATA_PORT_NAME), data_size);
+  BasicPort data_port(std::string(DECODER_DATA_IN_PORT_NAME), data_size);
   ModulePortId mem_data_port = module_manager.add_port(mem_module, data_port, ModuleManager::MODULE_INPUT_PORT);
 
   /* Add each output port: port width should match the number of memories */
@@ -700,7 +700,7 @@ void build_frame_memory_module(ModuleManager& module_manager,
 
     /* Wire decoder data_out port to sram WL ports */
     ModulePortId sram_wl_port = module_manager.find_module_port(sram_mem_module, circuit_lib.port_lib_name(sram_wl_ports[0]));
-    ModulePortId decoder_data_port = module_manager.find_module_port(decoder_module, std::string(DECODER_DATA_PORT_NAME));
+    ModulePortId decoder_data_port = module_manager.find_module_port(decoder_module, std::string(DECODER_DATA_OUT_PORT_NAME));
     ModuleNetId wl_net = module_manager.create_module_net(mem_module);
     /* Source node of the input net is the input of memory module */
     module_manager.add_module_net_source(mem_module, wl_net, decoder_module, 0, decoder_data_port, sram_instance);
@@ -709,7 +709,7 @@ void build_frame_memory_module(ModuleManager& module_manager,
     /* Optional: Wire decoder data_out inverted port to sram WLB ports */
     if (true == use_data_inv) {
       ModulePortId sram_wlb_port = module_manager.find_module_port(sram_mem_module, circuit_lib.port_lib_name(sram_wlb_ports[0]));
-      ModulePortId decoder_data_inv_port = module_manager.find_module_port(decoder_module, std::string(DECODER_DATA_INV_PORT_NAME));
+      ModulePortId decoder_data_inv_port = module_manager.find_module_port(decoder_module, std::string(DECODER_DATA_OUT_INV_PORT_NAME));
       ModuleNetId wlb_net = module_manager.create_module_net(mem_module);
       /* Source node of the input net is the input of memory module */
       module_manager.add_module_net_source(mem_module, wlb_net, decoder_module, 0, decoder_data_inv_port, sram_instance);
diff --git a/openfpga/src/fabric/build_routing_modules.cpp b/openfpga/src/fabric/build_routing_modules.cpp
index b00cc5dc5..98a94baa8 100644
--- a/openfpga/src/fabric/build_routing_modules.cpp
+++ b/openfpga/src/fabric/build_routing_modules.cpp
@@ -329,6 +329,7 @@ void build_switch_block_interc_modules(ModuleManager& module_manager,
  ********************************************************************/
 static 
 void build_switch_block_module(ModuleManager& module_manager, 
+                               DecoderLibrary& decoder_lib,
                                const VprDeviceAnnotation& device_annotation,
                                const RRGraph& rr_graph,
                                const CircuitLibrary& circuit_lib,
@@ -438,7 +439,8 @@ void build_switch_block_module(ModuleManager& module_manager,
    * This is a one-shot addition that covers all the memory modules in this primitive module!
    */
   if (0 < module_manager.configurable_children(sb_module).size()) {
-    add_module_nets_memory_config_bus(module_manager, sb_module, 
+    add_module_nets_memory_config_bus(module_manager, decoder_lib, 
+                                      sb_module, 
                                       sram_orgz_type, circuit_lib.design_tech_type(sram_model));
   }
 
@@ -709,6 +711,7 @@ void build_connection_block_interc_modules(ModuleManager& module_manager,
  ********************************************************************/
 static 
 void build_connection_block_module(ModuleManager& module_manager, 
+                                   DecoderLibrary& decoder_lib,
                                    const VprDeviceAnnotation& device_annotation,
                                    const RRGraph& rr_graph,
                                    const CircuitLibrary& circuit_lib, 
@@ -846,7 +849,8 @@ void build_connection_block_module(ModuleManager& module_manager,
    * This is a one-shot addition that covers all the memory modules in this primitive module!
    */
   if (0 < module_manager.configurable_children(cb_module).size()) {
-    add_module_nets_memory_config_bus(module_manager, cb_module, 
+    add_module_nets_memory_config_bus(module_manager, decoder_lib,
+                                      cb_module, 
                                       sram_orgz_type, circuit_lib.design_tech_type(sram_model));
   }
 
@@ -860,6 +864,7 @@ void build_connection_block_module(ModuleManager& module_manager,
  *******************************************************************/
 static 
 void build_flatten_connection_block_modules(ModuleManager& module_manager, 
+                                            DecoderLibrary& decoder_lib,
                                             const DeviceContext& device_ctx,
                                             const VprDeviceAnnotation& device_annotation,
                                             const DeviceRRGSB& device_rr_gsb,
@@ -882,6 +887,7 @@ void build_flatten_connection_block_modules(ModuleManager& module_manager,
         continue;
       }
       build_connection_block_module(module_manager, 
+                                    decoder_lib,
                                     device_annotation,
                                     device_ctx.rr_graph,
                                     circuit_lib, 
@@ -902,6 +908,7 @@ void build_flatten_connection_block_modules(ModuleManager& module_manager,
  * 2. Switch blocks
  *******************************************************************/
 void build_flatten_routing_modules(ModuleManager& module_manager,
+                                   DecoderLibrary& decoder_lib,
                                    const DeviceContext& device_ctx,
                                    const VprDeviceAnnotation& device_annotation,
                                    const DeviceRRGSB& device_rr_gsb,
@@ -922,6 +929,7 @@ void build_flatten_routing_modules(ModuleManager& module_manager,
         continue;
       }
       build_switch_block_module(module_manager,
+                                decoder_lib,
                                 device_annotation,
                                 device_ctx.rr_graph,
                                 circuit_lib, 
@@ -932,6 +940,7 @@ void build_flatten_routing_modules(ModuleManager& module_manager,
   }
 
   build_flatten_connection_block_modules(module_manager,
+                                         decoder_lib,
                                          device_ctx, 
                                          device_annotation, 
                                          device_rr_gsb, 
@@ -941,6 +950,7 @@ void build_flatten_routing_modules(ModuleManager& module_manager,
                                          verbose);
 
   build_flatten_connection_block_modules(module_manager,
+                                         decoder_lib,
                                          device_ctx, 
                                          device_annotation, 
                                          device_rr_gsb, 
@@ -962,6 +972,7 @@ void build_flatten_routing_modules(ModuleManager& module_manager,
  * the option compact_routing_hierarchy is turned on!!!
  *******************************************************************/
 void build_unique_routing_modules(ModuleManager& module_manager,
+                                  DecoderLibrary& decoder_lib,
                                   const DeviceContext& device_ctx,
                                   const VprDeviceAnnotation& device_annotation,
                                   const DeviceRRGSB& device_rr_gsb,
@@ -976,6 +987,7 @@ void build_unique_routing_modules(ModuleManager& module_manager,
   for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_module(); ++isb) {
     const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(isb);
     build_switch_block_module(module_manager,
+                              decoder_lib,
                               device_annotation,
                               device_ctx.rr_graph,
                               circuit_lib, 
@@ -989,6 +1001,7 @@ void build_unique_routing_modules(ModuleManager& module_manager,
     const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANX, icb);
 
     build_connection_block_module(module_manager, 
+                                  decoder_lib,
                                   device_annotation,
                                   device_ctx.rr_graph,
                                   circuit_lib,  
@@ -1002,6 +1015,7 @@ void build_unique_routing_modules(ModuleManager& module_manager,
     const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANY, icb);
 
     build_connection_block_module(module_manager, 
+                                  decoder_lib,
                                   device_annotation,
                                   device_ctx.rr_graph,
                                   circuit_lib, 
diff --git a/openfpga/src/fabric/build_routing_modules.h b/openfpga/src/fabric/build_routing_modules.h
index d8eb09784..d82ce3a69 100644
--- a/openfpga/src/fabric/build_routing_modules.h
+++ b/openfpga/src/fabric/build_routing_modules.h
@@ -8,6 +8,7 @@
 #include "vpr_device_annotation.h"
 #include "device_rr_gsb.h"
 #include "mux_library.h"
+#include "decoder_library.h"
 #include "circuit_library.h"
 #include "module_manager.h"
 
@@ -19,6 +20,7 @@
 namespace openfpga {
 
 void build_flatten_routing_modules(ModuleManager& module_manager,
+                                   DecoderLibrary& decoder_lib,
                                    const DeviceContext& device_ctx,
                                    const VprDeviceAnnotation& device_annotation,
                                    const DeviceRRGSB& device_rr_gsb,
@@ -28,6 +30,7 @@ void build_flatten_routing_modules(ModuleManager& module_manager,
                                    const bool& verbose);
 
 void build_unique_routing_modules(ModuleManager& module_manager,
+                                  DecoderLibrary& decoder_lib,
                                   const DeviceContext& device_ctx,
                                   const VprDeviceAnnotation& device_annotation,
                                   const DeviceRRGSB& device_rr_gsb,
diff --git a/openfpga/src/fabric/build_top_module.cpp b/openfpga/src/fabric/build_top_module.cpp
index 112b32a52..6124333c0 100644
--- a/openfpga/src/fabric/build_top_module.cpp
+++ b/openfpga/src/fabric/build_top_module.cpp
@@ -361,6 +361,13 @@ void build_top_module(ModuleManager& module_manager,
    */
   add_module_gpio_ports_from_child_modules(module_manager, top_module);
 
+  /* Organize the list of memory modules and instances */
+  organize_top_module_memory_modules(module_manager, top_module, 
+                                     circuit_lib, sram_orgz_type, sram_model,
+                                     grids, grid_instance_ids, 
+                                     device_rr_gsb, sb_instance_ids, cb_instance_ids,
+                                     compact_routing_hierarchy);
+
   /* Add shared SRAM ports from the sub-modules under this Verilog module
    * This is a much easier job after adding sub modules (instances), 
    * we just need to find all the I/O ports from the child modules and build a list of it
@@ -379,13 +386,6 @@ void build_top_module(ModuleManager& module_manager,
     add_sram_ports_to_module_manager(module_manager, top_module, circuit_lib, sram_model, sram_orgz_type, module_num_config_bits);
   }
 
-  /* Organize the list of memory modules and instances */
-  organize_top_module_memory_modules(module_manager, top_module, 
-                                     circuit_lib, sram_orgz_type, sram_model,
-                                     grids, grid_instance_ids, 
-                                     device_rr_gsb, sb_instance_ids, cb_instance_ids,
-                                     compact_routing_hierarchy);
-
   /* Add module nets to connect memory cells inside
    * This is a one-shot addition that covers all the memory modules in this pb module!
    */
diff --git a/openfpga/src/fabric/build_top_module_memory.cpp b/openfpga/src/fabric/build_top_module_memory.cpp
index 21f7a5e6c..28c003957 100644
--- a/openfpga/src/fabric/build_top_module_memory.cpp
+++ b/openfpga/src/fabric/build_top_module_memory.cpp
@@ -421,6 +421,9 @@ void add_top_module_nets_cmos_memory_config_bus(ModuleManager& module_manager,
   case CONFIG_MEM_MEMORY_BANK:
     /* TODO: */
     break;
+  case CONFIG_MEM_FRAME_BASED:
+    /* TODO: */
+    break;
   default:
     VTR_LOGF_ERROR(__FILE__, __LINE__,
                    "Invalid type of SRAM organization!\n");
diff --git a/openfpga/src/utils/memory_utils.cpp b/openfpga/src/utils/memory_utils.cpp
index 8452626d8..ef0433502 100644
--- a/openfpga/src/utils/memory_utils.cpp
+++ b/openfpga/src/utils/memory_utils.cpp
@@ -337,6 +337,10 @@ std::vector<std::string> generate_sram_port_names(const CircuitLibrary& circuit_
     }
     break;
   }
+  case CONFIG_MEM_FRAME_BASED: {
+    model_port_types.push_back(CIRCUIT_MODEL_PORT_INPUT);
+    break;
+  }
   default:
     VTR_LOG_ERROR("Invalid type of SRAM organization !\n");
     exit(1);
diff --git a/openfpga/src/utils/module_manager_utils.cpp b/openfpga/src/utils/module_manager_utils.cpp
index 44e13c65a..2819cc0b4 100644
--- a/openfpga/src/utils/module_manager_utils.cpp
+++ b/openfpga/src/utils/module_manager_utils.cpp
@@ -18,7 +18,9 @@
 #include "memory_utils.h"
 #include "pb_type_utils.h"
 
+#include "build_decoder_modules.h"
 #include "circuit_library_utils.h"
+#include "decoder_library_utils.h"
 #include "module_manager_utils.h"
 
 /* begin namespace openfpga */
@@ -173,6 +175,11 @@ void add_formal_verification_sram_ports_to_module_manager(ModuleManager& module_
  *    The other two ports are optional: BLB and WLB
  *    Note that the constraints are correletated to the checking rules 
  *    in check_circuit_library()
+ * 4. Frame-based memory:
+ *    - An Enable signal
+ *    - An address port, whose size depends on the number of config bits 
+ *      and the maximum size of address ports of configurable children
+ *    - An data_in port (single-bit)
  ********************************************************************/
 void add_sram_ports_to_module_manager(ModuleManager& module_manager, 
                                       const ModuleId& module_id,
@@ -214,6 +221,18 @@ void add_sram_ports_to_module_manager(ModuleManager& module_manager,
     }
     break;
   }
+  case CONFIG_MEM_FRAME_BASED: { 
+    BasicPort en_port(std::string(DECODER_ENABLE_PORT_NAME), 1);
+    module_manager.add_port(module_id, en_port, ModuleManager::MODULE_INPUT_PORT);
+
+    BasicPort addr_port(std::string(DECODER_ADDRESS_PORT_NAME), num_config_bits);
+    module_manager.add_port(module_id, addr_port, ModuleManager::MODULE_INPUT_PORT);
+
+    BasicPort din_port(std::string(DECODER_DATA_IN_PORT_NAME), 1);
+    module_manager.add_port(module_id, din_port, ModuleManager::MODULE_INPUT_PORT);
+
+    break;
+  }
   default:
     VTR_LOG_ERROR("Invalid type of SRAM organization !\n");
     exit(1);
@@ -750,6 +769,194 @@ void add_module_nets_cmos_memory_chain_config_bus(ModuleManager& module_manager,
   }
 }
 
+/********************************************************************
+ * This function will 
+ * - Add a frame decoder to the parent module 
+ *   - If the decoder exists in the library, we use the module
+ *   - If the decoder does not exist, we create a new module and use it
+ * - create nets for the following types of connections:
+ *   - Connect the EN signal, first few bits of address of parent module 
+ *     to the frame decoder inputs
+ *   - Connect the enable (EN) port of memory modules under the parent module
+ *     to the frame decoder outputs
+ *   - Connect the data_in (Din) of parent module to the data_in of the all
+ *     the memory modules
+ *
+ *       EN      ADDR[X - 1: X - log(N)/log2]
+ *        |        |
+ *        v        v                                        
+ *  +--------------------------------------------+
+ *  |             Frame-based decoder            |
+ *  |                                            |
+ *  |                Data out                    |
+ *  +--------------------------------------------+
+ *                     |
+ *       +-------------+--------------------+
+ *       |             |                    |  
+ *   Din |         Din |                Din |  
+ *    |  |          |  |                 |  |
+ *    v  v          v  v                 v  v
+ *  +--------+    +--------+            +--------+
+ *  | Memory |    | Memory |    ...     | Memory |
+ *  | Module |    | Module |            | Module |
+ *  |   [0]  |    |   [1]  |            |  [N-1] |             
+ *  +--------+    +--------+            +--------+
+ *       ^             ^                    ^
+ *       |             |                    |
+ *       +-------------+--------------------+
+ *                     |
+ *                  ADDR[X - log(N)/log2 - 1: 0]
+ *
+ * Note:
+ *  - X is the port size of address port of the parent module
+ *  - the address port of child memory modules may be smaller than 
+ *    X - log(N)/log2. In such case, we will drop the MSBs until it fit
+ *
+ *********************************************************************/
+void add_module_nets_cmos_memory_frame_config_bus(ModuleManager& module_manager,
+                                                  DecoderLibrary& decoder_lib,
+                                                  const ModuleId& parent_module) {
+  std::vector<ModuleId> configurable_children = module_manager.configurable_children(parent_module);
+
+  /* Find the decoder specification */
+  size_t addr_size = find_mux_local_decoder_addr_size(configurable_children.size());
+  /* Data input should match the WL (data_in) of a SRAM */
+  size_t data_size = configurable_children.size(); 
+
+  /* Search the decoder library and try to find one 
+   * If not found, create a new module and add it to the module manager 
+   */
+  DecoderId decoder_id = decoder_lib.find_decoder(addr_size, data_size, true, true, false);
+  if (DecoderId::INVALID() == decoder_id) {
+    decoder_id = decoder_lib.add_decoder(addr_size, data_size, true, true, false);
+  }
+  VTR_ASSERT(DecoderId::INVALID() != decoder_id);
+
+  /* Create a module if not existed yet */
+  std::string decoder_module_name = generate_frame_memory_decoder_subckt_name(addr_size, data_size);
+  ModuleId decoder_module = module_manager.find_module(decoder_module_name);
+  if (ModuleId::INVALID() == decoder_module) {
+    decoder_module = build_frame_memory_decoder_module(module_manager,
+                                                       decoder_lib,
+                                                       decoder_id);
+  }
+  VTR_ASSERT(ModuleId::INVALID() != decoder_module);
+
+  /* Instanciate the decoder module here */
+  VTR_ASSERT(0 == module_manager.num_instance(parent_module, decoder_module));
+  module_manager.add_child_module(parent_module, decoder_module);
+
+  /* Connect the enable (EN) port of memory modules under the parent module
+   * to the frame decoder inputs
+   */
+  ModulePortId parent_en_port = module_manager.find_module_port(parent_module, std::string(DECODER_ENABLE_PORT_NAME));
+  ModulePortId decoder_en_port = module_manager.find_module_port(decoder_module, std::string(DECODER_ENABLE_PORT_NAME));
+  add_module_bus_nets(module_manager, parent_module,
+                      parent_module, 0, parent_en_port,
+                      decoder_module, 0, decoder_en_port);
+
+  /* Connect the address port of the parent module to the frame decoder address port
+   * Note that we only connect to the first few bits of address port
+   */
+  ModulePortId parent_addr_port = module_manager.find_module_port(parent_module, std::string(DECODER_ADDRESS_PORT_NAME));
+  ModulePortId decoder_addr_port = module_manager.find_module_port(decoder_module, std::string(DECODER_ADDRESS_PORT_NAME));
+  BasicPort parent_addr_port_info = module_manager.module_port(parent_module, parent_addr_port);
+  BasicPort decoder_addr_port_info = module_manager.module_port(decoder_module, decoder_addr_port);
+  for (size_t ipin = 0; ipin < decoder_addr_port_info.get_width(); ++ipin) {
+    ModuleNetId net = module_manager.module_instance_port_net(parent_module,
+                                                              parent_module, 0, 
+                                                              parent_addr_port,
+                                                              parent_addr_port_info.get_msb() - ipin);
+    if (ModuleNetId::INVALID() == net) { 
+      net = module_manager.create_module_net(parent_module);
+      /* Configure the net source */
+      module_manager.add_module_net_source(parent_module, net,
+                                           parent_module, 0,
+                                           parent_addr_port,
+                                           parent_addr_port_info.get_msb() - ipin);
+    }
+    /* Configure the net sink */
+    module_manager.add_module_net_sink(parent_module, net,
+                                       decoder_module, 0,
+                                       decoder_addr_port,
+                                       decoder_addr_port_info.get_msb() - ipin);
+  } 
+
+  /* Connect the address port of the parent module to the address port of configurable children
+   * Note that we only connect to the last few bits of address port
+   */
+  for (size_t mem_index = 0; mem_index < module_manager.configurable_children(parent_module).size(); ++mem_index) {
+    ModuleId child_module = module_manager.configurable_children(parent_module)[mem_index]; 
+    ModulePortId child_addr_port = module_manager.find_module_port(child_module, std::string(DECODER_ADDRESS_PORT_NAME));
+    BasicPort child_addr_port_info = module_manager.module_port(child_module, child_addr_port);
+    for (size_t ipin = 0; ipin < child_addr_port_info.get_width(); ++ipin) {
+      ModuleNetId net = module_manager.module_instance_port_net(parent_module,
+                                                                parent_module, 0, 
+                                                                parent_addr_port,
+                                                                parent_addr_port_info.get_lsb() + ipin);
+      if (ModuleNetId::INVALID() == net) { 
+        net = module_manager.create_module_net(parent_module);
+        /* Configure the net source */
+        module_manager.add_module_net_source(parent_module, net,
+                                             parent_module, 0,
+                                             parent_addr_port,
+                                             parent_addr_port_info.get_lsb() + ipin);
+      }
+      /* Configure the net sink */
+      module_manager.add_module_net_sink(parent_module, net,
+                                         child_module, 0,
+                                         child_addr_port,
+                                         child_addr_port_info.get_lsb() + ipin);
+    }
+  }
+
+  /* Connect the data_in (Din) of parent module to the data_in of the all
+   * the memory modules
+   */
+  ModulePortId parent_din_port = module_manager.find_module_port(parent_module, std::string(DECODER_DATA_IN_PORT_NAME));
+  for (size_t mem_index = 0; mem_index < module_manager.configurable_children(parent_module).size(); ++mem_index) {
+    ModuleId child_module = module_manager.configurable_children(parent_module)[mem_index]; 
+    ModulePortId child_din_port = module_manager.find_module_port(child_module, std::string(DECODER_DATA_IN_PORT_NAME));
+    add_module_bus_nets(module_manager, parent_module,
+                        parent_module, 0, parent_din_port,
+                        child_module, 0, child_din_port);
+  }
+
+  /* Connect the data_out port of the decoder module 
+   * to the enable port of configurable children
+   */
+  ModulePortId decoder_dout_port = module_manager.find_module_port(decoder_module, std::string(DECODER_DATA_OUT_PORT_NAME));
+  BasicPort decoder_dout_port_info = module_manager.module_port(decoder_module, decoder_dout_port);
+  VTR_ASSERT(decoder_dout_port_info.get_width() == module_manager.configurable_children(parent_module).size());
+  for (size_t mem_index = 0; mem_index < module_manager.configurable_children(parent_module).size(); ++mem_index) {
+    ModuleId child_module = module_manager.configurable_children(parent_module)[mem_index]; 
+    ModulePortId child_en_port = module_manager.find_module_port(child_module, std::string(DECODER_ENABLE_PORT_NAME));
+    BasicPort child_en_port_info = module_manager.module_port(child_module, child_en_port);
+    for (size_t ipin = 0; ipin < child_en_port_info.get_width(); ++ipin) {
+      ModuleNetId net = module_manager.module_instance_port_net(parent_module,
+                                                                decoder_module, 0, 
+                                                                decoder_dout_port,
+                                                                decoder_dout_port_info.pins()[mem_index]);
+      if (ModuleNetId::INVALID() == net) { 
+        net = module_manager.create_module_net(parent_module);
+        /* Configure the net source */
+        module_manager.add_module_net_source(parent_module, net,
+                                             decoder_module, 0,
+                                             decoder_dout_port,
+                                             decoder_dout_port_info.pins()[mem_index]);
+      }
+      /* Configure the net sink */
+      module_manager.add_module_net_sink(parent_module, net,
+                                         child_module, 0,
+                                         child_en_port,
+                                         child_en_port_info.pins()[ipin]);
+    }
+  }
+
+  /* Add the decoder as the last configurable children */
+  module_manager.add_configurable_child(parent_module, decoder_module, 0);
+}
+
 /*********************************************************************
  * Add the port-to-port connection between all the memory modules 
  * and their parent module
@@ -796,6 +1003,7 @@ void add_module_nets_cmos_memory_chain_config_bus(ModuleManager& module_manager,
  **********************************************************************/
 static 
 void add_module_nets_cmos_memory_config_bus(ModuleManager& module_manager,
+                                            DecoderLibrary& decoder_lib,
                                             const ModuleId& parent_module,
                                             const e_config_protocol_type& sram_orgz_type) {
   switch (sram_orgz_type) {
@@ -809,6 +1017,10 @@ void add_module_nets_cmos_memory_config_bus(ModuleManager& module_manager,
   case CONFIG_MEM_MEMORY_BANK:
     /* TODO: */
     break;
+  case CONFIG_MEM_FRAME_BASED:
+    /* TODO: */
+    add_module_nets_cmos_memory_frame_config_bus(module_manager, decoder_lib, parent_module);
+    break;
   default:
     VTR_LOG_ERROR("Invalid type of SRAM organization!\n");
     exit(1);
@@ -871,12 +1083,14 @@ void add_module_nets_cmos_memory_config_bus(ModuleManager& module_manager,
  * and its child module (logic_module and memory_module) is created! 
  *******************************************************************/
 void add_module_nets_memory_config_bus(ModuleManager& module_manager,
+                                       DecoderLibrary& decoder_lib,
                                        const ModuleId& parent_module,
                                        const e_config_protocol_type& sram_orgz_type, 
                                        const e_circuit_model_design_tech& mem_tech) {
   switch (mem_tech) {
   case CIRCUIT_MODEL_DESIGN_CMOS:
-    add_module_nets_cmos_memory_config_bus(module_manager, parent_module, 
+    add_module_nets_cmos_memory_config_bus(module_manager, decoder_lib,
+                                           parent_module, 
                                            sram_orgz_type);
     break;
   case CIRCUIT_MODEL_DESIGN_RRAM:
@@ -1219,10 +1433,38 @@ size_t find_module_num_config_bits_from_child_modules(ModuleManager& module_mana
                                                       const e_config_protocol_type& sram_orgz_type) {
   size_t num_config_bits = 0;
 
-  /* Iterate over the child modules */
-  for (const ModuleId& child : module_manager.child_modules(module_id)) {
-    num_config_bits += find_module_num_config_bits(module_manager, child, circuit_lib, sram_model, sram_orgz_type);
-  } 
+  switch (sram_orgz_type) {
+  case CONFIG_MEM_STANDALONE: 
+  case CONFIG_MEM_SCAN_CHAIN: 
+  case CONFIG_MEM_MEMORY_BANK: {
+    /* For scan-chain, standalone and memory bank configuration protocol
+     * The number of configuration bits is the sum of configuration bits 
+     * per configurable children 
+     */
+    for (const ModuleId& child : module_manager.configurable_children(module_id)) {
+      num_config_bits += find_module_num_config_bits(module_manager, child, circuit_lib, sram_model, sram_orgz_type);
+    } 
+    break;
+  }
+  case CONFIG_MEM_FRAME_BASED: {
+    /* For frame-based configuration protocol
+     * The number of configuration bits is the sum of
+     * - the maximum of configuration bits among configurable children
+     * - and the number of configurable children
+     */
+    for (const ModuleId& child : module_manager.configurable_children(module_id)) {
+      size_t temp_num_config_bits = find_module_num_config_bits(module_manager, child, circuit_lib, sram_model, sram_orgz_type);
+      num_config_bits = std::max((int)temp_num_config_bits, (int)num_config_bits);
+    } 
+
+    num_config_bits += find_mux_local_decoder_addr_size(module_manager.configurable_children(module_id).size());
+
+    break;
+  }
+  default:
+    VTR_LOG_ERROR("Invalid type of SRAM organization !\n");
+    exit(1);
+  }
 
   return num_config_bits;
 }
@@ -1280,9 +1522,9 @@ void add_module_bus_nets(ModuleManager& module_manager,
                                                               src_module_port_id, src_port.pins()[pin_id]);
     if (ModuleNetId::INVALID() == net) { 
       net = module_manager.create_module_net(cur_module_id);
+      /* Configure the net source */
+      module_manager.add_module_net_source(cur_module_id, net, src_module_id, src_instance_id, src_module_port_id, src_port.pins()[pin_id]);
     }
-    /* Configure the net source */
-    module_manager.add_module_net_source(cur_module_id, net, src_module_id, src_instance_id, src_module_port_id, src_port.pins()[pin_id]);
     /* Configure the net sink */
     module_manager.add_module_net_sink(cur_module_id, net, des_module_id, des_instance_id, des_module_port_id, des_port.pins()[pin_id]);
   }
diff --git a/openfpga/src/utils/module_manager_utils.h b/openfpga/src/utils/module_manager_utils.h
index 0ecdfd282..d52727a40 100644
--- a/openfpga/src/utils/module_manager_utils.h
+++ b/openfpga/src/utils/module_manager_utils.h
@@ -20,6 +20,7 @@
 #include "circuit_types.h"
 #include "circuit_library.h"
 
+#include "decoder_library.h"
 #include "module_manager.h"
 #include "vpr_device_annotation.h"
 
@@ -94,7 +95,12 @@ void add_module_nets_cmos_memory_chain_config_bus(ModuleManager& module_manager,
                                                   const ModuleId& parent_module,
                                                   const e_config_protocol_type& sram_orgz_type);
 
+void add_module_nets_cmos_memory_frame_config_bus(ModuleManager& module_manager,
+                                                  DecoderLibrary& decoder_lib,
+                                                  const ModuleId& parent_module);
+
 void add_module_nets_memory_config_bus(ModuleManager& module_manager,
+                                       DecoderLibrary& decoder_lib,
                                        const ModuleId& parent_module,
                                        const e_config_protocol_type& sram_orgz_type, 
                                        const e_circuit_model_design_tech& mem_tech);

From ed2325ec9e696d1c0c84a6c0dcc3010b39d4f38c Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 26 May 2020 19:34:45 -0600
Subject: [PATCH 564/645] add frame decoder build-up to top-level module

---
 openfpga/src/fabric/build_device_module.cpp     | 4 +++-
 openfpga/src/fabric/build_top_module.cpp        | 4 +++-
 openfpga/src/fabric/build_top_module.h          | 2 ++
 openfpga/src/fabric/build_top_module_memory.cpp | 6 +++++-
 openfpga/src/fabric/build_top_module_memory.h   | 2 ++
 5 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/openfpga/src/fabric/build_device_module.cpp b/openfpga/src/fabric/build_device_module.cpp
index ee2547d7d..4b2375057 100644
--- a/openfpga/src/fabric/build_device_module.cpp
+++ b/openfpga/src/fabric/build_device_module.cpp
@@ -105,7 +105,9 @@ ModuleManager build_device_module_graph(IoLocationMap& io_location_map,
   }
 
   /* Build FPGA fabric top-level module */
-  build_top_module(module_manager, io_location_map,
+  build_top_module(module_manager,
+                   io_location_map,
+                   decoder_lib,
                    openfpga_ctx.arch().circuit_lib, 
                    vpr_device_ctx.grid,
                    vpr_device_ctx.rr_graph,
diff --git a/openfpga/src/fabric/build_top_module.cpp b/openfpga/src/fabric/build_top_module.cpp
index 6124333c0..072548807 100644
--- a/openfpga/src/fabric/build_top_module.cpp
+++ b/openfpga/src/fabric/build_top_module.cpp
@@ -311,6 +311,7 @@ vtr::Matrix<size_t> add_top_module_connection_block_instances(ModuleManager& mod
  *******************************************************************/
 void build_top_module(ModuleManager& module_manager,
                       IoLocationMap& io_location_map,
+                      DecoderLibrary& decoder_lib,
                       const CircuitLibrary& circuit_lib,
                       const DeviceGrid& grids,
                       const RRGraph& rr_graph,
@@ -390,7 +391,8 @@ void build_top_module(ModuleManager& module_manager,
    * This is a one-shot addition that covers all the memory modules in this pb module!
    */
   if (0 < module_manager.configurable_children(top_module).size()) {
-    add_top_module_nets_memory_config_bus(module_manager, top_module, 
+    add_top_module_nets_memory_config_bus(module_manager, decoder_lib,
+                                          top_module, 
                                           sram_orgz_type, circuit_lib.design_tech_type(sram_model));
   }
 }
diff --git a/openfpga/src/fabric/build_top_module.h b/openfpga/src/fabric/build_top_module.h
index 4ced0735b..d64de2755 100644
--- a/openfpga/src/fabric/build_top_module.h
+++ b/openfpga/src/fabric/build_top_module.h
@@ -11,6 +11,7 @@
 #include "rr_graph_obj.h"
 #include "device_rr_gsb.h"
 #include "circuit_library.h"
+#include "decoder_library.h"
 #include "tile_direct.h"
 #include "arch_direct.h"
 #include "module_manager.h"
@@ -25,6 +26,7 @@ namespace openfpga {
 
 void build_top_module(ModuleManager& module_manager,
                       IoLocationMap& io_location_map,
+                      DecoderLibrary& decoder_lib,
                       const CircuitLibrary& circuit_lib,
                       const DeviceGrid& grids,
                       const RRGraph& rr_graph,
diff --git a/openfpga/src/fabric/build_top_module_memory.cpp b/openfpga/src/fabric/build_top_module_memory.cpp
index 28c003957..c488599a9 100644
--- a/openfpga/src/fabric/build_top_module_memory.cpp
+++ b/openfpga/src/fabric/build_top_module_memory.cpp
@@ -408,6 +408,7 @@ void organize_top_module_memory_modules(ModuleManager& module_manager,
  **********************************************************************/
 static 
 void add_top_module_nets_cmos_memory_config_bus(ModuleManager& module_manager,
+                                                DecoderLibrary& decoder_lib,
                                                 const ModuleId& parent_module,
                                                 const e_config_protocol_type& sram_orgz_type) {
   switch (sram_orgz_type) {
@@ -423,6 +424,7 @@ void add_top_module_nets_cmos_memory_config_bus(ModuleManager& module_manager,
     break;
   case CONFIG_MEM_FRAME_BASED:
     /* TODO: */
+    add_module_nets_cmos_memory_frame_config_bus(module_manager, decoder_lib, parent_module);
     break;
   default:
     VTR_LOGF_ERROR(__FILE__, __LINE__,
@@ -464,12 +466,14 @@ void add_top_module_nets_cmos_memory_config_bus(ModuleManager& module_manager,
  * and its child module (logic_module and memory_module) is created! 
  *******************************************************************/
 void add_top_module_nets_memory_config_bus(ModuleManager& module_manager,
+                                           DecoderLibrary& decoder_lib,
                                            const ModuleId& parent_module,
                                            const e_config_protocol_type& sram_orgz_type, 
                                            const e_circuit_model_design_tech& mem_tech) {
   switch (mem_tech) {
   case CIRCUIT_MODEL_DESIGN_CMOS:
-    add_top_module_nets_cmos_memory_config_bus(module_manager, parent_module, 
+    add_top_module_nets_cmos_memory_config_bus(module_manager, decoder_lib,
+                                               parent_module, 
                                                sram_orgz_type);
     break;
   case CIRCUIT_MODEL_DESIGN_RRAM:
diff --git a/openfpga/src/fabric/build_top_module_memory.h b/openfpga/src/fabric/build_top_module_memory.h
index dfa9a5c78..1d0295b87 100644
--- a/openfpga/src/fabric/build_top_module_memory.h
+++ b/openfpga/src/fabric/build_top_module_memory.h
@@ -11,6 +11,7 @@
 #include "module_manager.h"
 #include "circuit_types.h"
 #include "circuit_library.h"
+#include "decoder_library.h"
 #include "device_grid.h"
 #include "device_rr_gsb.h"
 
@@ -34,6 +35,7 @@ void organize_top_module_memory_modules(ModuleManager& module_manager,
                                         const bool& compact_routing_hierarchy);
 
 void add_top_module_nets_memory_config_bus(ModuleManager& module_manager,
+                                           DecoderLibrary& decoder_lib,
                                            const ModuleId& parent_module,
                                            const e_config_protocol_type& sram_orgz_type, 
                                            const e_circuit_model_design_tech& mem_tech);

From c696e3d20f8fd063ba167ff8cbd855fd8287a868 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 26 May 2020 20:01:02 -0600
Subject: [PATCH 565/645] refine frame-based memory addition to compact the
 area

---
 .../src/fabric/build_top_module_memory.cpp    |   1 -
 openfpga/src/utils/module_manager_utils.cpp   | 100 ++++++++++++++++--
 2 files changed, 91 insertions(+), 10 deletions(-)

diff --git a/openfpga/src/fabric/build_top_module_memory.cpp b/openfpga/src/fabric/build_top_module_memory.cpp
index c488599a9..c15070488 100644
--- a/openfpga/src/fabric/build_top_module_memory.cpp
+++ b/openfpga/src/fabric/build_top_module_memory.cpp
@@ -423,7 +423,6 @@ void add_top_module_nets_cmos_memory_config_bus(ModuleManager& module_manager,
     /* TODO: */
     break;
   case CONFIG_MEM_FRAME_BASED:
-    /* TODO: */
     add_module_nets_cmos_memory_frame_config_bus(module_manager, decoder_lib, parent_module);
     break;
   default:
diff --git a/openfpga/src/utils/module_manager_utils.cpp b/openfpga/src/utils/module_manager_utils.cpp
index 2819cc0b4..27231aaf3 100644
--- a/openfpga/src/utils/module_manager_utils.cpp
+++ b/openfpga/src/utils/module_manager_utils.cpp
@@ -769,6 +769,58 @@ void add_module_nets_cmos_memory_chain_config_bus(ModuleManager& module_manager,
   }
 }
 
+/********************************************************************
+ * This function will create nets for the following types of connections:
+ *  - Connect the enable signal to the EN of memory module
+ *  - Connect the address port to the address port of memory module
+ *  - Connect the data_in (Din) to the data_in of the memory module
+ *
+ *       EN      ADDR      DATA_IN
+ *        |        |          |
+ *        v        v          v                              
+ *   +-----------------------------+
+ *   |        Memory Module        |
+ *   |           [0]               |
+ *   |                             |
+ *   +-----------------------------+
+ *
+ * Note:
+ *  - This function is ONLY applicable to single configurable child case!!!
+ *
+ *********************************************************************/
+static 
+void add_module_nets_cmos_memory_frame_short_config_bus(ModuleManager& module_manager,
+                                                        const ModuleId& parent_module) {
+  std::vector<ModuleId> configurable_children = module_manager.configurable_children(parent_module);
+
+  VTR_ASSERT(1 == configurable_children.size());
+  ModuleId child_module = configurable_children[0]; 
+
+  /* Connect the enable (EN) port of the parent module
+   * to the EN port of memory module
+   */
+  ModulePortId parent_en_port = module_manager.find_module_port(parent_module, std::string(DECODER_ENABLE_PORT_NAME));
+  ModulePortId child_en_port = module_manager.find_module_port(child_module, std::string(DECODER_ENABLE_PORT_NAME));
+  add_module_bus_nets(module_manager, parent_module,
+                      parent_module, 0, parent_en_port,
+                      child_module, 0, child_en_port);
+
+  /* Connect the address port of the parent module to the child module address port */
+  ModulePortId parent_addr_port = module_manager.find_module_port(parent_module, std::string(DECODER_ADDRESS_PORT_NAME));
+  ModulePortId child_addr_port = module_manager.find_module_port(child_module, std::string(DECODER_ADDRESS_PORT_NAME));
+  add_module_bus_nets(module_manager, parent_module,
+                      parent_module, 0, parent_addr_port,
+                      child_module, 0, child_addr_port);
+
+  /* Connect the data_in (Din) of parent module to the data_in of the memory module
+   */
+  ModulePortId parent_din_port = module_manager.find_module_port(parent_module, std::string(DECODER_DATA_IN_PORT_NAME));
+  ModulePortId child_din_port = module_manager.find_module_port(child_module, std::string(DECODER_DATA_IN_PORT_NAME));
+  add_module_bus_nets(module_manager, parent_module,
+                      parent_module, 0, parent_din_port,
+                      child_module, 0, child_din_port);
+}
+
 /********************************************************************
  * This function will 
  * - Add a frame decoder to the parent module 
@@ -811,11 +863,13 @@ void add_module_nets_cmos_memory_chain_config_bus(ModuleManager& module_manager,
  *  - X is the port size of address port of the parent module
  *  - the address port of child memory modules may be smaller than 
  *    X - log(N)/log2. In such case, we will drop the MSBs until it fit
+ *  - This function is only applicable to 2+ configurable children!!!
  *
  *********************************************************************/
-void add_module_nets_cmos_memory_frame_config_bus(ModuleManager& module_manager,
-                                                  DecoderLibrary& decoder_lib,
-                                                  const ModuleId& parent_module) {
+static 
+void add_module_nets_cmos_memory_frame_decoder_config_bus(ModuleManager& module_manager,
+                                                          DecoderLibrary& decoder_lib,
+                                                          const ModuleId& parent_module) {
   std::vector<ModuleId> configurable_children = module_manager.configurable_children(parent_module);
 
   /* Find the decoder specification */
@@ -885,7 +939,7 @@ void add_module_nets_cmos_memory_frame_config_bus(ModuleManager& module_manager,
   /* Connect the address port of the parent module to the address port of configurable children
    * Note that we only connect to the last few bits of address port
    */
-  for (size_t mem_index = 0; mem_index < module_manager.configurable_children(parent_module).size(); ++mem_index) {
+  for (size_t mem_index = 0; mem_index < configurable_children.size(); ++mem_index) {
     ModuleId child_module = module_manager.configurable_children(parent_module)[mem_index]; 
     ModulePortId child_addr_port = module_manager.find_module_port(child_module, std::string(DECODER_ADDRESS_PORT_NAME));
     BasicPort child_addr_port_info = module_manager.module_port(child_module, child_addr_port);
@@ -915,7 +969,7 @@ void add_module_nets_cmos_memory_frame_config_bus(ModuleManager& module_manager,
    */
   ModulePortId parent_din_port = module_manager.find_module_port(parent_module, std::string(DECODER_DATA_IN_PORT_NAME));
   for (size_t mem_index = 0; mem_index < module_manager.configurable_children(parent_module).size(); ++mem_index) {
-    ModuleId child_module = module_manager.configurable_children(parent_module)[mem_index]; 
+    ModuleId child_module = configurable_children[mem_index]; 
     ModulePortId child_din_port = module_manager.find_module_port(child_module, std::string(DECODER_DATA_IN_PORT_NAME));
     add_module_bus_nets(module_manager, parent_module,
                         parent_module, 0, parent_din_port,
@@ -927,9 +981,9 @@ void add_module_nets_cmos_memory_frame_config_bus(ModuleManager& module_manager,
    */
   ModulePortId decoder_dout_port = module_manager.find_module_port(decoder_module, std::string(DECODER_DATA_OUT_PORT_NAME));
   BasicPort decoder_dout_port_info = module_manager.module_port(decoder_module, decoder_dout_port);
-  VTR_ASSERT(decoder_dout_port_info.get_width() == module_manager.configurable_children(parent_module).size());
-  for (size_t mem_index = 0; mem_index < module_manager.configurable_children(parent_module).size(); ++mem_index) {
-    ModuleId child_module = module_manager.configurable_children(parent_module)[mem_index]; 
+  VTR_ASSERT(decoder_dout_port_info.get_width() == configurable_children.size());
+  for (size_t mem_index = 0; mem_index < configurable_children.size(); ++mem_index) {
+    ModuleId child_module = configurable_children[mem_index]; 
     ModulePortId child_en_port = module_manager.find_module_port(child_module, std::string(DECODER_ENABLE_PORT_NAME));
     BasicPort child_en_port_info = module_manager.module_port(child_module, child_en_port);
     for (size_t ipin = 0; ipin < child_en_port_info.get_width(); ++ipin) {
@@ -957,6 +1011,29 @@ void add_module_nets_cmos_memory_frame_config_bus(ModuleManager& module_manager,
   module_manager.add_configurable_child(parent_module, decoder_module, 0);
 }
 
+/*********************************************************************
+ * Top-level function to add nets for frame-based memories
+ * Add nets depending on the need
+ * - If there is no configurable child, return directly.
+ * - If there is only one configurable child, short wire the EN, ADDR and DATA_IN to it
+ * - If there are more than two configurable childern, add a decoder and build interconnection
+ *   between it and the children 
+ **********************************************************************/
+void add_module_nets_cmos_memory_frame_config_bus(ModuleManager& module_manager,
+                                                  DecoderLibrary& decoder_lib,
+                                                  const ModuleId& parent_module) {
+  if (0 == module_manager.configurable_children(parent_module).size()) {
+    return; 
+  }
+  
+  if (1 == module_manager.configurable_children(parent_module).size()) {
+    add_module_nets_cmos_memory_frame_short_config_bus(module_manager, parent_module);
+  } else {
+    VTR_ASSERT (1 < module_manager.configurable_children(parent_module).size());
+    add_module_nets_cmos_memory_frame_decoder_config_bus(module_manager, decoder_lib, parent_module);
+  }
+}
+
 /*********************************************************************
  * Add the port-to-port connection between all the memory modules 
  * and their parent module
@@ -1457,7 +1534,12 @@ size_t find_module_num_config_bits_from_child_modules(ModuleManager& module_mana
       num_config_bits = std::max((int)temp_num_config_bits, (int)num_config_bits);
     } 
 
-    num_config_bits += find_mux_local_decoder_addr_size(module_manager.configurable_children(module_id).size());
+    /* If there are more than 2 configurable children, we need a decoder
+     * Otherwise, we can just short wire the address port to the children
+     */
+    if (1 < module_manager.configurable_children(module_id).size()) {
+      num_config_bits += find_mux_local_decoder_addr_size(module_manager.configurable_children(module_id).size());
+    }
 
     break;
   }

From 5c5a044c68a9af946fe68e79e23335718d34e671 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 27 May 2020 14:25:06 -0600
Subject: [PATCH 566/645] add architecture decoder (for frame-based config
 memory) to Verilog writer

---
 openfpga/src/base/openfpga_verilog.cpp        |   1 +
 openfpga/src/fpga_verilog/verilog_api.cpp     |   3 +-
 openfpga/src/fpga_verilog/verilog_api.h       |   2 +
 openfpga/src/fpga_verilog/verilog_constants.h |   1 +
 .../src/fpga_verilog/verilog_decoders.cpp     | 178 +++++++++++++++++-
 openfpga/src/fpga_verilog/verilog_decoders.h  |   7 +
 .../src/fpga_verilog/verilog_submodule.cpp    |   7 +
 openfpga/src/fpga_verilog/verilog_submodule.h |   2 +
 8 files changed, 198 insertions(+), 3 deletions(-)

diff --git a/openfpga/src/base/openfpga_verilog.cpp b/openfpga/src/base/openfpga_verilog.cpp
index 481bd2866..c67c270eb 100644
--- a/openfpga/src/base/openfpga_verilog.cpp
+++ b/openfpga/src/base/openfpga_verilog.cpp
@@ -48,6 +48,7 @@ int write_fabric_verilog(OpenfpgaContext& openfpga_ctx,
                       openfpga_ctx.mutable_verilog_netlists(),
                       openfpga_ctx.arch().circuit_lib,
                       openfpga_ctx.mux_lib(),
+                      openfpga_ctx.decoder_lib(),
                       g_vpr_ctx.device(),
                       openfpga_ctx.vpr_device_annotation(),
                       openfpga_ctx.device_rr_gsb(),
diff --git a/openfpga/src/fpga_verilog/verilog_api.cpp b/openfpga/src/fpga_verilog/verilog_api.cpp
index 06ef0e58e..2f92156fb 100644
--- a/openfpga/src/fpga_verilog/verilog_api.cpp
+++ b/openfpga/src/fpga_verilog/verilog_api.cpp
@@ -54,6 +54,7 @@ void fpga_fabric_verilog(ModuleManager& module_manager,
                          NetlistManager& netlist_manager,
                          const CircuitLibrary& circuit_lib,
                          const MuxLibrary& mux_lib,
+                         const DecoderLibrary& decoder_lib,
                          const DeviceContext& device_ctx, 
                          const VprDeviceAnnotation& device_annotation, 
                          const DeviceRRGSB& device_rr_gsb,
@@ -90,7 +91,7 @@ void fpga_fabric_verilog(ModuleManager& module_manager,
    * Without the modules in the module manager, core logic generation is not possible!!!
    */
   print_verilog_submodule(module_manager, netlist_manager,
-                          mux_lib, circuit_lib,
+                          mux_lib, decoder_lib, circuit_lib,
                           submodule_dir_path, 
                           options);
 
diff --git a/openfpga/src/fpga_verilog/verilog_api.h b/openfpga/src/fpga_verilog/verilog_api.h
index 301e68b3e..3076beb47 100644
--- a/openfpga/src/fpga_verilog/verilog_api.h
+++ b/openfpga/src/fpga_verilog/verilog_api.h
@@ -8,6 +8,7 @@
 #include <string>
 #include <vector>
 #include "mux_library.h"
+#include "decoder_library.h"
 #include "circuit_library.h"
 #include "vpr_context.h"
 #include "vpr_device_annotation.h"
@@ -32,6 +33,7 @@ void fpga_fabric_verilog(ModuleManager& module_manager,
                          NetlistManager& netlist_manager,
                          const CircuitLibrary& circuit_lib,
                          const MuxLibrary& mux_lib,
+                         const DecoderLibrary& decoder_lib,
                          const DeviceContext& device_ctx, 
                          const VprDeviceAnnotation& device_annotation, 
                          const DeviceRRGSB& device_rr_gsb,
diff --git a/openfpga/src/fpga_verilog/verilog_constants.h b/openfpga/src/fpga_verilog/verilog_constants.h
index 4456a1048..3266fe2f6 100644
--- a/openfpga/src/fpga_verilog/verilog_constants.h
+++ b/openfpga/src/fpga_verilog/verilog_constants.h
@@ -37,6 +37,7 @@ constexpr char* LUTS_VERILOG_FILE_NAME = "luts.v";
 constexpr char* ROUTING_VERILOG_FILE_NAME = "routing.v";
 constexpr char* MUXES_VERILOG_FILE_NAME = "muxes.v";
 constexpr char* LOCAL_ENCODER_VERILOG_FILE_NAME = "local_encoder.v";
+constexpr char* ARCH_ENCODER_VERILOG_FILE_NAME = "arch_encoder.v";
 constexpr char* MEMORIES_VERILOG_FILE_NAME = "memories.v";
 constexpr char* WIRES_VERILOG_FILE_NAME = "wires.v";
 constexpr char* ESSENTIALS_VERILOG_FILE_NAME = "inv_buf_passgate.v";
diff --git a/openfpga/src/fpga_verilog/verilog_decoders.cpp b/openfpga/src/fpga_verilog/verilog_decoders.cpp
index 30789e36f..66a1a8ed8 100644
--- a/openfpga/src/fpga_verilog/verilog_decoders.cpp
+++ b/openfpga/src/fpga_verilog/verilog_decoders.cpp
@@ -1,7 +1,6 @@
 /***************************************************************************************
  * This file includes functions to generate Verilog modules of decoders
  ***************************************************************************************/
-/* TODO: merge verilog_decoder.c to this source file and rename to verilog_decoder.cpp */
 #include <string>
 
 /* Headers from vtrutil library */
@@ -15,6 +14,7 @@
 #include "decoder_library_utils.h"
 #include "module_manager.h"
 
+#include "openfpga_reserved_words.h"
 #include "openfpga_naming.h"
 
 #include "verilog_constants.h"
@@ -133,7 +133,6 @@ void print_verilog_mux_local_decoder_module(std::fstream& fp,
   print_verilog_module_end(fp, module_name);
 }
 
-
 /***************************************************************************************
  * This function will generate all the unique Verilog modules of local decoders for 
  * the multiplexers used in a FPGA fabric
@@ -227,4 +226,179 @@ void print_verilog_submodule_mux_local_decoders(const ModuleManager& module_mana
   VTR_LOG("Done\n");
 }
 
+/***************************************************************************************
+ * Create a Verilog module for a decoder used as a configuration protocol 
+ * in FPGA architecture
+ *
+ *                     Address
+ *                   | | ... | 
+ *                   v v     v
+ *                 +-----------+
+ *        Enable->/             \
+ *               /    Decoder    \
+ *              +-----------------+
+ *                | | | ... | | |
+ *                v v v     v v v
+ *                    Data output
+ *
+ *  The outputs are assumes to be one-hot codes (at most only one '1' exist)
+ *  Considering this fact, there are only num_of_outputs conditions to be encoded.
+ *  Therefore, the number of inputs is ceil(log(num_of_outputs)/log(2))
+ *
+ *  The decoder has an enable signal which is active at logic '1'. 
+ *  When activated, the decoder will output decoding results to the data output port
+ *  Otherwise, the data output port will be always all-zero
+ ***************************************************************************************/
+static 
+void print_verilog_arch_decoder_module(std::fstream& fp, 
+                                       const ModuleManager& module_manager,
+                                       const DecoderLibrary& decoder_lib,
+                                       const DecoderId& decoder) {
+  /* Get the number of inputs */
+  size_t addr_size = decoder_lib.addr_size(decoder);
+  size_t data_size = decoder_lib.data_size(decoder);
+
+  /* Validate the FILE handler */
+  VTR_ASSERT(true == valid_file_stream(fp));
+
+  /* Create a name for the decoder */
+  std::string module_name = generate_frame_memory_decoder_subckt_name(addr_size, data_size);
+
+  /* Create a Verilog Module based on the circuit model, and add to module manager */
+  ModuleId module_id = module_manager.find_module(module_name); 
+  VTR_ASSERT(true == module_manager.valid_module_id(module_id));
+  /* Find module ports */
+  /* Enable port */
+  ModulePortId enable_port_id = module_manager.find_module_port(module_id, std::string(DECODER_ENABLE_PORT_NAME));
+  BasicPort enable_port = module_manager.module_port(module_id, enable_port_id);
+  /* Address port */
+  ModulePortId addr_port_id = module_manager.find_module_port(module_id, std::string(DECODER_ADDRESS_PORT_NAME));
+  BasicPort addr_port = module_manager.module_port(module_id, addr_port_id);
+  /* Find each output port */
+  ModulePortId data_port_id = module_manager.find_module_port(module_id, std::string(DECODER_DATA_OUT_PORT_NAME));
+  BasicPort data_port = module_manager.module_port(module_id, data_port_id);
+  /* Data port is registered. It should be outputted as 
+   *   output reg [lsb:msb] data 
+   */
+  BasicPort data_inv_port(std::string(DECODER_DATA_OUT_INV_PORT_NAME), data_size);
+  if (true == decoder_lib.use_data_inv_port(decoder)) {
+    ModulePortId data_inv_port_id = module_manager.find_module_port(module_id, std::string(DECODER_DATA_OUT_INV_PORT_NAME));
+    data_inv_port = module_manager.module_port(module_id, data_inv_port_id);
+  }
+
+  /* dump module definition + ports */
+  print_verilog_module_declaration(fp, module_manager, module_id);
+  /* Finish dumping ports */
+
+  print_verilog_comment(fp, std::string("----- BEGIN Verilog codes for Decoder convert " + std::to_string(addr_size) + "-bit addr to " + std::to_string(data_size) + "-bit data -----"));
+
+  /* Print the truth table of this decoder */
+  /* Internal logics */
+  /* Early exit: Corner case for data size = 1 the logic is very simple:
+   * data = addr;  
+   * data_inv = ~data_inv
+   */
+  if (1 == data_size) {
+    print_verilog_wire_connection(fp, data_port, addr_port, false);
+
+    /* Depend on if the inverted data output port is needed or not */
+    if (true == decoder_lib.use_data_inv_port(decoder)) {
+      print_verilog_wire_connection(fp, data_inv_port, addr_port, true);
+    }
+
+    print_verilog_comment(fp, std::string("----- END Verilog codes for Decoder convert " + std::to_string(addr_size) + "-bit addr to " + std::to_string(data_size) + "-bit data -----"));
+
+    /* Put an end to the Verilog module */
+    print_verilog_module_end(fp, module_name);
+    return;
+  }
+
+  /* We use a magic number -1 as the addr=1 should be mapped to ...1
+   * Otherwise addr will map addr=1 to ..10 
+   * Note that there should be a range for the shift operators
+   * We should narrow the encoding to be applied to a given set of data
+   * This will lead to that any addr which falls out of the op code of data
+   * will give a all-zero code
+   * For example: 
+   * data is 5-bit while addr is 3-bit 
+   * data=8'b0_0000 will be encoded to addr=3'b001;
+   * data=8'b0_0001 will be encoded to addr=3'b010;
+   * data=8'b0_0010 will be encoded to addr=3'b011;
+   * data=8'b0_0100 will be encoded to addr=3'b100;
+   * data=8'b0_1000 will be encoded to addr=3'b101;
+   * data=8'b1_0000 will be encoded to addr=3'b110;
+   * The rest of addr codes 3'b110, 3'b111 will be decoded to data=8'b0_0000;
+   */
+
+  fp << "\t" << "always@(" << generate_verilog_port(VERILOG_PORT_CONKT, addr_port) << ")" << std::endl;
+  fp << "\tif (" << generate_verilog_port(VERILOG_PORT_CONKT, enable_port) << "1'b1) begin" << std::endl;
+  fp << "\t\t" << "case (" << generate_verilog_port(VERILOG_PORT_CONKT, addr_port) << ")" << std::endl;
+  /* Create a string for addr and data */
+  for (size_t i = 0; i < data_size; ++i) {
+    fp << "\t\t\t" << generate_verilog_constant_values(itobin_vec(i, addr_size)); 
+    fp << " : ";
+    fp << generate_verilog_port_constant_values(data_port, ito1hot_vec(i, data_size)); 
+    fp << ";" << std::endl;
+  }
+  fp << "\t\t\t" << "default : ";
+  fp << generate_verilog_port_constant_values(data_port, ito1hot_vec(data_size - 1, data_size)); 
+  fp << ";" << std::endl;
+  fp << "\t\t" << "endcase" << std::endl;
+  fp << "\t" << "end" << std::endl;
+
+  if (true == decoder_lib.use_data_inv_port(decoder)) {
+    print_verilog_wire_connection(fp, data_inv_port, data_port, true);
+  }
+  
+  print_verilog_comment(fp, std::string("----- END Verilog codes for Decoder convert " + std::to_string(addr_size) + "-bit addr to " + std::to_string(data_size) + "-bit data -----"));
+
+  /* Put an end to the Verilog module */
+  print_verilog_module_end(fp, module_name);
+}
+
+/***************************************************************************************
+ * This function will generate all the unique Verilog modules of decoders for 
+ * configuration protocols in a FPGA fabric
+ * It will generate these decoder Verilog modules using behavioral description.
+ * Note that the implementation of local decoders can be dependent on the technology
+ * and standard cell libraries.
+ * Therefore, behavioral Verilog is used and the local decoders should be synthesized 
+ * before running the back-end flow for FPGA fabric 
+ * See more details in the function print_verilog_arch_decoder() for more details
+ ***************************************************************************************/
+void print_verilog_submodule_arch_decoders(const ModuleManager& module_manager,
+                                           NetlistManager& netlist_manager,
+                                           const DecoderLibrary& decoder_lib,
+                                           const std::string& submodule_dir) {
+  std::string verilog_fname(submodule_dir + std::string(ARCH_ENCODER_VERILOG_FILE_NAME));
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
+
+  check_file_stream(verilog_fname.c_str(), fp);
+
+  /* Print out debugging information for if the file is not opened/created properly */
+  VTR_LOG("Writing Verilog netlist for configuration decoders '%s'...",
+          verilog_fname.c_str()); 
+
+  print_verilog_file_header(fp, "Decoders for fabric configuration protocol "); 
+
+  /* Generate Verilog modules for the found unique local encoders */
+  for (const auto& decoder : decoder_lib.decoders()) {
+    print_verilog_arch_decoder_module(fp, module_manager, decoder_lib, decoder);
+  }
+
+  /* Close the file stream */
+  fp.close();
+
+  /* Add fname to the netlist name list */
+  NetlistId nlist_id = netlist_manager.add_netlist(verilog_fname);
+  VTR_ASSERT(NetlistId::INVALID() != nlist_id);
+  netlist_manager.set_netlist_type(nlist_id, NetlistManager::SUBMODULE_NETLIST);
+
+  VTR_LOG("Done\n");
+}
+
+
 } /* end namespace openfpga */
diff --git a/openfpga/src/fpga_verilog/verilog_decoders.h b/openfpga/src/fpga_verilog/verilog_decoders.h
index 9b2bbb6b1..e15d5299a 100644
--- a/openfpga/src/fpga_verilog/verilog_decoders.h
+++ b/openfpga/src/fpga_verilog/verilog_decoders.h
@@ -11,6 +11,7 @@
 #include "circuit_library.h"
 #include "mux_graph.h"
 #include "mux_library.h"
+#include "decoder_library.h"
 #include "module_manager.h"
 #include "netlist_manager.h"
 
@@ -27,6 +28,12 @@ void print_verilog_submodule_mux_local_decoders(const ModuleManager& module_mana
                                                 const CircuitLibrary& circuit_lib,
                                                 const std::string& submodule_dir);
 
+void print_verilog_submodule_arch_decoders(const ModuleManager& module_manager,
+                                           NetlistManager& netlist_manager,
+                                           const DecoderLibrary& decoder_lib,
+                                           const std::string& submodule_dir);
+
+
 } /* end namespace openfpga */
 
 #endif
diff --git a/openfpga/src/fpga_verilog/verilog_submodule.cpp b/openfpga/src/fpga_verilog/verilog_submodule.cpp
index 37df77c60..6756824ab 100644
--- a/openfpga/src/fpga_verilog/verilog_submodule.cpp
+++ b/openfpga/src/fpga_verilog/verilog_submodule.cpp
@@ -34,6 +34,7 @@ namespace openfpga {
 void print_verilog_submodule(ModuleManager& module_manager, 
                              NetlistManager& netlist_manager,
                              const MuxLibrary& mux_lib,
+                             const DecoderLibrary& decoder_lib,
                              const CircuitLibrary& circuit_lib, 
                              const std::string& submodule_dir, 
                              const FabricVerilogOption& fpga_verilog_opts) {
@@ -49,6 +50,12 @@ void print_verilog_submodule(ModuleManager& module_manager,
                                      submodule_dir,
                                      circuit_lib);
 
+  /* Decoders for architecture */
+  print_verilog_submodule_arch_decoders(const_cast<const ModuleManager&>(module_manager),
+                                        netlist_manager, 
+                                        decoder_lib, 
+                                        submodule_dir);
+
   /* Routing multiplexers */
   /* NOTE: local decoders generation must go before the MUX generation!!! 
    *       because local decoders modules will be instanciated in the MUX modules 
diff --git a/openfpga/src/fpga_verilog/verilog_submodule.h b/openfpga/src/fpga_verilog/verilog_submodule.h
index 06bb7aeef..27bf7fdba 100644
--- a/openfpga/src/fpga_verilog/verilog_submodule.h
+++ b/openfpga/src/fpga_verilog/verilog_submodule.h
@@ -7,6 +7,7 @@
 #include "module_manager.h"
 #include "netlist_manager.h"
 #include "mux_library.h"
+#include "decoder_library.h"
 #include "fabric_verilog_options.h"
 
 /********************************************************************
@@ -19,6 +20,7 @@ namespace openfpga {
 void print_verilog_submodule(ModuleManager& module_manager, 
                              NetlistManager& netlist_manager,
                              const MuxLibrary& mux_lib,
+                             const DecoderLibrary& decoder_lib,
                              const CircuitLibrary& circuit_lib, 
                              const std::string& submodule_dir, 
                              const FabricVerilogOption& fpga_verilog_opts);

From 8c14cced84deddb8b8d522bd2ec5af6716d5cac3 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 27 May 2020 15:09:18 -0600
Subject: [PATCH 567/645] start improve fabric bitstream database to support
 frame-based configuration protocol

---
 .../src/fpga_bitstream/fabric_bitstream.cpp   | 77 ++++++++++++++++
 .../src/fpga_bitstream/fabric_bitstream.h     | 90 +++++++++++++++++++
 .../src/fpga_bitstream/fabric_bitstream_fwd.h | 23 +++++
 3 files changed, 190 insertions(+)
 create mode 100644 openfpga/src/fpga_bitstream/fabric_bitstream.cpp
 create mode 100644 openfpga/src/fpga_bitstream/fabric_bitstream.h
 create mode 100644 openfpga/src/fpga_bitstream/fabric_bitstream_fwd.h

diff --git a/openfpga/src/fpga_bitstream/fabric_bitstream.cpp b/openfpga/src/fpga_bitstream/fabric_bitstream.cpp
new file mode 100644
index 000000000..581a466d5
--- /dev/null
+++ b/openfpga/src/fpga_bitstream/fabric_bitstream.cpp
@@ -0,0 +1,77 @@
+/******************************************************************************
+ * This file includes member functions for data structure FabricBitstream
+ ******************************************************************************/
+#include <algorithm>
+
+#include "vtr_assert.h"
+#include "fabric_bitstream.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/**************************************************
+ * Public Accessors : Aggregates
+ *************************************************/
+/* Find all the configuration bits */
+FabricBitstream::fabric_bit_range FabricBitstream::bits() const {
+  return vtr::make_range(bit_ids_.begin(), bit_ids_.end());
+}
+
+/******************************************************************************
+ * Public Accessors
+ ******************************************************************************/
+ConfigBitId FabricBitstream::config_bit(const FabricBitId& bit_id) const {
+  /* Ensure a valid id */
+  VTR_ASSERT(true == valid_bit_id(bit_id));
+
+  return config_bit_ids_[bit_id];
+}
+
+std::vector<bool> FabricBitstream::bit_address(const FabricBitId& bit_id) const {
+  /* Ensure a valid id */
+  VTR_ASSERT(true == valid_bit_id(bit_id));
+
+  return bit_addresses_[bit_id];
+}
+
+bool FabricBitstream::bit_din(const FabricBitId& bit_id) const {
+  /* Ensure a valid id */
+  VTR_ASSERT(true == valid_bit_id(bit_id));
+
+  return bit_dins_[bit_id];
+}
+
+/******************************************************************************
+ * Public Mutators
+ ******************************************************************************/
+FabricBitId FabricBitstream::add_bit(const ConfigBitId& config_bit_id) {
+  FabricBitId bit = FabricBitId(bit_ids_.size());
+  /* Add a new bit, and allocate associated data structures */
+  bit_ids_.push_back(bit);
+  config_bit_ids_.push_back(config_bit_id);
+  bit_addresses_.emplace_back();
+  bit_dins_.push_back(false);
+
+  return bit; 
+}
+
+void FabricBitstream::set_bit_address(const FabricBitId& bit_id,
+                                             const std::vector<bool>& address) {
+  VTR_ASSERT(true == valid_bit_id(bit_id));
+  bit_addresses_[bit_id] = address;
+}
+
+void FabricBitstream::set_bit_din(const FabricBitId& bit_id,
+                                         const bool& din) {
+  VTR_ASSERT(true == valid_bit_id(bit_id));
+  bit_dins_[bit_id] = din;
+}
+
+/******************************************************************************
+ * Public Validators
+ ******************************************************************************/
+bool FabricBitstream::valid_bit_id(const FabricBitId& bit_id) const {
+  return (size_t(bit_id) < bit_ids_.size()) && (bit_id == bit_ids_[bit_id]);
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_bitstream/fabric_bitstream.h b/openfpga/src/fpga_bitstream/fabric_bitstream.h
new file mode 100644
index 000000000..3f13406c4
--- /dev/null
+++ b/openfpga/src/fpga_bitstream/fabric_bitstream.h
@@ -0,0 +1,90 @@
+/******************************************************************************
+ * This file introduces a data structure to store fabric-dependent bitstream information 
+ *
+ * General concept
+ * ---------------
+ * The idea is to create a unified data structure that stores the sequence of configuration 
+ * bit in the architecture bitstream database
+ * as well as the information (such as address of each bit) required by a specific 
+ * configuration protocol
+ *
+ * Cross-reference 
+ * ---------------
+ * By using the link between ArchBitstreamManager and FabricBitstream, 
+ * we can build a sequence of configuration bits to fit different configuration protocols.
+ *
+ *     +----------------------+                 +--------------------------+
+ *     |                      |   ConfigBitId   |                          |
+ *     | ArchBitstreamManager |---------------->|  FabricBitstream  |
+ *     |                      |                 |                          |   
+ *     +----------------------+                 +--------------------------+ 
+ *
+ * Restrictions:
+ * 1. Each block inside BitstreamManager should have only 1 parent block 
+ *    and multiple child block
+ * 2. Each bit inside BitstreamManager should have only 1 parent block 
+ * 
+ ******************************************************************************/
+#ifndef FABRIC_BITSTREAM_H
+#define FABRIC_BITSTREAM_H
+
+#include <vector>
+#include "vtr_vector.h"
+
+#include "bitstream_manager_fwd.h"
+#include "fabric_bitstream_fwd.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+class FabricBitstream {
+  public: /* Types and ranges */
+    typedef vtr::vector<FabricBitId, FabricBitId>::const_iterator fabric_bit_iterator;
+
+    typedef vtr::Range<fabric_bit_iterator> fabric_bit_range;
+
+  public: /* Public aggregators */
+    /* Find all the configuration bits */
+    fabric_bit_range bits() const;
+
+  public:  /* Public Accessors */
+    /* Find the configuration bit id in architecture bitstream database */
+    ConfigBitId config_bit(const FabricBitId& bit_id) const;
+
+    /* Find the address of bitstream */
+    std::vector<bool> bit_address(const FabricBitId& bit_id) const;
+
+    /* Find the data-in of bitstream */
+    bool bit_din(const FabricBitId& bit_id) const;
+
+  public:  /* Public Mutators */
+    /* Add a new configuration bit to the bitstream manager */
+    FabricBitId add_bit(const ConfigBitId& config_bit_id);
+
+    void set_bit_address(const FabricBitId& bit_id,
+                         const std::vector<bool>& address);
+
+    void set_bit_din(const FabricBitId& bit_id,
+                     const bool& din);
+
+  public:  /* Public Validators */
+    bool valid_bit_id(const FabricBitId& bit_id) const;
+
+  private: /* Internal data */
+    /* Unique id of a bit in the Bitstream */
+    vtr::vector<FabricBitId, FabricBitId> bit_ids_; 
+    vtr::vector<FabricBitId, ConfigBitId> config_bit_ids_; 
+
+    /* Address bits: this is designed for memory decoders
+     * Here we store the binary format of the address, which can be loaded
+     * to the configuration protocol directly 
+     */
+    vtr::vector<FabricBitId, std::vector<bool>> bit_addresses_;
+
+    /* Data input (Din) bits: this is designed for memory decoders */
+    vtr::vector<FabricBitId, bool> bit_dins_;
+};
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/fpga_bitstream/fabric_bitstream_fwd.h b/openfpga/src/fpga_bitstream/fabric_bitstream_fwd.h
new file mode 100644
index 000000000..d93eec638
--- /dev/null
+++ b/openfpga/src/fpga_bitstream/fabric_bitstream_fwd.h
@@ -0,0 +1,23 @@
+/**************************************************
+ * This file includes only declarations for 
+ * the data structures for fabric-dependent bitstream database
+ * Please refer to fabric_bitstream.h for more details
+ *************************************************/
+#ifndef FABRIC_BITSTREAM_FWD_H
+#define FABRIC_BITSTREAM_FWD_H
+
+#include "vtr_strong_id.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/* Strong Ids for BitstreamContext */
+struct fabric_bit_id_tag;
+
+typedef vtr::StrongId<fabric_bit_id_tag> FabricBitId;
+
+class FabricBitstream;
+
+} /* end namespace openfpga */
+
+#endif 

From 4a0e1cd90890faa3e0c71b03e85f98fa4b752958 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 27 May 2020 15:53:40 -0600
Subject: [PATCH 568/645] add fabric bitstream data structure and deploy it to
 Verilog testbench generation

---
 openfpga/src/base/openfpga_bitstream.cpp      |   1 +
 openfpga/src/base/openfpga_context.h          |   7 +-
 .../fpga_bitstream/build_fabric_bitstream.cpp | 127 ++++++++++++------
 .../fpga_bitstream/build_fabric_bitstream.h   |   9 +-
 .../src/fpga_bitstream/fabric_bitstream.cpp   |  10 +-
 .../src/fpga_bitstream/fabric_bitstream.h     |   5 +
 .../fabric_bitstream_writer.cpp               |   8 +-
 .../fpga_bitstream/fabric_bitstream_writer.h  |   3 +-
 openfpga/src/fpga_verilog/verilog_api.cpp     |   2 +-
 openfpga/src/fpga_verilog/verilog_api.h       |   3 +-
 .../fpga_verilog/verilog_top_testbench.cpp    |  14 +-
 .../src/fpga_verilog/verilog_top_testbench.h  |   3 +-
 12 files changed, 125 insertions(+), 67 deletions(-)

diff --git a/openfpga/src/base/openfpga_bitstream.cpp b/openfpga/src/base/openfpga_bitstream.cpp
index e131a2bfc..b1af639b5 100644
--- a/openfpga/src/base/openfpga_bitstream.cpp
+++ b/openfpga/src/base/openfpga_bitstream.cpp
@@ -62,6 +62,7 @@ int build_fabric_bitstream(OpenfpgaContext& openfpga_ctx,
   /* Build fabric bitstream here */
   openfpga_ctx.mutable_fabric_bitstream() = build_fabric_dependent_bitstream(openfpga_ctx.bitstream_manager(),
                                                                              openfpga_ctx.module_graph(),
+                                                                             openfpga_ctx.arch().config_protocol,
                                                                              cmd_context.option_enable(cmd, opt_verbose));
 
   /* Write fabric bitstream if required */
diff --git a/openfpga/src/base/openfpga_context.h b/openfpga/src/base/openfpga_context.h
index 8c025687f..0eb34c029 100644
--- a/openfpga/src/base/openfpga_context.h
+++ b/openfpga/src/base/openfpga_context.h
@@ -16,6 +16,7 @@
 #include "netlist_manager.h"
 #include "openfpga_flow_manager.h"
 #include "bitstream_manager.h"
+#include "fabric_bitstream.h"
 #include "device_rr_gsb.h"
 #include "io_location_map.h"
 
@@ -61,7 +62,7 @@ class OpenfpgaContext : public Context  {
     const openfpga::ModuleManager& module_graph() const { return module_graph_; }
     const openfpga::FlowManager& flow_manager() const { return flow_manager_; }
     const openfpga::BitstreamManager& bitstream_manager() const { return bitstream_manager_; }
-    const std::vector<openfpga::ConfigBitId>& fabric_bitstream() const { return fabric_bitstream_; }
+    const openfpga::FabricBitstream& fabric_bitstream() const { return fabric_bitstream_; }
     const openfpga::IoLocationMap& io_location_map() const { return io_location_map_; }
     const std::unordered_map<AtomNetId, t_net_power>& net_activity() const { return net_activity_; }
     const openfpga::NetlistManager& verilog_netlists() const { return verilog_netlists_; }
@@ -79,7 +80,7 @@ class OpenfpgaContext : public Context  {
     openfpga::ModuleManager& mutable_module_graph() { return module_graph_; }
     openfpga::FlowManager& mutable_flow_manager() { return flow_manager_; }
     openfpga::BitstreamManager& mutable_bitstream_manager() { return bitstream_manager_; }
-    std::vector<openfpga::ConfigBitId>& mutable_fabric_bitstream() { return fabric_bitstream_; }
+    openfpga::FabricBitstream& mutable_fabric_bitstream() { return fabric_bitstream_; }
     openfpga::IoLocationMap& mutable_io_location_map() { return io_location_map_; }
     std::unordered_map<AtomNetId, t_net_power>& mutable_net_activity() { return net_activity_; }
     openfpga::NetlistManager& mutable_verilog_netlists() { return verilog_netlists_; }
@@ -120,7 +121,7 @@ class OpenfpgaContext : public Context  {
 
     /* Bitstream database */
     openfpga::BitstreamManager bitstream_manager_;
-    std::vector<openfpga::ConfigBitId> fabric_bitstream_;
+    openfpga::FabricBitstream fabric_bitstream_;
 
     /* Netlist database 
      * TODO: Each format should have an independent entry
diff --git a/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp b/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp
index 0a15f6930..3953e0c16 100644
--- a/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp
+++ b/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp
@@ -28,11 +28,11 @@ namespace openfpga {
  * in the configurable_children) and configurable_child_instances() of each module of module manager 
  *******************************************************************/
 static 
-void rec_build_module_fabric_dependent_bitstream(const BitstreamManager& bitstream_manager,
-                                                 const ConfigBlockId& parent_block,
-                                                 const ModuleManager& module_manager,
-                                                 const ModuleId& parent_module,
-                                                 std::vector<ConfigBitId>& fabric_bitstream) {
+void rec_build_module_fabric_dependent_chain_bitstream(const BitstreamManager& bitstream_manager,
+                                                       const ConfigBlockId& parent_block,
+                                                       const ModuleManager& module_manager,
+                                                       const ModuleId& parent_module,
+                                                       FabricBitstream& fabric_bitstream) {
 
   /* Depth-first search: if we have any children in the parent_block, 
    * we dive to the next level first! 
@@ -51,9 +51,9 @@ void rec_build_module_fabric_dependent_bitstream(const BitstreamManager& bitstre
       VTR_ASSERT(true == bitstream_manager.valid_block_id(child_block));
 
       /* Go recursively */
-      rec_build_module_fabric_dependent_bitstream(bitstream_manager, child_block,
-                                                  module_manager, child_module,
-                                                  fabric_bitstream);
+      rec_build_module_fabric_dependent_chain_bitstream(bitstream_manager, child_block,
+                                                        module_manager, child_module,
+                                                        fabric_bitstream);
     }
     /* Ensure that there should be no configuration bits in the parent block */
     VTR_ASSERT(0 == bitstream_manager.block_bits(parent_block).size());
@@ -64,45 +64,47 @@ void rec_build_module_fabric_dependent_bitstream(const BitstreamManager& bitstre
    * And then, we can return
    */
   for (const ConfigBitId& config_bit : bitstream_manager.block_bits(parent_block)) {
-    fabric_bitstream.push_back(config_bit);
+    fabric_bitstream.add_bit(config_bit);
   }
 }
 
 /********************************************************************
- * A top-level function re-organizes the bitstream for a specific 
- * FPGA fabric, where configuration bits are organized in the sequence
- * that can be directly loaded to the FPGA configuration protocol.
- * Support:
- * 1. Configuration chain
- * 2. Memory decoders
- * This function does NOT modify the bitstream database
- * Instead, it builds a vector of ids for configuration bits in bitstream manager
- *
- * This function can be called ONLY after the function build_device_bitstream() 
- * Note that this function does NOT decode bitstreams from circuit implementation
- * It was done in the function build_device_bitstream() 
+ * Main function to build a fabric-dependent bitstream
+ * by considering the configuration protocol types 
  *******************************************************************/
-std::vector<ConfigBitId> build_fabric_dependent_bitstream(const BitstreamManager& bitstream_manager,
-                                                          const ModuleManager& module_manager,
-                                                          const bool& verbose) {
-  std::vector<ConfigBitId> fabric_bitstream; 
+static 
+void build_module_fabric_dependent_bitstream(const ConfigProtocol& config_protocol,
+                                             const BitstreamManager& bitstream_manager,
+                                             const ConfigBlockId& top_block,
+                                             const ModuleManager& module_manager,
+                                             const ModuleId& top_module,
+                                             FabricBitstream& fabric_bitstream) {
 
-  vtr::ScopedStartFinishTimer timer("\nBuild fabric dependent bitstream\n");
-
-  /* Get the top module name in module manager, which is our starting point */
-  std::string top_module_name = generate_fpga_top_module_name();
-  ModuleId top_module = module_manager.find_module(top_module_name);
-  VTR_ASSERT(true == module_manager.valid_module_id(top_module));
-
-  /* Find the top block in bitstream manager, which has not parents */
-  std::vector<ConfigBlockId> top_block = find_bitstream_manager_top_blocks(bitstream_manager);
-  /* Make sure we have only 1 top block and its name matches the top module */
-  VTR_ASSERT(1 == top_block.size());
-  VTR_ASSERT(0 == top_module_name.compare(bitstream_manager.block_name(top_block[0])));
-
-  rec_build_module_fabric_dependent_bitstream(bitstream_manager, top_block[0],
-                                              module_manager, top_module, 
-                                              fabric_bitstream);
+  switch (config_protocol.type()) {
+  case CONFIG_MEM_STANDALONE: {
+    rec_build_module_fabric_dependent_chain_bitstream(bitstream_manager, top_block,
+                                                      module_manager, top_module, 
+                                                      fabric_bitstream);
+    break;
+  }
+  case CONFIG_MEM_SCAN_CHAIN: { 
+    rec_build_module_fabric_dependent_chain_bitstream(bitstream_manager, top_block,
+                                                      module_manager, top_module, 
+                                                      fabric_bitstream);
+    fabric_bitstream.reverse();
+    break;
+  }
+  case CONFIG_MEM_MEMORY_BANK: { 
+    break;
+  }
+  case CONFIG_MEM_FRAME_BASED: {
+    break;
+  }
+  default:
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid SRAM organization.\n");
+    exit(1);
+  }
 
   /* Time-consuming sanity check: Uncomment these codes only for debugging!!!
    * Check which configuration bits are not touched 
@@ -124,11 +126,50 @@ std::vector<ConfigBitId> build_fabric_dependent_bitstream(const BitstreamManager
    */
 
   /* Ensure our fabric bitstream is in the same size as device bistream */
-  VTR_ASSERT(bitstream_manager.bits().size() == fabric_bitstream.size());
+  VTR_ASSERT(bitstream_manager.bits().size() == fabric_bitstream.bits().size());
+}
+
+/********************************************************************
+ * A top-level function re-organizes the bitstream for a specific 
+ * FPGA fabric, where configuration bits are organized in the sequence
+ * that can be directly loaded to the FPGA configuration protocol.
+ * Support:
+ * 1. Configuration chain
+ * 2. Memory decoders
+ * This function does NOT modify the bitstream database
+ * Instead, it builds a vector of ids for configuration bits in bitstream manager
+ *
+ * This function can be called ONLY after the function build_device_bitstream() 
+ * Note that this function does NOT decode bitstreams from circuit implementation
+ * It was done in the function build_device_bitstream() 
+ *******************************************************************/
+FabricBitstream build_fabric_dependent_bitstream(const BitstreamManager& bitstream_manager,
+                                                 const ModuleManager& module_manager,
+                                                 const ConfigProtocol& config_protocol,
+                                                 const bool& verbose) {
+  FabricBitstream fabric_bitstream; 
+
+  vtr::ScopedStartFinishTimer timer("\nBuild fabric dependent bitstream\n");
+
+  /* Get the top module name in module manager, which is our starting point */
+  std::string top_module_name = generate_fpga_top_module_name();
+  ModuleId top_module = module_manager.find_module(top_module_name);
+  VTR_ASSERT(true == module_manager.valid_module_id(top_module));
+
+  /* Find the top block in bitstream manager, which has not parents */
+  std::vector<ConfigBlockId> top_block = find_bitstream_manager_top_blocks(bitstream_manager);
+  /* Make sure we have only 1 top block and its name matches the top module */
+  VTR_ASSERT(1 == top_block.size());
+  VTR_ASSERT(0 == top_module_name.compare(bitstream_manager.block_name(top_block[0])));
+
+  build_module_fabric_dependent_bitstream(config_protocol,
+                                          bitstream_manager, top_block[0],
+                                          module_manager, top_module, 
+                                          fabric_bitstream);
 
   VTR_LOGV(verbose,
            "Built %lu configuration bits for fabric\n",
-           fabric_bitstream.size());
+           fabric_bitstream.bits().size());
 
   return fabric_bitstream;
 }
diff --git a/openfpga/src/fpga_bitstream/build_fabric_bitstream.h b/openfpga/src/fpga_bitstream/build_fabric_bitstream.h
index 507454059..3daadde75 100644
--- a/openfpga/src/fpga_bitstream/build_fabric_bitstream.h
+++ b/openfpga/src/fpga_bitstream/build_fabric_bitstream.h
@@ -5,7 +5,9 @@
  * Include header files that are required by function declaration
  *******************************************************************/
 #include <vector>
+#include "config_protocol.h"
 #include "bitstream_manager.h"
+#include "fabric_bitstream.h"
 #include "module_manager.h"
 
 /********************************************************************
@@ -15,9 +17,10 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-std::vector<ConfigBitId> build_fabric_dependent_bitstream(const BitstreamManager& bitstream_manager,
-                                                          const ModuleManager& module_manager,
-                                                          const bool& verbose);
+FabricBitstream build_fabric_dependent_bitstream(const BitstreamManager& bitstream_manager,
+                                                 const ModuleManager& module_manager,
+                                                 const ConfigProtocol& config_protocol,
+                                                 const bool& verbose);
 
 } /* end namespace openfpga */
 
diff --git a/openfpga/src/fpga_bitstream/fabric_bitstream.cpp b/openfpga/src/fpga_bitstream/fabric_bitstream.cpp
index 581a466d5..988839cf8 100644
--- a/openfpga/src/fpga_bitstream/fabric_bitstream.cpp
+++ b/openfpga/src/fpga_bitstream/fabric_bitstream.cpp
@@ -56,17 +56,23 @@ FabricBitId FabricBitstream::add_bit(const ConfigBitId& config_bit_id) {
 }
 
 void FabricBitstream::set_bit_address(const FabricBitId& bit_id,
-                                             const std::vector<bool>& address) {
+                                      const std::vector<bool>& address) {
   VTR_ASSERT(true == valid_bit_id(bit_id));
   bit_addresses_[bit_id] = address;
 }
 
 void FabricBitstream::set_bit_din(const FabricBitId& bit_id,
-                                         const bool& din) {
+                                  const bool& din) {
   VTR_ASSERT(true == valid_bit_id(bit_id));
   bit_dins_[bit_id] = din;
 }
 
+void FabricBitstream::reverse() {
+  std::reverse(config_bit_ids_.begin(), config_bit_ids_.end());
+  std::reverse(bit_addresses_.begin(), bit_addresses_.end());
+  std::reverse(bit_dins_.begin(), bit_dins_.end());
+}
+
 /******************************************************************************
  * Public Validators
  ******************************************************************************/
diff --git a/openfpga/src/fpga_bitstream/fabric_bitstream.h b/openfpga/src/fpga_bitstream/fabric_bitstream.h
index 3f13406c4..0b4842aa8 100644
--- a/openfpga/src/fpga_bitstream/fabric_bitstream.h
+++ b/openfpga/src/fpga_bitstream/fabric_bitstream.h
@@ -67,6 +67,11 @@ class FabricBitstream {
     void set_bit_din(const FabricBitId& bit_id,
                      const bool& din);
 
+    /* Reverse bit sequence of the fabric bitstream
+     * This is required by configuration chain protocol 
+     */
+    void reverse();
+
   public:  /* Public Validators */
     bool valid_bit_id(const FabricBitId& bit_id) const;
 
diff --git a/openfpga/src/fpga_bitstream/fabric_bitstream_writer.cpp b/openfpga/src/fpga_bitstream/fabric_bitstream_writer.cpp
index 069a99345..f8ca706fa 100644
--- a/openfpga/src/fpga_bitstream/fabric_bitstream_writer.cpp
+++ b/openfpga/src/fpga_bitstream/fabric_bitstream_writer.cpp
@@ -31,14 +31,14 @@ namespace openfpga {
  *     in this file
  *******************************************************************/
 void write_fabric_bitstream_to_text_file(const BitstreamManager& bitstream_manager,
-                                         const std::vector<ConfigBitId>& fabric_bitstream,
+                                         const FabricBitstream& fabric_bitstream,
                                          const std::string& fname) {
   /* Ensure that we have a valid file name */
   if (true == fname.empty()) {
     VTR_LOG_ERROR("Received empty file name to output bitstream!\n\tPlease specify a valid file name.\n");
   }
 
-  std::string timer_message = std::string("Write ") + std::to_string(fabric_bitstream.size()) + std::string(" fabric bitstream into plain text file '") + fname + std::string("'");
+  std::string timer_message = std::string("Write ") + std::to_string(fabric_bitstream.bits().size()) + std::string(" fabric bitstream into plain text file '") + fname + std::string("'");
   vtr::ScopedStartFinishTimer timer(timer_message);
 
   /* Create the file stream */
@@ -48,8 +48,8 @@ void write_fabric_bitstream_to_text_file(const BitstreamManager& bitstream_manag
   check_file_stream(fname.c_str(), fp);
 
   /* Put down pure 0|1 bitstream here */
-  for (const ConfigBitId& fabric_bit : fabric_bitstream) {
-    fp << bitstream_manager.bit_value(fabric_bit);
+  for (const FabricBitId& fabric_bit : fabric_bitstream.bits()) {
+    fp << bitstream_manager.bit_value(fabric_bitstream.config_bit(fabric_bit));
   }
   /* Print an end to the file here */
   fp << std::endl;
diff --git a/openfpga/src/fpga_bitstream/fabric_bitstream_writer.h b/openfpga/src/fpga_bitstream/fabric_bitstream_writer.h
index 6b2c0e771..71c2addd8 100644
--- a/openfpga/src/fpga_bitstream/fabric_bitstream_writer.h
+++ b/openfpga/src/fpga_bitstream/fabric_bitstream_writer.h
@@ -7,6 +7,7 @@
 #include <string>
 #include <vector>
 #include "bitstream_manager.h"
+#include "fabric_bitstream.h"
 
 /********************************************************************
  * Function declaration
@@ -16,7 +17,7 @@
 namespace openfpga {
 
 void write_fabric_bitstream_to_text_file(const BitstreamManager& bitstream_manager,
-                                         const std::vector<ConfigBitId>& fabric_bitstream,
+                                         const FabricBitstream& fabric_bitstream,
                                          const std::string& fname);
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/fpga_verilog/verilog_api.cpp b/openfpga/src/fpga_verilog/verilog_api.cpp
index 2f92156fb..705cd4a65 100644
--- a/openfpga/src/fpga_verilog/verilog_api.cpp
+++ b/openfpga/src/fpga_verilog/verilog_api.cpp
@@ -147,7 +147,7 @@ void fpga_fabric_verilog(ModuleManager& module_manager,
  ********************************************************************/
 void fpga_verilog_testbench(const ModuleManager& module_manager,
                             const BitstreamManager& bitstream_manager, 
-                            const std::vector<ConfigBitId>& fabric_bitstream, 
+                            const FabricBitstream& fabric_bitstream, 
                             const AtomContext& atom_ctx, 
                             const PlacementContext& place_ctx, 
                             const IoLocationMap& io_location_map,
diff --git a/openfpga/src/fpga_verilog/verilog_api.h b/openfpga/src/fpga_verilog/verilog_api.h
index 3076beb47..94fbf3a29 100644
--- a/openfpga/src/fpga_verilog/verilog_api.h
+++ b/openfpga/src/fpga_verilog/verilog_api.h
@@ -16,6 +16,7 @@
 #include "netlist_manager.h"
 #include "module_manager.h"
 #include "bitstream_manager.h"
+#include "fabric_bitstream.h"
 #include "simulation_setting.h"
 #include "io_location_map.h"
 #include "vpr_netlist_annotation.h"
@@ -41,7 +42,7 @@ void fpga_fabric_verilog(ModuleManager& module_manager,
 
 void fpga_verilog_testbench(const ModuleManager& module_manager,
                             const BitstreamManager& bitstream_manager, 
-                            const std::vector<ConfigBitId>& fabric_bitstream, 
+                            const FabricBitstream& fabric_bitstream, 
                             const AtomContext& atom_ctx, 
                             const PlacementContext& place_ctx, 
                             const IoLocationMap& io_location_map,
diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
index dc4856cb3..9edce0b52 100644
--- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
@@ -694,7 +694,7 @@ void print_verilog_top_testbench_generic_stimulus(std::fstream& fp,
 static 
 void print_verilog_top_testbench_configuration_chain_bitstream(std::fstream& fp,
                                                                const BitstreamManager& bitstream_manager,
-                                                               const std::vector<ConfigBitId>& fabric_bitstream) {
+                                                               const FabricBitstream& fabric_bitstream) {
   /* Validate the file stream */
   valid_file_stream(fp);
 
@@ -720,11 +720,9 @@ void print_verilog_top_testbench_configuration_chain_bitstream(std::fstream& fp,
   /* Attention: the configuration chain protcol requires the last configuration bit is fed first
    * We will visit the fabric bitstream in a reverse way  
    */
-  std::vector<ConfigBitId> cc_bitstream = fabric_bitstream;
-  std::reverse(cc_bitstream.begin(), cc_bitstream.end());
-  for (const ConfigBitId& bit_id : cc_bitstream) {
+  for (const FabricBitId& bit_id : fabric_bitstream.bits()) {
     fp << "\t\t" << std::string(TOP_TESTBENCH_CC_PROG_TASK_NAME);
-    fp << "(1'b" << (size_t)bitstream_manager.bit_value(bit_id) << ");" << std::endl;
+    fp << "(1'b" << (size_t)bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id)) << ");" << std::endl;
   }
 
   /* Raise the flag of configuration done when bitstream loading is complete */
@@ -753,7 +751,7 @@ static
 void print_verilog_top_testbench_bitstream(std::fstream& fp,
                                            const e_config_protocol_type& sram_orgz_type,
                                            const BitstreamManager& bitstream_manager,
-                                           const std::vector<ConfigBitId>& fabric_bitstream) {
+                                           const FabricBitstream& fabric_bitstream) {
   /* Branch on the type of configuration protocol */
   switch (sram_orgz_type) {
   case CONFIG_MEM_STANDALONE:
@@ -794,7 +792,7 @@ void print_verilog_top_testbench_bitstream(std::fstream& fp,
  *******************************************************************/
 void print_verilog_top_testbench(const ModuleManager& module_manager,
                                  const BitstreamManager& bitstream_manager,
-                                 const std::vector<ConfigBitId>& fabric_bitstream,
+                                 const FabricBitstream& fabric_bitstream,
                                  const e_config_protocol_type& sram_orgz_type,
                                  const CircuitLibrary& circuit_lib,
                                  const std::vector<CircuitPortId>& global_ports,
@@ -842,7 +840,7 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
    * by traversing the linked-list and count the number of SRAM=1 or BL=1&WL=1 in it.
    * We plus 1 additional config clock cycle here because we need to reset everything during the first clock cycle
    */
-  size_t num_config_clock_cycles = 1 + fabric_bitstream.size();
+  size_t num_config_clock_cycles = 1 + fabric_bitstream.bits().size();
 
   /* Generate stimuli for general control signals */
   print_verilog_top_testbench_generic_stimulus(fp,
diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.h b/openfpga/src/fpga_verilog/verilog_top_testbench.h
index 39a2024d1..07e671e57 100644
--- a/openfpga/src/fpga_verilog/verilog_top_testbench.h
+++ b/openfpga/src/fpga_verilog/verilog_top_testbench.h
@@ -8,6 +8,7 @@
 #include <vector>
 #include "module_manager.h"
 #include "bitstream_manager.h"
+#include "fabric_bitstream.h"
 #include "circuit_library.h"
 #include "vpr_context.h"
 #include "io_location_map.h"
@@ -23,7 +24,7 @@ namespace openfpga {
 
 void print_verilog_top_testbench(const ModuleManager& module_manager,
                                  const BitstreamManager& bitstream_manager,
-                                 const std::vector<ConfigBitId>& fabric_bitstream,
+                                 const FabricBitstream& fabric_bitstream,
                                  const e_config_protocol_type& sram_orgz_type,
                                  const CircuitLibrary& circuit_lib,
                                  const std::vector<CircuitPortId>& global_ports,

From 85921dcc05b29b1415332b40faf4f410a43ad4e4 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 27 May 2020 17:04:11 -0600
Subject: [PATCH 569/645] add fabric bitstream builder for frame-based
 configuration protocol

---
 .../fpga_bitstream/build_fabric_bitstream.cpp | 134 +++++++++++++++++-
 1 file changed, 132 insertions(+), 2 deletions(-)

diff --git a/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp b/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp
index 3953e0c16..80026cbef 100644
--- a/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp
+++ b/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp
@@ -9,6 +9,10 @@
 #include "vtr_log.h"
 #include "vtr_time.h"
 
+/* Headers from openfpgautil library */
+#include "openfpga_decode.h"
+
+#include "openfpga_reserved_words.h"
 #include "openfpga_naming.h"
 
 #include "bitstream_manager_utils.h"
@@ -18,14 +22,15 @@
 namespace openfpga {
 
 /********************************************************************
- * This function will walk through all the configurable children under a module
+ * This function aims to build a bitstream for configuration chain-like protocol
+ * It will walk through all the configurable children under a module
  * in a recursive way, following a Depth-First Search (DFS) strategy
  * For each configuration child, we use its instance name as a key to spot the 
  * configuration bits in bitstream manager.
  * Note that it is guarentee that the instance name in module manager is 
  * consistent with the block names in bitstream manager
  * We use this link to reorganize the bitstream in the sequence of memories as we stored
- * in the configurable_children) and configurable_child_instances() of each module of module manager 
+ * in the configurable_children() and configurable_child_instances() of each module of module manager 
  *******************************************************************/
 static 
 void rec_build_module_fabric_dependent_chain_bitstream(const BitstreamManager& bitstream_manager,
@@ -68,6 +73,125 @@ void rec_build_module_fabric_dependent_chain_bitstream(const BitstreamManager& b
   }
 }
 
+/********************************************************************
+ * This function aims to build a bitstream for frame-based configuration protocol
+ * It will walk through all the configurable children under a module
+ * in a recursive way, following a Depth-First Search (DFS) strategy
+ * For each configuration child, we use its instance name as a key to spot the 
+ * configuration bits in bitstream manager.
+ * Note that it is guarentee that the instance name in module manager is 
+ * consistent with the block names in bitstream manager
+ * We use this link to reorganize the bitstream in the sequence of memories as we stored
+ * in the configurable_children() and configurable_child_instances() of each module of module manager 
+ *
+ * For each configuration bits, we will infer its address based on 
+ *  - the child index in the configurable children list of current module
+ *  - the child index of all the parent modules in their configurable children list 
+ *    until the top in the hierarchy
+ *
+ * The address will be organized as follows:
+ *  <Address_in_top> ... <Address_in_parent_module>
+ * The address will be decoded to a binary format
+ *
+ * For each configuration bit, the data_in for the frame-based decoders will be 
+ * the same as the configuration bit in bitstream manager.
+ *******************************************************************/
+static 
+void rec_build_module_fabric_dependent_frame_bitstream(const BitstreamManager& bitstream_manager,
+                                                       const std::vector<ConfigBlockId>& parent_blocks,
+                                                       const ModuleManager& module_manager,
+                                                       const std::vector<ModuleId>& parent_modules,
+                                                       const std::vector<bool>& addr_code,
+                                                       FabricBitstream& fabric_bitstream) {
+
+  /* Depth-first search: if we have any children in the parent_block, 
+   * we dive to the next level first! 
+   */
+  if (0 < bitstream_manager.block_children(parent_blocks.back()).size()) {
+    const ConfigBlockId& parent_block = parent_blocks.back();
+    const ModuleId& parent_module = parent_modules.back();
+
+    size_t num_configurable_children = module_manager.configurable_children(parent_modules.back()).size();
+
+    bool add_addr_code = true;
+    ModuleId decoder_module = ModuleId::INVALID();
+
+    /* Early exit if there is no configurable children */
+    if (0 == num_configurable_children) {
+      return;
+    }
+
+    /* For only 1 configurable child, there is not frame decoder need, we can pass on addr code directly */
+    if (1 == num_configurable_children) {
+      add_addr_code = false;
+    } else {
+    /* For more than 2 children, there is a decoder in the tail of the list
+     * We will not decode that, but will access the address size from that module
+     * So, we reduce the number of children by 1
+     */
+      VTR_ASSERT(2 < num_configurable_children);
+      num_configurable_children--;
+      decoder_module = module_manager.configurable_children(parent_module).back();
+    }
+
+    for (size_t child_id = 0; child_id < num_configurable_children; ++child_id) {
+      ModuleId child_module = module_manager.configurable_children(parent_modules.back())[child_id]; 
+      size_t child_instance = module_manager.configurable_child_instances(parent_module)[child_id]; 
+      /* Get the instance name and ensure it is not empty */
+      std::string instance_name = module_manager.instance_name(parent_module, child_module, child_instance);
+       
+      /* Find the child block that matches the instance name! */ 
+      ConfigBlockId child_block = bitstream_manager.find_child_block(parent_block, instance_name); 
+      /* We must have one valid block id! */
+      if (true != bitstream_manager.valid_block_id(child_block))
+      VTR_ASSERT(true == bitstream_manager.valid_block_id(child_block));
+
+      /* Pass on the list of blocks, modules and address lists */
+      std::vector<ConfigBlockId> child_blocks = parent_blocks;
+      child_blocks.push_back(child_block);
+
+      std::vector<ModuleId> child_modules = parent_modules;
+      child_modules.push_back(child_module);
+
+      /* Set address, apply binary conversion from the first to the last element in the address list */
+      std::vector<bool> child_addr_code = addr_code;
+
+      if (true == add_addr_code) { 
+        /* Find the address port from the decoder module */
+        const ModulePortId& decoder_addr_port_id = module_manager.find_module_port(decoder_module, std::string(DECODER_ADDRESS_PORT_NAME));
+        const BasicPort& decoder_addr_port = module_manager.module_port(decoder_module, decoder_addr_port_id);
+        std::vector<size_t> addr_bits_vec = itobin_vec(child_id, decoder_addr_port.get_width());
+        for (const size_t& bit : addr_bits_vec) {
+          VTR_ASSERT((0 == bit) || (1 == bit));
+          child_addr_code.push_back(bit);
+        }
+      }
+
+      /* Go recursively */
+      rec_build_module_fabric_dependent_frame_bitstream(bitstream_manager, child_blocks,
+                                                        module_manager, child_modules,
+                                                        child_addr_code,
+                                                        fabric_bitstream);
+    }
+    /* Ensure that there should be no configuration bits in the parent block */
+    VTR_ASSERT(0 == bitstream_manager.block_bits(parent_block).size());
+  }
+
+  /* Note that, reach here, it means that this is a leaf node. 
+   * We add the configuration bits to the fabric_bitstream,
+   * And then, we can return
+   */
+  for (const ConfigBitId& config_bit : bitstream_manager.block_bits(parent_blocks.back())) {
+    const FabricBitId& fabric_bit = fabric_bitstream.add_bit(config_bit);
+
+    /* Set address */
+    fabric_bitstream.set_bit_address(fabric_bit, addr_code);
+    
+    /* Set data input */
+    fabric_bitstream.set_bit_din(fabric_bit, bitstream_manager.bit_value(config_bit));
+  }
+}
+
 /********************************************************************
  * Main function to build a fabric-dependent bitstream
  * by considering the configuration protocol types 
@@ -98,6 +222,12 @@ void build_module_fabric_dependent_bitstream(const ConfigProtocol& config_protoc
     break;
   }
   case CONFIG_MEM_FRAME_BASED: {
+    rec_build_module_fabric_dependent_frame_bitstream(bitstream_manager,
+                                                      std::vector<ConfigBlockId>(1, top_block),
+                                                      module_manager,
+                                                      std::vector<ModuleId>(1, top_module),
+                                                      std::vector<bool>(),
+                                                      fabric_bitstream);
     break;
   }
   default:

From cff5b5cfc1f52a13c52da0808a3e9d42adfd7fe3 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 27 May 2020 18:40:45 -0600
Subject: [PATCH 570/645] break the configuration testbench. This commit is to
 spot which modification leads to the problem

---
 .../fpga_bitstream/build_fabric_bitstream.cpp |  11 +-
 .../src/fpga_bitstream/fabric_bitstream.cpp   |   4 +-
 .../src/fpga_bitstream/fabric_bitstream.h     |   6 +-
 .../fpga_verilog/verilog_top_testbench.cpp    | 217 +++++++++++++++++-
 4 files changed, 215 insertions(+), 23 deletions(-)

diff --git a/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp b/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp
index 80026cbef..4dc8ee70b 100644
--- a/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp
+++ b/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp
@@ -101,7 +101,7 @@ void rec_build_module_fabric_dependent_frame_bitstream(const BitstreamManager& b
                                                        const std::vector<ConfigBlockId>& parent_blocks,
                                                        const ModuleManager& module_manager,
                                                        const std::vector<ModuleId>& parent_modules,
-                                                       const std::vector<bool>& addr_code,
+                                                       const std::vector<size_t>& addr_code,
                                                        FabricBitstream& fabric_bitstream) {
 
   /* Depth-first search: if we have any children in the parent_block, 
@@ -154,17 +154,14 @@ void rec_build_module_fabric_dependent_frame_bitstream(const BitstreamManager& b
       child_modules.push_back(child_module);
 
       /* Set address, apply binary conversion from the first to the last element in the address list */
-      std::vector<bool> child_addr_code = addr_code;
+      std::vector<size_t> child_addr_code = addr_code;
 
       if (true == add_addr_code) { 
         /* Find the address port from the decoder module */
         const ModulePortId& decoder_addr_port_id = module_manager.find_module_port(decoder_module, std::string(DECODER_ADDRESS_PORT_NAME));
         const BasicPort& decoder_addr_port = module_manager.module_port(decoder_module, decoder_addr_port_id);
         std::vector<size_t> addr_bits_vec = itobin_vec(child_id, decoder_addr_port.get_width());
-        for (const size_t& bit : addr_bits_vec) {
-          VTR_ASSERT((0 == bit) || (1 == bit));
-          child_addr_code.push_back(bit);
-        }
+        child_addr_code.insert(child_addr_code.end(), addr_bits_vec.begin(), addr_bits_vec.end());
       }
 
       /* Go recursively */
@@ -226,7 +223,7 @@ void build_module_fabric_dependent_bitstream(const ConfigProtocol& config_protoc
                                                       std::vector<ConfigBlockId>(1, top_block),
                                                       module_manager,
                                                       std::vector<ModuleId>(1, top_module),
-                                                      std::vector<bool>(),
+                                                      std::vector<size_t>(),
                                                       fabric_bitstream);
     break;
   }
diff --git a/openfpga/src/fpga_bitstream/fabric_bitstream.cpp b/openfpga/src/fpga_bitstream/fabric_bitstream.cpp
index 988839cf8..7306eba01 100644
--- a/openfpga/src/fpga_bitstream/fabric_bitstream.cpp
+++ b/openfpga/src/fpga_bitstream/fabric_bitstream.cpp
@@ -27,7 +27,7 @@ ConfigBitId FabricBitstream::config_bit(const FabricBitId& bit_id) const {
   return config_bit_ids_[bit_id];
 }
 
-std::vector<bool> FabricBitstream::bit_address(const FabricBitId& bit_id) const {
+std::vector<size_t> FabricBitstream::bit_address(const FabricBitId& bit_id) const {
   /* Ensure a valid id */
   VTR_ASSERT(true == valid_bit_id(bit_id));
 
@@ -56,7 +56,7 @@ FabricBitId FabricBitstream::add_bit(const ConfigBitId& config_bit_id) {
 }
 
 void FabricBitstream::set_bit_address(const FabricBitId& bit_id,
-                                      const std::vector<bool>& address) {
+                                      const std::vector<size_t>& address) {
   VTR_ASSERT(true == valid_bit_id(bit_id));
   bit_addresses_[bit_id] = address;
 }
diff --git a/openfpga/src/fpga_bitstream/fabric_bitstream.h b/openfpga/src/fpga_bitstream/fabric_bitstream.h
index 0b4842aa8..12d1c7885 100644
--- a/openfpga/src/fpga_bitstream/fabric_bitstream.h
+++ b/openfpga/src/fpga_bitstream/fabric_bitstream.h
@@ -52,7 +52,7 @@ class FabricBitstream {
     ConfigBitId config_bit(const FabricBitId& bit_id) const;
 
     /* Find the address of bitstream */
-    std::vector<bool> bit_address(const FabricBitId& bit_id) const;
+    std::vector<size_t> bit_address(const FabricBitId& bit_id) const;
 
     /* Find the data-in of bitstream */
     bool bit_din(const FabricBitId& bit_id) const;
@@ -62,7 +62,7 @@ class FabricBitstream {
     FabricBitId add_bit(const ConfigBitId& config_bit_id);
 
     void set_bit_address(const FabricBitId& bit_id,
-                         const std::vector<bool>& address);
+                         const std::vector<size_t>& address);
 
     void set_bit_din(const FabricBitId& bit_id,
                      const bool& din);
@@ -84,7 +84,7 @@ class FabricBitstream {
      * Here we store the binary format of the address, which can be loaded
      * to the configuration protocol directly 
      */
-    vtr::vector<FabricBitId, std::vector<bool>> bit_addresses_;
+    vtr::vector<FabricBitId, std::vector<size_t>> bit_addresses_;
 
     /* Data input (Din) bits: this is designed for memory decoders */
     vtr::vector<FabricBitId, bool> bit_dins_;
diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
index 9edce0b52..3d2cad1ea 100644
--- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
@@ -41,7 +41,7 @@ constexpr char* TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX = "_fpga";
 
 constexpr char* TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX = "_flag";
 
-constexpr char* TOP_TESTBENCH_CC_PROG_TASK_NAME = "prog_cycle_task";
+constexpr char* TOP_TESTBENCH_PROG_TASK_NAME = "prog_cycle_task";
 
 constexpr char* TOP_TESTBENCH_SIM_START_PORT_NAME = "sim_start";
 
@@ -79,12 +79,49 @@ void print_verilog_top_testbench_config_chain_port(std::fstream& fp) {
   fp << generate_verilog_port(VERILOG_PORT_WIRE, config_chain_tail_port) << ";" << std::endl;
 }
 
+/********************************************************************
+ * Print local wires for frame-based decoder protocols
+ *******************************************************************/
+static 
+void print_verilog_top_testbench_frame_decoder_port(std::fstream& fp,
+                                                    const ModuleManager& module_manager,
+                                                    const ModuleId& top_module) {
+  /* Validate the file stream */
+  valid_file_stream(fp);
+
+  /* Print the address port for the frame-based decoder here */
+  print_verilog_comment(fp, std::string("---- Address port for frame-based decoder -----"));
+  ModulePortId addr_port_id = module_manager.find_module_port(top_module,
+                                                              std::string(DECODER_ADDRESS_PORT_NAME));
+  BasicPort addr_port = module_manager.module_port(top_module, addr_port_id);
+
+  fp << generate_verilog_port(VERILOG_PORT_REG, addr_port) << ";" << std::endl;
+
+  /* Print the data-input port for the frame-based decoder here */
+  print_verilog_comment(fp, std::string("---- Data input port for frame-based decoder -----"));
+  ModulePortId din_port_id = module_manager.find_module_port(top_module,
+                                                             std::string(DECODER_DATA_IN_PORT_NAME));
+  BasicPort din_port = module_manager.module_port(top_module, din_port_id);
+  fp << generate_verilog_port(VERILOG_PORT_WIRE, din_port) << ";" << std::endl;
+
+  /* Wire the programming clock to the enable signal */
+  print_verilog_comment(fp, std::string("---- Wire enable port of frame-based decoder to programming clock -----"));
+  ModulePortId en_port_id = module_manager.find_module_port(top_module,
+                                                            std::string(DECODER_ENABLE_PORT_NAME));
+  BasicPort en_port = module_manager.module_port(top_module, en_port_id);
+  BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME), 1);
+
+  print_verilog_wire_connection(fp, en_port, prog_clock_port, false);
+}
+
 /********************************************************************
  * Print local wires for different types of configuration protocols
  *******************************************************************/
 static 
 void print_verilog_top_testbench_config_protocol_port(std::fstream& fp,
-                                                      const e_config_protocol_type& sram_orgz_type) {
+                                                      const e_config_protocol_type& sram_orgz_type,
+                                                      const ModuleManager& module_manager,
+                                                      const ModuleId& top_module) {
   switch(sram_orgz_type) {
   case CONFIG_MEM_STANDALONE:
     /* TODO */
@@ -95,6 +132,9 @@ void print_verilog_top_testbench_config_protocol_port(std::fstream& fp,
   case CONFIG_MEM_MEMORY_BANK:
     /* TODO */
     break;
+  case CONFIG_MEM_FRAME_BASED:
+    print_verilog_top_testbench_frame_decoder_port(fp, module_manager, top_module);
+    break;
   default:
     VTR_LOGF_ERROR(__FILE__, __LINE__,
                    "Invalid type of SRAM organization!\n");
@@ -398,7 +438,8 @@ void print_verilog_top_testbench_ports(std::fstream& fp,
   fp << generate_verilog_port(VERILOG_PORT_REG, set_port) << ";" << std::endl;
 
   /* Configuration ports depend on the organization of SRAMs */
-  print_verilog_top_testbench_config_protocol_port(fp, sram_orgz_type);
+  print_verilog_top_testbench_config_protocol_port(fp, sram_orgz_type,
+                                                   module_manager, top_module);
 
   /* Create a clock port if the benchmark have one but not in the default name! 
    * We will wire the clock directly to the operating clock directly
@@ -506,15 +547,72 @@ void print_verilog_top_testbench_load_bitstream_task_configuration_chain(std::fs
    * It aims at avoid racing the programming clock (scan-chain data changes at the rising edge). 
    */
   print_verilog_comment(fp, std::string("----- Task: input values during a programming clock cycle -----"));
-  fp << "task " << std::string(TOP_TESTBENCH_CC_PROG_TASK_NAME) << ";" << std::endl;
+  fp << "task " << std::string(TOP_TESTBENCH_PROG_TASK_NAME) << ";" << std::endl;
   fp << generate_verilog_port(VERILOG_PORT_INPUT, cc_head_value) << ";" << std::endl;
   fp << "\tbegin" << std::endl;
   fp << "\t\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ");" << std::endl;
   fp << "\t\t\t"; 
-  fp << generate_verilog_port(VERILOG_PORT_CONKT, cc_head_port);
-  fp << " = ";
-  fp << generate_verilog_port(VERILOG_PORT_CONKT, cc_head_value);
-  fp << ";" << std::endl;
+  print_verilog_wire_connection(fp, cc_head_port, cc_head_value, false);
+  fp << std::endl;
+
+  fp << "\tend" << std::endl;
+  fp << "endtask" << std::endl;
+
+  /* Add an empty line as splitter */
+  fp << std::endl;
+}
+
+/********************************************************************
+ * Print tasks (processes) in Verilog format, 
+ * which is very useful in generating stimuli for each clock cycle 
+ * This function is tuned for frame-based memory manipulation: 
+ * During each programming cycle, we feed
+ * - an address to the address port of top module
+ * - a data input to the din port of top module
+ *******************************************************************/
+static 
+void print_verilog_top_testbench_load_bitstream_task_frame_decoder(std::fstream& fp,
+                                                                   const ModuleManager& module_manager,
+                                                                   const ModuleId& top_module) {
+
+  /* Validate the file stream */
+  valid_file_stream(fp);
+
+  BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME), 1);
+
+  ModulePortId addr_port_id = module_manager.find_module_port(top_module,
+                                                              std::string(DECODER_ADDRESS_PORT_NAME));
+  BasicPort addr_port = module_manager.module_port(top_module, addr_port_id);
+  BasicPort addr_value = addr_port;
+  addr_value.set_name(std::string(DECODER_ADDRESS_PORT_NAME) + std::string("_val"));
+
+  ModulePortId din_port_id = module_manager.find_module_port(top_module,
+                                                             std::string(DECODER_DATA_IN_PORT_NAME));
+  BasicPort din_port = module_manager.module_port(top_module, din_port_id);
+  BasicPort din_value = din_port;
+  din_value.set_name(std::string(DECODER_DATA_IN_PORT_NAME) + std::string("_val"));
+
+  /* Add an empty line as splitter */
+  fp << std::endl;
+
+  /* Feed the address and data input at each rising edge of programming clock 
+   * As the enable signal is wired to the programming clock, we should synchronize
+   * address and data with the enable signal
+   */
+  print_verilog_comment(fp, std::string("----- Task: address and data values during a programming clock cycle -----"));
+  fp << "task " << std::string(TOP_TESTBENCH_PROG_TASK_NAME) << ";" << std::endl;
+  fp << generate_verilog_port(VERILOG_PORT_INPUT, addr_value) << ";" << std::endl;
+  fp << generate_verilog_port(VERILOG_PORT_INPUT, din_value) << ";" << std::endl;
+  fp << "\tbegin" << std::endl;
+  fp << "\t\t@(posedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ");" << std::endl;
+
+  fp << "\t\t\t"; 
+  print_verilog_wire_connection(fp, addr_port, addr_value, false);
+  fp << std::endl;
+
+  fp << "\t\t\t"; 
+  print_verilog_wire_connection(fp, din_port, din_value, false);
+  fp << std::endl;
 
   fp << "\tend" << std::endl;
   fp << "endtask" << std::endl;
@@ -528,7 +626,9 @@ void print_verilog_top_testbench_load_bitstream_task_configuration_chain(std::fs
  *******************************************************************/
 static 
 void print_verilog_top_testbench_load_bitstream_task(std::fstream& fp,
-                                                     const e_config_protocol_type& sram_orgz_type) {
+                                                     const e_config_protocol_type& sram_orgz_type,
+                                                     const ModuleManager& module_manager,
+                                                     const ModuleId& top_module) {
   switch (sram_orgz_type) {
   case CONFIG_MEM_STANDALONE:
     break;
@@ -540,6 +640,11 @@ void print_verilog_top_testbench_load_bitstream_task(std::fstream& fp,
     dump_verilog_top_testbench_stimuli_serial_version_tasks_memory_bank(cur_sram_orgz_info, fp);
      */
     break;
+  case CONFIG_MEM_FRAME_BASED:
+    print_verilog_top_testbench_load_bitstream_task_frame_decoder(fp,
+                                                                  module_manager,
+                                                                  top_module);
+    break;
   default:
     VTR_LOGF_ERROR(__FILE__, __LINE__,
                    "Invalid type of SRAM organization!\n");
@@ -721,7 +826,7 @@ void print_verilog_top_testbench_configuration_chain_bitstream(std::fstream& fp,
    * We will visit the fabric bitstream in a reverse way  
    */
   for (const FabricBitId& bit_id : fabric_bitstream.bits()) {
-    fp << "\t\t" << std::string(TOP_TESTBENCH_CC_PROG_TASK_NAME);
+    fp << "\t\t" << std::string(TOP_TESTBENCH_PROG_TASK_NAME);
     fp << "(1'b" << (size_t)bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id)) << ");" << std::endl;
   }
 
@@ -741,6 +846,86 @@ void print_verilog_top_testbench_configuration_chain_bitstream(std::fstream& fp,
   print_verilog_comment(fp, "----- End bitstream loading during configuration phase -----");
 }
 
+/********************************************************************
+ * Print stimulus for a FPGA fabric with a frame-based configuration protocol 
+ * where configuration bits are programming in serial (one by one)
+ *
+ * We will use the programming task function created before
+ *******************************************************************/
+static 
+void print_verilog_top_testbench_frame_decoder_bitstream(std::fstream& fp,
+                                                         const ModuleManager& module_manager,
+                                                         const ModuleId& top_module,
+                                                         const FabricBitstream& fabric_bitstream) {
+  /* Validate the file stream */
+  valid_file_stream(fp);
+
+  /* Feed addresss and data input pair one by one 
+   * Note: the first cycle is reserved for programming reset
+   * We should give dummy values 
+   */
+  ModulePortId addr_port_id = module_manager.find_module_port(top_module,
+                                                              std::string(DECODER_ADDRESS_PORT_NAME));
+  BasicPort addr_port = module_manager.module_port(top_module, addr_port_id);
+  std::vector<size_t> initial_addr_values(addr_port.get_width(), 0);
+
+  ModulePortId din_port_id = module_manager.find_module_port(top_module,
+                                                             std::string(DECODER_DATA_IN_PORT_NAME));
+  BasicPort din_port = module_manager.module_port(top_module, din_port_id);
+  std::vector<size_t> initial_din_values(din_port.get_width(), 0);
+
+  print_verilog_comment(fp, "----- Begin bitstream loading during configuration phase -----");
+  fp << "initial" << std::endl;
+  fp << "\tbegin" << std::endl;
+  print_verilog_comment(fp, "----- Address port default input -----");
+  fp << "\t\t";
+  fp << generate_verilog_port_constant_values(addr_port, initial_addr_values);
+  fp << ";";
+
+  print_verilog_comment(fp, "----- Data-input port default input -----");
+  fp << "\t\t";
+  fp << generate_verilog_port_constant_values(din_port, initial_din_values);
+  fp << ";";
+
+  fp << std::endl;
+
+  /* Attention: the configuration chain protcol requires the last configuration bit is fed first
+   * We will visit the fabric bitstream in a reverse way  
+   */
+  for (const FabricBitId& bit_id : fabric_bitstream.bits()) {
+    fp << "\t\t" << std::string(TOP_TESTBENCH_PROG_TASK_NAME);
+    fp << "(" << addr_port.get_width() << "'b";
+    VTR_ASSERT(addr_port.get_width() == fabric_bitstream.bit_address(bit_id).size());
+    for (const size_t& addr_bit : fabric_bitstream.bit_address(bit_id)) {
+      fp << addr_bit; 
+    }
+    fp << ", ";
+    fp <<"1'b";
+    if (true == fabric_bitstream.bit_din(bit_id)) {
+      fp << "1";
+    } else {
+      VTR_ASSERT(false == fabric_bitstream.bit_din(bit_id));
+      fp << "0";
+    }
+    fp << ");" << std::endl;
+  }
+
+  /* Raise the flag of configuration done when bitstream loading is complete */
+  BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME), 1);
+  fp << "\t\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ");" << std::endl;
+  
+  BasicPort config_done_port(std::string(TOP_TB_CONFIG_DONE_PORT_NAME), 1);
+  fp << "\t\t\t";
+  fp << generate_verilog_port(VERILOG_PORT_CONKT, config_done_port);
+  fp << " <= ";
+  std::vector<size_t> config_done_enable_values(config_done_port.get_width(), 1);
+  fp << generate_verilog_constant_values(config_done_enable_values);
+  fp << ";" << std::endl;
+
+  fp << "\tend" << std::endl;
+  print_verilog_comment(fp, "----- End bitstream loading during configuration phase -----");
+}
+
 /********************************************************************
  * Generate the stimuli for the top-level testbench 
  * The simulation consists of two phases: configuration phase and operation phase
@@ -750,6 +935,8 @@ void print_verilog_top_testbench_configuration_chain_bitstream(std::fstream& fp,
 static 
 void print_verilog_top_testbench_bitstream(std::fstream& fp,
                                            const e_config_protocol_type& sram_orgz_type,
+                                           const ModuleManager& module_manager,
+                                           const ModuleId& top_module,
                                            const BitstreamManager& bitstream_manager,
                                            const FabricBitstream& fabric_bitstream) {
   /* Branch on the type of configuration protocol */
@@ -763,6 +950,11 @@ void print_verilog_top_testbench_bitstream(std::fstream& fp,
   case CONFIG_MEM_MEMORY_BANK:
     /* TODO */
     break;
+  case CONFIG_MEM_FRAME_BASED:
+    print_verilog_top_testbench_frame_decoder_bitstream(fp,
+                                                        module_manager, top_module,
+                                                        fabric_bitstream);
+    break;
   default: 
     VTR_LOGF_ERROR(__FILE__, __LINE__,
                    "Invalid SRAM organization type!\n");
@@ -875,10 +1067,13 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
                                                  explicit_port_mapping); 
 
   /* Print tasks used for loading bitstreams */
-  print_verilog_top_testbench_load_bitstream_task(fp, sram_orgz_type);
+  print_verilog_top_testbench_load_bitstream_task(fp,
+                                                  sram_orgz_type,
+                                                  module_manager, top_module);
 
   /* load bitstream to FPGA fabric in a configuration phase */
   print_verilog_top_testbench_bitstream(fp, sram_orgz_type,
+                                        module_manager, top_module,
                                         bitstream_manager, fabric_bitstream);
 
   /* Add stimuli for reset, set, clock and iopad signals */

From ece651ade20ac48acb0b753d2254f393d766b27c Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 27 May 2020 18:47:27 -0600
Subject: [PATCH 571/645] bug fixed in the configuration chian errrors

---
 .../src/fpga_verilog/verilog_top_testbench.cpp   | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
index 3d2cad1ea..9041df361 100644
--- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
@@ -552,8 +552,10 @@ void print_verilog_top_testbench_load_bitstream_task_configuration_chain(std::fs
   fp << "\tbegin" << std::endl;
   fp << "\t\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ");" << std::endl;
   fp << "\t\t\t"; 
-  print_verilog_wire_connection(fp, cc_head_port, cc_head_value, false);
-  fp << std::endl;
+  fp << generate_verilog_port(VERILOG_PORT_CONKT, cc_head_port);
+  fp << " = "; 
+  fp << generate_verilog_port(VERILOG_PORT_CONKT, cc_head_value);
+  fp << ";" << std::endl;
 
   fp << "\tend" << std::endl;
   fp << "endtask" << std::endl;
@@ -607,11 +609,17 @@ void print_verilog_top_testbench_load_bitstream_task_frame_decoder(std::fstream&
   fp << "\t\t@(posedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ");" << std::endl;
 
   fp << "\t\t\t"; 
-  print_verilog_wire_connection(fp, addr_port, addr_value, false);
+  fp << generate_verilog_port(VERILOG_PORT_CONKT, addr_port);
+  fp << " = "; 
+  fp << generate_verilog_port(VERILOG_PORT_CONKT, addr_value);
+  fp << ";" << std::endl;
   fp << std::endl;
 
   fp << "\t\t\t"; 
-  print_verilog_wire_connection(fp, din_port, din_value, false);
+  fp << generate_verilog_port(VERILOG_PORT_CONKT, din_port);
+  fp << " = "; 
+  fp << generate_verilog_port(VERILOG_PORT_CONKT, din_value);
+  fp << ";" << std::endl;
   fp << std::endl;
 
   fp << "\tend" << std::endl;

From 3fa3b170610905711455011781c3207e878b3b64 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 28 May 2020 10:19:04 -0600
Subject: [PATCH 572/645] start testing the frame-based configuration protocol.
 To distinguish, rename xml to identify between configuration chain and
 frame-based. This should not impact the pre-config testbenches.

---
 ...penfpga.xml => k4_N4_40nm_cc_openfpga.xml} |   0
 .../k4_N4_40nm_frame_openfpga.xml             | 229 ++++++++++++++++++
 .../configuration_chain/config/task.conf      |   2 +-
 3 files changed, 230 insertions(+), 1 deletion(-)
 rename openfpga_flow/openfpga_arch/{k4_N4_40nm_openfpga.xml => k4_N4_40nm_cc_openfpga.xml} (100%)
 create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml

diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
similarity index 100%
rename from openfpga_flow/openfpga_arch/k4_N4_40nm_openfpga.xml
rename to openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml
new file mode 100644
index 000000000..e5fe5a89b
--- /dev/null
+++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml
@@ -0,0 +1,229 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="4"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="16"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="sram" name="config_mem" prefix="config_mem" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/sram.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="bl" prefix="bl" size="1"/>
+       <port type="wl" prefix="wl" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="Qb" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="config_mem" default_val="1"/>
+      <port type="input" prefix="outpad" size="1"/>
+      <port type="output" prefix="inpad" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="frame_based" circuit_model_name="config_mem"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="static_dff"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>
+<openfpga_simulation_setting>
+  <clock_setting>
+    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
+    <programming frequency="100e6"/>
+  </clock_setting>
+  <simulator_option>
+    <operating_condition temperature="25"/>
+    <output_log verbose="false" captab="false"/>
+    <accuracy type="abs" value="1e-13"/>
+    <runtime fast_simulation="true"/>
+  </simulator_option>
+  <monte_carlo num_simulation_points="2"/>
+  <measurement_setting>
+    <slew>
+      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
+      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
+    </slew>
+    <delay>
+      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
+      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
+    </delay>
+  </measurement_setting>
+  <stimulus>
+    <clock>
+      <rise slew_type="abs" slew_time="20e-12" />
+      <fall slew_type="abs" slew_time="20e-12" />
+    </clock>
+    <input>
+      <rise slew_type="abs" slew_time="25e-12" />
+      <fall slew_type="abs" slew_time="25e-12" />
+    </input>
+  </stimulus>
+</openfpga_simulation_setting>
diff --git a/openfpga_flow/tasks/openfpga_shell/configuration_chain/config/task.conf b/openfpga_flow/tasks/openfpga_shell/configuration_chain/config/task.conf
index 9e18efc65..8318c1dea 100644
--- a/openfpga_flow/tasks/openfpga_shell/configuration_chain/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/configuration_chain/config/task.conf
@@ -15,7 +15,7 @@ spice_output=false
 verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
-openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_openfpga.xml
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml

From 3a0d3b4e95e13b84d83bc649c9d338f4b7e958bd Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 28 May 2020 11:01:08 -0600
Subject: [PATCH 573/645] fix the broken CI/regression tests due to incorrect
 file path

---
 .../src/check_circuit_library.cpp             |  2 +-
 .../src/read_xml_circuit_library.cpp          |  2 +-
 .../configuration_frame/config/task.conf      | 34 +++++++++++++++++++
 .../sdc_time_unit/config/task.conf            |  2 +-
 4 files changed, 37 insertions(+), 3 deletions(-)
 create mode 100644 openfpga_flow/tasks/openfpga_shell/configuration_frame/config/task.conf

diff --git a/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp b/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp
index f37742a5a..11cea2d44 100644
--- a/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp
+++ b/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp
@@ -282,7 +282,7 @@ size_t check_sram_circuit_model_ports(const CircuitLibrary& circuit_lib,
   /* Check if we has 1 output with size 2 */
   num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model, 
                                                                  CIRCUIT_MODEL_PORT_OUTPUT,
-                                                                 1, 2, false);
+                                                                 2, 2, false);
   /* basic check finished here */
   if (false == check_blwl) {
     return num_err;
diff --git a/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp b/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp
index ba6e6af7f..7a894ab34 100644
--- a/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp
+++ b/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp
@@ -553,7 +553,7 @@ void read_xml_circuit_port(pugi::xml_node& xml_port,
      || (CIRCUIT_MODEL_PORT_WL  == circuit_lib.port_type(port))
      || (CIRCUIT_MODEL_PORT_BLB == circuit_lib.port_type(port))
      || (CIRCUIT_MODEL_PORT_WLB == circuit_lib.port_type(port)) ) {
-    circuit_lib.set_port_inv_model_name(port, get_attribute(xml_port, "inv_circuit_model_name", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string(nullptr));
+    circuit_lib.set_port_inv_model_name(port, get_attribute(xml_port, "inv_circuit_model_name", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string());
   }
 }
 
diff --git a/openfpga_flow/tasks/openfpga_shell/configuration_frame/config/task.conf b/openfpga_flow/tasks/openfpga_shell/configuration_frame/config/task.conf
new file mode 100644
index 000000000..87c487f63
--- /dev/null
+++ b/openfpga_flow/tasks/openfpga_shell/configuration_frame/config/task.conf
@@ -0,0 +1,34 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+#vpr_fpga_verilog_formal_verification_top_netlist=
diff --git a/openfpga_flow/tasks/openfpga_shell/sdc_time_unit/config/task.conf b/openfpga_flow/tasks/openfpga_shell/sdc_time_unit/config/task.conf
index 1aeaa036f..332020fab 100644
--- a/openfpga_flow/tasks/openfpga_shell/sdc_time_unit/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/sdc_time_unit/config/task.conf
@@ -15,7 +15,7 @@ spice_output=false
 verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
-openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_openfpga.xml
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml

From 65df309419c483371cd492c981261d36bf63b28f Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 28 May 2020 12:25:47 -0600
Subject: [PATCH 574/645] bug fixing for frame-based configuration protocol and
 rename some naming function to be generic

---
 .../src/check_circuit_library.cpp             |  8 ++--
 openfpga/src/base/openfpga_naming.cpp         |  8 ++--
 openfpga/src/base/openfpga_naming.h           |  4 +-
 openfpga/src/fabric/build_grid_modules.cpp    | 11 +++--
 openfpga/src/fabric/build_memory_modules.cpp  | 44 ++++++++++++++-----
 .../fpga_bitstream/arch_bitstream_writer.cpp  |  2 +-
 .../fpga_bitstream/build_grid_bitstream.cpp   |  6 +--
 .../build_routing_bitstream.cpp               |  4 +-
 .../verilog_preconfig_top_module.cpp          |  8 ++--
 openfpga/src/utils/circuit_library_utils.cpp  |  3 +-
 openfpga/src/utils/memory_utils.cpp           | 19 +++++---
 openfpga/src/utils/module_manager_utils.cpp   | 21 ++++++---
 openfpga/src/utils/mux_utils.cpp              |  1 +
 13 files changed, 90 insertions(+), 49 deletions(-)

diff --git a/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp b/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp
index 11cea2d44..fe364bf0f 100644
--- a/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp
+++ b/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp
@@ -135,9 +135,11 @@ size_t check_one_circuit_model_port_size_required(const CircuitLibrary& circuit_
   size_t num_err = 0;
 
   if (port_size_to_check != circuit_lib.port_size(circuit_port)) {
-    VTR_LOG_ERROR(circuit_lib.model_name(circuit_model).c_str(), 
+    VTR_LOG_ERROR("Expect circuit model %s to have %d %s ports but only see %d!\n",
+                  circuit_lib.model_name(circuit_model).c_str(), 
+                  port_size_to_check,
                   CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(circuit_lib.port_type(circuit_port))],
-                  port_size_to_check);
+                  circuit_lib.port_size(circuit_port));
     /* Incremental the counter for errors */
     num_err++;
   }
@@ -282,7 +284,7 @@ size_t check_sram_circuit_model_ports(const CircuitLibrary& circuit_lib,
   /* Check if we has 1 output with size 2 */
   num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model, 
                                                                  CIRCUIT_MODEL_PORT_OUTPUT,
-                                                                 2, 2, false);
+                                                                 2, 1, false);
   /* basic check finished here */
   if (false == check_blwl) {
     return num_err;
diff --git a/openfpga/src/base/openfpga_naming.cpp b/openfpga/src/base/openfpga_naming.cpp
index 5c9c81eb3..dd5e7df2c 100644
--- a/openfpga/src/base/openfpga_naming.cpp
+++ b/openfpga/src/base/openfpga_naming.cpp
@@ -687,18 +687,18 @@ std::string generate_configuration_chain_tail_name() {
 }
 
 /*********************************************************************
- * Generate the memory output port name of a configuration chain
+ * Generate the memory output port name of a configurable memory
  * TODO: This could be replaced as a constexpr string
  *********************************************************************/
-std::string generate_configuration_chain_data_out_name() {
+std::string generate_configurable_memory_data_out_name() {
   return std::string("mem_out");
 }
 
 /*********************************************************************
- * Generate the inverted memory output port name of a configuration chain
+ * Generate the inverted memory output port name of a configurable memory
  * TODO: This could be replaced as a constexpr string
  *********************************************************************/
-std::string generate_configuration_chain_inverted_data_out_name() {
+std::string generate_configurable_memory_inverted_data_out_name() {
   return std::string("mem_outb");
 }
 
diff --git a/openfpga/src/base/openfpga_naming.h b/openfpga/src/base/openfpga_naming.h
index d3cfb04f0..4e1c44fa9 100644
--- a/openfpga/src/base/openfpga_naming.h
+++ b/openfpga/src/base/openfpga_naming.h
@@ -168,9 +168,9 @@ std::string generate_configuration_chain_head_name();
 
 std::string generate_configuration_chain_tail_name();
 
-std::string generate_configuration_chain_data_out_name();
+std::string generate_configurable_memory_data_out_name();
 
-std::string generate_configuration_chain_inverted_data_out_name();
+std::string generate_configurable_memory_inverted_data_out_name();
 
 std::string generate_mux_local_decoder_addr_port_name();
 
diff --git a/openfpga/src/fabric/build_grid_modules.cpp b/openfpga/src/fabric/build_grid_modules.cpp
index b189a20fe..7a9e3b2b4 100644
--- a/openfpga/src/fabric/build_grid_modules.cpp
+++ b/openfpga/src/fabric/build_grid_modules.cpp
@@ -414,7 +414,8 @@ void add_module_pb_graph_pin2pin_net(ModuleManager& module_manager,
     module_manager.add_module_net_sink(pb_module, pin2pin_net, pin_pb_type_module, pin_pb_type_instance, pin_module_port_id, pin_module_pin_id);
     break;
   default:
-    VTR_LOGF_ERROR(__FILE__, __LINE__, "Invalid pin-to-pin interconnection type!\n");
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid pin-to-pin interconnection type!\n");
     exit(1);
   }
 }
@@ -598,8 +599,9 @@ void add_module_pb_graph_pin_interc(ModuleManager& module_manager,
     break;
   }
   default:
-    VTR_LOGF_ERROR(__FILE__, __LINE__, "Invalid interconnection type for %s [at Architecture XML LINE%d]!\n",
-                  cur_interc->name, cur_interc->line_num);
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid interconnection type for %s [at Architecture XML LINE%d]!\n",
+                   cur_interc->name, cur_interc->line_num);
     exit(1);
   }
 }
@@ -686,7 +688,8 @@ void add_module_pb_graph_port_interc(ModuleManager& module_manager,
     break;
   }
   default:
-    VTR_LOGF_ERROR(__FILE__, __LINE__, "Invalid pb port type!\n");
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid pb port type!\n");
     exit(1);
   }
 }
diff --git a/openfpga/src/fabric/build_memory_modules.cpp b/openfpga/src/fabric/build_memory_modules.cpp
index f8db73d7a..58ddd6de6 100644
--- a/openfpga/src/fabric/build_memory_modules.cpp
+++ b/openfpga/src/fabric/build_memory_modules.cpp
@@ -396,10 +396,10 @@ void build_memory_chain_module(ModuleManager& module_manager,
   for (size_t iport = 0; iport < sram_output_ports.size(); ++iport) {
     std::string port_name;
     if (0 == iport) {
-      port_name = generate_configuration_chain_data_out_name();
+      port_name = generate_configurable_memory_data_out_name();
     } else {
       VTR_ASSERT( 1 == iport);
-      port_name = generate_configuration_chain_inverted_data_out_name();
+      port_name = generate_configurable_memory_inverted_data_out_name();
     }
     BasicPort output_port(port_name, num_mems);
     module_manager.add_port(mem_module, output_port, ModuleManager::MODULE_OUTPUT_PORT);
@@ -421,10 +421,10 @@ void build_memory_chain_module(ModuleManager& module_manager,
     for (size_t iport = 0; iport < sram_output_ports.size(); ++iport) {
       std::string port_name;
       if (0 == iport) {
-        port_name = generate_configuration_chain_data_out_name();
+        port_name = generate_configurable_memory_data_out_name();
       } else {
         VTR_ASSERT( 1 == iport);
-        port_name = generate_configuration_chain_inverted_data_out_name();
+        port_name = generate_configurable_memory_inverted_data_out_name();
       }
       std::vector<ModuleNetId> output_nets = add_module_output_nets_to_chain_mem_modules(module_manager, mem_module, 
                                                                                          port_name, circuit_lib, sram_output_ports[iport],
@@ -657,12 +657,22 @@ void build_frame_memory_module(ModuleManager& module_manager,
   ModulePortId mem_addr_port = module_manager.add_port(mem_module, addr_port, ModuleManager::MODULE_INPUT_PORT);
 
   /* Input: Data port */
-  BasicPort data_port(std::string(DECODER_DATA_IN_PORT_NAME), data_size);
+  BasicPort data_port(std::string(DECODER_DATA_IN_PORT_NAME), 1);
   ModulePortId mem_data_port = module_manager.add_port(mem_module, data_port, ModuleManager::MODULE_INPUT_PORT);
 
+  /* Should have only 1 or 2 output port */
+  VTR_ASSERT( (1 == sram_output_ports.size()) || ( 2 == sram_output_ports.size()) );
+
   /* Add each output port: port width should match the number of memories */
-  for (const auto& port : sram_output_ports) {
-    BasicPort output_port(circuit_lib.port_prefix(port), num_mems * circuit_lib.port_size(port));
+  for (size_t iport = 0; iport < sram_output_ports.size(); ++iport) {
+    std::string port_name;
+    if (0 == iport) {
+      port_name = generate_configurable_memory_data_out_name();
+    } else {
+      VTR_ASSERT( 1 == iport);
+      port_name = generate_configurable_memory_inverted_data_out_name();
+    }
+    BasicPort output_port(port_name, num_mems);
     module_manager.add_port(mem_module, output_port, ModuleManager::MODULE_OUTPUT_PORT);
   }
 
@@ -717,7 +727,19 @@ void build_frame_memory_module(ModuleManager& module_manager,
     }
 
     /* Wire inputs of parent module to outputs of child modules */
-    add_module_output_nets_to_mem_modules(module_manager, mem_module, circuit_lib, sram_output_ports, sram_mem_module, i, sram_instance);
+    for (size_t iport = 0; iport < sram_output_ports.size(); ++iport) {
+      std::string port_name;
+      if (0 == iport) {
+        port_name = generate_configurable_memory_data_out_name();
+      } else {
+        VTR_ASSERT( 1 == iport);
+        port_name = generate_configurable_memory_inverted_data_out_name();
+      }
+
+      add_module_output_nets_to_chain_mem_modules(module_manager, mem_module, 
+                                                  port_name, circuit_lib, sram_output_ports[iport],
+                                                  sram_mem_module, i, sram_instance);
+    }
   }
 
   /* Add global ports to the pb_module:
@@ -727,7 +749,6 @@ void build_frame_memory_module(ModuleManager& module_manager,
   add_module_global_ports_from_child_modules(module_manager, mem_module);
 }
 
-
 /*********************************************************************
  * Generate Verilog modules for the memories that are used
  * by a circuit model 
@@ -818,8 +839,9 @@ void build_mux_memory_module(ModuleManager& module_manager,
      */ 
     break;
   default:
-    VTR_LOGF_ERROR(__FILE__, __LINE__, "Invalid design technology of multiplexer '%s'\n",
-                  circuit_lib.model_name(mux_model).c_str()); 
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid design technology of multiplexer '%s'\n",
+                   circuit_lib.model_name(mux_model).c_str()); 
     exit(1);
   }
 }
diff --git a/openfpga/src/fpga_bitstream/arch_bitstream_writer.cpp b/openfpga/src/fpga_bitstream/arch_bitstream_writer.cpp
index 6a87a6768..7f7e8ed07 100644
--- a/openfpga/src/fpga_bitstream/arch_bitstream_writer.cpp
+++ b/openfpga/src/fpga_bitstream/arch_bitstream_writer.cpp
@@ -85,7 +85,7 @@ void rec_write_block_bitstream_to_xml_file(std::fstream& fp,
   fp << "\t<bitstream>" << std::endl;
   for (const ConfigBitId& child_bit : bitstream_manager.block_bits(block)) {
     fp << "\t\t<bit";
-    fp << " memory_port=\"" << generate_configuration_chain_data_out_name() << "[" << bit_counter << "]" << "\"";
+    fp << " memory_port=\"" << generate_configurable_memory_data_out_name() << "[" << bit_counter << "]" << "\"";
     fp << " value=\"" << bitstream_manager.bit_value(child_bit) << "\"";
     fp << "/>" << std::endl;
     bit_counter++;
diff --git a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
index 204b80260..204d7b31e 100644
--- a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
+++ b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
@@ -98,7 +98,7 @@ void build_primitive_bitstream(BitstreamManager& bitstream_manager,
   std::string mem_block_name = generate_memory_module_name(circuit_lib, primitive_model, sram_models[0], std::string(MEMORY_MODULE_POSTFIX));
   ModuleId mem_module = module_manager.find_module(mem_block_name);
   VTR_ASSERT (true == module_manager.valid_module_id(mem_module));
-  ModulePortId mem_out_port_id = module_manager.find_module_port(mem_module, generate_configuration_chain_data_out_name());
+  ModulePortId mem_out_port_id = module_manager.find_module_port(mem_module, generate_configurable_memory_data_out_name());
   VTR_ASSERT(mode_select_bitstream.size() == module_manager.module_port(mem_module, mem_out_port_id).get_width());
 
   /* Create a block for the bitstream which corresponds to the memory module associated to the LUT */
@@ -194,7 +194,7 @@ void build_physical_block_pin_interc_bitstream(BitstreamManager& bitstream_manag
     std::string mem_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string(MEMORY_MODULE_POSTFIX)); 
     ModuleId mux_mem_module = module_manager.find_module(mem_module_name); 
     VTR_ASSERT (true == module_manager.valid_module_id(mux_mem_module));
-    ModulePortId mux_mem_out_port_id = module_manager.find_module_port(mux_mem_module, generate_configuration_chain_data_out_name());
+    ModulePortId mux_mem_out_port_id = module_manager.find_module_port(mux_mem_module, generate_configurable_memory_data_out_name());
     VTR_ASSERT(mux_bitstream.size() == module_manager.module_port(mux_mem_module, mux_mem_out_port_id).get_width());
   
     /* Add the bistream to the bitstream manager */
@@ -424,7 +424,7 @@ void build_lut_bitstream(BitstreamManager& bitstream_manager,
   std::string mem_block_name = generate_memory_module_name(circuit_lib, lut_model, sram_models[0], std::string(MEMORY_MODULE_POSTFIX));
   ModuleId mem_module = module_manager.find_module(mem_block_name);
   VTR_ASSERT (true == module_manager.valid_module_id(mem_module));
-  ModulePortId mem_out_port_id = module_manager.find_module_port(mem_module, generate_configuration_chain_data_out_name());
+  ModulePortId mem_out_port_id = module_manager.find_module_port(mem_module, generate_configurable_memory_data_out_name());
   VTR_ASSERT(lut_bitstream.size() == module_manager.module_port(mem_module, mem_out_port_id).get_width());
 
   /* Create a block for the bitstream which corresponds to the memory module associated to the LUT */
diff --git a/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp b/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp
index faef05174..0713fcb09 100644
--- a/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp
+++ b/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp
@@ -76,7 +76,7 @@ void build_switch_block_mux_bitstream(BitstreamManager& bitstream_manager,
   std::string mem_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string(MEMORY_MODULE_POSTFIX)); 
   ModuleId mux_mem_module = module_manager.find_module(mem_module_name); 
   VTR_ASSERT (true == module_manager.valid_module_id(mux_mem_module));
-  ModulePortId mux_mem_out_port_id = module_manager.find_module_port(mux_mem_module, generate_configuration_chain_data_out_name());
+  ModulePortId mux_mem_out_port_id = module_manager.find_module_port(mux_mem_module, generate_configurable_memory_data_out_name());
   VTR_ASSERT(mux_bitstream.size() == module_manager.module_port(mux_mem_module, mux_mem_out_port_id).get_width());
 
   /* Add the bistream to the bitstream manager */
@@ -230,7 +230,7 @@ void build_connection_block_mux_bitstream(BitstreamManager& bitstream_manager,
   std::string mem_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string(MEMORY_MODULE_POSTFIX)); 
   ModuleId mux_mem_module = module_manager.find_module(mem_module_name); 
   VTR_ASSERT (true == module_manager.valid_module_id(mux_mem_module));
-  ModulePortId mux_mem_out_port_id = module_manager.find_module_port(mux_mem_module, generate_configuration_chain_data_out_name());
+  ModulePortId mux_mem_out_port_id = module_manager.find_module_port(mux_mem_module, generate_configurable_memory_data_out_name());
   VTR_ASSERT(mux_bitstream.size() == module_manager.module_port(mux_mem_module, mux_mem_out_port_id).get_width());
 
   /* Add the bistream to the bitstream manager */
diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
index 8e577dfb4..973f7d0ff 100644
--- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
+++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
@@ -206,7 +206,7 @@ void print_verilog_preconfig_top_module_assign_bitstream(std::fstream& fp,
     bit_hierarchy_path += std::string(".");
 
     /* Find the bit index in the parent block */
-    BasicPort config_data_port(bit_hierarchy_path + generate_configuration_chain_data_out_name(),
+    BasicPort config_data_port(bit_hierarchy_path + generate_configurable_memory_data_out_name(),
                                bitstream_manager.block_bits(config_block_id).size());
 
     /* Wire it to the configuration bit: access both data out and data outb ports */
@@ -239,7 +239,7 @@ void print_verilog_preconfig_top_module_assign_bitstream(std::fstream& fp,
     bit_hierarchy_path += std::string(".");
 
     /* Find the bit index in the parent block */
-    BasicPort config_datab_port(bit_hierarchy_path + generate_configuration_chain_inverted_data_out_name(),
+    BasicPort config_datab_port(bit_hierarchy_path + generate_configurable_memory_inverted_data_out_name(),
                                 bitstream_manager.block_bits(config_block_id).size());
 
     std::vector<size_t> config_datab_values;
@@ -290,10 +290,10 @@ void print_verilog_preconfig_top_module_deposit_bitstream(std::fstream& fp,
     bit_hierarchy_path += std::string(".");
 
     /* Find the bit index in the parent block */
-    BasicPort config_data_port(bit_hierarchy_path + generate_configuration_chain_data_out_name(),
+    BasicPort config_data_port(bit_hierarchy_path + generate_configurable_memory_data_out_name(),
                                bitstream_manager.block_bits(config_block_id).size());
 
-    BasicPort config_datab_port(bit_hierarchy_path + generate_configuration_chain_inverted_data_out_name(),
+    BasicPort config_datab_port(bit_hierarchy_path + generate_configurable_memory_inverted_data_out_name(),
                                bitstream_manager.block_bits(config_block_id).size());
 
     /* Wire it to the configuration bit: access both data out and data outb ports */
diff --git a/openfpga/src/utils/circuit_library_utils.cpp b/openfpga/src/utils/circuit_library_utils.cpp
index 082349008..74d0c1e50 100644
--- a/openfpga/src/utils/circuit_library_utils.cpp
+++ b/openfpga/src/utils/circuit_library_utils.cpp
@@ -143,7 +143,8 @@ size_t find_circuit_num_shared_config_bits(const CircuitLibrary& circuit_lib,
        num_shared_config_bits = std::max((int)num_shared_config_bits, (int)find_rram_circuit_num_shared_config_bits(circuit_lib, sram_model, sram_orgz_type));
        break;
     default:
-      VTR_LOG_ERROR("Invalid design technology for SRAM model!\n");
+      VTR_LOGF_ERROR(__FILE__, __LINE__,
+                     "Invalid design technology for SRAM model!\n");
       exit(1);
     }
   } 
diff --git a/openfpga/src/utils/memory_utils.cpp b/openfpga/src/utils/memory_utils.cpp
index ef0433502..05b6e8736 100644
--- a/openfpga/src/utils/memory_utils.cpp
+++ b/openfpga/src/utils/memory_utils.cpp
@@ -70,8 +70,8 @@ std::map<std::string, BasicPort> generate_cmos_mem_module_port2port_map(const Ba
 
     /* Link the SRAM output ports of the memory module */ 
     VTR_ASSERT( 2 == mem_output_bus_ports.size() );
-    port2port_name_map[generate_configuration_chain_data_out_name()] = mem_output_bus_ports[0];
-    port2port_name_map[generate_configuration_chain_inverted_data_out_name()] = mem_output_bus_ports[1];
+    port2port_name_map[generate_configurable_memory_data_out_name()] = mem_output_bus_ports[0];
+    port2port_name_map[generate_configurable_memory_inverted_data_out_name()] = mem_output_bus_ports[1];
     break;
   }
   case CONFIG_MEM_MEMORY_BANK:
@@ -127,15 +127,16 @@ std::map<std::string, BasicPort> generate_rram_mem_module_port2port_map(const Ba
 
     /* Link the SRAM output ports of the memory module */ 
     VTR_ASSERT( 2 == mem_output_bus_ports.size() );
-    port2port_name_map[generate_configuration_chain_data_out_name()] = mem_output_bus_ports[0];
-    port2port_name_map[generate_configuration_chain_inverted_data_out_name()] = mem_output_bus_ports[1];
+    port2port_name_map[generate_configurable_memory_data_out_name()] = mem_output_bus_ports[0];
+    port2port_name_map[generate_configurable_memory_inverted_data_out_name()] = mem_output_bus_ports[1];
     break;
   }
   case CONFIG_MEM_MEMORY_BANK:
     /* TODO: link BL/WL/Reserved Ports to the inputs of a memory module */
     break;
   default:
-    VTR_LOG_ERROR("Invalid type of SRAM organization!\n");
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid type of SRAM organization!\n");
     exit(1);
   }
 
@@ -342,7 +343,8 @@ std::vector<std::string> generate_sram_port_names(const CircuitLibrary& circuit_
     break;
   }
   default:
-    VTR_LOG_ERROR("Invalid type of SRAM organization !\n");
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid type of SRAM organization !\n");
     exit(1);
   }
 
@@ -378,8 +380,11 @@ size_t generate_sram_port_size(const e_config_protocol_type sram_orgz_type,
     break;
   case CONFIG_MEM_MEMORY_BANK:
     break;
+  case CONFIG_MEM_FRAME_BASED:
+    break;
   default:
-    VTR_LOG_ERROR("Invalid type of SRAM organization !\n");
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid type of SRAM organization!\n");
     exit(1);
   }
 
diff --git a/openfpga/src/utils/module_manager_utils.cpp b/openfpga/src/utils/module_manager_utils.cpp
index 27231aaf3..85e71de3f 100644
--- a/openfpga/src/utils/module_manager_utils.cpp
+++ b/openfpga/src/utils/module_manager_utils.cpp
@@ -234,7 +234,8 @@ void add_sram_ports_to_module_manager(ModuleManager& module_manager,
     break;
   }
   default:
-    VTR_LOG_ERROR("Invalid type of SRAM organization !\n");
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid type of SRAM organization !\n");
     exit(1);
   }
 }
@@ -613,8 +614,8 @@ void add_module_nets_between_logic_and_memory_sram_bus(ModuleManager& module_man
   }
 
   /* Get the SRAM port name of memory model */
-  /* TODO: this should be a constant expression and it should be the same for all the memory module! */
-  std::string memory_model_sram_port_name = generate_configuration_chain_data_out_name();
+  /* This should be a constant expression and it should be the same for all the memory module! */
+  std::string memory_model_sram_port_name = generate_configurable_memory_data_out_name();
   /* Find the corresponding ports in memory module */ 
   ModulePortId mem_module_sram_port_id = module_manager.find_module_port(memory_module, memory_model_sram_port_name);
 
@@ -649,7 +650,7 @@ void add_module_nets_between_logic_and_memory_sram_bus(ModuleManager& module_man
   }
 
   /* Get the SRAM port name of memory model */
-  std::string memory_model_sramb_port_name = generate_configuration_chain_inverted_data_out_name();
+  std::string memory_model_sramb_port_name = generate_configurable_memory_inverted_data_out_name();
   /* Find the corresponding ports in memory module */ 
   ModulePortId mem_module_sramb_port_id = module_manager.find_module_port(memory_module, memory_model_sramb_port_name);
 
@@ -1099,7 +1100,8 @@ void add_module_nets_cmos_memory_config_bus(ModuleManager& module_manager,
     add_module_nets_cmos_memory_frame_config_bus(module_manager, decoder_lib, parent_module);
     break;
   default:
-    VTR_LOG_ERROR("Invalid type of SRAM organization!\n");
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid type of SRAM organization!\n");
     exit(1);
   }
 }
@@ -1174,7 +1176,8 @@ void add_module_nets_memory_config_bus(ModuleManager& module_manager,
     /* TODO: */
     break;
   default:
-    VTR_LOG_ERROR("Invalid type of memory design technology !\n");
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid type of memory design technology!\n");
     exit(1);
   }
 }
@@ -1593,7 +1596,11 @@ void add_module_bus_nets(ModuleManager& module_manager,
 
   if (src_port.get_width() != des_port.get_width()) {
     VTR_LOGF_ERROR(__FILE__, __LINE__,
-                   "Unmatched port size: src_port is %lu while des_port is %lu!\n");
+                   "Unmatched port size: src_port %s is %lu while des_port %s is %lu!\n",
+                   src_port.get_name().c_str(),
+                   src_port.get_width(),
+                   des_port.get_name().c_str(),
+                   des_port.get_width());
     exit(1);
   }
 
diff --git a/openfpga/src/utils/mux_utils.cpp b/openfpga/src/utils/mux_utils.cpp
index b921f0589..15c7a97d7 100644
--- a/openfpga/src/utils/mux_utils.cpp
+++ b/openfpga/src/utils/mux_utils.cpp
@@ -260,6 +260,7 @@ size_t find_cmos_mux_num_config_bits(const CircuitLibrary& circuit_lib,
   case CONFIG_MEM_MEMORY_BANK:
   case CONFIG_MEM_SCAN_CHAIN:
   case CONFIG_MEM_STANDALONE:
+  case CONFIG_MEM_FRAME_BASED:
     num_config_bits = mux_graph.num_memory_bits();
     break;
   default:

From bf9f62f0f7e8e5f21643b6dbc2bbfec73c5bde36 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 28 May 2020 13:09:01 -0600
Subject: [PATCH 575/645] keep bug fixing for frame-based configuration
 protocol.

---
 openfpga/src/fabric/build_grid_modules.cpp   |  2 +-
 openfpga/src/utils/circuit_library_utils.cpp | 25 +++++++++++++++++++-
 openfpga/src/utils/circuit_library_utils.h   |  3 ++-
 3 files changed, 27 insertions(+), 3 deletions(-)

diff --git a/openfpga/src/fabric/build_grid_modules.cpp b/openfpga/src/fabric/build_grid_modules.cpp
index 7a9e3b2b4..ff2fe5d14 100644
--- a/openfpga/src/fabric/build_grid_modules.cpp
+++ b/openfpga/src/fabric/build_grid_modules.cpp
@@ -270,7 +270,7 @@ void build_primitive_block_module(ModuleManager& module_manager,
   }
 
   /* Regular (independent) SRAM ports */
-  size_t num_config_bits = find_circuit_num_config_bits(circuit_lib, primitive_model);
+  size_t num_config_bits = find_circuit_num_config_bits(sram_orgz_type, circuit_lib, primitive_model);
   if (0 < num_config_bits) {
     add_sram_ports_to_module_manager(module_manager, primitive_module,
                                      circuit_lib, sram_model, sram_orgz_type,
diff --git a/openfpga/src/utils/circuit_library_utils.cpp b/openfpga/src/utils/circuit_library_utils.cpp
index 74d0c1e50..07ef140a3 100644
--- a/openfpga/src/utils/circuit_library_utils.cpp
+++ b/openfpga/src/utils/circuit_library_utils.cpp
@@ -12,6 +12,7 @@
 #include "vtr_log.h"
 
 #include "check_circuit_library.h"
+#include "decoder_library_utils.h"
 #include "circuit_library_utils.h"
 
 /* begin namespace openfpga */
@@ -161,7 +162,8 @@ size_t find_circuit_num_shared_config_bits(const CircuitLibrary& circuit_lib,
  * for a multiplexer, because the multiplexer size is determined during 
  * the FPGA architecture generation (NOT during the XML parsing). 
  *******************************************************************/
-size_t find_circuit_num_config_bits(const CircuitLibrary& circuit_lib,
+size_t find_circuit_num_config_bits(const e_config_protocol_type& config_protocol_type,
+                                    const CircuitLibrary& circuit_lib,
                                     const CircuitModelId& circuit_model) {
   size_t num_config_bits = 0;
 
@@ -170,6 +172,27 @@ size_t find_circuit_num_config_bits(const CircuitLibrary& circuit_lib,
     num_config_bits += circuit_lib.port_size(sram_port); 
   } 
 
+  switch (config_protocol_type) {
+  case CONFIG_MEM_STANDALONE: 
+  case CONFIG_MEM_SCAN_CHAIN: 
+  case CONFIG_MEM_MEMORY_BANK: {
+    break;
+  }
+  case CONFIG_MEM_FRAME_BASED: {
+    /* For frame-based configuration protocol
+     * The number of configuration bits is the address size
+     */
+    if (0 < num_config_bits) {
+      num_config_bits = find_mux_local_decoder_addr_size(num_config_bits);
+    }
+    break;
+  }
+  default:
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid type of SRAM organization !\n");
+    exit(1);
+  }
+
   return num_config_bits;
 }
 
diff --git a/openfpga/src/utils/circuit_library_utils.h b/openfpga/src/utils/circuit_library_utils.h
index b03c03156..255da4f4f 100644
--- a/openfpga/src/utils/circuit_library_utils.h
+++ b/openfpga/src/utils/circuit_library_utils.h
@@ -31,7 +31,8 @@ size_t find_circuit_num_shared_config_bits(const CircuitLibrary& circuit_lib,
                                            const CircuitModelId& circuit_model,
                                            const e_config_protocol_type& sram_orgz_type);
 
-size_t find_circuit_num_config_bits(const CircuitLibrary& circuit_lib,
+size_t find_circuit_num_config_bits(const e_config_protocol_type& config_protocol_type,
+                                    const CircuitLibrary& circuit_lib,
                                     const CircuitModelId& circuit_model);
 
 std::vector<CircuitPortId> find_circuit_library_global_ports(const CircuitLibrary& circuit_lib);

From 8298bbff78cad19f399dab4e052af9820acc25e0 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 28 May 2020 16:55:13 -0600
Subject: [PATCH 576/645] bug fixed in the fabric bitstream for frame-based
 configurable memories.

---
 openfpga/src/fabric/build_memory_modules.cpp  |  4 +
 .../fpga_bitstream/build_fabric_bitstream.cpp | 89 +++++++++++++++++--
 openfpga/src/utils/module_manager_utils.cpp   | 13 +--
 3 files changed, 92 insertions(+), 14 deletions(-)

diff --git a/openfpga/src/fabric/build_memory_modules.cpp b/openfpga/src/fabric/build_memory_modules.cpp
index 58ddd6de6..bc04dd07d 100644
--- a/openfpga/src/fabric/build_memory_modules.cpp
+++ b/openfpga/src/fabric/build_memory_modules.cpp
@@ -701,6 +701,7 @@ void build_frame_memory_module(ModuleManager& module_manager,
     /* Memory seed module instanciation */
     size_t sram_instance = module_manager.num_instance(mem_module, sram_mem_module);
     module_manager.add_child_module(mem_module, sram_mem_module);
+    module_manager.add_configurable_child(mem_module, sram_mem_module, sram_instance);
 
     /* Wire data_in port to SRAM BL port */
     ModulePortId sram_bl_port = module_manager.find_module_port(sram_mem_module, circuit_lib.port_lib_name(sram_bl_ports[0]));
@@ -747,6 +748,9 @@ void build_frame_memory_module(ModuleManager& module_manager,
    * we just need to find all the global ports from the child modules and build a list of it
    */
   add_module_global_ports_from_child_modules(module_manager, mem_module);
+
+  /* Add the decoder as the last configurable children */
+  module_manager.add_configurable_child(mem_module, decoder_module, 0);
 }
 
 /*********************************************************************
diff --git a/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp b/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp
index 4dc8ee70b..f281a72dc 100644
--- a/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp
+++ b/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp
@@ -79,7 +79,7 @@ void rec_build_module_fabric_dependent_chain_bitstream(const BitstreamManager& b
  * in a recursive way, following a Depth-First Search (DFS) strategy
  * For each configuration child, we use its instance name as a key to spot the 
  * configuration bits in bitstream manager.
- * Note that it is guarentee that the instance name in module manager is 
+ * Note that it is guarenteed that the instance name in module manager is 
  * consistent with the block names in bitstream manager
  * We use this link to reorganize the bitstream in the sequence of memories as we stored
  * in the configurable_children() and configurable_child_instances() of each module of module manager 
@@ -112,16 +112,21 @@ void rec_build_module_fabric_dependent_frame_bitstream(const BitstreamManager& b
     const ModuleId& parent_module = parent_modules.back();
 
     size_t num_configurable_children = module_manager.configurable_children(parent_modules.back()).size();
-
+ 
+    size_t max_child_addr_code_size = 0;
     bool add_addr_code = true;
     ModuleId decoder_module = ModuleId::INVALID();
 
     /* Early exit if there is no configurable children */
     if (0 == num_configurable_children) {
+      /* Ensure that there should be no configuration bits in the parent block */
+      VTR_ASSERT(0 == bitstream_manager.block_bits(parent_block).size());
       return;
     }
 
-    /* For only 1 configurable child, there is not frame decoder need, we can pass on addr code directly */
+    /* For only 1 configurable child,
+     * there is no frame decoder here, we can pass on addr code directly
+     */
     if (1 == num_configurable_children) {
       add_addr_code = false;
     } else {
@@ -132,10 +137,18 @@ void rec_build_module_fabric_dependent_frame_bitstream(const BitstreamManager& b
       VTR_ASSERT(2 < num_configurable_children);
       num_configurable_children--;
       decoder_module = module_manager.configurable_children(parent_module).back();
+
+      /* The address code size is the max. of address port of all the configurable children */
+      for (size_t child_id = 0; child_id < num_configurable_children; ++child_id) {
+        ModuleId child_module = module_manager.configurable_children(parent_module)[child_id]; 
+        const ModulePortId& child_addr_port_id = module_manager.find_module_port(child_module, std::string(DECODER_ADDRESS_PORT_NAME));
+        const BasicPort& child_addr_port = module_manager.module_port(child_module, child_addr_port_id);
+        max_child_addr_code_size = std::max((int)child_addr_port.get_width(), (int)max_child_addr_code_size);
+      } 
     }
 
     for (size_t child_id = 0; child_id < num_configurable_children; ++child_id) {
-      ModuleId child_module = module_manager.configurable_children(parent_modules.back())[child_id]; 
+      ModuleId child_module = module_manager.configurable_children(parent_module)[child_id]; 
       size_t child_instance = module_manager.configurable_child_instances(parent_module)[child_id]; 
       /* Get the instance name and ensure it is not empty */
       std::string instance_name = module_manager.instance_name(parent_module, child_module, child_instance);
@@ -161,7 +174,46 @@ void rec_build_module_fabric_dependent_frame_bitstream(const BitstreamManager& b
         const ModulePortId& decoder_addr_port_id = module_manager.find_module_port(decoder_module, std::string(DECODER_ADDRESS_PORT_NAME));
         const BasicPort& decoder_addr_port = module_manager.module_port(decoder_module, decoder_addr_port_id);
         std::vector<size_t> addr_bits_vec = itobin_vec(child_id, decoder_addr_port.get_width());
-        child_addr_code.insert(child_addr_code.end(), addr_bits_vec.begin(), addr_bits_vec.end());
+
+        child_addr_code.insert(child_addr_code.begin(), addr_bits_vec.begin(), addr_bits_vec.end());
+
+        /* Note that the address port size of the child module may be smaller than the maximum
+         * of other child modules at this level.
+         * We will add dummy '0's to the head of addr_bit_vec.
+         *
+         * For example:
+         *  Decoder is the decoder to access all the child modules
+         *  whose address is decoded by the addr_bits_vec
+         *  The child modules may use part of the address lines,
+         *  we should add dummy '0' to fill the gap
+         *
+         *  Addr_code for child[0]: '000' + addr_bits_vec
+         *  Addr_code for child[1]: '0'  + addr_bits_vec 
+         *  Addr_code for child[2]: addr_bits_vec 
+         *
+         *                   Addr[6:8]
+         *                     |
+         *                     v
+         *  +-------------------------------------------+
+         *  |            Decoder Module                 |
+         *  +-------------------------------------------+
+         *   
+         *     Addr[0:2]       Addr[0:4]        Addr[0:5]
+         *        |                |               |
+         *        v                v               v
+         * +-----------+  +-------------+  +------------+
+         * | Child[0]  |  |  Child[1]   |  |  Child[2]  |
+         * +-----------+  +-------------+  +------------+
+         *
+         * Child[2] has the maximum address lines among the children
+         *
+         */
+        const ModulePortId& child_addr_port_id = module_manager.find_module_port(child_module, std::string(DECODER_ADDRESS_PORT_NAME));
+        const BasicPort& child_addr_port = module_manager.module_port(child_module, child_addr_port_id);
+        if (0 < max_child_addr_code_size - child_addr_port.get_width()) {
+          std::vector<size_t> dummy_codes(max_child_addr_code_size - child_addr_port.get_width(), 0);
+          child_addr_code.insert(child_addr_code.begin(), dummy_codes.begin(), dummy_codes.end());
+        }
       }
 
       /* Go recursively */
@@ -172,17 +224,36 @@ void rec_build_module_fabric_dependent_frame_bitstream(const BitstreamManager& b
     }
     /* Ensure that there should be no configuration bits in the parent block */
     VTR_ASSERT(0 == bitstream_manager.block_bits(parent_block).size());
+   
+    return;
   }
 
   /* Note that, reach here, it means that this is a leaf node. 
-   * We add the configuration bits to the fabric_bitstream,
-   * And then, we can return
+   * A leaf node (a memory module) always has a decoder inside
+   * which is the last of configurable children.
+   * We will find the address bit and add it to addr_code
+   * Then we can add the configuration bits to the fabric_bitstream.
    */
-  for (const ConfigBitId& config_bit : bitstream_manager.block_bits(parent_blocks.back())) {
+  if (!(1 < module_manager.configurable_children(parent_modules.back()).size()))
+  VTR_ASSERT(1 < module_manager.configurable_children(parent_modules.back()).size());
+  ModuleId decoder_module = module_manager.configurable_children(parent_modules.back()).back();
+  /* Find the address port from the decoder module */
+  const ModulePortId& decoder_addr_port_id = module_manager.find_module_port(decoder_module, std::string(DECODER_ADDRESS_PORT_NAME));
+  const BasicPort& decoder_addr_port = module_manager.module_port(decoder_module, decoder_addr_port_id);
+
+  for (size_t ibit = 0; ibit < bitstream_manager.block_bits(parent_blocks.back()).size(); ++ibit) {
+    
+    ConfigBitId config_bit = bitstream_manager.block_bits(parent_blocks.back())[ibit];
+    std::vector<size_t> addr_bits_vec = itobin_vec(ibit, decoder_addr_port.get_width());
+
+    std::vector<size_t> child_addr_code = addr_code;
+
+    child_addr_code.insert(child_addr_code.begin(), addr_bits_vec.begin(), addr_bits_vec.end());
+
     const FabricBitId& fabric_bit = fabric_bitstream.add_bit(config_bit);
 
     /* Set address */
-    fabric_bitstream.set_bit_address(fabric_bit, addr_code);
+    fabric_bitstream.set_bit_address(fabric_bit, child_addr_code);
     
     /* Set data input */
     fabric_bitstream.set_bit_din(fabric_bit, bitstream_manager.bit_value(config_bit));
diff --git a/openfpga/src/utils/module_manager_utils.cpp b/openfpga/src/utils/module_manager_utils.cpp
index 85e71de3f..eebe9008a 100644
--- a/openfpga/src/utils/module_manager_utils.cpp
+++ b/openfpga/src/utils/module_manager_utils.cpp
@@ -941,7 +941,8 @@ void add_module_nets_cmos_memory_frame_decoder_config_bus(ModuleManager& module_
    * Note that we only connect to the last few bits of address port
    */
   for (size_t mem_index = 0; mem_index < configurable_children.size(); ++mem_index) {
-    ModuleId child_module = module_manager.configurable_children(parent_module)[mem_index]; 
+    ModuleId child_module = configurable_children[mem_index]; 
+    size_t child_instance = module_manager.configurable_child_instances(parent_module)[mem_index];
     ModulePortId child_addr_port = module_manager.find_module_port(child_module, std::string(DECODER_ADDRESS_PORT_NAME));
     BasicPort child_addr_port_info = module_manager.module_port(child_module, child_addr_port);
     for (size_t ipin = 0; ipin < child_addr_port_info.get_width(); ++ipin) {
@@ -959,7 +960,7 @@ void add_module_nets_cmos_memory_frame_decoder_config_bus(ModuleManager& module_
       }
       /* Configure the net sink */
       module_manager.add_module_net_sink(parent_module, net,
-                                         child_module, 0,
+                                         child_module, child_instance,
                                          child_addr_port,
                                          child_addr_port_info.get_lsb() + ipin);
     }
@@ -969,12 +970,13 @@ void add_module_nets_cmos_memory_frame_decoder_config_bus(ModuleManager& module_
    * the memory modules
    */
   ModulePortId parent_din_port = module_manager.find_module_port(parent_module, std::string(DECODER_DATA_IN_PORT_NAME));
-  for (size_t mem_index = 0; mem_index < module_manager.configurable_children(parent_module).size(); ++mem_index) {
+  for (size_t mem_index = 0; mem_index < configurable_children.size(); ++mem_index) {
     ModuleId child_module = configurable_children[mem_index]; 
+    size_t child_instance = module_manager.configurable_child_instances(parent_module)[mem_index];
     ModulePortId child_din_port = module_manager.find_module_port(child_module, std::string(DECODER_DATA_IN_PORT_NAME));
     add_module_bus_nets(module_manager, parent_module,
                         parent_module, 0, parent_din_port,
-                        child_module, 0, child_din_port);
+                        child_module, child_instance, child_din_port);
   }
 
   /* Connect the data_out port of the decoder module 
@@ -985,6 +987,7 @@ void add_module_nets_cmos_memory_frame_decoder_config_bus(ModuleManager& module_
   VTR_ASSERT(decoder_dout_port_info.get_width() == configurable_children.size());
   for (size_t mem_index = 0; mem_index < configurable_children.size(); ++mem_index) {
     ModuleId child_module = configurable_children[mem_index]; 
+    size_t child_instance = module_manager.configurable_child_instances(parent_module)[mem_index];
     ModulePortId child_en_port = module_manager.find_module_port(child_module, std::string(DECODER_ENABLE_PORT_NAME));
     BasicPort child_en_port_info = module_manager.module_port(child_module, child_en_port);
     for (size_t ipin = 0; ipin < child_en_port_info.get_width(); ++ipin) {
@@ -1002,7 +1005,7 @@ void add_module_nets_cmos_memory_frame_decoder_config_bus(ModuleManager& module_
       }
       /* Configure the net sink */
       module_manager.add_module_net_sink(parent_module, net,
-                                         child_module, 0,
+                                         child_module, child_instance,
                                          child_en_port,
                                          child_en_port_info.pins()[ipin]);
     }

From 1e73fd6def99fc5def3011a31fd13509c685607a Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 28 May 2020 16:57:04 -0600
Subject: [PATCH 577/645] create configuration frame example script

---
 ...onfiguration_frame_example_script.openfpga | 68 +++++++++++++++++++
 .../configuration_frame/config/task.conf      |  2 +-
 2 files changed, 69 insertions(+), 1 deletion(-)
 create mode 100644 openfpga_flow/OpenFPGAShellScripts/configuration_frame_example_script.openfpga

diff --git a/openfpga_flow/OpenFPGAShellScripts/configuration_frame_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/configuration_frame_example_script.openfpga
new file mode 100644
index 000000000..bcc8d36e3
--- /dev/null
+++ b/openfpga_flow/OpenFPGAShellScripts/configuration_frame_example_script.openfpga
@@ -0,0 +1,68 @@
+# Run VPR for the 'and' design
+#--write_rr_graph example_rr_graph.xml
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
+
+# Annotate the OpenFPGA architecture to VPR data base
+# to debug use --verbose options
+link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to clustering nets based on routing results
+pb_pin_fixup --verbose
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup
+
+# Build the module graph
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules
+build_fabric --compress_routing #--verbose
+
+# Write the fabric hierarchy of module graph to a file
+# This is used by hierarchical PnR flows
+write_fabric_hierarchy --file ./fabric_hierarchy.txt
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --file fabric_indepenent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here
+write_pnr_sdc --file ./SDC
+
+# Write SDC to disable timing for configure ports
+write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+write_analysis_sdc --file ./SDC_analysis
+
+# Finish and exit OpenFPGA
+exit
+
+# Note :
+# To run verification at the end of the flow maintain source in ./SRC directory
diff --git a/openfpga_flow/tasks/openfpga_shell/configuration_frame/config/task.conf b/openfpga_flow/tasks/openfpga_shell/configuration_frame/config/task.conf
index 87c487f63..7a448e3e8 100644
--- a/openfpga_flow/tasks/openfpga_shell/configuration_frame/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/configuration_frame/config/task.conf
@@ -8,7 +8,7 @@
 
 [GENERAL]
 run_engine=openfpga_shell
-openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/configuration_frame_example_script.openfpga
 power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
 power_analysis = true
 spice_output=false

From 8aa665b3b2856e1dddf9a6fa430c30486b52b7f5 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 28 May 2020 17:46:14 -0600
Subject: [PATCH 578/645] bug fix in the Verilog codes for frame decoders

---
 openfpga/src/fpga_verilog/verilog_decoders.cpp | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/openfpga/src/fpga_verilog/verilog_decoders.cpp b/openfpga/src/fpga_verilog/verilog_decoders.cpp
index 66a1a8ed8..9a37ba46b 100644
--- a/openfpga/src/fpga_verilog/verilog_decoders.cpp
+++ b/openfpga/src/fpga_verilog/verilog_decoders.cpp
@@ -330,8 +330,8 @@ void print_verilog_arch_decoder_module(std::fstream& fp,
    * The rest of addr codes 3'b110, 3'b111 will be decoded to data=8'b0_0000;
    */
 
-  fp << "\t" << "always@(" << generate_verilog_port(VERILOG_PORT_CONKT, addr_port) << ")" << std::endl;
-  fp << "\tif (" << generate_verilog_port(VERILOG_PORT_CONKT, enable_port) << "1'b1) begin" << std::endl;
+  fp << "always@(" << generate_verilog_port(VERILOG_PORT_CONKT, addr_port) << ") begin" << std::endl;
+  fp << "\tif (" << generate_verilog_port(VERILOG_PORT_CONKT, enable_port) << " == 1'b1) begin" << std::endl;
   fp << "\t\t" << "case (" << generate_verilog_port(VERILOG_PORT_CONKT, addr_port) << ")" << std::endl;
   /* Create a string for addr and data */
   for (size_t i = 0; i < data_size; ++i) {
@@ -340,11 +340,19 @@ void print_verilog_arch_decoder_module(std::fstream& fp,
     fp << generate_verilog_port_constant_values(data_port, ito1hot_vec(i, data_size)); 
     fp << ";" << std::endl;
   }
+  /* Different from the MUX encoders, architecture decoders will output all-zero by default!!! */
   fp << "\t\t\t" << "default : ";
-  fp << generate_verilog_port_constant_values(data_port, ito1hot_vec(data_size - 1, data_size)); 
+  fp << generate_verilog_port_constant_values(data_port, ito1hot_vec(data_size, data_size)); 
   fp << ";" << std::endl;
   fp << "\t\t" << "endcase" << std::endl;
   fp << "\t" << "end" << std::endl;
+  
+  /* If not enabled, we output all-zero */
+  fp << "\t" << "else begin" << std::endl;
+  fp << "\t\t" << generate_verilog_port_constant_values(data_port, ito1hot_vec(data_size, data_size)) << ";"<< std::endl; 
+  fp << "\t" << "end" << std::endl;
+
+  fp << "end" << std::endl;
 
   if (true == decoder_lib.use_data_inv_port(decoder)) {
     print_verilog_wire_connection(fp, data_inv_port, data_port, true);

From f5968fda52ea31f21026f2d9c32bfb0f1709e1a7 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 28 May 2020 18:13:06 -0600
Subject: [PATCH 579/645] add configurable latch Verilog codes

---
 openfpga_flow/VerilogNetlists/config_latch.v | 38 ++++++++++++++++++++
 1 file changed, 38 insertions(+)
 create mode 100644 openfpga_flow/VerilogNetlists/config_latch.v

diff --git a/openfpga_flow/VerilogNetlists/config_latch.v b/openfpga_flow/VerilogNetlists/config_latch.v
new file mode 100644
index 000000000..6cbe5657e
--- /dev/null
+++ b/openfpga_flow/VerilogNetlists/config_latch.v
@@ -0,0 +1,38 @@
+//-----------------------------------------------------
+// Design Name : config_latch
+// File Name   : config_latch.v
+// Function    : A Configurable Latch where data storage
+//               can be updated at rising clock edge 
+//               when wl is enabled
+// Coder       : Xifan TANG
+//-----------------------------------------------------
+module config_latch (
+  input reset, // Reset input
+  input clk, // Clock Input
+  input wl, // Data Enable
+  input bl, // Data Input
+  output Q, // Q output
+  output Qb // Q output
+);
+//------------Internal Variables--------
+reg q_reg;
+
+//-------------Code Starts Here---------
+always @ ( posedge clk or posedge reset) begin
+  if (reset) begin
+    q_reg <= 1'b0;
+  end else if (1'b1 == wl) begin
+    q_reg <= bl;
+  end
+end
+
+`ifndef ENABLE_FORMAL_VERIFICATION
+// Wire q_reg to Q
+assign Q = q_reg;
+assign Qb = ~q_reg;
+`else
+assign Q = 1'bZ;
+assign Qb = !Q;
+`endif
+
+endmodule

From 6a72c66eb8e610bbc300590a35bc8496a0d3c47b Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 28 May 2020 18:22:27 -0600
Subject: [PATCH 580/645] bug fixed for frame-based configuration memory in
 top-level full testbench

---
 openfpga/src/fpga_verilog/verilog_decoders.cpp            | 5 +++++
 openfpga/src/fpga_verilog/verilog_top_testbench.cpp       | 3 ++-
 openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml | 6 +++---
 3 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/openfpga/src/fpga_verilog/verilog_decoders.cpp b/openfpga/src/fpga_verilog/verilog_decoders.cpp
index 9a37ba46b..70b65ee61 100644
--- a/openfpga/src/fpga_verilog/verilog_decoders.cpp
+++ b/openfpga/src/fpga_verilog/verilog_decoders.cpp
@@ -299,7 +299,12 @@ void print_verilog_arch_decoder_module(std::fstream& fp,
    * data_inv = ~data_inv
    */
   if (1 == data_size) {
+    fp << "always@(" << generate_verilog_port(VERILOG_PORT_CONKT, addr_port) << ") begin" << std::endl;
+    fp << "\tif (" << generate_verilog_port(VERILOG_PORT_CONKT, enable_port) << " == 1'b1) begin" << std::endl;
+    fp << "\t";
     print_verilog_wire_connection(fp, data_port, addr_port, false);
+    fp << "\t" << "end" << std::endl;
+    fp << "end" << std::endl;
 
     /* Depend on if the inverted data output port is needed or not */
     if (true == decoder_lib.use_data_inv_port(decoder)) {
diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
index 9041df361..5a5d98aed 100644
--- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
@@ -102,7 +102,7 @@ void print_verilog_top_testbench_frame_decoder_port(std::fstream& fp,
   ModulePortId din_port_id = module_manager.find_module_port(top_module,
                                                              std::string(DECODER_DATA_IN_PORT_NAME));
   BasicPort din_port = module_manager.module_port(top_module, din_port_id);
-  fp << generate_verilog_port(VERILOG_PORT_WIRE, din_port) << ";" << std::endl;
+  fp << generate_verilog_port(VERILOG_PORT_REG, din_port) << ";" << std::endl;
 
   /* Wire the programming clock to the enable signal */
   print_verilog_comment(fp, std::string("---- Wire enable port of frame-based decoder to programming clock -----"));
@@ -111,6 +111,7 @@ void print_verilog_top_testbench_frame_decoder_port(std::fstream& fp,
   BasicPort en_port = module_manager.module_port(top_module, en_port_id);
   BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME), 1);
 
+  fp << generate_verilog_port(VERILOG_PORT_WIRE, en_port) << ";" << std::endl;
   print_verilog_wire_connection(fp, en_port, prog_clock_port, false);
 }
 
diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml
index e5fe5a89b..a0e0194b5 100644
--- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml
@@ -142,7 +142,7 @@
       <port type="sram" prefix="sram" size="16"/>
     </circuit_model>
     <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
-    <circuit_model type="sram" name="config_mem" prefix="config_mem" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/sram.v">
+    <circuit_model type="sram" name="config_latch" prefix="config_latch" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/config_latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/config_latch.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
@@ -158,13 +158,13 @@
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
       <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
-      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="config_mem" default_val="1"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="config_latch" default_val="1"/>
       <port type="input" prefix="outpad" size="1"/>
       <port type="output" prefix="inpad" size="1"/>
     </circuit_model>
   </circuit_library>
   <configuration_protocol>
-    <organization type="frame_based" circuit_model_name="config_mem"/>
+    <organization type="frame_based" circuit_model_name="config_latch"/>
   </configuration_protocol>
   <connection_block>
     <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>

From 986956e47468c2213912a3886ed2879b69ac141e Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 28 May 2020 18:29:22 -0600
Subject: [PATCH 581/645] bug fix for arch decoder Verilog codes. Now Modelsim
 compiles ok.

---
 openfpga/src/fpga_verilog/verilog_decoders.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/openfpga/src/fpga_verilog/verilog_decoders.cpp b/openfpga/src/fpga_verilog/verilog_decoders.cpp
index 70b65ee61..2637736ea 100644
--- a/openfpga/src/fpga_verilog/verilog_decoders.cpp
+++ b/openfpga/src/fpga_verilog/verilog_decoders.cpp
@@ -301,8 +301,8 @@ void print_verilog_arch_decoder_module(std::fstream& fp,
   if (1 == data_size) {
     fp << "always@(" << generate_verilog_port(VERILOG_PORT_CONKT, addr_port) << ") begin" << std::endl;
     fp << "\tif (" << generate_verilog_port(VERILOG_PORT_CONKT, enable_port) << " == 1'b1) begin" << std::endl;
-    fp << "\t";
-    print_verilog_wire_connection(fp, data_port, addr_port, false);
+    fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, data_port);
+    fp << " = " << generate_verilog_port(VERILOG_PORT_CONKT, addr_port) << ";" << std::endl;
     fp << "\t" << "end" << std::endl;
     fp << "end" << std::endl;
 

From bdc9efb38fe15dd4711b78ad15b86945d002e6c1 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 28 May 2020 18:34:18 -0600
Subject: [PATCH 582/645] bug fix in top-level testbench for frame-based
 decoders

---
 openfpga/src/fpga_verilog/verilog_top_testbench.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
index 5a5d98aed..26ce99b92 100644
--- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
@@ -598,7 +598,7 @@ void print_verilog_top_testbench_load_bitstream_task_frame_decoder(std::fstream&
   /* Add an empty line as splitter */
   fp << std::endl;
 
-  /* Feed the address and data input at each rising edge of programming clock 
+  /* Feed the address and data input at each falling edge of programming clock 
    * As the enable signal is wired to the programming clock, we should synchronize
    * address and data with the enable signal
    */
@@ -607,7 +607,7 @@ void print_verilog_top_testbench_load_bitstream_task_frame_decoder(std::fstream&
   fp << generate_verilog_port(VERILOG_PORT_INPUT, addr_value) << ";" << std::endl;
   fp << generate_verilog_port(VERILOG_PORT_INPUT, din_value) << ";" << std::endl;
   fp << "\tbegin" << std::endl;
-  fp << "\t\t@(posedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ");" << std::endl;
+  fp << "\t\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ");" << std::endl;
 
   fp << "\t\t\t"; 
   fp << generate_verilog_port(VERILOG_PORT_CONKT, addr_port);

From b8c449d520931882b5771bcf29d5ddbbc29e7a6f Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 28 May 2020 18:46:47 -0600
Subject: [PATCH 583/645] add comments for decoding functions to help debugging
 the frame-based decoders

---
 .../libopenfpgautil/src/openfpga_decode.cpp   | 21 +++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/libopenfpga/libopenfpgautil/src/openfpga_decode.cpp b/libopenfpga/libopenfpgautil/src/openfpga_decode.cpp
index 9839f13b9..06b3487b0 100644
--- a/libopenfpga/libopenfpgautil/src/openfpga_decode.cpp
+++ b/libopenfpga/libopenfpgautil/src/openfpga_decode.cpp
@@ -14,6 +14,21 @@ namespace openfpga {
 
 /******************************************************************** 
  * Convert an integer to an one-hot encoding integer array
+ * For example: 
+ *   Input integer: 3
+ *   Binary length : 4
+ *   Output:
+ *     index | 0 | 1 | 2 | 3
+ *     ret   | 0 | 0 | 0 | 1
+ *
+ * If you need all zero code, set the input integer same as the binary length
+ * For example: 
+ *   Input integer: 4
+ *   Binary length : 4
+ *   Output:
+ *     index | 0 | 1 | 2 | 3
+ *     ret   | 0 | 0 | 0 | 0
+ *           
  ********************************************************************/
 std::vector<size_t> ito1hot_vec(const size_t& in_int,
                                 const size_t& bin_len) {
@@ -33,6 +48,12 @@ std::vector<size_t> ito1hot_vec(const size_t& in_int,
 
 /******************************************************************** 
  * Converter an integer to a binary vector 
+ * For example: 
+ *   Input integer: 4
+ *   Binary length : 3
+ *   Output:
+ *     index | 0 | 1 | 2
+ *     ret   | 0 | 0 | 1 
  ********************************************************************/
 std::vector<size_t> itobin_vec(const size_t& in_int,
                                const size_t& bin_len) {

From 31c9a011dd8b7a13d019e53409c1a678acd0f5c8 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 28 May 2020 21:24:41 -0600
Subject: [PATCH 584/645] keep bug fixing for arch decoders

---
 .../src/fpga_verilog/verilog_decoders.cpp     | 30 ++++++++++++-------
 1 file changed, 19 insertions(+), 11 deletions(-)

diff --git a/openfpga/src/fpga_verilog/verilog_decoders.cpp b/openfpga/src/fpga_verilog/verilog_decoders.cpp
index 2637736ea..64568515c 100644
--- a/openfpga/src/fpga_verilog/verilog_decoders.cpp
+++ b/openfpga/src/fpga_verilog/verilog_decoders.cpp
@@ -299,10 +299,13 @@ void print_verilog_arch_decoder_module(std::fstream& fp,
    * data_inv = ~data_inv
    */
   if (1 == data_size) {
-    fp << "always@(" << generate_verilog_port(VERILOG_PORT_CONKT, addr_port) << ") begin" << std::endl;
+    fp << "always@(" << generate_verilog_port(VERILOG_PORT_CONKT, addr_port);
+    fp << " or " << generate_verilog_port(VERILOG_PORT_CONKT, enable_port);
+    fp << ") begin" << std::endl;
     fp << "\tif (" << generate_verilog_port(VERILOG_PORT_CONKT, enable_port) << " == 1'b1) begin" << std::endl;
-    fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, data_port);
-    fp << " = " << generate_verilog_port(VERILOG_PORT_CONKT, addr_port) << ";" << std::endl;
+    fp << "\t\t" << generate_verilog_port_constant_values(data_port, std::vector<size_t>(1, 1)) << ";" << std::endl; 
+    fp << "\t" << "end else begin" << std::endl;
+    fp << "\t\t" << generate_verilog_port_constant_values(data_port, std::vector<size_t>(1, 0)) << ";" << std::endl; 
     fp << "\t" << "end" << std::endl;
     fp << "end" << std::endl;
 
@@ -335,7 +338,9 @@ void print_verilog_arch_decoder_module(std::fstream& fp,
    * The rest of addr codes 3'b110, 3'b111 will be decoded to data=8'b0_0000;
    */
 
-  fp << "always@(" << generate_verilog_port(VERILOG_PORT_CONKT, addr_port) << ") begin" << std::endl;
+  fp << "always@(" << generate_verilog_port(VERILOG_PORT_CONKT, addr_port);
+  fp << " or " << generate_verilog_port(VERILOG_PORT_CONKT, enable_port);
+  fp << ") begin" << std::endl;
   fp << "\tif (" << generate_verilog_port(VERILOG_PORT_CONKT, enable_port) << " == 1'b1) begin" << std::endl;
   fp << "\t\t" << "case (" << generate_verilog_port(VERILOG_PORT_CONKT, addr_port) << ")" << std::endl;
   /* Create a string for addr and data */
@@ -345,18 +350,21 @@ void print_verilog_arch_decoder_module(std::fstream& fp,
     fp << generate_verilog_port_constant_values(data_port, ito1hot_vec(i, data_size)); 
     fp << ";" << std::endl;
   }
-  /* Different from the MUX encoders, architecture decoders will output all-zero by default!!! */
-  fp << "\t\t\t" << "default : ";
+  /* Different from MUX decoder, we assign default values which is all zero */
+  fp << "\t\t\t" << "default"; 
+  fp << " : ";
   fp << generate_verilog_port_constant_values(data_port, ito1hot_vec(data_size, data_size)); 
   fp << ";" << std::endl;
+
   fp << "\t\t" << "endcase" << std::endl;
   fp << "\t" << "end" << std::endl;
-  
-  /* If not enabled, we output all-zero */
-  fp << "\t" << "else begin" << std::endl;
-  fp << "\t\t" << generate_verilog_port_constant_values(data_port, ito1hot_vec(data_size, data_size)) << ";"<< std::endl; 
-  fp << "\t" << "end" << std::endl;
 
+  /* If enable is not active, we should give all zero */
+  fp << "\t" << "else begin" << std::endl;
+  fp << "\t\t" << generate_verilog_port_constant_values(data_port, ito1hot_vec(data_size, data_size)); 
+  fp << ";" << std::endl;
+  fp << "\t" << "end" << std::endl;
+  
   fp << "end" << std::endl;
 
   if (true == decoder_lib.use_data_inv_port(decoder)) {

From 583c15131bfa991c73d327aa90d982b49869601f Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 28 May 2020 21:33:44 -0600
Subject: [PATCH 585/645] change configuration latch to be triggered at
 negative edge; Frame-based fabric passed Modelsim verification but failed in
 iVerilog

---
 openfpga_flow/VerilogNetlists/config_latch.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/openfpga_flow/VerilogNetlists/config_latch.v b/openfpga_flow/VerilogNetlists/config_latch.v
index 6cbe5657e..e177fe2e7 100644
--- a/openfpga_flow/VerilogNetlists/config_latch.v
+++ b/openfpga_flow/VerilogNetlists/config_latch.v
@@ -18,7 +18,7 @@ module config_latch (
 reg q_reg;
 
 //-------------Code Starts Here---------
-always @ ( posedge clk or posedge reset) begin
+always @ ( negedge clk or posedge reset) begin
   if (reset) begin
     q_reg <= 1'b0;
   end else if (1'b1 == wl) begin

From b5e5182f524713c6c6c7f1172ca1b1561c092ebb Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 28 May 2020 23:05:24 -0600
Subject: [PATCH 586/645] frame-based configuration protocol is working on k4n4
 arch now. Spot bugs in iVerilog about negedge flip-flops

---
 .../fpga_verilog/verilog_top_testbench.cpp    | 25 ++++++++++++++-----
 openfpga_flow/VerilogNetlists/config_latch.v  |  2 +-
 2 files changed, 20 insertions(+), 7 deletions(-)

diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
index 26ce99b92..91e5eb8cf 100644
--- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
@@ -104,15 +104,15 @@ void print_verilog_top_testbench_frame_decoder_port(std::fstream& fp,
   BasicPort din_port = module_manager.module_port(top_module, din_port_id);
   fp << generate_verilog_port(VERILOG_PORT_REG, din_port) << ";" << std::endl;
 
-  /* Wire the programming clock to the enable signal */
-  print_verilog_comment(fp, std::string("---- Wire enable port of frame-based decoder to programming clock -----"));
+  /* Wire the INVERTED programming clock to the enable signal !!! */
+  print_verilog_comment(fp, std::string("---- Wire enable port of frame-based decoder to inverted programming clock -----"));
   ModulePortId en_port_id = module_manager.find_module_port(top_module,
                                                             std::string(DECODER_ENABLE_PORT_NAME));
   BasicPort en_port = module_manager.module_port(top_module, en_port_id);
   BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME), 1);
 
   fp << generate_verilog_port(VERILOG_PORT_WIRE, en_port) << ";" << std::endl;
-  print_verilog_wire_connection(fp, en_port, prog_clock_port, false);
+  print_verilog_wire_connection(fp, en_port, prog_clock_port, true);
 }
 
 /********************************************************************
@@ -581,7 +581,9 @@ void print_verilog_top_testbench_load_bitstream_task_frame_decoder(std::fstream&
   /* Validate the file stream */
   valid_file_stream(fp);
 
-  BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME), 1);
+  ModulePortId en_port_id = module_manager.find_module_port(top_module,
+                                                            std::string(DECODER_ENABLE_PORT_NAME));
+  BasicPort en_port = module_manager.module_port(top_module, en_port_id);
 
   ModulePortId addr_port_id = module_manager.find_module_port(top_module,
                                                               std::string(DECODER_ADDRESS_PORT_NAME));
@@ -602,12 +604,12 @@ void print_verilog_top_testbench_load_bitstream_task_frame_decoder(std::fstream&
    * As the enable signal is wired to the programming clock, we should synchronize
    * address and data with the enable signal
    */
-  print_verilog_comment(fp, std::string("----- Task: address and data values during a programming clock cycle -----"));
+  print_verilog_comment(fp, std::string("----- Task: assign address and data values at rising edge of enable signal -----"));
   fp << "task " << std::string(TOP_TESTBENCH_PROG_TASK_NAME) << ";" << std::endl;
   fp << generate_verilog_port(VERILOG_PORT_INPUT, addr_value) << ";" << std::endl;
   fp << generate_verilog_port(VERILOG_PORT_INPUT, din_value) << ";" << std::endl;
   fp << "\tbegin" << std::endl;
-  fp << "\t\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ");" << std::endl;
+  fp << "\t\t@(posedge " << generate_verilog_port(VERILOG_PORT_CONKT, en_port) << ");" << std::endl;
 
   fp << "\t\t\t"; 
   fp << generate_verilog_port(VERILOG_PORT_CONKT, addr_port);
@@ -919,6 +921,17 @@ void print_verilog_top_testbench_frame_decoder_bitstream(std::fstream& fp,
     fp << ");" << std::endl;
   }
 
+  /* Disable the address and din */
+  fp << "\t\t" << std::string(TOP_TESTBENCH_PROG_TASK_NAME);
+  fp << "(" << addr_port.get_width() << "'b";
+  std::vector<size_t> all_zero_addr(addr_port.get_width(), 0);
+  for (const size_t& addr_bit : all_zero_addr) {
+    fp << addr_bit; 
+  }
+  fp << ", ";
+  fp <<"1'b0";
+  fp << ");" << std::endl;
+
   /* Raise the flag of configuration done when bitstream loading is complete */
   BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME), 1);
   fp << "\t\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ");" << std::endl;
diff --git a/openfpga_flow/VerilogNetlists/config_latch.v b/openfpga_flow/VerilogNetlists/config_latch.v
index e177fe2e7..6cbe5657e 100644
--- a/openfpga_flow/VerilogNetlists/config_latch.v
+++ b/openfpga_flow/VerilogNetlists/config_latch.v
@@ -18,7 +18,7 @@ module config_latch (
 reg q_reg;
 
 //-------------Code Starts Here---------
-always @ ( negedge clk or posedge reset) begin
+always @ ( posedge clk or posedge reset) begin
   if (reset) begin
     q_reg <= 1'b0;
   end else if (1'b1 == wl) begin

From cdc2237008ad70104bbde858f80bc13f61bfb790 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 28 May 2020 23:07:03 -0600
Subject: [PATCH 587/645] deploy frame-based configuration protocol to travis
 CI

---
 .travis/script.sh | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/.travis/script.sh b/.travis/script.sh
index ba4c209a1..0cb3326e6 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -51,6 +51,9 @@ echo -e "Testing OpenFPGA Shell";
 echo -e "Testing configuration chain of a K4N4 FPGA";
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/configuration_chain --debug --show_thread_logs
 
+echo -e "Testing fram-based configuration protocol of a K4N4 FPGA";
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/configuration_frame --debug --show_thread_logs
+
 echo -e "Testing user-defined simulation settings: clock frequency and number of cycles";
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/fixed_simulation_settings --debug --show_thread_logs
 

From de07712a3a1bbb5477ee8853c381fce44178dd3b Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 29 May 2020 14:02:33 -0600
Subject: [PATCH 588/645] update documentation about the frame-based
 configuration protocol

---
 .../manual/arch_lang/annotate_vpr_arch.rst    |  80 -----------
 .../arch_lang/circuit_model_examples.rst      |  57 +++++++-
 .../manual/arch_lang/config_protocol.rst      | 126 ++++++++++++++++++
 .../manual/arch_lang/figures/config_latch.png | Bin 0 -> 16495 bytes
 .../figures/frame_config_protocol.png         | Bin 0 -> 85962 bytes
 .../figures/frame_config_protocol_example.png | Bin 0 -> 259112 bytes
 .../manual/arch_lang/figures/sram_blwl.png    | Bin 0 -> 41280 bytes
 docs/source/manual/arch_lang/index.rst        |   2 +
 8 files changed, 184 insertions(+), 81 deletions(-)
 create mode 100644 docs/source/manual/arch_lang/config_protocol.rst
 create mode 100644 docs/source/manual/arch_lang/figures/config_latch.png
 create mode 100644 docs/source/manual/arch_lang/figures/frame_config_protocol.png
 create mode 100644 docs/source/manual/arch_lang/figures/frame_config_protocol_example.png
 create mode 100644 docs/source/manual/arch_lang/figures/sram_blwl.png

diff --git a/docs/source/manual/arch_lang/annotate_vpr_arch.rst b/docs/source/manual/arch_lang/annotate_vpr_arch.rst
index 69aed061e..39e02269c 100644
--- a/docs/source/manual/arch_lang/annotate_vpr_arch.rst
+++ b/docs/source/manual/arch_lang/annotate_vpr_arch.rst
@@ -4,86 +4,6 @@ Bind circuit modules to VPR architecture
 ----------------------------------------
 Each defined circuit model should be linked to an FPGA module defined in the original part of architecture descriptions. It helps FPGA-circuit creating the circuit netlists for logic/routing blocks. Since the original part lacks such support, we create a few XML properties to link to Circuit models.
 
-Configuration Protocol
-~~~~~~~~~~~~~~~~~~~~~~
-
-Configuration protocol is the circuitry designed to program an FPGA.
-As an interface, configuration protocol could be really different in FPGAs, depending on the application context.
-
-Template
-````````
-
-.. code-block:: xml
-
-  <configuration_protocol>
-    <organization type="<string>" circuit_model_name="<string>"/>
-  </configuration_protocol>
-
-.. option:: type="scan_chain|memory_bank|standalone"
-
-  Specify the type of configuration circuits.
-
-  OpenFPGA supports different types of configuration protocols to program FPGA fabrics:
-    - ``scan_chain``: configurable memories are connected in a chain. Bitstream is loaded serially to program a FPGA
-    - ``memory_bank``: configurable memories are organized in an array, where each element can be accessed by an unique address to the BL/WL decoders
-    - ``standalone``: configurable memories are directly accessed through ports of FPGA fabrics. In other words, there are no protocol to control the memories. This allows full customization on the configuration protocol for hardware engineers.
-
-  .. note:: Avoid to use ``standalone`` when designing an FPGA chip. It will causes a huge number of I/Os required, far beyond any package size. It is well applicable to eFPGAs, where designers do need customized protocols between FPGA and processors. 
-
-.. warning:: Currently FPGA-SPICE only supports standalone memory organization.
-
-.. warning:: Currently RRAM-based FPGA only supports memory-bank organization for Verilog Generator.
-
-.. option:: circuit_model_name="<string>"
-
-  Specify the name of circuit model to be used as configurable memory.
-  - ``scan_chain`` requires a circuit model type of ``ccff``
-  - ``memory_bank`` requires a circuit model type of ``sram``
-  - ``standalone`` requires a circuit model type of ``sram``
-
-Configuration Chain Example
-```````````````````````````
-The following XML code describes a scan-chain circuitry to configure the core logic of FPGA, as illustrated in :numref:`fig_ccff_fpga`.
-It will use the circuit model defined in :ref:`circuit_model_examples`.
-
-.. code-block:: xml
-
-  <configuration_protocol>
-    <organization type="scan_chain" circuit_model_name="ccff"/>
-  </configuration_protocol>
-
-.. _fig_ccff_fpga:
-
-.. figure:: figures/ccff_fpga.png
-   :scale: 60%
-   :alt: map to buried treasure
- 
-   Example of a configuration chain to program core logic of a FPGA 
-
-Memory bank Example
-```````````````````
-The following XML code describes a memory-bank circuitry to configure the core logic of FPGA, as illustrated in :numref:`fig_sram`.
-It will use the circuit model defined in :ref:`circuit_model_examples`.
-
-.. code-block:: xml
-
-  <configuration_protocol>
-    <organization type="memory_bank" circuit_model_name="sram"/>
-  </configuration_protocol>
-
-.. _fig_sram:
-
-.. figure:: figures/sram.png
-   :scale: 60%
-   :alt: map to buried treasure
- 
-   Example of a memory organization using memory decoders 
-
-Standalone SRAM Example
-```````````````````````
-
-.. warning:: TO BE CONSTRUCTED
-
 Switch Blocks
 ~~~~~~~~~~~~~
 
diff --git a/docs/source/manual/arch_lang/circuit_model_examples.rst b/docs/source/manual/arch_lang/circuit_model_examples.rst
index 9b689d2f7..e93d18e6a 100644
--- a/docs/source/manual/arch_lang/circuit_model_examples.rst
+++ b/docs/source/manual/arch_lang/circuit_model_examples.rst
@@ -240,7 +240,62 @@ Template
 
 .. note:: The information of input and output buffer should be clearly specified according to the customized Verilog/SPICE netlist! The existence of input/output buffers will influence the decision in creating testbenches, which may leads to larger errors in power analysis.
 
-.. note:: The support SRAM modules should have a BL and a WL when the memory-bank-style configuration circuit is declared. Note that the WL should be the write/read enable signal, while BL is the data input.
+SRAM with BL/WL
+```````````````
+.. _fig_sram_blwl:
+
+.. figure:: ./figures/sram_blwl.png
+   :scale: 100%
+
+   An example of a SRAM with Bit-Line (BL) and Word-Line (WL) control signals
+
+The following XML codes describes the SRAM cell shown in :numref:`fig_sram_blwl`.
+
+.. code-block:: xml
+
+  <circuit_model type="sram" name="sram_blwl" prefix="sram_blwl" verilog_netlist="sram.v" spice_netlist="sram.sp"/>
+    <design_technology type="cmos"/>
+    <input_buffer exist="false"/>
+    <output_buffer exist="false"/>
+    <port type="bl" prefix="bl" size="1"/>
+    <port type="blb" prefix="blb" size="1"/>
+    <port type="wl" prefix="wl" size="1"/>
+    <port type="output" prefix="out" size="1"/>
+    <port type="output" prefix="outb" size="1"/>
+  </circuit_model>
+
+.. note:: OpenFPGA always assume that a ``WL`` port should be the write/read enable signal, while a ``BL`` port is the data input.
+
+.. note:: When the ``memory_bank`` type of configuration procotol is specified, SRAM modules should have a BL and a WL.
+
+Configurable Latch
+``````````````````
+
+.. _fig_config_latch:
+
+.. figure:: ./figures/config_latch.png
+   :scale: 100%
+
+   An example of a SRAM-based configurable latch with Bit-Line (BL) and Word-Line (WL) control signals
+
+The following XML codes describes the configurable latch shown in :numref:`fig_config_latch`.
+
+.. code-block:: xml
+
+  <circuit_model type="sram" name="config_latch" prefix="config_latch" verilog_netlist="sram.v" spice_netlist="sram.sp"/>
+    <design_technology type="cmos"/>
+    <input_buffer exist="false"/>
+    <output_buffer exist="false"/>
+    <port type="clock" prefix="clk" size="1"/>
+    <port type="bl" prefix="bl" size="1"/>
+    <port type="wl" prefix="wl" size="1"/>
+    <port type="output" prefix="out" size="1"/>
+    <port type="output" prefix="outb" size="1"/>
+  </circuit_model>
+
+.. note:: OpenFPGA always assume that a ``WL`` port should be the write/read enable signal, while a ``BL`` port is the data input.
+
+.. note:: When the ``frame_based`` type of configuration procotol is specified, the configurable latch or a SRAM with ``BL`` and ``WL`` should be specified.
 
 Logic gates
 ~~~~~~~~~~~
diff --git a/docs/source/manual/arch_lang/config_protocol.rst b/docs/source/manual/arch_lang/config_protocol.rst
new file mode 100644
index 000000000..f37c7f18b
--- /dev/null
+++ b/docs/source/manual/arch_lang/config_protocol.rst
@@ -0,0 +1,126 @@
+.. _config_protocol:
+
+Configuration Protocol
+----------------------
+
+Configuration protocol is the circuitry designed to program an FPGA.
+As an interface, configuration protocol could be really different in FPGAs, depending on the application context.
+OpenFPGA supports versatile configuration protocol, providing different trade-offs between speed and area. 
+
+Template
+~~~~~~~~
+
+.. code-block:: xml
+
+  <configuration_protocol>
+    <organization type="<string>" circuit_model_name="<string>"/>
+  </configuration_protocol>
+
+.. option:: type="scan_chain|memory_bank|standalone"
+
+  Specify the type of configuration circuits.
+
+  OpenFPGA supports different types of configuration protocols to program FPGA fabrics:
+    - ``scan_chain``: configurable memories are connected in a chain. Bitstream is loaded serially to program a FPGA
+    - ``frame_based``: configurable memories are organized by frames. Each module of a FPGA fabric, e.g., Configurable Logic Block (CLB), Switch Block (SB) and Connection Block (CB), is considered as a frame of configurable memories. Inside each frame, all the memory banks are accessed through an address decoder. Users can write each memory cell with a specific address. Note that the frame-based memory organization is applid hierarchically. Each frame may consists of a number of sub frames, each of which follows the similar organization.
+    - ``memory_bank``: configurable memories are organized in an array, where each element can be accessed by an unique address to the BL/WL decoders
+    - ``standalone``: configurable memories are directly accessed through ports of FPGA fabrics. In other words, there are no protocol to control the memories. This allows full customization on the configuration protocol for hardware engineers.
+
+  .. note:: Avoid to use ``standalone`` when designing an FPGA chip. It will causes a huge number of I/Os required, far beyond any package size. It is well applicable to eFPGAs, where designers do need customized protocols between FPGA and processors. 
+
+.. warning:: Currently FPGA-SPICE only supports standalone memory organization.
+
+.. warning:: Currently RRAM-based FPGA only supports memory-bank organization for Verilog Generator.
+
+.. option:: circuit_model_name="<string>"
+
+  Specify the name of circuit model to be used as configurable memory.
+  - ``scan_chain`` requires a circuit model type of ``ccff``
+  - ``frame_based`` requires a circuit model type of ``sram``
+  - ``memory_bank`` requires a circuit model type of ``sram``
+  - ``standalone`` requires a circuit model type of ``sram``
+
+Configuration Chain Example
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+The following XML code describes a scan-chain circuitry to configure the core logic of FPGA, as illustrated in :numref:`fig_ccff_fpga`.
+It will use the circuit model defined in :numref:`fig_ccff`.
+
+.. code-block:: xml
+
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="ccff"/>
+  </configuration_protocol>
+
+.. _fig_ccff_fpga:
+
+.. figure:: figures/ccff_fpga.png
+   :scale: 60%
+   :alt: map to buried treasure
+ 
+   Example of a configuration chain to program core logic of a FPGA 
+
+Frame-based Example
+~~~~~~~~~~~~~~~~~~~
+The following XML code describes frame-based memory banks to configure the core logic of FPGA.
+It will use the circuit model defined in :numref:`fig_config_latch`.
+
+.. code-block:: xml
+
+  <configuration_protocol>
+    <organization type="frame_based" circuit_model_name="config_latch"/>
+  </configuration_protocol>
+
+Through frame-based configuration protocol, each memory cell can be accessed with an unique address given to decoders.
+:numref:`fig_frame_config_protocol_example` illustrates an example about how the configurable memories are organizaed inside a Logic Element (LE) shown in :numref:`fig_k4n4_arch`.
+The decoder inside the LE will enable the decoders of the Look-Up Table (LUT) and the routing multiplexer, based on the given address at ``address[2:2]``.
+When the decoder of sub block, e.g., the LUT, is enabled, each memory cells can be accessed throught the ``address[1:0]`` and the data to write is provided at ``data_in``.
+
+.. _fig_frame_config_protocol_example:
+
+.. figure:: figures/frame_config_protocol_example.png
+   :scale: 25%
+   :alt: map to buried treasure
+ 
+   Example of a frame-based memory organization inside a Logic Element
+
+:numref:`fig_frame_config_protocol` shows a hierarchical view on how the frame-based decoders across a FPGA fabric. 
+
+.. _fig_frame_config_protocol:
+
+.. figure:: figures/frame_config_protocol.png
+   :scale: 60%
+   :alt: map to buried treasure
+ 
+   Frame-based memory organization in a hierarchical view
+
+.. note:: Frame-based decoders does require a memory cell to have 
+
+  -  two outputs (one regular and another inverted)
+  -  a Bit-Line input to load the data
+  -  a Word-Line input to enable data write 
+
+Memory bank Example
+~~~~~~~~~~~~~~~~~~~
+The following XML code describes a memory-bank circuitry to configure the core logic of FPGA, as illustrated in :numref:`fig_sram`.
+It will use the circuit model defined in :numref:`fig_sram_blwl`.
+
+.. code-block:: xml
+
+  <configuration_protocol>
+    <organization type="memory_bank" circuit_model_name="sram"/>
+  </configuration_protocol>
+
+.. _fig_sram:
+
+.. figure:: figures/sram.png
+   :scale: 60%
+   :alt: map to buried treasure
+ 
+   Example of a memory organization using memory decoders 
+
+.. warning:: THIS IS STILL UNDER CONSTRUCTION
+
+Standalone SRAM Example
+~~~~~~~~~~~~~~~~~~~~~~~
+
+.. warning:: TO BE CONSTRUCTED
diff --git a/docs/source/manual/arch_lang/figures/config_latch.png b/docs/source/manual/arch_lang/figures/config_latch.png
new file mode 100644
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HcmV?d00001

diff --git a/docs/source/manual/arch_lang/index.rst b/docs/source/manual/arch_lang/index.rst
index b7e33de15..f2fd146fb 100644
--- a/docs/source/manual/arch_lang/index.rst
+++ b/docs/source/manual/arch_lang/index.rst
@@ -11,6 +11,8 @@ OpenFPGA Architecture Description
 
    addon_vpr_syntax
 
+   config_protocol
+
    direct_interconnect 
    
    simulation_setting

From 827e2e6713f6f96b9f654c05da5bf760e176cf14 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 29 May 2020 15:59:57 -0600
Subject: [PATCH 589/645] file moving in regression tests

---
 .travis/script.sh                                             | 4 ++--
 .../{ => full_testbench}/configuration_chain/config/task.conf | 0
 .../{ => full_testbench}/configuration_frame/config/task.conf | 0
 3 files changed, 2 insertions(+), 2 deletions(-)
 rename openfpga_flow/tasks/openfpga_shell/{ => full_testbench}/configuration_chain/config/task.conf (100%)
 rename openfpga_flow/tasks/openfpga_shell/{ => full_testbench}/configuration_frame/config/task.conf (100%)

diff --git a/.travis/script.sh b/.travis/script.sh
index 0cb3326e6..8a716156b 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -49,10 +49,10 @@ python3 openfpga_flow/scripts/run_fpga_task.py duplicate_grid_pin --debug --show
 echo -e "Testing OpenFPGA Shell";
 
 echo -e "Testing configuration chain of a K4N4 FPGA";
-python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/configuration_chain --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/configuration_chain --debug --show_thread_logs
 
 echo -e "Testing fram-based configuration protocol of a K4N4 FPGA";
-python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/configuration_frame --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/configuration_frame --debug --show_thread_logs
 
 echo -e "Testing user-defined simulation settings: clock frequency and number of cycles";
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/fixed_simulation_settings --debug --show_thread_logs
diff --git a/openfpga_flow/tasks/openfpga_shell/configuration_chain/config/task.conf b/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_chain/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/openfpga_shell/configuration_chain/config/task.conf
rename to openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_chain/config/task.conf
diff --git a/openfpga_flow/tasks/openfpga_shell/configuration_frame/config/task.conf b/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_frame/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/openfpga_shell/configuration_frame/config/task.conf
rename to openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_frame/config/task.conf

From 05aa166a9e852277174add04e19ec75e987ba90e Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 29 May 2020 16:12:51 -0600
Subject: [PATCH 590/645] add preconfig testbench cases to regression tests for
 different configuration protocols

---
 .../configuration_chain/config/task.conf      | 34 +++++++++++++++++++
 .../configuration_frame/config/task.conf      | 34 +++++++++++++++++++
 2 files changed, 68 insertions(+)
 create mode 100644 openfpga_flow/tasks/openfpga_shell/preconfig_testbench/configuration_chain/config/task.conf
 create mode 100644 openfpga_flow/tasks/openfpga_shell/preconfig_testbench/configuration_frame/config/task.conf

diff --git a/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/configuration_chain/config/task.conf b/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/configuration_chain/config/task.conf
new file mode 100644
index 000000000..3fd340a7b
--- /dev/null
+++ b/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/configuration_chain/config/task.conf
@@ -0,0 +1,34 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=
diff --git a/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/configuration_frame/config/task.conf b/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/configuration_frame/config/task.conf
new file mode 100644
index 000000000..4a41fc671
--- /dev/null
+++ b/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/configuration_frame/config/task.conf
@@ -0,0 +1,34 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

From 22648cdb9cabaa4e37b5c41d548aef87c1707f8f Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 29 May 2020 16:14:22 -0600
Subject: [PATCH 591/645] deploy the preconfig testbench cases to CI

---
 .travis/script.sh | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/.travis/script.sh b/.travis/script.sh
index 8a716156b..37ad55006 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -50,9 +50,11 @@ echo -e "Testing OpenFPGA Shell";
 
 echo -e "Testing configuration chain of a K4N4 FPGA";
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/configuration_chain --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/preconfig_testbench/configuration_chain --debug --show_thread_logs
 
 echo -e "Testing fram-based configuration protocol of a K4N4 FPGA";
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/configuration_frame --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/preconfig_testbench/configuration_frame --debug --show_thread_logs
 
 echo -e "Testing user-defined simulation settings: clock frequency and number of cycles";
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/fixed_simulation_settings --debug --show_thread_logs

From 8b3e79766c4c0a78212fbc51ffb948daffb4ffac Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 29 May 2020 18:07:21 -0600
Subject: [PATCH 592/645] add fast configuration option to fpga_verilog to
 speed up full testbench simulation

---
 openfpga/src/base/openfpga_verilog.cpp        |  2 +
 .../src/base/openfpga_verilog_command.cpp     |  3 +
 openfpga/src/fpga_verilog/verilog_api.cpp     |  1 +
 .../verilog_testbench_options.cpp             |  8 +++
 .../fpga_verilog/verilog_testbench_options.h  |  3 +
 .../fpga_verilog/verilog_top_testbench.cpp    | 63 +++++++++++++++--
 .../src/fpga_verilog/verilog_top_testbench.h  |  1 +
 ...onfiguration_frame_example_script.openfpga |  2 +-
 .../full_testbench_example_script.openfpga    | 68 +++++++++++++++++++
 .../configuration_frame/config/task.conf      |  2 +-
 10 files changed, 145 insertions(+), 8 deletions(-)
 create mode 100644 openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga

diff --git a/openfpga/src/base/openfpga_verilog.cpp b/openfpga/src/base/openfpga_verilog.cpp
index c67c270eb..926e0f8d3 100644
--- a/openfpga/src/base/openfpga_verilog.cpp
+++ b/openfpga/src/base/openfpga_verilog.cpp
@@ -67,6 +67,7 @@ int write_verilog_testbench(OpenfpgaContext& openfpga_ctx,
   CommandOptionId opt_output_dir = cmd.option("file");
   CommandOptionId opt_reference_benchmark = cmd.option("reference_benchmark_file_path");
   CommandOptionId opt_print_top_testbench = cmd.option("print_top_testbench");
+  CommandOptionId opt_fast_configuration = cmd.option("fast_configuration");
   CommandOptionId opt_print_formal_verification_top_netlist = cmd.option("print_formal_verification_top_netlist");
   CommandOptionId opt_print_preconfig_top_testbench = cmd.option("print_preconfig_top_testbench");
   CommandOptionId opt_print_simulation_ini = cmd.option("print_simulation_ini");
@@ -81,6 +82,7 @@ int write_verilog_testbench(OpenfpgaContext& openfpga_ctx,
   options.set_reference_benchmark_file_path(cmd_context.option_value(cmd, opt_reference_benchmark));
   options.set_print_formal_verification_top_netlist(cmd_context.option_enable(cmd, opt_print_formal_verification_top_netlist));
   options.set_print_preconfig_top_testbench(cmd_context.option_enable(cmd, opt_print_preconfig_top_testbench));
+  options.set_fast_configuration(cmd_context.option_enable(cmd, opt_fast_configuration));
   options.set_print_top_testbench(cmd_context.option_enable(cmd, opt_print_top_testbench));
   options.set_print_simulation_ini(cmd_context.option_value(cmd, opt_print_simulation_ini));
   options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping));
diff --git a/openfpga/src/base/openfpga_verilog_command.cpp b/openfpga/src/base/openfpga_verilog_command.cpp
index 99ee7a319..89c4e27e3 100644
--- a/openfpga/src/base/openfpga_verilog_command.cpp
+++ b/openfpga/src/base/openfpga_verilog_command.cpp
@@ -79,6 +79,9 @@ ShellCommandId add_openfpga_write_verilog_testbench_command(openfpga::Shell<Open
   /* Add an option '--print_top_testbench' */
   shell_cmd.add_option("print_top_testbench", false, "Generate a full testbench for top-level fabric module with autocheck capability");
 
+  /* Add an option '--fast_configuration' */
+  shell_cmd.add_option("fast_configuration", false, "Reduce the period of configuration by skip zero data points");
+
   /* Add an option '--print_formal_verification_top_netlist' */
   shell_cmd.add_option("print_formal_verification_top_netlist", false, "Generate a top-level module which can be used in formal verification");
 
diff --git a/openfpga/src/fpga_verilog/verilog_api.cpp b/openfpga/src/fpga_verilog/verilog_api.cpp
index 705cd4a65..27ddc28b4 100644
--- a/openfpga/src/fpga_verilog/verilog_api.cpp
+++ b/openfpga/src/fpga_verilog/verilog_api.cpp
@@ -213,6 +213,7 @@ void fpga_verilog_testbench(const ModuleManager& module_manager,
                                 netlist_name,
                                 top_testbench_file_path,
                                 simulation_setting,
+                                options.fast_configuration(),
                                 options.explicit_port_mapping());
   }
  
diff --git a/openfpga/src/fpga_verilog/verilog_testbench_options.cpp b/openfpga/src/fpga_verilog/verilog_testbench_options.cpp
index 9fc6bfd33..d56037f81 100644
--- a/openfpga/src/fpga_verilog/verilog_testbench_options.cpp
+++ b/openfpga/src/fpga_verilog/verilog_testbench_options.cpp
@@ -46,6 +46,10 @@ bool VerilogTestbenchOption::print_top_testbench() const {
   return print_top_testbench_;
 }
 
+bool VerilogTestbenchOption::fast_configuration() const {
+  return fast_configuration_;
+}
+
 bool VerilogTestbenchOption::print_simulation_ini() const {
   return !simulation_ini_path_.empty();
 }
@@ -82,6 +86,10 @@ void VerilogTestbenchOption::set_print_formal_verification_top_netlist(const boo
   print_formal_verification_top_netlist_ = enabled;
 }
 
+void VerilogTestbenchOption::set_fast_configuration(const bool& enabled) {
+  fast_configuration_ = enabled;
+}
+
 void VerilogTestbenchOption::set_print_preconfig_top_testbench(const bool& enabled) {
   print_preconfig_top_testbench_ = enabled
                                  && (!reference_benchmark_file_path_.empty());
diff --git a/openfpga/src/fpga_verilog/verilog_testbench_options.h b/openfpga/src/fpga_verilog/verilog_testbench_options.h
index 2572e3dee..89d93b46e 100644
--- a/openfpga/src/fpga_verilog/verilog_testbench_options.h
+++ b/openfpga/src/fpga_verilog/verilog_testbench_options.h
@@ -24,6 +24,7 @@ class VerilogTestbenchOption {
   public: /* Public accessors */
     std::string output_directory() const;
     std::string reference_benchmark_file_path() const;
+    bool fast_configuration() const;
     bool print_formal_verification_top_netlist() const;
     bool print_preconfig_top_testbench() const;
     bool print_top_testbench() const;
@@ -44,6 +45,7 @@ class VerilogTestbenchOption {
     void set_print_formal_verification_top_netlist(const bool& enabled);
     /* The preconfig top testbench generation can be enabled only when formal verification top netlist is enabled */
     void set_print_preconfig_top_testbench(const bool& enabled);
+    void set_fast_configuration(const bool& enabled);
     void set_print_top_testbench(const bool& enabled);
     void set_print_simulation_ini(const std::string& simulation_ini_path);
     void set_explicit_port_mapping(const bool& enabled);
@@ -51,6 +53,7 @@ class VerilogTestbenchOption {
   private: /* Internal Data */
     std::string output_directory_;
     std::string reference_benchmark_file_path_;
+    bool fast_configuration_;
     bool print_formal_verification_top_netlist_;
     bool print_preconfig_top_testbench_;
     bool print_top_testbench_;
diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
index 91e5eb8cf..5c6795132 100644
--- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
@@ -481,6 +481,48 @@ void print_verilog_top_testbench_ports(std::fstream& fp,
   fp << "\tinteger " << TOP_TESTBENCH_ERROR_COUNTER << "= 0;" << std::endl;
 }
 
+/********************************************************************
+ * Estimate the number of configuration clock cycles 
+ * by traversing the linked-list and count the number of SRAM=1 or BL=1&WL=1 in it.
+ * We plus 1 additional config clock cycle here because we need to reset everything during the first clock cycle
+ * If we consider fast configuration, the number of clock cycles will be 
+ * the number of non-zero data points in the fabric bitstream
+ * Note that this will not applicable to configuration chain!!!
+ *******************************************************************/
+static 
+size_t calculate_num_config_clock_cycles(const e_config_protocol_type& sram_orgz_type,
+                                         const bool& fast_configuration,
+                                         const FabricBitstream& fabric_bitstream) {
+  size_t num_config_clock_cycles = 1 + fabric_bitstream.bits().size();
+
+  /* Branch on the type of configuration protocol */
+  switch (sram_orgz_type) {
+  case CONFIG_MEM_STANDALONE:
+  case CONFIG_MEM_SCAN_CHAIN:
+  case CONFIG_MEM_MEMORY_BANK:
+    /* TODO */
+    break;
+  case CONFIG_MEM_FRAME_BASED: {
+    /* For fast configuration, we will skip all the zero data points */
+    if (true == fast_configuration) {
+      num_config_clock_cycles = 1;
+      for (const FabricBitId& bit_id : fabric_bitstream.bits()) {
+        if (true == fabric_bitstream.bit_din(bit_id)) {
+          num_config_clock_cycles++;
+        }
+      }
+    }
+    break;
+  }
+  default: 
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid SRAM organization type!\n");
+    exit(1);
+  }
+
+  return num_config_clock_cycles;
+}
+
 /********************************************************************
  * Instanciate the input benchmark module
  *******************************************************************/
@@ -865,6 +907,7 @@ void print_verilog_top_testbench_configuration_chain_bitstream(std::fstream& fp,
  *******************************************************************/
 static 
 void print_verilog_top_testbench_frame_decoder_bitstream(std::fstream& fp,
+                                                         const bool& fast_configuration,
                                                          const ModuleManager& module_manager,
                                                          const ModuleId& top_module,
                                                          const FabricBitstream& fabric_bitstream) {
@@ -904,6 +947,12 @@ void print_verilog_top_testbench_frame_decoder_bitstream(std::fstream& fp,
    * We will visit the fabric bitstream in a reverse way  
    */
   for (const FabricBitId& bit_id : fabric_bitstream.bits()) {
+    /* When fast configuration is enabled, we skip zero data_in values */
+    if ((true == fast_configuration)
+      && (false == fabric_bitstream.bit_din(bit_id))) {
+      continue;
+    }
+
     fp << "\t\t" << std::string(TOP_TESTBENCH_PROG_TASK_NAME);
     fp << "(" << addr_port.get_width() << "'b";
     VTR_ASSERT(addr_port.get_width() == fabric_bitstream.bit_address(bit_id).size());
@@ -957,6 +1006,7 @@ void print_verilog_top_testbench_frame_decoder_bitstream(std::fstream& fp,
 static 
 void print_verilog_top_testbench_bitstream(std::fstream& fp,
                                            const e_config_protocol_type& sram_orgz_type,
+                                           const bool& fast_configuration,
                                            const ModuleManager& module_manager,
                                            const ModuleId& top_module,
                                            const BitstreamManager& bitstream_manager,
@@ -973,7 +1023,7 @@ void print_verilog_top_testbench_bitstream(std::fstream& fp,
     /* TODO */
     break;
   case CONFIG_MEM_FRAME_BASED:
-    print_verilog_top_testbench_frame_decoder_bitstream(fp,
+    print_verilog_top_testbench_frame_decoder_bitstream(fp, fast_configuration,
                                                         module_manager, top_module,
                                                         fabric_bitstream);
     break;
@@ -1017,6 +1067,7 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
                                  const std::string& circuit_name,
                                  const std::string& verilog_fname,
                                  const SimulationSetting& simulation_parameters,
+                                 const bool& fast_configuration,
                                  const bool& explicit_port_mapping) {
 
   std::string timer_message = std::string("Write autocheck testbench for FPGA top-level Verilog netlist for '") + circuit_name + std::string("'");
@@ -1050,11 +1101,10 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
   /* Find the clock period */
   float prog_clock_period = (1./simulation_parameters.programming_clock_frequency());
   float op_clock_period = (1./simulation_parameters.operating_clock_frequency());
-  /* Estimate the number of configuration clock cycles 
-   * by traversing the linked-list and count the number of SRAM=1 or BL=1&WL=1 in it.
-   * We plus 1 additional config clock cycle here because we need to reset everything during the first clock cycle
-   */
-  size_t num_config_clock_cycles = 1 + fabric_bitstream.bits().size();
+  /* Estimate the number of configuration clock cycles */ 
+  size_t num_config_clock_cycles = calculate_num_config_clock_cycles(sram_orgz_type,
+                                                                     fast_configuration,
+                                                                     fabric_bitstream);
 
   /* Generate stimuli for general control signals */
   print_verilog_top_testbench_generic_stimulus(fp,
@@ -1095,6 +1145,7 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
 
   /* load bitstream to FPGA fabric in a configuration phase */
   print_verilog_top_testbench_bitstream(fp, sram_orgz_type,
+                                        fast_configuration,
                                         module_manager, top_module,
                                         bitstream_manager, fabric_bitstream);
 
diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.h b/openfpga/src/fpga_verilog/verilog_top_testbench.h
index 07e671e57..270fba24e 100644
--- a/openfpga/src/fpga_verilog/verilog_top_testbench.h
+++ b/openfpga/src/fpga_verilog/verilog_top_testbench.h
@@ -35,6 +35,7 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
                                  const std::string& circuit_name,
                                  const std::string& verilog_fname,
                                  const SimulationSetting& simulation_parameters,
+                                 const bool& fast_configuration,
                                  const bool& explicit_port_mapping);
 
 } /* end namespace openfpga */
diff --git a/openfpga_flow/OpenFPGAShellScripts/configuration_frame_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/configuration_frame_example_script.openfpga
index bcc8d36e3..94e16b906 100644
--- a/openfpga_flow/OpenFPGAShellScripts/configuration_frame_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/configuration_frame_example_script.openfpga
@@ -49,7 +49,7 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --inc
 #  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
+write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping --fast_configuration
 
 # Write the SDC files for PnR backend
 #  - Turn on every options here
diff --git a/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga
new file mode 100644
index 000000000..bcc8d36e3
--- /dev/null
+++ b/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga
@@ -0,0 +1,68 @@
+# Run VPR for the 'and' design
+#--write_rr_graph example_rr_graph.xml
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
+
+# Annotate the OpenFPGA architecture to VPR data base
+# to debug use --verbose options
+link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to clustering nets based on routing results
+pb_pin_fixup --verbose
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup
+
+# Build the module graph
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules
+build_fabric --compress_routing #--verbose
+
+# Write the fabric hierarchy of module graph to a file
+# This is used by hierarchical PnR flows
+write_fabric_hierarchy --file ./fabric_hierarchy.txt
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --file fabric_indepenent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here
+write_pnr_sdc --file ./SDC
+
+# Write SDC to disable timing for configure ports
+write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+write_analysis_sdc --file ./SDC_analysis
+
+# Finish and exit OpenFPGA
+exit
+
+# Note :
+# To run verification at the end of the flow maintain source in ./SRC directory
diff --git a/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_frame/config/task.conf b/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_frame/config/task.conf
index 7a448e3e8..2f5baca4d 100644
--- a/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_frame/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_frame/config/task.conf
@@ -8,7 +8,7 @@
 
 [GENERAL]
 run_engine=openfpga_shell
-openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/configuration_frame_example_script.openfpga
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga
 power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
 power_analysis = true
 spice_output=false

From a5138113e422bf73ec7e037281ff3e3c81655a9b Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 29 May 2020 18:08:16 -0600
Subject: [PATCH 593/645] add fast configuration testcase

---
 .../fast_configuration_frame/config/task.conf | 34 +++++++++++++++++++
 1 file changed, 34 insertions(+)
 create mode 100644 openfpga_flow/tasks/openfpga_shell/full_testbench/fast_configuration_frame/config/task.conf

diff --git a/openfpga_flow/tasks/openfpga_shell/full_testbench/fast_configuration_frame/config/task.conf b/openfpga_flow/tasks/openfpga_shell/full_testbench/fast_configuration_frame/config/task.conf
new file mode 100644
index 000000000..7a448e3e8
--- /dev/null
+++ b/openfpga_flow/tasks/openfpga_shell/full_testbench/fast_configuration_frame/config/task.conf
@@ -0,0 +1,34 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/configuration_frame_example_script.openfpga
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+#vpr_fpga_verilog_formal_verification_top_netlist=

From 9e176b8d383da30f1880267b30eed967963928fe Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 29 May 2020 18:22:36 -0600
Subject: [PATCH 594/645] add fast configuration stats to log

---
 openfpga/src/fpga_verilog/verilog_top_testbench.cpp | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
index 5c6795132..4a1072c70 100644
--- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
@@ -505,12 +505,17 @@ size_t calculate_num_config_clock_cycles(const e_config_protocol_type& sram_orgz
   case CONFIG_MEM_FRAME_BASED: {
     /* For fast configuration, we will skip all the zero data points */
     if (true == fast_configuration) {
+      size_t full_num_config_clock_cycles = num_config_clock_cycles;
       num_config_clock_cycles = 1;
       for (const FabricBitId& bit_id : fabric_bitstream.bits()) {
         if (true == fabric_bitstream.bit_din(bit_id)) {
           num_config_clock_cycles++;
         }
       }
+      VTR_LOG("Fast configuration reduces number of configuration clock cycles from %lu to %lu (compression_rate = %f%)\n",
+              full_num_config_clock_cycles,
+              num_config_clock_cycles,
+              100. * ((float)num_config_clock_cycles / (float)full_num_config_clock_cycles - 1.));
     }
     break;
   }
@@ -520,6 +525,9 @@ size_t calculate_num_config_clock_cycles(const e_config_protocol_type& sram_orgz
     exit(1);
   }
 
+  VTR_LOG("Will use %ld configuration clock cycles to top testbench\n",
+          num_config_clock_cycles);
+
   return num_config_clock_cycles;
 }
 

From 9a6a5e331024b2fa5f7759b198aa0eba4b167f45 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 29 May 2020 18:23:12 -0600
Subject: [PATCH 595/645] deploy fast configuration testcase to CI

---
 .travis/script.sh | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.travis/script.sh b/.travis/script.sh
index 37ad55006..9d222c17a 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -54,6 +54,7 @@ python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/preconfig_testbenc
 
 echo -e "Testing fram-based configuration protocol of a K4N4 FPGA";
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/configuration_frame --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/fast_configuration_frame --debug --show_thread_logs
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/preconfig_testbench/configuration_frame --debug --show_thread_logs
 
 echo -e "Testing user-defined simulation settings: clock frequency and number of cycles";

From d2d443a988d65ec5a0677a990f1581e5594ea024 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 29 May 2020 20:55:45 -0600
Subject: [PATCH 596/645] start developing memory bank and standalone
 configuration protocol

---
 openfpga/src/base/openfpga_reserved_words.h  |   2 +
 openfpga/src/fabric/build_memory_modules.cpp | 276 +++++++------------
 2 files changed, 100 insertions(+), 178 deletions(-)

diff --git a/openfpga/src/base/openfpga_reserved_words.h b/openfpga/src/base/openfpga_reserved_words.h
index 132858687..40a2af96b 100644
--- a/openfpga/src/base/openfpga_reserved_words.h
+++ b/openfpga/src/base/openfpga_reserved_words.h
@@ -23,6 +23,8 @@ constexpr char* GRID_MEM_INSTANCE_PREFIX = "mem_";
 constexpr char* SWITCH_BLOCK_MEM_INSTANCE_PREFIX = "mem_"; 
 constexpr char* CONNECTION_BLOCK_MEM_INSTANCE_PREFIX = "mem_"; 
 constexpr char* MEMORY_MODULE_POSTFIX = "_mem";
+constexpr char* MEMORY_BL_PORT_NAME = "bl";
+constexpr char* MEMORY_WL_PORT_NAME = "wl";
 
 /* Multiplexer naming constant strings */
 constexpr char* MUX_BASIS_MODULE_POSTFIX = "_basis";
diff --git a/openfpga/src/fabric/build_memory_modules.cpp b/openfpga/src/fabric/build_memory_modules.cpp
index bc04dd07d..f634408b1 100644
--- a/openfpga/src/fabric/build_memory_modules.cpp
+++ b/openfpga/src/fabric/build_memory_modules.cpp
@@ -40,59 +40,31 @@ namespace openfpga {
 static 
 void add_module_input_nets_to_mem_modules(ModuleManager& module_manager,
                                           const ModuleId& mem_module,
+                                          const ModulePortId& module_port,
                                           const CircuitLibrary& circuit_lib,
-                                          const std::vector<CircuitPortId>& circuit_ports,
+                                          const CircuitPortId& circuit_port,
                                           const ModuleId& child_module,
                                           const size_t& child_index,
                                           const size_t& child_instance) {
   /* Wire inputs of parent module to inputs of child modules */
-  for (const auto& port : circuit_ports) {
-    ModulePortId src_port_id = module_manager.find_module_port(mem_module, circuit_lib.port_prefix(port));
-    ModulePortId sink_port_id = module_manager.find_module_port(child_module, circuit_lib.port_prefix(port));
-    for (size_t pin_id = 0; pin_id < module_manager.module_port(mem_module, sink_port_id).pins().size(); ++pin_id) {
-      ModuleNetId net = module_manager.create_module_net(mem_module);
-      /* Source pin is shifted by the number of memories */
-      size_t src_pin_id = child_index * circuit_lib.port_size(port) + module_manager.module_port(mem_module, src_port_id).pins()[pin_id];
-      /* Source node of the input net is the input of memory module */
-      module_manager.add_module_net_source(mem_module, net, mem_module, 0, src_port_id, src_pin_id);
-      /* Sink node of the input net is the input of sram module */
-      size_t sink_pin_id = module_manager.module_port(child_module, sink_port_id).pins()[pin_id];
-      module_manager.add_module_net_sink(mem_module, net, child_module, child_instance, sink_port_id, sink_pin_id);
-    }
-  }
-}
+  ModulePortId src_port_id = module_port;
+  ModulePortId sink_port_id = module_manager.find_module_port(child_module, circuit_lib.port_prefix(circuit_port));
 
-/*********************************************************************
- * Add module nets to connect an output port of a memory module to 
- * an output port of its child module
- * Restriction: this function is really designed for memory modules
- * 1. It assumes that output port name of child module is the same as memory module
- * 2. It assumes exact pin-to-pin mapping: 
- *     j-th pin of output port of the i-th child module is wired to the j + i*W -th
- *     pin of output port of the memory module, where W is the size of port 
- ********************************************************************/
-static 
-void add_module_output_nets_to_mem_modules(ModuleManager& module_manager,
-                                           const ModuleId& mem_module,
-                                           const CircuitLibrary& circuit_lib,
-                                           const std::vector<CircuitPortId>& circuit_ports,
-                                           const ModuleId& child_module,
-                                           const size_t& child_index,
-                                           const size_t& child_instance) {
-  /* Wire inputs of parent module to inputs of child modules */
-  for (const auto& port : circuit_ports) {
-    ModulePortId src_port_id = module_manager.find_module_port(child_module, circuit_lib.port_prefix(port));
-    ModulePortId sink_port_id = module_manager.find_module_port(mem_module, circuit_lib.port_prefix(port));
-    for (size_t pin_id = 0; pin_id < module_manager.module_port(child_module, src_port_id).pins().size(); ++pin_id) {
-      ModuleNetId net = module_manager.create_module_net(mem_module);
-      /* Source pin is shifted by the number of memories */
-      size_t src_pin_id = module_manager.module_port(child_module, src_port_id).pins()[pin_id];
-      /* Source node of the input net is the input of memory module */
-      module_manager.add_module_net_source(mem_module, net, child_module, child_instance, src_port_id, src_pin_id);
-      /* Sink node of the input net is the input of sram module */
-      size_t sink_pin_id = child_index * circuit_lib.port_size(port) + module_manager.module_port(mem_module, sink_port_id).pins()[pin_id];
-      module_manager.add_module_net_sink(mem_module, net, mem_module, 0, sink_port_id, sink_pin_id);
-    }
+  /* Source pin is shifted by the number of memories */
+  size_t src_pin_id = module_manager.module_port(mem_module, src_port_id).pins()[child_index];
+
+  ModuleNetId net = module_manager.module_instance_port_net(mem_module,
+                                                            mem_module, 0, 
+                                                            src_port_id, src_pin_id);
+  if (ModuleNetId::INVALID() == net) { 
+    net = module_manager.create_module_net(mem_module);
+    module_manager.add_module_net_source(mem_module, net, mem_module, 0, src_port_id, src_pin_id);
+  }
+
+  for (size_t pin_id = 0; pin_id < module_manager.module_port(mem_module, sink_port_id).pins().size(); ++pin_id) {
+    /* Sink node of the input net is the input of sram module */
+    size_t sink_pin_id = module_manager.module_port(child_module, sink_port_id).pins()[pin_id];
+    module_manager.add_module_net_sink(mem_module, net, child_module, child_instance, sink_port_id, sink_pin_id);
   }
 }
 
@@ -139,6 +111,38 @@ std::vector<ModuleNetId> add_module_output_nets_to_chain_mem_modules(ModuleManag
   return module_nets;
 }
 
+/*********************************************************************
+ * Add module nets to connect an output port of a memory module to 
+ * an output port of its child module
+ * Restriction: this function is really designed for memory modules
+ * 1. It assumes that output port name of child module is the same as memory module
+ * 2. It assumes exact pin-to-pin mapping: 
+ *     j-th pin of output port of the i-th child module is wired to the j + i*W -th
+ *     pin of output port of the memory module, where W is the size of port 
+ ********************************************************************/
+static 
+void add_module_output_nets_to_mem_modules(ModuleManager& module_manager,
+                                           const ModuleId& mem_module,
+                                           const CircuitLibrary& circuit_lib,
+                                           const std::vector<CircuitPortId>& sram_output_ports,
+                                           const ModuleId& child_module,
+                                           const size_t& child_index,
+                                           const size_t& child_instance) {
+
+  for (size_t iport = 0; iport < sram_output_ports.size(); ++iport) {
+    std::string port_name;
+    if (0 == iport) {
+      port_name = generate_configurable_memory_data_out_name();
+    } else {
+      VTR_ASSERT( 1 == iport);
+      port_name = generate_configurable_memory_inverted_data_out_name();
+    }
+    add_module_output_nets_to_chain_mem_modules(module_manager, mem_module, 
+                                                port_name, circuit_lib, sram_output_ports[iport],
+                                                child_module, child_index, child_instance);
+  }
+}
+
 /********************************************************************
  * Connect all the memory modules under the parent module in a chain
  * 
@@ -273,9 +277,14 @@ void add_module_nets_to_cmos_memory_chain_module(ModuleManager& module_manager,
 }
 
 /*********************************************************************
- * Flat memory modules 
+ * Flatten memory organization
  *
- *        in[0]        in[1]           in[N]
+ *           Bit lines(BL/BLB) Word lines (WL/WLB)
+ *               |               |
+ *               v               v
+ *      +------------------------------------+
+ *      |   Memory Module Configuration port |
+ *      +------------------------------------+
  *          |            |               |
  *          v            v               v
  *      +-------+    +-------+       +-------+
@@ -289,33 +298,49 @@ void add_module_nets_to_cmos_memory_chain_module(ModuleManager& module_manager,
  *
  ********************************************************************/
 static 
-void build_memory_standalone_module(ModuleManager& module_manager,
-                                    const CircuitLibrary& circuit_lib,
-                                    const std::string& module_name,
-                                    const CircuitModelId& sram_model,
-                                    const size_t& num_mems) {
+void build_memory_flatten_module(ModuleManager& module_manager,
+                                 const CircuitLibrary& circuit_lib,
+                                 const std::string& module_name,
+                                 const CircuitModelId& sram_model,
+                                 const size_t& num_mems) {
   /* Get the global ports required by the SRAM */
   std::vector<enum e_circuit_model_port_type> global_port_types;
   global_port_types.push_back(CIRCUIT_MODEL_PORT_CLOCK);
   global_port_types.push_back(CIRCUIT_MODEL_PORT_INPUT);
   std::vector<CircuitPortId> sram_global_ports = circuit_lib.model_global_ports_by_type(sram_model, global_port_types, true, false);
-  /* Get the input ports from the SRAM */
-  std::vector<CircuitPortId> sram_input_ports = circuit_lib.model_ports_by_type(sram_model, CIRCUIT_MODEL_PORT_INPUT, true);
+  /* Get the BL/WL ports from the SRAM */
+  std::vector<CircuitPortId> sram_bl_ports = circuit_lib.model_ports_by_type(sram_model, CIRCUIT_MODEL_PORT_BL, true);
+  std::vector<CircuitPortId> sram_wl_ports = circuit_lib.model_ports_by_type(sram_model, CIRCUIT_MODEL_PORT_WL, true);
   /* Get the output ports from the SRAM */
   std::vector<CircuitPortId> sram_output_ports = circuit_lib.model_ports_by_type(sram_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
 
+  /* Ensure that we have only 1 BL, 1 WL and 2 output ports*/
+  VTR_ASSERT(1 == sram_bl_ports.size());
+  VTR_ASSERT(1 == sram_wl_ports.size());
+  VTR_ASSERT(2 == sram_output_ports.size());
+
   /* Create a module and add to the module manager */
   ModuleId mem_module = module_manager.add_module(module_name); 
   VTR_ASSERT(true == module_manager.valid_module_id(mem_module));
   
-  /* Add each input port */
-  for (const auto& port : sram_input_ports) {
-    BasicPort input_port(circuit_lib.port_prefix(port), num_mems);
-    module_manager.add_port(mem_module, input_port, ModuleManager::MODULE_INPUT_PORT);
-  }
+  /* Add module ports */
+  /* Input: BL port */
+  BasicPort bl_port(std::string(MEMORY_BL_PORT_NAME), num_mems);
+  ModulePortId mem_bl_port = module_manager.add_port(mem_module, bl_port, ModuleManager::MODULE_INPUT_PORT);
+
+  BasicPort wl_port(std::string(MEMORY_BL_PORT_NAME), num_mems);
+  ModulePortId mem_wl_port = module_manager.add_port(mem_module, wl_port, ModuleManager::MODULE_INPUT_PORT);
+
   /* Add each output port: port width should match the number of memories */
-  for (const auto& port : sram_output_ports) {
-    BasicPort output_port(circuit_lib.port_prefix(port), num_mems);
+  for (size_t iport = 0; iport < sram_output_ports.size(); ++iport) {
+    std::string port_name;
+    if (0 == iport) {
+      port_name = generate_configurable_memory_data_out_name();
+    } else {
+      VTR_ASSERT( 1 == iport);
+      port_name = generate_configurable_memory_inverted_data_out_name();
+    }
+    BasicPort output_port(port_name, num_mems);
     module_manager.add_port(mem_module, output_port, ModuleManager::MODULE_OUTPUT_PORT);
   }
 
@@ -330,8 +355,13 @@ void build_memory_standalone_module(ModuleManager& module_manager,
 
     /* Build module nets */
     /* Wire inputs of parent module to inputs of child modules */
-    add_module_input_nets_to_mem_modules(module_manager, mem_module, circuit_lib, sram_input_ports, sram_mem_module, i, sram_mem_instance);
-    /* Wire inputs of parent module to outputs of child modules */
+    for (const CircuitPortId& port : sram_bl_ports) {
+      add_module_input_nets_to_mem_modules(module_manager, mem_module, mem_bl_port, circuit_lib, port, sram_mem_module, i, sram_mem_instance);
+    }
+    for (const CircuitPortId& port : sram_wl_ports) {
+      add_module_input_nets_to_mem_modules(module_manager, mem_module, mem_wl_port, circuit_lib, port, sram_mem_module, i, sram_mem_instance);
+    }
+    /* Wire outputs of child module to outputs of parent module */
     add_module_output_nets_to_mem_modules(module_manager, mem_module, circuit_lib, sram_output_ports, sram_mem_module, i, sram_mem_instance);
   }
 
@@ -448,113 +478,6 @@ void build_memory_chain_module(ModuleManager& module_manager,
   add_module_global_ports_from_child_modules(module_manager, mem_module);
 }
 
-/*********************************************************************
- * Memory bank organization
- *
- *           Bit lines(BL/BLB) Word lines (WL/WLB)
- *               |               |
- *               v               v
- *      +------------------------------------+
- *      |   Memory Module Configuration port |
- *      +------------------------------------+
- *          |            |               |
- *          v            v               v
- *      +-------+    +-------+       +-------+
- *      | SRAM  |    | SRAM  |  ...  | SRAM  |
- *      |  [0]  |    |  [1]  |       | [N-1] |
- *      +-------+    +-------+       +-------+
- *          |            |      ...      |
- *          v            v               v
- *      +------------------------------------+
- *      |   Multiplexer Configuration port   |
- *
- ********************************************************************/
-static 
-void build_memory_bank_module(ModuleManager& module_manager,
-                              const CircuitLibrary& circuit_lib,
-                              const std::string& module_name,
-                              const CircuitModelId& sram_model,
-                              const size_t& num_mems) {
-  /* Get the global ports required by the SRAM */
-  std::vector<enum e_circuit_model_port_type> global_port_types;
-  global_port_types.push_back(CIRCUIT_MODEL_PORT_CLOCK);
-  global_port_types.push_back(CIRCUIT_MODEL_PORT_INPUT);
-  std::vector<CircuitPortId> sram_global_ports = circuit_lib.model_global_ports_by_type(sram_model, global_port_types, true, false);
-  /* Get the input ports from the SRAM */
-  std::vector<CircuitPortId> sram_input_ports = circuit_lib.model_ports_by_type(sram_model, CIRCUIT_MODEL_PORT_INPUT, true);
-  /* A SRAM cell with BL/WL should not have any input */
-  VTR_ASSERT( 0 == sram_input_ports.size() );
-  /* Get the output ports from the SRAM */
-  std::vector<CircuitPortId> sram_output_ports = circuit_lib.model_ports_by_type(sram_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
-  /* Get the BL/WL ports from the SRAM */
-  std::vector<CircuitPortId> sram_bl_ports  = circuit_lib.model_ports_by_type(sram_model, CIRCUIT_MODEL_PORT_BL, true);
-  std::vector<CircuitPortId> sram_blb_ports = circuit_lib.model_ports_by_type(sram_model, CIRCUIT_MODEL_PORT_BLB, true);
-  std::vector<CircuitPortId> sram_wl_ports  = circuit_lib.model_ports_by_type(sram_model, CIRCUIT_MODEL_PORT_WL, true);
-  std::vector<CircuitPortId> sram_wlb_ports = circuit_lib.model_ports_by_type(sram_model, CIRCUIT_MODEL_PORT_WLB, true);
-
-  /* Create a module and add to the module manager */
-  ModuleId mem_module = module_manager.add_module(module_name); 
-  VTR_ASSERT(true == module_manager.valid_module_id(mem_module));
-  
-  /* Add module ports: the ports come from the SRAM modules */
-  /* Add each input port */
-  for (const auto& port : sram_input_ports) {
-    BasicPort input_port(circuit_lib.port_prefix(port), num_mems * circuit_lib.port_size(port));
-    module_manager.add_port(mem_module, input_port, ModuleManager::MODULE_INPUT_PORT);
-  }
-  /* Add each output port: port width should match the number of memories */
-  for (const auto& port : sram_output_ports) {
-    BasicPort output_port(circuit_lib.port_prefix(port), num_mems * circuit_lib.port_size(port));
-    module_manager.add_port(mem_module, output_port, ModuleManager::MODULE_OUTPUT_PORT);
-  }
-  /* Add each output port: port width should match the number of memories */
-  for (const auto& port : sram_bl_ports) {
-    BasicPort bl_port(circuit_lib.port_prefix(port), num_mems * circuit_lib.port_size(port));
-    module_manager.add_port(mem_module, bl_port, ModuleManager::MODULE_INPUT_PORT);
-  }
-  for (const auto& port : sram_blb_ports) {
-    BasicPort blb_port(circuit_lib.port_prefix(port), num_mems * circuit_lib.port_size(port));
-    module_manager.add_port(mem_module, blb_port, ModuleManager::MODULE_INPUT_PORT);
-  }
-  for (const auto& port : sram_wl_ports) {
-    BasicPort wl_port(circuit_lib.port_prefix(port), num_mems * circuit_lib.port_size(port));
-    module_manager.add_port(mem_module, wl_port, ModuleManager::MODULE_INPUT_PORT);
-  }
-  for (const auto& port : sram_wlb_ports) {
-    BasicPort wlb_port(circuit_lib.port_prefix(port), num_mems * circuit_lib.port_size(port));
-    module_manager.add_port(mem_module, wlb_port, ModuleManager::MODULE_INPUT_PORT);
-  }
-
-  /* Find the sram module in the module manager */
-  ModuleId sram_mem_module = module_manager.find_module(circuit_lib.model_name(sram_model));
-
-  /* Instanciate each submodule */
-  for (size_t i = 0; i < num_mems; ++i) {
-    /* Memory seed module instanciation */
-    size_t sram_instance = module_manager.num_instance(mem_module, sram_mem_module);
-    module_manager.add_child_module(mem_module, sram_mem_module);
-
-    /* Build module nets */
-    /* Wire inputs of parent module to inputs of child modules */
-    add_module_input_nets_to_mem_modules(module_manager, mem_module, circuit_lib, sram_input_ports, sram_mem_module, i, sram_instance);
-    /* Wire inputs of parent module to outputs of child modules */
-    add_module_output_nets_to_mem_modules(module_manager, mem_module, circuit_lib, sram_output_ports, sram_mem_module, i, sram_instance);
-    /* Wire BL/WLs of parent module to BL/WLs of child modules */
-    add_module_input_nets_to_mem_modules(module_manager, mem_module, circuit_lib, sram_bl_ports, sram_mem_module, i, sram_instance);
-    add_module_input_nets_to_mem_modules(module_manager, mem_module, circuit_lib, sram_blb_ports, sram_mem_module, i, sram_instance);
-    add_module_input_nets_to_mem_modules(module_manager, mem_module, circuit_lib, sram_wl_ports, sram_mem_module, i, sram_instance);
-    add_module_input_nets_to_mem_modules(module_manager, mem_module, circuit_lib, sram_wlb_ports, sram_mem_module, i, sram_instance);
-  }
-
-  /* TODO: if a local memory decoder is required, instanciate it here */
-
-  /* Add global ports to the pb_module:
-   * This is a much easier job after adding sub modules (instances), 
-   * we just need to find all the global ports from the child modules and build a list of it
-   */
-  add_module_global_ports_from_child_modules(module_manager, mem_module);
-}
-
 /*********************************************************************
  * Frame-based Memory organization
  *
@@ -773,17 +696,14 @@ void build_memory_module(ModuleManager& module_manager,
                          const size_t& num_mems) {
   switch (sram_orgz_type) {
   case CONFIG_MEM_STANDALONE:
-    build_memory_standalone_module(module_manager, circuit_lib, 
-                                   module_name, sram_model, num_mems);
+  case CONFIG_MEM_MEMORY_BANK:
+    build_memory_flatten_module(module_manager, circuit_lib, 
+                                module_name, sram_model, num_mems);
     break;
   case CONFIG_MEM_SCAN_CHAIN:
     build_memory_chain_module(module_manager, circuit_lib,  
                               module_name, sram_model, num_mems);
     break;
-  case CONFIG_MEM_MEMORY_BANK:
-    build_memory_bank_module(module_manager, circuit_lib,
-                             module_name, sram_model, num_mems);
-    break;
   case CONFIG_MEM_FRAME_BASED:
     build_frame_memory_module(module_manager, arch_decoder_lib, circuit_lib,
                               module_name, sram_model, num_mems);

From fbe05963e00e7203f2e236643c42198952e63e00 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 29 May 2020 22:41:56 -0600
Subject: [PATCH 597/645] add configuration bus builder for flatten memory
 organization (applicable to memory bank and standalone configuration
 protocol)

---
 openfpga/src/base/openfpga_naming.cpp       |  36 ++----
 openfpga/src/utils/memory_utils.cpp         |   7 +-
 openfpga/src/utils/module_manager_utils.cpp | 131 +++++++++++++++++---
 openfpga/src/utils/module_manager_utils.h   |  12 ++
 4 files changed, 139 insertions(+), 47 deletions(-)

diff --git a/openfpga/src/base/openfpga_naming.cpp b/openfpga/src/base/openfpga_naming.cpp
index dd5e7df2c..5cf00bf7f 100644
--- a/openfpga/src/base/openfpga_naming.cpp
+++ b/openfpga/src/base/openfpga_naming.cpp
@@ -744,19 +744,6 @@ std::string generate_sram_port_name(const e_config_protocol_type& sram_orgz_type
   std::string port_name;
 
   switch (sram_orgz_type) {
-  case CONFIG_MEM_STANDALONE: {
-    /* Two types of ports are available:  
-     * (1) Regular output of a SRAM, enabled by port type of INPUT
-     * (2) Inverted output of a SRAM, enabled by port type of OUTPUT
-     */
-    if (CIRCUIT_MODEL_PORT_INPUT == port_type) {
-      port_name = std::string("mem_out"); 
-    } else {
-      VTR_ASSERT( CIRCUIT_MODEL_PORT_OUTPUT == port_type );
-      port_name = std::string("mem_outb"); 
-    }
-    break;
-  }
   case CONFIG_MEM_SCAN_CHAIN:
     /* Two types of ports are available:  
      * (1) Head of a chain of Configuration-chain Flip-Flops (CCFFs), enabled by port type of INPUT
@@ -772,30 +759,25 @@ std::string generate_sram_port_name(const e_config_protocol_type& sram_orgz_type
       port_name = std::string("ccff_tail"); 
     }
     break;
+  case CONFIG_MEM_STANDALONE:
   case CONFIG_MEM_MEMORY_BANK:
-    /* Four types of ports are available:  
+    /* Two types of ports are available:  
      * (1) Bit Lines (BLs) of a SRAM cell, enabled by port type of BL
      * (2) Word Lines (WLs) of a SRAM cell, enabled by port type of WL
-     * (3) Inverted Bit Lines (BLBs) of a SRAM cell, enabled by port type of BLB
-     * (4) Inverted Word Lines (WLBs) of a SRAM cell, enabled by port type of WLB
      *
-     *           BL BLB WL WLB    BL BLB WL WLB    BL BLB WL WLB
-     *          [0] [0] [0] [0]  [1] [1] [1] [1]  [i] [i] [i] [i]
-     *            ^  ^  ^  ^       ^  ^  ^  ^       ^  ^  ^  ^
-     *            |  |  |  |       |  |  |  |       |  |  |  |
+     *           BL     WL        BL     WL        BL     WL    
+     *          [0]     [0]      [1]     [1]      [i]     [i]    
+     *            ^     ^          ^     ^          ^     ^    
+     *            |     |          |     |          |     |    
      *           +----------+     +----------+     +----------+
      *           |   SRAM   |     |   SRAM   | ... |   SRAM   |         
      *           +----------+     +----------+     +----------+
      */
     if (CIRCUIT_MODEL_PORT_BL == port_type) {
-      port_name = std::string("bl"); 
-    } else if (CIRCUIT_MODEL_PORT_WL == port_type) {
-      port_name = std::string("wl"); 
-    } else if (CIRCUIT_MODEL_PORT_BLB == port_type) {
-      port_name = std::string("blb"); 
+      port_name = std::string(MEMORY_BL_PORT_NAME); 
     } else {
-      VTR_ASSERT( CIRCUIT_MODEL_PORT_WLB == port_type );
-      port_name = std::string("wlb"); 
+      VTR_ASSERT( CIRCUIT_MODEL_PORT_WL == port_type );
+      port_name = std::string(MEMORY_WL_PORT_NAME); 
     }
     break;
   case CONFIG_MEM_FRAME_BASED:
diff --git a/openfpga/src/utils/memory_utils.cpp b/openfpga/src/utils/memory_utils.cpp
index 05b6e8736..bb7cefee7 100644
--- a/openfpga/src/utils/memory_utils.cpp
+++ b/openfpga/src/utils/memory_utils.cpp
@@ -314,20 +314,15 @@ std::vector<std::string> generate_sram_port_names(const CircuitLibrary& circuit_
   std::vector<e_circuit_model_port_type> model_port_types; 
 
   switch (sram_orgz_type) {
-  case CONFIG_MEM_STANDALONE: 
-    model_port_types.push_back(CIRCUIT_MODEL_PORT_INPUT);
-    model_port_types.push_back(CIRCUIT_MODEL_PORT_OUTPUT);
-    break;
   case CONFIG_MEM_SCAN_CHAIN: 
     model_port_types.push_back(CIRCUIT_MODEL_PORT_INPUT);
     model_port_types.push_back(CIRCUIT_MODEL_PORT_OUTPUT);
     break;
+  case CONFIG_MEM_STANDALONE: 
   case CONFIG_MEM_MEMORY_BANK: {
     std::vector<e_circuit_model_port_type> ports_to_search;
     ports_to_search.push_back(CIRCUIT_MODEL_PORT_BL);
     ports_to_search.push_back(CIRCUIT_MODEL_PORT_WL);
-    ports_to_search.push_back(CIRCUIT_MODEL_PORT_BLB);
-    ports_to_search.push_back(CIRCUIT_MODEL_PORT_WLB);
     /* Try to find a BL/WL/BLB/WLB port and update the port types/module port types to be added */
     for (const auto& port_to_search : ports_to_search) {
       std::vector<CircuitPortId> found_port = circuit_lib.model_ports_by_type(sram_model, port_to_search);
diff --git a/openfpga/src/utils/module_manager_utils.cpp b/openfpga/src/utils/module_manager_utils.cpp
index eebe9008a..cf9808466 100644
--- a/openfpga/src/utils/module_manager_utils.cpp
+++ b/openfpga/src/utils/module_manager_utils.cpp
@@ -664,6 +664,85 @@ void add_module_nets_between_logic_and_memory_sram_bus(ModuleManager& module_man
   }
 }
 
+/********************************************************************
+ * Connect all the memory modules under the parent module in a flatten way
+ *
+ *   BL
+ *   |
+ *   +---------------+--------- ... --------+
+ *   |               |                      |
+ *   v               v                      v
+ *  +--------+    +--------+            +--------+
+ *  | Memory |    | Memory |    ...     | Memory |               
+ *  | Module |    | Module |            | Module |
+ *  |   [0]  |    |   [1]  |            |  [N-1] |             
+ *  +--------+    +--------+            +--------+
+ *      ^            ^                      ^
+ *      |            |                      |
+ *      +------------+----------------------+
+ *      |
+ *     WL
+ * 
+ * Note: 
+ *   - This function will do the connection for only one type of the port,
+ *      either BL or WL. So, you should call this function twice to complete 
+ *      the configuration bus connection!!!
+ *
+ *********************************************************************/
+void add_module_nets_cmos_flatten_memory_config_bus(ModuleManager& module_manager,
+                                                    const ModuleId& parent_module,
+                                                    const e_config_protocol_type& sram_orgz_type,
+                                                    const e_circuit_model_port_type& config_port_type) {
+  /* A counter for the current pin id for the source port of parent module */
+  size_t cur_src_pin_id = 0;
+
+  ModuleId net_src_module_id;
+  size_t net_src_instance_id;
+  ModulePortId net_src_port_id;
+
+  /* Find the port name of parent module */
+  std::string src_port_name = generate_sram_port_name(sram_orgz_type, config_port_type);
+  net_src_module_id = parent_module; 
+  net_src_instance_id = 0;
+  net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name); 
+
+  /* Get the pin id for source port */
+  BasicPort net_src_port = module_manager.module_port(net_src_module_id, net_src_port_id); 
+
+  for (size_t mem_index = 0; mem_index < module_manager.configurable_children(parent_module).size(); ++mem_index) {
+    ModuleId net_sink_module_id;
+    size_t net_sink_instance_id;
+    ModulePortId net_sink_port_id;
+
+    /* Find the port name of next memory module */
+    std::string sink_port_name = generate_sram_port_name(sram_orgz_type, config_port_type);
+    net_sink_module_id = module_manager.configurable_children(parent_module)[mem_index]; 
+    net_sink_instance_id = module_manager.configurable_child_instances(parent_module)[mem_index];
+    net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name); 
+
+    /* Get the pin id for sink port */
+    BasicPort net_sink_port = module_manager.module_port(net_sink_module_id, net_sink_port_id); 
+    
+    /* Create a net for each pin */
+    for (size_t pin_id = 0; pin_id < net_sink_port.pins().size(); ++pin_id) {
+      /* Create a net and add source and sink to it */
+      ModuleNetId net = create_module_source_pin_net(module_manager, parent_module, 
+                                                     net_src_module_id, net_src_instance_id, 
+                                                     net_src_port_id, net_src_port.pins()[cur_src_pin_id]);
+      VTR_ASSERT(ModuleNetId::INVALID() != net);
+
+      /* Add net sink */
+      module_manager.add_module_net_sink(parent_module, net, net_sink_module_id, net_sink_instance_id, net_sink_port_id, net_sink_port.pins()[pin_id]);
+
+      /* Move to the next src pin */
+      cur_src_pin_id++;
+    }
+  }
+
+  /* We should used all the pins of the source port!!! */
+  VTR_ASSERT(net_src_port.get_width() == cur_src_pin_id);
+}
+
 /********************************************************************
  * Connect all the memory modules under the parent module in a chain
  * 
@@ -1088,18 +1167,19 @@ void add_module_nets_cmos_memory_config_bus(ModuleManager& module_manager,
                                             const ModuleId& parent_module,
                                             const e_config_protocol_type& sram_orgz_type) {
   switch (sram_orgz_type) {
-  case CONFIG_MEM_STANDALONE:
-    /* Nothing to do */
-    break;
   case CONFIG_MEM_SCAN_CHAIN: {
-    add_module_nets_cmos_memory_chain_config_bus(module_manager, parent_module, sram_orgz_type);
+    add_module_nets_cmos_memory_chain_config_bus(module_manager, parent_module,
+                                                 sram_orgz_type);
     break;
   }
+  case CONFIG_MEM_STANDALONE:
   case CONFIG_MEM_MEMORY_BANK:
-    /* TODO: */
+    add_module_nets_cmos_flatten_memory_config_bus(module_manager, parent_module,
+                                                   sram_orgz_type, CIRCUIT_MODEL_PORT_BL);
+    add_module_nets_cmos_flatten_memory_config_bus(module_manager, parent_module,
+                                                   sram_orgz_type, CIRCUIT_MODEL_PORT_WL);
     break;
   case CONFIG_MEM_FRAME_BASED:
-    /* TODO: */
     add_module_nets_cmos_memory_frame_config_bus(module_manager, decoder_lib, parent_module);
     break;
   default:
@@ -1557,6 +1637,32 @@ size_t find_module_num_config_bits_from_child_modules(ModuleManager& module_mana
   return num_config_bits;
 }
 
+/********************************************************************
+ * Try to create a net for the source pin
+ * This function will try
+ *   - Find if there is already a net created whose source is the pin
+ *     If so, it will return the net id
+ *   - If not, it will create a net and configure its source
+ *******************************************************************/
+ModuleNetId create_module_source_pin_net(ModuleManager& module_manager,
+                                         const ModuleId& cur_module_id,
+                                         const ModuleId& src_module_id,
+                                         const size_t& src_instance_id,
+                                         const ModulePortId& src_module_port_id,
+                                         const size_t& src_pin_id) {
+  ModuleNetId net = module_manager.module_instance_port_net(cur_module_id,
+                                                            src_module_id, src_instance_id, 
+                                                            src_module_port_id, src_pin_id);
+  if (ModuleNetId::INVALID() == net) { 
+    net = module_manager.create_module_net(cur_module_id);
+    module_manager.add_module_net_source(cur_module_id, net,
+                                         src_module_id, src_instance_id,
+                                         src_module_port_id, src_pin_id);
+  }
+
+  return net;
+}
+
 /********************************************************************
  * Add a bus of nets to a module (cur_module_id)
  * Note: 
@@ -1609,14 +1715,11 @@ void add_module_bus_nets(ModuleManager& module_manager,
 
   /* Create a net for each pin */
   for (size_t pin_id = 0; pin_id < src_port.pins().size(); ++pin_id) {
-    ModuleNetId net = module_manager.module_instance_port_net(cur_module_id,
-                                                              src_module_id, src_instance_id, 
-                                                              src_module_port_id, src_port.pins()[pin_id]);
-    if (ModuleNetId::INVALID() == net) { 
-      net = module_manager.create_module_net(cur_module_id);
-      /* Configure the net source */
-      module_manager.add_module_net_source(cur_module_id, net, src_module_id, src_instance_id, src_module_port_id, src_port.pins()[pin_id]);
-    }
+    ModuleNetId net = create_module_source_pin_net(module_manager, cur_module_id, 
+                                                   src_module_id, src_instance_id, 
+                                                   src_module_port_id, src_port.pins()[pin_id]);
+    VTR_ASSERT(ModuleNetId::INVALID() != net);
+
     /* Configure the net sink */
     module_manager.add_module_net_sink(cur_module_id, net, des_module_id, des_instance_id, des_module_port_id, des_port.pins()[pin_id]);
   }
diff --git a/openfpga/src/utils/module_manager_utils.h b/openfpga/src/utils/module_manager_utils.h
index d52727a40..640d798ab 100644
--- a/openfpga/src/utils/module_manager_utils.h
+++ b/openfpga/src/utils/module_manager_utils.h
@@ -91,6 +91,11 @@ void add_module_nets_between_logic_and_memory_sram_bus(ModuleManager& module_man
                                                        const CircuitLibrary& circuit_lib,
                                                        const CircuitModelId& logic_model);
 
+void add_module_nets_cmos_flatten_memory_config_bus(ModuleManager& module_manager,
+                                                    const ModuleId& parent_module,
+                                                    const e_config_protocol_type& sram_orgz_type,
+                                                    const e_circuit_model_port_type& config_port_type);
+
 void add_module_nets_cmos_memory_chain_config_bus(ModuleManager& module_manager,
                                                   const ModuleId& parent_module,
                                                   const e_config_protocol_type& sram_orgz_type);
@@ -135,6 +140,13 @@ size_t find_module_num_config_bits_from_child_modules(ModuleManager& module_mana
                                                       const CircuitModelId& sram_model,
                                                       const e_config_protocol_type& sram_orgz_type);
 
+ModuleNetId create_module_source_pin_net(ModuleManager& module_manager,
+                                         const ModuleId& cur_module_id,
+                                         const ModuleId& src_module_id,
+                                         const size_t& src_instance_id,
+                                         const ModulePortId& src_module_port_id,
+                                         const size_t& src_pin_id);
+
 void add_module_bus_nets(ModuleManager& module_manager,
                          const ModuleId& cur_module_id,
                          const ModuleId& src_module_id,

From b9aac3cbdf70ebe3e17ccf6e1a3ba2710d5757e6 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 29 May 2020 23:22:01 -0600
Subject: [PATCH 598/645] updated fpga verilog testbench generation to support
 vanilla (standalone) configuration protocol

---
 .../src/fabric/build_top_module_memory.cpp    |   7 +-
 .../fpga_verilog/verilog_top_testbench.cpp    | 128 +++++++++++++++++-
 2 files changed, 131 insertions(+), 4 deletions(-)

diff --git a/openfpga/src/fabric/build_top_module_memory.cpp b/openfpga/src/fabric/build_top_module_memory.cpp
index c15070488..b5d7f1db1 100644
--- a/openfpga/src/fabric/build_top_module_memory.cpp
+++ b/openfpga/src/fabric/build_top_module_memory.cpp
@@ -413,14 +413,17 @@ void add_top_module_nets_cmos_memory_config_bus(ModuleManager& module_manager,
                                                 const e_config_protocol_type& sram_orgz_type) {
   switch (sram_orgz_type) {
   case CONFIG_MEM_STANDALONE:
-    /* Nothing to do */
+    add_module_nets_cmos_flatten_memory_config_bus(module_manager, parent_module,
+                                                   sram_orgz_type, CIRCUIT_MODEL_PORT_BL);
+    add_module_nets_cmos_flatten_memory_config_bus(module_manager, parent_module,
+                                                   sram_orgz_type, CIRCUIT_MODEL_PORT_WL);
     break;
   case CONFIG_MEM_SCAN_CHAIN: {
     add_module_nets_cmos_memory_chain_config_bus(module_manager, parent_module, CONFIG_MEM_SCAN_CHAIN);
     break;
   }
   case CONFIG_MEM_MEMORY_BANK:
-    /* TODO: */
+    /* TODO */
     break;
   case CONFIG_MEM_FRAME_BASED:
     add_module_nets_cmos_memory_frame_config_bus(module_manager, decoder_lib, parent_module);
diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
index 4a1072c70..7ece43460 100644
--- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
@@ -60,6 +60,30 @@ constexpr char* TOP_TB_CLOCK_REG_POSTFIX = "_reg";
 
 constexpr char* AUTOCHECK_TOP_TESTBENCH_VERILOG_MODULE_POSTFIX = "_autocheck_top_tb";
 
+/********************************************************************
+ * Print local wires for flatten memory (standalone) configuration protocols
+ *******************************************************************/
+static 
+void print_verilog_top_testbench_flatten_memory_port(std::fstream& fp,
+                                                     const ModuleManager& module_manager,
+                                                     const ModuleId& top_module) {
+  /* Validate the file stream */
+  valid_file_stream(fp);
+
+  /* Print the port for Bit-Line */
+  print_verilog_comment(fp, std::string("---- Bit Line ports -----"));
+  ModulePortId bl_port_id = module_manager.find_module_port(top_module, std::string(MEMORY_BL_PORT_NAME));
+  BasicPort bl_port = module_manager.module_port(top_module, bl_port_id);
+  fp << generate_verilog_port(VERILOG_PORT_REG, bl_port) << ";" << std::endl;
+
+  /* Print the port for Word-Line */
+  print_verilog_comment(fp, std::string("---- Word Line ports -----"));
+  ModulePortId wl_port_id = module_manager.find_module_port(top_module, std::string(MEMORY_WL_PORT_NAME));
+  BasicPort wl_port = module_manager.module_port(top_module, wl_port_id);
+  fp << generate_verilog_port(VERILOG_PORT_REG, wl_port) << ";" << std::endl;
+}
+
+
 /********************************************************************
  * Print local wires for configuration chain protocols
  *******************************************************************/
@@ -125,7 +149,7 @@ void print_verilog_top_testbench_config_protocol_port(std::fstream& fp,
                                                       const ModuleId& top_module) {
   switch(sram_orgz_type) {
   case CONFIG_MEM_STANDALONE:
-    /* TODO */
+    print_verilog_top_testbench_flatten_memory_port(fp, module_manager, top_module);
     break;
   case CONFIG_MEM_SCAN_CHAIN:
     print_verilog_top_testbench_config_chain_port(fp);
@@ -498,6 +522,11 @@ size_t calculate_num_config_clock_cycles(const e_config_protocol_type& sram_orgz
   /* Branch on the type of configuration protocol */
   switch (sram_orgz_type) {
   case CONFIG_MEM_STANDALONE:
+    /* We just need 1 clock cycle to load all the configuration bits 
+     * since all the ports are exposed at the top-level
+     */
+    num_config_clock_cycles = 2;
+    break;
   case CONFIG_MEM_SCAN_CHAIN:
   case CONFIG_MEM_MEMORY_BANK:
     /* TODO */
@@ -692,6 +721,7 @@ void print_verilog_top_testbench_load_bitstream_task(std::fstream& fp,
                                                      const ModuleId& top_module) {
   switch (sram_orgz_type) {
   case CONFIG_MEM_STANDALONE:
+    /* No need to have a specific task. Loading is done in 1 clock cycle */
     break;
   case CONFIG_MEM_SCAN_CHAIN:
     print_verilog_top_testbench_load_bitstream_task_configuration_chain(fp);
@@ -845,6 +875,98 @@ void print_verilog_top_testbench_generic_stimulus(std::fstream& fp,
   fp << std::endl;
 }
 
+/********************************************************************
+ * Print stimulus for a FPGA fabric with a flatten memory (standalone) configuration protocol 
+ * We will load the bitstream in the second clock cycle, right after the first reset cycle
+ *******************************************************************/
+static 
+void print_verilog_top_testbench_vanilla_bitstream(std::fstream& fp,
+                                                   const ModuleManager& module_manager,
+                                                   const ModuleId& top_module,
+                                                   const BitstreamManager& bitstream_manager,
+                                                   const FabricBitstream& fabric_bitstream) {
+  /* Validate the file stream */
+  valid_file_stream(fp);
+
+  /* Find Bit-Line and Word-Line port */
+  BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME), 1);
+
+  /* Find Bit-Line and Word-Line port */
+  ModulePortId bl_port_id = module_manager.find_module_port(top_module, std::string(MEMORY_BL_PORT_NAME));
+  BasicPort bl_port = module_manager.module_port(top_module, bl_port_id);
+
+  ModulePortId wl_port_id = module_manager.find_module_port(top_module, std::string(MEMORY_WL_PORT_NAME));
+  BasicPort wl_port = module_manager.module_port(top_module, wl_port_id);
+
+  /* Initial value should be the first configuration bits
+   * In the rest of programming cycles, 
+   * configuration bits are fed at the falling edge of programming clock.
+   * We do not care the value of scan_chain head during the first programming cycle 
+   * It is reset anyway
+   */
+  std::vector<size_t> initial_bl_values(bl_port.get_width(), 0);
+  std::vector<size_t> initial_wl_values(wl_port.get_width(), 0);
+
+  print_verilog_comment(fp, "----- Begin bitstream loading during configuration phase -----");
+  fp << "initial" << std::endl;
+  fp << "\tbegin" << std::endl;
+  print_verilog_comment(fp, "----- Configuration chain default input -----");
+  fp << "\t\t";
+  fp << generate_verilog_port_constant_values(bl_port, initial_bl_values);
+  fp << ";";
+  fp << "\t\t";
+  fp << generate_verilog_port_constant_values(wl_port, initial_wl_values);
+  fp << ";";
+
+  fp << std::endl;
+
+  fp << "\t\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ");" << std::endl;
+  fp << "\t\t\t"; 
+
+  /* Enable all the WLs */
+  std::vector<size_t> enabled_wl_values(wl_port.get_width(), 1);
+  fp << generate_verilog_port(VERILOG_PORT_CONKT, wl_port);
+  fp << " = "; 
+  fp << generate_verilog_port_constant_values(wl_port, enabled_wl_values);
+
+  size_t ibit = 0;
+  for (const FabricBitId& bit_id : fabric_bitstream.bits()) {
+    BasicPort cur_bl_port(bl_port);
+    cur_bl_port.set_width(ibit, ibit);
+
+    fp << generate_verilog_port(VERILOG_PORT_CONKT, cur_bl_port);
+    fp << " = "; 
+    fp << "1'b" << (size_t)bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id));
+    fp << ";" << std::endl;
+
+    ibit++;
+  }
+
+  fp << "\tend" << std::endl;
+
+  /* Disable all the WLs */
+  fp << "\t\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ");" << std::endl;
+  fp << generate_verilog_port(VERILOG_PORT_CONKT, wl_port);
+  fp << " = "; 
+  fp << generate_verilog_port_constant_values(wl_port, initial_wl_values);
+  fp << "\t\t\t"; 
+
+  /* Raise the flag of configuration done when bitstream loading is complete */
+  fp << "\t\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ");" << std::endl;
+  
+  BasicPort config_done_port(std::string(TOP_TB_CONFIG_DONE_PORT_NAME), 1);
+  fp << "\t\t\t";
+  fp << generate_verilog_port(VERILOG_PORT_CONKT, config_done_port);
+  fp << " <= ";
+  std::vector<size_t> config_done_enable_values(config_done_port.get_width(), 1);
+  fp << generate_verilog_constant_values(config_done_enable_values);
+  fp << ";" << std::endl;
+
+  fp << "\tend" << std::endl;
+  print_verilog_comment(fp, "----- End bitstream loading during configuration phase -----");
+}
+
+
 /********************************************************************
  * Print stimulus for a FPGA fabric with a configuration chain protocol 
  * where configuration bits are programming in serial (one by one)
@@ -1022,7 +1144,9 @@ void print_verilog_top_testbench_bitstream(std::fstream& fp,
   /* Branch on the type of configuration protocol */
   switch (sram_orgz_type) {
   case CONFIG_MEM_STANDALONE:
-    /* TODO */
+    print_verilog_top_testbench_vanilla_bitstream(fp, 
+                                                  module_manager, top_module,
+                                                  bitstream_manager, fabric_bitstream);
     break;
   case CONFIG_MEM_SCAN_CHAIN:
     print_verilog_top_testbench_configuration_chain_bitstream(fp, bitstream_manager, fabric_bitstream);

From 8b5b221a211ed2e41cbf4c6395de6c5f88da4635 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 30 May 2020 11:36:00 -0600
Subject: [PATCH 599/645] add new architecture for standalone memory
 organization

---
 .../k4_N4_40nm_standalone_openfpga.xml        | 229 ++++++++++++++++++
 1 file changed, 229 insertions(+)
 create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml

diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml
new file mode 100644
index 000000000..fc97f75c1
--- /dev/null
+++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml
@@ -0,0 +1,229 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="4"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="16"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="sram" name="config_latch" prefix="config_latch" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/config_latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/config_latch.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="bl" prefix="bl" size="1"/>
+       <port type="wl" prefix="wl" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="Qb" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="config_latch" default_val="1"/>
+      <port type="input" prefix="outpad" size="1"/>
+      <port type="output" prefix="inpad" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="standalone" circuit_model_name="config_latch"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="static_dff"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>
+<openfpga_simulation_setting>
+  <clock_setting>
+    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
+    <programming frequency="100e6"/>
+  </clock_setting>
+  <simulator_option>
+    <operating_condition temperature="25"/>
+    <output_log verbose="false" captab="false"/>
+    <accuracy type="abs" value="1e-13"/>
+    <runtime fast_simulation="true"/>
+  </simulator_option>
+  <monte_carlo num_simulation_points="2"/>
+  <measurement_setting>
+    <slew>
+      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
+      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
+    </slew>
+    <delay>
+      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
+      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
+    </delay>
+  </measurement_setting>
+  <stimulus>
+    <clock>
+      <rise slew_type="abs" slew_time="20e-12" />
+      <fall slew_type="abs" slew_time="20e-12" />
+    </clock>
+    <input>
+      <rise slew_type="abs" slew_time="25e-12" />
+      <fall slew_type="abs" slew_time="25e-12" />
+    </input>
+  </stimulus>
+</openfpga_simulation_setting>

From 5f6a790effffee2dd00a9af8e384ebde442773e3 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 30 May 2020 11:39:24 -0600
Subject: [PATCH 600/645] add new test cases for the standalone memory
 configuration protocol

---
 .../flatten_memory/config/task.conf           | 34 +++++++++++++++++++
 1 file changed, 34 insertions(+)
 create mode 100644 openfpga_flow/tasks/openfpga_shell/full_testbench/flatten_memory/config/task.conf

diff --git a/openfpga_flow/tasks/openfpga_shell/full_testbench/flatten_memory/config/task.conf b/openfpga_flow/tasks/openfpga_shell/full_testbench/flatten_memory/config/task.conf
new file mode 100644
index 000000000..d2bf1bb9f
--- /dev/null
+++ b/openfpga_flow/tasks/openfpga_shell/full_testbench/flatten_memory/config/task.conf
@@ -0,0 +1,34 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+#vpr_fpga_verilog_formal_verification_top_netlist=

From 8ec8ac41181b9e628bfa6b37033faff5a2f1e0e1 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 30 May 2020 12:16:41 -0600
Subject: [PATCH 601/645] bug fixed in flatten memory organization. Passed
 verification

---
 openfpga/src/fabric/build_memory_modules.cpp  |  4 +--
 .../fpga_verilog/verilog_top_testbench.cpp    | 21 ++++++-----
 .../src/fpga_verilog/verilog_writer_utils.cpp | 36 ++++++++++++++++---
 .../src/fpga_verilog/verilog_writer_utils.h   |  3 +-
 4 files changed, 45 insertions(+), 19 deletions(-)

diff --git a/openfpga/src/fabric/build_memory_modules.cpp b/openfpga/src/fabric/build_memory_modules.cpp
index f634408b1..72d1315ad 100644
--- a/openfpga/src/fabric/build_memory_modules.cpp
+++ b/openfpga/src/fabric/build_memory_modules.cpp
@@ -61,7 +61,7 @@ void add_module_input_nets_to_mem_modules(ModuleManager& module_manager,
     module_manager.add_module_net_source(mem_module, net, mem_module, 0, src_port_id, src_pin_id);
   }
 
-  for (size_t pin_id = 0; pin_id < module_manager.module_port(mem_module, sink_port_id).pins().size(); ++pin_id) {
+  for (size_t pin_id = 0; pin_id < module_manager.module_port(child_module, sink_port_id).pins().size(); ++pin_id) {
     /* Sink node of the input net is the input of sram module */
     size_t sink_pin_id = module_manager.module_port(child_module, sink_port_id).pins()[pin_id];
     module_manager.add_module_net_sink(mem_module, net, child_module, child_instance, sink_port_id, sink_pin_id);
@@ -328,7 +328,7 @@ void build_memory_flatten_module(ModuleManager& module_manager,
   BasicPort bl_port(std::string(MEMORY_BL_PORT_NAME), num_mems);
   ModulePortId mem_bl_port = module_manager.add_port(mem_module, bl_port, ModuleManager::MODULE_INPUT_PORT);
 
-  BasicPort wl_port(std::string(MEMORY_BL_PORT_NAME), num_mems);
+  BasicPort wl_port(std::string(MEMORY_WL_PORT_NAME), num_mems);
   ModulePortId mem_wl_port = module_manager.add_port(mem_module, wl_port, ModuleManager::MODULE_INPUT_PORT);
 
   /* Add each output port: port width should match the number of memories */
diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
index 7ece43460..68d1e3dba 100644
--- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
@@ -913,27 +913,27 @@ void print_verilog_top_testbench_vanilla_bitstream(std::fstream& fp,
   print_verilog_comment(fp, "----- Configuration chain default input -----");
   fp << "\t\t";
   fp << generate_verilog_port_constant_values(bl_port, initial_bl_values);
-  fp << ";";
+  fp << ";" << std::endl;
   fp << "\t\t";
   fp << generate_verilog_port_constant_values(wl_port, initial_wl_values);
-  fp << ";";
+  fp << ";" << std::endl;
 
   fp << std::endl;
 
-  fp << "\t\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ");" << std::endl;
-  fp << "\t\t\t"; 
+  fp << "\t\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ") begin" << std::endl;
 
   /* Enable all the WLs */
   std::vector<size_t> enabled_wl_values(wl_port.get_width(), 1);
-  fp << generate_verilog_port(VERILOG_PORT_CONKT, wl_port);
-  fp << " = "; 
+  fp << "\t\t\t"; 
   fp << generate_verilog_port_constant_values(wl_port, enabled_wl_values);
+  fp << ";" << std::endl;
 
   size_t ibit = 0;
   for (const FabricBitId& bit_id : fabric_bitstream.bits()) {
     BasicPort cur_bl_port(bl_port);
     cur_bl_port.set_width(ibit, ibit);
 
+    fp << "\t\t\t"; 
     fp << generate_verilog_port(VERILOG_PORT_CONKT, cur_bl_port);
     fp << " = "; 
     fp << "1'b" << (size_t)bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id));
@@ -942,14 +942,14 @@ void print_verilog_top_testbench_vanilla_bitstream(std::fstream& fp,
     ibit++;
   }
 
-  fp << "\tend" << std::endl;
+  fp << "\t\tend" << std::endl;
 
   /* Disable all the WLs */
   fp << "\t\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ");" << std::endl;
-  fp << generate_verilog_port(VERILOG_PORT_CONKT, wl_port);
-  fp << " = "; 
-  fp << generate_verilog_port_constant_values(wl_port, initial_wl_values);
+
   fp << "\t\t\t"; 
+  fp << generate_verilog_port_constant_values(wl_port, initial_wl_values);
+  fp << ";" << std::endl;
 
   /* Raise the flag of configuration done when bitstream loading is complete */
   fp << "\t\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ");" << std::endl;
@@ -966,7 +966,6 @@ void print_verilog_top_testbench_vanilla_bitstream(std::fstream& fp,
   print_verilog_comment(fp, "----- End bitstream loading during configuration phase -----");
 }
 
-
 /********************************************************************
  * Print stimulus for a FPGA fabric with a configuration chain protocol 
  * where configuration bits are programming in serial (one by one)
diff --git a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp
index 90ee95e9c..c59d92dd0 100644
--- a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp
+++ b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp
@@ -644,12 +644,38 @@ std::string generate_verilog_local_wire(const BasicPort& output_port,
 /********************************************************************
  * Generate a string for a constant value in Verilog format:
  *  <#.of bits>'b<binary numbers>
+ *
+ * Optimization: short_constant
+ *   When this switch is turned on, we will generate short version
+ *   for all-zero/all-one vectors
+ *   {<length>{1'b<zero/one>}}
  *******************************************************************/
-std::string generate_verilog_constant_values(const std::vector<size_t>& const_values) {
-  std::string str = std::to_string(const_values.size());
-  str += "'b";
-  for (const auto& val : const_values) {
-    str += std::to_string(val);
+std::string generate_verilog_constant_values(const std::vector<size_t>& const_values,
+                                             const bool& short_constant) {
+  VTR_ASSERT(!const_values.empty());
+
+  bool same_values = true;
+  size_t first_val = const_values.back();
+  if (true == short_constant) {
+    for (const auto& val : const_values) {
+      if (first_val != val) {
+        same_values = false;
+        break;
+      }
+    }
+  }
+
+  std::string str;
+
+  if ( (true == short_constant) 
+    && (true == same_values) ) {
+    str = "{" + std::to_string(const_values.size()) + "{1'b" + std::to_string(first_val) + "}}";
+  } else {
+    str = std::to_string(const_values.size());
+    str += "'b";
+    for (const auto& val : const_values) {
+      str += std::to_string(val);
+    }
   }
   return str;
 }
diff --git a/openfpga/src/fpga_verilog/verilog_writer_utils.h b/openfpga/src/fpga_verilog/verilog_writer_utils.h
index 8e6cddaaa..0d8219283 100644
--- a/openfpga/src/fpga_verilog/verilog_writer_utils.h
+++ b/openfpga/src/fpga_verilog/verilog_writer_utils.h
@@ -96,7 +96,8 @@ BasicPort generate_verilog_bus_port(const std::vector<BasicPort>& input_ports,
 std::string generate_verilog_local_wire(const BasicPort& output_port,
                                         const std::vector<BasicPort>& input_ports);
 
-std::string generate_verilog_constant_values(const std::vector<size_t>& const_values);
+std::string generate_verilog_constant_values(const std::vector<size_t>& const_values,
+                                             const bool& short_constant = false);
 
 std::string generate_verilog_port_constant_values(const BasicPort& output_port,
                                                   const std::vector<size_t>& const_values);

From 1fedd009124770eceeb45388b6b15f61f60de10e Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 30 May 2020 12:23:48 -0600
Subject: [PATCH 602/645] deploy the flatten configuration memory testcase to
 CI

---
 .travis/script.sh | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/.travis/script.sh b/.travis/script.sh
index 9d222c17a..034704c10 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -57,6 +57,9 @@ python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/con
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/fast_configuration_frame --debug --show_thread_logs
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/preconfig_testbench/configuration_frame --debug --show_thread_logs
 
+echo -e "Testing standalone (flatten memory) configuration protocol of a K4N4 FPGA";
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/flatten_memory --debug --show_thread_logs
+
 echo -e "Testing user-defined simulation settings: clock frequency and number of cycles";
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/fixed_simulation_settings --debug --show_thread_logs
 

From 2def059b5b6d3663dcde451b823cb646d4818f11 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 30 May 2020 12:25:29 -0600
Subject: [PATCH 603/645] add standalone configuration protocol to pre config
 test cases

---
 .../flatten_memory/config/task.conf           | 34 +++++++++++++++++++
 1 file changed, 34 insertions(+)
 create mode 100644 openfpga_flow/tasks/openfpga_shell/preconfig_testbench/flatten_memory/config/task.conf

diff --git a/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/flatten_memory/config/task.conf b/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/flatten_memory/config/task.conf
new file mode 100644
index 000000000..1a02eb45f
--- /dev/null
+++ b/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/flatten_memory/config/task.conf
@@ -0,0 +1,34 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

From c456ef4d0029979d226dc28a4e1709cada47ef35 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 30 May 2020 12:26:05 -0600
Subject: [PATCH 604/645] deploy the standalone preconfig testcase to CI

---
 .travis/script.sh | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.travis/script.sh b/.travis/script.sh
index 034704c10..846ec847f 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -59,6 +59,7 @@ python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/preconfig_testbenc
 
 echo -e "Testing standalone (flatten memory) configuration protocol of a K4N4 FPGA";
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/flatten_memory --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/preconfig_testbench/flatten_memory --debug --show_thread_logs
 
 echo -e "Testing user-defined simulation settings: clock frequency and number of cycles";
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/fixed_simulation_settings --debug --show_thread_logs

From fe2ba7d50aadc9f398549c579f90dde740cdbf43 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 30 May 2020 12:52:59 -0600
Subject: [PATCH 605/645] update documentation for standalone configuration
 protocol

---
 .../manual/arch_lang/config_protocol.rst      |  28 ++++++++++++++++--
 .../figures/frame_config_protocol_example.png | Bin 259112 -> 263616 bytes
 .../figures/vanilla_config_protocol.png       | Bin 0 -> 184972 bytes
 3 files changed, 26 insertions(+), 2 deletions(-)
 create mode 100644 docs/source/manual/arch_lang/figures/vanilla_config_protocol.png

diff --git a/docs/source/manual/arch_lang/config_protocol.rst b/docs/source/manual/arch_lang/config_protocol.rst
index f37c7f18b..3eba78fd4 100644
--- a/docs/source/manual/arch_lang/config_protocol.rst
+++ b/docs/source/manual/arch_lang/config_protocol.rst
@@ -107,7 +107,7 @@ It will use the circuit model defined in :numref:`fig_sram_blwl`.
 .. code-block:: xml
 
   <configuration_protocol>
-    <organization type="memory_bank" circuit_model_name="sram"/>
+    <organization type="memory_bank" circuit_model_name="sram_blwl"/>
   </configuration_protocol>
 
 .. _fig_sram:
@@ -122,5 +122,29 @@ It will use the circuit model defined in :numref:`fig_sram_blwl`.
 
 Standalone SRAM Example
 ~~~~~~~~~~~~~~~~~~~~~~~
+In the standalone configuration protocol, every memory cell of the core logic of a FPGA fabric can be directly accessed at the top-level module, as illustrated in :numref:`fig_vanilla_config_protocol`.
+
+.. _fig_vanilla_config_protocol:
+
+.. figure:: figures/vanilla_config_protocol.png
+   :scale: 30%
+   :alt: map to buried treasure
+ 
+   Vanilla (standalone) memory organization in a hierarchical view
+
+The following XML code shows an example where we use the circuit model defined in :numref:`fig_sram_blwl`.
+
+.. code-block:: xml
+
+  <configuration_protocol>
+    <organization type="standalone" circuit_model_name="sram_blwl"/>
+  </configuration_protocol>
+
+.. note:: The standalone protocol does require a memory cell to have 
+
+  -  two outputs (one regular and another inverted)
+  -  a Bit-Line input to load the data
+  -  a Word-Line input to enable data write 
+
+.. warning:: This is a vanilla configuration method, which allow users to build their own configuration protocol on top of it. 
 
-.. warning:: TO BE CONSTRUCTED
diff --git a/docs/source/manual/arch_lang/figures/frame_config_protocol_example.png b/docs/source/manual/arch_lang/figures/frame_config_protocol_example.png
index 9cc4e7e4d84b5a48976fe69e60a1d9f4e540d242..cd24907994c64ca4316262564df631854c98eb8e 100644
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literal 0
HcmV?d00001


From 0931eccbf685174c589f301def305cf03bdc2eb8 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 30 May 2020 12:58:42 -0600
Subject: [PATCH 606/645] update documentation for the fast configuration
 options

---
 docs/source/manual/openfpga_shell/openfpga_commands.rst | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/docs/source/manual/openfpga_shell/openfpga_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands.rst
index 1ac4ed69b..6e2f0e490 100644
--- a/docs/source/manual/openfpga_shell/openfpga_commands.rst
+++ b/docs/source/manual/openfpga_shell/openfpga_commands.rst
@@ -172,6 +172,8 @@ FPGA-Verilog
 
   - ``--reference_benchmark_file_path`` Must specify the reference benchmark Verilog file if you want to output any testbenches
 
+  - ``--fast_configuration`` Enable fast configuration phase for the top-level testbench in order to reduce runtime of simulations. It is applicable to memory bank and frame-based configuration protocols. When enabled, all the zero configuration bits will be skipped. So ensure that your memory cells can be correctly reset to zero with a reset signal. 
+
   - ``--print_top_testbench`` Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
 
   - ``--print_formal_verification_top_netlist`` Generate a top-level module which can be used in formal verification

From ad7422359d795a449db21fd686b9dea19fe4db9c Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 30 May 2020 13:04:55 -0600
Subject: [PATCH 607/645] deploy compact constant values in Verilog codes

---
 openfpga/src/fpga_verilog/verilog_writer_utils.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/openfpga/src/fpga_verilog/verilog_writer_utils.h b/openfpga/src/fpga_verilog/verilog_writer_utils.h
index 0d8219283..21c12509b 100644
--- a/openfpga/src/fpga_verilog/verilog_writer_utils.h
+++ b/openfpga/src/fpga_verilog/verilog_writer_utils.h
@@ -97,7 +97,7 @@ std::string generate_verilog_local_wire(const BasicPort& output_port,
                                         const std::vector<BasicPort>& input_ports);
 
 std::string generate_verilog_constant_values(const std::vector<size_t>& const_values,
-                                             const bool& short_constant = false);
+                                             const bool& short_constant = true);
 
 std::string generate_verilog_port_constant_values(const BasicPort& output_port,
                                                   const std::vector<size_t>& const_values);

From c00653961e732af832e3e7ef7545ddf699a3fc03 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 30 May 2020 15:26:22 -0600
Subject: [PATCH 608/645] minor format fix in documentation

---
 docs/source/manual/arch_lang/config_protocol.rst | 1 +
 1 file changed, 1 insertion(+)

diff --git a/docs/source/manual/arch_lang/config_protocol.rst b/docs/source/manual/arch_lang/config_protocol.rst
index 3eba78fd4..2fcdae535 100644
--- a/docs/source/manual/arch_lang/config_protocol.rst
+++ b/docs/source/manual/arch_lang/config_protocol.rst
@@ -35,6 +35,7 @@ Template
 .. option:: circuit_model_name="<string>"
 
   Specify the name of circuit model to be used as configurable memory.
+
   - ``scan_chain`` requires a circuit model type of ``ccff``
   - ``frame_based`` requires a circuit model type of ``sram``
   - ``memory_bank`` requires a circuit model type of ``sram``

From fa8dfc1fbdc021208a10daac2c9f60f4b223faff Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 30 May 2020 15:49:15 -0600
Subject: [PATCH 609/645] add configuration protocol ports to top module for
 memory bank organization

---
 openfpga/src/base/openfpga_reserved_words.h   |   2 +
 openfpga/src/fabric/build_top_module.cpp      |   4 +-
 .../src/fabric/build_top_module_memory.cpp    | 100 ++++++++++++++++++
 openfpga/src/fabric/build_top_module_memory.h |   7 ++
 openfpga/src/utils/decoder_library_utils.cpp  |  39 +++++++
 openfpga/src/utils/decoder_library_utils.h    |   2 +
 openfpga/src/utils/module_manager_utils.cpp   |   2 +-
 7 files changed, 154 insertions(+), 2 deletions(-)

diff --git a/openfpga/src/base/openfpga_reserved_words.h b/openfpga/src/base/openfpga_reserved_words.h
index 40a2af96b..a9b31f64e 100644
--- a/openfpga/src/base/openfpga_reserved_words.h
+++ b/openfpga/src/base/openfpga_reserved_words.h
@@ -38,6 +38,8 @@ constexpr char* DECODER_ADDRESS_PORT_NAME = "address";
 constexpr char* DECODER_DATA_IN_PORT_NAME = "data_in";
 constexpr char* DECODER_DATA_OUT_PORT_NAME = "data_out";
 constexpr char* DECODER_DATA_OUT_INV_PORT_NAME = "data_out_inv";
+constexpr char* DECODER_BL_ADDRESS_PORT_NAME = "bl_address";
+constexpr char* DECODER_WL_ADDRESS_PORT_NAME = "wl_address";
 
 /* Inverted port naming */
 constexpr char* INV_PORT_POSTFIX = "_inv";
diff --git a/openfpga/src/fabric/build_top_module.cpp b/openfpga/src/fabric/build_top_module.cpp
index 072548807..7b05a5676 100644
--- a/openfpga/src/fabric/build_top_module.cpp
+++ b/openfpga/src/fabric/build_top_module.cpp
@@ -384,7 +384,9 @@ void build_top_module(ModuleManager& module_manager,
    */
   size_t module_num_config_bits = find_module_num_config_bits_from_child_modules(module_manager, top_module, circuit_lib, sram_model, sram_orgz_type); 
   if (0 < module_num_config_bits) {
-    add_sram_ports_to_module_manager(module_manager, top_module, circuit_lib, sram_model, sram_orgz_type, module_num_config_bits);
+    add_top_module_sram_ports(module_manager, top_module,
+                              circuit_lib, sram_model,
+                              sram_orgz_type, module_num_config_bits);
   }
 
   /* Add module nets to connect memory cells inside
diff --git a/openfpga/src/fabric/build_top_module_memory.cpp b/openfpga/src/fabric/build_top_module_memory.cpp
index b5d7f1db1..c2a726ea9 100644
--- a/openfpga/src/fabric/build_top_module_memory.cpp
+++ b/openfpga/src/fabric/build_top_module_memory.cpp
@@ -13,6 +13,8 @@
 #include "openfpga_reserved_words.h"
 #include "openfpga_naming.h"
 
+#include "memory_utils.h"
+#include "decoder_library_utils.h"
 #include "module_manager_utils.h"
 #include "build_top_module_memory.h"
 
@@ -361,6 +363,104 @@ void organize_top_module_memory_modules(ModuleManager& module_manager,
   }
 }
 
+/********************************************************************
+ * Add a list of ports that are used for SRAM configuration to the FPGA 
+ * top-level module
+ * The type and names of added ports strongly depend on the 
+ * organization of SRAMs.
+ * 1. Standalone SRAMs: 
+ *    two ports will be added, which are BL and WL 
+ * 2. Scan-chain Flip-flops:
+ *    two ports will be added, which are the head of scan-chain 
+ *    and the tail of scan-chain
+ *    IMPORTANT: the port size will be forced to 1 in this case 
+ *               because the head and tail are both 1-bit ports!!!
+ * 3. Memory decoders:
+ *    - An enable signal
+ *    - A BL address port
+ *    - A WL address port
+ *    - A data-in port for the BL decoder
+ * 4. Frame-based memory:
+ *    - An Enable signal
+ *    - An address port, whose size depends on the number of config bits 
+ *      and the maximum size of address ports of configurable children
+ *    - An data_in port (single-bit)
+ ********************************************************************/
+void add_top_module_sram_ports(ModuleManager& module_manager, 
+                               const ModuleId& module_id,
+                               const CircuitLibrary& circuit_lib,
+                               const CircuitModelId& sram_model,
+                               const e_config_protocol_type sram_orgz_type,
+                               const size_t& num_config_bits) {
+  std::vector<std::string> sram_port_names = generate_sram_port_names(circuit_lib, sram_model, sram_orgz_type);
+  size_t sram_port_size = generate_sram_port_size(sram_orgz_type, num_config_bits); 
+
+  /* Add ports to the module manager */
+  switch (sram_orgz_type) {
+  case CONFIG_MEM_STANDALONE: { 
+    for (const std::string& sram_port_name : sram_port_names) {
+      /* Add generated ports to the ModuleManager */
+      BasicPort sram_port(sram_port_name, sram_port_size);
+      module_manager.add_port(module_id, sram_port, ModuleManager::MODULE_INPUT_PORT);
+    }
+    break;
+  }
+  case CONFIG_MEM_MEMORY_BANK: {
+    BasicPort en_port(std::string(DECODER_ENABLE_PORT_NAME), 1);
+    module_manager.add_port(module_id, en_port, ModuleManager::MODULE_INPUT_PORT);
+
+    size_t bl_addr_size = find_memory_decoder_addr_size(num_config_bits);
+    BasicPort bl_addr_port(std::string(DECODER_BL_ADDRESS_PORT_NAME), bl_addr_size);
+    module_manager.add_port(module_id, bl_addr_port, ModuleManager::MODULE_INPUT_PORT);
+
+    size_t wl_addr_size = find_memory_decoder_addr_size(num_config_bits);
+    BasicPort wl_addr_port(std::string(DECODER_WL_ADDRESS_PORT_NAME), wl_addr_size);
+    module_manager.add_port(module_id, wl_addr_port, ModuleManager::MODULE_INPUT_PORT);
+
+    BasicPort din_port(std::string(DECODER_DATA_IN_PORT_NAME), 1);
+    module_manager.add_port(module_id, din_port, ModuleManager::MODULE_INPUT_PORT);
+
+    break;
+  }
+  case CONFIG_MEM_SCAN_CHAIN: { 
+    /* Note that configuration chain tail is an output while head is an input 
+     * IMPORTANT: this is co-designed with function generate_sram_port_names()
+     * If the return vector is changed, the following codes MUST be adapted!
+     */
+    VTR_ASSERT(2 == sram_port_names.size());
+    size_t port_counter = 0;
+    for (const std::string& sram_port_name : sram_port_names) {
+      /* Add generated ports to the ModuleManager */
+      BasicPort sram_port(sram_port_name, sram_port_size);
+      if (0 == port_counter) { 
+        module_manager.add_port(module_id, sram_port, ModuleManager::MODULE_INPUT_PORT);
+      } else {
+        VTR_ASSERT(1 == port_counter);
+        module_manager.add_port(module_id, sram_port, ModuleManager::MODULE_OUTPUT_PORT);
+      }
+      port_counter++;
+    }
+    break;
+  }
+  case CONFIG_MEM_FRAME_BASED: { 
+    BasicPort en_port(std::string(DECODER_ENABLE_PORT_NAME), 1);
+    module_manager.add_port(module_id, en_port, ModuleManager::MODULE_INPUT_PORT);
+
+    BasicPort addr_port(std::string(DECODER_ADDRESS_PORT_NAME), num_config_bits);
+    module_manager.add_port(module_id, addr_port, ModuleManager::MODULE_INPUT_PORT);
+
+    BasicPort din_port(std::string(DECODER_DATA_IN_PORT_NAME), 1);
+    module_manager.add_port(module_id, din_port, ModuleManager::MODULE_INPUT_PORT);
+
+    break;
+  }
+  default:
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid type of SRAM organization !\n");
+    exit(1);
+  }
+}
+
 
 /*********************************************************************
  * Add the port-to-port connection between all the memory modules 
diff --git a/openfpga/src/fabric/build_top_module_memory.h b/openfpga/src/fabric/build_top_module_memory.h
index 1d0295b87..a912845b2 100644
--- a/openfpga/src/fabric/build_top_module_memory.h
+++ b/openfpga/src/fabric/build_top_module_memory.h
@@ -34,6 +34,13 @@ void organize_top_module_memory_modules(ModuleManager& module_manager,
                                         const std::map<t_rr_type, vtr::Matrix<size_t>>& cb_instance_ids,
                                         const bool& compact_routing_hierarchy);
 
+void add_top_module_sram_ports(ModuleManager& module_manager, 
+                               const ModuleId& module_id,
+                               const CircuitLibrary& circuit_lib,
+                               const CircuitModelId& sram_model,
+                               const e_config_protocol_type sram_orgz_type,
+                               const size_t& num_config_bits);
+
 void add_top_module_nets_memory_config_bus(ModuleManager& module_manager,
                                            DecoderLibrary& decoder_lib,
                                            const ModuleId& parent_module,
diff --git a/openfpga/src/utils/decoder_library_utils.cpp b/openfpga/src/utils/decoder_library_utils.cpp
index a41e439ef..20f7473b2 100644
--- a/openfpga/src/utils/decoder_library_utils.cpp
+++ b/openfpga/src/utils/decoder_library_utils.cpp
@@ -38,6 +38,45 @@ size_t find_mux_local_decoder_addr_size(const size_t& data_size) {
   return ceil(log(data_size) / log(2));
 }
 
+/***************************************************************************************
+ * Find the size of address lines for a memory decoder to access a memory array
+ *                   Addr lines 
+ *                   | | ... | 
+ *                   v v     v
+ *                 +-----------+
+ *                /    Local    \
+ *               /    Decoder    \
+ *              +-----------------+
+ *                | | | ... | | |
+ *                v v v     v v v
+ *                   Data outputs
+ *
+ *          +------+  +------+      +------+
+ *          | SRAM |  | SRAM |  ... | SRAM |
+ *          | [0]  |  | [1]  |      |  [i] |
+ *          +------+  +------+      +------+
+ *
+ *          +------+  +------+      +------+
+ *          | SRAM |  | SRAM |  ... | SRAM |
+ *          | [i+1]|  | [i+2]|      |[2i-1]|
+ *          +------+  +------+      +------+
+ *
+ *            ...       ...            ...
+ *
+ *          +------+  +------+      +------+
+ *          | SRAM |  | SRAM |  ... | SRAM |
+ *          | [x]  |  | [x+1]|      |  [N] |
+ *          +------+  +------+      +------+
+ *
+ *  Due to the shared lines in the array, 
+ *  each memory decoder (BL or WL) will access sqrt(N) control lins (BL or WL)
+ *  Then we can use the function for mux local encoder to compute the address size 
+ *               
+ ***************************************************************************************/
+size_t find_memory_decoder_addr_size(const size_t& num_mems) {
+  return find_mux_local_decoder_addr_size((size_t)std::ceil(std::sqrt((float)num_mems)));
+}
+
 /***************************************************************************************
  * Try to find if the decoder already exists in the library, 
  * If there is no such decoder, add it to the library 
diff --git a/openfpga/src/utils/decoder_library_utils.h b/openfpga/src/utils/decoder_library_utils.h
index d55a0750a..e43068f5f 100644
--- a/openfpga/src/utils/decoder_library_utils.h
+++ b/openfpga/src/utils/decoder_library_utils.h
@@ -13,6 +13,8 @@ bool need_mux_local_decoder(const size_t& data_size);
 
 size_t find_mux_local_decoder_addr_size(const size_t& data_size);
 
+size_t find_memory_decoder_addr_size(const size_t& num_mems);
+
 DecoderId add_mux_local_decoder_to_library(DecoderLibrary& decoder_lib, 
                                            const size_t data_size);
 
diff --git a/openfpga/src/utils/module_manager_utils.cpp b/openfpga/src/utils/module_manager_utils.cpp
index cf9808466..ec871368a 100644
--- a/openfpga/src/utils/module_manager_utils.cpp
+++ b/openfpga/src/utils/module_manager_utils.cpp
@@ -163,7 +163,7 @@ void add_formal_verification_sram_ports_to_module_manager(ModuleManager& module_
  * The type and names of added ports strongly depend on the 
  * organization of SRAMs.
  * 1. Standalone SRAMs: 
- *    two ports will be added, which are regular output and inverted output 
+ *    two ports will be added, which are BL and WL 
  * 2. Scan-chain Flip-flops:
  *    two ports will be added, which are the head of scan-chain 
  *    and the tail of scan-chain

From 0e16ee10300e606b26230f5a472e9174fd0b9907 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 30 May 2020 18:14:36 -0600
Subject: [PATCH 610/645] add configuration bus nets for memory bank decoders
 at top module

---
 openfpga/src/base/openfpga_naming.cpp         |  28 ++
 openfpga/src/base/openfpga_naming.h           |   6 +
 openfpga/src/fabric/build_decoder_modules.cpp | 113 ++++++++
 openfpga/src/fabric/build_decoder_modules.h   |   8 +
 .../src/fabric/build_top_module_memory.cpp    | 245 ++++++++++++++++++
 openfpga/src/utils/decoder_library_utils.cpp  |   4 +
 openfpga/src/utils/decoder_library_utils.h    |   2 +
 7 files changed, 406 insertions(+)

diff --git a/openfpga/src/base/openfpga_naming.cpp b/openfpga/src/base/openfpga_naming.cpp
index 5cf00bf7f..1c792d26d 100644
--- a/openfpga/src/base/openfpga_naming.cpp
+++ b/openfpga/src/base/openfpga_naming.cpp
@@ -156,6 +156,34 @@ std::string generate_frame_memory_decoder_subckt_name(const size_t& addr_size,
   return subckt_name;
 } 
 
+/************************************************
+ * Generate the module name of a bit-line decoder
+ * for memories
+ ***********************************************/
+std::string generate_bl_memory_decoder_subckt_name(const size_t& addr_size, 
+                                                   const size_t& data_size) {
+  std::string subckt_name = "bl_decoder";
+  subckt_name += std::to_string(addr_size);
+  subckt_name += "to";
+  subckt_name += std::to_string(data_size);
+
+  return subckt_name;
+} 
+
+/************************************************
+ * Generate the module name of a word-line decoder
+ * for memories
+ ***********************************************/
+std::string generate_wl_memory_decoder_subckt_name(const size_t& addr_size, 
+                                                   const size_t& data_size) {
+  std::string subckt_name = "wl_decoder";
+  subckt_name += std::to_string(addr_size);
+  subckt_name += "to";
+  subckt_name += std::to_string(data_size);
+
+  return subckt_name;
+} 
+
 /************************************************
  * Generate the module name of a routing track wire
  ***********************************************/
diff --git a/openfpga/src/base/openfpga_naming.h b/openfpga/src/base/openfpga_naming.h
index 4e1c44fa9..534bf2a78 100644
--- a/openfpga/src/base/openfpga_naming.h
+++ b/openfpga/src/base/openfpga_naming.h
@@ -53,6 +53,12 @@ std::string generate_mux_local_decoder_subckt_name(const size_t& addr_size,
 std::string generate_frame_memory_decoder_subckt_name(const size_t& addr_size, 
                                                       const size_t& data_size);
 
+std::string generate_bl_memory_decoder_subckt_name(const size_t& addr_size, 
+                                                   const size_t& data_size);
+
+std::string generate_wl_memory_decoder_subckt_name(const size_t& addr_size, 
+                                                   const size_t& data_size);
+
 std::string generate_segment_wire_subckt_name(const std::string& wire_model_name, 
                                               const size_t& segment_id); 
 
diff --git a/openfpga/src/fabric/build_decoder_modules.cpp b/openfpga/src/fabric/build_decoder_modules.cpp
index ada36e3e7..fb8a29e5c 100644
--- a/openfpga/src/fabric/build_decoder_modules.cpp
+++ b/openfpga/src/fabric/build_decoder_modules.cpp
@@ -74,6 +74,119 @@ ModuleId build_frame_memory_decoder_module(ModuleManager& module_manager,
   return module_id;
 }
 
+/***************************************************************************************
+ * Create a module for a BL decoder with a given output size
+ *
+ *                  BL Address
+ *                   | | ... | 
+ *                   v v     v
+ *                 +-----------+
+ *                /             \<-- data_in
+ *      enable-->/    Decoder    \
+ *              +-----------------+
+ *                | | | ... | | |
+ *                v v v     v v v
+ *                  Data Outputs
+ *               
+ *  The outputs are assumes to be one-hot codes (at most only one '1' exist)
+ *  Considering this fact, there are only num_of_outputs conditions to be encoded.
+ *  Therefore, the number of inputs is ceil(log(num_of_outputs)/log(2))
+ ***************************************************************************************/
+ModuleId build_bl_memory_decoder_module(ModuleManager& module_manager,
+                                        const DecoderLibrary& decoder_lib,
+                                        const DecoderId& decoder) {
+  /* Get the number of inputs */
+  size_t addr_size = decoder_lib.addr_size(decoder);
+  size_t data_size = decoder_lib.data_size(decoder);
+
+  /* Create a name for the local encoder */
+  std::string module_name = generate_bl_memory_decoder_subckt_name(addr_size, data_size);
+
+  /* Create a Verilog Module based on the circuit model, and add to module manager */
+  ModuleId module_id = module_manager.add_module(module_name); 
+  VTR_ASSERT(true == module_manager.valid_module_id(module_id));
+
+  /* Add enable port */
+  BasicPort en_port(std::string(DECODER_ENABLE_PORT_NAME), 1);
+  module_manager.add_port(module_id, en_port, ModuleManager::MODULE_INPUT_PORT);
+  /* Add each input port */
+  BasicPort addr_port(std::string(DECODER_ADDRESS_PORT_NAME), addr_size);
+  module_manager.add_port(module_id, addr_port, ModuleManager::MODULE_INPUT_PORT);
+  /* Add each input port */
+  BasicPort din_port(std::string(DECODER_DATA_IN_PORT_NAME), 1);
+  module_manager.add_port(module_id, din_port, ModuleManager::MODULE_INPUT_PORT);
+  /* Add each output port */
+  BasicPort data_port(std::string(DECODER_DATA_OUT_PORT_NAME), data_size);
+  module_manager.add_port(module_id, data_port, ModuleManager::MODULE_OUTPUT_PORT);
+
+  /* Data port is registered. It should be outputted as 
+   *   output reg [lsb:msb] data 
+   */
+  module_manager.set_port_is_register(module_id, data_port.get_name(), true);
+  /* Add data_in port */
+  if (true == decoder_lib.use_data_inv_port(decoder)) {
+    BasicPort data_inv_port(std::string(DECODER_DATA_OUT_INV_PORT_NAME), data_size);
+    module_manager.add_port(module_id, data_inv_port, ModuleManager::MODULE_OUTPUT_PORT);
+  }
+
+  return module_id;
+}
+
+/***************************************************************************************
+ * Create a module for a Word-line decoder with a given output size
+ *
+ *                  WL Address
+ *                   | | ... | 
+ *                   v v     v
+ *                 +-----------+
+ *                /             \
+ *      enable-->/    Decoder    \
+ *              +-----------------+
+ *                | | | ... | | |
+ *                v v v     v v v
+ *                  Data Outputs
+ *               
+ *  The outputs are assumes to be one-hot codes (at most only one '1' exist)
+ *  Considering this fact, there are only num_of_outputs conditions to be encoded.
+ *  Therefore, the number of inputs is ceil(log(num_of_outputs)/log(2))
+ ***************************************************************************************/
+ModuleId build_wl_memory_decoder_module(ModuleManager& module_manager,
+                                        const DecoderLibrary& decoder_lib,
+                                        const DecoderId& decoder) {
+  /* Get the number of inputs */
+  size_t addr_size = decoder_lib.addr_size(decoder);
+  size_t data_size = decoder_lib.data_size(decoder);
+
+  /* Create a name for the local encoder */
+  std::string module_name = generate_wl_memory_decoder_subckt_name(addr_size, data_size);
+
+  /* Create a Verilog Module based on the circuit model, and add to module manager */
+  ModuleId module_id = module_manager.add_module(module_name); 
+  VTR_ASSERT(true == module_manager.valid_module_id(module_id));
+
+  /* Add enable port */
+  BasicPort en_port(std::string(DECODER_ENABLE_PORT_NAME), 1);
+  module_manager.add_port(module_id, en_port, ModuleManager::MODULE_INPUT_PORT);
+  /* Add each input port */
+  BasicPort addr_port(std::string(DECODER_ADDRESS_PORT_NAME), addr_size);
+  module_manager.add_port(module_id, addr_port, ModuleManager::MODULE_INPUT_PORT);
+  /* Add each output port */
+  BasicPort data_port(std::string(DECODER_DATA_OUT_PORT_NAME), data_size);
+  module_manager.add_port(module_id, data_port, ModuleManager::MODULE_OUTPUT_PORT);
+
+  /* Data port is registered. It should be outputted as 
+   *   output reg [lsb:msb] data 
+   */
+  module_manager.set_port_is_register(module_id, data_port.get_name(), true);
+  /* Add data_in port */
+  if (true == decoder_lib.use_data_inv_port(decoder)) {
+    BasicPort data_inv_port(std::string(DECODER_DATA_OUT_INV_PORT_NAME), data_size);
+    module_manager.add_port(module_id, data_inv_port, ModuleManager::MODULE_OUTPUT_PORT);
+  }
+
+  return module_id;
+}
+
 /***************************************************************************************
  * Create a module for a decoder with a given output size
  *
diff --git a/openfpga/src/fabric/build_decoder_modules.h b/openfpga/src/fabric/build_decoder_modules.h
index bf18e47d4..13d5091d4 100644
--- a/openfpga/src/fabric/build_decoder_modules.h
+++ b/openfpga/src/fabric/build_decoder_modules.h
@@ -20,6 +20,14 @@ ModuleId build_frame_memory_decoder_module(ModuleManager& module_manager,
                                            const DecoderLibrary& decoder_lib,
                                            const DecoderId& decoder);
 
+ModuleId build_bl_memory_decoder_module(ModuleManager& module_manager,
+                                        const DecoderLibrary& decoder_lib,
+                                        const DecoderId& decoder);
+
+ModuleId build_wl_memory_decoder_module(ModuleManager& module_manager,
+                                        const DecoderLibrary& decoder_lib,
+                                        const DecoderId& decoder);
+
 void build_mux_local_decoder_modules(ModuleManager& module_manager,
                                      const MuxLibrary& mux_lib,
                                      const CircuitLibrary& circuit_lib);
diff --git a/openfpga/src/fabric/build_top_module_memory.cpp b/openfpga/src/fabric/build_top_module_memory.cpp
index c2a726ea9..278a33f2d 100644
--- a/openfpga/src/fabric/build_top_module_memory.cpp
+++ b/openfpga/src/fabric/build_top_module_memory.cpp
@@ -16,6 +16,7 @@
 #include "memory_utils.h"
 #include "decoder_library_utils.h"
 #include "module_manager_utils.h"
+#include "build_decoder_modules.h"
 #include "build_top_module_memory.h"
 
 /* begin namespace openfpga */
@@ -461,6 +462,249 @@ void add_top_module_sram_ports(ModuleManager& module_manager,
   }
 }
 
+/*********************************************************************
+ * Top-level function to add nets for memory banks
+ * - Find the number of BLs and WLs required
+ * - Create BL and WL decoders, and add them to decoder library
+ * - Create nets to connect from top-level module inputs to inputs of decoders
+ * - Create nets to connect from outputs of decoders to BL/WL of configurable children
+ *
+ *                            WL_enable  WL address 
+ *                               |           |
+ *                               v           v
+ *                           +-----------------------------------------------+
+ *                           |     Word Line Decoder                         |
+ *                           +-----------------------------------------------+
+ *               +---------+    |             |                   | 
+ *  BL           |         |    |             |                   |
+ *  enable  ---->|         |-----------+--------------+----  ...  |------+--> BL[0]
+ *               |         |    |      |      |       |           |      |
+ *               |         |    |      v      |       v           |      v
+ *               | Bit     |    |   +------+  |   +------+        |  +------+
+ *  BL           | Line    |    +-->| SRAM |  +-->| SRAM |        +->| SRAM |
+ *  address ---->| Decoder |    |   | [0]  |  |   |  [1] |   ...  |  |  [i] |
+ *               |         |    |   +------+  |   +------+        |  +------+
+ *               |         |    |             |                   |
+ *               |         |-----------+--------------+----  ---  | -----+--> BL[1]
+ *               |         |    |      |      |       |           |      |
+ *               |         |    |      v      |       v           |      v
+ *               |         |    |   +------+  |   +------+        |  +------+
+ *               |         |    +-->| SRAM |  |   | SRAM |        +->| SRAM |
+ *               |         |    |   | [x]  |  |   | [x+1]|   ...  |  | [x+i]|
+ *               |         |    |   +------+  |   +------+        |  +------+
+ *               |         |    |                                 |
+ *               |         |    |     ...    ...    ...           |    ...
+ *               |         |    |             |                   |
+ *               |         |-----------+--------------+----  ---  | -----+--> BL[y]
+ *               |         |    |      |      |       |           |      |
+ *               |         |    |      v      |       v           |      v
+ *               |         |    |   +------+  |   +------+        |  +------+
+ *               |         |    +-->| SRAM |  +-->| SRAM |        +->| SRAM |
+ *               |         |    |   | [y]  |  |   |[y+1] |   ...  |  |[y+i] |
+ *               |         |    |   +------+  |   +------+        |  +------+
+ *  BL           |         |    v             v                   v
+ *  data_in ---->|         |  WL[0]          WL[1]              WL[i]
+ *               +---------+
+ *
+ **********************************************************************/
+static 
+void add_top_module_nets_cmos_memory_bank_config_bus(ModuleManager& module_manager,
+                                                     DecoderLibrary& decoder_lib,
+                                                     const ModuleId& top_module) {
+  /* Find Enable port from the top-level module */ 
+  ModulePortId en_port = module_manager.find_module_port(top_module, std::string(DECODER_ENABLE_PORT_NAME));
+  BasicPort en_port_info = module_manager.module_port(top_module, en_port);
+
+  /* Find data-in port from the top-level module */ 
+  ModulePortId din_port = module_manager.find_module_port(top_module, std::string(DECODER_DATA_IN_PORT_NAME));
+  BasicPort din_port_info = module_manager.module_port(top_module, din_port);
+
+  /* Find BL and WL address port from the top-level module */ 
+  ModulePortId bl_addr_port = module_manager.find_module_port(top_module, std::string(DECODER_BL_ADDRESS_PORT_NAME));
+  BasicPort bl_addr_port_info = module_manager.module_port(top_module, bl_addr_port);
+
+  ModulePortId wl_addr_port = module_manager.find_module_port(top_module, std::string(DECODER_WL_ADDRESS_PORT_NAME));
+  BasicPort wl_addr_port_info = module_manager.module_port(top_module, wl_addr_port);
+
+  /* Find the number of BLs and WLs required to access each memory bit */
+  size_t bl_addr_size = bl_addr_port_info.get_width();
+  size_t wl_addr_size = wl_addr_port_info.get_width();
+  size_t num_bls = find_memory_decoder_data_size(bl_addr_size);
+  size_t num_wls = find_memory_decoder_data_size(wl_addr_size);
+  
+  /* Add the BL decoder module 
+   * Search the decoder library
+   * If we find one, we use the module.
+   * Otherwise, we create one and add it to the decoder library
+   */
+  DecoderId bl_decoder_id = decoder_lib.find_decoder(bl_addr_size, num_bls,
+                                                     true, true, false);
+  if (DecoderId::INVALID() == bl_decoder_id) {
+    bl_decoder_id = decoder_lib.add_decoder(bl_addr_size, num_bls, true, true, false);
+  }
+  VTR_ASSERT(DecoderId::INVALID() != bl_decoder_id);
+
+  /* Create a module if not existed yet */
+  std::string bl_decoder_module_name = generate_bl_memory_decoder_subckt_name(bl_addr_size, num_bls);
+  ModuleId bl_decoder_module = module_manager.find_module(bl_decoder_module_name);
+  if (ModuleId::INVALID() == bl_decoder_module) {
+    /* BL decoder has the same ports as the frame-based decoders
+     * We reuse it here
+     */
+    bl_decoder_module = build_bl_memory_decoder_module(module_manager,
+                                                       decoder_lib,
+                                                       bl_decoder_id);
+  }
+  VTR_ASSERT(ModuleId::INVALID() != bl_decoder_module);
+  VTR_ASSERT(0 == module_manager.num_instance(top_module, bl_decoder_module));
+  module_manager.add_child_module(top_module, bl_decoder_module);
+
+  /* Add the WL decoder module 
+   * Search the decoder library
+   * If we find one, we use the module.
+   * Otherwise, we create one and add it to the decoder library
+   */
+  DecoderId wl_decoder_id = decoder_lib.find_decoder(wl_addr_size, num_wls,
+                                                     true, false, false);
+  if (DecoderId::INVALID() == wl_decoder_id) {
+    wl_decoder_id = decoder_lib.add_decoder(wl_addr_size, num_wls, true, false, false);
+  }
+  VTR_ASSERT(DecoderId::INVALID() != wl_decoder_id);
+
+  /* Create a module if not existed yet */
+  std::string wl_decoder_module_name = generate_bl_memory_decoder_subckt_name(wl_addr_size, num_wls);
+  ModuleId wl_decoder_module = module_manager.find_module(wl_decoder_module_name);
+  if (ModuleId::INVALID() == wl_decoder_module) {
+    /* BL decoder has the same ports as the frame-based decoders
+     * We reuse it here
+     */
+    wl_decoder_module = build_wl_memory_decoder_module(module_manager,
+                                                       decoder_lib,
+                                                       wl_decoder_id);
+  }
+  VTR_ASSERT(ModuleId::INVALID() != wl_decoder_module);
+  VTR_ASSERT(0 == module_manager.num_instance(top_module, wl_decoder_module));
+  module_manager.add_child_module(top_module, wl_decoder_module);
+
+  /* Add module nets from the top module to BL decoder's inputs */
+  ModulePortId bl_decoder_en_port = module_manager.find_module_port(bl_decoder_module, std::string(DECODER_ENABLE_PORT_NAME));
+  BasicPort bl_decoder_en_port_info = module_manager.module_port(bl_decoder_module, bl_decoder_en_port);
+
+  ModulePortId bl_decoder_addr_port = module_manager.find_module_port(bl_decoder_module, std::string(DECODER_ADDRESS_PORT_NAME));
+  BasicPort bl_decoder_addr_port_info = module_manager.module_port(bl_decoder_module, bl_decoder_addr_port);
+
+  ModulePortId bl_decoder_din_port = module_manager.find_module_port(bl_decoder_module, std::string(DECODER_DATA_IN_PORT_NAME));
+  BasicPort bl_decoder_din_port_info = module_manager.module_port(bl_decoder_module, bl_decoder_din_port);
+
+  /* Top module Enable port -> BL Decoder Enable port */
+  add_module_bus_nets(module_manager,
+                      top_module,
+                      top_module, 0, en_port,
+                      bl_decoder_module, 0, bl_decoder_en_port);
+
+  /* Top module Address port -> BL Decoder Address port */
+  add_module_bus_nets(module_manager,
+                      top_module,
+                      top_module, 0, bl_addr_port,
+                      bl_decoder_module, 0, bl_decoder_addr_port);
+
+  /* Top module data_in port -> BL Decoder data_in port */
+  add_module_bus_nets(module_manager,
+                      top_module,
+                      top_module, 0, din_port,
+                      bl_decoder_module, 0, bl_decoder_din_port);
+
+  /* Add module nets from the top module to WL decoder's inputs */
+  ModulePortId wl_decoder_en_port = module_manager.find_module_port(wl_decoder_module, std::string(DECODER_ENABLE_PORT_NAME));
+  BasicPort wl_decoder_en_port_info = module_manager.module_port(wl_decoder_module, wl_decoder_en_port);
+
+  ModulePortId wl_decoder_addr_port = module_manager.find_module_port(wl_decoder_module, std::string(DECODER_ADDRESS_PORT_NAME));
+  BasicPort wl_decoder_addr_port_info = module_manager.module_port(wl_decoder_module, bl_decoder_addr_port);
+
+  /* Top module Enable port -> WL Decoder Enable port */
+  add_module_bus_nets(module_manager,
+                      top_module,
+                      top_module, 0, en_port,
+                      wl_decoder_module, 0, wl_decoder_en_port);
+
+  /* Top module Address port -> WL Decoder Address port */
+  add_module_bus_nets(module_manager,
+                      top_module,
+                      top_module, 0, wl_addr_port,
+                      wl_decoder_module, 0, wl_decoder_addr_port);
+
+  /* Add nets from BL data out to each configurable child */
+  size_t cur_bl_index = 0;
+
+  ModulePortId bl_decoder_dout_port = module_manager.find_module_port(bl_decoder_module, std::string(DECODER_DATA_OUT_PORT_NAME));
+  BasicPort bl_decoder_dout_port_info = module_manager.module_port(bl_decoder_module, bl_decoder_dout_port);
+
+  for (size_t child_id = 0; child_id < module_manager.configurable_children(top_module).size(); ++child_id) {
+    ModuleId child_module = module_manager.configurable_children(top_module)[child_id];
+    size_t child_instance = module_manager.configurable_child_instances(top_module)[child_id];
+
+    /* Find the BL port */
+    ModulePortId child_bl_port = module_manager.find_module_port(child_module, std::string(MEMORY_BL_PORT_NAME));
+    BasicPort child_bl_port_info = module_manager.module_port(child_module, child_bl_port);
+
+    for (const size_t& sink_bl_pin : child_bl_port_info.pins()) {
+      /* Find the BL decoder data index: 
+       * It should be the residual when divided by the number of BLs
+       */
+      size_t bl_pin_id = cur_bl_index / num_bls;
+
+      /* Create net */
+      ModuleNetId net = create_module_source_pin_net(module_manager, top_module,
+                                                     bl_decoder_module, 0,
+                                                     bl_decoder_dout_port,
+                                                     bl_decoder_dout_port_info.pins()[bl_pin_id]);
+      VTR_ASSERT(ModuleNetId::INVALID() != net);
+
+      /* Add net sink */
+      module_manager.add_module_net_sink(top_module, net,
+                                         child_module, child_instance, child_bl_port, sink_bl_pin);
+
+      /* Increment the BL index */
+      cur_bl_index++;
+    }
+  }
+
+  /* Add nets from WL data out to each configurable child */
+  size_t cur_wl_index = 0;
+
+  ModulePortId wl_decoder_dout_port = module_manager.find_module_port(wl_decoder_module, std::string(DECODER_DATA_OUT_PORT_NAME));
+  BasicPort wl_decoder_dout_port_info = module_manager.module_port(wl_decoder_module, wl_decoder_dout_port);
+
+  for (size_t child_id = 0; child_id < module_manager.configurable_children(top_module).size(); ++child_id) {
+    ModuleId child_module = module_manager.configurable_children(top_module)[child_id];
+    size_t child_instance = module_manager.configurable_child_instances(top_module)[child_id];
+
+    /* Find the WL port */
+    ModulePortId child_wl_port = module_manager.find_module_port(child_module, std::string(MEMORY_WL_PORT_NAME));
+    BasicPort child_wl_port_info = module_manager.module_port(child_module, child_wl_port);
+
+    for (const size_t& sink_wl_pin : child_wl_port_info.pins()) {
+      /* Find the BL decoder data index: 
+       * It should be the residual when divided by the number of BLs
+       */
+      size_t wl_pin_id = cur_wl_index % num_wls;
+
+      /* Create net */
+      ModuleNetId net = create_module_source_pin_net(module_manager, top_module,
+                                                     wl_decoder_module, 0,
+                                                     wl_decoder_dout_port,
+                                                     wl_decoder_dout_port_info.pins()[wl_pin_id]);
+      VTR_ASSERT(ModuleNetId::INVALID() != net);
+
+      /* Add net sink */
+      module_manager.add_module_net_sink(top_module, net,
+                                         child_module, child_instance, child_wl_port, sink_wl_pin);
+
+      /* Increment the WL index */
+      cur_wl_index++;
+    }
+  }
+}
 
 /*********************************************************************
  * Add the port-to-port connection between all the memory modules 
@@ -524,6 +768,7 @@ void add_top_module_nets_cmos_memory_config_bus(ModuleManager& module_manager,
   }
   case CONFIG_MEM_MEMORY_BANK:
     /* TODO */
+    add_top_module_nets_cmos_memory_bank_config_bus(module_manager, decoder_lib, parent_module);
     break;
   case CONFIG_MEM_FRAME_BASED:
     add_module_nets_cmos_memory_frame_config_bus(module_manager, decoder_lib, parent_module);
diff --git a/openfpga/src/utils/decoder_library_utils.cpp b/openfpga/src/utils/decoder_library_utils.cpp
index 20f7473b2..8fd7e2208 100644
--- a/openfpga/src/utils/decoder_library_utils.cpp
+++ b/openfpga/src/utils/decoder_library_utils.cpp
@@ -77,6 +77,10 @@ size_t find_memory_decoder_addr_size(const size_t& num_mems) {
   return find_mux_local_decoder_addr_size((size_t)std::ceil(std::sqrt((float)num_mems)));
 }
 
+size_t find_memory_decoder_data_size(const size_t& num_addr) {
+  return (size_t)std::pow(2., num_addr);
+}
+
 /***************************************************************************************
  * Try to find if the decoder already exists in the library, 
  * If there is no such decoder, add it to the library 
diff --git a/openfpga/src/utils/decoder_library_utils.h b/openfpga/src/utils/decoder_library_utils.h
index e43068f5f..f7f06f733 100644
--- a/openfpga/src/utils/decoder_library_utils.h
+++ b/openfpga/src/utils/decoder_library_utils.h
@@ -15,6 +15,8 @@ size_t find_mux_local_decoder_addr_size(const size_t& data_size);
 
 size_t find_memory_decoder_addr_size(const size_t& num_mems);
 
+size_t find_memory_decoder_data_size(const size_t& num_addr);
+
 DecoderId add_mux_local_decoder_to_library(DecoderLibrary& decoder_lib, 
                                            const size_t data_size);
 

From 51e1559352c5a64e909ca391622c8550c1e51088 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 30 May 2020 19:12:46 -0600
Subject: [PATCH 611/645] add fabric bitstream support for memory bank
 configuration protocol

---
 .../fpga_bitstream/build_fabric_bitstream.cpp | 102 ++++++++++++++++++
 .../src/fpga_bitstream/fabric_bitstream.cpp   |  26 ++++-
 .../src/fpga_bitstream/fabric_bitstream.h     |  20 +++-
 3 files changed, 141 insertions(+), 7 deletions(-)

diff --git a/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp b/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp
index f281a72dc..1be2025b3 100644
--- a/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp
+++ b/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp
@@ -15,6 +15,7 @@
 #include "openfpga_reserved_words.h"
 #include "openfpga_naming.h"
 
+#include "decoder_library_utils.h"
 #include "bitstream_manager_utils.h"
 #include "build_fabric_bitstream.h"
 
@@ -73,6 +74,90 @@ void rec_build_module_fabric_dependent_chain_bitstream(const BitstreamManager& b
   }
 }
 
+/********************************************************************
+ * This function aims to build a bitstream for memory-bank protocol
+ * It will walk through all the configurable children under a module
+ * in a recursive way, following a Depth-First Search (DFS) strategy
+ * For each configuration child, we use its instance name as a key to spot the 
+ * configuration bits in bitstream manager.
+ * Note that it is guarentee that the instance name in module manager is 
+ * consistent with the block names in bitstream manager
+ * We use this link to reorganize the bitstream in the sequence of memories as we stored
+ * in the configurable_children() and configurable_child_instances() of each module of module manager 
+ *
+ * In such configuration organization, each memory cell has an unique index.
+ * Using this index, we can infer the address codes for both BL and WL decoders.
+ * Note that, we must get the number of BLs and WLs before using this function!
+ *******************************************************************/
+static 
+void rec_build_module_fabric_dependent_memory_bank_bitstream(const BitstreamManager& bitstream_manager,
+                                                             const ConfigBlockId& parent_block,
+                                                             const ModuleManager& module_manager,
+                                                             const ModuleId& parent_module,
+                                                             const size_t& bl_addr_size,
+                                                             const size_t& wl_addr_size,
+                                                             const size_t& num_bls,
+                                                             const size_t& num_wls, 
+                                                             size_t& cur_mem_index,
+                                                             FabricBitstream& fabric_bitstream) {
+
+  /* Depth-first search: if we have any children in the parent_block, 
+   * we dive to the next level first! 
+   */
+  if (0 < bitstream_manager.block_children(parent_block).size()) {
+    for (size_t child_id = 0; child_id < module_manager.configurable_children(parent_module).size(); ++child_id) {
+      ModuleId child_module = module_manager.configurable_children(parent_module)[child_id]; 
+      size_t child_instance = module_manager.configurable_child_instances(parent_module)[child_id]; 
+      /* Get the instance name and ensure it is not empty */
+      std::string instance_name = module_manager.instance_name(parent_module, child_module, child_instance);
+       
+      /* Find the child block that matches the instance name! */ 
+      ConfigBlockId child_block = bitstream_manager.find_child_block(parent_block, instance_name); 
+      /* We must have one valid block id! */
+      if (true != bitstream_manager.valid_block_id(child_block))
+      VTR_ASSERT(true == bitstream_manager.valid_block_id(child_block));
+
+      /* Go recursively */
+      rec_build_module_fabric_dependent_memory_bank_bitstream(bitstream_manager, child_block,
+                                                              module_manager, child_module,
+                                                              bl_addr_size, wl_addr_size,
+                                                              num_bls, num_wls,
+                                                              cur_mem_index,
+                                                              fabric_bitstream);
+    }
+    /* Ensure that there should be no configuration bits in the parent block */
+    VTR_ASSERT(0 == bitstream_manager.block_bits(parent_block).size());
+  }
+
+  /* Note that, reach here, it means that this is a leaf node. 
+   * We add the configuration bits to the fabric_bitstream,
+   * And then, we can return
+   */
+  for (const ConfigBitId& config_bit : bitstream_manager.block_bits(parent_block)) {
+    FabricBitId fabric_bit = fabric_bitstream.add_bit(config_bit);
+  
+    /* Find BL address */
+    size_t cur_bl_index = cur_mem_index / num_bls;
+    std::vector<size_t> bl_addr_bits_vec = itobin_vec(cur_bl_index, bl_addr_size);
+
+    /* Find WL address */
+    size_t cur_wl_index = cur_mem_index % num_wls;
+    std::vector<size_t> wl_addr_bits_vec = itobin_vec(cur_wl_index, wl_addr_size);
+
+    /* Set BL address */
+    fabric_bitstream.set_bit_bl_address(fabric_bit, bl_addr_bits_vec);
+
+    /* Set WL address */
+    fabric_bitstream.set_bit_wl_address(fabric_bit, wl_addr_bits_vec);
+    
+    /* Set data input */
+    fabric_bitstream.set_bit_din(fabric_bit, bitstream_manager.bit_value(config_bit));
+
+    /* Increase the memory index */
+    cur_mem_index++;
+  }
+}
+
 /********************************************************************
  * This function aims to build a bitstream for frame-based configuration protocol
  * It will walk through all the configurable children under a module
@@ -287,6 +372,23 @@ void build_module_fabric_dependent_bitstream(const ConfigProtocol& config_protoc
     break;
   }
   case CONFIG_MEM_MEMORY_BANK: { 
+    size_t cur_mem_index = 0;
+    /* Find BL address port size */
+    ModulePortId bl_addr_port = module_manager.find_module_port(top_module, std::string(MEMORY_BL_PORT_NAME));
+    BasicPort bl_addr_port_info = module_manager.module_port(top_module, bl_addr_port);
+    size_t num_bls = find_memory_decoder_data_size(bl_addr_port_info.get_width()); 
+
+    /* Find WL address port size */
+    ModulePortId wl_addr_port = module_manager.find_module_port(top_module, std::string(MEMORY_WL_PORT_NAME));
+    BasicPort wl_addr_port_info = module_manager.module_port(top_module, wl_addr_port);
+    size_t num_wls = find_memory_decoder_data_size(wl_addr_port_info.get_width()); 
+
+    rec_build_module_fabric_dependent_memory_bank_bitstream(bitstream_manager, top_block,
+                                                            module_manager, top_module, 
+                                                            bl_addr_port_info.get_width(),
+                                                            wl_addr_port_info.get_width(),
+                                                            num_bls, num_wls,
+                                                            cur_mem_index, fabric_bitstream);
     break;
   }
   case CONFIG_MEM_FRAME_BASED: {
diff --git a/openfpga/src/fpga_bitstream/fabric_bitstream.cpp b/openfpga/src/fpga_bitstream/fabric_bitstream.cpp
index 7306eba01..1e318a530 100644
--- a/openfpga/src/fpga_bitstream/fabric_bitstream.cpp
+++ b/openfpga/src/fpga_bitstream/fabric_bitstream.cpp
@@ -31,7 +31,18 @@ std::vector<size_t> FabricBitstream::bit_address(const FabricBitId& bit_id) cons
   /* Ensure a valid id */
   VTR_ASSERT(true == valid_bit_id(bit_id));
 
-  return bit_addresses_[bit_id];
+  return bit_addresses_[bit_id][0];
+}
+
+std::vector<size_t> FabricBitstream::bit_bl_address(const FabricBitId& bit_id) const {
+  return bit_address(bit_id);
+}
+
+std::vector<size_t> FabricBitstream::bit_wl_address(const FabricBitId& bit_id) const {
+  /* Ensure a valid id */
+  VTR_ASSERT(true == valid_bit_id(bit_id));
+
+  return bit_addresses_[bit_id][1];
 }
 
 bool FabricBitstream::bit_din(const FabricBitId& bit_id) const {
@@ -58,7 +69,18 @@ FabricBitId FabricBitstream::add_bit(const ConfigBitId& config_bit_id) {
 void FabricBitstream::set_bit_address(const FabricBitId& bit_id,
                                       const std::vector<size_t>& address) {
   VTR_ASSERT(true == valid_bit_id(bit_id));
-  bit_addresses_[bit_id] = address;
+  bit_addresses_[bit_id][0] = address;
+}
+
+void FabricBitstream::set_bit_bl_address(const FabricBitId& bit_id,
+                                         const std::vector<size_t>& address) {
+  set_bit_address(bit_id, address);
+}
+
+void FabricBitstream::set_bit_wl_address(const FabricBitId& bit_id,
+                                         const std::vector<size_t>& address) {
+  VTR_ASSERT(true == valid_bit_id(bit_id));
+  bit_addresses_[bit_id][1] = address;
 }
 
 void FabricBitstream::set_bit_din(const FabricBitId& bit_id,
diff --git a/openfpga/src/fpga_bitstream/fabric_bitstream.h b/openfpga/src/fpga_bitstream/fabric_bitstream.h
index 12d1c7885..519330dae 100644
--- a/openfpga/src/fpga_bitstream/fabric_bitstream.h
+++ b/openfpga/src/fpga_bitstream/fabric_bitstream.h
@@ -13,11 +13,11 @@
  * By using the link between ArchBitstreamManager and FabricBitstream, 
  * we can build a sequence of configuration bits to fit different configuration protocols.
  *
- *     +----------------------+                 +--------------------------+
- *     |                      |   ConfigBitId   |                          |
+ *     +----------------------+                 +-------------------+
+ *     |                      |   ConfigBitId   |                   |
  *     | ArchBitstreamManager |---------------->|  FabricBitstream  |
- *     |                      |                 |                          |   
- *     +----------------------+                 +--------------------------+ 
+ *     |                      |                 |                   |   
+ *     +----------------------+                 +-------------------+ 
  *
  * Restrictions:
  * 1. Each block inside BitstreamManager should have only 1 parent block 
@@ -53,6 +53,8 @@ class FabricBitstream {
 
     /* Find the address of bitstream */
     std::vector<size_t> bit_address(const FabricBitId& bit_id) const;
+    std::vector<size_t> bit_bl_address(const FabricBitId& bit_id) const;
+    std::vector<size_t> bit_wl_address(const FabricBitId& bit_id) const;
 
     /* Find the data-in of bitstream */
     bool bit_din(const FabricBitId& bit_id) const;
@@ -64,6 +66,12 @@ class FabricBitstream {
     void set_bit_address(const FabricBitId& bit_id,
                          const std::vector<size_t>& address);
 
+    void set_bit_bl_address(const FabricBitId& bit_id,
+                            const std::vector<size_t>& address);
+
+    void set_bit_wl_address(const FabricBitId& bit_id,
+                            const std::vector<size_t>& address);
+
     void set_bit_din(const FabricBitId& bit_id,
                      const bool& din);
 
@@ -83,8 +91,10 @@ class FabricBitstream {
     /* Address bits: this is designed for memory decoders
      * Here we store the binary format of the address, which can be loaded
      * to the configuration protocol directly 
+     *
+     * We use a 2-element array, as we may have a BL address and a WL address
      */
-    vtr::vector<FabricBitId, std::vector<size_t>> bit_addresses_;
+    vtr::vector<FabricBitId, std::array<std::vector<size_t>, 2>> bit_addresses_;
 
     /* Data input (Din) bits: this is designed for memory decoders */
     vtr::vector<FabricBitId, bool> bit_dins_;

From e14c39e14cc2b8329498866b8b0f6d7d21faed80 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 30 May 2020 20:04:44 -0600
Subject: [PATCH 612/645] update Verilog full testbench generation to support
 memory bank configuration protocol

---
 .../fpga_verilog/verilog_top_testbench.cpp    | 264 +++++++++++++++++-
 1 file changed, 257 insertions(+), 7 deletions(-)

diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
index 68d1e3dba..e741e16ee 100644
--- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
@@ -103,6 +103,51 @@ void print_verilog_top_testbench_config_chain_port(std::fstream& fp) {
   fp << generate_verilog_port(VERILOG_PORT_WIRE, config_chain_tail_port) << ";" << std::endl;
 }
 
+/********************************************************************
+ * Print local wires for memory bank configuration protocols
+ *******************************************************************/
+static 
+void print_verilog_top_testbench_memory_bank_port(std::fstream& fp,
+                                                  const ModuleManager& module_manager,
+                                                  const ModuleId& top_module) {
+  /* Validate the file stream */
+  valid_file_stream(fp);
+
+  /* Print the address port for the Bit-Line decoder here */
+  print_verilog_comment(fp, std::string("---- Address port for Bit-Line decoder -----"));
+  ModulePortId bl_addr_port_id = module_manager.find_module_port(top_module,
+                                                                 std::string(MEMORY_BL_PORT_NAME));
+  BasicPort bl_addr_port = module_manager.module_port(top_module, bl_addr_port_id);
+
+  fp << generate_verilog_port(VERILOG_PORT_REG, bl_addr_port) << ";" << std::endl;
+
+  /* Print the address port for the Word-Line decoder here */
+  print_verilog_comment(fp, std::string("---- Address port for Word-Line decoder -----"));
+  ModulePortId wl_addr_port_id = module_manager.find_module_port(top_module,
+                                                                 std::string(MEMORY_WL_PORT_NAME));
+  BasicPort wl_addr_port = module_manager.module_port(top_module, wl_addr_port_id);
+
+  fp << generate_verilog_port(VERILOG_PORT_REG, wl_addr_port) << ";" << std::endl;
+
+  /* Print the data-input port for the frame-based decoder here */
+  print_verilog_comment(fp, std::string("---- Data input port for frame-based decoder -----"));
+  ModulePortId din_port_id = module_manager.find_module_port(top_module,
+                                                             std::string(DECODER_DATA_IN_PORT_NAME));
+  BasicPort din_port = module_manager.module_port(top_module, din_port_id);
+  fp << generate_verilog_port(VERILOG_PORT_REG, din_port) << ";" << std::endl;
+
+  /* Wire the INVERTED programming clock to the enable signal !!! */
+  print_verilog_comment(fp, std::string("---- Wire enable port of frame-based decoder to inverted programming clock -----"));
+  ModulePortId en_port_id = module_manager.find_module_port(top_module,
+                                                            std::string(DECODER_ENABLE_PORT_NAME));
+  BasicPort en_port = module_manager.module_port(top_module, en_port_id);
+  BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME), 1);
+
+  fp << generate_verilog_port(VERILOG_PORT_WIRE, en_port) << ";" << std::endl;
+  print_verilog_wire_connection(fp, en_port, prog_clock_port, true);
+}
+
+
 /********************************************************************
  * Print local wires for frame-based decoder protocols
  *******************************************************************/
@@ -155,7 +200,7 @@ void print_verilog_top_testbench_config_protocol_port(std::fstream& fp,
     print_verilog_top_testbench_config_chain_port(fp);
     break;
   case CONFIG_MEM_MEMORY_BANK:
-    /* TODO */
+    print_verilog_top_testbench_memory_bank_port(fp, module_manager, top_module);
     break;
   case CONFIG_MEM_FRAME_BASED:
     print_verilog_top_testbench_frame_decoder_port(fp, module_manager, top_module);
@@ -528,9 +573,9 @@ size_t calculate_num_config_clock_cycles(const e_config_protocol_type& sram_orgz
     num_config_clock_cycles = 2;
     break;
   case CONFIG_MEM_SCAN_CHAIN:
-  case CONFIG_MEM_MEMORY_BANK:
-    /* TODO */
+    /* Fast configuraiton is not applicable to configuration chain protocol*/
     break;
+  case CONFIG_MEM_MEMORY_BANK:
   case CONFIG_MEM_FRAME_BASED: {
     /* For fast configuration, we will skip all the zero data points */
     if (true == fast_configuration) {
@@ -644,6 +689,89 @@ void print_verilog_top_testbench_load_bitstream_task_configuration_chain(std::fs
   fp << std::endl;
 }
 
+/********************************************************************
+ * Print tasks (processes) in Verilog format, 
+ * which is very useful in generating stimuli for each clock cycle 
+ * This function is tuned for memory bank manipulation: 
+ * During each programming cycle, we feed
+ * - an address to the BL address port of top module
+ * - an address to the WL address port of top module
+ * - a data input to the din port of top module
+ *******************************************************************/
+static 
+void print_verilog_top_testbench_load_bitstream_task_memory_bank(std::fstream& fp,
+                                                                 const ModuleManager& module_manager,
+                                                                 const ModuleId& top_module) {
+
+  /* Validate the file stream */
+  valid_file_stream(fp);
+
+  ModulePortId en_port_id = module_manager.find_module_port(top_module,
+                                                            std::string(DECODER_ENABLE_PORT_NAME));
+  BasicPort en_port = module_manager.module_port(top_module, en_port_id);
+
+  ModulePortId bl_addr_port_id = module_manager.find_module_port(top_module,
+                                                                 std::string(MEMORY_BL_PORT_NAME));
+  BasicPort bl_addr_port = module_manager.module_port(top_module, bl_addr_port_id);
+  BasicPort bl_addr_value = bl_addr_port;
+  bl_addr_value.set_name(std::string(MEMORY_BL_PORT_NAME) + std::string("_val"));
+
+  ModulePortId wl_addr_port_id = module_manager.find_module_port(top_module,
+                                                                 std::string(MEMORY_WL_PORT_NAME));
+  BasicPort wl_addr_port = module_manager.module_port(top_module, wl_addr_port_id);
+  BasicPort wl_addr_value = wl_addr_port;
+  wl_addr_value.set_name(std::string(MEMORY_WL_PORT_NAME) + std::string("_val"));
+
+  ModulePortId din_port_id = module_manager.find_module_port(top_module,
+                                                             std::string(DECODER_DATA_IN_PORT_NAME));
+  BasicPort din_port = module_manager.module_port(top_module, din_port_id);
+  BasicPort din_value = din_port;
+  din_value.set_name(std::string(DECODER_DATA_IN_PORT_NAME) + std::string("_val"));
+
+  /* Add an empty line as splitter */
+  fp << std::endl;
+
+  /* Feed the address and data input at each falling edge of programming clock 
+   * As the enable signal is wired to the programming clock, we should synchronize
+   * address and data with the enable signal
+   */
+  print_verilog_comment(fp, std::string("----- Task: assign BL and WL address, and data values at rising edge of enable signal -----"));
+  fp << "task " << std::string(TOP_TESTBENCH_PROG_TASK_NAME) << ";" << std::endl;
+  fp << generate_verilog_port(VERILOG_PORT_INPUT, bl_addr_value) << ";" << std::endl;
+  fp << generate_verilog_port(VERILOG_PORT_INPUT, wl_addr_value) << ";" << std::endl;
+  fp << generate_verilog_port(VERILOG_PORT_INPUT, din_value) << ";" << std::endl;
+  fp << "\tbegin" << std::endl;
+  fp << "\t\t@(posedge " << generate_verilog_port(VERILOG_PORT_CONKT, en_port) << ");" << std::endl;
+
+  fp << "\t\t\t"; 
+  fp << generate_verilog_port(VERILOG_PORT_CONKT, bl_addr_port);
+  fp << " = "; 
+  fp << generate_verilog_port(VERILOG_PORT_CONKT, bl_addr_value);
+  fp << ";" << std::endl;
+  fp << std::endl;
+
+  fp << "\t\t\t"; 
+  fp << generate_verilog_port(VERILOG_PORT_CONKT, wl_addr_port);
+  fp << " = "; 
+  fp << generate_verilog_port(VERILOG_PORT_CONKT, wl_addr_value);
+  fp << ";" << std::endl;
+  fp << std::endl;
+
+  fp << "\t\t\t"; 
+  fp << generate_verilog_port(VERILOG_PORT_CONKT, din_port);
+  fp << " = "; 
+  fp << generate_verilog_port(VERILOG_PORT_CONKT, din_value);
+  fp << ";" << std::endl;
+  fp << std::endl;
+
+  fp << "\tend" << std::endl;
+  fp << "endtask" << std::endl;
+
+  /* Add an empty line as splitter */
+  fp << std::endl;
+}
+
+
 /********************************************************************
  * Print tasks (processes) in Verilog format, 
  * which is very useful in generating stimuli for each clock cycle 
@@ -727,9 +855,9 @@ void print_verilog_top_testbench_load_bitstream_task(std::fstream& fp,
     print_verilog_top_testbench_load_bitstream_task_configuration_chain(fp);
     break;
   case CONFIG_MEM_MEMORY_BANK:
-    /* TODO: 
-    dump_verilog_top_testbench_stimuli_serial_version_tasks_memory_bank(cur_sram_orgz_info, fp);
-     */
+    print_verilog_top_testbench_load_bitstream_task_memory_bank(fp,
+                                                                module_manager,
+                                                                top_module);
     break;
   case CONFIG_MEM_FRAME_BASED:
     print_verilog_top_testbench_load_bitstream_task_frame_decoder(fp,
@@ -1028,6 +1156,126 @@ void print_verilog_top_testbench_configuration_chain_bitstream(std::fstream& fp,
   print_verilog_comment(fp, "----- End bitstream loading during configuration phase -----");
 }
 
+/********************************************************************
+ * Print stimulus for a FPGA fabric with a memory bank configuration protocol 
+ * where configuration bits are programming in serial (one by one)
+ *
+ * We will use the programming task function created before
+ *******************************************************************/
+static 
+void print_verilog_top_testbench_memory_bank_bitstream(std::fstream& fp,
+                                                       const bool& fast_configuration,
+                                                       const ModuleManager& module_manager,
+                                                       const ModuleId& top_module,
+                                                       const FabricBitstream& fabric_bitstream) {
+  /* Validate the file stream */
+  valid_file_stream(fp);
+
+  /* Feed addresss and data input pair one by one 
+   * Note: the first cycle is reserved for programming reset
+   * We should give dummy values 
+   */
+  ModulePortId bl_addr_port_id = module_manager.find_module_port(top_module,
+                                                                 std::string(MEMORY_BL_PORT_NAME));
+  BasicPort bl_addr_port = module_manager.module_port(top_module, bl_addr_port_id);
+  std::vector<size_t> initial_bl_addr_values(bl_addr_port.get_width(), 0);
+
+  ModulePortId wl_addr_port_id = module_manager.find_module_port(top_module,
+                                                                 std::string(MEMORY_WL_PORT_NAME));
+  BasicPort wl_addr_port = module_manager.module_port(top_module, wl_addr_port_id);
+  std::vector<size_t> initial_wl_addr_values(wl_addr_port.get_width(), 0);
+
+  ModulePortId din_port_id = module_manager.find_module_port(top_module,
+                                                             std::string(DECODER_DATA_IN_PORT_NAME));
+  BasicPort din_port = module_manager.module_port(top_module, din_port_id);
+  std::vector<size_t> initial_din_values(din_port.get_width(), 0);
+
+  print_verilog_comment(fp, "----- Begin bitstream loading during configuration phase -----");
+  fp << "initial" << std::endl;
+  fp << "\tbegin" << std::endl;
+  print_verilog_comment(fp, "----- Address port default input -----");
+  fp << "\t\t";
+  fp << generate_verilog_port_constant_values(bl_addr_port, initial_bl_addr_values);
+  fp << generate_verilog_port_constant_values(wl_addr_port, initial_wl_addr_values);
+  fp << ";";
+
+  print_verilog_comment(fp, "----- Data-input port default input -----");
+  fp << "\t\t";
+  fp << generate_verilog_port_constant_values(din_port, initial_din_values);
+  fp << ";";
+
+  fp << std::endl;
+
+  /* Attention: the configuration chain protcol requires the last configuration bit is fed first
+   * We will visit the fabric bitstream in a reverse way  
+   */
+  for (const FabricBitId& bit_id : fabric_bitstream.bits()) {
+    /* When fast configuration is enabled, we skip zero data_in values */
+    if ((true == fast_configuration)
+      && (false == fabric_bitstream.bit_din(bit_id))) {
+      continue;
+    }
+
+    fp << "\t\t" << std::string(TOP_TESTBENCH_PROG_TASK_NAME);
+    fp << "(" << bl_addr_port.get_width() << "'b";
+    VTR_ASSERT(bl_addr_port.get_width() == fabric_bitstream.bit_bl_address(bit_id).size());
+    for (const size_t& addr_bit : fabric_bitstream.bit_bl_address(bit_id)) {
+      fp << addr_bit; 
+    }
+
+    fp << ", ";
+    fp << wl_addr_port.get_width() << "'b";
+    VTR_ASSERT(wl_addr_port.get_width() == fabric_bitstream.bit_wl_address(bit_id).size());
+    for (const size_t& addr_bit : fabric_bitstream.bit_wl_address(bit_id)) {
+      fp << addr_bit; 
+    }
+
+    fp << ", ";
+    fp <<"1'b";
+    if (true == fabric_bitstream.bit_din(bit_id)) {
+      fp << "1";
+    } else {
+      VTR_ASSERT(false == fabric_bitstream.bit_din(bit_id));
+      fp << "0";
+    }
+    fp << ");" << std::endl;
+  }
+
+  /* Disable the address and din */
+  fp << "\t\t" << std::string(TOP_TESTBENCH_PROG_TASK_NAME);
+  fp << "(" << bl_addr_port.get_width() << "'b";
+  std::vector<size_t> all_zero_bl_addr(bl_addr_port.get_width(), 0);
+  for (const size_t& addr_bit : all_zero_bl_addr) {
+    fp << addr_bit; 
+  }
+
+  fp << ", ";
+  fp << wl_addr_port.get_width() << "'b";
+  std::vector<size_t> all_zero_wl_addr(wl_addr_port.get_width(), 0);
+  for (const size_t& addr_bit : all_zero_wl_addr) {
+    fp << addr_bit; 
+  }
+
+  fp << ", ";
+  fp <<"1'b0";
+  fp << ");" << std::endl;
+
+  /* Raise the flag of configuration done when bitstream loading is complete */
+  BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME), 1);
+  fp << "\t\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ");" << std::endl;
+  
+  BasicPort config_done_port(std::string(TOP_TB_CONFIG_DONE_PORT_NAME), 1);
+  fp << "\t\t\t";
+  fp << generate_verilog_port(VERILOG_PORT_CONKT, config_done_port);
+  fp << " <= ";
+  std::vector<size_t> config_done_enable_values(config_done_port.get_width(), 1);
+  fp << generate_verilog_constant_values(config_done_enable_values);
+  fp << ";" << std::endl;
+
+  fp << "\tend" << std::endl;
+  print_verilog_comment(fp, "----- End bitstream loading during configuration phase -----");
+}
+
 /********************************************************************
  * Print stimulus for a FPGA fabric with a frame-based configuration protocol 
  * where configuration bits are programming in serial (one by one)
@@ -1151,7 +1399,9 @@ void print_verilog_top_testbench_bitstream(std::fstream& fp,
     print_verilog_top_testbench_configuration_chain_bitstream(fp, bitstream_manager, fabric_bitstream);
     break;
   case CONFIG_MEM_MEMORY_BANK:
-    /* TODO */
+    print_verilog_top_testbench_memory_bank_bitstream(fp, fast_configuration,
+                                                      module_manager, top_module,
+                                                      fabric_bitstream);
     break;
   case CONFIG_MEM_FRAME_BASED:
     print_verilog_top_testbench_frame_decoder_bitstream(fp, fast_configuration,

From a1ec6833c29b5c07bcce3522599acb3025e8dad1 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 30 May 2020 20:07:06 -0600
Subject: [PATCH 613/645] add memory bank example arch xml

---
 .../k4_N4_40nm_bank_openfpga.xml              | 229 ++++++++++++++++++
 1 file changed, 229 insertions(+)
 create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml

diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml
new file mode 100644
index 000000000..7de3ec8c4
--- /dev/null
+++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml
@@ -0,0 +1,229 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="4"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="16"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="sram" name="config_latch" prefix="config_latch" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/config_latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/config_latch.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="bl" prefix="bl" size="1"/>
+       <port type="wl" prefix="wl" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="Qb" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="config_latch" default_val="1"/>
+      <port type="input" prefix="outpad" size="1"/>
+      <port type="output" prefix="inpad" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="memory_bank" circuit_model_name="config_latch"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="static_dff"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>
+<openfpga_simulation_setting>
+  <clock_setting>
+    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
+    <programming frequency="100e6"/>
+  </clock_setting>
+  <simulator_option>
+    <operating_condition temperature="25"/>
+    <output_log verbose="false" captab="false"/>
+    <accuracy type="abs" value="1e-13"/>
+    <runtime fast_simulation="true"/>
+  </simulator_option>
+  <monte_carlo num_simulation_points="2"/>
+  <measurement_setting>
+    <slew>
+      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
+      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
+    </slew>
+    <delay>
+      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
+      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
+    </delay>
+  </measurement_setting>
+  <stimulus>
+    <clock>
+      <rise slew_type="abs" slew_time="20e-12" />
+      <fall slew_type="abs" slew_time="20e-12" />
+    </clock>
+    <input>
+      <rise slew_type="abs" slew_time="25e-12" />
+      <fall slew_type="abs" slew_time="25e-12" />
+    </input>
+  </stimulus>
+</openfpga_simulation_setting>

From 0bee70bee6ee2997551a36f5294bd9c50e4776b5 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 30 May 2020 20:53:19 -0600
Subject: [PATCH 614/645] finish memory bank configuration protocol support.

---
 openfpga/src/base/openfpga_naming.cpp         |  26 +---
 openfpga/src/base/openfpga_naming.h           |  11 +-
 openfpga/src/fabric/build_decoder_modules.cpp |   6 +-
 openfpga/src/fabric/build_memory_modules.cpp  |   6 +-
 .../src/fabric/build_top_module_memory.cpp    |   4 +-
 .../fpga_bitstream/build_fabric_bitstream.cpp |   4 +-
 .../src/fpga_verilog/verilog_decoders.cpp     | 134 +++++++++++++++++-
 .../fpga_verilog/verilog_top_testbench.cpp    |  17 ++-
 openfpga/src/utils/module_manager_utils.cpp   |   6 +-
 9 files changed, 166 insertions(+), 48 deletions(-)

diff --git a/openfpga/src/base/openfpga_naming.cpp b/openfpga/src/base/openfpga_naming.cpp
index 1c792d26d..44eb2c8cd 100644
--- a/openfpga/src/base/openfpga_naming.cpp
+++ b/openfpga/src/base/openfpga_naming.cpp
@@ -146,23 +146,9 @@ std::string generate_mux_local_decoder_subckt_name(const size_t& addr_size,
  * Generate the module name of a decoder
  * for frame-based memories
  ***********************************************/
-std::string generate_frame_memory_decoder_subckt_name(const size_t& addr_size, 
-                                                      const size_t& data_size) {
-  std::string subckt_name = "frame_decoder";
-  subckt_name += std::to_string(addr_size);
-  subckt_name += "to";
-  subckt_name += std::to_string(data_size);
-
-  return subckt_name;
-} 
-
-/************************************************
- * Generate the module name of a bit-line decoder
- * for memories
- ***********************************************/
-std::string generate_bl_memory_decoder_subckt_name(const size_t& addr_size, 
-                                                   const size_t& data_size) {
-  std::string subckt_name = "bl_decoder";
+std::string generate_memory_decoder_subckt_name(const size_t& addr_size, 
+                                                const size_t& data_size) {
+  std::string subckt_name = "decoder";
   subckt_name += std::to_string(addr_size);
   subckt_name += "to";
   subckt_name += std::to_string(data_size);
@@ -174,9 +160,9 @@ std::string generate_bl_memory_decoder_subckt_name(const size_t& addr_size,
  * Generate the module name of a word-line decoder
  * for memories
  ***********************************************/
-std::string generate_wl_memory_decoder_subckt_name(const size_t& addr_size, 
-                                                   const size_t& data_size) {
-  std::string subckt_name = "wl_decoder";
+std::string generate_memory_decoder_with_data_in_subckt_name(const size_t& addr_size, 
+                                                             const size_t& data_size) {
+  std::string subckt_name = "decoder_with_data_in_";
   subckt_name += std::to_string(addr_size);
   subckt_name += "to";
   subckt_name += std::to_string(data_size);
diff --git a/openfpga/src/base/openfpga_naming.h b/openfpga/src/base/openfpga_naming.h
index 534bf2a78..3634be27a 100644
--- a/openfpga/src/base/openfpga_naming.h
+++ b/openfpga/src/base/openfpga_naming.h
@@ -50,14 +50,11 @@ std::string generate_mux_branch_subckt_name(const CircuitLibrary& circuit_lib,
 std::string generate_mux_local_decoder_subckt_name(const size_t& addr_size, 
                                                    const size_t& data_size); 
 
-std::string generate_frame_memory_decoder_subckt_name(const size_t& addr_size, 
-                                                      const size_t& data_size);
+std::string generate_memory_decoder_subckt_name(const size_t& addr_size, 
+                                                const size_t& data_size);
 
-std::string generate_bl_memory_decoder_subckt_name(const size_t& addr_size, 
-                                                   const size_t& data_size);
-
-std::string generate_wl_memory_decoder_subckt_name(const size_t& addr_size, 
-                                                   const size_t& data_size);
+std::string generate_memory_decoder_with_data_in_subckt_name(const size_t& addr_size, 
+                                                             const size_t& data_size);
 
 std::string generate_segment_wire_subckt_name(const std::string& wire_model_name, 
                                               const size_t& segment_id); 
diff --git a/openfpga/src/fabric/build_decoder_modules.cpp b/openfpga/src/fabric/build_decoder_modules.cpp
index fb8a29e5c..eecb31344 100644
--- a/openfpga/src/fabric/build_decoder_modules.cpp
+++ b/openfpga/src/fabric/build_decoder_modules.cpp
@@ -45,7 +45,7 @@ ModuleId build_frame_memory_decoder_module(ModuleManager& module_manager,
   size_t data_size = decoder_lib.data_size(decoder);
 
   /* Create a name for the local encoder */
-  std::string module_name = generate_frame_memory_decoder_subckt_name(addr_size, data_size);
+  std::string module_name = generate_memory_decoder_subckt_name(addr_size, data_size);
 
   /* Create a Verilog Module based on the circuit model, and add to module manager */
   ModuleId module_id = module_manager.add_module(module_name); 
@@ -100,7 +100,7 @@ ModuleId build_bl_memory_decoder_module(ModuleManager& module_manager,
   size_t data_size = decoder_lib.data_size(decoder);
 
   /* Create a name for the local encoder */
-  std::string module_name = generate_bl_memory_decoder_subckt_name(addr_size, data_size);
+  std::string module_name = generate_memory_decoder_with_data_in_subckt_name(addr_size, data_size);
 
   /* Create a Verilog Module based on the circuit model, and add to module manager */
   ModuleId module_id = module_manager.add_module(module_name); 
@@ -158,7 +158,7 @@ ModuleId build_wl_memory_decoder_module(ModuleManager& module_manager,
   size_t data_size = decoder_lib.data_size(decoder);
 
   /* Create a name for the local encoder */
-  std::string module_name = generate_wl_memory_decoder_subckt_name(addr_size, data_size);
+  std::string module_name = generate_memory_decoder_subckt_name(addr_size, data_size);
 
   /* Create a Verilog Module based on the circuit model, and add to module manager */
   ModuleId module_id = module_manager.add_module(module_name); 
diff --git a/openfpga/src/fabric/build_memory_modules.cpp b/openfpga/src/fabric/build_memory_modules.cpp
index 72d1315ad..e3c8a0c03 100644
--- a/openfpga/src/fabric/build_memory_modules.cpp
+++ b/openfpga/src/fabric/build_memory_modules.cpp
@@ -554,14 +554,14 @@ void build_frame_memory_module(ModuleManager& module_manager,
    * If we find one, we use the module.
    * Otherwise, we create one and add it to the decoder library
    */
-  DecoderId decoder_id = frame_decoder_lib.find_decoder(addr_size, data_size, true, true, use_data_inv);
+  DecoderId decoder_id = frame_decoder_lib.find_decoder(addr_size, data_size, true, false, use_data_inv);
   if (DecoderId::INVALID() == decoder_id) {
-    decoder_id = frame_decoder_lib.add_decoder(addr_size, data_size, true, true, use_data_inv);
+    decoder_id = frame_decoder_lib.add_decoder(addr_size, data_size, true, false, use_data_inv);
   }
   VTR_ASSERT(DecoderId::INVALID() != decoder_id);
 
   /* Create a module if not existed yet */
-  std::string decoder_module_name = generate_frame_memory_decoder_subckt_name(addr_size, data_size);
+  std::string decoder_module_name = generate_memory_decoder_subckt_name(addr_size, data_size);
   ModuleId decoder_module = module_manager.find_module(decoder_module_name);
   if (ModuleId::INVALID() == decoder_module) {
     decoder_module = build_frame_memory_decoder_module(module_manager,
diff --git a/openfpga/src/fabric/build_top_module_memory.cpp b/openfpga/src/fabric/build_top_module_memory.cpp
index 278a33f2d..0de55ca4e 100644
--- a/openfpga/src/fabric/build_top_module_memory.cpp
+++ b/openfpga/src/fabric/build_top_module_memory.cpp
@@ -545,7 +545,7 @@ void add_top_module_nets_cmos_memory_bank_config_bus(ModuleManager& module_manag
   VTR_ASSERT(DecoderId::INVALID() != bl_decoder_id);
 
   /* Create a module if not existed yet */
-  std::string bl_decoder_module_name = generate_bl_memory_decoder_subckt_name(bl_addr_size, num_bls);
+  std::string bl_decoder_module_name = generate_memory_decoder_with_data_in_subckt_name(bl_addr_size, num_bls);
   ModuleId bl_decoder_module = module_manager.find_module(bl_decoder_module_name);
   if (ModuleId::INVALID() == bl_decoder_module) {
     /* BL decoder has the same ports as the frame-based decoders
@@ -572,7 +572,7 @@ void add_top_module_nets_cmos_memory_bank_config_bus(ModuleManager& module_manag
   VTR_ASSERT(DecoderId::INVALID() != wl_decoder_id);
 
   /* Create a module if not existed yet */
-  std::string wl_decoder_module_name = generate_bl_memory_decoder_subckt_name(wl_addr_size, num_wls);
+  std::string wl_decoder_module_name = generate_memory_decoder_subckt_name(wl_addr_size, num_wls);
   ModuleId wl_decoder_module = module_manager.find_module(wl_decoder_module_name);
   if (ModuleId::INVALID() == wl_decoder_module) {
     /* BL decoder has the same ports as the frame-based decoders
diff --git a/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp b/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp
index 1be2025b3..a9c5b6ec7 100644
--- a/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp
+++ b/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp
@@ -374,12 +374,12 @@ void build_module_fabric_dependent_bitstream(const ConfigProtocol& config_protoc
   case CONFIG_MEM_MEMORY_BANK: { 
     size_t cur_mem_index = 0;
     /* Find BL address port size */
-    ModulePortId bl_addr_port = module_manager.find_module_port(top_module, std::string(MEMORY_BL_PORT_NAME));
+    ModulePortId bl_addr_port = module_manager.find_module_port(top_module, std::string(DECODER_BL_ADDRESS_PORT_NAME));
     BasicPort bl_addr_port_info = module_manager.module_port(top_module, bl_addr_port);
     size_t num_bls = find_memory_decoder_data_size(bl_addr_port_info.get_width()); 
 
     /* Find WL address port size */
-    ModulePortId wl_addr_port = module_manager.find_module_port(top_module, std::string(MEMORY_WL_PORT_NAME));
+    ModulePortId wl_addr_port = module_manager.find_module_port(top_module, std::string(DECODER_WL_ADDRESS_PORT_NAME));
     BasicPort wl_addr_port_info = module_manager.module_port(top_module, wl_addr_port);
     size_t num_wls = find_memory_decoder_data_size(wl_addr_port_info.get_width()); 
 
diff --git a/openfpga/src/fpga_verilog/verilog_decoders.cpp b/openfpga/src/fpga_verilog/verilog_decoders.cpp
index 64568515c..6e6025ea6 100644
--- a/openfpga/src/fpga_verilog/verilog_decoders.cpp
+++ b/openfpga/src/fpga_verilog/verilog_decoders.cpp
@@ -262,7 +262,7 @@ void print_verilog_arch_decoder_module(std::fstream& fp,
   VTR_ASSERT(true == valid_file_stream(fp));
 
   /* Create a name for the decoder */
-  std::string module_name = generate_frame_memory_decoder_subckt_name(addr_size, data_size);
+  std::string module_name = generate_memory_decoder_subckt_name(addr_size, data_size);
 
   /* Create a Verilog Module based on the circuit model, and add to module manager */
   ModuleId module_id = module_manager.find_module(module_name); 
@@ -377,6 +377,132 @@ void print_verilog_arch_decoder_module(std::fstream& fp,
   print_verilog_module_end(fp, module_name);
 }
 
+/***************************************************************************************
+ * Create a Verilog module for a decoder with data_in used as a configuration protocol 
+ * in FPGA architecture
+ *
+ *                     Address
+ *                   | | ... | 
+ *                   v v     v
+ *                 +-----------+
+ *        Enable->/             \<-data_in
+ *               /    Decoder    \
+ *              +-----------------+
+ *                | | | ... | | |
+ *                v v v     v v v
+ *                    Data output
+ *
+ *  The outputs are assumes to be one-hot codes (at most only one '1' exist)
+ *  Only the data output at the address bit will show data_in
+ *
+ *  The decoder has an enable signal which is active at logic '1'. 
+ *  When activated, the decoder will output decoding results to the data output port
+ *  Otherwise, the data output port will be always all-zero
+ ***************************************************************************************/
+static 
+void print_verilog_arch_decoder_with_data_in_module(std::fstream& fp, 
+                                                    const ModuleManager& module_manager,
+                                                    const DecoderLibrary& decoder_lib,
+                                                    const DecoderId& decoder) {
+  /* Get the number of inputs */
+  size_t addr_size = decoder_lib.addr_size(decoder);
+  size_t data_size = decoder_lib.data_size(decoder);
+  VTR_ASSERT(true == decoder_lib.use_data_in(decoder));
+
+  /* Validate the FILE handler */
+  VTR_ASSERT(true == valid_file_stream(fp));
+
+  /* Create a name for the decoder */
+  std::string module_name = generate_memory_decoder_with_data_in_subckt_name(addr_size, data_size);
+
+  /* Create a Verilog Module based on the circuit model, and add to module manager */
+  ModuleId module_id = module_manager.find_module(module_name); 
+  VTR_ASSERT(true == module_manager.valid_module_id(module_id));
+  /* Find module ports */
+  /* Enable port */
+  ModulePortId enable_port_id = module_manager.find_module_port(module_id, std::string(DECODER_ENABLE_PORT_NAME));
+  BasicPort enable_port = module_manager.module_port(module_id, enable_port_id);
+  /* Address port */
+  ModulePortId addr_port_id = module_manager.find_module_port(module_id, std::string(DECODER_ADDRESS_PORT_NAME));
+  BasicPort addr_port = module_manager.module_port(module_id, addr_port_id);
+  /* Find data-in port*/
+  ModulePortId din_port_id = module_manager.find_module_port(module_id, std::string(DECODER_DATA_IN_PORT_NAME));
+  BasicPort din_port = module_manager.module_port(module_id, din_port_id);
+  /* Find each output port */
+  ModulePortId data_port_id = module_manager.find_module_port(module_id, std::string(DECODER_DATA_OUT_PORT_NAME));
+  BasicPort data_port = module_manager.module_port(module_id, data_port_id);
+  /* Data port is registered. It should be outputted as 
+   *   output reg [lsb:msb] data 
+   */
+  BasicPort data_inv_port(std::string(DECODER_DATA_OUT_INV_PORT_NAME), data_size);
+  if (true == decoder_lib.use_data_inv_port(decoder)) {
+    ModulePortId data_inv_port_id = module_manager.find_module_port(module_id, std::string(DECODER_DATA_OUT_INV_PORT_NAME));
+    data_inv_port = module_manager.module_port(module_id, data_inv_port_id);
+  }
+
+  /* dump module definition + ports */
+  print_verilog_module_declaration(fp, module_manager, module_id);
+  /* Finish dumping ports */
+
+  print_verilog_comment(fp, std::string("----- BEGIN Verilog codes for Decoder convert " + std::to_string(addr_size) + "-bit addr to " + std::to_string(data_size) + "-bit data -----"));
+
+  /* Print the truth table of this decoder */
+  /* Internal logics */
+  /* Early exit: Corner case for data size = 1 the logic is very simple:
+   * data = addr;  
+   * data_inv = ~data_inv
+   */
+  if (1 == data_size) {
+    fp << "always@(" << generate_verilog_port(VERILOG_PORT_CONKT, addr_port);
+    fp << " or " << generate_verilog_port(VERILOG_PORT_CONKT, enable_port);
+    fp << ") begin" << std::endl;
+    fp << "\tif (" << generate_verilog_port(VERILOG_PORT_CONKT, enable_port) << " == 1'b1) begin" << std::endl;
+    fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, din_port) << ";" << std::endl; 
+    fp << "\t" << "end else begin" << std::endl;
+    fp << "\t\t" << generate_verilog_port_constant_values(data_port, std::vector<size_t>(1, 0)) << ";" << std::endl; 
+    fp << "\t" << "end" << std::endl;
+    fp << "end" << std::endl;
+
+    /* Depend on if the inverted data output port is needed or not */
+    if (true == decoder_lib.use_data_inv_port(decoder)) {
+      print_verilog_wire_connection(fp, data_inv_port, addr_port, true);
+    }
+
+    print_verilog_comment(fp, std::string("----- END Verilog codes for Decoder convert " + std::to_string(addr_size) + "-bit addr to " + std::to_string(data_size) + "-bit data -----"));
+
+    /* Put an end to the Verilog module */
+    print_verilog_module_end(fp, module_name);
+    return;
+  }
+
+  /* Only the selected data output bit will be set to the value of data_in, 
+   * other data output bits will be '0'
+   */
+  fp << "always@(" << generate_verilog_port(VERILOG_PORT_CONKT, addr_port);
+  fp << ", " << generate_verilog_port(VERILOG_PORT_CONKT, enable_port);
+  fp << ", " << generate_verilog_port(VERILOG_PORT_CONKT, din_port);
+  fp << ") begin" << std::endl;
+
+  fp << "\t" << generate_verilog_port_constant_values(data_port, ito1hot_vec(data_size, data_size)) << ";" << std::endl; 
+
+  fp << "\tif (" << generate_verilog_port(VERILOG_PORT_CONKT, enable_port) << " == 1'b1) begin" << std::endl;
+  fp << "\t\t" << data_port.get_name().c_str() << "[" << addr_port.get_name().c_str() << "]";
+  fp << " = " << generate_verilog_port(VERILOG_PORT_CONKT, din_port) << ";" << std::endl;
+
+  fp << "\t" << "end" << std::endl;
+
+  fp << "end" << std::endl;
+
+  if (true == decoder_lib.use_data_inv_port(decoder)) {
+    print_verilog_wire_connection(fp, data_inv_port, data_port, true);
+  }
+  
+  print_verilog_comment(fp, std::string("----- END Verilog codes for Decoder convert " + std::to_string(addr_size) + "-bit addr to " + std::to_string(data_size) + "-bit data -----"));
+
+  /* Put an end to the Verilog module */
+  print_verilog_module_end(fp, module_name);
+}
+
 /***************************************************************************************
  * This function will generate all the unique Verilog modules of decoders for 
  * configuration protocols in a FPGA fabric
@@ -407,7 +533,11 @@ void print_verilog_submodule_arch_decoders(const ModuleManager& module_manager,
 
   /* Generate Verilog modules for the found unique local encoders */
   for (const auto& decoder : decoder_lib.decoders()) {
-    print_verilog_arch_decoder_module(fp, module_manager, decoder_lib, decoder);
+    if (true == decoder_lib.use_data_in(decoder)) {
+      print_verilog_arch_decoder_with_data_in_module(fp, module_manager, decoder_lib, decoder);
+    } else {
+      print_verilog_arch_decoder_module(fp, module_manager, decoder_lib, decoder);
+    }
   }
 
   /* Close the file stream */
diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
index e741e16ee..670074d74 100644
--- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
@@ -116,7 +116,7 @@ void print_verilog_top_testbench_memory_bank_port(std::fstream& fp,
   /* Print the address port for the Bit-Line decoder here */
   print_verilog_comment(fp, std::string("---- Address port for Bit-Line decoder -----"));
   ModulePortId bl_addr_port_id = module_manager.find_module_port(top_module,
-                                                                 std::string(MEMORY_BL_PORT_NAME));
+                                                                 std::string(DECODER_BL_ADDRESS_PORT_NAME));
   BasicPort bl_addr_port = module_manager.module_port(top_module, bl_addr_port_id);
 
   fp << generate_verilog_port(VERILOG_PORT_REG, bl_addr_port) << ";" << std::endl;
@@ -124,7 +124,7 @@ void print_verilog_top_testbench_memory_bank_port(std::fstream& fp,
   /* Print the address port for the Word-Line decoder here */
   print_verilog_comment(fp, std::string("---- Address port for Word-Line decoder -----"));
   ModulePortId wl_addr_port_id = module_manager.find_module_port(top_module,
-                                                                 std::string(MEMORY_WL_PORT_NAME));
+                                                                 std::string(DECODER_WL_ADDRESS_PORT_NAME));
   BasicPort wl_addr_port = module_manager.module_port(top_module, wl_addr_port_id);
 
   fp << generate_verilog_port(VERILOG_PORT_REG, wl_addr_port) << ";" << std::endl;
@@ -711,13 +711,13 @@ void print_verilog_top_testbench_load_bitstream_task_memory_bank(std::fstream& f
   BasicPort en_port = module_manager.module_port(top_module, en_port_id);
 
   ModulePortId bl_addr_port_id = module_manager.find_module_port(top_module,
-                                                                 std::string(MEMORY_BL_PORT_NAME));
+                                                                 std::string(DECODER_BL_ADDRESS_PORT_NAME));
   BasicPort bl_addr_port = module_manager.module_port(top_module, bl_addr_port_id);
   BasicPort bl_addr_value = bl_addr_port;
   bl_addr_value.set_name(std::string(MEMORY_BL_PORT_NAME) + std::string("_val"));
 
   ModulePortId wl_addr_port_id = module_manager.find_module_port(top_module,
-                                                                 std::string(MEMORY_WL_PORT_NAME));
+                                                                 std::string(DECODER_WL_ADDRESS_PORT_NAME));
   BasicPort wl_addr_port = module_manager.module_port(top_module, wl_addr_port_id);
   BasicPort wl_addr_value = wl_addr_port;
   wl_addr_value.set_name(std::string(MEMORY_WL_PORT_NAME) + std::string("_val"));
@@ -1176,12 +1176,12 @@ void print_verilog_top_testbench_memory_bank_bitstream(std::fstream& fp,
    * We should give dummy values 
    */
   ModulePortId bl_addr_port_id = module_manager.find_module_port(top_module,
-                                                                 std::string(MEMORY_BL_PORT_NAME));
+                                                                 std::string(DECODER_BL_ADDRESS_PORT_NAME));
   BasicPort bl_addr_port = module_manager.module_port(top_module, bl_addr_port_id);
   std::vector<size_t> initial_bl_addr_values(bl_addr_port.get_width(), 0);
 
   ModulePortId wl_addr_port_id = module_manager.find_module_port(top_module,
-                                                                 std::string(MEMORY_WL_PORT_NAME));
+                                                                 std::string(DECODER_WL_ADDRESS_PORT_NAME));
   BasicPort wl_addr_port = module_manager.module_port(top_module, wl_addr_port_id);
   std::vector<size_t> initial_wl_addr_values(wl_addr_port.get_width(), 0);
 
@@ -1196,8 +1196,12 @@ void print_verilog_top_testbench_memory_bank_bitstream(std::fstream& fp,
   print_verilog_comment(fp, "----- Address port default input -----");
   fp << "\t\t";
   fp << generate_verilog_port_constant_values(bl_addr_port, initial_bl_addr_values);
+  fp << ";";
+  fp << std::endl;
+
   fp << generate_verilog_port_constant_values(wl_addr_port, initial_wl_addr_values);
   fp << ";";
+  fp << std::endl;
 
   print_verilog_comment(fp, "----- Data-input port default input -----");
   fp << "\t\t";
@@ -1312,6 +1316,7 @@ void print_verilog_top_testbench_frame_decoder_bitstream(std::fstream& fp,
   fp << "\t\t";
   fp << generate_verilog_port_constant_values(addr_port, initial_addr_values);
   fp << ";";
+  fp << std::endl;
 
   print_verilog_comment(fp, "----- Data-input port default input -----");
   fp << "\t\t";
diff --git a/openfpga/src/utils/module_manager_utils.cpp b/openfpga/src/utils/module_manager_utils.cpp
index ec871368a..0fe16987c 100644
--- a/openfpga/src/utils/module_manager_utils.cpp
+++ b/openfpga/src/utils/module_manager_utils.cpp
@@ -960,14 +960,14 @@ void add_module_nets_cmos_memory_frame_decoder_config_bus(ModuleManager& module_
   /* Search the decoder library and try to find one 
    * If not found, create a new module and add it to the module manager 
    */
-  DecoderId decoder_id = decoder_lib.find_decoder(addr_size, data_size, true, true, false);
+  DecoderId decoder_id = decoder_lib.find_decoder(addr_size, data_size, true, false, false);
   if (DecoderId::INVALID() == decoder_id) {
-    decoder_id = decoder_lib.add_decoder(addr_size, data_size, true, true, false);
+    decoder_id = decoder_lib.add_decoder(addr_size, data_size, true, false, false);
   }
   VTR_ASSERT(DecoderId::INVALID() != decoder_id);
 
   /* Create a module if not existed yet */
-  std::string decoder_module_name = generate_frame_memory_decoder_subckt_name(addr_size, data_size);
+  std::string decoder_module_name = generate_memory_decoder_subckt_name(addr_size, data_size);
   ModuleId decoder_module = module_manager.find_module(decoder_module_name);
   if (ModuleId::INVALID() == decoder_module) {
     decoder_module = build_frame_memory_decoder_module(module_manager,

From 73d4c835b739548d9aca2a18421c3b224e1143f9 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 30 May 2020 20:54:05 -0600
Subject: [PATCH 615/645] add regression test case for memory bank

---
 .../memory_bank/config/task.conf              | 34 +++++++++++++++++++
 1 file changed, 34 insertions(+)
 create mode 100644 openfpga_flow/tasks/openfpga_shell/full_testbench/memory_bank/config/task.conf

diff --git a/openfpga_flow/tasks/openfpga_shell/full_testbench/memory_bank/config/task.conf b/openfpga_flow/tasks/openfpga_shell/full_testbench/memory_bank/config/task.conf
new file mode 100644
index 000000000..b000c0ba6
--- /dev/null
+++ b/openfpga_flow/tasks/openfpga_shell/full_testbench/memory_bank/config/task.conf
@@ -0,0 +1,34 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+#vpr_fpga_verilog_formal_verification_top_netlist=

From 288294c23aed63f3b8170716e77ce3f84b3640cd Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 30 May 2020 20:56:54 -0600
Subject: [PATCH 616/645] add fast configuration test case for memory bank
 configuration protocol

---
 ...ast_configuration_example_script.openfpga} |  0
 .../fast_configuration_frame/config/task.conf |  2 +-
 .../fast_memory_bank/config/task.conf         | 34 +++++++++++++++++++
 3 files changed, 35 insertions(+), 1 deletion(-)
 rename openfpga_flow/OpenFPGAShellScripts/{configuration_frame_example_script.openfpga => fast_configuration_example_script.openfpga} (100%)
 create mode 100644 openfpga_flow/tasks/openfpga_shell/full_testbench/fast_memory_bank/config/task.conf

diff --git a/openfpga_flow/OpenFPGAShellScripts/configuration_frame_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga
similarity index 100%
rename from openfpga_flow/OpenFPGAShellScripts/configuration_frame_example_script.openfpga
rename to openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga
diff --git a/openfpga_flow/tasks/openfpga_shell/full_testbench/fast_configuration_frame/config/task.conf b/openfpga_flow/tasks/openfpga_shell/full_testbench/fast_configuration_frame/config/task.conf
index 7a448e3e8..55c98dda1 100644
--- a/openfpga_flow/tasks/openfpga_shell/full_testbench/fast_configuration_frame/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/full_testbench/fast_configuration_frame/config/task.conf
@@ -8,7 +8,7 @@
 
 [GENERAL]
 run_engine=openfpga_shell
-openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/configuration_frame_example_script.openfpga
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga
 power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
 power_analysis = true
 spice_output=false
diff --git a/openfpga_flow/tasks/openfpga_shell/full_testbench/fast_memory_bank/config/task.conf b/openfpga_flow/tasks/openfpga_shell/full_testbench/fast_memory_bank/config/task.conf
new file mode 100644
index 000000000..61b3d8b72
--- /dev/null
+++ b/openfpga_flow/tasks/openfpga_shell/full_testbench/fast_memory_bank/config/task.conf
@@ -0,0 +1,34 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+#vpr_fpga_verilog_formal_verification_top_netlist=

From 03e56f5ca6769f069c6cd670695e729f6a8a51e1 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 30 May 2020 20:58:02 -0600
Subject: [PATCH 617/645] deploy memory bank regression tests to CI

---
 .travis/script.sh | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/.travis/script.sh b/.travis/script.sh
index 846ec847f..11056cbed 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -57,6 +57,11 @@ python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/con
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/fast_configuration_frame --debug --show_thread_logs
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/preconfig_testbench/configuration_frame --debug --show_thread_logs
 
+echo -e "Testing memory bank configuration protocol of a K4N4 FPGA";
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/memory_bank --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/fast_memory_bank --debug --show_thread_logs
+
+
 echo -e "Testing standalone (flatten memory) configuration protocol of a K4N4 FPGA";
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/flatten_memory --debug --show_thread_logs
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/preconfig_testbench/flatten_memory --debug --show_thread_logs

From 3f9afea3e88fa8e96a3c78da3151ab7b9fc01f70 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 30 May 2020 20:59:14 -0600
Subject: [PATCH 618/645] add preconfig testbench test case for memory bank
 configuration protocol

---
 .../memory_bank/config/task.conf              | 34 +++++++++++++++++++
 1 file changed, 34 insertions(+)
 create mode 100644 openfpga_flow/tasks/openfpga_shell/preconfig_testbench/memory_bank/config/task.conf

diff --git a/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/memory_bank/config/task.conf b/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/memory_bank/config/task.conf
new file mode 100644
index 000000000..75579406c
--- /dev/null
+++ b/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/memory_bank/config/task.conf
@@ -0,0 +1,34 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

From e46651e0c10f55d62ab5904b35fa494db9447a4d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 30 May 2020 20:59:40 -0600
Subject: [PATCH 619/645] deploy preconfig regression test for memory bank to
 CI

---
 .travis/script.sh | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.travis/script.sh b/.travis/script.sh
index 11056cbed..907e1a3cf 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -60,6 +60,7 @@ python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/preconfig_testbenc
 echo -e "Testing memory bank configuration protocol of a K4N4 FPGA";
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/memory_bank --debug --show_thread_logs
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/fast_memory_bank --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/preconfig_testbench/memory_bank --debug --show_thread_logs
 
 
 echo -e "Testing standalone (flatten memory) configuration protocol of a K4N4 FPGA";

From b9dd47d465fe7fdd5ab54c9f3f71b00083ffc344 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 30 May 2020 21:01:38 -0600
Subject: [PATCH 620/645] update documentation about memory bank configuration
 protocol

---
 docs/source/manual/arch_lang/config_protocol.rst | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/docs/source/manual/arch_lang/config_protocol.rst b/docs/source/manual/arch_lang/config_protocol.rst
index 2fcdae535..48fd66ac3 100644
--- a/docs/source/manual/arch_lang/config_protocol.rst
+++ b/docs/source/manual/arch_lang/config_protocol.rst
@@ -100,6 +100,8 @@ When the decoder of sub block, e.g., the LUT, is enabled, each memory cells can
   -  a Bit-Line input to load the data
   -  a Word-Line input to enable data write 
 
+.. warning:: Please do NOT add inverted Bit-Line and Word-Line inputs. It is not supported yet!
+
 Memory bank Example
 ~~~~~~~~~~~~~~~~~~~
 The following XML code describes a memory-bank circuitry to configure the core logic of FPGA, as illustrated in :numref:`fig_sram`.
@@ -119,7 +121,13 @@ It will use the circuit model defined in :numref:`fig_sram_blwl`.
  
    Example of a memory organization using memory decoders 
 
-.. warning:: THIS IS STILL UNDER CONSTRUCTION
+.. note:: Memory-bank decoders does require a memory cell to have 
+
+  -  two outputs (one regular and another inverted)
+  -  a Bit-Line input to load the data
+  -  a Word-Line input to enable data write 
+
+.. warning:: Please do NOT add inverted Bit-Line and Word-Line inputs. It is not supported yet!
 
 Standalone SRAM Example
 ~~~~~~~~~~~~~~~~~~~~~~~
@@ -147,5 +155,7 @@ The following XML code shows an example where we use the circuit model defined i
   -  a Bit-Line input to load the data
   -  a Word-Line input to enable data write 
 
+.. warning:: Please do NOT add inverted Bit-Line and Word-Line inputs. It is not supported yet!
+
 .. warning:: This is a vanilla configuration method, which allow users to build their own configuration protocol on top of it. 
 

From dda6fe19ae975680f8e24bee814ef127ecfecb30 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 30 May 2020 22:28:12 -0600
Subject: [PATCH 621/645] show iverilog version in CI

---
 .travis/install.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.travis/install.sh b/.travis/install.sh
index 27d1cad5b..f8860b711 100755
--- a/.travis/install.sh
+++ b/.travis/install.sh
@@ -32,7 +32,7 @@ set -e
 #  export PATH=${DEPS_DIR}/iverilog-10_3/bin:${PATH}
 #  echo ${PATH}
 #fi
-#iverilog -V
+iverilog -V
 #cd -
 
 

From b191732d32ce52cdd2e8e7c852bad68d96ba6dd1 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 30 May 2020 22:29:40 -0600
Subject: [PATCH 622/645] show vvp version in CI

---
 .travis/install.sh | 1 +
 .travis/script.sh  | 4 ++--
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/.travis/install.sh b/.travis/install.sh
index f8860b711..46d535342 100755
--- a/.travis/install.sh
+++ b/.travis/install.sh
@@ -33,6 +33,7 @@ set -e
 #  echo ${PATH}
 #fi
 iverilog -V
+vvp -V
 #cd -
 
 
diff --git a/.travis/script.sh b/.travis/script.sh
index 907e1a3cf..c16c2eeac 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -58,8 +58,8 @@ python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/fas
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/preconfig_testbench/configuration_frame --debug --show_thread_logs
 
 echo -e "Testing memory bank configuration protocol of a K4N4 FPGA";
-python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/memory_bank --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/fast_memory_bank --debug --show_thread_logs
+#python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/memory_bank --debug --show_thread_logs
+#python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/fast_memory_bank --debug --show_thread_logs
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/preconfig_testbench/memory_bank --debug --show_thread_logs
 
 

From c85ccceac77cc761078d4e8c082a6a6e49d42a05 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 30 May 2020 23:41:33 -0600
Subject: [PATCH 623/645] try bug fixing in memory bank configuration protocol

---
 .../src/fpga_verilog/verilog_decoders.cpp     | 30 ++++++++++++++++---
 1 file changed, 26 insertions(+), 4 deletions(-)

diff --git a/openfpga/src/fpga_verilog/verilog_decoders.cpp b/openfpga/src/fpga_verilog/verilog_decoders.cpp
index 6e6025ea6..0ae2c70b3 100644
--- a/openfpga/src/fpga_verilog/verilog_decoders.cpp
+++ b/openfpga/src/fpga_verilog/verilog_decoders.cpp
@@ -483,16 +483,38 @@ void print_verilog_arch_decoder_with_data_in_module(std::fstream& fp,
   fp << ", " << generate_verilog_port(VERILOG_PORT_CONKT, din_port);
   fp << ") begin" << std::endl;
 
-  fp << "\t" << generate_verilog_port_constant_values(data_port, ito1hot_vec(data_size, data_size)) << ";" << std::endl; 
-
   fp << "\tif (" << generate_verilog_port(VERILOG_PORT_CONKT, enable_port) << " == 1'b1) begin" << std::endl;
-  fp << "\t\t" << data_port.get_name().c_str() << "[" << addr_port.get_name().c_str() << "]";
-  fp << " = " << generate_verilog_port(VERILOG_PORT_CONKT, din_port) << ";" << std::endl;
+  fp << "\t\t" << generate_verilog_port_constant_values(data_port, ito1hot_vec(data_size, data_size)); 
+  fp << ";" << std::endl;
+  fp << "\t\t" << "case (" << generate_verilog_port(VERILOG_PORT_CONKT, addr_port) << ")" << std::endl;
+  /* Create a string for addr and data */
+  for (size_t i = 0; i < data_size; ++i) {
+    BasicPort cur_data_port(data_port.get_name(), i, i);
+    fp << "\t\t\t" << generate_verilog_constant_values(itobin_vec(i, addr_size)); 
+    fp << " : ";
+    fp << generate_verilog_port(VERILOG_PORT_CONKT, cur_data_port); 
+    fp << " = ";
+    fp << generate_verilog_port(VERILOG_PORT_CONKT, din_port); 
+    fp << ";" << std::endl;
+  }
+  /* Different from MUX decoder, we assign default values which is all zero */
+  fp << "\t\t\t" << "default"; 
+  fp << " : ";
+  fp << generate_verilog_port_constant_values(data_port, ito1hot_vec(data_size, data_size)); 
+  fp << ";" << std::endl;
 
+  fp << "\t\t" << "endcase" << std::endl;
   fp << "\t" << "end" << std::endl;
 
+  /* If enable is not active, we should give all zero */
+  fp << "\t" << "else begin" << std::endl;
+  fp << "\t\t" << generate_verilog_port_constant_values(data_port, ito1hot_vec(data_size, data_size)); 
+  fp << ";" << std::endl;
+  fp << "\t" << "end" << std::endl;
+  
   fp << "end" << std::endl;
 
+
   if (true == decoder_lib.use_data_inv_port(decoder)) {
     print_verilog_wire_connection(fp, data_inv_port, data_port, true);
   }

From 5368485bd6e17cd2f961fa1088db8473819a4f8b Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 31 May 2020 12:44:38 -0600
Subject: [PATCH 624/645] keep bug fixing for memory bank configuration
 protocol. Reduce number of BL/WLs at the top-level

---
 openfpga/src/fabric/build_top_module.cpp      |  3 +-
 .../src/fabric/build_top_module_memory.cpp    | 25 ++++++++----
 openfpga/src/fabric/build_top_module_memory.h |  3 +-
 .../fpga_bitstream/build_fabric_bitstream.cpp | 39 +++++++++++++++----
 .../fpga_verilog/verilog_top_testbench.cpp    | 19 ---------
 openfpga/src/utils/decoder_library_utils.cpp  | 11 ++++--
 openfpga/src/utils/decoder_library_utils.h    |  2 +-
 7 files changed, 61 insertions(+), 41 deletions(-)

diff --git a/openfpga/src/fabric/build_top_module.cpp b/openfpga/src/fabric/build_top_module.cpp
index 7b05a5676..762ba66f0 100644
--- a/openfpga/src/fabric/build_top_module.cpp
+++ b/openfpga/src/fabric/build_top_module.cpp
@@ -395,7 +395,8 @@ void build_top_module(ModuleManager& module_manager,
   if (0 < module_manager.configurable_children(top_module).size()) {
     add_top_module_nets_memory_config_bus(module_manager, decoder_lib,
                                           top_module, 
-                                          sram_orgz_type, circuit_lib.design_tech_type(sram_model));
+                                          sram_orgz_type, circuit_lib.design_tech_type(sram_model),
+                                          module_num_config_bits);
   }
 }
 
diff --git a/openfpga/src/fabric/build_top_module_memory.cpp b/openfpga/src/fabric/build_top_module_memory.cpp
index 0de55ca4e..568646d57 100644
--- a/openfpga/src/fabric/build_top_module_memory.cpp
+++ b/openfpga/src/fabric/build_top_module_memory.cpp
@@ -510,7 +510,8 @@ void add_top_module_sram_ports(ModuleManager& module_manager,
 static 
 void add_top_module_nets_cmos_memory_bank_config_bus(ModuleManager& module_manager,
                                                      DecoderLibrary& decoder_lib,
-                                                     const ModuleId& top_module) {
+                                                     const ModuleId& top_module,
+                                                     const size_t& num_config_bits) {
   /* Find Enable port from the top-level module */ 
   ModulePortId en_port = module_manager.find_module_port(top_module, std::string(DECODER_ENABLE_PORT_NAME));
   BasicPort en_port_info = module_manager.module_port(top_module, en_port);
@@ -529,8 +530,8 @@ void add_top_module_nets_cmos_memory_bank_config_bus(ModuleManager& module_manag
   /* Find the number of BLs and WLs required to access each memory bit */
   size_t bl_addr_size = bl_addr_port_info.get_width();
   size_t wl_addr_size = wl_addr_port_info.get_width();
-  size_t num_bls = find_memory_decoder_data_size(bl_addr_size);
-  size_t num_wls = find_memory_decoder_data_size(wl_addr_size);
+  size_t num_bls = find_memory_decoder_data_size(num_config_bits);
+  size_t num_wls = find_memory_decoder_data_size(num_config_bits);
   
   /* Add the BL decoder module 
    * Search the decoder library
@@ -704,6 +705,12 @@ void add_top_module_nets_cmos_memory_bank_config_bus(ModuleManager& module_manag
       cur_wl_index++;
     }
   }
+
+  /* Add the BL and WL decoders to the end of configurable children list
+   * Note: this MUST be done after adding all the module nets to other regular configurable children
+   */
+  module_manager.add_configurable_child(top_module, bl_decoder_module, 0);
+  module_manager.add_configurable_child(top_module, wl_decoder_module, 0);
 }
 
 /*********************************************************************
@@ -754,7 +761,8 @@ static
 void add_top_module_nets_cmos_memory_config_bus(ModuleManager& module_manager,
                                                 DecoderLibrary& decoder_lib,
                                                 const ModuleId& parent_module,
-                                                const e_config_protocol_type& sram_orgz_type) {
+                                                const e_config_protocol_type& sram_orgz_type,
+                                                const size_t& num_config_bits) {
   switch (sram_orgz_type) {
   case CONFIG_MEM_STANDALONE:
     add_module_nets_cmos_flatten_memory_config_bus(module_manager, parent_module,
@@ -767,8 +775,7 @@ void add_top_module_nets_cmos_memory_config_bus(ModuleManager& module_manager,
     break;
   }
   case CONFIG_MEM_MEMORY_BANK:
-    /* TODO */
-    add_top_module_nets_cmos_memory_bank_config_bus(module_manager, decoder_lib, parent_module);
+    add_top_module_nets_cmos_memory_bank_config_bus(module_manager, decoder_lib, parent_module, num_config_bits);
     break;
   case CONFIG_MEM_FRAME_BASED:
     add_module_nets_cmos_memory_frame_config_bus(module_manager, decoder_lib, parent_module);
@@ -816,12 +823,14 @@ void add_top_module_nets_memory_config_bus(ModuleManager& module_manager,
                                            DecoderLibrary& decoder_lib,
                                            const ModuleId& parent_module,
                                            const e_config_protocol_type& sram_orgz_type, 
-                                           const e_circuit_model_design_tech& mem_tech) {
+                                           const e_circuit_model_design_tech& mem_tech,
+                                           const size_t& num_config_bits) {
   switch (mem_tech) {
   case CIRCUIT_MODEL_DESIGN_CMOS:
     add_top_module_nets_cmos_memory_config_bus(module_manager, decoder_lib,
                                                parent_module, 
-                                               sram_orgz_type);
+                                               sram_orgz_type,
+                                               num_config_bits);
     break;
   case CIRCUIT_MODEL_DESIGN_RRAM:
     /* TODO: */
diff --git a/openfpga/src/fabric/build_top_module_memory.h b/openfpga/src/fabric/build_top_module_memory.h
index a912845b2..b67389790 100644
--- a/openfpga/src/fabric/build_top_module_memory.h
+++ b/openfpga/src/fabric/build_top_module_memory.h
@@ -45,7 +45,8 @@ void add_top_module_nets_memory_config_bus(ModuleManager& module_manager,
                                            DecoderLibrary& decoder_lib,
                                            const ModuleId& parent_module,
                                            const e_config_protocol_type& sram_orgz_type, 
-                                           const e_circuit_model_design_tech& mem_tech);
+                                           const e_circuit_model_design_tech& mem_tech,
+                                           const size_t& num_config_bits);
 
 } /* end namespace openfpga */
 
diff --git a/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp b/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp
index a9c5b6ec7..a69594f48 100644
--- a/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp
+++ b/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp
@@ -93,6 +93,7 @@ static
 void rec_build_module_fabric_dependent_memory_bank_bitstream(const BitstreamManager& bitstream_manager,
                                                              const ConfigBlockId& parent_block,
                                                              const ModuleManager& module_manager,
+                                                             const ModuleId& top_module,
                                                              const ModuleId& parent_module,
                                                              const size_t& bl_addr_size,
                                                              const size_t& wl_addr_size,
@@ -105,8 +106,17 @@ void rec_build_module_fabric_dependent_memory_bank_bitstream(const BitstreamMana
    * we dive to the next level first! 
    */
   if (0 < bitstream_manager.block_children(parent_block).size()) {
-    for (size_t child_id = 0; child_id < module_manager.configurable_children(parent_module).size(); ++child_id) {
-      ModuleId child_module = module_manager.configurable_children(parent_module)[child_id]; 
+    /* For top module, we will skip the two decoders at the end of the configurable children list */
+    std::vector<ModuleId> configurable_children = module_manager.configurable_children(parent_module);
+
+    size_t num_configurable_children = configurable_children.size();
+    if (parent_module == top_module) {
+      VTR_ASSERT(2 <= configurable_children.size()); 
+      num_configurable_children -= 2;
+    }
+
+    for (size_t child_id = 0; child_id < num_configurable_children; ++child_id) {
+      ModuleId child_module = configurable_children[child_id]; 
       size_t child_instance = module_manager.configurable_child_instances(parent_module)[child_id]; 
       /* Get the instance name and ensure it is not empty */
       std::string instance_name = module_manager.instance_name(parent_module, child_module, child_instance);
@@ -114,12 +124,12 @@ void rec_build_module_fabric_dependent_memory_bank_bitstream(const BitstreamMana
       /* Find the child block that matches the instance name! */ 
       ConfigBlockId child_block = bitstream_manager.find_child_block(parent_block, instance_name); 
       /* We must have one valid block id! */
-      if (true != bitstream_manager.valid_block_id(child_block))
+      if (true != bitstream_manager.valid_block_id(child_block)) 
       VTR_ASSERT(true == bitstream_manager.valid_block_id(child_block));
 
       /* Go recursively */
       rec_build_module_fabric_dependent_memory_bank_bitstream(bitstream_manager, child_block,
-                                                              module_manager, child_module,
+                                                              module_manager, top_module, child_module,
                                                               bl_addr_size, wl_addr_size,
                                                               num_bls, num_wls,
                                                               cur_mem_index,
@@ -376,18 +386,31 @@ void build_module_fabric_dependent_bitstream(const ConfigProtocol& config_protoc
     /* Find BL address port size */
     ModulePortId bl_addr_port = module_manager.find_module_port(top_module, std::string(DECODER_BL_ADDRESS_PORT_NAME));
     BasicPort bl_addr_port_info = module_manager.module_port(top_module, bl_addr_port);
-    size_t num_bls = find_memory_decoder_data_size(bl_addr_port_info.get_width()); 
 
     /* Find WL address port size */
     ModulePortId wl_addr_port = module_manager.find_module_port(top_module, std::string(DECODER_WL_ADDRESS_PORT_NAME));
     BasicPort wl_addr_port_info = module_manager.module_port(top_module, wl_addr_port);
-    size_t num_wls = find_memory_decoder_data_size(wl_addr_port_info.get_width()); 
+
+    /* Find BL and WL decoders which are the last two configurable children*/
+    std::vector<ModuleId> configurable_children = module_manager.configurable_children(top_module);
+    VTR_ASSERT(2 <= configurable_children.size()); 
+    ModuleId bl_decoder_module = configurable_children[configurable_children.size() - 2];
+    VTR_ASSERT(0 == module_manager.configurable_child_instances(top_module)[configurable_children.size() - 2]);
+    ModuleId wl_decoder_module = configurable_children[configurable_children.size() - 1];
+    VTR_ASSERT(0 == module_manager.configurable_child_instances(top_module)[configurable_children.size() - 1]);
+
+    ModulePortId bl_port = module_manager.find_module_port(bl_decoder_module, std::string(DECODER_DATA_OUT_PORT_NAME));
+    BasicPort bl_port_info = module_manager.module_port(bl_decoder_module, bl_port);
+
+    ModulePortId wl_port = module_manager.find_module_port(wl_decoder_module, std::string(DECODER_DATA_OUT_PORT_NAME));
+    BasicPort wl_port_info = module_manager.module_port(wl_decoder_module, wl_port);
 
     rec_build_module_fabric_dependent_memory_bank_bitstream(bitstream_manager, top_block,
-                                                            module_manager, top_module, 
+                                                            module_manager, top_module, top_module, 
                                                             bl_addr_port_info.get_width(),
                                                             wl_addr_port_info.get_width(),
-                                                            num_bls, num_wls,
+                                                            bl_port_info.get_width(),
+                                                            wl_port_info.get_width(),
                                                             cur_mem_index, fabric_bitstream);
     break;
   }
diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
index 670074d74..5c05d666f 100644
--- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
@@ -1245,25 +1245,6 @@ void print_verilog_top_testbench_memory_bank_bitstream(std::fstream& fp,
     fp << ");" << std::endl;
   }
 
-  /* Disable the address and din */
-  fp << "\t\t" << std::string(TOP_TESTBENCH_PROG_TASK_NAME);
-  fp << "(" << bl_addr_port.get_width() << "'b";
-  std::vector<size_t> all_zero_bl_addr(bl_addr_port.get_width(), 0);
-  for (const size_t& addr_bit : all_zero_bl_addr) {
-    fp << addr_bit; 
-  }
-
-  fp << ", ";
-  fp << wl_addr_port.get_width() << "'b";
-  std::vector<size_t> all_zero_wl_addr(wl_addr_port.get_width(), 0);
-  for (const size_t& addr_bit : all_zero_wl_addr) {
-    fp << addr_bit; 
-  }
-
-  fp << ", ";
-  fp <<"1'b0";
-  fp << ");" << std::endl;
-
   /* Raise the flag of configuration done when bitstream loading is complete */
   BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME), 1);
   fp << "\t\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ");" << std::endl;
diff --git a/openfpga/src/utils/decoder_library_utils.cpp b/openfpga/src/utils/decoder_library_utils.cpp
index 8fd7e2208..f4db14ba7 100644
--- a/openfpga/src/utils/decoder_library_utils.cpp
+++ b/openfpga/src/utils/decoder_library_utils.cpp
@@ -74,11 +74,16 @@ size_t find_mux_local_decoder_addr_size(const size_t& data_size) {
  *               
  ***************************************************************************************/
 size_t find_memory_decoder_addr_size(const size_t& num_mems) {
-  return find_mux_local_decoder_addr_size((size_t)std::ceil(std::sqrt((float)num_mems)));
+  return find_mux_local_decoder_addr_size(find_memory_decoder_data_size(num_mems));
 }
 
-size_t find_memory_decoder_data_size(const size_t& num_addr) {
-  return (size_t)std::pow(2., num_addr);
+/***************************************************************************************
+ * Find the size of data lines (BLs and WLs) for a memory decoder to access a memory array
+ * As the memory cells are organized in an array with shared bit lines and word lines,
+ * the number of data lines will be a square root of the number of memory cells.
+ ***************************************************************************************/
+size_t find_memory_decoder_data_size(const size_t& num_mems) {
+  return (size_t)std::ceil(std::sqrt((float)num_mems));
 }
 
 /***************************************************************************************
diff --git a/openfpga/src/utils/decoder_library_utils.h b/openfpga/src/utils/decoder_library_utils.h
index f7f06f733..aa25d0df2 100644
--- a/openfpga/src/utils/decoder_library_utils.h
+++ b/openfpga/src/utils/decoder_library_utils.h
@@ -15,7 +15,7 @@ size_t find_mux_local_decoder_addr_size(const size_t& data_size);
 
 size_t find_memory_decoder_addr_size(const size_t& num_mems);
 
-size_t find_memory_decoder_data_size(const size_t& num_addr);
+size_t find_memory_decoder_data_size(const size_t& num_mems);
 
 DecoderId add_mux_local_decoder_to_library(DecoderLibrary& decoder_lib, 
                                            const size_t data_size);

From 82b04ae3f06e76e1e33e76b0a40e6a1260ba86c4 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 31 May 2020 13:03:54 -0600
Subject: [PATCH 625/645] add SRAM verilog for memory bank usage

---
 openfpga_flow/VerilogNetlists/sram.v | 49 ++++++++++++++++++++++++++++
 1 file changed, 49 insertions(+)

diff --git a/openfpga_flow/VerilogNetlists/sram.v b/openfpga_flow/VerilogNetlists/sram.v
index 536c1012a..8b2c6c2d6 100644
--- a/openfpga_flow/VerilogNetlists/sram.v
+++ b/openfpga_flow/VerilogNetlists/sram.v
@@ -1,3 +1,52 @@
+//-----------------------------------------------------
+// Design Name : sram_blwl
+// File Name   : sram.v
+// Function    : A SRAM cell is is accessible
+//               when wl is enabled
+// Coder       : Xifan TANG
+//-----------------------------------------------------
+module sram_blwl(
+input wl, // Word line control signal
+input bl, // Bit line control signal
+output out, // Data output
+output outb, // Data output
+);
+
+  //----- local variable need to be registered
+  reg data;
+
+  //----- when wl is enabled, we can read in data from bl
+  always @(bl, wl) 
+  begin
+    //----- Cases to program internal memory bit 
+    //----- case 1: bl = 1, wl = 1, a -> 0
+    if ((1'b1 == bl)&&(1'b1 == wl)) begin
+      data <= 1'b1;
+    end 
+    //----- case 2: bl = 0, wl = 1, a -> 0
+    if ((1'b0 == bl)&&(1'b1 == wl)) begin
+     data <= 1'b0;
+    end 
+  end
+
+`ifdef ENABLE_SIGNAL_INITIALIZATION
+   initial begin
+     $deposit(data, $random);
+   end
+`endif
+
+`ifndef ENABLE_FORMAL_VERIFICATION
+    // Wire q_reg to Q
+    assign out = data;
+    assign outb = ~data;
+`else
+    assign out = 1'bZ;
+    assign outb = !out;
+`endif
+
+endmodule
+
+
 //------ Module: sram6T_blwl -----//
 //------ Verilog file: sram.v -----//
 //------ Author: Xifan TANG -----//

From aac2e8c805d4b7a6636d24c093b40691184fcd72 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 31 May 2020 13:08:13 -0600
Subject: [PATCH 626/645] update openfpga architecture for memory bank usage

---
 .../openfpga_arch/k4_N4_40nm_bank_openfpga.xml       | 12 +++++-------
 1 file changed, 5 insertions(+), 7 deletions(-)

diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml
index 7de3ec8c4..487cd91e0 100644
--- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml
@@ -142,29 +142,27 @@
       <port type="sram" prefix="sram" size="16"/>
     </circuit_model>
     <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
-    <circuit_model type="sram" name="config_latch" prefix="config_latch" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/config_latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/config_latch.v">
+    <circuit_model type="sram" name="sram_blwl" prefix="sram_blwl" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/sram.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
        <port type="bl" prefix="bl" size="1"/>
        <port type="wl" prefix="wl" size="1"/>
-       <port type="output" prefix="Q" size="1"/>
-       <port type="output" prefix="Qb" size="1"/>
-       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+       <port type="output" prefix="out" size="1"/>
+       <port type="output" prefix="outb" size="1"/>
     </circuit_model>
     <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
       <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
-      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="config_latch" default_val="1"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sram_blwl" default_val="1"/>
       <port type="input" prefix="outpad" size="1"/>
       <port type="output" prefix="inpad" size="1"/>
     </circuit_model>
   </circuit_library>
   <configuration_protocol>
-    <organization type="memory_bank" circuit_model_name="config_latch"/>
+    <organization type="memory_bank" circuit_model_name="sram_blwl"/>
   </configuration_protocol>
   <connection_block>
     <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>

From 8267dad8ef567e7d876cd9ce9de4664ac7a452a7 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 31 May 2020 13:12:00 -0600
Subject: [PATCH 627/645] add decoder support for Z signals

---
 libopenfpga/libarchopenfpga/src/check_circuit_library.cpp | 1 -
 openfpga/src/fpga_verilog/verilog_decoders.cpp            | 5 ++++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp b/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp
index fe364bf0f..b38fbf1b6 100644
--- a/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp
+++ b/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp
@@ -508,7 +508,6 @@ bool check_circuit_library(const CircuitLibrary& circuit_lib) {
 
   /* 6. SRAM must have at least an input and an output ports*/
   std::vector<enum e_circuit_model_port_type> sram_port_types_required;
-  sram_port_types_required.push_back(CIRCUIT_MODEL_PORT_INPUT);
   sram_port_types_required.push_back(CIRCUIT_MODEL_PORT_OUTPUT);
 
   num_err += check_circuit_model_port_required(circuit_lib, CIRCUIT_MODEL_SRAM, sram_port_types_required);
diff --git a/openfpga/src/fpga_verilog/verilog_decoders.cpp b/openfpga/src/fpga_verilog/verilog_decoders.cpp
index 0ae2c70b3..327cb51b7 100644
--- a/openfpga/src/fpga_verilog/verilog_decoders.cpp
+++ b/openfpga/src/fpga_verilog/verilog_decoders.cpp
@@ -484,7 +484,10 @@ void print_verilog_arch_decoder_with_data_in_module(std::fstream& fp,
   fp << ") begin" << std::endl;
 
   fp << "\tif (" << generate_verilog_port(VERILOG_PORT_CONKT, enable_port) << " == 1'b1) begin" << std::endl;
-  fp << "\t\t" << generate_verilog_port_constant_values(data_port, ito1hot_vec(data_size, data_size)); 
+  fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, data_port); 
+  fp << " = ";
+  std::string high_res_str = "{" + std::to_string(data_port.get_width()) + "{1'bz}}";
+  fp << high_res_str;
   fp << ";" << std::endl;
   fp << "\t\t" << "case (" << generate_verilog_port(VERILOG_PORT_CONKT, addr_port) << ")" << std::endl;
   /* Create a string for addr and data */

From baa2c6b7ef16a7ad054a74a19740a011fe2f570c Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 31 May 2020 13:26:55 -0600
Subject: [PATCH 628/645] update arch to support reset signal for SRAm

---
 openfpga_flow/VerilogNetlists/sram.v             | 16 ++++++----------
 .../openfpga_arch/k4_N4_40nm_bank_openfpga.xml   |  1 +
 2 files changed, 7 insertions(+), 10 deletions(-)

diff --git a/openfpga_flow/VerilogNetlists/sram.v b/openfpga_flow/VerilogNetlists/sram.v
index 8b2c6c2d6..c27dbeebe 100644
--- a/openfpga_flow/VerilogNetlists/sram.v
+++ b/openfpga_flow/VerilogNetlists/sram.v
@@ -6,10 +6,11 @@
 // Coder       : Xifan TANG
 //-----------------------------------------------------
 module sram_blwl(
+input reset, // Word line control signal
 input wl, // Word line control signal
 input bl, // Bit line control signal
 output out, // Data output
-output outb, // Data output
+output outb // Data output
 );
 
   //----- local variable need to be registered
@@ -18,23 +19,18 @@ output outb, // Data output
   //----- when wl is enabled, we can read in data from bl
   always @(bl, wl) 
   begin
+    if (1'b1 == reset) begin 
+      data <= 1'b0;
+    end else if ((1'b1 == bl)&&(1'b1 == wl)) begin
     //----- Cases to program internal memory bit 
     //----- case 1: bl = 1, wl = 1, a -> 0
-    if ((1'b1 == bl)&&(1'b1 == wl)) begin
       data <= 1'b1;
-    end 
+    end else if ((1'b0 == bl)&&(1'b1 == wl)) begin
     //----- case 2: bl = 0, wl = 1, a -> 0
-    if ((1'b0 == bl)&&(1'b1 == wl)) begin
      data <= 1'b0;
     end 
   end
 
-`ifdef ENABLE_SIGNAL_INITIALIZATION
-   initial begin
-     $deposit(data, $random);
-   end
-`endif
-
 `ifndef ENABLE_FORMAL_VERIFICATION
     // Wire q_reg to Q
     assign out = data;
diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml
index 487cd91e0..fe7d3f1b8 100644
--- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml
@@ -146,6 +146,7 @@
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
        <port type="bl" prefix="bl" size="1"/>
        <port type="wl" prefix="wl" size="1"/>
        <port type="output" prefix="out" size="1"/>

From 3c10af7f2bdc0380bbd5d33dbabfba49a5040f1b Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 31 May 2020 16:12:42 -0600
Subject: [PATCH 629/645] bug fixed in memory bank configuration protocol which
 is due to the wrong Verilog port merging algorithm

---
 .../src/fabric/build_top_module_memory.cpp    |  4 +-
 .../fpga_bitstream/build_fabric_bitstream.cpp | 12 +++++-
 .../src/fpga_verilog/verilog_decoders.cpp     |  8 +++-
 .../src/fpga_verilog/verilog_writer_utils.cpp | 40 +++++++++----------
 4 files changed, 38 insertions(+), 26 deletions(-)

diff --git a/openfpga/src/fabric/build_top_module_memory.cpp b/openfpga/src/fabric/build_top_module_memory.cpp
index 568646d57..6466d98e5 100644
--- a/openfpga/src/fabric/build_top_module_memory.cpp
+++ b/openfpga/src/fabric/build_top_module_memory.cpp
@@ -2,6 +2,8 @@
  * This file includes functions that are used to organize memories 
  * in the top module of FPGA fabric
  *******************************************************************/
+#include <cmath>
+
 /* Headers from vtrutil library */
 #include "vtr_assert.h"
 #include "vtr_log.h"
@@ -652,7 +654,7 @@ void add_top_module_nets_cmos_memory_bank_config_bus(ModuleManager& module_manag
       /* Find the BL decoder data index: 
        * It should be the residual when divided by the number of BLs
        */
-      size_t bl_pin_id = cur_bl_index / num_bls;
+      size_t bl_pin_id = std::floor(cur_bl_index / num_bls);
 
       /* Create net */
       ModuleNetId net = create_module_source_pin_net(module_manager, top_module,
diff --git a/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp b/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp
index a69594f48..240f19028 100644
--- a/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp
+++ b/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp
@@ -2,6 +2,7 @@
  * This file includes functions to build fabric dependent bitstream
  *******************************************************************/
 #include <string>
+#include <cmath>
 #include <algorithm>
 
 /* Headers from vtrutil library */
@@ -115,6 +116,13 @@ void rec_build_module_fabric_dependent_memory_bank_bitstream(const BitstreamMana
       num_configurable_children -= 2;
     }
 
+    /* Early exit if there is no configurable children */
+    if (0 == num_configurable_children) {
+      /* Ensure that there should be no configuration bits in the parent block */
+      VTR_ASSERT(0 == bitstream_manager.block_bits(parent_block).size());
+      return;
+    }
+
     for (size_t child_id = 0; child_id < num_configurable_children; ++child_id) {
       ModuleId child_module = configurable_children[child_id]; 
       size_t child_instance = module_manager.configurable_child_instances(parent_module)[child_id]; 
@@ -137,6 +145,8 @@ void rec_build_module_fabric_dependent_memory_bank_bitstream(const BitstreamMana
     }
     /* Ensure that there should be no configuration bits in the parent block */
     VTR_ASSERT(0 == bitstream_manager.block_bits(parent_block).size());
+
+    return;
   }
 
   /* Note that, reach here, it means that this is a leaf node. 
@@ -147,7 +157,7 @@ void rec_build_module_fabric_dependent_memory_bank_bitstream(const BitstreamMana
     FabricBitId fabric_bit = fabric_bitstream.add_bit(config_bit);
   
     /* Find BL address */
-    size_t cur_bl_index = cur_mem_index / num_bls;
+    size_t cur_bl_index = std::floor(cur_mem_index / num_bls);
     std::vector<size_t> bl_addr_bits_vec = itobin_vec(cur_bl_index, bl_addr_size);
 
     /* Find WL address */
diff --git a/openfpga/src/fpga_verilog/verilog_decoders.cpp b/openfpga/src/fpga_verilog/verilog_decoders.cpp
index 327cb51b7..b0259f247 100644
--- a/openfpga/src/fpga_verilog/verilog_decoders.cpp
+++ b/openfpga/src/fpga_verilog/verilog_decoders.cpp
@@ -503,7 +503,9 @@ void print_verilog_arch_decoder_with_data_in_module(std::fstream& fp,
   /* Different from MUX decoder, we assign default values which is all zero */
   fp << "\t\t\t" << "default"; 
   fp << " : ";
-  fp << generate_verilog_port_constant_values(data_port, ito1hot_vec(data_size, data_size)); 
+  fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, data_port); 
+  fp << " = ";
+  fp << high_res_str;
   fp << ";" << std::endl;
 
   fp << "\t\t" << "endcase" << std::endl;
@@ -511,7 +513,9 @@ void print_verilog_arch_decoder_with_data_in_module(std::fstream& fp,
 
   /* If enable is not active, we should give all zero */
   fp << "\t" << "else begin" << std::endl;
-  fp << "\t\t" << generate_verilog_port_constant_values(data_port, ito1hot_vec(data_size, data_size)); 
+  fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, data_port); 
+  fp << " = ";
+  fp << high_res_str;
   fp << ";" << std::endl;
   fp << "\t" << "end" << std::endl;
   
diff --git a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp
index c59d92dd0..900c3da37 100644
--- a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp
+++ b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp
@@ -517,31 +517,27 @@ std::vector<BasicPort> combine_verilog_ports(const std::vector<BasicPort>& ports
     if (&port == &ports[0]) {
       continue;
     } 
-    /* Identify if the port name can be potentially merged: if the port name is already in the merged port list, it may be merged */
-    bool merged = false;
-    for (auto& merged_port : merged_ports) {
-      if (false == port.mergeable(merged_port)) {
-        /* Unable to merge, Go to next */
-        continue;
-      }
-      /* May be merged, check LSB of port and MSB of merged_port */
-      if (merged_port.get_msb() + 1 != port.get_lsb()) {
-        /* Unable to merge, Go to next */
-        continue;
-      } 
-      /* Reach here, we should merge the ports,
-       * LSB of merged_port remains the same,
-       * MSB of merged_port will be updated 
-       * to the MSB of port 
-       */
-      merged_port.set_msb(port.get_msb());
-      merged = true;
-      break;
-    }
-    if (false == merged) {
+    /* Identify if the port name can be potentially merged: 
+     * if the port can be merged to the last port in the list, it may be merged
+     */
+    if (false == port.mergeable(merged_ports.back())) {
       /* Unable to merge, add the port to merged port list */
       merged_ports.push_back(port);
+      continue;
     }
+    /* May be merged, check LSB of port and MSB of merged_port */
+    if (merged_ports.back().get_msb() + 1 != port.get_lsb()) {
+      /* Unable to merge, add the port to merged port list */
+      merged_ports.push_back(port);
+      continue;
+    } 
+    /* Reach here, we should merge the ports,
+     * LSB of merged_port remains the same,
+     * MSB of merged_port will be updated 
+     * to the MSB of port 
+     */
+    BasicPort& port_to_merge = merged_ports.back();
+    port_to_merge.set_msb(port.get_msb());
   }
 
   return merged_ports;

From 0b9971cb5c7a03380dd8e65e726129cd57b35472 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 31 May 2020 16:14:38 -0600
Subject: [PATCH 630/645] try to deploy the memory bank protocol test case to
 CI

---
 .travis/script.sh | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/.travis/script.sh b/.travis/script.sh
index c16c2eeac..907e1a3cf 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -58,8 +58,8 @@ python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/fas
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/preconfig_testbench/configuration_frame --debug --show_thread_logs
 
 echo -e "Testing memory bank configuration protocol of a K4N4 FPGA";
-#python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/memory_bank --debug --show_thread_logs
-#python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/fast_memory_bank --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/memory_bank --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/fast_memory_bank --debug --show_thread_logs
 python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/preconfig_testbench/memory_bank --debug --show_thread_logs
 
 

From f73dfa2bccd895d0da3d522e9e0fa09451739e82 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 31 May 2020 18:58:44 -0600
Subject: [PATCH 631/645] bug fixed in k6_n10_40 architecture

---
 openfpga_flow/arch/vpr_only_templates/k6_N10_40nm.xml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/openfpga_flow/arch/vpr_only_templates/k6_N10_40nm.xml b/openfpga_flow/arch/vpr_only_templates/k6_N10_40nm.xml
index e94f339c1..4ab67628f 100644
--- a/openfpga_flow/arch/vpr_only_templates/k6_N10_40nm.xml
+++ b/openfpga_flow/arch/vpr_only_templates/k6_N10_40nm.xml
@@ -54,7 +54,7 @@
         <site pb_type="clb"/>
       </equivalent_sites>
       <input name="I" num_pins="40" equivalent="full"/>
-      <output name="O" num_pins="10" equivalent="instance"/>
+      <output name="O" num_pins="10" equivalent="none"/>
       <clock name="clk" num_pins="1"/>
       <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
       <pinlocations pattern="spread"/>
@@ -197,7 +197,7 @@
 	   -->
     <pb_type name="clb">
       <input name="I" num_pins="40" equivalent="full"/>
-      <output name="O" num_pins="10" equivalent="instance"/>
+      <output name="O" num_pins="10" equivalent="none"/>
       <clock name="clk" num_pins="1"/>
       <!-- Describe basic logic element.  
              Each basic logic element has a 6-LUT that can be optionally registered

From c87dbc4880777c8be1563acc4750636806b42d8d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 31 May 2020 19:52:18 -0600
Subject: [PATCH 632/645] start using counter benchmark in regression tests

---
 .../counter/counter_output_verilog.v          | 84 +++++++++++++++++++
 .../counter/counter_post_yosys.blif           | 69 +++++++++++++++
 .../counter/counter_pre_vpr.act               | 20 +++++
 .../implicit_verilog/config/task.conf         |  8 +-
 4 files changed, 177 insertions(+), 4 deletions(-)
 create mode 100644 openfpga_flow/benchmarks/micro_benchmark/counter/counter_output_verilog.v
 create mode 100644 openfpga_flow/benchmarks/micro_benchmark/counter/counter_post_yosys.blif
 create mode 100644 openfpga_flow/benchmarks/micro_benchmark/counter/counter_pre_vpr.act

diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter/counter_output_verilog.v b/openfpga_flow/benchmarks/micro_benchmark/counter/counter_output_verilog.v
new file mode 100644
index 000000000..17896cc04
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/counter/counter_output_verilog.v
@@ -0,0 +1,84 @@
+/* Generated by Yosys 0.9 (git sha1 f110c953, gcc 8.4.0-1ubuntu1~18.04 -fPIC -Os) */
+
+module counter(clk_counter, rst_counter, \q_counter[0] , \q_counter[1] , \q_counter[2] , \q_counter[3] , \q_counter[4] , \q_counter[5] , \q_counter[6] , \q_counter[7] );
+  wire _00_;
+  wire _01_;
+  input clk_counter;
+  wire n22;
+  wire n26;
+  wire n30;
+  wire n34;
+  wire n38;
+  wire n42;
+  wire n46;
+  wire n50;
+  output \q_counter[0] ;
+  reg \q_counter[0] ;
+  output \q_counter[1] ;
+  reg \q_counter[1] ;
+  output \q_counter[2] ;
+  reg \q_counter[2] ;
+  output \q_counter[3] ;
+  reg \q_counter[3] ;
+  output \q_counter[4] ;
+  reg \q_counter[4] ;
+  output \q_counter[5] ;
+  reg \q_counter[5] ;
+  output \q_counter[6] ;
+  reg \q_counter[6] ;
+  output \q_counter[7] ;
+  reg \q_counter[7] ;
+  input rst_counter;
+  
+  always @(posedge clk_counter)
+  begin
+	if(rst_counter) \q_counter[0] <= 1'b0;
+    else \q_counter[0]  <= n22;
+  end
+  always @(posedge clk_counter)
+  begin
+	if(rst_counter) \q_counter[1] <= 1'b0;
+    else \q_counter[1]  <= n26;
+  end
+  always @(posedge clk_counter)
+  begin
+	if(rst_counter) \q_counter[2] <= 1'b0;
+    else \q_counter[2]  <= n30;
+  end
+  always @(posedge clk_counter)
+  begin
+	if(rst_counter) \q_counter[3] <= 1'b0;
+    else \q_counter[3]  <= n34;
+  end
+  always @(posedge clk_counter)
+  begin
+	if(rst_counter) \q_counter[4] <= 1'b0;
+    else \q_counter[4]  <= n38;
+  end
+  always @(posedge clk_counter)
+  begin
+	if(rst_counter) \q_counter[5] <= 1'b0;
+    else \q_counter[5]  <= n42;
+  end
+  always @(posedge clk_counter)
+  begin
+	if(rst_counter) \q_counter[6] <= 1'b0;
+    else \q_counter[6]  <= n46;
+  end
+  always @(posedge clk_counter)
+  begin
+	if(rst_counter) \q_counter[7] <= 1'b0;
+    else \q_counter[7]  <= n50;
+  end
+  
+  assign n26 = 8'h14 >> { \q_counter[0] , \q_counter[1] , rst_counter };
+  assign n30 = 16'h0708 >> { \q_counter[2] , rst_counter, \q_counter[0] , \q_counter[1]  };
+  assign n34 = 32'd8323200 >> { \q_counter[3] , rst_counter, \q_counter[0] , \q_counter[1] , \q_counter[2]  };
+  assign n38 = 64'h00007fff00008000 >> { \q_counter[4] , rst_counter, \q_counter[0] , \q_counter[1] , \q_counter[2] , \q_counter[3]  };
+  assign n42 = 8'h14 >> { _00_, \q_counter[5] , rst_counter };
+  assign _00_ = 32'd2147483648 >> { \q_counter[0] , \q_counter[1] , \q_counter[2] , \q_counter[3] , \q_counter[4]  };
+  assign n46 = 8'h14 >> { _01_, \q_counter[6] , rst_counter };
+  assign _01_ = 64'h8000000000000000 >> { \q_counter[0] , \q_counter[1] , \q_counter[2] , \q_counter[3] , \q_counter[4] , \q_counter[5]  };
+  assign n50 = 16'h0708 >> { \q_counter[7] , rst_counter, _01_, \q_counter[6]  };
+  assign n22 = 4'h1 >> { \q_counter[0] , rst_counter };
+endmodule
diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter/counter_post_yosys.blif b/openfpga_flow/benchmarks/micro_benchmark/counter/counter_post_yosys.blif
new file mode 100644
index 000000000..ebf780381
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/counter/counter_post_yosys.blif
@@ -0,0 +1,69 @@
+# Generated by Yosys 0.9 (git sha1 UNKNOWN, clang 7.0.0 -fPIC -Os)
+
+.model counter
+.inputs clk_counter rst_counter
+.outputs q_counter[0] q_counter[1] q_counter[2] q_counter[3] q_counter[4] q_counter[5] q_counter[6] q_counter[7]
+.names $false
+.names $true
+1
+.names $undef
+.names q_counter[7] rst_counter q_counter[6] $abc$3686$new_n20_ $0\q_counter[7][0:0]
+0011 1
+1000 1
+1001 1
+1010 1
+.names q_counter[4] q_counter[5] q_counter[3] q_counter[2] q_counter[1] q_counter[0] $abc$3686$new_n20_
+111111 1
+.names q_counter[6] $abc$3686$new_n20_ rst_counter $0\q_counter[6][0:0]
+010 1
+100 1
+.names q_counter[5] $abc$3686$new_n23_ rst_counter $0\q_counter[5][0:0]
+010 1
+100 1
+.names q_counter[4] q_counter[3] q_counter[2] q_counter[1] q_counter[0] $abc$3686$new_n23_
+11111 1
+.names q_counter[2] rst_counter q_counter[1] q_counter[0] $0\q_counter[2][0:0]
+0011 1
+1000 1
+1001 1
+1010 1
+.names q_counter[4] rst_counter q_counter[3] q_counter[2] q_counter[1] q_counter[0] $0\q_counter[4][0:0]
+001111 1
+100000 1
+100001 1
+100010 1
+100011 1
+100100 1
+100101 1
+100110 1
+100111 1
+101000 1
+101001 1
+101010 1
+101011 1
+101100 1
+101101 1
+101110 1
+.names q_counter[3] rst_counter q_counter[2] q_counter[1] q_counter[0] $0\q_counter[3][0:0]
+00111 1
+10000 1
+10001 1
+10010 1
+10011 1
+10100 1
+10101 1
+10110 1
+.names q_counter[1] q_counter[0] rst_counter $0\q_counter[1][0:0]
+010 1
+100 1
+.names q_counter[0] rst_counter $0\q_counter[0][0:0]
+00 1
+.latch $0\q_counter[7][0:0] q_counter[7] re clk_counter 2
+.latch $0\q_counter[6][0:0] q_counter[6] re clk_counter 2
+.latch $0\q_counter[5][0:0] q_counter[5] re clk_counter 2
+.latch $0\q_counter[4][0:0] q_counter[4] re clk_counter 2
+.latch $0\q_counter[3][0:0] q_counter[3] re clk_counter 2
+.latch $0\q_counter[2][0:0] q_counter[2] re clk_counter 2
+.latch $0\q_counter[1][0:0] q_counter[1] re clk_counter 2
+.latch $0\q_counter[0][0:0] q_counter[0] re clk_counter 2
+.end
diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter/counter_pre_vpr.act b/openfpga_flow/benchmarks/micro_benchmark/counter/counter_pre_vpr.act
new file mode 100644
index 000000000..800b2a89e
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/counter/counter_pre_vpr.act
@@ -0,0 +1,20 @@
+clk_counter 0.500000 2.000000
+rst_counter 0.492200 0.201800
+q_counter[0] 0.281800 0.563400
+q_counter[1] 0.248200 0.273600
+q_counter[2] 0.183200 0.125600
+q_counter[3] 0.097400 0.044800
+q_counter[4] 0.022600 0.007200
+q_counter[5] 0.002200 0.000800
+q_counter[6] 0.000000 0.000000
+q_counter[7] 0.000000 0.000000
+$0\q_counter[7][0:0] 0 0
+$0\q_counter[6][0:0] 0 0
+$0\q_counter[5][0:0] 0 0
+$0\q_counter[4][0:0] 0 0
+$0\q_counter[3][0:0] 0 0
+$0\q_counter[2][0:0] 0 0
+$0\q_counter[1][0:0] 0 0
+$0\q_counter[0][0:0] 0 0
+$abc$3686$new_n23_ 0 0
+$abc$3686$new_n20_ 0 0
diff --git a/openfpga_flow/tasks/openfpga_shell/implicit_verilog/config/task.conf b/openfpga_flow/tasks/openfpga_shell/implicit_verilog/config/task.conf
index 21751cc7f..4040caee1 100644
--- a/openfpga_flow/tasks/openfpga_shell/implicit_verilog/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/implicit_verilog/config/task.conf
@@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter_post_yosys.blif
 
 [SYNTHESIS_PARAM]
-bench0_top = and2
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench0_top = counter
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter_pre_vpr.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter_output_verilog.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]

From b8bc74cc2682ed692fafe767aceca3bf12b1b7e6 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 10 Jun 2020 14:24:17 -0600
Subject: [PATCH 633/645] trying to fix the dependency problem of VPR GUI in
 openfpga shell

---
 vpr/CMakeLists.txt | 1 -
 1 file changed, 1 deletion(-)

diff --git a/vpr/CMakeLists.txt b/vpr/CMakeLists.txt
index 592fa2edb..9df8703da 100644
--- a/vpr/CMakeLists.txt
+++ b/vpr/CMakeLists.txt
@@ -89,7 +89,6 @@ if (VPR_USE_EZGL STREQUAL "on")
         ${RESOURCE_LIST}
     )
 
-
     add_custom_target(
       resource ALL
       DEPENDS

From 15f087598c3ce8704c69d6605b7796a6523d1bc7 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 10 Jun 2020 15:10:19 -0600
Subject: [PATCH 634/645] split simulation settings to a separated XML file

---
 libopenfpga/libarchopenfpga/CMakeLists.txt    | 19 ++++------
 .../arch/sample_simulation_setting.xml        | 36 ++++++++++++++++++
 .../src/read_xml_openfpga_arch.cpp            | 32 ++++++++++++++++
 .../src/read_xml_openfpga_arch.h              |  2 +
 .../src/read_xml_simulation_setting.cpp       | 20 +++++-----
 .../src/read_xml_simulation_setting.h         |  5 ++-
 .../src/simulation_setting.cpp                |  5 +++
 .../libarchopenfpga/src/simulation_setting.h  |  5 +++
 .../src/write_xml_openfpga_arch.cpp           | 24 +++++++++++-
 .../src/write_xml_openfpga_arch.h             |  4 ++
 .../src/write_xml_simulation_setting.cpp      | 16 ++++----
 .../src/write_xml_simulation_setting.h        |  2 +-
 libopenfpga/libarchopenfpga/test/main.cpp     | 37 -------------------
 13 files changed, 137 insertions(+), 70 deletions(-)
 create mode 100644 libopenfpga/libarchopenfpga/arch/sample_simulation_setting.xml
 delete mode 100644 libopenfpga/libarchopenfpga/test/main.cpp

diff --git a/libopenfpga/libarchopenfpga/CMakeLists.txt b/libopenfpga/libarchopenfpga/CMakeLists.txt
index b8a9a3fc1..d204718d7 100644
--- a/libopenfpga/libarchopenfpga/CMakeLists.txt
+++ b/libopenfpga/libarchopenfpga/CMakeLists.txt
@@ -2,7 +2,7 @@ cmake_minimum_required(VERSION 3.9)
 
 project("libarchopenfpga")
 
-file(GLOB_RECURSE EXEC_SOURCES test/main.cpp)
+file(GLOB_RECURSE EXEC_SOURCES test/*.cpp)
 file(GLOB_RECURSE LIB_SOURCES src/*.cpp)
 file(GLOB_RECURSE LIB_HEADERS src/*.h)
 files_to_dirs(LIB_HEADERS LIB_INCLUDE_DIRS)
@@ -26,13 +26,10 @@ target_link_libraries(libarchopenfpga
                       libpugiutil)
 
 #Create the test executable
-add_executable(read_arch_openfpga ${EXEC_SOURCES})
-target_link_libraries(read_arch_openfpga libarchopenfpga)
-
-#Supress IPO link warnings if IPO is enabled
-get_target_property(READ_ARCH_USES_IPO read_arch_openfpga INTERPROCEDURAL_OPTIMIZATION)
-if (READ_ARCH_USES_IPO)
-    set_target_properties(read_arch_openfpga PROPERTIES LINK_FLAGS ${IPO_LINK_WARN_SUPRESS_FLAGS})
-endif()
-
-install(TARGETS libarchopenfpga read_arch_openfpga DESTINATION bin)
+foreach(testsourcefile ${EXEC_SOURCES})
+    # Use a simple string replace, to cut off .cpp.
+    get_filename_component(testname ${testsourcefile} NAME_WE)
+    add_executable(${testname} ${testsourcefile})
+    # Make sure the library is linked to each test executable
+    target_link_libraries(${testname} libarchopenfpga)
+endforeach(testsourcefile ${EXEC_SOURCES})
diff --git a/libopenfpga/libarchopenfpga/arch/sample_simulation_setting.xml b/libopenfpga/libarchopenfpga/arch/sample_simulation_setting.xml
new file mode 100644
index 000000000..349a49a89
--- /dev/null
+++ b/libopenfpga/libarchopenfpga/arch/sample_simulation_setting.xml
@@ -0,0 +1,36 @@
+<!-- An example of simulation settings, where we define the options 
+     and process variations to be considered in simulations
+  -->
+<openfpga_simulation_setting>
+  <clock_setting>
+    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
+    <programming frequency="10e6"/>
+  </clock_setting>
+  <simulator_option>
+    <operating_condition temperature="25"/>
+    <output_log verbose="false" captab="false"/>
+    <accuracy type="abs" value="1e-13"/>
+    <runtime fast_simulation="true"/>
+  </simulator_option>
+  <monte_carlo num_simulation_points="2"/>
+  <measurement_setting>
+    <slew>
+      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
+      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
+    </slew>
+    <delay>
+      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
+      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
+    </delay>
+  </measurement_setting>
+  <stimulus>
+    <clock>
+      <rise slew_type="abs" slew_time="20e-12" />
+      <fall slew_type="abs" slew_time="20e-12" />
+    </clock>
+    <input>
+      <rise slew_type="abs" slew_time="25e-12" />
+      <fall slew_type="abs" slew_time="25e-12" />
+    </input>
+  </stimulus>
+</openfpga_simulation_setting>
diff --git a/libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.cpp b/libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.cpp
index 4c773f87f..031946346 100644
--- a/libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.cpp
+++ b/libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.cpp
@@ -113,3 +113,35 @@ openfpga::Arch read_xml_openfpga_arch(const char* arch_file_name) {
 
   return openfpga_arch;
 }
+
+/********************************************************************
+ * Top-level function to parse an XML file and load data to simulation settings
+ *******************************************************************/
+openfpga::SimulationSetting read_xml_openfpga_simulation_settings(const char* sim_setting_file_name) {
+  vtr::ScopedStartFinishTimer timer("Read OpenFPGA simulation settings");
+
+  openfpga::SimulationSetting openfpga_sim_setting;
+
+  pugi::xml_node Next;
+
+  /* Parse the file */
+  pugi::xml_document doc;
+  pugiutil::loc_data loc_data;
+
+  try {
+    loc_data = pugiutil::load_xml(doc, sim_setting_file_name);
+
+    /* Second node should be <openfpga_simulation_setting> */
+    auto xml_simulation_settings = get_single_child(doc, "openfpga_simulation_setting", loc_data); 
+
+    /* Parse simulation settings to data structure */
+    openfpga_sim_setting = read_xml_simulation_setting(xml_simulation_settings, loc_data);
+
+  } catch (pugiutil::XmlError& e) {
+    archfpga_throw(sim_setting_file_name, e.line(),
+                   "%s", e.what());
+  }
+
+  return openfpga_sim_setting; 
+}
+
diff --git a/libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.h b/libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.h
index e23018c8f..660baeec0 100644
--- a/libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.h
+++ b/libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.h
@@ -12,4 +12,6 @@
  *******************************************************************/
 openfpga::Arch read_xml_openfpga_arch(const char* arch_file_name);
 
+openfpga::SimulationSetting read_xml_openfpga_simulation_settings(const char* sim_setting_file_name);
+
 #endif
diff --git a/libopenfpga/libarchopenfpga/src/read_xml_simulation_setting.cpp b/libopenfpga/libarchopenfpga/src/read_xml_simulation_setting.cpp
index 60821e2ed..6007a14bf 100644
--- a/libopenfpga/libarchopenfpga/src/read_xml_simulation_setting.cpp
+++ b/libopenfpga/libarchopenfpga/src/read_xml_simulation_setting.cpp
@@ -40,7 +40,7 @@ e_sim_accuracy_type string_to_sim_accuracy_type(const std::string& type_string)
 static 
 void read_xml_clock_setting(pugi::xml_node& xml_clock_setting,
                             const pugiutil::loc_data& loc_data,
-                            SimulationSetting& sim_setting) {
+                            openfpga::SimulationSetting& sim_setting) {
   /* Parse operating clock setting */
   pugi::xml_node xml_operating_clock_setting = get_single_child(xml_clock_setting, "operating", loc_data);
 
@@ -73,7 +73,7 @@ void read_xml_clock_setting(pugi::xml_node& xml_clock_setting,
 static 
 void read_xml_simulator_option(pugi::xml_node& xml_sim_option,
                                const pugiutil::loc_data& loc_data,
-                               SimulationSetting& sim_setting) {
+                               openfpga::SimulationSetting& sim_setting) {
 
   pugi::xml_node xml_operating_condition = get_single_child(xml_sim_option, "operating_condition", loc_data);
   sim_setting.set_simulation_temperature(get_attribute(xml_operating_condition, "temperature", loc_data).as_float(0.));
@@ -119,7 +119,7 @@ void read_xml_simulator_option(pugi::xml_node& xml_sim_option,
 static 
 void read_xml_monte_carlo(pugi::xml_node& xml_mc,
                           const pugiutil::loc_data& loc_data,
-                          SimulationSetting& sim_setting) {
+                          openfpga::SimulationSetting& sim_setting) {
   sim_setting.set_monte_carlo_simulation_points(get_attribute(xml_mc, "num_simulation_points", loc_data).as_int(0));
 }
 
@@ -129,7 +129,7 @@ void read_xml_monte_carlo(pugi::xml_node& xml_mc,
 static 
 void read_xml_measurement_setting(pugi::xml_node& xml_measurement,
                                   const pugiutil::loc_data& loc_data,
-                                  SimulationSetting& sim_setting) {
+                                  openfpga::SimulationSetting& sim_setting) {
   pugi::xml_node xml_slew = get_single_child(xml_measurement, "slew", loc_data);
   pugi::xml_node xml_slew_rise = get_single_child(xml_slew, "rise", loc_data);
   sim_setting.set_measure_slew_upper_threshold(SIM_SIGNAL_RISE, get_attribute(xml_slew_rise, "upper_thres_pct", loc_data).as_float(0.));
@@ -155,7 +155,7 @@ void read_xml_measurement_setting(pugi::xml_node& xml_measurement,
 static 
 void read_xml_stimulus_clock(pugi::xml_node& xml_stimuli_clock,
                              const pugiutil::loc_data& loc_data,
-                             SimulationSetting& sim_setting,
+                             openfpga::SimulationSetting& sim_setting,
                              const e_sim_signal_type& signal_type) {
   /* Find the type of accuracy */
   const char* type_attr = get_attribute(xml_stimuli_clock, "slew_type", loc_data).value();
@@ -188,7 +188,7 @@ void read_xml_stimulus_clock(pugi::xml_node& xml_stimuli_clock,
 static 
 void read_xml_stimulus_input(pugi::xml_node& xml_stimuli_input,
                              const pugiutil::loc_data& loc_data,
-                             SimulationSetting& sim_setting,
+                             openfpga::SimulationSetting& sim_setting,
                              const e_sim_signal_type& signal_type) {
   /* Find the type of accuracy */
   const char* type_attr = get_attribute(xml_stimuli_input, "slew_type", loc_data).value();
@@ -221,7 +221,7 @@ void read_xml_stimulus_input(pugi::xml_node& xml_stimuli_input,
 static 
 void read_xml_stimulus(pugi::xml_node& xml_stimulus,
                        const pugiutil::loc_data& loc_data,
-                       SimulationSetting& sim_setting) {
+                       openfpga::SimulationSetting& sim_setting) {
   pugi::xml_node xml_clock = get_single_child(xml_stimulus, "clock", loc_data);
   pugi::xml_node xml_clock_rise = get_single_child(xml_clock, "rise", loc_data);
   read_xml_stimulus_clock(xml_clock_rise, loc_data, sim_setting, SIM_SIGNAL_RISE);
@@ -240,9 +240,9 @@ void read_xml_stimulus(pugi::xml_node& xml_stimulus,
 /********************************************************************
  * Parse XML codes about <openfpga_simulation_setting> to an object of technology library
  *******************************************************************/
-SimulationSetting read_xml_simulation_setting(pugi::xml_node& Node,
-                                              const pugiutil::loc_data& loc_data) {
-  SimulationSetting sim_setting;
+openfpga::SimulationSetting read_xml_simulation_setting(pugi::xml_node& Node,
+                                                        const pugiutil::loc_data& loc_data) {
+  openfpga::SimulationSetting sim_setting;
 
   /* Parse clock settings */
   pugi::xml_node xml_clock_setting = get_single_child(Node, "clock_setting", loc_data);
diff --git a/libopenfpga/libarchopenfpga/src/read_xml_simulation_setting.h b/libopenfpga/libarchopenfpga/src/read_xml_simulation_setting.h
index 801caad2e..df6f2856c 100644
--- a/libopenfpga/libarchopenfpga/src/read_xml_simulation_setting.h
+++ b/libopenfpga/libarchopenfpga/src/read_xml_simulation_setting.h
@@ -11,7 +11,8 @@
 /********************************************************************
  * Function declaration
  *******************************************************************/
-SimulationSetting read_xml_simulation_setting(pugi::xml_node& Node,
-                                              const pugiutil::loc_data& loc_data);
+
+openfpga::SimulationSetting read_xml_simulation_setting(pugi::xml_node& Node,
+                                                        const pugiutil::loc_data& loc_data);
 
 #endif
diff --git a/libopenfpga/libarchopenfpga/src/simulation_setting.cpp b/libopenfpga/libarchopenfpga/src/simulation_setting.cpp
index 2e332a29d..63f20a90c 100644
--- a/libopenfpga/libarchopenfpga/src/simulation_setting.cpp
+++ b/libopenfpga/libarchopenfpga/src/simulation_setting.cpp
@@ -2,6 +2,9 @@
 
 #include "simulation_setting.h"
 
+/* namespace openfpga begins */
+namespace openfpga {
+
 /************************************************************************
  * Member functions for class SimulationSetting
  ***********************************************************************/
@@ -208,3 +211,5 @@ void SimulationSetting::set_stimuli_input_slew(const e_sim_signal_type& signal_t
 bool SimulationSetting::valid_signal_threshold(const float& threshold) const {
   return (0. < threshold) && (threshold < 1);
 }
+
+} /* namespace openfpga ends */
diff --git a/libopenfpga/libarchopenfpga/src/simulation_setting.h b/libopenfpga/libarchopenfpga/src/simulation_setting.h
index f2e4add5c..7be1294eb 100644
--- a/libopenfpga/libarchopenfpga/src/simulation_setting.h
+++ b/libopenfpga/libarchopenfpga/src/simulation_setting.h
@@ -34,6 +34,9 @@ enum e_sim_accuracy_type {
 /* Strings correspond to each accuracy type */
 constexpr std::array<const char*, NUM_SIM_ACCURACY_TYPES> SIM_ACCURACY_TYPE_STRING = {{"frac", "abs"}};
 
+/* namespace openfpga begins */
+namespace openfpga {
+
 /********************************************************************
  * A data structure to describe simulation settings
  *
@@ -211,4 +214,6 @@ class SimulationSetting {
     std::array<float, NUM_SIM_ACCURACY_TYPES> input_slews_;
 };
 
+} /* namespace openfpga ends */
+
 #endif
diff --git a/libopenfpga/libarchopenfpga/src/write_xml_openfpga_arch.cpp b/libopenfpga/libarchopenfpga/src/write_xml_openfpga_arch.cpp
index 6d0a8ff06..468924ad2 100644
--- a/libopenfpga/libarchopenfpga/src/write_xml_openfpga_arch.cpp
+++ b/libopenfpga/libarchopenfpga/src/write_xml_openfpga_arch.cpp
@@ -20,7 +20,7 @@
 #include "write_xml_openfpga_arch.h"
 
 /********************************************************************
- * A writer to output an OpenFPGAArch to XML format
+ * A writer to output an OpenFPGA arch database to XML format
  *******************************************************************/
 void write_xml_openfpga_arch(const char* fname, 
                              const openfpga::Arch& openfpga_arch) {
@@ -69,3 +69,25 @@ void write_xml_openfpga_arch(const char* fname,
   /* Close the file stream */
   fp.close();
 }
+
+/********************************************************************
+ * A writer to output an OpenFPGA simulation setting database to XML format
+ *******************************************************************/
+void write_xml_openfpga_simulation_settings(const char* fname, 
+                                            const openfpga::SimulationSetting& openfpga_sim_setting) {
+  vtr::ScopedStartFinishTimer timer("Write OpenFPGA simulation settings");
+
+  /* Create a file handler */
+  std::fstream fp;
+  /* Open the file stream */
+  fp.open(std::string(fname), std::fstream::out | std::fstream::trunc);
+
+  /* Validate the file stream */
+  openfpga::check_file_stream(fname, fp);
+
+  /* Write the simulation */
+  write_xml_simulation_setting(fp, fname, openfpga_sim_setting);
+
+  /* Close the file stream */
+  fp.close();
+}
diff --git a/libopenfpga/libarchopenfpga/src/write_xml_openfpga_arch.h b/libopenfpga/libarchopenfpga/src/write_xml_openfpga_arch.h
index 790d483f4..68611493f 100644
--- a/libopenfpga/libarchopenfpga/src/write_xml_openfpga_arch.h
+++ b/libopenfpga/libarchopenfpga/src/write_xml_openfpga_arch.h
@@ -13,4 +13,8 @@
 void write_xml_openfpga_arch(const char* xml_fname, 
                              const openfpga::Arch& openfpga_arch);
 
+void write_xml_openfpga_simulation_settings(const char* xml_fname, 
+                                            const openfpga::SimulationSetting& openfpga_sim_setting);
+
+
 #endif
diff --git a/libopenfpga/libarchopenfpga/src/write_xml_simulation_setting.cpp b/libopenfpga/libarchopenfpga/src/write_xml_simulation_setting.cpp
index c5ff0beca..9403036c6 100644
--- a/libopenfpga/libarchopenfpga/src/write_xml_simulation_setting.cpp
+++ b/libopenfpga/libarchopenfpga/src/write_xml_simulation_setting.cpp
@@ -20,7 +20,7 @@
 static 
 void write_xml_clock_setting(std::fstream& fp,
                              const char* fname,
-                             const SimulationSetting& sim_setting) {
+                             const openfpga::SimulationSetting& sim_setting) {
   /* Validate the file stream */
   openfpga::check_file_stream(fname, fp);
 
@@ -53,7 +53,7 @@ void write_xml_clock_setting(std::fstream& fp,
 static 
 void write_xml_simulator_option(std::fstream& fp,
                                 const char* fname,
-                                const SimulationSetting& sim_setting) {
+                                const openfpga::SimulationSetting& sim_setting) {
   /* Validate the file stream */
   openfpga::check_file_stream(fname, fp);
 
@@ -87,7 +87,7 @@ void write_xml_simulator_option(std::fstream& fp,
 static 
 void write_xml_monte_carlo(std::fstream& fp,
                            const char* fname,
-                           const SimulationSetting& sim_setting) {
+                           const openfpga::SimulationSetting& sim_setting) {
   /* Validate the file stream */
   openfpga::check_file_stream(fname, fp);
 
@@ -111,7 +111,7 @@ void write_xml_monte_carlo(std::fstream& fp,
 static 
 void write_xml_slew_measurement(std::fstream& fp,
                                 const char* fname,
-                                const SimulationSetting& sim_setting,
+                                const openfpga::SimulationSetting& sim_setting,
                                 const e_sim_signal_type& signal_type) {
   /* Validate the file stream */
   openfpga::check_file_stream(fname, fp);
@@ -130,7 +130,7 @@ void write_xml_slew_measurement(std::fstream& fp,
 static 
 void write_xml_delay_measurement(std::fstream& fp,
                                 const char* fname,
-                                const SimulationSetting& sim_setting,
+                                const openfpga::SimulationSetting& sim_setting,
                                 const e_sim_signal_type& signal_type) {
   /* Validate the file stream */
   openfpga::check_file_stream(fname, fp);
@@ -149,7 +149,7 @@ void write_xml_delay_measurement(std::fstream& fp,
 static 
 void write_xml_measurement(std::fstream& fp,
                            const char* fname,
-                           const SimulationSetting& sim_setting) {
+                           const openfpga::SimulationSetting& sim_setting) {
   /* Validate the file stream */
   openfpga::check_file_stream(fname, fp);
 
@@ -174,7 +174,7 @@ void write_xml_measurement(std::fstream& fp,
 static 
 void write_xml_stimulus(std::fstream& fp,
                         const char* fname,
-                        const SimulationSetting& sim_setting) {
+                        const openfpga::SimulationSetting& sim_setting) {
   /* Validate the file stream */
   openfpga::check_file_stream(fname, fp);
 
@@ -216,7 +216,7 @@ void write_xml_stimulus(std::fstream& fp,
  *******************************************************************/
 void write_xml_simulation_setting(std::fstream& fp,
                                   const char* fname,
-                                  const SimulationSetting& sim_setting) {
+                                  const openfpga::SimulationSetting& sim_setting) {
   /* Validate the file stream */
   openfpga::check_file_stream(fname, fp);
   
diff --git a/libopenfpga/libarchopenfpga/src/write_xml_simulation_setting.h b/libopenfpga/libarchopenfpga/src/write_xml_simulation_setting.h
index 1c23ef0ca..d0581a8c6 100644
--- a/libopenfpga/libarchopenfpga/src/write_xml_simulation_setting.h
+++ b/libopenfpga/libarchopenfpga/src/write_xml_simulation_setting.h
@@ -12,6 +12,6 @@
  *******************************************************************/
 void write_xml_simulation_setting(std::fstream& fp,
                                   const char* fname,
-                                  const SimulationSetting& sim_setting);
+                                  const openfpga::SimulationSetting& sim_setting);
 
 #endif
diff --git a/libopenfpga/libarchopenfpga/test/main.cpp b/libopenfpga/libarchopenfpga/test/main.cpp
deleted file mode 100644
index 7974cf258..000000000
--- a/libopenfpga/libarchopenfpga/test/main.cpp
+++ /dev/null
@@ -1,37 +0,0 @@
-/********************************************************************
- * Unit test functions to validate the correctness of 
- * 1. parser of data structures
- * 2. writer of data structures
- *******************************************************************/
-/* Headers from vtrutils */
-#include "vtr_assert.h"
-#include "vtr_log.h"
-
-/* Headers from readarchopenfpga */
-#include "check_circuit_library.h"
-#include "read_xml_openfpga_arch.h"
-#include "write_xml_openfpga_arch.h"
-
-int main(int argc, const char** argv) {
-  /* Ensure we have only one or two argument */
-  VTR_ASSERT((2 == argc) || (3 == argc));
-
-  /* Parse the circuit library from an XML file */
-  const openfpga::Arch& openfpga_arch = read_xml_openfpga_arch(argv[1]); 
-  VTR_LOG("Parsed %lu circuit models from XML into circuit library.\n",
-          openfpga_arch.circuit_lib.num_models());
-
-  /* Check the circuit library */
-  check_circuit_library(openfpga_arch.circuit_lib);
-  
-  /* Output the circuit library to an XML file
-   * This is optional only used when there is a second argument
-   */
-  if (3 <= argc) { 
-    write_xml_openfpga_arch(argv[2], openfpga_arch);
-    VTR_LOG("Echo the OpenFPGA architecture to an XML file: %s.\n",
-            argv[2]);
-  }
-}
-
-

From 4a2f6dfae21cf52fec402eea3a07c827b358912e Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 10 Jun 2020 15:23:32 -0600
Subject: [PATCH 635/645] add read/write simulation setting commands to
 openfpga shell

---
 openfpga/src/base/openfpga_context.h         |  3 +
 openfpga/src/base/openfpga_read_arch.cpp     | 54 ++++++++++++++++
 openfpga/src/base/openfpga_read_arch.h       |  6 ++
 openfpga/src/base/openfpga_setup_command.cpp | 66 ++++++++++++++++++++
 4 files changed, 129 insertions(+)

diff --git a/openfpga/src/base/openfpga_context.h b/openfpga/src/base/openfpga_context.h
index 0eb34c029..e18a3fd34 100644
--- a/openfpga/src/base/openfpga_context.h
+++ b/openfpga/src/base/openfpga_context.h
@@ -50,6 +50,7 @@
 class OpenfpgaContext : public Context  {
   public:  /* Public accessors */
     const openfpga::Arch& arch() const { return arch_; }
+    const openfpga::SimulationSetting& simulation_setting() const { return sim_setting_; }
     const openfpga::VprDeviceAnnotation& vpr_device_annotation() const { return vpr_device_annotation_; }
     const openfpga::VprNetlistAnnotation& vpr_netlist_annotation() const { return vpr_netlist_annotation_; }
     const openfpga::VprClusteringAnnotation& vpr_clustering_annotation() const { return vpr_clustering_annotation_; }
@@ -68,6 +69,7 @@ class OpenfpgaContext : public Context  {
     const openfpga::NetlistManager& verilog_netlists() const { return verilog_netlists_; }
   public:  /* Public mutators */
     openfpga::Arch& mutable_arch() { return arch_; }
+    openfpga::SimulationSetting& mutable_simulation_setting() { return sim_setting_; }
     openfpga::VprDeviceAnnotation& mutable_vpr_device_annotation() { return vpr_device_annotation_; }
     openfpga::VprNetlistAnnotation& mutable_vpr_netlist_annotation() { return vpr_netlist_annotation_; }
     openfpga::VprClusteringAnnotation& mutable_vpr_clustering_annotation() { return vpr_clustering_annotation_; }
@@ -87,6 +89,7 @@ class OpenfpgaContext : public Context  {
   private: /* Internal data */
     /* Data structure to store information from read_openfpga_arch library */
     openfpga::Arch arch_;
+    openfpga::SimulationSetting sim_setting_;
 
     /* Annotation to pb_type of VPR */
     openfpga::VprDeviceAnnotation vpr_device_annotation_;
diff --git a/openfpga/src/base/openfpga_read_arch.cpp b/openfpga/src/base/openfpga_read_arch.cpp
index db9b09b5b..ce7aed6ba 100644
--- a/openfpga/src/base/openfpga_read_arch.cpp
+++ b/openfpga/src/base/openfpga_read_arch.cpp
@@ -87,5 +87,59 @@ int write_arch(const OpenfpgaContext& openfpga_context,
   return CMD_EXEC_SUCCESS;
 } 
 
+/********************************************************************
+ * Top-level function to read an OpenFPGA simulation setting file
+ * we use the APIs from the libarchopenfpga library 
+ *
+ * The command will accept an option '--file' which is the simulation setting
+ * file provided by users  
+ *******************************************************************/
+int read_simulation_setting(OpenfpgaContext& openfpga_context,
+                            const Command& cmd, const CommandContext& cmd_context) {
+  /* Check the option '--file' is enabled or not 
+   * Actually, it must be enabled as the shell interface will check 
+   * before reaching this fuction
+   */
+  CommandOptionId opt_file = cmd.option("file");
+  VTR_ASSERT(true == cmd_context.option_enable(cmd, opt_file));
+  VTR_ASSERT(false == cmd_context.option_value(cmd, opt_file).empty());
+
+  std::string arch_file_name = cmd_context.option_value(cmd, opt_file);
+
+  VTR_LOG("Reading XML simulation setting '%s'...\n",
+          arch_file_name.c_str());
+  openfpga_context.mutable_simulation_setting() = read_xml_openfpga_simulation_settings(arch_file_name.c_str());
+
+  /* TODO: should identify the error code from internal function execution */
+  return CMD_EXEC_SUCCESS;
+}
+
+/********************************************************************
+ * A function to write an OpenFPGA simulation setting file
+ * we use the APIs from the libarchopenfpga library 
+ *
+ * The command will accept an option '--file' which is the simulation setting
+ * file provided by users  
+ *******************************************************************/
+int write_simulation_setting(const OpenfpgaContext& openfpga_context,
+                             const Command& cmd, const CommandContext& cmd_context) {
+  /* Check the option '--file' is enabled or not 
+   * Actually, it must be enabled as the shell interface will check 
+   * before reaching this fuction
+   */
+  CommandOptionId opt_file = cmd.option("file");
+  VTR_ASSERT(true == cmd_context.option_enable(cmd, opt_file));
+  VTR_ASSERT(false == cmd_context.option_value(cmd, opt_file).empty());
+
+  std::string arch_file_name = cmd_context.option_value(cmd, opt_file);
+
+  VTR_LOG("Writing XML simulation setting to '%s'...\n",
+          arch_file_name.c_str());
+  write_xml_openfpga_simulation_settings(arch_file_name.c_str(), openfpga_context.simulation_setting());
+
+  /* TODO: should identify the error code from internal function execution */
+  return CMD_EXEC_SUCCESS;
+} 
+
 } /* end namespace openfpga */
 
diff --git a/openfpga/src/base/openfpga_read_arch.h b/openfpga/src/base/openfpga_read_arch.h
index b664a7b3e..d5502db56 100644
--- a/openfpga/src/base/openfpga_read_arch.h
+++ b/openfpga/src/base/openfpga_read_arch.h
@@ -21,6 +21,12 @@ int read_arch(OpenfpgaContext& openfpga_context,
 int write_arch(const OpenfpgaContext& openfpga_context,
                const Command& cmd, const CommandContext& cmd_context);
 
+int read_simulation_setting(OpenfpgaContext& openfpga_context,
+                            const Command& cmd, const CommandContext& cmd_context); 
+
+int write_simulation_setting(const OpenfpgaContext& openfpga_context,
+                             const Command& cmd, const CommandContext& cmd_context);
+
 } /* end namespace openfpga */
 
 #endif
diff --git a/openfpga/src/base/openfpga_setup_command.cpp b/openfpga/src/base/openfpga_setup_command.cpp
index 8af22e7da..b47cfb97a 100644
--- a/openfpga/src/base/openfpga_setup_command.cpp
+++ b/openfpga/src/base/openfpga_setup_command.cpp
@@ -64,6 +64,55 @@ ShellCommandId add_openfpga_write_arch_command(openfpga::Shell<OpenfpgaContext>&
   return shell_cmd_id;
 }
 
+/********************************************************************
+ * - Add a command to Shell environment: read_openfpga_simulation_setting
+ * - Add associated options 
+ * - Add command dependency
+ *******************************************************************/
+static 
+ShellCommandId add_openfpga_read_simulation_setting_command(openfpga::Shell<OpenfpgaContext>& shell,
+                                                            const ShellCommandClassId& cmd_class_id) {
+  Command shell_cmd("read_openfpga_simulation_setting");
+
+  /* Add an option '--file' in short '-f'*/
+  CommandOptionId opt_file = shell_cmd.add_option("file", true, "file path to the simulation setting XML");
+  shell_cmd.set_option_short_name(opt_file, "f");
+  shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING);
+
+  /* Add command 'read_openfpga_arch' to the Shell */
+  ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "read OpenFPGA simulation setting file");
+  shell.set_command_class(shell_cmd_id, cmd_class_id);
+  shell.set_command_execute_function(shell_cmd_id, read_simulation_setting);
+
+  return shell_cmd_id;
+}
+
+/********************************************************************
+ * - Add a command to Shell environment: write_openfpga_simulation_setting
+ * - Add associated options 
+ * - Add command dependency
+ *******************************************************************/
+static 
+ShellCommandId add_openfpga_write_simulation_setting_command(openfpga::Shell<OpenfpgaContext>& shell,
+                                                             const ShellCommandClassId& cmd_class_id,
+                                                             const std::vector<ShellCommandId>& dependent_cmds) {
+  Command shell_cmd("write_openfpga_simulation_setting");
+  /* Add an option '--file' in short '-f'*/
+  CommandOptionId opt_file = shell_cmd.add_option("file", true, "file path to the simulation setting XML");
+  shell_cmd.set_option_short_name(opt_file, "f");
+  shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING);
+
+  /* Add command 'write_openfpga_arch' to the Shell */
+  ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "write OpenFPGA simulation setting file");
+  shell.set_command_class(shell_cmd_id, cmd_class_id);
+  shell.set_command_const_execute_function(shell_cmd_id, write_simulation_setting);
+
+  /* Add command dependency to the Shell */
+  shell.set_command_dependency(shell_cmd_id, dependent_cmds);
+
+  return shell_cmd_id;
+}
+
 /********************************************************************
  * - Add a command to Shell environment: link_openfpga_arch
  * - Add associated options 
@@ -295,16 +344,33 @@ void add_openfpga_setup_commands(openfpga::Shell<OpenfpgaContext>& shell) {
                                   openfpga_setup_cmd_class,
                                   write_arch_dependent_cmds);
 
+  /******************************** 
+   * Command 'read_openfpga_simulation_setting' 
+   */
+  ShellCommandId read_sim_setting_cmd_id = add_openfpga_read_simulation_setting_command(shell,
+                                                                                        openfpga_setup_cmd_class);
+
+  /******************************** 
+   * Command 'write_openfpga_simulation_setting' 
+   */
+  /* The 'write_openfpga_simulation_setting' command should NOT be executed before 'read_openfpga_simulation_setting' */
+  std::vector<ShellCommandId> write_sim_setting_dependent_cmds(1, read_sim_setting_cmd_id);
+  add_openfpga_write_simulation_setting_command(shell,
+                                                openfpga_setup_cmd_class,
+                                                write_sim_setting_dependent_cmds);
+
   /******************************** 
    * Command 'link_openfpga_arch' 
    */
   /* The 'link_openfpga_arch' command should NOT be executed before 'vpr' */
   std::vector<ShellCommandId> link_arch_dependent_cmds;
   link_arch_dependent_cmds.push_back(read_arch_cmd_id);
+  link_arch_dependent_cmds.push_back(read_sim_setting_cmd_id);
   link_arch_dependent_cmds.push_back(vpr_cmd_id);
   ShellCommandId link_arch_cmd_id = add_openfpga_link_arch_command(shell,
                                                                    openfpga_setup_cmd_class,
                                                                    link_arch_dependent_cmds);
+
   /******************************** 
    * Command 'write_gsb' 
    */

From 96b58dfdbbb12c14462d067848ae6038cdce4e95 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 10 Jun 2020 15:37:17 -0600
Subject: [PATCH 636/645] use new simulation setting command in openfpga shell

---
 openfpga/src/base/openfpga_link_arch.cpp                    | 6 +++++-
 openfpga/src/base/openfpga_sdc.cpp                          | 6 +++---
 openfpga/src/base/openfpga_setup_command.cpp                | 4 +++-
 openfpga/src/base/openfpga_verilog.cpp                      | 2 +-
 .../configuration_chain_example_script.openfpga             | 3 +++
 .../duplicated_grid_pin_example_script.openfpga             | 3 +++
 openfpga_flow/OpenFPGAShellScripts/example_script.openfpga  | 3 +++
 .../fast_configuration_example_script.openfpga              | 3 +++
 .../flatten_routing_example_script.openfpga                 | 3 +++
 .../full_testbench_example_script.openfpga                  | 3 +++
 .../generate_fabric_example_script.openfpga                 | 3 +++
 .../generate_testbench_example_script.openfpga              | 3 +++
 .../implicit_verilog_example_script.openfpga                | 3 +++
 .../OpenFPGAShellScripts/mcnc_example_script.openfpga       | 3 +++
 .../sdc_time_unit_example_script.openfpga                   | 3 +++
 15 files changed, 45 insertions(+), 6 deletions(-)

diff --git a/openfpga/src/base/openfpga_link_arch.cpp b/openfpga/src/base/openfpga_link_arch.cpp
index 65aef7cf8..c67619caa 100644
--- a/openfpga/src/base/openfpga_link_arch.cpp
+++ b/openfpga/src/base/openfpga_link_arch.cpp
@@ -147,9 +147,13 @@ int link_arch(OpenfpgaContext& openfpga_ctx,
    * We SHOULD create a new simulation setting for OpenFPGA use only
    * Avoid overwrite the raw data achieved when parsing!!!
    */
+  /* OVERWRITE the simulation setting in openfpga context from the arch
+   * TODO: This will be removed when openfpga flow is updated  
+   */
+  openfpga_ctx.mutable_simulation_setting() = openfpga_ctx.mutable_arch().sim_setting;
   annotate_simulation_setting(g_vpr_ctx.atom(),
                               openfpga_ctx.net_activity(),
-                              openfpga_ctx.mutable_arch().sim_setting);
+                              openfpga_ctx.mutable_simulation_setting());
 
   /* TODO: should identify the error code from internal function execution */
   return CMD_EXEC_SUCCESS;
diff --git a/openfpga/src/base/openfpga_sdc.cpp b/openfpga/src/base/openfpga_sdc.cpp
index 2d44520db..9bcbc26df 100644
--- a/openfpga/src/base/openfpga_sdc.cpp
+++ b/openfpga/src/base/openfpga_sdc.cpp
@@ -88,8 +88,8 @@ int write_pnr_sdc(const OpenfpgaContext& openfpga_ctx,
   /* Execute only when sdc is enabled */
   if (true == options.generate_sdc_pnr()) { 
     print_pnr_sdc(options,
-                  1./openfpga_ctx.arch().sim_setting.programming_clock_frequency(),
-                  1./openfpga_ctx.arch().sim_setting.operating_clock_frequency(),
+                  1./openfpga_ctx.simulation_setting().programming_clock_frequency(),
+                  1./openfpga_ctx.simulation_setting().operating_clock_frequency(),
                   g_vpr_ctx.device(),
                   openfpga_ctx.vpr_device_annotation(),
                   openfpga_ctx.device_rr_gsb(),
@@ -200,7 +200,7 @@ int write_analysis_sdc(const OpenfpgaContext& openfpga_ctx,
 
   if (true == options.generate_sdc_analysis()) {
     print_analysis_sdc(options,
-                       1./openfpga_ctx.arch().sim_setting.operating_clock_frequency(),
+                       1./openfpga_ctx.simulation_setting().operating_clock_frequency(),
                        g_vpr_ctx, 
                        openfpga_ctx,
                        global_ports,
diff --git a/openfpga/src/base/openfpga_setup_command.cpp b/openfpga/src/base/openfpga_setup_command.cpp
index b47cfb97a..e9d759b1f 100644
--- a/openfpga/src/base/openfpga_setup_command.cpp
+++ b/openfpga/src/base/openfpga_setup_command.cpp
@@ -365,7 +365,9 @@ void add_openfpga_setup_commands(openfpga::Shell<OpenfpgaContext>& shell) {
   /* The 'link_openfpga_arch' command should NOT be executed before 'vpr' */
   std::vector<ShellCommandId> link_arch_dependent_cmds;
   link_arch_dependent_cmds.push_back(read_arch_cmd_id);
-  link_arch_dependent_cmds.push_back(read_sim_setting_cmd_id);
+  /* TODO: This will be uncommented when openfpga flow script is updated
+   * link_arch_dependent_cmds.push_back(read_sim_setting_cmd_id);
+   */
   link_arch_dependent_cmds.push_back(vpr_cmd_id);
   ShellCommandId link_arch_cmd_id = add_openfpga_link_arch_command(shell,
                                                                    openfpga_setup_cmd_class,
diff --git a/openfpga/src/base/openfpga_verilog.cpp b/openfpga/src/base/openfpga_verilog.cpp
index 926e0f8d3..58ea20f2e 100644
--- a/openfpga/src/base/openfpga_verilog.cpp
+++ b/openfpga/src/base/openfpga_verilog.cpp
@@ -96,7 +96,7 @@ int write_verilog_testbench(OpenfpgaContext& openfpga_ctx,
                          openfpga_ctx.io_location_map(),
                          openfpga_ctx.vpr_netlist_annotation(),
                          openfpga_ctx.arch().circuit_lib,
-                         openfpga_ctx.arch().sim_setting,
+                         openfpga_ctx.simulation_setting(),
                          openfpga_ctx.arch().config_protocol.type(),
                          options);
 
diff --git a/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga
index 11f3ed295..7492854a2 100644
--- a/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga
@@ -5,6 +5,9 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
 # Read OpenFPGA architecture definition
 read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
 
+# Read OpenFPGA simulation settings
+#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE
+
 # Annotate the OpenFPGA architecture to VPR data base
 # to debug use --verbose options
 link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
diff --git a/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga
index bcc8d36e3..83707cf53 100644
--- a/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga
@@ -5,6 +5,9 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
 # Read OpenFPGA architecture definition
 read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
 
+# Read OpenFPGA simulation settings
+#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE
+
 # Annotate the OpenFPGA architecture to VPR data base
 # to debug use --verbose options
 link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
diff --git a/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
index bcc8d36e3..83707cf53 100644
--- a/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
@@ -5,6 +5,9 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
 # Read OpenFPGA architecture definition
 read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
 
+# Read OpenFPGA simulation settings
+#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE
+
 # Annotate the OpenFPGA architecture to VPR data base
 # to debug use --verbose options
 link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
diff --git a/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga
index 94e16b906..56d05257c 100644
--- a/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga
@@ -5,6 +5,9 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
 # Read OpenFPGA architecture definition
 read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
 
+# Read OpenFPGA simulation settings
+#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE
+
 # Annotate the OpenFPGA architecture to VPR data base
 # to debug use --verbose options
 link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
diff --git a/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga
index 3210b411f..fa376dbe3 100644
--- a/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga
@@ -5,6 +5,9 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
 # Read OpenFPGA architecture definition
 read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
 
+# Read OpenFPGA simulation settings
+#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE
+
 # Annotate the OpenFPGA architecture to VPR data base
 # to debug use --verbose options
 link_openfpga_arch --activity_file ${ACTIVITY_FILE}
diff --git a/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga
index bcc8d36e3..83707cf53 100644
--- a/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga
@@ -5,6 +5,9 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
 # Read OpenFPGA architecture definition
 read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
 
+# Read OpenFPGA simulation settings
+#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE
+
 # Annotate the OpenFPGA architecture to VPR data base
 # to debug use --verbose options
 link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga
index ff40f4c76..434c573e1 100644
--- a/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga
@@ -5,6 +5,9 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
 # Read OpenFPGA architecture definition
 read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
 
+# Read OpenFPGA simulation settings
+#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE
+
 # Annotate the OpenFPGA architecture to VPR data base
 # to debug use --verbose options
 link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga
index a426a7833..6fe802168 100644
--- a/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga
@@ -5,6 +5,9 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
 # Read OpenFPGA architecture definition
 read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
 
+# Read OpenFPGA simulation settings
+#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE
+
 # Annotate the OpenFPGA architecture to VPR data base
 # to debug use --verbose options
 link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
diff --git a/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga
index 579e113a9..021488557 100644
--- a/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga
@@ -5,6 +5,9 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
 # Read OpenFPGA architecture definition
 read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
 
+# Read OpenFPGA simulation settings
+#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE
+
 # Annotate the OpenFPGA architecture to VPR data base
 # to debug use --verbose options
 link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
diff --git a/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga
index 3293979ea..ebd6c217c 100644
--- a/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga
@@ -5,6 +5,9 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --absorb_buffe
 # Read OpenFPGA architecture definition
 read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
 
+# Read OpenFPGA simulation settings
+#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE
+
 # Annotate the OpenFPGA architecture to VPR data base
 # to debug use --verbose options
 link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
diff --git a/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga
index 6841eb935..3411f6e87 100644
--- a/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga
@@ -5,6 +5,9 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
 # Read OpenFPGA architecture definition
 read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
 
+# Read OpenFPGA simulation settings
+#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE
+
 # Annotate the OpenFPGA architecture to VPR data base
 # to debug use --verbose options
 link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges

From cb09896f23b059a5f617fd689607d210d7eb0449 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 10 Jun 2020 15:41:46 -0600
Subject: [PATCH 637/645] add example simulation setting for openfpga flow

---
 .../auto_sim_openfpga.xml                     | 39 +++++++++++++++++++
 .../fixed_sim_openfpga.xml                    | 37 ++++++++++++++++++
 2 files changed, 76 insertions(+)
 create mode 100644 openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 create mode 100644 openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml

diff --git a/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml b/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
new file mode 100644
index 000000000..99ff97235
--- /dev/null
+++ b/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
@@ -0,0 +1,39 @@
+<!-- Simulation Setting for OpenFPGA framework
+     This file will use automatic inference for any settings
+     including:
+     - auto select the number of simulation cycles
+     - auto select the simulation clock frequency from VPR results
+  -->
+<openfpga_simulation_setting>
+  <clock_setting>
+    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
+    <programming frequency="100e6"/>
+  </clock_setting>
+  <simulator_option>
+    <operating_condition temperature="25"/>
+    <output_log verbose="false" captab="false"/>
+    <accuracy type="abs" value="1e-13"/>
+    <runtime fast_simulation="true"/>
+  </simulator_option>
+  <monte_carlo num_simulation_points="2"/>
+  <measurement_setting>
+    <slew>
+      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
+      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
+    </slew>
+    <delay>
+      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
+      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
+    </delay>
+  </measurement_setting>
+  <stimulus>
+    <clock>
+      <rise slew_type="abs" slew_time="20e-12" />
+      <fall slew_type="abs" slew_time="20e-12" />
+    </clock>
+    <input>
+      <rise slew_type="abs" slew_time="25e-12" />
+      <fall slew_type="abs" slew_time="25e-12" />
+    </input>
+  </stimulus>
+</openfpga_simulation_setting>
diff --git a/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml b/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
new file mode 100644
index 000000000..94593863d
--- /dev/null
+++ b/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
@@ -0,0 +1,37 @@
+<!-- Simulation Setting for OpenFPGA framework
+     This file will use 
+     - a fixed simulation clock frequency
+  -->
+<openfpga_simulation_setting>
+  <clock_setting>
+    <operating frequency="500e6" num_cycles="10" slack="0.2"/>
+    <programming frequency="300e6"/>
+  </clock_setting>
+  <simulator_option>
+    <operating_condition temperature="25"/>
+    <output_log verbose="false" captab="false"/>
+    <accuracy type="abs" value="1e-13"/>
+    <runtime fast_simulation="true"/>
+  </simulator_option>
+  <monte_carlo num_simulation_points="2"/>
+  <measurement_setting>
+    <slew>
+      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
+      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
+    </slew>
+    <delay>
+      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
+      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
+    </delay>
+  </measurement_setting>
+  <stimulus>
+    <clock>
+      <rise slew_type="abs" slew_time="20e-12" />
+      <fall slew_type="abs" slew_time="20e-12" />
+    </clock>
+    <input>
+      <rise slew_type="abs" slew_time="25e-12" />
+      <fall slew_type="abs" slew_time="25e-12" />
+    </input>
+  </stimulus>
+</openfpga_simulation_setting>

From dfdfea208149ab99aadf676251a380c1f18bceb1 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 10 Jun 2020 15:49:20 -0600
Subject: [PATCH 638/645] fix the bug in CMake Script due to splitted
 simulation setting files

---
 CMakeLists.txt | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/CMakeLists.txt b/CMakeLists.txt
index f46955c8b..6aa930b94 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -258,12 +258,6 @@ set_target_properties(libvpr vpr_shell
   LIBRARY_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/vpr7_x2p/vpr"
   RUNTIME_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/vpr7_x2p/vpr")
 
-set_target_properties(libarchopenfpga read_arch_openfpga
-  PROPERTIES
-  ARCHIVE_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/libopenfpga/libarchopenfpga"
-  LIBRARY_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/libopenfpga/libarchopenfpga"
-  RUNTIME_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/libopenfpga/libarchopenfpga")
-
 set_target_properties(libvpr8 vpr8
   PROPERTIES
   ARCHIVE_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/vpr"

From f26550141fd4f1a11ac382b3da6c1f358f23cd9c Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 10 Jun 2020 15:56:37 -0600
Subject: [PATCH 639/645] add missing files

---
 .../test/read_arch_openfpga.cpp               | 37 +++++++++++++++++++
 .../test/read_simulation_setting_openfpga.cpp | 31 ++++++++++++++++
 2 files changed, 68 insertions(+)
 create mode 100644 libopenfpga/libarchopenfpga/test/read_arch_openfpga.cpp
 create mode 100644 libopenfpga/libarchopenfpga/test/read_simulation_setting_openfpga.cpp

diff --git a/libopenfpga/libarchopenfpga/test/read_arch_openfpga.cpp b/libopenfpga/libarchopenfpga/test/read_arch_openfpga.cpp
new file mode 100644
index 000000000..7974cf258
--- /dev/null
+++ b/libopenfpga/libarchopenfpga/test/read_arch_openfpga.cpp
@@ -0,0 +1,37 @@
+/********************************************************************
+ * Unit test functions to validate the correctness of 
+ * 1. parser of data structures
+ * 2. writer of data structures
+ *******************************************************************/
+/* Headers from vtrutils */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+/* Headers from readarchopenfpga */
+#include "check_circuit_library.h"
+#include "read_xml_openfpga_arch.h"
+#include "write_xml_openfpga_arch.h"
+
+int main(int argc, const char** argv) {
+  /* Ensure we have only one or two argument */
+  VTR_ASSERT((2 == argc) || (3 == argc));
+
+  /* Parse the circuit library from an XML file */
+  const openfpga::Arch& openfpga_arch = read_xml_openfpga_arch(argv[1]); 
+  VTR_LOG("Parsed %lu circuit models from XML into circuit library.\n",
+          openfpga_arch.circuit_lib.num_models());
+
+  /* Check the circuit library */
+  check_circuit_library(openfpga_arch.circuit_lib);
+  
+  /* Output the circuit library to an XML file
+   * This is optional only used when there is a second argument
+   */
+  if (3 <= argc) { 
+    write_xml_openfpga_arch(argv[2], openfpga_arch);
+    VTR_LOG("Echo the OpenFPGA architecture to an XML file: %s.\n",
+            argv[2]);
+  }
+}
+
+
diff --git a/libopenfpga/libarchopenfpga/test/read_simulation_setting_openfpga.cpp b/libopenfpga/libarchopenfpga/test/read_simulation_setting_openfpga.cpp
new file mode 100644
index 000000000..b8540240b
--- /dev/null
+++ b/libopenfpga/libarchopenfpga/test/read_simulation_setting_openfpga.cpp
@@ -0,0 +1,31 @@
+/********************************************************************
+ * Unit test functions to validate the correctness of 
+ * 1. parser of data structures
+ * 2. writer of data structures
+ *******************************************************************/
+/* Headers from vtrutils */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+/* Headers from readarchopenfpga */
+#include "read_xml_openfpga_arch.h"
+#include "write_xml_openfpga_arch.h"
+
+int main(int argc, const char** argv) {
+  /* Ensure we have only one or two argument */
+  VTR_ASSERT((2 == argc) || (3 == argc));
+
+  /* Parse the simulation settings from an XML file */
+  const openfpga::SimulationSetting& openfpga_sim_setting = read_xml_openfpga_simulation_settings(argv[1]); 
+  VTR_LOG("Parsed simulation settings from XML %s.\n",
+          argv[1]);
+
+  /* Output the simulation settings to an XML file
+   * This is optional only used when there is a second argument
+   */
+  if (3 <= argc) { 
+    write_xml_openfpga_simulation_settings(argv[2], openfpga_sim_setting);
+    VTR_LOG("Echo the OpenFPGA simulation settings to an XML file: %s.\n",
+            argv[2]);
+  }
+}

From 1a006f2ddb484d34610adad212c0bb85a410e33f Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 10 Jun 2020 20:05:43 -0600
Subject: [PATCH 640/645] update documentation for separated XML files

---
 docs/source/manual/arch_lang/generality.rst   | 53 ++++++++++++-------
 docs/source/manual/fpga_spice/index.rst       |  5 +-
 .../openfpga_shell/openfpga_commands.rst      | 18 ++++++-
 3 files changed, 53 insertions(+), 23 deletions(-)

diff --git a/docs/source/manual/arch_lang/generality.rst b/docs/source/manual/arch_lang/generality.rst
index d594ff896..af7719b9a 100644
--- a/docs/source/manual/arch_lang/generality.rst
+++ b/docs/source/manual/arch_lang/generality.rst
@@ -1,4 +1,4 @@
-.. _generality:
+.. _arch_generality:
 
 General Hierarchy
 -----------------
@@ -13,34 +13,49 @@ In the following sub-sections, we will introduce the structures of these XML nod
 For OpenFPGA using VPR8
 ~~~~~~~~~~~~~~~~~~~~~~~
 
-OpenFPGA uses a separated XML file other than the VPR8 architecture description file.
+OpenFPGA uses separated XMLs file other than the VPR8 architecture description file.
 This is to keep a loose integration to VPR8 so that OpenFPGA can easily integrate any future version of VPR with least engineering effort.
 However, to implement a physical FPGA, OpenFPGA requires the original VPR XML to include full physical design details.
 Full syntax can be found in :ref:`addon_vpr_syntax`.
 
-The OpenFPGA architecture description XML file consisting of the following parts:
+The OpenFPGA requires two XML files: an architecture description file and a simulation setting description file.
 
-  - ``<openfpga_architecture>`` contains architecture-level information, such as device-level description, circuit-level and architecture annotations to original VPR architecture XML. It consists of the following code blocks
+OpenFPGA Architecture Description File
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+This file contains device-level and circuit-level details as well as annotations to the original VPR architecture.
+It contains a root node called ``<openfpga_architecture>`` under which architecture-level information, such as device-level description, circuit-level and architecture annotations to original VPR architecture XML are defined.
+
+It consists of the following code blocks
 
     - ``<circuit_library>`` includes a number of ``circuit_model``, each of which describe a primitive block in FPGA architecture, such as Look-Up Tables and multiplexers. Full syntax can be found in :ref:`circuit_library`.
-    - ``<technology_library>`` includes transistor-level parameters, where users can specify which transistor models are going to be used when building the ``circuit models``. 
-    - ``<configuration_protocol>`` includes detailed description on the configuration protocols to be used in FPGA fabric.
-    - ``<connection_block>`` includes annotation on the connection block definition ``<connection_block>`` in original VPR XML
-    - ``<switch_block>`` includes annotation on the switch block definition ``<switchlist>`` in original VPR XML
-    - ``<routing_segment>`` includes annotation on the routing segment definition ``<segmentlist>`` in original VPR XML
-    - ``<direct_connection>`` includes annotation on the inter-tile direct connection definitioin ``<directlist>`` in original VPR XML
-    - ``<pb_type_annotation>`` includes annotation on the programmable block architecture ``<complexblocklist>`` in original VPR XML
-
-  - ``<openfpga_simulation_setting>`` includes all the parameters to be used in generate testbenches in simulation purpose. Full syntax can be found in :ref:`simulation_setting`.
-
-    - ``<clock_setting>`` defines the clock-related settings in simulation, such as clock frequency and number of clock cycles to be used
-    - ``<simulator_option>`` defines universal options available in both HDL and SPICE simulators. This is mainly used by FPGA-SPICE
-    - ``<monte_carlo>`` defines critical parameters to be used in monte-carlo simulations. This is used by FPGA-SPICE
-    - ``<measurement_setting>`` defines the parameters used to measure signal slew and delays. This is used by FPGA-SPICE
-    - ``<stimulus>`` defines the parameters used to generate voltage stimuli in testbenches. This is used by FPGA-SPICE
+    - ``<technology_library>`` includes transistor-level parameters, where users can specify which transistor models are going to be used when building the ``circuit models``.  Full syntax can be found in :ref:`technology_library`.
+    - ``<configuration_protocol>`` includes detailed description on the configuration protocols to be used in FPGA fabric. Full syntax can be found in :ref:`config_protocol`.
+    - ``<connection_block>`` includes annotation on the connection block definition ``<connection_block>`` in original VPR XML. Full syntax can be found in :ref:`annotate_vpr_arch`.
+    - ``<switch_block>`` includes annotation on the switch block definition ``<switchlist>`` in original VPR XML. Full syntax can be found in :ref:`annotate_vpr_arch`.
+    - ``<routing_segment>`` includes annotation on the routing segment definition ``<segmentlist>`` in original VPR XML. Full syntax can be found in :ref:`annotate_vpr_arch`.
+    - ``<direct_connection>`` includes annotation on the inter-tile direct connection definitioin ``<directlist>`` in original VPR XML. Full syntax can be found in :ref:`direct_interconnect`.
+    - ``<pb_type_annotation>`` includes annotation on the programmable block architecture ``<complexblocklist>`` in original VPR XML. Full syntax can be found in :ref:`annotate_vpr_arch`.
 
 .. note:: ``<technology_library>`` will be applied to ``circuit_model`` when running FPGA-SPICE. It will not impact FPGA-Verilog, FPGA-Bitstream, FPGA-SDC.
 
+
+OpenFPGA Simulation Setting File
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+This file contains parameters required by testbench generators.
+It contains a root node ``<openfpga_simulation_setting>``, under which all the parameters to be used in generate testbenches in simulation purpose are defined.
+
+It consists of the following code blocks
+
+    - ``<clock_setting>`` defines the clock-related settings in simulation, such as clock frequency and number of clock cycles to be used.
+    - ``<simulator_option>`` defines universal options available in both HDL and SPICE simulators. This is mainly used by :ref:`fpga_spice`.
+    - ``<monte_carlo>`` defines critical parameters to be used in monte-carlo simulations. This is used by  :ref:`fpga_spice`.
+    - ``<measurement_setting>`` defines the parameters used to measure signal slew and delays. This is used by :ref:`fpga_spice`.
+    - ``<stimulus>`` defines the parameters used to generate voltage stimuli in testbenches. This is used by :ref:`fpga_spice`.
+
+Full syntax can be found in :ref:`simulation_setting`.
+
 .. note:: the parameters in ``<clock_setting>`` will be applied to both FPGA-Verilog and FPGA-SPICE simulations
 
 
diff --git a/docs/source/manual/fpga_spice/index.rst b/docs/source/manual/fpga_spice/index.rst
index 4cdffcc0f..b8ce29223 100644
--- a/docs/source/manual/fpga_spice/index.rst
+++ b/docs/source/manual/fpga_spice/index.rst
@@ -1,11 +1,10 @@
+.. _fpga_spice:
+
 FPGA-SPICE
 ----------
 
 .. warning:: FPGA-SPICE has not been integrated to VPR8 version yet. Please the following tool guide is for VPR7 version now
 
-.. _fpga_spice:
-   FPGA-SPICE
- 
 .. toctree::
    :maxdepth: 2
   
diff --git a/docs/source/manual/openfpga_shell/openfpga_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands.rst
index 6e2f0e490..eb5929861 100644
--- a/docs/source/manual/openfpga_shell/openfpga_commands.rst
+++ b/docs/source/manual/openfpga_shell/openfpga_commands.rst
@@ -28,7 +28,7 @@ Setup OpenFPGA
 
 .. option:: read_openfpga_arch
 
-  Read the XML architecture file required by OpenFPGA
+  Read the XML file about architecture description (see details in :ref:`arch_generality`)
 
   - ``--file`` or ``-f`` Specify the file name 
 
@@ -42,6 +42,22 @@ Setup OpenFPGA
 
   - ``--verbose`` Show verbose log
 
+.. option:: read_openfpga_simulation_setting
+
+  Read the XML file about simulation settings (see details in :ref:`simulation_setting`)
+
+  - ``--file`` or ``-f`` Specify the file name 
+
+  - ``--verbose`` Show verbose log
+
+.. option:: write_openfpga_simulation_setting
+
+  Write the OpenFPGA XML simulation settings to a file
+
+  - ``--file`` or ``-f`` Specify the file name 
+
+  - ``--verbose`` Show verbose log
+
 .. option:: link_openfpga_arch
 
   Annotate the OpenFPGA architecture to VPR data base

From 1842bf51e1d37bbc077a3fe211665ff465d1795b Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 11 Jun 2020 11:22:47 -0600
Subject: [PATCH 641/645] deploy read_openfpga_simulation_setting in CI on a
 single test case

---
 .../configuration_chain_example_script.openfpga                 | 2 +-
 .../full_testbench/configuration_chain/config/task.conf         | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga
index 7492854a2..0cf8a6448 100644
--- a/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga
@@ -6,7 +6,7 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
 read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
 
 # Read OpenFPGA simulation settings
-#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE
+read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
 
 # Annotate the OpenFPGA architecture to VPR data base
 # to debug use --verbose options
diff --git a/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_chain/config/task.conf b/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_chain/config/task.conf
index 8318c1dea..9b4921136 100644
--- a/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_chain/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_chain/config/task.conf
@@ -16,6 +16,7 @@ verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml

From 068d9943e746c4d830d9d6c6e709f073512f6d87 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 11 Jun 2020 11:41:36 -0600
Subject: [PATCH 642/645] update all the templates and regression test cases
 with simulation settings

---
 .../duplicated_grid_pin_example_script.openfpga                 | 2 +-
 openfpga_flow/OpenFPGAShellScripts/example_script.openfpga      | 2 +-
 .../fast_configuration_example_script.openfpga                  | 2 +-
 .../flatten_routing_example_script.openfpga                     | 2 +-
 .../OpenFPGAShellScripts/full_testbench_example_script.openfpga | 2 +-
 .../generate_fabric_example_script.openfpga                     | 2 +-
 .../generate_testbench_example_script.openfpga                  | 2 +-
 .../implicit_verilog_example_script.openfpga                    | 2 +-
 openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga | 2 +-
 .../OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga  | 2 +-
 .../tasks/openfpga_shell/behavioral_verilog/config/task.conf    | 1 +
 .../tasks/openfpga_shell/bram/dpram16k/config/task.conf         | 1 +
 .../tasks/openfpga_shell/bram/wide_dpram16k/config/task.conf    | 2 +-
 .../tasks/openfpga_shell/duplicated_grid_pin/config/task.conf   | 1 +
 .../openfpga_shell/fabric_chain/adder_chain/config/task.conf    | 1 +
 .../openfpga_shell/fabric_chain/register_chain/config/task.conf | 1 +
 .../openfpga_shell/fabric_chain/scan_chain/config/task.conf     | 1 +
 .../openfpga_shell/fixed_simulation_settings/config/task.conf   | 1 +
 .../tasks/openfpga_shell/flatten_routing/config/task.conf       | 1 +
 .../full_testbench/configuration_frame/config/task.conf         | 1 +
 .../full_testbench/fast_configuration_frame/config/task.conf    | 1 +
 .../full_testbench/fast_memory_bank/config/task.conf            | 1 +
 .../full_testbench/flatten_memory/config/task.conf              | 1 +
 .../openfpga_shell/full_testbench/memory_bank/config/task.conf  | 1 +
 .../tasks/openfpga_shell/generate_fabric/config/task.conf       | 1 +
 .../tasks/openfpga_shell/generate_testbench/config/task.conf    | 1 +
 openfpga_flow/tasks/openfpga_shell/hard_adder/config/task.conf  | 1 +
 .../tasks/openfpga_shell/implicit_verilog/config/task.conf      | 1 +
 openfpga_flow/tasks/openfpga_shell/io/aib/config/task.conf      | 1 +
 .../tasks/openfpga_shell/io/multi_io_capacity/config/task.conf  | 1 +
 .../tasks/openfpga_shell/io/reduced_io/config/task.conf         | 1 +
 .../tasks/openfpga_shell/lut_design/frac_lut/config/task.conf   | 1 +
 .../lut_design/intermediate_buffer/config/task.conf             | 1 +
 .../openfpga_shell/lut_design/single_mode/config/task.conf      | 1 +
 .../openfpga_shell/mux_design/local_encoder/config/task.conf    | 1 +
 .../openfpga_shell/mux_design/stdcell_mux2/config/task.conf     | 1 +
 .../openfpga_shell/mux_design/tree_structure/config/task.conf   | 1 +
 .../preconfig_testbench/configuration_chain/config/task.conf    | 1 +
 .../preconfig_testbench/configuration_frame/config/task.conf    | 1 +
 .../preconfig_testbench/flatten_memory/config/task.conf         | 1 +
 .../preconfig_testbench/memory_bank/config/task.conf            | 1 +
 .../tasks/openfpga_shell/sdc_time_unit/config/task.conf         | 1 +
 openfpga_flow/tasks/openfpga_shell/spypad/config/task.conf      | 1 +
 openfpga_flow/tasks/openfpga_shell/untileable/config/task.conf  | 1 +
 44 files changed, 44 insertions(+), 11 deletions(-)

diff --git a/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga
index 83707cf53..ae729290e 100644
--- a/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga
@@ -6,7 +6,7 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
 read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
 
 # Read OpenFPGA simulation settings
-#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE
+read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
 
 # Annotate the OpenFPGA architecture to VPR data base
 # to debug use --verbose options
diff --git a/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
index 83707cf53..ae729290e 100644
--- a/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
@@ -6,7 +6,7 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
 read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
 
 # Read OpenFPGA simulation settings
-#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE
+read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
 
 # Annotate the OpenFPGA architecture to VPR data base
 # to debug use --verbose options
diff --git a/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga
index 56d05257c..fceabcaaa 100644
--- a/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga
@@ -6,7 +6,7 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
 read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
 
 # Read OpenFPGA simulation settings
-#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE
+read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
 
 # Annotate the OpenFPGA architecture to VPR data base
 # to debug use --verbose options
diff --git a/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga
index fa376dbe3..5ab1c56b6 100644
--- a/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga
@@ -6,7 +6,7 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
 read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
 
 # Read OpenFPGA simulation settings
-#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE
+read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
 
 # Annotate the OpenFPGA architecture to VPR data base
 # to debug use --verbose options
diff --git a/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga
index 83707cf53..ae729290e 100644
--- a/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga
@@ -6,7 +6,7 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
 read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
 
 # Read OpenFPGA simulation settings
-#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE
+read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
 
 # Annotate the OpenFPGA architecture to VPR data base
 # to debug use --verbose options
diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga
index 434c573e1..38ebc9d28 100644
--- a/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga
@@ -6,7 +6,7 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
 read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
 
 # Read OpenFPGA simulation settings
-#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE
+read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
 
 # Annotate the OpenFPGA architecture to VPR data base
 # to debug use --verbose options
diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga
index 6fe802168..971f8d374 100644
--- a/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga
@@ -6,7 +6,7 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
 read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
 
 # Read OpenFPGA simulation settings
-#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE
+read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
 
 # Annotate the OpenFPGA architecture to VPR data base
 # to debug use --verbose options
diff --git a/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga
index 021488557..e86ba055e 100644
--- a/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga
@@ -6,7 +6,7 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
 read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
 
 # Read OpenFPGA simulation settings
-#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE
+read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
 
 # Annotate the OpenFPGA architecture to VPR data base
 # to debug use --verbose options
diff --git a/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga
index ebd6c217c..dc7af60ae 100644
--- a/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga
@@ -6,7 +6,7 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --absorb_buffe
 read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
 
 # Read OpenFPGA simulation settings
-#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE
+read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
 
 # Annotate the OpenFPGA architecture to VPR data base
 # to debug use --verbose options
diff --git a/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga
index 3411f6e87..36c3c88b9 100644
--- a/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga
@@ -6,7 +6,7 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
 read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
 
 # Read OpenFPGA simulation settings
-#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE
+read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
 
 # Annotate the OpenFPGA architecture to VPR data base
 # to debug use --verbose options
diff --git a/openfpga_flow/tasks/openfpga_shell/behavioral_verilog/config/task.conf b/openfpga_flow/tasks/openfpga_shell/behavioral_verilog/config/task.conf
index e11da844f..3693bd3db 100644
--- a/openfpga_flow/tasks/openfpga_shell/behavioral_verilog/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/behavioral_verilog/config/task.conf
@@ -16,6 +16,7 @@ verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
diff --git a/openfpga_flow/tasks/openfpga_shell/bram/dpram16k/config/task.conf b/openfpga_flow/tasks/openfpga_shell/bram/dpram16k/config/task.conf
index 4996f42e2..93e491745 100644
--- a/openfpga_flow/tasks/openfpga_shell/bram/dpram16k/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/bram/dpram16k/config/task.conf
@@ -16,6 +16,7 @@ verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml
diff --git a/openfpga_flow/tasks/openfpga_shell/bram/wide_dpram16k/config/task.conf b/openfpga_flow/tasks/openfpga_shell/bram/wide_dpram16k/config/task.conf
index 5cfc3ce57..3d89335d9 100644
--- a/openfpga_flow/tasks/openfpga_shell/bram/wide_dpram16k/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/bram/wide_dpram16k/config/task.conf
@@ -16,7 +16,7 @@ verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
-
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml
diff --git a/openfpga_flow/tasks/openfpga_shell/duplicated_grid_pin/config/task.conf b/openfpga_flow/tasks/openfpga_shell/duplicated_grid_pin/config/task.conf
index f2777f7ee..328203c08 100644
--- a/openfpga_flow/tasks/openfpga_shell/duplicated_grid_pin/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/duplicated_grid_pin/config/task.conf
@@ -16,6 +16,7 @@ verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
diff --git a/openfpga_flow/tasks/openfpga_shell/fabric_chain/adder_chain/config/task.conf b/openfpga_flow/tasks/openfpga_shell/fabric_chain/adder_chain/config/task.conf
index 5e9533e36..4ab0447a3 100644
--- a/openfpga_flow/tasks/openfpga_shell/fabric_chain/adder_chain/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/fabric_chain/adder_chain/config/task.conf
@@ -16,6 +16,7 @@ verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_40nm.xml
diff --git a/openfpga_flow/tasks/openfpga_shell/fabric_chain/register_chain/config/task.conf b/openfpga_flow/tasks/openfpga_shell/fabric_chain/register_chain/config/task.conf
index 1b76cb3e9..06441b7f3 100644
--- a/openfpga_flow/tasks/openfpga_shell/fabric_chain/register_chain/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/fabric_chain/register_chain/config/task.conf
@@ -16,6 +16,7 @@ verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_chain_40nm.xml
diff --git a/openfpga_flow/tasks/openfpga_shell/fabric_chain/scan_chain/config/task.conf b/openfpga_flow/tasks/openfpga_shell/fabric_chain/scan_chain/config/task.conf
index ac398aa4c..0d1f49c94 100644
--- a/openfpga_flow/tasks/openfpga_shell/fabric_chain/scan_chain/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/fabric_chain/scan_chain/config/task.conf
@@ -16,6 +16,7 @@ verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml
diff --git a/openfpga_flow/tasks/openfpga_shell/fixed_simulation_settings/config/task.conf b/openfpga_flow/tasks/openfpga_shell/fixed_simulation_settings/config/task.conf
index 4875931e3..813aabc03 100644
--- a/openfpga_flow/tasks/openfpga_shell/fixed_simulation_settings/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/fixed_simulation_settings/config/task.conf
@@ -16,6 +16,7 @@ verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml
diff --git a/openfpga_flow/tasks/openfpga_shell/flatten_routing/config/task.conf b/openfpga_flow/tasks/openfpga_shell/flatten_routing/config/task.conf
index 2879e95ed..36bdb28bd 100644
--- a/openfpga_flow/tasks/openfpga_shell/flatten_routing/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/flatten_routing/config/task.conf
@@ -16,6 +16,7 @@ verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
diff --git a/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_frame/config/task.conf b/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_frame/config/task.conf
index 2f5baca4d..e99b9c2ab 100644
--- a/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_frame/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_frame/config/task.conf
@@ -16,6 +16,7 @@ verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml
diff --git a/openfpga_flow/tasks/openfpga_shell/full_testbench/fast_configuration_frame/config/task.conf b/openfpga_flow/tasks/openfpga_shell/full_testbench/fast_configuration_frame/config/task.conf
index 55c98dda1..0a95022d3 100644
--- a/openfpga_flow/tasks/openfpga_shell/full_testbench/fast_configuration_frame/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/full_testbench/fast_configuration_frame/config/task.conf
@@ -16,6 +16,7 @@ verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml
diff --git a/openfpga_flow/tasks/openfpga_shell/full_testbench/fast_memory_bank/config/task.conf b/openfpga_flow/tasks/openfpga_shell/full_testbench/fast_memory_bank/config/task.conf
index 61b3d8b72..eb3aafbd3 100644
--- a/openfpga_flow/tasks/openfpga_shell/full_testbench/fast_memory_bank/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/full_testbench/fast_memory_bank/config/task.conf
@@ -16,6 +16,7 @@ verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml
diff --git a/openfpga_flow/tasks/openfpga_shell/full_testbench/flatten_memory/config/task.conf b/openfpga_flow/tasks/openfpga_shell/full_testbench/flatten_memory/config/task.conf
index d2bf1bb9f..b893a163f 100644
--- a/openfpga_flow/tasks/openfpga_shell/full_testbench/flatten_memory/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/full_testbench/flatten_memory/config/task.conf
@@ -16,6 +16,7 @@ verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml
diff --git a/openfpga_flow/tasks/openfpga_shell/full_testbench/memory_bank/config/task.conf b/openfpga_flow/tasks/openfpga_shell/full_testbench/memory_bank/config/task.conf
index b000c0ba6..fadc53968 100644
--- a/openfpga_flow/tasks/openfpga_shell/full_testbench/memory_bank/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/full_testbench/memory_bank/config/task.conf
@@ -16,6 +16,7 @@ verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml
diff --git a/openfpga_flow/tasks/openfpga_shell/generate_fabric/config/task.conf b/openfpga_flow/tasks/openfpga_shell/generate_fabric/config/task.conf
index 75bc6c703..077bafbc5 100644
--- a/openfpga_flow/tasks/openfpga_shell/generate_fabric/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/generate_fabric/config/task.conf
@@ -16,6 +16,7 @@ verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
diff --git a/openfpga_flow/tasks/openfpga_shell/generate_testbench/config/task.conf b/openfpga_flow/tasks/openfpga_shell/generate_testbench/config/task.conf
index 9540b767f..02d4fb597 100644
--- a/openfpga_flow/tasks/openfpga_shell/generate_testbench/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/generate_testbench/config/task.conf
@@ -16,6 +16,7 @@ verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
diff --git a/openfpga_flow/tasks/openfpga_shell/hard_adder/config/task.conf b/openfpga_flow/tasks/openfpga_shell/hard_adder/config/task.conf
index c0198598e..2d8c162d0 100644
--- a/openfpga_flow/tasks/openfpga_shell/hard_adder/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/hard_adder/config/task.conf
@@ -16,6 +16,7 @@ verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_40nm.xml
diff --git a/openfpga_flow/tasks/openfpga_shell/implicit_verilog/config/task.conf b/openfpga_flow/tasks/openfpga_shell/implicit_verilog/config/task.conf
index 4040caee1..36cc8208d 100644
--- a/openfpga_flow/tasks/openfpga_shell/implicit_verilog/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/implicit_verilog/config/task.conf
@@ -16,6 +16,7 @@ verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
diff --git a/openfpga_flow/tasks/openfpga_shell/io/aib/config/task.conf b/openfpga_flow/tasks/openfpga_shell/io/aib/config/task.conf
index 0f4727657..ab8b7849e 100644
--- a/openfpga_flow/tasks/openfpga_shell/io/aib/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/io/aib/config/task.conf
@@ -16,6 +16,7 @@ verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 
 #####################################
 # Debugging status 
diff --git a/openfpga_flow/tasks/openfpga_shell/io/multi_io_capacity/config/task.conf b/openfpga_flow/tasks/openfpga_shell/io/multi_io_capacity/config/task.conf
index 8ae3286c5..c751ed64c 100644
--- a/openfpga_flow/tasks/openfpga_shell/io/multi_io_capacity/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/io/multi_io_capacity/config/task.conf
@@ -16,6 +16,7 @@ verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml
diff --git a/openfpga_flow/tasks/openfpga_shell/io/reduced_io/config/task.conf b/openfpga_flow/tasks/openfpga_shell/io/reduced_io/config/task.conf
index 190acfda7..17b2c8564 100644
--- a/openfpga_flow/tasks/openfpga_shell/io/reduced_io/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/io/reduced_io/config/task.conf
@@ -16,6 +16,7 @@ verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml
diff --git a/openfpga_flow/tasks/openfpga_shell/lut_design/frac_lut/config/task.conf b/openfpga_flow/tasks/openfpga_shell/lut_design/frac_lut/config/task.conf
index 030c0d41e..39bbeb784 100644
--- a/openfpga_flow/tasks/openfpga_shell/lut_design/frac_lut/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/lut_design/frac_lut/config/task.conf
@@ -16,6 +16,7 @@ verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
diff --git a/openfpga_flow/tasks/openfpga_shell/lut_design/intermediate_buffer/config/task.conf b/openfpga_flow/tasks/openfpga_shell/lut_design/intermediate_buffer/config/task.conf
index b2535bd7c..885569b51 100644
--- a/openfpga_flow/tasks/openfpga_shell/lut_design/intermediate_buffer/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/lut_design/intermediate_buffer/config/task.conf
@@ -16,6 +16,7 @@ verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_N10_tileable_40nm.xml
diff --git a/openfpga_flow/tasks/openfpga_shell/lut_design/single_mode/config/task.conf b/openfpga_flow/tasks/openfpga_shell/lut_design/single_mode/config/task.conf
index 4216a7482..0c735e07f 100644
--- a/openfpga_flow/tasks/openfpga_shell/lut_design/single_mode/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/lut_design/single_mode/config/task.conf
@@ -16,6 +16,7 @@ verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_N10_tileable_40nm.xml
diff --git a/openfpga_flow/tasks/openfpga_shell/mux_design/local_encoder/config/task.conf b/openfpga_flow/tasks/openfpga_shell/mux_design/local_encoder/config/task.conf
index 76cf4b589..7b48cf6e2 100644
--- a/openfpga_flow/tasks/openfpga_shell/mux_design/local_encoder/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/mux_design/local_encoder/config/task.conf
@@ -16,6 +16,7 @@ verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
diff --git a/openfpga_flow/tasks/openfpga_shell/mux_design/stdcell_mux2/config/task.conf b/openfpga_flow/tasks/openfpga_shell/mux_design/stdcell_mux2/config/task.conf
index 60df151e7..08bebdf04 100644
--- a/openfpga_flow/tasks/openfpga_shell/mux_design/stdcell_mux2/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/mux_design/stdcell_mux2/config/task.conf
@@ -16,6 +16,7 @@ verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
diff --git a/openfpga_flow/tasks/openfpga_shell/mux_design/tree_structure/config/task.conf b/openfpga_flow/tasks/openfpga_shell/mux_design/tree_structure/config/task.conf
index 3f8b56582..48633266c 100644
--- a/openfpga_flow/tasks/openfpga_shell/mux_design/tree_structure/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/mux_design/tree_structure/config/task.conf
@@ -16,6 +16,7 @@ verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
diff --git a/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/configuration_chain/config/task.conf b/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/configuration_chain/config/task.conf
index 3fd340a7b..9c9fc9627 100644
--- a/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/configuration_chain/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/configuration_chain/config/task.conf
@@ -16,6 +16,7 @@ verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml
diff --git a/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/configuration_frame/config/task.conf b/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/configuration_frame/config/task.conf
index 4a41fc671..e55a6ea8e 100644
--- a/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/configuration_frame/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/configuration_frame/config/task.conf
@@ -16,6 +16,7 @@ verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml
diff --git a/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/flatten_memory/config/task.conf b/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/flatten_memory/config/task.conf
index 1a02eb45f..78d1e818c 100644
--- a/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/flatten_memory/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/flatten_memory/config/task.conf
@@ -16,6 +16,7 @@ verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml
diff --git a/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/memory_bank/config/task.conf b/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/memory_bank/config/task.conf
index 75579406c..c9505c1d5 100644
--- a/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/memory_bank/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/memory_bank/config/task.conf
@@ -16,6 +16,7 @@ verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml
diff --git a/openfpga_flow/tasks/openfpga_shell/sdc_time_unit/config/task.conf b/openfpga_flow/tasks/openfpga_shell/sdc_time_unit/config/task.conf
index 332020fab..11cd98766 100644
--- a/openfpga_flow/tasks/openfpga_shell/sdc_time_unit/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/sdc_time_unit/config/task.conf
@@ -16,6 +16,7 @@ verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml
diff --git a/openfpga_flow/tasks/openfpga_shell/spypad/config/task.conf b/openfpga_flow/tasks/openfpga_shell/spypad/config/task.conf
index b42e17287..d7d55eb62 100644
--- a/openfpga_flow/tasks/openfpga_shell/spypad/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/spypad/config/task.conf
@@ -16,6 +16,7 @@ verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml
diff --git a/openfpga_flow/tasks/openfpga_shell/untileable/config/task.conf b/openfpga_flow/tasks/openfpga_shell/untileable/config/task.conf
index 7dcf88915..a7e1939ed 100644
--- a/openfpga_flow/tasks/openfpga_shell/untileable/config/task.conf
+++ b/openfpga_flow/tasks/openfpga_shell/untileable/config/task.conf
@@ -16,6 +16,7 @@ verilog_output=true
 timeout_each_job = 20*60
 fpga_flow=vpr_blif
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_40nm.xml

From 58807bfcb3227e67e7744291a3b2db61570d0439 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 11 Jun 2020 11:58:18 -0600
Subject: [PATCH 643/645] remove simulation settings from openfpga arch data
 structure

---
 libopenfpga/libarchopenfpga/src/openfpga_arch.h             | 3 ---
 libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.cpp  | 6 ------
 libopenfpga/libarchopenfpga/src/write_xml_openfpga_arch.cpp | 3 ---
 openfpga/src/base/openfpga_link_arch.cpp                    | 2 +-
 openfpga/src/base/openfpga_setup_command.cpp                | 2 +-
 5 files changed, 2 insertions(+), 14 deletions(-)

diff --git a/libopenfpga/libarchopenfpga/src/openfpga_arch.h b/libopenfpga/libarchopenfpga/src/openfpga_arch.h
index a3dd71a12..33d8f1b6c 100644
--- a/libopenfpga/libarchopenfpga/src/openfpga_arch.h
+++ b/libopenfpga/libarchopenfpga/src/openfpga_arch.h
@@ -29,9 +29,6 @@ struct Arch {
   /* Technology devices */
   TechnologyLibrary tech_lib;
 
-  /* Simulation settings */
-  SimulationSetting sim_setting;
-
   /* Configuration protocol settings */
   ConfigProtocol config_protocol;
 
diff --git a/libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.cpp b/libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.cpp
index 031946346..1d5f23e9e 100644
--- a/libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.cpp
+++ b/libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.cpp
@@ -100,12 +100,6 @@ openfpga::Arch read_xml_openfpga_arch(const char* arch_file_name) {
     /* Parse the pb_type annotation */
     openfpga_arch.pb_type_annotations = read_xml_pb_type_annotations(xml_openfpga_arch, loc_data);
 
-    /* Second node should be <openfpga_simulation_setting> */
-    auto xml_simulation_settings = get_single_child(doc, "openfpga_simulation_setting", loc_data); 
-
-    /* Parse simulation settings to data structure */
-    openfpga_arch.sim_setting = read_xml_simulation_setting(xml_simulation_settings, loc_data);
-
   } catch (pugiutil::XmlError& e) {
     archfpga_throw(arch_file_name, e.line(),
                    "%s", e.what());
diff --git a/libopenfpga/libarchopenfpga/src/write_xml_openfpga_arch.cpp b/libopenfpga/libarchopenfpga/src/write_xml_openfpga_arch.cpp
index 468924ad2..2c5134d4e 100644
--- a/libopenfpga/libarchopenfpga/src/write_xml_openfpga_arch.cpp
+++ b/libopenfpga/libarchopenfpga/src/write_xml_openfpga_arch.cpp
@@ -63,9 +63,6 @@ void write_xml_openfpga_arch(const char* fname,
 
   fp << "</openfpga_architecture>" << "\n";
 
-  /* Write the simulation */
-  write_xml_simulation_setting(fp, fname, openfpga_arch.sim_setting);
-
   /* Close the file stream */
   fp.close();
 }
diff --git a/openfpga/src/base/openfpga_link_arch.cpp b/openfpga/src/base/openfpga_link_arch.cpp
index c67619caa..af75ff6a2 100644
--- a/openfpga/src/base/openfpga_link_arch.cpp
+++ b/openfpga/src/base/openfpga_link_arch.cpp
@@ -150,7 +150,7 @@ int link_arch(OpenfpgaContext& openfpga_ctx,
   /* OVERWRITE the simulation setting in openfpga context from the arch
    * TODO: This will be removed when openfpga flow is updated  
    */
-  openfpga_ctx.mutable_simulation_setting() = openfpga_ctx.mutable_arch().sim_setting;
+  //openfpga_ctx.mutable_simulation_setting() = openfpga_ctx.mutable_arch().sim_setting;
   annotate_simulation_setting(g_vpr_ctx.atom(),
                               openfpga_ctx.net_activity(),
                               openfpga_ctx.mutable_simulation_setting());
diff --git a/openfpga/src/base/openfpga_setup_command.cpp b/openfpga/src/base/openfpga_setup_command.cpp
index e9d759b1f..bf2412a6f 100644
--- a/openfpga/src/base/openfpga_setup_command.cpp
+++ b/openfpga/src/base/openfpga_setup_command.cpp
@@ -366,8 +366,8 @@ void add_openfpga_setup_commands(openfpga::Shell<OpenfpgaContext>& shell) {
   std::vector<ShellCommandId> link_arch_dependent_cmds;
   link_arch_dependent_cmds.push_back(read_arch_cmd_id);
   /* TODO: This will be uncommented when openfpga flow script is updated
-   * link_arch_dependent_cmds.push_back(read_sim_setting_cmd_id);
    */
+  link_arch_dependent_cmds.push_back(read_sim_setting_cmd_id);
   link_arch_dependent_cmds.push_back(vpr_cmd_id);
   ShellCommandId link_arch_cmd_id = add_openfpga_link_arch_command(shell,
                                                                    openfpga_setup_cmd_class,

From 60dd37e08603c5a863651a35ca4aac2037885dcc Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 11 Jun 2020 12:05:12 -0600
Subject: [PATCH 644/645] remove simulation settings from openfpga arch XML

update travis to split CI tests

fix errors in travis configuration

fixing travis errors in scripts

keep fixing travis

fix travis on build.sh

bug fixing in travis CI

bug fix in travis regression test run

fixing bugs in the travis scripts

bug fix in travis script: remove common.sh in regression test call

keep bug fixing in travis
---
 .travis.yml                                   | 180 +++++++++---------
 .travis/build.sh                              |  17 ++
 .travis/install.sh                            |  25 +--
 .travis/openfpga_vpr7_reg_test.sh             |  30 +++
 .../{script.sh => openfpga_vpr8_reg_test.sh}  |  39 +---
 .../k4_N4_40nm_bank_openfpga.xml              |  33 ----
 .../openfpga_arch/k4_N4_40nm_cc_openfpga.xml  |  33 ----
 .../k4_N4_40nm_fixed_sim_openfpga.xml         |  33 ----
 .../k4_N4_40nm_frame_openfpga.xml             |  33 ----
 .../k4_N4_40nm_standalone_openfpga.xml        |  33 ----
 .../openfpga_arch/k6_N10_40nm_openfpga.xml    |  33 ----
 ..._N10_intermediate_buffer_40nm_openfpga.xml |  33 ----
 .../k6_frac_N10_40nm_openfpga.xml             |  34 ----
 .../k6_frac_N10_adder_chain_40nm_openfpga.xml |  34 ----
 ...c_N10_adder_chain_mem16K_40nm_openfpga.xml |  34 ----
 ...0_adder_chain_mem16K_aib_40nm_openfpga.xml |  34 ----
 ...c_N10_adder_column_chain_40nm_openfpga.xml |  34 ----
 ...N10_adder_register_chain_40nm_openfpga.xml |  34 ----
 ...dder_register_scan_chain_40nm_openfpga.xml |  34 ----
 ...ister_scan_chain_depop50_40nm_openfpga.xml |  34 ----
 ...can_chain_depop50_spypad_40nm_openfpga.xml |  34 ----
 .../k6_frac_N10_behavioral_40nm_openfpga.xml  |  34 ----
 ...6_frac_N10_local_encoder_40nm_openfpga.xml |  34 ----
 .../k6_frac_N10_spyio_40nm_openfpga.xml       |  34 ----
 .../k6_frac_N10_stdcell_mux_40nm_openfpga.xml |  34 ----
 .../k6_frac_N10_tree_mux_40nm_openfpga.xml    |  34 ----
 26 files changed, 148 insertions(+), 850 deletions(-)
 create mode 100644 .travis/build.sh
 create mode 100755 .travis/openfpga_vpr7_reg_test.sh
 rename .travis/{script.sh => openfpga_vpr8_reg_test.sh} (82%)

diff --git a/.travis.yml b/.travis.yml
index 0b5ce92fb..13b89c162 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -14,105 +14,99 @@ cache:
 # Currently sudo is not required, NO ENV is used
 
 # Supported Operating systems
-#os:
-#  - linux
-#  - osx
-# Create a matrix to branch the building environment
-matrix:
-  include:
-    - os: linux
-    # Compiler is specified in ./travis/common.sh
-      sudo: false
-      dist: bionic
-      compiler: g++-8
-      addons:
-        apt:
-          sources:
-          - ubuntu-toolchain-r-test # For newer GCC
-          - llvm_toolchain-trusty-7
-          packages:
-          - autoconf
-          - automake
-          - bash
-          - bison
-          - build-essential
-          - cmake
-          - ctags
-          - curl
-          - doxygen
-          - flex
-          - fontconfig
-          - g++-8
-          - gcc-8
-          - gdb
-          - git
-          - gperf
-          - iverilog
-          - libcairo2-dev
-          - libevent-dev
-          - libfontconfig1-dev
-          - liblist-moreutils-perl
-          - libncurses5-dev
-          - libx11-dev
-          - libxft-dev
-          - libxml++2.6-dev
-          - perl
-          - python
-          - python-lxml
-          - texinfo
-          - time
-          - valgrind
-          - zip
-          - qt5-default
-          - clang-format-7
-#    - os: osx
-#      osx_image: xcode10.2 # we target latest MacOS Mojave
-#      sudo: true
-#      compiler: gcc-4.9 # Use clang instead of gcc in MacOS
-#      addons:
-#        homebrew:
-#          packages:
-#          - bison
-#          - cmake
-#          - ctags
-#          - flex
-#          - fontconfig
-#          - git
-#          - gcc@6
-#          - gcc@4.9
-#          - gawk
-#          - icarus-verilog
-#          - libxml++
-#          - qt5
+dist: bionic
+compiler: g++-8
+addons:
+  apt:
+    sources:
+    - ubuntu-toolchain-r-test # For newer GCC
+    - llvm_toolchain-trusty-7
+    packages:
+    - autoconf
+    - automake
+    - bash
+    - bison
+    - build-essential
+    - cmake
+    - ctags
+    - curl
+    - doxygen
+    - flex
+    - fontconfig
+    - g++-8
+    - gcc-8
+    - gdb
+    - git
+    - gperf
+    - iverilog
+    - libcairo2-dev
+    - libevent-dev
+    - libfontconfig1-dev
+    - liblist-moreutils-perl
+    - libncurses5-dev
+    - libx11-dev
+    - libxft-dev
+    - libxml++2.6-dev
+    - perl
+    - python
+    - python-lxml
+    - texinfo
+    - time
+    - valgrind
+    - zip
+    - qt5-default
+    - clang-format-7
+#- os: osx
+#  osx_image: xcode10.2 # we target latest MacOS Mojave
+#  sudo: true
+#  compiler: gcc-4.9 # Use clang instead of gcc in MacOS
+#  addons:
+#    homebrew:
+#      packages:
+#      - bison
+#      - cmake
+#      - ctags
+#      - flex
+#      - fontconfig
+#      - git
+#      - gcc@6
+#      - gcc@4.9
+#      - gawk
+#      - icarus-verilog
+#      - libxml++
+#      - qt5
 
-before_install:
+before_script:
   - source .travis/common.sh
-
-install:
-  - DEPS_DIR="${HOME}/deps"
-  - mkdir -p ${DEPS_DIR} && cd ${DEPS_DIR}
-  - |
-    if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then
-      CMAKE_URL="https://cmake.org/files/v3.16/cmake-3.16.3-Linux-x86_64.tar.gz"
-      mkdir -p cmake && travis_retry wget --no-clobber --no-check-certificate --quiet -O - ${CMAKE_URL} | tar --strip-components=1 -xz -C cmake
-      export PATH=${DEPS_DIR}/cmake/bin:${PATH}
-      echo ${PATH}
-    else
-      brew install cmake || brew upgrade cmake
-    fi
-  - cmake --version
-  - cd -
   - source .travis/install.sh
 
+stages:
+  - name: Test
+    if: type != cron
+
+jobs:
+  include:
+    - stage: Test
+      name: "OpenFPGA + VPR7 regression tests"
+      script:
+        - source .travis/build.sh
+        - source .travis/openfpga_vpr7_reg_test.sh
+
+    - stage: Test
+      name: "OpenFPGA + VPR8 regression tests"
+      script:
+        - source .travis/build.sh
+        - source .travis/openfpga_vpr8_reg_test.sh
+
+#after_failure:
+#  - .travis/after_failure.sh
+
+#after_success:
+#  - .travis/after_success.sh
+
 script:
-  - .travis/script.sh
-  #- .travis/regression.sh
+  - true
 
-after_failure:
-  - .travis/after_failure.sh
-
-after_success:
-  - .travis/after_success.sh
 notifications:
   slack:
     secure: L8tzicFh+EKcK21GBA2m3rQ3jmnDdqiRXIZcb0iqYlhT0V5asYvCqwlpPDUDV1wmBXqPgRJBI/jitAJlKFWu74pLTVc6FscUIDYM7S0DJfHEcufLknZx88lMmmV0IsYLQe3/s89tWoudMf1bNBo/8YWzLDffqUQ7s/rTPD9SWLppb01X0Xm158oDlA0rWETs35nuNFgJxWcSyIyIvnRNE3dHjzmBETUR9mYDsUSYlcOI44FMD8rE6emicdkqdn1zVxScobrl4Dt2bPsMfKopgIKK1x+38AuaqQa7t5F5ICnF0WfxmQ6/TcRNwIij0fDu68w/fcU8SyV+Ex5aZBKYUU7PG7ELTOq+q1geDoTlbguvFSIT4EzqErc4hbJmcUn79BKLhdjshZtGihKatntJx2faXYNYGFjwmnPFRYpqsozydztgMjzv4prZ5yoh7jhoDiGj44QcpXlQ9otM17JdfqveowMLHBYzATsxIRG93irZfXG/E3S8FvXg8mYOIEn8UK7H6i8VWL3JHlw8RbpLdNLswZOUlpEaDAeTm5tvYcw7FGH2nlZ2e5aXLxN6dTovSSRztQHbWdJTGG0N+xldBXcCiChmok4nXGReIkMc+99nZjRsiCB0R16tCNb25/p7NAVkItfVe1qRTzdnhi1hdE7LPURK4kxoFRJ6sFVuYjw=
diff --git a/.travis/build.sh b/.travis/build.sh
new file mode 100644
index 000000000..d7d2fcef9
--- /dev/null
+++ b/.travis/build.sh
@@ -0,0 +1,17 @@
+#!/bin/bash
+
+source .travis/common.sh
+set -e
+
+start_section "OpenFPGA.build" "${GREEN}Building..${NC}"
+cd ${TRAVIS_BUILD_DIR}
+mkdir build
+cd build
+
+if [[ $TRAVIS_OS_NAME == 'osx' ]]; then
+  cmake .. -DCMAKE_BUILD_TYPE=debug -DENABLE_VPR_GRAPHICS=off
+else
+  cmake .. -DCMAKE_BUILD_TYPE=debug
+fi
+ make -j16
+end_section "OpenFPGA.build"
diff --git a/.travis/install.sh b/.travis/install.sh
index 46d535342..23841212d 100755
--- a/.travis/install.sh
+++ b/.travis/install.sh
@@ -4,18 +4,19 @@ source .travis/common.sh
 set -e
 
 ## Install necessary package which is not available on Travis CI 
-#export DEPS_DIR="${HOME}/deps"
-#mkdir -p ${DEPS_DIR} && cd ${DEPS_DIR}
-## Install CMake
-#if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then
-#  export CMAKE_URL="https://cmake.org/files/v3.13/cmake-3.13.0-rc3-Linux-x86_64.tar.gz"
-#  mkdir -p cmake && travis_retry wget --no-check-certificate --quiet -O - ${CMAKE_URL} | tar --strip-components=1 -xz -C cmake
-#  export PATH=${DEPS_DIR}/cmake/bin:${PATH}
-#  echo ${PATH}
-#else
-#  brew install cmake || brew upgrade cmake
-#fi
-#  cmake --version
+export DEPS_DIR="${HOME}/deps"
+mkdir -p ${DEPS_DIR} && cd ${DEPS_DIR}
+# Install CMake
+if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then
+  export CMAKE_URL="https://cmake.org/files/v3.16/cmake-3.16.3-Linux-x86_64.tar.gz"
+  mkdir -p cmake && travis_retry wget --no-check-certificate --quiet -O - ${CMAKE_URL} | tar --strip-components=1 -xz -C cmake
+  export PATH=${DEPS_DIR}/cmake/bin:${PATH}
+  echo ${PATH}
+else
+  brew install cmake || brew upgrade cmake
+fi
+cmake --version
+cd -
 #
 ## Install latest iVerilog. Since no deb is provided, compile from source codes
 #if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then
diff --git a/.travis/openfpga_vpr7_reg_test.sh b/.travis/openfpga_vpr7_reg_test.sh
new file mode 100755
index 000000000..c04d202a4
--- /dev/null
+++ b/.travis/openfpga_vpr7_reg_test.sh
@@ -0,0 +1,30 @@
+#!/bin/bash
+set -e
+
+start_section "OpenFPGA+VPR7.TaskTun" "${GREEN}..Running_Regression..${NC}"
+cd ${TRAVIS_BUILD_DIR}
+
+###############################################
+# OpenFPGA with VPR7
+# TO BE DEPRECATED
+##############################################
+echo -e "Testing single-mode architectures";
+python3 openfpga_flow/scripts/run_fpga_task.py single_mode --debug --show_thread_logs
+#python3 openfpga_flow/scripts/run_fpga_task.py s298 
+
+echo -e "Testing multi-mode architectures";
+python3 openfpga_flow/scripts/run_fpga_task.py multi_mode --maxthreads 4 --debug --show_thread_logs
+
+echo -e "Testing compact routing techniques";
+python3 openfpga_flow/scripts/run_fpga_task.py compact_routing --debug --show_thread_logs
+
+echo -e "Testing tileable architectures";
+python3 openfpga_flow/scripts/run_fpga_task.py tileable_routing --debug --show_thread_logs
+
+echo -e "Testing Verilog generation with explicit port mapping ";
+python3 openfpga_flow/scripts/run_fpga_task.py explicit_verilog --debug --show_thread_logs
+
+echo -e "Testing Verilog generation with grid pin duplication ";
+python3 openfpga_flow/scripts/run_fpga_task.py duplicate_grid_pin --debug --show_thread_logs
+
+end_section "OpenFPGA+VPR7.TaskTun"
diff --git a/.travis/script.sh b/.travis/openfpga_vpr8_reg_test.sh
similarity index 82%
rename from .travis/script.sh
rename to .travis/openfpga_vpr8_reg_test.sh
index 907e1a3cf..046f8210f 100755
--- a/.travis/script.sh
+++ b/.travis/openfpga_vpr8_reg_test.sh
@@ -1,46 +1,9 @@
 #!/bin/bash
 
-source .travis/common.sh
 set -e
 
-start_section "OpenFPGA.build" "${GREEN}Building..${NC}"
-mkdir build
-cd build
-
-if [[ $TRAVIS_OS_NAME == 'osx' ]]; then
-  cmake .. -DCMAKE_BUILD_TYPE=debug -DENABLE_VPR_GRAPHICS=off
-else
-  cmake .. -DCMAKE_BUILD_TYPE=debug
-fi
- make -j16
-end_section "OpenFPGA.build"
-
-
 start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
-cd -
-
-###############################################
-# OpenFPGA with VPR7
-# TO BE DEPRECATED
-##############################################
-echo -e "Testing single-mode architectures";
-python3 openfpga_flow/scripts/run_fpga_task.py single_mode --debug --show_thread_logs
-#python3 openfpga_flow/scripts/run_fpga_task.py s298 
-
-echo -e "Testing multi-mode architectures";
-python3 openfpga_flow/scripts/run_fpga_task.py multi_mode --maxthreads 4 --debug --show_thread_logs
-
-echo -e "Testing compact routing techniques";
-python3 openfpga_flow/scripts/run_fpga_task.py compact_routing --debug --show_thread_logs
-
-echo -e "Testing tileable architectures";
-python3 openfpga_flow/scripts/run_fpga_task.py tileable_routing --debug --show_thread_logs
-
-echo -e "Testing Verilog generation with explicit port mapping ";
-python3 openfpga_flow/scripts/run_fpga_task.py explicit_verilog --debug --show_thread_logs
-
-echo -e "Testing Verilog generation with grid pin duplication ";
-python3 openfpga_flow/scripts/run_fpga_task.py duplicate_grid_pin --debug --show_thread_logs
+cd ${TRAVIS_BUILD_DIR}
 
 ###############################################
 # OpenFPGA Shell with VPR8
diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml
index fe7d3f1b8..14a7881ef 100644
--- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml
@@ -193,36 +193,3 @@
     <!-- End physical pb_type binding in complex block IO -->
   </pb_type_annotations>
 </openfpga_architecture>
-<openfpga_simulation_setting>
-  <clock_setting>
-    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
-    <programming frequency="100e6"/>
-  </clock_setting>
-  <simulator_option>
-    <operating_condition temperature="25"/>
-    <output_log verbose="false" captab="false"/>
-    <accuracy type="abs" value="1e-13"/>
-    <runtime fast_simulation="true"/>
-  </simulator_option>
-  <monte_carlo num_simulation_points="2"/>
-  <measurement_setting>
-    <slew>
-      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
-      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
-    </slew>
-    <delay>
-      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
-      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
-    </delay>
-  </measurement_setting>
-  <stimulus>
-    <clock>
-      <rise slew_type="abs" slew_time="20e-12" />
-      <fall slew_type="abs" slew_time="20e-12" />
-    </clock>
-    <input>
-      <rise slew_type="abs" slew_time="25e-12" />
-      <fall slew_type="abs" slew_time="25e-12" />
-    </input>
-  </stimulus>
-</openfpga_simulation_setting>
diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
index 298e0c0c0..13eb292b0 100644
--- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
@@ -193,36 +193,3 @@
     <!-- End physical pb_type binding in complex block IO -->
   </pb_type_annotations>
 </openfpga_architecture>
-<openfpga_simulation_setting>
-  <clock_setting>
-    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
-    <programming frequency="100e6"/>
-  </clock_setting>
-  <simulator_option>
-    <operating_condition temperature="25"/>
-    <output_log verbose="false" captab="false"/>
-    <accuracy type="abs" value="1e-13"/>
-    <runtime fast_simulation="true"/>
-  </simulator_option>
-  <monte_carlo num_simulation_points="2"/>
-  <measurement_setting>
-    <slew>
-      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
-      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
-    </slew>
-    <delay>
-      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
-      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
-    </delay>
-  </measurement_setting>
-  <stimulus>
-    <clock>
-      <rise slew_type="abs" slew_time="20e-12" />
-      <fall slew_type="abs" slew_time="20e-12" />
-    </clock>
-    <input>
-      <rise slew_type="abs" slew_time="25e-12" />
-      <fall slew_type="abs" slew_time="25e-12" />
-    </input>
-  </stimulus>
-</openfpga_simulation_setting>
diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml
index 677061785..13eb292b0 100644
--- a/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml
@@ -193,36 +193,3 @@
     <!-- End physical pb_type binding in complex block IO -->
   </pb_type_annotations>
 </openfpga_architecture>
-<openfpga_simulation_setting>
-  <clock_setting>
-    <operating frequency="500e6" num_cycles="10" slack="0.2"/>
-    <programming frequency="300e6"/>
-  </clock_setting>
-  <simulator_option>
-    <operating_condition temperature="25"/>
-    <output_log verbose="false" captab="false"/>
-    <accuracy type="abs" value="1e-13"/>
-    <runtime fast_simulation="true"/>
-  </simulator_option>
-  <monte_carlo num_simulation_points="2"/>
-  <measurement_setting>
-    <slew>
-      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
-      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
-    </slew>
-    <delay>
-      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
-      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
-    </delay>
-  </measurement_setting>
-  <stimulus>
-    <clock>
-      <rise slew_type="abs" slew_time="20e-12" />
-      <fall slew_type="abs" slew_time="20e-12" />
-    </clock>
-    <input>
-      <rise slew_type="abs" slew_time="25e-12" />
-      <fall slew_type="abs" slew_time="25e-12" />
-    </input>
-  </stimulus>
-</openfpga_simulation_setting>
diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml
index a0e0194b5..da2322044 100644
--- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml
@@ -194,36 +194,3 @@
     <!-- End physical pb_type binding in complex block IO -->
   </pb_type_annotations>
 </openfpga_architecture>
-<openfpga_simulation_setting>
-  <clock_setting>
-    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
-    <programming frequency="100e6"/>
-  </clock_setting>
-  <simulator_option>
-    <operating_condition temperature="25"/>
-    <output_log verbose="false" captab="false"/>
-    <accuracy type="abs" value="1e-13"/>
-    <runtime fast_simulation="true"/>
-  </simulator_option>
-  <monte_carlo num_simulation_points="2"/>
-  <measurement_setting>
-    <slew>
-      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
-      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
-    </slew>
-    <delay>
-      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
-      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
-    </delay>
-  </measurement_setting>
-  <stimulus>
-    <clock>
-      <rise slew_type="abs" slew_time="20e-12" />
-      <fall slew_type="abs" slew_time="20e-12" />
-    </clock>
-    <input>
-      <rise slew_type="abs" slew_time="25e-12" />
-      <fall slew_type="abs" slew_time="25e-12" />
-    </input>
-  </stimulus>
-</openfpga_simulation_setting>
diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml
index fc97f75c1..05b096a03 100644
--- a/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml
@@ -194,36 +194,3 @@
     <!-- End physical pb_type binding in complex block IO -->
   </pb_type_annotations>
 </openfpga_architecture>
-<openfpga_simulation_setting>
-  <clock_setting>
-    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
-    <programming frequency="100e6"/>
-  </clock_setting>
-  <simulator_option>
-    <operating_condition temperature="25"/>
-    <output_log verbose="false" captab="false"/>
-    <accuracy type="abs" value="1e-13"/>
-    <runtime fast_simulation="true"/>
-  </simulator_option>
-  <monte_carlo num_simulation_points="2"/>
-  <measurement_setting>
-    <slew>
-      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
-      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
-    </slew>
-    <delay>
-      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
-      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
-    </delay>
-  </measurement_setting>
-  <stimulus>
-    <clock>
-      <rise slew_type="abs" slew_time="20e-12" />
-      <fall slew_type="abs" slew_time="20e-12" />
-    </clock>
-    <input>
-      <rise slew_type="abs" slew_time="25e-12" />
-      <fall slew_type="abs" slew_time="25e-12" />
-    </input>
-  </stimulus>
-</openfpga_simulation_setting>
diff --git a/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml
index e6e53d9f6..9512672a9 100644
--- a/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml
@@ -193,36 +193,3 @@
     <!-- End physical pb_type binding in complex block IO -->
   </pb_type_annotations>
 </openfpga_architecture>
-<openfpga_simulation_setting>
-  <clock_setting>
-    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
-    <programming frequency="100e6"/>
-  </clock_setting>
-  <simulator_option>
-    <operating_condition temperature="25"/>
-    <output_log verbose="false" captab="false"/>
-    <accuracy type="abs" value="1e-13"/>
-    <runtime fast_simulation="true"/>
-  </simulator_option>
-  <monte_carlo num_simulation_points="2"/>
-  <measurement_setting>
-    <slew>
-      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
-      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
-    </slew>
-    <delay>
-      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
-      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
-    </delay>
-  </measurement_setting>
-  <stimulus>
-    <clock>
-      <rise slew_type="abs" slew_time="20e-12" />
-      <fall slew_type="abs" slew_time="20e-12" />
-    </clock>
-    <input>
-      <rise slew_type="abs" slew_time="25e-12" />
-      <fall slew_type="abs" slew_time="25e-12" />
-    </input>
-  </stimulus>
-</openfpga_simulation_setting>
diff --git a/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml
index b211bd040..2127c0b3c 100644
--- a/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml
@@ -194,36 +194,3 @@
     <!-- End physical pb_type binding in complex block IO -->
   </pb_type_annotations>
 </openfpga_architecture>
-<openfpga_simulation_setting>
-  <clock_setting>
-    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
-    <programming frequency="100e6"/>
-  </clock_setting>
-  <simulator_option>
-    <operating_condition temperature="25"/>
-    <output_log verbose="false" captab="false"/>
-    <accuracy type="abs" value="1e-13"/>
-    <runtime fast_simulation="true"/>
-  </simulator_option>
-  <monte_carlo num_simulation_points="2"/>
-  <measurement_setting>
-    <slew>
-      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
-      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
-    </slew>
-    <delay>
-      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
-      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
-    </delay>
-  </measurement_setting>
-  <stimulus>
-    <clock>
-      <rise slew_type="abs" slew_time="20e-12" />
-      <fall slew_type="abs" slew_time="20e-12" />
-    </clock>
-    <input>
-      <rise slew_type="abs" slew_time="25e-12" />
-      <fall slew_type="abs" slew_time="25e-12" />
-    </input>
-  </stimulus>
-</openfpga_simulation_setting>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
index 9b20ab2a2..222d0d3e6 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
@@ -224,37 +224,3 @@
     <!-- End physical pb_type binding in complex block IO -->
   </pb_type_annotations>
 </openfpga_architecture>
-<openfpga_simulation_setting>
-  <clock_setting>
-    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
-    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
-    <programming frequency="100e6"/>
-  </clock_setting>
-  <simulator_option>
-    <operating_condition temperature="25"/>
-    <output_log verbose="false" captab="false"/>
-    <accuracy type="abs" value="1e-13"/>
-    <runtime fast_simulation="true"/>
-  </simulator_option>
-  <monte_carlo num_simulation_points="2"/>
-  <measurement_setting>
-    <slew>
-      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
-      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
-    </slew>
-    <delay>
-      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
-      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
-    </delay>
-  </measurement_setting>
-  <stimulus>
-    <clock>
-      <rise slew_type="abs" slew_time="20e-12" />
-      <fall slew_type="abs" slew_time="20e-12" />
-    </clock>
-    <input>
-      <rise slew_type="abs" slew_time="25e-12" />
-      <fall slew_type="abs" slew_time="25e-12" />
-    </input>
-  </stimulus>
-</openfpga_simulation_setting>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
index 10051a9ca..be9bd0d3b 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
@@ -249,37 +249,3 @@
     <!-- End physical pb_type binding in complex block IO -->
   </pb_type_annotations>
 </openfpga_architecture>
-<openfpga_simulation_setting>
-  <clock_setting>
-    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
-    <!--operating frequency="200e6" num_cycles="auto" slack="0.2"/-->
-    <programming frequency="100e6"/>
-  </clock_setting>
-  <simulator_option>
-    <operating_condition temperature="25"/>
-    <output_log verbose="false" captab="false"/>
-    <accuracy type="abs" value="1e-13"/>
-    <runtime fast_simulation="true"/>
-  </simulator_option>
-  <monte_carlo num_simulation_points="2"/>
-  <measurement_setting>
-    <slew>
-      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
-      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
-    </slew>
-    <delay>
-      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
-      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
-    </delay>
-  </measurement_setting>
-  <stimulus>
-    <clock>
-      <rise slew_type="abs" slew_time="20e-12" />
-      <fall slew_type="abs" slew_time="20e-12" />
-    </clock>
-    <input>
-      <rise slew_type="abs" slew_time="25e-12" />
-      <fall slew_type="abs" slew_time="25e-12" />
-    </input>
-  </stimulus>
-</openfpga_simulation_setting>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
index 40a451b55..6dfb6ac71 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
@@ -266,37 +266,3 @@
     <!-- END physical pb_type binding in complex block memory -->
   </pb_type_annotations>
 </openfpga_architecture>
-<openfpga_simulation_setting>
-  <clock_setting>
-    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
-    <!--operating frequency="200e6" num_cycles="auto" slack="0.2"/-->
-    <programming frequency="100e6"/>
-  </clock_setting>
-  <simulator_option>
-    <operating_condition temperature="25"/>
-    <output_log verbose="false" captab="false"/>
-    <accuracy type="abs" value="1e-13"/>
-    <runtime fast_simulation="true"/>
-  </simulator_option>
-  <monte_carlo num_simulation_points="2"/>
-  <measurement_setting>
-    <slew>
-      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
-      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
-    </slew>
-    <delay>
-      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
-      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
-    </delay>
-  </measurement_setting>
-  <stimulus>
-    <clock>
-      <rise slew_type="abs" slew_time="20e-12" />
-      <fall slew_type="abs" slew_time="20e-12" />
-    </clock>
-    <input>
-      <rise slew_type="abs" slew_time="25e-12" />
-      <fall slew_type="abs" slew_time="25e-12" />
-    </input>
-  </stimulus>
-</openfpga_simulation_setting>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
index 9e608ead9..81dfd17ce 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
@@ -278,37 +278,3 @@
     <!-- END physical pb_type binding in complex block memory -->
   </pb_type_annotations>
 </openfpga_architecture>
-<openfpga_simulation_setting>
-  <clock_setting>
-    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
-    <!--operating frequency="200e6" num_cycles="auto" slack="0.2"/-->
-    <programming frequency="100e6"/>
-  </clock_setting>
-  <simulator_option>
-    <operating_condition temperature="25"/>
-    <output_log verbose="false" captab="false"/>
-    <accuracy type="abs" value="1e-13"/>
-    <runtime fast_simulation="true"/>
-  </simulator_option>
-  <monte_carlo num_simulation_points="2"/>
-  <measurement_setting>
-    <slew>
-      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
-      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
-    </slew>
-    <delay>
-      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
-      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
-    </delay>
-  </measurement_setting>
-  <stimulus>
-    <clock>
-      <rise slew_type="abs" slew_time="20e-12" />
-      <fall slew_type="abs" slew_time="20e-12" />
-    </clock>
-    <input>
-      <rise slew_type="abs" slew_time="25e-12" />
-      <fall slew_type="abs" slew_time="25e-12" />
-    </input>
-  </stimulus>
-</openfpga_simulation_setting>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml
index 79b82375f..9a5d94056 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml
@@ -249,37 +249,3 @@
     <!-- End physical pb_type binding in complex block IO -->
   </pb_type_annotations>
 </openfpga_architecture>
-<openfpga_simulation_setting>
-  <clock_setting>
-    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
-    <!--operating frequency="200e6" num_cycles="auto" slack="0.2"/-->
-    <programming frequency="100e6"/>
-  </clock_setting>
-  <simulator_option>
-    <operating_condition temperature="25"/>
-    <output_log verbose="false" captab="false"/>
-    <accuracy type="abs" value="1e-13"/>
-    <runtime fast_simulation="true"/>
-  </simulator_option>
-  <monte_carlo num_simulation_points="2"/>
-  <measurement_setting>
-    <slew>
-      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
-      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
-    </slew>
-    <delay>
-      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
-      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
-    </delay>
-  </measurement_setting>
-  <stimulus>
-    <clock>
-      <rise slew_type="abs" slew_time="20e-12" />
-      <fall slew_type="abs" slew_time="20e-12" />
-    </clock>
-    <input>
-      <rise slew_type="abs" slew_time="25e-12" />
-      <fall slew_type="abs" slew_time="25e-12" />
-    </input>
-  </stimulus>
-</openfpga_simulation_setting>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml
index 33cfa9e61..d2cb8a163 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml
@@ -252,37 +252,3 @@
     <!-- End physical pb_type binding in complex block IO -->
   </pb_type_annotations>
 </openfpga_architecture>
-<openfpga_simulation_setting>
-  <clock_setting>
-    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
-    <!--operating frequency="200e6" num_cycles="auto" slack="0.2"/-->
-    <programming frequency="100e6"/>
-  </clock_setting>
-  <simulator_option>
-    <operating_condition temperature="25"/>
-    <output_log verbose="false" captab="false"/>
-    <accuracy type="abs" value="1e-13"/>
-    <runtime fast_simulation="true"/>
-  </simulator_option>
-  <monte_carlo num_simulation_points="2"/>
-  <measurement_setting>
-    <slew>
-      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
-      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
-    </slew>
-    <delay>
-      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
-      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
-    </delay>
-  </measurement_setting>
-  <stimulus>
-    <clock>
-      <rise slew_type="abs" slew_time="20e-12" />
-      <fall slew_type="abs" slew_time="20e-12" />
-    </clock>
-    <input>
-      <rise slew_type="abs" slew_time="25e-12" />
-      <fall slew_type="abs" slew_time="25e-12" />
-    </input>
-  </stimulus>
-</openfpga_simulation_setting>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml
index 460c8743e..129e11f71 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml
@@ -258,37 +258,3 @@
     <!-- End physical pb_type binding in complex block IO -->
   </pb_type_annotations>
 </openfpga_architecture>
-<openfpga_simulation_setting>
-  <clock_setting>
-    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
-    <!--operating frequency="200e6" num_cycles="auto" slack="0.2"/-->
-    <programming frequency="100e6"/>
-  </clock_setting>
-  <simulator_option>
-    <operating_condition temperature="25"/>
-    <output_log verbose="false" captab="false"/>
-    <accuracy type="abs" value="1e-13"/>
-    <runtime fast_simulation="true"/>
-  </simulator_option>
-  <monte_carlo num_simulation_points="2"/>
-  <measurement_setting>
-    <slew>
-      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
-      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
-    </slew>
-    <delay>
-      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
-      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
-    </delay>
-  </measurement_setting>
-  <stimulus>
-    <clock>
-      <rise slew_type="abs" slew_time="20e-12" />
-      <fall slew_type="abs" slew_time="20e-12" />
-    </clock>
-    <input>
-      <rise slew_type="abs" slew_time="25e-12" />
-      <fall slew_type="abs" slew_time="25e-12" />
-    </input>
-  </stimulus>
-</openfpga_simulation_setting>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml
index 4bb4a24a2..f22ec1fc9 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml
@@ -253,37 +253,3 @@
     <!-- End physical pb_type binding in complex block CLB -->
   </pb_type_annotations>
 </openfpga_architecture>
-<openfpga_simulation_setting>
-  <clock_setting>
-    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
-    <!--operating frequency="200e6" num_cycles="auto" slack="0.2"/-->
-    <programming frequency="100e6"/>
-  </clock_setting>
-  <simulator_option>
-    <operating_condition temperature="25"/>
-    <output_log verbose="false" captab="false"/>
-    <accuracy type="abs" value="1e-13"/>
-    <runtime fast_simulation="true"/>
-  </simulator_option>
-  <monte_carlo num_simulation_points="2"/>
-  <measurement_setting>
-    <slew>
-      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
-      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
-    </slew>
-    <delay>
-      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
-      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
-    </delay>
-  </measurement_setting>
-  <stimulus>
-    <clock>
-      <rise slew_type="abs" slew_time="20e-12" />
-      <fall slew_type="abs" slew_time="20e-12" />
-    </clock>
-    <input>
-      <rise slew_type="abs" slew_time="25e-12" />
-      <fall slew_type="abs" slew_time="25e-12" />
-    </input>
-  </stimulus>
-</openfpga_simulation_setting>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml
index e1dde16b6..650e30a6b 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml
@@ -337,37 +337,3 @@
 
   </pb_type_annotations>
 </openfpga_architecture>
-<openfpga_simulation_setting>
-  <clock_setting>
-    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
-    <!--operating frequency="200e6" num_cycles="auto" slack="0.2"/-->
-    <programming frequency="100e6"/>
-  </clock_setting>
-  <simulator_option>
-    <operating_condition temperature="25"/>
-    <output_log verbose="false" captab="false"/>
-    <accuracy type="abs" value="1e-13"/>
-    <runtime fast_simulation="true"/>
-  </simulator_option>
-  <monte_carlo num_simulation_points="2"/>
-  <measurement_setting>
-    <slew>
-      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
-      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
-    </slew>
-    <delay>
-      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
-      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
-    </delay>
-  </measurement_setting>
-  <stimulus>
-    <clock>
-      <rise slew_type="abs" slew_time="20e-12" />
-      <fall slew_type="abs" slew_time="20e-12" />
-    </clock>
-    <input>
-      <rise slew_type="abs" slew_time="25e-12" />
-      <fall slew_type="abs" slew_time="25e-12" />
-    </input>
-  </stimulus>
-</openfpga_simulation_setting>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml
index ebad2d203..2d6a765d0 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml
@@ -224,37 +224,3 @@
     <!-- End physical pb_type binding in complex block IO -->
   </pb_type_annotations>
 </openfpga_architecture>
-<openfpga_simulation_setting>
-  <clock_setting>
-    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
-    <!--operating frequency="200e6" num_cycles="auto" slack="0.2"/-->
-    <programming frequency="100e6"/>
-  </clock_setting>
-  <simulator_option>
-    <operating_condition temperature="25"/>
-    <output_log verbose="false" captab="false"/>
-    <accuracy type="abs" value="1e-13"/>
-    <runtime fast_simulation="true"/>
-  </simulator_option>
-  <monte_carlo num_simulation_points="2"/>
-  <measurement_setting>
-    <slew>
-      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
-      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
-    </slew>
-    <delay>
-      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
-      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
-    </delay>
-  </measurement_setting>
-  <stimulus>
-    <clock>
-      <rise slew_type="abs" slew_time="20e-12" />
-      <fall slew_type="abs" slew_time="20e-12" />
-    </clock>
-    <input>
-      <rise slew_type="abs" slew_time="25e-12" />
-      <fall slew_type="abs" slew_time="25e-12" />
-    </input>
-  </stimulus>
-</openfpga_simulation_setting>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml
index b32deb8a9..b351666a7 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml
@@ -224,37 +224,3 @@
     <!-- End physical pb_type binding in complex block IO -->
   </pb_type_annotations>
 </openfpga_architecture>
-<openfpga_simulation_setting>
-  <clock_setting>
-    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
-    <!--operating frequency="200e6" num_cycles="auto" slack="0.2"/-->
-    <programming frequency="100e6"/>
-  </clock_setting>
-  <simulator_option>
-    <operating_condition temperature="25"/>
-    <output_log verbose="false" captab="false"/>
-    <accuracy type="abs" value="1e-13"/>
-    <runtime fast_simulation="true"/>
-  </simulator_option>
-  <monte_carlo num_simulation_points="2"/>
-  <measurement_setting>
-    <slew>
-      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
-      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
-    </slew>
-    <delay>
-      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
-      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
-    </delay>
-  </measurement_setting>
-  <stimulus>
-    <clock>
-      <rise slew_type="abs" slew_time="20e-12" />
-      <fall slew_type="abs" slew_time="20e-12" />
-    </clock>
-    <input>
-      <rise slew_type="abs" slew_time="25e-12" />
-      <fall slew_type="abs" slew_time="25e-12" />
-    </input>
-  </stimulus>
-</openfpga_simulation_setting>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml
index c980065bb..94c8f9fb8 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml
@@ -228,37 +228,3 @@
     <!-- End physical pb_type binding in complex block IO -->
   </pb_type_annotations>
 </openfpga_architecture>
-<openfpga_simulation_setting>
-  <clock_setting>
-    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
-    <!--operating frequency="200e6" num_cycles="auto" slack="0.2"/-->
-    <programming frequency="100e6"/>
-  </clock_setting>
-  <simulator_option>
-    <operating_condition temperature="25"/>
-    <output_log verbose="false" captab="false"/>
-    <accuracy type="abs" value="1e-13"/>
-    <runtime fast_simulation="true"/>
-  </simulator_option>
-  <monte_carlo num_simulation_points="2"/>
-  <measurement_setting>
-    <slew>
-      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
-      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
-    </slew>
-    <delay>
-      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
-      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
-    </delay>
-  </measurement_setting>
-  <stimulus>
-    <clock>
-      <rise slew_type="abs" slew_time="20e-12" />
-      <fall slew_type="abs" slew_time="20e-12" />
-    </clock>
-    <input>
-      <rise slew_type="abs" slew_time="25e-12" />
-      <fall slew_type="abs" slew_time="25e-12" />
-    </input>
-  </stimulus>
-</openfpga_simulation_setting>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml
index 2b42cdced..794f10d4f 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml
@@ -216,37 +216,3 @@
     <!-- End physical pb_type binding in complex block IO -->
   </pb_type_annotations>
 </openfpga_architecture>
-<openfpga_simulation_setting>
-  <clock_setting>
-    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
-    <!--operating frequency="200e6" num_cycles="auto" slack="0.2"/-->
-    <programming frequency="100e6"/>
-  </clock_setting>
-  <simulator_option>
-    <operating_condition temperature="25"/>
-    <output_log verbose="false" captab="false"/>
-    <accuracy type="abs" value="1e-13"/>
-    <runtime fast_simulation="true"/>
-  </simulator_option>
-  <monte_carlo num_simulation_points="2"/>
-  <measurement_setting>
-    <slew>
-      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
-      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
-    </slew>
-    <delay>
-      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
-      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
-    </delay>
-  </measurement_setting>
-  <stimulus>
-    <clock>
-      <rise slew_type="abs" slew_time="20e-12" />
-      <fall slew_type="abs" slew_time="20e-12" />
-    </clock>
-    <input>
-      <rise slew_type="abs" slew_time="25e-12" />
-      <fall slew_type="abs" slew_time="25e-12" />
-    </input>
-  </stimulus>
-</openfpga_simulation_setting>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml
index c26c30f31..e9081fa86 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml
@@ -215,37 +215,3 @@
     <!-- End physical pb_type binding in complex block IO -->
   </pb_type_annotations>
 </openfpga_architecture>
-<openfpga_simulation_setting>
-  <clock_setting>
-    <operating frequency="auto" num_cycles="auto" slack="0.2"/>
-    <!--operating frequency="200e6" num_cycles="auto" slack="0.2"/-->
-    <programming frequency="100e6"/>
-  </clock_setting>
-  <simulator_option>
-    <operating_condition temperature="25"/>
-    <output_log verbose="false" captab="false"/>
-    <accuracy type="abs" value="1e-13"/>
-    <runtime fast_simulation="true"/>
-  </simulator_option>
-  <monte_carlo num_simulation_points="2"/>
-  <measurement_setting>
-    <slew>
-      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
-      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
-    </slew>
-    <delay>
-      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
-      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
-    </delay>
-  </measurement_setting>
-  <stimulus>
-    <clock>
-      <rise slew_type="abs" slew_time="20e-12" />
-      <fall slew_type="abs" slew_time="20e-12" />
-    </clock>
-    <input>
-      <rise slew_type="abs" slew_time="25e-12" />
-      <fall slew_type="abs" slew_time="25e-12" />
-    </input>
-  </stimulus>
-</openfpga_simulation_setting>

From aaa52b6e89241645feec6d4cb35ea708e73d0d1a Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 11 Jun 2020 18:33:47 -0600
Subject: [PATCH 645/645] start using multiple jobs in travis CI

---
 .travis/build.sh | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/.travis/build.sh b/.travis/build.sh
index d7d2fcef9..254133177 100644
--- a/.travis/build.sh
+++ b/.travis/build.sh
@@ -13,5 +13,9 @@ if [[ $TRAVIS_OS_NAME == 'osx' ]]; then
 else
   cmake .. -DCMAKE_BUILD_TYPE=debug
 fi
- make -j16
+make -j16
+
+# Return to upper directory
+cd ${TRAVIS_BUILD_DIR}
+
 end_section "OpenFPGA.build"