From 616d7706c9d774940e5f55193f0c17d0552257da Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Mon, 19 Aug 2019 19:05:08 -0600 Subject: [PATCH] Added list of intermidiate files filename --- .../misc/fpgaflow_default_tool_path.conf | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/openfpga_flow/misc/fpgaflow_default_tool_path.conf b/openfpga_flow/misc/fpgaflow_default_tool_path.conf index cf4d3e289..78e1dc46a 100644 --- a/openfpga_flow/misc/fpgaflow_default_tool_path.conf +++ b/openfpga_flow/misc/fpgaflow_default_tool_path.conf @@ -44,5 +44,32 @@ lut6_power="^\s+lut6\s+([0-9]+)", str ff_power="^\s+ff\s+([0-9]+)", str [INTERMIDIATE_FILE_PREFIX] +# Yosys files +yosys_out_blif=${PATH:TOP_MODULE}_yosys_out.blif +yosys_output=yosys_output.txt +# ACE2 and intermidiate file +activity_file=${PATH:TOP_MODULE}_ace_out.act +ace_output_blif=${PATH:TOP_MODULE}_ace_out.blif +corrected_format_blif=${PATH:TOP_MODULE}.blif +blackbox_blif=${PATH:TOP_MODULE}_bb.blif + +# VPR Files +min_chann_vpr_output=${PATH:TOP_MODULE}_min_chan_width_vpr.txt +reroute_chan_vpr_output=${PATH:TOP_MODULE}_reroute_vpr.txt +fixed_chan_vpr_output=${PATH:TOP_MODULE}_fr_chan_width.txt +vpr_stat_parse_fn=vpr_stat.txt +vpr_power_stat_parse_fn=vpr_power_stat.txt +vpr_net_file=${PATH:TOP_MODULE}_vpr.net +vpr_place_file=${PATH:TOP_MODULE}_vpr.place +vpr_route_file=${PATH:TOP_MODULE}_vpr.route + +#Iverilog verification file +iverilog_output=iverilog_output.txt +vvp_output=vvp_sim_output.txt + +[CMD_ARGUMENT_DEPENDANCY] +vpr_fpga_verilog=vpr_fpga_verilog_dir +vpr_fpga_verilog_dir=vpr_fpga_verilog +arg1=arg2,arg3,arg4|arg5