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[Test] Bug fix in the 5clock test case

This commit is contained in:
tangxifan 2021-02-22 11:46:23 -07:00
parent 71e0026a50
commit 60dc194d8f
3 changed files with 14 additions and 9 deletions
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9
openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/pin_constraints.xml
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@ -3,9 +3,10 @@
- the clk0 signal to the clk[0] port of the FPGA fabric - the clk0 signal to the clk[0] port of the FPGA fabric
- the clk1 signal to the clk[1] port of the FPGA fabric - the clk1 signal to the clk[1] port of the FPGA fabric
--> -->
<set_io pin="clk[0]" net="clk0"/> <set_io pin="clk[0]" net="clk1"/>
<set_io pin="clk[1]" net="clk1"/> <set_io pin="clk[1]" net="clk2"/>
<set_io pin="clk[2]" net="OPEN"/> <set_io pin="clk[2]" net="clk3"/>
<set_io pin="clk[3]" net="OPEN"/> <set_io pin="clk[3]" net="clk4"/>
<set_io pin="clk[4]" net="clk5"/>
</pin_constraints> </pin_constraints>

12
openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/repack_pin_constraints.xml
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@ -6,9 +6,13 @@
- the clk[2] port of all the clb tiles available in the FPGA fabric - the clk[2] port of all the clb tiles available in the FPGA fabric
- the clk[3] port of all the clb tiles available in the FPGA fabric - the clk[3] port of all the clb tiles available in the FPGA fabric
--> -->
<pin_constraint pb_type="clb" pin="clk[0]" net="clk0"/> <pin_constraint pb_type="clb" pin="clk[0]" net="clk1"/>
<pin_constraint pb_type="clb" pin="clk[1]" net="clk1"/> <pin_constraint pb_type="clb" pin="clk[1]" net="clk2"/>
<pin_constraint pb_type="clb" pin="clk[2]" net="OPEN"/> <pin_constraint pb_type="clb" pin="clk[2]" net="clk3"/>
<pin_constraint pb_type="clb" pin="clk[3]" net="OPEN"/> <pin_constraint pb_type="clb" pin="clk[3]" net="clk4"/>
<pin_constraint pb_type="clb" pin="clk[4]" net="clk5"/>
<pin_constraint pb_type="clb" pin="clk[5]" net="OPEN"/>
<pin_constraint pb_type="clb" pin="clk[6]" net="OPEN"/>
<pin_constraint pb_type="clb" pin="clk[7]" net="OPEN"/>
</repack_design_constraints> </repack_design_constraints>

2
openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf
View File

@ -25,7 +25,7 @@ fpga_flow=yosys_vpr
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_bitstream_global_tile_multiclock_example_script.openfpga openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_bitstream_global_tile_multiclock_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTile8Clk_cc_openfpga.xml openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTile8Clk_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_8clock_sim_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_8clock_sim_openfpga.xml
openfpga_repack_design_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/counter5clock_test/config/repack_pin_constraints.xml openfpga_repack_design_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/repack_pin_constraints.xml
openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/pin_constraints.xml openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/pin_constraints.xml
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