Merge branch 'refactoring' into dev
This commit is contained in:
tangxifan
commit
60d56cbdf1
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@ -66,4 +66,7 @@ void write_xml_openfpga_arch(const char* fname,
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/* Write the simulation */
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write_xml_simulation_setting(fp, fname, openfpga_arch.sim_setting);
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/* Close the file stream */
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fp.close();
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}
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@ -0,0 +1,254 @@
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/********************************************************************
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* This file includes functions to detect and correct any naming
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* in the users' BLIF netlist that violates the syntax of OpenFPGA
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* fabric generator, i.e., Verilog generator and SPICE generator
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*******************************************************************/
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#include <string>
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#include <fstream>
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/* Headers from vtrutil library */
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#include "vtr_time.h"
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#include "vtr_assert.h"
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#include "vtr_log.h"
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/* Headers from archopenfpga library */
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#include "write_xml_utils.h"
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/* Headers from openfpgautil library */
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#include "openfpga_digest.h"
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#include "check_netlist_naming_conflict.h"
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/* Include global variables of VPR */
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#include "globals.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* This function aims to check if the name contains any of the
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* sensitive characters in the list
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* Return a string of sensitive characters which are contained
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* in the name
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*******************************************************************/
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static
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std::string name_contain_sensitive_chars(const std::string& name,
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const std::string& sensitive_chars) {
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std::string violation;
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for (const char& sensitive_char : sensitive_chars) {
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/* Return true since we find a characters */
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if (std::string::npos != name.find(sensitive_char)) {
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violation.push_back(sensitive_char);
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}
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}
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return violation;
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}
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/********************************************************************
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* This function aims to fix up a name that contains any of the
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* sensitive characters in the list
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* Return a string the fixed name
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*******************************************************************/
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static
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std::string fix_name_contain_sensitive_chars(const std::string& name,
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const std::string& sensitive_chars,
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const std::string& fix_chars) {
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std::string fixed_name = name;
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VTR_ASSERT(sensitive_chars.length() == fix_chars.length());
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for (size_t ichar = 0; ichar < sensitive_chars.length(); ++ichar) {
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/* Keep fixing the characters until we cannot find anymore */
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std::string::size_type pos = 0u;
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while (std::string::npos != (pos = fixed_name.find(sensitive_chars[ichar], pos))) {
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fixed_name.replace(pos, 1, std::string(1, fix_chars[ichar]));
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pos += 1;
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}
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}
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return fixed_name;
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}
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/********************************************************************
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* Detect and report any naming conflict by checking a list of
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* sensitive characters
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* - Iterate over all the blocks and see if any block name contain
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* any sensitive character
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* - Iterate over all the nets and see if any net name contain
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* any sensitive character
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*******************************************************************/
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static
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size_t detect_netlist_naming_conflict(const AtomNetlist& atom_netlist,
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const std::string& sensitive_chars) {
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size_t num_conflicts = 0;
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/* Walk through blocks in the netlist */
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for (const auto& block : atom_netlist.blocks()) {
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const std::string& block_name = atom_netlist.block_name(block);
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const std::string& violation = name_contain_sensitive_chars(block_name, sensitive_chars);
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if (false == violation.empty()) {
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VTR_LOG("Block '%s' contains illegal characters '%s'\n",
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block_name.c_str(), violation.c_str());
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num_conflicts++;
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}
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}
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/* Walk through nets in the netlist */
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for (const auto& net : atom_netlist.nets()) {
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const std::string& net_name = atom_netlist.net_name(net);
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const std::string& violation = name_contain_sensitive_chars(net_name, sensitive_chars);
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if (false == violation.empty()) {
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VTR_LOG("Net '%s' contains illegal characters '%s'\n",
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net_name.c_str(), violation.c_str());
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num_conflicts++;
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}
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}
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return num_conflicts;
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}
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/********************************************************************
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* Correct and report any naming conflict by checking a list of
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* sensitive characters
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* - Iterate over all the blocks and correct any block name that contains
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* any sensitive character
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* - Iterate over all the nets and correct any net name that contains
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* any sensitive character
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*******************************************************************/
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static
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void fix_netlist_naming_conflict(const AtomNetlist& atom_netlist,
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const std::string& sensitive_chars,
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const std::string& fix_chars,
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VprNetlistAnnotation& vpr_netlist_annotation) {
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size_t num_fixes = 0;
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/* Walk through blocks in the netlist */
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for (const auto& block : atom_netlist.blocks()) {
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const std::string& block_name = atom_netlist.block_name(block);
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const std::string& violation = name_contain_sensitive_chars(block_name, sensitive_chars);
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if (false == violation.empty()) {
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/* Apply fix-up here */
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vpr_netlist_annotation.rename_block(block, fix_name_contain_sensitive_chars(block_name, sensitive_chars, fix_chars));
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num_fixes++;
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}
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}
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/* Walk through nets in the netlist */
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for (const auto& net : atom_netlist.nets()) {
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const std::string& net_name = atom_netlist.net_name(net);
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const std::string& violation = name_contain_sensitive_chars(net_name, sensitive_chars);
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if (false == violation.empty()) {
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/* Apply fix-up here */
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vpr_netlist_annotation.rename_net(net, fix_name_contain_sensitive_chars(net_name, sensitive_chars, fix_chars));
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num_fixes++;
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}
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}
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if (0 < num_fixes) {
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VTR_LOG("Fixed %ld naming conflicts in the netlist.\n",
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num_fixes);
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}
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}
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/********************************************************************
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* Report all the fix-up in the naming of netlist components,
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* i.e., blocks, nets
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*******************************************************************/
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static
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void print_netlist_naming_fix_report(const std::string& fname,
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const AtomNetlist& atom_netlist,
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const VprNetlistAnnotation& vpr_netlist_annotation) {
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/* Create a file handler */
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std::fstream fp;
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/* Open the file stream */
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fp.open(fname, std::fstream::out | std::fstream::trunc);
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/* Validate the file stream */
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openfpga::check_file_stream(fname.c_str(), fp);
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fp << "<!-- Netlist naming fix-up report --> " << "\n";
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fp << "<netlist>" << "\n";
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fp << "\t" << "<blocks>" << "\n";
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for (const auto& block : atom_netlist.blocks()) {
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const std::string& block_name = atom_netlist.block_name(block);
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if (false == vpr_netlist_annotation.is_block_renamed(block)) {
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continue;
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}
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fp << "\t\t" << "<block";
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write_xml_attribute(fp, "previous", block_name.c_str());
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write_xml_attribute(fp, "current", vpr_netlist_annotation.block_name(block).c_str());
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fp << "/>" << "\n";
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}
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fp << "\t" << "</blocks>" << "\n";
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fp << "\t" << "<nets>" << "\n";
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for (const auto& net : atom_netlist.nets()) {
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const std::string& net_name = atom_netlist.net_name(net);
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if (false == vpr_netlist_annotation.is_net_renamed(net)) {
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continue;
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}
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fp << "\t\t" << "<net";
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write_xml_attribute(fp, "previous", net_name.c_str());
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write_xml_attribute(fp, "current", vpr_netlist_annotation.net_name(net).c_str());
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fp << "/>" << "\n";
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}
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fp << "\t" << "</nets>" << "\n";
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fp << "</netlist>" << "\n";
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/* Close the file stream */
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fp.close();
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}
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/********************************************************************
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* Top-level function to detect and correct any naming
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* in the users' BLIF netlist that violates the syntax of OpenFPGA
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* fabric generator, i.e., Verilog generator and SPICE generator
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*******************************************************************/
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void check_netlist_naming_conflict(OpenfpgaContext& openfpga_context,
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const Command& cmd, const CommandContext& cmd_context) {
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vtr::ScopedStartFinishTimer timer("Check naming violations of netlist blocks and nets");
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/* By default, we replace all the illegal characters with '_' */
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const std::string& sensitive_chars(".,:;\'\"+-<>()[]{}!@#$%^&*~`?/");
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const std::string& fix_chars("____________________________");
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CommandOptionId opt_fix = cmd.option("fix");
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/* Do the main job first: detect any naming in the BLIF netlist that violates the syntax */
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if (false == cmd_context.option_enable(cmd, opt_fix)) {
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size_t num_conflicts = detect_netlist_naming_conflict(g_vpr_ctx.atom().nlist, sensitive_chars);
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VTR_LOGV_ERROR((0 < num_conflicts && (false == cmd_context.option_enable(cmd, opt_fix))),
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"Found %ld naming conflicts in the netlist. Please correct so as to use any fabric generators.\n",
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num_conflicts);
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VTR_LOGV(0 == num_conflicts,
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"Check naming conflicts in the netlist passed.\n");
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return;
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}
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/* If the auto correction is enabled, we apply a fix */
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if (true == cmd_context.option_enable(cmd, opt_fix)) {
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fix_netlist_naming_conflict(g_vpr_ctx.atom().nlist, sensitive_chars,
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fix_chars, openfpga_context.mutable_vpr_netlist_annotation());
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CommandOptionId opt_report = cmd.option("report");
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if (true == cmd_context.option_enable(cmd, opt_report)) {
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print_netlist_naming_fix_report(cmd_context.option_value(cmd, opt_report),
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g_vpr_ctx.atom().nlist,
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openfpga_context.vpr_netlist_annotation());
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VTR_LOG("Naming fix-up report is generated to file '%s'\n",
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cmd_context.option_value(cmd, opt_report).c_str());
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}
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}
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}
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} /* end namespace openfpga */
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@ -0,0 +1,23 @@
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#ifndef CHECK_NETLIST_NAMING_CONFLICT_H
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#define CHECK_NETLIST_NAMING_CONFLICT_H
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/********************************************************************
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* Include header files that are required by function declaration
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*******************************************************************/
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#include "command.h"
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#include "command_context.h"
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#include "openfpga_context.h"
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/********************************************************************
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* Function declaration
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*******************************************************************/
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/* begin namespace openfpga */
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namespace openfpga {
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void check_netlist_naming_conflict(OpenfpgaContext& openfpga_context,
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const Command& cmd, const CommandContext& cmd_context);
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} /* end namespace openfpga */
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#endif
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@ -3,6 +3,7 @@
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#include "vpr_context.h"
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#include "openfpga_arch.h"
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#include "vpr_netlist_annotation.h"
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#include "vpr_pb_type_annotation.h"
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/********************************************************************
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@ -36,14 +37,18 @@ class OpenfpgaContext : public Context {
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public: /* Public accessors */
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const openfpga::Arch& arch() const { return arch_; }
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const openfpga::VprPbTypeAnnotation& vpr_pb_type_annotation() const { return vpr_pb_type_annotation_; }
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const openfpga::VprNetlistAnnotation& vpr_netlist_annotation() const { return vpr_netlist_annotation_; }
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public: /* Public mutators */
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openfpga::Arch& mutable_arch() { return arch_; }
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openfpga::VprPbTypeAnnotation& mutable_vpr_pb_type_annotation() { return vpr_pb_type_annotation_; }
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openfpga::VprNetlistAnnotation& mutable_vpr_netlist_annotation() { return vpr_netlist_annotation_; }
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private: /* Internal data */
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/* Data structure to store information from read_openfpga_arch library */
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openfpga::Arch arch_;
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/* Annotation to pb_type of VPR */
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openfpga::VprPbTypeAnnotation vpr_pb_type_annotation_;
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/* Naming fix to netlist */
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openfpga::VprNetlistAnnotation vpr_netlist_annotation_;
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};
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#endif
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|
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@ -5,16 +5,22 @@
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*******************************************************************/
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#include "openfpga_read_arch.h"
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#include "openfpga_link_arch.h"
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#include "check_netlist_naming_conflict.h"
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#include "openfpga_setup_command.h"
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/* begin namespace openfpga */
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namespace openfpga {
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void add_openfpga_setup_commands(openfpga::Shell<OpenfpgaContext>& shell) {
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/* Get the unique id of 'vpr' command which is to be used in creating the dependency graph */
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const ShellCommandId& shell_cmd_vpr_id = shell.command(std::string("vpr"));
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/* Add a new class of commands */
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ShellCommandClassId openfpga_setup_cmd_class = shell.add_command_class("OpenFPGA setup");
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/* Command 'read_openfpga_arch' */
|
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/********************************
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* Command 'read_openfpga_arch'
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*/
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Command shell_cmd_read_arch("read_openfpga_arch");
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/* Add an option '--file' in short '-f'*/
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CommandOptionId read_arch_opt_file = shell_cmd_read_arch.add_option("file", true, "file path to the architecture XML");
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|
|
@ -26,7 +32,9 @@ void add_openfpga_setup_commands(openfpga::Shell<OpenfpgaContext>& shell) {
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shell.set_command_class(shell_cmd_read_arch_id, openfpga_setup_cmd_class);
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shell.set_command_execute_function(shell_cmd_read_arch_id, read_arch);
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/* Command 'write_openfpga_arch' */
|
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/********************************
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* Command 'write_openfpga_arch'
|
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*/
|
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Command shell_cmd_write_arch("write_openfpga_arch");
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/* Add an option '--file' in short '-f'*/
|
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CommandOptionId write_arch_opt_file = shell_cmd_write_arch.add_option("file", true, "file path to the architecture XML");
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|
|
@ -40,7 +48,9 @@ void add_openfpga_setup_commands(openfpga::Shell<OpenfpgaContext>& shell) {
|
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/* The 'write_openfpga_arch' command should NOT be executed before 'read_openfpga_arch' */
|
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shell.set_command_dependency(shell_cmd_write_arch_id, std::vector<ShellCommandId>(1, shell_cmd_read_arch_id));
|
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|
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/* Command 'link_openfpga_arch' */
|
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/********************************
|
||||
* Command 'link_openfpga_arch'
|
||||
*/
|
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Command shell_cmd_link_openfpga_arch("link_openfpga_arch");
|
||||
|
||||
/* Add command 'link_openfpga_arch' to the Shell */
|
||||
|
|
@ -48,12 +58,28 @@ void add_openfpga_setup_commands(openfpga::Shell<OpenfpgaContext>& shell) {
|
|||
shell.set_command_class(shell_cmd_link_openfpga_arch_id, openfpga_setup_cmd_class);
|
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shell.set_command_execute_function(shell_cmd_link_openfpga_arch_id, link_arch);
|
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/* The 'link_openfpga_arch' command should NOT be executed before 'read_openfpga_arch' and 'vpr' */
|
||||
const ShellCommandId& shell_cmd_vpr_id = shell.command(std::string("vpr"));
|
||||
std::vector<ShellCommandId> cmd_dependency_link_openfpga_arch;
|
||||
cmd_dependency_link_openfpga_arch.push_back(shell_cmd_read_arch_id);
|
||||
cmd_dependency_link_openfpga_arch.push_back(shell_cmd_vpr_id);
|
||||
shell.set_command_dependency(shell_cmd_link_openfpga_arch_id, cmd_dependency_link_openfpga_arch);
|
||||
|
||||
/*******************************************
|
||||
* Command 'check_netlist_naming_conflict'
|
||||
*/
|
||||
Command shell_cmd_check_netlist_naming_conflict("check_netlist_naming_conflict");
|
||||
/* Add an option '--correction' */
|
||||
shell_cmd_check_netlist_naming_conflict.add_option("fix", false, "Apply correction to any conflicts found");
|
||||
/* Add an option '--report' */
|
||||
CommandOptionId check_netlist_opt_rpt = shell_cmd_check_netlist_naming_conflict.add_option("report", false, "Output a report file about what any correction applied");
|
||||
shell_cmd_check_netlist_naming_conflict.set_option_require_value(check_netlist_opt_rpt, openfpga::OPT_STRING);
|
||||
|
||||
/* Add command 'check_netlist_naming_conflict' to the Shell */
|
||||
ShellCommandId shell_cmd_check_netlist_naming_conflict_id = shell.add_command(shell_cmd_check_netlist_naming_conflict, "Check any block/net naming in users' BLIF netlist violates the syntax of fabric generator");
|
||||
shell.set_command_class(shell_cmd_check_netlist_naming_conflict_id, openfpga_setup_cmd_class);
|
||||
shell.set_command_execute_function(shell_cmd_check_netlist_naming_conflict_id, check_netlist_naming_conflict);
|
||||
/* The 'link_openfpga_arch' command should NOT be executed before 'read_openfpga_arch' and 'vpr' */
|
||||
std::vector<ShellCommandId> cmd_dependency_check_netlist_naming_conflict(1, shell_cmd_vpr_id);
|
||||
shell.set_command_dependency(shell_cmd_link_openfpga_arch_id, cmd_dependency_check_netlist_naming_conflict);
|
||||
}
|
||||
|
||||
} /* end namespace openfpga */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,68 @@
|
|||
/************************************************************************
|
||||
* Member functions for class VprNetlistAnnotation
|
||||
***********************************************************************/
|
||||
#include "vtr_log.h"
|
||||
#include "vtr_assert.h"
|
||||
#include "vpr_netlist_annotation.h"
|
||||
|
||||
/* namespace openfpga begins */
|
||||
namespace openfpga {
|
||||
|
||||
/************************************************************************
|
||||
* Constructors
|
||||
***********************************************************************/
|
||||
VprNetlistAnnotation::VprNetlistAnnotation() {
|
||||
return;
|
||||
}
|
||||
|
||||
/************************************************************************
|
||||
* Public accessors
|
||||
***********************************************************************/
|
||||
bool VprNetlistAnnotation::is_block_renamed(const AtomBlockId& block) const {
|
||||
/* Ensure that the pb_type is in the list */
|
||||
std::map<AtomBlockId, std::string>::const_iterator it = block_names_.find(block);
|
||||
return it != block_names_.end();
|
||||
}
|
||||
|
||||
std::string VprNetlistAnnotation::block_name(const AtomBlockId& block) const {
|
||||
VTR_ASSERT(true == is_block_renamed(block));
|
||||
return block_names_.at(block);
|
||||
}
|
||||
|
||||
bool VprNetlistAnnotation::is_net_renamed(const AtomNetId& net) const {
|
||||
/* Ensure that the pb_type is in the list */
|
||||
std::map<AtomNetId, std::string>::const_iterator it = net_names_.find(net);
|
||||
return it != net_names_.end();
|
||||
}
|
||||
|
||||
std::string VprNetlistAnnotation::net_name(const AtomNetId& net) const {
|
||||
VTR_ASSERT(true == is_net_renamed(net));
|
||||
return net_names_.at(net);
|
||||
}
|
||||
|
||||
/************************************************************************
|
||||
* Public mutators
|
||||
***********************************************************************/
|
||||
void VprNetlistAnnotation::rename_block(const AtomBlockId& block, const std::string& name) {
|
||||
/* Warn any override attempt */
|
||||
std::map<AtomBlockId, std::string>::const_iterator it = block_names_.find(block);
|
||||
if (it != block_names_.end()) {
|
||||
VTR_LOG_WARN("Override the block with name '%s' in netlist annotation!\n",
|
||||
name.c_str());
|
||||
}
|
||||
|
||||
block_names_[block] = name;
|
||||
}
|
||||
|
||||
void VprNetlistAnnotation::rename_net(const AtomNetId& net, const std::string& name) {
|
||||
/* Warn any override attempt */
|
||||
std::map<AtomNetId, std::string>::const_iterator it = net_names_.find(net);
|
||||
if (it != net_names_.end()) {
|
||||
VTR_LOG_WARN("Override the net with name '%s' in netlist annotation!\n",
|
||||
name.c_str());
|
||||
}
|
||||
|
||||
net_names_[net] = name;
|
||||
}
|
||||
|
||||
} /* End namespace openfpga*/
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
#ifndef VPR_NETLIST_ANNOTATION_H
|
||||
#define VPR_NETLIST_ANNOTATION_H
|
||||
|
||||
/********************************************************************
|
||||
* Include header files required by the data structure definition
|
||||
*******************************************************************/
|
||||
#include <map>
|
||||
|
||||
/* Header from vpr library */
|
||||
#include "atom_netlist.h"
|
||||
|
||||
/* Begin namespace openfpga */
|
||||
namespace openfpga {
|
||||
|
||||
/********************************************************************
|
||||
* This is the critical data structure to link the pb_type in VPR
|
||||
* to openfpga annotations
|
||||
* With a given pb_type pointer, it aims to identify:
|
||||
* 1. if the pb_type is a physical pb_type or a operating pb_type
|
||||
* 2. what is the circuit model id linked to a physical pb_type
|
||||
* 3. what is the physical pb_type for an operating pb_type
|
||||
* 4. what is the mode pointer that represents the physical mode for a pb_type
|
||||
*******************************************************************/
|
||||
class VprNetlistAnnotation {
|
||||
public: /* Constructor */
|
||||
VprNetlistAnnotation();
|
||||
public: /* Public accessors */
|
||||
bool is_block_renamed(const AtomBlockId& block) const;
|
||||
std::string block_name(const AtomBlockId& block) const;
|
||||
bool is_net_renamed(const AtomNetId& net) const;
|
||||
std::string net_name(const AtomNetId& net) const;
|
||||
public: /* Public mutators */
|
||||
void rename_block(const AtomBlockId& block, const std::string& name);
|
||||
void rename_net(const AtomNetId& net, const std::string& name);
|
||||
private: /* Internal data */
|
||||
/* Pair a regular pb_type to its physical pb_type */
|
||||
std::map<AtomBlockId, std::string> block_names_;
|
||||
std::map<AtomNetId, std::string> net_names_;
|
||||
};
|
||||
|
||||
} /* End namespace openfpga*/
|
||||
|
||||
#endif
|
||||
|
|
@ -7,5 +7,8 @@ read_openfpga_arch -f ./test_openfpga_arch/k6_N10_40nm_openfpga.xml
|
|||
# Annotate the OpenFPGA architecture to VPR data base
|
||||
link_openfpga_arch
|
||||
|
||||
# Check and correct any naming conflicts in the BLIF netlist
|
||||
check_netlist_naming_conflict --fix --report ./netlist_renaming.rpt
|
||||
|
||||
# Finish and exit OpenFPGA
|
||||
exit
|
||||
|
|
|
|||
Loading…
Reference in New Issue