From 6055a42196039ef28772555c81eacb8dc3248285 Mon Sep 17 00:00:00 2001 From: ubuntu Date: Fri, 1 Dec 2023 03:04:32 -0800 Subject: [PATCH] add test case --- .../config/pin_constraints.xml | 5 ++ .../config/repack_design_constraints.xml | 7 +++ .../config/rst_on_lut_pc.xml | 5 ++ .../config/rst_on_lut_repack_dc.xml | 8 +++ .../repack_ignore_nets/config/task.conf | 50 +++++++++++++++++++ 5 files changed, 75 insertions(+) create mode 100644 openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/pin_constraints.xml create mode 100644 openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/repack_design_constraints.xml create mode 100644 openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/rst_on_lut_pc.xml create mode 100644 openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/rst_on_lut_repack_dc.xml create mode 100644 openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/task.conf diff --git a/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/pin_constraints.xml b/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/pin_constraints.xml new file mode 100644 index 000000000..e297abb77 --- /dev/null +++ b/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/pin_constraints.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/repack_design_constraints.xml b/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/repack_design_constraints.xml new file mode 100644 index 000000000..d3fc31c4c --- /dev/null +++ b/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/repack_design_constraints.xml @@ -0,0 +1,7 @@ + + + + + + + diff --git a/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/rst_on_lut_pc.xml b/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/rst_on_lut_pc.xml new file mode 100644 index 000000000..00b4b2bd6 --- /dev/null +++ b/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/rst_on_lut_pc.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/rst_on_lut_repack_dc.xml b/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/rst_on_lut_repack_dc.xml new file mode 100644 index 000000000..73436da74 --- /dev/null +++ b/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/rst_on_lut_repack_dc.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/task.conf new file mode 100644 index 000000000..63ffd257c --- /dev/null +++ b/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/task.conf @@ -0,0 +1,50 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 3*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/ignore_global_nets_on_pins_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/repack_design_constraints.xml +openfpga_vpr_device_layout=2x2 + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_localRstGen_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/two_dff_inv_rst/two_dff_inv_rst.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut/rst_on_lut.v + +[SYNTHESIS_PARAM] +# Yosys script parameters +bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v +bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v +bench_read_verilog_options_common = -nolatches +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys + +bench0_top = two_dff_inv_rst +bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints.xml +bench0_openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/repack_design_constraints.xml + +bench1_top = rst_on_lut +bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/rst_on_lut_pc.xml +bench1_openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/rst_on_lut_repack_dc.xml + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist=