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[Arch] Bug fix in tileable I/O arch example

This commit is contained in:
tangxifan 2020-12-04 17:56:54 -07:00
parent 73aaa261d8
commit 6001da3a40
1 changed files with 2 additions and 2 deletions
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4
openfpga_flow/vpr_arch/k4_N4_tileableIO_40nm.xml
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@ -43,8 +43,8 @@
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom"> <pinlocations pattern="custom">
<loc side="top">io.outpad io.inpad</loc> <loc side="top">io.outpad</loc>
<loc side="right">io.outpad io.inpad</loc> <loc side="right">io.inpad</loc>
</pinlocations> </pinlocations>
</tile> </tile>
<tile name="clb" area="53894"> <tile name="clb" area="53894">