From 5fe039dd7cc7c8aed34e414ca9e9fb45ed2904c0 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 16 Sep 2020 17:35:49 -0600 Subject: [PATCH] [Regression Tests] Deploy the fully connected crossbar test to CI --- .travis/fpga_verilog_reg_test.sh | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.travis/fpga_verilog_reg_test.sh b/.travis/fpga_verilog_reg_test.sh index 35086b65b..8956cab1e 100755 --- a/.travis/fpga_verilog_reg_test.sh +++ b/.travis/fpga_verilog_reg_test.sh @@ -90,6 +90,9 @@ python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/power_gated_design/p echo -e "Testing Depopulated crossbar in local routing"; python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/depopulate_crossbar --debug --show_thread_logs +echo -e "Testing Fully connected output crossbar in local routing"; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fully_connected_output_crossbar --debug --show_thread_logs + echo -e "Testing through channels in tileable routing"; python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/thru_channel/thru_narrow_tile --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/thru_channel/thru_wide_tile --debug --show_thread_logs